X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=arch%2Farm%2Fimx-common%2Fcpu.c;h=5a09107c5ab3228441a7cd5de8aa7f375a4d3e6d;hp=fa1d4680416ff2d3470257cd007351650df441e6;hb=b07161c321d9bc4ca5c610087b5d4e0566402d20;hpb=9fe2cfb43aab2225a8c970a69341534b2488da8c

diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index fa1d468041..5a09107c5a 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -4,23 +4,7 @@
  *
  * (C) Copyright 2009 Freescale Semiconductor, Inc.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
@@ -30,6 +14,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
+#include <ipu_pixfmt.h>
 
 #ifdef CONFIG_FSL_ESDHC
 #include <fsl_esdhc.h>
@@ -64,20 +49,72 @@ char *get_reset_cause(void)
 	}
 }
 
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_MX53)
+#define MEMCTL_BASE	ESDCTL_BASE_ADDR
+#else
+#define MEMCTL_BASE	MMDC_P0_BASE_ADDR
+#endif
+static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
+static const unsigned char bank_lookup[] = {3, 2};
+
+/* these MMDC registers are common to the IMX53 and IMX6 */
+struct esd_mmdc_regs {
+	uint32_t	ctl;
+	uint32_t	pdc;
+	uint32_t	otc;
+	uint32_t	cfg0;
+	uint32_t	cfg1;
+	uint32_t	cfg2;
+	uint32_t	misc;
+};
+
+#define ESD_MMDC_CTL_GET_ROW(mdctl)	((ctl >> 24) & 7)
+#define ESD_MMDC_CTL_GET_COLUMN(mdctl)	((ctl >> 20) & 7)
+#define ESD_MMDC_CTL_GET_WIDTH(mdctl)	((ctl >> 16) & 3)
+#define ESD_MMDC_CTL_GET_CS1(mdctl)	((ctl >> 30) & 1)
+#define ESD_MMDC_MISC_GET_BANK(mdmisc)	((misc >> 5) & 1)
+
+/*
+ * imx_ddr_size - return size in bytes of DRAM according MMDC config
+ * The MMDC MDCTL register holds the number of bits for row, col, and data
+ * width and the MMDC MDMISC register holds the number of banks. Combine
+ * all these bits to determine the meme size the MMDC has been configured for
+ */
+unsigned imx_ddr_size(void)
+{
+	struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
+	unsigned ctl = readl(&mem->ctl);
+	unsigned misc = readl(&mem->misc);
+	int bits = 11 + 0 + 0 + 1;      /* row + col + bank + width */
+
+	bits += ESD_MMDC_CTL_GET_ROW(ctl);
+	bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
+	bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
+	bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
+	bits += ESD_MMDC_CTL_GET_CS1(ctl);
+	return 1 << bits;
+}
+#endif
+
 #if defined(CONFIG_DISPLAY_CPUINFO)
 
-static const char *get_imx_type(u32 imxtype)
+const char *get_imx_type(u32 imxtype)
 {
 	switch (imxtype) {
-	case 0x63:
+	case MXC_CPU_MX6Q:
 		return "6Q";	/* Quad-core version of the mx6 */
-	case 0x61:
-		return "6DS";	/* Dual/Solo version of the mx6 */
-	case 0x60:
+	case MXC_CPU_MX6D:
+		return "6D";	/* Dual-core version of the mx6 */
+	case MXC_CPU_MX6DL:
+		return "6DL";	/* Dual Lite version of the mx6 */
+	case MXC_CPU_MX6SOLO:
+		return "6SOLO";	/* Solo version of the mx6 */
+	case MXC_CPU_MX6SL:
 		return "6SL";	/* Solo-Lite version of the mx6 */
-	case 0x51:
+	case MXC_CPU_MX51:
 		return "51";
-	case 0x53:
+	case MXC_CPU_MX53:
 		return "53";
 	default:
 		return "??";
@@ -122,11 +159,6 @@ int cpu_mmc_init(bd_t *bis)
 }
 #endif
 
-void reset_cpu(ulong addr)
-{
-	__raw_writew(4, WDOG1_BASE_ADDR);
-}
-
 u32 get_ahb_clk(void)
 {
 	struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -138,3 +170,11 @@ u32 get_ahb_clk(void)
 
 	return get_periph_clk() / (ahb_podf + 1);
 }
+
+#if defined(CONFIG_VIDEO_IPUV3)
+void arch_preboot_os(void)
+{
+	/* disable video before launching O/S */
+	ipuv3_fb_shutdown();
+}
+#endif