X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=arch%2Fmips%2Fcpu%2Fmips32%2Fcache.S;h=d3f156e4822a908738e9e96cdc793a937506b249;hp=296593805a7334a333321a73d1cb051c909d88d7;hb=ee8b1e29597bcf18bfebd6fd8eccc8e245046352;hpb=75df0d594990875419121c6f8687472ac9f4ae7a diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S index 296593805a..d3f156e482 100644 --- a/arch/mips/cpu/mips32/cache.S +++ b/arch/mips/cpu/mips32/cache.S @@ -3,23 +3,7 @@ * * Copyright (c) 2003 Wolfgang Denk * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -30,7 +14,11 @@ #include #include -#define RA t8 +#ifndef CONFIG_SYS_MIPS_CACHE_MODE +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT +#endif + +#define RA t9 /* * 16kB is the maximum size of instruction and data caches on MIPS 4K, @@ -51,75 +39,6 @@ .set pop .endm -/* - * cacheop macro to automate cache operations - * first some helpers... - */ -#define _mincache(size, maxsize) \ - bltu size,maxsize,9f ; \ - move size,maxsize ; \ -9: - -#define _align(minaddr, maxaddr, linesize) \ - .set noat ; \ - subu AT,linesize,1 ; \ - not AT ; \ - and minaddr,AT ; \ - addu maxaddr,-1 ; \ - and maxaddr,AT ; \ - .set at - -/* general operations */ -#define doop1(op1) \ - cache op1,0(a0) -#define doop2(op1, op2) \ - cache op1,0(a0) ; \ - nop ; \ - cache op2,0(a0) - -/* specials for cache initialisation */ -#define doop1lw(op1) \ - lw zero,0(a0) -#define doop1lw1(op1) \ - cache op1,0(a0) ; \ - lw zero,0(a0) ; \ - cache op1,0(a0) -#define doop121(op1,op2) \ - cache op1,0(a0) ; \ - nop; \ - cache op2,0(a0) ; \ - nop; \ - cache op1,0(a0) - -#define _oploopn(minaddr, maxaddr, linesize, tag, ops) \ - .set noreorder ; \ -10: doop##tag##ops ; \ - bne minaddr,maxaddr,10b ; \ - add minaddr,linesize ; \ - .set reorder - -/* finally the cache operation macros */ -#define vcacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \ - blez n,11f ; \ - addu n,kva ; \ - _align(kva, n, cacheLineSize) ; \ - _oploopn(kva, n, cacheLineSize, tag, ops) ; \ -11: - -#define icacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \ - _mincache(n, cacheSize); \ - blez n,11f ; \ - addu n,kva ; \ - _align(kva, n, cacheLineSize) ; \ - _oploopn(kva, n, cacheLineSize, tag, ops) ; \ -11: - -#define vcacheop(kva, n, cacheSize, cacheLineSize, op) \ - vcacheopn(kva, n, cacheSize, cacheLineSize, 1, (op)) - -#define icacheop(kva, n, cacheSize, cacheLineSize, op) \ - icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op)) - .macro f_fill64 dst, offset, val LONG_S \val, (\offset + 0 * LONGSIZE)(\dst) LONG_S \val, (\offset + 1 * LONGSIZE)(\dst) @@ -145,37 +64,37 @@ * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz) */ LEAF(mips_init_icache) - blez a1, 9f - mtc0 zero, CP0_TAGLO + blez a1, 9f + mtc0 zero, CP0_TAGLO /* clear tag to invalidate */ PTR_LI t0, INDEX_BASE PTR_ADDU t1, t0, a1 -1: cache_op Index_Store_Tag_I t0 +1: cache_op INDEX_STORE_TAG_I t0 PTR_ADDU t0, a2 bne t0, t1, 1b /* fill once, so data field parity is correct */ PTR_LI t0, INDEX_BASE -2: cache_op Fill t0 +2: cache_op FILL t0 PTR_ADDU t0, a2 bne t0, t1, 2b /* invalidate again - prudent but not strictly neccessary */ PTR_LI t0, INDEX_BASE -1: cache_op Index_Store_Tag_I t0 +1: cache_op INDEX_STORE_TAG_I t0 PTR_ADDU t0, a2 bne t0, t1, 1b -9: jr ra +9: jr ra END(mips_init_icache) /* * mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz) */ LEAF(mips_init_dcache) - blez a1, 9f - mtc0 zero, CP0_TAGLO + blez a1, 9f + mtc0 zero, CP0_TAGLO /* clear all tags */ PTR_LI t0, INDEX_BASE PTR_ADDU t1, t0, a1 -1: cache_op Index_Store_Tag_D t0 +1: cache_op INDEX_STORE_TAG_D t0 PTR_ADDU t0, a2 bne t0, t1, 1b /* load from each line (in cached space) */ @@ -185,34 +104,31 @@ LEAF(mips_init_dcache) bne t0, t1, 2b /* clear all tags */ PTR_LI t0, INDEX_BASE -1: cache_op Index_Store_Tag_D t0 +1: cache_op INDEX_STORE_TAG_D t0 PTR_ADDU t0, a2 bne t0, t1, 1b -9: jr ra +9: jr ra END(mips_init_dcache) -/******************************************************************************* -* -* mips_cache_reset - low level initialisation of the primary caches -* -* This routine initialises the primary caches to ensure that they -* have good parity. It must be called by the ROM before any cached locations -* are used to prevent the possibility of data with bad parity being written to -* memory. -* To initialise the instruction cache it is essential that a source of data -* with good parity is available. This routine -* will initialise an area of memory starting at location zero to be used as -* a source of parity. -* -* RETURNS: N/A -* -*/ +/* + * mips_cache_reset - low level initialisation of the primary caches + * + * This routine initialises the primary caches to ensure that they have good + * parity. It must be called by the ROM before any cached locations are used + * to prevent the possibility of data with bad parity being written to memory. + * + * To initialise the instruction cache it is essential that a source of data + * with good parity is available. This routine will initialise an area of + * memory starting at location zero to be used as a source of parity. + * + * RETURNS: N/A + * + */ NESTED(mips_cache_reset, 0, ra) move RA, ra li t2, CONFIG_SYS_ICACHE_SIZE li t3, CONFIG_SYS_DCACHE_SIZE - li t4, CONFIG_SYS_CACHELINE_SIZE - move t5, t4 + li t8, CONFIG_SYS_CACHELINE_SIZE li v0, MIPS_MAX_CACHE_SIZE @@ -239,7 +155,7 @@ NESTED(mips_cache_reset, 0, ra) * Initialize the I-cache first, */ move a1, t2 - move a2, t4 + move a2, t8 PTR_LA t7, mips_init_icache jalr t7 @@ -247,20 +163,19 @@ NESTED(mips_cache_reset, 0, ra) * then initialize D-cache. */ move a1, t3 - move a2, t5 + move a2, t8 PTR_LA t7, mips_init_dcache jalr t7 jr RA END(mips_cache_reset) -/******************************************************************************* -* -* dcache_status - get cache status -* -* RETURNS: 0 - cache disabled; 1 - cache enabled -* -*/ +/* + * dcache_status - get cache status + * + * RETURNS: 0 - cache disabled; 1 - cache enabled + * + */ LEAF(dcache_status) mfc0 t0, CP0_CONFIG li t1, CONF_CM_UNCACHED @@ -271,13 +186,12 @@ LEAF(dcache_status) 2: jr ra END(dcache_status) -/******************************************************************************* -* -* dcache_disable - disable cache -* -* RETURNS: N/A -* -*/ +/* + * dcache_disable - disable cache + * + * RETURNS: N/A + * + */ LEAF(dcache_disable) mfc0 t0, CP0_CONFIG li t1, -8 @@ -287,42 +201,17 @@ LEAF(dcache_disable) jr ra END(dcache_disable) -/******************************************************************************* -* -* dcache_enable - enable cache -* -* RETURNS: N/A -* -*/ +/* + * dcache_enable - enable cache + * + * RETURNS: N/A + * + */ LEAF(dcache_enable) mfc0 t0, CP0_CONFIG ori t0, CONF_CM_CMASK xori t0, CONF_CM_CMASK - ori t0, CONF_CM_CACHABLE_NONCOHERENT + ori t0, CONFIG_SYS_MIPS_CACHE_MODE mtc0 t0, CP0_CONFIG jr ra END(dcache_enable) - -#ifdef CONFIG_SYS_INIT_RAM_LOCK_MIPS -/******************************************************************************* -* -* mips_cache_lock - lock RAM area pointed to by a0 in cache. -* -* RETURNS: N/A -* -*/ -# define CACHE_LOCK_SIZE (CONFIG_SYS_DCACHE_SIZE) - .globl mips_cache_lock - .ent mips_cache_lock -mips_cache_lock: - li a1, CKSEG0 - CACHE_LOCK_SIZE - addu a0, a1 - li a2, CACHE_LOCK_SIZE - li a3, CONFIG_SYS_CACHELINE_SIZE - move a1, a2 - icacheop(a0,a1,a2,a3,0x1d) - - jr ra - - .end mips_cache_lock -#endif /* CONFIG_SYS_INIT_RAM_LOCK_MIPS */