X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=board%2Famcc%2Fluan%2Fluan.c;h=4e12e9af12a0d98af88e142c76e176a43e7bad12;hp=0067ce0e7e52d215909baa848ae00e6599fefeb9;hb=9d62f20d0861ef87460d073dc189c851715b46ae;hpb=b90296fc39a33f84bb2b0aa79bf997be495ba791 diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c index 0067ce0e7e..4e12e9af12 100644 --- a/board/amcc/luan/luan.c +++ b/board/amcc/luan/luan.c @@ -25,12 +25,13 @@ #include #include #include +#include #include #include "epld.h" DECLARE_GLOBAL_DATA_PTR; -extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /************************************************************************* @@ -39,30 +40,36 @@ extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ ************************************************************************/ int board_early_init_f(void) { - mtebc( pb0ap, 0x03800000 ); /* set chip selects */ - mtebc( pb0cr, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */ - mtebc( pb1ap, 0x03800000 ); - mtebc( pb1cr, 0xff018000 ); /* ebc0_b1cr, 1MB at 0xff000000 CS1 */ - mtebc( pb2ap, 0x03800000 ); - mtebc( pb2cr, 0xff838000 ); /* ebc0_b2cr, 2MB at 0xff800000 CS2 */ - - mtdcr( uic1sr, 0xffffffff ); /* Clear all interrupts */ - mtdcr( uic1er, 0x00000000 ); /* disable all interrupts */ - mtdcr( uic1cr, 0x00000000 ); /* Set Critical / Non Critical interrupts */ - mtdcr( uic1pr, 0x7fff83ff ); /* Set Interrupt Polarities */ - mtdcr( uic1tr, 0x001f8000 ); /* Set Interrupt Trigger Levels */ - mtdcr( uic1vr, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */ - mtdcr( uic1sr, 0x00000000 ); /* clear all interrupts */ - mtdcr( uic1sr, 0xffffffff ); - - mtdcr( uic0sr, 0xffffffff ); /* Clear all interrupts */ - mtdcr( uic0er, 0x00000000 ); /* disable all interrupts excepted cascade */ - mtdcr( uic0cr, 0x00000001 ); /* Set Critical / Non Critical interrupts */ - mtdcr( uic0pr, 0xffffffff ); /* Set Interrupt Polarities */ - mtdcr( uic0tr, 0x01000004 ); /* Set Interrupt Trigger Levels */ - mtdcr( uic0vr, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */ - mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */ - mtdcr( uic0sr, 0xffffffff ); + u32 mfr; + + mtebc( PB0AP, 0x03800000 ); /* set chip selects */ + mtebc( PB0CR, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */ + mtebc( PB1AP, 0x03800000 ); + mtebc( PB1CR, 0xff018000 ); /* ebc0_b1cr, 1MB at 0xff000000 CS1 */ + mtebc( PB2AP, 0x03800000 ); + mtebc( PB2CR, 0xff838000 ); /* ebc0_b2cr, 2MB at 0xff800000 CS2 */ + + mtdcr( UIC1SR, 0xffffffff ); /* Clear all interrupts */ + mtdcr( UIC1ER, 0x00000000 ); /* disable all interrupts */ + mtdcr( UIC1CR, 0x00000000 ); /* Set Critical / Non Critical interrupts */ + mtdcr( UIC1PR, 0x7fff83ff ); /* Set Interrupt Polarities */ + mtdcr( UIC1TR, 0x001f8000 ); /* Set Interrupt Trigger Levels */ + mtdcr( UIC1VR, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */ + mtdcr( UIC1SR, 0x00000000 ); /* clear all interrupts */ + mtdcr( UIC1SR, 0xffffffff ); + + mtdcr( UIC0SR, 0xffffffff ); /* Clear all interrupts */ + mtdcr( UIC0ER, 0x00000000 ); /* disable all interrupts excepted cascade */ + mtdcr( UIC0CR, 0x00000001 ); /* Set Critical / Non Critical interrupts */ + mtdcr( UIC0PR, 0xffffffff ); /* Set Interrupt Polarities */ + mtdcr( UIC0TR, 0x01000004 ); /* Set Interrupt Trigger Levels */ + mtdcr( UIC0VR, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */ + mtdcr( UIC0SR, 0x00000000 ); /* clear all interrupts */ + mtdcr( UIC0SR, 0xffffffff ); + + mfsdr(SDR0_MFR, mfr); + mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ + mtsdr(SDR0_MFR, mfr); return 0; } @@ -74,7 +81,7 @@ int board_early_init_f(void) ************************************************************************/ int misc_init_r(void) { - volatile epld_t *x = (epld_t *) CFG_EPLD_BASE; + volatile epld_t *x = (epld_t *) CONFIG_SYS_EPLD_BASE; /* set modes of operation */ x->ethuart |= EPLD2_ETH_MODE_10 | EPLD2_ETH_MODE_100 | @@ -112,153 +119,13 @@ int checkboard(void) } /* - * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with + * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with * board specific values. */ u32 ddr_clktr(u32 default_val) { return (SDRAM_CLKTR_CLKP_180_DEG_ADV); } -/************************************************************************* - * int testdram() - * - ************************************************************************/ -#if defined(CFG_DRAM_TEST) -int testdram(void) -{ - unsigned long *mem = (unsigned long *) 0; - const unsigned long kend = (1024 / sizeof(unsigned long)); - unsigned long k, n; - - mtmsr(0); - - for (k = 0; k < CFG_KBYTES_SDRAM; - ++k, mem += (1024 / sizeof(unsigned long))) { - if ((k & 1023) == 0) { - printf("%3d MB\r", k / 1024); - } - - memset(mem, 0xaaaaaaaa, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0xaaaaaaaa) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - - memset(mem, 0x55555555, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0x55555555) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - } - printf("SDRAM test passes\n"); - - return 0; -} -#endif - - -/************************************************************************* - * pci_pre_init - * - * This routine is called just prior to registering the hose and gives - * the board the opportunity to check things. Returning a value of zero - * indicates that things are bad & PCI initialization should be aborted. - * - * Different boards may wish to customize the pci controller structure - * (add regions, override default access routines, etc) or perform - * certain pre-initialization actions. - * - ************************************************************************/ -#if defined(CONFIG_PCI) -int pci_pre_init( struct pci_controller *hose ) -{ - unsigned long strap; - - /*--------------------------------------------------------------------------+ - * The luan board is always configured as the host & requires the - * PCI arbiter to be enabled. - *--------------------------------------------------------------------------*/ - mfsdr(sdr_sdstp1, strap); - if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) { - printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); - - return 0; - } - - return 1; -} -#endif /* defined(CONFIG_PCI) */ - - -/************************************************************************* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller *hose) -{ - /*--------------------------------------------------------------------------+ - * Disable everything - *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0SA, 0 ); /* disable */ - out32r( PCIX0_PIM1SA, 0 ); /* disable */ - out32r( PCIX0_PIM2SA, 0 ); /* disable */ - out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ - - /*--------------------------------------------------------------------------+ - * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping - * options to not support sizes such as 128/256 MB. - *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); - out32r( PCIX0_PIM0LAH, 0 ); - out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); - - out32r( PCIX0_BAR0, 0 ); - - /*--------------------------------------------------------------------------+ - * Program the board's subsystem id/vendor id - *--------------------------------------------------------------------------*/ - out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); - - out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); -} -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ - - -/************************************************************************* - * is_pci_host - * - * This routine is called to determine if a pci scan should be - * performed. With various hardware environments (especially cPCI and - * PPMC) it's insufficient to depend on the state of the arbiter enable - * bit in the strap register, or generic host/adapter assumptions. - * - * Rather than hard-code a bad assumption in the general 440 code, the - * 440 pci code requires the board to decide at runtime. - * - * Return 0 for adapter mode, non-zero for host (monarch) mode. - * - * - ************************************************************************/ -#if defined(CONFIG_PCI) -int is_pci_host(struct pci_controller *hose) -{ - return 1; -} -#endif /* defined(CONFIG_PCI) */ - - /************************************************************************* * hw_watchdog_reset * @@ -293,7 +160,7 @@ static int on_off( const char *s ) ************************************************************************/ static void l2cache_disable(void) { - mtdcr( l2_cache_cfg, 0 ); + mtdcr( L2_CACHE_CFG, 0 ); } @@ -303,24 +170,24 @@ static void l2cache_disable(void) ************************************************************************/ static void l2cache_enable(void) /* see p258 7.4.1 Enabling L2 Cache */ { - mtdcr( l2_cache_cfg, 0x80000000 ); /* enable L2_MODE L2_CFG[L2M] */ + mtdcr( L2_CACHE_CFG, 0x80000000 ); /* enable L2_MODE L2_CFG[L2M] */ - mtdcr( l2_cache_addr, 0 ); /* set L2_ADDR with all zeros */ + mtdcr( L2_CACHE_ADDR, 0 ); /* set L2_ADDR with all zeros */ - mtdcr( l2_cache_cmd, 0x80000000 ); /* issue HCLEAR command via L2_CMD */ + mtdcr( L2_CACHE_CMD, 0x80000000 ); /* issue HCLEAR command via L2_CMD */ - while (!(mfdcr( l2_cache_stat ) & 0x80000000 )) ;; /* poll L2_SR for completion */ + while (!(mfdcr( L2_CACHE_STAT ) & 0x80000000 )) ;; /* poll L2_SR for completion */ - mtdcr( l2_cache_cmd, 0x10000000 ); /* clear cache errors L2_CMD[CCP] */ + mtdcr( L2_CACHE_CMD, 0x10000000 ); /* clear cache errors L2_CMD[CCP] */ - mtdcr( l2_cache_cmd, 0x08000000 ); /* clear tag errors L2_CMD[CTE] */ + mtdcr( L2_CACHE_CMD, 0x08000000 ); /* clear tag errors L2_CMD[CTE] */ - mtdcr( l2_cache_snp0, 0 ); /* snoop registers */ - mtdcr( l2_cache_snp1, 0 ); + mtdcr( L2_CACHE_SNP0, 0 ); /* snoop registers */ + mtdcr( L2_CACHE_SNP1, 0 ); __asm__ volatile ("sync"); /* msync */ - mtdcr( l2_cache_cfg, 0xe0000000 ); /* inst and data use L2 */ + mtdcr( L2_CACHE_CFG, 0xe0000000 ); /* inst and data use L2 */ __asm__ volatile ("sync"); } @@ -332,7 +199,7 @@ static void l2cache_enable(void) /* see p258 7.4.1 Enabling L2 Cache */ ************************************************************************/ static int l2cache_status(void) { - return (mfdcr( l2_cache_cfg ) & 0x60000000) != 0; + return (mfdcr( L2_CACHE_CFG ) & 0x60000000) != 0; } @@ -356,7 +223,7 @@ int do_l2cache( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] ) l2cache_status() ? "ON" : "OFF"); return 0; default: - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -366,7 +233,7 @@ int do_l2cache( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] ) U_BOOT_CMD( l2cache, 2, 1, do_l2cache, - "l2cache - enable or disable L2 cache\n", + "enable or disable L2 cache", "[on, off]\n" - " - enable or disable L2 cache\n" - ); + " - enable or disable L2 cache" +);