X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=board%2Fkaro%2Ftx53%2Ftx53.c;h=e877b2c44cbb44e7b796ee694ea6af45ee08f846;hp=bfd9d85c8c8ffcae9d884c2091183962219ecb17;hb=f1cd0e93f99e9ff56817d90607286a3d1ea4245c;hpb=599095ee92fe3488ef394d532e659dce1ed2c445 diff --git a/board/karo/tx53/tx53.c b/board/karo/tx53/tx53.c index bfd9d85c8c..e877b2c44c 100644 --- a/board/karo/tx53/tx53.c +++ b/board/karo/tx53/tx53.c @@ -189,6 +189,8 @@ static void tx53_print_cpuinfo(void) enum LTC3589_REGS { LTC3589_SCR1 = 0x07, + LTC3589_SCR2 = 0x12, + LTC3589_VCCR = 0x20, LTC3589_CLIRQ = 0x21, LTC3589_B1DTV1 = 0x23, LTC3589_B1DTV2 = 0x24, @@ -201,12 +203,15 @@ enum LTC3589_REGS { LTC3589_L2DTV2 = 0x33, }; -#define LTC3589_PGOOD_MASK (1 << 5) +#define LTC3589_BnDTV1_PGOOD_MASK (1 << 5) +#define LTC3589_BnDTV1_SLEW(n) (((n) & 3) << 6) -#define LTC3589_CLK_RATE_LOW (1 << 5) +#define LTC3589_CLK_RATE_LOW (1 << 5) + +#define LTC3589_SCR2_PGOOD_SHUTDWN (1 << 7) #define VDD_LDO2_VAL mV_to_regval(vout_to_vref(1325 * 10, 2)) -#define VDD_CORE_VAL mV_to_regval(vout_to_vref(1240 * 10, 3)) +#define VDD_CORE_VAL mV_to_regval(vout_to_vref(1100 * 10, 3)) #define VDD_SOC_VAL mV_to_regval(vout_to_vref(1325 * 10, 4)) #define VDD_BUCK3_VAL mV_to_regval(vout_to_vref(2500 * 10, 5)) @@ -250,19 +255,23 @@ static struct pmic_regs { u8 val; } ltc3589_regs[] = { { LTC3589_SCR1, 0x15, }, /* burst mode for all regulators except buck boost */ + { LTC3589_SCR2, LTC3589_SCR2_PGOOD_SHUTDWN, }, /* enable shutdown on PGOOD Timeout */ - { LTC3589_L2DTV1, VDD_LDO2_VAL | LTC3589_PGOOD_MASK, }, + { LTC3589_L2DTV1, VDD_LDO2_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, }, { LTC3589_L2DTV2, VDD_LDO2_VAL | LTC3589_CLK_RATE_LOW, }, - { LTC3589_B1DTV1, VDD_CORE_VAL | LTC3589_PGOOD_MASK, }, + { LTC3589_B1DTV1, VDD_CORE_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, }, { LTC3589_B1DTV2, VDD_CORE_VAL, }, - { LTC3589_B2DTV1, VDD_SOC_VAL | LTC3589_PGOOD_MASK, }, + { LTC3589_B2DTV1, VDD_SOC_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, }, { LTC3589_B2DTV2, VDD_SOC_VAL, }, - { LTC3589_B3DTV1, VDD_BUCK3_VAL | LTC3589_PGOOD_MASK, }, + { LTC3589_B3DTV1, VDD_BUCK3_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, }, { LTC3589_B3DTV2, VDD_BUCK3_VAL, }, + /* Select ref 0 for all regulators and enable slew */ + { LTC3589_VCCR, 0x55, }, + { LTC3589_CLIRQ, 0, }, /* clear all interrupt flags */ }; @@ -305,6 +314,94 @@ static int setup_pmic_voltages(void) return 0; } +static struct { + u32 max_freq; + u32 mV; +} tx53_core_voltages[] = { + { 800000000, 1100, }, + { 1000000000, 1240, }, + { 1200000000, 1350, }, +}; + +int adjust_core_voltage(u32 freq) +{ + int ret; + int i; + + printf("%s@%d\n", __func__, __LINE__); + + for (i = 0; i < ARRAY_SIZE(tx53_core_voltages); i++) { + if (freq <= tx53_core_voltages[i].max_freq) { + int retries = 0; + const int max_tries = 10; + const int delay_us = 1; + u32 mV = tx53_core_voltages[i].mV; + u8 val = mV_to_regval(vout_to_vref(mV * 10, 3)); + u8 v; + + printf("regval[%umV]=%02x\n", mV, val); + + ret = i2c_read(CONFIG_SYS_I2C_SLAVE, LTC3589_B1DTV1, 1, + &v, 1); + if (ret) { + printf("%s: failed to read PMIC register %02x: %d\n", + __func__, LTC3589_B1DTV1, ret); + return ret; + } + printf("Changing reg %02x from %02x to %02x\n", + LTC3589_B1DTV1, v, (v & ~0x1f) | + mV_to_regval(vout_to_vref(mV * 10, 3))); + v &= ~0x1f; + v |= mV_to_regval(vout_to_vref(mV * 10, 3)); + ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3589_B1DTV1, 1, + &v, 1); + if (ret) { + printf("%s: failed to write PMIC register %02x: %d\n", + __func__, LTC3589_B1DTV1, ret); + return ret; + } + ret = i2c_read(CONFIG_SYS_I2C_SLAVE, LTC3589_VCCR, 1, + &v, 1); + if (ret) { + printf("%s: failed to read PMIC register %02x: %d\n", + __func__, LTC3589_VCCR, ret); + return ret; + } + v |= 0x1; + ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3589_VCCR, 1, + &v, 1); + if (ret) { + printf("%s: failed to write PMIC register %02x: %d\n", + __func__, LTC3589_VCCR, ret); + return ret; + } + for (retries = 0; retries < max_tries; retries++) { + ret = i2c_read(CONFIG_SYS_I2C_SLAVE, + LTC3589_VCCR, 1, &v, 1); + if (ret) { + printf("%s: failed to read PMIC register %02x: %d\n", + __func__, LTC3589_VCCR, ret); + return ret; + } + if (!(v & 1)) + break; + udelay(delay_us); + } + if (v & 1) { + printf("change of VDDCORE did not complete after %uµs\n", + retries * delay_us); + return -ETIMEDOUT; + } + + printf("VDDCORE set to %umV after %u loops\n", + DIV_ROUND(vref_to_vout(regval_to_mV(val & 0x1f), 3), + 10), retries); + return 0; + } + } + return -EINVAL; +} + int board_early_init_f(void) { struct mxc_ccm_reg *ccm_regs = (void *)CCM_BASE_ADDR; @@ -472,9 +569,6 @@ int board_mmc_init(bd_t *bis) struct tx53_esdhc_cfg *cfg = &tx53_esdhc_cfg[i]; int ret; - if (i >= CONFIG_SYS_FSL_ESDHC_NUM) - break; - imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads); cfg->cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); @@ -607,12 +701,14 @@ static const struct gpio stk5_gpios[] = { }; #ifdef CONFIG_LCD +static u16 tx53_cmap[256]; vidinfo_t panel_info = { /* set to max. size supported by SoC */ .vl_col = 1600, .vl_row = 1200, .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */ + .cmap = tx53_cmap, }; static struct fb_videomode tx53_fb_modes[] = { @@ -768,6 +864,12 @@ static struct fb_videomode tx53_fb_modes[] = { }; static int lcd_enabled = 1; +static int lcd_bl_polarity; + +static int lcd_backlight_polarity(void) +{ + return lcd_bl_polarity; +} void lcd_enable(void) { @@ -786,7 +888,8 @@ void lcd_enable(void) udelay(100); gpio_set_value(TX53_LCD_RST_GPIO, 1); udelay(300000); - gpio_set_value(TX53_LCD_BACKLIGHT_GPIO, is_lvds()); + gpio_set_value(TX53_LCD_BACKLIGHT_GPIO, + lcd_backlight_polarity()); } } @@ -802,7 +905,8 @@ void lcd_panel_disable(void) { if (lcd_enabled) { debug("Switching LCD off\n"); - gpio_set_value(TX53_LCD_BACKLIGHT_GPIO, !is_lvds()); + gpio_set_value(TX53_LCD_BACKLIGHT_GPIO, + !lcd_backlight_polarity()); gpio_set_value(TX53_LCD_RST_GPIO, 0); gpio_set_value(TX53_LCD_PWR_GPIO, 0); } @@ -896,6 +1000,7 @@ void lcd_ctrl_init(void *lcdbase) } karo_fdt_move_fdt(); + lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt); if (video_mode == NULL) { debug("Disabling LCD\n"); @@ -1028,11 +1133,10 @@ void lcd_ctrl_init(void *lcdbase) p->pixclock = KHZ2PICOS(refresh * (p->xres + p->left_margin + p->right_margin + p->hsync_len) * - (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) - / 1000); + (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) / + 1000); debug("Pixel clock set to %lu.%03lu MHz\n", - PICOS2KHZ(p->pixclock) / 1000, - PICOS2KHZ(p->pixclock) % 1000); + PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000); if (p != &fb_mode) { int ret; @@ -1132,7 +1236,6 @@ static void stk5v5_board_init(void) static void tx53_set_cpu_clock(void) { unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0); - int ret; if (had_ctrlc() || (wrsr & WRSR_TOUT)) return; @@ -1140,14 +1243,13 @@ static void tx53_set_cpu_clock(void) if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000) return; - ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK); - if (ret != 0) { + if (mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK) == 0) { + cpu_clk = mxc_get_clock(MXC_ARM_CLK); + printf("CPU clock set to %lu.%03lu MHz\n", + cpu_clk / 1000000, cpu_clk / 1000 % 1000); + } else { printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk); - return; } - printf("CPU clock set to %u.%03u MHz\n", - mxc_get_clock(MXC_ARM_CLK) / 1000000, - mxc_get_clock(MXC_ARM_CLK) / 1000 % 1000); } static void tx53_init_mac(void) @@ -1176,12 +1278,20 @@ int board_late_init(void) if (!baseboard) goto exit; + printf("Baseboard: %s\n", baseboard); + if (strncmp(baseboard, "stk5", 4) == 0) { - printf("Baseboard: %s\n", baseboard); if ((strlen(baseboard) == 4) || strcmp(baseboard, "stk5-v3") == 0) { stk5v3_board_init(); } else if (strcmp(baseboard, "stk5-v5") == 0) { + const char *otg_mode = getenv("otg_mode"); + + if (otg_mode && strcmp(otg_mode, "host") == 0) { + printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n", + otg_mode, baseboard); + setenv("otg_mode", "none"); + } stk5v5_board_init(); } else { printf("WARNING: Unsupported STK5 board rev.: %s\n", @@ -1195,6 +1305,7 @@ int board_late_init(void) exit: tx53_init_mac(); + gpio_set_value(TX53_RESET_OUT_GPIO, 1); clear_ctrlc(); return ret; @@ -1217,7 +1328,6 @@ int checkboard(void) static struct node_info nodes[] = { { "fsl,imx53-nand", MTD_DEV_TYPE_NAND, }, }; - #else #define fdt_fixup_mtdparts(b,n,c) do { } while (0) #endif @@ -1234,20 +1344,10 @@ static inline void tx53_fixup_rtc(void *blob) } #endif /* CONFIG_SYS_TX53_HWREV_2 */ -#ifndef CONFIG_SYS_LVDS_IF -static inline void tx53_fdt_fixup_sata(void *blob) -{ - karo_fdt_enable_node(blob, "/soc/sata", 0); -} -#else -static inline void tx53_fdt_fixup_sata(void *blob) -{ -} -#endif - static const char *tx53_touchpanels[] = { "ti,tsc2007", "edt,edt-ft5x06", + "eeti,egalax_ts", }; void ft_board_setup(void *blob, bd_t *bd) @@ -1255,13 +1355,21 @@ void ft_board_setup(void *blob, bd_t *bd) const char *baseboard = getenv("baseboard"); int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0); const char *video_mode = karo_get_vmode(getenv("video_mode")); + int ret; + + ret = fdt_increase_size(blob, 4096); + if (ret) + printf("Failed to increase FDT size: %s\n", fdt_strerror(ret)); + + if (stk5_v5) + karo_fdt_enable_node(blob, "stk5led", 0); fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); fdt_fixup_ethernet(blob); karo_fdt_fixup_touchpanel(blob, tx53_touchpanels, ARRAY_SIZE(tx53_touchpanels)); - karo_fdt_fixup_usb_otg(blob, "fsl,imx-otg", "fsl,usbphy"); + karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy"); karo_fdt_fixup_flexcan(blob, stk5_v5); tx53_fixup_rtc(blob); karo_fdt_update_fb_mode(blob, video_mode);