X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=board%2Fkaro%2Ftx6%2Flowlevel_init.S;h=d9abf72d4e106688dec05d6bfe834a6de433ebd7;hp=3ef04a8f957bb7979b79d938689fdcbb1d4054eb;hb=0bacb4d60fb1d17a66c032eb13ed8d01599bcc37;hpb=2d2e56167cfbdae55f114162a7906d56d057a538 diff --git a/board/karo/tx6/lowlevel_init.S b/board/karo/tx6/lowlevel_init.S index 3ef04a8f95..d9abf72d4e 100644 --- a/board/karo/tx6/lowlevel_init.S +++ b/board/karo/tx6/lowlevel_init.S @@ -17,25 +17,42 @@ #define SDRAM_CLK CONFIG_SYS_SDRAM_CLK #ifdef PHYS_SDRAM_2_SIZE -#define SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) +#define SDRAM_SIZE ((PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) / SZ_1M) #else -#define SDRAM_SIZE PHYS_SDRAM_1_SIZE +#define SDRAM_SIZE (PHYS_SDRAM_1_SIZE / SZ_1M) #endif +#define BIT(x) (1 << (x)) +#define CCGR(m) (3 << ((m) * 2)) + #define CPU_2_BE_32(l) \ ((((l) << 24) & 0xFF000000) | \ (((l) << 8) & 0x00FF0000) | \ (((l) >> 8) & 0x0000FF00) | \ (((l) >> 24) & 0x000000FF)) -#define CHECK_DCD_ADDR(a) ( \ +#ifndef CONFIG_TX6QP +#define CHECK_DCD_ADDR(a) ( \ ((a) >= 0x020E0000 && (a) <= 0x020E3FFF) /* IOMUXC */ || \ - ((a) >= 0x020C4000 && (a) <= 0x020C7FFF) /* CCM */ || \ + ((a) >= 0x020C4000 && (a) <= 0x020C7FFF) /* CCM */ || \ ((a) >= 0x020C8000 && (a) <= 0x020C8FFF) /* ANALOG */ || \ - ((a) >= 0x021B0000 && (a) <= 0x021B7FFF) /* MMDC */ || \ - ((a) >= 0x00907000 && (a) <= 0x00937FF0) /* OCRAM */ || \ + ((a) >= 0x021B0000 && (a) <= 0x021B7FFF) /* MMDC */ || \ + ((a) >= 0x00907000 && (a) <= 0x00937FF0) /* OCRAM */ || \ ((a) >= 0x08000000 && (a) <= 0x0FFEFFFF) /* EIM (CS0) */ || \ + ((a) >= 0x021B8000 && (a) <= 0x021BBFFF) /* EIM registers */ || \ ((a) >= 0x10000000 && (a) <= 0xFFFFFFFF) /* SDRAM */) +#else +#define CHECK_DCD_ADDR(a) ( \ + ((a) >= 0x020E0000 && (a) <= 0x020E3FFF) /* IOMUXC */ || \ + ((a) >= 0x020C4000 && (a) <= 0x020C7FFF) /* CCM */ || \ + ((a) >= 0x020C8000 && (a) <= 0x020C8FFF) /* ANALOG */ || \ + ((a) >= 0x021B0000 && (a) <= 0x021B7FFF) /* MMDC */ || \ + ((a) >= 0x00907000 && (a) <= 0x00937FF0) /* OCRAM */ || \ + ((a) >= 0x08000000 && (a) <= 0x0FFEFFFF) /* EIM (CS0) */ || \ + ((a) >= 0x021B8000 && (a) <= 0x021BBFFF) /* EIM registers */ || \ + ((a) >= 0x10000000 && (a) <= 0xFFFFFFFF) /* SDRAM */ || \ + ((a) >= 0x00BB0000 && (a) <= 0x00BB003F) /* NoC DDR config */) +#endif .macro mxc_dcd_item addr, val .ifne CHECK_DCD_ADDR(\addr) @@ -111,6 +128,7 @@ dcd_end: #define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK) #define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000) #define NS_TO_CK10(ns) DIV_ROUND_UP(NS_TO_CK(ns), 10) +#define NS_TO_CK100(ns) DIV_ROUND_UP(NS_TO_CK(ns), 100) #define PS_TO_CK(ps) DIV_ROUND_UP(NS_TO_CK(ps), 1000) .macro CK_VAL, name, clks, offs, max @@ -182,6 +200,10 @@ dcd_end: #error SDRAM clock out of range: 303 .. 800 #endif +#if SDRAM_SIZE < 2048 +#define ROW_ADDR_BITS 14 +#define COL_ADDR_BITS 10 + /* MDCFG0 0x0c */ NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */ CK_MAX tXS, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */ @@ -208,6 +230,39 @@ CK_MAX tRRD, NS_TO_CK(10), 4, 1, 7 /* clks - 1 (0..7) (MT41K128M16JT: 6ns) */ /* MDOR 0x30 */ CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */ +#else +/* 4096MiB SDRAM: IM4G16D3EABG-125I */ +#define ROW_ADDR_BITS 15 +#define COL_ADDR_BITS 10 + +/* MDCFG0 0x0c */ +NS_VAL tRFC, 260, 1, 255 /* clks - 1 (0..255) */ +CK_MAX tXS, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */ +CK_MAX tXP, NS_TO_CK(6), 3, 1, 7 /* clks - 1 (0..7) */ /* max(3tCK, 7.5ns) */ +CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */ +NS_VAL tFAW, 30, 1, 31 /* clks - 1 (0..31) */ +CK_VAL tCL, CL_VAL, 3, 8 /* clks - 3 (0..8) CAS Latency */ + +/* MDCFG1 0x10 */ +CK_VAL tRCD, NS_TO_CK100(1375), 1, 7 /* clks - 1 (0..7) */ /* 13.75 */ +CK_VAL tRP, NS_TO_CK100(1375), 1, 7 /* clks - 1 (0..7) */ /* 13.75 */ +CK_VAL tRC, NS_TO_CK100(4875), 1, 31 /* clks - 1 (0..31) */ /* 48.75 */ +CK_VAL tRAS, NS_TO_CK(35), 1, 31 /* clks - 1 (0..31) */ /* 35 */ +CK_VAL tRPA, 1, 0, 1 /* clks (0..1) */ +NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */ +CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */ +CK_VAL tCWL, CWL_VAL, 2, 6 /* clks - 2 (0..6) */ + +/* MDCFG2 0x14 */ +CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */ +CK_MAX tRTP, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */ +CK_MAX tWTR, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */ +CK_MAX tRRD, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */ + +/* MDOR 0x30 */ +CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */ +#endif + #define tSDE_RST (DIV_ROUND_UP(200000, MDOR_CLK_PERIOD_ns) + 2) #define tRST_CKE (DIV_ROUND_UP(500000, MDOR_CLK_PERIOD_ns) + 2) @@ -244,9 +299,6 @@ CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7 (PWDT << 8) \ ) -#define ROW_ADDR_BITS 14 -#define COL_ADDR_BITS 10 - #define Rtt_Nom 1 /* ODT: 0: off 1: RZQ/4 2: RZQ/2 3: RZQ/6 4: RZQ/12 5: RZQ/8 */ #define Rtt_WR 0 /* Dynamic ODT: 0: off 1: RZQ/4 2: RZQ/2 */ #define DLL_DISABLE 0 @@ -413,7 +465,9 @@ ivt_end: #define MMDC1_MDOR 0x021b0030 #define MMDC1_MDASP 0x021b0040 +#define MMDC1_MAARCR 0x021b0400 #define MMDC1_MAPSR 0x021b0404 +#define MMDC1_MADPCR0 0x021b0410 #define MMDC1_MPZQHWCTRL 0x021b0800 #define MMDC1_MPWLGCR 0x021b0808 @@ -434,7 +488,11 @@ ivt_end: #define MMDC1_MPWRDLST 0x021b0854 #define MMDC1_MPRDDLHWCTL 0x021b0860 #define MMDC1_MPWRDLHWCTL 0x021b0864 +#define MMDC1_MPDGHWST0 0x021b087c +#define MMDC1_MPDGHWST1 0x021b0880 #define MMDC1_MPPDCMPR2 0x021b0890 +#define MMDC1_MPDGHWST2 0x021b0884 +#define MMDC1_MPDGHWST3 0x021b0888 #define MMDC1_MPSWDRDR0 0x021b0898 #define MMDC1_MPSWDRDR1 0x021b089c #define MMDC1_MPSWDRDR2 0x021b08a0 @@ -486,7 +544,20 @@ ivt_end: #endif #ifdef CONFIG_SOC_MX6Q +#define IOMUXC_GPR0 0x020e0000 #define IOMUXC_GPR1 0x020e0004 +#define IOMUXC_GPR2 0x020e0008 +#define IOMUXC_GPR3 0x020e000c +#define IOMUXC_GPR4 0x020e0010 +#define IOMUXC_GPR5 0x020e0014 +#define IOMUXC_GPR6 0x020e0018 +#define IOMUXC_GPR7 0x020e001c +#define IOMUXC_GPR8 0x020e0020 +#define IOMUXC_GPR9 0x020e0024 +#define IOMUXC_GPR10 0x020e0028 +#define IOMUXC_GPR11 0x020e002c +#define IOMUXC_GPR12 0x020e0030 +#define IOMUXC_GPR13 0x020e0034 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20 0x020e00a0 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 0x020e00a4 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28 0x020e00c4 @@ -595,9 +666,7 @@ ivt_end: #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21 0x020e0898 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28 0x020e089c #define TX6_I2C1_SEL_INP_VAL 0 -#endif - -#if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S) +#elif defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S) #define IOMUXC_GPR1 0x020e0004 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20 0x020e0154 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 0x020e0158 @@ -723,27 +792,48 @@ dcd_hdr: /* RESET_OUT GPIO_7_12 */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_GPIO17, 0x00000005) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_GPIO17, 0x000030b0) - +#ifndef CONFIG_TX6_EMMC + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CLR) + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, CCGR(14)) + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR(7)) + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) +#ifndef CONFIG_TX6QP MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x006336c1) /* default: 0x007236c1 */ - MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CHSCCDR, 0x00012093) /* default: 0x0002a150 */ - MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CSCDR2, 0x00012090) /* default: 0x0002a150 */ - +#else + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x0061b6c1) /* default: 0x007236c1 */ +#endif + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET) + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, CCGR(14)) + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR(7)) + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) +#endif + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CHSCCDR, 0x00012093) /* default: 0x0002a150 (0x00029148) */ + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CSCDR2, 0x00012090) /* default: 0x0002a150 (0x00029148) */ MXC_DCD_ITEM(ANATOP_BASE_ADDR + ANATOP_PLL_ENET, 0x00002001) /* ENET PLL */ /* enable all relevant clocks... */ - MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR0, 0xf0c03f3f) /* default: 0xf0c03f0f APBH-DMA */ - MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, 0xf0fc0c00) /* default: 0xf0fc0000 */ - MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, 0xfc3ff0cc) /* default: 0xfc3ff00c I2C1 */ - MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR3, 0x3ff00000) /* default: 0x3ff00000 */ - MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, 0xff00ff00) /* default: 0x0000ff00 GPMI BCH */ - MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR5, 0xff033f0f) /* default: 0xf0033f0f UART1 */ - MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, 0xffff03ff) /* default: 0xffff0003 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) */ - MXC_DCD_ITEM(0x020c80a0, 0x80082029) /* set video PLL to 984MHz */ + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET) + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR0, CCGR(2)) /* 0xf0c03f3f default: 0xf0c03f0f APBH-DMA */ + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, CCGR(5)) /* 0xf0fc0c00 default: 0xf0fc0000 ENET */ + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR(3)) /* 0xfc3fc0cc default: 0xfc3fc00c I2C1 */ +// MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR3, CCGR()) /* 0x3ff00000 default: 0x3ff0000f */ + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, CCGR(15) | CCGR(14) | CCGR(13) | CCGR(12)) /* 0xff00ff00 default: 0x0000ff00 GPMI BCH */ + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR5, CCGR(13) | CCGR(12)) /* 0xff033f3f default: 0xf0033f3f UART1 */ + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, CCGR(4) | CCGR(3) | CCGR(2) | CCGR(1)) /* 0xffff03ff default: 0xffff0000 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) USDHC1 USDHC1 */ + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) + MXC_DCD_ITEM(0x020c80a0, 0x00082029) /* set video PLL to 498MHz */ MXC_DCD_ITEM(0x020c80b0, 0x00065b9a) MXC_DCD_ITEM(0x020c80c0, 0x000f4240) /* IOMUX: */ MXC_DCD_ITEM(IOMUXC_GPR1, 0x48640005) /* default: 0x48400005 ENET_CLK output */ +#ifdef CONFIG_TX6QP + /* enable AXI cache for VDOA/VPU/IPU */ + MXC_DCD_ITEM(IOMUXC_GPR4, 0xf00000cf) + /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */ + MXC_DCD_ITEM(IOMUXC_GPR6, 0x77177717) + MXC_DCD_ITEM(IOMUXC_GPR7, 0x77177717) +#endif /* UART1 pad config */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7, 0x00000001) /* UART1 TXD */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6, 0x00000001) /* UART1 RXD */ @@ -882,12 +972,22 @@ dcd_hdr: MXC_DCD_ITEM_32(MMDC1_MPWLDECTRL1, (WL_DLY_DQS3 << 16) | (WL_DLY_DQS2 << 0)) MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL0, (WL_DLY_DQS5 << 16) | (WL_DLY_DQS4 << 0)) MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL1, (WL_DLY_DQS7 << 16) | (WL_DLY_DQS6 << 0)) - - MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x43240334) - MXC_DCD_ITEM(MMDC1_MPDGCTRL1, 0x0324031a) - MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x43340344) - MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x03280276) - +#if defined(CONFIG_SOC_MX6Q) + MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x43430349) + MXC_DCD_ITEM_32(MMDC1_MPDGCTRL1, 0x03330334) + MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x434b0351) + MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x033d030e) +#elif defined(CONFIG_SOC_MX6DL) + MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x423a0236) + MXC_DCD_ITEM_32(MMDC1_MPDGCTRL1, 0x02210227) + MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x42240226) + MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x02120223) +#elif defined(CONFIG_SOC_MX6S) + MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x42490244) + MXC_DCD_ITEM_32(MMDC1_MPDGCTRL1, 0x022f0238) +#else +#error No DGCTRL settings for selected SoC +#endif MXC_DCD_ITEM(MMDC1_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */ MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */ MXC_DCD_ITEM_64(MMDC2_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */ @@ -953,6 +1053,11 @@ dcd_hdr: /* DDR3 calibration */ MXC_DCD_ITEM(MMDC1_MPPDCMPR2, 0x00000003) /* select default compare pattern for DQ calibration */ +#ifdef CONFIG_TX6QP + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET) + MXC_DCD_ITEM(MMDC1_MAARCR, BIT(25)) /* MMDC reorder disable BOOT_CFG3[5:4] */ + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) +#endif MXC_DCD_ITEM(MMDC1_MAPSR, 1) #ifdef DO_DDR_CALIB @@ -969,8 +1074,6 @@ dcd_hdr: #if BANK_ADDR_BITS > 1 MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */ #endif - - MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL) /* DRAM_SDQS[0..7] pad config */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK)