X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=board%2Fkaro%2Ftx6%2Ftx6qdl.c;h=5d2317dde43072ad72a692b91942587452499495;hp=2b59efb0e77f850bf29918f2119509dcd2c32340;hb=1f2979b99ea4206881f280fe3ed12bc67c36ece7;hpb=4c4ce6b7b01b7a0c30ae6d5f8e6b6a241f9b4ffb

diff --git a/board/karo/tx6/tx6qdl.c b/board/karo/tx6/tx6qdl.c
index 2b59efb0e7..5d2317dde4 100644
--- a/board/karo/tx6/tx6qdl.c
+++ b/board/karo/tx6/tx6qdl.c
@@ -37,10 +37,11 @@
 #include <asm/arch/sys_proto.h>
 
 #include "../common/karo.h"
+#include "pmic.h"
 
 #define TX6_FEC_RST_GPIO		IMX_GPIO_NR(7, 6)
 #define TX6_FEC_PWR_GPIO		IMX_GPIO_NR(3, 20)
-#define TX6_FEC_INT_GPIO		IMX_GPIO_NR(2, 4)
+#define TX6_FEC_INT_GPIO		IMX_GPIO_NR(7, 1)
 #define TX6_LED_GPIO			IMX_GPIO_NR(2, 20)
 
 #define TX6_LCD_PWR_GPIO		IMX_GPIO_NR(2, 31)
@@ -58,6 +59,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define MUX_CFG_SION			IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
 
 static const iomux_v3_cfg_t tx6qdl_pads[] = {
+#ifndef CONFIG_NO_NAND
 	/* NAND flash pads */
 	MX6_PAD_NANDF_CLE__RAWNAND_CLE,
 	MX6_PAD_NANDF_ALE__RAWNAND_ALE,
@@ -74,7 +76,7 @@ static const iomux_v3_cfg_t tx6qdl_pads[] = {
 	MX6_PAD_NANDF_D5__RAWNAND_D5,
 	MX6_PAD_NANDF_D6__RAWNAND_D6,
 	MX6_PAD_NANDF_D7__RAWNAND_D7,
-
+#endif
 	/* RESET_OUT */
 	MX6_PAD_GPIO_17__GPIO_7_12,
 
@@ -195,6 +197,8 @@ static void print_reset_cause(void)
 int read_cpu_temperature(void);
 int check_cpu_temperature(int boot);
 
+static const char *tx6_mod_suffix;
+
 static void tx6qdl_print_cpuinfo(void)
 {
 	u32 cpurev = get_cpu_rev();
@@ -203,15 +207,19 @@ static void tx6qdl_print_cpuinfo(void)
 	switch ((cpurev >> 12) & 0xff) {
 	case MXC_CPU_MX6SL:
 		cpu_str = "SL";
+		tx6_mod_suffix = "?";
 		break;
 	case MXC_CPU_MX6DL:
 		cpu_str = "DL";
+		tx6_mod_suffix = "U";
 		break;
 	case MXC_CPU_MX6SOLO:
 		cpu_str = "SOLO";
+		tx6_mod_suffix = "S";
 		break;
 	case MXC_CPU_MX6Q:
 		cpu_str = "Q";
+		tx6_mod_suffix = "Q";
 		break;
 	}
 
@@ -225,192 +233,6 @@ static void tx6qdl_print_cpuinfo(void)
 	check_cpu_temperature(1);
 }
 
-#define LTC3676_BUCK1		0x01
-#define LTC3676_BUCK2		0x02
-#define LTC3676_BUCK3		0x03
-#define LTC3676_BUCK4		0x04
-#define LTC3676_DVB1A		0x0A
-#define LTC3676_DVB1B		0x0B
-#define LTC3676_DVB2A		0x0C
-#define LTC3676_DVB2B		0x0D
-#define LTC3676_DVB3A		0x0E
-#define LTC3676_DVB3B		0x0F
-#define LTC3676_DVB4A		0x10
-#define LTC3676_DVB4B		0x11
-#define LTC3676_MSKPG		0x13
-#define LTC3676_CLIRQ		0x1f
-
-#define LTC3676_BUCK_DVDT_FAST	(1 << 0)
-#define LTC3676_BUCK_KEEP_ALIVE	(1 << 1)
-#define LTC3676_BUCK_CLK_RATE_LOW (1 << 2)
-#define LTC3676_BUCK_PHASE_SEL	(1 << 3)
-#define LTC3676_BUCK_ENABLE_300	(1 << 4)
-#define LTC3676_BUCK_PULSE_SKIP	(0 << 5)
-#define LTC3676_BUCK_BURST_MODE	(1 << 5)
-#define LTC3676_BUCK_CONTINUOUS	(2 << 5)
-#define LTC3676_BUCK_ENABLE	(1 << 7)
-
-#define LTC3676_PGOOD_MASK	(1 << 5)
-
-#define LTC3676_MSKPG_BUCK1	(1 << 0)
-#define LTC3676_MSKPG_BUCK2	(1 << 1)
-#define LTC3676_MSKPG_BUCK3	(1 << 2)
-#define LTC3676_MSKPG_BUCK4	(1 << 3)
-#define LTC3676_MSKPG_LDO2	(1 << 5)
-#define LTC3676_MSKPG_LDO3	(1 << 6)
-#define LTC3676_MSKPG_LDO4	(1 << 7)
-
-#define VDD_IO_VAL		mV_to_regval(vout_to_vref(3300 * 10, 5))
-#define VDD_IO_VAL_LP		mV_to_regval(vout_to_vref(3100 * 10, 5))
-#define VDD_IO_VAL_2		mV_to_regval(vout_to_vref(3300 * 10, 5_2))
-#define VDD_IO_VAL_2_LP		mV_to_regval(vout_to_vref(3100 * 10, 5_2))
-#define VDD_SOC_VAL		mV_to_regval(vout_to_vref(1425 * 10, 6))
-#define VDD_SOC_VAL_LP		mV_to_regval(vout_to_vref(900 * 10, 6))
-#define VDD_DDR_VAL		mV_to_regval(vout_to_vref(1500 * 10, 7))
-#define VDD_CORE_VAL		mV_to_regval(vout_to_vref(1425 * 10, 8))
-#define VDD_CORE_VAL_LP		mV_to_regval(vout_to_vref(900 * 10, 8))
-
-/* LDO1 */
-#define R1_1			470
-#define R2_1			150
-/* LDO4 */
-#define R1_4			470
-#define R2_4			150
-/* Buck1 */
-#define R1_5			390
-#define R2_5			110
-#define R1_5_2			470
-#define R2_5_2			150
-/* Buck2 */
-#define R1_6			150
-#define R2_6			180
-/* Buck3 */
-#define R1_7			150
-#define R2_7			140
-/* Buck4 */
-#define R1_8			150
-#define R2_8			180
-
-/* calculate voltages in 10mV */
-#define R1(idx)			R1_##idx
-#define R2(idx)			R2_##idx
-
-#define vout_to_vref(vout, idx)	((vout) * R2(idx) / (R1(idx) + R2(idx)))
-#define vref_to_vout(vref, idx)	DIV_ROUND_UP((vref) * (R1(idx) + R2(idx)), R2(idx))
-
-#define mV_to_regval(mV)	DIV_ROUND(((((mV) < 4125) ? 4125 : (mV)) - 4125), 125)
-#define regval_to_mV(v)		(((v) * 125 + 4125))
-
-static struct ltc3673_regs {
-	u8 addr;
-	u8 val;
-	u8 mask;
-} ltc3676_regs[] = {
-	{ LTC3676_MSKPG, ~LTC3676_MSKPG_BUCK1, },
-	{ LTC3676_DVB2B, VDD_SOC_VAL | LTC3676_PGOOD_MASK, ~0x3f, },
-	{ LTC3676_DVB3B, VDD_DDR_VAL, ~0x3f, },
-	{ LTC3676_DVB4B, VDD_CORE_VAL | LTC3676_PGOOD_MASK, ~0x3f, },
-	{ LTC3676_DVB2A, VDD_SOC_VAL, ~0x3f, },
-	{ LTC3676_DVB3A, VDD_DDR_VAL, ~0x3f, },
-	{ LTC3676_DVB4A, VDD_CORE_VAL, ~0x3f, },
-	{ LTC3676_BUCK1, LTC3676_BUCK_BURST_MODE | LTC3676_BUCK_CLK_RATE_LOW, },
-	{ LTC3676_BUCK2, LTC3676_BUCK_BURST_MODE, },
-	{ LTC3676_BUCK3, LTC3676_BUCK_BURST_MODE, },
-	{ LTC3676_BUCK4, LTC3676_BUCK_BURST_MODE, },
-	{ LTC3676_CLIRQ, 0, }, /* clear interrupt status */
-};
-
-static struct ltc3673_regs ltc3676_regs_1[] = {
-	{ LTC3676_DVB1B, VDD_IO_VAL_LP | LTC3676_PGOOD_MASK, ~0x3f, },
-	{ LTC3676_DVB1A, VDD_IO_VAL, ~0x3f, },
-};
-
-static struct ltc3673_regs ltc3676_regs_2[] = {
-	{ LTC3676_DVB1B, VDD_IO_VAL_2_LP | LTC3676_PGOOD_MASK, ~0x3f, },
-	{ LTC3676_DVB1A, VDD_IO_VAL_2, ~0x3f, },
-};
-
-static int tx6_rev_2(void)
-{
-	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
-	struct fuse_bank5_regs *fuse = (void *)ocotp->bank[5].fuse_regs;
-	u32 pad_settings = readl(&fuse->pad_settings);
-
-	debug("Fuse pad_settings @ %p = %08x\n",
-		&fuse->pad_settings, pad_settings);
-	return pad_settings & 1;
-}
-
-static int tx6_ltc3676_setup_regs(struct ltc3673_regs *r, size_t count)
-{
-	int ret;
-	int i;
-
-	for (i = 0; i < count; i++, r++) {
-#ifdef DEBUG
-		unsigned char value;
-
-		ret = i2c_read(CONFIG_SYS_I2C_SLAVE, r->addr, 1, &value, 1);
-		if ((value & ~r->mask) != r->val) {
-			printf("Changing PMIC reg %02x from %02x to %02x\n",
-				r->addr, value, r->val);
-		}
-		if (ret) {
-			printf("%s: failed to read PMIC register %02x: %d\n",
-				__func__, r->addr, ret);
-			return ret;
-		}
-#endif
-		ret = i2c_write(CONFIG_SYS_I2C_SLAVE,
-				r->addr, 1, &r->val, 1);
-		if (ret) {
-			printf("%s: failed to write PMIC register %02x: %d\n",
-				__func__, r->addr, ret);
-			return ret;
-		}
-	}
-	return 0;
-}
-
-static int setup_pmic_voltages(void)
-{
-	int ret;
-	unsigned char value;
-
-	ret = i2c_probe(CONFIG_SYS_I2C_SLAVE);
-	if (ret != 0) {
-		printf("Failed to initialize I2C\n");
-		return ret;
-	}
-
-	ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1);
-	if (ret) {
-		printf("%s: i2c_read error: %d\n", __func__, ret);
-		return ret;
-	}
-
-	ret = tx6_ltc3676_setup_regs(ltc3676_regs, ARRAY_SIZE(ltc3676_regs));
-	if (ret)
-		return ret;
-
-	printf("VDDCORE set to %umV\n",
-		DIV_ROUND(vref_to_vout(regval_to_mV(VDD_CORE_VAL), 8), 10));
-	printf("VDDSOC  set to %umV\n",
-		DIV_ROUND(vref_to_vout(regval_to_mV(VDD_SOC_VAL), 6), 10));
-
-	if (tx6_rev_2()) {
-		ret = tx6_ltc3676_setup_regs(ltc3676_regs_2,
-				ARRAY_SIZE(ltc3676_regs_2));
-		printf("VDDIO   set to %umV\n",
-			DIV_ROUND(vref_to_vout(
-					regval_to_mV(VDD_IO_VAL_2), 5_2), 10));
-	} else {
-		ret = tx6_ltc3676_setup_regs(ltc3676_regs_1,
-				ARRAY_SIZE(ltc3676_regs_1));
-	}
-	return ret;
-}
-
 int board_early_init_f(void)
 {
 	gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
@@ -425,15 +247,13 @@ int board_init(void)
 
 	/* Address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
-#ifdef CONFIG_OF_LIBFDT
 	gd->bd->bi_arch_number = -1;
-#else
-	gd->bd->bi_arch_number = 4429;
-#endif
+
 	if (ctrlc()) {
 		printf("CTRL-C detected; Skipping PMIC setup\n");
 		return 1;
 	}
+
 	ret = setup_pmic_voltages();
 	if (ret) {
 		printf("Failed to setup PMIC voltages\n");
@@ -463,28 +283,45 @@ void dram_init_banksize(void)
 }
 
 #ifdef	CONFIG_CMD_MMC
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
 static const iomux_v3_cfg_t mmc0_pads[] = {
-	MX6_PAD_SD1_CMD__USDHC1_CMD,
-	MX6_PAD_SD1_CLK__USDHC1_CLK,
-	MX6_PAD_SD1_DAT0__USDHC1_DAT0,
-	MX6_PAD_SD1_DAT1__USDHC1_DAT1,
-	MX6_PAD_SD1_DAT2__USDHC1_DAT2,
-	MX6_PAD_SD1_DAT3__USDHC1_DAT3,
+	MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	/* SD1 CD */
 	MX6_PAD_SD3_CMD__GPIO_7_2,
 };
 
 static const iomux_v3_cfg_t mmc1_pads[] = {
-	MX6_PAD_SD2_CMD__USDHC2_CMD,
-	MX6_PAD_SD2_CLK__USDHC2_CLK,
-	MX6_PAD_SD2_DAT0__USDHC2_DAT0,
-	MX6_PAD_SD2_DAT1__USDHC2_DAT1,
-	MX6_PAD_SD2_DAT2__USDHC2_DAT2,
-	MX6_PAD_SD2_DAT3__USDHC2_DAT3,
+	MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	/* SD2 CD */
 	MX6_PAD_SD3_CLK__GPIO_7_3,
 };
 
+#ifdef CONFIG_MMC_BOOT_SIZE
+static const iomux_v3_cfg_t mmc3_pads[] = {
+	MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	/* eMMC RESET */
+	MX6_PAD_NANDF_ALE__USDHC4_RST,
+};
+#endif
+
 static struct tx6_esdhc_cfg {
 	const iomux_v3_cfg_t *pads;
 	int num_pads;
@@ -492,6 +329,18 @@ static struct tx6_esdhc_cfg {
 	struct fsl_esdhc_cfg cfg;
 	int cd_gpio;
 } tx6qdl_esdhc_cfg[] = {
+#ifdef CONFIG_MMC_BOOT_SIZE
+	{
+		.pads = mmc3_pads,
+		.num_pads = ARRAY_SIZE(mmc3_pads),
+		.clkid = MXC_ESDHC4_CLK,
+		.cfg = {
+			.esdhc_base = (void __iomem *)USDHC4_BASE_ADDR,
+			.max_bus_width = 4,
+		},
+		.cd_gpio = -EINVAL,
+	},
+#endif
 	{
 		.pads = mmc0_pads,
 		.num_pads = ARRAY_SIZE(mmc0_pads),
@@ -524,7 +373,7 @@ int board_mmc_getcd(struct mmc *mmc)
 	struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
 
 	if (cfg->cd_gpio < 0)
-		return cfg->cd_gpio;
+		return 1;
 
 	debug("SD card %d is %spresent\n",
 		cfg - tx6qdl_esdhc_cfg,
@@ -541,18 +390,17 @@ int board_mmc_init(bd_t *bis)
 		struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
 		int ret;
 
-		if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
-			break;
-
 		cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
 		imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
 
-		ret = gpio_request_one(cfg->cd_gpio,
-				GPIOF_INPUT, "MMC CD");
-		if (ret) {
-			printf("Error %d requesting GPIO%d_%d\n",
-				ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
-			continue;
+		if (cfg->cd_gpio >= 0) {
+			ret = gpio_request_one(cfg->cd_gpio,
+					GPIOF_INPUT, "MMC CD");
+			if (ret) {
+				printf("Error %d requesting GPIO%d_%d\n",
+					ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
+				continue;
+			}
 		}
 
 		debug("%s: Initializing MMC slot %d\n", __func__, i);
@@ -561,7 +409,7 @@ int board_mmc_init(bd_t *bis)
 		mmc = find_mmc_device(i);
 		if (mmc == NULL)
 			continue;
-		if (board_mmc_getcd(mmc) > 0)
+		if (board_mmc_getcd(mmc))
 			mmc_init(mmc);
 	}
 	return 0;
@@ -641,36 +489,6 @@ static const iomux_v3_cfg_t stk5_pads[] = {
 	/* SW controlled LED on STK5 baseboard */
 	MX6_PAD_EIM_A18__GPIO_2_20,
 
-	/* LCD data pins */
-	MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
-	MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
-	MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
-	MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
-	MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
-	MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
-	MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
-	MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
-	MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
-	MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
-	MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
-	MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
-	MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
-	MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
-	MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
-	MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
-	MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
-	MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
-	MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
-	MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
-	MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
-	MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
-	MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
-	MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
-	MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* HSYNC */
-	MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* VSYNC */
-	MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
-	MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
-
 	/* I2C bus on DIMM pins 40/41 */
 	MX6_PAD_GPIO_6__I2C3_SDA,
 	MX6_PAD_GPIO_3__I2C3_SCL,
@@ -703,12 +521,14 @@ static const struct gpio stk5_gpios[] = {
 };
 
 #ifdef CONFIG_LCD
+static u16 tx6_cmap[256];
 vidinfo_t panel_info = {
 	/* set to max. size supported by SoC */
 	.vl_col = 1920,
 	.vl_row = 1080,
 
 	.vl_bpix = LCD_COLOR24,	   /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
+	.cmap = tx6_cmap,
 };
 
 static struct fb_videomode tx6_fb_modes[] = {
@@ -831,6 +651,23 @@ static struct fb_videomode tx6_fb_modes[] = {
 		.lower_margin	= 525 - 480 - 35,
 		.sync		= FB_SYNC_CLK_LAT_FALL,
 	},
+	{
+		/* Emerging ET070001DM6 800 x 480 display.
+		 * 152.4 mm x 91.44 mm display area.
+		 */
+		.name		= "ET070001DM6",
+		.refresh	= 60,
+		.xres		= 800,
+		.yres		= 480,
+		.pixclock	= KHZ2PICOS(33260),
+		.left_margin	= 216 - 128,
+		.hsync_len	= 128,
+		.right_margin	= 1056 - 800 - 216,
+		.upper_margin	= 35 - 2,
+		.vsync_len	= 2,
+		.lower_margin	= 525 - 480 - 35,
+		.sync		= 0,
+	},
 #else
 	{
 		/* HannStar HSD100PXN1
@@ -864,6 +701,12 @@ static struct fb_videomode tx6_fb_modes[] = {
 };
 
 static int lcd_enabled = 1;
+static int lcd_bl_polarity;
+
+static int lcd_backlight_polarity(void)
+{
+	return lcd_bl_polarity;
+}
 
 void lcd_enable(void)
 {
@@ -882,7 +725,8 @@ void lcd_enable(void)
 		udelay(100);
 		gpio_set_value(TX6_LCD_RST_GPIO, 1);
 		udelay(300000);
-		gpio_set_value(TX6_LCD_BACKLIGHT_GPIO, is_lvds());
+		gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
+			lcd_backlight_polarity());
 	}
 }
 
@@ -898,7 +742,8 @@ void lcd_panel_disable(void)
 {
 	if (lcd_enabled) {
 		debug("Switching LCD off\n");
-		gpio_set_value(TX6_LCD_BACKLIGHT_GPIO, !is_lvds());
+		gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
+			!lcd_backlight_polarity());
 		gpio_set_value(TX6_LCD_RST_GPIO, 0);
 		gpio_set_value(TX6_LCD_PWR_GPIO, 0);
 	}
@@ -912,11 +757,8 @@ static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 	/* LCD Backlight (PWM) */
 	MX6_PAD_GPIO_1__GPIO_1_1,
 
+#ifndef CONFIG_SYS_LVDS_IF
 	/* Display */
-	MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
-	MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
-	MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2,
-	MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3,
 	MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
 	MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
 	MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
@@ -941,6 +783,11 @@ static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 	MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
 	MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
 	MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
+	MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* HSYNC */
+	MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* VSYNC */
+	MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
+	MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
+#endif
 };
 
 static const struct gpio stk5_lcd_gpios[] = {
@@ -959,7 +806,8 @@ void lcd_ctrl_init(void *lcdbase)
 	struct fb_videomode *p = &tx6_fb_modes[0];
 	struct fb_videomode fb_mode;
 	int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
-	int pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB24;
+	int pix_fmt;
+	int lcd_bus_width;
 	unsigned long di_clk_rate = 65000000;
 
 	if (!lcd_enabled) {
@@ -975,6 +823,7 @@ void lcd_ctrl_init(void *lcdbase)
 	}
 
 	karo_fdt_move_fdt();
+	lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
 
 	if (video_mode == NULL) {
 		debug("Disabling LCD\n");
@@ -1029,7 +878,7 @@ void lcd_ctrl_init(void *lcdbase)
 					switch (val) {
 					case 32:
 					case 24:
-						if (pix_fmt == IPU_PIX_FMT_LVDS666)
+						if (is_lvds())
 							pix_fmt = IPU_PIX_FMT_LVDS888;
 						/* fallthru */
 					case 16:
@@ -1038,7 +887,7 @@ void lcd_ctrl_init(void *lcdbase)
 						break;
 
 					case 18:
-						if (pix_fmt == IPU_PIX_FMT_LVDS666) {
+						if (is_lvds()) {
 							color_depth = val;
 							break;
 						}
@@ -1127,24 +976,56 @@ void lcd_ctrl_init(void *lcdbase)
 	imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
 					ARRAY_SIZE(stk5_lcd_pads));
 
-	debug("Initializing FB driver\n");
-#ifdef CONFIG_SYS_LVDS_IF
-	if (pix_fmt == IPU_PIX_FMT_LVDS666) {
-		writel(0x01, IOMUXC_BASE_ADDR + 8);
-	} else if (pix_fmt == IPU_PIX_FMT_LVDS888) {
-		writel(0x21, IOMUXC_BASE_ADDR + 8);
+	lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
+	switch (lcd_bus_width) {
+	case 24:
+		pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
+		break;
+
+	case 18:
+		pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
+		break;
+
+	case 16:
+		if (!is_lvds()) {
+			pix_fmt = IPU_PIX_FMT_RGB565;
+			break;
+		}
+		/* fallthru */
+	default:
+		lcd_enabled = 0;
+		printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
+			lcd_bus_width);
+		return;
 	}
-	{
-		struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-		/* enable LDB & DI0 clock */
-		writel(readl(&ccm_regs->CCGR3) | MXC_CCM_CCGR3_LDB_DI0_MASK |
-			MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK,
-			&ccm_regs->CCGR3);
+	if (is_lvds()) {
+		int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
+		int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
+		uint32_t gpr2;
+
+		if (lvds_chan_mask == 0) {
+			printf("No LVDS channel active\n");
+			lcd_enabled = 0;
+			return;
+		}
+
+		gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
+		if (lcd_bus_width == 24)
+			gpr2 |= (1 << 5) | (1 << 7);
+		gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
+		gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
+		debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
+		writel(gpr2, IOMUXC_BASE_ADDR + 8);
 	}
-#endif
 	if (karo_load_splashimage(0) == 0) {
+		int ret;
+
 		debug("Initializing LCD controller\n");
-		ipuv3_fb_init(p, 0, pix_fmt, DI_PCLK_PLL3, di_clk_rate, -1);
+		ret = ipuv3_fb_init(p, 0, pix_fmt, DI_PCLK_PLL3, di_clk_rate, -1);
+		if (ret) {
+			printf("Failed to initialize FB driver: %d\n", ret);
+			lcd_enabled = 0;
+		}
 	} else {
 		debug("Skipping initialization of LCD controller\n");
 	}
@@ -1188,7 +1069,7 @@ static void tx6qdl_set_cpu_clock(void)
 		printf("CPU clock set to %lu.%03lu MHz\n",
 			cpu_clk / 1000000, cpu_clk / 1000 % 1000);
 	} else {
-		printf("Failed to set CPU clock to %lu MHz\n", cpu_clk);
+		printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
 	}
 }
 
@@ -1202,8 +1083,8 @@ static void tx6_init_mac(void)
 		return;
 	}
 
-	eth_setenv_enetaddr("ethaddr", mac);
 	printf("MAC addr from fuse: %pM\n", mac);
+	eth_setenv_enetaddr("ethaddr", mac);
 }
 
 int board_late_init(void)
@@ -1251,6 +1132,65 @@ exit:
 	return ret;
 }
 
+#ifdef CONFIG_NO_NAND
+#ifdef CONFIG_MMC_BOOT_SIZE
+#define TX6_FLASH_SZ	(CONFIG_MMC_BOOT_SIZE / 1024 - 1 + 2)
+#else
+#define TX6_FLASH_SZ	3
+#endif
+#else /* CONFIG_NO_NAND */
+#define TX6_FLASH_SZ	(CONFIG_SYS_NAND_BLOCKS / 1024 - 1)
+#endif /* CONFIG_NO_NAND */
+
+#ifdef CONFIG_SYS_SDRAM_BUS_WIDTH
+#define TX6_DDR_SZ	(ffs(CONFIG_SYS_SDRAM_BUS_WIDTH / 16) - 1)
+#else
+#define TX6_DDR_SZ	2
+#endif
+
+#if CONFIG_TX6_REV >= 0x3
+static char tx6_mem_table[] = {
+	'4', /* 256MiB SDRAM; 128MiB NAND */
+	'1', /* 512MiB SDRAM; 128MiB NAND */
+	'0', /* 1GiB SDRAM; 128MiB NAND */
+	'?', /* 256MiB SDRAM; 256MiB NAND */
+	'?', /* 512MiB SDRAM; 256MiB NAND */
+	'2', /* 1GiB SDRAM; 256MiB NAND */
+	'?', /* 256MiB SDRAM; 4GiB eMMC */
+	'5', /* 512MiB SDRAM; 4GiB eMMC */
+	'3', /* 1GiB SDRAM; 4GiB eMMC */
+	'?', /* 256MiB SDRAM; 8GiB eMMC */
+	'?', /* 512MiB SDRAM; 8GiB eMMC */
+	'?', /* 1GiB SDRAM; 8GiB eMMC */
+};
+
+static inline char tx6_mem_suffix(void)
+{
+	size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ;
+
+	debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n",
+		TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx);
+
+	if (mem_idx >= ARRAY_SIZE(tx6_mem_table))
+		return '?';
+
+	return tx6_mem_table[mem_idx];
+};
+#else /* CONFIG_TX6_REV >= 0x3 */
+static inline char tx6_mem_suffix(void)
+{
+#ifdef CONFIG_SYS_SDRAM_BUS_WIDTH
+	if (CONFIG_SYS_SDRAM_BUS_WIDTH == 32)
+		return '1';
+#endif
+#ifdef CONFIG_SYS_NAND_BLOCKS
+	if (CONFIG_SYS_NAND_BLOCKS == 2048)
+		return '2';
+#endif
+	return '0';
+}
+#endif /* CONFIG_TX6_REV >= 0x3 */
+
 int checkboard(void)
 {
 	u32 cpurev = get_cpu_rev();
@@ -1258,10 +1198,11 @@ int checkboard(void)
 
 	tx6qdl_print_cpuinfo();
 
-	printf("Board: Ka-Ro TX6%c-%d%d1%d\n",
-		cpu_variant == MXC_CPU_MX6Q ? 'Q' : 'U',
+	printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
+		tx6_mod_suffix,
 		cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
-		is_lvds(), 1 - PHYS_SDRAM_1_WIDTH / 64);
+		is_lvds(), CONFIG_TX6_REV,
+		tx6_mem_suffix());
 
 	return 0;
 }
@@ -1291,6 +1232,7 @@ static struct node_info nodes[] = {
 static const char *tx6_touchpanels[] = {
 	"ti,tsc2007",
 	"edt,edt-ft5x06",
+	"eeti,egalax_ts",
 };
 
 void ft_board_setup(void *blob, bd_t *bd)
@@ -1298,6 +1240,11 @@ void ft_board_setup(void *blob, bd_t *bd)
 	const char *baseboard = getenv("baseboard");
 	int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
 	const char *video_mode = karo_get_vmode(getenv("video_mode"));
+	int ret;
+
+	ret = fdt_increase_size(blob, 4096);
+	if (ret)
+		printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
 
 	if (stk5_v5)
 		karo_fdt_enable_node(blob, "stk5led", 0);
@@ -1307,7 +1254,7 @@ void ft_board_setup(void *blob, bd_t *bd)
 
 	karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
 				ARRAY_SIZE(tx6_touchpanels));
-	karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy");
+	karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
 	karo_fdt_fixup_flexcan(blob, stk5_v5);
 
 	karo_fdt_update_fb_mode(blob, video_mode);