X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=board%2Fkaro%2Ftx6%2Ftx6ul.c;h=193f690990264cfa7b099f0d72d76f29148c39dc;hp=062b1610bf3aba375f032f0eab1c03d17de801c7;hb=9c867060812647af60840df7caf78f6567b2bd29;hpb=960763f01ab2e4c83e5fcf51ecdb44740c60dd8c

diff --git a/board/karo/tx6/tx6ul.c b/board/karo/tx6/tx6ul.c
index 062b1610bf..193f690990 100644
--- a/board/karo/tx6/tx6ul.c
+++ b/board/karo/tx6/tx6ul.c
@@ -34,14 +34,20 @@
 #define TX6UL_FEC_RST_GPIO		IMX_GPIO_NR(5, 6)
 #define TX6UL_FEC_PWR_GPIO		IMX_GPIO_NR(5, 7)
 #define TX6UL_FEC_INT_GPIO		IMX_GPIO_NR(5, 5)
+
+#define TX6UL_FEC2_RST_GPIO		IMX_GPIO_NR(4, 28)
+#define TX6UL_FEC2_INT_GPIO		IMX_GPIO_NR(4, 27)
+
 #define TX6UL_LED_GPIO			IMX_GPIO_NR(5, 9)
 
 #define TX6UL_LCD_PWR_GPIO		IMX_GPIO_NR(5, 4)
 #define TX6UL_LCD_RST_GPIO		IMX_GPIO_NR(3, 4)
 #define TX6UL_LCD_BACKLIGHT_GPIO	IMX_GPIO_NR(4, 16)
 
+#ifdef CONFIG_SYS_I2C_SOFT
 #define TX6UL_I2C1_SCL_GPIO		CONFIG_SOFT_I2C_GPIO_SCL
 #define TX6UL_I2C1_SDA_GPIO		CONFIG_SOFT_I2C_GPIO_SDA
+#endif
 
 #define TX6UL_SD1_CD_GPIO		IMX_GPIO_NR(4, 14)
 
@@ -65,169 +71,208 @@ char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
 char __csf_data[0] __attribute__((section(".__csf_data")));
 #endif
 
+#define TX6UL_DEFAULT_PAD_CTRL	MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |	\
+					PAD_CTL_SPEED_MED |		\
+					PAD_CTL_DSE_40ohm |		\
+					PAD_CTL_SRE_FAST)
+#define TX6UL_I2C_PAD_CTRL	MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |	\
+					PAD_CTL_ODE |			\
+					PAD_CTL_HYS |			\
+					PAD_CTL_SPEED_LOW |		\
+					PAD_CTL_DSE_34ohm |		\
+					PAD_CTL_SRE_FAST)
+#define TX6UL_I2C_GPIO_PAD_CTRL	MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |	\
+					PAD_CTL_HYS |			\
+					PAD_CTL_DSE_34ohm |		\
+					PAD_CTL_SPEED_MED)
+#define TX6UL_ENET_PAD_CTRL	MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH |	\
+					PAD_CTL_DSE_48ohm |		\
+					PAD_CTL_PUS_100K_UP |		\
+					PAD_CTL_SRE_FAST)
+#define TX6UL_GPIO_OUT_PAD_CTRL	MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |	\
+					PAD_CTL_DSE_60ohm |		\
+					PAD_CTL_SRE_SLOW)
+#define TX6UL_GPIO_IN_PAD_CTRL	MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |	\
+					PAD_CTL_PUS_47K_UP)
+
+
 static const iomux_v3_cfg_t const tx6ul_pads[] = {
 	/* UART pads */
 #if CONFIG_MXC_UART_BASE == UART1_BASE
-	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX,
-	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX,
-	MX6_PAD_UART1_RTS_B__UART1_DCE_RTS,
-	MX6_PAD_UART1_CTS_B__UART1_DCE_CTS,
+	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
+	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
+	MX6_PAD_UART1_RTS_B__UART1_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
+	MX6_PAD_UART1_CTS_B__UART1_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
 #endif
 #if CONFIG_MXC_UART_BASE == UART2_BASE
-	MX6_PAD_UART2_TX_DATA__UART2_DCE_TX,
-	MX6_PAD_UART2_RX_DATA__UART2_DCE_RX,
-	MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS,
-	MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS,
+	MX6_PAD_UART2_TX_DATA__UART2_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
+	MX6_PAD_UART2_RX_DATA__UART2_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
+	MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
+	MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
 #endif
 #if CONFIG_MXC_UART_BASE == UART5_BASE
-	MX6_PAD_GPIO1_IO04__UART5_DCE_TX,
-	MX6_PAD_GPIO1_IO05__UART5_DCE_RX,
-	MX6_PAD_GPIO1_IO08__UART5_DCE_RTS,
-	MX6_PAD_GPIO1_IO09__UART5_DCE_CTS,
+	MX6_PAD_GPIO1_IO04__UART5_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
+	MX6_PAD_GPIO1_IO05__UART5_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
+	MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
+	MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
 #endif
-	/* internal I2C */
-	MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
-			MUX_PAD_CTRL(PAD_CTL_DSE_240ohm), /* I2C SCL */
-	MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
-			MUX_PAD_CTRL(PAD_CTL_DSE_240ohm | PAD_CTL_HYS |
-			PAD_CTL_ODE), /* I2C SDA */
-
 	/* FEC PHY GPIO functions */
-	MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_CFG_SION, /* PHY POWER */
-	MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 | MUX_CFG_SION, /* PHY RESET */
-	MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
-							PAD_CTL_DSE_40ohm), /* PHY INT */
+	MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | TX6UL_GPIO_OUT_PAD_CTRL, /* PHY POWER */
+	MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 | TX6UL_GPIO_OUT_PAD_CTRL, /* PHY RESET */
+	MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 | TX6UL_GPIO_IN_PAD_CTRL, /* PHY INT */
 };
 
-#define TX6_ENET_PAD_CTRL	(PAD_CTL_SPEED_HIGH |	\
-				PAD_CTL_DSE_48ohm |	\
-				PAD_CTL_PUS_100K_UP |	\
-				PAD_CTL_SRE_FAST)
-#define TX6_GPIO_OUT_PAD_CTRL	(PAD_CTL_SPEED_LOW |	\
-				PAD_CTL_DSE_60ohm |	\
-				PAD_CTL_SRE_SLOW)
-#define TX6_GPIO_IN_PAD_CTRL	(PAD_CTL_SPEED_LOW |	\
-				PAD_CTL_PUS_47K_UP)
-
 static const iomux_v3_cfg_t const tx6ul_enet1_pads[] = {
 	/* FEC functions */
 	MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(PAD_CTL_DSE_48ohm |
 				PAD_CTL_SPEED_MED),
 	MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |
-				PAD_CTL_DSE_48ohm |
-				PAD_CTL_SPEED_MED),
+				PAD_CTL_DSE_48ohm | PAD_CTL_SPEED_MED),
 	MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_CFG_SION |
 				MUX_PAD_CTRL(PAD_CTL_SPEED_MED |
-				PAD_CTL_DSE_40ohm |
-				PAD_CTL_SRE_FAST),
-	MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
-	MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
-	MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
-	MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
-	MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
-	MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
-	MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
+				PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST),
+	MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | TX6UL_ENET_PAD_CTRL,
+	MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | TX6UL_ENET_PAD_CTRL,
+	MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | TX6UL_ENET_PAD_CTRL,
+	MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | TX6UL_ENET_PAD_CTRL,
+	MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | TX6UL_ENET_PAD_CTRL,
+	MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | TX6UL_ENET_PAD_CTRL,
+	MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | TX6UL_ENET_PAD_CTRL,
+};
 
+static const iomux_v3_cfg_t const tx6ul_enet2_pads[] = {
 	MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_CFG_SION |
 				MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH |
-				PAD_CTL_DSE_48ohm |
-				PAD_CTL_SRE_FAST),
-	MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
-	MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
-	MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
-	MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
-	MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
-	MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
-	MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
+				PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST),
+	MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | TX6UL_ENET_PAD_CTRL,
+	MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | TX6UL_ENET_PAD_CTRL,
+	MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | TX6UL_ENET_PAD_CTRL,
+	MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | TX6UL_ENET_PAD_CTRL,
+	MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | TX6UL_ENET_PAD_CTRL,
+	MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | TX6UL_ENET_PAD_CTRL,
+	MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | TX6UL_ENET_PAD_CTRL,
 };
 
-#define TX6_I2C_PAD_CTRL	(PAD_CTL_PUS_22K_UP |	\
-				PAD_CTL_SPEED_MED |	\
-				PAD_CTL_DSE_34ohm |	\
-				PAD_CTL_SRE_FAST)
-
-static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
+static const iomux_v3_cfg_t const tx6ul_i2c_pads[] = {
 	/* internal I2C */
 	MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
-			MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
+			TX6UL_I2C_PAD_CTRL, /* I2C SCL */
+	MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
+			TX6UL_I2C_PAD_CTRL, /* I2C SDA */
+};
+
+static const iomux_v3_cfg_t const tx6ul_i2c_gpio_pads[] = {
+	/* internal I2C set up for I2C bus recovery */
+	MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
+			TX6UL_I2C_PAD_CTRL, /* I2C SCL */
 	MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
-			MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
+			TX6UL_I2C_PAD_CTRL, /* I2C SDA */
 };
 
 static const struct gpio const tx6ul_gpios[] = {
+#ifdef CONFIG_SYS_I2C_SOFT
 	/* These two entries are used to forcefully reinitialize the I2C bus */
 	{ TX6UL_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
 	{ TX6UL_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
-
+#endif
 	{ TX6UL_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 	{ TX6UL_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 	{ TX6UL_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
 };
 
+static const struct gpio const tx6ul_fec2_gpios[] = {
+	{ TX6UL_FEC2_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC2 PHY RESET", },
+	{ TX6UL_FEC2_INT_GPIO, GPIOFLAG_INPUT, "FEC2 PHY INT", },
+};
+
 #define GPIO_DR 0
 #define GPIO_DIR 4
 #define GPIO_PSR 8
 
 /* run with default environment */
-static void tx6_i2c_recover(void)
+#if defined(TX6UL_I2C1_SCL_GPIO) && defined(TX6UL_I2C1_SDA_GPIO)
+#define SCL_BANK	(TX6UL_I2C1_SCL_GPIO / 32)
+#define SDA_BANK	(TX6UL_I2C1_SDA_GPIO / 32)
+#define SCL_BIT		(1 << (TX6UL_I2C1_SCL_GPIO % 32))
+#define SDA_BIT		(1 << (TX6UL_I2C1_SDA_GPIO % 32))
+
+static void * const gpio_ports[] = {
+	(void *)GPIO1_BASE_ADDR,
+	(void *)GPIO2_BASE_ADDR,
+	(void *)GPIO3_BASE_ADDR,
+	(void *)GPIO4_BASE_ADDR,
+	(void *)GPIO5_BASE_ADDR,
+};
+
+static void tx6ul_i2c_recover(void)
 {
 	int i;
 	int bad = 0;
-#define SCL_BIT		(1 << (TX6UL_I2C1_SCL_GPIO % 32))
-#define SDA_BIT		(1 << (TX6UL_I2C1_SDA_GPIO % 32))
-#define I2C_GPIO_BASE	(GPIO1_BASE_ADDR + TX6UL_I2C1_SCL_GPIO / 32 * 0x4000)
+	struct gpio_regs *scl_regs = gpio_ports[SCL_BANK];
+	struct gpio_regs *sda_regs = gpio_ports[SDA_BANK];
 
-	if ((readl(I2C_GPIO_BASE + GPIO_PSR) &
-			(SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT))
+	if ((readl(&scl_regs->gpio_psr) & SCL_BIT) &&
+		(readl(&sda_regs->gpio_psr) & SDA_BIT))
 		return;
 
 	debug("Clearing I2C bus\n");
-	if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SCL_BIT)) {
+	if (!(readl(&scl_regs->gpio_psr) & SCL_BIT)) {
 		printf("I2C SCL stuck LOW\n");
 		bad++;
 
-		writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT,
-			I2C_GPIO_BASE + GPIO_DR);
-		writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT,
-			I2C_GPIO_BASE + GPIO_DIR);
+		setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
+		setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
+
+		imx_iomux_v3_setup_pad(MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 |
+				MUX_CFG_SION | TX6UL_GPIO_OUT_PAD_CTRL);
 	}
-	if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)) {
+	if (!(readl(&sda_regs->gpio_psr) & SDA_BIT)) {
 		printf("I2C SDA stuck LOW\n");
 		bad++;
 
-		writel(readl(I2C_GPIO_BASE + GPIO_DIR) & ~SDA_BIT,
-			I2C_GPIO_BASE + GPIO_DIR);
-		writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT,
-			I2C_GPIO_BASE + GPIO_DR);
-		writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT,
-			I2C_GPIO_BASE + GPIO_DIR);
+		clrbits_le32(&sda_regs->gpio_dir, SDA_BIT);
+		setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
+		setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
+
+		imx_iomux_v3_setup_multiple_pads(tx6ul_i2c_gpio_pads,
+						ARRAY_SIZE(tx6ul_i2c_gpio_pads));
 
-		imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
-						ARRAY_SIZE(tx6_i2c_gpio_pads));
-		udelay(10);
+		udelay(5);
 
 		for (i = 0; i < 18; i++) {
-			u32 reg = readl(I2C_GPIO_BASE + GPIO_DR) ^ SCL_BIT;
+			u32 reg = readl(&scl_regs->gpio_dr) ^ SCL_BIT;
 
 			debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
-			writel(reg, I2C_GPIO_BASE + GPIO_DR);
-			udelay(10);
-			if (reg & SCL_BIT &&
-				readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)
+			writel(reg, &scl_regs->gpio_dr);
+			udelay(5);
+			if (reg & SCL_BIT) {
+				if (readl(&sda_regs->gpio_psr) & SDA_BIT)
+					break;
+				if (!(readl(&scl_regs->gpio_psr) & SCL_BIT))
+					break;
 				break;
+			}
 		}
 	}
 	if (bad) {
-		u32 reg = readl(I2C_GPIO_BASE + GPIO_PSR);
+		bool scl = !!(readl(&scl_regs->gpio_psr) & SCL_BIT);
+		bool sda = !!(readl(&sda_regs->gpio_psr) & SDA_BIT);
 
-		if ((reg & (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) {
+		if (scl && sda) {
 			printf("I2C bus recovery succeeded\n");
 		} else {
-			printf("I2C bus recovery FAILED: %08x:%08x\n", reg,
-				SCL_BIT | SDA_BIT);
+			printf("I2C bus recovery FAILED: SCL: %d SDA: %d\n",
+				scl, sda);
 		}
+		imx_iomux_v3_setup_multiple_pads(tx6ul_i2c_pads,
+						ARRAY_SIZE(tx6ul_i2c_pads));
 	}
 }
+#else
+static inline void tx6ul_i2c_recover(void)
+{
+}
+#endif
 
 /* placed in section '.data' to prevent overwriting relocation info
  * overlayed with bss
@@ -346,23 +391,16 @@ int checkboard(void)
 	u32 cpurev = get_cpu_rev();
 	char *cpu_str = "?";
 
-	switch ((cpurev >> 12) & 0xff) {
-	case MXC_CPU_MX6SL:
+	if (is_cpu_type(MXC_CPU_MX6SL))
 		cpu_str = "SL";
-		break;
-	case MXC_CPU_MX6DL:
+	else if (is_cpu_type(MXC_CPU_MX6DL))
 		cpu_str = "DL";
-		break;
-	case MXC_CPU_MX6SOLO:
+	else if (is_cpu_type(MXC_CPU_MX6SOLO))
 		cpu_str = "SOLO";
-		break;
-	case MXC_CPU_MX6Q:
+	else if (is_cpu_type(MXC_CPU_MX6Q))
 		cpu_str = "Q";
-		break;
-	case MXC_CPU_MX6UL:
+	else if (is_cpu_type(MXC_CPU_MX6UL))
 		cpu_str = "UL";
-		break;
-	}
 
 	printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
 		cpu_str,
@@ -375,7 +413,7 @@ int checkboard(void)
 #ifdef CONFIG_MX6_TEMPERATURE_HOT
 	check_cpu_temperature(1);
 #endif
-	tx6_i2c_recover();
+	tx6ul_i2c_recover();
 	return 0;
 }
 
@@ -386,9 +424,9 @@ int board_early_init_f(void)
 }
 
 #ifndef CONFIG_MX6_TEMPERATURE_HOT
-static bool tx6_temp_check_enabled = true;
+static bool tx6ul_temp_check_enabled = true;
 #else
-#define tx6_temp_check_enabled	0
+#define tx6ul_temp_check_enabled	0
 #endif
 
 static inline u8 tx6ul_mem_suffix(void)
@@ -400,51 +438,71 @@ static inline u8 tx6ul_mem_suffix(void)
 #endif
 }
 
+#ifdef CONFIG_RN5T567
 /* PMIC settings */
 #define VDD_RTC_VAL		rn5t_mV_to_regval_rtc(3000)
 #define VDD_CORE_VAL		rn5t_mV_to_regval(1300)		/* DCDC1 */
 #define VDD_CORE_VAL_LP		rn5t_mV_to_regval(900)
 #define VDD_DDR_VAL		rn5t_mV_to_regval(1350)		/* DCDC3 */
 #define VDD_DDR_VAL_LP		rn5t_mV_to_regval(1350)
-#define VDD_HIGH_VAL		rn5t_mV_to_regval(3300)		/* DCDC4 */
-#define VDD_HIGH_VAL_LP		rn5t_mV_to_regval(3300)
-#define VDD_CSI_VAL		rn5t_mV_to_regval2(3300)	/* LDO4 */
-#define VDD_CSI_VAL_LP		rn5t_mV_to_regval2(3300)
+#define VDD_IO_EXT_VAL		rn5t_mV_to_regval(3300)		/* DCDC4 */
+#define VDD_IO_EXT_VAL_LP	rn5t_mV_to_regval(3300)
+#define VDD_IO_INT_VAL		rn5t_mV_to_regval2(3300)	/* LDO1 */
+#define VDD_IO_INT_VAL_LP	rn5t_mV_to_regval2(3300)
+#define VDD_ADC_VAL		rn5t_mV_to_regval2(3300)	/* LDO2 */
+#define VDD_ADC_VAL_LP		rn5t_mV_to_regval2(3300)
+#define VDD_PMIC_VAL		rn5t_mV_to_regval2(2500)	/* LDO3 */
+#define VDD_PMIC_VAL_LP		rn5t_mV_to_regval2(2500)
+#define VDD_CSI_VAL		rn5t_mV_to_regval2(1800)	/* LDO4 */
+#define VDD_CSI_VAL_LP		rn5t_mV_to_regval2(1800)
 
 static struct pmic_regs rn5t567_regs[] = {
 	{ RN5T567_NOETIMSET, NOETIMSET_DIS_OFF_NOE_TIM | 0x5, },
-	{ RN5T567_DC2CTL, DC2_DC2DIS, },
 	{ RN5T567_DC1DAC, VDD_CORE_VAL, },
 	{ RN5T567_DC3DAC, VDD_DDR_VAL, },
-	{ RN5T567_DC4DAC, VDD_HIGH_VAL, },
+	{ RN5T567_DC4DAC, VDD_IO_EXT_VAL, },
 	{ RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
 	{ RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
-	{ RN5T567_DC4DAC_SLP, VDD_HIGH_VAL_LP, },
-	{ RN5T567_LDOEN1, 0x01f, ~0x1f, },
-	{ RN5T567_LDOEN2, 0x10, ~0x30, },
-	{ RN5T567_LDODIS, 0x00, },
-	{ RN5T567_LDO4DAC, VDD_CSI_VAL, },
+	{ RN5T567_DC4DAC_SLP, VDD_IO_EXT_VAL_LP, },
+	{ RN5T567_DC1CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
+	{ RN5T567_DC2CTL, DCnCTL_DCnDIS, },
+	{ RN5T567_DC3CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
+	{ RN5T567_DC4CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
 	{ RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
 	{ RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
+	{ RN5T567_LDO1DAC, VDD_IO_INT_VAL, },
+	{ RN5T567_LDO2DAC, VDD_ADC_VAL, },
+	{ RN5T567_LDO3DAC, VDD_PMIC_VAL, },
+	{ RN5T567_LDO4DAC, VDD_CSI_VAL, },
+	{ RN5T567_LDOEN1, 0x0f, ~0x1f, },
+	{ RN5T567_LDOEN2, 0x10, ~0x30, },
+	{ RN5T567_LDODIS, 0x10, ~0x1f, },
+	{ RN5T567_INTPOL, 0, },
+	{ RN5T567_INTEN, 0x3, },
+	{ RN5T567_IREN, 0xf, },
+	{ RN5T567_EN_GPIR, 0, },
 };
 
-static int pmic_addr __maybe_unused = 0x33;
+static int pmic_addr = 0x33;
+#endif
 
 int board_init(void)
 {
 	int ret;
+	u32 cpurev = get_cpu_rev();
 
 	debug("%s@%d: \n", __func__, __LINE__);
 
-	printf("Board: Ka-Ro TXUL-001%c\n",
+	printf("Board: Ka-Ro TXUL-%c01%c\n",
+		((cpurev &0xff) > 0x10) ? '5' : '0',
 		tx6ul_mem_suffix());
 
 	get_hab_status();
 
 	ret = gpio_request_array(tx6ul_gpios, ARRAY_SIZE(tx6ul_gpios));
-	if (ret < 0) {
+	if (ret < 0)
 		printf("Failed to request tx6ul_gpios: %d\n", ret);
-	}
+
 	imx_iomux_v3_setup_multiple_pads(tx6ul_pads, ARRAY_SIZE(tx6ul_pads));
 
 	/* Address of boot parameters */
@@ -457,7 +515,7 @@ int board_init(void)
 		else
 			printf("<CTRL-C> detected; safeboot enabled\n");
 #ifndef CONFIG_MX6_TEMPERATURE_HOT
-		tx6_temp_check_enabled = false;
+		tx6ul_temp_check_enabled = false;
 #endif
 		return 0;
 	}
@@ -495,37 +553,37 @@ void dram_init_banksize(void)
 }
 
 #ifdef	CONFIG_FSL_ESDHC
-#define TX6_SD_PAD_CTRL		(PAD_CTL_PUS_47K_UP |	\
-				PAD_CTL_SPEED_MED |	\
-				PAD_CTL_DSE_40ohm |	\
-				PAD_CTL_SRE_FAST)
+#define TX6UL_SD_PAD_CTRL	MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |	\
+					PAD_CTL_SPEED_MED |		\
+					PAD_CTL_DSE_40ohm |		\
+					PAD_CTL_SRE_FAST)
 
 static const iomux_v3_cfg_t mmc0_pads[] = {
-	MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
-	MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
-	MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
-	MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
-	MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
-	MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
+	MX6_PAD_SD1_CMD__USDHC1_CMD | TX6UL_SD_PAD_CTRL,
+	MX6_PAD_SD1_CLK__USDHC1_CLK | TX6UL_SD_PAD_CTRL,
+	MX6_PAD_SD1_DATA0__USDHC1_DATA0 | TX6UL_SD_PAD_CTRL,
+	MX6_PAD_SD1_DATA1__USDHC1_DATA1 | TX6UL_SD_PAD_CTRL,
+	MX6_PAD_SD1_DATA2__USDHC1_DATA2 | TX6UL_SD_PAD_CTRL,
+	MX6_PAD_SD1_DATA3__USDHC1_DATA3 | TX6UL_SD_PAD_CTRL,
 	/* SD1 CD */
-	MX6_PAD_NAND_CE1_B__GPIO4_IO14 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
+	MX6_PAD_NAND_CE1_B__GPIO4_IO14 | TX6UL_SD_PAD_CTRL,
 };
 
 #ifdef CONFIG_TX6_EMMC
 static const iomux_v3_cfg_t mmc1_pads[] = {
-	MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
-	MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
-	MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
-	MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
-	MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
-	MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
+	MX6_PAD_NAND_WE_B__USDHC2_CMD | TX6UL_SD_PAD_CTRL,
+	MX6_PAD_NAND_RE_B__USDHC2_CLK | TX6UL_SD_PAD_CTRL,
+	MX6_PAD_NAND_DATA00__USDHC2_DATA0 | TX6UL_SD_PAD_CTRL,
+	MX6_PAD_NAND_DATA01__USDHC2_DATA1 | TX6UL_SD_PAD_CTRL,
+	MX6_PAD_NAND_DATA02__USDHC2_DATA2 | TX6UL_SD_PAD_CTRL,
+	MX6_PAD_NAND_DATA03__USDHC2_DATA3 | TX6UL_SD_PAD_CTRL,
 	/* eMMC RESET */
 	MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
 						PAD_CTL_DSE_40ohm),
 };
 #endif
 
-static struct tx6_esdhc_cfg {
+static struct tx6ul_esdhc_cfg {
 	const iomux_v3_cfg_t *pads;
 	int num_pads;
 	enum mxc_clock clkid;
@@ -556,14 +614,14 @@ static struct tx6_esdhc_cfg {
 	},
 };
 
-static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
+static inline struct tx6ul_esdhc_cfg *to_tx6ul_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 {
-	return container_of(cfg, struct tx6_esdhc_cfg, cfg);
+	return container_of(cfg, struct tx6ul_esdhc_cfg, cfg);
 }
 
 int board_mmc_getcd(struct mmc *mmc)
 {
-	struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
+	struct tx6ul_esdhc_cfg *cfg = to_tx6ul_esdhc_cfg(mmc->priv);
 
 	if (cfg->cd_gpio < 0)
 		return 1;
@@ -581,9 +639,15 @@ int board_mmc_init(bd_t *bis)
 
 	debug("%s@%d: \n", __func__, __LINE__);
 
+#ifndef CONFIG_ENV_IS_IN_MMC
+	if (!(gd->flags & GD_FLG_ENV_READY)) {
+		printf("deferred ...");
+		return 0;
+	}
+#endif
 	for (i = 0; i < ARRAY_SIZE(tx6ul_esdhc_cfg); i++) {
 		struct mmc *mmc;
-		struct tx6_esdhc_cfg *cfg = &tx6ul_esdhc_cfg[i];
+		struct tx6ul_esdhc_cfg *cfg = &tx6ul_esdhc_cfg[i];
 		int ret;
 
 		cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
@@ -610,67 +674,7 @@ int board_mmc_init(bd_t *bis)
 	}
 	return 0;
 }
-#endif /* CONFIG_CMD_MMC */
-
-#ifdef CONFIG_FEC_MXC
-
-#ifndef ETH_ALEN
-#define ETH_ALEN 6
-#endif
-
-int board_eth_init(bd_t *bis)
-{
-	int ret;
-
-	debug("%s@%d: \n", __func__, __LINE__);
-
-	/* delay at least 21ms for the PHY internal POR signal to deassert */
-	udelay(22000);
-
-	imx_iomux_v3_setup_multiple_pads(tx6ul_enet1_pads,
-					ARRAY_SIZE(tx6ul_enet1_pads));
-
-	/* Deassert RESET to the external phy */
-	gpio_set_value(TX6UL_FEC_RST_GPIO, 1);
-
-	if (getenv("ethaddr")) {
-		ret = fecmxc_initialize_multi(bis, 0, -1, ENET_BASE_ADDR);
-		if (ret) {
-			printf("failed to initialize FEC0: %d\n", ret);
-			return ret;
-		}
-	}
-	if (getenv("eth1addr")) {
-		ret = fecmxc_initialize_multi(bis, 1, -1, ENET2_BASE_ADDR);
-		if (ret) {
-			printf("failed to initialize FEC1: %d\n", ret);
-			return ret;
-		}
-	}
-	return 0;
-}
-
-static void tx6_init_mac(void)
-{
-	u8 mac[ETH_ALEN];
-
-	imx_get_mac_from_fuse(0, mac);
-	if (!is_valid_ethaddr(mac)) {
-		printf("No valid MAC address programmed\n");
-		return;
-	}
-
-	printf("MAC addr from fuse: %pM\n", mac);
-	eth_setenv_enetaddr("ethaddr", mac);
-
-	imx_get_mac_from_fuse(1, mac);
-	eth_setenv_enetaddr("eth1addr", mac);
-}
-#else
-static inline void tx6_init_mac(void)
-{
-}
-#endif /* CONFIG_FEC_MXC */
+#endif /* CONFIG_FSL_ESDHC */
 
 enum {
 	LED_STATE_INIT = -1,
@@ -681,7 +685,7 @@ enum {
 
 static inline int calc_blink_rate(void)
 {
-	if (!tx6_temp_check_enabled)
+	if (!tx6ul_temp_check_enabled)
 		return CONFIG_SYS_HZ;
 
 	return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
@@ -726,54 +730,57 @@ void show_activity(int arg)
 	}
 }
 
+static const iomux_v3_cfg_t stk5_jtag_pads[] = {
+	MX6_PAD_JTAG_MOD__SJC_MOD | TX6UL_GPIO_IN_PAD_CTRL,
+	MX6_PAD_JTAG_TCK__SJC_TCK | TX6UL_GPIO_IN_PAD_CTRL,
+	MX6_PAD_JTAG_TRST_B__SJC_TRSTB | TX6UL_GPIO_IN_PAD_CTRL,
+	MX6_PAD_JTAG_TDI__SJC_TDI | TX6UL_GPIO_IN_PAD_CTRL,
+	MX6_PAD_JTAG_TDO__SJC_TDO | TX6UL_GPIO_OUT_PAD_CTRL,
+	MX6_PAD_JTAG_TMS__SJC_TMS | TX6UL_GPIO_IN_PAD_CTRL,
+};
+
 static const iomux_v3_cfg_t stk5_pads[] = {
 	/* SW controlled LED on STK5 baseboard */
 	MX6_PAD_SNVS_TAMPER9__GPIO5_IO09,
 
 	/* I2C bus on DIMM pins 40/41 */
-	MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
-	MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
+	MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
+	MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
 
 	/* TSC200x PEN IRQ */
-	MX6_PAD_JTAG_TMS__GPIO1_IO11 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL),
-#if 0
+	MX6_PAD_JTAG_TMS__GPIO1_IO11 | TX6UL_GPIO_IN_PAD_CTRL,
+
 	/* EDT-FT5x06 Polytouch panel */
-	MX6_PAD_NAND_CS2__GPIO6_IO15 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* IRQ */
-	MX6_PAD_EIM_A16__GPIO2_IO22 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* RESET */
-	MX6_PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* WAKE */
+	MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | TX6UL_GPIO_IN_PAD_CTRL, /* IRQ */
+	MX6_PAD_SNVS_TAMPER3__GPIO5_IO03 | TX6UL_GPIO_OUT_PAD_CTRL, /* RESET */
+	MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | TX6UL_GPIO_OUT_PAD_CTRL, /* WAKE */
 
 	/* USBH1 */
-	MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */
-	MX6_PAD_EIM_D30__GPIO3_IO30 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */
+	MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
+	MX6_PAD_GPIO1_IO03__USB_OTG2_OC | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
+
 	/* USBOTG */
-	MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* USBOTG ID */
-	MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */
-	MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */
-#endif
+	MX6_PAD_UART3_CTS_B__GPIO1_IO26 | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
+	MX6_PAD_UART3_RTS_B__GPIO1_IO27 | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
 };
 
 static const struct gpio stk5_gpios[] = {
 	{ TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 
-	{ IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", },
-	{ IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
-	{ IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
-	{ IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
-	{ IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
+	{ IMX_GPIO_NR(1, 27), GPIOFLAG_INPUT, "USBOTG OC", },
+	{ IMX_GPIO_NR(1, 26), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 };
 
 #ifdef CONFIG_LCD
-static u16 tx6_cmap[256];
 vidinfo_t panel_info = {
 	/* set to max. size supported by SoC */
 	.vl_col = 4096,
 	.vl_row = 1024,
 
 	.vl_bpix = LCD_COLOR32,	   /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
-	.cmap = tx6_cmap,
 };
 
-static struct fb_videomode tx6_fb_modes[] = {
+static struct fb_videomode tx6ul_fb_modes[] = {
 #ifndef CONFIG_SYS_LVDS_IF
 	{
 		/* Standard VGA timing */
@@ -952,11 +959,11 @@ static int lcd_backlight_polarity(void)
 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 #ifdef CONFIG_LCD
 	/* LCD RESET */
-	MX6_PAD_LCD_RESET__GPIO3_IO04 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL),
+	MX6_PAD_LCD_RESET__GPIO3_IO04 | TX6UL_GPIO_OUT_PAD_CTRL,
 	/* LCD POWER_ENABLE */
-	MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL),
+	MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | TX6UL_GPIO_OUT_PAD_CTRL,
 	/* LCD Backlight (PWM) */
-	MX6_PAD_NAND_DQS__GPIO4_IO16 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL),
+	MX6_PAD_NAND_DQS__GPIO4_IO16 | TX6UL_GPIO_OUT_PAD_CTRL,
 	/* Display */
 	MX6_PAD_LCD_DATA00__LCDIF_DATA00,
 	MX6_PAD_LCD_DATA01__LCDIF_DATA01,
@@ -1034,7 +1041,7 @@ void lcd_ctrl_init(void *lcdbase)
 	const char *vm;
 	unsigned long val;
 	int refresh = 60;
-	struct fb_videomode *p = &tx6_fb_modes[0];
+	struct fb_videomode *p = &tx6ul_fb_modes[0];
 	struct fb_videomode fb_mode;
 	int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
 
@@ -1146,7 +1153,7 @@ void lcd_ctrl_init(void *lcdbase)
 		printf("Invalid video mode: %s\n", getenv("video_mode"));
 		lcd_enabled = 0;
 		printf("Supported video modes are:");
-		for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
+		for (p = &tx6ul_fb_modes[0]; p->name != NULL; p++) {
 			printf(" %s", p->name);
 		}
 		printf("\n");
@@ -1220,6 +1227,20 @@ void lcd_ctrl_init(void *lcdbase)
 #define lcd_enabled 0
 #endif /* CONFIG_LCD */
 
+#ifndef CONFIG_ENV_IS_IN_MMC
+static void tx6ul_mmc_init(void)
+{
+	puts("MMC:   ");
+	if (board_mmc_init(gd->bd) < 0)
+		cpu_mmc_init(gd->bd);
+	print_mmc_devices(',');
+}
+#else
+static inline void tx6ul_mmc_init(void)
+{
+}
+#endif
+
 static void stk5_board_init(void)
 {
 	int ret;
@@ -1230,6 +1251,10 @@ static void stk5_board_init(void)
 		return;
 	}
 	imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
+	if (getenv_yesno("jtag_enable") != 0) {
+		/* true if unset or set to one of: 'yYtT1' */
+		imx_iomux_v3_setup_multiple_pads(stk5_jtag_pads, ARRAY_SIZE(stk5_jtag_pads));
+	}
 	debug("%s@%d: \n", __func__, __LINE__);
 }
 
@@ -1238,6 +1263,7 @@ static void stk5v3_board_init(void)
 	debug("%s@%d: \n", __func__, __LINE__);
 	stk5_board_init();
 	debug("%s@%d: \n", __func__, __LINE__);
+	tx6ul_mmc_init();
 }
 
 static void stk5v5_board_init(void)
@@ -1245,6 +1271,7 @@ static void stk5v5_board_init(void)
 	int ret;
 
 	stk5_board_init();
+	tx6ul_mmc_init();
 
 	ret = gpio_request_one(IMX_GPIO_NR(3, 5), GPIOFLAG_OUTPUT_INIT_HIGH,
 			"Flexcan Transceiver");
@@ -1254,7 +1281,7 @@ static void stk5v5_board_init(void)
 	}
 
 	imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA00__GPIO3_IO05 |
-			MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL));
+			TX6UL_GPIO_OUT_PAD_CTRL);
 }
 
 static void tx6ul_set_cpu_clock(void)
@@ -1286,7 +1313,7 @@ int board_late_init(void)
 
 	env_cleanup();
 
-	if (tx6_temp_check_enabled)
+	if (tx6ul_temp_check_enabled)
 		check_cpu_temperature(1);
 
 	tx6ul_set_cpu_clock();
@@ -1321,6 +1348,15 @@ int board_late_init(void)
 			printf("WARNING: Unsupported STK5 board rev.: %s\n",
 				baseboard + 4);
 		}
+	} else if (strncmp(baseboard, "ulmb-", 5) == 0) {
+			const char *otg_mode = getenv("otg_mode");
+
+			if (otg_mode && strcmp(otg_mode, "host") == 0) {
+				printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
+					otg_mode, baseboard);
+				setenv("otg_mode", "none");
+			}
+			stk5_board_init();
 	} else {
 		printf("WARNING: Unsupported baseboard: '%s'\n",
 			baseboard);
@@ -1330,13 +1366,90 @@ int board_late_init(void)
 
 exit:
 	debug("%s@%d: \n", __func__, __LINE__);
-	tx6_init_mac();
-	debug("%s@%d: \n", __func__, __LINE__);
 
 	clear_ctrlc();
 	return 0;
 }
 
+#ifdef CONFIG_FEC_MXC
+
+#ifndef ETH_ALEN
+#define ETH_ALEN 6
+#endif
+
+static void tx6ul_init_mac(void)
+{
+	u8 mac[ETH_ALEN];
+	const char *baseboard = getenv("baseboard");
+
+	imx_get_mac_from_fuse(0, mac);
+	if (!is_valid_ethaddr(mac)) {
+		printf("No valid MAC address programmed\n");
+		return;
+	}
+	printf("MAC addr from fuse: %pM\n", mac);
+	if (!getenv("ethaddr"))
+		eth_setenv_enetaddr("ethaddr", mac);
+
+	if (!baseboard || strncmp(baseboard, "stk5", 4) == 0) {
+		setenv("eth1addr", NULL);
+		return;
+	}
+	if (getenv("eth1addr"))
+		return;
+	imx_get_mac_from_fuse(1, mac);
+	eth_setenv_enetaddr("eth1addr", mac);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int ret;
+
+	tx6ul_init_mac();
+
+	/* delay at least 21ms for the PHY internal POR signal to deassert */
+	udelay(22000);
+
+	imx_iomux_v3_setup_multiple_pads(tx6ul_enet1_pads,
+					ARRAY_SIZE(tx6ul_enet1_pads));
+
+	/* Deassert RESET to the external phys */
+	gpio_set_value(TX6UL_FEC_RST_GPIO, 1);
+
+	if (getenv("ethaddr")) {
+		ret = fecmxc_initialize_multi(bis, 0, 0, ENET_BASE_ADDR);
+		if (ret) {
+			printf("failed to initialize FEC0: %d\n", ret);
+			return ret;
+		}
+	}
+	if (getenv("eth1addr")) {
+		ret = gpio_request_array(tx6ul_fec2_gpios,
+					ARRAY_SIZE(tx6ul_fec2_gpios));
+		if (ret < 0) {
+			printf("Failed to request tx6ul_fec2_gpios: %d\n", ret);
+		}
+		imx_iomux_v3_setup_multiple_pads(tx6ul_enet2_pads,
+						ARRAY_SIZE(tx6ul_enet2_pads));
+
+		writel(0x00100000, 0x020c80e4); /* assert ENET2_125M_EN */
+
+		/* Minimum PHY reset duration */
+		udelay(100);
+		gpio_set_value(TX6UL_FEC2_RST_GPIO, 1);
+		/* Wait for PHY internal POR to finish */
+		udelay(22000);
+
+		ret = fecmxc_initialize_multi(bis, 1, 2, ENET2_BASE_ADDR);
+		if (ret) {
+			printf("failed to initialize FEC1: %d\n", ret);
+			return ret;
+		}
+	}
+	return 0;
+}
+#endif /* CONFIG_FEC_MXC */
+
 #ifdef CONFIG_SERIAL_TAG
 void get_board_serial(struct tag_serialnr *serialnr)
 {
@@ -1359,7 +1472,7 @@ static struct node_info nodes[] = {
 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
 #endif
 
-static const char *tx6_touchpanels[] = {
+static const char *tx6ul_touchpanels[] = {
 	"ti,tsc2007",
 	"edt,edt-ft5x06",
 	"eeti,egalax_ts",
@@ -1382,8 +1495,8 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
 
-	karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
-				ARRAY_SIZE(tx6_touchpanels));
+	karo_fdt_fixup_touchpanel(blob, tx6ul_touchpanels,
+				ARRAY_SIZE(tx6ul_touchpanels));
 	karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
 	karo_fdt_fixup_flexcan(blob, stk5_v5);