X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=board%2Fzeus%2Fzeus.c;h=e2951512f88f8677e8c3cba5d1e093cb92b130b0;hp=974bdf29c15a067af255db1299d5ac4e4983701a;hb=54841ab50c20d6fa6c9cc3eb826989da3a22d934;hpb=f61f1e150c84f5b9347fca79a4bc5f2286c545d2

diff --git a/board/zeus/zeus.c b/board/zeus/zeus.c
index 974bdf29c1..e2951512f8 100644
--- a/board/zeus/zeus.c
+++ b/board/zeus/zeus.c
@@ -44,24 +44,24 @@ extern uchar default_environment[];
 
 ulong flash_get_size(ulong base, int banknum);
 void env_crc_update(void);
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
 
 static u32 start_time;
 
 int board_early_init_f(void)
 {
-	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr(uicer, 0x00000000);	/* disable all ints */
-	mtdcr(uiccr, 0x00000000);
-	mtdcr(uicpr, 0xFFFF7F00);	/* set int polarities */
-	mtdcr(uictr, 0x00000000);	/* set int trigger levels */
-	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr(uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);
+	mtdcr(UIC0PR, 0xFFFF7F00);	/* set int polarities */
+	mtdcr(UIC0TR, 0x00000000);	/* set int trigger levels */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
 
 	/*
 	 * Configure CPC0_PCI to enable PerWE as output
 	 */
-	mtdcr(cpc0_pci, CPC0_PCI_SPE);
+	mtdcr(CPC0_PCI, CPC0_PCI_SPE);
 
 	return 0;
 }
@@ -107,7 +107,7 @@ int misc_init_r(void)
 	/* Re-do sizing to get full correct info */
 
 	/* adjust flash start and offset */
-	mfebc(pb0cr, pbcr);
+	mfebc(PB0CR, pbcr);
 	switch (gd->bd->bi_flashsize) {
 	case 1 << 20:
 		size_val = 0;
@@ -135,7 +135,7 @@ int misc_init_r(void)
 		break;
 	}
 	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
-	mtebc(pb0cr, pbcr);
+	mtebc(PB0CR, pbcr);
 
 	/*
 	 * Re-check to get correct base address
@@ -278,7 +278,7 @@ static int restore_default(void)
 	return 0;
 }
 
-int do_set_default(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int do_set_default(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	char *buf;
 	char *buf_save;
@@ -327,8 +327,8 @@ int do_set_default(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 U_BOOT_CMD(
 	setdef,	4,	1,	do_set_default,
-	"setdef  - write board-specific values to EEPROM (ethaddr...)\n",
-	"ethaddr eth1addr serial#\n    - write board-specific values to EEPROM\n"
+	"write board-specific values to EEPROM (ethaddr...)",
+	"ethaddr eth1addr serial#\n    - write board-specific values to EEPROM"
 	);
 
 static inline int sw_reset_pressed(void)
@@ -336,7 +336,7 @@ static inline int sw_reset_pressed(void)
 	return !(in_be32((void *)GPIO0_IR) & GPIO_VAL(CONFIG_SYS_GPIO_SW_RESET));
 }
 
-int do_chkreset(cmd_tbl_t* cmdtp, int flag, int argc, char* argv[])
+int do_chkreset(cmd_tbl_t* cmdtp, int flag, int argc, char * const argv[])
 {
 	int delta;
 	int count = 0;
@@ -418,8 +418,8 @@ int do_chkreset(cmd_tbl_t* cmdtp, int flag, int argc, char* argv[])
 
 U_BOOT_CMD (
 	chkreset, 1, 1, do_chkreset,
-	"chkreset- Check for status of SW-reset button and act accordingly\n",
-	NULL
+	"Check for status of SW-reset button and act accordingly",
+	""
 );
 
 #if defined(CONFIG_POST)