X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=drivers%2Fddr%2Faltera%2Fsequencer.c;h=2bd01092eedc1476fe2c171e4083aaae6f7f07ed;hp=4596f552b3519e33e0311d8ad3c5c99776fe4094;hb=c726808d43c2f57748763b53d0d9f435065882cf;hpb=2c61b08914bbec15ac82e29b3a2cd4768300ff07 diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c index 4596f552b3..2bd01092ee 100644 --- a/drivers/ddr/altera/sequencer.c +++ b/drivers/ddr/altera/sequencer.c @@ -10,39 +10,30 @@ #include #include "sequencer.h" -/* - * FIXME: This path is temporary until the SDRAM driver gets - * a proper thorough cleanup. - */ -#include "../../../board/altera/socfpga/qts/sequencer_auto.h" -#include "../../../board/altera/socfpga/qts/sequencer_defines.h" - static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs = - (struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800); - + (struct socfpga_sdr_rw_load_manager *) + (SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800); static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs = - (struct socfpga_sdr_rw_load_jump_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00); - + (struct socfpga_sdr_rw_load_jump_manager *) + (SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00); static struct socfpga_sdr_reg_file *sdr_reg_file = (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS; - static struct socfpga_sdr_scc_mgr *sdr_scc_mgr = - (struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00); - + (struct socfpga_sdr_scc_mgr *) + (SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00); static struct socfpga_phy_mgr_cmd *phy_mgr_cmd = (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS; - static struct socfpga_phy_mgr_cfg *phy_mgr_cfg = - (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40); - + (struct socfpga_phy_mgr_cfg *) + (SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40); static struct socfpga_data_mgr *data_mgr = (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS; - static struct socfpga_sdr_ctrl *sdr_ctrl = (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS; const struct socfpga_sdram_rw_mgr_config *rwcfg; const struct socfpga_sdram_io_config *iocfg; +const struct socfpga_sdram_misc_config *misccfg; #define DELTA_D 1 @@ -66,7 +57,7 @@ const struct socfpga_sdram_io_config *iocfg; STATIC_SKIP_DELAY_LOOPS) /* calibration steps requested by the rtl */ -uint16_t dyn_calib_steps; +u16 dyn_calib_steps; /* * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option @@ -77,7 +68,7 @@ uint16_t dyn_calib_steps; * zero when skipping */ -uint16_t skip_delay_mask; /* mask off bits when skipping/not-skipping */ +u16 skip_delay_mask; /* mask off bits when skipping/not-skipping */ #define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \ ((non_skip_value) & skip_delay_mask) @@ -85,8 +76,8 @@ uint16_t skip_delay_mask; /* mask off bits when skipping/not-skipping */ struct gbl_type *gbl; struct param_type *param; -static void set_failing_group_stage(uint32_t group, uint32_t stage, - uint32_t substage) +static void set_failing_group_stage(u32 group, u32 stage, + u32 substage) { /* * Only set the global stage if there was not been any other @@ -292,49 +283,49 @@ static void scc_mgr_initialize(void) } } -static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t phase) +static void scc_mgr_set_dqdqs_output_phase(u32 write_group, u32 phase) { scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase); } -static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group, uint32_t delay) +static void scc_mgr_set_dqs_bus_in_delay(u32 read_group, u32 delay) { scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay); } -static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase) +static void scc_mgr_set_dqs_en_phase(u32 read_group, u32 phase) { scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase); } -static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay) +static void scc_mgr_set_dqs_en_delay(u32 read_group, u32 delay) { scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay); } -static void scc_mgr_set_dqs_io_in_delay(uint32_t delay) +static void scc_mgr_set_dqs_io_in_delay(u32 delay) { scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs, delay); } -static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group, uint32_t delay) +static void scc_mgr_set_dq_in_delay(u32 dq_in_group, u32 delay) { scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay); } -static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay) +static void scc_mgr_set_dq_out1_delay(u32 dq_in_group, u32 delay) { scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay); } -static void scc_mgr_set_dqs_out1_delay(uint32_t delay) +static void scc_mgr_set_dqs_out1_delay(u32 delay) { scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs, delay); } -static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay) +static void scc_mgr_set_dm_out1_delay(u32 dm, u32 delay) { scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs + 1 + dm, @@ -342,7 +333,7 @@ static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay) } /* load up dqs config settings */ -static void scc_mgr_load_dqs(uint32_t dqs) +static void scc_mgr_load_dqs(u32 dqs) { writel(dqs, &sdr_scc_mgr->dqs_ena); } @@ -354,13 +345,13 @@ static void scc_mgr_load_dqs_io(void) } /* load up dq config settings */ -static void scc_mgr_load_dq(uint32_t dq_in_group) +static void scc_mgr_load_dq(u32 dq_in_group) { writel(dq_in_group, &sdr_scc_mgr->dq_ena); } /* load up dm config settings */ -static void scc_mgr_load_dm(uint32_t dm) +static void scc_mgr_load_dm(u32 dm) { writel(dm, &sdr_scc_mgr->dm_ena); } @@ -405,8 +396,8 @@ static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase) read_group, phase, 0); } -static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group, - uint32_t phase) +static void scc_mgr_set_dqdqs_output_phase_all_ranks(u32 write_group, + u32 phase) { /* * USER although the h/w doesn't support different phases per @@ -420,8 +411,8 @@ static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group, write_group, phase, 0); } -static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group, - uint32_t delay) +static void scc_mgr_set_dqs_en_delay_all_ranks(u32 read_group, + u32 delay) { /* * In shadow register mode, the T11 settings are stored in @@ -621,9 +612,9 @@ static void scc_mgr_zero_group(const u32 write_group, const int out_only) * apply and load a particular input delay for the DQ pins in a group * group_bgn is the index of the first dq pin (in the write group) */ -static void scc_mgr_apply_group_dq_in_delay(uint32_t group_bgn, uint32_t delay) +static void scc_mgr_apply_group_dq_in_delay(u32 group_bgn, u32 delay) { - uint32_t i, p; + u32 i, p; for (i = 0, p = group_bgn; i < rwcfg->mem_dq_per_read_dqs; i++, p++) { scc_mgr_set_dq_in_delay(p, delay); @@ -648,9 +639,9 @@ static void scc_mgr_apply_group_dq_out1_delay(const u32 delay) } /* apply and load a particular output delay for the DM pins in a group */ -static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1) +static void scc_mgr_apply_group_dm_out1_delay(u32 delay1) { - uint32_t i; + u32 i; for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) { scc_mgr_set_dm_out1_delay(i, delay1); @@ -660,8 +651,8 @@ static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1) /* apply and load delay on both DQS and OCT out1 */ -static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group, - uint32_t delay) +static void scc_mgr_apply_group_dqs_io_and_oct_out1(u32 write_group, + u32 delay) { scc_mgr_set_dqs_out1_delay(delay); scc_mgr_load_dqs_io(); @@ -772,7 +763,7 @@ static void delay_for_n_mem_clocks(const u32 clocks) debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks); /* Scale (rounding up) to get afi clocks. */ - afi_clocks = DIV_ROUND_UP(clocks, AFI_RATE_RATIO); + afi_clocks = DIV_ROUND_UP(clocks, misccfg->afi_rate_ratio); if (afi_clocks) /* Temporary underflow protection */ afi_clocks--; @@ -806,30 +797,30 @@ static void delay_for_n_mem_clocks(const u32 clocks) */ if (afi_clocks < 0x100) { writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner), - &sdr_rw_load_mgr_regs->load_cntr1); + &sdr_rw_load_mgr_regs->load_cntr1); writel(rwcfg->idle_loop1, - &sdr_rw_load_jump_mgr_regs->load_jump_add1); + &sdr_rw_load_jump_mgr_regs->load_jump_add1); writel(rwcfg->idle_loop1, SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET); } else { writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner), - &sdr_rw_load_mgr_regs->load_cntr0); + &sdr_rw_load_mgr_regs->load_cntr0); writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer), - &sdr_rw_load_mgr_regs->load_cntr1); + &sdr_rw_load_mgr_regs->load_cntr1); writel(rwcfg->idle_loop2, - &sdr_rw_load_jump_mgr_regs->load_jump_add0); + &sdr_rw_load_jump_mgr_regs->load_jump_add0); writel(rwcfg->idle_loop2, - &sdr_rw_load_jump_mgr_regs->load_jump_add1); + &sdr_rw_load_jump_mgr_regs->load_jump_add1); do { writel(rwcfg->idle_loop2, - SDR_PHYGRP_RWMGRGRP_ADDRESS | - RW_MGR_RUN_SINGLE_GROUP_OFFSET); + SDR_PHYGRP_RWMGRGRP_ADDRESS | + RW_MGR_RUN_SINGLE_GROUP_OFFSET); } while (c_loop-- != 0); } debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks); @@ -846,7 +837,7 @@ static void delay_for_n_mem_clocks(const u32 clocks) */ static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump) { - uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS | + u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET; /* Load counters */ @@ -965,8 +956,9 @@ static void rw_mgr_mem_initialize(void) * One possible solution is n = 0 , a = 256 , b = 106 => a = FF, * b = 6A */ - rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL, SEQ_TINIT_CNTR1_VAL, - SEQ_TINIT_CNTR2_VAL, + rw_mgr_mem_init_load_regs(misccfg->tinit_cntr0_val, + misccfg->tinit_cntr1_val, + misccfg->tinit_cntr2_val, rwcfg->init_reset_0_cke_0); /* Indicate that memory is stable. */ @@ -986,8 +978,9 @@ static void rw_mgr_mem_initialize(void) * One possible solution is n = 2 , a = 131 , b = 256 => a = 83, * b = FF */ - rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL, SEQ_TRESET_CNTR1_VAL, - SEQ_TRESET_CNTR2_VAL, + rw_mgr_mem_init_load_regs(misccfg->treset_cntr0_val, + misccfg->treset_cntr1_val, + misccfg->treset_cntr2_val, rwcfg->init_reset_1_cke_0); /* Bring up clock enable. */ @@ -1028,7 +1021,7 @@ static void rw_mgr_mem_calibrate_write_test_issue(u32 group, { const u32 quick_write_mode = (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES) && - ENABLE_SUPER_QUICK_CALIBRATION; + misccfg->enable_super_quick_calibration; u32 mcc_instruction; u32 rw_wl_nop_cycles; @@ -1079,9 +1072,9 @@ static void rw_mgr_mem_calibrate_write_test_issue(u32 group, } else { mcc_instruction = rwcfg->lfsr_wr_rd_bank_0_wl_1; writel(rwcfg->lfsr_wr_rd_bank_0_data, - &sdr_rw_load_jump_mgr_regs->load_jump_add2); + &sdr_rw_load_jump_mgr_regs->load_jump_add2); writel(rwcfg->lfsr_wr_rd_bank_0_nop, - &sdr_rw_load_jump_mgr_regs->load_jump_add3); + &sdr_rw_load_jump_mgr_regs->load_jump_add3); } } else if (rw_wl_nop_cycles == 0) { /* @@ -1099,7 +1092,7 @@ static void rw_mgr_mem_calibrate_write_test_issue(u32 group, } else { mcc_instruction = rwcfg->lfsr_wr_rd_bank_0; writel(rwcfg->lfsr_wr_rd_bank_0_dqs, - &sdr_rw_load_jump_mgr_regs->load_jump_add2); + &sdr_rw_load_jump_mgr_regs->load_jump_add2); } } else { /* @@ -1118,11 +1111,11 @@ static void rw_mgr_mem_calibrate_write_test_issue(u32 group, if (test_dm) { mcc_instruction = rwcfg->lfsr_wr_rd_dm_bank_0; writel(rwcfg->lfsr_wr_rd_dm_bank_0_nop, - &sdr_rw_load_jump_mgr_regs->load_jump_add3); + &sdr_rw_load_jump_mgr_regs->load_jump_add3); } else { mcc_instruction = rwcfg->lfsr_wr_rd_bank_0; writel(rwcfg->lfsr_wr_rd_bank_0_nop, - &sdr_rw_load_jump_mgr_regs->load_jump_add3); + &sdr_rw_load_jump_mgr_regs->load_jump_add3); } } @@ -1144,10 +1137,10 @@ static void rw_mgr_mem_calibrate_write_test_issue(u32 group, if (test_dm) { writel(rwcfg->lfsr_wr_rd_dm_bank_0_wait, - &sdr_rw_load_jump_mgr_regs->load_jump_add1); + &sdr_rw_load_jump_mgr_regs->load_jump_add1); } else { writel(rwcfg->lfsr_wr_rd_bank_0_wait, - &sdr_rw_load_jump_mgr_regs->load_jump_add1); + &sdr_rw_load_jump_mgr_regs->load_jump_add1); } writel(mcc_instruction, (SDR_PHYGRP_RWMGRGRP_ADDRESS | @@ -1260,11 +1253,11 @@ rw_mgr_mem_calibrate_read_test_patterns(const u32 rank_bgn, const u32 group, /* Load up a constant bursts of read commands */ writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0); writel(rwcfg->guaranteed_read, - &sdr_rw_load_jump_mgr_regs->load_jump_add0); + &sdr_rw_load_jump_mgr_regs->load_jump_add0); writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1); writel(rwcfg->guaranteed_read_cont, - &sdr_rw_load_jump_mgr_regs->load_jump_add1); + &sdr_rw_load_jump_mgr_regs->load_jump_add1); tmp_bit_chk = 0; for (vg = rwcfg->mem_virtual_groups_per_read_dqs - 1; @@ -1324,22 +1317,22 @@ static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn, writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0); writel(rwcfg->guaranteed_write_wait0, - &sdr_rw_load_jump_mgr_regs->load_jump_add0); + &sdr_rw_load_jump_mgr_regs->load_jump_add0); writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1); writel(rwcfg->guaranteed_write_wait1, - &sdr_rw_load_jump_mgr_regs->load_jump_add1); + &sdr_rw_load_jump_mgr_regs->load_jump_add1); writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2); writel(rwcfg->guaranteed_write_wait2, - &sdr_rw_load_jump_mgr_regs->load_jump_add2); + &sdr_rw_load_jump_mgr_regs->load_jump_add2); writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3); writel(rwcfg->guaranteed_write_wait3, - &sdr_rw_load_jump_mgr_regs->load_jump_add3); + &sdr_rw_load_jump_mgr_regs->load_jump_add3); writel(rwcfg->guaranteed_write, SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET); @@ -1372,7 +1365,7 @@ rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group, (rank_bgn + NUM_RANKS_PER_SHADOW_REG); const u32 quick_read_mode = ((STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS) && - ENABLE_SUPER_QUICK_CALIBRATION); + misccfg->enable_super_quick_calibration); u32 correct_mask_vg = param->read_correct_mask_vg; u32 tmp_bit_chk; u32 base_rw_mgr; @@ -1389,11 +1382,11 @@ rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group, writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1); writel(rwcfg->read_b2b_wait1, - &sdr_rw_load_jump_mgr_regs->load_jump_add1); + &sdr_rw_load_jump_mgr_regs->load_jump_add1); writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2); writel(rwcfg->read_b2b_wait2, - &sdr_rw_load_jump_mgr_regs->load_jump_add2); + &sdr_rw_load_jump_mgr_regs->load_jump_add2); if (quick_read_mode) writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0); @@ -1404,7 +1397,7 @@ rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group, writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0); writel(rwcfg->read_b2b, - &sdr_rw_load_jump_mgr_regs->load_jump_add0); + &sdr_rw_load_jump_mgr_regs->load_jump_add0); if (all_groups) writel(rwcfg->mem_if_read_dqs_width * rwcfg->mem_virtual_groups_per_read_dqs - 1, @@ -1413,7 +1406,7 @@ rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group, writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3); writel(rwcfg->read_b2b, - &sdr_rw_load_jump_mgr_regs->load_jump_add3); + &sdr_rw_load_jump_mgr_regs->load_jump_add3); tmp_bit_chk = 0; for (vg = rwcfg->mem_virtual_groups_per_read_dqs - 1; vg >= 0; @@ -1432,8 +1425,9 @@ rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group, } writel(rwcfg->read_b2b, addr + - ((group * rwcfg->mem_virtual_groups_per_read_dqs + - vg) << 2)); + ((group * + rwcfg->mem_virtual_groups_per_read_dqs + + vg) << 2)); base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS); tmp_bit_chk <<= rwcfg->mem_dq_per_read_dqs / @@ -1506,7 +1500,7 @@ static void rw_mgr_decr_vfifo(const u32 grp) { u32 i; - for (i = 0; i < VFIFO_SIZE - 1; i++) + for (i = 0; i < misccfg->read_valid_fifo_size - 1; i++) rw_mgr_incr_vfifo(grp); } @@ -1520,7 +1514,7 @@ static int find_vfifo_failing_read(const u32 grp) { u32 v, ret, fail_cnt = 0; - for (v = 0; v < VFIFO_SIZE; v++) { + for (v = 0; v < misccfg->read_valid_fifo_size; v++) { debug_cond(DLEVEL == 2, "%s:%d: vfifo %u\n", __func__, __LINE__, v); ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1, @@ -1555,7 +1549,8 @@ static int find_vfifo_failing_read(const u32 grp) static int sdr_find_phase_delay(int working, int delay, const u32 grp, u32 *work, const u32 work_inc, u32 *pd) { - const u32 max = delay ? iocfg->dqs_en_delay_max : iocfg->dqs_en_phase_max; + const u32 max = delay ? iocfg->dqs_en_delay_max : + iocfg->dqs_en_phase_max; u32 ret; for (; *pd <= max; (*pd)++) { @@ -1591,7 +1586,7 @@ static int sdr_find_phase_delay(int working, int delay, const u32 grp, static int sdr_find_phase(int working, const u32 grp, u32 *work, u32 *i, u32 *p) { - const u32 end = VFIFO_SIZE + (working ? 0 : 1); + const u32 end = misccfg->read_valid_fifo_size + (working ? 0 : 1); int ret; for (; *i < end; (*i)++) { @@ -1671,7 +1666,8 @@ static void sdr_backup_phase(const u32 grp, u32 *work_bgn, u32 *p) tmp_delay = *work_bgn - iocfg->delay_per_opa_tap; scc_mgr_set_dqs_en_phase_all_ranks(grp, *p); - for (d = 0; d <= iocfg->dqs_en_delay_max && tmp_delay < *work_bgn; d++) { + for (d = 0; d <= iocfg->dqs_en_delay_max && tmp_delay < *work_bgn; + d++) { scc_mgr_set_dqs_en_delay_all_ranks(grp, d); ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1, @@ -1758,7 +1754,8 @@ static int sdr_find_window_center(const u32 grp, const u32 work_bgn, debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", p, tmp_delay); - d = DIV_ROUND_UP(work_mid - tmp_delay, iocfg->delay_per_dqs_en_dchain_tap); + d = DIV_ROUND_UP(work_mid - tmp_delay, + iocfg->delay_per_dqs_en_dchain_tap); if (d > iocfg->dqs_en_delay_max) d = iocfg->dqs_en_delay_max; tmp_delay += d * iocfg->delay_per_dqs_en_dchain_tap; @@ -1772,7 +1769,7 @@ static int sdr_find_window_center(const u32 grp, const u32 work_bgn, * push vfifo until we can successfully calibrate. We can do this * because the largest possible margin in 1 VFIFO cycle. */ - for (i = 0; i < VFIFO_SIZE; i++) { + for (i = 0; i < misccfg->read_valid_fifo_size; i++) { debug_cond(DLEVEL == 2, "find_dqs_en_phase: center\n"); if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1, PASS_ONE_BIT, @@ -1814,7 +1811,8 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp) scc_mgr_set_dqs_en_phase_all_ranks(grp, 0); /* Step 0: Determine number of delay taps for each phase tap. */ - dtaps_per_ptap = iocfg->delay_per_opa_tap / iocfg->delay_per_dqs_en_dchain_tap; + dtaps_per_ptap = iocfg->delay_per_opa_tap / + iocfg->delay_per_dqs_en_dchain_tap; /* Step 1: First push vfifo until we get a failing read. */ find_vfifo_failing_read(grp); @@ -2028,8 +2026,10 @@ static void search_left_edge(const int write, const int rank_bgn, u32 *sticky_bit_chk, int *left_edge, int *right_edge, const u32 use_read_test) { - const u32 delay_max = write ? iocfg->io_out1_delay_max : iocfg->io_in_delay_max; - const u32 dqs_max = write ? iocfg->io_out1_delay_max : iocfg->dqs_in_delay_max; + const u32 delay_max = write ? iocfg->io_out1_delay_max : + iocfg->io_in_delay_max; + const u32 dqs_max = write ? iocfg->io_out1_delay_max : + iocfg->dqs_in_delay_max; const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs : rwcfg->mem_dq_per_read_dqs; u32 stop, bit_chk; @@ -2114,8 +2114,6 @@ static void search_left_edge(const int write, const int rank_bgn, *sticky_bit_chk |= 1; } } - - } /** @@ -2139,8 +2137,10 @@ static int search_right_edge(const int write, const int rank_bgn, u32 *sticky_bit_chk, int *left_edge, int *right_edge, const u32 use_read_test) { - const u32 delay_max = write ? iocfg->io_out1_delay_max : iocfg->io_in_delay_max; - const u32 dqs_max = write ? iocfg->io_out1_delay_max : iocfg->dqs_in_delay_max; + const u32 delay_max = write ? iocfg->io_out1_delay_max : + iocfg->io_in_delay_max; + const u32 dqs_max = write ? iocfg->io_out1_delay_max : + iocfg->dqs_in_delay_max; const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs : rwcfg->mem_dq_per_read_dqs; u32 stop, bit_chk; @@ -2153,7 +2153,7 @@ static int search_right_edge(const int write, const int rank_bgn, } else { /* READ-ONLY */ scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs); if (iocfg->shift_dqs_en_when_shift_dqs) { - uint32_t delay = d + start_dqs_en; + u32 delay = d + start_dqs_en; if (delay > iocfg->dqs_en_delay_max) delay = iocfg->dqs_en_delay_max; scc_mgr_set_dqs_en_delay(read_group, delay); @@ -2168,7 +2168,8 @@ static int search_right_edge(const int write, const int rank_bgn, use_read_test); if (stop == 1) { if (write && (d == 0)) { /* WRITE-ONLY */ - for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) { + for (i = 0; i < rwcfg->mem_dq_per_write_dqs; + i++) { /* * d = 0 failed, but it passed when * testing the left edge, so it must be @@ -2307,7 +2308,8 @@ static void center_dq_windows(const int write, int *left_edge, int *right_edge, const int min_index, const int test_bgn, int *dq_margin, int *dqs_margin) { - const u32 delay_max = write ? iocfg->io_out1_delay_max : iocfg->io_in_delay_max; + const u32 delay_max = write ? iocfg->io_out1_delay_max : + iocfg->io_in_delay_max; const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs : rwcfg->mem_dq_per_read_dqs; const u32 delay_off = write ? SCC_MGR_IO_OUT1_DELAY_OFFSET : @@ -2345,9 +2347,11 @@ static void center_dq_windows(const int write, int *left_edge, int *right_edge, i, shift_dq); if (write) - scc_mgr_set_dq_out1_delay(i, temp_dq_io_delay1 + shift_dq); + scc_mgr_set_dq_out1_delay(i, + temp_dq_io_delay1 + shift_dq); else - scc_mgr_set_dq_in_delay(p, temp_dq_io_delay1 + shift_dq); + scc_mgr_set_dq_in_delay(p, + temp_dq_io_delay1 + shift_dq); scc_mgr_load_dq(p); @@ -2363,7 +2367,6 @@ static void center_dq_windows(const int write, int *left_edge, int *right_edge, if (right_edge[i] + shift_dq - (-mid_min) < *dqs_margin) *dqs_margin = right_edge[i] + shift_dq - (-mid_min); } - } /** @@ -2387,7 +2390,7 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn, * Store these as signed since there are comparisons with * signed numbers. */ - uint32_t sticky_bit_chk; + u32 sticky_bit_chk; int32_t left_edge[rwcfg->mem_dq_per_read_dqs]; int32_t right_edge[rwcfg->mem_dq_per_read_dqs]; int32_t orig_mid_min, mid_min; @@ -2467,7 +2470,8 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn, if (iocfg->shift_dqs_en_when_shift_dqs) { if (start_dqs_en - mid_min > iocfg->dqs_en_delay_max) - mid_min += start_dqs_en - mid_min - iocfg->dqs_en_delay_max; + mid_min += start_dqs_en - mid_min - + iocfg->dqs_en_delay_max; else if (start_dqs_en - mid_min < 0) mid_min += start_dqs_en - mid_min; } @@ -2671,9 +2675,9 @@ rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group, const u32 test_bgn, */ static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn) { - uint32_t p, d; - uint32_t dtaps_per_ptap; - uint32_t failed_substage; + u32 p, d; + u32 dtaps_per_ptap; + u32 failed_substage; int ret; @@ -2789,7 +2793,7 @@ static int rw_mgr_mem_calibrate_vfifo_end(const u32 rw_group, * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages". * Calibrate LFIFO to find smallest read latency. */ -static uint32_t rw_mgr_mem_calibrate_lfifo(void) +static u32 rw_mgr_mem_calibrate_lfifo(void) { int found_one = 0; @@ -2873,8 +2877,8 @@ static void search_window(const int search_dm, /* For DQS, we go from 0...max */ d = max - di; /* - * Note: This only shifts DQS, so are we limiting ourselve to - * width of DQ unnecessarily. + * Note: This only shifts DQS, so are we limiting + * ourselves to width of DQ unnecessarily. */ scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, d + new_dqs); @@ -3140,11 +3144,11 @@ static void mem_precharge_and_activate(void) writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0); writel(rwcfg->activate_0_and_1_wait1, - &sdr_rw_load_jump_mgr_regs->load_jump_add0); + &sdr_rw_load_jump_mgr_regs->load_jump_add0); writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1); writel(rwcfg->activate_0_and_1_wait2, - &sdr_rw_load_jump_mgr_regs->load_jump_add1); + &sdr_rw_load_jump_mgr_regs->load_jump_add1); /* Activate rows. */ writel(rwcfg->activate_0_and_1, SDR_PHYGRP_RWMGRGRP_ADDRESS | @@ -3164,7 +3168,7 @@ static void mem_init_latency(void) * so max latency in AFI clocks, used here, is correspondingly * smaller. */ - const u32 max_latency = (1 << MAX_LATENCY_COUNT_WIDTH) - 1; + const u32 max_latency = (1 << misccfg->max_latency_count_width) - 1; u32 rlat, wlat; debug("%s:%d\n", __func__, __LINE__); @@ -3199,8 +3203,8 @@ static void mem_init_latency(void) */ static void mem_skip_calibrate(void) { - uint32_t vfifo_offset; - uint32_t i, j, r; + u32 vfifo_offset; + u32 i, j, r; debug("%s:%d\n", __func__, __LINE__); /* Need to update every shadow register set used by the interface */ @@ -3234,7 +3238,8 @@ static void mem_skip_calibrate(void) * * Hence, to make DQS aligned to CK, we need to delay * DQS by: - * (720 - 90 - 180 - 2 * (360 / iocfg->dll_chain_length)) + * (720 - 90 - 180 - 2) * + * (360 / iocfg->dll_chain_length) * * Dividing the above by (360 / iocfg->dll_chain_length) * gives us the number of ptaps, which simplies to: @@ -3242,7 +3247,7 @@ static void mem_skip_calibrate(void) * (1.25 * iocfg->dll_chain_length - 2) */ scc_mgr_set_dqdqs_output_phase(i, - 1.25 * iocfg->dll_chain_length - 2); + 1.25 * iocfg->dll_chain_length - 2); } writel(0xff, &sdr_scc_mgr->dqs_ena); writel(0xff, &sdr_scc_mgr->dqs_io_ena); @@ -3267,7 +3272,7 @@ static void mem_skip_calibrate(void) * ArriaV has hard FIFOs that can only be initialized by incrementing * in sequencer. */ - vfifo_offset = CALIB_VFIFO_OFFSET; + vfifo_offset = misccfg->calib_vfifo_offset; for (j = 0; j < vfifo_offset; j++) writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy); writel(0, &phy_mgr_cmd->fifo_reset); @@ -3276,7 +3281,7 @@ static void mem_skip_calibrate(void) * For Arria V and Cyclone V with hard LFIFO, we get the skip-cal * setting from generation-time constant. */ - gbl->curr_read_lat = CALIB_LFIFO_OFFSET; + gbl->curr_read_lat = misccfg->calib_lfifo_offset; writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat); } @@ -3285,15 +3290,15 @@ static void mem_skip_calibrate(void) * * Perform memory calibration. */ -static uint32_t mem_calibrate(void) +static u32 mem_calibrate(void) { - uint32_t i; - uint32_t rank_bgn, sr; - uint32_t write_group, write_test_bgn; - uint32_t read_group, read_test_bgn; - uint32_t run_groups, current_run; - uint32_t failing_groups = 0; - uint32_t group_failed = 0; + u32 i; + u32 rank_bgn, sr; + u32 write_group, write_test_bgn; + u32 read_group, read_test_bgn; + u32 run_groups, current_run; + u32 failing_groups = 0; + u32 group_failed = 0; const u32 rwdqs_ratio = rwcfg->mem_if_read_dqs_width / rwcfg->mem_if_write_dqs_width; @@ -3352,7 +3357,6 @@ static uint32_t mem_calibrate(void) for (write_group = 0, write_test_bgn = 0; write_group < rwcfg->mem_if_write_dqs_width; write_group++, write_test_bgn += rwcfg->mem_dq_per_write_dqs) { - /* Initialize the group failure */ group_failed = 0; @@ -3381,7 +3385,8 @@ static uint32_t mem_calibrate(void) read_test_bgn)) continue; - if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS)) + if (!(gbl->phy_debug_mode_flags & + PHY_DEBUG_SWEEP_ALL_GROUPS)) return 0; /* The group failed, we're done. */ @@ -3396,16 +3401,19 @@ static uint32_t mem_calibrate(void) continue; /* Not needed in quick mode! */ - if (STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS) + if (STATIC_CALIB_STEPS & + CALIB_SKIP_DELAY_SWEEPS) continue; /* Calibrate WRITEs */ if (!rw_mgr_mem_calibrate_writes(rank_bgn, - write_group, write_test_bgn)) + write_group, + write_test_bgn)) continue; group_failed = 1; - if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS)) + if (!(gbl->phy_debug_mode_flags & + PHY_DEBUG_SWEEP_ALL_GROUPS)) return 0; } @@ -3422,10 +3430,11 @@ static uint32_t mem_calibrate(void) continue; if (!rw_mgr_mem_calibrate_vfifo_end(read_group, - read_test_bgn)) + read_test_bgn)) continue; - if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS)) + if (!(gbl->phy_debug_mode_flags & + PHY_DEBUG_SWEEP_ALL_GROUPS)) return 0; /* The group failed, we're done. */ @@ -3512,7 +3521,7 @@ static int run_mem_calibrate(void) */ static void debug_mem_calibrate(int pass) { - uint32_t debug_info; + u32 debug_info; if (pass) { printf("%s: CALIBRATION PASSED\n", __FILE__); @@ -3584,7 +3593,7 @@ static void hc_initialize_rom_data(void) static void initialize_reg_file(void) { /* Initialize the register file with the correct data */ - writel(REG_FILE_INIT_SEQ_SIGNATURE, &sdr_reg_file->signature); + writel(misccfg->reg_file_init_seq_signature, &sdr_reg_file->signature); writel(0, &sdr_reg_file->debug_data_addr); writel(0, &sdr_reg_file->cur_stage); writel(0, &sdr_reg_file->fom); @@ -3600,13 +3609,13 @@ static void initialize_reg_file(void) */ static void initialize_hps_phy(void) { - uint32_t reg; + u32 reg; /* * Tracking also gets configured here because it's in the * same register. */ - uint32_t trk_sample_count = 7500; - uint32_t trk_long_idle_sample_count = (10 << 16) | 100; + u32 trk_sample_count = 7500; + u32 trk_long_idle_sample_count = (10 << 16) | 100; /* * Format is number of outer loops in the 16 MSB, sample * count in 16 LSB. @@ -3655,7 +3664,8 @@ static void initialize_tracking(void) * Compute usable version of value in case we skip full * computation later. */ - writel(DIV_ROUND_UP(iocfg->delay_per_opa_tap, iocfg->delay_per_dchain_tap) - 1, + writel(DIV_ROUND_UP(iocfg->delay_per_opa_tap, + iocfg->delay_per_dchain_tap) - 1, &sdr_reg_file->dtaps_per_ptap); /* trk_sample_count */ @@ -3690,7 +3700,7 @@ int sdram_calibration_full(void) { struct param_type my_param; struct gbl_type my_gbl; - uint32_t pass; + u32 pass; memset(&my_param, 0, sizeof(my_param)); memset(&my_gbl, 0, sizeof(my_gbl)); @@ -3700,6 +3710,7 @@ int sdram_calibration_full(void) rwcfg = socfpga_get_sdram_rwmgr_config(); iocfg = socfpga_get_sdram_io_config(); + misccfg = socfpga_get_sdram_misc_config(); /* Set the calibration enabled by default */ gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT; @@ -3736,7 +3747,8 @@ int sdram_calibration_full(void) iocfg->delay_per_opa_tap, iocfg->delay_per_dchain_tap); debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u", iocfg->delay_per_dqs_en_dchain_tap, iocfg->dll_chain_length); - debug_cond(DLEVEL == 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ", + debug_cond(DLEVEL == 1, + "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ", iocfg->dqs_en_phase_max, iocfg->dqdqs_out_phase_max, iocfg->dqs_en_delay_max, iocfg->dqs_in_delay_max); debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",