X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=drivers%2Fmtd%2Fnand%2Fomap_gpmc.c;h=5af213c75849d0615c022d1bceae7f8f2d2abcb4;hp=d5f3248157733dae95465b0ea8071b47a37135a5;hb=9221826dc2c5b9141e32df612436326f2cdd1b78;hpb=eecf9e2e78c3af4304740804b3649f3d4b8a922a diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index d5f3248157..5af213c758 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -2,23 +2,7 @@ * (C) Copyright 2004-2008 Texas Instruments, * Rohit Choraria * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -41,6 +25,190 @@ static __maybe_unused struct nand_ecclayout hw_nand_oob = static __maybe_unused struct nand_ecclayout hw_bch8_nand_oob = GPMC_NAND_HW_BCH8_ECC_LAYOUT; +static struct gpmc __iomem *gpmc_cfg = (void __iomem *)GPMC_BASE; + +#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT +static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' }; +static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' }; + +static struct nand_bbt_descr bbt_main_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | + NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 0, /* may be overwritten depending on ECC layout */ + .len = 4, + .veroffs = 4, /* may be overwritten depending on ECC layout */ + .maxblocks = 4, + .pattern = bbt_pattern, +}; + +static struct nand_bbt_descr bbt_mirror_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | + NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 0, /* may be overwritten depending on ECC layout */ + .len = 4, + .veroffs = 4, /* may be overwritten depending on ECC layout */ + .maxblocks = 4, + .pattern = mirror_pattern, +}; +#endif + +#define PREFETCH_FIFOTHRESHOLD_MAX 0x40 +#define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8) + +#define PREFETCH_ENABLEOPTIMIZEDACCESS (0x1 << 27) + +#define GPMC_PREFETCH_STATUS_FIFO_CNT(val) (((val) >> 24) & 0x7F) +#define GPMC_PREFETCH_STATUS_COUNT(val) ((val) & 0x00003fff) + +#define CS_NUM_SHIFT 24 +#define ENABLE_PREFETCH (0x1 << 7) +#define DMA_MPU_MODE 2 + +#define OMAP_NAND_TIMEOUT_MS 5000 + +#define PRINT_REG(x) debug("+++ %.15s (0x%08x)=0x%08x\n", #x, &gpmc_cfg->x, readl(&gpmc_cfg->x)) + +#ifdef CONFIG_SYS_GPMC_PREFETCH_ENABLE +/** + * gpmc_prefetch_enable - configures and starts prefetch transfer + * @cs: cs (chip select) number + * @fifo_th: fifo threshold to be used for read/ write + * @count: number of bytes to be transferred + * @is_write: prefetch read(0) or write post(1) mode + */ +static inline void gpmc_prefetch_enable(int cs, int fifo_th, + unsigned int count, int is_write) +{ + writel(count, &gpmc_cfg->pref_config2); + + /* Set the prefetch read / post write and enable the engine. + * Set which cs is has requested for. + */ + uint32_t val = (cs << CS_NUM_SHIFT) | + PREFETCH_ENABLEOPTIMIZEDACCESS | + PREFETCH_FIFOTHRESHOLD(fifo_th) | + ENABLE_PREFETCH | + !!is_write; + writel(val, &gpmc_cfg->pref_config1); + + /* Start the prefetch engine */ + writel(0x1, &gpmc_cfg->pref_control); +} + +/** + * gpmc_prefetch_reset - disables and stops the prefetch engine + */ +static inline void gpmc_prefetch_reset(void) +{ + /* Stop the PFPW engine */ + writel(0x0, &gpmc_cfg->pref_control); + + /* Reset/disable the PFPW engine */ + writel(0x0, &gpmc_cfg->pref_config1); +} + +//#define FIFO_IOADDR (nand->IO_ADDR_R) +#define FIFO_IOADDR PISMO1_NAND_BASE + +/** + * read_buf_pref - read data from NAND controller into buffer + * @mtd: MTD device structure + * @buf: buffer to store date + * @len: number of bytes to read + */ +static void read_buf_pref(struct mtd_info *mtd, u_char *buf, int len) +{ + gpmc_prefetch_enable(cs, PREFETCH_FIFOTHRESHOLD_MAX, len, 0); + do { + // Get number of bytes waiting in the FIFO + uint32_t read_bytes = GPMC_PREFETCH_STATUS_FIFO_CNT(readl(&gpmc_cfg->pref_status)); + + if (read_bytes == 0) + continue; + // Alignment of Destination Buffer + while (read_bytes && ((unsigned int)buf & 3)) { + *buf++ = readb(FIFO_IOADDR); + read_bytes--; + len--; + } + // Use maximum word size (32bit) inside this loop, because speed is limited by + // GPMC bus arbitration with a maximum transfer rate of 3.000.000/sec. + len -= read_bytes & ~3; + while (read_bytes >= 4) { + *((uint32_t*)buf) = readl(FIFO_IOADDR); + buf += 4; + read_bytes -= 4; + } + // Transfer the last (non-aligned) bytes only at the last iteration, + // to maintain full speed up to the end of the transfer. + if (read_bytes == len) { + while (read_bytes) { + *buf++ = readb(FIFO_IOADDR); + read_bytes--; + } + len = 0; + } + } while (len > 0); + gpmc_prefetch_reset(); +} + +/* + * write_buf_pref - write buffer to NAND controller + * @mtd: MTD device structure + * @buf: data buffer + * @len: number of bytes to write + */ +static void write_buf_pref(struct mtd_info *mtd, const u_char *buf, int len) +{ + /* configure and start prefetch transfer */ + gpmc_prefetch_enable(cs, PREFETCH_FIFOTHRESHOLD_MAX, len, 1); + + while (len) { + // Get number of free bytes in the FIFO + uint32_t write_bytes = GPMC_PREFETCH_STATUS_FIFO_CNT(readl(&gpmc_cfg->pref_status)); + + // don't write more bytes than requested + if (write_bytes > len) + write_bytes = len; + + // Alignment of Source Buffer + while (write_bytes && ((unsigned int)buf & 3)) { + writeb(*buf++, FIFO_IOADDR); + write_bytes--; + len--; + } + + // Use maximum word size (32bit) inside this loop, because speed is limited by + // GPMC bus arbitration with a maximum transfer rate of 3.000.000/sec. + len -= write_bytes & ~3; + while (write_bytes >= 4) { + writel(*((uint32_t*)buf), FIFO_IOADDR); + buf += 4; + write_bytes -= 4; + } + + // Transfer the last (non-aligned) bytes only at the last iteration, + // to maintain full speed up to the end of the transfer. + if (write_bytes == len) { + while (write_bytes) { + writeb(*buf++, FIFO_IOADDR); + write_bytes--; + } + len = 0; + } + } + + /* wait for data to be flushed out before resetting the prefetch */ + while ((len = GPMC_PREFETCH_STATUS_COUNT(readl(&gpmc_cfg->pref_status)))) { + debug("%u bytes still in FIFO\n", PREFETCH_FIFOTHRESHOLD_MAX - len); + ndelay(1); + } + + /* disable and stop the PFPW engine */ + gpmc_prefetch_reset(); +} +#endif /* CONFIG_SYS_GPMC_PREFETCH_ENABLE */ + /* * omap_nand_hwcontrol - Set the address pointers corretly for the * following address/data/command operation @@ -74,7 +242,7 @@ static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd, /* Check wait pin as dev ready indicator */ int omap_spl_dev_ready(struct mtd_info *mtd) { - return gpmc_cfg->status & (1 << 8); + return readl(&gpmc_cfg->status) & (1 << 8); } #endif @@ -232,12 +400,11 @@ static void __maybe_unused omap_enable_hwecc(struct mtd_info *mtd, int32_t mode) */ writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, &gpmc_cfg->ecc_size_config); - val = (dev_width << 7) | (cs << 1) | (0x1); + val = (dev_width << 7) | (cs << 1) | (1 << 0); writel(val, &gpmc_cfg->ecc_config); break; default: printf("Error: Unrecognized Mode[%d]!\n", mode); - break; } } @@ -276,7 +443,7 @@ static __maybe_unused struct nand_bch_priv bch_priv = { .mode = NAND_ECC_HW_BCH, .type = ECC_BCH8, .nibbles = ECC_BCH8_NIBBLES, - .control = NULL + .control = NULL, }; /* @@ -341,7 +508,7 @@ static void omap_hwecc_init_bch(struct nand_chip *chip, int32_t mode) * This ecc_size_config setting is for BCH sw library. * * Note: we only support BCH8 currently with BCH sw library! - * Should be really easy to adobt to BCH4, however some omap3 have + * Should be really easy to adopt to BCH4, however some omap3 have * flaws with BCH4. * * Here we are using wrapping mode 6 both for reading and writing, with: @@ -357,11 +524,14 @@ static void omap_hwecc_init_bch(struct nand_chip *chip, int32_t mode) * Configure the ecc engine in gpmc * We assume 512 Byte sector pages for access to NAND. */ - val = (1 << 16); /* enable BCH mode */ - val |= (bch->type << 12); /* setup BCH type */ - val |= (wr_mode << 8); /* setup wrapping mode */ - val |= (dev_width << 7); /* setup device width (16 or 8 bit) */ - val |= (cs << 1); /* setup chip select to work on */ + val = 1 << 16; /* select BCH mode */ + val |= bch->type << 12; /* setup BCH type */ + val |= wr_mode << 8; /* setup wrapping mode */ + val |= dev_width << 7; /* setup device width (16 or 8 bit) */ + val |= (chip->ecc.size / 512 - 1) << 4; /* set ECC size */ + val |= cs << 1; /* setup chip select to work on */ + val |= 1 << 0; /* enable ECC engine */ + debug("set ECC_CONFIG=0x%08x\n", val); writel(val, &gpmc_cfg->ecc_config); } @@ -377,8 +547,6 @@ static void omap_enable_ecc_bch(struct mtd_info *mtd, int32_t mode) struct nand_chip *chip = mtd->priv; omap_hwecc_init_bch(chip, mode); - /* enable ecc */ - writel((readl(&gpmc_cfg->ecc_config) | 0x1), &gpmc_cfg->ecc_config); } /* @@ -406,29 +574,33 @@ static void omap_read_bch8_result(struct mtd_info *mtd, uint8_t big_endian, uint8_t *ecc_code) { uint32_t *ptr; - int8_t i = 0, j; - - if (big_endian) { - ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3]; - ecc_code[i++] = readl(ptr) & 0xFF; - ptr--; - for (j = 0; j < 3; j++) { - ecc_code[i++] = (readl(ptr) >> 24) & 0xFF; - ecc_code[i++] = (readl(ptr) >> 16) & 0xFF; - ecc_code[i++] = (readl(ptr) >> 8) & 0xFF; + int8_t i = 0, j, k; + struct nand_chip *chip = mtd->priv; + int num_steps = chip->ecc.size / 512; + + for (k = 0; k < num_steps; k++) { + if (big_endian) { + ptr = &gpmc_cfg->bch_result_0_3[k].bch_result_x[3]; ecc_code[i++] = readl(ptr) & 0xFF; ptr--; - } - } else { - ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[0]; - for (j = 0; j < 3; j++) { + for (j = 0; j < 3; j++) { + ecc_code[i++] = (readl(ptr) >> 24) & 0xFF; + ecc_code[i++] = (readl(ptr) >> 16) & 0xFF; + ecc_code[i++] = (readl(ptr) >> 8) & 0xFF; + ecc_code[i++] = readl(ptr) & 0xFF; + ptr--; + } + } else { + ptr = &gpmc_cfg->bch_result_0_3[k].bch_result_x[0]; + for (j = 0; j < 3; j++) { + ecc_code[i++] = readl(ptr) & 0xFF; + ecc_code[i++] = (readl(ptr) >> 8) & 0xFF; + ecc_code[i++] = (readl(ptr) >> 16) & 0xFF; + ecc_code[i++] = (readl(ptr) >> 24) & 0xFF; + ptr++; + } ecc_code[i++] = readl(ptr) & 0xFF; - ecc_code[i++] = (readl(ptr) >> 8) & 0xFF; - ecc_code[i++] = (readl(ptr) >> 16) & 0xFF; - ecc_code[i++] = (readl(ptr) >> 24) & 0xFF; - ptr++; } - ecc_code[i++] = readl(ptr) & 0xFF; ecc_code[i++] = 0; /* 14th byte is always zero */ } } @@ -438,7 +610,7 @@ static void omap_read_bch8_result(struct mtd_info *mtd, uint8_t big_endian, * * @mtd: MTD device structure * @calc_ecc: ECC read from ECC registers - * @syndrome: Rotated syndrome will be retuned in this array + * @syndrome: Rotated syndrome will be returned in this array * */ static void omap_rotate_ecc_bch(struct mtd_info *mtd, uint8_t *calc_ecc, @@ -464,7 +636,7 @@ static void omap_rotate_ecc_bch(struct mtd_info *mtd, uint8_t *calc_ecc, break; } - for (i = 0, j = (n_bytes-1); i < n_bytes; i++, j--) + for (i = 0, j = n_bytes - 1; i < n_bytes; i++, j--) syndrome[i] = calc_ecc[j]; } @@ -553,35 +725,52 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, uint32_t error_count = 0; uint32_t error_loc[8]; uint32_t i, ecc_flag; + int k, ecc_bytes, num_steps; + + num_steps = chip->ecc.size / 512; + ecc_bytes = chip->ecc.bytes / num_steps; + + for (k = 0; k < num_steps; k++) { + ecc_flag = 0; + /* check if area is flashed */ + for (i = 0; i < chip->ecc.bytes && !ecc_flag; i++) + if (read_ecc[i] != 0xff) + ecc_flag = 1; + + if (ecc_flag) { + ecc_flag = 0; + /* check if any ecc error */ + for (i = 0; (i < ecc_bytes) && !ecc_flag; i++) + if (calc_ecc[i] != 0) + ecc_flag = 1; + } - ecc_flag = 0; - for (i = 0; i < chip->ecc.bytes; i++) - if (read_ecc[i] != 0xff) - ecc_flag = 1; + if (!ecc_flag) + return 0; - if (!ecc_flag) - return 0; + elm_reset(); + elm_config((enum bch_level)(bch->type)); - elm_reset(); - elm_config((enum bch_level)(bch->type)); + /* + * while reading ECC result we read it in big endian. + * Hence while loading to ELM we have rotate to get the right endian. + */ + omap_rotate_ecc_bch(mtd, calc_ecc, syndrome); - /* - * while reading ECC result we read it in big endian. - * Hence while loading to ELM we have rotate to get the right endian. - */ - omap_rotate_ecc_bch(mtd, calc_ecc, syndrome); + /* use elm module to check for errors */ + if (elm_check_error(syndrome, bch->nibbles, &error_count, + error_loc) != 0) { + printf("ECC: uncorrectable.\n"); + return -1; + } - /* use elm module to check for errors */ - if (elm_check_error(syndrome, bch->nibbles, &error_count, - error_loc) != 0) { - printf("ECC: uncorrectable.\n"); - return -1; + /* correct bch error */ + if (error_count > 0) + omap_fix_errors_bch(mtd, dat, error_count, error_loc); + dat += 512; + read_ecc += ecc_bytes; + calc_ecc += ecc_bytes; } - - /* correct bch error */ - if (error_count > 0) - omap_fix_errors_bch(mtd, dat, error_count, error_loc); - return 0; } @@ -604,14 +793,13 @@ static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip, uint8_t *ecc_calc = chip->buffers->ecccalc; uint8_t *ecc_code = chip->buffers->ecccode; uint32_t *eccpos = chip->ecc.layout->eccpos; - uint8_t *oob = chip->oob_poi; + uint8_t *oob = &chip->oob_poi[eccpos[0]]; uint32_t data_pos; uint32_t oob_pos; data_pos = 0; /* oob area start */ - oob_pos = (eccsize * eccsteps) + chip->ecc.layout->eccpos[0]; - oob += chip->ecc.layout->eccpos[0]; + oob_pos = (eccsize * eccsteps) + eccpos[0]; for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize, oob += eccbytes) { @@ -626,6 +814,12 @@ static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip, /* read syndrome */ chip->ecc.calculate(mtd, p, &ecc_calc[i]); + if (oob_required) { + /* reread the OOB area to get the metadata */ + chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, page); + chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); + } + data_pos += eccsize; oob_pos += eccbytes; } @@ -730,22 +924,22 @@ static int omap_correct_data_bch(struct mtd_info *mtd, u_char *data, data[errloc[i]/8] ^= 1 << (errloc[i] & 7); printf("corrected bitflip %u\n", errloc[i]); #ifdef DEBUG - puts("read_ecc: "); + printf("read_ecc: "); /* * BCH8 have 13 bytes of ECC; BCH4 needs adoption * here! */ for (i = 0; i < 13; i++) printf("%02x ", read_ecc[i]); - puts("\n"); - puts("calc_ecc: "); + printf("\n"); + printf("calc_ecc: "); for (i = 0; i < 13; i++) printf("%02x ", calc_ecc[i]); - puts("\n"); + printf("\n"); #endif } } else if (count < 0) { - puts("ecc unrecoverable error\n"); + printf("ecc unrecoverable error\n"); } return count; } @@ -903,7 +1097,7 @@ int board_nand_init(struct nand_chip *nand) nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd; nand->cmd_ctrl = omap_nand_hwcontrol; - nand->options = NAND_NO_PADDING | NAND_CACHEPRG; + nand->options = NAND_NO_PADDING | NAND_CACHEPRG | NAND_NO_SUBPAGE_WRITE; /* If we are 16 bit dev, our gpmc config tells us that */ if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000) nand->options |= NAND_BUSWIDTH_16; @@ -922,7 +1116,7 @@ int board_nand_init(struct nand_chip *nand) */ bch_priv.control = init_bch(13, 8, 0x201b /* hw polynominal */); if (!bch_priv.control) { - puts("Could not init_bch()\n"); + printf("Failed to initialize BCH engine\n"); return -ENODEV; } #endif @@ -934,8 +1128,14 @@ int board_nand_init(struct nand_chip *nand) #if defined(CONFIG_AM33XX) || defined(CONFIG_NAND_OMAP_BCH8) nand->ecc.mode = NAND_ECC_HW; nand->ecc.layout = &hw_bch8_nand_oob; +#ifdef CONFIG_SYS_GPMC_PREFETCH_ENABLE + nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE * 4; + nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES * 4; +#else nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE; nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES; +#endif + nand->ecc.strength = 8; nand->ecc.hwctl = omap_enable_ecc_bch; nand->ecc.correct = omap_correct_data_bch; nand->ecc.calculate = omap_calculate_ecc_bch; @@ -954,9 +1154,25 @@ int board_nand_init(struct nand_chip *nand) nand->ecc.hwctl = omap_enable_hwecc; nand->ecc.correct = omap_correct_data; nand->ecc.calculate = omap_calculate_ecc; + nand->ecc.strength = 1; omap_hwecc_init(nand); #endif #endif +#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT + if (nand->ecc.layout) { + bbt_main_descr.offs = nand->ecc.layout->oobfree[0].offset; + bbt_main_descr.veroffs = bbt_main_descr.offs + + sizeof(bbt_pattern); + + bbt_mirror_descr.offs = nand->ecc.layout->oobfree[0].offset; + bbt_mirror_descr.veroffs = bbt_mirror_descr.offs + + sizeof(mirror_pattern); + } + + nand->bbt_options |= NAND_BBT_USE_FLASH; + nand->bbt_td = &bbt_main_descr; + nand->bbt_md = &bbt_mirror_descr; +#endif #ifdef CONFIG_SPL_BUILD if (nand->options & NAND_BUSWIDTH_16) @@ -964,7 +1180,12 @@ int board_nand_init(struct nand_chip *nand) else nand->read_buf = nand_read_buf; nand->dev_ready = omap_spl_dev_ready; -#endif +#else +#ifdef CONFIG_SYS_GPMC_PREFETCH_ENABLE + nand->write_buf = write_buf_pref; + nand->read_buf = read_buf_pref; +#endif /* CONFIG_SYS_GPMC_PREFETCH_ENABLE */ +#endif /* CONFIG_SPL_BUILD */ return 0; }