X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=include%2Fconfigs%2FMPC8641HPCN.h;h=f20ee79e872938cfc48117ed83b2eadabecbbb30;hp=d92b12df74808a8427b45bd17fba84dd1100627a;hb=92aae64ec72b73346e4cdd978b3d4178afe77bfc;hpb=cacc342d5aa311673efdc05770cb53246dd41c9f diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index d92b12df74..f20ee79e87 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -1,39 +1,25 @@ /* - * Copyright 2006, 2010 Freescale Semiconductor. + * Copyright 2006, 2010-2011 Freescale Semiconductor. * * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ /* * MPC8641HPCN board configuration file * * Make sure you change the MAC address and other network params first, - * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. + * search for CONFIG_SERVERIP, etc. in this file. */ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* High Level Configuration Options */ -#define CONFIG_MPC86xx 1 /* MPC86xx */ #define CONFIG_MPC8641 1 /* MPC8641 specific */ #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ #define CONFIG_MP 1 /* support multiple processors */ @@ -41,6 +27,12 @@ /*#define CONFIG_PHYS_64BIT 1*/ /* Place devices in 36-bit space */ #define CONFIG_ADDR_MAP 1 /* Use addr map */ +/* + * default CCSRBAR is at 0xff700000 + * assume U-Boot is less than 0.5MB + */ +#define CONFIG_SYS_TEXT_BASE 0xeff00000 + #ifdef RUN_DIAG #define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE #endif @@ -51,18 +43,14 @@ */ #define CONFIG_SYS_SCRATCH_VA 0xe0000000 -/* - * set this to enable Rapid IO. PCI and RIO are mutually exclusive - */ -/*#define CONFIG_RIO 1*/ +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ -#ifndef CONFIG_RIO /* RIO/PCI are mutually exclusive */ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ #define CONFIG_PCIE1 1 /* PCIE controler 1 (ULI bridge) */ #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot) */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ -#endif #define CONFIG_FSL_LAW 1 /* Use common FSL law init code */ #define CONFIG_TSEC_ENET /* tsec ethernet support */ @@ -88,8 +76,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) #endif -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ #define CONFIG_SYS_MEMTEST_END 0x00400000 @@ -99,9 +85,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0. */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f00000000ULL +#define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f #else -#define CONFIG_SYS_PHYS_ADDR_HIGH 0x0 +#define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000 #endif /* @@ -114,21 +100,17 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* Physical addresses */ #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf -#define CONFIG_SYS_CCSRBAR_PHYS (CONFIG_SYS_CCSRBAR_PHYS_LOW \ - | ((u64)CONFIG_SYS_CCSRBAR_PHYS_HIGH << 32)) -#else -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW -#endif +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH CONFIG_SYS_PHYS_ADDR_HIGH +#define CONFIG_SYS_CCSRBAR_PHYS \ + PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ + CONFIG_SYS_CCSRBAR_PHYS_HIGH) #define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */ /* * DDR Setup */ -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD @@ -181,8 +163,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */ -#define CONFIG_SYS_FLASH_BASE_PHYS (CONFIG_SYS_FLASH_BASE \ - | CONFIG_SYS_PHYS_ADDR_HIGH) +#define CONFIG_SYS_FLASH_BASE_PHYS_LOW CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_FLASH_BASE_PHYS \ + PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ + CONFIG_SYS_PHYS_ADDR_HIGH) #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} @@ -204,12 +188,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * required for the smallest BAT mapping, so there's a 64k hole. */ #define CONFIG_SYS_LBC_BASE 0xffde0000 -#define CONFIG_SYS_LBC_BASE_PHYS (CONFIG_SYS_LBC_BASE \ - | CONFIG_SYS_PHYS_ADDR_HIGH) +#define CONFIG_SYS_LBC_BASE_PHYS_LOW CONFIG_SYS_LBC_BASE #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ #define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000) -#define PIXIS_BASE_PHYS (CONFIG_SYS_LBC_BASE_PHYS + 0x00010000) +#define PIXIS_BASE_PHYS_LOW (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000) +#define PIXIS_BASE_PHYS PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \ + CONFIG_SYS_PHYS_ADDR_HIGH) #define PIXIS_SIZE 0x00008000 /* 32k */ #define PIXIS_ID 0x0 /* Board ID at offset 0 */ #define PIXIS_VER 0x1 /* Board version at offset 1 */ @@ -239,7 +224,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #undef CONFIG_SYS_FLASH_CHECKSUM #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ #define CONFIG_FLASH_CFI_DRIVER @@ -265,13 +250,12 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #else #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ #endif -#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ /* Serial Port */ @@ -289,9 +273,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* Use the HUSH parser */ #define CONFIG_SYS_HUSH_PARSER -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#endif /* * Pass open firmware flat tree to kernel @@ -303,43 +284,55 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* * I2C */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3100 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* * RapidIO MMU */ -#define CONFIG_SYS_RIO_MEM_BASE 0x80000000 /* base address */ +#define CONFIG_SYS_SRIO1_MEM_BASE 0x80000000 /* base address */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_RIO_MEM_PHYS 0x0000000c00000000ULL +#define CONFIG_SYS_SRIO1_MEM_PHYS_LOW 0x00000000 +#define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x0000000c #else -#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE +#define CONFIG_SYS_SRIO1_MEM_PHYS_LOW CONFIG_SYS_SRIO1_MEM_BASE +#define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x00000000 #endif -#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ +#define CONFIG_SYS_SRIO1_MEM_PHYS \ + PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ + CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */ /* * General PCI * Addresses are mapped 1-1. */ +#define CONFIG_SYS_PCIE1_NAME "ULI" #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x0000000c00000000ULL +#define CONFIG_SYS_PCIE1_MEM_PHYS_LOW 0x00000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x0000000c #else #define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_VIRT +#define CONFIG_SYS_PCIE1_MEM_PHYS_LOW CONFIG_SYS_PCIE1_MEM_VIRT +#define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x00000000 #endif +#define CONFIG_SYS_PCIE1_MEM_PHYS \ + PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ + CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 -#define CONFIG_SYS_PCIE1_IO_PHYS (CONFIG_SYS_PCIE1_IO_VIRT \ - | CONFIG_SYS_PHYS_ADDR_HIGH) +#define CONFIG_SYS_PCIE1_IO_PHYS_LOW CONFIG_SYS_PCIE1_IO_VIRT +#define CONFIG_SYS_PCIE1_IO_PHYS \ + PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ + CONFIG_SYS_PHYS_ADDR_HIGH) #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */ #ifdef CONFIG_PHYS_64BIT @@ -355,12 +348,17 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif #define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \ + CONFIG_SYS_PCIE1_MEM_SIZE) +#define CONFIG_SYS_PCIE2_MEM_PHYS_LOW (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \ + + CONFIG_SYS_PCIE1_MEM_SIZE) +#define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH CONFIG_SYS_PCIE1_MEM_PHYS_HIGH #define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \ + CONFIG_SYS_PCIE1_MEM_SIZE) #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \ + CONFIG_SYS_PCIE1_IO_SIZE) +#define CONFIG_SYS_PCIE2_IO_PHYS_LOW (CONFIG_SYS_PCIE1_IO_PHYS_LOW \ + + CONFIG_SYS_PCIE1_IO_SIZE) #define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \ + CONFIG_SYS_PCIE1_IO_SIZE) #define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE @@ -371,7 +369,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE -#define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ #define CONFIG_RTL8139 @@ -417,6 +414,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SCSI_AHCI #ifdef CONFIG_SCSI_AHCI +#define CONFIG_LIBATA #define CONFIG_SATA_ULI5288 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 #define CONFIG_SYS_SCSI_MAX_LUN 1 @@ -428,10 +426,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #if defined(CONFIG_TSEC_ENET) -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 -#endif - #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_TSEC1 1 @@ -460,21 +454,22 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif /* CONFIG_TSEC_ENET */ -/* Contort an addr into the format needed for BATs */ -#ifdef CONFIG_PHYS_64BIT -#define BAT_PHYS_ADDR(x) ((unsigned long) \ - ((x & 0x00000000ffffffffULL) | \ - ((x & 0x0000000e00000000ULL) >> 24) | \ - ((x & 0x0000000100000000ULL) >> 30))) -#else -#define BAT_PHYS_ADDR(x) (x) -#endif - -/* Put high physical address bits into the BAT format */ +#ifdef CONFIG_PHYS_64BIT #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8) #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2) +/* Put physical address into the BAT format */ +#define BAT_PHYS_ADDR(low, high) \ + (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high)) +/* Convert high/low pairs to actual 64-bit value */ +#define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32)) +#else +/* 32-bit systems just ignore the "high" bits */ +#define BAT_PHYS_ADDR(low, high) (low) +#define PAIRED_PHYS_TO_PHYS(low, high) (low) +#endif + /* * BAT0 DDR */ @@ -484,12 +479,14 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* * BAT1 LBC (PIXIS/CF) */ -#define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \ +#define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \ + CONFIG_SYS_PHYS_ADDR_HIGH) \ | BATL_PP_RW | BATL_CACHEINHIBIT | \ BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \ | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \ +#define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \ + CONFIG_SYS_PHYS_ADDR_HIGH) \ | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U @@ -499,45 +496,41 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * BAT2 Rapidio Memory */ #ifdef CONFIG_PCI -#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS) \ +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ + CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \ | BATL_PP_RW | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \ | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS) \ +#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ + CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \ | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U #else /* CONFIG_RIO */ -#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \ +#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ + CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \ | BATL_PP_RW | BATL_CACHEINHIBIT | \ BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M \ +#define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \ | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \ +#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ + CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \ | BATL_PP_RW | BATL_CACHEINHIBIT) - -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW \ - | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U #endif /* * BAT3 CCSR Space - * This BAT is used early; don't use any macros with ULL - use HIGH/LOW pairs - * instead. The assembler chokes on ULL. */ -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR_PHYS_LOW \ - | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ - | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ +#define CONFIG_SYS_DBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ + CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ | BATL_PP_RW | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \ | BATU_VP) -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR_PHYS_LOW \ - | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ - | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ +#define CONFIG_SYS_IBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ + CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U @@ -555,12 +548,14 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* * BAT4 PCIE1_IO and PCIE2_IO */ -#define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS) \ +#define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ + CONFIG_SYS_PHYS_ADDR_HIGH) \ | BATL_PP_RW | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \ | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS) \ +#define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ + CONFIG_SYS_PHYS_ADDR_HIGH) \ | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U @@ -575,19 +570,21 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* * BAT6 FLASH */ -#define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ +#define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ + CONFIG_SYS_PHYS_ADDR_HIGH) \ | BATL_PP_RW | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \ | BATU_VP) -#define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ +#define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ + CONFIG_SYS_PHYS_ADDR_HIGH) \ | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U /* Map the last 1M of flash where we're running from reset */ #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY @@ -605,7 +602,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); */ #ifndef CONFIG_SYS_RAMBOOT #define CONFIG_ENV_IS_IN_FLASH 1 - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000) + #define CONFIG_ENV_ADDR \ + (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ #else #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ @@ -629,16 +627,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* * Command line configuration. */ -#include - #define CONFIG_CMD_PING #define CONFIG_CMD_I2C #define CONFIG_CMD_REGINFO -#if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_SAVEENV -#endif - #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI #define CONFIG_CMD_SCSI @@ -655,7 +647,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -666,7 +657,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data @@ -675,31 +665,14 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); */ #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ - #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* * Environment Configuration */ -/* The mac addresses for all ethernet interface */ -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_ETHADDR 00:E0:0C:00:00:01 -#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD -#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD -#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD -#endif - #define CONFIG_HAS_ETH0 1 #define CONFIG_HAS_ETH1 1 #define CONFIG_HAS_ETH2 1 @@ -708,8 +681,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_IPADDR 192.168.1.100 #define CONFIG_HOSTNAME unknown -#define CONFIG_ROOTPATH /opt/nfsroot -#define CONFIG_BOOTFILE uImage +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ #define CONFIG_SERVERIP 192.168.1.1 @@ -726,13 +699,18 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ - "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ "tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ - "erase " MK_STR(TEXT_BASE) " +$filesize; " \ - "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ - "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ - "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ + " +$filesize; " \ + "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ + " +$filesize; " \ + "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ + " $filesize; " \ + "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ + " +$filesize; " \ + "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ + " $filesize\0" \ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=your.ramdisk.u-boot\0" \