X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=include%2Fconfigs%2Ftx6.h;h=d8ab70c31e92af68878c0aeee18ca5a15ac0f59d;hp=160b14257821b2973b532e1d19dc8082815e7448;hb=b86a63c42e39f4eb501dc923d51d2f7703aa90c7;hpb=047997571bf2c5bd43058c8e9da8052e09d9111f diff --git a/include/configs/tx6.h b/include/configs/tx6.h index 160b142578..d8ab70c31e 100644 --- a/include/configs/tx6.h +++ b/include/configs/tx6.h @@ -41,17 +41,27 @@ #define CONFIG_BOARD_LATE_INIT #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_CMD_GPIO #ifndef CONFIG_TX6_UBOOT_MFG /* LCD Logo and Splash screen support */ #ifdef CONFIG_LCD #define CONFIG_SPLASH_SCREEN #define CONFIG_SPLASH_SCREEN_ALIGN +#ifndef CONFIG_SOC_MX6UL #define CONFIG_VIDEO_IPUV3 #define CONFIG_IPUV3_CLK (CONFIG_SYS_SDRAM_CLK * 1000000 / 2) +#else +#define CONFIG_VIDEO_MXS +#define MXS_LCDIF_BASE 0x021c8000UL +#endif /* CONFIG_SOC_MX6UL */ #define CONFIG_LCD_LOGO #define LCD_BPP LCD_COLOR32 #define CONFIG_CMD_BMP +#define CONFIG_BMP_8BPP +#define CONFIG_BMP_16BPP +#define CONFIG_BMP_24BPP +#define CONFIG_BMP_32BPP #define CONFIG_VIDEO_BMP_RLE8 #endif /* CONFIG_LCD */ #endif /* CONFIG_TX6_UBOOT_MFG */ @@ -60,17 +70,36 @@ * Memory configuration options */ #define CONFIG_NR_DRAM_BANKS 0x1 /* # of SDRAM banks */ +#ifndef CONFIG_SOC_MX6UL #define PHYS_SDRAM_1 0x10000000 /* Base address of bank 1 */ -#ifdef CONFIG_SYS_SDRAM_BUS_WIDTH -#define PHYS_SDRAM_1_WIDTH CONFIG_SYS_SDRAM_BUS_WIDTH -#elif defined(CONFIG_SYS_SDRAM_BUS_WIDTH_32) -#define PHYS_SDRAM_1_WIDTH 32 +#define CONFIG_SYS_MPU_CLK 792 +#else +#define PHYS_SDRAM_1 0x80000000 /* Base address of bank 1 */ +#define CONFIG_SYS_MPU_CLK 528 +#endif +#ifndef CONFIG_SYS_SDRAM_BUS_WIDTH +#if defined(CONFIG_SYS_SDRAM_BUS_WIDTH_32) +#define CONFIG_SYS_SDRAM_BUS_WIDTH 32 #elif defined(CONFIG_SYS_SDRAM_BUS_WIDTH_16) -#define PHYS_SDRAM_1_WIDTH 16 +#define CONFIG_SYS_SDRAM_BUS_WIDTH 16 +#else +#define CONFIG_SYS_SDRAM_BUS_WIDTH 64 +#endif +#endif /* CONFIG_SYS_SDRAM_BUS_WIDTH */ +#ifdef __ASSEMBLY__ +#define _AC(x,s) x +#else +#define _AC(x,s) (x##s) +#endif +#define UL(x) _AC(x,UL) +#define PHYS_SDRAM_1_SIZE (UL(CONFIG_SYS_SDRAM_CHIP_SIZE) * SZ_1M \ + / 32 * CONFIG_SYS_SDRAM_BUS_WIDTH) +#if PHYS_SDRAM_1_SIZE > SZ_1G +#define FDT_HIGH_STR "fdt_high=ffffffff\0" #else -#define PHYS_SDRAM_1_WIDTH 64 +#define FDT_HIGH_STR "" #endif -#define PHYS_SDRAM_1_SIZE (SZ_512M / 32 * PHYS_SDRAM_1_WIDTH) + #ifdef CONFIG_SOC_MX6Q #define CONFIG_SYS_SDRAM_CLK 528 #else @@ -89,6 +118,7 @@ #if defined(CONFIG_SOC_MX6Q) #elif defined(CONFIG_SOC_MX6DL) #elif defined(CONFIG_SOC_MX6S) +#elif defined(CONFIG_SOC_MX6UL) #else #error Unsupported i.MX6 processor variant #endif @@ -166,6 +196,8 @@ "mtdids=" MTDIDS_DEFAULT "\0" \ "mtdparts=" MTDPARTS_DEFAULT "\0" #else +#define CONFIG_SYS_CPU_CLK_STR xstr(CONFIG_SYS_MPU_CLK) + #define CONFIG_EXTRA_ENV_SETTINGS \ "autostart=no\0" \ "baseboard=stk5-v3\0" \ @@ -190,13 +222,14 @@ ";dhcp\0" \ "bootm_cmd=bootm ${loadaddr} - ${fdtaddr}\0" \ "boot_mode=" CONFIG_SYS_DEFAULT_BOOT_MODE "\0" \ - "cpu_clk=800\0" \ + "cpu_clk=" CONFIG_SYS_CPU_CLK_STR "\0" \ "default_bootargs=setenv bootargs " CONFIG_BOOTARGS \ " ${append_bootargs}\0" \ EMMC_BOOT_PART_STR \ EMMC_BOOT_ACK_STR \ "fdtaddr=" xstr(CONFIG_FDTADDR) "\0" \ - CONFIG_SYS_FDTSAVE_CMD \ + FDT_HIGH_STR \ + FDTSAVE_CMD_STR \ "mtdids=" MTDIDS_DEFAULT "\0" \ "mtdparts=" MTDPARTS_DEFAULT "\0" \ "nfsroot=/tftpboot/rootfs\0" \ @@ -210,7 +243,7 @@ #define CONFIG_SYS_DEFAULT_BOOT_MODE "nand" #define CONFIG_SYS_BOOT_CMD_NAND \ "bootcmd_nand=setenv autostart no;run bootargs_ubifs;nboot linux\0" -#define CONFIG_SYS_FDTSAVE_CMD \ +#define FDTSAVE_CMD_STR \ "fdtsave=fdt resize;nand erase.part dtb" \ ";nand write ${fdtaddr} dtb ${fdtsize}\0" #define MTD_NAME "gpmi-nand" @@ -224,7 +257,7 @@ #define CONFIG_SYS_DEFAULT_BOOT_MODE "mmc" #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SYS_BOOT_CMD_NAND "" -#define CONFIG_SYS_FDTSAVE_CMD \ +#define FDTSAVE_CMD_STR \ "fdtsave=mmc partconf 0 ${emmc_boot_ack} ${emmc_boot_part} ${emmc_boot_part}" \ ";mmc write ${fdtaddr} " xstr(CONFIG_SYS_DTB_BLKNO) " 80" \ ";mmc partconf 0 ${emmc_boot_ack} ${emmc_boot_part} 0\0" @@ -259,7 +292,12 @@ /* This is required for the FEC driver to work with cache enabled */ #define CONFIG_SYS_ARM_CACHE_WRITETHROUGH +#ifndef CONFIG_SOC_MX6UL +#define CONFIG_FEC_MXC_PHYADDR 0 #define IMX_FEC_BASE ENET_BASE_ADDR +#else +#define FEC_MDIO_BASE_ADDR ENET_BASE_ADDR +#endif #define CONFIG_FEC_XCV_TYPE RMII #endif @@ -269,24 +307,38 @@ #ifdef CONFIG_HARD_I2C #define CONFIG_SYS_I2C_BASE I2C1_BASE_ADDR #define CONFIG_SYS_I2C_SPEED 400000 +#endif /* CONFIG_HARD_I2C */ #if defined(CONFIG_TX6_REV) #if CONFIG_TX6_REV == 0x1 -#define CONFIG_SYS_I2C_SLAVE 0x3c #define CONFIG_LTC3676 #elif CONFIG_TX6_REV == 0x2 -#define CONFIG_SYS_I2C_SLAVE 0x32 #define CONFIG_RN5T618 #elif CONFIG_TX6_REV == 0x3 -#define CONFIG_SYS_I2C_SLAVE 0x33 #define CONFIG_RN5T567 #else #error Unsupported TX6 module revision #endif -#endif /* CONFIG_TX6_REV */ +#else /* CONFIG_TX6_REV */ /* autodetect which PMIC is present to derive TX6_REV */ +#ifdef CONFIG_SOC_MX6UL +#ifndef CONFIG_TX6_UBOOT_NOENV +/* NOENV U-Boot is used for initial bootstrap. + * Since the TAMPER_PIN_DISABLE fuses have to be programmed + * to be able to use the TAMPER pins as GPIO to access the + * PMIC I2C bus, this is not possible on virgin hardware. + */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_SOFT +#define CONFIG_SYS_I2C_SOFT_SPEED 400000 +#define CONFIG_SOFT_I2C_GPIO_SCL IMX_GPIO_NR(5, 0) +#define CONFIG_SOFT_I2C_GPIO_SDA IMX_GPIO_NR(5, 1) +#define CONFIG_SOFT_I2C_READ_REPEATED_START +#endif /* CONFIG_TX6_UBOOT_NOENV */ +#else /* !CONFIG_SOC_MX6UL */ #define CONFIG_LTC3676 /* TX6_REV == 1 */ +#endif /* CONFIG_SOC_MX6UL */ #define CONFIG_RN5T567 /* TX6_REV == 3 */ -#endif /* CONFIG_CMD_I2C */ +#endif /* CONFIG_TX6_REV */ #define CONFIG_ENV_OVERWRITE