X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=include%2Ffpga.h;h=e0d12981b283ea93f9e4ef9fcf66076e4cc5bbda;hp=52d93b10096517361f50bcd3117671ba1e7957ca;hb=e05a951b1dc9e67859603d608e2afc36210eb10f;hpb=0ad4770f8eb052a84800925ea4ab342cfc10dc32

diff --git a/include/fpga.h b/include/fpga.h
index 52d93b1009..e0d12981b2 100644
--- a/include/fpga.h
+++ b/include/fpga.h
@@ -2,24 +2,7 @@
  * (C) Copyright 2002
  * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <linux/types.h>	       /* for ulong typedef */
@@ -31,24 +14,6 @@
 #define CONFIG_MAX_FPGA_DEVICES		5
 #endif
 
-/* these probably belong somewhere else */
-#ifndef FALSE
-#define FALSE			(0)
-#endif
-#ifndef TRUE
-#define TRUE			(!FALSE)
-#endif
-
-/* CONFIG_FPGA bit assignments */
-#define CFG_FPGA_MAN(x)		(x)
-#define CFG_FPGA_DEV(x)		((x) << 8 )
-#define CFG_FPGA_IF(x)		((x) << 16 )
-
-/* FPGA Manufacturer bits in CONFIG_FPGA */
-#define CFG_FPGA_XILINX		CFG_FPGA_MAN( 0x1 )
-#define CFG_FPGA_ALTERA		CFG_FPGA_MAN( 0x2 )
-
-
 /* fpga_xxxx function return value definitions */
 #define FPGA_SUCCESS		0
 #define FPGA_FAIL		-1
@@ -61,6 +26,7 @@ typedef enum {			/* typedef fpga_type */
 	fpga_min_type,		/* range check value */
 	fpga_xilinx,		/* Xilinx Family) */
 	fpga_altera,		/* unimplemented */
+	fpga_lattice,		/* Lattice family */
 	fpga_undefined		/* invalid range check value */
 } fpga_type;			/* end, typedef fpga_type */
 
@@ -69,13 +35,33 @@ typedef struct {		/* typedef fpga_desc */
 	void *devdesc;		/* real device descriptor */
 } fpga_desc;			/* end, typedef fpga_desc */
 
+typedef struct {                /* typedef fpga_desc */
+	unsigned int blocksize;
+	char *interface;
+	char *dev_part;
+	char *filename;
+	int fstype;
+} fpga_fs_info;
+
+typedef enum {
+	BIT_FULL = 0,
+	BIT_PARTIAL,
+} bitstream_type;
 
 /* root function definitions */
-extern void fpga_init( ulong reloc_off );
-extern int fpga_add( fpga_type devtype, void *desc );
-extern int fpga_count( void );
-extern int fpga_load( int devnum, void *buf, size_t bsize );
-extern int fpga_dump( int devnum, void *buf, size_t bsize );
-extern int fpga_info( int devnum );
+void fpga_init(void);
+int fpga_add(fpga_type devtype, void *desc);
+int fpga_count(void);
+const fpga_desc *const fpga_get_desc(int devnum);
+int fpga_load(int devnum, const void *buf, size_t bsize,
+	      bitstream_type bstype);
+int fpga_fsload(int devnum, const void *buf, size_t size,
+		fpga_fs_info *fpga_fsinfo);
+int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
+		       bitstream_type bstype);
+int fpga_dump(int devnum, const void *buf, size_t bsize);
+int fpga_info(int devnum);
+const fpga_desc *const fpga_validate(int devnum, const void *buf,
+				     size_t bsize, char *fn);
 
 #endif	/* _FPGA_H_ */