X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=include%2Fgdsys_fpga.h;h=8a5efe732ade33db532dab5df0694f9abc24e722;hp=f50e0e2733764bb3fcd8dfb27031c28771c37a80;hb=b64a3b26e26f988cbbb87080d630848c17749d63;hpb=56b50286d57d0a8769d28611a4e104fca972b3ff

diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h
index f50e0e2733..8a5efe732a 100644
--- a/include/gdsys_fpga.h
+++ b/include/gdsys_fpga.h
@@ -2,7 +2,7 @@
  * (C) Copyright 2010
  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
  *
- * SPDX-License-Identifier:	GPL-2.0+ 
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #ifndef __GDSYS_FPGA_H
@@ -43,10 +43,12 @@ struct ihs_gpio {
 };
 
 struct ihs_i2c {
-	u16 write_mailbox;
+	u16 interrupt_status;
+	u16 interrupt_enable;
 	u16 write_mailbox_ext;
-	u16 read_mailbox;
+	u16 write_mailbox;
 	u16 read_mailbox_ext;
+	u16 read_mailbox;
 };
 
 struct ihs_osd {
@@ -59,6 +61,22 @@ struct ihs_osd {
 	u16 y_pos;
 };
 
+struct ihs_mdio {
+	u16 control;
+	u16 address_data;
+	u16 rx_data;
+};
+
+struct ihs_io_ep {
+	u16 transmit_data;
+	u16 rx_tx_control;
+	u16 receive_data;
+	u16 rx_tx_status;
+	u16 reserved;
+	u16 device_address;
+	u16 target_address;
+};
+
 #ifdef CONFIG_NEO
 struct ihs_fpga {
 	u16 reflection_low;	/* 0x0000 */
@@ -84,7 +102,6 @@ struct ihs_fpga {
 #endif
 
 #ifdef CONFIG_IO64
-
 struct ihs_fpga_channel {
 	u16 status_int;
 	u16 config_int;
@@ -118,12 +135,50 @@ struct ihs_fpga {
 	u16 versions;		/* 0x0002 */
 	u16 fpga_version;	/* 0x0004 */
 	u16 fpga_features;	/* 0x0006 */
-	u16 reserved_0[6];	/* 0x0008 */
+	u16 reserved_0[1];	/* 0x0008 */
+	u16 top_interrupt;	/* 0x000a */
+	u16 reserved_1[4];	/* 0x000c */
+	struct ihs_gpio gpio;	/* 0x0014 */
+	u16 mpc3w_control;	/* 0x001a */
+	u16 reserved_2[2];	/* 0x001c */
+	struct ihs_io_ep ep;	/* 0x0020 */
+	u16 reserved_3[9];	/* 0x002e */
+	struct ihs_i2c i2c;	/* 0x0040 */
+	u16 reserved_4[10];	/* 0x004c */
+	u16 mc_int;		/* 0x0060 */
+	u16 mc_int_en;		/* 0x0062 */
+	u16 mc_status;		/* 0x0064 */
+	u16 mc_control;		/* 0x0066 */
+	u16 mc_tx_data;		/* 0x0068 */
+	u16 mc_tx_address;	/* 0x006a */
+	u16 mc_tx_cmd;		/* 0x006c */
+	u16 mc_res;		/* 0x006e */
+	u16 mc_rx_cmd_status;	/* 0x0070 */
+	u16 mc_rx_data;		/* 0x0072 */
+	u16 reserved_5[69];	/* 0x0074 */
+	u16 reflection_high;	/* 0x00fe */
+	struct ihs_osd osd;	/* 0x0100 */
+	u16 reserved_6[889];	/* 0x010e */
+	u16 videomem[31736];	/* 0x0800 */
+};
+#endif
+
+#ifdef CONFIG_HRCON
+struct ihs_fpga {
+	u16 reflection_low;	/* 0x0000 */
+	u16 versions;		/* 0x0002 */
+	u16 fpga_version;	/* 0x0004 */
+	u16 fpga_features;	/* 0x0006 */
+	u16 reserved_0[1];	/* 0x0008 */
+	u16 top_interrupt;	/* 0x000a */
+	u16 reserved_1[4];	/* 0x000c */
 	struct ihs_gpio gpio;	/* 0x0014 */
 	u16 mpc3w_control;	/* 0x001a */
-	u16 reserved_1[19];	/* 0x001c */
-	u16 videocontrol;	/* 0x0042 */
-	u16 reserved_2[14];	/* 0x0044 */
+	u16 reserved_2[2];	/* 0x001c */
+	struct ihs_io_ep ep;	/* 0x0020 */
+	u16 reserved_3[9];	/* 0x002e */
+	struct ihs_i2c i2c;	/* 0x0040 */
+	u16 reserved_4[10];	/* 0x004c */
 	u16 mc_int;		/* 0x0060 */
 	u16 mc_int_en;		/* 0x0062 */
 	u16 mc_status;		/* 0x0064 */
@@ -134,10 +189,10 @@ struct ihs_fpga {
 	u16 mc_res;		/* 0x006e */
 	u16 mc_rx_cmd_status;	/* 0x0070 */
 	u16 mc_rx_data;		/* 0x0072 */
-	u16 reserved_3[69];	/* 0x0074 */
+	u16 reserved_5[69];	/* 0x0074 */
 	u16 reflection_high;	/* 0x00fe */
 	struct ihs_osd osd;	/* 0x0100 */
-	u16 reserved_4[889];	/* 0x010e */
+	u16 reserved_6[889];	/* 0x010e */
 	u16 videomem[31736];	/* 0x0800 */
 };
 #endif
@@ -150,15 +205,13 @@ struct ihs_fpga {
 	u16 fpga_features;	/* 0x0006 */
 	u16 reserved_0[10];	/* 0x0008 */
 	u16 extended_interrupt; /* 0x001c */
-	u16 reserved_1[9];	/* 0x001e */
-	struct ihs_i2c i2c;	/* 0x0030 */
-	u16 reserved_2[16];	/* 0x0038 */
+	u16 reserved_1[29];	/* 0x001e */
 	u16 mpc3w_control;	/* 0x0058 */
-	u16 reserved_3[34];	/* 0x005a */
-	u16 videocontrol;	/* 0x009e */
-	u16 reserved_4[176];	/* 0x00a0 */
+	u16 reserved_2[3];	/* 0x005a */
+	struct ihs_i2c i2c;	/* 0x0060 */
+	u16 reserved_3[205];	/* 0x0066 */
 	struct ihs_osd osd;	/* 0x0200 */
-	u16 reserved_5[761];	/* 0x020e */
+	u16 reserved_4[761];	/* 0x020e */
 	u16 videomem[31736];	/* 0x0800 */
 };
 #endif