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EXYNOS5: Change parent clock of FIMD to MPLL
authorAjay Kumar <ajaykumar.rs@samsung.com>
Tue, 8 Jan 2013 20:42:23 +0000 (20:42 +0000)
committerMinkyu Kang <mk7.kang@samsung.com>
Thu, 10 Jan 2013 01:19:47 +0000 (10:19 +0900)
commit1673f199d917e0649098e0cb7ef5b375b96bd6cb
tree827f9a574affebaab94e75ee1f909585f4c2357btree | snapshot
parent9b572852c0547365b186651d27b3df5dcbe82be2commit | diff
EXYNOS5: Change parent clock of FIMD to MPLL

With VPLL as source clock to FIMD,
Exynos DP Initializaton was failing sometimes with unstable clock.
Changing FIMD source to MPLL resolves this issue.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
arch/arm/cpu/armv7/exynos/clock.c diff | blob | history
UBoot for KaRo TX COM modules