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(parent: ec145e8) | patch
fsl-ddr: change the default burst mode for DDR3
authorDave Liu <daveliu@freescale.com>
Fri, 5 Mar 2010 04:22:00 +0000 (12:22 +0800)
committerKumar Gala <galak@kernel.crashing.org>
Wed, 7 Apr 2010 05:08:06 +0000 (00:08 -0500)
commit22c9de064a218ae617bfeea35d2164532df91597
tree6e1584e8e71653185bdc0232568b1e73f976d722tree | snapshot
parentec145e87b80f6764d17a6b0aebf521fe758c3fdccommit | diff
fsl-ddr: change the default burst mode for DDR3

For 64B cacheline SoC, set the fixed 8-beat burst len,
for 32B cacheline SoC, set the On-The-Fly as default.

Signed-off-by: Dave Liu <daveliu@freescale.com>
cpu/mpc8xxx/ddr/options.c diff | blob | history
UBoot for KaRo TX COM modules