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(parent: 844f07d) | patch
ppc4xx/POST: Handle cached SDRAM correctly in Denali (440EPx) ECC POST
authorStefan Roese <sr@denx.de>
Fri, 26 Nov 2010 14:45:22 +0000 (15:45 +0100)
committerStefan Roese <sr@denx.de>
Sun, 28 Nov 2010 10:06:47 +0000 (11:06 +0100)
commit28e94bb2f7b796f58587752ab018b7d23fdc9061
treed753ad2372c254ea98e9c53ddc97fbe0a429e7eatree | snapshot
parent844f07d8a1f1330c97631b23fbf6425db2dc1508commit | diff
ppc4xx/POST: Handle cached SDRAM correctly in Denali (440EPx) ECC POST

This patch fixes a problem in the Denali (440EPx) SDRAM ECC POST test.
When cache is enabled in the SDRAM area, the values written to SDRAM
need to be flushed from cache to SDRAM using the dcfb instruction.

Without this patch the POST ECC test failed. Now its working again on
platforms with cache enabled in SDRAM.

Signed-off-by: Stefan Roese <sr@denx.de>
post/cpu/ppc4xx/denali_ecc.c diff | blob | history
UBoot for KaRo TX COM modules