nand: lpc32xx: add SLC NAND controller support
authorVladimir Zapolskiy <vz@mleia.com>
Sat, 18 Jul 2015 00:07:52 +0000 (03:07 +0300)
committerLothar Waßmann <LW@KARO-electronics.de>
Thu, 10 Sep 2015 06:24:12 +0000 (08:24 +0200)
commit4ace9bb52864de73b4a092e7110129fb38b1e451
tree25723422d5ad0d05bcbe41b0b5c9669bfbc4db97
parent052e88dfa4cb3eb4785037f28037f896bde1d431
nand: lpc32xx: add SLC NAND controller support

The change adds support of LPC32xx SLC NAND controller.

LPC32xx SoC has two different mutually exclusive NAND controllers to
communicate with single and multiple layer chips.

This simple driver allows to specify NAND chip timings and defines
custom read_buf()/write_buf() operations, because access to 8-bit data
register must be 32-bit aligned.

Support of hardware ECC calculation is not implemented (data
correction is always done by software), since it requires a working
DMA engine.

The driver can be included to an SPL image.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
arch/arm/cpu/arm926ejs/lpc32xx/devices.c
arch/arm/include/asm/arch-lpc32xx/clk.h
arch/arm/include/asm/arch-lpc32xx/sys_proto.h
drivers/mtd/nand/Makefile
drivers/mtd/nand/lpc32xx_nand_slc.c [new file with mode: 0644]