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Change PCIE1&2 deciide logic on MPC8544DS board more readable
authorRoy Zang <tie-fei.zang@freescale.com>
Fri, 9 Jan 2009 08:02:35 +0000 (16:02 +0800)
committerAndrew Fleming-AFLEMING <afleming@freescale.com>
Tue, 13 Jan 2009 22:32:53 +0000 (16:32 -0600)
commit6d3a10f73ece7ffb736890c10e023222612a4aa0
tree91218ae8474793be1d2a49b9b8078b1b7486bff7tree | snapshot
parent028e116811d28a031660f1ad9e20ac1293b3c5c7commit | diff
Change PCIE1&2 deciide logic on MPC8544DS board more readable

The IO port selection for MPC8544DS board:
 Port cfg_io_ports
 PCIE1 0x2, 0x3, 0x4, 0x5, 0x6, 0x7
 PCIE2 0x4, 0x5, 0x6, 0x7
 PCIE3 0x6, 0x7
 This patch changes the PCIE12 and PCIE2 logic more readable.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
board/freescale/mpc8544ds/mpc8544ds.c diff | blob | history
UBoot for KaRo TX COM modules