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(parent: be7bebe) | patch
p1014rdb: set ddr bus width properly depending on SVR
authorMatthew McClintock <msm@freescale.com>
Mon, 13 Aug 2012 08:10:37 +0000 (08:10 +0000)
committerAndy Fleming <afleming@freescale.com>
Thu, 23 Aug 2012 15:24:16 +0000 (10:24 -0500)
commit9c6b47d53ed329b31c5f26e9ec710f67559c07f0
treee249bf392017d29d3a90389685ac2f972c5fc4a9tree | snapshot
parentbe7bebeac24f33bd7eef2f5047579c1a680d8df1commit | diff
p1014rdb: set ddr bus width properly depending on SVR

Currently, for NAND boot for the P1010/4RDB we hard code the DDR
configuration. We can still dynamically set the DDR bus width in
the nand spl so the P1010/4RDB boards can boot from the same
u-boot image

Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
arch/powerpc/include/asm/fsl_ddr_sdram.h diff | blob | history
nand_spl/board/freescale/p1010rdb/nand_boot.c diff | blob | history
UBoot for KaRo TX COM modules