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(parent: 024333c) | patch
net/designware: Consecutive writes must have delay
authorArmando Visconti <armando.visconti@st.com>
Mon, 26 Mar 2012 00:09:55 +0000 (00:09 +0000)
committerJoe Hershberger <joe.hershberger@ni.com>
Wed, 4 Apr 2012 15:47:09 +0000 (10:47 -0500)
commitaa51005c3f7e517164fa000d68672041f6c4191f
tree83108435981ec813e9f8bcb007237021bd8245f5tree | snapshot
parent024333c96fecb698efe703e01f2326c1256114a4commit | diff
net/designware: Consecutive writes must have delay

This patch solves a TX/RX problem which happens at 10Mbps, due to the
fact that we are not respecting 4 cyles of the phy_clk (2.5MHz) between
two consecutive writes on the same register.

Signed-off-by: Armando Visconti <armando.visconti@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
drivers/net/designware.c diff | blob | history
UBoot for KaRo TX COM modules