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Tegra: Configure L2 cache control reg properly.
authorTom Warren <twarren@nvidia.com>
Mon, 25 Mar 2013 23:22:26 +0000 (16:22 -0700)
committerTom Warren <twarren@nvidia.com>
Mon, 15 Apr 2013 18:01:38 +0000 (11:01 -0700)
commitd0edce4fa394325a0ccfd38a5d668fb5ee1af34d
tree5a7ea0c182d9b2c33699fcfff230f83ba7b4ff84tree | snapshot
parent85434f9d7123c283b2233614178e7cfc968d329bcommit | diff
Tegra: Configure L2 cache control reg properly.

Without this change, kernel fails at calling function cache_clean_flush
during kernel early boot.

Aprocryphally, intended for T114 only, so I check for a T114 SoC.
Works (i.e. dalmore 3.8 kernel now starts printing to console).

Signed-off-by: Tom Warren <twarren@nvidia.com>
arch/arm/cpu/tegra-common/Makefile diff | blob | history
arch/arm/cpu/tegra-common/ap.c diff | blob | history
arch/arm/cpu/tegra-common/cache.c [new file with mode: 0644] blob
arch/arm/include/asm/arch-tegra/ap.h diff | blob | history
UBoot for KaRo TX COM modules