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driver/ddr/fsl: Fix DDR4 driver
authorYork Sun <yorksun@freescale.com>
Thu, 11 Sep 2014 20:32:06 +0000 (13:32 -0700)
committerYork Sun <yorksun@freescale.com>
Thu, 25 Sep 2014 15:36:20 +0000 (08:36 -0700)
commitf80d6472b47e73e35e4eaed6fc56ce5df2c82cdb
tree0d8686b5543a221089465049b6366fc993b826a1tree | snapshot
parent8aeb893a8ed97bac679149386cec53b275be3715commit | diff
driver/ddr/fsl: Fix DDR4 driver

When accumulated ECC is enabled, the DQ_MAP for ECC[4:7] needs to be set
to 0, i.e. 0->0, 1->1, etc., required by controller logic, even these pins
are not actually connected.

Also fix a bug when reading from DDR register to use proper accessor for
correct endianess.

Signed-off-by: York Sun <yorksun@freescale.com>
drivers/ddr/fsl/ctrl_regs.c diff | blob | history
drivers/ddr/fsl/fsl_ddr_gen4.c diff | blob | history
UBoot for KaRo TX COM modules