lpc32xx: devkit3250: add spl build support
authorVladimir Zapolskiy <vz@mleia.com>
Fri, 17 Jul 2015 22:47:11 +0000 (01:47 +0300)
committerLothar Waßmann <LW@KARO-electronics.de>
Thu, 10 Sep 2015 06:24:13 +0000 (08:24 +0200)
The change adds SPL build support to Timll DevKit3250 board, the
generated SPL image can be uploaded over UART5, JTAG or stored on
NAND. SPL is designed to load U-boot image from NAND.

All new NAND chip defines in board configuration are needed by
SPL NAND "simple" framework, the framework is used to reduce
potentially duplicated code from LPC32xx SLC NAND driver.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
arch/arm/Kconfig
board/timll/devkit3250/Makefile
board/timll/devkit3250/devkit3250_spl.c [new file with mode: 0644]
configs/devkit3250_defconfig
include/configs/devkit3250.h

index 7db7a5c..1fa6616 100644 (file)
@@ -178,6 +178,7 @@ config TARGET_MAXBCM
 config TARGET_DEVKIT3250
        bool "Support devkit3250"
        select CPU_ARM926EJS
+       select SUPPORT_SPL
 
 config TARGET_WORK_92105
        bool "Support work_92105"
index 4722986..74d5cd3 100644 (file)
@@ -6,3 +6,4 @@
 #
 
 obj-y  := devkit3250.o
+obj-$(CONFIG_SPL_BUILD) += devkit3250_spl.o
diff --git a/board/timll/devkit3250/devkit3250_spl.c b/board/timll/devkit3250/devkit3250_spl.c
new file mode 100644 (file)
index 0000000..bf52698
--- /dev/null
@@ -0,0 +1,68 @@
+/*
+ * Timll DevKit3250 board support, SPL board configuration
+ *
+ * (C) Copyright 2015 Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/emc.h>
+#include <asm/arch-lpc32xx/gpio.h>
+#include <spl.h>
+
+static struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
+
+/*
+ * SDRAM K4S561632N-LC60 settings are selected in assumption that
+ * SDRAM clock may be set up to 166 MHz, however at the moment
+ * it is 104 MHz. Most delay values are converted to be a multiple of
+ * base clock, and precise pinned values are not needed here.
+ */
+struct emc_dram_settings dram_64mb = {
+       .cmddelay       = 0x0001C000,
+       .config0        = 0x00005682,
+       .rascas0        = 0x00000302,
+       .rdconfig       = 0x00000011,   /* undocumented but crucial value */
+
+       .trp    = 83333333,
+       .tras   = 23809524,
+       .tsrex  = 12500000,
+       .twr    = 83000000,             /* tWR = tRDL = 2 CLK */
+       .trc    = 15384616,
+       .trfc   = 15384616,
+       .txsr   = 12500000,
+       .trrd   = 1,
+       .tmrd   = 1,
+       .tcdlr  = 0,
+
+       .refresh        = 130000,       /* 800 clock cycles */
+
+       .mode   = 0x00018000,
+       .emode  = 0x02000000,
+};
+
+void spl_board_init(void)
+{
+       /* First of all silence buzzer controlled by GPO_20 */
+       writel((1 << 20), &gpio->p3_outp_clr);
+
+       lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
+       preloader_console_init();
+
+       ddr_init(&dram_64mb);
+
+       /*
+        * NAND initialization is done by nand_init(),
+        * here just enable NAND SLC clocks
+        */
+       lpc32xx_slc_nand_init();
+}
+
+u32 spl_boot_device(void)
+{
+       return BOOT_DEVICE_NAND;
+}
index 56d719f..7246da5 100644 (file)
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_DEVKIT3250=y
+CONFIG_SPL=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_DM=y
index b8218b5..cc6a53e 100644 (file)
@@ -21,7 +21,9 @@
 
 #define CONFIG_SYS_ICACHE_OFF
 #define CONFIG_SYS_DCACHE_OFF
+#if !defined(CONFIG_SPL_BUILD)
 #define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
 #define CONFIG_BOARD_EARLY_INIT_F
 
 /*
 #define CONFIG_BOOTARGS                        "console=ttyS0,115200n8"
 #define CONFIG_LOADADDR                        0x80008000
 
+/*
+ * SPL specific defines
+ */
+/* SPL will be executed at offset 0 */
+#define CONFIG_SPL_TEXT_BASE           0x00000000
+
+/* SPL will use SRAM as stack */
+#define CONFIG_SPL_STACK               0x0000FFF8
+#define CONFIG_SPL_BOARD_INIT
+
+/* Use the framework and generic lib */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+
+/* SPL will use serial */
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+/* SPL loads an image from NAND */
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_NAND_RAW_ONLY
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_DRIVERS
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE     0x20000
+#define CONFIG_SYS_NAND_PAGE_SIZE      0x800
+#define CONFIG_SYS_NAND_ECCSIZE                0x100
+#define CONFIG_SYS_NAND_OOBSIZE                64
+#define CONFIG_SYS_NAND_ECCPOS         { 40, 41, 42, 43, 44, 45, 46, 47, \
+                                         48, 49, 50, 51, 52, 53, 54, 55, \
+                                         56, 57, 58, 59, 60, 61, 62, 63, }
+#define CONFIG_SYS_NAND_ECCBYTES       3
+#define CONFIG_SYS_NAND_PAGE_COUNT     64
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS  NAND_LARGE_BADBLOCK_POS
+
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_NAND_SOFTECC
+
+#define CONFIG_SPL_MAX_SIZE            0x20000
+#define CONFIG_SPL_PAD_TO              CONFIG_SPL_MAX_SIZE
+
+/* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS    0x40000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE    0x60000
+
+#define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_DST     CONFIG_SYS_TEXT_BASE
+
+/* See common/spl/spl.c  spl_set_header_raw_uboot() */
+#define CONFIG_SYS_MONITOR_LEN         CONFIG_SYS_NAND_U_BOOT_SIZE
+
 /*
  * Include SoC specific configuration
  */