ARM: armv7 fix spelling of SCTRL

SCTLR is the abbreviation of System Control Register, so we should
use SCTLR but not SCTRL.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>

diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c
index 01cdb7ee76b7f13aaeb1c396e9f7a5e0829fbeeb..c56417dd2f1ec81d8fa1088d8c12fc0aaf6c3848 100644 (file)
--- a/arch/arm/cpu/armv7/cpu.c
+++ b/arch/arm/cpu/armv7/cpu.c
@@ -53,7 +53,7 @@ int cleanup_before_linux(void)
         * After D-cache is flushed and before it is disabled there may
         * be some new valid entries brought into the cache. We are sure
         * that these lines are not dirty and will not affect our execution.
-        * (because unwinding the call-stack and setting a bit in CP15 SCTRL
+        * (because unwinding the call-stack and setting a bit in CP15 SCTLR
         * is all we did during this. We have not pushed anything on to the
         * stack. Neither have we affected any static data)
         * So just invalidate the entire d-cache again to avoid coherency

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index fdc05b942f15bb80415c295faba6832e689d8b01..70048c10aee6736117e078931b75c4b6ba7756a5 100644 (file)
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -52,10 +52,10 @@ reset:
  * Continue to use ROM code vector only in OMAP4 spl)
  */
 #if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
-       /* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */
-       mrc     p15, 0, r0, c1, c0, 0   @ Read CP15 SCTRL Register
+       /* Set V=0 in CP15 SCTLR register - for VBAR to point to vector */
+       mrc     p15, 0, r0, c1, c0, 0   @ Read CP15 SCTLR Register
        bic     r0, #CR_V               @ V = 0
-       mcr     p15, 0, r0, c1, c0, 0   @ Write CP15 SCTRL Register
+       mcr     p15, 0, r0, c1, c0, 0   @ Write CP15 SCTLR Register
 
        /* Set vector address in CP15 VBAR register */
        ldr     r0, =_start