x86: bayleybay: Configure PCI IRQ
authorBin Meng <bmeng.cn@gmail.com>
Thu, 30 Jul 2015 10:49:18 +0000 (03:49 -0700)
committerLothar Waßmann <LW@KARO-electronics.de>
Thu, 10 Sep 2015 06:00:50 +0000 (08:00 +0200)
Add PCI IRQ routing information in the board device tree and enable
writing PIRQ routing table and MP table.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
arch/x86/cpu/baytrail/valleyview.c
arch/x86/dts/bayleybay.dts
configs/bayleybay_defconfig
include/configs/bayleybay.h

index 9915da5..d8d2b8d 100644 (file)
@@ -7,6 +7,7 @@
 #include <common.h>
 #include <mmc.h>
 #include <pci_ids.h>
+#include <asm/irq.h>
 #include <asm/post.h>
 
 static struct pci_device_id mmc_supported[] = {
@@ -35,3 +36,10 @@ int arch_cpu_init(void)
 
        return 0;
 }
+
+int arch_misc_init(void)
+{
+       pirq_init();
+
+       return 0;
+}
index cbbdee2..9f8fa70 100644 (file)
@@ -7,6 +7,7 @@
 /dts-v1/;
 
 #include <dt-bindings/gpio/x86-gpio.h>
+#include <dt-bindings/interrupt-router/intel-irq.h>
 
 /include/ "skeleton.dtsi"
 /include/ "serial.dtsi"
                ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
                          0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
                          0x01000000 0x0 0x2000 0x2000 0 0xe000>;
+
+               irq-router@1f,0 {
+                       reg = <0x0000f800 0 0 0 0>;
+                       compatible = "intel,irq-router";
+                       intel,pirq-config = "ibase";
+                       intel,ibase-offset = <0x50>;
+                       intel,pirq-link = <8 8>;
+                       intel,pirq-mask = <0xdee0>;
+                       intel,pirq-routing = <
+                               /* BayTrail PCI devices */
+                               PCI_BDF(0, 2, 0) INTA PIRQA
+                               PCI_BDF(0, 3, 0) INTA PIRQA
+                               PCI_BDF(0, 16, 0) INTA PIRQA
+                               PCI_BDF(0, 17, 0) INTA PIRQA
+                               PCI_BDF(0, 18, 0) INTA PIRQA
+                               PCI_BDF(0, 19, 0) INTA PIRQA
+                               PCI_BDF(0, 20, 0) INTA PIRQA
+                               PCI_BDF(0, 21, 0) INTA PIRQA
+                               PCI_BDF(0, 22, 0) INTA PIRQA
+                               PCI_BDF(0, 23, 0) INTA PIRQA
+                               PCI_BDF(0, 24, 0) INTA PIRQA
+                               PCI_BDF(0, 24, 1) INTC PIRQC
+                               PCI_BDF(0, 24, 2) INTD PIRQD
+                               PCI_BDF(0, 24, 3) INTB PIRQB
+                               PCI_BDF(0, 24, 4) INTA PIRQA
+                               PCI_BDF(0, 24, 5) INTC PIRQC
+                               PCI_BDF(0, 24, 6) INTD PIRQD
+                               PCI_BDF(0, 24, 7) INTB PIRQB
+                               PCI_BDF(0, 26, 0) INTA PIRQA
+                               PCI_BDF(0, 27, 0) INTA PIRQA
+                               PCI_BDF(0, 28, 0) INTA PIRQA
+                               PCI_BDF(0, 28, 1) INTB PIRQB
+                               PCI_BDF(0, 28, 2) INTC PIRQC
+                               PCI_BDF(0, 28, 3) INTD PIRQD
+                               PCI_BDF(0, 29, 0) INTA PIRQA
+                               PCI_BDF(0, 30, 0) INTA PIRQA
+                               PCI_BDF(0, 30, 1) INTD PIRQD
+                               PCI_BDF(0, 30, 2) INTB PIRQB
+                               PCI_BDF(0, 30, 3) INTC PIRQC
+                               PCI_BDF(0, 30, 4) INTD PIRQD
+                               PCI_BDF(0, 30, 5) INTB PIRQB
+                               PCI_BDF(0, 31, 3) INTB PIRQB
+
+                               /* PCIe root ports downstream interrupts */
+                               PCI_BDF(1, 0, 0) INTA PIRQA
+                               PCI_BDF(1, 0, 0) INTB PIRQB
+                               PCI_BDF(1, 0, 0) INTC PIRQC
+                               PCI_BDF(1, 0, 0) INTD PIRQD
+                               PCI_BDF(2, 0, 0) INTA PIRQB
+                               PCI_BDF(2, 0, 0) INTB PIRQC
+                               PCI_BDF(2, 0, 0) INTC PIRQD
+                               PCI_BDF(2, 0, 0) INTD PIRQA
+                               PCI_BDF(3, 0, 0) INTA PIRQC
+                               PCI_BDF(3, 0, 0) INTB PIRQD
+                               PCI_BDF(3, 0, 0) INTC PIRQA
+                               PCI_BDF(3, 0, 0) INTD PIRQB
+                               PCI_BDF(4, 0, 0) INTA PIRQD
+                               PCI_BDF(4, 0, 0) INTB PIRQA
+                               PCI_BDF(4, 0, 0) INTC PIRQB
+                               PCI_BDF(4, 0, 0) INTD PIRQC
+                       >;
+               };
        };
 
        microcode {
index e10e86a..7f92ead 100644 (file)
@@ -5,6 +5,8 @@ CONFIG_TARGET_BAYLEYBAY=y
 CONFIG_HAVE_INTEL_ME=y
 CONFIG_SMP=y
 CONFIG_HAVE_VGA_BIOS=y
+CONFIG_GENERATE_PIRQ_TABLE=y
+CONFIG_GENERATE_MP_TABLE=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
index cc95aec..740166a 100644 (file)
@@ -14,6 +14,7 @@
 #include <configs/x86-common.h>
 
 #define CONFIG_SYS_MONITOR_LEN         (1 << 20)
+#define CONFIG_ARCH_MISC_INIT
 
 #define CONFIG_X86_SERIAL