]> git.kernelconcepts.de Git - karo-tx-uboot.git/commitdiff
vf610: Add I2C support for Vybrid VF610 platform
authorAlison Wang <b18965@freescale.com>
Mon, 17 Jun 2013 07:30:38 +0000 (15:30 +0800)
committerHeiko Schocher <hs@denx.de>
Tue, 23 Jul 2013 06:34:57 +0000 (08:34 +0200)
This patch adds I2C support for Vybrid VF610 platform and adds
I2C0 support to VF610TWR board.

Signed-off-by: Alison Wang <b18965@freescale.com>
arch/arm/cpu/armv7/vf610/generic.c
arch/arm/include/asm/arch-vf610/clock.h
arch/arm/include/asm/arch-vf610/crm_regs.h
arch/arm/include/asm/arch-vf610/imx-regs.h
arch/arm/include/asm/arch-vf610/iomux-vf610.h
board/freescale/vf610twr/vf610twr.c
include/configs/vf610twr.h

index 87f2a8642df55838998c4b65d223521da2651b6c..f6ef495382430907e3763df9369c053779ab030d 100644 (file)
@@ -204,6 +204,11 @@ u32 get_fec_clk(void)
        return freq;
 }
 
+static u32 get_i2c_clk(void)
+{
+       return get_ipg_clk();
+}
+
 unsigned int mxc_get_clock(enum mxc_clock clk)
 {
        switch (clk) {
@@ -219,6 +224,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
                return get_sdhc_clk();
        case MXC_FEC_CLK:
                return get_fec_clk();
+       case MXC_I2C_CLK:
+               return get_i2c_clk();
        default:
                break;
        }
index 04e418cf843b22c3ea6b74858ed4c0bd7bbbd897..3cbae0b829f780682250ea104f2467d251feb41b 100644 (file)
@@ -29,6 +29,7 @@ enum mxc_clock {
        MXC_UART_CLK,
        MXC_ESDHC_CLK,
        MXC_FEC_CLK,
+       MXC_I2C_CLK,
 };
 
 void enable_ocotp_clk(unsigned char enable);
index e3f703dc832da925ed9516fd64d004baa875d28a..6a67eb048c28deb0a66ea9362c89d16b02f9433d 100644 (file)
@@ -190,6 +190,7 @@ struct anadig_reg {
 #define CCM_CCGR4_WKUP_CTRL_MASK               (0x3 << 20)
 #define CCM_CCGR4_CCM_CTRL_MASK                        (0x3 << 22)
 #define CCM_CCGR4_GPC_CTRL_MASK                        (0x3 << 24)
+#define CCM_CCGR4_I2C0_CTRL_MASK               (0x3 << 12)
 #define CCM_CCGR6_OCOTP_CTRL_MASK              (0x3 << 10)
 #define CCM_CCGR6_DDRMC_CTRL_MASK              (0x3 << 28)
 #define CCM_CCGR7_SDHC1_CTRL_MASK              (0x3 << 4)
index c9df32a21d7f419ee60ce9d100a827e1ac30d9d9..742e20a60680e9f1bca046fbc4dfb9dba01583d8 100644 (file)
 #define CONFIG_IOMUX_SHARE_CONF_REG
 
 #define FEC_QUIRK_ENET_MAC
+#define I2C_QUIRK_REG
 
 /* MSCM interrupt rounter */
 #define MSCM_IRSPRC_CP0_EN                             1
index 1c728fa6b727d86ace37deec0c8410c36fe268ba..7aeadce38001d3e8a4dce216f8a77e019300583c 100644 (file)
@@ -30,6 +30,8 @@
 #define VF610_ENET_PAD_CTRL    (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \
                                PAD_CTL_OBE_IBE_ENABLE)
 #define VF610_DDR_PAD_CTRL     PAD_CTL_DSE_25ohm
+#define VF610_I2C_PAD_CTRL     (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \
+                               PAD_CTL_SPEED_HIGH | PAD_CTL_OBE_IBE_ENABLE)
 
 enum {
        VF610_PAD_PTA6__RMII0_CLKIN             = IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL),
@@ -50,6 +52,8 @@ enum {
        VF610_PAD_PTA27__ESDHC1_DAT1            = IOMUX_PAD(0x0044, 0x0044, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
        VF610_PAD_PTA28__ESDHC1_DAT2            = IOMUX_PAD(0x0048, 0x0048, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
        VF610_PAD_PTA29__ESDHC1_DAT3            = IOMUX_PAD(0x004c, 0x004c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
+       VF610_PAD_PTB14__I2C0_SCL               = IOMUX_PAD(0x0090, 0x0090, 2, 0x033c, 1, VF610_I2C_PAD_CTRL),
+       VF610_PAD_PTB15__I2C0_SDA               = IOMUX_PAD(0x0094, 0x0094, 2, 0x0340, 1, VF610_I2C_PAD_CTRL),
        VF610_PAD_DDR_A15__DDR_A_15             = IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
        VF610_PAD_DDR_A14__DDR_A_14             = IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
        VF610_PAD_DDR_A13__DDR_A_13             = IOMUX_PAD(0x0228, 0x0228, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
index f14df8b6e19913a07b16777b3f53b2dd9fb59c1b..391f97e41726fc369c32f81e01686c6d017f5a75 100644 (file)
@@ -27,6 +27,7 @@
 #include <fsl_esdhc.h>
 #include <miiphy.h>
 #include <netdev.h>
+#include <i2c.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -280,6 +281,16 @@ static void setup_iomux_enet(void)
        imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
 }
 
+static void setup_iomux_i2c(void)
+{
+       static const iomux_v3_cfg_t i2c0_pads[] = {
+               VF610_PAD_PTB14__I2C0_SCL,
+               VF610_PAD_PTB15__I2C0_SDA,
+       };
+
+       imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads));
+}
+
 #ifdef CONFIG_FSL_ESDHC
 struct fsl_esdhc_cfg esdhc_cfg[1] = {
        {ESDHC1_BASE_ADDR},
@@ -328,7 +339,7 @@ static void clock_init(void)
                CCM_CCGR3_ANADIG_CTRL_MASK);
        clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
                CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
-               CCM_CCGR4_GPC_CTRL_MASK);
+               CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK);
        clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
                CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
        clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
@@ -387,6 +398,7 @@ int board_early_init_f(void)
 
        setup_iomux_uart();
        setup_iomux_enet();
+       setup_iomux_i2c();
 
        return 0;
 }
index 5012fc81808105b679dc4f8895624c7a00fd24ab..9aba5bc9a540dd1ec5e84d6c0b0d43f2633e06f1 100644 (file)
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_MICREL
 
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_BASE            I2C0_BASE_ADDR
+#define CONFIG_SYS_I2C_SPEED           100000
+
 #define CONFIG_BOOTDELAY               3
 
 #define CONFIG_LOADADDR                        0x82000000