Merge branch 'tx6-bugfix'
authorLothar Waßmann <LW@KARO-electronics.de>
Mon, 4 Jul 2016 12:49:53 +0000 (14:49 +0200)
committerLothar Waßmann <LW@KARO-electronics.de>
Mon, 4 Jul 2016 12:49:53 +0000 (14:49 +0200)
71 files changed:
board/karo/tx6/Kconfig
board/karo/tx6/flash.c
board/karo/tx6/pmic.c
board/karo/tx6/tx6qdl.c
board/karo/tx6/tx6ul.c
configs/tx6q-1020_defconfig
configs/tx6q-1020_mfg_defconfig
configs/tx6q-1020_noenv_defconfig
configs/tx6q-1020_sec_defconfig
configs/tx6q-1036_defconfig
configs/tx6q-1036_mfg_defconfig
configs/tx6q-1036_noenv_defconfig
configs/tx6q-1036_sec_defconfig
configs/tx6q-10x0_defconfig
configs/tx6q-10x0_mfg_defconfig
configs/tx6q-10x0_noenv_defconfig
configs/tx6q-10x0_sec_defconfig
configs/tx6q-11x0_defconfig
configs/tx6q-11x0_mfg_defconfig
configs/tx6q-11x0_noenv_defconfig
configs/tx6q-11x0_sec_defconfig
configs/tx6qp-8037_defconfig
configs/tx6qp-8037_mfg_defconfig
configs/tx6qp-8037_noenv_defconfig
configs/tx6qp-8037_sec_defconfig
configs/tx6s-8034_defconfig
configs/tx6s-8034_mfg_defconfig
configs/tx6s-8034_noenv_defconfig
configs/tx6s-8034_sec_defconfig
configs/tx6s-8035_defconfig
configs/tx6s-8035_mfg_defconfig
configs/tx6s-8035_noenv_defconfig
configs/tx6s-8035_sec_defconfig
configs/tx6s-8134_defconfig [moved from configs/tx6u-8011_defconfig with 84% similarity]
configs/tx6s-8134_mfg_defconfig [moved from configs/tx6u-8011_mfg_defconfig with 84% similarity]
configs/tx6s-8134_noenv_defconfig [moved from configs/tx6u-8011_noenv_defconfig with 84% similarity]
configs/tx6s-8134_sec_defconfig [moved from configs/tx6u-8111_sec_defconfig with 89% similarity]
configs/tx6s-8135_defconfig [new file with mode: 0644]
configs/tx6s-8135_mfg_defconfig [new file with mode: 0644]
configs/tx6s-8135_noenv_defconfig [new file with mode: 0644]
configs/tx6s-8135_sec_defconfig [new file with mode: 0644]
configs/tx6u-8012_defconfig
configs/tx6u-8012_mfg_defconfig
configs/tx6u-8012_noenv_defconfig
configs/tx6u-8012_sec_defconfig
configs/tx6u-8033_defconfig
configs/tx6u-8033_mfg_defconfig
configs/tx6u-8033_noenv_defconfig
configs/tx6u-8033_sec_defconfig
configs/tx6u-80x0_defconfig
configs/tx6u-80x0_mfg_defconfig
configs/tx6u-80x0_noenv_defconfig
configs/tx6u-80x0_sec_defconfig
configs/tx6u-8133_defconfig [moved from configs/tx6u-8111_defconfig with 74% similarity]
configs/tx6u-8133_mfg_defconfig [moved from configs/tx6u-8111_mfg_defconfig with 74% similarity]
configs/tx6u-8133_noenv_defconfig [moved from configs/tx6u-8111_noenv_defconfig with 74% similarity]
configs/tx6u-8133_sec_defconfig [moved from configs/tx6u-8011_sec_defconfig with 74% similarity]
configs/tx6u-81x0_defconfig
configs/tx6u-81x0_mfg_defconfig
configs/tx6u-81x0_noenv_defconfig
configs/tx6u-81x0_sec_defconfig
configs/tx6ul-0010_defconfig
configs/tx6ul-0010_mfg_defconfig
configs/tx6ul-0010_noenv_defconfig
configs/tx6ul-0010_sec_defconfig
configs/tx6ul-0011_defconfig
configs/tx6ul-0011_mfg_defconfig
configs/tx6ul-0011_noenv_defconfig
configs/tx6ul-0011_sec_defconfig
drivers/i2c/Kconfig
include/configs/tx6.h

index fbf1d2a..1121891 100644 (file)
@@ -54,6 +54,8 @@ config TX6_EMMC
 config TX6UL
        bool
        select SOC_MX6UL
+       select SYS_I2C
+       select SYS_I2C_SOFT
        select SYS_SDRAM_BUS_WIDTH_16
 
 config TX6QP
@@ -77,100 +79,56 @@ config SYS_SDRAM_CHIP_SIZE
 choice
        prompt "TX6 module variant"
 
-config TARGET_TX6Q_1020
-       bool "TX6Q-1020"
+config TARGET_TX6Q_NAND
+       bool "TX6Q modules with NAND flash (TX6Q-1030/TX6Q-1130)"
        select SOC_MX6Q
        select SYS_I2C
        select SYS_I2C_MXC
-       select TX6_EMMC
 
-config TARGET_TX6Q_1036
-       bool "TX6Q-1036"
+config TARGET_TX6Q_EMMC
+       bool "TX6Q modules with eMMC (TX6Q-1020/TX6Q-1036)"
        select SOC_MX6Q
        select SYS_I2C
        select SYS_I2C_MXC
        select TX6_EMMC
 
-config TARGET_TX6Q_10X0
-       bool "TX6Q-1010 and TX6Q-1030"
-       select SOC_MX6Q
-       select SYS_I2C
-       select SYS_I2C_MXC
-
-config TARGET_TX6Q_11X0
-       bool "TX6Q-1110 and TX6Q-1130"
-       select SOC_MX6Q
-       select SYS_I2C
-       select SYS_I2C_MXC
-       select SYS_LVDS_IF
-       
-config TARGET_TX6S_8034
-       bool "TX6S-8034"
+config TARGET_TX6S_NAND
+       bool "TX6S modules with NAND flash (TX6S-8034/TX6S-8134)"
        select SOC_MX6S
        select SYS_I2C
        select SYS_I2C_MXC
-       select SYS_SDRAM_BUS_WIDTH_16
 
-config TARGET_TX6S_8035
-       bool "TX6S-8035"
+config TARGET_TX6S_EMMC
+       bool "TX6S modules with eMMC (TX6S-8035/TX6S-8135)"
        select SOC_MX6S
        select SYS_I2C
        select SYS_I2C_MXC
-       select SYS_SDRAM_BUS_WIDTH_32
        select TX6_EMMC
 
-config TARGET_TX6U_8011
-       bool "TX6U-8011"
-       select SOC_MX6DL
-       select SYS_I2C
-       select SYS_I2C_MXC
-       select SYS_SDRAM_BUS_WIDTH_32
-
-config TARGET_TX6U_8012
-       bool "TX6U-8012"
+config TARGET_TX6U_NAND
+       bool "TX6U (i.MX6DL) modules with NAND flash (TX6U-8030/TX6U-8032)"
        select SOC_MX6DL
        select SYS_I2C
        select SYS_I2C_MXC
 
-config TARGET_TX6U_8033
-       bool "TX6U-8033"
+config TARGET_TX6U_EMMC
+       bool "TX6U (i.MX6DL) modules with eMMC (TX6U-8033/TX6U-8133)"
        select SOC_MX6DL
        select SYS_I2C
        select SYS_I2C_MXC
        select TX6_EMMC
 
-config TARGET_TX6U_80X0
-       bool "TX6U-8010 and TX6U-8030"
-       select SOC_MX6DL
-       select SYS_I2C
-       select SYS_I2C_MXC
-
-config TARGET_TX6U_8111
-       bool "TX6U-8111"
-       select SOC_MX6DL
-       select SYS_I2C
-       select SYS_I2C_MXC
-       select SYS_LVDS_IF
-       select SYS_SDRAM_BUS_WIDTH_32
-
-config TARGET_TX6U_81X0
-       bool "TX6U-8110 and TX6U-8130"
-       select SOC_MX6DL
-       select SYS_I2C
-       select SYS_I2C_MXC
-       select SYS_LVDS_IF
-
-config TARGET_TX6UL_0010
-       bool "TX6U-0010"
+config TARGET_TX6UL_NAND
+       bool "TXUL (i.MX6UL) modules with NAND flash (TXUL-5010)"
        select TX6UL
 
-config TARGET_TX6UL_0011
-       bool "TX6U-0011"
+config TARGET_TX6UL_EMMC
+       bool "TXUL (i.MX6UL) modules with eMMC (TXUL-5011)"
        select TX6UL
        select TX6_EMMC
 
-config TARGET_TX6QP_8037
-       bool "TX6QP-8037"
+config TARGET_TX6QP_EMMC
+       bool "TX6Q modules with i.MX6Q+ and eMMC (TX6QP-8037)"
        select SOC_MX6Q
        select SYS_I2C
        select SYS_I2C_MXC
index c46d28b..dcd9416 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2012-2015 Lothar Waßmann <LW@KARO-electronics.de>
+ * Copyright (C) 2012-2016 Lothar Waßmann <LW@KARO-electronics.de>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -365,9 +365,9 @@ static int tx6_prog_uboot(void *addr, int start_block, int skip,
        nand_erase_options_t erase_opts = { 0, };
        size_t actual;
        size_t prg_length = max_len - skip * mtd->erasesize;
-       int prg_start = (start_block + skip) * mtd->erasesize;
+       int prg_start = start_block * mtd->erasesize;
 
-       erase_opts.offset = start_block * mtd->erasesize;
+       erase_opts.offset = (start_block - skip) * mtd->erasesize;
        erase_opts.length = max_len;
        erase_opts.quiet = 1;
 
@@ -676,7 +676,7 @@ int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
        }
 
        printf("Programming U-Boot image from %p to block %lu @ %08llx\n",
-               buf, fw1_start_block, (u64)fw1_start_block * mtd->erasesize);
+               addr, fw1_start_block, (u64)fw1_start_block * mtd->erasesize);
        ret = tx6_prog_uboot(addr, fw1_start_block, fw1_skip, size,
                        max_len1);
 
index 75a0bf9..e670b6a 100644 (file)
@@ -37,33 +37,33 @@ static struct {
 #endif
 };
 
-int tx6_pmic_init(int addr, struct pmic_regs *regs, size_t num_regs)
+int tx6_pmic_init(int i2c_addr, struct pmic_regs *regs, size_t num_regs)
 {
        int ret = -ENODEV;
        int i;
+       const char *pmic = "N/A";
 
        printf("PMIC: ");
 
-       debug("Probing for I2C dev 0x%02x\n", addr);
        for (i = 0; i < ARRAY_SIZE(i2c_addrs); i++) {
-               u8 i2c_addr = i2c_addrs[i].addr;
 
-               if (i2c_addr != addr)
-                       continue;
-
-               debug("Probing for I2C dev 0x%02x\n", i2c_addr);
-               ret = i2c_probe(i2c_addr);
-               if (ret == 0) {
-                       debug("Initializing PMIC at I2C addr 0x%02x\n", i2c_addr);
-                       ret = i2c_addrs[i].init(i2c_addr, regs, num_regs);
+               if (i2c_addrs[i].addr == i2c_addr) {
+                       pmic = i2c_addrs[i].name;
                        break;
                }
        }
-       printf("%s\n", i == ARRAY_SIZE(i2c_addrs) ? "N/A" : i2c_addrs[i].name);
+       printf("%s\n", pmic);
+
+       debug("Probing for I2C dev 0x%02x\n", i2c_addr);
+       ret = i2c_probe(i2c_addr);
+       if (ret == 0) {
+               debug("Initializing PMIC at I2C addr 0x%02x\n", i2c_addr);
+               ret = i2c_addrs[i].init(i2c_addr, regs, num_regs);
+       }
        return ret;
 }
 #else
-int tx6_pmic_init(int addr, struct pmic_regs *regs, size_t num_regs)
+int tx6_pmic_init(int i2c_addr, struct pmic_regs *regs, size_t num_regs)
 {
        printf("PMIC: N/A\n");
        return 0;
index d2d1e83..d183db6 100644 (file)
@@ -64,68 +64,85 @@ char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
 char __csf_data[0] __attribute__((section(".__csf_data")));
 #endif
 
+#define TX6_DEFAULT_PAD_CTRL   MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |      \
+                                       PAD_CTL_SPEED_MED |             \
+                                       PAD_CTL_DSE_40ohm |             \
+                                       PAD_CTL_SRE_FAST)
+#define TX6_FEC_PAD_CTRL       MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |      \
+                                       PAD_CTL_SPEED_MED |             \
+                                       PAD_CTL_DSE_40ohm |             \
+                                       PAD_CTL_SRE_FAST)
+#define TX6_GPIO_PAD_CTRL      MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |       \
+                                       PAD_CTL_SPEED_MED |             \
+                                       PAD_CTL_DSE_34ohm |             \
+                                       PAD_CTL_SRE_FAST)
+#define TX6_I2C_PAD_CTRL       MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |       \
+                                       PAD_CTL_HYS |                   \
+                                       PAD_CTL_SPEED_LOW |             \
+                                       PAD_CTL_DSE_40ohm |             \
+                                       PAD_CTL_SRE_SLOW)
+
 static const iomux_v3_cfg_t const tx6qdl_pads[] = {
        /* RESET_OUT */
-       MX6_PAD_GPIO_17__GPIO7_IO12,
+       MX6_PAD_GPIO_17__GPIO7_IO12 | TX6_DEFAULT_PAD_CTRL,
 
        /* UART pads */
 #if CONFIG_MXC_UART_BASE == UART1_BASE
-       MX6_PAD_SD3_DAT7__UART1_TX_DATA,
-       MX6_PAD_SD3_DAT6__UART1_RX_DATA,
-       MX6_PAD_SD3_DAT1__UART1_RTS_B,
-       MX6_PAD_SD3_DAT0__UART1_CTS_B,
+       MX6_PAD_SD3_DAT7__UART1_TX_DATA | TX6_DEFAULT_PAD_CTRL,
+       MX6_PAD_SD3_DAT6__UART1_RX_DATA | TX6_DEFAULT_PAD_CTRL,
+       MX6_PAD_SD3_DAT1__UART1_RTS_B | TX6_DEFAULT_PAD_CTRL,
+       MX6_PAD_SD3_DAT0__UART1_CTS_B | TX6_DEFAULT_PAD_CTRL,
 #endif
 #if CONFIG_MXC_UART_BASE == UART2_BASE
-       MX6_PAD_SD4_DAT4__UART2_RX_DATA,
-       MX6_PAD_SD4_DAT7__UART2_TX_DATA,
-       MX6_PAD_SD4_DAT5__UART2_RTS_B,
-       MX6_PAD_SD4_DAT6__UART2_CTS_B,
+       MX6_PAD_SD4_DAT4__UART2_RX_DATA | TX6_DEFAULT_PAD_CTRL,
+       MX6_PAD_SD4_DAT7__UART2_TX_DATA | TX6_DEFAULT_PAD_CTRL,
+       MX6_PAD_SD4_DAT5__UART2_RTS_B | TX6_DEFAULT_PAD_CTRL,
+       MX6_PAD_SD4_DAT6__UART2_CTS_B | TX6_DEFAULT_PAD_CTRL,
 #endif
 #if CONFIG_MXC_UART_BASE == UART3_BASE
-       MX6_PAD_EIM_D24__UART3_TX_DATA,
-       MX6_PAD_EIM_D25__UART3_RX_DATA,
-       MX6_PAD_SD3_RST__UART3_RTS_B,
-       MX6_PAD_SD3_DAT3__UART3_CTS_B,
+       MX6_PAD_EIM_D24__UART3_TX_DATA | TX6_DEFAULT_PAD_CTRL,
+       MX6_PAD_EIM_D25__UART3_RX_DATA | TX6_DEFAULT_PAD_CTRL,
+       MX6_PAD_SD3_RST__UART3_RTS_B | TX6_DEFAULT_PAD_CTRL,
+       MX6_PAD_SD3_DAT3__UART3_CTS_B | TX6_DEFAULT_PAD_CTRL,
 #endif
        /* internal I2C */
-       MX6_PAD_EIM_D28__I2C1_SDA,
-       MX6_PAD_EIM_D21__I2C1_SCL,
+       MX6_PAD_EIM_D28__I2C1_SDA | TX6_DEFAULT_PAD_CTRL,
+       MX6_PAD_EIM_D21__I2C1_SCL | TX6_DEFAULT_PAD_CTRL,
 
        /* FEC PHY GPIO functions */
-       MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_CFG_SION, /* PHY POWER */
-       MX6_PAD_SD3_DAT2__GPIO7_IO06 | MUX_CFG_SION, /* PHY RESET */
-       MX6_PAD_SD3_DAT4__GPIO7_IO01, /* PHY INT */
+       MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_CFG_SION |
+                       TX6_DEFAULT_PAD_CTRL, /* PHY POWER */
+       MX6_PAD_SD3_DAT2__GPIO7_IO06 | MUX_CFG_SION |
+                       TX6_DEFAULT_PAD_CTRL, /* PHY RESET */
+       MX6_PAD_SD3_DAT4__GPIO7_IO01 | TX6_DEFAULT_PAD_CTRL, /* PHY INT */
 };
 
 static const iomux_v3_cfg_t const tx6qdl_fec_pads[] = {
        /* FEC functions */
-       MX6_PAD_ENET_MDC__ENET_MDC,
-       MX6_PAD_ENET_MDIO__ENET_MDIO,
-       MX6_PAD_GPIO_16__ENET_REF_CLK,
-       MX6_PAD_ENET_RX_ER__ENET_RX_ER,
-       MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
-       MX6_PAD_ENET_RXD1__ENET_RX_DATA1,
-       MX6_PAD_ENET_RXD0__ENET_RX_DATA0,
-       MX6_PAD_ENET_TX_EN__ENET_TX_EN,
-       MX6_PAD_ENET_TXD1__ENET_TX_DATA1,
-       MX6_PAD_ENET_TXD0__ENET_TX_DATA0,
+       MX6_PAD_ENET_MDC__ENET_MDC | TX6_FEC_PAD_CTRL,
+       MX6_PAD_ENET_MDIO__ENET_MDIO | TX6_FEC_PAD_CTRL,
+       MX6_PAD_GPIO_16__ENET_REF_CLK | TX6_FEC_PAD_CTRL,
+       MX6_PAD_ENET_RX_ER__ENET_RX_ER | TX6_FEC_PAD_CTRL,
+       MX6_PAD_ENET_CRS_DV__ENET_RX_EN | TX6_FEC_PAD_CTRL,
+       MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | TX6_FEC_PAD_CTRL,
+       MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | TX6_FEC_PAD_CTRL,
+       MX6_PAD_ENET_TX_EN__ENET_TX_EN | TX6_FEC_PAD_CTRL,
+       MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | TX6_FEC_PAD_CTRL,
+       MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | TX6_FEC_PAD_CTRL,
 };
 
-#define TX6_I2C_GPIO_PAD_CTRL  (PAD_CTL_PUS_22K_UP |   \
-                               PAD_CTL_SPEED_MED |     \
-                               PAD_CTL_DSE_34ohm |     \
-                               PAD_CTL_SRE_FAST)
-
 static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
        /* internal I2C */
-       MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_GPIO_PAD_CTRL),
-       MX6_PAD_EIM_D21__GPIO3_IO21 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_GPIO_PAD_CTRL),
+       MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_CFG_SION |
+                       TX6_GPIO_PAD_CTRL,
+       MX6_PAD_EIM_D21__GPIO3_IO21 | MUX_CFG_SION |
+                       TX6_GPIO_PAD_CTRL,
 };
 
 static const iomux_v3_cfg_t const tx6_i2c_pads[] = {
        /* internal I2C */
-       MX6_PAD_EIM_D28__I2C1_SDA,
-       MX6_PAD_EIM_D21__I2C1_SCL,
+       MX6_PAD_EIM_D28__I2C1_SDA | TX6_I2C_PAD_CTRL,
+       MX6_PAD_EIM_D21__I2C1_SCL | TX6_I2C_PAD_CTRL,
 };
 
 static const struct gpio const tx6qdl_gpios[] = {
@@ -545,43 +562,42 @@ void dram_init_banksize(void)
 }
 
 #ifdef CONFIG_FSL_ESDHC
-#define SD_PAD_CTRL (PAD_CTL_PUS_47K_UP |              \
-       PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |         \
-       PAD_CTL_SRE_FAST)
+#define SD_PAD_CTRL            MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |       \
+                               PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+                               PAD_CTL_SRE_FAST)
 
 static const iomux_v3_cfg_t mmc0_pads[] = {
-       MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
-       MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
-       MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
-       MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
-       MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
-       MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
+       MX6_PAD_SD1_CMD__SD1_CMD | SD_PAD_CTRL,
+       MX6_PAD_SD1_CLK__SD1_CLK | SD_PAD_CTRL,
+       MX6_PAD_SD1_DAT0__SD1_DATA0 | SD_PAD_CTRL,
+       MX6_PAD_SD1_DAT1__SD1_DATA1 | SD_PAD_CTRL,
+       MX6_PAD_SD1_DAT2__SD1_DATA2 | SD_PAD_CTRL,
+       MX6_PAD_SD1_DAT3__SD1_DATA3 | SD_PAD_CTRL,
        /* SD1 CD */
-       MX6_PAD_SD3_CMD__GPIO7_IO02,
+       MX6_PAD_SD3_CMD__GPIO7_IO02 | TX6_GPIO_PAD_CTRL,
 };
 
 static const iomux_v3_cfg_t mmc1_pads[] = {
-       MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
-       MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
-       MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
-       MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
-       MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
-       MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
+       MX6_PAD_SD2_CMD__SD2_CMD | SD_PAD_CTRL,
+       MX6_PAD_SD2_CLK__SD2_CLK | SD_PAD_CTRL,
+       MX6_PAD_SD2_DAT0__SD2_DATA0 | SD_PAD_CTRL,
+       MX6_PAD_SD2_DAT1__SD2_DATA1 | SD_PAD_CTRL,
+       MX6_PAD_SD2_DAT2__SD2_DATA2 | SD_PAD_CTRL,
+       MX6_PAD_SD2_DAT3__SD2_DATA3 | SD_PAD_CTRL,
        /* SD2 CD */
-       MX6_PAD_SD3_CLK__GPIO7_IO03,
+       MX6_PAD_SD3_CLK__GPIO7_IO03 | TX6_GPIO_PAD_CTRL,
 };
 
 #ifdef CONFIG_TX6_EMMC
 static const iomux_v3_cfg_t mmc3_pads[] = {
-       MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
-       MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
-       MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
-       MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
-       MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
-       MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
+       MX6_PAD_SD4_CMD__SD4_CMD | SD_PAD_CTRL,
+       MX6_PAD_SD4_CLK__SD4_CLK | SD_PAD_CTRL,
+       MX6_PAD_SD4_DAT0__SD4_DATA0 | SD_PAD_CTRL,
+       MX6_PAD_SD4_DAT1__SD4_DATA1 | SD_PAD_CTRL,
+       MX6_PAD_SD4_DAT2__SD4_DATA2 | SD_PAD_CTRL,
+       MX6_PAD_SD4_DAT3__SD4_DATA3 | SD_PAD_CTRL,
        /* eMMC RESET */
-       MX6_PAD_NANDF_ALE__SD4_RESET | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
-                                               PAD_CTL_DSE_40ohm),
+       MX6_PAD_NANDF_ALE__SD4_RESET | SD_PAD_CTRL,
 };
 #endif
 
@@ -772,27 +788,27 @@ void show_activity(int arg)
 
 static const iomux_v3_cfg_t stk5_pads[] = {
        /* SW controlled LED on STK5 baseboard */
-       MX6_PAD_EIM_A18__GPIO2_IO20,
+       MX6_PAD_EIM_A18__GPIO2_IO20 | TX6_GPIO_PAD_CTRL,
 
        /* I2C bus on DIMM pins 40/41 */
-       MX6_PAD_GPIO_6__I2C3_SDA,
-       MX6_PAD_GPIO_3__I2C3_SCL,
+       MX6_PAD_GPIO_6__I2C3_SDA | TX6_I2C_PAD_CTRL,
+       MX6_PAD_GPIO_3__I2C3_SCL | TX6_I2C_PAD_CTRL,
 
        /* TSC200x PEN IRQ */
-       MX6_PAD_EIM_D26__GPIO3_IO26,
+       MX6_PAD_EIM_D26__GPIO3_IO26 | TX6_GPIO_PAD_CTRL,
 
        /* EDT-FT5x06 Polytouch panel */
-       MX6_PAD_NANDF_CS2__GPIO6_IO15, /* IRQ */
-       MX6_PAD_EIM_A16__GPIO2_IO22, /* RESET */
-       MX6_PAD_EIM_A17__GPIO2_IO21, /* WAKE */
+       MX6_PAD_NANDF_CS2__GPIO6_IO15 | TX6_GPIO_PAD_CTRL, /* IRQ */
+       MX6_PAD_EIM_A16__GPIO2_IO22 | TX6_GPIO_PAD_CTRL, /* RESET */
+       MX6_PAD_EIM_A17__GPIO2_IO21 | TX6_GPIO_PAD_CTRL, /* WAKE */
 
        /* USBH1 */
-       MX6_PAD_EIM_D31__GPIO3_IO31, /* VBUSEN */
-       MX6_PAD_EIM_D30__GPIO3_IO30, /* OC */
+       MX6_PAD_EIM_D31__GPIO3_IO31 | TX6_GPIO_PAD_CTRL, /* VBUSEN */
+       MX6_PAD_EIM_D30__GPIO3_IO30 | TX6_GPIO_PAD_CTRL, /* OC */
        /* USBOTG */
-       MX6_PAD_EIM_D23__GPIO3_IO23, /* USBOTG ID */
-       MX6_PAD_GPIO_7__GPIO1_IO07, /* VBUSEN */
-       MX6_PAD_GPIO_8__GPIO1_IO08, /* OC */
+       MX6_PAD_EIM_D23__GPIO3_IO23 | TX6_GPIO_PAD_CTRL, /* USBOTG ID */
+       MX6_PAD_GPIO_7__GPIO1_IO07 | TX6_GPIO_PAD_CTRL, /* VBUSEN */
+       MX6_PAD_GPIO_8__GPIO1_IO08 | TX6_GPIO_PAD_CTRL, /* OC */
 };
 
 static const struct gpio stk5_gpios[] = {
@@ -1033,42 +1049,42 @@ void lcd_panel_disable(void)
 
 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
        /* LCD RESET */
-       MX6_PAD_EIM_D29__GPIO3_IO29,
+       MX6_PAD_EIM_D29__GPIO3_IO29 | TX6_GPIO_PAD_CTRL,
        /* LCD POWER_ENABLE */
-       MX6_PAD_EIM_EB3__GPIO2_IO31,
+       MX6_PAD_EIM_EB3__GPIO2_IO31 | TX6_GPIO_PAD_CTRL,
        /* LCD Backlight (PWM) */
-       MX6_PAD_GPIO_1__GPIO1_IO01,
+       MX6_PAD_GPIO_1__GPIO1_IO01 | TX6_GPIO_PAD_CTRL,
 
 #ifndef CONFIG_SYS_LVDS_IF
        /* Display */
-       MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
-       MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
-       MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
-       MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
-       MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
-       MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
-       MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
-       MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
-       MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
-       MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
-       MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
-       MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
-       MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
-       MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
-       MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
-       MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
-       MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
-       MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
-       MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
-       MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
-       MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
-       MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
-       MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
-       MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
-       MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* HSYNC */
-       MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* VSYNC */
-       MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
-       MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
+       MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | TX6_GPIO_PAD_CTRL,
+       MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | TX6_GPIO_PAD_CTRL,
+       MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | TX6_GPIO_PAD_CTRL,
+       MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | TX6_GPIO_PAD_CTRL,
+       MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | TX6_GPIO_PAD_CTRL,
+       MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | TX6_GPIO_PAD_CTRL,
+       MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | TX6_GPIO_PAD_CTRL,
+       MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | TX6_GPIO_PAD_CTRL,
+       MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | TX6_GPIO_PAD_CTRL,
+       MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | TX6_GPIO_PAD_CTRL,
+       MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | TX6_GPIO_PAD_CTRL,
+       MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | TX6_GPIO_PAD_CTRL,
+       MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | TX6_GPIO_PAD_CTRL,
+       MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | TX6_GPIO_PAD_CTRL,
+       MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | TX6_GPIO_PAD_CTRL,
+       MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | TX6_GPIO_PAD_CTRL,
+       MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | TX6_GPIO_PAD_CTRL,
+       MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | TX6_GPIO_PAD_CTRL,
+       MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | TX6_GPIO_PAD_CTRL,
+       MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | TX6_GPIO_PAD_CTRL,
+       MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | TX6_GPIO_PAD_CTRL,
+       MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | TX6_GPIO_PAD_CTRL,
+       MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | TX6_GPIO_PAD_CTRL,
+       MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | TX6_GPIO_PAD_CTRL,
+       MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | TX6_GPIO_PAD_CTRL, /* HSYNC */
+       MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | TX6_GPIO_PAD_CTRL, /* VSYNC */
+       MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | TX6_GPIO_PAD_CTRL, /* OE_ACD */
+       MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | TX6_GPIO_PAD_CTRL, /* LSCLK */
 #endif
 };
 
@@ -1095,7 +1111,6 @@ void lcd_ctrl_init(void *lcdbase)
        if (!lcd_enabled) {
                debug("LCD disabled\n");
                goto disable;
-               return;
        }
 
        if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
@@ -1103,7 +1118,6 @@ void lcd_ctrl_init(void *lcdbase)
                lcd_enabled = 0;
                setenv("splashimage", NULL);
                goto disable;
-               return;
        }
 
        karo_fdt_move_fdt();
@@ -1113,7 +1127,6 @@ void lcd_ctrl_init(void *lcdbase)
                debug("Disabling LCD\n");
                lcd_enabled = 0;
                goto disable;
-               return;
        }
        vm = video_mode;
        if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
@@ -1127,7 +1140,6 @@ void lcd_ctrl_init(void *lcdbase)
                                panel_info.vl_col, panel_info.vl_row);
                        lcd_enabled = 0;
                        goto disable;
-                       return;
                }
        }
        if (p->name != NULL)
@@ -1219,14 +1231,12 @@ void lcd_ctrl_init(void *lcdbase)
                }
                printf("\n");
                goto disable;
-               return;
        }
        if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
                printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
                        p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
                lcd_enabled = 0;
                goto disable;
-               return;
        }
        panel_info.vl_col = p->xres;
        panel_info.vl_row = p->yres;
@@ -1285,7 +1295,6 @@ void lcd_ctrl_init(void *lcdbase)
                printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
                        lcd_bus_width);
                goto disable;
-               return;
        }
        if (is_lvds()) {
                int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
@@ -1297,7 +1306,6 @@ void lcd_ctrl_init(void *lcdbase)
                        printf("No LVDS channel active\n");
                        lcd_enabled = 0;
                        goto disable;
-                       return;
                }
 
                gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
@@ -1368,7 +1376,8 @@ static void stk5v5_board_init(void)
                return;
        }
 
-       imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO4_IO21);
+       imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO4_IO21 |
+                       TX6_GPIO_PAD_CTRL);
 }
 
 static void tx6qdl_set_cpu_clock(void)
index 0fc9876..1817e27 100644 (file)
@@ -71,95 +71,102 @@ char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
 char __csf_data[0] __attribute__((section(".__csf_data")));
 #endif
 
+#define TX6UL_DEFAULT_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |      \
+                                       PAD_CTL_SPEED_MED |             \
+                                       PAD_CTL_DSE_40ohm |             \
+                                       PAD_CTL_SRE_FAST)
+#define TX6UL_I2C_PAD_CTRL     MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |       \
+                                       PAD_CTL_ODE |                   \
+                                       PAD_CTL_HYS |                   \
+                                       PAD_CTL_SPEED_LOW |             \
+                                       PAD_CTL_DSE_34ohm |             \
+                                       PAD_CTL_SRE_FAST)
+#define TX6UL_I2C_GPIO_PAD_CTRL        MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |       \
+                                       PAD_CTL_HYS |                   \
+                                       PAD_CTL_DSE_34ohm |             \
+                                       PAD_CTL_SPEED_MED)
+#define TX6UL_ENET_PAD_CTRL    MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH |       \
+                                       PAD_CTL_DSE_48ohm |             \
+                                       PAD_CTL_PUS_100K_UP |           \
+                                       PAD_CTL_SRE_FAST)
+#define TX6UL_GPIO_OUT_PAD_CTRL        MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |        \
+                                       PAD_CTL_DSE_60ohm |             \
+                                       PAD_CTL_SRE_SLOW)
+#define TX6UL_GPIO_IN_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |        \
+                                       PAD_CTL_PUS_47K_UP)
+
+
 static const iomux_v3_cfg_t const tx6ul_pads[] = {
        /* UART pads */
 #if CONFIG_MXC_UART_BASE == UART1_BASE
-       MX6_PAD_UART1_TX_DATA__UART1_DCE_TX,
-       MX6_PAD_UART1_RX_DATA__UART1_DCE_RX,
-       MX6_PAD_UART1_RTS_B__UART1_DCE_RTS,
-       MX6_PAD_UART1_CTS_B__UART1_DCE_CTS,
+       MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
+       MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
+       MX6_PAD_UART1_RTS_B__UART1_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
+       MX6_PAD_UART1_CTS_B__UART1_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
 #endif
 #if CONFIG_MXC_UART_BASE == UART2_BASE
-       MX6_PAD_UART2_TX_DATA__UART2_DCE_TX,
-       MX6_PAD_UART2_RX_DATA__UART2_DCE_RX,
-       MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS,
-       MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS,
+       MX6_PAD_UART2_TX_DATA__UART2_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
+       MX6_PAD_UART2_RX_DATA__UART2_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
+       MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
+       MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
 #endif
 #if CONFIG_MXC_UART_BASE == UART5_BASE
-       MX6_PAD_GPIO1_IO04__UART5_DCE_TX,
-       MX6_PAD_GPIO1_IO05__UART5_DCE_RX,
-       MX6_PAD_GPIO1_IO08__UART5_DCE_RTS,
-       MX6_PAD_GPIO1_IO09__UART5_DCE_CTS,
+       MX6_PAD_GPIO1_IO04__UART5_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
+       MX6_PAD_GPIO1_IO05__UART5_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
+       MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
+       MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
 #endif
-       /* internal I2C */
-       MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
-                       MUX_PAD_CTRL(PAD_CTL_DSE_240ohm), /* I2C SCL */
-       MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
-                       MUX_PAD_CTRL(PAD_CTL_DSE_240ohm | PAD_CTL_HYS |
-                       PAD_CTL_ODE), /* I2C SDA */
-
        /* FEC PHY GPIO functions */
-       MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_CFG_SION, /* PHY POWER */
-       MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 | MUX_CFG_SION, /* PHY RESET */
-       MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
-                                                       PAD_CTL_DSE_40ohm), /* PHY INT */
+       MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | TX6UL_GPIO_OUT_PAD_CTRL, /* PHY POWER */
+       MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 | TX6UL_GPIO_OUT_PAD_CTRL, /* PHY RESET */
+       MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 | TX6UL_GPIO_IN_PAD_CTRL, /* PHY INT */
 };
 
-#define TX6_ENET_PAD_CTRL      (PAD_CTL_SPEED_HIGH |   \
-                               PAD_CTL_DSE_48ohm |     \
-                               PAD_CTL_PUS_100K_UP |   \
-                               PAD_CTL_SRE_FAST)
-#define TX6_GPIO_OUT_PAD_CTRL  (PAD_CTL_SPEED_LOW |    \
-                               PAD_CTL_DSE_60ohm |     \
-                               PAD_CTL_SRE_SLOW)
-#define TX6_GPIO_IN_PAD_CTRL   (PAD_CTL_SPEED_LOW |    \
-                               PAD_CTL_PUS_47K_UP)
-
 static const iomux_v3_cfg_t const tx6ul_enet1_pads[] = {
        /* FEC functions */
        MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(PAD_CTL_DSE_48ohm |
                                PAD_CTL_SPEED_MED),
        MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |
-                               PAD_CTL_DSE_48ohm |
-                               PAD_CTL_SPEED_MED),
+                               PAD_CTL_DSE_48ohm | PAD_CTL_SPEED_MED),
        MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_CFG_SION |
                                MUX_PAD_CTRL(PAD_CTL_SPEED_MED |
-                               PAD_CTL_DSE_40ohm |
-                               PAD_CTL_SRE_FAST),
-       MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
-       MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
-       MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
-       MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
-       MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
-       MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
-       MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
+                               PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST),
+       MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | TX6UL_ENET_PAD_CTRL,
+       MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | TX6UL_ENET_PAD_CTRL,
+       MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | TX6UL_ENET_PAD_CTRL,
+       MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | TX6UL_ENET_PAD_CTRL,
+       MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | TX6UL_ENET_PAD_CTRL,
+       MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | TX6UL_ENET_PAD_CTRL,
+       MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | TX6UL_ENET_PAD_CTRL,
 };
 
 static const iomux_v3_cfg_t const tx6ul_enet2_pads[] = {
        MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_CFG_SION |
                                MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH |
-                               PAD_CTL_DSE_48ohm |
-                               PAD_CTL_SRE_FAST),
-       MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
-       MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
-       MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
-       MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
-       MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
-       MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
-       MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
+                               PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST),
+       MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | TX6UL_ENET_PAD_CTRL,
+       MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | TX6UL_ENET_PAD_CTRL,
+       MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | TX6UL_ENET_PAD_CTRL,
+       MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | TX6UL_ENET_PAD_CTRL,
+       MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | TX6UL_ENET_PAD_CTRL,
+       MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | TX6UL_ENET_PAD_CTRL,
+       MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | TX6UL_ENET_PAD_CTRL,
 };
 
-#define TX6_I2C_PAD_CTRL       (PAD_CTL_PUS_22K_UP |   \
-                               PAD_CTL_SPEED_MED |     \
-                               PAD_CTL_DSE_34ohm |     \
-                               PAD_CTL_SRE_FAST)
-
-static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
+static const iomux_v3_cfg_t const tx6ul_i2c_pads[] = {
        /* internal I2C */
        MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
-                       MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
+                       TX6UL_I2C_PAD_CTRL, /* I2C SCL */
        MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
-                       MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
+                       TX6UL_I2C_PAD_CTRL, /* I2C SDA */
+};
+
+static const iomux_v3_cfg_t const tx6ul_i2c_gpio_pads[] = {
+       /* internal I2C set up for I2C bus recovery */
+       MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
+                       TX6UL_I2C_PAD_CTRL, /* I2C SCL */
+       MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
+                       TX6UL_I2C_PAD_CTRL, /* I2C SDA */
 };
 
 static const struct gpio const tx6ul_gpios[] = {
@@ -184,67 +191,85 @@ static const struct gpio const tx6ul_fec2_gpios[] = {
 
 /* run with default environment */
 #if defined(TX6UL_I2C1_SCL_GPIO) && defined(TX6UL_I2C1_SDA_GPIO)
-static void tx6_i2c_recover(void)
+#define SCL_BANK       (TX6UL_I2C1_SCL_GPIO / 32)
+#define SDA_BANK       (TX6UL_I2C1_SDA_GPIO / 32)
+#define SCL_BIT                (1 << (TX6UL_I2C1_SCL_GPIO % 32))
+#define SDA_BIT                (1 << (TX6UL_I2C1_SDA_GPIO % 32))
+
+static void * const gpio_ports[] = {
+       (void *)GPIO1_BASE_ADDR,
+       (void *)GPIO2_BASE_ADDR,
+       (void *)GPIO3_BASE_ADDR,
+       (void *)GPIO4_BASE_ADDR,
+       (void *)GPIO5_BASE_ADDR,
+};
+
+static void tx6ul_i2c_recover(void)
 {
        int i;
        int bad = 0;
-#define SCL_BIT                (1 << (TX6UL_I2C1_SCL_GPIO % 32))
-#define SDA_BIT                (1 << (TX6UL_I2C1_SDA_GPIO % 32))
-#define I2C_GPIO_BASE  (GPIO1_BASE_ADDR + TX6UL_I2C1_SCL_GPIO / 32 * 0x4000)
+       struct gpio_regs *scl_regs = gpio_ports[SCL_BANK];
+       struct gpio_regs *sda_regs = gpio_ports[SDA_BANK];
 
-       if ((readl(I2C_GPIO_BASE + GPIO_PSR) &
-                       (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT))
+       if ((readl(&scl_regs->gpio_psr) & SCL_BIT) &&
+               (readl(&sda_regs->gpio_psr) & SDA_BIT))
                return;
 
        debug("Clearing I2C bus\n");
-       if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SCL_BIT)) {
+       if (!(readl(&scl_regs->gpio_psr) & SCL_BIT)) {
                printf("I2C SCL stuck LOW\n");
                bad++;
 
-               writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT,
-                       I2C_GPIO_BASE + GPIO_DR);
-               writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT,
-                       I2C_GPIO_BASE + GPIO_DIR);
+               setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
+               setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
+
+               imx_iomux_v3_setup_pad(MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 |
+                               MUX_CFG_SION | TX6UL_GPIO_OUT_PAD_CTRL);
        }
-       if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)) {
+       if (!(readl(&sda_regs->gpio_psr) & SDA_BIT)) {
                printf("I2C SDA stuck LOW\n");
                bad++;
 
-               writel(readl(I2C_GPIO_BASE + GPIO_DIR) & ~SDA_BIT,
-                       I2C_GPIO_BASE + GPIO_DIR);
-               writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT,
-                       I2C_GPIO_BASE + GPIO_DR);
-               writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT,
-                       I2C_GPIO_BASE + GPIO_DIR);
+               clrbits_le32(&sda_regs->gpio_dir, SDA_BIT);
+               setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
+               setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
+
+               imx_iomux_v3_setup_multiple_pads(tx6ul_i2c_gpio_pads,
+                                               ARRAY_SIZE(tx6ul_i2c_gpio_pads));
 
-               imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
-                                               ARRAY_SIZE(tx6_i2c_gpio_pads));
-               udelay(10);
+               udelay(5);
 
                for (i = 0; i < 18; i++) {
-                       u32 reg = readl(I2C_GPIO_BASE + GPIO_DR) ^ SCL_BIT;
+                       u32 reg = readl(&scl_regs->gpio_dr) ^ SCL_BIT;
 
                        debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
-                       writel(reg, I2C_GPIO_BASE + GPIO_DR);
-                       udelay(10);
-                       if (reg & SCL_BIT &&
-                               readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)
+                       writel(reg, &scl_regs->gpio_dr);
+                       udelay(5);
+                       if (reg & SCL_BIT) {
+                               if (readl(&sda_regs->gpio_psr) & SDA_BIT)
+                                       break;
+                               if (!(readl(&scl_regs->gpio_psr) & SCL_BIT))
+                                       break;
                                break;
+                       }
                }
        }
        if (bad) {
-               u32 reg = readl(I2C_GPIO_BASE + GPIO_PSR);
+               bool scl = !!(readl(&scl_regs->gpio_psr) & SCL_BIT);
+               bool sda = !!(readl(&sda_regs->gpio_psr) & SDA_BIT);
 
-               if ((reg & (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) {
+               if (scl && sda) {
                        printf("I2C bus recovery succeeded\n");
                } else {
-                       printf("I2C bus recovery FAILED: %08x:%08x\n", reg,
-                               SCL_BIT | SDA_BIT);
+                       printf("I2C bus recovery FAILED: SCL: %d SDA: %d\n",
+                               scl, sda);
                }
+               imx_iomux_v3_setup_multiple_pads(tx6ul_i2c_pads,
+                                               ARRAY_SIZE(tx6ul_i2c_pads));
        }
 }
 #else
-static inline void tx6_i2c_recover(void)
+static inline void tx6ul_i2c_recover(void)
 {
 }
 #endif
@@ -388,7 +413,7 @@ int checkboard(void)
 #ifdef CONFIG_MX6_TEMPERATURE_HOT
        check_cpu_temperature(1);
 #endif
-       tx6_i2c_recover();
+       tx6ul_i2c_recover();
        return 0;
 }
 
@@ -399,14 +424,14 @@ int board_early_init_f(void)
 }
 
 #ifndef CONFIG_MX6_TEMPERATURE_HOT
-static bool tx6_temp_check_enabled = true;
+static bool tx6ul_temp_check_enabled = true;
 #else
-#define tx6_temp_check_enabled 0
+#define tx6ul_temp_check_enabled       0
 #endif
 
 static inline u8 tx6ul_mem_suffix(void)
 {
-#ifdef CONFIG_TX6_NAND
+#ifdef CONFIG_TX6UL_NAND
        return '0';
 #else
        return '1';
@@ -442,7 +467,7 @@ static struct pmic_regs rn5t567_regs[] = {
        { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
 };
 
-static int pmic_addr __maybe_unused = 0x33;
+static int pmic_addr = 0x33;
 #endif
 
 int board_init(void)
@@ -459,9 +484,9 @@ int board_init(void)
        get_hab_status();
 
        ret = gpio_request_array(tx6ul_gpios, ARRAY_SIZE(tx6ul_gpios));
-       if (ret < 0) {
+       if (ret < 0)
                printf("Failed to request tx6ul_gpios: %d\n", ret);
-       }
+
        imx_iomux_v3_setup_multiple_pads(tx6ul_pads, ARRAY_SIZE(tx6ul_pads));
 
        /* Address of boot parameters */
@@ -474,7 +499,7 @@ int board_init(void)
                else
                        printf("<CTRL-C> detected; safeboot enabled\n");
 #ifndef CONFIG_MX6_TEMPERATURE_HOT
-               tx6_temp_check_enabled = false;
+               tx6ul_temp_check_enabled = false;
 #endif
                return 0;
        }
@@ -512,37 +537,37 @@ void dram_init_banksize(void)
 }
 
 #ifdef CONFIG_FSL_ESDHC
-#define TX6_SD_PAD_CTRL                (PAD_CTL_PUS_47K_UP |   \
-                               PAD_CTL_SPEED_MED |     \
-                               PAD_CTL_DSE_40ohm |     \
-                               PAD_CTL_SRE_FAST)
+#define TX6UL_SD_PAD_CTRL      MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |       \
+                                       PAD_CTL_SPEED_MED |             \
+                                       PAD_CTL_DSE_40ohm |             \
+                                       PAD_CTL_SRE_FAST)
 
 static const iomux_v3_cfg_t mmc0_pads[] = {
-       MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
-       MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
-       MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
-       MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
-       MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
-       MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
+       MX6_PAD_SD1_CMD__USDHC1_CMD | TX6UL_SD_PAD_CTRL,
+       MX6_PAD_SD1_CLK__USDHC1_CLK | TX6UL_SD_PAD_CTRL,
+       MX6_PAD_SD1_DATA0__USDHC1_DATA0 | TX6UL_SD_PAD_CTRL,
+       MX6_PAD_SD1_DATA1__USDHC1_DATA1 | TX6UL_SD_PAD_CTRL,
+       MX6_PAD_SD1_DATA2__USDHC1_DATA2 | TX6UL_SD_PAD_CTRL,
+       MX6_PAD_SD1_DATA3__USDHC1_DATA3 | TX6UL_SD_PAD_CTRL,
        /* SD1 CD */
-       MX6_PAD_NAND_CE1_B__GPIO4_IO14 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
+       MX6_PAD_NAND_CE1_B__GPIO4_IO14 | TX6UL_SD_PAD_CTRL,
 };
 
 #ifdef CONFIG_TX6_EMMC
 static const iomux_v3_cfg_t mmc1_pads[] = {
-       MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
-       MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
-       MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
-       MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
-       MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
-       MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
+       MX6_PAD_NAND_WE_B__USDHC2_CMD | TX6UL_SD_PAD_CTRL,
+       MX6_PAD_NAND_RE_B__USDHC2_CLK | TX6UL_SD_PAD_CTRL,
+       MX6_PAD_NAND_DATA00__USDHC2_DATA0 | TX6UL_SD_PAD_CTRL,
+       MX6_PAD_NAND_DATA01__USDHC2_DATA1 | TX6UL_SD_PAD_CTRL,
+       MX6_PAD_NAND_DATA02__USDHC2_DATA2 | TX6UL_SD_PAD_CTRL,
+       MX6_PAD_NAND_DATA03__USDHC2_DATA3 | TX6UL_SD_PAD_CTRL,
        /* eMMC RESET */
        MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
                                                PAD_CTL_DSE_40ohm),
 };
 #endif
 
-static struct tx6_esdhc_cfg {
+static struct tx6ul_esdhc_cfg {
        const iomux_v3_cfg_t *pads;
        int num_pads;
        enum mxc_clock clkid;
@@ -573,14 +598,14 @@ static struct tx6_esdhc_cfg {
        },
 };
 
-static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
+static inline struct tx6ul_esdhc_cfg *to_tx6ul_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 {
-       return container_of(cfg, struct tx6_esdhc_cfg, cfg);
+       return container_of(cfg, struct tx6ul_esdhc_cfg, cfg);
 }
 
 int board_mmc_getcd(struct mmc *mmc)
 {
-       struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
+       struct tx6ul_esdhc_cfg *cfg = to_tx6ul_esdhc_cfg(mmc->priv);
 
        if (cfg->cd_gpio < 0)
                return 1;
@@ -606,7 +631,7 @@ int board_mmc_init(bd_t *bis)
 #endif
        for (i = 0; i < ARRAY_SIZE(tx6ul_esdhc_cfg); i++) {
                struct mmc *mmc;
-               struct tx6_esdhc_cfg *cfg = &tx6ul_esdhc_cfg[i];
+               struct tx6ul_esdhc_cfg *cfg = &tx6ul_esdhc_cfg[i];
                int ret;
 
                cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
@@ -644,7 +669,7 @@ enum {
 
 static inline int calc_blink_rate(void)
 {
-       if (!tx6_temp_check_enabled)
+       if (!tx6ul_temp_check_enabled)
                return CONFIG_SYS_HZ;
 
        return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
@@ -689,29 +714,38 @@ void show_activity(int arg)
        }
 }
 
+static const iomux_v3_cfg_t stk5_jtag_pads[] = {
+       MX6_PAD_JTAG_MOD__SJC_MOD | TX6UL_GPIO_IN_PAD_CTRL,
+       MX6_PAD_JTAG_TCK__SJC_TCK | TX6UL_GPIO_IN_PAD_CTRL,
+       MX6_PAD_JTAG_TRST_B__SJC_TRSTB | TX6UL_GPIO_IN_PAD_CTRL,
+       MX6_PAD_JTAG_TDI__SJC_TDI | TX6UL_GPIO_IN_PAD_CTRL,
+       MX6_PAD_JTAG_TDO__SJC_TDO | TX6UL_GPIO_OUT_PAD_CTRL,
+       MX6_PAD_JTAG_TMS__SJC_TMS | TX6UL_GPIO_IN_PAD_CTRL,
+};
+
 static const iomux_v3_cfg_t stk5_pads[] = {
        /* SW controlled LED on STK5 baseboard */
        MX6_PAD_SNVS_TAMPER9__GPIO5_IO09,
 
        /* I2C bus on DIMM pins 40/41 */
-       MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
-       MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
+       MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
+       MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
 
        /* TSC200x PEN IRQ */
-       MX6_PAD_JTAG_TMS__GPIO1_IO11 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL),
+       MX6_PAD_JTAG_TMS__GPIO1_IO11 | TX6UL_GPIO_IN_PAD_CTRL,
 
        /* EDT-FT5x06 Polytouch panel */
-       MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* IRQ */
-       MX6_PAD_SNVS_TAMPER3__GPIO5_IO03 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* RESET */
-       MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* WAKE */
+       MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | TX6UL_GPIO_IN_PAD_CTRL, /* IRQ */
+       MX6_PAD_SNVS_TAMPER3__GPIO5_IO03 | TX6UL_GPIO_OUT_PAD_CTRL, /* RESET */
+       MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | TX6UL_GPIO_OUT_PAD_CTRL, /* WAKE */
 
        /* USBH1 */
-       MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */
-       MX6_PAD_GPIO1_IO03__USB_OTG2_OC | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */
+       MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
+       MX6_PAD_GPIO1_IO03__USB_OTG2_OC | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
 
        /* USBOTG */
-       MX6_PAD_UART3_CTS_B__GPIO1_IO26 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */
-       MX6_PAD_UART3_RTS_B__GPIO1_IO27 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */
+       MX6_PAD_UART3_CTS_B__GPIO1_IO26 | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
+       MX6_PAD_UART3_RTS_B__GPIO1_IO27 | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
 };
 
 static const struct gpio stk5_gpios[] = {
@@ -730,7 +764,7 @@ vidinfo_t panel_info = {
        .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 };
 
-static struct fb_videomode tx6_fb_modes[] = {
+static struct fb_videomode tx6ul_fb_modes[] = {
 #ifndef CONFIG_SYS_LVDS_IF
        {
                /* Standard VGA timing */
@@ -909,11 +943,11 @@ static int lcd_backlight_polarity(void)
 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 #ifdef CONFIG_LCD
        /* LCD RESET */
-       MX6_PAD_LCD_RESET__GPIO3_IO04 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL),
+       MX6_PAD_LCD_RESET__GPIO3_IO04 | TX6UL_GPIO_OUT_PAD_CTRL,
        /* LCD POWER_ENABLE */
-       MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL),
+       MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | TX6UL_GPIO_OUT_PAD_CTRL,
        /* LCD Backlight (PWM) */
-       MX6_PAD_NAND_DQS__GPIO4_IO16 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL),
+       MX6_PAD_NAND_DQS__GPIO4_IO16 | TX6UL_GPIO_OUT_PAD_CTRL,
        /* Display */
        MX6_PAD_LCD_DATA00__LCDIF_DATA00,
        MX6_PAD_LCD_DATA01__LCDIF_DATA01,
@@ -991,7 +1025,7 @@ void lcd_ctrl_init(void *lcdbase)
        const char *vm;
        unsigned long val;
        int refresh = 60;
-       struct fb_videomode *p = &tx6_fb_modes[0];
+       struct fb_videomode *p = &tx6ul_fb_modes[0];
        struct fb_videomode fb_mode;
        int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
 
@@ -1103,7 +1137,7 @@ void lcd_ctrl_init(void *lcdbase)
                printf("Invalid video mode: %s\n", getenv("video_mode"));
                lcd_enabled = 0;
                printf("Supported video modes are:");
-               for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
+               for (p = &tx6ul_fb_modes[0]; p->name != NULL; p++) {
                        printf(" %s", p->name);
                }
                printf("\n");
@@ -1178,7 +1212,7 @@ void lcd_ctrl_init(void *lcdbase)
 #endif /* CONFIG_LCD */
 
 #ifndef CONFIG_ENV_IS_IN_MMC
-static void tx6_mmc_init(void)
+static void tx6ul_mmc_init(void)
 {
        puts("MMC:   ");
        if (board_mmc_init(gd->bd) < 0)
@@ -1186,7 +1220,7 @@ static void tx6_mmc_init(void)
        print_mmc_devices(',');
 }
 #else
-static inline void tx6_mmc_init(void)
+static inline void tx6ul_mmc_init(void)
 {
 }
 #endif
@@ -1201,6 +1235,10 @@ static void stk5_board_init(void)
                return;
        }
        imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
+       if (getenv_yesno("jtag_enable") != 0) {
+               /* true if unset or set to one of: 'yYtT1' */
+               imx_iomux_v3_setup_multiple_pads(stk5_jtag_pads, ARRAY_SIZE(stk5_jtag_pads));
+       }
        debug("%s@%d: \n", __func__, __LINE__);
 }
 
@@ -1209,7 +1247,7 @@ static void stk5v3_board_init(void)
        debug("%s@%d: \n", __func__, __LINE__);
        stk5_board_init();
        debug("%s@%d: \n", __func__, __LINE__);
-       tx6_mmc_init();
+       tx6ul_mmc_init();
 }
 
 static void stk5v5_board_init(void)
@@ -1217,7 +1255,7 @@ static void stk5v5_board_init(void)
        int ret;
 
        stk5_board_init();
-       tx6_mmc_init();
+       tx6ul_mmc_init();
 
        ret = gpio_request_one(IMX_GPIO_NR(3, 5), GPIOFLAG_OUTPUT_INIT_HIGH,
                        "Flexcan Transceiver");
@@ -1227,7 +1265,7 @@ static void stk5v5_board_init(void)
        }
 
        imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA00__GPIO3_IO05 |
-                       MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL));
+                       TX6UL_GPIO_OUT_PAD_CTRL);
 }
 
 static void tx6ul_set_cpu_clock(void)
@@ -1259,7 +1297,7 @@ int board_late_init(void)
 
        env_cleanup();
 
-       if (tx6_temp_check_enabled)
+       if (tx6ul_temp_check_enabled)
                check_cpu_temperature(1);
 
        tx6ul_set_cpu_clock();
@@ -1323,7 +1361,7 @@ exit:
 #define ETH_ALEN 6
 #endif
 
-static void tx6_init_mac(void)
+static void tx6ul_init_mac(void)
 {
        u8 mac[ETH_ALEN];
        const char *baseboard = getenv("baseboard");
@@ -1351,7 +1389,7 @@ int board_eth_init(bd_t *bis)
 {
        int ret;
 
-       tx6_init_mac();
+       tx6ul_init_mac();
 
        /* delay at least 21ms for the PHY internal POR signal to deassert */
        udelay(22000);
@@ -1418,7 +1456,7 @@ static struct node_info nodes[] = {
 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
 #endif
 
-static const char *tx6_touchpanels[] = {
+static const char *tx6ul_touchpanels[] = {
        "ti,tsc2007",
        "edt,edt-ft5x06",
        "eeti,egalax_ts",
@@ -1441,8 +1479,8 @@ int ft_board_setup(void *blob, bd_t *bd)
 
        fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
 
-       karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
-                               ARRAY_SIZE(tx6_touchpanels));
+       karo_fdt_fixup_touchpanel(blob, tx6ul_touchpanels,
+                               ARRAY_SIZE(tx6ul_touchpanels));
        karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
        karo_fdt_fixup_flexcan(blob, stk5_v5);
 
index b8567d9..a3684da 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=4096,TX6_REV=0x2"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6Q_1020=y
+CONFIG_TARGET_TX6Q_EMMC=y
 CONFIG_TX6_UBOOT=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index 92513b5..eab82df 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=4096,TX6_REV=0x2"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6Q_1020=y
+CONFIG_TARGET_TX6Q_EMMC=y
 CONFIG_TX6_UBOOT_MFG=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index c60060a..c8a841a 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=4096,TX6_REV=0x2"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6Q_1020=y
+CONFIG_TARGET_TX6Q_EMMC=y
 CONFIG_TX6_UBOOT_NOENV=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index c55066a..e35c396 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=4096,SECURE_BOOT,TX6_REV=0x2"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6Q_1020=y
+CONFIG_TARGET_TX6Q_EMMC=y
 CONFIG_TX6_UBOOT=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index cce4940..d4e3865 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=4096"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6Q_1036=y
+CONFIG_TARGET_TX6Q_EMMC=y
 CONFIG_TX6_UBOOT=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index b44e41c..772bb77 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=4096"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6Q_1036=y
+CONFIG_TARGET_TX6Q_EMMC=y
 CONFIG_TX6_UBOOT_MFG=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index bc6dd53..aba1798 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=4096"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6Q_1036=y
+CONFIG_TARGET_TX6Q_EMMC=y
 CONFIG_TX6_UBOOT_NOENV=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index 7a775a9..1cca243 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=4096,SECURE_BOOT"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6Q_1036=y
+CONFIG_TARGET_TX6Q_EMMC=y
 CONFIG_TX6_UBOOT=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index fb4dc15..6e1514c 100644 (file)
@@ -1,7 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6Q_10X0=y
+CONFIG_TARGET_TX6Q_NAND=y
 CONFIG_TX6_UBOOT=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index 97e0635..a8b1b28 100644 (file)
@@ -1,7 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6Q_10X0=y
+CONFIG_TARGET_TX6Q_NAND=y
 CONFIG_TX6_UBOOT_MFG=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index 5b63d3a..e9e090c 100644 (file)
@@ -1,7 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6Q_10X0=y
+CONFIG_TARGET_TX6Q_NAND=y
 CONFIG_TX6_UBOOT_NOENV=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index cd2db4b..ac64560 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6Q_10X0=y
+CONFIG_TARGET_TX6Q_NAND=y
 CONFIG_TX6_UBOOT=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index 4856a32..16862b7 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6Q_11X0=y
+CONFIG_TARGET_TX6Q_NAND=y
 CONFIG_TX6_UBOOT=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index 25d7b10..fcb47dc 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6Q_11X0=y
+CONFIG_TARGET_TX6Q_NAND=y
 CONFIG_TX6_UBOOT_MFG=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index 50d1be5..ee3cfe2 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6Q_11X0=y
+CONFIG_TARGET_TX6Q_NAND=y
 CONFIG_TX6_UBOOT_NOENV=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index 4a0a117..3744f9a 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT,SYS_LVDS_IF"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6Q_11X0=y
+CONFIG_TARGET_TX6Q_NAND=y
 CONFIG_TX6_UBOOT=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index 8f2947b..046d2b9 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6QP_8037=y
+CONFIG_TARGET_TX6QP_EMMC=y
 CONFIG_TX6_UBOOT=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index dd26543..1fa3366 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6QP_8037=y
+CONFIG_TARGET_TX6QP_EMMC=y
 CONFIG_TX6_UBOOT_MFG=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index d363bb4..cf1e7d5 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6QP_8037=y
+CONFIG_TARGET_TX6QP_EMMC=y
 CONFIG_TX6_UBOOT_NOENV=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index 70b9d7c..88820f6 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SECURE_BOOT"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6QP_8037=y
+CONFIG_TARGET_TX6QP_EMMC=y
 CONFIG_TX6_UBOOT=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index ff723a7..3c10572 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=16"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6S_8034=y
+CONFIG_TARGET_TX6S_NAND=y
 CONFIG_TX6_UBOOT=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index a639f13..08b04f0 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=16"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6S_8034=y
+CONFIG_TARGET_TX6S_NAND=y
 CONFIG_TX6_UBOOT_MFG=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index ed4e98d..0639684 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=16"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6S_8034=y
+CONFIG_TARGET_TX6S_NAND=y
 CONFIG_TX6_UBOOT_NOENV=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index 4bdc10b..b8cc8dd 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT,SYS_SDRAM_BUS_WIDTH=16"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6S_8034=y
+CONFIG_TARGET_TX6S_NAND=y
 CONFIG_TX6_UBOOT=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index 8656148..fb477c4 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SYS_SDRAM_BUS_WIDTH=32"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6S_8035=y
+CONFIG_TARGET_TX6S_EMMC=y
 CONFIG_TX6_UBOOT=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index 1b2f6d6..4fcbbea 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SYS_SDRAM_BUS_WIDTH=32"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6S_8035=y
+CONFIG_TARGET_TX6S_EMMC=y
 CONFIG_TX6_UBOOT_MFG=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index 52241ab..6bd85a2 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SYS_SDRAM_BUS_WIDTH=32"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6S_8035=y
+CONFIG_TARGET_TX6S_EMMC=y
 CONFIG_TX6_UBOOT_NOENV=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index ea6e847..f38d9b4 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SECURE_BOOT,SYS_SDRAM_BUS_WIDTH=32"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6S_8035=y
+CONFIG_TARGET_TX6S_EMMC=y
 CONFIG_TX6_UBOOT=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
similarity index 84%
rename from configs/tx6u-8011_defconfig
rename to configs/tx6s-8134_defconfig
index ca0371c..1c044f6 100644 (file)
@@ -1,8 +1,8 @@
-CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32,TX6_REV=0x1"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF,SYS_SDRAM_BUS_WIDTH=16"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6U_8011=y
+CONFIG_TARGET_TX6S_NAND=y
 CONFIG_TX6_UBOOT=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
@@ -33,5 +33,5 @@ CONFIG_MMC=y
 CONFIG_NET=y
 CONFIG_NETDEVICES=y
 CONFIG_PHY_SMSC=y
-CONFIG_SYS_PROMPT="TX6DL U-Boot > "
+CONFIG_SYS_PROMPT="TX6S U-Boot > "
 CONFIG_SYS_SDRAM_CHIP_SIZE=512
similarity index 84%
rename from configs/tx6u-8011_mfg_defconfig
rename to configs/tx6s-8134_mfg_defconfig
index 3fca82e..3acf425 100644 (file)
@@ -1,8 +1,8 @@
-CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32,TX6_REV=0x1"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF,SYS_SDRAM_BUS_WIDTH=16"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6U_8011=y
+CONFIG_TARGET_TX6S_NAND=y
 CONFIG_TX6_UBOOT_MFG=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
@@ -32,5 +32,5 @@ CONFIG_MMC=y
 CONFIG_NET=y
 CONFIG_NETDEVICES=y
 CONFIG_PHY_SMSC=y
-CONFIG_SYS_PROMPT="TX6DL U-Boot > "
+CONFIG_SYS_PROMPT="TX6S U-Boot > "
 CONFIG_SYS_SDRAM_CHIP_SIZE=512
similarity index 84%
rename from configs/tx6u-8011_noenv_defconfig
rename to configs/tx6s-8134_noenv_defconfig
index 26f0c76..c43825c 100644 (file)
@@ -1,8 +1,8 @@
-CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32,TX6_REV=0x1"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF,SYS_SDRAM_BUS_WIDTH=16"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6U_8011=y
+CONFIG_TARGET_TX6S_NAND=y
 CONFIG_TX6_UBOOT_NOENV=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
@@ -32,5 +32,5 @@ CONFIG_MMC=y
 CONFIG_NET=y
 CONFIG_NETDEVICES=y
 CONFIG_PHY_SMSC=y
-CONFIG_SYS_PROMPT="TX6DL U-Boot > "
+CONFIG_SYS_PROMPT="TX6S U-Boot > "
 CONFIG_SYS_SDRAM_CHIP_SIZE=512
similarity index 89%
rename from configs/tx6u-8111_sec_defconfig
rename to configs/tx6s-8134_sec_defconfig
index cc03891..d3fd702 100644 (file)
@@ -1,8 +1,8 @@
-CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT,SYS_LVDS_IF,SYS_SDRAM_BUS_WIDTH=32,TX6_REV=0x1"
+CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT,SYS_LVDS_IF,SYS_SDRAM_BUS_WIDTH=16"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6U_8111=y
+CONFIG_TARGET_TX6S_NAND=y
 CONFIG_TX6_UBOOT=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
@@ -33,5 +33,5 @@ CONFIG_MMC=y
 CONFIG_NET=y
 CONFIG_NETDEVICES=y
 CONFIG_PHY_SMSC=y
-CONFIG_SYS_PROMPT="TX6DL U-Boot > "
+CONFIG_SYS_PROMPT="TX6S U-Boot > "
 CONFIG_SYS_SDRAM_CHIP_SIZE=512
diff --git a/configs/tx6s-8135_defconfig b/configs/tx6s-8135_defconfig
new file mode 100644 (file)
index 0000000..bc07420
--- /dev/null
@@ -0,0 +1,33 @@
+CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SYS_LVDS_IF,SYS_SDRAM_BUS_WIDTH=32"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_TX6=y
+CONFIG_TARGET_TX6S_EMMC=y
+CONFIG_TX6_UBOOT=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FEC_MXC=y
+CONFIG_FEC_MXC_PHYADDR=0
+CONFIG_IMX_WATCHDOG=y
+CONFIG_LCD=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
+CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6S U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
diff --git a/configs/tx6s-8135_mfg_defconfig b/configs/tx6s-8135_mfg_defconfig
new file mode 100644 (file)
index 0000000..1d95a2c
--- /dev/null
@@ -0,0 +1,32 @@
+CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SYS_LVDS_IF,SYS_SDRAM_BUS_WIDTH=32"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_TX6=y
+CONFIG_TARGET_TX6S_EMMC=y
+CONFIG_TX6_UBOOT_MFG=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FEC_MXC=y
+CONFIG_FEC_MXC_PHYADDR=0
+CONFIG_IMX_WATCHDOG=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
+CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6S U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
diff --git a/configs/tx6s-8135_noenv_defconfig b/configs/tx6s-8135_noenv_defconfig
new file mode 100644 (file)
index 0000000..ce464f1
--- /dev/null
@@ -0,0 +1,32 @@
+CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SYS_LVDS_IF,SYS_SDRAM_BUS_WIDTH=32"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_TX6=y
+CONFIG_TARGET_TX6S_EMMC=y
+CONFIG_TX6_UBOOT_NOENV=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FEC_MXC=y
+CONFIG_FEC_MXC_PHYADDR=0
+CONFIG_IMX_WATCHDOG=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
+CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6S U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
diff --git a/configs/tx6s-8135_sec_defconfig b/configs/tx6s-8135_sec_defconfig
new file mode 100644 (file)
index 0000000..c5be306
--- /dev/null
@@ -0,0 +1,33 @@
+CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SECURE_BOOT,SYS_SDRAM_BUS_WIDTH=32,SYS_LVDS_IF"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_TX6=y
+CONFIG_TARGET_TX6S_EMMC=y
+CONFIG_TX6_UBOOT=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FEC_MXC=y
+CONFIG_FEC_MXC_PHYADDR=0
+CONFIG_IMX_WATCHDOG=y
+CONFIG_LCD=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
+CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6S U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
index 7d0d775..b8331e5 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BLOCKS=2048,TX6_REV=0x1"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6U_8012=y
+CONFIG_TARGET_TX6U_NAND=y
 CONFIG_TX6_UBOOT=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index 398d38d..40eb32e 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BLOCKS=2048,TX6_REV=0x1"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6U_8012=y
+CONFIG_TARGET_TX6U_NAND=y
 CONFIG_TX6_UBOOT_MFG=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index 78f1e74..d8956c6 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BLOCKS=2048,TX6_REV=0x1"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6U_8012=y
+CONFIG_TARGET_TX6U_NAND=y
 CONFIG_TX6_UBOOT_NOENV=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index fadc106..cb657e1 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT,SYS_NAND_BLOCKS=2048,TX6_REV=0x1"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6U_8012=y
+CONFIG_TARGET_TX6U_NAND=y
 CONFIG_TX6_UBOOT=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index 0a08ec1..b9d7c16 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6U_8033=y
+CONFIG_TARGET_TX6U_EMMC=y
 CONFIG_TX6_UBOOT=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index f5104b0..d6323d4 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6U_8033=y
+CONFIG_TARGET_TX6U_EMMC=y
 CONFIG_TX6_UBOOT_MFG=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index 10f9571..0fddb34 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6U_8033=y
+CONFIG_TARGET_TX6U_EMMC=y
 CONFIG_TX6_UBOOT_NOENV=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index 35de96e..640284f 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SECURE_BOOT"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6U_8033=y
+CONFIG_TARGET_TX6U_EMMC=y
 CONFIG_TX6_UBOOT=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index cd28f7b..8ef4f36 100644 (file)
@@ -1,7 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6U_80X0=y
+CONFIG_TARGET_TX6U_NAND=y
 CONFIG_TX6_UBOOT=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index a0e422e..1634be6 100644 (file)
@@ -1,7 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6U_80X0=y
+CONFIG_TARGET_TX6U_NAND=y
 CONFIG_TX6_UBOOT_MFG=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index 0b50a79..f70c0fb 100644 (file)
@@ -1,7 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6U_80X0=y
+CONFIG_TARGET_TX6U_NAND=y
 CONFIG_TX6_UBOOT_NOENV=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index e045c55..9ca5b74 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6U_80X0=y
+CONFIG_TARGET_TX6U_NAND=y
 CONFIG_TX6_UBOOT=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
similarity index 74%
rename from configs/tx6u-8111_defconfig
rename to configs/tx6u-8133_defconfig
index b4b7090..21d65b4 100644 (file)
@@ -1,8 +1,8 @@
-CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32,SYS_LVDS_IF,TX6_REV=0x1"
+CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SYS_LVDS_IF"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6U_8111=y
+CONFIG_TARGET_TX6U_EMMC=y
 CONFIG_TX6_UBOOT=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
@@ -18,18 +18,14 @@ CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_MMC=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_DOS_PARTITION=y
-CONFIG_ENV_IS_IN_NAND=y
+CONFIG_ENV_IS_IN_MMC=y
 CONFIG_FEC_MXC=y
 CONFIG_FEC_MXC_PHYADDR=0
 CONFIG_IMX_WATCHDOG=y
 CONFIG_LCD=y
-CONFIG_MMC=y
 CONFIG_NET=y
 CONFIG_NETDEVICES=y
 CONFIG_PHY_SMSC=y
similarity index 74%
rename from configs/tx6u-8111_mfg_defconfig
rename to configs/tx6u-8133_mfg_defconfig
index 2adc272..53ade5c 100644 (file)
@@ -1,8 +1,8 @@
-CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32,SYS_LVDS_IF,TX6_REV=0x1"
+CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SYS_LVDS_IF"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6U_8111=y
+CONFIG_TARGET_TX6U_EMMC=y
 CONFIG_TX6_UBOOT_MFG=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
@@ -18,17 +18,13 @@ CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_MMC=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_DOS_PARTITION=y
-CONFIG_ENV_IS_IN_NAND=y
+CONFIG_ENV_IS_IN_MMC=y
 CONFIG_FEC_MXC=y
 CONFIG_FEC_MXC_PHYADDR=0
 CONFIG_IMX_WATCHDOG=y
-CONFIG_MMC=y
 CONFIG_NET=y
 CONFIG_NETDEVICES=y
 CONFIG_PHY_SMSC=y
similarity index 74%
rename from configs/tx6u-8111_noenv_defconfig
rename to configs/tx6u-8133_noenv_defconfig
index 5329690..5dd4e8f 100644 (file)
@@ -1,8 +1,8 @@
-CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32,SYS_LVDS_IF,TX6_REV=0x1"
+CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SYS_LVDS_IF"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6U_8111=y
+CONFIG_TARGET_TX6U_EMMC=y
 CONFIG_TX6_UBOOT_NOENV=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
@@ -18,17 +18,13 @@ CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_MMC=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_DOS_PARTITION=y
-CONFIG_ENV_IS_IN_NAND=y
+CONFIG_ENV_IS_IN_MMC=y
 CONFIG_FEC_MXC=y
 CONFIG_FEC_MXC_PHYADDR=0
 CONFIG_IMX_WATCHDOG=y
-CONFIG_MMC=y
 CONFIG_NET=y
 CONFIG_NETDEVICES=y
 CONFIG_PHY_SMSC=y
similarity index 74%
rename from configs/tx6u-8011_sec_defconfig
rename to configs/tx6u-8133_sec_defconfig
index 20f697d..2771871 100644 (file)
@@ -1,8 +1,8 @@
-CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT,SYS_SDRAM_BUS_WIDTH=32,TX6_REV=0x1"
+CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SECURE_BOOT,SYS_LVDS_IF"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6U_8011=y
+CONFIG_TARGET_TX6U_EMMC=y
 CONFIG_TX6_UBOOT=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
@@ -18,18 +18,14 @@ CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_MMC=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_NAND_TRIMFFS=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_DOS_PARTITION=y
-CONFIG_ENV_IS_IN_NAND=y
+CONFIG_ENV_IS_IN_MMC=y
 CONFIG_FEC_MXC=y
 CONFIG_FEC_MXC_PHYADDR=0
 CONFIG_IMX_WATCHDOG=y
 CONFIG_LCD=y
-CONFIG_MMC=y
 CONFIG_NET=y
 CONFIG_NETDEVICES=y
 CONFIG_PHY_SMSC=y
index bdc7428..97ad112 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6U_81X0=y
+CONFIG_TARGET_TX6U_NAND=y
 CONFIG_TX6_UBOOT=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index c0e8e5f..7a6d7aa 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6U_81X0=y
+CONFIG_TARGET_TX6U_NAND=y
 CONFIG_TX6_UBOOT_MFG=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index 357face..55df71d 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6U_81X0=y
+CONFIG_TARGET_TX6U_NAND=y
 CONFIG_TX6_UBOOT_NOENV=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index c1988c2..7e9114b 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT,SYS_LVDS_IF"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6U_81X0=y
+CONFIG_TARGET_TX6U_NAND=y
 CONFIG_TX6_UBOOT=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index b03ffb1..550e931 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SOC_MX6UL=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6UL_0010=y
+CONFIG_TARGET_TX6UL_NAND=y
 CONFIG_TX6_UBOOT=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
@@ -13,6 +13,7 @@ CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_FUSE=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_MII=y
index 988e3ee..3857bb7 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SOC_MX6UL=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6UL_0010=y
+CONFIG_TARGET_TX6UL_NAND=y
 CONFIG_TX6_UBOOT_MFG=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index 5d52305..d9edfed 100644 (file)
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SOC_MX6UL=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6UL_0010=y
+CONFIG_TARGET_TX6UL_NAND=y
 CONFIG_TX6_UBOOT_NOENV=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index 27d8df0..83ce789 100644 (file)
@@ -3,7 +3,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SOC_MX6UL=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6UL_0010=y
+CONFIG_TARGET_TX6UL_NAND=y
 CONFIG_TX6_UBOOT=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index 34fc697..747cfec 100644 (file)
@@ -3,7 +3,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SOC_MX6UL=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6UL_0011=y
+CONFIG_TARGET_TX6UL_EMMC=y
 CONFIG_TX6_UBOOT=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
@@ -14,6 +14,7 @@ CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_FUSE=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_MII=y
index 6c9b3c1..db2e47b 100644 (file)
@@ -3,7 +3,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SOC_MX6UL=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6UL_0011=y
+CONFIG_TARGET_TX6UL_EMMC=y
 CONFIG_TX6_UBOOT_MFG=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index dac05c9..9fcebbc 100644 (file)
@@ -3,7 +3,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SOC_MX6UL=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6UL_0011=y
+CONFIG_TARGET_TX6UL_EMMC=y
 CONFIG_TX6_UBOOT_NOENV=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index 63f4154..6c9f9f7 100644 (file)
@@ -3,7 +3,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SOC_MX6UL=y
 CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6UL_0011=y
+CONFIG_TARGET_TX6UL_EMMC=y
 CONFIG_TX6_UBOOT=y
 CONFIG_BOOTP_DNS=y
 CONFIG_BOOTP_GATEWAY=y
index fced6eb..f0dc19a 100644 (file)
@@ -10,6 +10,10 @@ config HARD_I2C
 config SYS_I2C
        bool
 
+config SYS_I2C_SOFT
+       bool "Software emulated I2C bus driver"
+       depends on SYS_I2C
+
 config DM_I2C
        bool "Enable Driver Model for I2C drivers"
        depends on DM
index 8b1b05b..dcd36de 100644 (file)
 #error Unsupported TX6 module revision
 #endif
 #else /* CONFIG_TX6_REV */
-/* autodetect which PMIC is present to derive TX6_REV */
 #ifdef CONFIG_SOC_MX6UL
-#ifndef CONFIG_TX6_UBOOT_NOENV
+#ifdef CONFIG_SYS_I2C_SOFT
 /* NOENV U-Boot is used for initial bootstrap.
  * Since the TAMPER_PIN_DISABLE fuses have to be programmed
  * to be able to use the TAMPER pins as GPIO to access the
  * PMIC I2C bus, this is not possible on virgin hardware.
  */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT
 #define CONFIG_SYS_I2C_SOFT_SPEED      400000
+#define CONFIG_SYS_I2C_SPEED           CONFIG_SYS_I2C_SOFT_SPEED
 #define CONFIG_SOFT_I2C_GPIO_SCL       IMX_GPIO_NR(5, 0)
 #define CONFIG_SOFT_I2C_GPIO_SDA       IMX_GPIO_NR(5, 1)
 #define CONFIG_SOFT_I2C_READ_REPEATED_START
-#endif /* CONFIG_TX6_UBOOT_NOENV */
+#endif /* CONFIG_SYS_I2C_SOFT */
 #else /* !CONFIG_SOC_MX6UL */
+/* autodetect which PMIC is present to derive TX6_REV */
 #define CONFIG_LTC3676                 /* TX6_REV == 1 */
 #endif /*  CONFIG_SOC_MX6UL */
 #define CONFIG_RN5T567                 /* TX6_REV == 3 */