--- /dev/null
+/*
+ * (C) Copyright 2010-2011 Texas Instruments, <www.ti.com>
+ * Mansoor Ahamed <mansoor.ahamed@ti.com>
+ *
+ * BCH Error Location Module (ELM) support.
+ *
+ * NOTE:
+ * 1. Supports only continuous mode. Dont see need for page mode in uboot
+ * 2. Supports only syndrome polynomial 0. i.e. poly local variable is
+ * always set to ELM_DEFAULT_POLY. Dont see need for other polynomial
+ * sets in uboot
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/nand.h>
+
+#define ELM_DEFAULT_POLY (0)
+
+static struct elm *elm_cfg;
+
+/**
+ * elm_load_syndromes - Load BCH syndromes based on nibble selection
+ * @syndrome: BCH syndrome
+ * @nibbles:
+ * @poly: Syndrome Polynomial set to use
+ *
+ * Load BCH syndromes based on nibble selection
+ */
+static void elm_load_syndromes(u8 *syndrome, u32 nibbles, u8 poly)
+{
+ u32 *ptr;
+ u32 val;
+
+ /* reg 0 */
+ ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[0];
+ val = syndrome[0] | (syndrome[1] << 8) | (syndrome[2] << 16) |
+ (syndrome[3] << 24);
+ writel(val, ptr);
+ /* reg 1 */
+ ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[1];
+ val = syndrome[4] | (syndrome[5] << 8) | (syndrome[6] << 16) |
+ (syndrome[7] << 24);
+ writel(val, ptr);
+
+ /* BCH 8-bit with 26 nibbles (4*8=32) */
+ if (nibbles > 13) {
+ /* reg 2 */
+ ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[2];
+ val = syndrome[8] | (syndrome[9] << 8) | (syndrome[10] << 16) |
+ (syndrome[11] << 24);
+ writel(val, ptr);
+ /* reg 3 */
+ ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[3];
+ val = syndrome[12] | (syndrome[13] << 8) | (syndrome[14] << 16) |
+ (syndrome[15] << 24);
+ writel(val, ptr);
+ }
+
+ /* BCH 16-bit with 52 nibbles (7*8=56) */
+ if (nibbles > 26) {
+ /* reg 4 */
+ ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[4];
+ val = syndrome[16] | (syndrome[17] << 8) | (syndrome[18] << 16) |
+ (syndrome[19] << 24);
+ writel(val, ptr);
+
+ /* reg 5 */
+ ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[5];
+ val = syndrome[20] | (syndrome[21] << 8) | (syndrome[22] << 16) |
+ (syndrome[23] << 24);
+ writel(val, ptr);
+
+ /* reg 6 */
+ ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6];
+ val = syndrome[24] | (syndrome[25] << 8) | (syndrome[26] << 16) |
+ (syndrome[27] << 24);
+ writel(val, ptr);
+ }
+}
+
+/**
+ * elm_check_errors - Check for BCH errors and return error locations
+ * @syndrome: BCH syndrome
+ * @nibbles:
+ * @error_count: Returns number of errrors in the syndrome
+ * @error_locations: Returns error locations (in decimal) in this array
+ *
+ * Check the provided syndrome for BCH errors and return error count
+ * and locations in the array passed. Returns -1 if error is not correctable,
+ * else returns 0
+ */
+int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count,
+ u32 *error_locations)
+{
+ u8 poly = ELM_DEFAULT_POLY;
+ s8 i;
+ u32 location_status;
+
+ elm_load_syndromes(syndrome, nibbles, poly);
+
+ /* start processing */
+ writel((readl(&elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6])
+ | ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID),
+ &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6]);
+
+ /* wait for processing to complete */
+ while((readl(&elm_cfg->irqstatus) & (0x1 << poly)) != 0x1);
+ /* clear status */
+ writel((readl(&elm_cfg->irqstatus) | (0x1 << poly)), &elm_cfg->irqstatus);
+
+ /* check if correctable */
+ location_status = readl(&elm_cfg->error_location[poly].location_status);
+ if (!(location_status & ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK))
+ return -1;
+
+ /* get error count */
+ *error_count = readl(&elm_cfg->error_location[poly].location_status) &
+ ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK;
+
+ for (i = 0; i < *error_count; i++)
+ error_locations[i] =
+ readl(&elm_cfg->error_location[poly].error_location_x[i]);
+
+ return 0;
+}
+
+
+/**
+ * elm_config - Configure ELM module
+ * @level: 4 / 8 / 16 bit BCH
+ * @buffer_size: Buffer size in bytes
+ *
+ * Configure ELM module based on BCH level and buffer size passed.
+ * Set mode as continuous mode.
+ * Currently we are using only syndrome 0 and syndromes 1 to 6 are not used.
+ * Also, the mode is set only for syndrome 0
+ */
+/* int elm_config(enum bch_level level, u32 buffer_size) */
+int elm_config(enum bch_level level)
+{
+ u32 val;
+ u8 poly = ELM_DEFAULT_POLY;
+ u32 buffer_size= 0x7FF;
+
+ /* config size and level */
+ val = (u32)(level) & ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_MASK;
+ val |= ((buffer_size << ELM_LOCATION_CONFIG_ECC_SIZE_POS) &
+ ELM_LOCATION_CONFIG_ECC_SIZE_MASK);
+ writel(val, &elm_cfg->location_config);
+
+ /* config continous mode */
+ /* enable interrupt generation for syndrome polynomial set */
+ writel((readl(&elm_cfg->irqenable) | (0x1 << poly)), &elm_cfg->irqenable);
+ /* set continuous mode for the syndrome polynomial set */
+ writel((readl(&elm_cfg->page_ctrl) & ~(0x1 << poly)), &elm_cfg->page_ctrl);
+
+ return 0;
+}
+
+/**
+ * elm_reset - Do a soft reset of ELM
+ *
+ * Perform a soft reset of ELM and return after reset is done.
+ */
+void elm_reset(void)
+{
+ /* initiate reset */
+ writel((readl(&elm_cfg->sysconfig) | ELM_SYSCONFIG_SOFTRESET),
+ &elm_cfg->sysconfig);
+
+ /* wait for reset complete and normal operation */
+ while((readl(&elm_cfg->sysstatus) & ELM_SYSSTATUS_RESETDONE) !=
+ ELM_SYSSTATUS_RESETDONE);
+}
+
+/**
+ * elm_init - Initialize ELM module
+ *
+ * Initialize ELM support. Currently it does only base address init
+ * and ELM reset.
+ */
+void elm_init( void )
+{
+ elm_cfg = (struct elm *)ELM_BASE;
+ elm_reset();
+}
+
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Mansoor Ahamed <mansoor.ahamed@ti.com>
+ *
+ * Initial Code from:
+ * Manikandan Pillai <mani.pillai@ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <command.h>
+
+struct gpmc *gpmc_cfg;
+
+#if defined(CONFIG_CMD_NAND)
+static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
+ M_NAND_GPMC_CONFIG1,
+ M_NAND_GPMC_CONFIG2,
+ M_NAND_GPMC_CONFIG3,
+ M_NAND_GPMC_CONFIG4,
+ M_NAND_GPMC_CONFIG5,
+ M_NAND_GPMC_CONFIG6, 0
+};
+
+#define GPMC_CS 0
+
+#endif
+
+
+void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
+ u32 size)
+{
+ writel(0, &cs->config7);
+ sdelay(1000);
+ /* Delay for settling */
+ writel(gpmc_config[0], &cs->config1);
+ writel(gpmc_config[1], &cs->config2);
+ writel(gpmc_config[2], &cs->config3);
+ writel(gpmc_config[3], &cs->config4);
+ writel(gpmc_config[4], &cs->config5);
+ writel(gpmc_config[5], &cs->config6);
+ /* Enable the config */
+ writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
+ (1 << 6)), &cs->config7);
+ sdelay(2000);
+}
+
+/*****************************************************
+ * gpmc_init(): init gpmc bus
+ * Init GPMC for x16, MuxMode (SDRAM in x32).
+ * This code can only be executed from SRAM or SDRAM.
+ *****************************************************/
+void gpmc_init(void)
+{
+ /* putting a blanket check on GPMC based on ZeBu for now */
+ gpmc_cfg = (struct gpmc *)GPMC_BASE;
+
+#if defined(CONFIG_CMD_NAND) || defined(CONFIG_CMD_ONENAND)
+ const u32 *gpmc_config = NULL;
+ u32 base = 0;
+ u32 size = 0;
+#endif
+ /* global settings */
+ writel(0x00000008, &gpmc_cfg->sysconfig);
+ writel(0x00000100, &gpmc_cfg->irqstatus);
+ writel(0x00000200, &gpmc_cfg->irqenable);
+ writel(0x00000012, &gpmc_cfg->config);
+ /*
+ * Disable the GPMC0 config set by ROM code
+ */
+ writel(0, &gpmc_cfg->cs[0].config7);
+ sdelay(1000);
+
+#if defined(CONFIG_CMD_NAND) /* CS 0 */
+ gpmc_config = gpmc_m_nand;
+
+ base = PISMO1_NAND_BASE;
+ size = PISMO1_NAND_SIZE;
+ enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
+#endif
+}
--- /dev/null
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author
+ * Mansoor Ahamed <mansoor.ahamed@ti.com>
+ *
+ * Initial Code from:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _MEM_H_
+#define _MEM_H_
+
+#define CS0 0x0
+#define CS1 0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */
+
+#ifndef __ASSEMBLY__
+enum {
+ STACKED = 0,
+ IP_DDR = 1,
+ COMBO_DDR = 2,
+ IP_SDR = 3,
+};
+#endif /* __ASSEMBLY__ */
+
+#define EARLY_INIT 1
+
+/*
+ * GPMC settings -
+ * Definitions is as per the following format
+ * #define <PART>_GPMC_CONFIG<x> <value>
+ * Where:
+ * PART is the part name e.g. STNOR - Intel Strata Flash
+ * x is GPMC config registers from 1 to 6 (there will be 6 macros)
+ * Value is corresponding value
+ *
+ * For every valid PRCM configuration there should be only one definition of
+ * the same. if values are independent of the board, this definition will be
+ * present in this file if values are dependent on the board, then this should
+ * go into corresponding mem-boardName.h file
+ *
+ * Currently valid part Names are (PART):
+ * STNOR - Intel Strata Flash
+ * SMNAND - Samsung NAND
+ * MPDB - H4 MPDB board
+ * SBNOR - Sibley NOR
+ * MNAND - Micron Large page x16 NAND
+ * ONNAND - Samsung One NAND
+ *
+ * include/configs/file.h contains the defn - for all CS we are interested
+ * #define OMAP34XX_GPMC_CSx PART
+ * #define OMAP34XX_GPMC_CSx_SIZE Size
+ * #define OMAP34XX_GPMC_CSx_MAP Map
+ * Where:
+ * x - CS number
+ * PART - Part Name as defined above
+ * SIZE - how big is the mapping to be
+ * GPMC_SIZE_128M - 0x8
+ * GPMC_SIZE_64M - 0xC
+ * GPMC_SIZE_32M - 0xE
+ * GPMC_SIZE_16M - 0xF
+ * MAP - Map this CS to which address(GPMC address space)- Absolute address
+ * >>24 before being used.
+ */
+#define GPMC_SIZE_256M 0x0
+#define GPMC_SIZE_128M 0x8
+#define GPMC_SIZE_64M 0xC
+#define GPMC_SIZE_32M 0xE
+#define GPMC_SIZE_16M 0xF
+
+#define SMNAND_GPMC_CONFIG1 0x00000800
+#define SMNAND_GPMC_CONFIG2 0x00141400
+#define SMNAND_GPMC_CONFIG3 0x00141400
+#define SMNAND_GPMC_CONFIG4 0x0F010F01
+#define SMNAND_GPMC_CONFIG5 0x010C1414
+#define SMNAND_GPMC_CONFIG6 0x1F0F0A80
+#define SMNAND_GPMC_CONFIG7 0x00000C44
+
+
+#ifdef CONFIG_AM33XX /* SA 8-Bit Nand */
+#define M_NAND_GPMC_CONFIG1 0x00000800
+#else
+#define M_NAND_GPMC_CONFIG1 0x00001810
+#endif
+#define M_NAND_GPMC_CONFIG2 0x001e1e00
+#define M_NAND_GPMC_CONFIG3 0x001e1e00
+#define M_NAND_GPMC_CONFIG4 0x16051807
+#define M_NAND_GPMC_CONFIG5 0x00151e1e
+#define M_NAND_GPMC_CONFIG6 0x16000f80
+#define M_NAND_GPMC_CONFIG7 0x00000008
+
+#define STNOR_GPMC_CONFIG1 0x3
+#define STNOR_GPMC_CONFIG2 0x00151501
+#define STNOR_GPMC_CONFIG3 0x00060602
+#define STNOR_GPMC_CONFIG4 0x11091109
+#define STNOR_GPMC_CONFIG5 0x01141F1F
+#define STNOR_GPMC_CONFIG6 0x000004c4
+
+#define SIBNOR_GPMC_CONFIG1 0x1200
+#define SIBNOR_GPMC_CONFIG2 0x001f1f00
+#define SIBNOR_GPMC_CONFIG3 0x00080802
+#define SIBNOR_GPMC_CONFIG4 0x1C091C09
+#define SIBNOR_GPMC_CONFIG5 0x01131F1F
+#define SIBNOR_GPMC_CONFIG6 0x1F0F03C2
+
+#define SDPV2_MPDB_GPMC_CONFIG1 0x00611200
+#define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01
+#define SDPV2_MPDB_GPMC_CONFIG3 0x00080803
+#define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09
+#define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F
+#define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4
+
+#define MPDB_GPMC_CONFIG1 0x00011000
+#define MPDB_GPMC_CONFIG2 0x001f1f01
+#define MPDB_GPMC_CONFIG3 0x00080803
+#define MPDB_GPMC_CONFIG4 0x1c0b1c0a
+#define MPDB_GPMC_CONFIG5 0x041f1F1F
+#define MPDB_GPMC_CONFIG6 0x1F0F04C4
+
+#define P2_GPMC_CONFIG1 0x0
+#define P2_GPMC_CONFIG2 0x0
+#define P2_GPMC_CONFIG3 0x0
+#define P2_GPMC_CONFIG4 0x0
+#define P2_GPMC_CONFIG5 0x0
+#define P2_GPMC_CONFIG6 0x0
+
+#define ONENAND_GPMC_CONFIG1 0x00001200
+#define ONENAND_GPMC_CONFIG2 0x000F0F01
+#define ONENAND_GPMC_CONFIG3 0x00030301
+#define ONENAND_GPMC_CONFIG4 0x0F040F04
+#define ONENAND_GPMC_CONFIG5 0x010F1010
+#define ONENAND_GPMC_CONFIG6 0x1F060000
+
+#define NET_GPMC_CONFIG1 0x00001000
+#define NET_GPMC_CONFIG2 0x001e1e01
+#define NET_GPMC_CONFIG3 0x00080300
+#define NET_GPMC_CONFIG4 0x1c091c09
+#define NET_GPMC_CONFIG5 0x04181f1f
+#define NET_GPMC_CONFIG6 0x00000FCF
+#define NET_GPMC_CONFIG7 0x00000f6c
+
+/* max number of GPMC Chip Selects */
+#define GPMC_MAX_CS 8
+/* max number of GPMC regs */
+#define GPMC_MAX_REG 7
+
+#define PISMO1_NOR 1
+#define PISMO1_NAND 2
+#define PISMO2_CS0 3
+#define PISMO2_CS1 4
+#define PISMO1_ONENAND 5
+#define DBG_MPDB 6
+#define PISMO2_NAND_CS0 7
+#define PISMO2_NAND_CS1 8
+
+/* make it readable for the gpmc_init */
+#define PISMO1_NOR_BASE FLASH_BASE
+#define PISMO1_NAND_BASE NAND_BASE
+#define PISMO1_NAND_SIZE GPMC_SIZE_256M
+
+#endif /* endif _MEM_H_ */
+
--- /dev/null
+/*
+ * (C) Copyright 2010-2011 Texas Instruments, <www.ti.com>
+ * Mansoor Ahamed <mansoor.ahamed@ti.com>
+ *
+ * Derived from work done by Rohit Choraria <rohitkc@ti.com> for omap3
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_OMAP_GPMC_H
+#define __ASM_ARCH_OMAP_GPMC_H
+
+#include <linux/mtd/nand.h>
+
+#define GPMC_BUF_EMPTY 0
+#define GPMC_BUF_FULL 1
+
+#define ECCCLEAR (0x1 << 8)
+#define ECCRESULTREG1 (0x1 << 0)
+#define ECCSIZE512BYTE 0xFF
+#define ECCSIZE1 (ECCSIZE512BYTE << 22)
+#define ECCSIZE0 (ECCSIZE512BYTE << 12)
+#define ECCSIZE0SEL (0x000 << 0)
+
+/* Generic ECC Layouts */
+/* Large Page x8 NAND device Layout */
+#ifdef GPMC_NAND_ECC_LP_x8_LAYOUT
+#define GPMC_NAND_HW_ECC_LAYOUT {\
+ .eccbytes = 12,\
+ .eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\
+ 9, 10, 11, 12},\
+ .oobfree = {\
+ {.offset = 13,\
+ .length = 51 } } \
+}
+#endif
+
+/* Large Page x16 NAND device Layout */
+#ifdef GPMC_NAND_ECC_LP_x16_LAYOUT
+#define GPMC_NAND_HW_ECC_LAYOUT {\
+ .eccbytes = 12,\
+ .eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\
+ 10, 11, 12, 13},\
+ .oobfree = {\
+ {.offset = 14,\
+ .length = 50 } } \
+}
+#endif
+
+/* NAND device layout in synch with the kernel */
+#ifdef GPMC_NAND_ECC_LP_x16_LAYOUT
+#define GPMC_NAND_HW_ECC_LAYOUT_KERNEL {\
+ .eccbytes = 12,\
+ .eccpos = {\
+ 40, 41, 42, 43, 44, 45, 46, 47,\
+ 48, 49, 50, 51},\
+ .oobfree = {\
+ {.offset = 2,\
+ .length = 38} } \
+}
+#endif
+
+/* Small Page x8 NAND device Layout */
+#ifdef GPMC_NAND_ECC_SP_x8_LAYOUT
+#define GPMC_NAND_HW_ECC_LAYOUT {\
+ .eccbytes = 3,\
+ .eccpos = {1, 2, 3},\
+ .oobfree = {\
+ {.offset = 4,\
+ .length = 12 } } \
+}
+#endif
+
+/* Small Page x16 NAND device Layout */
+#ifdef GPMC_NAND_ECC_SP_x16_LAYOUT
+#define GPMC_NAND_HW_ECC_LAYOUT {\
+ .eccbytes = 3,\
+ .eccpos = {2, 3, 4},\
+ .oobfree = {\
+ {.offset = 58,\
+ .length = 6 } } \
+}
+#endif
+
+#define GPMC_NAND_HW_BCH4_ECC_LAYOUT {\
+ .eccbytes = 32,\
+ .eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
+ 28, 29, 30, 31, 32, 33},\
+ .oobfree = {\
+ {.offset = 34,\
+ .length = 30 } } \
+}
+
+#define GPMC_NAND_HW_BCH8_ECC_LAYOUT {\
+ .eccbytes = 56,\
+ .eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
+ 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\
+ 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,\
+ 52, 53, 54, 55, 56, 57},\
+ .oobfree = {\
+ {.offset = 58,\
+ .length = 6 } } \
+}
+
+#define GPMC_NAND_HW_BCH16_ECC_LAYOUT {\
+ .eccbytes = 104,\
+ .eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
+ 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\
+ 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,\
+ 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,\
+ 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,\
+ 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,\
+ 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,\
+ 100, 101, 102, 103, 104, 105},\
+ .oobfree = {\
+ {.offset = 106,\
+ .length = 8 } } \
+}
+
+/*
+ * ELM Module Registers
+ */
+
+/* ELM registers bit fields */
+#define ELM_SYSCONFIG_SOFTRESET_MASK (0x2)
+#define ELM_SYSCONFIG_SOFTRESET (0x2)
+#define ELM_SYSSTATUS_RESETDONE_MASK (0x1)
+#define ELM_SYSSTATUS_RESETDONE (0x1)
+#define ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_MASK (0x3)
+#define ELM_LOCATION_CONFIG_ECC_SIZE_MASK (0x7FF0000)
+#define ELM_LOCATION_CONFIG_ECC_SIZE_POS (16)
+#define ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID (0x00010000)
+#define ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK (0x100)
+#define ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK (0x1F)
+
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+
+enum bch_level {
+ BCH_4_BIT = 0,
+ BCH_8_BIT,
+ BCH_16_BIT
+};
+
+
+/* BCH syndrome registers */
+struct syndrome {
+ u32 syndrome_fragment_x[7]; /* 0x400, 0x404.... 0x418 */
+ u8 res1[36]; /* 0x41c */
+};
+
+/* BCH error status & location register */
+struct location {
+ u32 location_status; /* 0x800 */
+ u8 res1[124]; /* 0x804 */
+ u32 error_location_x[16]; /* 0x880.... */
+ u8 res2[64]; /* 0x8c0 */
+};
+
+/* BCH ELM register map - do not try to allocate memmory for this structure.
+ * We have used plenty of reserved variables to fill the slots in the ELM
+ * register memory map.
+ * Directly initialize the struct pointer to ELM base address.
+ */
+struct elm {
+ u32 rev; /* 0x000 */
+ u8 res1[12]; /* 0x004 */
+ u32 sysconfig; /* 0x010 */
+ u32 sysstatus; /* 0x014 */
+ u32 irqstatus; /* 0x018 */
+ u32 irqenable; /* 0x01c */
+ u32 location_config; /* 0x020 */
+ u8 res2[92]; /* 0x024 */
+ u32 page_ctrl; /* 0x080 */
+ u8 res3[892]; /* 0x084 */
+ struct syndrome syndrome_fragments[8]; /* 0x400 */
+ u8 res4[512]; /* 0x600 */
+ struct location error_location[8]; /* 0x800 */
+};
+
+int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count,
+ u32 *error_locations);
+int elm_config(enum bch_level level);
+void elm_reset(void);
+void elm_init(void);
+void am33xx_nand_switch_ecc(nand_ecc_modes_t hardware, int32_t mode);
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+
+#endif /* __ASM_ARCH_OMAP_GPMC_H */
+
off = last + nand->writesize;
last = off;
-
+#ifndef CONFIG_NAND_AM33XX
datbuf = malloc(nand->writesize);
+#else
+ datbuf = malloc(nand->writesize + nand->oobsize);
+#endif
oobbuf = malloc(nand->oobsize);
if (!datbuf || !oobbuf) {
puts("No memory for page buffer\n");
}
puts("OOB:\n");
i = nand->oobsize >> 3;
+#ifndef CONFIG_NAND_AM33XX
p = oobbuf;
+#endif
while (i--) {
printf("\t%02x %02x %02x %02x %02x %02x %02x %02x\n",
p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
COBJS-y += nand_base.o
COBJS-$(CONFIG_NAND_ECC_BCH) += nand_bch.o
+COBJS-$(CONFIG_NAND_AM33XX) += am33xx_nand.o
COBJS-$(CONFIG_NAND_ATMEL) += atmel_nand.o
COBJS-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o
COBJS-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
COBJS-$(CONFIG_NAND_MXS) += mxs_nand.o
COBJS-$(CONFIG_NAND_NDFC) += ndfc.o
COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o
+COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_bch_decoder.o omap_gpmc.o omap_bch_soft.o
+COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o
COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o
COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o
COBJS-$(CONFIG_NAND_SPEAR) += spr_nand.o
-COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
-COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o
endif
COBJS := $(COBJS-y)
--- /dev/null
+/*
+ * (C) Copyright 2012 Lothar Waßmann <LW@KARO-electronics.de>
+ * based on ti81xx_nand.c
+ * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
+ * Mansoor Ahamed <mansoor.ahamed@ti.com>
+ *
+ * Derived from work done by Rohit Choraria <rohitkc@ti.com> for omap
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/nand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <nand.h>
+
+struct nand_bch_priv {
+ uint8_t type;
+ uint8_t nibbles;
+};
+
+/* bch types */
+#define ECC_BCH4 0
+#define ECC_BCH8 1
+#define ECC_BCH16 2
+
+/* BCH nibbles for diff bch levels */
+#define ECC_BCH4_NIBBLES 13
+#define ECC_BCH8_NIBBLES 26
+#define ECC_BCH16_NIBBLES 52
+
+static uint8_t cs;
+#ifndef CONFIG_SPL_BUILD
+static struct nand_ecclayout hw_nand_oob = GPMC_NAND_HW_ECC_LAYOUT_KERNEL;
+static struct nand_ecclayout hw_bch4_nand_oob = GPMC_NAND_HW_BCH4_ECC_LAYOUT;
+static struct nand_ecclayout hw_bch16_nand_oob = GPMC_NAND_HW_BCH16_ECC_LAYOUT;
+#endif
+static struct nand_ecclayout hw_bch8_nand_oob = GPMC_NAND_HW_BCH8_ECC_LAYOUT;
+
+static struct gpmc *gpmc_cfg = (struct gpmc *)GPMC_BASE;
+
+static struct nand_bch_priv bch_priv = {
+ .type = ECC_BCH8,
+ .nibbles = ECC_BCH8_NIBBLES
+};
+
+/*
+ * am33xx_read_bch8_result - Read BCH result for BCH8 level
+ *
+ * @mtd: MTD device structure
+ * @big_endian: When set read register 3 first
+ * @ecc_code: Read syndrome from BCH result registers
+ */
+static void am33xx_read_bch8_result(struct mtd_info *mtd, uint8_t big_endian,
+ uint8_t *ecc_code)
+{
+ uint32_t *ptr;
+ int8_t i = 0, j;
+
+ if (big_endian) {
+ ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3];
+ ecc_code[i++] = readl(ptr) & 0xFF;
+ ptr--;
+ for (j = 0; j < 3; j++) {
+ ecc_code[i++] = (readl(ptr) >> 24) & 0xFF;
+ ecc_code[i++] = (readl(ptr) >> 16) & 0xFF;
+ ecc_code[i++] = (readl(ptr) >> 8) & 0xFF;
+ ecc_code[i++] = readl(ptr) & 0xFF;
+ ptr--;
+ }
+ }
+ else {
+ ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[0];
+ for (j = 0; j < 3; j++) {
+ ecc_code[i++] = readl(ptr) & 0xFF;
+ ecc_code[i++] = (readl(ptr) >> 8) & 0xFF;
+ ecc_code[i++] = (readl(ptr) >> 16) & 0xFF;
+ ecc_code[i++] = (readl(ptr) >> 24) & 0xFF;
+ ptr++;
+ }
+ ecc_code[i++] = readl(ptr) & 0xFF;
+ }
+}
+
+/*
+ * am33xx_ecc_disable - Disable H/W ECC calculation
+ *
+ * @mtd: MTD device structure
+ *
+ */
+static void am33xx_ecc_disable(struct mtd_info *mtd) {
+
+ writel((readl(&gpmc_cfg->ecc_config) & ~0x1),
+ &gpmc_cfg->ecc_config);
+}
+
+#if 0
+/*
+ * am33xx_ecc_enable_bch - Enable BCH H/W ECC calculation
+ *
+ * @mtd: MTD device structure
+ *
+ */
+static void am33xx_ecc_enable_bch(struct mtd_info *mtd) {
+ uint32_t val;
+
+ val = readl(&gpmc_cfg->ecc_control);
+ val |= 0x00000100u;
+ writel(val, &gpmc_cfg->ecc_control); /* clear ECC outputs */
+
+ val = readl(&gpmc_cfg->ecc_control);
+ val &= ~0xF;
+ val |= 0x1;
+ writel(val, &gpmc_cfg->ecc_control); /* reset ecc pointer to result 1 */
+
+ val = readl(&gpmc_cfg->ecc_config);
+ val |= 0x1;
+ writel(val, &gpmc_cfg->ecc_config); /* enable ecc */
+}
+#endif
+
+/*
+ * am33xx_nand_hwcontrol - Set the address pointers correctly for the
+ * following address/data/command operation
+ */
+static void am33xx_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
+ uint32_t ctrl)
+{
+ register struct nand_chip *this = mtd->priv;
+
+ /*
+ * Point the IO_ADDR to DATA and ADDRESS registers instead
+ * of chip address
+ */
+ switch (ctrl) {
+ case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
+ this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
+ break;
+ case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
+ this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_adr;
+ break;
+ case NAND_CTRL_CHANGE | NAND_NCE:
+ this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
+ }
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
+}
+
+/*
+ * am33xx_hwecc_init_bch - Initialize the BCH Hardware ECC for NAND flash in
+ * GPMC controller
+ * @mtd: MTD device structure
+ * @mode: Read/Write mode
+ */
+static void am33xx_hwecc_init_bch(struct nand_chip *chip, int32_t mode)
+{
+ uint32_t val, dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1;
+ uint32_t unused_length = 0;
+ struct nand_bch_priv *bch = chip->priv;
+
+ switch(bch->nibbles) {
+ case ECC_BCH4_NIBBLES:
+ unused_length = 3;
+ break;
+ case ECC_BCH8_NIBBLES:
+ unused_length = 2;
+ break;
+ case ECC_BCH16_NIBBLES:
+ unused_length = 0;
+ }
+
+ /* Clear the ecc result registers, select ecc reg as 1 */
+ writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
+
+ switch (mode) {
+ case NAND_ECC_WRITE:
+ /* eccsize1 config */
+ val = ((unused_length + bch->nibbles) << 22);
+ break;
+
+ case NAND_ECC_READ:
+ default:
+ /* by default eccsize0 selected for ecc1resultsize */
+ /* eccsize0 config */
+ val = (bch->nibbles << 12);
+ /* eccsize1 config */
+ val |= (unused_length << 22);
+ }
+ /* ecc size configuration */
+ writel(val, &gpmc_cfg->ecc_size_config);
+ /* by default 512bytes sector page is selected */
+ /* set bch mode */
+ val = (1 << 16);
+ /* bch4 / bch8 / bch16 */
+ val |= (bch->type << 12);
+ /* set wrap mode to 1 */
+ val |= (1 << 8);
+ val |= (dev_width << 7);
+ val |= (cs << 1);
+ /* enable ecc */
+ /* val |= (1); */ /* should not enable ECC just init i.e. config */
+ writel(val, &gpmc_cfg->ecc_config);
+}
+
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ * am33xx_hwecc_init - Initialize the Hardware ECC for NAND flash in
+ * GPMC controller
+ * @mtd: MTD device structure
+ *
+ */
+static void am33xx_hwecc_init(struct nand_chip *chip)
+{
+ /*
+ * Init ECC Control Register
+ * Clear all ECC | Enable Reg1
+ */
+ writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
+ writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, &gpmc_cfg->ecc_size_config);
+}
+
+/*
+ * gen_true_ecc - This function will generate true ECC value, which
+ * can be used when correcting data read from NAND flash memory core
+ *
+ * @ecc_buf: buffer to store ecc code
+ *
+ * @return: re-formatted ECC value
+ */
+static uint32_t gen_true_ecc(uint8_t *ecc_buf)
+{
+ return ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xF0) << 20) |
+ ((ecc_buf[2] & 0x0F) << 8);
+}
+#endif
+
+/*
+ * am33xx_rotate_ecc_bch - Rotate the syndrome bytes
+ *
+ * @mtd: MTD device structure
+ * @calc_ecc: ECC read from ECC registers
+ * @syndrome: Rotated syndrome will be retuned in this array
+ *
+ */
+static void am33xx_rotate_ecc_bch(struct mtd_info *mtd, uint8_t *calc_ecc,
+ uint8_t *syndrome)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct nand_bch_priv *bch = chip->priv;
+ uint8_t n_bytes = 0;
+ int8_t i,j;
+
+ switch(bch->type) {
+ case ECC_BCH4:
+ n_bytes = 8;
+ break;
+
+ case ECC_BCH16:
+ n_bytes = 28;
+ break;
+
+ case ECC_BCH8:
+ default:
+ n_bytes = 13;
+ }
+
+ for (i = 0, j = (n_bytes-1); i < n_bytes; i++, j--)
+ syndrome[i] = calc_ecc[j];
+}
+
+
+/*
+ * am33xx_fix_errors_bch - Correct bch error in the data
+ *
+ * @mtd: MTD device structure
+ * @data: Data read from flash
+ * @error_count:Number of errors in data
+ * @error_loc: Locations of errors in the data
+ *
+ */
+static void am33xx_fix_errors_bch(struct mtd_info *mtd, uint8_t *data,
+ uint32_t error_count, uint32_t *error_loc)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct nand_bch_priv *bch = chip->priv;
+ uint8_t count = 0;
+ uint32_t error_byte_pos;
+ uint32_t error_bit_mask;
+ uint32_t last_bit = (bch->nibbles * 4) - 1;
+
+ /* Flip all bits as specified by the error location array. */
+ /* FOR( each found error location flip the bit ) */
+ for (count = 0; count < error_count; count++) {
+ if (error_loc[count] > last_bit) {
+ /* Remove the ECC spare bits from correction. */
+ error_loc[count] -= (last_bit + 1);
+ /* Offset bit in data region */
+ error_byte_pos = ((512 * 8) - (error_loc[count]) - 1) / 8;
+ /* Error Bit mask */
+ error_bit_mask = 0x1 << (error_loc[count] % 8);
+ /* Toggle the error bit to make the correction. */
+ data[error_byte_pos] ^= error_bit_mask;
+ }
+ }
+}
+
+/*
+ * am33xx_correct_data_bch - Compares the ecc read from nand spare area
+ * with ECC registers values and corrects one bit error if it has occured
+ *
+ * @mtd: MTD device structure
+ * @dat: page data
+ * @read_ecc: ecc read from nand flash (ignored)
+ * @calc_ecc: ecc read from ECC registers
+ *
+ * @return 0 if data is OK or corrected, else returns -1
+ */
+static int am33xx_correct_data_bch(struct mtd_info *mtd, uint8_t *dat,
+ uint8_t *read_ecc, uint8_t *calc_ecc)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct nand_bch_priv *bch = chip->priv;
+ uint8_t syndrome[28];
+ uint32_t error_count = 0;
+ uint32_t error_loc[8];
+ uint32_t i, ecc_flag;
+
+ ecc_flag = 0;
+ for (i = 0; i < (chip->ecc.bytes - 1); i++)
+ if (read_ecc[i] != 0xff)
+ ecc_flag = 1;
+
+ if (!ecc_flag)
+ return 0;
+
+ elm_reset();
+ elm_config(bch->type);
+
+ /* while reading ECC result we read it in big endian.
+ * Hence while loading to ELM we have rotate to get the right endian.
+ */
+ am33xx_rotate_ecc_bch(mtd, calc_ecc, syndrome);
+
+#ifdef DEBUG
+ {
+ uint8_t i = 0;
+
+ printf("ecc: ");
+ for (i = 0; i < 13; i++)
+ printf(" 0x%02x", syndrome[i]);
+ printf("\n");
+ }
+#endif
+
+
+ /* use elm module to check for errors */
+ if (elm_check_error(syndrome, bch->nibbles, &error_count, error_loc) != 0) {
+#ifndef CONFIG_SPL_BUILD
+ /* This currently sees all pages as being completely full of
+ * uncorrectable errors. The suspicion is that this is due
+ * to limitations in the elm support we have in U-Boot today
+ */
+ printf("ECC: uncorrectable.\n");
+#endif
+ return -1;
+ }
+
+ /* correct bch error */
+ if (error_count > 0) {
+ am33xx_fix_errors_bch(mtd, dat, error_count, error_loc);
+ }
+
+ return 0;
+}
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ * am33xx_correct_data - Compares the ecc read from nand spare area with ECC
+ * registers values and corrects one bit error if it has occured
+ * Further details can be had from Am33xx TRM and the following selected links:
+ * http://en.wikipedia.org/wiki/Hamming_code
+ * http://www.cs.utexas.edu/users/plaxton/c/337/05f/slides/ErrorCorrection-4.pdf
+ *
+ * @mtd: MTD device structure
+ * @dat: page data
+ * @read_ecc: ecc read from nand flash
+ * @calc_ecc: ecc read from ECC registers
+ *
+ * @return 0 if data is OK or corrected, else returns -1
+ */
+static int am33xx_correct_data(struct mtd_info *mtd, uint8_t *dat,
+ uint8_t *read_ecc, uint8_t *calc_ecc)
+{
+ uint32_t orig_ecc, new_ecc, res, hm;
+ uint16_t parity_bits, byte;
+ uint8_t bit;
+
+ /* Regenerate the orginal ECC */
+ orig_ecc = gen_true_ecc(read_ecc);
+ new_ecc = gen_true_ecc(calc_ecc);
+ /* Get the XOR of real ecc */
+ res = orig_ecc ^ new_ecc;
+ if (res) {
+ /* Get the hamming width */
+ hm = hweight32(res);
+ /* Single bit errors can be corrected! */
+ if (hm == 12) {
+ /* Correctable data! */
+ parity_bits = res >> 16;
+ bit = (parity_bits & 0x7);
+ byte = (parity_bits >> 3) & 0x1FF;
+ /* Flip the bit to correct */
+ dat[byte] ^= (0x1 << bit);
+ } else if (hm == 1) {
+ printf("am33xx_nand: Error: Corrupted ECC\n");
+ /* ECC itself is corrupted */
+ return 2;
+ } else {
+ /*
+ * hm distance != parity pairs OR one, could mean 2 bit
+ * error OR potentially be on a blank page..
+ * orig_ecc: contains spare area data from nand flash.
+ * new_ecc: generated ecc while reading data area.
+ * Note: if the ecc = 0, all data bits from which it was
+ * generated are 0xFF.
+ * The 3 byte(24 bits) ecc is generated per 512byte
+ * chunk of a page. If orig_ecc(from spare area)
+ * is 0xFF && new_ecc(computed now from data area)=0x0,
+ * this means that data area is 0xFF and spare area is
+ * 0xFF. A sure sign of an erased page!
+ */
+ if ((orig_ecc == 0x0FFF0FFF) && (new_ecc == 0x00000000))
+ return 0;
+ printf("am33xx_nand: Error: Multibit error detected; hm=%d\n",
+ hm);
+ /* detected 2 bit error */
+ return -1;
+ }
+ }
+ return 0;
+}
+#endif
+
+/*
+ * am33xx_calculate_ecc_bch - Read BCH ECC result
+ *
+ * @mtd: MTD structure
+ * @dat: unused
+ * @ecc_code: ecc_code buffer
+ */
+static int am33xx_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat,
+ uint8_t *ecc_code)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct nand_bch_priv *bch = chip->priv;
+ uint8_t big_endian = 1;
+ int8_t ret = 0;
+
+ if (bch->type == ECC_BCH8)
+ am33xx_read_bch8_result(mtd, big_endian, ecc_code);
+ else /* BCH4 and BCH16 currently not supported */
+ ret = -1;
+
+#ifdef DEBUG
+ {
+ int8_t i = 0;
+
+ printf("ECC: ");
+ for (i = 0; i < 13; i++)
+ printf(" 0x%02x", ecc_code[i]);
+ printf("\n");
+ }
+#endif
+
+ /*
+ * Stop reading anymore ECC vals and clear old results
+ * enable will be called if more reads are required
+ */
+ am33xx_ecc_disable(mtd);
+
+ return ret;
+}
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ * am33xx_calculate_ecc - Generate non-inverted ECC bytes.
+ *
+ * Using noninverted ECC can be considered ugly since writing a blank
+ * page ie. padding will clear the ECC bytes. This is no problem as
+ * long nobody is trying to write data on the seemingly unused page.
+ * Reading an erased page will produce an ECC mismatch between
+ * generated and read ECC bytes that has to be dealt with separately.
+ * E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC
+ * is used, the result of read will be 0x0 while the ECC offsets of the
+ * spare area will be 0xFF which will result in an ECC mismatch.
+ * @mtd: MTD structure
+ * @dat: unused
+ * @ecc_code: ecc_code buffer
+ */
+static int am33xx_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
+ uint8_t *ecc_code)
+{
+ u_int32_t val;
+
+ /* Start Reading from HW ECC1_Result = 0x200 */
+ val = readl(&gpmc_cfg->ecc1_result);
+
+ ecc_code[0] = val & 0xFF;
+ ecc_code[1] = (val >> 16) & 0xFF;
+ ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
+
+ /*
+ * Stop reading anymore ECC vals and clear old results
+ * enable will be called if more reads are required
+ */
+ writel(0x000, &gpmc_cfg->ecc_config);
+
+ return 0;
+}
+
+/**
+ * am33xx_write_page_bch - [REPLACABLE] hardware ecc based page write function
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: data buffer
+ */
+static void am33xx_write_page_bch(struct mtd_info *mtd,
+ struct nand_chip *chip, const uint8_t *buf)
+{
+ int i, eccsize = chip->ecc.size;
+ int eccbytes = chip->ecc.bytes;
+ int eccsteps = chip->ecc.steps;
+ uint8_t *ecc_calc = chip->buffers->ecccalc;
+ const uint8_t *p = buf;
+ uint32_t *eccpos = chip->ecc.layout->eccpos;
+
+ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+ chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
+ chip->write_buf(mtd, p, eccsize);
+ chip->ecc.calculate(mtd, p, &ecc_calc[i]);
+ }
+
+ for (i = 0; i < chip->ecc.total; i++)
+ chip->oob_poi[eccpos[i]] = ecc_calc[i];
+
+ chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
+}
+
+
+/**
+ * am33xx_read_page_bch - hardware ecc based page read function
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: buffer to store read data
+ * @page: page number to read
+ *
+ */
+static int am33xx_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buf, int page)
+{
+ int i, eccsize = chip->ecc.size;
+ int eccbytes = chip->ecc.bytes;
+ int eccsteps = chip->ecc.steps;
+ uint8_t *p = buf;
+ uint8_t *ecc_calc = chip->buffers->ecccalc;
+ uint8_t *ecc_code = chip->buffers->ecccode;
+ uint32_t *eccpos = chip->ecc.layout->eccpos;
+ uint8_t *oob = chip->oob_poi;
+ uint32_t data_pos;
+ uint32_t oob_pos;
+
+ data_pos = 0;
+ /* oob area start */
+ oob_pos = (eccsize * eccsteps) + chip->ecc.layout->eccpos[0];
+ //oob_pos = (eccsize * eccsteps) + 2;
+
+ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize,
+ oob += eccbytes) {
+ chip->ecc.hwctl(mtd, NAND_ECC_READ);
+ /* read data */
+ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, page);
+ chip->read_buf(mtd, p, eccsize);
+#ifdef DEBUG
+ {
+ uint32_t j;
+
+ printf("DATA: ");
+ for (j = 0; j < 13; j++)
+ printf(" 0x%02x", p[j]);
+ printf("\n");
+ }
+#endif
+
+ /* read respective ecc from oob area */
+ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, page);
+ chip->read_buf(mtd, oob, eccbytes);
+#ifdef DEBUG
+ {
+ uint32_t j;
+
+ printf("OOB: ");
+ for (j = 0; j < 13; j++)
+ printf(" 0x%02x", oob[j]);
+ printf("\n");
+ }
+#endif
+ /* read syndrome */
+ chip->ecc.calculate(mtd, p, &ecc_calc[i]);
+
+ data_pos += eccsize;
+ oob_pos += eccbytes;
+ }
+
+ for (i = 0; i < chip->ecc.total; i++)
+ ecc_code[i] = chip->oob_poi[eccpos[i]];
+
+ eccsteps = chip->ecc.steps;
+ p = buf;
+
+ for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+ int stat;
+
+ stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
+ if (stat < 0) {
+ printf("am33xx_nand: uncorrectable ECC error in page %5d\n",
+ page);
+ mtd->ecc_stats.failed++;
+ } else {
+ mtd->ecc_stats.corrected += stat;
+ }
+ }
+ return 0;
+}
+#endif
+
+/*
+ * am33xx_enable_ecc_bch- This function enables the bch h/w ecc functionality
+ * @mtd: MTD device structure
+ * @mode: Read/Write mode
+ *
+ */
+static void am33xx_enable_ecc_bch(struct mtd_info *mtd, int32_t mode)
+{
+ struct nand_chip *chip = mtd->priv;
+
+ am33xx_hwecc_init_bch(chip, mode);
+ /* enable ecc */
+ writel(readl(&gpmc_cfg->ecc_config) | 0x1, &gpmc_cfg->ecc_config);
+}
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ * am33xx_enable_ecc - This function enables the hardware ecc functionality
+ * @mtd: MTD device structure
+ * @mode: Read/Write mode
+ */
+static void am33xx_enable_ecc(struct mtd_info *mtd, int32_t mode)
+{
+ struct nand_chip *chip = mtd->priv;
+ uint32_t val, dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1;
+
+ switch (mode) {
+ case NAND_ECC_READ:
+ case NAND_ECC_WRITE:
+ /* Clear the ecc result registers, select ecc reg as 1 */
+ writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
+
+ /*
+ * Size 0 = 0xFF, Size1 is 0xFF - both are 512 bytes
+ * tell all regs to generate size0 sized regs
+ * we just have a single ECC engine for all CS
+ */
+ writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL,
+ &gpmc_cfg->ecc_size_config);
+ val = (dev_width << 7) | (cs << 1) | (0x1);
+ writel(val, &gpmc_cfg->ecc_config);
+ break;
+ default:
+ printf("Error: Unrecognized Mode[%d]!\n", mode);
+ }
+}
+
+/*
+ * __am33xx_nand_switch_ecc - switch the ECC operation ib/w h/w ecc
+ * (i.e. hamming / bch) and s/w ecc.
+ * The default is to come up on s/w ecc
+ *
+ * @nand: NAND chip datastructure
+ * @hardware: NAND_ECC_HW -switch to h/w ecc
+ * NAND_ECC_SOFT -switch to s/w ecc
+ *
+ * @mode: 0 - hamming code
+ * 1 - bch4
+ * 2 - bch8
+ * 3 - bch16
+ */
+void __am33xx_nand_switch_ecc(struct nand_chip *nand,
+ nand_ecc_modes_t hardware, int32_t mode)
+{
+ struct nand_bch_priv *bch;
+
+ debug("switching ECC mode to %d %d\n", hardware, mode);
+
+ bch = nand->priv;
+ nand->options |= NAND_OWN_BUFFERS;
+
+ /* Reset ecc interface */
+ nand->ecc.read_page = NULL;
+ nand->ecc.write_page = NULL;
+ nand->ecc.read_oob = NULL;
+ nand->ecc.write_oob = NULL;
+ nand->ecc.hwctl = NULL;
+ nand->ecc.correct = NULL;
+ nand->ecc.calculate = NULL;
+
+ nand->ecc.mode = hardware;
+ /* Setup the ecc configurations again */
+ if (hardware == NAND_ECC_HW) {
+ if (mode) {
+ /* -1 for converting mode to bch type */
+ bch->type = mode - 1;
+ debug("HW ECC BCH");
+ switch (bch->type) {
+ case ECC_BCH4:
+ nand->ecc.layout = &hw_bch4_nand_oob;
+ bch->nibbles = ECC_BCH4_NIBBLES;
+ nand->ecc.bytes = 8;
+ debug("4 not supported\n");
+ return;
+
+ case ECC_BCH16:
+ nand->ecc.bytes = 26;
+ nand->ecc.layout = &hw_bch16_nand_oob;
+ bch->nibbles = ECC_BCH16_NIBBLES;
+ debug("16 not supported\n");
+ return;
+
+ case ECC_BCH8:
+ default:
+ nand->ecc.bytes = 14;
+ nand->ecc.layout = &hw_bch8_nand_oob;
+ bch->nibbles = ECC_BCH8_NIBBLES;
+ debug("8 Selected\n");
+ }
+ nand->ecc.mode = NAND_ECC_HW_SYNDROME;
+ nand->ecc.steps = 4;
+ nand->ecc.size = 512;
+ nand->ecc.total = nand->ecc.steps * nand->ecc.bytes;
+ nand->ecc.write_page = am33xx_write_page_bch;
+ nand->ecc.read_page = am33xx_read_page_bch;
+ nand->ecc.hwctl = am33xx_enable_ecc_bch;
+ nand->ecc.correct = am33xx_correct_data_bch;
+ nand->ecc.calculate = am33xx_calculate_ecc_bch;
+ am33xx_hwecc_init_bch(nand, NAND_ECC_READ);
+ } else {
+ nand->ecc.layout = &hw_nand_oob;
+ nand->ecc.size = 512;
+ nand->ecc.bytes = 3;
+ nand->ecc.hwctl = am33xx_enable_ecc;
+ nand->ecc.correct = am33xx_correct_data;
+ nand->ecc.calculate = am33xx_calculate_ecc;
+ am33xx_hwecc_init(nand);
+ debug("HW ECC Hamming Code selected\n");
+ }
+ } else if (hardware == NAND_ECC_SOFT) {
+ /* Use mtd default settings */
+ nand->ecc.layout = NULL;
+ debug("SW ECC selected\n");
+ } else {
+ debug("ECC Disabled\n");
+ }
+}
+
+/*
+ * am33xx_nand_switch_ecc - switch the ECC operation ib/w h/w ecc
+ * (i.e. hamming / bch) and s/w ecc.
+ * The default is to come up on s/w ecc
+ *
+ * @hardware - NAND_ECC_HW -switch to h/w ecc
+ * NAND_ECC_SOFT -switch to s/w ecc
+ *
+ * @mode - 0 - hamming code
+ * 1 - bch4
+ * 2 - bch8
+ * 3 - bch16
+ */
+void am33xx_nand_switch_ecc(nand_ecc_modes_t hardware, int32_t mode)
+{
+ struct nand_chip *nand;
+ struct mtd_info *mtd;
+
+ if (nand_curr_device < 0 ||
+ nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE) {
+ printf("Error: Can't switch ecc, no devices available\n");
+ return;
+ }
+
+ mtd = &nand_info[nand_curr_device];
+ nand = mtd->priv;
+
+ __am33xx_nand_switch_ecc(nand, hardware, mode);
+
+ /* Update NAND handling after ECC mode switch */
+ nand_scan_tail(mtd);
+
+ nand->options &= ~NAND_OWN_BUFFERS;
+ return;
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+/* Check wait pin as dev ready indicator */
+static int am33xx_spl_dev_ready(struct mtd_info *mtd)
+{
+ return gpmc_cfg->status & (1 << 8);
+}
+#endif
+
+/*
+ * Board-specific NAND initialization. The following members of the
+ * argument are board-specific:
+ * - IO_ADDR_R: address to read the 8 I/O lines of the flash device
+ * - IO_ADDR_W: address to write the 8 I/O lines of the flash device
+ * - cmd_ctrl: hardwarespecific function for accesing control-lines
+ * - waitfunc: hardwarespecific function for accesing device ready/busy line
+ * - ecc.hwctl: function to enable (reset) hardware ecc generator
+ * - ecc.mode: mode of ecc, see defines
+ * - chip_delay: chip dependent delay for transfering data from array to
+ * read regs (tR)
+ * - options: various chip options. They can partly be set to inform
+ * nand_scan about special functionality. See the defines for further
+ * explanation
+ */
+int board_nand_init(struct nand_chip *nand)
+{
+ /* int32_t gpmc_config = 0; */
+ cs = 0;
+
+ /*
+ * xloader/Uboot's gpmc configuration would have configured GPMC for
+ * nand type of memory. The following logic scans and latches on to the
+ * first CS with NAND type memory.
+ * TBD: need to make this logic generic to handle multiple CS NAND
+ * devices.
+ */
+ while (cs < GPMC_MAX_CS) {
+ /* Check if NAND type is set */
+ if ((readl(&gpmc_cfg->cs[cs].config1) & 0xC00) == 0x800) {
+ /* Found it!! */
+ debug("Searching for NAND device @ GPMC CS:%d\n", cs);
+ break;
+ }
+ cs++;
+ }
+ if (cs >= GPMC_MAX_CS) {
+ printf("NAND: Unable to find NAND settings in "
+ "GPMC Configuration - quitting\n");
+ return -ENODEV;
+ }
+
+ nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
+ nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
+
+ nand->cmd_ctrl = am33xx_nand_hwcontrol;
+ nand->options = NAND_NO_PADDING | NAND_CACHEPRG | NAND_NO_AUTOINCR;
+ /* If we are 16 bit dev, our gpmc config tells us that */
+ if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000) {
+ nand->options |= NAND_BUSWIDTH_16;
+ }
+
+ nand->chip_delay = 100;
+
+ /* required in case of BCH */
+ elm_init();
+
+ /* BCH info that will be correct for SPL or overridden otherwise. */
+ nand->priv = &bch_priv;
+
+#ifndef CONFIG_SPL_BUILD
+ /* For undocumented reasons we need to currently keep our environment
+ * in 1-bit ECC so we configure ourself thusly. */
+ nand_curr_device = 0;
+ am33xx_nand_switch_ecc(NAND_ECC_HW, 0);
+#else
+ /* The NAND chip present requires that we have written data in with
+ * at least 4-bit ECC so we configure outself for that in SPL.
+ */
+ nand->ecc.mode = NAND_ECC_HW_SYNDROME;
+ nand->ecc.layout = &hw_bch8_nand_oob;
+ nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
+ nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
+ nand->ecc.steps = CONFIG_SYS_NAND_ECCSTEPS;
+ nand->ecc.total = CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS;
+ nand->ecc.hwctl = am33xx_enable_ecc_bch;
+ nand->ecc.correct = am33xx_correct_data_bch;
+ nand->ecc.calculate = am33xx_calculate_ecc_bch;
+
+#if 1
+ if (nand->options & NAND_BUSWIDTH_16)
+ nand->read_buf = nand_read_buf16;
+ else
+ nand->read_buf = nand_read_buf;
+#else
+ nand_scan_ident(&nand_info[nand_curr_device], 1, NULL);
+#endif
+ nand->dev_ready = am33xx_spl_dev_ready;
+
+ am33xx_hwecc_init_bch(nand, NAND_ECC_READ);
+#endif
+
+ return 0;
+}
int ret = 0;
uint32_t readlen = ops->len;
uint32_t oobreadlen = ops->ooblen;
- uint32_t max_oobsize = ops->mode == MTD_OOB_AUTO ?
- mtd->oobavail : mtd->oobsize;
-
uint8_t *bufpoi, *oob, *buf;
stats = mtd->ecc_stats;
buf += bytes;
if (unlikely(oob)) {
-
- int toread = min(oobreadlen, max_oobsize);
-
+ /* Raw mode does data:oob:data:oob */
+ if (ops->mode != MTD_OOB_RAW) {
+ int toread = min(oobreadlen,
+ chip->ecc.layout->oobavail);
if (toread) {
oob = nand_transfer_oob(chip,
oob, ops, toread);
oobreadlen -= toread;
}
+ } else
+ buf = nand_transfer_oob(chip,
+ buf, ops, mtd->oobsize);
}
if (!(chip->options & NAND_NO_READRDY)) {
return NULL;
}
-#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
-
/**
* nand_do_write_ops - [Internal] NAND write with ECC
* @mtd: MTD device structure
*/
int nand_scan_tail(struct mtd_info *mtd)
{
+ uint32_t dev_width;
int i;
struct nand_chip *chip = mtd->priv;
/* Set the internal oob buffer location, just after the page data */
chip->oob_poi = chip->buffers->databuf + mtd->writesize;
+ dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1;
+
/*
* If no default placement scheme is given, select an appropriate one
*/
projects / karo-tx-uboot.git / commitdiff