ARM: keystone2: Use common structure for PLLs
authorLokesh Vutla <lokeshvutla@ti.com>
Tue, 28 Jul 2015 08:46:45 +0000 (14:16 +0530)
committerLothar Waßmann <LW@KARO-electronics.de>
Thu, 10 Sep 2015 08:19:12 +0000 (10:19 +0200)
Register Base addresses are same for PLLs in all
keystone platforms. If a PLL is not available, the corresponding
register addresses are marked as reserved.
Hence use a common definition.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
arch/arm/mach-keystone/clock-k2e.c
arch/arm/mach-keystone/clock-k2hk.c
arch/arm/mach-keystone/clock-k2l.c
arch/arm/mach-keystone/clock.c
arch/arm/mach-keystone/include/mach/clock-k2e.h
arch/arm/mach-keystone/include/mach/clock-k2hk.h
arch/arm/mach-keystone/include/mach/clock-k2l.h
arch/arm/mach-keystone/include/mach/clock.h
arch/arm/mach-keystone/include/mach/hardware-k2hk.h
arch/arm/mach-keystone/include/mach/hardware.h

index 42092e1..b23d2a5 100644 (file)
 #include <asm/arch/clock.h>
 #include <asm/arch/clock_defs.h>
 
-const struct keystone_pll_regs keystone_pll_regs[] = {
-       [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
-       [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
-       [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
-};
-
 /**
  * pll_freq_get - get pll frequency
  * Fout = Fref * NF(mult) / NR(prediv) / OD
index 96a9f72..2e36891 100644 (file)
 #include <asm/arch/clock.h>
 #include <asm/arch/clock_defs.h>
 
-const struct keystone_pll_regs keystone_pll_regs[] = {
-       [CORE_PLL]      = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
-       [PASS_PLL]      = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
-       [TETRIS_PLL]    = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
-       [DDR3A_PLL]     = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
-       [DDR3B_PLL]     = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
-};
-
 /**
  * pll_freq_get - get pll frequency
  * Fout = Fref * NF(mult) / NR(prediv) / OD
index 80c1f51..0bd0fd6 100644 (file)
 #include <asm/arch/clock.h>
 #include <asm/arch/clock_defs.h>
 
-const struct keystone_pll_regs keystone_pll_regs[] = {
-       [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
-       [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
-       [TETRIS_PLL] = {KS2_ARMPLLCTL0,  KS2_ARMPLLCTL1},
-       [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
-};
-
 /**
  * pll_freq_get - get pll frequency
  * Fout = Fref * NF(mult) / NR(prediv) / OD
index aaeef79..de5dfe1 100644 (file)
@@ -25,6 +25,14 @@ int __weak speeds[DEVSPEED_NUMSPDS] = {
        SPD800,
 };
 
+const struct keystone_pll_regs keystone_pll_regs[] = {
+       [CORE_PLL]      = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
+       [PASS_PLL]      = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
+       [TETRIS_PLL]    = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
+       [DDR3A_PLL]     = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
+       [DDR3B_PLL]     = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
+};
+
 static void wait_for_completion(const struct pll_init_data *data)
 {
        int i;
index 6f53e43..8fdc0f0 100644 (file)
@@ -50,14 +50,6 @@ extern unsigned int external_clk[ext_clk_count];
 
 #define KS2_CLK1_6     sys_clk0_6_clk
 
-/* PLL identifiers */
-enum pll_type_e {
-       CORE_PLL,
-       PASS_PLL,
-       DDR3_PLL,
-       TETRIS_PLL,
-};
-
 #define CORE_PLL_800   {CORE_PLL, 16, 1, 2}
 #define CORE_PLL_850   {CORE_PLL, 17, 1, 2}
 #define CORE_PLL_1000  {CORE_PLL, 20, 1, 2}
index c41210c..366bf0e 100644 (file)
@@ -55,15 +55,6 @@ extern unsigned int external_clk[ext_clk_count];
 
 #define KS2_CLK1_6 sys_clk0_6_clk
 
-/* PLL identifiers */
-enum pll_type_e {
-       CORE_PLL,
-       PASS_PLL,
-       TETRIS_PLL,
-       DDR3A_PLL,
-       DDR3B_PLL,
-};
-
 #define CORE_PLL_799    {CORE_PLL,     13,     1,      2}
 #define CORE_PLL_983    {CORE_PLL,     16,     1,      2}
 #define CORE_PLL_999   {CORE_PLL,      122,    15,     1}
index c145a1e..e3f005a 100644 (file)
@@ -51,14 +51,6 @@ extern unsigned int external_clk[ext_clk_count];
 
 #define KS2_CLK1_6     sys_clk0_6_clk
 
-/* PLL identifiers */
-enum pll_type_e {
-       CORE_PLL,
-       PASS_PLL,
-       TETRIS_PLL,
-       DDR3_PLL,
-};
-
 #define CORE_PLL_799   {CORE_PLL, 13, 1, 2}
 #define CORE_PLL_983   {CORE_PLL, 16, 1, 2}
 #define CORE_PLL_1000  {CORE_PLL, 114, 7, 2}
index cb2b43c..9ba4463 100644 (file)
@@ -24,7 +24,8 @@
 #include <asm/arch/clock-k2l.h>
 #endif
 
-#define MAIN_PLL CORE_PLL
+#define CORE_PLL MAIN_PLL
+#define DDR3_PLL DDR3A_PLL
 
 #include <asm/types.h>
 
@@ -44,6 +45,16 @@ enum {
        NUM_SPDS,
 };
 
+/* PLL identifiers */
+enum {
+       MAIN_PLL,
+       TETRIS_PLL,
+       PASS_PLL,
+       DDR3A_PLL,
+       DDR3B_PLL,
+       MAX_PLL_COUNT,
+};
+
 enum clk_e {
        CLK_LIST(GENERATE_ENUM)
 };
index 195c0d3..8c771dc 100644 (file)
 /* PA SS Registers */
 #define KS2_PASS_BASE                  0x02000000
 
-/* PLL control registers */
-#define KS2_DDR3BPLLCTL0               (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
-#define KS2_DDR3BPLLCTL1               (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
-
 /* Power and Sleep Controller (PSC) Domains */
 #define KS2_LPSC_MOD                   0
 #define KS2_LPSC_DUMMY1                        1
index cf32ae5..53f28ec 100644 (file)
@@ -165,6 +165,8 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_PASSPLLCTL1                        (KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
 #define KS2_DDR3APLLCTL0               (KS2_DEVICE_STATE_CTRL_BASE + 0x360)
 #define KS2_DDR3APLLCTL1               (KS2_DEVICE_STATE_CTRL_BASE + 0x364)
+#define KS2_DDR3BPLLCTL0               (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
+#define KS2_DDR3BPLLCTL1               (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
 #define KS2_ARMPLLCTL0                 (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
 #define KS2_ARMPLLCTL1                 (KS2_DEVICE_STATE_CTRL_BASE + 0x374)