ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 3

Zap the useless addr variable.

Signed-off-by: Marek Vasut <marex@denx.de>

diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index cc5db16e36725c6054430b99b02632d6b9413d65..986f0889f2523693a916ffc09a4319fa8d5d689e 100644 (file)
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -2977,7 +2977,6 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group,
        int i;
        u32 sticky_bit_chk;
        u32 min_index;
-       u32 addr;
        int left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
        int right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
        int mid;
@@ -2996,8 +2995,8 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group,
 
        dm_margin = 0;
 
-       addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
-       start_dqs = readl(addr +
+       start_dqs = readl((SDR_PHYGRP_SCCGRP_ADDRESS |
+                         SCC_MGR_IO_OUT1_DELAY_OFFSET) +
                          (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
 
        /* Per-bit deskew. */