--- /dev/null
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+/include/ "imx6qdl.dtsi"
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ next-level-cache = <&L2>;
+ operating-points = <
+ /* kHz uV */
+ 792000 1150000
+ 396000 950000
+ >;
+ clock-latency = <61036>; /* two CLK32 periods */
+ clocks = <&clks 104>, <&clks 6>, <&clks 16>,
+ <&clks 17>, <&clks 170>;
+ clock-names = "arm", "pll2_pfd2_396m", "step",
+ "pll1_sw", "pll1_sys";
+ arm-supply = <®_arm>;
+ pu-supply = <®_pu>;
+ soc-supply = <®_soc>;
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a9";
+ reg = <1>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ soc {
+ aips-bus@02000000 { /* AIPS1 */
+ spba-bus@02000000 {
+ ecspi5: ecspi@02018000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,iMX6DL-ecspi", "fsl,imx51-ecspi";
+ reg = <0x02018000 0x4000>;
+ interrupts = <0 35 0x04>;
+ clocks = <&clks 116>, <&clks 116>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+ };
+
+ iomuxc: iomuxc@020e0000 {
+ compatible = "fsl,iMX6DL-iomuxc";
+ reg = <0x020e0000 0x4000>;
+
+ /* shared pinctrl settings */
+ audmux {
+ pinctrl_audmux_1: audmux-1 {
+ fsl,pins = <
+ 18 0x80000000 /* MX6DL_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
+ 1586 0x80000000 /* MX6DL_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
+ 11 0x80000000 /* MX6DL_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
+ 3 0x80000000 /* MX6DL_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
+ >;
+ };
+ };
+
+ ecspi1 {
+ pinctrl_ecspi1_1: ecspi1grp-1 {
+ fsl,pins = <
+ 101 0x100b1 /* MX6DL_PAD_EIM_D17__ECSPI1_MISO */
+ 109 0x100b1 /* MX6DL_PAD_EIM_D18__ECSPI1_MOSI */
+ 94 0x100b1 /* MX6DL_PAD_EIM_D16__ECSPI1_SCLK */
+ >;
+ };
+ };
+
+ enet {
+ pinctrl_enet_1: enetgrp-1 {
+ fsl,pins = <
+ 695 0x1b0b0 /* MX6DL_PAD_ENET_MDIO__ENET_MDIO */
+ 756 0x1b0b0 /* MX6DL_PAD_ENET_MDC__ENET_MDC */
+ 24 0x1b0b0 /* MX6DL_PAD_RGMII_TXC__ENET_RGMII_TXC */
+ 30 0x1b0b0 /* MX6DL_PAD_RGMII_TD0__ENET_RGMII_TD0 */
+ 34 0x1b0b0 /* MX6DL_PAD_RGMII_TD1__ENET_RGMII_TD1 */
+ 39 0x1b0b0 /* MX6DL_PAD_RGMII_TD2__ENET_RGMII_TD2 */
+ 44 0x1b0b0 /* MX6DL_PAD_RGMII_TD3__ENET_RGMII_TD3 */
+ 56 0x1b0b0 /* MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
+ 702 0x1b0b0 /* MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK */
+ 74 0x1b0b0 /* MX6DL_PAD_RGMII_RXC__ENET_RGMII_RXC */
+ 52 0x1b0b0 /* MX6DL_PAD_RGMII_RD0__ENET_RGMII_RD0 */
+ 61 0x1b0b0 /* MX6DL_PAD_RGMII_RD1__ENET_RGMII_RD1 */
+ 66 0x1b0b0 /* MX6DL_PAD_RGMII_RD2__ENET_RGMII_RD2 */
+ 70 0x1b0b0 /* MX6DL_PAD_RGMII_RD3__ENET_RGMII_RD3 */
+ 48 0x1b0b0 /* MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
+ 1033 0x4001b0a8 /* MX6DL_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT*/
+ >;
+ };
+
+ pinctrl_enet_2: enetgrp-2 {
+ fsl,pins = <
+ 890 0x1b0b0 /* MX6DL_PAD_KEY_COL1__ENET_MDIO */
+ 909 0x1b0b0 /* MX6DL_PAD_KEY_COL2__ENET_MDC */
+ 24 0x1b0b0 /* MX6DL_PAD_RGMII_TXC__ENET_RGMII_TXC */
+ 30 0x1b0b0 /* MX6DL_PAD_RGMII_TD0__ENET_RGMII_TD0 */
+ 34 0x1b0b0 /* MX6DL_PAD_RGMII_TD1__ENET_RGMII_TD1 */
+ 39 0x1b0b0 /* MX6DL_PAD_RGMII_TD2__ENET_RGMII_TD2 */
+ 44 0x1b0b0 /* MX6DL_PAD_RGMII_TD3__ENET_RGMII_TD3 */
+ 56 0x1b0b0 /* MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
+ 702 0x1b0b0 /* MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK */
+ 74 0x1b0b0 /* MX6DL_PAD_RGMII_RXC__ENET_RGMII_RXC */
+ 52 0x1b0b0 /* MX6DL_PAD_RGMII_RD0__ENET_RGMII_RD0 */
+ 61 0x1b0b0 /* MX6DL_PAD_RGMII_RD1__ENET_RGMII_RD1 */
+ 66 0x1b0b0 /* MX6DL_PAD_RGMII_RD2__ENET_RGMII_RD2 */
+ 70 0x1b0b0 /* MX6DL_PAD_RGMII_RD3__ENET_RGMII_RD3 */
+ 48 0x1b0b0 /* MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
+ >;
+ };
+ };
+
+ gpmi-nand {
+ pinctrl_gpmi_nand_1: gpmi-nand-1 {
+ fsl,pins = <
+ 1328 0xb0b1 /* MX6DL_PAD_NANDF_CLE__RAWNAND_CLE */
+ 1336 0xb0b1 /* MX6DL_PAD_NANDF_ALE__RAWNAND_ALE */
+ 1344 0xb0b1 /* MX6DL_PAD_NANDF_WP_B__RAWNAND_RESETN */
+ 1352 0xb000 /* MX6DL_PAD_NANDF_RB0__RAWNAND_READY0 */
+ 1360 0xb0b1 /* MX6DL_PAD_NANDF_CS0__RAWNAND_CE0N */
+ 1365 0xb0b1 /* MX6DL_PAD_NANDF_CS1__RAWNAND_CE1N */
+ 1371 0xb0b1 /* MX6DL_PAD_NANDF_CS2__RAWNAND_CE2N */
+ 1378 0xb0b1 /* MX6DL_PAD_NANDF_CS3__RAWNAND_CE3N */
+ 1387 0xb0b1 /* MX6DL_PAD_SD4_CMD__RAWNAND_RDN */
+ 1393 0xb0b1 /* MX6DL_PAD_SD4_CLK__RAWNAND_WRN */
+ 1397 0xb0b1 /* MX6DL_PAD_NANDF_D0__RAWNAND_D0 */
+ 1405 0xb0b1 /* MX6DL_PAD_NANDF_D1__RAWNAND_D1 */
+ 1413 0xb0b1 /* MX6DL_PAD_NANDF_D2__RAWNAND_D2 */
+ 1421 0xb0b1 /* MX6DL_PAD_NANDF_D3__RAWNAND_D3 */
+ 1429 0xb0b1 /* MX6DL_PAD_NANDF_D4__RAWNAND_D4 */
+ 1437 0xb0b1 /* MX6DL_PAD_NANDF_D5__RAWNAND_D5 */
+ 1445 0xb0b1 /* MX6DL_PAD_NANDF_D6__RAWNAND_D6 */
+ 1453 0xb0b1 /* MX6DL_PAD_NANDF_D7__RAWNAND_D7 */
+ 1463 0x00b1 /* MX6DL_PAD_SD4_DAT0__RAWNAND_DQS */
+ >;
+ };
+ };
+
+ i2c1 {
+ pinctrl_i2c1_1: i2c1grp-1 {
+ fsl,pins = <
+ 137 0x4001b8b1 /* MX6DL_PAD_EIM_D21__I2C1_SCL */
+ 196 0x4001b8b1 /* MX6DL_PAD_EIM_D28__I2C1_SDA */
+ >;
+ };
+ };
+
+ uart1 {
+ pinctrl_uart1_1: uart1grp-1 {
+ fsl,pins = <
+ 1140 0x1b0b1 /* MX6DL_PAD_CSI0_DAT10__UART1_TXD */
+ 1148 0x1b0b1 /* MX6DL_PAD_CSI0_DAT11__UART1_RXD */
+ >;
+ };
+ pinctrl_uart1_2: uart1-grp-2 {
+ fsl,pins = <
+ 120 0x1b0b1 /* MX6DL_PAD_EIM_D19__UART1_CTS */
+ 128 0x1b0b1 /* MX6DL_PAD_EIM_D20__UART1_RTS */
+ >;
+ };
+
+ pinctrl_uart1_3: uart1grp-3 {
+ fsl,pins = <
+ 1242 0x1b0b1 /* MX6DL_PAD_SD3_DAT7__UART1_TXD */
+ 1250 0x1b0b1 /* MX6DL_PAD_SD3_DAT6__UART1_RXD */
+ >;
+ };
+ pinctrl_uart1_4: uart1-grp-4 {
+ fsl,pins = <
+ 1290 0x1b0b1 /* MX6DL_PAD_SD3_DAT0__UART1_CTS */
+ 1298 0x1b0b1 /* MX6DL_PAD_SD3_DAT1__UART1_RTS */
+ >;
+ };
+ };
+
+ uart2 {
+ pinctrl_uart2_1: uart2grp-1 {
+ fsl,pins = <
+ 183 0x1b0b1 /* MX6DL_PAD_EIM_D26__UART2_TXD */
+ 191 0x1b0b1 /* MX6DL_PAD_EIM_D27__UART2_RXD */
+ >;
+ };
+ pinctrl_uart2_2: uart2grp-2 {
+ fsl,pins = <
+ 199 0x1b0b1 /* MX6DL_PAD_EIM_D28__UART2_CTS */
+ 206 0x1b0b1 /* MX6DL_PAD_EIM_D29__UART2_RTS */
+ >;
+ };
+
+ pinctrl_uart2_3: uart2grp-3 {
+ fsl,pins = <
+ 1258 0x1b0b1 /* MX6DL_PAD_SD3_DAT5__UART2_TXD */
+ 1266 0x1b0b1 /* MX6DL_PAD_SD3_DAT6__UART2_RXD */
+ >;
+ };
+ pinctrl_uart2_4: uart2grp-4 {
+ fsl,pins = <
+ 1274 0x1b0b1 /* MX6DL_PAD_SD3_CMD__UART2_CTS */
+ 1282 0x1b0b1 /* MX6DL_PAD_SD3_CLK__UART2_RTS */
+ >;
+ };
+
+ pinctrl_uart2_5: uart2grp-5 {
+ fsl,pins = <
+ 1518 0x1b0b1 /* MX6DL_PAD_SD4_DAT7__UART2_TXD */
+ 1494 0x1b0b1 /* MX6DL_PAD_SD4_DAT4__UART2_RXD */
+ >;
+ };
+ pinctrl_uart2_6: uart2grp-6 {
+ fsl,pins = <
+ 1510 0x1b0b1 /* MX6DL_PAD_SD4_DAT6__UART2_CTS */
+ 1502 0x1b0b1 /* MX6DL_PAD_SD4_DAT5__UART2_RTS */
+ >;
+ };
+
+ pinctrl_uart2_7: uart2grp-7 {
+ fsl,pins = <
+ 1019 0x1b0b1 /* MX6DL_PAD_GPIO_7__UART2_TXD */
+ 1027 0x1b0b1 /* MX6DL_PAD_GPIO_8__UART2_RXD */
+ >;
+ };
+ };
+
+ uart3 {
+ pinctrl_uart3_1: uart3grp-1 {
+ fsl,pins = <
+ 165 0x1b0b1 /* MX6DL_PAD_EIM_D24__UART3_TXD */
+ 173 0x1b0b1 /* MX6DL_PAD_EIM_D25__UART3_RXD */
+ >;
+ };
+ pinctrl_uart3_2: uart3grp-2 {
+ fsl,pins = <
+ 149 0x1b0b1 /* MX6DL_PAD_EIM_D23__UART3_CTS */
+ 157 0x1b0b1 /* MX6DL_PAD_EIM_EB3__UART3_RTS */
+ >;
+ };
+
+ pinctrl_uart3_3: uart3grp-3 {
+ fsl,pins = <
+ 1388 0x1b0b1 /* MX6DL_PAD_SD4_CMD__UART3_TXD */
+ 1394 0x1b0b1 /* MX6DL_PAD_SD4_CLK__UART3_RXD */
+ >;
+ };
+ pinctrl_uart3_4: uart3grp-4 {
+ fsl,pins = <
+ 1313 0x1b0b1 /* MX6DL_PAD_SD3_DAT3__UART3_CTS */
+ 1321 0x1b0b1 /* MX6DL_PAD_SD3_RST__UART3_RTS */
+ >;
+ };
+
+ pinctrl_uart3_5: uart3grp-5 {
+ fsl,pins = <
+ 214 0x1b0b1 /* MX6DL_PAD_EIM_D30__UART3_CTS */
+ 222 0x1b0b1 /* MX6DL_PAD_EIM_D31__UART3_RTS */
+ >;
+ };
+ };
+
+ uart4 {
+ pinctrl_uart4_1: uart4grp-1 {
+ fsl,pins = <
+ 877 0x1b0b1 /* MX6DL_PAD_KEY_COL0__UART4_TXD */
+ 885 0x1b0b1 /* MX6DL_PAD_KEY_ROW0__UART4_RXD */
+ >;
+ };
+ };
+
+ usbotg {
+ pinctrl_usbotg_1: usbotggrp-1 {
+ fsl,pins = <
+ 1592 0x17059 /* MX6DL_PAD_GPIO_1__ANATOP_USBOTG_ID */
+ >;
+ };
+ };
+
+ usdhc1 {
+ pinctrl_usdhc1_1: usdhc1grp-1 {
+ fsl,pins = <
+ 1548 0x17059 /* MX6DL_PAD_SD1_CMD__USDHC1_CMD */
+ 1562 0x10059 /* MX6DL_PAD_SD1_CLK__USDHC1_CLK */
+ 1532 0x17059 /* MX6DL_PAD_SD1_DAT0__USDHC1_DAT0 */
+ 1524 0x17059 /* MX6DL_PAD_SD1_DAT1__USDHC1_DAT1 */
+ 1554 0x17059 /* MX6DL_PAD_SD1_DAT2__USDHC1_DAT2 */
+ 1540 0x17059 /* MX6DL_PAD_SD1_DAT3__USDHC1_DAT3 */
+ 1398 0x17059 /* MX6DL_PAD_NANDF_D0__USDHC1_DAT4 */
+ 1406 0x17059 /* MX6DL_PAD_NANDF_D1__USDHC1_DAT5 */
+ 1414 0x17059 /* MX6DL_PAD_NANDF_D2__USDHC1_DAT6 */
+ 1422 0x17059 /* MX6DL_PAD_NANDF_D3__USDHC1_DAT7 */
+ >;
+ };
+
+ pinctrl_usdhc1_2: usdhc1grp-2 {
+ fsl,pins = <
+ 1548 0x17059 /* MX6DL_PAD_SD1_CMD__USDHC1_CMD */
+ 1562 0x10059 /* MX6DL_PAD_SD1_CLK__USDHC1_CLK */
+ 1532 0x17059 /* MX6DL_PAD_SD1_DAT0__USDHC1_DAT0 */
+ 1524 0x17059 /* MX6DL_PAD_SD1_DAT1__USDHC1_DAT1 */
+ 1554 0x17059 /* MX6DL_PAD_SD1_DAT2__USDHC1_DAT2 */
+ 1540 0x17059 /* MX6DL_PAD_SD1_DAT3__USDHC1_DAT3 */
+ >;
+ };
+ };
+
+ usdhc2 {
+ pinctrl_usdhc2_1: usdhc2grp-1 {
+ fsl,pins = <
+ 1577 0x17059 /* MX6DL_PAD_SD2_CMD__USDHC2_CMD */
+ 1569 0x10059 /* MX6DL_PAD_SD2_CLK__USDHC2_CLK */
+ 16 0x17059 /* MX6DL_PAD_SD2_DAT0__USDHC2_DAT0 */
+ 0 0x17059 /* MX6DL_PAD_SD2_DAT1__USDHC2_DAT1 */
+ 8 0x17059 /* MX6DL_PAD_SD2_DAT2__USDHC2_DAT2 */
+ 1583 0x17059 /* MX6DL_PAD_SD2_DAT3__USDHC2_DAT3 */
+ 1430 0x17059 /* MX6DL_PAD_NANDF_D4__USDHC2_DAT4 */
+ 1438 0x17059 /* MX6DL_PAD_NANDF_D5__USDHC2_DAT5 */
+ 1446 0x17059 /* MX6DL_PAD_NANDF_D6__USDHC2_DAT6 */
+ 1454 0x17059 /* MX6DL_PAD_NANDF_D7__USDHC2_DAT7 */
+ >;
+ };
+
+ pinctrl_usdhc2_2: usdhc2grp-2 {
+ fsl,pins = <
+ 1577 0x17059 /* MX6DL_PAD_SD2_CMD__USDHC2_CMD */
+ 1569 0x10059 /* MX6DL_PAD_SD2_CLK__USDHC2_CLK */
+ 16 0x17059 /* MX6DL_PAD_SD2_DAT0__USDHC2_DAT0 */
+ 0 0x17059 /* MX6DL_PAD_SD2_DAT1__USDHC2_DAT1 */
+ 8 0x17059 /* MX6DL_PAD_SD2_DAT2__USDHC2_DAT2 */
+ 1583 0x17059 /* MX6DL_PAD_SD2_DAT3__USDHC2_DAT3 */
+ >;
+ };
+ };
+
+ usdhc3 {
+ pinctrl_usdhc3_1: usdhc3grp-1 {
+ fsl,pins = <
+ 1273 0x17059 /* MX6DL_PAD_SD3_CMD__USDHC3_CMD */
+ 1281 0x10059 /* MX6DL_PAD_SD3_CLK__USDHC3_CLK */
+ 1289 0x17059 /* MX6DL_PAD_SD3_DAT0__USDHC3_DAT0 */
+ 1297 0x17059 /* MX6DL_PAD_SD3_DAT1__USDHC3_DAT1 */
+ 1305 0x17059 /* MX6DL_PAD_SD3_DAT2__USDHC3_DAT2 */
+ 1312 0x17059 /* MX6DL_PAD_SD3_DAT3__USDHC3_DAT3 */
+ 1265 0x17059 /* MX6DL_PAD_SD3_DAT4__USDHC3_DAT4 */
+ 1257 0x17059 /* MX6DL_PAD_SD3_DAT5__USDHC3_DAT5 */
+ 1249 0x17059 /* MX6DL_PAD_SD3_DAT6__USDHC3_DAT6 */
+ 1241 0x17059 /* MX6DL_PAD_SD3_DAT7__USDHC3_DAT7 */
+ >;
+ };
+
+ pinctrl_usdhc3_2: usdhc3grp-2 {
+ fsl,pins = <
+ 1273 0x17059 /* MX6DL_PAD_SD3_CMD__USDHC3_CMD */
+ 1281 0x10059 /* MX6DL_PAD_SD3_CLK__USDHC3_CLK */
+ 1289 0x17059 /* MX6DL_PAD_SD3_DAT0__USDHC3_DAT0 */
+ 1297 0x17059 /* MX6DL_PAD_SD3_DAT1__USDHC3_DAT1 */
+ 1305 0x17059 /* MX6DL_PAD_SD3_DAT2__USDHC3_DAT2 */
+ 1312 0x17059 /* MX6DL_PAD_SD3_DAT3__USDHC3_DAT3 */
+ >;
+ };
+ };
+
+ usdhc4 {
+ pinctrl_usdhc4_1: usdhc4grp-1 {
+ fsl,pins = <
+ 1386 0x17059 /* MX6DL_PAD_SD4_CMD__USDHC4_CMD */
+ 1392 0x10059 /* MX6DL_PAD_SD4_CLK__USDHC4_CLK */
+ 1462 0x17059 /* MX6DL_PAD_SD4_DAT0__USDHC4_DAT0 */
+ 1470 0x17059 /* MX6DL_PAD_SD4_DAT1__USDHC4_DAT1 */
+ 1478 0x17059 /* MX6DL_PAD_SD4_DAT2__USDHC4_DAT2 */
+ 1486 0x17059 /* MX6DL_PAD_SD4_DAT3__USDHC4_DAT3 */
+ 1493 0x17059 /* MX6DL_PAD_SD4_DAT4__USDHC4_DAT4 */
+ 1501 0x17059 /* MX6DL_PAD_SD4_DAT5__USDHC4_DAT5 */
+ 1509 0x17059 /* MX6DL_PAD_SD4_DAT6__USDHC4_DAT6 */
+ 1517 0x17059 /* MX6DL_PAD_SD4_DAT7__USDHC4_DAT7 */
+ >;
+ };
+
+ pinctrl_usdhc4_2: usdhc4grp-2 {
+ fsl,pins = <
+ 1386 0x17059 /* MX6DL_PAD_SD4_CMD__USDHC4_CMD */
+ 1392 0x10059 /* MX6DL_PAD_SD4_CLK__USDHC4_CLK */
+ 1462 0x17059 /* MX6DL_PAD_SD4_DAT0__USDHC4_DAT0 */
+ 1470 0x17059 /* MX6DL_PAD_SD4_DAT1__USDHC4_DAT1 */
+ 1478 0x17059 /* MX6DL_PAD_SD4_DAT2__USDHC4_DAT2 */
+ 1486 0x17059 /* MX6DL_PAD_SD4_DAT3__USDHC4_DAT3 */
+ >;
+ };
+ };
+ };
+ };
+
+ ipu2: ipu@02800000 {
+ #crtc-cells = <1>;
+ compatible = "fsl,iMX6DL-ipu";
+ reg = <0x02800000 0x400000>;
+ interrupts = <0 8 0x4 0 7 0x4>;
+ clocks = <&clks 133>, <&clks 134>, <&clks 137>;
+ clock-names = "bus", "di0", "di1";
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Auto Generate file, please don't edit it
+ *
+ */
+
+#ifndef __MACH_IOMUX_MX6DL_H__
+#define __MACH_IOMUX_MX6DL_H__
+
+#include <asm/arch/iomux-v3.h>
+
+/*
+ * Use to set PAD control
+ */
+#define MX6_PAD_CTL_HYS (1 << 16)
+
+#define MX6_PAD_CTL_PUS_100K_DOWN (MX6_PAD_CTL_PULL | (0 << 14))
+#define MX6_PAD_CTL_PUS_47K_UP (MX6_PAD_CTL_PULL | (1 << 14))
+#define MX6_PAD_CTL_PUS_100K_UP (MX6_PAD_CTL_PULL | (2 << 14))
+#define MX6_PAD_CTL_PUS_22K_UP (MX6_PAD_CTL_PULL | (3 << 14))
+
+#define MX6_PAD_CTL_PULL (MX6_PAD_CTL_PKE | MX6_PAD_CTL_PUE)
+#define MX6_PAD_CTL_PUE (1 << 13)
+#define MX6_PAD_CTL_PKE (1 << 12)
+#define MX6_PAD_CTL_ODE (1 << 11)
+
+#define MX6_PAD_CTL_SPEED_LOW (1 << 6)
+#define MX6_PAD_CTL_SPEED_MED (2 << 6)
+#define MX6_PAD_CTL_SPEED_HIGH (3 << 6)
+
+#define MX6_PAD_CTL_DSE_DISABLE (0 << 3)
+#define MX6_PAD_CTL_DSE_240ohm (1 << 3)
+#define MX6_PAD_CTL_DSE_120ohm (2 << 3)
+#define MX6_PAD_CTL_DSE_80ohm (3 << 3)
+#define MX6_PAD_CTL_DSE_60ohm (4 << 3)
+#define MX6_PAD_CTL_DSE_48ohm (5 << 3)
+#define MX6_PAD_CTL_DSE_40ohm (6 << 3)
+#define MX6_PAD_CTL_DSE_34ohm (7 << 3)
+
+#define MX6_PAD_CTL_SRE_FAST (1 << 0)
+#define MX6_PAD_CTL_SRE_SLOW (0 << 0)
+
+#define MX6DL_CCM_CLK0_PAD_CTRL (MX6_PAD_CTL_PKE | MX6_PAD_CTL_PUE | \
+ MX6_PAD_CTL_PUS_47K_UP | MX6_PAD_CTL_SPEED_LOW | \
+ MX6_PAD_CTL_DSE_80ohm | MX6_PAD_CTL_SRE_FAST | MX6_PAD_CTL_HYS)
+
+#define MX6DL_MLB150_PAD_CTRL (MX6_PAD_CTL_SPEED_LOW | \
+ MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_SRE_FAST) \
+
+#define MX6DL_UART_PAD_CTRL (MX6_PAD_CTL_PKE | MX6_PAD_CTL_PUE | \
+ MX6_PAD_CTL_PUS_100K_UP | MX6_PAD_CTL_SPEED_MED | \
+ MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_SRE_FAST | MX6_PAD_CTL_HYS)
+
+#define MX6DL_USDHC_PAD_CTRL (MX6_PAD_CTL_PKE | MX6_PAD_CTL_PUE | \
+ MX6_PAD_CTL_PUS_22K_UP | MX6_PAD_CTL_SPEED_LOW | \
+ MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_SRE_FAST | MX6_PAD_CTL_HYS)
+
+#define MX6DL_USDHC_PAD_CTRL_50MHZ_40OHM (MX6_PAD_CTL_PKE | MX6_PAD_CTL_PUE | \
+ MX6_PAD_CTL_PUS_47K_UP | MX6_PAD_CTL_SPEED_LOW | \
+ MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_SRE_FAST | MX6_PAD_CTL_HYS)
+
+#define MX6DL_USDHC_PAD_CTRL_100MHZ (MX6_PAD_CTL_PKE | MX6_PAD_CTL_PUE | \
+ MX6_PAD_CTL_PUS_47K_UP | MX6_PAD_CTL_SPEED_MED | \
+ MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_SRE_FAST | MX6_PAD_CTL_HYS)
+
+#define MX6DL_USDHC_PAD_CTRL_200MHZ (MX6_PAD_CTL_PKE | MX6_PAD_CTL_PUE | \
+ MX6_PAD_CTL_PUS_47K_UP | MX6_PAD_CTL_SPEED_HIGH | \
+ MX6_PAD_CTL_DSE_34ohm | MX6_PAD_CTL_SRE_FAST | MX6_PAD_CTL_HYS)
+
+#define MX6DL_ENET_PAD_CTRL (MX6_PAD_CTL_PKE | MX6_PAD_CTL_PUE | \
+ MX6_PAD_CTL_PUS_100K_UP | MX6_PAD_CTL_SPEED_MED | \
+ MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS)
+
+#define MX6DL_ENET_REF_CLK_PAD_CTRL (MX6_PAD_CTL_PUE | \
+ MX6_PAD_CTL_PUS_100K_UP | MX6_PAD_CTL_SPEED_MED | \
+ MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_SRE_FAST)
+
+#define MX6DL_I2C_PAD_CTRL (MX6_PAD_CTL_PKE | MX6_PAD_CTL_PUE | \
+ MX6_PAD_CTL_PUS_100K_UP | MX6_PAD_CTL_SPEED_MED | \
+ MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_SRE_FAST | \
+ MX6_PAD_CTL_HYS | MX6_PAD_CTL_ODE)
+
+#define MX6DL_ESAI_PAD_CTRL (MX6_PAD_CTL_PKE | MX6_PAD_CTL_PUE | \
+ MX6_PAD_CTL_PUS_100K_UP | MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS)
+
+#define MX6DL_USB_HSIC_PAD_CTRL (MX6_PAD_CTL_PKE | MX6_PAD_CTL_PUE | \
+ MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS)
+
+#define MX6DL_ECSPI_PAD_CTRL (MX6_PAD_CTL_SRE_FAST | MX6_PAD_CTL_SPEED_MED | \
+ MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS)
+
+#define MX6DL_WEIM_NOR_PAD_CTRL (MX6_PAD_CTL_SRE_FAST | MX6_PAD_CTL_DSE_40ohm | \
+ MX6_PAD_CTL_SPEED_MED | MX6_PAD_CTL_PKE | MX6_PAD_CTL_PUE | \
+ MX6_PAD_CTL_PUS_100K_UP)
+
+#define MX6DL_ADU_PAD_CTRL (MX6_PAD_CTL_PKE | MX6_PAD_CTL_PUE | \
+ MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_PUS_100K_DOWN | \
+ MX6_PAD_CTL_HYS | MX6_PAD_CTL_SPEED_MED)
+
+#define MX6DL_GPMI_PAD_CTRL0 (MX6_PAD_CTL_PKE | MX6_PAD_CTL_PUE | MX6_PAD_CTL_PUS_100K_UP)
+#define MX6DL_GPMI_PAD_CTRL1 (MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_SPEED_MED | MX6_PAD_CTL_SRE_FAST)
+#define MX6DL_GPMI_PAD_CTRL2 (MX6DL_GPMI_PAD_CTRL0 | MX6DL_GPMI_PAD_CTRL1)
+#define MX6DL_SPDIF_OUT_PAD_CTRL (MX6_PAD_CTL_DSE_120ohm | MX6_PAD_CTL_SRE_FAST)
+
+#define ENET_IRQ_PAD_CTRL (MX6_PAD_CTL_SRE_FAST | MX6_PAD_CTL_DSE_40ohm | \
+ MX6_PAD_CTL_SPEED_MED)
+
+#define MX6DL_PAD_CSI0_DAT10__IPU1_CSI0_D_10 \
+ IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC \
+ IOMUX_PAD(0x0360, 0x004C, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT10__ECSPI2_MISO \
+ IOMUX_PAD(0x0360, 0x004C, 2, 0x07F8, 0, 0)
+#define MX6DL_PAD_CSI0_DAT10__UART1_TXD \
+ IOMUX_PAD(0x0360, 0x004C, 3, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_CSI0_DAT10__UART1_RXD \
+ IOMUX_PAD(0x0360, 0x004C, 3, 0x08FC, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 \
+ IOMUX_PAD(0x0360, 0x004C, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT10__GPIO_5_28 \
+ IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 \
+ IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT10__SIMBA_TRACE_7 \
+ IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_CSI0_DAT11__IPU1_CSI0_D_11 \
+ IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS \
+ IOMUX_PAD(0x0364, 0x0050, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT11__ECSPI2_SS0 \
+ IOMUX_PAD(0x0364, 0x0050, 2, 0x0800, 0, 0)
+#define MX6DL_PAD_CSI0_DAT11__UART1_TXD \
+ IOMUX_PAD(0x0364, 0x0050, 3, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_CSI0_DAT11__UART1_RXD \
+ IOMUX_PAD(0x0364, 0x0050, 3, 0x08FC, 1, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 \
+ IOMUX_PAD(0x0364, 0x0050, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT11__GPIO_5_29 \
+ IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 \
+ IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT11__SIMBA_TRACE_8 \
+ IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_CSI0_DAT12__IPU1_CSI0_D_12 \
+ IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT12__WEIM_WEIM_D_8 \
+ IOMUX_PAD(0x0368, 0x0054, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 \
+ IOMUX_PAD(0x0368, 0x0054, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT12__UART4_TXD \
+ IOMUX_PAD(0x0368, 0x0054, 3, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_CSI0_DAT12__UART4_RXD \
+ IOMUX_PAD(0x0368, 0x0054, 3, 0x0914, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 \
+ IOMUX_PAD(0x0368, 0x0054, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT12__GPIO_5_30 \
+ IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 \
+ IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT12__SIMBA_TRACE_9 \
+ IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_CSI0_DAT13__IPU1_CSI0_D_13 \
+ IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT13__WEIM_WEIM_D_9 \
+ IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 \
+ IOMUX_PAD(0x036C, 0x0058, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT13__UART4_TXD \
+ IOMUX_PAD(0x036C, 0x0058, 3, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_CSI0_DAT13__UART4_RXD \
+ IOMUX_PAD(0x036C, 0x0058, 3, 0x0914, 1, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 \
+ IOMUX_PAD(0x036C, 0x0058, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT13__GPIO_5_31 \
+ IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 \
+ IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT13__SIMBA_TRACE_10 \
+ IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_CSI0_DAT14__IPU1_CSI0_D_14 \
+ IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT14__WEIM_WEIM_D_10 \
+ IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 \
+ IOMUX_PAD(0x0370, 0x005C, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT14__UART5_TXD \
+ IOMUX_PAD(0x0370, 0x005C, 3, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_CSI0_DAT14__UART5_RXD \
+ IOMUX_PAD(0x0370, 0x005C, 3, 0x091C, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 \
+ IOMUX_PAD(0x0370, 0x005C, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT14__GPIO_6_0 \
+ IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 \
+ IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT14__SIMBA_TRACE_11 \
+ IOMUX_PAD(0x0370, 0x005C, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_CSI0_DAT15__IPU1_CSI0_D_15 \
+ IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT15__WEIM_WEIM_D_11 \
+ IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 \
+ IOMUX_PAD(0x0374, 0x0060, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT15__UART5_TXD \
+ IOMUX_PAD(0x0374, 0x0060, 3, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_CSI0_DAT15__UART5_RXD \
+ IOMUX_PAD(0x0374, 0x0060, 3, 0x091C, 1, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 \
+ IOMUX_PAD(0x0374, 0x0060, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT15__GPIO_6_1 \
+ IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 \
+ IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT15__SIMBA_TRACE_12 \
+ IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_CSI0_DAT16__IPU1_CSI0_D_16 \
+ IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT16__WEIM_WEIM_D_12 \
+ IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 \
+ IOMUX_PAD(0x0378, 0x0064, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT16__UART4_CTS \
+ IOMUX_PAD(0x0378, 0x0064, 3, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_CSI0_DAT16__UART4_RTS \
+ IOMUX_PAD(0x0378, 0x0064, 3, 0x0910, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 \
+ IOMUX_PAD(0x0378, 0x0064, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT16__GPIO_6_2 \
+ IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 \
+ IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT16__SIMBA_TRACE_13 \
+ IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_CSI0_DAT17__IPU1_CSI0_D_17 \
+ IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT17__WEIM_WEIM_D_13 \
+ IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 \
+ IOMUX_PAD(0x037C, 0x0068, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT17__UART4_CTS \
+ IOMUX_PAD(0x037C, 0x0068, 3, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_CSI0_DAT17__UART4_RTS \
+ IOMUX_PAD(0x037C, 0x0068, 3, 0x0910, 1, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 \
+ IOMUX_PAD(0x037C, 0x0068, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT17__GPIO_6_3 \
+ IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 \
+ IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT17__SIMBA_TRACE_14 \
+ IOMUX_PAD(0x037C, 0x0068, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_CSI0_DAT18__IPU1_CSI0_D_18 \
+ IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT18__WEIM_WEIM_D_14 \
+ IOMUX_PAD(0x0380, 0x006C, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 \
+ IOMUX_PAD(0x0380, 0x006C, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT18__UART5_CTS \
+ IOMUX_PAD(0x0380, 0x006C, 3, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_CSI0_DAT18__UART5_RTS \
+ IOMUX_PAD(0x0380, 0x006C, 3, 0x0918, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 \
+ IOMUX_PAD(0x0380, 0x006C, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT18__GPIO_6_4 \
+ IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 \
+ IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT18__SIMBA_TRACE_15 \
+ IOMUX_PAD(0x0380, 0x006C, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_CSI0_DAT19__IPU1_CSI0_D_19 \
+ IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT19__WEIM_WEIM_D_15 \
+ IOMUX_PAD(0x0384, 0x0070, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 \
+ IOMUX_PAD(0x0384, 0x0070, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT19__UART5_CTS \
+ IOMUX_PAD(0x0384, 0x0070, 3, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_CSI0_DAT19__UART5_RTS \
+ IOMUX_PAD(0x0384, 0x0070, 3, 0x0918, 1, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 \
+ IOMUX_PAD(0x0384, 0x0070, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT19__GPIO_6_5 \
+ IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 \
+ IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 \
+ IOMUX_PAD(0x0384, 0x0070, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_CSI0_DAT4__IPU1_CSI0_D_4 \
+ IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT4__WEIM_WEIM_D_2 \
+ IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT4__ECSPI1_SCLK \
+ IOMUX_PAD(0x0388, 0x0074, 2, 0x07D8, 0, 0)
+#define MX6DL_PAD_CSI0_DAT4__KPP_COL_5 \
+ IOMUX_PAD(0x0388, 0x0074, 3, 0x08C0, 0, 0)
+#define MX6DL_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC \
+ IOMUX_PAD(0x0388, 0x0074, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT4__GPIO_5_22 \
+ IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 \
+ IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT4__SIMBA_TRACE_1 \
+ IOMUX_PAD(0x0388, 0x0074, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_CSI0_DAT5__IPU1_CSI0_D_5 \
+ IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT5__WEIM_WEIM_D_3 \
+ IOMUX_PAD(0x038C, 0x0078, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT5__ECSPI1_MOSI \
+ IOMUX_PAD(0x038C, 0x0078, 2, 0x07E0, 0, 0)
+#define MX6DL_PAD_CSI0_DAT5__KPP_ROW_5 \
+ IOMUX_PAD(0x038C, 0x0078, 3, 0x08CC, 0, 0)
+#define MX6DL_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD \
+ IOMUX_PAD(0x038C, 0x0078, 4, 0x0000, 0, MX6DL_ADU_PAD_CTRL)
+#define MX6DL_PAD_CSI0_DAT5__GPIO_5_23 \
+ IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 \
+ IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT5__SIMBA_TRACE_2 \
+ IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_CSI0_DAT6__IPU1_CSI0_D_6 \
+ IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT6__WEIM_WEIM_D_4 \
+ IOMUX_PAD(0x0390, 0x007C, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT6__ECSPI1_MISO \
+ IOMUX_PAD(0x0390, 0x007C, 2, 0x07DC, 0, 0)
+#define MX6DL_PAD_CSI0_DAT6__KPP_COL_6 \
+ IOMUX_PAD(0x0390, 0x007C, 3, 0x08C4, 0, 0)
+#define MX6DL_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS \
+ IOMUX_PAD(0x0390, 0x007C, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT6__GPIO_5_24 \
+ IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 \
+ IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT6__SIMBA_TRACE_3 \
+ IOMUX_PAD(0x0390, 0x007C, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_CSI0_DAT7__IPU1_CSI0_D_7 \
+ IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT7__WEIM_WEIM_D_5 \
+ IOMUX_PAD(0x0394, 0x0080, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT7__ECSPI1_SS0 \
+ IOMUX_PAD(0x0394, 0x0080, 2, 0x07E4, 0, 0)
+#define MX6DL_PAD_CSI0_DAT7__KPP_ROW_6 \
+ IOMUX_PAD(0x0394, 0x0080, 3, 0x08D0, 0, 0)
+#define MX6DL_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD \
+ IOMUX_PAD(0x0394, 0x0080, 4, 0x0000, 0, MX6DL_ADU_PAD_CTRL)
+#define MX6DL_PAD_CSI0_DAT7__GPIO_5_25 \
+ IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 \
+ IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT7__SIMBA_TRACE_4 \
+ IOMUX_PAD(0x0394, 0x0080, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_CSI0_DAT8__IPU1_CSI0_D_8 \
+ IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT8__WEIM_WEIM_D_6 \
+ IOMUX_PAD(0x0398, 0x0084, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT8__ECSPI2_SCLK \
+ IOMUX_PAD(0x0398, 0x0084, 2, 0x07F4, 0, 0)
+#define MX6DL_PAD_CSI0_DAT8__KPP_COL_7 \
+ IOMUX_PAD(0x0398, 0x0084, 3, 0x08C8, 0, 0)
+#define MX6DL_PAD_CSI0_DAT8__I2C1_SDA \
+ IOMUX_PAD(0x0398, 0x0084, 4 | IOMUX_CONFIG_SION, 0x086C, 0, MX6DL_I2C_PAD_CTRL)
+#define MX6DL_PAD_CSI0_DAT8__GPIO_5_26 \
+ IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 \
+ IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT8__SIMBA_TRACE_5 \
+ IOMUX_PAD(0x0398, 0x0084, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_CSI0_DAT9__IPU1_CSI0_D_9 \
+ IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT9__WEIM_WEIM_D_7 \
+ IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT9__ECSPI2_MOSI \
+ IOMUX_PAD(0x039C, 0x0088, 2, 0x07FC, 0, 0)
+#define MX6DL_PAD_CSI0_DAT9__KPP_ROW_7 \
+ IOMUX_PAD(0x039C, 0x0088, 3, 0x08D4, 0, 0)
+#define MX6DL_PAD_CSI0_DAT9__I2C1_SCL \
+ IOMUX_PAD(0x039C, 0x0088, 4 | IOMUX_CONFIG_SION, 0x0868, 0, MX6DL_I2C_PAD_CTRL)
+#define MX6DL_PAD_CSI0_DAT9__GPIO_5_27 \
+ IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 \
+ IOMUX_PAD(0x039C, 0x0088, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DAT9__SIMBA_TRACE_6 \
+ IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN \
+ IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 \
+ IOMUX_PAD(0x03A0, 0x008C, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 \
+ IOMUX_PAD(0x03A0, 0x008C, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 \
+ IOMUX_PAD(0x03A0, 0x008C, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DATA_EN__GPIO_5_20 \
+ IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 \
+ IOMUX_PAD(0x03A0, 0x008C, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_DATA_EN__SIMBA_TRCLK \
+ IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC \
+ IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 \
+ IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_MCLK__CCM_CLKO \
+ IOMUX_PAD(0x03A4, 0x0090, 3, 0x0000, 0, MX6DL_CCM_CLK0_PAD_CTRL)
+#define MX6DL_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 \
+ IOMUX_PAD(0x03A4, 0x0090, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_MCLK__GPIO_5_19 \
+ IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 \
+ IOMUX_PAD(0x03A4, 0x0090, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_MCLK__SIMBA_TRCTL \
+ IOMUX_PAD(0x03A4, 0x0090, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK \
+ IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 \
+ IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 \
+ IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_PIXCLK__GPIO_5_18 \
+ IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 \
+ IOMUX_PAD(0x03A8, 0x0094, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_PIXCLK__SIMBA_EVENTO \
+ IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC \
+ IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 \
+ IOMUX_PAD(0x03AC, 0x0098, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 \
+ IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 \
+ IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_VSYNC__GPIO_5_21 \
+ IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 \
+ IOMUX_PAD(0x03AC, 0x0098, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_CSI0_VSYNC__SIMBA_TRACE_0 \
+ IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK \
+ IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_DI0_DISP_CLK__LCDIF_CLK \
+ IOMUX_PAD(0x03B0, 0x009C, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 \
+ IOMUX_PAD(0x03B0, 0x009C, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 \
+ IOMUX_PAD(0x03B0, 0x009C, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_DI0_DISP_CLK__GPIO_4_16 \
+ IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 \
+ IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_DI0_DISP_CLK__TPSMP_HDATA_DIR \
+ IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_DI0_DISP_CLK__LCDIF_WR_RWN \
+ IOMUX_PAD(0x03B0, 0x009C, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DI0_PIN15__IPU1_DI0_PIN15 \
+ IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_DI0_PIN15__LCDIF_ENABLE \
+ IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_DI0_PIN15__AUDMUX_AUD6_TXC \
+ IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 \
+ IOMUX_PAD(0x03B4, 0x00A0, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 \
+ IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_DI0_PIN15__GPIO_4_17 \
+ IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 \
+ IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_DI0_PIN15__PL301_SIM_MX6DL_PER1_HSIZE_0 \
+ IOMUX_PAD(0x03B4, 0x00A0, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_DI0_PIN15__LCDIF_RD_E \
+ IOMUX_PAD(0x03B4, 0x00A0, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DI0_PIN2__IPU1_DI0_PIN2 \
+ IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_DI0_PIN2__LCDIF_HSYNC \
+ IOMUX_PAD(0x03B8, 0x00A4, 1, 0x08D8, 0, 0)
+#define MX6DL_PAD_DI0_PIN2__AUDMUX_AUD6_TXD \
+ IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 \
+ IOMUX_PAD(0x03B8, 0x00A4, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 \
+ IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_DI0_PIN2__GPIO_4_18 \
+ IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 \
+ IOMUX_PAD(0x03B8, 0x00A4, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_DI0_PIN2__PL301_SIM_MX6DL_PER1_HADDR_9 \
+ IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_DI0_PIN2__LCDIF_RS \
+ IOMUX_PAD(0x03B8, 0x00A4, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DI0_PIN3__IPU1_DI0_PIN3 \
+ IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_DI0_PIN3__LCDIF_VSYNC \
+ IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS \
+ IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 \
+ IOMUX_PAD(0x03BC, 0x00A8, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 \
+ IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_DI0_PIN3__GPIO_4_19 \
+ IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 \
+ IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_DI0_PIN3__PL301_SIM_MX6DL_PER1_HADDR_10 \
+ IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_DI0_PIN3__LCDIF_CS \
+ IOMUX_PAD(0x03BC, 0x00A8, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DI0_PIN4__IPU1_DI0_PIN4 \
+ IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_DI0_PIN4__LCDIF_BUSY \
+ IOMUX_PAD(0x03C0, 0x00AC, 1, 0x08D8, 1, 0)
+#define MX6DL_PAD_DI0_PIN4__AUDMUX_AUD6_RXD \
+ IOMUX_PAD(0x03C0, 0x00AC, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_DI0_PIN4__USDHC1_WP \
+ IOMUX_PAD(0x03C0, 0x00AC, 3, 0x092C, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_DI0_PIN4__SDMA_DEBUG_YIELD \
+ IOMUX_PAD(0x03C0, 0x00AC, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_DI0_PIN4__GPIO_4_20 \
+ IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 \
+ IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_DI0_PIN4__PL301_SIM_MX6DL_PER1_HADDR_11 \
+ IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_DI0_PIN4__LCDIF_RESET \
+ IOMUX_PAD(0x03C0, 0x00AC, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 \
+ IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT0__LCDIF_DAT_0 \
+ IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT0__ECSPI3_SCLK \
+ IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 \
+ IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN \
+ IOMUX_PAD(0x03C4, 0x00B0, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT0__GPIO_4_21 \
+ IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 \
+ IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT0__PL301_SIM_MX6DL_PER1_HSIZE_1 \
+ IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 \
+ IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT1__LCDIF_DAT_1 \
+ IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT1__ECSPI3_MOSI \
+ IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 \
+ IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL \
+ IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT1__GPIO_4_22 \
+ IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 \
+ IOMUX_PAD(0x03C8, 0x00B4, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT1__PL301_SIM_MX6DL_PER1_HADDR_12 \
+ IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 \
+ IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT10__LCDIF_DAT_10 \
+ IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 \
+ IOMUX_PAD(0x03CC, 0x00B8, 3, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 \
+ IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT10__GPIO_4_31 \
+ IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 \
+ IOMUX_PAD(0x03CC, 0x00B8, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT10__PL301_SIM_MX6DL_PER1_HADDR_21 \
+ IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 \
+ IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT11__LCDIF_DAT_11 \
+ IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 \
+ IOMUX_PAD(0x03D0, 0x00BC, 3, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 \
+ IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT11__GPIO_5_5 \
+ IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 \
+ IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT11__PL301_SIM_MX6DL_PER1_HADDR_22 \
+ IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 \
+ IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT12__LCDIF_DAT_12 \
+ IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 \
+ IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT12__GPIO_5_6 \
+ IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 \
+ IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT12__PL301_SIM_MX6DL_PER1_HADDR_23 \
+ IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 \
+ IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT13__LCDIF_DAT_13 \
+ IOMUX_PAD(0x03D8, 0x00C4, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS \
+ IOMUX_PAD(0x03D8, 0x00C4, 3, 0x07BC, 0, 0)
+#define MX6DL_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 \
+ IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT13__GPIO_5_7 \
+ IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 \
+ IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT13__PL301_SIM_MX6DL_PER1_HADDR_24 \
+ IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 \
+ IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT14__LCDIF_DAT_14 \
+ IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC \
+ IOMUX_PAD(0x03DC, 0x00C8, 3, 0x07B8, 0, 0)
+#define MX6DL_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 \
+ IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT14__GPIO_5_8 \
+ IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 \
+ IOMUX_PAD(0x03DC, 0x00C8, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT14__PL301_SIM_MX6DL_PER1_HSIZE_2 \
+ IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 \
+ IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT15__LCDIF_DAT_15 \
+ IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT15__ECSPI1_SS1 \
+ IOMUX_PAD(0x03E0, 0x00CC, 2, 0x07E8, 0, 0)
+#define MX6DL_PAD_DISP0_DAT15__ECSPI2_SS1 \
+ IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0804, 0, 0)
+#define MX6DL_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 \
+ IOMUX_PAD(0x03E0, 0x00CC, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT15__GPIO_5_9 \
+ IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 \
+ IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT15__PL301_SIM_MX6DL_PER1_HADDR_25 \
+ IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 \
+ IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT16__LCDIF_DAT_16 \
+ IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT16__ECSPI2_MOSI \
+ IOMUX_PAD(0x03E4, 0x00D0, 2, 0x07FC, 1, 0)
+#define MX6DL_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC \
+ IOMUX_PAD(0x03E4, 0x00D0, 3, 0x07C0, 0, 0)
+#define MX6DL_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 \
+ IOMUX_PAD(0x03E4, 0x00D0, 4, 0x08E8, 0, 0)
+#define MX6DL_PAD_DISP0_DAT16__GPIO_5_10 \
+ IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 \
+ IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT16__PL301_SIM_MX6DL_PER1_HADDR_26 \
+ IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 \
+ IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT17__LCDIF_DAT_17 \
+ IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT17__ECSPI2_MISO \
+ IOMUX_PAD(0x03E8, 0x00D4, 2, 0x07F8, 1, 0)
+#define MX6DL_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD \
+ IOMUX_PAD(0x03E8, 0x00D4, 3, 0x07B4, 0, 0)
+#define MX6DL_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 \
+ IOMUX_PAD(0x03E8, 0x00D4, 4, 0x08EC, 0, 0)
+#define MX6DL_PAD_DISP0_DAT17__GPIO_5_11 \
+ IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 \
+ IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT17__PL301_SIM_MX6DL_PER1_HADDR_27 \
+ IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 \
+ IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT18__LCDIF_DAT_18 \
+ IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT18__ECSPI2_SS0 \
+ IOMUX_PAD(0x03EC, 0x00D8, 2, 0x0800, 1, 0)
+#define MX6DL_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS \
+ IOMUX_PAD(0x03EC, 0x00D8, 3, 0x07C4, 0, 0)
+#define MX6DL_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS \
+ IOMUX_PAD(0x03EC, 0x00D8, 4, 0x07A4, 0, 0)
+#define MX6DL_PAD_DISP0_DAT18__GPIO_5_12 \
+ IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 \
+ IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 \
+ IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 \
+ IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT19__LCDIF_DAT_19 \
+ IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT19__ECSPI2_SCLK \
+ IOMUX_PAD(0x03F0, 0x00DC, 2, 0x07F4, 1, 0)
+#define MX6DL_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD \
+ IOMUX_PAD(0x03F0, 0x00DC, 3, 0x07B0, 0, 0)
+#define MX6DL_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC \
+ IOMUX_PAD(0x03F0, 0x00DC, 4, 0x07A0, 0, 0)
+#define MX6DL_PAD_DISP0_DAT19__GPIO_5_13 \
+ IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 \
+ IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 \
+ IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 \
+ IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT2__LCDIF_DAT_2 \
+ IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT2__ECSPI3_MISO \
+ IOMUX_PAD(0x03F4, 0x00E0, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 \
+ IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_DISP0_DAT2__SDMA_DEBUG_MODE \
+ IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT2__GPIO_4_23 \
+ IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 \
+ IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT2__PL301_SIM_MX6DL_PER1_HADDR_13 \
+ IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 \
+ IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT20__LCDIF_DAT_20 \
+ IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT20__ECSPI1_SCLK \
+ IOMUX_PAD(0x03F8, 0x00E4, 2, 0x07D8, 1, 0)
+#define MX6DL_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC \
+ IOMUX_PAD(0x03F8, 0x00E4, 3, 0x07A8, 0, 0)
+#define MX6DL_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 \
+ IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT20__GPIO_5_14 \
+ IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 \
+ IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT20__PL301_SIM_MX6DL_PER1_HADDR_28 \
+ IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 \
+ IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT21__LCDIF_DAT_21 \
+ IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT21__ECSPI1_MOSI \
+ IOMUX_PAD(0x03FC, 0x00E8, 2, 0x07E0, 1, 0)
+#define MX6DL_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD \
+ IOMUX_PAD(0x03FC, 0x00E8, 3, 0x079C, 0, 0)
+#define MX6DL_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 \
+ IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT21__GPIO_5_15 \
+ IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 \
+ IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT21__PL301_SIM_MX6DL_PER1_HADDR_29 \
+ IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 \
+ IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT22__LCDIF_DAT_22 \
+ IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT22__ECSPI1_MISO \
+ IOMUX_PAD(0x0400, 0x00EC, 2, 0x07DC, 1, 0)
+#define MX6DL_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS \
+ IOMUX_PAD(0x0400, 0x00EC, 3, 0x07AC, 0, 0)
+#define MX6DL_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 \
+ IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT22__GPIO_5_16 \
+ IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 \
+ IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT22__PL301_SIM_MX6DL_PER1_HADDR_30 \
+ IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 \
+ IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT23__LCDIF_DAT_23 \
+ IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT23__ECSPI1_SS0 \
+ IOMUX_PAD(0x0404, 0x00F0, 2, 0x07E4, 1, 0)
+#define MX6DL_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD \
+ IOMUX_PAD(0x0404, 0x00F0, 3, 0x0798, 0, 0)
+#define MX6DL_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 \
+ IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT23__GPIO_5_17 \
+ IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 \
+ IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT23__PL301_SIM_MX6DL_PER1_HADDR_31 \
+ IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 \
+ IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT3__LCDIF_DAT_3 \
+ IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT3__ECSPI3_SS0 \
+ IOMUX_PAD(0x0408, 0x00F4, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 \
+ IOMUX_PAD(0x0408, 0x00F4, 3, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR \
+ IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT3__GPIO_4_24 \
+ IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 \
+ IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT3__PL301_SIM_MX6DL_PER1_HADDR_14 \
+ IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 \
+ IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT4__LCDIF_DAT_4 \
+ IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT4__ECSPI3_SS1 \
+ IOMUX_PAD(0x040C, 0x00F8, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 \
+ IOMUX_PAD(0x040C, 0x00F8, 3, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB \
+ IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT4__GPIO_4_25 \
+ IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 \
+ IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT4__PL301_SIM_MX6DL_PER1_HADDR_15 \
+ IOMUX_PAD(0x040C, 0x00F8, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 \
+ IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT5__LCDIF_DAT_5 \
+ IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT5__ECSPI3_SS2 \
+ IOMUX_PAD(0x0410, 0x00FC, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS \
+ IOMUX_PAD(0x0410, 0x00FC, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS \
+ IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT5__GPIO_4_26 \
+ IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 \
+ IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT5__PL301_SIM_MX6DL_PER1_HADDR_16 \
+ IOMUX_PAD(0x0410, 0x00FC, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 \
+ IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT6__LCDIF_DAT_6 \
+ IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT6__ECSPI3_SS3 \
+ IOMUX_PAD(0x0414, 0x0100, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC \
+ IOMUX_PAD(0x0414, 0x0100, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE \
+ IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT6__GPIO_4_27 \
+ IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 \
+ IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT6__PL301_SIM_MX6DL_PER1_HADDR_17 \
+ IOMUX_PAD(0x0414, 0x0100, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 \
+ IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT7__LCDIF_DAT_7 \
+ IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT7__ECSPI3_RDY \
+ IOMUX_PAD(0x0418, 0x0104, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 \
+ IOMUX_PAD(0x0418, 0x0104, 3, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 \
+ IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT7__GPIO_4_28 \
+ IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 \
+ IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT7__PL301_SIM_MX6DL_PER1_HADDR_18 \
+ IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 \
+ IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT8__LCDIF_DAT_8 \
+ IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT8__PWM1_PWMO \
+ IOMUX_PAD(0x041C, 0x0108, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT8__WDOG1_WDOG_B \
+ IOMUX_PAD(0x041C, 0x0108, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 \
+ IOMUX_PAD(0x041C, 0x0108, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT8__GPIO_4_29 \
+ IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 \
+ IOMUX_PAD(0x041C, 0x0108, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT8__PL301_SIM_MX6DL_PER1_HADDR_19 \
+ IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 \
+ IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT9__LCDIF_DAT_9 \
+ IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT9__PWM2_PWMO \
+ IOMUX_PAD(0x0420, 0x010C, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT9__WDOG2_WDOG_B \
+ IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 \
+ IOMUX_PAD(0x0420, 0x010C, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT9__GPIO_4_30 \
+ IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 \
+ IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_DISP0_DAT9__PL301_SIM_MX6DL_PER1_HADDR_20 \
+ IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_A0__MMDC_DRAM_A_0 \
+ IOMUX_PAD(0x0424, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_A1__MMDC_DRAM_A_1 \
+ IOMUX_PAD(0x0428, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_A10__MMDC_DRAM_A_10 \
+ IOMUX_PAD(0x042C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_A11__MMDC_DRAM_A_11 \
+ IOMUX_PAD(0x0430, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_A12__MMDC_DRAM_A_12 \
+ IOMUX_PAD(0x0434, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_A13__MMDC_DRAM_A_13 \
+ IOMUX_PAD(0x0438, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_A14__MMDC_DRAM_A_14 \
+ IOMUX_PAD(0x043C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_A15__MMDC_DRAM_A_15 \
+ IOMUX_PAD(0x0440, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_A2__MMDC_DRAM_A_2 \
+ IOMUX_PAD(0x0444, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_A3__MMDC_DRAM_A_3 \
+ IOMUX_PAD(0x0448, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_A4__MMDC_DRAM_A_4 \
+ IOMUX_PAD(0x044C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_A5__MMDC_DRAM_A_5 \
+ IOMUX_PAD(0x0450, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_A6__MMDC_DRAM_A_6 \
+ IOMUX_PAD(0x0454, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_A7__MMDC_DRAM_A_7 \
+ IOMUX_PAD(0x0458, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_A8__MMDC_DRAM_A_8 \
+ IOMUX_PAD(0x045C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_A9__MMDC_DRAM_A_9 \
+ IOMUX_PAD(0x0460, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_CAS__MMDC_DRAM_CAS \
+ IOMUX_PAD(0x0464, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_CS0__MMDC_DRAM_CS_0 \
+ IOMUX_PAD(0x0468, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_CS1__MMDC_DRAM_CS_1 \
+ IOMUX_PAD(0x046C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D0__MMDC_DRAM_D_0 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D1__MMDC_DRAM_D_1 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D10__MMDC_DRAM_D_10 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D11__MMDC_DRAM_D_11 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D12__MMDC_DRAM_D_12 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D13__MMDC_DRAM_D_13 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D14__MMDC_DRAM_D_14 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D15__MMDC_DRAM_D_15 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D16__MMDC_DRAM_D_16 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D17__MMDC_DRAM_D_17 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D18__MMDC_DRAM_D_18 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D19__MMDC_DRAM_D_19 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D2__MMDC_DRAM_D_2 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D20__MMDC_DRAM_D_20 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D21__MMDC_DRAM_D_21 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D22__MMDC_DRAM_D_22 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D23__MMDC_DRAM_D_23 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D24__MMDC_DRAM_D_24 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D25__MMDC_DRAM_D_25 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D26__MMDC_DRAM_D_26 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D27__MMDC_DRAM_D_27 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D28__MMDC_DRAM_D_28 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D29__MMDC_DRAM_D_29 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D3__MMDC_DRAM_D_3 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D30__MMDC_DRAM_D_30 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D31__MMDC_DRAM_D_31 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D32__MMDC_DRAM_D_32 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D33__MMDC_DRAM_D_33 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D34__MMDC_DRAM_D_34 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D35__MMDC_DRAM_D_35 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D36__MMDC_DRAM_D_36 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D37__MMDC_DRAM_D_37 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D38__MMDC_DRAM_D_38 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D39__MMDC_DRAM_D_39 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D4__MMDC_DRAM_D_4 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D40__MMDC_DRAM_D_40 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D41__MMDC_DRAM_D_41 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D42__MMDC_DRAM_D_42 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D43__MMDC_DRAM_D_43 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D44__MMDC_DRAM_D_44 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D45__MMDC_DRAM_D_45 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D46__MMDC_DRAM_D_46 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D47__MMDC_DRAM_D_47 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D48__MMDC_DRAM_D_48 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D49__MMDC_DRAM_D_49 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D5__MMDC_DRAM_D_5 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D50__MMDC_DRAM_D_50 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D51__MMDC_DRAM_D_51 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D52__MMDC_DRAM_D_52 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D53__MMDC_DRAM_D_53 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D54__MMDC_DRAM_D_54 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D55__MMDC_DRAM_D_55 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D56__MMDC_DRAM_D_56 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D57__MMDC_DRAM_D_57 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D58__MMDC_DRAM_D_58 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D59__MMDC_DRAM_D_59 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D6__MMDC_DRAM_D_6 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D60__MMDC_DRAM_D_60 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D61__MMDC_DRAM_D_61 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D62__MMDC_DRAM_D_62 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D63__MMDC_DRAM_D_63 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D7__MMDC_DRAM_D_7 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D8__MMDC_DRAM_D_8 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_D9__MMDC_DRAM_D_9 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 \
+ IOMUX_PAD(0x0470, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 \
+ IOMUX_PAD(0x0474, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 \
+ IOMUX_PAD(0x0478, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 \
+ IOMUX_PAD(0x047C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 \
+ IOMUX_PAD(0x0480, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 \
+ IOMUX_PAD(0x0484, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 \
+ IOMUX_PAD(0x0488, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 \
+ IOMUX_PAD(0x048C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_RAS__MMDC_DRAM_RAS \
+ IOMUX_PAD(0x0490, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_RESET__MMDC_DRAM_RESET \
+ IOMUX_PAD(0x0494, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 \
+ IOMUX_PAD(0x0498, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 \
+ IOMUX_PAD(0x049C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 \
+ IOMUX_PAD(0x04A0, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 \
+ IOMUX_PAD(0x04A4, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 \
+ IOMUX_PAD(0x04A8, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 \
+ IOMUX_PAD(0x04AC, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 \
+ IOMUX_PAD(0x04B0, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 \
+ IOMUX_PAD(0x04B4, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 \
+ IOMUX_PAD(0x04B8, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 \
+ IOMUX_PAD(0x04BC, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 \
+ IOMUX_PAD(0x04C0, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 \
+ IOMUX_PAD(0x04C4, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 \
+ IOMUX_PAD(0x04C8, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 \
+ IOMUX_PAD(0x04CC, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 \
+ IOMUX_PAD(0x04D0, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 \
+ IOMUX_PAD(0x04D4, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 \
+ IOMUX_PAD(0x04D8, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_DRAM_SDWE__MMDC_DRAM_SDWE \
+ IOMUX_PAD(0x04DC, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_A16__WEIM_WEIM_A_16 \
+ IOMUX_PAD(0x04E0, 0x0110, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_A16__IPU1_DI1_DISP_CLK \
+ IOMUX_PAD(0x04E0, 0x0110, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A16__IPU1_CSI1_PIXCLK \
+ IOMUX_PAD(0x04E0, 0x0110, 2, 0x08B8, 0, 0)
+#define MX6DL_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 \
+ IOMUX_PAD(0x04E0, 0x0110, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A16__GPIO_2_22 \
+ IOMUX_PAD(0x04E0, 0x0110, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A16__TPSMP_HDATA_6 \
+ IOMUX_PAD(0x04E0, 0x0110, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A16__SRC_BT_CFG_16 \
+ IOMUX_PAD(0x04E0, 0x0110, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A16__EPDC_SDDO_0 \
+ IOMUX_PAD(0x04E0, 0x0110, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_A17__WEIM_WEIM_A_17 \
+ IOMUX_PAD(0x04E4, 0x0114, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_A17__IPU1_DISP1_DAT_12 \
+ IOMUX_PAD(0x04E4, 0x0114, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A17__IPU1_CSI1_D_12 \
+ IOMUX_PAD(0x04E4, 0x0114, 2, 0x0890, 0, 0)
+#define MX6DL_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 \
+ IOMUX_PAD(0x04E4, 0x0114, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A17__GPIO_2_21 \
+ IOMUX_PAD(0x04E4, 0x0114, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A17__TPSMP_HDATA_5 \
+ IOMUX_PAD(0x04E4, 0x0114, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A17__SRC_BT_CFG_17 \
+ IOMUX_PAD(0x04E4, 0x0114, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A17__EPDC_PWRSTAT \
+ IOMUX_PAD(0x04E4, 0x0114, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_A18__WEIM_WEIM_A_18 \
+ IOMUX_PAD(0x04E8, 0x0118, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_A18__IPU1_DISP1_DAT_13 \
+ IOMUX_PAD(0x04E8, 0x0118, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A18__IPU1_CSI1_D_13 \
+ IOMUX_PAD(0x04E8, 0x0118, 2, 0x0894, 0, 0)
+#define MX6DL_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 \
+ IOMUX_PAD(0x04E8, 0x0118, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A18__GPIO_2_20 \
+ IOMUX_PAD(0x04E8, 0x0118, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A18__TPSMP_HDATA_4 \
+ IOMUX_PAD(0x04E8, 0x0118, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A18__SRC_BT_CFG_18 \
+ IOMUX_PAD(0x04E8, 0x0118, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A18__EPDC_PWRCTRL_0 \
+ IOMUX_PAD(0x04E8, 0x0118, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_A19__WEIM_WEIM_A_19 \
+ IOMUX_PAD(0x04EC, 0x011C, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_A19__IPU1_DISP1_DAT_14 \
+ IOMUX_PAD(0x04EC, 0x011C, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A19__IPU1_CSI1_D_14 \
+ IOMUX_PAD(0x04EC, 0x011C, 2, 0x0898, 0, 0)
+#define MX6DL_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 \
+ IOMUX_PAD(0x04EC, 0x011C, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A19__GPIO_2_19 \
+ IOMUX_PAD(0x04EC, 0x011C, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A19__TPSMP_HDATA_3 \
+ IOMUX_PAD(0x04EC, 0x011C, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A19__SRC_BT_CFG_19 \
+ IOMUX_PAD(0x04EC, 0x011C, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A19__EPDC_PWRCTRL_1 \
+ IOMUX_PAD(0x04EC, 0x011C, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_A20__WEIM_WEIM_A_20 \
+ IOMUX_PAD(0x04F0, 0x0120, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_A20__IPU1_DISP1_DAT_15 \
+ IOMUX_PAD(0x04F0, 0x0120, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A20__IPU1_CSI1_D_15 \
+ IOMUX_PAD(0x04F0, 0x0120, 2, 0x089C, 0, 0)
+#define MX6DL_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 \
+ IOMUX_PAD(0x04F0, 0x0120, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A20__GPIO_2_18 \
+ IOMUX_PAD(0x04F0, 0x0120, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A20__TPSMP_HDATA_2 \
+ IOMUX_PAD(0x04F0, 0x0120, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A20__SRC_BT_CFG_20 \
+ IOMUX_PAD(0x04F0, 0x0120, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A20__EPDC_PWRCTRL_2 \
+ IOMUX_PAD(0x04F0, 0x0120, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_A21__WEIM_WEIM_A_21 \
+ IOMUX_PAD(0x04F4, 0x0124, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_A21__IPU1_DISP1_DAT_16 \
+ IOMUX_PAD(0x04F4, 0x0124, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A21__IPU1_CSI1_D_16 \
+ IOMUX_PAD(0x04F4, 0x0124, 2, 0x08A0, 0, 0)
+#define MX6DL_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 \
+ IOMUX_PAD(0x04F4, 0x0124, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A21__GPIO_2_17 \
+ IOMUX_PAD(0x04F4, 0x0124, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A21__TPSMP_HDATA_1 \
+ IOMUX_PAD(0x04F4, 0x0124, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A21__SRC_BT_CFG_21 \
+ IOMUX_PAD(0x04F4, 0x0124, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A21__EPDC_GDCLK \
+ IOMUX_PAD(0x04F4, 0x0124, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_A22__WEIM_WEIM_A_22 \
+ IOMUX_PAD(0x04F8, 0x0128, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_A22__IPU1_DISP1_DAT_17 \
+ IOMUX_PAD(0x04F8, 0x0128, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A22__IPU1_CSI1_D_17 \
+ IOMUX_PAD(0x04F8, 0x0128, 2, 0x08A4, 0, 0)
+#define MX6DL_PAD_EIM_A22__GPIO_2_16 \
+ IOMUX_PAD(0x04F8, 0x0128, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A22__TPSMP_HDATA_0 \
+ IOMUX_PAD(0x04F8, 0x0128, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A22__SRC_BT_CFG_22 \
+ IOMUX_PAD(0x04F8, 0x0128, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A22__EPDC_GDSP \
+ IOMUX_PAD(0x04F8, 0x0128, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_A23__WEIM_WEIM_A_23 \
+ IOMUX_PAD(0x04FC, 0x012C, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_A23__IPU1_DISP1_DAT_18 \
+ IOMUX_PAD(0x04FC, 0x012C, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A23__IPU1_CSI1_D_18 \
+ IOMUX_PAD(0x04FC, 0x012C, 2, 0x08A8, 0, 0)
+#define MX6DL_PAD_EIM_A23__IPU1_SISG_3 \
+ IOMUX_PAD(0x04FC, 0x012C, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A23__GPIO_6_6 \
+ IOMUX_PAD(0x04FC, 0x012C, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A23__PL301_SIM_MX6DL_PER1_HPROT_3 \
+ IOMUX_PAD(0x04FC, 0x012C, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A23__SRC_BT_CFG_23 \
+ IOMUX_PAD(0x04FC, 0x012C, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A23__EPDC_GDOE \
+ IOMUX_PAD(0x04FC, 0x012C, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_A24__WEIM_WEIM_A_24 \
+ IOMUX_PAD(0x0500, 0x0130, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A24__IPU1_DISP1_DAT_19 \
+ IOMUX_PAD(0x0500, 0x0130, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A24__IPU1_CSI1_D_19 \
+ IOMUX_PAD(0x0500, 0x0130, 2, 0x08AC, 0, 0)
+#define MX6DL_PAD_EIM_A24__IPU1_SISG_2 \
+ IOMUX_PAD(0x0500, 0x0130, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A24__GPIO_5_4 \
+ IOMUX_PAD(0x0500, 0x0130, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A24__PL301_SIM_MX6DL_PER1_HPROT_2 \
+ IOMUX_PAD(0x0500, 0x0130, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A24__SRC_BT_CFG_24 \
+ IOMUX_PAD(0x0500, 0x0130, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A24__EPDC_GDRL \
+ IOMUX_PAD(0x0500, 0x0130, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_A25__WEIM_WEIM_A_25 \
+ IOMUX_PAD(0x0504, 0x0134, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A25__ECSPI4_SS1 \
+ IOMUX_PAD(0x0504, 0x0134, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A25__ECSPI2_RDY \
+ IOMUX_PAD(0x0504, 0x0134, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A25__IPU1_DI1_PIN12 \
+ IOMUX_PAD(0x0504, 0x0134, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A25__IPU1_DI0_D1_CS \
+ IOMUX_PAD(0x0504, 0x0134, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A25__GPIO_5_2 \
+ IOMUX_PAD(0x0504, 0x0134, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A25__HDMI_TX_CEC_LINE \
+ IOMUX_PAD(0x0504, 0x0134, 6, 0x085C, 0, 0)
+#define MX6DL_PAD_EIM_A25__PL301_SIM_MX6DL_PER1_HBURST_0 \
+ IOMUX_PAD(0x0504, 0x0134, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A25__EPDC_SDDO_15 \
+ IOMUX_PAD(0x0504, 0x0134, 8, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_A25__WEIM_ACLK_FREERUN \
+ IOMUX_PAD(0x0504, 0x0134, 9, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_BCLK__WEIM_WEIM_BCLK \
+ IOMUX_PAD(0x0508, 0x0138, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_BCLK__IPU1_DI1_PIN16 \
+ IOMUX_PAD(0x0508, 0x0138, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_BCLK__GPIO_6_31 \
+ IOMUX_PAD(0x0508, 0x0138, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_BCLK__TPSMP_HDATA_31 \
+ IOMUX_PAD(0x0508, 0x0138, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_BCLK__EPDC_SDCE_9 \
+ IOMUX_PAD(0x0508, 0x0138, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_CS0__WEIM_WEIM_CS_0 \
+ IOMUX_PAD(0x050C, 0x013C, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_CS0__IPU1_DI1_PIN5 \
+ IOMUX_PAD(0x050C, 0x013C, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_CS0__ECSPI2_SCLK \
+ IOMUX_PAD(0x050C, 0x013C, 2, 0x07F4, 2, 0)
+#define MX6DL_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 \
+ IOMUX_PAD(0x050C, 0x013C, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_CS0__GPIO_2_23 \
+ IOMUX_PAD(0x050C, 0x013C, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_CS0__TPSMP_HDATA_7 \
+ IOMUX_PAD(0x050C, 0x013C, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_CS0__EPDC_SDDO_6 \
+ IOMUX_PAD(0x050C, 0x013C, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_CS1__WEIM_WEIM_CS_1 \
+ IOMUX_PAD(0x0510, 0x0140, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_CS1__IPU1_DI1_PIN6 \
+ IOMUX_PAD(0x0510, 0x0140, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_CS1__ECSPI2_MOSI \
+ IOMUX_PAD(0x0510, 0x0140, 2, 0x07FC, 2, 0)
+#define MX6DL_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 \
+ IOMUX_PAD(0x0510, 0x0140, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_CS1__GPIO_2_24 \
+ IOMUX_PAD(0x0510, 0x0140, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_CS1__TPSMP_HDATA_8 \
+ IOMUX_PAD(0x0510, 0x0140, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_CS1__EPDC_SDDO_8 \
+ IOMUX_PAD(0x0510, 0x0140, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_D16__WEIM_WEIM_D_16 \
+ IOMUX_PAD(0x0514, 0x0144, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_D16__ECSPI1_SCLK \
+ IOMUX_PAD(0x0514, 0x0144, 1, 0x07D8, 2, MX6DL_ECSPI_PAD_CTRL)
+#define MX6DL_PAD_EIM_D16__IPU1_DI0_PIN5 \
+ IOMUX_PAD(0x0514, 0x0144, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D16__IPU1_CSI1_D_18 \
+ IOMUX_PAD(0x0514, 0x0144, 3, 0x08A8, 1, 0)
+#define MX6DL_PAD_EIM_D16__HDMI_TX_DDC_SDA \
+ IOMUX_PAD(0x0514, 0x0144, 4, 0x0864, 0, 0)
+#define MX6DL_PAD_EIM_D16__GPIO_3_16 \
+ IOMUX_PAD(0x0514, 0x0144, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D16__I2C2_SDA \
+ IOMUX_PAD(0x0514, 0x0144, 6 | IOMUX_CONFIG_SION, 0x0874, 0, MX6DL_I2C_PAD_CTRL)
+#define MX6DL_PAD_EIM_D16__TPSMP_HTRANS_0 \
+ IOMUX_PAD(0x0514, 0x0144, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D16__EPDC_SDDO_10 \
+ IOMUX_PAD(0x0514, 0x0144, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_D17__WEIM_WEIM_D_17 \
+ IOMUX_PAD(0x0518, 0x0148, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_D17__ECSPI1_MISO \
+ IOMUX_PAD(0x0518, 0x0148, 1, 0x07DC, 2, MX6DL_ECSPI_PAD_CTRL)
+#define MX6DL_PAD_EIM_D17__IPU1_DI0_PIN6 \
+ IOMUX_PAD(0x0518, 0x0148, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D17__IPU1_CSI1_PIXCLK \
+ IOMUX_PAD(0x0518, 0x0148, 3, 0x08B8, 1, 0)
+#define MX6DL_PAD_EIM_D17__DCIC1_DCIC_OUT \
+ IOMUX_PAD(0x0518, 0x0148, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D17__GPIO_3_17 \
+ IOMUX_PAD(0x0518, 0x0148, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D17__I2C3_SCL \
+ IOMUX_PAD(0x0518, 0x0148, 6 | IOMUX_CONFIG_SION, 0x0878, 0, MX6DL_I2C_PAD_CTRL)
+#define MX6DL_PAD_EIM_D17__PL301_SIM_MX6DL_PER1_HBURST_1 \
+ IOMUX_PAD(0x0518, 0x0148, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D17__EPDC_VCOM_0 \
+ IOMUX_PAD(0x0518, 0x0148, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_D18__WEIM_WEIM_D_18 \
+ IOMUX_PAD(0x051C, 0x014C, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_D18__ECSPI1_MOSI \
+ IOMUX_PAD(0x051C, 0x014C, 1, 0x07E0, 2, MX6DL_ECSPI_PAD_CTRL)
+#define MX6DL_PAD_EIM_D18__IPU1_DI0_PIN7 \
+ IOMUX_PAD(0x051C, 0x014C, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D18__IPU1_CSI1_D_17 \
+ IOMUX_PAD(0x051C, 0x014C, 3, 0x08A4, 1, 0)
+#define MX6DL_PAD_EIM_D18__IPU1_DI1_D0_CS \
+ IOMUX_PAD(0x051C, 0x014C, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D18__GPIO_3_18 \
+ IOMUX_PAD(0x051C, 0x014C, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D18__I2C3_SDA \
+ IOMUX_PAD(0x051C, 0x014C, 6 | IOMUX_CONFIG_SION, 0x087C, 0, MX6DL_I2C_PAD_CTRL)
+#define MX6DL_PAD_EIM_D18__PL301_SIM_MX6DL_PER1_HBURST_2 \
+ IOMUX_PAD(0x051C, 0x014C, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D18__EPDC_VCOM_1 \
+ IOMUX_PAD(0x051C, 0x014C, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_D19__WEIM_WEIM_D_19 \
+ IOMUX_PAD(0x0520, 0x0150, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_D19__ECSPI1_SS1 \
+ IOMUX_PAD(0x0520, 0x0150, 1, 0x07E8, 1, MX6DL_ECSPI_PAD_CTRL)
+#define MX6DL_PAD_EIM_D19__IPU1_DI0_PIN8 \
+ IOMUX_PAD(0x0520, 0x0150, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D19__IPU1_CSI1_D_16 \
+ IOMUX_PAD(0x0520, 0x0150, 3, 0x08A0, 1, 0)
+#define MX6DL_PAD_EIM_D19__UART1_CTS \
+ IOMUX_PAD(0x0520, 0x0150, 4, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_EIM_D19__UART1_RTS \
+ IOMUX_PAD(0x0520, 0x0150, 4, 0x08F8, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_EIM_D19__GPIO_3_19 \
+ IOMUX_PAD(0x0520, 0x0150, 5, 0x0000, 0, MX6DL_ECSPI_PAD_CTRL)
+#define MX6DL_PAD_EIM_D19__EPIT1_EPITO \
+ IOMUX_PAD(0x0520, 0x0150, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D19__PL301_SIM_MX6DL_PER1_HRESP \
+ IOMUX_PAD(0x0520, 0x0150, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D19__EPDC_SDDO_12 \
+ IOMUX_PAD(0x0520, 0x0150, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_D20__WEIM_WEIM_D_20 \
+ IOMUX_PAD(0x0524, 0x0154, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_D20__ECSPI4_SS0 \
+ IOMUX_PAD(0x0524, 0x0154, 1, 0x0808, 0, 0)
+#define MX6DL_PAD_EIM_D20__IPU1_DI0_PIN16 \
+ IOMUX_PAD(0x0524, 0x0154, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D20__IPU1_CSI1_D_15 \
+ IOMUX_PAD(0x0524, 0x0154, 3, 0x089C, 1, 0)
+#define MX6DL_PAD_EIM_D20__UART1_CTS \
+ IOMUX_PAD(0x0524, 0x0154, 4, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_EIM_D20__UART1_RTS \
+ IOMUX_PAD(0x0524, 0x0154, 4, 0x08F8, 1, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_EIM_D20__GPIO_3_20 \
+ IOMUX_PAD(0x0524, 0x0154, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D20__EPIT2_EPITO \
+ IOMUX_PAD(0x0524, 0x0154, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D20__TPSMP_HTRANS_1 \
+ IOMUX_PAD(0x0524, 0x0154, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_D21__WEIM_WEIM_D_21 \
+ IOMUX_PAD(0x0528, 0x0158, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_D21__ECSPI4_SCLK \
+ IOMUX_PAD(0x0528, 0x0158, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D21__IPU1_DI0_PIN17 \
+ IOMUX_PAD(0x0528, 0x0158, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D21__IPU1_CSI1_D_11 \
+ IOMUX_PAD(0x0528, 0x0158, 3, 0x088C, 0, 0)
+#define MX6DL_PAD_EIM_D21__USBOH3_USBOTG_OC \
+ IOMUX_PAD(0x0528, 0x0158, 4, 0x0920, 0, 0)
+#define MX6DL_PAD_EIM_D21__GPIO_3_21 \
+ IOMUX_PAD(0x0528, 0x0158, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D21__I2C1_SCL \
+ IOMUX_PAD(0x0528, 0x0158, 6 | IOMUX_CONFIG_SION, 0x0868, 1, MX6DL_I2C_PAD_CTRL)
+#define MX6DL_PAD_EIM_D21__SPDIF_IN1 \
+ IOMUX_PAD(0x0528, 0x0158, 7, 0x08F0, 0, 0)
+
+#define MX6DL_PAD_EIM_D22__WEIM_WEIM_D_22 \
+ IOMUX_PAD(0x052C, 0x015C, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_D22__ECSPI4_MISO \
+ IOMUX_PAD(0x052C, 0x015C, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D22__IPU1_DI0_PIN1 \
+ IOMUX_PAD(0x052C, 0x015C, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D22__IPU1_CSI1_D_10 \
+ IOMUX_PAD(0x052C, 0x015C, 3, 0x0888, 0, 0)
+#define MX6DL_PAD_EIM_D22__USBOH3_USBOTG_PWR \
+ IOMUX_PAD(0x052C, 0x015C, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D22__GPIO_3_22 \
+ IOMUX_PAD(0x052C, 0x015C, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D22__SPDIF_OUT1 \
+ IOMUX_PAD(0x052C, 0x015C, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D22__PL301_SIM_MX6DL_PER1_HWRITE \
+ IOMUX_PAD(0x052C, 0x015C, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D22__EPDC_SDCE_6 \
+ IOMUX_PAD(0x052C, 0x015C, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_D23__WEIM_WEIM_D_23 \
+ IOMUX_PAD(0x0530, 0x0160, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_D23__IPU1_DI0_D0_CS \
+ IOMUX_PAD(0x0530, 0x0160, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D23__UART3_CTS \
+ IOMUX_PAD(0x0530, 0x0160, 2, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_EIM_D23__UART3_RTS \
+ IOMUX_PAD(0x0530, 0x0160, 2, 0x0908, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_EIM_D23__UART1_DCD \
+ IOMUX_PAD(0x0530, 0x0160, 3, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_EIM_D23__IPU1_CSI1_DATA_EN \
+ IOMUX_PAD(0x0530, 0x0160, 4, 0x08B0, 0, 0)
+#define MX6DL_PAD_EIM_D23__GPIO_3_23 \
+ IOMUX_PAD(0x0530, 0x0160, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D23__IPU1_DI1_PIN2 \
+ IOMUX_PAD(0x0530, 0x0160, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D23__IPU1_DI1_PIN14 \
+ IOMUX_PAD(0x0530, 0x0160, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D23__EPDC_SDDO_11 \
+ IOMUX_PAD(0x0530, 0x0160, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_D24__WEIM_WEIM_D_24 \
+ IOMUX_PAD(0x0534, 0x0164, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_D24__ECSPI4_SS2 \
+ IOMUX_PAD(0x0534, 0x0164, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D24__UART3_TXD \
+ IOMUX_PAD(0x0534, 0x0164, 2, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_EIM_D24__UART3_RXD \
+ IOMUX_PAD(0x0534, 0x0164, 2, 0x090C, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_EIM_D24__ECSPI1_SS2 \
+ IOMUX_PAD(0x0534, 0x0164, 3, 0x07EC, 0, 0)
+#define MX6DL_PAD_EIM_D24__ECSPI2_SS2 \
+ IOMUX_PAD(0x0534, 0x0164, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D24__GPIO_3_24 \
+ IOMUX_PAD(0x0534, 0x0164, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D24__AUDMUX_AUD5_RXFS \
+ IOMUX_PAD(0x0534, 0x0164, 6, 0x07BC, 1, 0)
+#define MX6DL_PAD_EIM_D24__UART1_DTR \
+ IOMUX_PAD(0x0534, 0x0164, 7, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_EIM_D24__EPDC_SDCE_7 \
+ IOMUX_PAD(0x0534, 0x0164, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_D25__WEIM_WEIM_D_25 \
+ IOMUX_PAD(0x0538, 0x0168, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_D25__ECSPI4_SS3 \
+ IOMUX_PAD(0x0538, 0x0168, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D25__UART3_TXD \
+ IOMUX_PAD(0x0538, 0x0168, 2, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_EIM_D25__UART3_RXD \
+ IOMUX_PAD(0x0538, 0x0168, 2, 0x090C, 1, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_EIM_D25__ECSPI1_SS3 \
+ IOMUX_PAD(0x0538, 0x0168, 3, 0x07F0, 0, 0)
+#define MX6DL_PAD_EIM_D25__ECSPI2_SS3 \
+ IOMUX_PAD(0x0538, 0x0168, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D25__GPIO_3_25 \
+ IOMUX_PAD(0x0538, 0x0168, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D25__AUDMUX_AUD5_RXC \
+ IOMUX_PAD(0x0538, 0x0168, 6, 0x07B8, 1, 0)
+#define MX6DL_PAD_EIM_D25__UART1_DSR \
+ IOMUX_PAD(0x0538, 0x0168, 7, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_EIM_D25__EPDC_SDCE_8 \
+ IOMUX_PAD(0x0538, 0x0168, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_D26__WEIM_WEIM_D_26 \
+ IOMUX_PAD(0x053C, 0x016C, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_D26__IPU1_DI1_PIN11 \
+ IOMUX_PAD(0x053C, 0x016C, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D26__IPU1_CSI0_D_1 \
+ IOMUX_PAD(0x053C, 0x016C, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D26__IPU1_CSI1_D_14 \
+ IOMUX_PAD(0x053C, 0x016C, 3, 0x0898, 1, 0)
+#define MX6DL_PAD_EIM_D26__UART2_TXD \
+ IOMUX_PAD(0x053C, 0x016C, 4, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_EIM_D26__UART2_RXD \
+ IOMUX_PAD(0x053C, 0x016C, 4, 0x0904, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_EIM_D26__GPIO_3_26 \
+ IOMUX_PAD(0x053C, 0x016C, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D26__IPU1_SISG_2 \
+ IOMUX_PAD(0x053C, 0x016C, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D26__IPU1_DISP1_DAT_22 \
+ IOMUX_PAD(0x053C, 0x016C, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D26__EPDC_SDOED \
+ IOMUX_PAD(0x053C, 0x016C, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_D27__WEIM_WEIM_D_27 \
+ IOMUX_PAD(0x0540, 0x0170, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_D27__IPU1_DI1_PIN13 \
+ IOMUX_PAD(0x0540, 0x0170, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D27__IPU1_CSI0_D_0 \
+ IOMUX_PAD(0x0540, 0x0170, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D27__IPU1_CSI1_D_13 \
+ IOMUX_PAD(0x0540, 0x0170, 3, 0x0894, 1, 0)
+#define MX6DL_PAD_EIM_D27__UART2_TXD \
+ IOMUX_PAD(0x0540, 0x0170, 4, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_EIM_D27__UART2_RXD \
+ IOMUX_PAD(0x0540, 0x0170, 4, 0x0904, 1, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_EIM_D27__GPIO_3_27 \
+ IOMUX_PAD(0x0540, 0x0170, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D27__IPU1_SISG_3 \
+ IOMUX_PAD(0x0540, 0x0170, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D27__IPU1_DISP1_DAT_23 \
+ IOMUX_PAD(0x0540, 0x0170, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D27__EPDC_SDOE \
+ IOMUX_PAD(0x0540, 0x0170, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_D28__WEIM_WEIM_D_28 \
+ IOMUX_PAD(0x0544, 0x0174, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_D28__I2C1_SDA \
+ IOMUX_PAD(0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, MX6DL_I2C_PAD_CTRL)
+#define MX6DL_PAD_EIM_D28__ECSPI4_MOSI \
+ IOMUX_PAD(0x0544, 0x0174, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D28__IPU1_CSI1_D_12 \
+ IOMUX_PAD(0x0544, 0x0174, 3, 0x0890, 1, 0)
+#define MX6DL_PAD_EIM_D28__UART2_CTS \
+ IOMUX_PAD(0x0544, 0x0174, 4, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_EIM_D28__UART2_RTS \
+ IOMUX_PAD(0x0544, 0x0174, 4, 0x0900, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_EIM_D28__GPIO_3_28 \
+ IOMUX_PAD(0x0544, 0x0174, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D28__IPU1_EXT_TRIG \
+ IOMUX_PAD(0x0544, 0x0174, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D28__IPU1_DI0_PIN13 \
+ IOMUX_PAD(0x0544, 0x0174, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D28__EPDC_PWRCTRL_3 \
+ IOMUX_PAD(0x0544, 0x0174, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_D29__WEIM_WEIM_D_29 \
+ IOMUX_PAD(0x0548, 0x0178, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_D29__IPU1_DI1_PIN15 \
+ IOMUX_PAD(0x0548, 0x0178, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D29__ECSPI4_SS0 \
+ IOMUX_PAD(0x0548, 0x0178, 2, 0x0808, 1, 0)
+#define MX6DL_PAD_EIM_D29__UART2_CTS \
+ IOMUX_PAD(0x0548, 0x0178, 4, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_EIM_D29__UART2_RTS \
+ IOMUX_PAD(0x0548, 0x0178, 4, 0x0900, 1, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_EIM_D29__GPIO_3_29 \
+ IOMUX_PAD(0x0548, 0x0178, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D29__IPU1_CSI1_VSYNC \
+ IOMUX_PAD(0x0548, 0x0178, 6, 0x08BC, 0, 0)
+#define MX6DL_PAD_EIM_D29__IPU1_DI0_PIN14 \
+ IOMUX_PAD(0x0548, 0x0178, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D29__EPDC_PWRWAKE \
+ IOMUX_PAD(0x0548, 0x0178, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_D30__WEIM_WEIM_D_30 \
+ IOMUX_PAD(0x054C, 0x017C, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_D30__IPU1_DISP1_DAT_21 \
+ IOMUX_PAD(0x054C, 0x017C, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D30__IPU1_DI0_PIN11 \
+ IOMUX_PAD(0x054C, 0x017C, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D30__IPU1_CSI0_D_3 \
+ IOMUX_PAD(0x054C, 0x017C, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D30__UART3_CTS \
+ IOMUX_PAD(0x054C, 0x017C, 4, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_EIM_D30__UART3_RTS \
+ IOMUX_PAD(0x054C, 0x017C, 4, 0x0908, 1, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_EIM_D30__GPIO_3_30 \
+ IOMUX_PAD(0x054C, 0x017C, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D30__USBOH3_USBH1_OC \
+ IOMUX_PAD(0x054C, 0x017C, 6, 0x0924, 0, 0)
+#define MX6DL_PAD_EIM_D30__PL301_SIM_MX6DL_PER1_HPROT_0 \
+ IOMUX_PAD(0x054C, 0x017C, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D30__EPDC_SDOEZ \
+ IOMUX_PAD(0x054C, 0x017C, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_D31__WEIM_WEIM_D_31 \
+ IOMUX_PAD(0x0550, 0x0180, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_D31__IPU1_DISP1_DAT_20 \
+ IOMUX_PAD(0x0550, 0x0180, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D31__IPU1_DI0_PIN12 \
+ IOMUX_PAD(0x0550, 0x0180, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D31__IPU1_CSI0_D_2 \
+ IOMUX_PAD(0x0550, 0x0180, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D31__UART3_CTS \
+ IOMUX_PAD(0x0550, 0x0180, 4, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_EIM_D31__UART3_RTS \
+ IOMUX_PAD(0x0550, 0x0180, 4, 0x0908, 2, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_EIM_D31__GPIO_3_31 \
+ IOMUX_PAD(0x0550, 0x0180, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D31__USBOH3_USBH1_PWR \
+ IOMUX_PAD(0x0550, 0x0180, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D31__PL301_SIM_MX6DL_PER1_HPROT_1 \
+ IOMUX_PAD(0x0550, 0x0180, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D31__EPDC_SDCLK \
+ IOMUX_PAD(0x0550, 0x0180, 8, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_D31__WEIM_ACLK_FREERUN \
+ IOMUX_PAD(0x0550, 0x0180, 9, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 \
+ IOMUX_PAD(0x0554, 0x0184, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_DA0__IPU1_DISP1_DAT_9 \
+ IOMUX_PAD(0x0554, 0x0184, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA0__IPU1_CSI1_D_9 \
+ IOMUX_PAD(0x0554, 0x0184, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 \
+ IOMUX_PAD(0x0554, 0x0184, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA0__GPIO_3_0 \
+ IOMUX_PAD(0x0554, 0x0184, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA0__TPSMP_HDATA_14 \
+ IOMUX_PAD(0x0554, 0x0184, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA0__SRC_BT_CFG_0 \
+ IOMUX_PAD(0x0554, 0x0184, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA0__EPDC_SDCLKN \
+ IOMUX_PAD(0x0554, 0x0184, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 \
+ IOMUX_PAD(0x0558, 0x0188, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_DA1__IPU1_DISP1_DAT_8 \
+ IOMUX_PAD(0x0558, 0x0188, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA1__IPU1_CSI1_D_8 \
+ IOMUX_PAD(0x0558, 0x0188, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 \
+ IOMUX_PAD(0x0558, 0x0188, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE \
+ IOMUX_PAD(0x0558, 0x0188, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA1__GPIO_3_1 \
+ IOMUX_PAD(0x0558, 0x0188, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA1__TPSMP_HDATA_15 \
+ IOMUX_PAD(0x0558, 0x0188, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA1__SRC_BT_CFG_1 \
+ IOMUX_PAD(0x0558, 0x0188, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA1__EPDC_SDLE \
+ IOMUX_PAD(0x0558, 0x0188, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 \
+ IOMUX_PAD(0x055C, 0x018C, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_DA10__IPU1_DI1_PIN15 \
+ IOMUX_PAD(0x055C, 0x018C, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA10__IPU1_CSI1_DATA_EN \
+ IOMUX_PAD(0x055C, 0x018C, 2, 0x08B0, 1, 0)
+#define MX6DL_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 \
+ IOMUX_PAD(0x055C, 0x018C, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA10__GPIO_3_10 \
+ IOMUX_PAD(0x055C, 0x018C, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA10__TPSMP_HDATA_24 \
+ IOMUX_PAD(0x055C, 0x018C, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA10__SRC_BT_CFG_10 \
+ IOMUX_PAD(0x055C, 0x018C, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA10__EPDC_SDDO_1 \
+ IOMUX_PAD(0x055C, 0x018C, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 \
+ IOMUX_PAD(0x0560, 0x0190, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_DA11__IPU1_DI1_PIN2 \
+ IOMUX_PAD(0x0560, 0x0190, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA11__IPU1_CSI1_HSYNC \
+ IOMUX_PAD(0x0560, 0x0190, 2, 0x08B4, 0, 0)
+#define MX6DL_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 \
+ IOMUX_PAD(0x0560, 0x0190, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 \
+ IOMUX_PAD(0x0560, 0x0190, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA11__GPIO_3_11 \
+ IOMUX_PAD(0x0560, 0x0190, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA11__TPSMP_HDATA_25 \
+ IOMUX_PAD(0x0560, 0x0190, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA11__SRC_BT_CFG_11 \
+ IOMUX_PAD(0x0560, 0x0190, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA11__EPDC_SDDO_3 \
+ IOMUX_PAD(0x0560, 0x0190, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 \
+ IOMUX_PAD(0x0564, 0x0194, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_DA12__IPU1_DI1_PIN3 \
+ IOMUX_PAD(0x0564, 0x0194, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA12__IPU1_CSI1_VSYNC \
+ IOMUX_PAD(0x0564, 0x0194, 2, 0x08BC, 1, 0)
+#define MX6DL_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 \
+ IOMUX_PAD(0x0564, 0x0194, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 \
+ IOMUX_PAD(0x0564, 0x0194, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA12__GPIO_3_12 \
+ IOMUX_PAD(0x0564, 0x0194, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA12__TPSMP_HDATA_26 \
+ IOMUX_PAD(0x0564, 0x0194, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA12__SRC_BT_CFG_12 \
+ IOMUX_PAD(0x0564, 0x0194, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA12__EPDC_SDDO_2 \
+ IOMUX_PAD(0x0564, 0x0194, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 \
+ IOMUX_PAD(0x0568, 0x0198, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_DA13__IPU1_DI1_D0_CS \
+ IOMUX_PAD(0x0568, 0x0198, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA13__CCM_DI1_EXT_CLK \
+ IOMUX_PAD(0x0568, 0x0198, 2, 0x07D0, 0, 0)
+#define MX6DL_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 \
+ IOMUX_PAD(0x0568, 0x0198, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 \
+ IOMUX_PAD(0x0568, 0x0198, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA13__GPIO_3_13 \
+ IOMUX_PAD(0x0568, 0x0198, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA13__TPSMP_HDATA_27 \
+ IOMUX_PAD(0x0568, 0x0198, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA13__SRC_BT_CFG_13 \
+ IOMUX_PAD(0x0568, 0x0198, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA13__EPDC_SDDO_13 \
+ IOMUX_PAD(0x0568, 0x0198, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 \
+ IOMUX_PAD(0x056C, 0x019C, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_DA14__IPU1_DI1_D1_CS \
+ IOMUX_PAD(0x056C, 0x019C, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA14__CCM_DI0_EXT_CLK \
+ IOMUX_PAD(0x056C, 0x019C, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 \
+ IOMUX_PAD(0x056C, 0x019C, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 \
+ IOMUX_PAD(0x056C, 0x019C, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA14__GPIO_3_14 \
+ IOMUX_PAD(0x056C, 0x019C, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA14__TPSMP_HDATA_28 \
+ IOMUX_PAD(0x056C, 0x019C, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA14__SRC_BT_CFG_14 \
+ IOMUX_PAD(0x056C, 0x019C, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA14__EPDC_SDDO_14 \
+ IOMUX_PAD(0x056C, 0x019C, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 \
+ IOMUX_PAD(0x0570, 0x01A0, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_DA15__IPU1_DI1_PIN1 \
+ IOMUX_PAD(0x0570, 0x01A0, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA15__IPU1_DI1_PIN4 \
+ IOMUX_PAD(0x0570, 0x01A0, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 \
+ IOMUX_PAD(0x0570, 0x01A0, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA15__GPIO_3_15 \
+ IOMUX_PAD(0x0570, 0x01A0, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA15__TPSMP_HDATA_29 \
+ IOMUX_PAD(0x0570, 0x01A0, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA15__SRC_BT_CFG_15 \
+ IOMUX_PAD(0x0570, 0x01A0, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA15__EPDC_SDDO_9 \
+ IOMUX_PAD(0x0570, 0x01A0, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 \
+ IOMUX_PAD(0x0574, 0x01A4, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_DA2__IPU1_DISP1_DAT_7 \
+ IOMUX_PAD(0x0574, 0x01A4, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA2__IPU1_CSI1_D_7 \
+ IOMUX_PAD(0x0574, 0x01A4, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 \
+ IOMUX_PAD(0x0574, 0x01A4, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE \
+ IOMUX_PAD(0x0574, 0x01A4, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA2__GPIO_3_2 \
+ IOMUX_PAD(0x0574, 0x01A4, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA2__TPSMP_HDATA_16 \
+ IOMUX_PAD(0x0574, 0x01A4, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA2__SRC_BT_CFG_2 \
+ IOMUX_PAD(0x0574, 0x01A4, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA2__EPDC_BDR_0 \
+ IOMUX_PAD(0x0574, 0x01A4, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 \
+ IOMUX_PAD(0x0578, 0x01A8, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_DA3__IPU1_DISP1_DAT_6 \
+ IOMUX_PAD(0x0578, 0x01A8, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA3__IPU1_CSI1_D_6 \
+ IOMUX_PAD(0x0578, 0x01A8, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 \
+ IOMUX_PAD(0x0578, 0x01A8, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ \
+ IOMUX_PAD(0x0578, 0x01A8, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA3__GPIO_3_3 \
+ IOMUX_PAD(0x0578, 0x01A8, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA3__TPSMP_HDATA_17 \
+ IOMUX_PAD(0x0578, 0x01A8, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA3__SRC_BT_CFG_3 \
+ IOMUX_PAD(0x0578, 0x01A8, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA3__EPDC_BDR_1 \
+ IOMUX_PAD(0x0578, 0x01A8, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 \
+ IOMUX_PAD(0x057C, 0x01AC, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_DA4__IPU1_DISP1_DAT_5 \
+ IOMUX_PAD(0x057C, 0x01AC, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA4__IPU1_CSI1_D_5 \
+ IOMUX_PAD(0x057C, 0x01AC, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 \
+ IOMUX_PAD(0x057C, 0x01AC, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN \
+ IOMUX_PAD(0x057C, 0x01AC, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA4__GPIO_3_4 \
+ IOMUX_PAD(0x057C, 0x01AC, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA4__TPSMP_HDATA_18 \
+ IOMUX_PAD(0x057C, 0x01AC, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA4__SRC_BT_CFG_4 \
+ IOMUX_PAD(0x057C, 0x01AC, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA4__EPDC_SDCE_0 \
+ IOMUX_PAD(0x057C, 0x01AC, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 \
+ IOMUX_PAD(0x0580, 0x01B0, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_DA5__IPU1_DISP1_DAT_4 \
+ IOMUX_PAD(0x0580, 0x01B0, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA5__IPU1_CSI1_D_4 \
+ IOMUX_PAD(0x0580, 0x01B0, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 \
+ IOMUX_PAD(0x0580, 0x01B0, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP \
+ IOMUX_PAD(0x0580, 0x01B0, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA5__GPIO_3_5 \
+ IOMUX_PAD(0x0580, 0x01B0, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA5__TPSMP_HDATA_19 \
+ IOMUX_PAD(0x0580, 0x01B0, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA5__SRC_BT_CFG_5 \
+ IOMUX_PAD(0x0580, 0x01B0, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA5__EPDC_SDCE_1 \
+ IOMUX_PAD(0x0580, 0x01B0, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 \
+ IOMUX_PAD(0x0584, 0x01B4, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_DA6__IPU1_DISP1_DAT_3 \
+ IOMUX_PAD(0x0584, 0x01B4, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA6__IPU1_CSI1_D_3 \
+ IOMUX_PAD(0x0584, 0x01B4, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 \
+ IOMUX_PAD(0x0584, 0x01B4, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN \
+ IOMUX_PAD(0x0584, 0x01B4, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA6__GPIO_3_6 \
+ IOMUX_PAD(0x0584, 0x01B4, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA6__TPSMP_HDATA_20 \
+ IOMUX_PAD(0x0584, 0x01B4, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA6__SRC_BT_CFG_6 \
+ IOMUX_PAD(0x0584, 0x01B4, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA6__EPDC_SDCE_2 \
+ IOMUX_PAD(0x0584, 0x01B4, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 \
+ IOMUX_PAD(0x0588, 0x01B8, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_DA7__IPU1_DISP1_DAT_2 \
+ IOMUX_PAD(0x0588, 0x01B8, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA7__IPU1_CSI1_D_2 \
+ IOMUX_PAD(0x0588, 0x01B8, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 \
+ IOMUX_PAD(0x0588, 0x01B8, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA7__GPIO_3_7 \
+ IOMUX_PAD(0x0588, 0x01B8, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA7__TPSMP_HDATA_21 \
+ IOMUX_PAD(0x0588, 0x01B8, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA7__SRC_BT_CFG_7 \
+ IOMUX_PAD(0x0588, 0x01B8, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA7__EPDC_SDCE_3 \
+ IOMUX_PAD(0x0588, 0x01B8, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 \
+ IOMUX_PAD(0x058C, 0x01BC, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_DA8__IPU1_DISP1_DAT_1 \
+ IOMUX_PAD(0x058C, 0x01BC, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA8__IPU1_CSI1_D_1 \
+ IOMUX_PAD(0x058C, 0x01BC, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 \
+ IOMUX_PAD(0x058C, 0x01BC, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA8__GPIO_3_8 \
+ IOMUX_PAD(0x058C, 0x01BC, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA8__TPSMP_HDATA_22 \
+ IOMUX_PAD(0x058C, 0x01BC, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA8__SRC_BT_CFG_8 \
+ IOMUX_PAD(0x058C, 0x01BC, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA8__EPDC_SDCE_4 \
+ IOMUX_PAD(0x058C, 0x01BC, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 \
+ IOMUX_PAD(0x0590, 0x01C0, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
+#define MX6DL_PAD_EIM_DA9__IPU1_DISP1_DAT_0 \
+ IOMUX_PAD(0x0590, 0x01C0, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA9__IPU1_CSI1_D_0 \
+ IOMUX_PAD(0x0590, 0x01C0, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 \
+ IOMUX_PAD(0x0590, 0x01C0, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA9__GPIO_3_9 \
+ IOMUX_PAD(0x0590, 0x01C0, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA9__TPSMP_HDATA_23 \
+ IOMUX_PAD(0x0590, 0x01C0, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA9__SRC_BT_CFG_9 \
+ IOMUX_PAD(0x0590, 0x01C0, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_DA9__EPDC_SDCE_5 \
+ IOMUX_PAD(0x0590, 0x01C0, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_EB0__WEIM_WEIM_EB_0 \
+ IOMUX_PAD(0x0594, 0x01C4, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_EB0__IPU1_DISP1_DAT_11 \
+ IOMUX_PAD(0x0594, 0x01C4, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_EB0__IPU1_CSI1_D_11 \
+ IOMUX_PAD(0x0594, 0x01C4, 2, 0x088C, 1, 0)
+#define MX6DL_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 \
+ IOMUX_PAD(0x0594, 0x01C4, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_EB0__CCM_PMIC_RDY \
+ IOMUX_PAD(0x0594, 0x01C4, 4, 0x07D4, 0, 0)
+#define MX6DL_PAD_EIM_EB0__GPIO_2_28 \
+ IOMUX_PAD(0x0594, 0x01C4, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_EB0__TPSMP_HDATA_12 \
+ IOMUX_PAD(0x0594, 0x01C4, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_EB0__SRC_BT_CFG_27 \
+ IOMUX_PAD(0x0594, 0x01C4, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_EB0__EPDC_PWRCOM \
+ IOMUX_PAD(0x0594, 0x01C4, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_EB1__WEIM_WEIM_EB_1 \
+ IOMUX_PAD(0x0598, 0x01C8, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_EB1__IPU1_DISP1_DAT_10 \
+ IOMUX_PAD(0x0598, 0x01C8, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_EB1__IPU1_CSI1_D_10 \
+ IOMUX_PAD(0x0598, 0x01C8, 2, 0x0888, 1, 0)
+#define MX6DL_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 \
+ IOMUX_PAD(0x0598, 0x01C8, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_EB1__GPIO_2_29 \
+ IOMUX_PAD(0x0598, 0x01C8, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_EB1__TPSMP_HDATA_13 \
+ IOMUX_PAD(0x0598, 0x01C8, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_EB1__SRC_BT_CFG_28 \
+ IOMUX_PAD(0x0598, 0x01C8, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_EB1__EPDC_SDSHR \
+ IOMUX_PAD(0x0598, 0x01C8, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_EB2__WEIM_WEIM_EB_2 \
+ IOMUX_PAD(0x059C, 0x01CC, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_EB2__ECSPI1_SS0 \
+ IOMUX_PAD(0x059C, 0x01CC, 1, 0x07E4, 2, MX6DL_ECSPI_PAD_CTRL)
+#define MX6DL_PAD_EIM_EB2__CCM_DI1_EXT_CLK \
+ IOMUX_PAD(0x059C, 0x01CC, 2, 0x07D0, 1, 0)
+#define MX6DL_PAD_EIM_EB2__IPU1_CSI1_D_19 \
+ IOMUX_PAD(0x059C, 0x01CC, 3, 0x08AC, 1, 0)
+#define MX6DL_PAD_EIM_EB2__HDMI_TX_DDC_SCL \
+ IOMUX_PAD(0x059C, 0x01CC, 4, 0x0860, 0, 0)
+#define MX6DL_PAD_EIM_EB2__GPIO_2_30 \
+ IOMUX_PAD(0x059C, 0x01CC, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_EB2__I2C2_SCL \
+ IOMUX_PAD(0x059C, 0x01CC, 6 | IOMUX_CONFIG_SION, 0x0870, 0, MX6DL_I2C_PAD_CTRL)
+#define MX6DL_PAD_EIM_EB2__SRC_BT_CFG_30 \
+ IOMUX_PAD(0x059C, 0x01CC, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_EB2__EPDC_SDDO_5 \
+ IOMUX_PAD(0x059C, 0x01CC, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_EB3__WEIM_WEIM_EB_3 \
+ IOMUX_PAD(0x05A0, 0x01D0, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_EB3__ECSPI4_RDY \
+ IOMUX_PAD(0x05A0, 0x01D0, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_EB3__UART3_CTS \
+ IOMUX_PAD(0x05A0, 0x01D0, 2, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_EIM_EB3__UART3_RTS \
+ IOMUX_PAD(0x05A0, 0x01D0, 2, 0x0908, 3, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_EIM_EB3__UART1_RI \
+ IOMUX_PAD(0x05A0, 0x01D0, 3, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_EIM_EB3__IPU1_CSI1_HSYNC \
+ IOMUX_PAD(0x05A0, 0x01D0, 4, 0x08B4, 1, 0)
+#define MX6DL_PAD_EIM_EB3__GPIO_2_31 \
+ IOMUX_PAD(0x05A0, 0x01D0, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_EB3__IPU1_DI1_PIN3 \
+ IOMUX_PAD(0x05A0, 0x01D0, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_EB3__SRC_BT_CFG_31 \
+ IOMUX_PAD(0x05A0, 0x01D0, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_EB3__EPDC_SDCE_0 \
+ IOMUX_PAD(0x05A0, 0x01D0, 8, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_EB3__WEIM_ACLK_FREERUN \
+ IOMUX_PAD(0x05A0, 0x01D0, 9, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_LBA__WEIM_WEIM_LBA \
+ IOMUX_PAD(0x05A4, 0x01D4, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_LBA__IPU1_DI1_PIN17 \
+ IOMUX_PAD(0x05A4, 0x01D4, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_LBA__ECSPI2_SS1 \
+ IOMUX_PAD(0x05A4, 0x01D4, 2, 0x0804, 1, 0)
+#define MX6DL_PAD_EIM_LBA__GPIO_2_27 \
+ IOMUX_PAD(0x05A4, 0x01D4, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_LBA__TPSMP_HDATA_11 \
+ IOMUX_PAD(0x05A4, 0x01D4, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_LBA__SRC_BT_CFG_26 \
+ IOMUX_PAD(0x05A4, 0x01D4, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_LBA__EPDC_SDDO_4 \
+ IOMUX_PAD(0x05A4, 0x01D4, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_OE__WEIM_WEIM_OE \
+ IOMUX_PAD(0x05A8, 0x01D8, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_OE__IPU1_DI1_PIN7 \
+ IOMUX_PAD(0x05A8, 0x01D8, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_OE__ECSPI2_MISO \
+ IOMUX_PAD(0x05A8, 0x01D8, 2, 0x07F8, 2, 0)
+#define MX6DL_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 \
+ IOMUX_PAD(0x05A8, 0x01D8, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_OE__GPIO_2_25 \
+ IOMUX_PAD(0x05A8, 0x01D8, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_OE__TPSMP_HDATA_9 \
+ IOMUX_PAD(0x05A8, 0x01D8, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_OE__EPDC_PWRIRQ \
+ IOMUX_PAD(0x05A8, 0x01D8, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_RW__WEIM_WEIM_RW \
+ IOMUX_PAD(0x05AC, 0x01DC, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_RW__IPU1_DI1_PIN8 \
+ IOMUX_PAD(0x05AC, 0x01DC, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_RW__ECSPI2_SS0 \
+ IOMUX_PAD(0x05AC, 0x01DC, 2, 0x0800, 2, 0)
+#define MX6DL_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 \
+ IOMUX_PAD(0x05AC, 0x01DC, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_RW__GPIO_2_26 \
+ IOMUX_PAD(0x05AC, 0x01DC, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_RW__TPSMP_HDATA_10 \
+ IOMUX_PAD(0x05AC, 0x01DC, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_RW__SRC_BT_CFG_29 \
+ IOMUX_PAD(0x05AC, 0x01DC, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_RW__EPDC_SDDO_7 \
+ IOMUX_PAD(0x05AC, 0x01DC, 8, 0x0000, 0, 0)
+
+#define MX6DL_PAD_EIM_WAIT__WEIM_WEIM_WAIT \
+ IOMUX_PAD(0x05B0, 0x01E0, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B \
+ IOMUX_PAD(0x05B0, 0x01E0, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_WAIT__GPIO_5_0 \
+ IOMUX_PAD(0x05B0, 0x01E0, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_WAIT__TPSMP_HDATA_30 \
+ IOMUX_PAD(0x05B0, 0x01E0, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_EIM_WAIT__SRC_BT_CFG_25 \
+ IOMUX_PAD(0x05B0, 0x01E0, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_ENET_CRS_DV__ENET_RX_EN \
+ IOMUX_PAD(0x05B4, 0x01E4, 1, 0x0828, 0, 0)
+#define MX6DL_PAD_ENET_CRS_DV__ESAI1_SCKT \
+ IOMUX_PAD(0x05B4, 0x01E4, 2, 0x0840, 0, MX6DL_ESAI_PAD_CTRL)
+#define MX6DL_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK \
+ IOMUX_PAD(0x05B4, 0x01E4, 3, 0x08F4, 0, 0)
+#define MX6DL_PAD_ENET_CRS_DV__GPIO_1_25 \
+ IOMUX_PAD(0x05B4, 0x01E4, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_ENET_CRS_DV__PHY_TDO \
+ IOMUX_PAD(0x05B4, 0x01E4, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD \
+ IOMUX_PAD(0x05B4, 0x01E4, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_ENET_MDC__MLB_MLBDAT \
+ IOMUX_PAD(0x05B8, 0x01E8, 0, 0x08E0, 0, 0)
+#define MX6DL_PAD_ENET_MDC__ENET_MDC \
+ IOMUX_PAD(0x05B8, 0x01E8, 1, 0x0000, 0, MX6DL_ENET_PAD_CTRL)
+#define MX6DL_PAD_ENET_MDC__ESAI1_TX5_RX0 \
+ IOMUX_PAD(0x05B8, 0x01E8, 2, 0x0858, 0, MX6DL_ESAI_PAD_CTRL)
+#define MX6DL_PAD_ENET_MDC__ENET_1588_EVENT1_IN \
+ IOMUX_PAD(0x05B8, 0x01E8, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_ENET_MDC__GPIO_1_31 \
+ IOMUX_PAD(0x05B8, 0x01E8, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET \
+ IOMUX_PAD(0x05B8, 0x01E8, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_ENET_MDIO__ENET_MDIO \
+ IOMUX_PAD(0x05BC, 0x01EC, 1, 0x0810, 0, MX6DL_ENET_PAD_CTRL)
+#define MX6DL_PAD_ENET_MDIO__ESAI1_SCKR \
+ IOMUX_PAD(0x05BC, 0x01EC, 2, 0x083C, 0, 0)
+#define MX6DL_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 \
+ IOMUX_PAD(0x05BC, 0x01EC, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT \
+ IOMUX_PAD(0x05BC, 0x01EC, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_ENET_MDIO__GPIO_1_22 \
+ IOMUX_PAD(0x05BC, 0x01EC, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_ENET_MDIO__SPDIF_PLOCK \
+ IOMUX_PAD(0x05BC, 0x01EC, 6, 0x0000, 0, 0)
+
+#define MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK \
+ IOMUX_PAD(0x05C0, 0x01F0, 1, 0x0000, 0, MX6DL_ENET_REF_CLK_PAD_CTRL)
+#define MX6DL_PAD_ENET_REF_CLK__ESAI1_FSR \
+ IOMUX_PAD(0x05C0, 0x01F0, 2, 0x082C, 0, 0)
+#define MX6DL_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 \
+ IOMUX_PAD(0x05C0, 0x01F0, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_ENET_REF_CLK__GPIO_1_23 \
+ IOMUX_PAD(0x05C0, 0x01F0, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_ENET_REF_CLK__SPDIF_SRCLK \
+ IOMUX_PAD(0x05C0, 0x01F0, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH \
+ IOMUX_PAD(0x05C0, 0x01F0, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_ENET_RX_ER__ANATOP_USBOTG_ID \
+ IOMUX_PAD(0x05C4, 0x01F4, 0, 0x0790, 0, 0)
+#define MX6DL_PAD_ENET_RX_ER__ENET_RX_ER \
+ IOMUX_PAD(0x05C4, 0x01F4, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_ENET_RX_ER__ESAI1_HCKR \
+ IOMUX_PAD(0x05C4, 0x01F4, 2, 0x0834, 0, MX6DL_ESAI_PAD_CTRL)
+#define MX6DL_PAD_ENET_RX_ER__SPDIF_IN1 \
+ IOMUX_PAD(0x05C4, 0x01F4, 3, 0x08F0, 1, 0)
+#define MX6DL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT \
+ IOMUX_PAD(0x05C4, 0x01F4, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_ENET_RX_ER__GPIO_1_24 \
+ IOMUX_PAD(0x05C4, 0x01F4, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_ENET_RX_ER__PHY_TDI \
+ IOMUX_PAD(0x05C4, 0x01F4, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD \
+ IOMUX_PAD(0x05C4, 0x01F4, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_ENET_RXD0__OSC32K_32K_OUT \
+ IOMUX_PAD(0x05C8, 0x01F8, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_ENET_RXD0__ENET_RDATA_0 \
+ IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0818, 0, 0)
+#define MX6DL_PAD_ENET_RXD0__ESAI1_HCKT \
+ IOMUX_PAD(0x05C8, 0x01F8, 2, 0x0838, 0, MX6DL_ESAI_PAD_CTRL)
+#define MX6DL_PAD_ENET_RXD0__SPDIF_OUT1 \
+ IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_ENET_RXD0__GPIO_1_27 \
+ IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_ENET_RXD0__PHY_TMS \
+ IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV \
+ IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_ENET_RXD1__MLB_MLBSIG \
+ IOMUX_PAD(0x05CC, 0x01FC, 0, 0x08E4, 0, 0)
+#define MX6DL_PAD_ENET_RXD1__ENET_RDATA_1 \
+ IOMUX_PAD(0x05CC, 0x01FC, 1, 0x081C, 0, 0)
+#define MX6DL_PAD_ENET_RXD1__ESAI1_FST \
+ IOMUX_PAD(0x05CC, 0x01FC, 2, 0x0830, 0, MX6DL_ESAI_PAD_CTRL)
+#define MX6DL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT \
+ IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_ENET_RXD1__GPIO_1_26 \
+ IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_ENET_RXD1__PHY_TCK \
+ IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET \
+ IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_ENET_TX_EN__ENET_TX_EN \
+ IOMUX_PAD(0x05D0, 0x0200, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_ENET_TX_EN__ESAI1_TX3_RX2 \
+ IOMUX_PAD(0x05D0, 0x0200, 2, 0x0850, 0, MX6DL_ESAI_PAD_CTRL)
+#define MX6DL_PAD_ENET_TX_EN__GPIO_1_28 \
+ IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH \
+ IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_ENET_TX_EN__I2C4_SCL \
+ IOMUX_PAD(0x05D0, 0x0200, 9 | IOMUX_CONFIG_SION, 0x0880, 0, MX6DL_I2C_PAD_CTRL)
+
+#define MX6DL_PAD_ENET_TXD0__ENET_TDATA_0 \
+ IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_ENET_TXD0__ESAI1_TX4_RX1 \
+ IOMUX_PAD(0x05D4, 0x0204, 2, 0x0854, 0, MX6DL_ESAI_PAD_CTRL)
+#define MX6DL_PAD_ENET_TXD0__GPIO_1_30 \
+ IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD \
+ IOMUX_PAD(0x05D4, 0x0204, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_ENET_TXD1__MLB_MLBCLK \
+ IOMUX_PAD(0x05D8, 0x0208, 0, 0x08DC, 0, 0)
+#define MX6DL_PAD_ENET_TXD1__ENET_TDATA_1 \
+ IOMUX_PAD(0x05D8, 0x0208, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_ENET_TXD1__ESAI1_TX2_RX3 \
+ IOMUX_PAD(0x05D8, 0x0208, 2, 0x084C, 0, MX6DL_ESAI_PAD_CTRL)
+#define MX6DL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN \
+ IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_ENET_TXD1__GPIO_1_29 \
+ IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD \
+ IOMUX_PAD(0x05D8, 0x0208, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_ENET_TXD1__I2C4_SDA \
+ IOMUX_PAD(0x05D8, 0x0208, 9 | IOMUX_CONFIG_SION, 0x0884, 0, MX6DL_I2C_PAD_CTRL)
+
+#define MX6DL_PAD_GPIO_0__CCM_CLKO \
+ IOMUX_PAD(0x05DC, 0x020C, 0, 0x0000, 0, MX6DL_CCM_CLK0_PAD_CTRL)
+#define MX6DL_PAD_GPIO_0__KPP_COL_5 \
+ IOMUX_PAD(0x05DC, 0x020C, 2, 0x08C0, 1, 0)
+#define MX6DL_PAD_GPIO_0__ASRC_ASRC_EXT_CLK \
+ IOMUX_PAD(0x05DC, 0x020C, 3, 0x0794, 0, 0)
+#define MX6DL_PAD_GPIO_0__EPIT1_EPITO \
+ IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_0__GPIO_1_0 \
+ IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_0__USBOH3_USBH1_PWR \
+ IOMUX_PAD(0x05DC, 0x020C, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 \
+ IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_GPIO_1__ESAI1_SCKR \
+ IOMUX_PAD(0x05E0, 0x0210, 0, 0x083C, 1, 0)
+#define MX6DL_PAD_GPIO_1__WDOG2_WDOG_B \
+ IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_1__KPP_ROW_5 \
+ IOMUX_PAD(0x05E0, 0x0210, 2, 0x08CC, 1, 0)
+#define MX6DL_PAD_GPIO_1__USBOTG_ID \
+ IOMUX_PAD(0x05E0, 0x0210, 3, 0x0790, 1, 0)
+#define MX6DL_PAD_GPIO_1__PWM2_PWMO \
+ IOMUX_PAD(0x05E0, 0x0210, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_1__GPIO_1_1 \
+ IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_1__USDHC1_CD \
+ IOMUX_PAD(0x05E0, 0x0210, 6, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_GPIO_1__SRC_TESTER_ACK \
+ IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_GPIO_16__ESAI1_TX3_RX2 \
+ IOMUX_PAD(0x05E4, 0x0214, 0, 0x0850, 1, 0)
+#define MX6DL_PAD_GPIO_16__ENET_1588_EVENT2_IN \
+ IOMUX_PAD(0x05E4, 0x0214, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT \
+ IOMUX_PAD(0x05E4, 0x0214, 0x12, 0x080C, 0, 0)
+#define MX6DL_PAD_GPIO_16__USDHC1_LCTL \
+ IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_GPIO_16__SPDIF_IN1 \
+ IOMUX_PAD(0x05E4, 0x0214, 4, 0x08F0, 2, 0)
+#define MX6DL_PAD_GPIO_16__GPIO_7_11 \
+ IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_16__I2C3_SDA \
+ IOMUX_PAD(0x05E4, 0x0214, 6 | IOMUX_CONFIG_SION, 0x087C, 1, MX6DL_I2C_PAD_CTRL)
+#define MX6DL_PAD_GPIO_16__SJC_DE_B \
+ IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_GPIO_17__ESAI1_TX0 \
+ IOMUX_PAD(0x05E8, 0x0218, 0, 0x0844, 0, MX6DL_ESAI_PAD_CTRL)
+#define MX6DL_PAD_GPIO_17__ENET_1588_EVENT3_IN \
+ IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_17__CCM_PMIC_RDY \
+ IOMUX_PAD(0x05E8, 0x0218, 2, 0x07D4, 1, 0)
+#define MX6DL_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 \
+ IOMUX_PAD(0x05E8, 0x0218, 3, 0x08E8, 1, 0)
+#define MX6DL_PAD_GPIO_17__SPDIF_OUT1 \
+ IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, MX6DL_SPDIF_OUT_PAD_CTRL)
+#define MX6DL_PAD_GPIO_17__GPIO_7_12 \
+ IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_17__SJC_JTAG_ACT \
+ IOMUX_PAD(0x05E8, 0x0218, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_GPIO_18__ESAI1_TX1 \
+ IOMUX_PAD(0x05EC, 0x021C, 0, 0x0848, 0, 0)
+#define MX6DL_PAD_GPIO_18__ENET_RX_CLK \
+ IOMUX_PAD(0x05EC, 0x021C, 1, 0x0814, 0, 0)
+#define MX6DL_PAD_GPIO_18__USDHC3_VSELECT \
+ IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 \
+ IOMUX_PAD(0x05EC, 0x021C, 3, 0x08EC, 1, 0)
+#define MX6DL_PAD_GPIO_18__ASRC_ASRC_EXT_CLK \
+ IOMUX_PAD(0x05EC, 0x021C, 4, 0x0794, 1, 0)
+#define MX6DL_PAD_GPIO_18__GPIO_7_13 \
+ IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL \
+ IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_18__SRC_SYSTEM_RST \
+ IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_GPIO_19__KPP_COL_5 \
+ IOMUX_PAD(0x05F0, 0x0220, 0, 0x08C0, 2, 0)
+#define MX6DL_PAD_GPIO_19__ENET_1588_EVENT0_OUT \
+ IOMUX_PAD(0x05F0, 0x0220, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_19__SPDIF_OUT1 \
+ IOMUX_PAD(0x05F0, 0x0220, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_19__CCM_CLKO \
+ IOMUX_PAD(0x05F0, 0x0220, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_19__ECSPI1_RDY \
+ IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_19__GPIO_4_5 \
+ IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_19__ENET_TX_ER \
+ IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_19__SRC_INT_BOOT \
+ IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_GPIO_2__ESAI1_FST \
+ IOMUX_PAD(0x05F4, 0x0224, 0, 0x0830, 1, 0)
+#define MX6DL_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 \
+ IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_2__KPP_ROW_6 \
+ IOMUX_PAD(0x05F4, 0x0224, 2, 0x08D0, 1, 0)
+#define MX6DL_PAD_GPIO_2__CCM_CCM_OUT_1 \
+ IOMUX_PAD(0x05F4, 0x0224, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 \
+ IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_2__GPIO_1_2 \
+ IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_2__USDHC2_WP \
+ IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_GPIO_2__MLB_MLBDAT \
+ IOMUX_PAD(0x05F4, 0x0224, 7, 0x08E0, 1, MX6DL_MLB150_PAD_CTRL)
+
+#define MX6DL_PAD_GPIO_3__ESAI1_HCKR \
+ IOMUX_PAD(0x05F8, 0x0228, 0, 0x0834, 1, 0)
+#define MX6DL_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 \
+ IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_3__I2C3_SCL \
+ IOMUX_PAD(0x05F8, 0x0228, 2 | IOMUX_CONFIG_SION, 0x0878, 1, MX6DL_I2C_PAD_CTRL)
+#define MX6DL_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT \
+ IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_3__CCM_CLKO2 \
+ IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_3__GPIO_1_3 \
+ IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_3__USBOH3_USBH1_OC \
+ IOMUX_PAD(0x05F8, 0x0228, 6, 0x0924, 1, 0)
+#define MX6DL_PAD_GPIO_3__MLB_MLBCLK \
+ IOMUX_PAD(0x05F8, 0x0228, 7, 0x08DC, 1, MX6DL_MLB150_PAD_CTRL)
+
+#define MX6DL_PAD_GPIO_4__ESAI1_HCKT \
+ IOMUX_PAD(0x05FC, 0x022C, 0, 0x0838, 1, 0)
+#define MX6DL_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 \
+ IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_4__KPP_COL_7 \
+ IOMUX_PAD(0x05FC, 0x022C, 2, 0x08C8, 1, 0)
+#define MX6DL_PAD_GPIO_4__CCM_CCM_OUT_2 \
+ IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 \
+ IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_4__GPIO_1_4 \
+ IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_4__USDHC2_CD \
+ IOMUX_PAD(0x05FC, 0x022C, 6, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED \
+ IOMUX_PAD(0x05FC, 0x022C, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_GPIO_5__ESAI1_TX2_RX3 \
+ IOMUX_PAD(0x0600, 0x0230, 0, 0x084C, 1, MX6DL_ESAI_PAD_CTRL)
+#define MX6DL_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 \
+ IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_5__KPP_ROW_7 \
+ IOMUX_PAD(0x0600, 0x0230, 2, 0x08D4, 1, 0)
+#define MX6DL_PAD_GPIO_5__CCM_CLKO \
+ IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 \
+ IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_5__GPIO_1_5 \
+ IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_5__I2C3_SCL \
+ IOMUX_PAD(0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, MX6DL_I2C_PAD_CTRL)
+#define MX6DL_PAD_GPIO_5__SIMBA_EVENTI \
+ IOMUX_PAD(0x0600, 0x0230, 7, 0x0000, 0, 0)
+
+#ifdef CONFIG_MX6_ENET_IRQ_TO_GPIO
+#define MX6DL_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 \
+ IOMUX_PAD(0x0604, 0x0234, 1 | IOMUX_CONFIG_SION, 0x0000, 0, ENET_IRQ_PAD_CTRL)
+#else
+#define MX6DL_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 \
+ IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_6__ESAI1_SCKT \
+ IOMUX_PAD(0x0604, 0x0234, 0, 0x0840, 1, 0)
+#define MX6DL_PAD_GPIO_6__I2C3_SDA \
+ IOMUX_PAD(0x0604, 0x0234, 2 | IOMUX_CONFIG_SION, 0x087C, 2, MX6DL_I2C_PAD_CTRL)
+#define MX6DL_PAD_GPIO_6__CCM_CCM_OUT_0 \
+ IOMUX_PAD(0x0604, 0x0234, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_6__CSU_CSU_INT_DEB \
+ IOMUX_PAD(0x0604, 0x0234, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_6__GPIO_1_6 \
+ IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_6__USDHC2_LCTL \
+ IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_GPIO_6__MLB_MLBSIG \
+ IOMUX_PAD(0x0604, 0x0234, 7, 0x08E4, 1, MX6DL_MLB150_PAD_CTRL)
+#endif
+
+#define MX6DL_PAD_GPIO_7__ESAI1_TX4_RX1 \
+ IOMUX_PAD(0x0608, 0x0238, 0, 0x0854, 1, 0)
+#define MX6DL_PAD_GPIO_7__EPIT1_EPITO \
+ IOMUX_PAD(0x0608, 0x0238, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_7__CAN1_TXCAN \
+ IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_7__UART2_TXD \
+ IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_GPIO_7__UART2_RXD \
+ IOMUX_PAD(0x0608, 0x0238, 4, 0x0904, 2, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_GPIO_7__GPIO_1_7 \
+ IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_7__SPDIF_PLOCK \
+ IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE \
+ IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_7__I2C4_SCL \
+ IOMUX_PAD(0x0608, 0x0238, 8 | IOMUX_CONFIG_SION, 0x0880, 1, MX6DL_I2C_PAD_CTRL)
+
+#define MX6DL_PAD_GPIO_8__ESAI1_TX5_RX0 \
+ IOMUX_PAD(0x060C, 0x023C, 0, 0x0858, 1, 0)
+#define MX6DL_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT \
+ IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_8__EPIT2_EPITO \
+ IOMUX_PAD(0x060C, 0x023C, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_8__CAN1_RXCAN \
+ IOMUX_PAD(0x060C, 0x023C, 3, 0x07C8, 0, 0)
+#define MX6DL_PAD_GPIO_8__UART2_TXD \
+ IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_GPIO_8__UART2_RXD \
+ IOMUX_PAD(0x060C, 0x023C, 4, 0x0904, 3, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_GPIO_8__GPIO_1_8 \
+ IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_8__SPDIF_SRCLK \
+ IOMUX_PAD(0x060C, 0x023C, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP \
+ IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_8__I2C4_SDA \
+ IOMUX_PAD(0x060C, 0x023C, 8 | IOMUX_CONFIG_SION, 0x0884, 1, MX6DL_I2C_PAD_CTRL)
+
+#define MX6DL_PAD_GPIO_9__ESAI1_FSR \
+ IOMUX_PAD(0x0610, 0x0240, 0, 0x082C, 1, MX6DL_ESAI_PAD_CTRL)
+#define MX6DL_PAD_GPIO_9__WDOG1_WDOG_B \
+ IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_9__KPP_COL_6 \
+ IOMUX_PAD(0x0610, 0x0240, 2, 0x08C4, 1, 0)
+#define MX6DL_PAD_GPIO_9__CCM_REF_EN_B \
+ IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_9__PWM1_PWMO \
+ IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_9__GPIO_1_9 \
+ IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_GPIO_9__USDHC1_WP \
+ IOMUX_PAD(0x0610, 0x0240, 6, 0x092C, 1, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_GPIO_9__SRC_EARLY_RST \
+ IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_JTAG_MOD__SJC_MOD \
+ IOMUX_PAD(0x0614, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_JTAG_TCK__SJC_TCK \
+ IOMUX_PAD(0x0618, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_JTAG_TDI__SJC_TDI \
+ IOMUX_PAD(0x061C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_JTAG_TDO__SJC_TDO \
+ IOMUX_PAD(0x0620, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_JTAG_TMS__SJC_TMS \
+ IOMUX_PAD(0x0624, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_JTAG_TRSTB__SJC_TRSTB \
+ IOMUX_PAD(0x0628, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_KEY_COL0__ECSPI1_SCLK \
+ IOMUX_PAD(0x062C, 0x0244, 0, 0x07D8, 3, 0)
+#define MX6DL_PAD_KEY_COL0__ENET_RDATA_3 \
+ IOMUX_PAD(0x062C, 0x0244, 1, 0x0824, 0, 0)
+#define MX6DL_PAD_KEY_COL0__AUDMUX_AUD5_TXC \
+ IOMUX_PAD(0x062C, 0x0244, 2, 0x07C0, 1, 0)
+#define MX6DL_PAD_KEY_COL0__KPP_COL_0 \
+ IOMUX_PAD(0x062C, 0x0244, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_KEY_COL0__UART4_TXD \
+ IOMUX_PAD(0x062C, 0x0244, 4, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_KEY_COL0__UART4_RXD \
+ IOMUX_PAD(0x062C, 0x0244, 4, 0x0914, 2, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_KEY_COL0__GPIO_4_6 \
+ IOMUX_PAD(0x062C, 0x0244, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_KEY_COL0__DCIC1_DCIC_OUT \
+ IOMUX_PAD(0x062C, 0x0244, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_KEY_COL0__SRC_ANY_PU_RST \
+ IOMUX_PAD(0x062C, 0x0244, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_KEY_COL1__ECSPI1_MISO \
+ IOMUX_PAD(0x0630, 0x0248, 0, 0x07DC, 3, 0)
+#define MX6DL_PAD_KEY_COL1__ENET_MDIO \
+ IOMUX_PAD(0x0630, 0x0248, 1, 0x0810, 1, MX6DL_ENET_PAD_CTRL)
+#define MX6DL_PAD_KEY_COL1__AUDMUX_AUD5_TXFS \
+ IOMUX_PAD(0x0630, 0x0248, 2, 0x07C4, 1, 0)
+#define MX6DL_PAD_KEY_COL1__KPP_COL_1 \
+ IOMUX_PAD(0x0630, 0x0248, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_KEY_COL1__UART5_TXD \
+ IOMUX_PAD(0x0630, 0x0248, 4, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_KEY_COL1__UART5_RXD \
+ IOMUX_PAD(0x0630, 0x0248, 4, 0x091C, 2, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_KEY_COL1__GPIO_4_8 \
+ IOMUX_PAD(0x0630, 0x0248, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_KEY_COL1__USDHC1_VSELECT \
+ IOMUX_PAD(0x0630, 0x0248, 6, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_KEY_COL1__PL301_SIM_MX6DL_PER1_HADDR_1 \
+ IOMUX_PAD(0x0630, 0x0248, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_KEY_COL2__ECSPI1_SS1 \
+ IOMUX_PAD(0x0634, 0x024C, 0, 0x07E8, 2, 0)
+#define MX6DL_PAD_KEY_COL2__ENET_RDATA_2 \
+ IOMUX_PAD(0x0634, 0x024C, 1, 0x0820, 0, 0)
+#define MX6DL_PAD_KEY_COL2__CAN1_TXCAN \
+ IOMUX_PAD(0x0634, 0x024C, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_KEY_COL2__KPP_COL_2 \
+ IOMUX_PAD(0x0634, 0x024C, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_KEY_COL2__ENET_MDC \
+ IOMUX_PAD(0x0634, 0x024C, 4, 0x0000, 0, MX6DL_ENET_PAD_CTRL)
+#define MX6DL_PAD_KEY_COL2__GPIO_4_10 \
+ IOMUX_PAD(0x0634, 0x024C, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP \
+ IOMUX_PAD(0x0634, 0x024C, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_KEY_COL2__PL301_SIM_MX6DL_PER1_HADDR_3 \
+ IOMUX_PAD(0x0634, 0x024C, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_KEY_COL3__ECSPI1_SS3 \
+ IOMUX_PAD(0x0638, 0x0250, 0, 0x07F0, 1, 0)
+#define MX6DL_PAD_KEY_COL3__ENET_CRS \
+ IOMUX_PAD(0x0638, 0x0250, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_KEY_COL3__HDMI_TX_DDC_SCL \
+ IOMUX_PAD(0x0638, 0x0250, 2 | IOMUX_CONFIG_SION, 0x0860, 1, \
+ MX6DL_I2C_PAD_CTRL)
+#define MX6DL_PAD_KEY_COL3__KPP_COL_3 \
+ IOMUX_PAD(0x0638, 0x0250, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_KEY_COL3__I2C2_SCL \
+ IOMUX_PAD(0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, \
+ MX6DL_I2C_PAD_CTRL)
+#define MX6DL_PAD_KEY_COL3__GPIO_4_12 \
+ IOMUX_PAD(0x0638, 0x0250, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_KEY_COL3__SPDIF_IN1 \
+ IOMUX_PAD(0x0638, 0x0250, 6, 0x08F0, 3, 0)
+#define MX6DL_PAD_KEY_COL3__PL301_SIM_MX6DL_PER1_HADDR_5 \
+ IOMUX_PAD(0x0638, 0x0250, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_KEY_COL4__CAN2_TXCAN \
+ IOMUX_PAD(0x063C, 0x0254, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_KEY_COL4__IPU1_SISG_4 \
+ IOMUX_PAD(0x063C, 0x0254, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_KEY_COL4__USBOH3_USBOTG_OC \
+ IOMUX_PAD(0x063C, 0x0254, 2, 0x0920, 1, 0)
+#define MX6DL_PAD_KEY_COL4__KPP_COL_4 \
+ IOMUX_PAD(0x063C, 0x0254, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_KEY_COL4__UART5_CTS \
+ IOMUX_PAD(0x063C, 0x0254, 4, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_KEY_COL4__UART5_RTS \
+ IOMUX_PAD(0x063C, 0x0254, 4, 0x0918, 2, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_KEY_COL4__GPIO_4_14 \
+ IOMUX_PAD(0x063C, 0x0254, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 \
+ IOMUX_PAD(0x063C, 0x0254, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_KEY_COL4__PL301_SIM_MX6DL_PER1_HADDR_7 \
+ IOMUX_PAD(0x063C, 0x0254, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_KEY_ROW0__ECSPI1_MOSI \
+ IOMUX_PAD(0x0640, 0x0258, 0, 0x07E0, 3, 0)
+#define MX6DL_PAD_KEY_ROW0__ENET_TDATA_3 \
+ IOMUX_PAD(0x0640, 0x0258, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_KEY_ROW0__AUDMUX_AUD5_TXD \
+ IOMUX_PAD(0x0640, 0x0258, 2, 0x07B4, 1, 0)
+#define MX6DL_PAD_KEY_ROW0__KPP_ROW_0 \
+ IOMUX_PAD(0x0640, 0x0258, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_KEY_ROW0__UART4_TXD \
+ IOMUX_PAD(0x0640, 0x0258, 4, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_KEY_ROW0__UART4_RXD \
+ IOMUX_PAD(0x0640, 0x0258, 4, 0x0914, 3, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_KEY_ROW0__GPIO_4_7 \
+ IOMUX_PAD(0x0640, 0x0258, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_KEY_ROW0__DCIC2_DCIC_OUT \
+ IOMUX_PAD(0x0640, 0x0258, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_KEY_ROW0__PL301_SIM_MX6DL_PER1_HADDR_0 \
+ IOMUX_PAD(0x0640, 0x0258, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_KEY_ROW1__ECSPI1_SS0 \
+ IOMUX_PAD(0x0644, 0x025C, 0, 0x07E4, 3, 0)
+#define MX6DL_PAD_KEY_ROW1__ENET_COL \
+ IOMUX_PAD(0x0644, 0x025C, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_KEY_ROW1__AUDMUX_AUD5_RXD \
+ IOMUX_PAD(0x0644, 0x025C, 2, 0x07B0, 1, 0)
+#define MX6DL_PAD_KEY_ROW1__KPP_ROW_1 \
+ IOMUX_PAD(0x0644, 0x025C, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_KEY_ROW1__UART5_TXD \
+ IOMUX_PAD(0x0644, 0x025C, 4, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_KEY_ROW1__UART5_RXD \
+ IOMUX_PAD(0x0644, 0x025C, 4, 0x091C, 3, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_KEY_ROW1__GPIO_4_9 \
+ IOMUX_PAD(0x0644, 0x025C, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_KEY_ROW1__USDHC2_VSELECT \
+ IOMUX_PAD(0x0644, 0x025C, 6, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_KEY_ROW1__PL301_SIM_MX6DL_PER1_HADDR_2 \
+ IOMUX_PAD(0x0644, 0x025C, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_KEY_ROW2__ECSPI1_SS2 \
+ IOMUX_PAD(0x0648, 0x0260, 0, 0x07EC, 1, 0)
+#define MX6DL_PAD_KEY_ROW2__ENET_TDATA_2 \
+ IOMUX_PAD(0x0648, 0x0260, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_KEY_ROW2__CAN1_RXCAN \
+ IOMUX_PAD(0x0648, 0x0260, 2, 0x07C8, 1, 0)
+#define MX6DL_PAD_KEY_ROW2__KPP_ROW_2 \
+ IOMUX_PAD(0x0648, 0x0260, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_KEY_ROW2__USDHC2_VSELECT \
+ IOMUX_PAD(0x0648, 0x0260, 4, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_KEY_ROW2__GPIO_4_11 \
+ IOMUX_PAD(0x0648, 0x0260, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE \
+ IOMUX_PAD(0x0648, 0x0260, 6, 0x085C, 1, 0)
+#define MX6DL_PAD_KEY_ROW2__PL301_SIM_MX6DL_PER1_HADDR_4 \
+ IOMUX_PAD(0x0648, 0x0260, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_KEY_ROW3__OSC32K_32K_OUT \
+ IOMUX_PAD(0x064C, 0x0264, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK \
+ IOMUX_PAD(0x064C, 0x0264, 1, 0x0794, 2, 0)
+#define MX6DL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA \
+ IOMUX_PAD(0x064C, 0x0264, 2 | IOMUX_CONFIG_SION, 0x0864, 1, \
+ MX6DL_I2C_PAD_CTRL)
+#define MX6DL_PAD_KEY_ROW3__KPP_ROW_3 \
+ IOMUX_PAD(0x064C, 0x0264, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_KEY_ROW3__I2C2_SDA \
+ IOMUX_PAD(0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, \
+ MX6DL_I2C_PAD_CTRL)
+#define MX6DL_PAD_KEY_ROW3__GPIO_4_13 \
+ IOMUX_PAD(0x064C, 0x0264, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_KEY_ROW3__USDHC1_VSELECT \
+ IOMUX_PAD(0x064C, 0x0264, 6, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_KEY_ROW3__PL301_SIM_MX6DL_PER1_HADDR_6 \
+ IOMUX_PAD(0x064C, 0x0264, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_KEY_ROW4__CAN2_RXCAN \
+ IOMUX_PAD(0x0650, 0x0268, 0, 0x07CC, 0, 0)
+#define MX6DL_PAD_KEY_ROW4__IPU1_SISG_5 \
+ IOMUX_PAD(0x0650, 0x0268, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_KEY_ROW4__USBOH3_USBOTG_PWR \
+ IOMUX_PAD(0x0650, 0x0268, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_KEY_ROW4__KPP_ROW_4 \
+ IOMUX_PAD(0x0650, 0x0268, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_KEY_ROW4__UART5_CTS \
+ IOMUX_PAD(0x0650, 0x0268, 4, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_KEY_ROW4__UART5_RTS \
+ IOMUX_PAD(0x0650, 0x0268, 4, 0x0918, 3, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_KEY_ROW4__GPIO_4_15 \
+ IOMUX_PAD(0x0650, 0x0268, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 \
+ IOMUX_PAD(0x0650, 0x0268, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_KEY_ROW4__PL301_SIM_MX6DL_PER1_HADDR_8 \
+ IOMUX_PAD(0x0650, 0x0268, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_NANDF_ALE__RAWNAND_ALE \
+ IOMUX_PAD(0x0654, 0x026C, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_ALE__USDHC4_RST \
+ IOMUX_PAD(0x0654, 0x026C, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 \
+ IOMUX_PAD(0x0654, 0x026C, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 \
+ IOMUX_PAD(0x0654, 0x026C, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 \
+ IOMUX_PAD(0x0654, 0x026C, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_ALE__GPIO_6_8 \
+ IOMUX_PAD(0x0654, 0x026C, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 \
+ IOMUX_PAD(0x0654, 0x026C, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_ALE__USDHC3_CLKI \
+ IOMUX_PAD(0x0654, 0x026C, 8, 0x0934, 0, MX6DL_USDHC_PAD_CTRL)
+
+#define MX6DL_PAD_NANDF_CLE__RAWNAND_CLE \
+ IOMUX_PAD(0x0658, 0x0270, 0, 0x0000, 0, MX6DL_GPMI_PAD_CTRL2)
+#define MX6DL_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 \
+ IOMUX_PAD(0x0658, 0x0270, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 \
+ IOMUX_PAD(0x0658, 0x0270, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 \
+ IOMUX_PAD(0x0658, 0x0270, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_CLE__GPIO_6_7 \
+ IOMUX_PAD(0x0658, 0x0270, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 \
+ IOMUX_PAD(0x0658, 0x0270, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_CLE__USDHC3_CLKO \
+ IOMUX_PAD(0x0658, 0x0270, 8, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+
+#define MX6DL_PAD_NANDF_CS0__RAWNAND_CE0N \
+ IOMUX_PAD(0x065C, 0x0274, 0, 0x0000, 0, MX6DL_GPMI_PAD_CTRL2)
+#define MX6DL_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 \
+ IOMUX_PAD(0x065C, 0x0274, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 \
+ IOMUX_PAD(0x065C, 0x0274, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_CS0__GPIO_6_11 \
+ IOMUX_PAD(0x065C, 0x0274, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_CS0__USDHC1_CLKO \
+ IOMUX_PAD(0x065C, 0x0274, 8, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+
+#define MX6DL_PAD_NANDF_CS1__RAWNAND_CE1N \
+ IOMUX_PAD(0x0660, 0x0278, 0, 0x0000, 0, MX6DL_GPMI_PAD_CTRL2)
+#define MX6DL_PAD_NANDF_CS1__USDHC4_VSELECT \
+ IOMUX_PAD(0x0660, 0x0278, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_NANDF_CS1__USDHC3_VSELECT \
+ IOMUX_PAD(0x0660, 0x0278, 2, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 \
+ IOMUX_PAD(0x0660, 0x0278, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_CS1__GPIO_6_14 \
+ IOMUX_PAD(0x0660, 0x0278, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_CS1__PL301_SIM_MX6DL_PER1_HREADYOUT \
+ IOMUX_PAD(0x0660, 0x0278, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_CS1__USDHC1_CLKI \
+ IOMUX_PAD(0x0660, 0x0278, 8, 0x0928, 0, MX6DL_USDHC_PAD_CTRL)
+
+#define MX6DL_PAD_NANDF_CS2__RAWNAND_CE2N \
+ IOMUX_PAD(0x0664, 0x027C, 0, 0x0000, 0, MX6DL_GPMI_PAD_CTRL2)
+#define MX6DL_PAD_NANDF_CS2__IPU1_SISG_0 \
+ IOMUX_PAD(0x0664, 0x027C, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_CS2__ESAI1_TX0 \
+ IOMUX_PAD(0x0664, 0x027C, 2, 0x0844, 1, MX6DL_ESAI_PAD_CTRL)
+#define MX6DL_PAD_NANDF_CS2__WEIM_WEIM_CRE \
+ IOMUX_PAD(0x0664, 0x027C, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_CS2__CCM_CLKO2 \
+ IOMUX_PAD(0x0664, 0x027C, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_CS2__GPIO_6_15 \
+ IOMUX_PAD(0x0664, 0x027C, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_CS2__USDHC2_CLKO \
+ IOMUX_PAD(0x0664, 0x027C, 8, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+
+#define MX6DL_PAD_NANDF_CS3__RAWNAND_CE3N \
+ IOMUX_PAD(0x0668, 0x0280, 0, 0x0000, 0, MX6DL_GPMI_PAD_CTRL2)
+#define MX6DL_PAD_NANDF_CS3__IPU1_SISG_1 \
+ IOMUX_PAD(0x0668, 0x0280, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_CS3__ESAI1_TX1 \
+ IOMUX_PAD(0x0668, 0x0280, 2, 0x0848, 1, MX6DL_ESAI_PAD_CTRL)
+#define MX6DL_PAD_NANDF_CS3__WEIM_WEIM_A_26 \
+ IOMUX_PAD(0x0668, 0x0280, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 \
+ IOMUX_PAD(0x0668, 0x0280, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_CS3__GPIO_6_16 \
+ IOMUX_PAD(0x0668, 0x0280, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_CS3__TPSMP_CLK \
+ IOMUX_PAD(0x0668, 0x0280, 7, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_CS3__USDHC2_CLKI \
+ IOMUX_PAD(0x0668, 0x0280, 8, 0x0930, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_NANDF_CS3__I2C4_SDA \
+ IOMUX_PAD(0x0668, 0x0280, 9 | IOMUX_CONFIG_SION, 0x0884, 2, MX6DL_I2C_PAD_CTRL)
+
+#define MX6DL_PAD_NANDF_D0__RAWNAND_D0 \
+ IOMUX_PAD(0x066C, 0x0284, 0, 0x0000, 0, MX6DL_GPMI_PAD_CTRL2)
+#define MX6DL_PAD_NANDF_D0__USDHC1_DAT4 \
+ IOMUX_PAD(0x066C, 0x0284, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 \
+ IOMUX_PAD(0x066C, 0x0284, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 \
+ IOMUX_PAD(0x066C, 0x0284, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 \
+ IOMUX_PAD(0x066C, 0x0284, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_D0__GPIO_2_0 \
+ IOMUX_PAD(0x066C, 0x0284, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 \
+ IOMUX_PAD(0x066C, 0x0284, 6, 0x0000, 0, 0)
+
+#define MX6DL_PAD_NANDF_D1__RAWNAND_D1 \
+ IOMUX_PAD(0x0670, 0x0288, 0, 0x0000, 0, MX6DL_GPMI_PAD_CTRL2)
+#define MX6DL_PAD_NANDF_D1__USDHC1_DAT5 \
+ IOMUX_PAD(0x0670, 0x0288, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 \
+ IOMUX_PAD(0x0670, 0x0288, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 \
+ IOMUX_PAD(0x0670, 0x0288, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 \
+ IOMUX_PAD(0x0670, 0x0288, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_D1__GPIO_2_1 \
+ IOMUX_PAD(0x0670, 0x0288, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 \
+ IOMUX_PAD(0x0670, 0x0288, 6, 0x0000, 0, 0)
+
+#define MX6DL_PAD_NANDF_D2__RAWNAND_D2 \
+ IOMUX_PAD(0x0674, 0x028C, 0, 0x0000, 0, MX6DL_GPMI_PAD_CTRL2)
+#define MX6DL_PAD_NANDF_D2__USDHC1_DAT6 \
+ IOMUX_PAD(0x0674, 0x028C, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 \
+ IOMUX_PAD(0x0674, 0x028C, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 \
+ IOMUX_PAD(0x0674, 0x028C, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 \
+ IOMUX_PAD(0x0674, 0x028C, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_D2__GPIO_2_2 \
+ IOMUX_PAD(0x0674, 0x028C, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 \
+ IOMUX_PAD(0x0674, 0x028C, 6, 0x0000, 0, 0)
+
+#define MX6DL_PAD_NANDF_D3__RAWNAND_D3 \
+ IOMUX_PAD(0x0678, 0x0290, 0, 0x0000, 0, MX6DL_GPMI_PAD_CTRL2)
+#define MX6DL_PAD_NANDF_D3__USDHC1_DAT7 \
+ IOMUX_PAD(0x0678, 0x0290, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 \
+ IOMUX_PAD(0x0678, 0x0290, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 \
+ IOMUX_PAD(0x0678, 0x0290, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 \
+ IOMUX_PAD(0x0678, 0x0290, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_D3__GPIO_2_3 \
+ IOMUX_PAD(0x0678, 0x0290, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 \
+ IOMUX_PAD(0x0678, 0x0290, 6, 0x0000, 0, 0)
+
+#define MX6DL_PAD_NANDF_D4__RAWNAND_D4 \
+ IOMUX_PAD(0x067C, 0x0294, 0, 0x0000, 0, MX6DL_GPMI_PAD_CTRL2)
+#define MX6DL_PAD_NANDF_D4__USDHC2_DAT4 \
+ IOMUX_PAD(0x067C, 0x0294, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 \
+ IOMUX_PAD(0x067C, 0x0294, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 \
+ IOMUX_PAD(0x067C, 0x0294, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 \
+ IOMUX_PAD(0x067C, 0x0294, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_D4__GPIO_2_4 \
+ IOMUX_PAD(0x067C, 0x0294, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 \
+ IOMUX_PAD(0x067C, 0x0294, 6, 0x0000, 0, 0)
+
+#define MX6DL_PAD_NANDF_D5__RAWNAND_D5 \
+ IOMUX_PAD(0x0680, 0x0298, 0, 0x0000, 0, MX6DL_GPMI_PAD_CTRL2)
+#define MX6DL_PAD_NANDF_D5__USDHC2_DAT5 \
+ IOMUX_PAD(0x0680, 0x0298, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 \
+ IOMUX_PAD(0x0680, 0x0298, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 \
+ IOMUX_PAD(0x0680, 0x0298, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 \
+ IOMUX_PAD(0x0680, 0x0298, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_D5__GPIO_2_5 \
+ IOMUX_PAD(0x0680, 0x0298, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 \
+ IOMUX_PAD(0x0680, 0x0298, 6, 0x0000, 0, 0)
+
+#define MX6DL_PAD_NANDF_D6__RAWNAND_D6 \
+ IOMUX_PAD(0x0684, 0x029C, 0, 0x0000, 0, MX6DL_GPMI_PAD_CTRL2)
+#define MX6DL_PAD_NANDF_D6__USDHC2_DAT6 \
+ IOMUX_PAD(0x0684, 0x029C, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 \
+ IOMUX_PAD(0x0684, 0x029C, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 \
+ IOMUX_PAD(0x0684, 0x029C, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 \
+ IOMUX_PAD(0x0684, 0x029C, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_D6__GPIO_2_6 \
+ IOMUX_PAD(0x0684, 0x029C, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 \
+ IOMUX_PAD(0x0684, 0x029C, 6, 0x0000, 0, 0)
+
+#define MX6DL_PAD_NANDF_D7__RAWNAND_D7 \
+ IOMUX_PAD(0x0688, 0x02A0, 0, 0x0000, 0, MX6DL_GPMI_PAD_CTRL2)
+#define MX6DL_PAD_NANDF_D7__USDHC2_DAT7 \
+ IOMUX_PAD(0x0688, 0x02A0, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 \
+ IOMUX_PAD(0x0688, 0x02A0, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 \
+ IOMUX_PAD(0x0688, 0x02A0, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 \
+ IOMUX_PAD(0x0688, 0x02A0, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_D7__GPIO_2_7 \
+ IOMUX_PAD(0x0688, 0x02A0, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 \
+ IOMUX_PAD(0x0688, 0x02A0, 6, 0x0000, 0, 0)
+
+#define MX6DL_PAD_NANDF_RB0__RAWNAND_READY0 \
+ IOMUX_PAD(0x068C, 0x02A4, 0, 0x0000, 0, MX6DL_GPMI_PAD_CTRL0)
+#define MX6DL_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 \
+ IOMUX_PAD(0x068C, 0x02A4, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 \
+ IOMUX_PAD(0x068C, 0x02A4, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 \
+ IOMUX_PAD(0x068C, 0x02A4, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_RB0__GPIO_6_10 \
+ IOMUX_PAD(0x068C, 0x02A4, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 \
+ IOMUX_PAD(0x068C, 0x02A4, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_RB0__USDHC4_CLKI \
+ IOMUX_PAD(0x068C, 0x02A4, 8, 0x0938, 0, MX6DL_USDHC_PAD_CTRL)
+
+#define MX6DL_PAD_NANDF_WP_B__RAWNAND_RESETN \
+ IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, MX6DL_GPMI_PAD_CTRL2)
+#define MX6DL_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 \
+ IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 \
+ IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 \
+ IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_WP_B__GPIO_6_9 \
+ IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 \
+ IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_NANDF_WP_B__USDHC4_CLKO \
+ IOMUX_PAD(0x0690, 0x02A8, 8, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_NANDF_WP_B__I2C4_SCL \
+ IOMUX_PAD(0x0690, 0x02A8, 9 | IOMUX_CONFIG_SION, 0x0880, 2, MX6DL_I2C_PAD_CTRL)
+
+#define MX6DL_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_POR_B__SRC_POR_B \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_RESET_IN_B__SRC_RESET_B \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6DL_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY \
+ IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_RGMII_RD0__ENET_RGMII_RD0 \
+ IOMUX_PAD(0x0694, 0x02AC, 1, 0x0818, 1, MX6DL_ENET_PAD_CTRL)
+#define MX6DL_PAD_RGMII_RD0__GPIO_6_25 \
+ IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 \
+ IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, 0)
+
+#define MX6DL_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG \
+ IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_RGMII_RD1__ENET_RGMII_RD1 \
+ IOMUX_PAD(0x0698, 0x02B0, 1, 0x081C, 1, MX6DL_ENET_PAD_CTRL)
+#define MX6DL_PAD_RGMII_RD1__GPIO_6_27 \
+ IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 \
+ IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_RGMII_RD1__SJC_FAIL \
+ IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA \
+ IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_RGMII_RD2__ENET_RGMII_RD2 \
+ IOMUX_PAD(0x069C, 0x02B4, 1, 0x0820, 1, MX6DL_ENET_PAD_CTRL)
+#define MX6DL_PAD_RGMII_RD2__GPIO_6_28 \
+ IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 \
+ IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0)
+
+#define MX6DL_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE \
+ IOMUX_PAD(0x06A0, 0x02B8, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_RGMII_RD3__ENET_RGMII_RD3 \
+ IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0824, 1, MX6DL_ENET_PAD_CTRL)
+#define MX6DL_PAD_RGMII_RD3__GPIO_6_29 \
+ IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 \
+ IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, 0)
+
+#define MX6DL_PAD_RGMII_RX_CTL__USBOH3_H3_DATA \
+ IOMUX_PAD(0x06A4, 0x02BC, 0 | IOMUX_CONFIG_SION, 0x0000, 0, MX6DL_USB_HSIC_PAD_CTRL)
+#define MX6DL_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL \
+ IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0828, 1, MX6DL_ENET_PAD_CTRL)
+#define MX6DL_PAD_RGMII_RX_CTL__GPIO_6_24 \
+ IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 \
+ IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0)
+
+#define MX6DL_PAD_RGMII_RXC__USBOH3_H3_STROBE \
+ IOMUX_PAD(0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, MX6DL_USB_HSIC_PAD_CTRL)
+#define MX6DL_PAD_RGMII_RXC__USBOH3_H3_STROBE_START \
+ IOMUX_PAD(0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, MX6DL_USB_HSIC_PAD_CTRL | MX6_PAD_CTL_PUS_47K_UP)
+#define MX6DL_PAD_RGMII_RXC__ENET_RGMII_RXC \
+ IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0814, 1, MX6DL_ENET_PAD_CTRL)
+#define MX6DL_PAD_RGMII_RXC__GPIO_6_30 \
+ IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 \
+ IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, 0)
+
+#define MX6DL_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY \
+ IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_RGMII_TD0__ENET_RGMII_TD0 \
+ IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, MX6DL_ENET_PAD_CTRL)
+#define MX6DL_PAD_RGMII_TD0__GPIO_6_20 \
+ IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 \
+ IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0)
+
+#define MX6DL_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG \
+ IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_RGMII_TD1__ENET_RGMII_TD1 \
+ IOMUX_PAD(0x06B0, 0x02C8, 1, 0x0000, 0, MX6DL_ENET_PAD_CTRL)
+#define MX6DL_PAD_RGMII_TD1__GPIO_6_21 \
+ IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 \
+ IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_RGMII_TD1__CCM_PLL3_BYP \
+ IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA \
+ IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_RGMII_TD2__ENET_RGMII_TD2 \
+ IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 0, MX6DL_ENET_PAD_CTRL)
+#define MX6DL_PAD_RGMII_TD2__GPIO_6_22 \
+ IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 \
+ IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_RGMII_TD2__CCM_PLL2_BYP \
+ IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE \
+ IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_RGMII_TD3__ENET_RGMII_TD3 \
+ IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, MX6DL_ENET_PAD_CTRL)
+#define MX6DL_PAD_RGMII_TD3__GPIO_6_23 \
+ IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 \
+ IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, 0)
+
+#define MX6DL_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE \
+ IOMUX_PAD(0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, MX6DL_USB_HSIC_PAD_CTRL)
+#define MX6DL_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE_START \
+ IOMUX_PAD(0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, MX6DL_USB_HSIC_PAD_CTRL | MX6_PAD_CTL_PUS_47K_UP)
+#define MX6DL_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL \
+ IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, MX6DL_ENET_PAD_CTRL)
+#define MX6DL_PAD_RGMII_TX_CTL__GPIO_6_26 \
+ IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 \
+ IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT \
+ IOMUX_PAD(0x06BC, 0x02D4, 7, 0x080C, 1, 0)
+
+#define MX6DL_PAD_RGMII_TXC__USBOH3_H2_DATA \
+ IOMUX_PAD(0x06C0, 0x02D8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, MX6DL_USB_HSIC_PAD_CTRL)
+#define MX6DL_PAD_RGMII_TXC__ENET_RGMII_TXC \
+ IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0)
+#define MX6DL_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK \
+ IOMUX_PAD(0x06C0, 0x02D8, 2, 0x08F4, 1, 0)
+#define MX6DL_PAD_RGMII_TXC__GPIO_6_19 \
+ IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 \
+ IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT \
+ IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_SD1_CLK__USDHC1_CLK \
+ IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0928, 1, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_SD1_CLK__USDHC1_CLK_50MHZ_40OHM \
+ IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0928, 1, MX6DL_USDHC_PAD_CTRL_50MHZ_40OHM)
+#define MX6DL_PAD_SD1_CLK__OSC32K_32K_OUT \
+ IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_SD1_CLK__GPT_CLKIN \
+ IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_SD1_CLK__GPIO_1_20 \
+ IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_SD1_CLK__PHY_DTB_0 \
+ IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, 0)
+
+#define MX6DL_PAD_SD1_CMD__USDHC1_CMD \
+ IOMUX_PAD(0x06C8, 0x02E0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_SD1_CMD__USDHC1_CMD_50MHZ_40OHM \
+ IOMUX_PAD(0x06C8, 0x02E0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_50MHZ_40OHM)
+#define MX6DL_PAD_SD1_CMD__PWM4_PWMO \
+ IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_SD1_CMD__GPT_CMPOUT1 \
+ IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_SD1_CMD__GPIO_1_18 \
+ IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 \
+ IOMUX_PAD(0x06C8, 0x02E0, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_SD1_DAT0__USDHC1_DAT0 \
+ IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_SD1_DAT0__USDHC1_DAT0_50MHZ_40OHM \
+ IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_50MHZ_40OHM)
+#define MX6DL_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS \
+ IOMUX_PAD(0x06CC, 0x02E4, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_SD1_DAT0__GPT_CAPIN1 \
+ IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 \
+ IOMUX_PAD(0x06CC, 0x02E4, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_SD1_DAT0__GPIO_1_16 \
+ IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 \
+ IOMUX_PAD(0x06CC, 0x02E4, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 \
+ IOMUX_PAD(0x06CC, 0x02E4, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_SD1_DAT1__USDHC1_DAT1 \
+ IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_SD1_DAT1__USDHC1_DAT1_50MHZ_40OHM \
+ IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_50MHZ_40OHM)
+#define MX6DL_PAD_SD1_DAT1__PWM3_PWMO \
+ IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_SD1_DAT1__GPT_CAPIN2 \
+ IOMUX_PAD(0x06D0, 0x02E8, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 \
+ IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_SD1_DAT1__GPIO_1_17 \
+ IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 \
+ IOMUX_PAD(0x06D0, 0x02E8, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 \
+ IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_SD1_DAT2__USDHC1_DAT2 \
+ IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_SD1_DAT2__USDHC1_DAT2_50MHZ_40OHM \
+ IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_50MHZ_40OHM)
+#define MX6DL_PAD_SD1_DAT2__GPT_CMPOUT2 \
+ IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_SD1_DAT2__PWM2_PWMO \
+ IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_SD1_DAT2__WDOG1_WDOG_B \
+ IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_SD1_DAT2__GPIO_1_19 \
+ IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB \
+ IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 \
+ IOMUX_PAD(0x06D4, 0x02EC, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_SD1_DAT3__USDHC1_DAT3 \
+ IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_SD1_DAT3__USDHC1_DAT3_50MHZ_40OHM \
+ IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_50MHZ_40OHM)
+#define MX6DL_PAD_SD1_DAT3__GPT_CMPOUT3 \
+ IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_SD1_DAT3__PWM1_PWMO \
+ IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_SD1_DAT3__WDOG2_WDOG_B \
+ IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_SD1_DAT3__GPIO_1_21 \
+ IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB \
+ IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 \
+ IOMUX_PAD(0x06D8, 0x02F0, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_SD2_CLK__USDHC2_CLK \
+ IOMUX_PAD(0x06DC, 0x02F4, 0, 0x0930, 1, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_SD2_CLK__KPP_COL_5 \
+ IOMUX_PAD(0x06DC, 0x02F4, 2, 0x08C0, 3, 0)
+#define MX6DL_PAD_SD2_CLK__AUDMUX_AUD4_RXFS \
+ IOMUX_PAD(0x06DC, 0x02F4, 3, 0x07A4, 1, 0)
+#define MX6DL_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 \
+ IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_SD2_CLK__GPIO_1_10 \
+ IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_SD2_CLK__PHY_DTB_1 \
+ IOMUX_PAD(0x06DC, 0x02F4, 6, 0x0000, 0, 0)
+
+#define MX6DL_PAD_SD2_CMD__USDHC2_CMD \
+ IOMUX_PAD(0x06E0, 0x02F8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_SD2_CMD__KPP_ROW_5 \
+ IOMUX_PAD(0x06E0, 0x02F8, 2, 0x08CC, 2, 0)
+#define MX6DL_PAD_SD2_CMD__AUDMUX_AUD4_RXC \
+ IOMUX_PAD(0x06E0, 0x02F8, 3, 0x07A0, 1, 0)
+#define MX6DL_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 \
+ IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_SD2_CMD__GPIO_1_11 \
+ IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0)
+
+#define MX6DL_PAD_SD2_DAT0__USDHC2_DAT0 \
+ IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_SD2_DAT0__AUDMUX_AUD4_RXD \
+ IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0798, 1, 0)
+#define MX6DL_PAD_SD2_DAT0__KPP_ROW_7 \
+ IOMUX_PAD(0x06E4, 0x02FC, 4, 0x08D4, 2, 0)
+#define MX6DL_PAD_SD2_DAT0__GPIO_1_15 \
+ IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_SD2_DAT0__DCIC2_DCIC_OUT \
+ IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 \
+ IOMUX_PAD(0x06E4, 0x02FC, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_SD2_DAT1__USDHC2_DAT1 \
+ IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_SD2_DAT1__WEIM_WEIM_CS_2 \
+ IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS \
+ IOMUX_PAD(0x06E8, 0x0300, 3, 0x07AC, 1, 0)
+#define MX6DL_PAD_SD2_DAT1__KPP_COL_7 \
+ IOMUX_PAD(0x06E8, 0x0300, 4, 0x08C8, 2, 0)
+#define MX6DL_PAD_SD2_DAT1__GPIO_1_14 \
+ IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_SD2_DAT1__CCM_WAIT \
+ IOMUX_PAD(0x06E8, 0x0300, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 \
+ IOMUX_PAD(0x06E8, 0x0300, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_SD2_DAT2__USDHC2_DAT2 \
+ IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_SD2_DAT2__WEIM_WEIM_CS_3 \
+ IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_SD2_DAT2__AUDMUX_AUD4_TXD \
+ IOMUX_PAD(0x06EC, 0x0304, 3, 0x079C, 1, 0)
+#define MX6DL_PAD_SD2_DAT2__KPP_ROW_6 \
+ IOMUX_PAD(0x06EC, 0x0304, 4, 0x08D0, 2, 0)
+#define MX6DL_PAD_SD2_DAT2__GPIO_1_13 \
+ IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_SD2_DAT2__CCM_STOP \
+ IOMUX_PAD(0x06EC, 0x0304, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 \
+ IOMUX_PAD(0x06EC, 0x0304, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_SD2_DAT3__USDHC2_DAT3 \
+ IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_SD2_DAT3__KPP_COL_6 \
+ IOMUX_PAD(0x06F0, 0x0308, 2, 0x08C4, 2, 0)
+#define MX6DL_PAD_SD2_DAT3__AUDMUX_AUD4_TXC \
+ IOMUX_PAD(0x06F0, 0x0308, 3, 0x07A8, 1, 0)
+#define MX6DL_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 \
+ IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_SD2_DAT3__GPIO_1_12 \
+ IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_SD2_DAT3__SJC_DONE \
+ IOMUX_PAD(0x06F0, 0x0308, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 \
+ IOMUX_PAD(0x06F0, 0x0308, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_SD3_CLK__USDHC3_CLK_50MHZ \
+ IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_SD3_CLK__USDHC3_CLK_100MHZ \
+ IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, MX6DL_USDHC_PAD_CTRL_100MHZ)
+#define MX6DL_PAD_SD3_CLK__USDHC3_CLK_200MHZ \
+ IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, MX6DL_USDHC_PAD_CTRL_200MHZ)
+#define MX6DL_PAD_SD3_CLK__UART2_CTS \
+ IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_SD3_CLK__UART2_RTS \
+ IOMUX_PAD(0x06F4, 0x030C, 1, 0x0900, 2, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_SD3_CLK__CAN1_RXCAN \
+ IOMUX_PAD(0x06F4, 0x030C, 2, 0x07C8, 2, 0)
+#define MX6DL_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 \
+ IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 \
+ IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_CLK__GPIO_7_3 \
+ IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 \
+ IOMUX_PAD(0x06F4, 0x030C, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 \
+ IOMUX_PAD(0x06F4, 0x030C, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_SD3_CMD__USDHC3_CMD_50MHZ \
+ IOMUX_PAD(0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_SD3_CMD__USDHC3_CMD_100MHZ \
+ IOMUX_PAD(0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_100MHZ)
+#define MX6DL_PAD_SD3_CMD__USDHC3_CMD_200MHZ \
+ IOMUX_PAD(0x06F8, 0x0310, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_200MHZ)
+#define MX6DL_PAD_SD3_CMD__UART2_CTS \
+ IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MXSDL_PAD_SD3_CMD__UART2_RTS \
+ IOMUX_PAD(0x06F8, 0x0310, 1, 0x0900, 3, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_SD3_CMD__CAN1_TXCAN \
+ IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 \
+ IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 \
+ IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_CMD__GPIO_7_2 \
+ IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 \
+ IOMUX_PAD(0x06F8, 0x0310, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 \
+ IOMUX_PAD(0x06F8, 0x0310, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ \
+ IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_SD3_DAT0__USDHC3_DAT0_100MHZ \
+ IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_100MHZ)
+#define MX6DL_PAD_SD3_DAT0__USDHC3_DAT0_200MHZ \
+ IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_200MHZ)
+#define MX6DL_PAD_SD3_DAT0__UART1_CTS \
+ IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_SD3_DAT0__UART1_RTS \
+ IOMUX_PAD(0x06FC, 0x0314, 1, 0x08F8, 2, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_SD3_DAT0__CAN2_TXCAN \
+ IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 \
+ IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 \
+ IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_DAT0__GPIO_7_4 \
+ IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 \
+ IOMUX_PAD(0x06FC, 0x0314, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 \
+ IOMUX_PAD(0x06FC, 0x0314, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ \
+ IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_SD3_DAT1__USDHC3_DAT1_100MHZ \
+ IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_100MHZ)
+#define MX6DL_PAD_SD3_DAT1__USDHC3_DAT1_200MHZ \
+ IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_200MHZ)
+#define MX6DL_PAD_SD3_DAT1__UART1_CTS \
+ IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_SD3_DAT1__UART1_RTS \
+ IOMUX_PAD(0x0700, 0x0318, 1, 0x08F8, 3, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_SD3_DAT1__CAN2_RXCAN \
+ IOMUX_PAD(0x0700, 0x0318, 2, 0x07CC, 1, 0)
+#define MX6DL_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 \
+ IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 \
+ IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_DAT1__GPIO_7_5 \
+ IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 \
+ IOMUX_PAD(0x0700, 0x0318, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 \
+ IOMUX_PAD(0x0700, 0x0318, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ \
+ IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_SD3_DAT2__USDHC3_DAT2_100MHZ \
+ IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_100MHZ)
+#define MX6DL_PAD_SD3_DAT2__USDHC3_DAT2_200MHZ \
+ IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_200MHZ)
+#define MX6DL_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 \
+ IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 \
+ IOMUX_PAD(0x0704, 0x031C, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 \
+ IOMUX_PAD(0x0704, 0x031C, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_DAT2__GPIO_7_6 \
+ IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 \
+ IOMUX_PAD(0x0704, 0x031C, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 \
+ IOMUX_PAD(0x0704, 0x031C, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ \
+ IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_SD3_DAT3__USDHC3_DAT3_100MHZ \
+ IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_100MHZ)
+#define MX6DL_PAD_SD3_DAT3__USDHC3_DAT3_200MHZ \
+ IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_200MHZ)
+#define MX6DL_PAD_SD3_DAT3__UART3_CTS \
+ IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_SD3_DAT3__UART3_RTS \
+ IOMUX_PAD(0x0708, 0x0320, 1, 0x0908, 4, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 \
+ IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 \
+ IOMUX_PAD(0x0708, 0x0320, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 \
+ IOMUX_PAD(0x0708, 0x0320, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_DAT3__GPIO_7_7 \
+ IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 \
+ IOMUX_PAD(0x0708, 0x0320, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 \
+ IOMUX_PAD(0x0708, 0x0320, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_SD3_DAT4__USDHC3_DAT4_50MHZ \
+ IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_SD3_DAT4__USDHC3_DAT4_100MHZ \
+ IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_100MHZ)
+#define MX6DL_PAD_SD3_DAT4__USDHC3_DAT4_200MHZ \
+ IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_200MHZ)
+#define MX6DL_PAD_SD3_DAT4__UART2_TXD \
+ IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_SD3_DAT4__UART2_RXD \
+ IOMUX_PAD(0x070C, 0x0324, 1, 0x0904, 4, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 \
+ IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 \
+ IOMUX_PAD(0x070C, 0x0324, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 \
+ IOMUX_PAD(0x070C, 0x0324, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_DAT4__GPIO_7_1 \
+ IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 \
+ IOMUX_PAD(0x070C, 0x0324, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 \
+ IOMUX_PAD(0x070C, 0x0324, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_SD3_DAT5__USDHC3_DAT5_50MHZ \
+ IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_SD3_DAT5__USDHC3_DAT5_100MHZ \
+ IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_100MHZ)
+#define MX6DL_PAD_SD3_DAT5__USDHC3_DAT5_200MHZ \
+ IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_200MHZ)
+#define MX6DL_PAD_SD3_DAT5__UART2_TXD \
+ IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_SD3_DAT5__UART2_RXD \
+ IOMUX_PAD(0x0710, 0x0328, 1, 0x0904, 5, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 \
+ IOMUX_PAD(0x0710, 0x0328, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 \
+ IOMUX_PAD(0x0710, 0x0328, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 \
+ IOMUX_PAD(0x0710, 0x0328, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_DAT5__GPIO_7_0 \
+ IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 \
+ IOMUX_PAD(0x0710, 0x0328, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 \
+ IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_SD3_DAT6__USDHC3_DAT6_50MHZ \
+ IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_SD3_DAT6__USDHC3_DAT6_100MHZ \
+ IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_100MHZ)
+#define MX6DL_PAD_SD3_DAT6__USDHC3_DAT6_200MHZ \
+ IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_200MHZ)
+#define MX6DL_PAD_SD3_DAT6__UART1_TXD \
+ IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_SD3_DAT6__UART1_RXD \
+ IOMUX_PAD(0x0714, 0x032C, 1, 0x08FC, 2, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 \
+ IOMUX_PAD(0x0714, 0x032C, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 \
+ IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 \
+ IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_DAT6__GPIO_6_18 \
+ IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 \
+ IOMUX_PAD(0x0714, 0x032C, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 \
+ IOMUX_PAD(0x0714, 0x032C, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_SD3_DAT7__USDHC3_DAT7_50MHZ \
+ IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_SD3_DAT7__USDHC3_DAT7_100MHZ \
+ IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_100MHZ)
+#define MX6DL_PAD_SD3_DAT7__USDHC3_DAT7_200MHZ \
+ IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_200MHZ)
+#define MX6DL_PAD_SD3_DAT7__UART1_TXD \
+ IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_SD3_DAT7__UART1_RXD \
+ IOMUX_PAD(0x0718, 0x0330, 1, 0x08FC, 3, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 \
+ IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 \
+ IOMUX_PAD(0x0718, 0x0330, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 \
+ IOMUX_PAD(0x0718, 0x0330, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_DAT7__GPIO_6_17 \
+ IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 \
+ IOMUX_PAD(0x0718, 0x0330, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV \
+ IOMUX_PAD(0x0718, 0x0330, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_SD3_RST__USDHC3_RST \
+ IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_SD3_RST__UART3_CTS \
+ IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_SD3_RST__UART3_RTS \
+ IOMUX_PAD(0x071C, 0x0334, 1, 0x0908, 5, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 \
+ IOMUX_PAD(0x071C, 0x0334, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 \
+ IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 \
+ IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_RST__GPIO_7_8 \
+ IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 \
+ IOMUX_PAD(0x071C, 0x0334, 6, 0x0000, 0, 0)
+#define MX6DL_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 \
+ IOMUX_PAD(0x071C, 0x0334, 7, 0x0000, 0, 0)
+
+#define MX6DL_PAD_SD4_CLK__USDHC4_CLK_50MHZ \
+ IOMUX_PAD(0x0720, 0x0338, 0, 0x0938, 1, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_SD4_CLK__USDHC4_CLK_100MHZ \
+ IOMUX_PAD(0x0720, 0x0338, 0, 0x0938, 1, MX6DL_USDHC_PAD_CTRL_100MHZ)
+#define MX6DL_PAD_SD4_CLK__USDHC4_CLK_200MHZ \
+ IOMUX_PAD(0x0720, 0x0338, 0, 0x0938, 1, MX6DL_USDHC_PAD_CTRL_200MHZ)
+#define MX6DL_PAD_SD4_CLK__RAWNAND_WRN \
+ IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, MX6DL_GPMI_PAD_CTRL2)
+#define MX6DL_PAD_SD4_CLK__UART3_TXD \
+ IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_SD4_CLK__UART3_RXD \
+ IOMUX_PAD(0x0720, 0x0338, 2, 0x090C, 2, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 \
+ IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_SD4_CLK__GPIO_7_10 \
+ IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0)
+
+#define MX6DL_PAD_SD4_CMD__USDHC4_CMD_50MHZ \
+ IOMUX_PAD(0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_SD4_CMD__USDHC4_CMD_100MHZ \
+ IOMUX_PAD(0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_100MHZ)
+#define MX6DL_PAD_SD4_CMD__USDHC4_CMD_200MHZ \
+ IOMUX_PAD(0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_200MHZ)
+#define MX6DL_PAD_SD4_CMD__RAWNAND_RDN \
+ IOMUX_PAD(0x0724, 0x033C, 1, 0x0000, 0, MX6DL_GPMI_PAD_CTRL2)
+#define MX6DL_PAD_SD4_CMD__UART3_TXD \
+ IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_SD4_CMD__UART3_RXD \
+ IOMUX_PAD(0x0724, 0x033C, 2, 0x090C, 3, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 \
+ IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_SD4_CMD__GPIO_7_9 \
+ IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0)
+
+#define MX6DL_PAD_SD4_DAT0__RAWNAND_D8 \
+ IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_SD4_DAT0__USDHC4_DAT0_50MHZ \
+ IOMUX_PAD(0x0728, 0x0340, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_SD4_DAT0__USDHC4_DAT0_100MHZ \
+ IOMUX_PAD(0x0728, 0x0340, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_100MHZ)
+#define MX6DL_PAD_SD4_DAT0__USDHC4_DAT0_200MHZ \
+ IOMUX_PAD(0x0728, 0x0340, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_200MHZ)
+#define MX6DL_PAD_SD4_DAT0__RAWNAND_DQS \
+ IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, MX6DL_GPMI_PAD_CTRL1)
+#define MX6DL_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 \
+ IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 \
+ IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_SD4_DAT0__GPIO_2_8 \
+ IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 \
+ IOMUX_PAD(0x0728, 0x0340, 6, 0x0000, 0, 0)
+
+#define MX6DL_PAD_SD4_DAT1__RAWNAND_D9 \
+ IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_SD4_DAT1__USDHC4_DAT1_50MHZ \
+ IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_SD4_DAT1__USDHC4_DAT1_100MHZ \
+ IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_100MHZ)
+#define MX6DL_PAD_SD4_DAT1__USDHC4_DAT1_200MHZ \
+ IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_200MHZ)
+#define MX6DL_PAD_SD4_DAT1__PWM3_PWMO \
+ IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 \
+ IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 \
+ IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_SD4_DAT1__GPIO_2_9 \
+ IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 \
+ IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0)
+
+#define MX6DL_PAD_SD4_DAT2__RAWNAND_D10 \
+ IOMUX_PAD(0x0730, 0x0348, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_SD4_DAT2__USDHC4_DAT2_50MHZ \
+ IOMUX_PAD(0x0730, 0x0348, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_SD4_DAT2__USDHC4_DAT2_100MHZ \
+ IOMUX_PAD(0x0730, 0x0348, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_100MHZ)
+#define MX6DL_PAD_SD4_DAT2__USDHC4_DAT2_200MHZ \
+ IOMUX_PAD(0x0730, 0x0348, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_200MHZ)
+#define MX6DL_PAD_SD4_DAT2__PWM4_PWMO \
+ IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0)
+#define MX6DL_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 \
+ IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 \
+ IOMUX_PAD(0x0730, 0x0348, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_SD4_DAT2__GPIO_2_10 \
+ IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 \
+ IOMUX_PAD(0x0730, 0x0348, 6, 0x0000, 0, 0)
+
+#define MX6DL_PAD_SD4_DAT3__RAWNAND_D11 \
+ IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_SD4_DAT3__USDHC4_DAT3_50MHZ \
+ IOMUX_PAD(0x0734, 0x034C, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_SD4_DAT3__USDHC4_DAT3_100MHZ \
+ IOMUX_PAD(0x0734, 0x034C, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_100MHZ)
+#define MX6DL_PAD_SD4_DAT3__USDHC4_DAT3_200MHZ \
+ IOMUX_PAD(0x0734, 0x034C, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_200MHZ)
+#define MX6DL_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 \
+ IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 \
+ IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_SD4_DAT3__GPIO_2_11 \
+ IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 \
+ IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0)
+
+#define MX6DL_PAD_SD4_DAT4__RAWNAND_D12 \
+ IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_SD4_DAT4__USDHC4_DAT4_50MHZ \
+ IOMUX_PAD(0x0738, 0x0350, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_SD4_DAT4__USDHC4_DAT4_100MHZ \
+ IOMUX_PAD(0x0738, 0x0350, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_100MHZ)
+#define MX6DL_PAD_SD4_DAT4__USDHC4_DAT4_200MHZ \
+ IOMUX_PAD(0x0738, 0x0350, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_200MHZ)
+#define MX6DL_PAD_SD4_DAT4__UART2_TXD \
+ IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_SD4_DAT4__UART2_RXD \
+ IOMUX_PAD(0x0738, 0x0350, 2, 0x0904, 6, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 \
+ IOMUX_PAD(0x0738, 0x0350, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 \
+ IOMUX_PAD(0x0738, 0x0350, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_SD4_DAT4__GPIO_2_12 \
+ IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 \
+ IOMUX_PAD(0x0738, 0x0350, 6, 0x0000, 0, 0)
+
+#define MX6DL_PAD_SD4_DAT5__RAWNAND_D13 \
+ IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_SD4_DAT5__USDHC4_DAT5_50MHZ \
+ IOMUX_PAD(0x073C, 0x0354, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_SD4_DAT5__USDHC4_DAT5_100MHZ \
+ IOMUX_PAD(0x073C, 0x0354, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_100MHZ)
+#define MX6DL_PAD_SD4_DAT5__USDHC4_DAT5_200MHZ \
+ IOMUX_PAD(0x073C, 0x0354, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_200MHZ)
+#define MX6DL_PAD_SD4_DAT5__UART2_CTS \
+ IOMUX_PAD(0x073C, 0x0354, 2, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_SD4_DAT5__UART2_RTS \
+ IOMUX_PAD(0x073C, 0x0354, 2, 0x0900, 4, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 \
+ IOMUX_PAD(0x073C, 0x0354, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 \
+ IOMUX_PAD(0x073C, 0x0354, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_SD4_DAT5__GPIO_2_13 \
+ IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 \
+ IOMUX_PAD(0x073C, 0x0354, 6, 0x0000, 0, 0)
+
+#define MX6DL_PAD_SD4_DAT6__RAWNAND_D14 \
+ IOMUX_PAD(0x0740, 0x0358, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_SD4_DAT6__USDHC4_DAT6_50MHZ \
+ IOMUX_PAD(0x0740, 0x0358, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_SD4_DAT6__USDHC4_DAT6_100MHZ \
+ IOMUX_PAD(0x0740, 0x0358, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_100MHZ)
+#define MX6DL_PAD_SD4_DAT6__USDHC4_DAT6_200MHZ \
+ IOMUX_PAD(0x0740, 0x0358, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_200MHZ)
+#define MX6DL_PAD_SD4_DAT6__UART2_CTS \
+ IOMUX_PAD(0x0740, 0x0358, 2, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_SD4_DAT6__UART2_RTS \
+ IOMUX_PAD(0x0740, 0x0358, 2, 0x0900, 5, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 \
+ IOMUX_PAD(0x0740, 0x0358, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 \
+ IOMUX_PAD(0x0740, 0x0358, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_SD4_DAT6__GPIO_2_14 \
+ IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 \
+ IOMUX_PAD(0x0740, 0x0358, 6, 0x0000, 0, 0)
+
+#define MX6DL_PAD_SD4_DAT7__RAWNAND_D15 \
+ IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0)
+#define MX6DL_PAD_SD4_DAT7__USDHC4_DAT7_50MHZ \
+ IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_SD4_DAT7__USDHC4_DAT7_100MHZ \
+ IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_100MHZ)
+#define MX6DL_PAD_SD4_DAT7__USDHC4_DAT7_200MHZ \
+ IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_200MHZ)
+#define MX6DL_PAD_SD4_DAT7__UART2_TXD \
+ IOMUX_PAD(0x0744, 0x035C, 2, 0x0000, 0, MX6DL_UART_PAD_CTRL)
+#define MX6DL_PAD_SD4_DAT7__UART2_RXD \
+ IOMUX_PAD(0x0744, 0x035C, 2, 0x0904, 7, 0)
+#define MX6DL_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 \
+ IOMUX_PAD(0x0744, 0x035C, 3, 0x0000, 0, 0)
+#define MX6DL_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 \
+ IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, 0)
+#define MX6DL_PAD_SD4_DAT7__GPIO_2_15 \
+ IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0)
+#define MX6DL_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 \
+ IOMUX_PAD(0x0744, 0x035C, 6, 0x0000, 0, 0)
+
+#endif /*__MACH_IOMUX_MX6DL_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Auto Generate file, please don't edit it
+ *
+ */
+
+#ifndef __MACH_IOMUX_MX6Q_H__
+#define __MACH_IOMUX_MX6Q_H__
+
+#include <mach/iomux-v3.h>
+
+#define MX6Q_CCM_CLK0_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define MX6Q_HIGH_DRV (PAD_CTL_DSE_120ohm)
+
+#define MX6Q_MLB150_PAD_CTRL (PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) \
+
+#define MX6Q_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define MX6Q_USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define MX6Q_USDHC_PAD_CTRL_100MHZ (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define MX6Q_USDHC_PAD_CTRL_200MHZ (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define MX6Q_ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define MX6Q_ENET_REF_CLK_PAD_CTRL (PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define MX6Q_GPIO_16_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define MX6Q_DISP_PAD_CLT MX6Q_HIGH_DRV
+
+#define MX6Q_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_HYS | PAD_CTL_SPEED_MED)
+
+#define MX6Q_ESAI_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+
+#define MX6Q_GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define MX6Q_GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | PAD_CTL_SRE_FAST)
+#define MX6Q_GPMI_PAD_CTRL2 (MX6Q_GPMI_PAD_CTRL0 | MX6Q_GPMI_PAD_CTRL1)
+
+#define MX6Q_SPDIF_OUT_PAD_CTRL (PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
+#define MX6Q_USB_HSIC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_DSE_40ohm)
+
+#define MX6Q_ECSPI_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define MX6Q_HDMICEC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_22K_UP | \
+ PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_ODE | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_SLOW)
+
+#define MX6Q_ADU_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_PUS_100K_DOWN | \
+ PAD_CTL_HYS | PAD_CTL_SPEED_MED)
+
+#define MX6Q_WEIM_NOR_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SPEED_MED | PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP)
+
+#define ENET_IRQ_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SPEED_MED)
+
+#define _MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 \
+ IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 \
+ IOMUX_PAD(0x0360, 0x004C, 1, 0x0834, 0, 0)
+#define _MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 \
+ IOMUX_PAD(0x0360, 0x004C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS \
+ IOMUX_PAD(0x0360, 0x004C, 3, 0x07C8, 0, 0)
+#define _MX6Q_PAD_SD2_DAT1__KPP_COL_7 \
+ IOMUX_PAD(0x0360, 0x004C, 4, 0x08F0, 0, 0)
+#define _MX6Q_PAD_SD2_DAT1__GPIO_1_14 \
+ IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT1__CCM_WAIT \
+ IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 \
+ IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 \
+ IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 \
+ IOMUX_PAD(0x0364, 0x0050, 1, 0x0838, 0, 0)
+#define _MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 \
+ IOMUX_PAD(0x0364, 0x0050, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD \
+ IOMUX_PAD(0x0364, 0x0050, 3, 0x07B8, 0, 0)
+#define _MX6Q_PAD_SD2_DAT2__KPP_ROW_6 \
+ IOMUX_PAD(0x0364, 0x0050, 4, 0x08F8, 0, 0)
+#define _MX6Q_PAD_SD2_DAT2__GPIO_1_13 \
+ IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT2__CCM_STOP \
+ IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 \
+ IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 \
+ IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT0__ECSPI5_MISO \
+ IOMUX_PAD(0x0368, 0x0054, 1, 0x082C, 0, 0)
+#define _MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD \
+ IOMUX_PAD(0x0368, 0x0054, 3, 0x07B4, 0, 0)
+#define _MX6Q_PAD_SD2_DAT0__KPP_ROW_7 \
+ IOMUX_PAD(0x0368, 0x0054, 4, 0x08FC, 0, 0)
+#define _MX6Q_PAD_SD2_DAT0__GPIO_1_15 \
+ IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT \
+ IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 \
+ IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA \
+ IOMUX_PAD(0x036C, 0x0058, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC \
+ IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK \
+ IOMUX_PAD(0x036C, 0x0058, 2, 0x0918, 0, 0)
+#define _MX6Q_PAD_RGMII_TXC__GPIO_6_19 \
+ IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 \
+ IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT \
+ IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY \
+ IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 \
+ IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD0__GPIO_6_20 \
+ IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 \
+ IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG \
+ IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 \
+ IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD1__GPIO_6_21 \
+ IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 \
+ IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP \
+ IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA \
+ IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 \
+ IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD2__GPIO_6_22 \
+ IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 \
+ IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP \
+ IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE \
+ IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 \
+ IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD3__GPIO_6_23 \
+ IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 \
+ IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA \
+ IOMUX_PAD(0x0380, 0x006C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL \
+ IOMUX_PAD(0x0380, 0x006C, 1, 0x0858, 0, 0)
+#define _MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 \
+ IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 \
+ IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY \
+ IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 \
+ IOMUX_PAD(0x0384, 0x0070, 1, 0x0848, 0, 0)
+#define _MX6Q_PAD_RGMII_RD0__GPIO_6_25 \
+ IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 \
+ IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE \
+ IOMUX_PAD(0x0388, 0x0074, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL \
+ IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 \
+ IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 \
+ IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT \
+ IOMUX_PAD(0x0388, 0x0074, 7, 0x083C, 0, 0)
+
+#define _MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG \
+ IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 \
+ IOMUX_PAD(0x038C, 0x0078, 1, 0x084C, 0, 0)
+#define _MX6Q_PAD_RGMII_RD1__GPIO_6_27 \
+ IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 \
+ IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RD1__SJC_FAIL \
+ IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA \
+ IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 \
+ IOMUX_PAD(0x0390, 0x007C, 1, 0x0850, 0, 0)
+#define _MX6Q_PAD_RGMII_RD2__GPIO_6_28 \
+ IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 \
+ IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE \
+ IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 \
+ IOMUX_PAD(0x0394, 0x0080, 1, 0x0854, 0, 0)
+#define _MX6Q_PAD_RGMII_RD3__GPIO_6_29 \
+ IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 \
+ IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE \
+ IOMUX_PAD(0x0398, 0x0084, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC \
+ IOMUX_PAD(0x0398, 0x0084, 1, 0x0844, 0, 0)
+#define _MX6Q_PAD_RGMII_RXC__GPIO_6_30 \
+ IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 \
+ IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 \
+ IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A25__ECSPI4_SS1 \
+ IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A25__ECSPI2_RDY \
+ IOMUX_PAD(0x039C, 0x0088, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 \
+ IOMUX_PAD(0x039C, 0x0088, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS \
+ IOMUX_PAD(0x039C, 0x0088, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A25__GPIO_5_2 \
+ IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE \
+ IOMUX_PAD(0x039C, 0x0088, 6, 0x088C, 0, 0)
+#define _MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0 \
+ IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 \
+ IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB2__ECSPI1_SS0 \
+ IOMUX_PAD(0x03A0, 0x008C, 1, 0x0800, 0, 0)
+#define _MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK \
+ IOMUX_PAD(0x03A0, 0x008C, 2, 0x07EC, 0, 0)
+#define _MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 \
+ IOMUX_PAD(0x03A0, 0x008C, 3, 0x08D4, 0, 0)
+#define _MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL \
+ IOMUX_PAD(0x03A0, 0x008C, 4, 0x0890, 0, 0)
+#define _MX6Q_PAD_EIM_EB2__GPIO_2_30 \
+ IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB2__I2C2_SCL \
+ IOMUX_PAD(0x03A0, 0x008C, 6 | IOMUX_CONFIG_SION, 0x08A0, 0, 0)
+#define _MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 \
+ IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 \
+ IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D16__ECSPI1_SCLK \
+ IOMUX_PAD(0x03A4, 0x0090, 1, 0x07F4, 0, 0)
+#define _MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 \
+ IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 \
+ IOMUX_PAD(0x03A4, 0x0090, 3, 0x08D0, 0, 0)
+#define _MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA \
+ IOMUX_PAD(0x03A4, 0x0090, 4, 0x0894, 0, 0)
+#define _MX6Q_PAD_EIM_D16__GPIO_3_16 \
+ IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D16__I2C2_SDA \
+ IOMUX_PAD(0x03A4, 0x0090, 6 | IOMUX_CONFIG_SION, 0x08A4, 0, 0)
+
+#define _MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 \
+ IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D17__ECSPI1_MISO \
+ IOMUX_PAD(0x03A8, 0x0094, 1, 0x07F8, 0, 0)
+#define _MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 \
+ IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK \
+ IOMUX_PAD(0x03A8, 0x0094, 3, 0x08E0, 0, 0)
+#define _MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT \
+ IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D17__GPIO_3_17 \
+ IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D17__I2C3_SCL \
+ IOMUX_PAD(0x03A8, 0x0094, 6 | IOMUX_CONFIG_SION, 0x08A8, 0, 0)
+#define _MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 \
+ IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 \
+ IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D18__ECSPI1_MOSI \
+ IOMUX_PAD(0x03AC, 0x0098, 1, 0x07FC, 0, 0)
+#define _MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 \
+ IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 \
+ IOMUX_PAD(0x03AC, 0x0098, 3, 0x08CC, 0, 0)
+#define _MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS \
+ IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D18__GPIO_3_18 \
+ IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D18__I2C3_SDA \
+ IOMUX_PAD(0x03AC, 0x0098, 6 | IOMUX_CONFIG_SION, 0x08AC, 0, 0)
+#define _MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 \
+ IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 \
+ IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D19__ECSPI1_SS1 \
+ IOMUX_PAD(0x03B0, 0x009C, 1, 0x0804, 0, 0)
+#define _MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 \
+ IOMUX_PAD(0x03B0, 0x009C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 \
+ IOMUX_PAD(0x03B0, 0x009C, 3, 0x08C8, 0, 0)
+#define _MX6Q_PAD_EIM_D19__UART1_CTS \
+ IOMUX_PAD(0x03B0, 0x009C, 4, 0x091C, 0, 0)
+#define _MX6Q_PAD_EIM_D19__GPIO_3_19 \
+ IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D19__EPIT1_EPITO \
+ IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP \
+ IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 \
+ IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D20__ECSPI4_SS0 \
+ IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0824, 0, 0)
+#define _MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 \
+ IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 \
+ IOMUX_PAD(0x03B4, 0x00A0, 3, 0x08C4, 0, 0)
+#define _MX6Q_PAD_EIM_D20__UART1_CTS \
+ IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D20__UART1_RTS \
+ IOMUX_PAD(0x03B4, 0x00A0, 4, 0x091C, 1, 0)
+#define _MX6Q_PAD_EIM_D20__GPIO_3_20 \
+ IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D20__EPIT2_EPITO \
+ IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 \
+ IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D21__ECSPI4_SCLK \
+ IOMUX_PAD(0x03B8, 0x00A4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 \
+ IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 \
+ IOMUX_PAD(0x03B8, 0x00A4, 3, 0x08B4, 0, 0)
+#define _MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC \
+ IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0944, 0, 0)
+#define _MX6Q_PAD_EIM_D21__GPIO_3_21 \
+ IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D21__I2C1_SCL \
+ IOMUX_PAD(0x03B8, 0x00A4, 6 | IOMUX_CONFIG_SION, 0x0898, 0, 0)
+#define _MX6Q_PAD_EIM_D21__SPDIF_IN1 \
+ IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0914, 0, 0)
+
+#define _MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 \
+ IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D22__ECSPI4_MISO \
+ IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 \
+ IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 \
+ IOMUX_PAD(0x03BC, 0x00A8, 3, 0x08B0, 0, 0)
+#define _MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR \
+ IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D22__GPIO_3_22 \
+ IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D22__SPDIF_OUT1 \
+ IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE \
+ IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 \
+ IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS \
+ IOMUX_PAD(0x03C0, 0x00AC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D23__UART3_CTS \
+ IOMUX_PAD(0x03C0, 0x00AC, 2, 0x092C, 0, 0)
+#define _MX6Q_PAD_EIM_D23__UART1_DCD \
+ IOMUX_PAD(0x03C0, 0x00AC, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN \
+ IOMUX_PAD(0x03C0, 0x00AC, 4, 0x08D8, 0, 0)
+#define _MX6Q_PAD_EIM_D23__GPIO_3_23 \
+ IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 \
+ IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 \
+ IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 \
+ IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB3__ECSPI4_RDY \
+ IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB3__UART3_CTS \
+ IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB3__UART3_RTS \
+ IOMUX_PAD(0x03C4, 0x00B0, 2, 0x092C, 1, 0)
+#define _MX6Q_PAD_EIM_EB3__UART1_RI \
+ IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC \
+ IOMUX_PAD(0x03C4, 0x00B0, 4, 0x08DC, 0, 0)
+#define _MX6Q_PAD_EIM_EB3__GPIO_2_31 \
+ IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 \
+ IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 \
+ IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 \
+ IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D24__ECSPI4_SS2 \
+ IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D24__UART3_TXD \
+ IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D24__UART3_RXD \
+ IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0930, 0, 0)
+#define _MX6Q_PAD_EIM_D24__ECSPI1_SS2 \
+ IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0808, 0, 0)
+#define _MX6Q_PAD_EIM_D24__ECSPI2_SS2 \
+ IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D24__GPIO_3_24 \
+ IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS \
+ IOMUX_PAD(0x03C8, 0x00B4, 6, 0x07D8, 0, 0)
+#define _MX6Q_PAD_EIM_D24__UART1_DTR \
+ IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 \
+ IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D25__ECSPI4_SS3 \
+ IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D25__UART3_TXD \
+ IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D25__UART3_RXD \
+ IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0930, 1, 0)
+#define _MX6Q_PAD_EIM_D25__ECSPI1_SS3 \
+ IOMUX_PAD(0x03CC, 0x00B8, 3, 0x080C, 0, 0)
+#define _MX6Q_PAD_EIM_D25__ECSPI2_SS3 \
+ IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D25__GPIO_3_25 \
+ IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC \
+ IOMUX_PAD(0x03CC, 0x00B8, 6, 0x07D4, 0, 0)
+#define _MX6Q_PAD_EIM_D25__UART1_DSR \
+ IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 \
+ IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 \
+ IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 \
+ IOMUX_PAD(0x03D0, 0x00BC, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 \
+ IOMUX_PAD(0x03D0, 0x00BC, 3, 0x08C0, 0, 0)
+#define _MX6Q_PAD_EIM_D26__UART2_TXD \
+ IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D26__UART2_RXD \
+ IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0928, 0, 0)
+#define _MX6Q_PAD_EIM_D26__GPIO_3_26 \
+ IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D26__IPU1_SISG_2 \
+ IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 \
+ IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 \
+ IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 \
+ IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 \
+ IOMUX_PAD(0x03D4, 0x00C0, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 \
+ IOMUX_PAD(0x03D4, 0x00C0, 3, 0x08BC, 0, 0)
+#define _MX6Q_PAD_EIM_D27__UART2_TXD \
+ IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D27__UART2_RXD \
+ IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0928, 1, 0)
+#define _MX6Q_PAD_EIM_D27__GPIO_3_27 \
+ IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D27__IPU1_SISG_3 \
+ IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 \
+ IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 \
+ IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D28__I2C1_SDA \
+ IOMUX_PAD(0x03D8, 0x00C4, 1 | IOMUX_CONFIG_SION, 0x089C, 0, 0)
+#define _MX6Q_PAD_EIM_D28__ECSPI4_MOSI \
+ IOMUX_PAD(0x03D8, 0x00C4, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 \
+ IOMUX_PAD(0x03D8, 0x00C4, 3, 0x08B8, 0, 0)
+#define _MX6Q_PAD_EIM_D28__UART2_CTS \
+ IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D28__UART2_RTS \
+ IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0924, 0, 0)
+#define _MX6Q_PAD_EIM_D28__GPIO_3_28 \
+ IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG \
+ IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 \
+ IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 \
+ IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 \
+ IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D29__ECSPI4_SS0 \
+ IOMUX_PAD(0x03DC, 0x00C8, 2, 0x0824, 1, 0)
+#define _MX6Q_PAD_EIM_D29__UART2_CTS \
+ IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D29__UART2_RTS \
+ IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0924, 1, 0)
+#define _MX6Q_PAD_EIM_D29__GPIO_3_29 \
+ IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC \
+ IOMUX_PAD(0x03DC, 0x00C8, 6, 0x08E4, 0, 0)
+#define _MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 \
+ IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 \
+ IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 \
+ IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 \
+ IOMUX_PAD(0x03E0, 0x00CC, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 \
+ IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D30__UART3_CTS \
+ IOMUX_PAD(0x03E0, 0x00CC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D30__GPIO_3_30 \
+ IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC \
+ IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0948, 0, 0)
+#define _MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0 \
+ IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 \
+ IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 \
+ IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 \
+ IOMUX_PAD(0x03E4, 0x00D0, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 \
+ IOMUX_PAD(0x03E4, 0x00D0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D31__UART3_CTS \
+ IOMUX_PAD(0x03E4, 0x00D0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D31__UART3_RTS \
+ IOMUX_PAD(0x03E4, 0x00D0, 4, 0x092C, 3, 0)
+#define _MX6Q_PAD_EIM_D31__GPIO_3_31 \
+ IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR \
+ IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1 \
+ IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 \
+ IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 \
+ IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 \
+ IOMUX_PAD(0x03E8, 0x00D4, 2, 0x08D4, 1, 0)
+#define _MX6Q_PAD_EIM_A24__IPU2_SISG_2 \
+ IOMUX_PAD(0x03E8, 0x00D4, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A24__IPU1_SISG_2 \
+ IOMUX_PAD(0x03E8, 0x00D4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A24__GPIO_5_4 \
+ IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2 \
+ IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 \
+ IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 \
+ IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 \
+ IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 \
+ IOMUX_PAD(0x03EC, 0x00D8, 2, 0x08D0, 1, 0)
+#define _MX6Q_PAD_EIM_A23__IPU2_SISG_3 \
+ IOMUX_PAD(0x03EC, 0x00D8, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A23__IPU1_SISG_3 \
+ IOMUX_PAD(0x03EC, 0x00D8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A23__GPIO_6_6 \
+ IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3 \
+ IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 \
+ IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 \
+ IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 \
+ IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 \
+ IOMUX_PAD(0x03F0, 0x00DC, 2, 0x08CC, 1, 0)
+#define _MX6Q_PAD_EIM_A22__GPIO_2_16 \
+ IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 \
+ IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 \
+ IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 \
+ IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 \
+ IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 \
+ IOMUX_PAD(0x03F4, 0x00E0, 2, 0x08C8, 1, 0)
+#define _MX6Q_PAD_EIM_A21__RESERVED_RESERVED \
+ IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 \
+ IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A21__GPIO_2_17 \
+ IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 \
+ IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 \
+ IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 \
+ IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 \
+ IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 \
+ IOMUX_PAD(0x03F8, 0x00E4, 2, 0x08C4, 1, 0)
+#define _MX6Q_PAD_EIM_A20__RESERVED_RESERVED \
+ IOMUX_PAD(0x03F8, 0x00E4, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 \
+ IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A20__GPIO_2_18 \
+ IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 \
+ IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 \
+ IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 \
+ IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 \
+ IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 \
+ IOMUX_PAD(0x03FC, 0x00E8, 2, 0x08C0, 1, 0)
+#define _MX6Q_PAD_EIM_A19__RESERVED_RESERVED \
+ IOMUX_PAD(0x03FC, 0x00E8, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 \
+ IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A19__GPIO_2_19 \
+ IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 \
+ IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 \
+ IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 \
+ IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 \
+ IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 \
+ IOMUX_PAD(0x0400, 0x00EC, 2, 0x08BC, 1, 0)
+#define _MX6Q_PAD_EIM_A18__RESERVED_RESERVED \
+ IOMUX_PAD(0x0400, 0x00EC, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 \
+ IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A18__GPIO_2_20 \
+ IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 \
+ IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 \
+ IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 \
+ IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 \
+ IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 \
+ IOMUX_PAD(0x0404, 0x00F0, 2, 0x08B8, 1, 0)
+#define _MX6Q_PAD_EIM_A17__RESERVED_RESERVED \
+ IOMUX_PAD(0x0404, 0x00F0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 \
+ IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A17__GPIO_2_21 \
+ IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 \
+ IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 \
+ IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 \
+ IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK \
+ IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK \
+ IOMUX_PAD(0x0408, 0x00F4, 2, 0x08E0, 1, 0)
+#define _MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 \
+ IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A16__GPIO_2_22 \
+ IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 \
+ IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 \
+ IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 \
+ IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 \
+ IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_CS0__ECSPI2_SCLK \
+ IOMUX_PAD(0x040C, 0x00F8, 2, 0x0810, 0, 0)
+#define _MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 \
+ IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_CS0__GPIO_2_23 \
+ IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 \
+ IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 \
+ IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 \
+ IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_CS1__ECSPI2_MOSI \
+ IOMUX_PAD(0x0410, 0x00FC, 2, 0x0818, 0, 0)
+#define _MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 \
+ IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_CS1__GPIO_2_24 \
+ IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 \
+ IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_OE__WEIM_WEIM_OE \
+ IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 \
+ IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_OE__ECSPI2_MISO \
+ IOMUX_PAD(0x0414, 0x0100, 2, 0x0814, 0, 0)
+#define _MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 \
+ IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_OE__GPIO_2_25 \
+ IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 \
+ IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_RW__WEIM_WEIM_RW \
+ IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 \
+ IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_RW__ECSPI2_SS0 \
+ IOMUX_PAD(0x0418, 0x0104, 2, 0x081C, 0, 0)
+#define _MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 \
+ IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_RW__GPIO_2_26 \
+ IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 \
+ IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 \
+ IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA \
+ IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 \
+ IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_LBA__ECSPI2_SS1 \
+ IOMUX_PAD(0x041C, 0x0108, 2, 0x0820, 0, 0)
+#define _MX6Q_PAD_EIM_LBA__GPIO_2_27 \
+ IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 \
+ IOMUX_PAD(0x041C, 0x0108, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 \
+ IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 \
+ IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 \
+ IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 \
+ IOMUX_PAD(0x0420, 0x010C, 2, 0x08B4, 1, 0)
+#define _MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 \
+ IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY \
+ IOMUX_PAD(0x0420, 0x010C, 4, 0x07F0, 0, 0)
+#define _MX6Q_PAD_EIM_EB0__GPIO_2_28 \
+ IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 \
+ IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 \
+ IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 \
+ IOMUX_PAD(0x0424, 0x0110, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 \
+ IOMUX_PAD(0x0424, 0x0110, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 \
+ IOMUX_PAD(0x0424, 0x0110, 2, 0x08B0, 1, 0)
+#define _MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 \
+ IOMUX_PAD(0x0424, 0x0110, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB1__GPIO_2_29 \
+ IOMUX_PAD(0x0424, 0x0110, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 \
+ IOMUX_PAD(0x0424, 0x0110, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 \
+ IOMUX_PAD(0x0424, 0x0110, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 \
+ IOMUX_PAD(0x0428, 0x0114, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 \
+ IOMUX_PAD(0x0428, 0x0114, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 \
+ IOMUX_PAD(0x0428, 0x0114, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 \
+ IOMUX_PAD(0x0428, 0x0114, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA0__GPIO_3_0 \
+ IOMUX_PAD(0x0428, 0x0114, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 \
+ IOMUX_PAD(0x0428, 0x0114, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 \
+ IOMUX_PAD(0x0428, 0x0114, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 \
+ IOMUX_PAD(0x042C, 0x0118, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 \
+ IOMUX_PAD(0x042C, 0x0118, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 \
+ IOMUX_PAD(0x042C, 0x0118, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 \
+ IOMUX_PAD(0x042C, 0x0118, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE \
+ IOMUX_PAD(0x042C, 0x0118, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA1__GPIO_3_1 \
+ IOMUX_PAD(0x042C, 0x0118, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 \
+ IOMUX_PAD(0x042C, 0x0118, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 \
+ IOMUX_PAD(0x042C, 0x0118, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 \
+ IOMUX_PAD(0x0430, 0x011C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 \
+ IOMUX_PAD(0x0430, 0x011C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 \
+ IOMUX_PAD(0x0430, 0x011C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 \
+ IOMUX_PAD(0x0430, 0x011C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE \
+ IOMUX_PAD(0x0430, 0x011C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA2__GPIO_3_2 \
+ IOMUX_PAD(0x0430, 0x011C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 \
+ IOMUX_PAD(0x0430, 0x011C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 \
+ IOMUX_PAD(0x0430, 0x011C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 \
+ IOMUX_PAD(0x0434, 0x0120, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 \
+ IOMUX_PAD(0x0434, 0x0120, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 \
+ IOMUX_PAD(0x0434, 0x0120, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 \
+ IOMUX_PAD(0x0434, 0x0120, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ \
+ IOMUX_PAD(0x0434, 0x0120, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA3__GPIO_3_3 \
+ IOMUX_PAD(0x0434, 0x0120, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 \
+ IOMUX_PAD(0x0434, 0x0120, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 \
+ IOMUX_PAD(0x0434, 0x0120, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 \
+ IOMUX_PAD(0x0438, 0x0124, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 \
+ IOMUX_PAD(0x0438, 0x0124, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 \
+ IOMUX_PAD(0x0438, 0x0124, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 \
+ IOMUX_PAD(0x0438, 0x0124, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN \
+ IOMUX_PAD(0x0438, 0x0124, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA4__GPIO_3_4 \
+ IOMUX_PAD(0x0438, 0x0124, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 \
+ IOMUX_PAD(0x0438, 0x0124, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 \
+ IOMUX_PAD(0x0438, 0x0124, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 \
+ IOMUX_PAD(0x043C, 0x0128, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 \
+ IOMUX_PAD(0x043C, 0x0128, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 \
+ IOMUX_PAD(0x043C, 0x0128, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 \
+ IOMUX_PAD(0x043C, 0x0128, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP \
+ IOMUX_PAD(0x043C, 0x0128, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA5__GPIO_3_5 \
+ IOMUX_PAD(0x043C, 0x0128, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 \
+ IOMUX_PAD(0x043C, 0x0128, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 \
+ IOMUX_PAD(0x043C, 0x0128, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 \
+ IOMUX_PAD(0x0440, 0x012C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 \
+ IOMUX_PAD(0x0440, 0x012C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 \
+ IOMUX_PAD(0x0440, 0x012C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 \
+ IOMUX_PAD(0x0440, 0x012C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN \
+ IOMUX_PAD(0x0440, 0x012C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA6__GPIO_3_6 \
+ IOMUX_PAD(0x0440, 0x012C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 \
+ IOMUX_PAD(0x0440, 0x012C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 \
+ IOMUX_PAD(0x0440, 0x012C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 \
+ IOMUX_PAD(0x0444, 0x0130, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 \
+ IOMUX_PAD(0x0444, 0x0130, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 \
+ IOMUX_PAD(0x0444, 0x0130, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 \
+ IOMUX_PAD(0x0444, 0x0130, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA7__GPIO_3_7 \
+ IOMUX_PAD(0x0444, 0x0130, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 \
+ IOMUX_PAD(0x0444, 0x0130, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 \
+ IOMUX_PAD(0x0444, 0x0130, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 \
+ IOMUX_PAD(0x0448, 0x0134, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 \
+ IOMUX_PAD(0x0448, 0x0134, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 \
+ IOMUX_PAD(0x0448, 0x0134, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 \
+ IOMUX_PAD(0x0448, 0x0134, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA8__GPIO_3_8 \
+ IOMUX_PAD(0x0448, 0x0134, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 \
+ IOMUX_PAD(0x0448, 0x0134, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 \
+ IOMUX_PAD(0x0448, 0x0134, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 \
+ IOMUX_PAD(0x044C, 0x0138, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 \
+ IOMUX_PAD(0x044C, 0x0138, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 \
+ IOMUX_PAD(0x044C, 0x0138, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 \
+ IOMUX_PAD(0x044C, 0x0138, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA9__GPIO_3_9 \
+ IOMUX_PAD(0x044C, 0x0138, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 \
+ IOMUX_PAD(0x044C, 0x0138, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 \
+ IOMUX_PAD(0x044C, 0x0138, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 \
+ IOMUX_PAD(0x0450, 0x013C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 \
+ IOMUX_PAD(0x0450, 0x013C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN \
+ IOMUX_PAD(0x0450, 0x013C, 2, 0x08D8, 1, 0)
+#define _MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 \
+ IOMUX_PAD(0x0450, 0x013C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA10__GPIO_3_10 \
+ IOMUX_PAD(0x0450, 0x013C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 \
+ IOMUX_PAD(0x0450, 0x013C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 \
+ IOMUX_PAD(0x0450, 0x013C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 \
+ IOMUX_PAD(0x0454, 0x0140, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 \
+ IOMUX_PAD(0x0454, 0x0140, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC \
+ IOMUX_PAD(0x0454, 0x0140, 2, 0x08DC, 1, 0)
+#define _MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 \
+ IOMUX_PAD(0x0454, 0x0140, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 \
+ IOMUX_PAD(0x0454, 0x0140, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA11__GPIO_3_11 \
+ IOMUX_PAD(0x0454, 0x0140, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 \
+ IOMUX_PAD(0x0454, 0x0140, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 \
+ IOMUX_PAD(0x0454, 0x0140, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 \
+ IOMUX_PAD(0x0458, 0x0144, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 \
+ IOMUX_PAD(0x0458, 0x0144, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC \
+ IOMUX_PAD(0x0458, 0x0144, 2, 0x08E4, 1, 0)
+#define _MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 \
+ IOMUX_PAD(0x0458, 0x0144, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 \
+ IOMUX_PAD(0x0458, 0x0144, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA12__GPIO_3_12 \
+ IOMUX_PAD(0x0458, 0x0144, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 \
+ IOMUX_PAD(0x0458, 0x0144, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 \
+ IOMUX_PAD(0x0458, 0x0144, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 \
+ IOMUX_PAD(0x045C, 0x0148, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS \
+ IOMUX_PAD(0x045C, 0x0148, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK \
+ IOMUX_PAD(0x045C, 0x0148, 2, 0x07EC, 1, 0)
+#define _MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 \
+ IOMUX_PAD(0x045C, 0x0148, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 \
+ IOMUX_PAD(0x045C, 0x0148, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA13__GPIO_3_13 \
+ IOMUX_PAD(0x045C, 0x0148, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 \
+ IOMUX_PAD(0x045C, 0x0148, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 \
+ IOMUX_PAD(0x045C, 0x0148, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 \
+ IOMUX_PAD(0x0460, 0x014C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS \
+ IOMUX_PAD(0x0460, 0x014C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK \
+ IOMUX_PAD(0x0460, 0x014C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 \
+ IOMUX_PAD(0x0460, 0x014C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 \
+ IOMUX_PAD(0x0460, 0x014C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA14__GPIO_3_14 \
+ IOMUX_PAD(0x0460, 0x014C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 \
+ IOMUX_PAD(0x0460, 0x014C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 \
+ IOMUX_PAD(0x0460, 0x014C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 \
+ IOMUX_PAD(0x0464, 0x0150, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 \
+ IOMUX_PAD(0x0464, 0x0150, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 \
+ IOMUX_PAD(0x0464, 0x0150, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 \
+ IOMUX_PAD(0x0464, 0x0150, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA15__GPIO_3_15 \
+ IOMUX_PAD(0x0464, 0x0150, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 \
+ IOMUX_PAD(0x0464, 0x0150, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 \
+ IOMUX_PAD(0x0464, 0x0150, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT \
+ IOMUX_PAD(0x0468, 0x0154, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B \
+ IOMUX_PAD(0x0468, 0x0154, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_WAIT__GPIO_5_0 \
+ IOMUX_PAD(0x0468, 0x0154, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 \
+ IOMUX_PAD(0x0468, 0x0154, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 \
+ IOMUX_PAD(0x0468, 0x0154, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK \
+ IOMUX_PAD(0x046C, 0x0158, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 \
+ IOMUX_PAD(0x046C, 0x0158, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_BCLK__GPIO_6_31 \
+ IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 \
+ IOMUX_PAD(0x046C, 0x0158, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK \
+ IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK \
+ IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 \
+ IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 \
+ IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 \
+ IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 \
+ IOMUX_PAD(0x0470, 0x015C, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 \
+ IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 \
+ IOMUX_PAD(0x0474, 0x0160, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC \
+ IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 \
+ IOMUX_PAD(0x0474, 0x0160, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 \
+ IOMUX_PAD(0x0474, 0x0160, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN15__GPIO_4_17 \
+ IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 \
+ IOMUX_PAD(0x0474, 0x0160, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 \
+ IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 \
+ IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD \
+ IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 \
+ IOMUX_PAD(0x0478, 0x0164, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 \
+ IOMUX_PAD(0x0478, 0x0164, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN2__GPIO_4_18 \
+ IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 \
+ IOMUX_PAD(0x0478, 0x0164, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9 \
+ IOMUX_PAD(0x0478, 0x0164, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 \
+ IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 \
+ IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS \
+ IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 \
+ IOMUX_PAD(0x047C, 0x0168, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 \
+ IOMUX_PAD(0x047C, 0x0168, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN3__GPIO_4_19 \
+ IOMUX_PAD(0x047C, 0x0168, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 \
+ IOMUX_PAD(0x047C, 0x0168, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10 \
+ IOMUX_PAD(0x047C, 0x0168, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 \
+ IOMUX_PAD(0x0480, 0x016C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 \
+ IOMUX_PAD(0x0480, 0x016C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD \
+ IOMUX_PAD(0x0480, 0x016C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN4__USDHC1_WP \
+ IOMUX_PAD(0x0480, 0x016C, 3, 0x094C, 0, 0)
+#define _MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD \
+ IOMUX_PAD(0x0480, 0x016C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN4__GPIO_4_20 \
+ IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 \
+ IOMUX_PAD(0x0480, 0x016C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11 \
+ IOMUX_PAD(0x0480, 0x016C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 \
+ IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 \
+ IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK \
+ IOMUX_PAD(0x0484, 0x0170, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 \
+ IOMUX_PAD(0x0484, 0x0170, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN \
+ IOMUX_PAD(0x0484, 0x0170, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT0__GPIO_4_21 \
+ IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 \
+ IOMUX_PAD(0x0484, 0x0170, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 \
+ IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 \
+ IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI \
+ IOMUX_PAD(0x0488, 0x0174, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 \
+ IOMUX_PAD(0x0488, 0x0174, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL \
+ IOMUX_PAD(0x0488, 0x0174, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT1__GPIO_4_22 \
+ IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 \
+ IOMUX_PAD(0x0488, 0x0174, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12 \
+ IOMUX_PAD(0x0488, 0x0174, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 \
+ IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 \
+ IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO \
+ IOMUX_PAD(0x048C, 0x0178, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 \
+ IOMUX_PAD(0x048C, 0x0178, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE \
+ IOMUX_PAD(0x048C, 0x0178, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT2__GPIO_4_23 \
+ IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 \
+ IOMUX_PAD(0x048C, 0x0178, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13 \
+ IOMUX_PAD(0x048C, 0x0178, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 \
+ IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 \
+ IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 \
+ IOMUX_PAD(0x0490, 0x017C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 \
+ IOMUX_PAD(0x0490, 0x017C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR \
+ IOMUX_PAD(0x0490, 0x017C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT3__GPIO_4_24 \
+ IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 \
+ IOMUX_PAD(0x0490, 0x017C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14 \
+ IOMUX_PAD(0x0490, 0x017C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 \
+ IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 \
+ IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 \
+ IOMUX_PAD(0x0494, 0x0180, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 \
+ IOMUX_PAD(0x0494, 0x0180, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB \
+ IOMUX_PAD(0x0494, 0x0180, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT4__GPIO_4_25 \
+ IOMUX_PAD(0x0494, 0x0180, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 \
+ IOMUX_PAD(0x0494, 0x0180, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15 \
+ IOMUX_PAD(0x0494, 0x0180, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 \
+ IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 \
+ IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 \
+ IOMUX_PAD(0x0498, 0x0184, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS \
+ IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS \
+ IOMUX_PAD(0x0498, 0x0184, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT5__GPIO_4_26 \
+ IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 \
+ IOMUX_PAD(0x0498, 0x0184, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16 \
+ IOMUX_PAD(0x0498, 0x0184, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 \
+ IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 \
+ IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 \
+ IOMUX_PAD(0x049C, 0x0188, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC \
+ IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE \
+ IOMUX_PAD(0x049C, 0x0188, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT6__GPIO_4_27 \
+ IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 \
+ IOMUX_PAD(0x049C, 0x0188, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17 \
+ IOMUX_PAD(0x049C, 0x0188, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 \
+ IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 \
+ IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY \
+ IOMUX_PAD(0x04A0, 0x018C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 \
+ IOMUX_PAD(0x04A0, 0x018C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 \
+ IOMUX_PAD(0x04A0, 0x018C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT7__GPIO_4_28 \
+ IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 \
+ IOMUX_PAD(0x04A0, 0x018C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18 \
+ IOMUX_PAD(0x04A0, 0x018C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 \
+ IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 \
+ IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT8__PWM1_PWMO \
+ IOMUX_PAD(0x04A4, 0x0190, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B \
+ IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 \
+ IOMUX_PAD(0x04A4, 0x0190, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT8__GPIO_4_29 \
+ IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 \
+ IOMUX_PAD(0x04A4, 0x0190, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19 \
+ IOMUX_PAD(0x04A4, 0x0190, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 \
+ IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 \
+ IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT9__PWM2_PWMO \
+ IOMUX_PAD(0x04A8, 0x0194, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B \
+ IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 \
+ IOMUX_PAD(0x04A8, 0x0194, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT9__GPIO_4_30 \
+ IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 \
+ IOMUX_PAD(0x04A8, 0x0194, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20 \
+ IOMUX_PAD(0x04A8, 0x0194, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 \
+ IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 \
+ IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 \
+ IOMUX_PAD(0x04AC, 0x0198, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 \
+ IOMUX_PAD(0x04AC, 0x0198, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT10__GPIO_4_31 \
+ IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 \
+ IOMUX_PAD(0x04AC, 0x0198, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21 \
+ IOMUX_PAD(0x04AC, 0x0198, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 \
+ IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 \
+ IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 \
+ IOMUX_PAD(0x04B0, 0x019C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 \
+ IOMUX_PAD(0x04B0, 0x019C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT11__GPIO_5_5 \
+ IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 \
+ IOMUX_PAD(0x04B0, 0x019C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22 \
+ IOMUX_PAD(0x04B0, 0x019C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 \
+ IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 \
+ IOMUX_PAD(0x04B4, 0x01A0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED \
+ IOMUX_PAD(0x04B4, 0x01A0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 \
+ IOMUX_PAD(0x04B4, 0x01A0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT12__GPIO_5_6 \
+ IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 \
+ IOMUX_PAD(0x04B4, 0x01A0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23 \
+ IOMUX_PAD(0x04B4, 0x01A0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 \
+ IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 \
+ IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS \
+ IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 \
+ IOMUX_PAD(0x04B8, 0x01A4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT13__GPIO_5_7 \
+ IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 \
+ IOMUX_PAD(0x04B8, 0x01A4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24 \
+ IOMUX_PAD(0x04B8, 0x01A4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 \
+ IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 \
+ IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC \
+ IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 \
+ IOMUX_PAD(0x04BC, 0x01A8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT14__GPIO_5_8 \
+ IOMUX_PAD(0x04BC, 0x01A8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 \
+ IOMUX_PAD(0x04BC, 0x01A8, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 \
+ IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 \
+ IOMUX_PAD(0x04C0, 0x01AC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 \
+ IOMUX_PAD(0x04C0, 0x01AC, 2, 0x0804, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 \
+ IOMUX_PAD(0x04C0, 0x01AC, 3, 0x0820, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 \
+ IOMUX_PAD(0x04C0, 0x01AC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT15__GPIO_5_9 \
+ IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 \
+ IOMUX_PAD(0x04C0, 0x01AC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25 \
+ IOMUX_PAD(0x04C0, 0x01AC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 \
+ IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 \
+ IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI \
+ IOMUX_PAD(0x04C4, 0x01B0, 2, 0x0818, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC \
+ IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 \
+ IOMUX_PAD(0x04C4, 0x01B0, 4, 0x090C, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT16__GPIO_5_10 \
+ IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 \
+ IOMUX_PAD(0x04C4, 0x01B0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26 \
+ IOMUX_PAD(0x04C4, 0x01B0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 \
+ IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 \
+ IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO \
+ IOMUX_PAD(0x04C8, 0x01B4, 2, 0x0814, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD \
+ IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 \
+ IOMUX_PAD(0x04C8, 0x01B4, 4, 0x0910, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT17__GPIO_5_11 \
+ IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 \
+ IOMUX_PAD(0x04C8, 0x01B4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27 \
+ IOMUX_PAD(0x04C8, 0x01B4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 \
+ IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 \
+ IOMUX_PAD(0x04CC, 0x01B8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 \
+ IOMUX_PAD(0x04CC, 0x01B8, 2, 0x081C, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS \
+ IOMUX_PAD(0x04CC, 0x01B8, 3, 0x07E0, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS \
+ IOMUX_PAD(0x04CC, 0x01B8, 4, 0x07C0, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT18__GPIO_5_12 \
+ IOMUX_PAD(0x04CC, 0x01B8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 \
+ IOMUX_PAD(0x04CC, 0x01B8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 \
+ IOMUX_PAD(0x04CC, 0x01B8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 \
+ IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 \
+ IOMUX_PAD(0x04D0, 0x01BC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK \
+ IOMUX_PAD(0x04D0, 0x01BC, 2, 0x0810, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD \
+ IOMUX_PAD(0x04D0, 0x01BC, 3, 0x07CC, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC \
+ IOMUX_PAD(0x04D0, 0x01BC, 4, 0x07BC, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT19__GPIO_5_13 \
+ IOMUX_PAD(0x04D0, 0x01BC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 \
+ IOMUX_PAD(0x04D0, 0x01BC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 \
+ IOMUX_PAD(0x04D0, 0x01BC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 \
+ IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 \
+ IOMUX_PAD(0x04D4, 0x01C0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK \
+ IOMUX_PAD(0x04D4, 0x01C0, 2, 0x07F4, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC \
+ IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 \
+ IOMUX_PAD(0x04D4, 0x01C0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT20__GPIO_5_14 \
+ IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 \
+ IOMUX_PAD(0x04D4, 0x01C0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28 \
+ IOMUX_PAD(0x04D4, 0x01C0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 \
+ IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 \
+ IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI \
+ IOMUX_PAD(0x04D8, 0x01C4, 2, 0x07FC, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD \
+ IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 \
+ IOMUX_PAD(0x04D8, 0x01C4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT21__GPIO_5_15 \
+ IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 \
+ IOMUX_PAD(0x04D8, 0x01C4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29 \
+ IOMUX_PAD(0x04D8, 0x01C4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 \
+ IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 \
+ IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO \
+ IOMUX_PAD(0x04DC, 0x01C8, 2, 0x07F8, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS \
+ IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 \
+ IOMUX_PAD(0x04DC, 0x01C8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT22__GPIO_5_16 \
+ IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 \
+ IOMUX_PAD(0x04DC, 0x01C8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30 \
+ IOMUX_PAD(0x04DC, 0x01C8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 \
+ IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 \
+ IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 \
+ IOMUX_PAD(0x04E0, 0x01CC, 2, 0x0800, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD \
+ IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 \
+ IOMUX_PAD(0x04E0, 0x01CC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT23__GPIO_5_17 \
+ IOMUX_PAD(0x04E0, 0x01CC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 \
+ IOMUX_PAD(0x04E0, 0x01CC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31 \
+ IOMUX_PAD(0x04E0, 0x01CC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED \
+ IOMUX_PAD(0x04E4, 0x01D0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_MDIO__ENET_MDIO \
+ IOMUX_PAD(0x04E4, 0x01D0, 1, 0x0840, 0, 0)
+#define _MX6Q_PAD_ENET_MDIO__ESAI1_SCKR \
+ IOMUX_PAD(0x04E4, 0x01D0, 2, 0x086C, 0, 0)
+#define _MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 \
+ IOMUX_PAD(0x04E4, 0x01D0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT \
+ IOMUX_PAD(0x04E4, 0x01D0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_MDIO__GPIO_1_22 \
+ IOMUX_PAD(0x04E4, 0x01D0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK \
+ IOMUX_PAD(0x04E4, 0x01D0, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_REF_CLK__RESERVED_RESERVED \
+ IOMUX_PAD(0x04E8, 0x01D4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK \
+ IOMUX_PAD(0x04E8, 0x01D4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR \
+ IOMUX_PAD(0x04E8, 0x01D4, 2, 0x085C, 0, 0)
+#define _MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 \
+ IOMUX_PAD(0x04E8, 0x01D4, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 \
+ IOMUX_PAD(0x04E8, 0x01D4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK \
+ IOMUX_PAD(0x04E8, 0x01D4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH \
+ IOMUX_PAD(0x04E8, 0x01D4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_RX_ER__ANATOP_USBOTG_ID \
+ IOMUX_PAD(0x04EC, 0x01D8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RX_ER__ENET_RX_ER \
+ IOMUX_PAD(0x04EC, 0x01D8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR \
+ IOMUX_PAD(0x04EC, 0x01D8, 2, 0x0864, 0, 0)
+#define _MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 \
+ IOMUX_PAD(0x04EC, 0x01D8, 3, 0x0914, 1, 0)
+#define _MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT \
+ IOMUX_PAD(0x04EC, 0x01D8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RX_ER__GPIO_1_24 \
+ IOMUX_PAD(0x04EC, 0x01D8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RX_ER__PHY_TDI \
+ IOMUX_PAD(0x04EC, 0x01D8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD \
+ IOMUX_PAD(0x04EC, 0x01D8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_CRS_DV__RESERVED_RESERVED \
+ IOMUX_PAD(0x04F0, 0x01DC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN \
+ IOMUX_PAD(0x04F0, 0x01DC, 1, 0x0858, 1, 0)
+#define _MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT \
+ IOMUX_PAD(0x04F0, 0x01DC, 2, 0x0870, 0, 0)
+#define _MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK \
+ IOMUX_PAD(0x04F0, 0x01DC, 3, 0x0918, 1, 0)
+#define _MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 \
+ IOMUX_PAD(0x04F0, 0x01DC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_CRS_DV__PHY_TDO \
+ IOMUX_PAD(0x04F0, 0x01DC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD \
+ IOMUX_PAD(0x04F0, 0x01DC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_RXD1__MLB_MLBSIG \
+ IOMUX_PAD(0x04F4, 0x01E0, 0, 0x0908, 0, 0)
+#define _MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 \
+ IOMUX_PAD(0x04F4, 0x01E0, 1, 0x084C, 1, 0)
+#define _MX6Q_PAD_ENET_RXD1__ESAI1_FST \
+ IOMUX_PAD(0x04F4, 0x01E0, 2, 0x0860, 0, 0)
+#define _MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT \
+ IOMUX_PAD(0x04F4, 0x01E0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RXD1__GPIO_1_26 \
+ IOMUX_PAD(0x04F4, 0x01E0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RXD1__PHY_TCK \
+ IOMUX_PAD(0x04F4, 0x01E0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET \
+ IOMUX_PAD(0x04F4, 0x01E0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT \
+ IOMUX_PAD(0x04F8, 0x01E4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 \
+ IOMUX_PAD(0x04F8, 0x01E4, 1, 0x0848, 1, 0)
+#define _MX6Q_PAD_ENET_RXD0__ESAI1_HCKT \
+ IOMUX_PAD(0x04F8, 0x01E4, 2, 0x0868, 0, 0)
+#define _MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 \
+ IOMUX_PAD(0x04F8, 0x01E4, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RXD0__GPIO_1_27 \
+ IOMUX_PAD(0x04F8, 0x01E4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RXD0__PHY_TMS \
+ IOMUX_PAD(0x04F8, 0x01E4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV \
+ IOMUX_PAD(0x04F8, 0x01E4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_TX_EN__RESERVED_RESERVED \
+ IOMUX_PAD(0x04FC, 0x01E8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TX_EN__ENET_TX_EN \
+ IOMUX_PAD(0x04FC, 0x01E8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 \
+ IOMUX_PAD(0x04FC, 0x01E8, 2, 0x0880, 0, 0)
+#define _MX6Q_PAD_ENET_TX_EN__GPIO_1_28 \
+ IOMUX_PAD(0x04FC, 0x01E8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI \
+ IOMUX_PAD(0x04FC, 0x01E8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH \
+ IOMUX_PAD(0x04FC, 0x01E8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_TXD1__MLB_MLBCLK \
+ IOMUX_PAD(0x0500, 0x01EC, 0, 0x0900, 0, 0)
+#define _MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 \
+ IOMUX_PAD(0x0500, 0x01EC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 \
+ IOMUX_PAD(0x0500, 0x01EC, 2, 0x087C, 0, 0)
+#define _MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN \
+ IOMUX_PAD(0x0500, 0x01EC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TXD1__GPIO_1_29 \
+ IOMUX_PAD(0x0500, 0x01EC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO \
+ IOMUX_PAD(0x0500, 0x01EC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD \
+ IOMUX_PAD(0x0500, 0x01EC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_TXD0__RESERVED_RESERVED \
+ IOMUX_PAD(0x0504, 0x01F0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 \
+ IOMUX_PAD(0x0504, 0x01F0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 \
+ IOMUX_PAD(0x0504, 0x01F0, 2, 0x0884, 0, 0)
+#define _MX6Q_PAD_ENET_TXD0__GPIO_1_30 \
+ IOMUX_PAD(0x0504, 0x01F0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK \
+ IOMUX_PAD(0x0504, 0x01F0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD \
+ IOMUX_PAD(0x0504, 0x01F0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_MDC__MLB_MLBDAT \
+ IOMUX_PAD(0x0508, 0x01F4, 0, 0x0904, 0, 0)
+#define _MX6Q_PAD_ENET_MDC__ENET_MDC \
+ IOMUX_PAD(0x0508, 0x01F4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 \
+ IOMUX_PAD(0x0508, 0x01F4, 2, 0x0888, 0, 0)
+#define _MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN \
+ IOMUX_PAD(0x0508, 0x01F4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_MDC__GPIO_1_31 \
+ IOMUX_PAD(0x0508, 0x01F4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_MDC__SATA_PHY_TMS \
+ IOMUX_PAD(0x0508, 0x01F4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET \
+ IOMUX_PAD(0x0508, 0x01F4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 \
+ IOMUX_PAD(0x050C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 \
+ IOMUX_PAD(0x0510, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 \
+ IOMUX_PAD(0x0514, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 \
+ IOMUX_PAD(0x0518, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 \
+ IOMUX_PAD(0x051C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 \
+ IOMUX_PAD(0x0520, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 \
+ IOMUX_PAD(0x0524, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 \
+ IOMUX_PAD(0x0528, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 \
+ IOMUX_PAD(0x052C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 \
+ IOMUX_PAD(0x0530, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 \
+ IOMUX_PAD(0x0534, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 \
+ IOMUX_PAD(0x0538, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 \
+ IOMUX_PAD(0x053C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 \
+ IOMUX_PAD(0x0540, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 \
+ IOMUX_PAD(0x0544, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 \
+ IOMUX_PAD(0x0548, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 \
+ IOMUX_PAD(0x054C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 \
+ IOMUX_PAD(0x0550, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 \
+ IOMUX_PAD(0x0554, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 \
+ IOMUX_PAD(0x0558, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 \
+ IOMUX_PAD(0x055C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 \
+ IOMUX_PAD(0x0560, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 \
+ IOMUX_PAD(0x0564, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 \
+ IOMUX_PAD(0x0568, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS \
+ IOMUX_PAD(0x056C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 \
+ IOMUX_PAD(0x0570, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 \
+ IOMUX_PAD(0x0574, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS \
+ IOMUX_PAD(0x0578, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET \
+ IOMUX_PAD(0x057C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 \
+ IOMUX_PAD(0x0580, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 \
+ IOMUX_PAD(0x0584, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 \
+ IOMUX_PAD(0x0588, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 \
+ IOMUX_PAD(0x058C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 \
+ IOMUX_PAD(0x0590, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 \
+ IOMUX_PAD(0x0594, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 \
+ IOMUX_PAD(0x0598, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 \
+ IOMUX_PAD(0x059C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 \
+ IOMUX_PAD(0x05A0, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE \
+ IOMUX_PAD(0x05A4, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 \
+ IOMUX_PAD(0x05A8, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 \
+ IOMUX_PAD(0x05AC, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 \
+ IOMUX_PAD(0x05B0, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 \
+ IOMUX_PAD(0x05B4, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 \
+ IOMUX_PAD(0x05B8, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 \
+ IOMUX_PAD(0x05BC, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 \
+ IOMUX_PAD(0x05C0, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 \
+ IOMUX_PAD(0x05C4, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_COL0__ECSPI1_SCLK \
+ IOMUX_PAD(0x05C8, 0x01F8, 0, 0x07F4, 2, 0)
+#define _MX6Q_PAD_KEY_COL0__ENET_RDATA_3 \
+ IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0854, 1, 0)
+#define _MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC \
+ IOMUX_PAD(0x05C8, 0x01F8, 2, 0x07DC, 1, 0)
+#define _MX6Q_PAD_KEY_COL0__KPP_COL_0 \
+ IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL0__UART4_TXD \
+ IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL0__UART4_RXD \
+ IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0938, 0, 0)
+#define _MX6Q_PAD_KEY_COL0__GPIO_4_6 \
+ IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT \
+ IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST \
+ IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI \
+ IOMUX_PAD(0x05CC, 0x01FC, 0, 0x07FC, 2, 0)
+#define _MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 \
+ IOMUX_PAD(0x05CC, 0x01FC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD \
+ IOMUX_PAD(0x05CC, 0x01FC, 2, 0x07D0, 1, 0)
+#define _MX6Q_PAD_KEY_ROW0__KPP_ROW_0 \
+ IOMUX_PAD(0x05CC, 0x01FC, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW0__UART4_TXD \
+ IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW0__UART4_RXD \
+ IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0938, 1, 0)
+#define _MX6Q_PAD_KEY_ROW0__GPIO_4_7 \
+ IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT \
+ IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0 \
+ IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_COL1__ECSPI1_MISO \
+ IOMUX_PAD(0x05D0, 0x0200, 0, 0x07F8, 2, 0)
+#define _MX6Q_PAD_KEY_COL1__ENET_MDIO \
+ IOMUX_PAD(0x05D0, 0x0200, 1, 0x0840, 1, 0)
+#define _MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS \
+ IOMUX_PAD(0x05D0, 0x0200, 2, 0x07E0, 1, 0)
+#define _MX6Q_PAD_KEY_COL1__KPP_COL_1 \
+ IOMUX_PAD(0x05D0, 0x0200, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL1__UART5_TXD \
+ IOMUX_PAD(0x05D0, 0x0200, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL1__UART5_RXD \
+ IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940, 0, 0)
+#define _MX6Q_PAD_KEY_COL1__GPIO_4_8 \
+ IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL1__USDHC1_VSELECT \
+ IOMUX_PAD(0x05D0, 0x0200, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1 \
+ IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 \
+ IOMUX_PAD(0x05D4, 0x0204, 0, 0x0800, 2, 0)
+#define _MX6Q_PAD_KEY_ROW1__ENET_COL \
+ IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD \
+ IOMUX_PAD(0x05D4, 0x0204, 2, 0x07CC, 1, 0)
+#define _MX6Q_PAD_KEY_ROW1__KPP_ROW_1 \
+ IOMUX_PAD(0x05D4, 0x0204, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW1__UART5_TXD \
+ IOMUX_PAD(0x05D4, 0x0204, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW1__UART5_RXD \
+ IOMUX_PAD(0x05D4, 0x0204, 4, 0x0940, 1, 0)
+#define _MX6Q_PAD_KEY_ROW1__GPIO_4_9 \
+ IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT \
+ IOMUX_PAD(0x05D4, 0x0204, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2 \
+ IOMUX_PAD(0x05D4, 0x0204, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_COL2__ECSPI1_SS1 \
+ IOMUX_PAD(0x05D8, 0x0208, 0, 0x0804, 2, 0)
+#define _MX6Q_PAD_KEY_COL2__ENET_RDATA_2 \
+ IOMUX_PAD(0x05D8, 0x0208, 1, 0x0850, 1, 0)
+#define _MX6Q_PAD_KEY_COL2__CAN1_TXCAN \
+ IOMUX_PAD(0x05D8, 0x0208, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL2__KPP_COL_2 \
+ IOMUX_PAD(0x05D8, 0x0208, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL2__ENET_MDC \
+ IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL2__GPIO_4_10 \
+ IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP \
+ IOMUX_PAD(0x05D8, 0x0208, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3 \
+ IOMUX_PAD(0x05D8, 0x0208, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 \
+ IOMUX_PAD(0x05DC, 0x020C, 0, 0x0808, 1, 0)
+#define _MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 \
+ IOMUX_PAD(0x05DC, 0x020C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW2__CAN1_RXCAN \
+ IOMUX_PAD(0x05DC, 0x020C, 2, 0x07E4, 0, 0)
+#define _MX6Q_PAD_KEY_ROW2__KPP_ROW_2 \
+ IOMUX_PAD(0x05DC, 0x020C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT \
+ IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW2__GPIO_4_11 \
+ IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE \
+ IOMUX_PAD(0x05DC, 0x020C, 6, 0x088C, 1, 0)
+#define _MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4 \
+ IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_COL3__ECSPI1_SS3 \
+ IOMUX_PAD(0x05E0, 0x0210, 0, 0x080C, 1, 0)
+#define _MX6Q_PAD_KEY_COL3__ENET_CRS \
+ IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL \
+ IOMUX_PAD(0x05E0, 0x0210, 2 | IOMUX_CONFIG_SION, 0x0890, 1, 0)
+#define _MX6Q_PAD_KEY_COL3__KPP_COL_3 \
+ IOMUX_PAD(0x05E0, 0x0210, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL3__I2C2_SCL \
+ IOMUX_PAD(0x05E0, 0x0210, 4 | IOMUX_CONFIG_SION, 0x08A0, 1, 0)
+#define _MX6Q_PAD_KEY_COL3__GPIO_4_12 \
+ IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL3__SPDIF_IN1 \
+ IOMUX_PAD(0x05E0, 0x0210, 6, 0x0914, 2, 0)
+#define _MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5 \
+ IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT \
+ IOMUX_PAD(0x05E4, 0x0214, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK \
+ IOMUX_PAD(0x05E4, 0x0214, 1, 0x07B0, 0, 0)
+#define _MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA \
+ IOMUX_PAD(0x05E4, 0x0214, 2 | IOMUX_CONFIG_SION, 0x0894, 1, 0)
+#define _MX6Q_PAD_KEY_ROW3__KPP_ROW_3 \
+ IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW3__I2C2_SDA \
+ IOMUX_PAD(0x05E4, 0x0214, 4 | IOMUX_CONFIG_SION, 0x08A4, 1, 0)
+#define _MX6Q_PAD_KEY_ROW3__GPIO_4_13 \
+ IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT \
+ IOMUX_PAD(0x05E4, 0x0214, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6 \
+ IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_COL4__CAN2_TXCAN \
+ IOMUX_PAD(0x05E8, 0x0218, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL4__IPU1_SISG_4 \
+ IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC \
+ IOMUX_PAD(0x05E8, 0x0218, 2, 0x0944, 1, 0)
+#define _MX6Q_PAD_KEY_COL4__KPP_COL_4 \
+ IOMUX_PAD(0x05E8, 0x0218, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL4__UART5_CTS \
+ IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL4__UART5_RTS \
+ IOMUX_PAD(0x05E8, 0x0218, 4, 0x093C, 0, 0)
+#define _MX6Q_PAD_KEY_COL4__GPIO_4_14 \
+ IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 \
+ IOMUX_PAD(0x05E8, 0x0218, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7 \
+ IOMUX_PAD(0x05E8, 0x0218, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_ROW4__CAN2_RXCAN \
+ IOMUX_PAD(0x05EC, 0x021C, 0, 0x07E8, 0, 0)
+#define _MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 \
+ IOMUX_PAD(0x05EC, 0x021C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR \
+ IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW4__KPP_ROW_4 \
+ IOMUX_PAD(0x05EC, 0x021C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW4__UART5_CTS \
+ IOMUX_PAD(0x05EC, 0x021C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW4__GPIO_4_15 \
+ IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 \
+ IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8 \
+ IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_0__CCM_CLKO \
+ IOMUX_PAD(0x05F0, 0x0220, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_0__KPP_COL_5 \
+ IOMUX_PAD(0x05F0, 0x0220, 2, 0x08E8, 0, 0)
+#define _MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK \
+ IOMUX_PAD(0x05F0, 0x0220, 3, 0x07B0, 1, 0)
+#define _MX6Q_PAD_GPIO_0__EPIT1_EPITO \
+ IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_0__GPIO_1_0 \
+ IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR \
+ IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 \
+ IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_1__ESAI1_SCKR \
+ IOMUX_PAD(0x05F4, 0x0224, 0, 0x086C, 1, 0)
+#define _MX6Q_PAD_GPIO_1__WDOG2_WDOG_B \
+ IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_1__KPP_ROW_5 \
+ IOMUX_PAD(0x05F4, 0x0224, 2, 0x08F4, 0, 0)
+#define MX6Q_PAD_GPIO_1__USBOTG_ID \
+ IOMUX_PAD(0x05F4, 0x0224, 3, 0x0000, 0, MX6Q_USDHC_PAD_CTRL)
+#define _MX6Q_PAD_GPIO_1__PWM2_PWMO \
+ IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_1__GPIO_1_1 \
+ IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_1__USDHC1_CD \
+ IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_1__SRC_TESTER_ACK \
+ IOMUX_PAD(0x05F4, 0x0224, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_9__ESAI1_FSR \
+ IOMUX_PAD(0x05F8, 0x0228, 0, 0x085C, 1, 0)
+#define _MX6Q_PAD_GPIO_9__WDOG1_WDOG_B \
+ IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_9__KPP_COL_6 \
+ IOMUX_PAD(0x05F8, 0x0228, 2, 0x08EC, 0, 0)
+#define _MX6Q_PAD_GPIO_9__CCM_REF_EN_B \
+ IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_9__PWM1_PWMO \
+ IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_9__GPIO_1_9 \
+ IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_9__USDHC1_WP \
+ IOMUX_PAD(0x05F8, 0x0228, 6, 0x094C, 1, 0)
+#define _MX6Q_PAD_GPIO_9__SRC_EARLY_RST \
+ IOMUX_PAD(0x05F8, 0x0228, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_3__ESAI1_HCKR \
+ IOMUX_PAD(0x05FC, 0x022C, 0, 0x0864, 1, 0)
+#define _MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 \
+ IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_3__I2C3_SCL \
+ IOMUX_PAD(0x05FC, 0x022C, 2 | IOMUX_CONFIG_SION, 0x08A8, 1, 0)
+#define _MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT \
+ IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_3__CCM_CLKO2 \
+ IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_3__GPIO_1_3 \
+ IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC \
+ IOMUX_PAD(0x05FC, 0x022C, 6, 0x0948, 1, 0)
+#define _MX6Q_PAD_GPIO_3__MLB_MLBCLK \
+ IOMUX_PAD(0x05FC, 0x022C, 7, 0x0900, 1, 0)
+
+#define _MX6Q_PAD_GPIO_6__ESAI1_SCKT \
+ IOMUX_PAD(0x0600, 0x0230, 0, 0x0870, 1, 0)
+#ifdef CONFIG_MX6_ENET_IRQ_TO_GPIO
+#define _MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 \
+ IOMUX_PAD(0x0600, 0x0230, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+#else
+#define _MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 \
+ IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0)
+#endif
+#define _MX6Q_PAD_GPIO_6__I2C3_SDA \
+ IOMUX_PAD(0x0600, 0x0230, 2 | IOMUX_CONFIG_SION, 0x08AC, 1, 0)
+#define _MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 \
+ IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB \
+ IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_6__GPIO_1_6 \
+ IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_6__USDHC2_LCTL \
+ IOMUX_PAD(0x0600, 0x0230, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_6__MLB_MLBSIG \
+ IOMUX_PAD(0x0600, 0x0230, 7, 0x0908, 1, 0)
+
+#define _MX6Q_PAD_GPIO_2__ESAI1_FST \
+ IOMUX_PAD(0x0604, 0x0234, 0, 0x0860, 1, 0)
+#define _MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 \
+ IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_2__KPP_ROW_6 \
+ IOMUX_PAD(0x0604, 0x0234, 2, 0x08F8, 1, 0)
+#define _MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 \
+ IOMUX_PAD(0x0604, 0x0234, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 \
+ IOMUX_PAD(0x0604, 0x0234, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_2__GPIO_1_2 \
+ IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_2__USDHC2_WP \
+ IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_2__MLB_MLBDAT \
+ IOMUX_PAD(0x0604, 0x0234, 7, 0x0904, 1, 0)
+
+#define _MX6Q_PAD_GPIO_4__ESAI1_HCKT \
+ IOMUX_PAD(0x0608, 0x0238, 0, 0x0868, 1, 0)
+#define _MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 \
+ IOMUX_PAD(0x0608, 0x0238, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_4__KPP_COL_7 \
+ IOMUX_PAD(0x0608, 0x0238, 2, 0x08F0, 1, 0)
+#define _MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 \
+ IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 \
+ IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_4__GPIO_1_4 \
+ IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_4__USDHC2_CD \
+ IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED \
+ IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 \
+ IOMUX_PAD(0x060C, 0x023C, 0, 0x087C, 1, 0)
+#define _MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 \
+ IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_5__KPP_ROW_7 \
+ IOMUX_PAD(0x060C, 0x023C, 2, 0x08FC, 1, 0)
+#define _MX6Q_PAD_GPIO_5__CCM_CLKO \
+ IOMUX_PAD(0x060C, 0x023C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 \
+ IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_5__GPIO_1_5 \
+ IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_5__I2C3_SCL \
+ IOMUX_PAD(0x060C, 0x023C, 6 | IOMUX_CONFIG_SION, 0x08A8, 2, 0)
+#define _MX6Q_PAD_GPIO_5__CHEETAH_EVENTI \
+ IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 \
+ IOMUX_PAD(0x0610, 0x0240, 0, 0x0884, 1, 0)
+#define _MX6Q_PAD_GPIO_7__ECSPI5_RDY \
+ IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_7__EPIT1_EPITO \
+ IOMUX_PAD(0x0610, 0x0240, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_7__CAN1_TXCAN \
+ IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_7__UART2_TXD \
+ IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_7__UART2_RXD \
+ IOMUX_PAD(0x0610, 0x0240, 4, 0x0928, 2, 0)
+#define _MX6Q_PAD_GPIO_7__GPIO_1_7 \
+ IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_7__SPDIF_PLOCK \
+ IOMUX_PAD(0x0610, 0x0240, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE \
+ IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 \
+ IOMUX_PAD(0x0614, 0x0244, 0, 0x0888, 1, 0)
+#define _MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT \
+ IOMUX_PAD(0x0614, 0x0244, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_8__EPIT2_EPITO \
+ IOMUX_PAD(0x0614, 0x0244, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_8__CAN1_RXCAN \
+ IOMUX_PAD(0x0614, 0x0244, 3, 0x07E4, 1, 0)
+#define _MX6Q_PAD_GPIO_8__UART2_TXD \
+ IOMUX_PAD(0x0614, 0x0244, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_8__UART2_RXD \
+ IOMUX_PAD(0x0614, 0x0244, 4, 0x0928, 3, 0)
+#define _MX6Q_PAD_GPIO_8__GPIO_1_8 \
+ IOMUX_PAD(0x0614, 0x0244, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_8__SPDIF_SRCLK \
+ IOMUX_PAD(0x0614, 0x0244, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP \
+ IOMUX_PAD(0x0614, 0x0244, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 \
+ IOMUX_PAD(0x0618, 0x0248, 0, 0x0880, 1, 0)
+#define _MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN \
+ IOMUX_PAD(0x0618, 0x0248, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT \
+ IOMUX_PAD(0x0618, 0x0248, 0x12, 0x083C, 1, 0)
+#define _MX6Q_PAD_GPIO_16__USDHC1_LCTL \
+ IOMUX_PAD(0x0618, 0x0248, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_16__SPDIF_IN1 \
+ IOMUX_PAD(0x0618, 0x0248, 4, 0x0914, 3, 0)
+#define _MX6Q_PAD_GPIO_16__GPIO_7_11 \
+ IOMUX_PAD(0x0618, 0x0248, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_16__I2C3_SDA \
+ IOMUX_PAD(0x0618, 0x0248, 6 | IOMUX_CONFIG_SION, 0x08AC, 2, 0)
+#define _MX6Q_PAD_GPIO_16__SJC_DE_B \
+ IOMUX_PAD(0x0618, 0x0248, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_17__ESAI1_TX0 \
+ IOMUX_PAD(0x061C, 0x024C, 0, 0x0874, 0, 0)
+#define _MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN \
+ IOMUX_PAD(0x061C, 0x024C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_17__CCM_PMIC_RDY \
+ IOMUX_PAD(0x061C, 0x024C, 2, 0x07F0, 1, 0)
+#define _MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 \
+ IOMUX_PAD(0x061C, 0x024C, 3, 0x090C, 1, 0)
+#define _MX6Q_PAD_GPIO_17__SPDIF_OUT1 \
+ IOMUX_PAD(0x061C, 0x024C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_17__GPIO_7_12 \
+ IOMUX_PAD(0x061C, 0x024C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_17__SJC_JTAG_ACT \
+ IOMUX_PAD(0x061C, 0x024C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_18__ESAI1_TX1 \
+ IOMUX_PAD(0x0620, 0x0250, 0, 0x0878, 0, 0)
+#define _MX6Q_PAD_GPIO_18__ENET_RX_CLK \
+ IOMUX_PAD(0x0620, 0x0250, 1, 0x0844, 1, 0)
+#define _MX6Q_PAD_GPIO_18__USDHC3_VSELECT \
+ IOMUX_PAD(0x0620, 0x0250, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 \
+ IOMUX_PAD(0x0620, 0x0250, 3, 0x0910, 1, 0)
+#define _MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK \
+ IOMUX_PAD(0x0620, 0x0250, 4, 0x07B0, 2, 0)
+#define _MX6Q_PAD_GPIO_18__GPIO_7_13 \
+ IOMUX_PAD(0x0620, 0x0250, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL \
+ IOMUX_PAD(0x0620, 0x0250, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST \
+ IOMUX_PAD(0x0620, 0x0250, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_19__KPP_COL_5 \
+ IOMUX_PAD(0x0624, 0x0254, 0, 0x08E8, 1, 0)
+#define _MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT \
+ IOMUX_PAD(0x0624, 0x0254, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_19__SPDIF_OUT1 \
+ IOMUX_PAD(0x0624, 0x0254, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_19__CCM_CLKO \
+ IOMUX_PAD(0x0624, 0x0254, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_19__ECSPI1_RDY \
+ IOMUX_PAD(0x0624, 0x0254, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_19__GPIO_4_5 \
+ IOMUX_PAD(0x0624, 0x0254, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_19__ENET_TX_ER \
+ IOMUX_PAD(0x0624, 0x0254, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_19__SRC_INT_BOOT \
+ IOMUX_PAD(0x0624, 0x0254, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK \
+ IOMUX_PAD(0x0628, 0x0258, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 \
+ IOMUX_PAD(0x0628, 0x0258, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 \
+ IOMUX_PAD(0x0628, 0x0258, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 \
+ IOMUX_PAD(0x0628, 0x0258, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 \
+ IOMUX_PAD(0x0628, 0x0258, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO \
+ IOMUX_PAD(0x0628, 0x0258, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC \
+ IOMUX_PAD(0x062C, 0x025C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 \
+ IOMUX_PAD(0x062C, 0x025C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_MCLK__CCM_CLKO \
+ IOMUX_PAD(0x062C, 0x025C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 \
+ IOMUX_PAD(0x062C, 0x025C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_MCLK__GPIO_5_19 \
+ IOMUX_PAD(0x062C, 0x025C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 \
+ IOMUX_PAD(0x062C, 0x025C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL \
+ IOMUX_PAD(0x062C, 0x025C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN \
+ IOMUX_PAD(0x0630, 0x0260, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 \
+ IOMUX_PAD(0x0630, 0x0260, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 \
+ IOMUX_PAD(0x0630, 0x0260, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 \
+ IOMUX_PAD(0x0630, 0x0260, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 \
+ IOMUX_PAD(0x0630, 0x0260, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 \
+ IOMUX_PAD(0x0630, 0x0260, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK \
+ IOMUX_PAD(0x0630, 0x0260, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC \
+ IOMUX_PAD(0x0634, 0x0264, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 \
+ IOMUX_PAD(0x0634, 0x0264, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 \
+ IOMUX_PAD(0x0634, 0x0264, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 \
+ IOMUX_PAD(0x0634, 0x0264, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 \
+ IOMUX_PAD(0x0634, 0x0264, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 \
+ IOMUX_PAD(0x0634, 0x0264, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 \
+ IOMUX_PAD(0x0634, 0x0264, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 \
+ IOMUX_PAD(0x0638, 0x0268, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 \
+ IOMUX_PAD(0x0638, 0x0268, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK \
+ IOMUX_PAD(0x0638, 0x0268, 2, 0x07F4, 3, 0)
+#define _MX6Q_PAD_CSI0_DAT4__KPP_COL_5 \
+ IOMUX_PAD(0x0638, 0x0268, 3, 0x08E8, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC \
+ IOMUX_PAD(0x0638, 0x0268, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT4__GPIO_5_22 \
+ IOMUX_PAD(0x0638, 0x0268, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 \
+ IOMUX_PAD(0x0638, 0x0268, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 \
+ IOMUX_PAD(0x0638, 0x0268, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 \
+ IOMUX_PAD(0x063C, 0x026C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 \
+ IOMUX_PAD(0x063C, 0x026C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI \
+ IOMUX_PAD(0x063C, 0x026C, 2, 0x07FC, 3, 0)
+#define _MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 \
+ IOMUX_PAD(0x063C, 0x026C, 3, 0x08F4, 1, 0)
+#define _MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD \
+ IOMUX_PAD(0x063C, 0x026C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT5__GPIO_5_23 \
+ IOMUX_PAD(0x063C, 0x026C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 \
+ IOMUX_PAD(0x063C, 0x026C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 \
+ IOMUX_PAD(0x063C, 0x026C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 \
+ IOMUX_PAD(0x0640, 0x0270, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 \
+ IOMUX_PAD(0x0640, 0x0270, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO \
+ IOMUX_PAD(0x0640, 0x0270, 2, 0x07F8, 3, 0)
+#define _MX6Q_PAD_CSI0_DAT6__KPP_COL_6 \
+ IOMUX_PAD(0x0640, 0x0270, 3, 0x08EC, 1, 0)
+#define _MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS \
+ IOMUX_PAD(0x0640, 0x0270, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT6__GPIO_5_24 \
+ IOMUX_PAD(0x0640, 0x0270, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 \
+ IOMUX_PAD(0x0640, 0x0270, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 \
+ IOMUX_PAD(0x0640, 0x0270, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 \
+ IOMUX_PAD(0x0644, 0x0274, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 \
+ IOMUX_PAD(0x0644, 0x0274, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 \
+ IOMUX_PAD(0x0644, 0x0274, 2, 0x0800, 3, 0)
+#define _MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 \
+ IOMUX_PAD(0x0644, 0x0274, 3, 0x08F8, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD \
+ IOMUX_PAD(0x0644, 0x0274, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT7__GPIO_5_25 \
+ IOMUX_PAD(0x0644, 0x0274, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 \
+ IOMUX_PAD(0x0644, 0x0274, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 \
+ IOMUX_PAD(0x0644, 0x0274, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 \
+ IOMUX_PAD(0x0648, 0x0278, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 \
+ IOMUX_PAD(0x0648, 0x0278, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK \
+ IOMUX_PAD(0x0648, 0x0278, 2, 0x0810, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT8__KPP_COL_7 \
+ IOMUX_PAD(0x0648, 0x0278, 3, 0x08F0, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT8__I2C1_SDA \
+ IOMUX_PAD(0x0648, 0x0278, 4 | IOMUX_CONFIG_SION, 0x089C, 1, 0)
+#define _MX6Q_PAD_CSI0_DAT8__GPIO_5_26 \
+ IOMUX_PAD(0x0648, 0x0278, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 \
+ IOMUX_PAD(0x0648, 0x0278, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 \
+ IOMUX_PAD(0x0648, 0x0278, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 \
+ IOMUX_PAD(0x064C, 0x027C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 \
+ IOMUX_PAD(0x064C, 0x027C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI \
+ IOMUX_PAD(0x064C, 0x027C, 2, 0x0818, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 \
+ IOMUX_PAD(0x064C, 0x027C, 3, 0x08FC, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT9__I2C1_SCL \
+ IOMUX_PAD(0x064C, 0x027C, 4 | IOMUX_CONFIG_SION, 0x0898, 1, 0)
+#define _MX6Q_PAD_CSI0_DAT9__GPIO_5_27 \
+ IOMUX_PAD(0x064C, 0x027C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 \
+ IOMUX_PAD(0x064C, 0x027C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 \
+ IOMUX_PAD(0x064C, 0x027C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 \
+ IOMUX_PAD(0x0650, 0x0280, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC \
+ IOMUX_PAD(0x0650, 0x0280, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO \
+ IOMUX_PAD(0x0650, 0x0280, 2, 0x0814, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT10__UART1_TXD \
+ IOMUX_PAD(0x0650, 0x0280, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT10__UART1_RXD \
+ IOMUX_PAD(0x0650, 0x0280, 3, 0x0920, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 \
+ IOMUX_PAD(0x0650, 0x0280, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT10__GPIO_5_28 \
+ IOMUX_PAD(0x0650, 0x0280, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 \
+ IOMUX_PAD(0x0650, 0x0280, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 \
+ IOMUX_PAD(0x0650, 0x0280, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 \
+ IOMUX_PAD(0x0654, 0x0284, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS \
+ IOMUX_PAD(0x0654, 0x0284, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 \
+ IOMUX_PAD(0x0654, 0x0284, 2, 0x081C, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT11__UART1_TXD \
+ IOMUX_PAD(0x0654, 0x0284, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT11__UART1_RXD \
+ IOMUX_PAD(0x0654, 0x0284, 3, 0x0920, 1, 0)
+#define _MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 \
+ IOMUX_PAD(0x0654, 0x0284, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT11__GPIO_5_29 \
+ IOMUX_PAD(0x0654, 0x0284, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 \
+ IOMUX_PAD(0x0654, 0x0284, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 \
+ IOMUX_PAD(0x0654, 0x0284, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 \
+ IOMUX_PAD(0x0658, 0x0288, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 \
+ IOMUX_PAD(0x0658, 0x0288, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 \
+ IOMUX_PAD(0x0658, 0x0288, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT12__UART4_TXD \
+ IOMUX_PAD(0x0658, 0x0288, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT12__UART4_RXD \
+ IOMUX_PAD(0x0658, 0x0288, 3, 0x0938, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 \
+ IOMUX_PAD(0x0658, 0x0288, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT12__GPIO_5_30 \
+ IOMUX_PAD(0x0658, 0x0288, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 \
+ IOMUX_PAD(0x0658, 0x0288, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 \
+ IOMUX_PAD(0x0658, 0x0288, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 \
+ IOMUX_PAD(0x065C, 0x028C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 \
+ IOMUX_PAD(0x065C, 0x028C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 \
+ IOMUX_PAD(0x065C, 0x028C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT13__UART4_TXD \
+ IOMUX_PAD(0x065C, 0x028C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT13__UART4_RXD \
+ IOMUX_PAD(0x065C, 0x028C, 3, 0x0938, 3, 0)
+#define _MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 \
+ IOMUX_PAD(0x065C, 0x028C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT13__GPIO_5_31 \
+ IOMUX_PAD(0x065C, 0x028C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 \
+ IOMUX_PAD(0x065C, 0x028C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 \
+ IOMUX_PAD(0x065C, 0x028C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 \
+ IOMUX_PAD(0x0660, 0x0290, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 \
+ IOMUX_PAD(0x0660, 0x0290, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 \
+ IOMUX_PAD(0x0660, 0x0290, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT14__UART5_TXD \
+ IOMUX_PAD(0x0660, 0x0290, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT14__UART5_RXD \
+ IOMUX_PAD(0x0660, 0x0290, 3, 0x0940, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 \
+ IOMUX_PAD(0x0660, 0x0290, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT14__GPIO_6_0 \
+ IOMUX_PAD(0x0660, 0x0290, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 \
+ IOMUX_PAD(0x0660, 0x0290, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 \
+ IOMUX_PAD(0x0660, 0x0290, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 \
+ IOMUX_PAD(0x0664, 0x0294, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 \
+ IOMUX_PAD(0x0664, 0x0294, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 \
+ IOMUX_PAD(0x0664, 0x0294, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT15__UART5_TXD \
+ IOMUX_PAD(0x0664, 0x0294, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT15__UART5_RXD \
+ IOMUX_PAD(0x0664, 0x0294, 3, 0x0940, 3, 0)
+#define _MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 \
+ IOMUX_PAD(0x0664, 0x0294, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT15__GPIO_6_1 \
+ IOMUX_PAD(0x0664, 0x0294, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 \
+ IOMUX_PAD(0x0664, 0x0294, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 \
+ IOMUX_PAD(0x0664, 0x0294, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 \
+ IOMUX_PAD(0x0668, 0x0298, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 \
+ IOMUX_PAD(0x0668, 0x0298, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 \
+ IOMUX_PAD(0x0668, 0x0298, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT16__UART4_CTS \
+ IOMUX_PAD(0x0668, 0x0298, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT16__UART4_RTS \
+ IOMUX_PAD(0x0668, 0x0298, 3, 0x0934, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 \
+ IOMUX_PAD(0x0668, 0x0298, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT16__GPIO_6_2 \
+ IOMUX_PAD(0x0668, 0x0298, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 \
+ IOMUX_PAD(0x0668, 0x0298, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 \
+ IOMUX_PAD(0x0668, 0x0298, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 \
+ IOMUX_PAD(0x066C, 0x029C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 \
+ IOMUX_PAD(0x066C, 0x029C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 \
+ IOMUX_PAD(0x066C, 0x029C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT17__UART4_CTS \
+ IOMUX_PAD(0x066C, 0x029C, 3, 0x0934, 1, 0)
+#define _MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 \
+ IOMUX_PAD(0x066C, 0x029C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT17__GPIO_6_3 \
+ IOMUX_PAD(0x066C, 0x029C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 \
+ IOMUX_PAD(0x066C, 0x029C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 \
+ IOMUX_PAD(0x066C, 0x029C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 \
+ IOMUX_PAD(0x0670, 0x02A0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 \
+ IOMUX_PAD(0x0670, 0x02A0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 \
+ IOMUX_PAD(0x0670, 0x02A0, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT18__UART5_CTS \
+ IOMUX_PAD(0x0670, 0x02A0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT18__UART5_RTS \
+ IOMUX_PAD(0x0670, 0x02A0, 3, 0x093C, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 \
+ IOMUX_PAD(0x0670, 0x02A0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT18__GPIO_6_4 \
+ IOMUX_PAD(0x0670, 0x02A0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 \
+ IOMUX_PAD(0x0670, 0x02A0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 \
+ IOMUX_PAD(0x0670, 0x02A0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 \
+ IOMUX_PAD(0x0674, 0x02A4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 \
+ IOMUX_PAD(0x0674, 0x02A4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 \
+ IOMUX_PAD(0x0674, 0x02A4, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT19__UART5_CTS \
+ IOMUX_PAD(0x0674, 0x02A4, 3, 0x093C, 3, 0)
+#define _MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 \
+ IOMUX_PAD(0x0674, 0x02A4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT19__GPIO_6_5 \
+ IOMUX_PAD(0x0674, 0x02A4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 \
+ IOMUX_PAD(0x0674, 0x02A4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 \
+ IOMUX_PAD(0x0674, 0x02A4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_JTAG_TMS__SJC_TMS \
+ IOMUX_PAD(0x0678, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_JTAG_MOD__SJC_MOD \
+ IOMUX_PAD(0x067C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB \
+ IOMUX_PAD(0x0680, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_JTAG_TDI__SJC_TDI \
+ IOMUX_PAD(0x0684, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_JTAG_TCK__SJC_TCK \
+ IOMUX_PAD(0x0688, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_JTAG_TDO__SJC_TDO \
+ IOMUX_PAD(0x068C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_POR_B__SRC_POR_B \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RESET_IN_B__SRC_RESET_B \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_TEST_MODE__TCU_TEST_MODE \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 \
+ IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT7__UART1_TXD \
+ IOMUX_PAD(0x0690, 0x02A8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT7__UART1_RXD \
+ IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0)
+#define _MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 \
+ IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 \
+ IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 \
+ IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT7__GPIO_6_17 \
+ IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 \
+ IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV \
+ IOMUX_PAD(0x0690, 0x02A8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 \
+ IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT6__UART1_TXD \
+ IOMUX_PAD(0x0694, 0x02AC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT6__UART1_RXD \
+ IOMUX_PAD(0x0694, 0x02AC, 1, 0x0920, 3, 0)
+#define _MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 \
+ IOMUX_PAD(0x0694, 0x02AC, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 \
+ IOMUX_PAD(0x0694, 0x02AC, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 \
+ IOMUX_PAD(0x0694, 0x02AC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT6__GPIO_6_18 \
+ IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 \
+ IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 \
+ IOMUX_PAD(0x0694, 0x02AC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 \
+ IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT5__UART2_TXD \
+ IOMUX_PAD(0x0698, 0x02B0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT5__UART2_RXD \
+ IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, 0)
+#define _MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 \
+ IOMUX_PAD(0x0698, 0x02B0, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 \
+ IOMUX_PAD(0x0698, 0x02B0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 \
+ IOMUX_PAD(0x0698, 0x02B0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT5__GPIO_7_0 \
+ IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 \
+ IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 \
+ IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 \
+ IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT4__UART2_TXD \
+ IOMUX_PAD(0x069C, 0x02B4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT4__UART2_RXD \
+ IOMUX_PAD(0x069C, 0x02B4, 1, 0x0928, 5, 0)
+#define _MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 \
+ IOMUX_PAD(0x069C, 0x02B4, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 \
+ IOMUX_PAD(0x069C, 0x02B4, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 \
+ IOMUX_PAD(0x069C, 0x02B4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT4__GPIO_7_1 \
+ IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 \
+ IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 \
+ IOMUX_PAD(0x069C, 0x02B4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_CMD__USDHC3_CMD \
+ IOMUX_PAD(0x06A0, 0x02B8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CMD__UART2_CTS \
+ IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0924, 2, 0)
+#define _MX6Q_PAD_SD3_CMD__CAN1_TXCAN \
+ IOMUX_PAD(0x06A0, 0x02B8, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 \
+ IOMUX_PAD(0x06A0, 0x02B8, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 \
+ IOMUX_PAD(0x06A0, 0x02B8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CMD__GPIO_7_2 \
+ IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 \
+ IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 \
+ IOMUX_PAD(0x06A0, 0x02B8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_CLK__USDHC3_CLK \
+ IOMUX_PAD(0x06A4, 0x02BC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CLK__UART2_CTS \
+ IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CLK__UART2_RTS \
+ IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0924, 3, 0)
+#define _MX6Q_PAD_SD3_CLK__CAN1_RXCAN \
+ IOMUX_PAD(0x06A4, 0x02BC, 2, 0x07E4, 2, 0)
+#define _MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 \
+ IOMUX_PAD(0x06A4, 0x02BC, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 \
+ IOMUX_PAD(0x06A4, 0x02BC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CLK__GPIO_7_3 \
+ IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 \
+ IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 \
+ IOMUX_PAD(0x06A4, 0x02BC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 \
+ IOMUX_PAD(0x06A8, 0x02C0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT0__UART1_CTS \
+ IOMUX_PAD(0x06A8, 0x02C0, 1, 0x091C, 2, 0)
+#define _MX6Q_PAD_SD3_DAT0__CAN2_TXCAN \
+ IOMUX_PAD(0x06A8, 0x02C0, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 \
+ IOMUX_PAD(0x06A8, 0x02C0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 \
+ IOMUX_PAD(0x06A8, 0x02C0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT0__GPIO_7_4 \
+ IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 \
+ IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 \
+ IOMUX_PAD(0x06A8, 0x02C0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 \
+ IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT1__UART1_CTS \
+ IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT1__UART1_RTS \
+ IOMUX_PAD(0x06AC, 0x02C4, 1, 0x091C, 3, 0)
+#define _MX6Q_PAD_SD3_DAT1__CAN2_RXCAN \
+ IOMUX_PAD(0x06AC, 0x02C4, 2, 0x07E8, 1, 0)
+#define _MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 \
+ IOMUX_PAD(0x06AC, 0x02C4, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 \
+ IOMUX_PAD(0x06AC, 0x02C4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT1__GPIO_7_5 \
+ IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 \
+ IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 \
+ IOMUX_PAD(0x06AC, 0x02C4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 \
+ IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 \
+ IOMUX_PAD(0x06B0, 0x02C8, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 \
+ IOMUX_PAD(0x06B0, 0x02C8, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 \
+ IOMUX_PAD(0x06B0, 0x02C8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT2__GPIO_7_6 \
+ IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 \
+ IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 \
+ IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 \
+ IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT3__UART3_CTS \
+ IOMUX_PAD(0x06B4, 0x02CC, 1, 0x092C, 4, 0)
+#define _MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 \
+ IOMUX_PAD(0x06B4, 0x02CC, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 \
+ IOMUX_PAD(0x06B4, 0x02CC, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 \
+ IOMUX_PAD(0x06B4, 0x02CC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT3__GPIO_7_7 \
+ IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 \
+ IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 \
+ IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_RST__USDHC3_RST \
+ IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_RST__UART3_CTS \
+ IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_RST__UART3_RTS \
+ IOMUX_PAD(0x06B8, 0x02D0, 1, 0x092C, 5, 0)
+#define _MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 \
+ IOMUX_PAD(0x06B8, 0x02D0, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 \
+ IOMUX_PAD(0x06B8, 0x02D0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 \
+ IOMUX_PAD(0x06B8, 0x02D0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_RST__GPIO_7_8 \
+ IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 \
+ IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 \
+ IOMUX_PAD(0x06B8, 0x02D0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_CLE__RAWNAND_CLE \
+ IOMUX_PAD(0x06BC, 0x02D4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 \
+ IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 \
+ IOMUX_PAD(0x06BC, 0x02D4, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 \
+ IOMUX_PAD(0x06BC, 0x02D4, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 \
+ IOMUX_PAD(0x06BC, 0x02D4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CLE__GPIO_6_7 \
+ IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 \
+ IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 \
+ IOMUX_PAD(0x06BC, 0x02D4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_ALE__RAWNAND_ALE \
+ IOMUX_PAD(0x06C0, 0x02D8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_ALE__USDHC4_RST \
+ IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 \
+ IOMUX_PAD(0x06C0, 0x02D8, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 \
+ IOMUX_PAD(0x06C0, 0x02D8, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 \
+ IOMUX_PAD(0x06C0, 0x02D8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_ALE__GPIO_6_8 \
+ IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 \
+ IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 \
+ IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN \
+ IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 \
+ IOMUX_PAD(0x06C4, 0x02DC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 \
+ IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 \
+ IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 \
+ IOMUX_PAD(0x06C4, 0x02DC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_WP_B__GPIO_6_9 \
+ IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 \
+ IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0 \
+ IOMUX_PAD(0x06C4, 0x02DC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 \
+ IOMUX_PAD(0x06C8, 0x02E0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 \
+ IOMUX_PAD(0x06C8, 0x02E0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 \
+ IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 \
+ IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 \
+ IOMUX_PAD(0x06C8, 0x02E0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_RB0__GPIO_6_10 \
+ IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 \
+ IOMUX_PAD(0x06C8, 0x02E0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1 \
+ IOMUX_PAD(0x06C8, 0x02E0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N \
+ IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 \
+ IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 \
+ IOMUX_PAD(0x06CC, 0x02E4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS0__GPIO_6_11 \
+ IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2 \
+ IOMUX_PAD(0x06CC, 0x02E4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N \
+ IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT \
+ IOMUX_PAD(0x06D0, 0x02E8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT \
+ IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 \
+ IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS1__GPIO_6_14 \
+ IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT \
+ IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N \
+ IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 \
+ IOMUX_PAD(0x06D4, 0x02EC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS2__ESAI1_TX0 \
+ IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0874, 1, 0)
+#define _MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE \
+ IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS2__CCM_CLKO2 \
+ IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS2__GPIO_6_15 \
+ IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 \
+ IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N \
+ IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 \
+ IOMUX_PAD(0x06D8, 0x02F0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS3__ESAI1_TX1 \
+ IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0878, 1, 0)
+#define _MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 \
+ IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 \
+ IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS3__GPIO_6_16 \
+ IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 \
+ IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS3__TPSMP_CLK \
+ IOMUX_PAD(0x06D8, 0x02F0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_CMD__USDHC4_CMD \
+ IOMUX_PAD(0x06DC, 0x02F4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_CMD__RAWNAND_RDN \
+ IOMUX_PAD(0x06DC, 0x02F4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_CMD__UART3_TXD \
+ IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_CMD__UART3_RXD \
+ IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0930, 2, 0)
+#define _MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 \
+ IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_CMD__GPIO_7_9 \
+ IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR \
+ IOMUX_PAD(0x06DC, 0x02F4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_CLK__USDHC4_CLK \
+ IOMUX_PAD(0x06E0, 0x02F8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_CLK__RAWNAND_WRN \
+ IOMUX_PAD(0x06E0, 0x02F8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_CLK__UART3_TXD \
+ IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_CLK__UART3_RXD \
+ IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0930, 3, 0)
+#define _MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 \
+ IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_CLK__GPIO_7_10 \
+ IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_D0__RAWNAND_D0 \
+ IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D0__USDHC1_DAT4 \
+ IOMUX_PAD(0x06E4, 0x02FC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 \
+ IOMUX_PAD(0x06E4, 0x02FC, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 \
+ IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 \
+ IOMUX_PAD(0x06E4, 0x02FC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D0__GPIO_2_0 \
+ IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 \
+ IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 \
+ IOMUX_PAD(0x06E4, 0x02FC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_D1__RAWNAND_D1 \
+ IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D1__USDHC1_DAT5 \
+ IOMUX_PAD(0x06E8, 0x0300, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 \
+ IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 \
+ IOMUX_PAD(0x06E8, 0x0300, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 \
+ IOMUX_PAD(0x06E8, 0x0300, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D1__GPIO_2_1 \
+ IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 \
+ IOMUX_PAD(0x06E8, 0x0300, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 \
+ IOMUX_PAD(0x06E8, 0x0300, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_D2__RAWNAND_D2 \
+ IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D2__USDHC1_DAT6 \
+ IOMUX_PAD(0x06EC, 0x0304, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 \
+ IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 \
+ IOMUX_PAD(0x06EC, 0x0304, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 \
+ IOMUX_PAD(0x06EC, 0x0304, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D2__GPIO_2_2 \
+ IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 \
+ IOMUX_PAD(0x06EC, 0x0304, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 \
+ IOMUX_PAD(0x06EC, 0x0304, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_D3__RAWNAND_D3 \
+ IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D3__USDHC1_DAT7 \
+ IOMUX_PAD(0x06F0, 0x0308, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 \
+ IOMUX_PAD(0x06F0, 0x0308, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 \
+ IOMUX_PAD(0x06F0, 0x0308, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 \
+ IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D3__GPIO_2_3 \
+ IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 \
+ IOMUX_PAD(0x06F0, 0x0308, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 \
+ IOMUX_PAD(0x06F0, 0x0308, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_D4__RAWNAND_D4 \
+ IOMUX_PAD(0x06F4, 0x030C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D4__USDHC2_DAT4 \
+ IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 \
+ IOMUX_PAD(0x06F4, 0x030C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 \
+ IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 \
+ IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D4__GPIO_2_4 \
+ IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 \
+ IOMUX_PAD(0x06F4, 0x030C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 \
+ IOMUX_PAD(0x06F4, 0x030C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_D5__RAWNAND_D5 \
+ IOMUX_PAD(0x06F8, 0x0310, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D5__USDHC2_DAT5 \
+ IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 \
+ IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 \
+ IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 \
+ IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D5__GPIO_2_5 \
+ IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 \
+ IOMUX_PAD(0x06F8, 0x0310, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 \
+ IOMUX_PAD(0x06F8, 0x0310, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_D6__RAWNAND_D6 \
+ IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D6__USDHC2_DAT6 \
+ IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 \
+ IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 \
+ IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 \
+ IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D6__GPIO_2_6 \
+ IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 \
+ IOMUX_PAD(0x06FC, 0x0314, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 \
+ IOMUX_PAD(0x06FC, 0x0314, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_D7__RAWNAND_D7 \
+ IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D7__USDHC2_DAT7 \
+ IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 \
+ IOMUX_PAD(0x0700, 0x0318, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 \
+ IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 \
+ IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D7__GPIO_2_7 \
+ IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 \
+ IOMUX_PAD(0x0700, 0x0318, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 \
+ IOMUX_PAD(0x0700, 0x0318, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_DAT0__RAWNAND_D8 \
+ IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 \
+ IOMUX_PAD(0x0704, 0x031C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT0__RAWNAND_DQS \
+ IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 \
+ IOMUX_PAD(0x0704, 0x031C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 \
+ IOMUX_PAD(0x0704, 0x031C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT0__GPIO_2_8 \
+ IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 \
+ IOMUX_PAD(0x0704, 0x031C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 \
+ IOMUX_PAD(0x0704, 0x031C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_DAT1__RAWNAND_D9 \
+ IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 \
+ IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT1__PWM3_PWMO \
+ IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 \
+ IOMUX_PAD(0x0708, 0x0320, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 \
+ IOMUX_PAD(0x0708, 0x0320, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT1__GPIO_2_9 \
+ IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 \
+ IOMUX_PAD(0x0708, 0x0320, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 \
+ IOMUX_PAD(0x0708, 0x0320, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_DAT2__RAWNAND_D10 \
+ IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 \
+ IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT2__PWM4_PWMO \
+ IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 \
+ IOMUX_PAD(0x070C, 0x0324, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 \
+ IOMUX_PAD(0x070C, 0x0324, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT2__GPIO_2_10 \
+ IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 \
+ IOMUX_PAD(0x070C, 0x0324, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 \
+ IOMUX_PAD(0x070C, 0x0324, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_DAT3__RAWNAND_D11 \
+ IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 \
+ IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 \
+ IOMUX_PAD(0x0710, 0x0328, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 \
+ IOMUX_PAD(0x0710, 0x0328, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT3__GPIO_2_11 \
+ IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 \
+ IOMUX_PAD(0x0710, 0x0328, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 \
+ IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_DAT4__RAWNAND_D12 \
+ IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 \
+ IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT4__UART2_TXD \
+ IOMUX_PAD(0x0714, 0x032C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT4__UART2_RXD \
+ IOMUX_PAD(0x0714, 0x032C, 2, 0x0928, 6, 0)
+#define _MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 \
+ IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 \
+ IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT4__GPIO_2_12 \
+ IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 \
+ IOMUX_PAD(0x0714, 0x032C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 \
+ IOMUX_PAD(0x0714, 0x032C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_DAT5__RAWNAND_D13 \
+ IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 \
+ IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT5__UART2_CTS \
+ IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT5__UART2_RTS \
+ IOMUX_PAD(0x0718, 0x0330, 2, 0x0924, 4, 0)
+#define _MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 \
+ IOMUX_PAD(0x0718, 0x0330, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 \
+ IOMUX_PAD(0x0718, 0x0330, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT5__GPIO_2_13 \
+ IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 \
+ IOMUX_PAD(0x0718, 0x0330, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 \
+ IOMUX_PAD(0x0718, 0x0330, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_DAT6__RAWNAND_D14 \
+ IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 \
+ IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT6__UART2_CTS \
+ IOMUX_PAD(0x071C, 0x0334, 2, 0x0924, 5, 0)
+#define _MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 \
+ IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 \
+ IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT6__GPIO_2_14 \
+ IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 \
+ IOMUX_PAD(0x071C, 0x0334, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 \
+ IOMUX_PAD(0x071C, 0x0334, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_DAT7__RAWNAND_D15 \
+ IOMUX_PAD(0x0720, 0x0338, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 \
+ IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT7__UART2_TXD \
+ IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT7__UART2_RXD \
+ IOMUX_PAD(0x0720, 0x0338, 2, 0x0928, 7, 0)
+#define _MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 \
+ IOMUX_PAD(0x0720, 0x0338, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 \
+ IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT7__GPIO_2_15 \
+ IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 \
+ IOMUX_PAD(0x0720, 0x0338, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 \
+ IOMUX_PAD(0x0720, 0x0338, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 \
+ IOMUX_PAD(0x0724, 0x033C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 \
+ IOMUX_PAD(0x0724, 0x033C, 1, 0x0834, 1, 0)
+#define _MX6Q_PAD_SD1_DAT1__PWM3_PWMO \
+ IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 \
+ IOMUX_PAD(0x0724, 0x033C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 \
+ IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT1__GPIO_1_17 \
+ IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 \
+ IOMUX_PAD(0x0724, 0x033C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 \
+ IOMUX_PAD(0x0724, 0x033C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 \
+ IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT0__ECSPI5_MISO \
+ IOMUX_PAD(0x0728, 0x0340, 1, 0x082C, 1, 0)
+#define _MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS \
+ IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 \
+ IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 \
+ IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT0__GPIO_1_16 \
+ IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 \
+ IOMUX_PAD(0x0728, 0x0340, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 \
+ IOMUX_PAD(0x0728, 0x0340, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 \
+ IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 \
+ IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 \
+ IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT3__PWM1_PWMO \
+ IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B \
+ IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT3__GPIO_1_21 \
+ IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB \
+ IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 \
+ IOMUX_PAD(0x072C, 0x0344, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD1_CMD__USDHC1_CMD \
+ IOMUX_PAD(0x0730, 0x0348, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_CMD__ECSPI5_MOSI \
+ IOMUX_PAD(0x0730, 0x0348, 1, 0x0830, 0, 0)
+#define _MX6Q_PAD_SD1_CMD__PWM4_PWMO \
+ IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 \
+ IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_CMD__GPIO_1_18 \
+ IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 \
+ IOMUX_PAD(0x0730, 0x0348, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 \
+ IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 \
+ IOMUX_PAD(0x0734, 0x034C, 1, 0x0838, 1, 0)
+#define _MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 \
+ IOMUX_PAD(0x0734, 0x034C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT2__PWM2_PWMO \
+ IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B \
+ IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT2__GPIO_1_19 \
+ IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB \
+ IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 \
+ IOMUX_PAD(0x0734, 0x034C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD1_CLK__USDHC1_CLK \
+ IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_CLK__ECSPI5_SCLK \
+ IOMUX_PAD(0x0738, 0x0350, 1, 0x0828, 0, 0)
+#define _MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT \
+ IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_CLK__GPT_CLKIN \
+ IOMUX_PAD(0x0738, 0x0350, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_CLK__GPIO_1_20 \
+ IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_CLK__PHY_DTB_0 \
+ IOMUX_PAD(0x0738, 0x0350, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 \
+ IOMUX_PAD(0x0738, 0x0350, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD2_CLK__USDHC2_CLK \
+ IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_CLK__ECSPI5_SCLK \
+ IOMUX_PAD(0x073C, 0x0354, 1, 0x0828, 1, 0)
+#define _MX6Q_PAD_SD2_CLK__KPP_COL_5 \
+ IOMUX_PAD(0x073C, 0x0354, 2, 0x08E8, 3, 0)
+#define _MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS \
+ IOMUX_PAD(0x073C, 0x0354, 3, 0x07C0, 1, 0)
+#define _MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 \
+ IOMUX_PAD(0x073C, 0x0354, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_CLK__GPIO_1_10 \
+ IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_CLK__PHY_DTB_1 \
+ IOMUX_PAD(0x073C, 0x0354, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 \
+ IOMUX_PAD(0x073C, 0x0354, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD2_CMD__USDHC2_CMD \
+ IOMUX_PAD(0x0740, 0x0358, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_CMD__ECSPI5_MOSI \
+ IOMUX_PAD(0x0740, 0x0358, 1, 0x0830, 1, 0)
+#define _MX6Q_PAD_SD2_CMD__KPP_ROW_5 \
+ IOMUX_PAD(0x0740, 0x0358, 2, 0x08F4, 2, 0)
+#define _MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC \
+ IOMUX_PAD(0x0740, 0x0358, 3, 0x07BC, 1, 0)
+#define _MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 \
+ IOMUX_PAD(0x0740, 0x0358, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_CMD__GPIO_1_11 \
+ IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 \
+ IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 \
+ IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT3__KPP_COL_6 \
+ IOMUX_PAD(0x0744, 0x035C, 2, 0x08EC, 2, 0)
+#define _MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC \
+ IOMUX_PAD(0x0744, 0x035C, 3, 0x07C4, 1, 0)
+#define _MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 \
+ IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT3__GPIO_1_12 \
+ IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT3__SJC_DONE \
+ IOMUX_PAD(0x0744, 0x035C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 \
+ IOMUX_PAD(0x0744, 0x035C, 7, 0x0000, 0, 0)
+
+
+
+#define MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 \
+ (_MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT1__USDHC2_DAT1_50MHZ_40OHM \
+ (_MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM))
+#define MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 \
+ (_MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 \
+ (_MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS \
+ (_MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT1__KPP_COL_7 \
+ (_MX6Q_PAD_SD2_DAT1__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT1__GPIO_1_14 \
+ (_MX6Q_PAD_SD2_DAT1__GPIO_1_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT1__CCM_WAIT \
+ (_MX6Q_PAD_SD2_DAT1__CCM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 \
+ (_MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 \
+ (_MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT2__USDHC2_DAT2_50MHZ_40OHM \
+ (_MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM))
+#define MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 \
+ (_MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 \
+ (_MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD \
+ (_MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT2__KPP_ROW_6 \
+ (_MX6Q_PAD_SD2_DAT2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT2__GPIO_1_13 \
+ (_MX6Q_PAD_SD2_DAT2__GPIO_1_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT2__CCM_STOP \
+ (_MX6Q_PAD_SD2_DAT2__CCM_STOP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 \
+ (_MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 \
+ (_MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT0__USDHC2_DAT0_50MHZ_40OHM \
+ (_MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM))
+#define MX6Q_PAD_SD2_DAT0__ECSPI5_MISO \
+ (_MX6Q_PAD_SD2_DAT0__ECSPI5_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD \
+ (_MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT0__KPP_ROW_7 \
+ (_MX6Q_PAD_SD2_DAT0__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT0__GPIO_1_15 \
+ (_MX6Q_PAD_SD2_DAT0__GPIO_1_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT \
+ (_MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 \
+ (_MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+
+#define MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA \
+ (_MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA | MUX_PAD_CTRL(MX6Q_USB_HSIC_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC \
+ (_MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK \
+ (_MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TXC__GPIO_6_19 \
+ (_MX6Q_PAD_RGMII_TXC__GPIO_6_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 \
+ (_MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT \
+ (_MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+
+#define MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY \
+ (_MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 \
+ (_MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TD0__GPIO_6_20 \
+ (_MX6Q_PAD_RGMII_TD0__GPIO_6_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 \
+ (_MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG \
+ (_MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 \
+ (_MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TD1__GPIO_6_21 \
+ (_MX6Q_PAD_RGMII_TD1__GPIO_6_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 \
+ (_MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP \
+ (_MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+
+#define MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA \
+ (_MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 \
+ (_MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TD2__GPIO_6_22 \
+ (_MX6Q_PAD_RGMII_TD2__GPIO_6_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 \
+ (_MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP \
+ (_MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+
+#define MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE \
+ (_MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 \
+ (_MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TD3__GPIO_6_23 \
+ (_MX6Q_PAD_RGMII_TD3__GPIO_6_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 \
+ (_MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+
+#define MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA \
+ (_MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA | MUX_PAD_CTRL(MX6Q_USB_HSIC_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL \
+ (_MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 \
+ (_MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 \
+ (_MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+
+#define MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY \
+ (_MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 \
+ (_MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RD0__GPIO_6_25 \
+ (_MX6Q_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 \
+ (_MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+
+#define MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE \
+ (_MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE | MUX_PAD_CTRL(MX6Q_USB_HSIC_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE_START \
+ (_MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE | \
+ MUX_PAD_CTRL(MX6Q_USB_HSIC_PAD_CTRL | PAD_CTL_PUS_47K_UP)\
+ )
+#define MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL \
+ (_MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 \
+ (_MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 \
+ (_MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT \
+ (_MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG \
+ (_MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 \
+ (_MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RD1__GPIO_6_27 \
+ (_MX6Q_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 \
+ (_MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RD1__SJC_FAIL \
+ (_MX6Q_PAD_RGMII_RD1__SJC_FAIL | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA \
+ (_MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 \
+ (_MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RD2__GPIO_6_28 \
+ (_MX6Q_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 \
+ (_MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE \
+ (_MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 \
+ (_MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RD3__GPIO_6_29 \
+ (_MX6Q_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 \
+ (_MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE \
+ (_MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE | MUX_PAD_CTRL(MX6Q_USB_HSIC_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE_START \
+ (_MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE | MUX_PAD_CTRL(MX6Q_USB_HSIC_PAD_CTRL | PAD_CTL_PUS_47K_UP))
+#define MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC \
+ (_MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RXC__GPIO_6_30 \
+ (_MX6Q_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 \
+ (_MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 \
+ (_MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A25__ECSPI4_SS1 \
+ (_MX6Q_PAD_EIM_A25__ECSPI4_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A25__ECSPI2_RDY \
+ (_MX6Q_PAD_EIM_A25__ECSPI2_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 \
+ (_MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS \
+ (_MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A25__GPIO_5_2 \
+ (_MX6Q_PAD_EIM_A25__GPIO_5_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE \
+ (_MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE | MUX_PAD_CTRL(MX6Q_HDMICEC_PAD_CTRL))
+#define MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0 \
+ (_MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 \
+ (_MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB2__ECSPI1_SS0 \
+ (_MX6Q_PAD_EIM_EB2__ECSPI1_SS0 | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK \
+ (_MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 \
+ (_MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL \
+ (_MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB2__GPIO_2_30 \
+ (_MX6Q_PAD_EIM_EB2__GPIO_2_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB2__I2C2_SCL \
+ (_MX6Q_PAD_EIM_EB2__I2C2_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 \
+ (_MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 \
+ (_MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_D16__ECSPI1_SCLK \
+ (_MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
+#define MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 \
+ (_MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 \
+ (_MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA \
+ (_MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D16__GPIO_3_16 \
+ (_MX6Q_PAD_EIM_D16__GPIO_3_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D16__I2C2_SDA \
+ (_MX6Q_PAD_EIM_D16__I2C2_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 \
+ (_MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_D17__ECSPI1_MISO \
+ (_MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
+#define MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 \
+ (_MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK \
+ (_MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT \
+ (_MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D17__GPIO_3_17 \
+ (_MX6Q_PAD_EIM_D17__GPIO_3_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D17__I2C3_SCL \
+ (_MX6Q_PAD_EIM_D17__I2C3_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 \
+ (_MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 \
+ (_MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_D18__ECSPI1_MOSI \
+ (_MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
+#define MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 \
+ (_MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 \
+ (_MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS \
+ (_MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D18__GPIO_3_18 \
+ (_MX6Q_PAD_EIM_D18__GPIO_3_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D18__I2C3_SDA \
+ (_MX6Q_PAD_EIM_D18__I2C3_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 \
+ (_MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 \
+ (_MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_D19__ECSPI1_SS1 \
+ (_MX6Q_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
+#define MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 \
+ (_MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 \
+ (_MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D19__UART1_CTS \
+ (_MX6Q_PAD_EIM_D19__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D19__GPIO_3_19 \
+ (_MX6Q_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
+#define MX6Q_PAD_EIM_D19__EPIT1_EPITO \
+ (_MX6Q_PAD_EIM_D19__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP \
+ (_MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 \
+ (_MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_D20__ECSPI4_SS0 \
+ (_MX6Q_PAD_EIM_D20__ECSPI4_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 \
+ (_MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 \
+ (_MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D20__UART1_CTS \
+ (_MX6Q_PAD_EIM_D20__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D20__UART1_RTS \
+ (_MX6Q_PAD_EIM_D20__UART1_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D20__GPIO_3_20 \
+ (_MX6Q_PAD_EIM_D20__GPIO_3_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D20__EPIT2_EPITO \
+ (_MX6Q_PAD_EIM_D20__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 \
+ (_MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_D21__ECSPI4_SCLK \
+ (_MX6Q_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 \
+ (_MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 \
+ (_MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC \
+ (_MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D21__GPIO_3_21 \
+ (_MX6Q_PAD_EIM_D21__GPIO_3_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D21__I2C1_SCL \
+ (_MX6Q_PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define MX6Q_PAD_EIM_D21__SPDIF_IN1 \
+ (_MX6Q_PAD_EIM_D21__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 \
+ (_MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_D22__ECSPI4_MISO \
+ (_MX6Q_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 \
+ (_MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 \
+ (_MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR \
+ (_MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D22__GPIO_3_22 \
+ (_MX6Q_PAD_EIM_D22__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D22__SPDIF_OUT1 \
+ (_MX6Q_PAD_EIM_D22__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE \
+ (_MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 \
+ (_MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS \
+ (_MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D23__UART3_CTS \
+ (_MX6Q_PAD_EIM_D23__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D23__UART1_DCD \
+ (_MX6Q_PAD_EIM_D23__UART1_DCD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN \
+ (_MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D23__GPIO_3_23 \
+ (_MX6Q_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 \
+ (_MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 \
+ (_MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 \
+ (_MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB3__ECSPI4_RDY \
+ (_MX6Q_PAD_EIM_EB3__ECSPI4_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB3__UART3_CTS \
+ (_MX6Q_PAD_EIM_EB3__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB3__UART3_RTS \
+ (_MX6Q_PAD_EIM_EB3__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB3__UART1_RI \
+ (_MX6Q_PAD_EIM_EB3__UART1_RI | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC \
+ (_MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB3__GPIO_2_31 \
+ (_MX6Q_PAD_EIM_EB3__GPIO_2_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 \
+ (_MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 \
+ (_MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 \
+ (_MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_D24__ECSPI4_SS2 \
+ (_MX6Q_PAD_EIM_D24__ECSPI4_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D24__UART3_TXD \
+ (_MX6Q_PAD_EIM_D24__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D24__UART3_RXD \
+ (_MX6Q_PAD_EIM_D24__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D24__ECSPI1_SS2 \
+ (_MX6Q_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D24__ECSPI2_SS2 \
+ (_MX6Q_PAD_EIM_D24__ECSPI2_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D24__GPIO_3_24 \
+ (_MX6Q_PAD_EIM_D24__GPIO_3_24 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
+#define MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS \
+ (_MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D24__UART1_DTR \
+ (_MX6Q_PAD_EIM_D24__UART1_DTR | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 \
+ (_MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_D25__ECSPI4_SS3 \
+ (_MX6Q_PAD_EIM_D25__ECSPI4_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D25__UART3_TXD \
+ (_MX6Q_PAD_EIM_D25__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D25__UART3_RXD \
+ (_MX6Q_PAD_EIM_D25__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D25__ECSPI1_SS3 \
+ (_MX6Q_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D25__ECSPI2_SS3 \
+ (_MX6Q_PAD_EIM_D25__ECSPI2_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D25__GPIO_3_25 \
+ (_MX6Q_PAD_EIM_D25__GPIO_3_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC \
+ (_MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D25__UART1_DSR \
+ (_MX6Q_PAD_EIM_D25__UART1_DSR | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 \
+ (_MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 \
+ (_MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 \
+ (_MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 \
+ (_MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D26__UART2_TXD \
+ (_MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D26__UART2_RXD \
+ (_MX6Q_PAD_EIM_D26__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D26__GPIO_3_26 \
+ (_MX6Q_PAD_EIM_D26__GPIO_3_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D26__IPU1_SISG_2 \
+ (_MX6Q_PAD_EIM_D26__IPU1_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 \
+ (_MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 \
+ (_MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 \
+ (_MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 \
+ (_MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 \
+ (_MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D27__UART2_TXD \
+ (_MX6Q_PAD_EIM_D27__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D27__UART2_RXD \
+ (_MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D27__GPIO_3_27 \
+ (_MX6Q_PAD_EIM_D27__GPIO_3_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D27__IPU1_SISG_3 \
+ (_MX6Q_PAD_EIM_D27__IPU1_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 \
+ (_MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 \
+ (_MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_D28__I2C1_SDA \
+ (_MX6Q_PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define MX6Q_PAD_EIM_D28__ECSPI4_MOSI \
+ (_MX6Q_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 \
+ (_MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D28__UART2_CTS \
+ (_MX6Q_PAD_EIM_D28__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D28__UART2_RTS \
+ (_MX6Q_PAD_EIM_D28__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D28__GPIO_3_28 \
+ (_MX6Q_PAD_EIM_D28__GPIO_3_28 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
+#define MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG \
+ (_MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 \
+ (_MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 \
+ (_MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 \
+ (_MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D29__ECSPI4_SS0 \
+ (_MX6Q_PAD_EIM_D29__ECSPI4_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D29__UART2_CTS \
+ (_MX6Q_PAD_EIM_D29__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D29__UART2_RTS \
+ (_MX6Q_PAD_EIM_D29__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D29__GPIO_3_29 \
+ (_MX6Q_PAD_EIM_D29__GPIO_3_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC \
+ (_MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 \
+ (_MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 \
+ (_MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 \
+ (_MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 \
+ (_MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 \
+ (_MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D30__UART3_CTS \
+ (_MX6Q_PAD_EIM_D30__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D30__GPIO_3_30 \
+ (_MX6Q_PAD_EIM_D30__GPIO_3_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC \
+ (_MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0 \
+ (_MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 \
+ (_MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 \
+ (_MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 \
+ (_MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 \
+ (_MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D31__UART3_CTS \
+ (_MX6Q_PAD_EIM_D31__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D31__UART3_RTS \
+ (_MX6Q_PAD_EIM_D31__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D31__GPIO_3_31 \
+ (_MX6Q_PAD_EIM_D31__GPIO_3_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR \
+ (_MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1 \
+ (_MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 \
+ (_MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 \
+ (_MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 \
+ (_MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A24__IPU2_SISG_2 \
+ (_MX6Q_PAD_EIM_A24__IPU2_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A24__IPU1_SISG_2 \
+ (_MX6Q_PAD_EIM_A24__IPU1_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A24__GPIO_5_4 \
+ (_MX6Q_PAD_EIM_A24__GPIO_5_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2 \
+ (_MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 \
+ (_MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 \
+ (_MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 \
+ (_MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 \
+ (_MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A23__IPU2_SISG_3 \
+ (_MX6Q_PAD_EIM_A23__IPU2_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A23__IPU1_SISG_3 \
+ (_MX6Q_PAD_EIM_A23__IPU1_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A23__GPIO_6_6 \
+ (_MX6Q_PAD_EIM_A23__GPIO_6_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3 \
+ (_MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 \
+ (_MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 \
+ (_MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 \
+ (_MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 \
+ (_MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A22__GPIO_2_16 \
+ (_MX6Q_PAD_EIM_A22__GPIO_2_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 \
+ (_MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 \
+ (_MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 \
+ (_MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 \
+ (_MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 \
+ (_MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A21__RESERVED_RESERVED \
+ (_MX6Q_PAD_EIM_A21__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 \
+ (_MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A21__GPIO_2_17 \
+ (_MX6Q_PAD_EIM_A21__GPIO_2_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 \
+ (_MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 \
+ (_MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 \
+ (_MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 \
+ (_MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 \
+ (_MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A20__RESERVED_RESERVED \
+ (_MX6Q_PAD_EIM_A20__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 \
+ (_MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A20__GPIO_2_18 \
+ (_MX6Q_PAD_EIM_A20__GPIO_2_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 \
+ (_MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 \
+ (_MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 \
+ (_MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 \
+ (_MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 \
+ (_MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A19__RESERVED_RESERVED \
+ (_MX6Q_PAD_EIM_A19__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 \
+ (_MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A19__GPIO_2_19 \
+ (_MX6Q_PAD_EIM_A19__GPIO_2_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 \
+ (_MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 \
+ (_MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 \
+ (_MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 \
+ (_MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 \
+ (_MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A18__RESERVED_RESERVED \
+ (_MX6Q_PAD_EIM_A18__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 \
+ (_MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A18__GPIO_2_20 \
+ (_MX6Q_PAD_EIM_A18__GPIO_2_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 \
+ (_MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 \
+ (_MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 \
+ (_MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 \
+ (_MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 \
+ (_MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A17__RESERVED_RESERVED \
+ (_MX6Q_PAD_EIM_A17__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 \
+ (_MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A17__GPIO_2_21 \
+ (_MX6Q_PAD_EIM_A17__GPIO_2_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 \
+ (_MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 \
+ (_MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 \
+ (_MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK \
+ (_MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK \
+ (_MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 \
+ (_MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A16__GPIO_2_22 \
+ (_MX6Q_PAD_EIM_A16__GPIO_2_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 \
+ (_MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 \
+ (_MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 \
+ (_MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 \
+ (_MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_CS0__ECSPI2_SCLK \
+ (_MX6Q_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 \
+ (_MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_CS0__GPIO_2_23 \
+ (_MX6Q_PAD_EIM_CS0__GPIO_2_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 \
+ (_MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 \
+ (_MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 \
+ (_MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_CS1__ECSPI2_MOSI \
+ (_MX6Q_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 \
+ (_MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_CS1__GPIO_2_24 \
+ (_MX6Q_PAD_EIM_CS1__GPIO_2_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 \
+ (_MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_OE__WEIM_WEIM_OE \
+ (_MX6Q_PAD_EIM_OE__WEIM_WEIM_OE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 \
+ (_MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_OE__ECSPI2_MISO \
+ (_MX6Q_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 \
+ (_MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_OE__GPIO_2_25 \
+ (_MX6Q_PAD_EIM_OE__GPIO_2_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 \
+ (_MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_RW__WEIM_WEIM_RW \
+ (_MX6Q_PAD_EIM_RW__WEIM_WEIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 \
+ (_MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_RW__ECSPI2_SS0 \
+ (_MX6Q_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 \
+ (_MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_RW__GPIO_2_26 \
+ (_MX6Q_PAD_EIM_RW__GPIO_2_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 \
+ (_MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 \
+ (_MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA \
+ (_MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 \
+ (_MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_LBA__ECSPI2_SS1 \
+ (_MX6Q_PAD_EIM_LBA__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_LBA__GPIO_2_27 \
+ (_MX6Q_PAD_EIM_LBA__GPIO_2_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 \
+ (_MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 \
+ (_MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 \
+ (_MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 \
+ (_MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 \
+ (_MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 \
+ (_MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY \
+ (_MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB0__GPIO_2_28 \
+ (_MX6Q_PAD_EIM_EB0__GPIO_2_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 \
+ (_MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 \
+ (_MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 \
+ (_MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 \
+ (_MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 \
+ (_MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 \
+ (_MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB1__GPIO_2_29 \
+ (_MX6Q_PAD_EIM_EB1__GPIO_2_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 \
+ (_MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 \
+ (_MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 \
+ (_MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 \
+ (_MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 \
+ (_MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 \
+ (_MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA0__GPIO_3_0 \
+ (_MX6Q_PAD_EIM_DA0__GPIO_3_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 \
+ (_MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 \
+ (_MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 \
+ (_MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 \
+ (_MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 \
+ (_MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 \
+ (_MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE \
+ (_MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA1__GPIO_3_1 \
+ (_MX6Q_PAD_EIM_DA1__GPIO_3_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 \
+ (_MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 \
+ (_MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 \
+ (_MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 \
+ (_MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 \
+ (_MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 \
+ (_MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE \
+ (_MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA2__GPIO_3_2 \
+ (_MX6Q_PAD_EIM_DA2__GPIO_3_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 \
+ (_MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 \
+ (_MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 \
+ (_MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 \
+ (_MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 \
+ (_MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 \
+ (_MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ \
+ (_MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA3__GPIO_3_3 \
+ (_MX6Q_PAD_EIM_DA3__GPIO_3_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 \
+ (_MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 \
+ (_MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 \
+ (_MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 \
+ (_MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 \
+ (_MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 \
+ (_MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN \
+ (_MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA4__GPIO_3_4 \
+ (_MX6Q_PAD_EIM_DA4__GPIO_3_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 \
+ (_MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 \
+ (_MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 \
+ (_MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 \
+ (_MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 \
+ (_MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 \
+ (_MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP \
+ (_MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA5__GPIO_3_5 \
+ (_MX6Q_PAD_EIM_DA5__GPIO_3_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 \
+ (_MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 \
+ (_MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 \
+ (_MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 \
+ (_MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 \
+ (_MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 \
+ (_MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN \
+ (_MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA6__GPIO_3_6 \
+ (_MX6Q_PAD_EIM_DA6__GPIO_3_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 \
+ (_MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 \
+ (_MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 \
+ (_MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 \
+ (_MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 \
+ (_MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 \
+ (_MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA7__GPIO_3_7 \
+ (_MX6Q_PAD_EIM_DA7__GPIO_3_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 \
+ (_MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 \
+ (_MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 \
+ (_MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 \
+ (_MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 \
+ (_MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 \
+ (_MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA8__GPIO_3_8 \
+ (_MX6Q_PAD_EIM_DA8__GPIO_3_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 \
+ (_MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 \
+ (_MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 \
+ (_MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 \
+ (_MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 \
+ (_MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 \
+ (_MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA9__GPIO_3_9 \
+ (_MX6Q_PAD_EIM_DA9__GPIO_3_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 \
+ (_MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 \
+ (_MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 \
+ (_MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 \
+ (_MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN \
+ (_MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 \
+ (_MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA10__GPIO_3_10 \
+ (_MX6Q_PAD_EIM_DA10__GPIO_3_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 \
+ (_MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 \
+ (_MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 \
+ (_MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 \
+ (_MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC \
+ (_MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 \
+ (_MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 \
+ (_MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA11__GPIO_3_11 \
+ (_MX6Q_PAD_EIM_DA11__GPIO_3_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 \
+ (_MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 \
+ (_MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 \
+ (_MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 \
+ (_MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC \
+ (_MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 \
+ (_MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 \
+ (_MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA12__GPIO_3_12 \
+ (_MX6Q_PAD_EIM_DA12__GPIO_3_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 \
+ (_MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 \
+ (_MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 \
+ (_MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS \
+ (_MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK \
+ (_MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 \
+ (_MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 \
+ (_MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA13__GPIO_3_13 \
+ (_MX6Q_PAD_EIM_DA13__GPIO_3_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 \
+ (_MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 \
+ (_MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 \
+ (_MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS \
+ (_MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK \
+ (_MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 \
+ (_MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 \
+ (_MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA14__GPIO_3_14 \
+ (_MX6Q_PAD_EIM_DA14__GPIO_3_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 \
+ (_MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 \
+ (_MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 \
+ (_MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 \
+ (_MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 \
+ (_MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 \
+ (_MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA15__GPIO_3_15 \
+ (_MX6Q_PAD_EIM_DA15__GPIO_3_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 \
+ (_MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 \
+ (_MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT \
+ (_MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B \
+ (_MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_WAIT__GPIO_5_0 \
+ (_MX6Q_PAD_EIM_WAIT__GPIO_5_0 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
+#define MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 \
+ (_MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 \
+ (_MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK \
+ (_MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 \
+ (_MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_BCLK__GPIO_6_31 \
+ (_MX6Q_PAD_EIM_BCLK__GPIO_6_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 \
+ (_MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK \
+ (_MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK \
+ (_MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 \
+ (_MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 \
+ (_MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 \
+ (_MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 \
+ (_MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 \
+ (_MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 \
+ (_MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC \
+ (_MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 \
+ (_MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 \
+ (_MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN15__GPIO_4_17 \
+ (_MX6Q_PAD_DI0_PIN15__GPIO_4_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 \
+ (_MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 \
+ (_MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 \
+ (_MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD \
+ (_MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 \
+ (_MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 \
+ (_MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN2__GPIO_4_18 \
+ (_MX6Q_PAD_DI0_PIN2__GPIO_4_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 \
+ (_MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9 \
+ (_MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 \
+ (_MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 \
+ (_MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS \
+ (_MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 \
+ (_MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 \
+ (_MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN3__GPIO_4_19 \
+ (_MX6Q_PAD_DI0_PIN3__GPIO_4_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 \
+ (_MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10 \
+ (_MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 \
+ (_MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 \
+ (_MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD \
+ (_MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN4__USDHC1_WP \
+ (_MX6Q_PAD_DI0_PIN4__USDHC1_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD \
+ (_MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN4__GPIO_4_20 \
+ (_MX6Q_PAD_DI0_PIN4__GPIO_4_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 \
+ (_MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11 \
+ (_MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 \
+ (_MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 \
+ (_MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK \
+ (_MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 \
+ (_MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN \
+ (_MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT0__GPIO_4_21 \
+ (_MX6Q_PAD_DISP0_DAT0__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 \
+ (_MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 \
+ (_MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 \
+ (_MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI \
+ (_MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 \
+ (_MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL \
+ (_MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT1__GPIO_4_22 \
+ (_MX6Q_PAD_DISP0_DAT1__GPIO_4_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 \
+ (_MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12 \
+ (_MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 \
+ (_MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 \
+ (_MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO \
+ (_MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 \
+ (_MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE \
+ (_MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT2__GPIO_4_23 \
+ (_MX6Q_PAD_DISP0_DAT2__GPIO_4_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 \
+ (_MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13 \
+ (_MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 \
+ (_MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 \
+ (_MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 \
+ (_MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 \
+ (_MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR \
+ (_MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT3__GPIO_4_24 \
+ (_MX6Q_PAD_DISP0_DAT3__GPIO_4_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 \
+ (_MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14 \
+ (_MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 \
+ (_MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 \
+ (_MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 \
+ (_MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 \
+ (_MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB \
+ (_MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT4__GPIO_4_25 \
+ (_MX6Q_PAD_DISP0_DAT4__GPIO_4_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 \
+ (_MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15 \
+ (_MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 \
+ (_MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 \
+ (_MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 \
+ (_MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS \
+ (_MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS \
+ (_MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT5__GPIO_4_26 \
+ (_MX6Q_PAD_DISP0_DAT5__GPIO_4_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 \
+ (_MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16 \
+ (_MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 \
+ (_MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 \
+ (_MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 \
+ (_MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC \
+ (_MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE \
+ (_MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT6__GPIO_4_27 \
+ (_MX6Q_PAD_DISP0_DAT6__GPIO_4_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 \
+ (_MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17 \
+ (_MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 \
+ (_MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 \
+ (_MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY \
+ (_MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 \
+ (_MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 \
+ (_MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT7__GPIO_4_28 \
+ (_MX6Q_PAD_DISP0_DAT7__GPIO_4_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 \
+ (_MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18 \
+ (_MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 \
+ (_MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 \
+ (_MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT8__PWM1_PWMO \
+ (_MX6Q_PAD_DISP0_DAT8__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B \
+ (_MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 \
+ (_MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT8__GPIO_4_29 \
+ (_MX6Q_PAD_DISP0_DAT8__GPIO_4_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 \
+ (_MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19 \
+ (_MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 \
+ (_MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 \
+ (_MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT9__PWM2_PWMO \
+ (_MX6Q_PAD_DISP0_DAT9__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B \
+ (_MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 \
+ (_MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT9__GPIO_4_30 \
+ (_MX6Q_PAD_DISP0_DAT9__GPIO_4_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 \
+ (_MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20 \
+ (_MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 \
+ (_MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 \
+ (_MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 \
+ (_MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 \
+ (_MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT10__GPIO_4_31 \
+ (_MX6Q_PAD_DISP0_DAT10__GPIO_4_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 \
+ (_MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21 \
+ (_MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 \
+ (_MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 \
+ (_MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 \
+ (_MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 \
+ (_MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT11__GPIO_5_5 \
+ (_MX6Q_PAD_DISP0_DAT11__GPIO_5_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 \
+ (_MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22 \
+ (_MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 \
+ (_MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 \
+ (_MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED \
+ (_MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 \
+ (_MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT12__GPIO_5_6 \
+ (_MX6Q_PAD_DISP0_DAT12__GPIO_5_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 \
+ (_MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23 \
+ (_MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 \
+ (_MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 \
+ (_MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS \
+ (_MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 \
+ (_MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT13__GPIO_5_7 \
+ (_MX6Q_PAD_DISP0_DAT13__GPIO_5_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 \
+ (_MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24 \
+ (_MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 \
+ (_MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 \
+ (_MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC \
+ (_MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 \
+ (_MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT14__GPIO_5_8 \
+ (_MX6Q_PAD_DISP0_DAT14__GPIO_5_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 \
+ (_MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 \
+ (_MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 \
+ (_MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 \
+ (_MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 \
+ (_MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 \
+ (_MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT15__GPIO_5_9 \
+ (_MX6Q_PAD_DISP0_DAT15__GPIO_5_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 \
+ (_MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25 \
+ (_MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 \
+ (_MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 \
+ (_MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI \
+ (_MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC \
+ (_MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 \
+ (_MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT16__GPIO_5_10 \
+ (_MX6Q_PAD_DISP0_DAT16__GPIO_5_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 \
+ (_MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26 \
+ (_MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 \
+ (_MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 \
+ (_MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO \
+ (_MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD \
+ (_MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 \
+ (_MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT17__GPIO_5_11 \
+ (_MX6Q_PAD_DISP0_DAT17__GPIO_5_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 \
+ (_MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27 \
+ (_MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 \
+ (_MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 \
+ (_MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 \
+ (_MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS \
+ (_MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS \
+ (_MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT18__GPIO_5_12 \
+ (_MX6Q_PAD_DISP0_DAT18__GPIO_5_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 \
+ (_MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 \
+ (_MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 \
+ (_MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 \
+ (_MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK \
+ (_MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD \
+ (_MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC \
+ (_MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT19__GPIO_5_13 \
+ (_MX6Q_PAD_DISP0_DAT19__GPIO_5_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 \
+ (_MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 \
+ (_MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 \
+ (_MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 \
+ (_MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK \
+ (_MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC \
+ (_MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 \
+ (_MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT20__GPIO_5_14 \
+ (_MX6Q_PAD_DISP0_DAT20__GPIO_5_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 \
+ (_MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28 \
+ (_MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 \
+ (_MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 \
+ (_MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI \
+ (_MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD \
+ (_MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 \
+ (_MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT21__GPIO_5_15 \
+ (_MX6Q_PAD_DISP0_DAT21__GPIO_5_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 \
+ (_MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29 \
+ (_MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 \
+ (_MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 \
+ (_MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO \
+ (_MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS \
+ (_MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 \
+ (_MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT22__GPIO_5_16 \
+ (_MX6Q_PAD_DISP0_DAT22__GPIO_5_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 \
+ (_MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30 \
+ (_MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 \
+ (_MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 \
+ (_MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 \
+ (_MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD \
+ (_MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 \
+ (_MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT23__GPIO_5_17 \
+ (_MX6Q_PAD_DISP0_DAT23__GPIO_5_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 \
+ (_MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31 \
+ (_MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED \
+ (_MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_MDIO__ENET_MDIO \
+ (_MX6Q_PAD_ENET_MDIO__ENET_MDIO | \
+ MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_ENET_MDIO__ESAI1_SCKR \
+ (_MX6Q_PAD_ENET_MDIO__ESAI1_SCKR | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
+#define MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 \
+ (_MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT \
+ (_MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_MDIO__GPIO_1_22 \
+ (_MX6Q_PAD_ENET_MDIO__GPIO_1_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK \
+ (_MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_ENET_REF_CLK__RESERVED_RESERVED \
+ (_MX6Q_PAD_ENET_REF_CLK__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK \
+ (_MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(MX6Q_ENET_REF_CLK_PAD_CTRL))
+#define MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR \
+ (_MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
+#define MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 \
+ (_MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 \
+ (_MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK \
+ (_MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH \
+ (_MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_ENET_RX_ER__ANATOP_USBOTG_ID \
+ (_MX6Q_PAD_ENET_RX_ER__ANATOP_USBOTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_RX_ER__ENET_RX_ER \
+ (_MX6Q_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR \
+ (_MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
+#define MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 \
+ (_MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT \
+ (_MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_RX_ER__GPIO_1_24 \
+ (_MX6Q_PAD_ENET_RX_ER__GPIO_1_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_RX_ER__PHY_TDI \
+ (_MX6Q_PAD_ENET_RX_ER__PHY_TDI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD \
+ (_MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_ENET_CRS_DV__RESERVED_RESERVED \
+ (_MX6Q_PAD_ENET_CRS_DV__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN \
+ (_MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT \
+ (_MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
+#define MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK \
+ (_MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 \
+ (_MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_CRS_DV__PHY_TDO \
+ (_MX6Q_PAD_ENET_CRS_DV__PHY_TDO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD \
+ (_MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_ENET_RXD1__MLB_MLBSIG \
+ (_MX6Q_PAD_ENET_RXD1__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 \
+ (_MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_RXD1__ESAI1_FST \
+ (_MX6Q_PAD_ENET_RXD1__ESAI1_FST | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
+#define MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT \
+ (_MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_RXD1__GPIO_1_26 \
+ (_MX6Q_PAD_ENET_RXD1__GPIO_1_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_RXD1__PHY_TCK \
+ (_MX6Q_PAD_ENET_RXD1__PHY_TCK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET \
+ (_MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT \
+ (_MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 \
+ (_MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_RXD0__ESAI1_HCKT \
+ (_MX6Q_PAD_ENET_RXD0__ESAI1_HCKT | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
+#define MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 \
+ (_MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_RXD0__GPIO_1_27 \
+ (_MX6Q_PAD_ENET_RXD0__GPIO_1_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_RXD0__PHY_TMS \
+ (_MX6Q_PAD_ENET_RXD0__PHY_TMS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV \
+ (_MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_ENET_TX_EN__RESERVED_RESERVED \
+ (_MX6Q_PAD_ENET_TX_EN__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_TX_EN__ENET_TX_EN \
+ (_MX6Q_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 \
+ (_MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
+#define MX6Q_PAD_ENET_TX_EN__GPIO_1_28 \
+ (_MX6Q_PAD_ENET_TX_EN__GPIO_1_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI \
+ (_MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH \
+ (_MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_ENET_TXD1__MLB_MLBCLK \
+ (_MX6Q_PAD_ENET_TXD1__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 \
+ (_MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 \
+ (_MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
+#define MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN \
+ (_MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_TXD1__GPIO_1_29 \
+ (_MX6Q_PAD_ENET_TXD1__GPIO_1_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO \
+ (_MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD \
+ (_MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_ENET_TXD0__RESERVED_RESERVED \
+ (_MX6Q_PAD_ENET_TXD0__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 \
+ (_MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 \
+ (_MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
+#define MX6Q_PAD_ENET_TXD0__GPIO_1_30 \
+ (_MX6Q_PAD_ENET_TXD0__GPIO_1_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK \
+ (_MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD \
+ (_MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_ENET_MDC__MLB_MLBDAT \
+ (_MX6Q_PAD_ENET_MDC__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_MDC__ENET_MDC \
+ (_MX6Q_PAD_ENET_MDC__ENET_MDC | \
+ MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 \
+ (_MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
+#define MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN \
+ (_MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_MDC__GPIO_1_31 \
+ (_MX6Q_PAD_ENET_MDC__GPIO_1_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_MDC__SATA_PHY_TMS \
+ (_MX6Q_PAD_ENET_MDC__SATA_PHY_TMS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET \
+ (_MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 \
+ (_MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 \
+ (_MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 \
+ (_MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 \
+ (_MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 \
+ (_MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 \
+ (_MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 \
+ (_MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 \
+ (_MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 \
+ (_MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 \
+ (_MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 \
+ (_MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 \
+ (_MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 \
+ (_MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 \
+ (_MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 \
+ (_MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 \
+ (_MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 \
+ (_MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 \
+ (_MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 \
+ (_MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 \
+ (_MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 \
+ (_MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 \
+ (_MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 \
+ (_MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 \
+ (_MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 \
+ (_MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 \
+ (_MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 \
+ (_MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 \
+ (_MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 \
+ (_MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 \
+ (_MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 \
+ (_MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 \
+ (_MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 \
+ (_MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 \
+ (_MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 \
+ (_MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 \
+ (_MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 \
+ (_MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 \
+ (_MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 \
+ (_MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 \
+ (_MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 \
+ (_MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 \
+ (_MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 \
+ (_MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 \
+ (_MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 \
+ (_MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 \
+ (_MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 \
+ (_MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 \
+ (_MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 \
+ (_MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 \
+ (_MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 \
+ (_MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 \
+ (_MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 \
+ (_MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 \
+ (_MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 \
+ (_MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 \
+ (_MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS \
+ (_MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 \
+ (_MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 \
+ (_MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS \
+ (_MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET \
+ (_MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 \
+ (_MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 \
+ (_MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 \
+ (_MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 \
+ (_MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 \
+ (_MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 \
+ (_MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 \
+ (_MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 \
+ (_MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 \
+ (_MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE \
+ (_MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 \
+ (_MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 \
+ (_MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 \
+ (_MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 \
+ (_MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 \
+ (_MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 \
+ (_MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 \
+ (_MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 \
+ (_MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 \
+ (_MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 \
+ (_MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 \
+ (_MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 \
+ (_MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 \
+ (_MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 \
+ (_MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 \
+ (_MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 \
+ (_MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 \
+ (_MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 \
+ (_MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 \
+ (_MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 \
+ (_MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 \
+ (_MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 \
+ (_MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 \
+ (_MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 \
+ (_MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 \
+ (_MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 \
+ (_MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 \
+ (_MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 \
+ (_MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 \
+ (_MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 \
+ (_MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 \
+ (_MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 \
+ (_MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 \
+ (_MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 \
+ (_MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 \
+ (_MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 \
+ (_MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 \
+ (_MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 \
+ (_MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 \
+ (_MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 \
+ (_MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_KEY_COL0__ECSPI1_SCLK \
+ (_MX6Q_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL0__ENET_RDATA_3 \
+ (_MX6Q_PAD_KEY_COL0__ENET_RDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC \
+ (_MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL0__KPP_COL_0 \
+ (_MX6Q_PAD_KEY_COL0__KPP_COL_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL0__UART4_TXD \
+ (_MX6Q_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL0__UART4_RXD \
+ (_MX6Q_PAD_KEY_COL0__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL0__GPIO_4_6 \
+ (_MX6Q_PAD_KEY_COL0__GPIO_4_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT \
+ (_MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST \
+ (_MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI \
+ (_MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 \
+ (_MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD \
+ (_MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW0__KPP_ROW_0 \
+ (_MX6Q_PAD_KEY_ROW0__KPP_ROW_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW0__UART4_TXD \
+ (_MX6Q_PAD_KEY_ROW0__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW0__UART4_RXD \
+ (_MX6Q_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW0__GPIO_4_7 \
+ (_MX6Q_PAD_KEY_ROW0__GPIO_4_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT \
+ (_MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0 \
+ (_MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_KEY_COL1__ECSPI1_MISO \
+ (_MX6Q_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL1__ENET_MDIO \
+ (_MX6Q_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS \
+ (_MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL1__KPP_COL_1 \
+ (_MX6Q_PAD_KEY_COL1__KPP_COL_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL1__UART5_TXD \
+ (_MX6Q_PAD_KEY_COL1__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL1__UART5_RXD \
+ (_MX6Q_PAD_KEY_COL1__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL1__GPIO_4_8 \
+ (_MX6Q_PAD_KEY_COL1__GPIO_4_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL1__USDHC1_VSELECT \
+ (_MX6Q_PAD_KEY_COL1__USDHC1_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1 \
+ (_MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 \
+ (_MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW1__ENET_COL \
+ (_MX6Q_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD \
+ (_MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW1__KPP_ROW_1 \
+ (_MX6Q_PAD_KEY_ROW1__KPP_ROW_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW1__UART5_TXD \
+ (_MX6Q_PAD_KEY_ROW1__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW1__UART5_RXD \
+ (_MX6Q_PAD_KEY_ROW1__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW1__GPIO_4_9 \
+ (_MX6Q_PAD_KEY_ROW1__GPIO_4_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT \
+ (_MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2 \
+ (_MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_KEY_COL2__ECSPI1_SS1 \
+ (_MX6Q_PAD_KEY_COL2__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL2__ENET_RDATA_2 \
+ (_MX6Q_PAD_KEY_COL2__ENET_RDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL2__CAN1_TXCAN \
+ (_MX6Q_PAD_KEY_COL2__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL2__KPP_COL_2 \
+ (_MX6Q_PAD_KEY_COL2__KPP_COL_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL2__ENET_MDC \
+ (_MX6Q_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL2__GPIO_4_10 \
+ (_MX6Q_PAD_KEY_COL2__GPIO_4_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP \
+ (_MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3 \
+ (_MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 \
+ (_MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 \
+ (_MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW2__CAN1_RXCAN \
+ (_MX6Q_PAD_KEY_ROW2__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW2__KPP_ROW_2 \
+ (_MX6Q_PAD_KEY_ROW2__KPP_ROW_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT \
+ (_MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW2__GPIO_4_11 \
+ (_MX6Q_PAD_KEY_ROW2__GPIO_4_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE \
+ (_MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE | MUX_PAD_CTRL(MX6Q_HDMICEC_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4 \
+ (_MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_KEY_COL3__ECSPI1_SS3 \
+ (_MX6Q_PAD_KEY_COL3__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL3__ENET_CRS \
+ (_MX6Q_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL \
+ (_MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL3__KPP_COL_3 \
+ (_MX6Q_PAD_KEY_COL3__KPP_COL_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL3__I2C2_SCL \
+ (_MX6Q_PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL3__GPIO_4_12 \
+ (_MX6Q_PAD_KEY_COL3__GPIO_4_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL3__SPDIF_IN1 \
+ (_MX6Q_PAD_KEY_COL3__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5 \
+ (_MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT \
+ (_MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK \
+ (_MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA \
+ (_MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW3__KPP_ROW_3 \
+ (_MX6Q_PAD_KEY_ROW3__KPP_ROW_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW3__I2C2_SDA \
+ (_MX6Q_PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW3__GPIO_4_13 \
+ (_MX6Q_PAD_KEY_ROW3__GPIO_4_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT \
+ (_MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6 \
+ (_MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_KEY_COL4__CAN2_TXCAN \
+ (_MX6Q_PAD_KEY_COL4__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL4__IPU1_SISG_4 \
+ (_MX6Q_PAD_KEY_COL4__IPU1_SISG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC \
+ (_MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL4__KPP_COL_4 \
+ (_MX6Q_PAD_KEY_COL4__KPP_COL_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL4__UART5_CTS \
+ (_MX6Q_PAD_KEY_COL4__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL4__UART5_RTS \
+ (_MX6Q_PAD_KEY_COL4__UART5_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL4__GPIO_4_14 \
+ (_MX6Q_PAD_KEY_COL4__GPIO_4_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 \
+ (_MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7 \
+ (_MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_KEY_ROW4__CAN2_RXCAN \
+ (_MX6Q_PAD_KEY_ROW4__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 \
+ (_MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR \
+ (_MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW4__KPP_ROW_4 \
+ (_MX6Q_PAD_KEY_ROW4__KPP_ROW_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW4__UART5_CTS \
+ (_MX6Q_PAD_KEY_ROW4__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW4__GPIO_4_15 \
+ (_MX6Q_PAD_KEY_ROW4__GPIO_4_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 \
+ (_MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8 \
+ (_MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_GPIO_0__CCM_CLKO \
+ (_MX6Q_PAD_GPIO_0__CCM_CLKO | MUX_PAD_CTRL(MX6Q_CCM_CLK0_PAD_CTRL))
+#define MX6Q_PAD_GPIO_0__KPP_COL_5 \
+ (_MX6Q_PAD_GPIO_0__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK \
+ (_MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_0__EPIT1_EPITO \
+ (_MX6Q_PAD_GPIO_0__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_0__GPIO_1_0 \
+ (_MX6Q_PAD_GPIO_0__GPIO_1_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR \
+ (_MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 \
+ (_MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_GPIO_1__ESAI1_SCKR \
+ (_MX6Q_PAD_GPIO_1__ESAI1_SCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_1__WDOG2_WDOG_B \
+ (_MX6Q_PAD_GPIO_1__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_1__KPP_ROW_5 \
+ (_MX6Q_PAD_GPIO_1__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_1__PWM2_PWMO \
+ (_MX6Q_PAD_GPIO_1__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_1__GPIO_1_1 \
+ (_MX6Q_PAD_GPIO_1__GPIO_1_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_1__USDHC1_CD \
+ (_MX6Q_PAD_GPIO_1__USDHC1_CD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_GPIO_1__SRC_TESTER_ACK \
+ (_MX6Q_PAD_GPIO_1__SRC_TESTER_ACK | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_GPIO_9__ESAI1_FSR \
+ (_MX6Q_PAD_GPIO_9__ESAI1_FSR | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
+#define MX6Q_PAD_GPIO_9__WDOG1_WDOG_B \
+ (_MX6Q_PAD_GPIO_9__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_9__KPP_COL_6 \
+ (_MX6Q_PAD_GPIO_9__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_9__CCM_REF_EN_B \
+ (_MX6Q_PAD_GPIO_9__CCM_REF_EN_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_9__PWM1_PWMO \
+ (_MX6Q_PAD_GPIO_9__PWM1_PWMO | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
+#define MX6Q_PAD_GPIO_9__GPIO_1_9 \
+ (_MX6Q_PAD_GPIO_9__GPIO_1_9 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
+#define MX6Q_PAD_GPIO_9__USDHC1_WP \
+ (_MX6Q_PAD_GPIO_9__USDHC1_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_GPIO_9__SRC_EARLY_RST \
+ (_MX6Q_PAD_GPIO_9__SRC_EARLY_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_GPIO_3__ESAI1_HCKR \
+ (_MX6Q_PAD_GPIO_3__ESAI1_HCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 \
+ (_MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_3__I2C3_SCL \
+ (_MX6Q_PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT \
+ (_MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_3__CCM_CLKO2 \
+ (_MX6Q_PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_3__GPIO_1_3 \
+ (_MX6Q_PAD_GPIO_3__GPIO_1_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC \
+ (_MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_3__MLB_MLBCLK \
+ (_MX6Q_PAD_GPIO_3__MLB_MLBCLK | MUX_PAD_CTRL(MX6Q_MLB150_PAD_CTRL))
+
+#ifdef CONFIG_MX6_ENET_IRQ_TO_GPIO
+#define MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 \
+ (_MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 | MUX_PAD_CTRL(ENET_IRQ_PAD_CTRL))
+#else
+#define MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 \
+ (_MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_6__ESAI1_SCKT \
+ (_MX6Q_PAD_GPIO_6__ESAI1_SCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_6__GPIO_1_6 \
+ (_MX6Q_PAD_GPIO_6__GPIO_1_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_6__I2C3_SDA \
+ (_MX6Q_PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 \
+ (_MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB \
+ (_MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_6__USDHC2_LCTL \
+ (_MX6Q_PAD_GPIO_6__USDHC2_LCTL | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_GPIO_6__MLB_MLBSIG \
+ (_MX6Q_PAD_GPIO_6__MLB_MLBSIG | MUX_PAD_CTRL(MX6Q_MLB150_PAD_CTRL))
+#endif
+
+#define MX6Q_PAD_GPIO_2__ESAI1_FST \
+ (_MX6Q_PAD_GPIO_2__ESAI1_FST | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 \
+ (_MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_2__KPP_ROW_6 \
+ (_MX6Q_PAD_GPIO_2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 \
+ (_MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 \
+ (_MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_2__GPIO_1_2 \
+ (_MX6Q_PAD_GPIO_2__GPIO_1_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_2__USDHC2_WP \
+ (_MX6Q_PAD_GPIO_2__USDHC2_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_GPIO_2__MLB_MLBDAT \
+ (_MX6Q_PAD_GPIO_2__MLB_MLBDAT | MUX_PAD_CTRL(MX6Q_MLB150_PAD_CTRL))
+
+#define MX6Q_PAD_GPIO_4__ESAI1_HCKT \
+ (_MX6Q_PAD_GPIO_4__ESAI1_HCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 \
+ (_MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_4__KPP_COL_7 \
+ (_MX6Q_PAD_GPIO_4__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 \
+ (_MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 \
+ (_MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_4__GPIO_1_4 \
+ (_MX6Q_PAD_GPIO_4__GPIO_1_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_4__USDHC2_CD \
+ (_MX6Q_PAD_GPIO_4__USDHC2_CD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED \
+ (_MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 \
+ (_MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
+#define MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 \
+ (_MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_5__KPP_ROW_7 \
+ (_MX6Q_PAD_GPIO_5__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_5__CCM_CLKO \
+ (_MX6Q_PAD_GPIO_5__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 \
+ (_MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_5__GPIO_1_5 \
+ (_MX6Q_PAD_GPIO_5__GPIO_1_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_5__I2C3_SCL \
+ (_MX6Q_PAD_GPIO_5__I2C3_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define MX6Q_PAD_GPIO_5__CHEETAH_EVENTI \
+ (_MX6Q_PAD_GPIO_5__CHEETAH_EVENTI | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 \
+ (_MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_7__ECSPI5_RDY \
+ (_MX6Q_PAD_GPIO_7__ECSPI5_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_7__EPIT1_EPITO \
+ (_MX6Q_PAD_GPIO_7__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_7__CAN1_TXCAN \
+ (_MX6Q_PAD_GPIO_7__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_7__UART2_TXD \
+ (_MX6Q_PAD_GPIO_7__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_GPIO_7__UART2_RXD \
+ (_MX6Q_PAD_GPIO_7__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_GPIO_7__GPIO_1_7 \
+ (_MX6Q_PAD_GPIO_7__GPIO_1_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_7__SPDIF_PLOCK \
+ (_MX6Q_PAD_GPIO_7__SPDIF_PLOCK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE \
+ (_MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 \
+ (_MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT \
+ (_MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_8__EPIT2_EPITO \
+ (_MX6Q_PAD_GPIO_8__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_8__CAN1_RXCAN \
+ (_MX6Q_PAD_GPIO_8__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_8__UART2_TXD \
+ (_MX6Q_PAD_GPIO_8__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_GPIO_8__UART2_RXD \
+ (_MX6Q_PAD_GPIO_8__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_GPIO_8__GPIO_1_8 \
+ (_MX6Q_PAD_GPIO_8__GPIO_1_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_8__SPDIF_SRCLK \
+ (_MX6Q_PAD_GPIO_8__SPDIF_SRCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP \
+ (_MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 \
+ (_MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN \
+ (_MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT \
+ (_MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT | \
+ MUX_PAD_CTRL(MX6Q_GPIO_16_PAD_CTRL))
+#define MX6Q_PAD_GPIO_16__USDHC1_LCTL \
+ (_MX6Q_PAD_GPIO_16__USDHC1_LCTL | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_GPIO_16__SPDIF_IN1 \
+ (_MX6Q_PAD_GPIO_16__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_16__GPIO_7_11 \
+ (_MX6Q_PAD_GPIO_16__GPIO_7_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_16__I2C3_SDA \
+ (_MX6Q_PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define MX6Q_PAD_GPIO_16__SJC_DE_B \
+ (_MX6Q_PAD_GPIO_16__SJC_DE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_GPIO_17__ESAI1_TX0 \
+ (_MX6Q_PAD_GPIO_17__ESAI1_TX0 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
+#define MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN \
+ (_MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_17__CCM_PMIC_RDY \
+ (_MX6Q_PAD_GPIO_17__CCM_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 \
+ (_MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_17__SPDIF_OUT1 \
+ (_MX6Q_PAD_GPIO_17__SPDIF_OUT1 | MUX_PAD_CTRL(MX6Q_SPDIF_OUT_PAD_CTRL))
+#define MX6Q_PAD_GPIO_17__GPIO_7_12 \
+ (_MX6Q_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_17__SJC_JTAG_ACT \
+ (_MX6Q_PAD_GPIO_17__SJC_JTAG_ACT | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_GPIO_18__ESAI1_TX1 \
+ (_MX6Q_PAD_GPIO_18__ESAI1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_18__ENET_RX_CLK \
+ (_MX6Q_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_18__USDHC3_VSELECT \
+ (_MX6Q_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 \
+ (_MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK \
+ (_MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_18__GPIO_7_13 \
+ (_MX6Q_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL \
+ (_MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST \
+ (_MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_GPIO_19__KPP_COL_5 \
+ (_MX6Q_PAD_GPIO_19__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT \
+ (_MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_19__SPDIF_OUT1 \
+ (_MX6Q_PAD_GPIO_19__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_19__CCM_CLKO \
+ (_MX6Q_PAD_GPIO_19__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_19__ECSPI1_RDY \
+ (_MX6Q_PAD_GPIO_19__ECSPI1_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_19__GPIO_4_5 \
+ (_MX6Q_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_19__ENET_TX_ER \
+ (_MX6Q_PAD_GPIO_19__ENET_TX_ER | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_19__SRC_INT_BOOT \
+ (_MX6Q_PAD_GPIO_19__SRC_INT_BOOT | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK \
+ (_MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 \
+ (_MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 \
+ (_MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 \
+ (_MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 \
+ (_MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO \
+ (_MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC \
+ (_MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 \
+ (_MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_MCLK__CCM_CLKO \
+ (_MX6Q_PAD_CSI0_MCLK__CCM_CLKO | MUX_PAD_CTRL(MX6Q_CCM_CLK0_PAD_CTRL))
+#define MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 \
+ (_MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_MCLK__GPIO_5_19 \
+ (_MX6Q_PAD_CSI0_MCLK__GPIO_5_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 \
+ (_MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL \
+ (_MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN \
+ (_MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 \
+ (_MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 \
+ (_MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 \
+ (_MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 \
+ (_MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 \
+ (_MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK \
+ (_MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC \
+ (_MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 \
+ (_MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 \
+ (_MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 \
+ (_MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 \
+ (_MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 \
+ (_MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 \
+ (_MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 \
+ (_MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 \
+ (_MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK \
+ (_MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT4__KPP_COL_5 \
+ (_MX6Q_PAD_CSI0_DAT4__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC \
+ (_MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT4__GPIO_5_22 \
+ (_MX6Q_PAD_CSI0_DAT4__GPIO_5_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 \
+ (_MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 \
+ (_MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 \
+ (_MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 \
+ (_MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI \
+ (_MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 \
+ (_MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD \
+ (_MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD | \
+ MUX_PAD_CTRL(MX6Q_ADU_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT5__GPIO_5_23 \
+ (_MX6Q_PAD_CSI0_DAT5__GPIO_5_23 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
+#define MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 \
+ (_MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 \
+ (_MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 \
+ (_MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 \
+ (_MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO \
+ (_MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT6__KPP_COL_6 \
+ (_MX6Q_PAD_CSI0_DAT6__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS \
+ (_MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT6__GPIO_5_24 \
+ (_MX6Q_PAD_CSI0_DAT6__GPIO_5_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 \
+ (_MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 \
+ (_MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 \
+ (_MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 \
+ (_MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 \
+ (_MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 \
+ (_MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD \
+ (_MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD | \
+ MUX_PAD_CTRL(MX6Q_ADU_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT7__GPIO_5_25 \
+ (_MX6Q_PAD_CSI0_DAT7__GPIO_5_25 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
+#define MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 \
+ (_MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 \
+ (_MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 \
+ (_MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 \
+ (_MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK \
+ (_MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT8__KPP_COL_7 \
+ (_MX6Q_PAD_CSI0_DAT8__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT8__I2C1_SDA \
+ (_MX6Q_PAD_CSI0_DAT8__I2C1_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT8__GPIO_5_26 \
+ (_MX6Q_PAD_CSI0_DAT8__GPIO_5_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 \
+ (_MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 \
+ (_MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 \
+ (_MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 \
+ (_MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI \
+ (_MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 \
+ (_MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT9__I2C1_SCL \
+ (_MX6Q_PAD_CSI0_DAT9__I2C1_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT9__GPIO_5_27 \
+ (_MX6Q_PAD_CSI0_DAT9__GPIO_5_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 \
+ (_MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 \
+ (_MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 \
+ (_MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC \
+ (_MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO \
+ (_MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT10__UART1_TXD \
+ (_MX6Q_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT10__UART1_RXD \
+ (_MX6Q_PAD_CSI0_DAT10__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 \
+ (_MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT10__GPIO_5_28 \
+ (_MX6Q_PAD_CSI0_DAT10__GPIO_5_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 \
+ (_MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 \
+ (_MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 \
+ (_MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS \
+ (_MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 \
+ (_MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT11__UART1_TXD \
+ (_MX6Q_PAD_CSI0_DAT11__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT11__UART1_RXD \
+ (_MX6Q_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 \
+ (_MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT11__GPIO_5_29 \
+ (_MX6Q_PAD_CSI0_DAT11__GPIO_5_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 \
+ (_MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 \
+ (_MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 \
+ (_MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 \
+ (_MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 \
+ (_MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT12__UART4_TXD \
+ (_MX6Q_PAD_CSI0_DAT12__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT12__UART4_RXD \
+ (_MX6Q_PAD_CSI0_DAT12__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 \
+ (_MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT12__GPIO_5_30 \
+ (_MX6Q_PAD_CSI0_DAT12__GPIO_5_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 \
+ (_MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 \
+ (_MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 \
+ (_MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 \
+ (_MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 \
+ (_MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT13__UART4_TXD \
+ (_MX6Q_PAD_CSI0_DAT13__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT13__UART4_RXD \
+ (_MX6Q_PAD_CSI0_DAT13__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 \
+ (_MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT13__GPIO_5_31 \
+ (_MX6Q_PAD_CSI0_DAT13__GPIO_5_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 \
+ (_MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 \
+ (_MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 \
+ (_MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 \
+ (_MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 \
+ (_MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT14__UART5_TXD \
+ (_MX6Q_PAD_CSI0_DAT14__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT14__UART5_RXD \
+ (_MX6Q_PAD_CSI0_DAT14__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 \
+ (_MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT14__GPIO_6_0 \
+ (_MX6Q_PAD_CSI0_DAT14__GPIO_6_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 \
+ (_MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 \
+ (_MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 \
+ (_MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 \
+ (_MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 \
+ (_MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT15__UART5_TXD \
+ (_MX6Q_PAD_CSI0_DAT15__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT15__UART5_RXD \
+ (_MX6Q_PAD_CSI0_DAT15__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 \
+ (_MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT15__GPIO_6_1 \
+ (_MX6Q_PAD_CSI0_DAT15__GPIO_6_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 \
+ (_MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 \
+ (_MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 \
+ (_MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 \
+ (_MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 \
+ (_MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT16__UART4_CTS \
+ (_MX6Q_PAD_CSI0_DAT16__UART4_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT16__UART4_RTS \
+ (_MX6Q_PAD_CSI0_DAT16__UART4_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 \
+ (_MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT16__GPIO_6_2 \
+ (_MX6Q_PAD_CSI0_DAT16__GPIO_6_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 \
+ (_MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 \
+ (_MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 \
+ (_MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 \
+ (_MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 \
+ (_MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT17__UART4_CTS \
+ (_MX6Q_PAD_CSI0_DAT17__UART4_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 \
+ (_MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT17__GPIO_6_3 \
+ (_MX6Q_PAD_CSI0_DAT17__GPIO_6_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 \
+ (_MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 \
+ (_MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 \
+ (_MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 \
+ (_MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 \
+ (_MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT18__UART5_CTS \
+ (_MX6Q_PAD_CSI0_DAT18__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT18__UART5_RTS \
+ (_MX6Q_PAD_CSI0_DAT18__UART5_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 \
+ (_MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT18__GPIO_6_4 \
+ (_MX6Q_PAD_CSI0_DAT18__GPIO_6_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 \
+ (_MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 \
+ (_MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 \
+ (_MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 \
+ (_MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 \
+ (_MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT19__UART5_CTS \
+ (_MX6Q_PAD_CSI0_DAT19__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 \
+ (_MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT19__GPIO_6_5 \
+ (_MX6Q_PAD_CSI0_DAT19__GPIO_6_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 \
+ (_MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 \
+ (_MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_JTAG_TMS__SJC_TMS \
+ (_MX6Q_PAD_JTAG_TMS__SJC_TMS | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_JTAG_MOD__SJC_MOD \
+ (_MX6Q_PAD_JTAG_MOD__SJC_MOD | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB \
+ (_MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_JTAG_TDI__SJC_TDI \
+ (_MX6Q_PAD_JTAG_TDI__SJC_TDI | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_JTAG_TCK__SJC_TCK \
+ (_MX6Q_PAD_JTAG_TCK__SJC_TCK | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_JTAG_TDO__SJC_TDO \
+ (_MX6Q_PAD_JTAG_TDO__SJC_TDO | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 \
+ (_MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 \
+ (_MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK \
+ (_MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 \
+ (_MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 \
+ (_MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 \
+ (_MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK \
+ (_MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 \
+ (_MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 \
+ (_MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 \
+ (_MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1 \
+ (_MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM \
+ (_MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ \
+ (_MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_POR_B__SRC_POR_B \
+ (_MX6Q_PAD_POR_B__SRC_POR_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 \
+ (_MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_RESET_IN_B__SRC_RESET_B \
+ (_MX6Q_PAD_RESET_IN_B__SRC_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 \
+ (_MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_TEST_MODE__TCU_TEST_MODE \
+ (_MX6Q_PAD_TEST_MODE__TCU_TEST_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD3_DAT7__USDHC3_DAT7_50MHZ \
+ (_MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT7__USDHC3_DAT7_100MHZ \
+ (_MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD3_DAT7__USDHC3_DAT7_200MHZ \
+ (_MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD3_DAT7__UART1_TXD \
+ (_MX6Q_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT7__UART1_RXD \
+ (_MX6Q_PAD_SD3_DAT7__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 \
+ (_MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 \
+ (_MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 \
+ (_MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT7__GPIO_6_17 \
+ (_MX6Q_PAD_SD3_DAT7__GPIO_6_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 \
+ (_MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV \
+ (_MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD3_DAT6__USDHC3_DAT6_50MHZ \
+ (_MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT6__USDHC3_DAT6_100MHZ \
+ (_MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD3_DAT6__USDHC3_DAT6_200MHZ \
+ (_MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD3_DAT6__UART1_TXD \
+ (_MX6Q_PAD_SD3_DAT6__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT6__UART1_RXD \
+ (_MX6Q_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 \
+ (_MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 \
+ (_MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 \
+ (_MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT6__GPIO_6_18 \
+ (_MX6Q_PAD_SD3_DAT6__GPIO_6_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 \
+ (_MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 \
+ (_MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD3_DAT5__USDHC3_DAT5_50MHZ \
+ (_MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT5__USDHC3_DAT5_100MHZ \
+ (_MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD3_DAT5__USDHC3_DAT5_200MHZ \
+ (_MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD3_DAT5__UART2_TXD \
+ (_MX6Q_PAD_SD3_DAT5__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT5__UART2_RXD \
+ (_MX6Q_PAD_SD3_DAT5__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 \
+ (_MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 \
+ (_MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 \
+ (_MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT5__GPIO_7_0 \
+ (_MX6Q_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 \
+ (_MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 \
+ (_MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD3_DAT4__USDHC3_DAT4_50MHZ \
+ (_MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT4__USDHC3_DAT4_100MHZ \
+ (_MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD3_DAT4__USDHC3_DAT4_200MHZ \
+ (_MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD3_DAT4__UART2_TXD \
+ (_MX6Q_PAD_SD3_DAT4__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT4__UART2_RXD \
+ (_MX6Q_PAD_SD3_DAT4__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 \
+ (_MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 \
+ (_MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 \
+ (_MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT4__GPIO_7_1 \
+ (_MX6Q_PAD_SD3_DAT4__GPIO_7_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 \
+ (_MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 \
+ (_MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD3_CMD__USDHC3_CMD_50MHZ \
+ (_MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD3_CMD__USDHC3_CMD_100MHZ \
+ (_MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD3_CMD__USDHC3_CMD_200MHZ \
+ (_MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD3_CMD__UART2_CTS \
+ (_MX6Q_PAD_SD3_CMD__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_CMD__CAN1_TXCAN \
+ (_MX6Q_PAD_SD3_CMD__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 \
+ (_MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 \
+ (_MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_CMD__GPIO_7_2 \
+ (_MX6Q_PAD_SD3_CMD__GPIO_7_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 \
+ (_MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 \
+ (_MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD3_CLK__USDHC3_CLK_50MHZ \
+ (_MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD3_CLK__USDHC3_CLK_100MHZ \
+ (_MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD3_CLK__USDHC3_CLK_200MHZ \
+ (_MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD3_CLK__UART2_CTS \
+ (_MX6Q_PAD_SD3_CLK__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_CLK__UART2_RTS \
+ (_MX6Q_PAD_SD3_CLK__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_CLK__CAN1_RXCAN \
+ (_MX6Q_PAD_SD3_CLK__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 \
+ (_MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 \
+ (_MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_CLK__GPIO_7_3 \
+ (_MX6Q_PAD_SD3_CLK__GPIO_7_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 \
+ (_MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 \
+ (_MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ \
+ (_MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_100MHZ \
+ (_MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_200MHZ \
+ (_MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD3_DAT0__UART1_CTS \
+ (_MX6Q_PAD_SD3_DAT0__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT0__CAN2_TXCAN \
+ (_MX6Q_PAD_SD3_DAT0__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 \
+ (_MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 \
+ (_MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT0__GPIO_7_4 \
+ (_MX6Q_PAD_SD3_DAT0__GPIO_7_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 \
+ (_MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 \
+ (_MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ \
+ (_MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_100MHZ \
+ (_MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_200MHZ \
+ (_MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD3_DAT1__UART1_CTS \
+ (_MX6Q_PAD_SD3_DAT1__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT1__UART1_RTS \
+ (_MX6Q_PAD_SD3_DAT1__UART1_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT1__CAN2_RXCAN \
+ (_MX6Q_PAD_SD3_DAT1__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 \
+ (_MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 \
+ (_MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT1__GPIO_7_5 \
+ (_MX6Q_PAD_SD3_DAT1__GPIO_7_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 \
+ (_MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 \
+ (_MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ \
+ (_MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_100MHZ \
+ (_MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_200MHZ \
+ (_MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 \
+ (_MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 \
+ (_MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 \
+ (_MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT2__GPIO_7_6 \
+ (_MX6Q_PAD_SD3_DAT2__GPIO_7_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 \
+ (_MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 \
+ (_MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ \
+ (_MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_100MHZ \
+ (_MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_200MHZ \
+ (_MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD3_DAT3__UART3_CTS \
+ (_MX6Q_PAD_SD3_DAT3__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 \
+ (_MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 \
+ (_MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 \
+ (_MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT3__GPIO_7_7 \
+ (_MX6Q_PAD_SD3_DAT3__GPIO_7_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 \
+ (_MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 \
+ (_MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD3_RST__USDHC3_RST \
+ (_MX6Q_PAD_SD3_RST__USDHC3_RST | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD3_RST__UART3_CTS \
+ (_MX6Q_PAD_SD3_RST__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_RST__UART3_RTS \
+ (_MX6Q_PAD_SD3_RST__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 \
+ (_MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 \
+ (_MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 \
+ (_MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_RST__GPIO_7_8 \
+ (_MX6Q_PAD_SD3_RST__GPIO_7_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 \
+ (_MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 \
+ (_MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_NANDF_CLE__RAWNAND_CLE \
+ (_MX6Q_PAD_NANDF_CLE__RAWNAND_CLE | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
+#define MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 \
+ (_MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 \
+ (_MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 \
+ (_MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 \
+ (_MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CLE__GPIO_6_7 \
+ (_MX6Q_PAD_NANDF_CLE__GPIO_6_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 \
+ (_MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 \
+ (_MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_NANDF_ALE__RAWNAND_ALE \
+ (_MX6Q_PAD_NANDF_ALE__RAWNAND_ALE | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
+#define MX6Q_PAD_NANDF_ALE__USDHC4_RST \
+ (_MX6Q_PAD_NANDF_ALE__USDHC4_RST | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 \
+ (_MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 \
+ (_MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 \
+ (_MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_ALE__GPIO_6_8 \
+ (_MX6Q_PAD_NANDF_ALE__GPIO_6_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 \
+ (_MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 \
+ (_MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN \
+ (_MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
+#define MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 \
+ (_MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 \
+ (_MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 \
+ (_MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 \
+ (_MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_WP_B__GPIO_6_9 \
+ (_MX6Q_PAD_NANDF_WP_B__GPIO_6_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 \
+ (_MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0 \
+ (_MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 \
+ (_MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL0))
+#define MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 \
+ (_MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 \
+ (_MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 \
+ (_MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 \
+ (_MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_RB0__GPIO_6_10 \
+ (_MX6Q_PAD_NANDF_RB0__GPIO_6_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 \
+ (_MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1 \
+ (_MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N \
+ (_MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
+#define MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 \
+ (_MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 \
+ (_MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CS0__GPIO_6_11 \
+ (_MX6Q_PAD_NANDF_CS0__GPIO_6_11 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2 \
+ (_MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N \
+ (_MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
+#define MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT \
+ (_MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT \
+ (_MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 \
+ (_MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CS1__GPIO_6_14 \
+ (_MX6Q_PAD_NANDF_CS1__GPIO_6_14 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT \
+ (_MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N \
+ (_MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
+#define MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 \
+ (_MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CS2__ESAI1_TX0 \
+ (_MX6Q_PAD_NANDF_CS2__ESAI1_TX0 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE \
+ (_MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CS2__CCM_CLKO2 \
+ (_MX6Q_PAD_NANDF_CS2__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CS2__GPIO_6_15 \
+ (_MX6Q_PAD_NANDF_CS2__GPIO_6_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 \
+ (_MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N \
+ (_MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
+#define MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 \
+ (_MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CS3__ESAI1_TX1 \
+ (_MX6Q_PAD_NANDF_CS3__ESAI1_TX1 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 \
+ (_MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 \
+ (_MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CS3__GPIO_6_16 \
+ (_MX6Q_PAD_NANDF_CS3__GPIO_6_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 \
+ (_MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CS3__TPSMP_CLK \
+ (_MX6Q_PAD_NANDF_CS3__TPSMP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD4_CMD__USDHC4_CMD_50MHZ \
+ (_MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD4_CMD__USDHC4_CMD_100MHZ \
+ (_MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD4_CMD__USDHC4_CMD_200MHZ \
+ (_MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD4_CMD__RAWNAND_RDN \
+ (_MX6Q_PAD_SD4_CMD__RAWNAND_RDN | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
+#define MX6Q_PAD_SD4_CMD__UART3_TXD \
+ (_MX6Q_PAD_SD4_CMD__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD4_CMD__UART3_RXD \
+ (_MX6Q_PAD_SD4_CMD__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 \
+ (_MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_CMD__GPIO_7_9 \
+ (_MX6Q_PAD_SD4_CMD__GPIO_7_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR \
+ (_MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD4_CLK__USDHC4_CLK_50MHZ \
+ (_MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD4_CLK__USDHC4_CLK_100MHZ \
+ (_MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD4_CLK__USDHC4_CLK_200MHZ \
+ (_MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD4_CLK__RAWNAND_WRN \
+ (_MX6Q_PAD_SD4_CLK__RAWNAND_WRN | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
+#define MX6Q_PAD_SD4_CLK__UART3_TXD \
+ (_MX6Q_PAD_SD4_CLK__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD4_CLK__UART3_RXD \
+ (_MX6Q_PAD_SD4_CLK__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 \
+ (_MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_CLK__GPIO_7_10 \
+ (_MX6Q_PAD_SD4_CLK__GPIO_7_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_NANDF_D0__RAWNAND_D0 \
+ (_MX6Q_PAD_NANDF_D0__RAWNAND_D0 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
+#define MX6Q_PAD_NANDF_D0__USDHC1_DAT4 \
+ (_MX6Q_PAD_NANDF_D0__USDHC1_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 \
+ (_MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 \
+ (_MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 \
+ (_MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D0__GPIO_2_0 \
+ (_MX6Q_PAD_NANDF_D0__GPIO_2_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 \
+ (_MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 \
+ (_MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_NANDF_D1__RAWNAND_D1 \
+ (_MX6Q_PAD_NANDF_D1__RAWNAND_D1 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
+#define MX6Q_PAD_NANDF_D1__USDHC1_DAT5 \
+ (_MX6Q_PAD_NANDF_D1__USDHC1_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 \
+ (_MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 \
+ (_MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 \
+ (_MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D1__GPIO_2_1 \
+ (_MX6Q_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 \
+ (_MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 \
+ (_MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_NANDF_D2__RAWNAND_D2 \
+ (_MX6Q_PAD_NANDF_D2__RAWNAND_D2 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
+#define MX6Q_PAD_NANDF_D2__USDHC1_DAT6 \
+ (_MX6Q_PAD_NANDF_D2__USDHC1_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 \
+ (_MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 \
+ (_MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 \
+ (_MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D2__GPIO_2_2 \
+ (_MX6Q_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 \
+ (_MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 \
+ (_MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_NANDF_D3__RAWNAND_D3 \
+ (_MX6Q_PAD_NANDF_D3__RAWNAND_D3 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
+#define MX6Q_PAD_NANDF_D3__USDHC1_DAT7 \
+ (_MX6Q_PAD_NANDF_D3__USDHC1_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 \
+ (_MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 \
+ (_MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 \
+ (_MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D3__GPIO_2_3 \
+ (_MX6Q_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 \
+ (_MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 \
+ (_MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_NANDF_D4__RAWNAND_D4 \
+ (_MX6Q_PAD_NANDF_D4__RAWNAND_D4 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
+#define MX6Q_PAD_NANDF_D4__USDHC2_DAT4 \
+ (_MX6Q_PAD_NANDF_D4__USDHC2_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 \
+ (_MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 \
+ (_MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 \
+ (_MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D4__GPIO_2_4 \
+ (_MX6Q_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 \
+ (_MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 \
+ (_MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_NANDF_D5__RAWNAND_D5 \
+ (_MX6Q_PAD_NANDF_D5__RAWNAND_D5 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
+#define MX6Q_PAD_NANDF_D5__USDHC2_DAT5 \
+ (_MX6Q_PAD_NANDF_D5__USDHC2_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 \
+ (_MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 \
+ (_MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 \
+ (_MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D5__GPIO_2_5 \
+ (_MX6Q_PAD_NANDF_D5__GPIO_2_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 \
+ (_MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 \
+ (_MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_NANDF_D6__RAWNAND_D6 \
+ (_MX6Q_PAD_NANDF_D6__RAWNAND_D6 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
+#define MX6Q_PAD_NANDF_D6__USDHC2_DAT6 \
+ (_MX6Q_PAD_NANDF_D6__USDHC2_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 \
+ (_MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 \
+ (_MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 \
+ (_MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D6__GPIO_2_6 \
+ (_MX6Q_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 \
+ (_MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 \
+ (_MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_NANDF_D7__RAWNAND_D7 \
+ (_MX6Q_PAD_NANDF_D7__RAWNAND_D7 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
+#define MX6Q_PAD_NANDF_D7__USDHC2_DAT7 \
+ (_MX6Q_PAD_NANDF_D7__USDHC2_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 \
+ (_MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 \
+ (_MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 \
+ (_MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D7__GPIO_2_7 \
+ (_MX6Q_PAD_NANDF_D7__GPIO_2_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 \
+ (_MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 \
+ (_MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD4_DAT0__RAWNAND_D8 \
+ (_MX6Q_PAD_SD4_DAT0__RAWNAND_D8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT0__USDHC4_DAT0_50MHZ \
+ (_MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT0__USDHC4_DAT0_100MHZ \
+ (_MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD4_DAT0__USDHC4_DAT0_200MHZ \
+ (_MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD4_DAT0__RAWNAND_DQS \
+ (_MX6Q_PAD_SD4_DAT0__RAWNAND_DQS | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL1))
+#define MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 \
+ (_MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 \
+ (_MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT0__GPIO_2_8 \
+ (_MX6Q_PAD_SD4_DAT0__GPIO_2_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 \
+ (_MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 \
+ (_MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD4_DAT1__RAWNAND_D9 \
+ (_MX6Q_PAD_SD4_DAT1__RAWNAND_D9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT1__USDHC4_DAT1_50MHZ \
+ (_MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT1__USDHC4_DAT1_100MHZ \
+ (_MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD4_DAT1__USDHC4_DAT1_200MHZ \
+ (_MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD4_DAT1__PWM3_PWMO \
+ (_MX6Q_PAD_SD4_DAT1__PWM3_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 \
+ (_MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 \
+ (_MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT1__GPIO_2_9 \
+ (_MX6Q_PAD_SD4_DAT1__GPIO_2_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 \
+ (_MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 \
+ (_MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD4_DAT2__RAWNAND_D10 \
+ (_MX6Q_PAD_SD4_DAT2__RAWNAND_D10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT2__USDHC4_DAT2_50MHZ \
+ (_MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT2__USDHC4_DAT2_100MHZ \
+ (_MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD4_DAT2__USDHC4_DAT2_200MHZ \
+ (_MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD4_DAT2__PWM4_PWMO \
+ (_MX6Q_PAD_SD4_DAT2__PWM4_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 \
+ (_MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 \
+ (_MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT2__GPIO_2_10 \
+ (_MX6Q_PAD_SD4_DAT2__GPIO_2_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 \
+ (_MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 \
+ (_MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD4_DAT3__RAWNAND_D11 \
+ (_MX6Q_PAD_SD4_DAT3__RAWNAND_D11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT3__USDHC4_DAT3_50MHZ \
+ (_MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT3__USDHC4_DAT3_100MHZ \
+ (_MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD4_DAT3__USDHC4_DAT3_200MHZ \
+ (_MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 \
+ (_MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 \
+ (_MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT3__GPIO_2_11 \
+ (_MX6Q_PAD_SD4_DAT3__GPIO_2_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 \
+ (_MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 \
+ (_MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD4_DAT4__RAWNAND_D12 \
+ (_MX6Q_PAD_SD4_DAT4__RAWNAND_D12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT4__USDHC4_DAT4_50MHZ \
+ (_MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT4__USDHC4_DAT4_100MHZ \
+ (_MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD4_DAT4__USDHC4_DAT4_200MHZ \
+ (_MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD4_DAT4__UART2_TXD \
+ (_MX6Q_PAD_SD4_DAT4__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT4__UART2_RXD \
+ (_MX6Q_PAD_SD4_DAT4__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 \
+ (_MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 \
+ (_MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT4__GPIO_2_12 \
+ (_MX6Q_PAD_SD4_DAT4__GPIO_2_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 \
+ (_MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 \
+ (_MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD4_DAT5__RAWNAND_D13 \
+ (_MX6Q_PAD_SD4_DAT5__RAWNAND_D13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT5__USDHC4_DAT5_50MHZ \
+ (_MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT5__USDHC4_DAT5_100MHZ \
+ (_MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD4_DAT5__USDHC4_DAT5_200MHZ \
+ (_MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD4_DAT5__UART2_CTS \
+ (_MX6Q_PAD_SD4_DAT5__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT5__UART2_RTS \
+ (_MX6Q_PAD_SD4_DAT5__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 \
+ (_MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 \
+ (_MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT5__GPIO_2_13 \
+ (_MX6Q_PAD_SD4_DAT5__GPIO_2_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 \
+ (_MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 \
+ (_MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD4_DAT6__RAWNAND_D14 \
+ (_MX6Q_PAD_SD4_DAT6__RAWNAND_D14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT6__USDHC4_DAT6_50MHZ \
+ (_MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT6__USDHC4_DAT6_100MHZ \
+ (_MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD4_DAT6__USDHC4_DAT6_200MHZ \
+ (_MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD4_DAT6__UART2_CTS \
+ (_MX6Q_PAD_SD4_DAT6__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 \
+ (_MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 \
+ (_MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT6__GPIO_2_14 \
+ (_MX6Q_PAD_SD4_DAT6__GPIO_2_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 \
+ (_MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 \
+ (_MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD4_DAT7__RAWNAND_D15 \
+ (_MX6Q_PAD_SD4_DAT7__RAWNAND_D15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT7__USDHC4_DAT7_50MHZ \
+ (_MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT7__USDHC4_DAT7_100MHZ \
+ (_MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD4_DAT7__USDHC4_DAT7_200MHZ \
+ (_MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD4_DAT7__UART2_TXD \
+ (_MX6Q_PAD_SD4_DAT7__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT7__UART2_RXD \
+ (_MX6Q_PAD_SD4_DAT7__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 \
+ (_MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 \
+ (_MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT7__GPIO_2_15 \
+ (_MX6Q_PAD_SD4_DAT7__GPIO_2_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 \
+ (_MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 \
+ (_MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 \
+ (_MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT1__USDHC1_DAT1_50MHZ_40OHM \
+ (_MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM))
+#define MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 \
+ (_MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT1__PWM3_PWMO \
+ (_MX6Q_PAD_SD1_DAT1__PWM3_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 \
+ (_MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 \
+ (_MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT1__GPIO_1_17 \
+ (_MX6Q_PAD_SD1_DAT1__GPIO_1_17 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
+#define MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 \
+ (_MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 \
+ (_MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 \
+ (_MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT0__USDHC1_DAT0_50MHZ_40OHM \
+ (_MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM))
+#define MX6Q_PAD_SD1_DAT0__ECSPI5_MISO \
+ (_MX6Q_PAD_SD1_DAT0__ECSPI5_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS \
+ (_MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 \
+ (_MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 \
+ (_MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT0__GPIO_1_16 \
+ (_MX6Q_PAD_SD1_DAT0__GPIO_1_16 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
+#define MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 \
+ (_MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 \
+ (_MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 \
+ (_MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT3__USDHC1_DAT3_50MHZ_40OHM \
+ (_MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM))
+#define MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 \
+ (_MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 \
+ (_MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT3__PWM1_PWMO \
+ (_MX6Q_PAD_SD1_DAT3__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B \
+ (_MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT3__GPIO_1_21 \
+ (_MX6Q_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB \
+ (_MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 \
+ (_MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD1_CMD__USDHC1_CMD \
+ (_MX6Q_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD1_CMD__USDHC1_CMD_50MHZ_40OHM \
+ (_MX6Q_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM))
+#define MX6Q_PAD_SD1_CMD__ECSPI5_MOSI \
+ (_MX6Q_PAD_SD1_CMD__ECSPI5_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_CMD__PWM4_PWMO \
+ (_MX6Q_PAD_SD1_CMD__PWM4_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 \
+ (_MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_CMD__GPIO_1_18 \
+ (_MX6Q_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 \
+ (_MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 \
+ (_MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT2__USDHC1_DAT2_50MHZ_40OHM \
+ (_MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM))
+#define MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 \
+ (_MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 \
+ (_MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT2__PWM2_PWMO \
+ (_MX6Q_PAD_SD1_DAT2__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B \
+ (_MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT2__GPIO_1_19 \
+ (_MX6Q_PAD_SD1_DAT2__GPIO_1_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB \
+ (_MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 \
+ (_MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD1_CLK__USDHC1_CLK \
+ (_MX6Q_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD1_CLK__USDHC1_CLK_50MHZ_40OHM \
+ (_MX6Q_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM))
+#define MX6Q_PAD_SD1_CLK__ECSPI5_SCLK \
+ (_MX6Q_PAD_SD1_CLK__ECSPI5_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT \
+ (_MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_CLK__GPT_CLKIN \
+ (_MX6Q_PAD_SD1_CLK__GPT_CLKIN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_CLK__GPIO_1_20 \
+ (_MX6Q_PAD_SD1_CLK__GPIO_1_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_CLK__PHY_DTB_0 \
+ (_MX6Q_PAD_SD1_CLK__PHY_DTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 \
+ (_MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD2_CLK__USDHC2_CLK \
+ (_MX6Q_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD2_CLK__USDHC2_CLK_50MHZ_40OHM \
+ (_MX6Q_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM))
+#define MX6Q_PAD_SD2_CLK__ECSPI5_SCLK \
+ (_MX6Q_PAD_SD2_CLK__ECSPI5_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_CLK__KPP_COL_5 \
+ (_MX6Q_PAD_SD2_CLK__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS \
+ (_MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 \
+ (_MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_CLK__GPIO_1_10 \
+ (_MX6Q_PAD_SD2_CLK__GPIO_1_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_CLK__PHY_DTB_1 \
+ (_MX6Q_PAD_SD2_CLK__PHY_DTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 \
+ (_MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD2_CMD__USDHC2_CMD \
+ (_MX6Q_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD2_CMD__USDHC2_CMD_50MHZ_40OHM \
+ (_MX6Q_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM))
+#define MX6Q_PAD_SD2_CMD__ECSPI5_MOSI \
+ (_MX6Q_PAD_SD2_CMD__ECSPI5_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_CMD__KPP_ROW_5 \
+ (_MX6Q_PAD_SD2_CMD__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC \
+ (_MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 \
+ (_MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_CMD__GPIO_1_11 \
+ (_MX6Q_PAD_SD2_CMD__GPIO_1_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 \
+ (_MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT3__USDHC2_DAT3_50MHZ_40OHM \
+ (_MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM))
+#define MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 \
+ (_MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT3__KPP_COL_6 \
+ (_MX6Q_PAD_SD2_DAT3__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC \
+ (_MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 \
+ (_MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT3__GPIO_1_12 \
+ (_MX6Q_PAD_SD2_DAT3__GPIO_1_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT3__SJC_DONE \
+ (_MX6Q_PAD_SD2_DAT3__SJC_DONE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 \
+ (_MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Auto Generate file, please don't edit it
+ *
+ */
+
+#ifndef __MACH_IOMUX_MX6SL_H__
+#define __MACH_IOMUX_MX6SL_H__
+
+#include <mach/iomux-v3.h>
+
+#define MX6SL_HIGH_DRV PAD_CTL_DSE_120ohm
+#define MX6SL_DISP_PAD_CLT MX6SL_HIGH_DRV
+
+#define MX6SL_CCM_CLKO_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define MX6SL_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define MX6SL_USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define MX6SL_USDHC_PAD_CTRL_100MHZ (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_34ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define MX6SL_USDHC_PAD_CTRL_200MHZ (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_HIGH | \
+ PAD_CTL_DSE_34ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define MX6SL_ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define MX6SL_I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \
+ PAD_CTL_HYS | PAD_CTL_ODE)
+
+#define MX6SL_ECSPI_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define MX6SL_USB_HSIC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define MX6SL_HP_DET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+#define MX6SL_LCDIF_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_PUE | PAD_CTL_PKE | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
+
+#define MX6SL_KEYPAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_120ohm)
+
+#define MX6SL_TSPAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_47K_UP)
+#define MX6SL_ADU_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_PUS_100K_DOWN | \
+ PAD_CTL_HYS | PAD_CTL_SPEED_MED)
+#define MX6SL_CHG_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_47K_UP)
+
+
+#define MX6SL_PAD_AUD_MCLK 0x02A4
+#define MX6SL_PAD_AUD_RXD 0x02AC
+#define MX6SL_PAD_AUD_TXC 0x02B4
+#define MX6SL_PAD_AUD_TXD 0x02B8
+#define MX6SL_PAD_AUD_TXFS 0x02BC
+#define MX6SL_PAD_HSIC_DAT 0x0444
+#define MX6SL_PAD_HSIC_STROBE 0x0448
+
+#define MX6SL_PAD_AUD_MCLK__AUDMUX_AUDIO_CLK_OUT \
+ IOMUX_PAD(0x02A4, 0x004C, 0, 0x0000, 0, MX6SL_ADU_PAD_CTRL)
+#define MX6SL_PAD_AUD_MCLK__PWM4_PWMO \
+ IOMUX_PAD(0x02A4, 0x004C, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY \
+ IOMUX_PAD(0x02A4, 0x004C, 2, 0x06B4, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_AUD_MCLK__FEC_MDC \
+ IOMUX_PAD(0x02A4, 0x004C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_AUD_MCLK__WDOG2_WDOG_RST_B_DEB \
+ IOMUX_PAD(0x02A4, 0x004C, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_AUD_MCLK__GPIO_1_6 \
+ IOMUX_PAD(0x02A4, 0x004C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_AUD_MCLK__SPDIF_SPDIF_EXT_CLK \
+ IOMUX_PAD(0x02A4, 0x004C, 6, 0x07F4, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_AUD_MCLK__TPSMP_HDATA_27 \
+ IOMUX_PAD(0x02A4, 0x004C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_AUD_RXC__AUDMUX_AUD3_RXC \
+ IOMUX_PAD(0x02A8, 0x0050, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_AUD_RXC__I2C1_SDA \
+ IOMUX_PAD(0x02A8, 0x0050, 1 | IOMUX_CONFIG_SION, 0x0720, 0, MX6SL_I2C_PAD_CTRL)
+#define MX6SL_PAD_AUD_RXC__UART3_TXD \
+ IOMUX_PAD(0x02A8, 0x0050, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_AUD_RXC__UART3_RXD \
+ IOMUX_PAD(0x02A8, 0x0050, 2, 0x080C, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_AUD_RXC__FEC_TX_CLK \
+ IOMUX_PAD(0x02A8, 0x0050, 3, 0x070C, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_AUD_RXC__I2C3_SDA \
+ IOMUX_PAD(0x02A8, 0x0050, 4 | IOMUX_CONFIG_SION, 0x0730, 0, MX6SL_I2C_PAD_CTRL)
+#define MX6SL_PAD_AUD_RXC__GPIO_1_1 \
+ IOMUX_PAD(0x02A8, 0x0050, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_AUD_RXC__ECSPI3_SS1 \
+ IOMUX_PAD(0x02A8, 0x0050, 6, 0x06C4, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_AUD_RXC__PL301_SIM_MX6SL_PER1_HREADYOUT \
+ IOMUX_PAD(0x02A8, 0x0050, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_AUD_RXD__AUDMUX_AUD3_RXD \
+ IOMUX_PAD(0x02AC, 0x0054, 0, 0x0000, 0, MX6SL_ADU_PAD_CTRL)
+#define MX6SL_PAD_AUD_RXD__ECSPI3_MOSI \
+ IOMUX_PAD(0x02AC, 0x0054, 1, 0x06BC, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_AUD_RXD__UART4_TXD \
+ IOMUX_PAD(0x02AC, 0x0054, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_AUD_RXD__UART4_RXD \
+ IOMUX_PAD(0x02AC, 0x0054, 2, 0x0814, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_AUD_RXD__FEC_RX_ER \
+ IOMUX_PAD(0x02AC, 0x0054, 3, 0x0708, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_AUD_RXD__USDHC1_LCTL \
+ IOMUX_PAD(0x02AC, 0x0054, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_AUD_RXD__GPIO_1_2 \
+ IOMUX_PAD(0x02AC, 0x0054, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_AUD_RXD__SRC_INT_BOOT \
+ IOMUX_PAD(0x02AC, 0x0054, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_AUD_RXD__PL301_SIM_MX6SL_PER1_HRESP \
+ IOMUX_PAD(0x02AC, 0x0054, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_AUD_RXFS__AUDMUX_AUD3_RXFS \
+ IOMUX_PAD(0x02B0, 0x0058, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_AUD_RXFS__I2C1_SCL \
+ IOMUX_PAD(0x02B0, 0x0058, 1 | IOMUX_CONFIG_SION, 0x071C, 0, MX6SL_I2C_PAD_CTRL)
+#define MX6SL_PAD_AUD_RXFS__UART3_TXD \
+ IOMUX_PAD(0x02B0, 0x0058, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_AUD_RXFS__UART3_RXD \
+ IOMUX_PAD(0x02B0, 0x0058, 2, 0x080C, 1, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_AUD_RXFS__FEC_MDIO \
+ IOMUX_PAD(0x02B0, 0x0058, 3, 0x06F4, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_AUD_RXFS__I2C3_SCL \
+ IOMUX_PAD(0x02B0, 0x0058, 4 | IOMUX_CONFIG_SION, 0x072C, 0, MX6SL_I2C_PAD_CTRL)
+#define MX6SL_PAD_AUD_RXFS__GPIO_1_0 \
+ IOMUX_PAD(0x02B0, 0x0058, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_AUD_RXFS__ECSPI3_SS0 \
+ IOMUX_PAD(0x02B0, 0x0058, 6, 0x06C0, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_AUD_RXFS__PL301_SIM_MX6SL_PER1_HPROT_1 \
+ IOMUX_PAD(0x02B0, 0x0058, 7, 0x07EC, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_AUD_TXC__AUDMUX_AUD3_TXC \
+ IOMUX_PAD(0x02B4, 0x005C, 0, 0x0000, 0, MX6SL_ADU_PAD_CTRL)
+#define MX6SL_PAD_AUD_TXC__ECSPI3_MISO \
+ IOMUX_PAD(0x02B4, 0x005C, 1, 0x06B8, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_AUD_TXC__UART4_TXD \
+ IOMUX_PAD(0x02B4, 0x005C, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_AUD_TXC__UART4_RXD \
+ IOMUX_PAD(0x02B4, 0x005C, 2, 0x0814, 1, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_AUD_TXC__FEC_RX_DV \
+ IOMUX_PAD(0x02B4, 0x005C, 3, 0x0704, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_AUD_TXC__USDHC2_LCTL \
+ IOMUX_PAD(0x02B4, 0x005C, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_AUD_TXC__GPIO_1_3 \
+ IOMUX_PAD(0x02B4, 0x005C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_AUD_TXC__SRC_SYSTEM_RST \
+ IOMUX_PAD(0x02B4, 0x005C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_AUD_TXC__TPSMP_HDATA_24 \
+ IOMUX_PAD(0x02B4, 0x005C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_AUD_TXD__AUDMUX_AUD3_TXD \
+ IOMUX_PAD(0x02B8, 0x0060, 0, 0x0000, 0, MX6SL_ADU_PAD_CTRL)
+#define MX6SL_PAD_AUD_TXD__ECSPI3_SCLK \
+ IOMUX_PAD(0x02B8, 0x0060, 1, 0x06B0, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_AUD_TXD__UART4_CTS \
+ IOMUX_PAD(0x02B8, 0x0060, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_AUD_TXD__UART4_RTS \
+ IOMUX_PAD(0x02B8, 0x0060, 2, 0x0810, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_AUD_TXD__FEC_TDATA_0 \
+ IOMUX_PAD(0x02B8, 0x0060, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_AUD_TXD__USDHC4_LCTL \
+ IOMUX_PAD(0x02B8, 0x0060, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_AUD_TXD__GPIO_1_5 \
+ IOMUX_PAD(0x02B8, 0x0060, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_AUD_TXD__ANATOP_ANATOP_TESTI_1 \
+ IOMUX_PAD(0x02B8, 0x0060, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_AUD_TXD__TPSMP_HDATA_26 \
+ IOMUX_PAD(0x02B8, 0x0060, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_AUD_TXFS__AUDMUX_AUD3_TXFS \
+ IOMUX_PAD(0x02BC, 0x0064, 0, 0x0000, 0, MX6SL_ADU_PAD_CTRL)
+#define MX6SL_PAD_AUD_TXFS__PWM3_PWMO \
+ IOMUX_PAD(0x02BC, 0x0064, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_AUD_TXFS__UART4_CTS \
+ IOMUX_PAD(0x02BC, 0x0064, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_AUD_TXFS__UART4_RTS \
+ IOMUX_PAD(0x02BC, 0x0064, 2, 0x0810, 1, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_AUD_TXFS__FEC_RDATA_1 \
+ IOMUX_PAD(0x02BC, 0x0064, 3, 0x06FC, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_AUD_TXFS__USDHC3_LCTL \
+ IOMUX_PAD(0x02BC, 0x0064, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_AUD_TXFS__GPIO_1_4 \
+ IOMUX_PAD(0x02BC, 0x0064, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_AUD_TXFS__ANATOP_ANATOP_TESTI_0 \
+ IOMUX_PAD(0x02BC, 0x0064, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_AUD_TXFS__TPSMP_HDATA_25 \
+ IOMUX_PAD(0x02BC, 0x0064, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_A0__MMDC_DRAM_A_0 \
+ IOMUX_PAD(0x02C0, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_A1__MMDC_DRAM_A_1 \
+ IOMUX_PAD(0x02C4, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_A10__MMDC_DRAM_A_10 \
+ IOMUX_PAD(0x02C8, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_A11__MMDC_DRAM_A_11 \
+ IOMUX_PAD(0x02CC, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_A12__MMDC_DRAM_A_12 \
+ IOMUX_PAD(0x02D0, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_A13__MMDC_DRAM_A_13 \
+ IOMUX_PAD(0x02D4, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_A14__MMDC_DRAM_A_14 \
+ IOMUX_PAD(0x02D8, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_A15__MMDC_DRAM_A_15 \
+ IOMUX_PAD(0x02DC, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_A2__MMDC_DRAM_A_2 \
+ IOMUX_PAD(0x02E0, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_A3__MMDC_DRAM_A_3 \
+ IOMUX_PAD(0x02E4, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_A4__MMDC_DRAM_A_4 \
+ IOMUX_PAD(0x02E8, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_A5__MMDC_DRAM_A_5 \
+ IOMUX_PAD(0x02EC, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_A6__MMDC_DRAM_A_6 \
+ IOMUX_PAD(0x02F0, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_A7__MMDC_DRAM_A_7 \
+ IOMUX_PAD(0x02F4, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_A8__MMDC_DRAM_A_8 \
+ IOMUX_PAD(0x02F8, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_A9__MMDC_DRAM_A_9 \
+ IOMUX_PAD(0x02FC, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_CAS__MMDC_DRAM_CAS \
+ IOMUX_PAD(0x0300, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_CS0__MMDC_DRAM_CS_0 \
+ IOMUX_PAD(0x0304, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_CS1__MMDC_DRAM_CS_1 \
+ IOMUX_PAD(0x0308, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_D0__MMDC_DRAM_D_0 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_D1__MMDC_DRAM_D_1 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_D10__MMDC_DRAM_D_10 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_D11__MMDC_DRAM_D_11 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_D12__MMDC_DRAM_D_12 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_D13__MMDC_DRAM_D_13 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_D14__MMDC_DRAM_D_14 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_D15__MMDC_DRAM_D_15 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_D16__MMDC_DRAM_D_16 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_D17__MMDC_DRAM_D_17 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_D18__MMDC_DRAM_D_18 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_D19__MMDC_DRAM_D_19 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_D2__MMDC_DRAM_D_2 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_D20__MMDC_DRAM_D_20 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_D21__MMDC_DRAM_D_21 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_D22__MMDC_DRAM_D_22 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_D23__MMDC_DRAM_D_23 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_D24__MMDC_DRAM_D_24 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_D25__MMDC_DRAM_D_25 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_D26__MMDC_DRAM_D_26 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_D27__MMDC_DRAM_D_27 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_D28__MMDC_DRAM_D_28 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_D29__MMDC_DRAM_D_29 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_D3__MMDC_DRAM_D_3 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_D30__MMDC_DRAM_D_30 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_D31__MMDC_DRAM_D_31 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_D4__MMDC_DRAM_D_4 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_D5__MMDC_DRAM_D_5 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_D6__MMDC_DRAM_D_6 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_D7__MMDC_DRAM_D_7 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_D8__MMDC_DRAM_D_8 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_D9__MMDC_DRAM_D_9 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 \
+ IOMUX_PAD(0x030C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 \
+ IOMUX_PAD(0x0310, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 \
+ IOMUX_PAD(0x0314, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 \
+ IOMUX_PAD(0x0318, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_RAS__MMDC_DRAM_RAS \
+ IOMUX_PAD(0x031C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_RESET__MMDC_DRAM_RESET \
+ IOMUX_PAD(0x0320, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 \
+ IOMUX_PAD(0x0324, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 \
+ IOMUX_PAD(0x0328, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 \
+ IOMUX_PAD(0x032C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 \
+ IOMUX_PAD(0x0330, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 \
+ IOMUX_PAD(0x0334, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 \
+ IOMUX_PAD(0x0338, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 \
+ IOMUX_PAD(0x033C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 \
+ IOMUX_PAD(0x0340, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 \
+ IOMUX_PAD(0x0344, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 \
+ IOMUX_PAD(0x0348, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 \
+ IOMUX_PAD(0x034C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 \
+ IOMUX_PAD(0x0350, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_DRAM_SDWE__MMDC_DRAM_SDWE \
+ IOMUX_PAD(0x0354, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO \
+ IOMUX_PAD(0x0358, 0x0068, 0, 0x0684, 0, MX6SL_ECSPI_PAD_CTRL)
+#define MX6SL_PAD_ECSPI1_MISO__AUDMUX_AUD4_TXFS \
+ IOMUX_PAD(0x0358, 0x0068, 1, 0x05F8, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_ECSPI1_MISO__UART5_CTS \
+ IOMUX_PAD(0x0358, 0x0068, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_ECSPI1_MISO__UART5_RTS \
+ IOMUX_PAD(0x0358, 0x0068, 2, 0x0818, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_ECSPI1_MISO__EPDC_BDR_0 \
+ IOMUX_PAD(0x0358, 0x0068, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_ECSPI1_MISO__USDHC2_WP \
+ IOMUX_PAD(0x0358, 0x0068, 4, 0x0834, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_ECSPI1_MISO__GPIO_4_10 \
+ IOMUX_PAD(0x0358, 0x0068, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_ECSPI1_MISO__CCM_PLL3_BYP \
+ IOMUX_PAD(0x0358, 0x0068, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_ECSPI1_MISO__MMDC_MMDC_DEBUG_40 \
+ IOMUX_PAD(0x0358, 0x0068, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI \
+ IOMUX_PAD(0x035C, 0x006C, 0, 0x0688, 0, MX6SL_ECSPI_PAD_CTRL)
+#define MX6SL_PAD_ECSPI1_MOSI__AUDMUX_AUD4_TXC \
+ IOMUX_PAD(0x035C, 0x006C, 1, 0x05F4, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_ECSPI1_MOSI__UART5_TXD \
+ IOMUX_PAD(0x035C, 0x006C, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_ECSPI1_MOSI__UART5_RXD \
+ IOMUX_PAD(0x035C, 0x006C, 2, 0x081C, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_ECSPI1_MOSI__EPDC_VCOM_1 \
+ IOMUX_PAD(0x035C, 0x006C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_ECSPI1_MOSI__USDHC2_VSELECT \
+ IOMUX_PAD(0x035C, 0x006C, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_ECSPI1_MOSI__GPIO_4_9 \
+ IOMUX_PAD(0x035C, 0x006C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_ECSPI1_MOSI__CCM_PLL2_BYP \
+ IOMUX_PAD(0x035C, 0x006C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_ECSPI1_MOSI__MMDC_MMDC_DEBUG_49 \
+ IOMUX_PAD(0x035C, 0x006C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK \
+ IOMUX_PAD(0x0360, 0x0070, 0, 0x067C, 0, MX6SL_ECSPI_PAD_CTRL)
+#define MX6SL_PAD_ECSPI1_SCLK__AUDMUX_AUD4_TXD \
+ IOMUX_PAD(0x0360, 0x0070, 1, 0x05E8, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_ECSPI1_SCLK__UART5_TXD \
+ IOMUX_PAD(0x0360, 0x0070, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_ECSPI1_SCLK__UART5_RXD \
+ IOMUX_PAD(0x0360, 0x0070, 2, 0x081C, 1, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_ECSPI1_SCLK__EPDC_VCOM_0 \
+ IOMUX_PAD(0x0360, 0x0070, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_ECSPI1_SCLK__USDHC2_RST \
+ IOMUX_PAD(0x0360, 0x0070, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_ECSPI1_SCLK__GPIO_4_8 \
+ IOMUX_PAD(0x0360, 0x0070, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_ECSPI1_SCLK__USB_USBOTG2_OC \
+ IOMUX_PAD(0x0360, 0x0070, 6, 0x0820, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_ECSPI1_SCLK__TPSMP_HDATA_18 \
+ IOMUX_PAD(0x0360, 0x0070, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_ECSPI1_SS0__ECSPI1_SS0 \
+ IOMUX_PAD(0x0364, 0x0074, 0, 0x068C, 0, MX6SL_ECSPI_PAD_CTRL)
+#define MX6SL_PAD_ECSPI1_SS0__AUDMUX_AUD4_RXD \
+ IOMUX_PAD(0x0364, 0x0074, 1, 0x05E4, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_ECSPI1_SS0__UART5_CTS \
+ IOMUX_PAD(0x0364, 0x0074, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_ECSPI1_SS0__UART5_RTS \
+ IOMUX_PAD(0x0364, 0x0074, 2, 0x0818, 1, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_ECSPI1_SS0__EPDC_BDR_1 \
+ IOMUX_PAD(0x0364, 0x0074, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_ECSPI1_SS0__USDHC2_CD \
+ IOMUX_PAD(0x0364, 0x0074, 4, 0x0830, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_ECSPI1_SS0__GPIO_4_11 \
+ IOMUX_PAD(0x0364, 0x0074, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_ECSPI1_SS0__USB_USBOTG2_PWR \
+ IOMUX_PAD(0x0364, 0x0074, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_ECSPI1_SS0__PL301_SIM_MX6SL_PER1_HADDR_23 \
+ IOMUX_PAD(0x0364, 0x0074, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_ECSPI2_MISO__GPIO_4_14 \
+ IOMUX_PAD(0x0368, 0x0078, 5, 0x0000, 0, MX6SL_CHG_PAD_CTRL)
+#define MX6SL_PAD_ECSPI2_MISO__USB_USBOTG1_OC \
+ IOMUX_PAD(0x0368, 0x0078, 6, 0x0824, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_ECSPI2_MISO__TPSMP_HDATA_23 \
+ IOMUX_PAD(0x0368, 0x0078, 7, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_ECSPI2_MISO__ECSPI2_MISO \
+ IOMUX_PAD(0x0368, 0x0078, 0, 0x06A0, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_ECSPI2_MISO__SDMA_SDMA_EXT_EVENT_0 \
+ IOMUX_PAD(0x0368, 0x0078, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_ECSPI2_MISO__UART3_CTS \
+ IOMUX_PAD(0x0368, 0x0078, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_ECSPI2_MISO__UART3_RTS \
+ IOMUX_PAD(0x0368, 0x0078, 2, 0x0808, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_ECSPI2_MISO__CSI_MCLK \
+ IOMUX_PAD(0x0368, 0x0078, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_ECSPI2_MISO__USDHC1_WP \
+ IOMUX_PAD(0x0368, 0x0078, 4, 0x082C, 0, MX6SL_USDHC_PAD_CTRL)
+
+#define MX6SL_PAD_ECSPI2_MOSI__ECSPI2_MOSI \
+ IOMUX_PAD(0x036C, 0x007C, 0, 0x06A4, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_ECSPI2_MOSI__SDMA_SDMA_EXT_EVENT_1 \
+ IOMUX_PAD(0x036C, 0x007C, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_ECSPI2_MOSI__UART3_TXD \
+ IOMUX_PAD(0x036C, 0x007C, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_ECSPI2_MOSI__UART3_RXD \
+ IOMUX_PAD(0x036C, 0x007C, 2, 0x080C, 2, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_ECSPI2_MOSI__CSI_HSYNC \
+ IOMUX_PAD(0x036C, 0x007C, 3, 0x0670, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_ECSPI2_MOSI__USDHC1_VSELECT \
+ IOMUX_PAD(0x036C, 0x007C, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_ECSPI2_MOSI__GPIO_4_13 \
+ IOMUX_PAD(0x036C, 0x007C, 5, 0x0000, 0, MX6SL_CHG_PAD_CTRL)
+#define MX6SL_PAD_ECSPI2_MOSI__ANATOP_ANATOP_TESTO_1 \
+ IOMUX_PAD(0x036C, 0x007C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_ECSPI2_MOSI__TPSMP_HDATA_22 \
+ IOMUX_PAD(0x036C, 0x007C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_ECSPI2_SCLK__ECSPI2_SCLK \
+ IOMUX_PAD(0x0370, 0x0080, 0, 0x069C, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_ECSPI2_SCLK__SPDIF_SPDIF_EXT_CLK \
+ IOMUX_PAD(0x0370, 0x0080, 1, 0x07F4, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_ECSPI2_SCLK__UART3_TXD \
+ IOMUX_PAD(0x0370, 0x0080, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_ECSPI2_SCLK__UART3_RXD \
+ IOMUX_PAD(0x0370, 0x0080, 2, 0x080C, 3, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_ECSPI2_SCLK__CSI_PIXCLK \
+ IOMUX_PAD(0x0370, 0x0080, 3, 0x0674, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_ECSPI2_SCLK__USDHC1_RST \
+ IOMUX_PAD(0x0370, 0x0080, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_ECSPI2_SCLK__GPIO_4_12 \
+ IOMUX_PAD(0x0370, 0x0080, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_ECSPI2_SCLK__USB_USBOTG2_OC \
+ IOMUX_PAD(0x0370, 0x0080, 6, 0x0820, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_ECSPI2_SCLK__TPSMP_HDATA_21 \
+ IOMUX_PAD(0x0370, 0x0080, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_ECSPI2_SS0__ECSPI2_SS0 \
+ IOMUX_PAD(0x0374, 0x0084, 0, 0x06A8, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_ECSPI2_SS0__ECSPI1_SS3 \
+ IOMUX_PAD(0x0374, 0x0084, 1, 0x0698, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_ECSPI2_SS0__UART3_CTS \
+ IOMUX_PAD(0x0374, 0x0084, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_ECSPI2_SS0__UART3_RTS \
+ IOMUX_PAD(0x0374, 0x0084, 2, 0x0808, 1, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_ECSPI2_SS0__CSI_VSYNC \
+ IOMUX_PAD(0x0374, 0x0084, 3, 0x0678, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_ECSPI2_SS0__USDHC1_CD \
+ IOMUX_PAD(0x0374, 0x0084, 4, 0x0828, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_ECSPI2_SS0__GPIO_4_15 \
+ IOMUX_PAD(0x0374, 0x0084, 5, 0x0000, 0, MX6SL_CHG_PAD_CTRL)
+#define MX6SL_PAD_ECSPI2_SS0__USB_USBOTG1_PWR \
+ IOMUX_PAD(0x0374, 0x0084, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_ECSPI2_SS0__PL301_SIM_MX6SL_PER1_HADDR_24 \
+ IOMUX_PAD(0x0374, 0x0084, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_BDR0__EPDC_BDR_0 \
+ IOMUX_PAD(0x0378, 0x0088, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_BDR0__USDHC4_CLK \
+ IOMUX_PAD(0x0378, 0x0088, 1, 0x0850, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_EPDC_BDR0__UART3_CTS \
+ IOMUX_PAD(0x0378, 0x0088, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_EPDC_BDR0__UART3_RTS \
+ IOMUX_PAD(0x0378, 0x0088, 2, 0x0808, 2, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_EPDC_BDR0__WEIM_WEIM_A_26 \
+ IOMUX_PAD(0x0378, 0x0088, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_BDR0__TCON_RL \
+ IOMUX_PAD(0x0378, 0x0088, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_BDR0__GPIO_2_5 \
+ IOMUX_PAD(0x0378, 0x0088, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_BDR0__EPDC_SDCE_7 \
+ IOMUX_PAD(0x0378, 0x0088, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_BDR0__MMDC_MMDC_DEBUG_9 \
+ IOMUX_PAD(0x0378, 0x0088, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_BDR1__EPDC_BDR_1 \
+ IOMUX_PAD(0x037C, 0x008C, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_BDR1__USDHC4_CMD \
+ IOMUX_PAD(0x037C, 0x008C, 1, 0x0858, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_EPDC_BDR1__UART3_CTS \
+ IOMUX_PAD(0x037C, 0x008C, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_EPDC_BDR1__UART3_RTS \
+ IOMUX_PAD(0x037C, 0x008C, 2, 0x0808, 3, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_EPDC_BDR1__WEIM_WEIM_CRE \
+ IOMUX_PAD(0x037C, 0x008C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_BDR1__TCON_UD \
+ IOMUX_PAD(0x037C, 0x008C, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_BDR1__GPIO_2_6 \
+ IOMUX_PAD(0x037C, 0x008C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_BDR1__EPDC_SDCE_8 \
+ IOMUX_PAD(0x037C, 0x008C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_BDR1__MMDC_MMDC_DEBUG_8 \
+ IOMUX_PAD(0x037C, 0x008C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_D0__EPDC_SDDO_0 \
+ IOMUX_PAD(0x0380, 0x0090, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D0__ECSPI4_MOSI \
+ IOMUX_PAD(0x0380, 0x0090, 1, 0x06D8, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D0__LCDIF_DAT_24 \
+ IOMUX_PAD(0x0380, 0x0090, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D0__CSI_D_0 \
+ IOMUX_PAD(0x0380, 0x0090, 3, 0x0630, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D0__TCON_E_DATA_0 \
+ IOMUX_PAD(0x0380, 0x0090, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D0__GPIO_1_7 \
+ IOMUX_PAD(0x0380, 0x0090, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D0__ANATOP_USBPHY1_TSTI_TX_HS_MODE \
+ IOMUX_PAD(0x0380, 0x0090, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D0__OBSERVE_MUX_OUT_0 \
+ IOMUX_PAD(0x0380, 0x0090, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_D1__EPDC_SDDO_1 \
+ IOMUX_PAD(0x0384, 0x0094, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D1__ECSPI4_MISO \
+ IOMUX_PAD(0x0384, 0x0094, 1, 0x06D4, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D1__LCDIF_DAT_25 \
+ IOMUX_PAD(0x0384, 0x0094, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D1__CSI_D_1 \
+ IOMUX_PAD(0x0384, 0x0094, 3, 0x0634, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D1__TCON_E_DATA_1 \
+ IOMUX_PAD(0x0384, 0x0094, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D1__GPIO_1_8 \
+ IOMUX_PAD(0x0384, 0x0094, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D1__ANATOP_USBPHY1_TSTI_TX_LS_MODE \
+ IOMUX_PAD(0x0384, 0x0094, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D1__OBSERVE_MUX_OUT_1 \
+ IOMUX_PAD(0x0384, 0x0094, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_D10__EPDC_SDDO_10 \
+ IOMUX_PAD(0x0388, 0x0098, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D10__ECSPI3_SS0 \
+ IOMUX_PAD(0x0388, 0x0098, 1, 0x06C0, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D10__EPDC_PWRCTRL_2 \
+ IOMUX_PAD(0x0388, 0x0098, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D10__WEIM_WEIM_A_18 \
+ IOMUX_PAD(0x0388, 0x0098, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D10__TCON_E_DATA_10 \
+ IOMUX_PAD(0x0388, 0x0098, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D10__GPIO_1_17 \
+ IOMUX_PAD(0x0388, 0x0098, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D10__USDHC4_WP \
+ IOMUX_PAD(0x0388, 0x0098, 6, 0x087C, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D10__MMDC_MMDC_DEBUG_29 \
+ IOMUX_PAD(0x0388, 0x0098, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_D11__EPDC_SDDO_11 \
+ IOMUX_PAD(0x038C, 0x009C, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D11__ECSPI3_SCLK \
+ IOMUX_PAD(0x038C, 0x009C, 1, 0x06B0, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D11__EPDC_PWRCTRL_3 \
+ IOMUX_PAD(0x038C, 0x009C, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D11__WEIM_WEIM_A_19 \
+ IOMUX_PAD(0x038C, 0x009C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D11__TCON_E_DATA_11 \
+ IOMUX_PAD(0x038C, 0x009C, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D11__GPIO_1_18 \
+ IOMUX_PAD(0x038C, 0x009C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D11__USDHC4_CD \
+ IOMUX_PAD(0x038C, 0x009C, 6, 0x0854, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D11__MMDC_MMDC_DEBUG_28 \
+ IOMUX_PAD(0x038C, 0x009C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_D12__EPDC_SDDO_12 \
+ IOMUX_PAD(0x0390, 0x00A0, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D12__UART2_TXD \
+ IOMUX_PAD(0x0390, 0x00A0, 1, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D12__UART2_RXD \
+ IOMUX_PAD(0x0390, 0x00A0, 1, 0x0804, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D12__EPDC_PWRCOM \
+ IOMUX_PAD(0x0390, 0x00A0, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D12__WEIM_WEIM_A_20 \
+ IOMUX_PAD(0x0390, 0x00A0, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D12__TCON_E_DATA_12 \
+ IOMUX_PAD(0x0390, 0x00A0, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D12__GPIO_1_19 \
+ IOMUX_PAD(0x0390, 0x00A0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D12__ECSPI3_SS1 \
+ IOMUX_PAD(0x0390, 0x00A0, 6, 0x06C4, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D12__MMDC_MMDC_DEBUG_27 \
+ IOMUX_PAD(0x0390, 0x00A0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_D13__EPDC_SDDO_13 \
+ IOMUX_PAD(0x0394, 0x00A4, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D13__UART2_TXD \
+ IOMUX_PAD(0x0394, 0x00A4, 1, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D13__UART2_RXD \
+ IOMUX_PAD(0x0394, 0x00A4, 1, 0x0804, 1, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D13__EPDC_PWRIRQ \
+ IOMUX_PAD(0x0394, 0x00A4, 2, 0x06E8, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D13__WEIM_WEIM_A_21 \
+ IOMUX_PAD(0x0394, 0x00A4, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D13__TCON_E_DATA_13 \
+ IOMUX_PAD(0x0394, 0x00A4, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D13__GPIO_1_20 \
+ IOMUX_PAD(0x0394, 0x00A4, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D13__ECSPI3_SS2 \
+ IOMUX_PAD(0x0394, 0x00A4, 6, 0x06C8, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D13__MMDC_MMDC_DEBUG_26 \
+ IOMUX_PAD(0x0394, 0x00A4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_D14__EPDC_SDDO_14 \
+ IOMUX_PAD(0x0398, 0x00A8, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D14__UART2_CTS \
+ IOMUX_PAD(0x0398, 0x00A8, 1, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D14__UART2_RTS \
+ IOMUX_PAD(0x0398, 0x00A8, 1, 0x0800, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D14__EPDC_PWRSTAT \
+ IOMUX_PAD(0x0398, 0x00A8, 2, 0x06EC, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D14__WEIM_WEIM_A_22 \
+ IOMUX_PAD(0x0398, 0x00A8, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D14__TCON_E_DATA_14 \
+ IOMUX_PAD(0x0398, 0x00A8, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D14__GPIO_1_21 \
+ IOMUX_PAD(0x0398, 0x00A8, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D14__ECSPI3_SS3 \
+ IOMUX_PAD(0x0398, 0x00A8, 6, 0x06CC, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D14__MMDC_MMDC_DEBUG_25 \
+ IOMUX_PAD(0x0398, 0x00A8, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_D15__EPDC_SDDO_15 \
+ IOMUX_PAD(0x039C, 0x00AC, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D15__UART2_CTS \
+ IOMUX_PAD(0x039C, 0x00AC, 1, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D15__UART2_RTS \
+ IOMUX_PAD(0x039C, 0x00AC, 1, 0x0800, 1, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D15__EPDC_PWRWAKE \
+ IOMUX_PAD(0x039C, 0x00AC, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D15__WEIM_WEIM_A_23 \
+ IOMUX_PAD(0x039C, 0x00AC, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D15__TCON_E_DATA_15 \
+ IOMUX_PAD(0x039C, 0x00AC, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D15__GPIO_1_22 \
+ IOMUX_PAD(0x039C, 0x00AC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D15__ECSPI3_RDY \
+ IOMUX_PAD(0x039C, 0x00AC, 6, 0x06B4, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D15__MMDC_MMDC_DEBUG_24 \
+ IOMUX_PAD(0x039C, 0x00AC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_D2__EPDC_SDDO_2 \
+ IOMUX_PAD(0x03A0, 0x00B0, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D2__ECSPI4_SS0 \
+ IOMUX_PAD(0x03A0, 0x00B0, 1, 0x06DC, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D2__LCDIF_DAT_26 \
+ IOMUX_PAD(0x03A0, 0x00B0, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D2__CSI_D_2 \
+ IOMUX_PAD(0x03A0, 0x00B0, 3, 0x0638, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D2__TCON_E_DATA_2 \
+ IOMUX_PAD(0x03A0, 0x00B0, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D2__GPIO_1_9 \
+ IOMUX_PAD(0x03A0, 0x00B0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D2__ANATOP_USBPHY1_TSTI_TX_DN \
+ IOMUX_PAD(0x03A0, 0x00B0, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D2__TPSMP_HDATA_28 \
+ IOMUX_PAD(0x03A0, 0x00B0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_D3__EPDC_SDDO_3 \
+ IOMUX_PAD(0x03A4, 0x00B4, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D3__ECSPI4_SCLK \
+ IOMUX_PAD(0x03A4, 0x00B4, 1, 0x06D0, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D3__LCDIF_DAT_27 \
+ IOMUX_PAD(0x03A4, 0x00B4, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D3__CSI_D_3 \
+ IOMUX_PAD(0x03A4, 0x00B4, 3, 0x063C, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D3__TCON_E_DATA_3 \
+ IOMUX_PAD(0x03A4, 0x00B4, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D3__GPIO_1_10 \
+ IOMUX_PAD(0x03A4, 0x00B4, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D3__ANATOP_USBPHY1_TSTI_TX_DP \
+ IOMUX_PAD(0x03A4, 0x00B4, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D3__TPSMP_HDATA_29 \
+ IOMUX_PAD(0x03A4, 0x00B4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_D4__EPDC_SDDO_4 \
+ IOMUX_PAD(0x03A8, 0x00B8, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D4__ECSPI4_SS1 \
+ IOMUX_PAD(0x03A8, 0x00B8, 1, 0x06E0, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D4__LCDIF_DAT_28 \
+ IOMUX_PAD(0x03A8, 0x00B8, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D4__CSI_D_4 \
+ IOMUX_PAD(0x03A8, 0x00B8, 3, 0x0640, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D4__TCON_E_DATA_4 \
+ IOMUX_PAD(0x03A8, 0x00B8, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D4__GPIO_1_11 \
+ IOMUX_PAD(0x03A8, 0x00B8, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D4__ANATOP_USBPHY1_TSTI_TX_EN \
+ IOMUX_PAD(0x03A8, 0x00B8, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D4__TPSMP_HDATA_30 \
+ IOMUX_PAD(0x03A8, 0x00B8, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_D5__EPDC_SDDO_5 \
+ IOMUX_PAD(0x03AC, 0x00BC, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D5__ECSPI4_SS2 \
+ IOMUX_PAD(0x03AC, 0x00BC, 1, 0x06E4, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D5__LCDIF_DAT_29 \
+ IOMUX_PAD(0x03AC, 0x00BC, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D5__CSI_D_5 \
+ IOMUX_PAD(0x03AC, 0x00BC, 3, 0x0644, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D5__TCON_E_DATA_5 \
+ IOMUX_PAD(0x03AC, 0x00BC, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D5__GPIO_1_12 \
+ IOMUX_PAD(0x03AC, 0x00BC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D5__ANATOP_USBPHY1_TSTI_TX_HIZ \
+ IOMUX_PAD(0x03AC, 0x00BC, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D5__TPSMP_HDATA_31 \
+ IOMUX_PAD(0x03AC, 0x00BC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_D6__EPDC_SDDO_6 \
+ IOMUX_PAD(0x03B0, 0x00C0, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D6__ECSPI4_SS3 \
+ IOMUX_PAD(0x03B0, 0x00C0, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D6__LCDIF_DAT_30 \
+ IOMUX_PAD(0x03B0, 0x00C0, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D6__CSI_D_6 \
+ IOMUX_PAD(0x03B0, 0x00C0, 3, 0x0648, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D6__TCON_E_DATA_6 \
+ IOMUX_PAD(0x03B0, 0x00C0, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D6__GPIO_1_13 \
+ IOMUX_PAD(0x03B0, 0x00C0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D6__ANATOP_USBPHY2_TSTO_RX_DISCON_DET \
+ IOMUX_PAD(0x03B0, 0x00C0, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D6__TPSMP_HDATA_20 \
+ IOMUX_PAD(0x03B0, 0x00C0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_D7__EPDC_SDDO_7 \
+ IOMUX_PAD(0x03B4, 0x00C4, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D7__ECSPI4_RDY \
+ IOMUX_PAD(0x03B4, 0x00C4, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D7__LCDIF_DAT_31 \
+ IOMUX_PAD(0x03B4, 0x00C4, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D7__CSI_D_7 \
+ IOMUX_PAD(0x03B4, 0x00C4, 3, 0x064C, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D7__TCON_E_DATA_7 \
+ IOMUX_PAD(0x03B4, 0x00C4, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D7__GPIO_1_14 \
+ IOMUX_PAD(0x03B4, 0x00C4, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D7__ANATOP_USBPHY2_TSTO_RX_FS_RXD \
+ IOMUX_PAD(0x03B4, 0x00C4, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D7__MMDC_MMDC_DEBUG_32 \
+ IOMUX_PAD(0x03B4, 0x00C4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_D8__EPDC_SDDO_8 \
+ IOMUX_PAD(0x03B8, 0x00C8, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D8__ECSPI3_MOSI \
+ IOMUX_PAD(0x03B8, 0x00C8, 1, 0x06BC, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D8__EPDC_PWRCTRL_0 \
+ IOMUX_PAD(0x03B8, 0x00C8, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D8__WEIM_WEIM_A_16 \
+ IOMUX_PAD(0x03B8, 0x00C8, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D8__TCON_E_DATA_8 \
+ IOMUX_PAD(0x03B8, 0x00C8, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D8__GPIO_1_15 \
+ IOMUX_PAD(0x03B8, 0x00C8, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D8__USDHC4_RST \
+ IOMUX_PAD(0x03B8, 0x00C8, 6, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D8__MMDC_MMDC_DEBUG_31 \
+ IOMUX_PAD(0x03B8, 0x00C8, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_D9__EPDC_SDDO_9 \
+ IOMUX_PAD(0x03BC, 0x00CC, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D9__ECSPI3_MISO \
+ IOMUX_PAD(0x03BC, 0x00CC, 1, 0x06B8, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D9__EPDC_PWRCTRL_1 \
+ IOMUX_PAD(0x03BC, 0x00CC, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D9__WEIM_WEIM_A_17 \
+ IOMUX_PAD(0x03BC, 0x00CC, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D9__TCON_E_DATA_9 \
+ IOMUX_PAD(0x03BC, 0x00CC, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D9__GPIO_1_16 \
+ IOMUX_PAD(0x03BC, 0x00CC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D9__USDHC4_VSELECT \
+ IOMUX_PAD(0x03BC, 0x00CC, 6, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_EPDC_D9__MMDC_MMDC_DEBUG_30 \
+ IOMUX_PAD(0x03BC, 0x00CC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_GDCLK__EPDC_GDCLK \
+ IOMUX_PAD(0x03C0, 0x00D0, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_GDCLK__ECSPI2_SS2 \
+ IOMUX_PAD(0x03C0, 0x00D0, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_GDCLK__TCON_YCKR \
+ IOMUX_PAD(0x03C0, 0x00D0, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_GDCLK__CSI_PIXCLK \
+ IOMUX_PAD(0x03C0, 0x00D0, 3, 0x0674, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_GDCLK__TCON_YCKL \
+ IOMUX_PAD(0x03C0, 0x00D0, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_GDCLK__GPIO_1_31 \
+ IOMUX_PAD(0x03C0, 0x00D0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_GDCLK__USDHC2_RST \
+ IOMUX_PAD(0x03C0, 0x00D0, 6, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_EPDC_GDCLK__MMDC_MMDC_DEBUG_15 \
+ IOMUX_PAD(0x03C0, 0x00D0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_GDOE__EPDC_GDOE \
+ IOMUX_PAD(0x03C4, 0x00D4, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_GDOE__ECSPI2_SS3 \
+ IOMUX_PAD(0x03C4, 0x00D4, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_GDOE__TCON_YOER \
+ IOMUX_PAD(0x03C4, 0x00D4, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_GDOE__CSI_HSYNC \
+ IOMUX_PAD(0x03C4, 0x00D4, 3, 0x0670, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_GDOE__TCON_YOEL \
+ IOMUX_PAD(0x03C4, 0x00D4, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_GDOE__GPIO_2_0 \
+ IOMUX_PAD(0x03C4, 0x00D4, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_GDOE__USDHC2_VSELECT \
+ IOMUX_PAD(0x03C4, 0x00D4, 6, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_EPDC_GDOE__MMDC_MMDC_DEBUG_14 \
+ IOMUX_PAD(0x03C4, 0x00D4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_GDRL__EPDC_GDRL \
+ IOMUX_PAD(0x03C8, 0x00D8, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_GDRL__ECSPI2_RDY \
+ IOMUX_PAD(0x03C8, 0x00D8, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_GDRL__TCON_YDIOUR \
+ IOMUX_PAD(0x03C8, 0x00D8, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_GDRL__CSI_MCLK \
+ IOMUX_PAD(0x03C8, 0x00D8, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_GDRL__TCON_YDIOUL \
+ IOMUX_PAD(0x03C8, 0x00D8, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_GDRL__GPIO_2_1 \
+ IOMUX_PAD(0x03C8, 0x00D8, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_GDRL__USDHC2_WP \
+ IOMUX_PAD(0x03C8, 0x00D8, 6, 0x0834, 1, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_EPDC_GDRL__MMDC_MMDC_DEBUG_13 \
+ IOMUX_PAD(0x03C8, 0x00D8, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_GDSP__EPDC_GDSP \
+ IOMUX_PAD(0x03CC, 0x00DC, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_GDSP__PWM4_PWMO \
+ IOMUX_PAD(0x03CC, 0x00DC, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_GDSP__TCON_YDIODR \
+ IOMUX_PAD(0x03CC, 0x00DC, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_GDSP__CSI_VSYNC \
+ IOMUX_PAD(0x03CC, 0x00DC, 3, 0x0678, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_GDSP__TCON_YDIODL \
+ IOMUX_PAD(0x03CC, 0x00DC, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_GDSP__GPIO_2_2 \
+ IOMUX_PAD(0x03CC, 0x00DC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_GDSP__USDHC2_CD \
+ IOMUX_PAD(0x03CC, 0x00DC, 6, 0x0830, 1, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_EPDC_GDSP__MMDC_MMDC_DEBUG_12 \
+ IOMUX_PAD(0x03CC, 0x00DC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_PWRCOM__EPDC_PWRCOM \
+ IOMUX_PAD(0x03D0, 0x00E0, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRCOM__USDHC4_DAT0 \
+ IOMUX_PAD(0x03D0, 0x00E0, 1, 0x085C, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRCOM__LCDIF_DAT_20 \
+ IOMUX_PAD(0x03D0, 0x00E0, 2, 0x07C8, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRCOM__WEIM_WEIM_BCLK \
+ IOMUX_PAD(0x03D0, 0x00E0, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID \
+ IOMUX_PAD(0x03D0, 0x00E0, 4, 0x05DC, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRCOM__GPIO_2_11 \
+ IOMUX_PAD(0x03D0, 0x00E0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRCOM__USDHC3_RST \
+ IOMUX_PAD(0x03D0, 0x00E0, 6, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRCOM__MMDC_MMDC_DEBUG_3 \
+ IOMUX_PAD(0x03D0, 0x00E0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_PWRCTRL0__EPDC_PWRCTRL_0 \
+ IOMUX_PAD(0x03D4, 0x00E4, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRCTRL0__AUDMUX_AUD5_RXC \
+ IOMUX_PAD(0x03D4, 0x00E4, 1, 0x0604, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRCTRL0__LCDIF_DAT_16 \
+ IOMUX_PAD(0x03D4, 0x00E4, 2, 0x07B8, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRCTRL0__WEIM_WEIM_RW \
+ IOMUX_PAD(0x03D4, 0x00E4, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRCTRL0__TCON_YCKL \
+ IOMUX_PAD(0x03D4, 0x00E4, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRCTRL0__GPIO_2_7 \
+ IOMUX_PAD(0x03D4, 0x00E4, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRCTRL0__USDHC4_RST \
+ IOMUX_PAD(0x03D4, 0x00E4, 6, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRCTRL0__MMDC_MMDC_DEBUG_7 \
+ IOMUX_PAD(0x03D4, 0x00E4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_PWRCTRL1__EPDC_PWRCTRL_1 \
+ IOMUX_PAD(0x03D8, 0x00E8, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRCTRL1__AUDMUX_AUD5_TXFS \
+ IOMUX_PAD(0x03D8, 0x00E8, 1, 0x0610, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRCTRL1__LCDIF_DAT_17 \
+ IOMUX_PAD(0x03D8, 0x00E8, 2, 0x07BC, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRCTRL1__WEIM_WEIM_OE \
+ IOMUX_PAD(0x03D8, 0x00E8, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRCTRL1__TCON_YOEL \
+ IOMUX_PAD(0x03D8, 0x00E8, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRCTRL1__GPIO_2_8 \
+ IOMUX_PAD(0x03D8, 0x00E8, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRCTRL1__USDHC4_VSELECT \
+ IOMUX_PAD(0x03D8, 0x00E8, 6, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRCTRL1__MMDC_MMDC_DEBUG_6 \
+ IOMUX_PAD(0x03D8, 0x00E8, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_PWRCTRL2__EPDC_PWRCTRL_2 \
+ IOMUX_PAD(0x03DC, 0x00EC, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRCTRL2__AUDMUX_AUD5_TXD \
+ IOMUX_PAD(0x03DC, 0x00EC, 1, 0x0600, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRCTRL2__LCDIF_DAT_18 \
+ IOMUX_PAD(0x03DC, 0x00EC, 2, 0x07C0, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRCTRL2__WEIM_WEIM_CS_0 \
+ IOMUX_PAD(0x03DC, 0x00EC, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRCTRL2__TCON_YDIOUL \
+ IOMUX_PAD(0x03DC, 0x00EC, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRCTRL2__GPIO_2_9 \
+ IOMUX_PAD(0x03DC, 0x00EC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRCTRL2__USDHC4_WP \
+ IOMUX_PAD(0x03DC, 0x00EC, 6, 0x087C, 1, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRCTRL2__MMDC_MMDC_DEBUG_5 \
+ IOMUX_PAD(0x03DC, 0x00EC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_PWRCTRL3__EPDC_PWRCTRL_3 \
+ IOMUX_PAD(0x03E0, 0x00F0, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRCTRL3__AUDMUX_AUD5_TXC \
+ IOMUX_PAD(0x03E0, 0x00F0, 1, 0x060C, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRCTRL3__LCDIF_DAT_19 \
+ IOMUX_PAD(0x03E0, 0x00F0, 2, 0x07C4, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRCTRL3__WEIM_WEIM_CS_1 \
+ IOMUX_PAD(0x03E0, 0x00F0, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRCTRL3__TCON_YDIODL \
+ IOMUX_PAD(0x03E0, 0x00F0, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRCTRL3__GPIO_2_10 \
+ IOMUX_PAD(0x03E0, 0x00F0, 5, 0x0000, 0, MX6SL_TSPAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRCTRL3__USDHC4_CD \
+ IOMUX_PAD(0x03E0, 0x00F0, 6, 0x0854, 1, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRCTRL3__MMDC_MMDC_DEBUG_4 \
+ IOMUX_PAD(0x03E0, 0x00F0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_PWRINT__EPDC_PWRIRQ \
+ IOMUX_PAD(0x03E4, 0x00F4, 0, 0x06E8, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRINT__USDHC4_DAT1 \
+ IOMUX_PAD(0x03E4, 0x00F4, 1, 0x0860, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRINT__LCDIF_DAT_21 \
+ IOMUX_PAD(0x03E4, 0x00F4, 2, 0x07CC, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRINT__WEIM_ACLK_FREERUN \
+ IOMUX_PAD(0x03E4, 0x00F4, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRINT__ANATOP_USBOTG2_ID \
+ IOMUX_PAD(0x03E4, 0x00F4, 4, 0x05E0, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRINT__GPIO_2_12 \
+ IOMUX_PAD(0x03E4, 0x00F4, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRINT__USDHC3_VSELECT \
+ IOMUX_PAD(0x03E4, 0x00F4, 6, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRINT__MMDC_MMDC_DEBUG_2 \
+ IOMUX_PAD(0x03E4, 0x00F4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_PWRSTAT__EPDC_PWRSTAT \
+ IOMUX_PAD(0x03E8, 0x00F8, 0, 0x06EC, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRSTAT__USDHC4_DAT2 \
+ IOMUX_PAD(0x03E8, 0x00F8, 1, 0x0864, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRSTAT__LCDIF_DAT_22 \
+ IOMUX_PAD(0x03E8, 0x00F8, 2, 0x07D0, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRSTAT__WEIM_WEIM_WAIT \
+ IOMUX_PAD(0x03E8, 0x00F8, 3, 0x0884, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRSTAT__KITTEN_EVENTI \
+ IOMUX_PAD(0x03E8, 0x00F8, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRSTAT__GPIO_2_13 \
+ IOMUX_PAD(0x03E8, 0x00F8, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRSTAT__USDHC3_WP \
+ IOMUX_PAD(0x03E8, 0x00F8, 6, 0x084C, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRSTAT__MMDC_MMDC_DEBUG_1 \
+ IOMUX_PAD(0x03E8, 0x00F8, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_PWRWAKEUP__EPDC_PWRWAKE \
+ IOMUX_PAD(0x03EC, 0x00FC, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRWAKEUP__USDHC4_DAT3 \
+ IOMUX_PAD(0x03EC, 0x00FC, 1, 0x0868, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRWAKEUP__LCDIF_DAT_23 \
+ IOMUX_PAD(0x03EC, 0x00FC, 2, 0x07D4, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRWAKEUP__WEIM_WEIM_DTACK_B \
+ IOMUX_PAD(0x03EC, 0x00FC, 3, 0x0880, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRWAKEUP__KITTEN_EVENTO \
+ IOMUX_PAD(0x03EC, 0x00FC, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRWAKEUP__GPIO_2_14 \
+ IOMUX_PAD(0x03EC, 0x00FC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRWAKEUP__USDHC3_CD \
+ IOMUX_PAD(0x03EC, 0x00FC, 6, 0x0838, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_EPDC_PWRWAKEUP__MMDC_MMDC_DEBUG_0 \
+ IOMUX_PAD(0x03EC, 0x00FC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_SDCE0__EPDC_SDCE_0 \
+ IOMUX_PAD(0x03F0, 0x0100, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDCE0__ECSPI2_SS1 \
+ IOMUX_PAD(0x03F0, 0x0100, 1, 0x06AC, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDCE0__PWM3_PWMO \
+ IOMUX_PAD(0x03F0, 0x0100, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDCE0__WEIM_WEIM_CS_2 \
+ IOMUX_PAD(0x03F0, 0x0100, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDCE0__TCON_YCKR \
+ IOMUX_PAD(0x03F0, 0x0100, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDCE0__GPIO_1_27 \
+ IOMUX_PAD(0x03F0, 0x0100, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDCE0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV \
+ IOMUX_PAD(0x03F0, 0x0100, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDCE0__MMDC_MMDC_DEBUG_19 \
+ IOMUX_PAD(0x03F0, 0x0100, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_SDCE1__EPDC_SDCE_1 \
+ IOMUX_PAD(0x03F4, 0x0104, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDCE1__WDOG2_WDOG_B \
+ IOMUX_PAD(0x03F4, 0x0104, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDCE1__PWM4_PWMO \
+ IOMUX_PAD(0x03F4, 0x0104, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDCE1__WEIM_WEIM_LBA \
+ IOMUX_PAD(0x03F4, 0x0104, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDCE1__TCON_YOER \
+ IOMUX_PAD(0x03F4, 0x0104, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDCE1__GPIO_1_28 \
+ IOMUX_PAD(0x03F4, 0x0104, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDCE1__ANATOP_USBPHY1_TSTO_RX_FS_RXD \
+ IOMUX_PAD(0x03F4, 0x0104, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDCE1__MMDC_MMDC_DEBUG_18 \
+ IOMUX_PAD(0x03F4, 0x0104, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_SDCE2__EPDC_SDCE_2 \
+ IOMUX_PAD(0x03F8, 0x0108, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDCE2__I2C3_SCL \
+ IOMUX_PAD(0x03F8, 0x0108, 1 | IOMUX_CONFIG_SION, 0x072C, 1, MX6SL_I2C_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDCE2__PWM1_PWMO \
+ IOMUX_PAD(0x03F8, 0x0108, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDCE2__WEIM_WEIM_EB_0 \
+ IOMUX_PAD(0x03F8, 0x0108, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDCE2__TCON_YDIOUR \
+ IOMUX_PAD(0x03F8, 0x0108, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDCE2__GPIO_1_29 \
+ IOMUX_PAD(0x03F8, 0x0108, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDCE2__ANATOP_USBPHY1_TSTO_RX_HS_RXD \
+ IOMUX_PAD(0x03F8, 0x0108, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDCE2__MMDC_MMDC_DEBUG_17 \
+ IOMUX_PAD(0x03F8, 0x0108, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_SDCE3__EPDC_SDCE_3 \
+ IOMUX_PAD(0x03FC, 0x010C, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDCE3__I2C3_SDA \
+ IOMUX_PAD(0x03FC, 0x010C, 1 | IOMUX_CONFIG_SION, 0x0730, 1, MX6SL_I2C_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDCE3__PWM2_PWMO \
+ IOMUX_PAD(0x03FC, 0x010C, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDCE3__WEIM_WEIM_EB_1 \
+ IOMUX_PAD(0x03FC, 0x010C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDCE3__TCON_YDIODR \
+ IOMUX_PAD(0x03FC, 0x010C, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDCE3__GPIO_1_30 \
+ IOMUX_PAD(0x03FC, 0x010C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDCE3__ANATOP_USBPHY1_TSTO_RX_SQUELCH \
+ IOMUX_PAD(0x03FC, 0x010C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDCE3__MMDC_MMDC_DEBUG_16 \
+ IOMUX_PAD(0x03FC, 0x010C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_SDCLK__EPDC_SDCLK \
+ IOMUX_PAD(0x0400, 0x0110, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDCLK__ECSPI2_MOSI \
+ IOMUX_PAD(0x0400, 0x0110, 1, 0x06A4, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDCLK__I2C2_SCL \
+ IOMUX_PAD(0x0400, 0x0110, 2 | IOMUX_CONFIG_SION, 0x0724, 0, MX6SL_I2C_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDCLK__CSI_D_8 \
+ IOMUX_PAD(0x0400, 0x0110, 3, 0x0650, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDCLK__TCON_CL \
+ IOMUX_PAD(0x0400, 0x0110, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDCLK__GPIO_1_23 \
+ IOMUX_PAD(0x0400, 0x0110, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDCLK__ANATOP_USBPHY2_TSTO_RX_HS_RXD \
+ IOMUX_PAD(0x0400, 0x0110, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDCLK__MMDC_MMDC_DEBUG_23 \
+ IOMUX_PAD(0x0400, 0x0110, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_SDLE__EPDC_SDLE \
+ IOMUX_PAD(0x0404, 0x0114, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDLE__ECSPI2_MISO \
+ IOMUX_PAD(0x0404, 0x0114, 1, 0x06A0, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDLE__I2C2_SDA \
+ IOMUX_PAD(0x0404, 0x0114, 2 | IOMUX_CONFIG_SION, 0x0728, 0, MX6SL_I2C_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDLE__CSI_D_9 \
+ IOMUX_PAD(0x0404, 0x0114, 3, 0x0654, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDLE__TCON_LD \
+ IOMUX_PAD(0x0404, 0x0114, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDLE__GPIO_1_24 \
+ IOMUX_PAD(0x0404, 0x0114, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDLE__ANATOP_USBPHY2_TSTO_RX_SQUELCH \
+ IOMUX_PAD(0x0404, 0x0114, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDLE__MMDC_MMDC_DEBUG_22 \
+ IOMUX_PAD(0x0404, 0x0114, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_SDOE__EPDC_SDOE \
+ IOMUX_PAD(0x0408, 0x0118, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDOE__ECSPI2_SS0 \
+ IOMUX_PAD(0x0408, 0x0118, 1, 0x06A8, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDOE__TCON_XDIOR \
+ IOMUX_PAD(0x0408, 0x0118, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDOE__CSI_D_10 \
+ IOMUX_PAD(0x0408, 0x0118, 3, 0x0658, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDOE__TCON_XDIOL \
+ IOMUX_PAD(0x0408, 0x0118, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDOE__GPIO_1_25 \
+ IOMUX_PAD(0x0408, 0x0118, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDOE__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV \
+ IOMUX_PAD(0x0408, 0x0118, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDOE__MMDC_MMDC_DEBUG_21 \
+ IOMUX_PAD(0x0408, 0x0118, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_SDSHR__EPDC_SDSHR \
+ IOMUX_PAD(0x040C, 0x011C, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDSHR__ECSPI2_SCLK \
+ IOMUX_PAD(0x040C, 0x011C, 1, 0x069C, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDSHR__EPDC_SDCE_4 \
+ IOMUX_PAD(0x040C, 0x011C, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDSHR__CSI_D_11 \
+ IOMUX_PAD(0x040C, 0x011C, 3, 0x065C, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDSHR__TCON_XDIOR \
+ IOMUX_PAD(0x040C, 0x011C, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDSHR__GPIO_1_26 \
+ IOMUX_PAD(0x040C, 0x011C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDSHR__ANATOP_USBPHY1_TSTO_RX_DISCON_DET \
+ IOMUX_PAD(0x040C, 0x011C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_SDSHR__MMDC_MMDC_DEBUG_20 \
+ IOMUX_PAD(0x040C, 0x011C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_VCOM0__EPDC_VCOM_0 \
+ IOMUX_PAD(0x0410, 0x0120, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_VCOM0__AUDMUX_AUD5_RXFS \
+ IOMUX_PAD(0x0410, 0x0120, 1, 0x0608, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_VCOM0__UART3_TXD \
+ IOMUX_PAD(0x0410, 0x0120, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_EPDC_VCOM0__UART3_RXD \
+ IOMUX_PAD(0x0410, 0x0120, 2, 0x080C, 4, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_EPDC_VCOM0__WEIM_WEIM_A_24 \
+ IOMUX_PAD(0x0410, 0x0120, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_VCOM0__TCON_VCOM_0 \
+ IOMUX_PAD(0x0410, 0x0120, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_VCOM0__GPIO_2_3 \
+ IOMUX_PAD(0x0410, 0x0120, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_VCOM0__EPDC_SDCE_5 \
+ IOMUX_PAD(0x0410, 0x0120, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_VCOM0__MMDC_MMDC_DEBUG_11 \
+ IOMUX_PAD(0x0410, 0x0120, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_EPDC_VCOM1__EPDC_VCOM_1 \
+ IOMUX_PAD(0x0414, 0x0124, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_VCOM1__AUDMUX_AUD5_RXD \
+ IOMUX_PAD(0x0414, 0x0124, 1, 0x05FC, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_VCOM1__UART3_TXD \
+ IOMUX_PAD(0x0414, 0x0124, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_EPDC_VCOM1__UART3_RXD \
+ IOMUX_PAD(0x0414, 0x0124, 2, 0x080C, 5, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_EPDC_VCOM1__WEIM_WEIM_A_25 \
+ IOMUX_PAD(0x0414, 0x0124, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_VCOM1__TCON_VCOM_1 \
+ IOMUX_PAD(0x0414, 0x0124, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_VCOM1__GPIO_2_4 \
+ IOMUX_PAD(0x0414, 0x0124, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_VCOM1__EPDC_SDCE_6 \
+ IOMUX_PAD(0x0414, 0x0124, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_EPDC_VCOM1__MMDC_MMDC_DEBUG_10 \
+ IOMUX_PAD(0x0414, 0x0124, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV \
+ IOMUX_PAD(0x0418, 0x0128, 0, 0x0704, 1, MX6SL_ENET_PAD_CTRL)
+#define MX6SL_PAD_FEC_CRS_DV__USDHC4_DAT1 \
+ IOMUX_PAD(0x0418, 0x0128, 1, 0x0860, 1, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_FEC_CRS_DV__AUDMUX_AUD6_TXC \
+ IOMUX_PAD(0x0418, 0x0128, 2, 0x0624, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_CRS_DV__ECSPI4_MISO \
+ IOMUX_PAD(0x0418, 0x0128, 3, 0x06D4, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_CRS_DV__GPT_CMPOUT2 \
+ IOMUX_PAD(0x0418, 0x0128, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_CRS_DV__GPIO_4_25 \
+ IOMUX_PAD(0x0418, 0x0128, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_CRS_DV__KITTEN_TRACE_31 \
+ IOMUX_PAD(0x0418, 0x0128, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_CRS_DV__PL301_SIM_MX6SL_PER1_HADDR_3 \
+ IOMUX_PAD(0x0418, 0x0128, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_FEC_MDC__FEC_MDC \
+ IOMUX_PAD(0x041C, 0x012C, 0, 0x0000, 0, MX6SL_ENET_PAD_CTRL)
+#define MX6SL_PAD_FEC_MDC__USDHC4_DAT4 \
+ IOMUX_PAD(0x041C, 0x012C, 1, 0x086C, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_FEC_MDC__AUDMUX_AUDIO_CLK_OUT \
+ IOMUX_PAD(0x041C, 0x012C, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_MDC__USDHC1_RST \
+ IOMUX_PAD(0x041C, 0x012C, 3, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_FEC_MDC__USDHC3_RST \
+ IOMUX_PAD(0x041C, 0x012C, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_FEC_MDC__GPIO_4_23 \
+ IOMUX_PAD(0x041C, 0x012C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_MDC__KITTEN_TRACE_29 \
+ IOMUX_PAD(0x041C, 0x012C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_MDC__PL301_SIM_MX6SL_PER1_HADDR_8 \
+ IOMUX_PAD(0x041C, 0x012C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_FEC_MDIO__FEC_MDIO \
+ IOMUX_PAD(0x0420, 0x0130, 0, 0x06F4, 1, MX6SL_ENET_PAD_CTRL)
+#define MX6SL_PAD_FEC_MDIO__USDHC4_CLK \
+ IOMUX_PAD(0x0420, 0x0130, 1, 0x0850, 1, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_FEC_MDIO__AUDMUX_AUD6_RXFS \
+ IOMUX_PAD(0x0420, 0x0130, 2, 0x0620, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_MDIO__ECSPI4_SS0 \
+ IOMUX_PAD(0x0420, 0x0130, 3, 0x06DC, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_MDIO__GPT_CAPIN1 \
+ IOMUX_PAD(0x0420, 0x0130, 4, 0x0710, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_MDIO__GPIO_4_20 \
+ IOMUX_PAD(0x0420, 0x0130, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_MDIO__KITTEN_TRACE_26 \
+ IOMUX_PAD(0x0420, 0x0130, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_MDIO__PL301_SIM_MX6SL_PER1_HADDR_15 \
+ IOMUX_PAD(0x0420, 0x0130, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT \
+ IOMUX_PAD(0x0424, 0x0134, 0x10, 0x0000, 0, MX6SL_ENET_PAD_CTRL)
+#define MX6SL_PAD_FEC_REF_CLK__USDHC4_RST \
+ IOMUX_PAD(0x0424, 0x0134, 1, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_FEC_REF_CLK__WDOG1_WDOG_B \
+ IOMUX_PAD(0x0424, 0x0134, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_REF_CLK__PWM4_PWMO \
+ IOMUX_PAD(0x0424, 0x0134, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_REF_CLK__CCM_PMIC_RDY \
+ IOMUX_PAD(0x0424, 0x0134, 4, 0x062C, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_REF_CLK__GPIO_4_26 \
+ IOMUX_PAD(0x0424, 0x0134, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_REF_CLK__SPDIF_SPDIF_EXT_CLK \
+ IOMUX_PAD(0x0424, 0x0134, 6, 0x07F4, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_REF_CLK__PL301_SIM_MX6SL_PER1_HADDR_0 \
+ IOMUX_PAD(0x0424, 0x0134, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_FEC_RX_ER__GPIO_4_19 \
+ IOMUX_PAD(0x0428, 0x0138, 5, 0x0000, 0, MX6SL_HP_DET_PAD_CTRL)
+#define MX6SL_PAD_FEC_RX_ER__KITTEN_TRACE_25 \
+ IOMUX_PAD(0x0428, 0x0138, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_RX_ER__PL301_SIM_MX6SL_PER1_HADDR_5 \
+ IOMUX_PAD(0x0428, 0x0138, 7, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_RX_ER__FEC_RX_ER \
+ IOMUX_PAD(0x0428, 0x0138, 0, 0x0708, 1, MX6SL_ENET_PAD_CTRL)
+#define MX6SL_PAD_FEC_RX_ER__USDHC4_DAT0 \
+ IOMUX_PAD(0x0428, 0x0138, 1, 0x085C, 1, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_FEC_RX_ER__AUDMUX_AUD6_RXD \
+ IOMUX_PAD(0x0428, 0x0138, 2, 0x0614, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_RX_ER__ECSPI4_MOSI \
+ IOMUX_PAD(0x0428, 0x0138, 3, 0x06D8, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_RX_ER__GPT_CMPOUT1 \
+ IOMUX_PAD(0x0428, 0x0138, 4, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_FEC_RXD0__FEC_RDATA_0 \
+ IOMUX_PAD(0x042C, 0x013C, 0, 0x06F8, 0, MX6SL_ENET_PAD_CTRL)
+#define MX6SL_PAD_FEC_RXD0__USDHC4_DAT5 \
+ IOMUX_PAD(0x042C, 0x013C, 1, 0x0870, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_FEC_RXD0__ANATOP_USBOTG1_ID \
+ IOMUX_PAD(0x042C, 0x013C, 2, 0x05DC, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_RXD0__USDHC1_VSELECT \
+ IOMUX_PAD(0x042C, 0x013C, 3, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_FEC_RXD0__USDHC3_VSELECT \
+ IOMUX_PAD(0x042C, 0x013C, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_FEC_RXD0__GPIO_4_17 \
+ IOMUX_PAD(0x042C, 0x013C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_RXD0__KITTEN_TRACE_24 \
+ IOMUX_PAD(0x042C, 0x013C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_RXD0__PL301_SIM_MX6SL_PER1_HADDR_7 \
+ IOMUX_PAD(0x042C, 0x013C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_FEC_RXD1__FEC_RDATA_1 \
+ IOMUX_PAD(0x0430, 0x0140, 0, 0x06FC, 1, MX6SL_ENET_PAD_CTRL)
+#define MX6SL_PAD_FEC_RXD1__USDHC4_DAT2 \
+ IOMUX_PAD(0x0430, 0x0140, 1, 0x0864, 1, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_FEC_RXD1__AUDMUX_AUD6_TXFS \
+ IOMUX_PAD(0x0430, 0x0140, 2, 0x0628, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_RXD1__ECSPI4_SS1 \
+ IOMUX_PAD(0x0430, 0x0140, 3, 0x06E0, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_RXD1__GPT_CMPOUT3 \
+ IOMUX_PAD(0x0430, 0x0140, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_RXD1__GPIO_4_18 \
+ IOMUX_PAD(0x0430, 0x0140, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_RXD1__FEC_COL \
+ IOMUX_PAD(0x0430, 0x0140, 6, 0x06F0, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_RXD1__PL301_SIM_MX6SL_PER1_HADDR_9 \
+ IOMUX_PAD(0x0430, 0x0140, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_FEC_TX_CLK__FEC_TX_CLK \
+ IOMUX_PAD(0x0434, 0x0144, 0, 0x070C, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_TX_CLK__USDHC4_CMD \
+ IOMUX_PAD(0x0434, 0x0144, 1, 0x0858, 1, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_FEC_TX_CLK__AUDMUX_AUD6_RXC \
+ IOMUX_PAD(0x0434, 0x0144, 2, 0x061C, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_TX_CLK__ECSPI4_SCLK \
+ IOMUX_PAD(0x0434, 0x0144, 3, 0x06D0, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_TX_CLK__GPT_CAPIN2 \
+ IOMUX_PAD(0x0434, 0x0144, 4, 0x0714, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_TX_CLK__GPIO_4_21 \
+ IOMUX_PAD(0x0434, 0x0144, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_TX_CLK__KITTEN_TRACE_27 \
+ IOMUX_PAD(0x0434, 0x0144, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_TX_CLK__PL301_SIM_MX6SL_PER1_HADDR_4 \
+ IOMUX_PAD(0x0434, 0x0144, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_FEC_TX_EN__FEC_TX_EN \
+ IOMUX_PAD(0x0438, 0x0148, 0, 0x0000, 0, MX6SL_ENET_PAD_CTRL)
+#define MX6SL_PAD_FEC_TX_EN__USDHC4_DAT6 \
+ IOMUX_PAD(0x0438, 0x0148, 1, 0x0874, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_FEC_TX_EN__SPDIF_IN1 \
+ IOMUX_PAD(0x0438, 0x0148, 2, 0x07F0, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_TX_EN__USDHC1_WP \
+ IOMUX_PAD(0x0438, 0x0148, 3, 0x082C, 1, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_FEC_TX_EN__USDHC3_WP \
+ IOMUX_PAD(0x0438, 0x0148, 4, 0x084C, 1, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_FEC_TX_EN__GPIO_4_22 \
+ IOMUX_PAD(0x0438, 0x0148, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_TX_EN__KITTEN_TRACE_28 \
+ IOMUX_PAD(0x0438, 0x0148, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_TX_EN__PL301_SIM_MX6SL_PER1_HADDR_1 \
+ IOMUX_PAD(0x0438, 0x0148, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_FEC_TXD0__FEC_TDATA_0 \
+ IOMUX_PAD(0x043C, 0x014C, 0, 0x0000, 0, MX6SL_ENET_PAD_CTRL)
+#define MX6SL_PAD_FEC_TXD0__USDHC4_DAT3 \
+ IOMUX_PAD(0x043C, 0x014C, 1, 0x0868, 1, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_FEC_TXD0__AUDMUX_AUD6_TXD \
+ IOMUX_PAD(0x043C, 0x014C, 2, 0x0618, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_TXD0__ECSPI4_SS2 \
+ IOMUX_PAD(0x043C, 0x014C, 3, 0x06E4, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_TXD0__GPT_CLKIN \
+ IOMUX_PAD(0x043C, 0x014C, 4, 0x0718, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_TXD0__GPIO_4_24 \
+ IOMUX_PAD(0x043C, 0x014C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_TXD0__KITTEN_TRACE_30 \
+ IOMUX_PAD(0x043C, 0x014C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_TXD0__PL301_SIM_MX6SL_PER1_HADDR_2 \
+ IOMUX_PAD(0x043C, 0x014C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_FEC_TXD1__FEC_TDATA_1 \
+ IOMUX_PAD(0x0440, 0x0150, 0, 0x0000, 0, MX6SL_ENET_PAD_CTRL)
+#define MX6SL_PAD_FEC_TXD1__USDHC4_DAT7 \
+ IOMUX_PAD(0x0440, 0x0150, 1, 0x0878, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_FEC_TXD1__SPDIF_OUT1 \
+ IOMUX_PAD(0x0440, 0x0150, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_TXD1__USDHC1_CD \
+ IOMUX_PAD(0x0440, 0x0150, 3, 0x0828, 1, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_FEC_TXD1__USDHC3_CD \
+ IOMUX_PAD(0x0440, 0x0150, 4, 0x0838, 1, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_FEC_TXD1__GPIO_4_16 \
+ IOMUX_PAD(0x0440, 0x0150, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_TXD1__FEC_RX_CLK \
+ IOMUX_PAD(0x0440, 0x0150, 6, 0x0700, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_FEC_TXD1__PL301_SIM_MX6SL_PER1_HADDR_6 \
+ IOMUX_PAD(0x0440, 0x0150, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_HSIC_DAT__USB_H_DATA \
+ IOMUX_PAD(0x0444, 0x0154, 0, 0x0000, 0, MX6SL_USB_HSIC_PAD_CTRL)
+#define MX6SL_PAD_HSIC_DAT__I2C1_SCL \
+ IOMUX_PAD(0x0444, 0x0154, 1 | IOMUX_CONFIG_SION, 0x071C, 1, MX6SL_I2C_PAD_CTRL)
+#define MX6SL_PAD_HSIC_DAT__PWM1_PWMO \
+ IOMUX_PAD(0x0444, 0x0154, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_HSIC_DAT__ANATOP_ANATOP_24M_OUT \
+ IOMUX_PAD(0x0444, 0x0154, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_HSIC_DAT__OSC32K_32K_OUT \
+ IOMUX_PAD(0x0444, 0x0154, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_HSIC_DAT__GPIO_3_19 \
+ IOMUX_PAD(0x0444, 0x0154, 5, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_HSIC_STROBE__USB_H_STROBE \
+ IOMUX_PAD(0x0448, 0x0158, 0, 0x0000, 0, MX6SL_USB_HSIC_PAD_CTRL)
+#define MX6SL_PAD_HSIC_STROBE__USB_H_STROBE_START \
+ IOMUX_PAD(0x0448, 0x0158, 0, 0x0000, 0, MX6SL_USB_HSIC_PAD_CTRL | PAD_CTL_PUS_47K_UP)
+#define MX6SL_PAD_HSIC_STROBE__I2C1_SDA \
+ IOMUX_PAD(0x0448, 0x0158, 1 | IOMUX_CONFIG_SION, 0x0720, 1, MX6SL_I2C_PAD_CTRL)
+#define MX6SL_PAD_HSIC_STROBE__PWM2_PWMO \
+ IOMUX_PAD(0x0448, 0x0158, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_HSIC_STROBE__ANATOP_ANATOP_32K_OUT \
+ IOMUX_PAD(0x0448, 0x0158, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_HSIC_STROBE__GPIO_3_20 \
+ IOMUX_PAD(0x0448, 0x0158, 5, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_I2C1_SCL__I2C1_SCL \
+ IOMUX_PAD(0x044C, 0x015C, 0 | IOMUX_CONFIG_SION, 0x071C, 2, MX6SL_I2C_PAD_CTRL)
+#define MX6SL_PAD_I2C1_SCL__UART1_CTS \
+ IOMUX_PAD(0x044C, 0x015C, 1, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_I2C1_SCL__UART1_RTS \
+ IOMUX_PAD(0x044C, 0x015C, 1, 0x07F8, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_I2C1_SCL__ECSPI3_SS2 \
+ IOMUX_PAD(0x044C, 0x015C, 2, 0x06C8, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_I2C1_SCL__FEC_RDATA_0 \
+ IOMUX_PAD(0x044C, 0x015C, 3, 0x06F8, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_I2C1_SCL__USDHC3_RST \
+ IOMUX_PAD(0x044C, 0x015C, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_I2C1_SCL__GPIO_3_12 \
+ IOMUX_PAD(0x044C, 0x015C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_I2C1_SCL__ECSPI1_SS1 \
+ IOMUX_PAD(0x044C, 0x015C, 6, 0x0690, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_I2C1_SCL__PL301_SIM_MX6SL_PER1_HSIZE_0 \
+ IOMUX_PAD(0x044C, 0x015C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_I2C1_SDA__I2C1_SDA \
+ IOMUX_PAD(0x0450, 0x0160, 0 | IOMUX_CONFIG_SION, 0x0720, 2, MX6SL_I2C_PAD_CTRL)
+#define MX6SL_PAD_I2C1_SDA__UART1_CTS \
+ IOMUX_PAD(0x0450, 0x0160, 1, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_I2C1_SDA__UART1_RTS \
+ IOMUX_PAD(0x0450, 0x0160, 1, 0x07F8, 1, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_I2C1_SDA__ECSPI3_SS3 \
+ IOMUX_PAD(0x0450, 0x0160, 2, 0x06CC, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_I2C1_SDA__FEC_TX_EN \
+ IOMUX_PAD(0x0450, 0x0160, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_I2C1_SDA__USDHC3_VSELECT \
+ IOMUX_PAD(0x0450, 0x0160, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_I2C1_SDA__GPIO_3_13 \
+ IOMUX_PAD(0x0450, 0x0160, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_I2C1_SDA__ECSPI1_SS2 \
+ IOMUX_PAD(0x0450, 0x0160, 6, 0x0694, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_I2C1_SDA__PL301_SIM_MX6SL_PER1_HSIZE_1 \
+ IOMUX_PAD(0x0450, 0x0160, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_I2C2_SCL__I2C2_SCL \
+ IOMUX_PAD(0x0454, 0x0164, 0 | IOMUX_CONFIG_SION, 0x0724, 1, MX6SL_I2C_PAD_CTRL)
+#define MX6SL_PAD_I2C2_SCL__AUDMUX_AUD4_RXFS \
+ IOMUX_PAD(0x0454, 0x0164, 1, 0x05F0, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_I2C2_SCL__SPDIF_IN1 \
+ IOMUX_PAD(0x0454, 0x0164, 2, 0x07F0, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_I2C2_SCL__FEC_TDATA_1 \
+ IOMUX_PAD(0x0454, 0x0164, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_I2C2_SCL__USDHC3_WP \
+ IOMUX_PAD(0x0454, 0x0164, 4, 0x084C, 2, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_I2C2_SCL__GPIO_3_14 \
+ IOMUX_PAD(0x0454, 0x0164, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_I2C2_SCL__ECSPI1_RDY \
+ IOMUX_PAD(0x0454, 0x0164, 6, 0x0680, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_I2C2_SCL__PL301_SIM_MX6SL_PER1_HSIZE_2 \
+ IOMUX_PAD(0x0454, 0x0164, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_I2C2_SDA__I2C2_SDA \
+ IOMUX_PAD(0x0458, 0x0168, 0 | IOMUX_CONFIG_SION, 0x0728, 1, MX6SL_I2C_PAD_CTRL)
+#define MX6SL_PAD_I2C2_SDA__AUDMUX_AUD4_RXC \
+ IOMUX_PAD(0x0458, 0x0168, 1, 0x05EC, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_I2C2_SDA__SPDIF_OUT1 \
+ IOMUX_PAD(0x0458, 0x0168, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_I2C2_SDA__FEC_REF_OUT \
+ IOMUX_PAD(0x0458, 0x0168, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_I2C2_SDA__USDHC3_CD \
+ IOMUX_PAD(0x0458, 0x0168, 4, 0x0838, 2, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_I2C2_SDA__GPIO_3_15 \
+ IOMUX_PAD(0x0458, 0x0168, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_I2C2_SDA__ANATOP_ANATOP_TESTO_0 \
+ IOMUX_PAD(0x0458, 0x0168, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_I2C2_SDA__PL301_SIM_MX6SL_PER1_HWRITE \
+ IOMUX_PAD(0x0458, 0x0168, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_JTAG_MOD__SJC_MOD \
+ IOMUX_PAD(0x045C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_JTAG_TCK__SJC_TCK \
+ IOMUX_PAD(0x0460, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_JTAG_TDI__SJC_TDI \
+ IOMUX_PAD(0x0464, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_JTAG_TDO__SJC_TDO \
+ IOMUX_PAD(0x0468, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_JTAG_TMS__SJC_TMS \
+ IOMUX_PAD(0x046C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_JTAG_TRSTB__SJC_TRSTB \
+ IOMUX_PAD(0x0470, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_KEY_COL0__KPP_COL_0 \
+ IOMUX_PAD(0x0474, 0x016C, 0, 0x0734, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL0__I2C2_SCL \
+ IOMUX_PAD(0x0474, 0x016C, 1 | IOMUX_CONFIG_SION, 0x0724, 2, MX6SL_I2C_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL0__LCDIF_DAT_0 \
+ IOMUX_PAD(0x0474, 0x016C, 2, 0x0778, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL0__WEIM_WEIM_DA_A_0 \
+ IOMUX_PAD(0x0474, 0x016C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL0__USDHC1_CD \
+ IOMUX_PAD(0x0474, 0x016C, 4, 0x0828, 2, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL0__GPIO_3_24 \
+ IOMUX_PAD(0x0474, 0x016C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL0__MSHC_SCLK \
+ IOMUX_PAD(0x0474, 0x016C, 6, 0x07E8, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL0__TPSMP_HDATA_0 \
+ IOMUX_PAD(0x0474, 0x016C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_KEY_COL1__KPP_COL_1 \
+ IOMUX_PAD(0x0478, 0x0170, 0, 0x0738, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL1__ECSPI4_MOSI \
+ IOMUX_PAD(0x0478, 0x0170, 1, 0x06D8, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL1__LCDIF_DAT_2 \
+ IOMUX_PAD(0x0478, 0x0170, 2, 0x0780, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL1__WEIM_WEIM_DA_A_2 \
+ IOMUX_PAD(0x0478, 0x0170, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL1__USDHC3_DAT4 \
+ IOMUX_PAD(0x0478, 0x0170, 4, 0x083C, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL1__GPIO_3_26 \
+ IOMUX_PAD(0x0478, 0x0170, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL1__MSHC_DATA_0 \
+ IOMUX_PAD(0x0478, 0x0170, 6, 0x07D8, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL1__TPSMP_HDATA_2 \
+ IOMUX_PAD(0x0478, 0x0170, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_KEY_COL2__KPP_COL_2 \
+ IOMUX_PAD(0x047C, 0x0174, 0, 0x073C, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL2__ECSPI4_SS0 \
+ IOMUX_PAD(0x047C, 0x0174, 1, 0x06DC, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL2__LCDIF_DAT_4 \
+ IOMUX_PAD(0x047C, 0x0174, 2, 0x0788, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL2__WEIM_WEIM_DA_A_4 \
+ IOMUX_PAD(0x047C, 0x0174, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL2__USDHC3_DAT6 \
+ IOMUX_PAD(0x047C, 0x0174, 4, 0x0844, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL2__GPIO_3_28 \
+ IOMUX_PAD(0x047C, 0x0174, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL2__MSHC_DATA_2 \
+ IOMUX_PAD(0x047C, 0x0174, 6, 0x07E0, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL2__TPSMP_HDATA_4 \
+ IOMUX_PAD(0x047C, 0x0174, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_KEY_COL3__KPP_COL_3 \
+ IOMUX_PAD(0x0480, 0x0178, 0, 0x0740, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL3__AUDMUX_AUD6_RXFS \
+ IOMUX_PAD(0x0480, 0x0178, 1, 0x0620, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL3__LCDIF_DAT_6 \
+ IOMUX_PAD(0x0480, 0x0178, 2, 0x0790, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL3__WEIM_WEIM_DA_A_6 \
+ IOMUX_PAD(0x0480, 0x0178, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL3__USDHC4_DAT6 \
+ IOMUX_PAD(0x0480, 0x0178, 4, 0x0874, 1, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL3__GPIO_3_30 \
+ IOMUX_PAD(0x0480, 0x0178, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL3__USDHC1_RST \
+ IOMUX_PAD(0x0480, 0x0178, 6, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL3__TPSMP_HDATA_6 \
+ IOMUX_PAD(0x0480, 0x0178, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_KEY_COL4__KPP_COL_4 \
+ IOMUX_PAD(0x0484, 0x017C, 0, 0x0744, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL4__AUDMUX_AUD6_RXD \
+ IOMUX_PAD(0x0484, 0x017C, 1, 0x0614, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL4__LCDIF_DAT_8 \
+ IOMUX_PAD(0x0484, 0x017C, 2, 0x0798, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL4__WEIM_WEIM_DA_A_8 \
+ IOMUX_PAD(0x0484, 0x017C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL4__USDHC4_CLK \
+ IOMUX_PAD(0x0484, 0x017C, 4, 0x0850, 2, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL4__GPIO_4_0 \
+ IOMUX_PAD(0x0484, 0x017C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL4__USB_USBOTG1_PWR \
+ IOMUX_PAD(0x0484, 0x017C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL4__TPSMP_HDATA_8 \
+ IOMUX_PAD(0x0484, 0x017C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_KEY_COL5__KPP_COL_5 \
+ IOMUX_PAD(0x0488, 0x0180, 0, 0x0748, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL5__AUDMUX_AUD6_TXFS \
+ IOMUX_PAD(0x0488, 0x0180, 1, 0x0628, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL5__LCDIF_DAT_10 \
+ IOMUX_PAD(0x0488, 0x0180, 2, 0x07A0, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL5__WEIM_WEIM_DA_A_10 \
+ IOMUX_PAD(0x0488, 0x0180, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL5__USDHC4_DAT0 \
+ IOMUX_PAD(0x0488, 0x0180, 4, 0x085C, 2, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL5__GPIO_4_2 \
+ IOMUX_PAD(0x0488, 0x0180, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL5__USB_USBOTG2_PWR \
+ IOMUX_PAD(0x0488, 0x0180, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL5__TPSMP_HDATA_10 \
+ IOMUX_PAD(0x0488, 0x0180, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_KEY_COL6__KPP_COL_6 \
+ IOMUX_PAD(0x048C, 0x0184, 0, 0x074C, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL6__UART4_TXD \
+ IOMUX_PAD(0x048C, 0x0184, 1, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL6__UART4_RXD \
+ IOMUX_PAD(0x048C, 0x0184, 1, 0x0814, 2, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL6__LCDIF_DAT_12 \
+ IOMUX_PAD(0x048C, 0x0184, 2, 0x07A8, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL6__WEIM_WEIM_DA_A_12 \
+ IOMUX_PAD(0x048C, 0x0184, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL6__USDHC4_DAT2 \
+ IOMUX_PAD(0x048C, 0x0184, 4, 0x0864, 2, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL6__GPIO_4_4 \
+ IOMUX_PAD(0x048C, 0x0184, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL6__USDHC3_RST \
+ IOMUX_PAD(0x048C, 0x0184, 6, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL6__TPSMP_HDATA_12 \
+ IOMUX_PAD(0x048C, 0x0184, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_KEY_COL7__KPP_COL_7 \
+ IOMUX_PAD(0x0490, 0x0188, 0, 0x0750, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL7__UART4_CTS \
+ IOMUX_PAD(0x0490, 0x0188, 1, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL7__UART4_RTS \
+ IOMUX_PAD(0x0490, 0x0188, 1, 0x0810, 2, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL7__LCDIF_DAT_14 \
+ IOMUX_PAD(0x0490, 0x0188, 2, 0x07B0, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL7__WEIM_WEIM_DA_A_14 \
+ IOMUX_PAD(0x0490, 0x0188, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL7__USDHC4_DAT4 \
+ IOMUX_PAD(0x0490, 0x0188, 4, 0x086C, 1, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL7__GPIO_4_6 \
+ IOMUX_PAD(0x0490, 0x0188, 5, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL7__USDHC1_WP \
+ IOMUX_PAD(0x0490, 0x0188, 6, 0x082C, 2, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_KEY_COL7__TPSMP_HDATA_14 \
+ IOMUX_PAD(0x0490, 0x0188, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_KEY_ROW0__KPP_ROW_0 \
+ IOMUX_PAD(0x0494, 0x018C, 0, 0x0754, 0, MX6SL_KEYPAD_CTRL)
+#define MX6SL_PAD_KEY_ROW0__I2C2_SDA \
+ IOMUX_PAD(0x0494, 0x018C, 1 | IOMUX_CONFIG_SION, 0x0728, 2, MX6SL_I2C_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW0__LCDIF_DAT_1 \
+ IOMUX_PAD(0x0494, 0x018C, 2, 0x077C, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW0__WEIM_WEIM_DA_A_1 \
+ IOMUX_PAD(0x0494, 0x018C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW0__USDHC1_WP \
+ IOMUX_PAD(0x0494, 0x018C, 4, 0x082C, 3, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW0__GPIO_3_25 \
+ IOMUX_PAD(0x0494, 0x018C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW0__MSHC_BS \
+ IOMUX_PAD(0x0494, 0x018C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW0__TPSMP_HDATA_1 \
+ IOMUX_PAD(0x0494, 0x018C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_KEY_ROW1__KPP_ROW_1 \
+ IOMUX_PAD(0x0498, 0x0190, 0, 0x0758, 0, MX6SL_KEYPAD_CTRL)
+#define MX6SL_PAD_KEY_ROW1__ECSPI4_MISO \
+ IOMUX_PAD(0x0498, 0x0190, 1, 0x06D4, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW1__LCDIF_DAT_3 \
+ IOMUX_PAD(0x0498, 0x0190, 2, 0x0784, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW1__WEIM_WEIM_DA_A_3 \
+ IOMUX_PAD(0x0498, 0x0190, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW1__USDHC3_DAT5 \
+ IOMUX_PAD(0x0498, 0x0190, 4, 0x0840, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW1__GPIO_3_27 \
+ IOMUX_PAD(0x0498, 0x0190, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW1__MSHC_DATA_1 \
+ IOMUX_PAD(0x0498, 0x0190, 6, 0x07DC, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW1__TPSMP_HDATA_3 \
+ IOMUX_PAD(0x0498, 0x0190, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_KEY_ROW2__KPP_ROW_2 \
+ IOMUX_PAD(0x049C, 0x0194, 0, 0x075C, 0, MX6SL_KEYPAD_CTRL)
+#define MX6SL_PAD_KEY_ROW2__ECSPI4_SCLK \
+ IOMUX_PAD(0x049C, 0x0194, 1, 0x06D0, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW2__LCDIF_DAT_5 \
+ IOMUX_PAD(0x049C, 0x0194, 2, 0x078C, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW2__WEIM_WEIM_DA_A_5 \
+ IOMUX_PAD(0x049C, 0x0194, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW2__USDHC3_DAT7 \
+ IOMUX_PAD(0x049C, 0x0194, 4, 0x0848, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW2__GPIO_3_29 \
+ IOMUX_PAD(0x049C, 0x0194, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW2__MSHC_DATA_3 \
+ IOMUX_PAD(0x049C, 0x0194, 6, 0x07E4, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW2__TPSMP_HDATA_5 \
+ IOMUX_PAD(0x049C, 0x0194, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_KEY_ROW3__KPP_ROW_3 \
+ IOMUX_PAD(0x04A0, 0x0198, 0, 0x0760, 0, MX6SL_KEYPAD_CTRL)
+#define MX6SL_PAD_KEY_ROW3__AUDMUX_AUD6_RXC \
+ IOMUX_PAD(0x04A0, 0x0198, 1, 0x061C, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW3__LCDIF_DAT_7 \
+ IOMUX_PAD(0x04A0, 0x0198, 2, 0x0794, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW3__WEIM_WEIM_DA_A_7 \
+ IOMUX_PAD(0x04A0, 0x0198, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW3__USDHC4_DAT7 \
+ IOMUX_PAD(0x04A0, 0x0198, 4, 0x0878, 1, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW3__GPIO_3_31 \
+ IOMUX_PAD(0x04A0, 0x0198, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW3__USDHC1_VSELECT \
+ IOMUX_PAD(0x04A0, 0x0198, 6, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW3__TPSMP_HDATA_7 \
+ IOMUX_PAD(0x04A0, 0x0198, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_KEY_ROW4__KPP_ROW_4 \
+ IOMUX_PAD(0x04A4, 0x019C, 0, 0x0764, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW4__AUDMUX_AUD6_TXC \
+ IOMUX_PAD(0x04A4, 0x019C, 1, 0x0624, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW4__LCDIF_DAT_9 \
+ IOMUX_PAD(0x04A4, 0x019C, 2, 0x079C, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW4__WEIM_WEIM_DA_A_9 \
+ IOMUX_PAD(0x04A4, 0x019C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW4__USDHC4_CMD \
+ IOMUX_PAD(0x04A4, 0x019C, 4, 0x0858, 2, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW4__GPIO_4_1 \
+ IOMUX_PAD(0x04A4, 0x019C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW4__USB_USBOTG1_OC \
+ IOMUX_PAD(0x04A4, 0x019C, 6, 0x0824, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW4__TPSMP_HDATA_9 \
+ IOMUX_PAD(0x04A4, 0x019C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_KEY_ROW5__KPP_ROW_5 \
+ IOMUX_PAD(0x04A8, 0x01A0, 0, 0x0768, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW5__AUDMUX_AUD6_TXD \
+ IOMUX_PAD(0x04A8, 0x01A0, 1, 0x0618, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW5__LCDIF_DAT_11 \
+ IOMUX_PAD(0x04A8, 0x01A0, 2, 0x07A4, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW5__WEIM_WEIM_DA_A_11 \
+ IOMUX_PAD(0x04A8, 0x01A0, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW5__USDHC4_DAT1 \
+ IOMUX_PAD(0x04A8, 0x01A0, 4, 0x0860, 2, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW5__GPIO_4_3 \
+ IOMUX_PAD(0x04A8, 0x01A0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW5__USB_USBOTG2_OC \
+ IOMUX_PAD(0x04A8, 0x01A0, 6, 0x0820, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW5__TPSMP_HDATA_11 \
+ IOMUX_PAD(0x04A8, 0x01A0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_KEY_ROW6__KPP_ROW_6 \
+ IOMUX_PAD(0x04AC, 0x01A4, 0, 0x076C, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW6__UART4_TXD \
+ IOMUX_PAD(0x04AC, 0x01A4, 1, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW6__UART4_RXD \
+ IOMUX_PAD(0x04AC, 0x01A4, 1, 0x0814, 3, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW6__LCDIF_DAT_13 \
+ IOMUX_PAD(0x04AC, 0x01A4, 2, 0x07AC, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW6__WEIM_WEIM_DA_A_13 \
+ IOMUX_PAD(0x04AC, 0x01A4, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW6__USDHC4_DAT3 \
+ IOMUX_PAD(0x04AC, 0x01A4, 4, 0x0868, 2, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW6__GPIO_4_5 \
+ IOMUX_PAD(0x04AC, 0x01A4, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW6__USDHC3_VSELECT \
+ IOMUX_PAD(0x04AC, 0x01A4, 6, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW6__TPSMP_HDATA_13 \
+ IOMUX_PAD(0x04AC, 0x01A4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_KEY_ROW7__KPP_ROW_7 \
+ IOMUX_PAD(0x04B0, 0x01A8, 0, 0x0770, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW7__UART4_CTS \
+ IOMUX_PAD(0x04B0, 0x01A8, 1, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW7__UART4_RTS \
+ IOMUX_PAD(0x04B0, 0x01A8, 1, 0x0810, 3, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW7__LCDIF_DAT_15 \
+ IOMUX_PAD(0x04B0, 0x01A8, 2, 0x07B4, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW7__WEIM_WEIM_DA_A_15 \
+ IOMUX_PAD(0x04B0, 0x01A8, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW7__USDHC4_DAT5 \
+ IOMUX_PAD(0x04B0, 0x01A8, 4, 0x0870, 1, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW7__GPIO_4_7 \
+ IOMUX_PAD(0x04B0, 0x01A8, 5, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW7__USDHC1_CD \
+ IOMUX_PAD(0x04B0, 0x01A8, 6, 0x0828, 3, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_KEY_ROW7__TPSMP_HDATA_15 \
+ IOMUX_PAD(0x04B0, 0x01A8, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_LCD_CLK__LCDIF_CLK \
+ IOMUX_PAD(0x04B4, 0x01AC, 0, 0x0000, 0, MX6SL_LCDIF_PAD_CTRL)
+#define MX6SL_PAD_LCD_CLK__USDHC4_DAT4 \
+ IOMUX_PAD(0x04B4, 0x01AC, 1, 0x086C, 2, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_LCD_CLK__LCDIF_WR_RWN \
+ IOMUX_PAD(0x04B4, 0x01AC, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_CLK__WEIM_WEIM_RW \
+ IOMUX_PAD(0x04B4, 0x01AC, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_CLK__PWM4_PWMO \
+ IOMUX_PAD(0x04B4, 0x01AC, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_CLK__GPIO_2_15 \
+ IOMUX_PAD(0x04B4, 0x01AC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_CLK__SRC_EARLY_RST \
+ IOMUX_PAD(0x04B4, 0x01AC, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_CLK__TPSMP_HTRANS_0 \
+ IOMUX_PAD(0x04B4, 0x01AC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_LCD_DAT0__LCDIF_DAT_0 \
+ IOMUX_PAD(0x04B8, 0x01B0, 0, 0x0778, 1, MX6SL_LCDIF_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT0__ECSPI1_MOSI \
+ IOMUX_PAD(0x04B8, 0x01B0, 1, 0x0688, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT0__ANATOP_USBOTG2_ID \
+ IOMUX_PAD(0x04B8, 0x01B0, 2, 0x05E0, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT0__PWM1_PWMO \
+ IOMUX_PAD(0x04B8, 0x01B0, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT0__UART5_DTR \
+ IOMUX_PAD(0x04B8, 0x01B0, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT0__GPIO_2_20 \
+ IOMUX_PAD(0x04B8, 0x01B0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT0__KITTEN_TRACE_0 \
+ IOMUX_PAD(0x04B8, 0x01B0, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT0__SRC_BT_CFG_0 \
+ IOMUX_PAD(0x04B8, 0x01B0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_LCD_DAT1__LCDIF_DAT_1 \
+ IOMUX_PAD(0x04BC, 0x01B4, 0, 0x077C, 1, MX6SL_LCDIF_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT1__ECSPI1_MISO \
+ IOMUX_PAD(0x04BC, 0x01B4, 1, 0x0684, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT1__ANATOP_USBOTG1_ID \
+ IOMUX_PAD(0x04BC, 0x01B4, 2, 0x05DC, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT1__PWM2_PWMO \
+ IOMUX_PAD(0x04BC, 0x01B4, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT1__AUDMUX_AUD4_RXFS \
+ IOMUX_PAD(0x04BC, 0x01B4, 4, 0x05F0, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT1__GPIO_2_21 \
+ IOMUX_PAD(0x04BC, 0x01B4, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT1__KITTEN_TRACE_1 \
+ IOMUX_PAD(0x04BC, 0x01B4, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT1__SRC_BT_CFG_1 \
+ IOMUX_PAD(0x04BC, 0x01B4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_LCD_DAT10__LCDIF_DAT_10 \
+ IOMUX_PAD(0x04C0, 0x01B8, 0, 0x07A0, 1, MX6SL_LCDIF_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT10__KPP_COL_1 \
+ IOMUX_PAD(0x04C0, 0x01B8, 1, 0x0738, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT10__CSI_D_7 \
+ IOMUX_PAD(0x04C0, 0x01B8, 2, 0x064C, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT10__WEIM_WEIM_D_4 \
+ IOMUX_PAD(0x04C0, 0x01B8, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT10__ECSPI2_MISO \
+ IOMUX_PAD(0x04C0, 0x01B8, 4, 0x06A0, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT10__GPIO_2_30 \
+ IOMUX_PAD(0x04C0, 0x01B8, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT10__KITTEN_TRACE_10 \
+ IOMUX_PAD(0x04C0, 0x01B8, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT10__SRC_BT_CFG_10 \
+ IOMUX_PAD(0x04C0, 0x01B8, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_LCD_DAT11__LCDIF_DAT_11 \
+ IOMUX_PAD(0x04C4, 0x01BC, 0, 0x07A4, 1, MX6SL_LCDIF_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT11__KPP_ROW_1 \
+ IOMUX_PAD(0x04C4, 0x01BC, 1, 0x0758, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT11__CSI_D_6 \
+ IOMUX_PAD(0x04C4, 0x01BC, 2, 0x0648, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT11__WEIM_WEIM_D_5 \
+ IOMUX_PAD(0x04C4, 0x01BC, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT11__ECSPI2_SS1 \
+ IOMUX_PAD(0x04C4, 0x01BC, 4, 0x06AC, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT11__GPIO_2_31 \
+ IOMUX_PAD(0x04C4, 0x01BC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT11__KITTEN_TRACE_11 \
+ IOMUX_PAD(0x04C4, 0x01BC, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT11__SRC_BT_CFG_11 \
+ IOMUX_PAD(0x04C4, 0x01BC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_LCD_DAT12__LCDIF_DAT_12 \
+ IOMUX_PAD(0x04C8, 0x01C0, 0, 0x07A8, 1, MX6SL_LCDIF_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT12__KPP_COL_2 \
+ IOMUX_PAD(0x04C8, 0x01C0, 1, 0x073C, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT12__CSI_D_5 \
+ IOMUX_PAD(0x04C8, 0x01C0, 2, 0x0644, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT12__WEIM_WEIM_D_6 \
+ IOMUX_PAD(0x04C8, 0x01C0, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT12__UART5_CTS \
+ IOMUX_PAD(0x04C8, 0x01C0, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT12__UART5_RTS \
+ IOMUX_PAD(0x04C8, 0x01C0, 4, 0x0818, 2, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT12__GPIO_3_0 \
+ IOMUX_PAD(0x04C8, 0x01C0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT12__KITTEN_TRACE_12 \
+ IOMUX_PAD(0x04C8, 0x01C0, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT12__SRC_BT_CFG_12 \
+ IOMUX_PAD(0x04C8, 0x01C0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_LCD_DAT13__LCDIF_DAT_13 \
+ IOMUX_PAD(0x04CC, 0x01C4, 0, 0x07AC, 1, MX6SL_LCDIF_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT13__KPP_ROW_2 \
+ IOMUX_PAD(0x04CC, 0x01C4, 1, 0x075C, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT13__CSI_D_4 \
+ IOMUX_PAD(0x04CC, 0x01C4, 2, 0x0640, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT13__WEIM_WEIM_D_7 \
+ IOMUX_PAD(0x04CC, 0x01C4, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT13__UART5_CTS \
+ IOMUX_PAD(0x04CC, 0x01C4, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT13__UART5_RTS \
+ IOMUX_PAD(0x04CC, 0x01C4, 4, 0x0818, 3, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT13__GPIO_3_1 \
+ IOMUX_PAD(0x04CC, 0x01C4, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT13__KITTEN_TRACE_13 \
+ IOMUX_PAD(0x04CC, 0x01C4, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT13__SRC_BT_CFG_13 \
+ IOMUX_PAD(0x04CC, 0x01C4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_LCD_DAT14__LCDIF_DAT_14 \
+ IOMUX_PAD(0x04D0, 0x01C8, 0, 0x07B0, 1, MX6SL_LCDIF_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT14__KPP_COL_3 \
+ IOMUX_PAD(0x04D0, 0x01C8, 1, 0x0740, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT14__CSI_D_3 \
+ IOMUX_PAD(0x04D0, 0x01C8, 2, 0x063C, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT14__WEIM_WEIM_D_8 \
+ IOMUX_PAD(0x04D0, 0x01C8, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT14__UART5_TXD \
+ IOMUX_PAD(0x04D0, 0x01C8, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT14__UART5_RXD \
+ IOMUX_PAD(0x04D0, 0x01C8, 4, 0x081C, 2, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT14__GPIO_3_2 \
+ IOMUX_PAD(0x04D0, 0x01C8, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT14__KITTEN_TRACE_14 \
+ IOMUX_PAD(0x04D0, 0x01C8, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT14__SRC_BT_CFG_14 \
+ IOMUX_PAD(0x04D0, 0x01C8, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_LCD_DAT15__LCDIF_DAT_15 \
+ IOMUX_PAD(0x04D4, 0x01CC, 0, 0x07B4, 1, MX6SL_LCDIF_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT15__KPP_ROW_3 \
+ IOMUX_PAD(0x04D4, 0x01CC, 1, 0x0760, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT15__CSI_D_2 \
+ IOMUX_PAD(0x04D4, 0x01CC, 2, 0x0638, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT15__WEIM_WEIM_D_9 \
+ IOMUX_PAD(0x04D4, 0x01CC, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT15__UART5_TXD \
+ IOMUX_PAD(0x04D4, 0x01CC, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT15__UART5_RXD \
+ IOMUX_PAD(0x04D4, 0x01CC, 4, 0x081C, 3, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT15__GPIO_3_3 \
+ IOMUX_PAD(0x04D4, 0x01CC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT15__KITTEN_TRACE_15 \
+ IOMUX_PAD(0x04D4, 0x01CC, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT15__SRC_BT_CFG_15 \
+ IOMUX_PAD(0x04D4, 0x01CC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_LCD_DAT16__LCDIF_DAT_16 \
+ IOMUX_PAD(0x04D8, 0x01D0, 0, 0x07B8, 1, MX6SL_LCDIF_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT16__KPP_COL_4 \
+ IOMUX_PAD(0x04D8, 0x01D0, 1, 0x0744, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT16__CSI_D_1 \
+ IOMUX_PAD(0x04D8, 0x01D0, 2, 0x0634, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT16__WEIM_WEIM_D_10 \
+ IOMUX_PAD(0x04D8, 0x01D0, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT16__I2C2_SCL \
+ IOMUX_PAD(0x04D8, 0x01D0, 4 | IOMUX_CONFIG_SION, 0x0724, 3, MX6SL_I2C_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT16__GPIO_3_4 \
+ IOMUX_PAD(0x04D8, 0x01D0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT16__KITTEN_TRACE_16 \
+ IOMUX_PAD(0x04D8, 0x01D0, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT16__SRC_BT_CFG_24 \
+ IOMUX_PAD(0x04D8, 0x01D0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_LCD_DAT17__LCDIF_DAT_17 \
+ IOMUX_PAD(0x04DC, 0x01D4, 0, 0x07BC, 1, MX6SL_LCDIF_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT17__KPP_ROW_4 \
+ IOMUX_PAD(0x04DC, 0x01D4, 1, 0x0764, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT17__CSI_D_0 \
+ IOMUX_PAD(0x04DC, 0x01D4, 2, 0x0630, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT17__WEIM_WEIM_D_11 \
+ IOMUX_PAD(0x04DC, 0x01D4, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT17__I2C2_SDA \
+ IOMUX_PAD(0x04DC, 0x01D4, 4 | IOMUX_CONFIG_SION, 0x0728, 3, MX6SL_I2C_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT17__GPIO_3_5 \
+ IOMUX_PAD(0x04DC, 0x01D4, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT17__KITTEN_TRACE_17 \
+ IOMUX_PAD(0x04DC, 0x01D4, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT17__SRC_BT_CFG_25 \
+ IOMUX_PAD(0x04DC, 0x01D4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_LCD_DAT18__LCDIF_DAT_18 \
+ IOMUX_PAD(0x04E0, 0x01D8, 0, 0x07C0, 1, MX6SL_LCDIF_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT18__KPP_COL_5 \
+ IOMUX_PAD(0x04E0, 0x01D8, 1, 0x0748, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT18__CSI_D_15 \
+ IOMUX_PAD(0x04E0, 0x01D8, 2, 0x066C, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT18__WEIM_WEIM_D_12 \
+ IOMUX_PAD(0x04E0, 0x01D8, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT18__GPT_CAPIN1 \
+ IOMUX_PAD(0x04E0, 0x01D8, 4, 0x0710, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT18__GPIO_3_6 \
+ IOMUX_PAD(0x04E0, 0x01D8, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT18__KITTEN_TRACE_18 \
+ IOMUX_PAD(0x04E0, 0x01D8, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT18__SRC_BT_CFG_26 \
+ IOMUX_PAD(0x04E0, 0x01D8, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_LCD_DAT19__LCDIF_DAT_19 \
+ IOMUX_PAD(0x04E4, 0x01DC, 0, 0x07C4, 1, MX6SL_LCDIF_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT19__KPP_ROW_5 \
+ IOMUX_PAD(0x04E4, 0x01DC, 1, 0x0768, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT19__CSI_D_14 \
+ IOMUX_PAD(0x04E4, 0x01DC, 2, 0x0668, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT19__WEIM_WEIM_D_13 \
+ IOMUX_PAD(0x04E4, 0x01DC, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT19__GPT_CAPIN2 \
+ IOMUX_PAD(0x04E4, 0x01DC, 4, 0x0714, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT19__GPIO_3_7 \
+ IOMUX_PAD(0x04E4, 0x01DC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT19__KITTEN_TRACE_19 \
+ IOMUX_PAD(0x04E4, 0x01DC, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT19__SRC_BT_CFG_27 \
+ IOMUX_PAD(0x04E4, 0x01DC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_LCD_DAT2__LCDIF_DAT_2 \
+ IOMUX_PAD(0x04E8, 0x01E0, 0, 0x0780, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT2__ECSPI1_SS0 \
+ IOMUX_PAD(0x04E8, 0x01E0, 1, 0x068C, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT2__EPIT2_EPITO \
+ IOMUX_PAD(0x04E8, 0x01E0, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT2__PWM3_PWMO \
+ IOMUX_PAD(0x04E8, 0x01E0, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT2__AUDMUX_AUD4_RXC \
+ IOMUX_PAD(0x04E8, 0x01E0, 4, 0x05EC, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT2__GPIO_2_22 \
+ IOMUX_PAD(0x04E8, 0x01E0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT2__KITTEN_TRACE_2 \
+ IOMUX_PAD(0x04E8, 0x01E0, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT2__SRC_BT_CFG_2 \
+ IOMUX_PAD(0x04E8, 0x01E0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_LCD_DAT20__LCDIF_DAT_20 \
+ IOMUX_PAD(0x04EC, 0x01E4, 0, 0x07C8, 1, MX6SL_LCDIF_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT20__KPP_COL_6 \
+ IOMUX_PAD(0x04EC, 0x01E4, 1, 0x074C, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT20__CSI_D_13 \
+ IOMUX_PAD(0x04EC, 0x01E4, 2, 0x0664, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT20__WEIM_WEIM_D_14 \
+ IOMUX_PAD(0x04EC, 0x01E4, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT20__GPT_CMPOUT1 \
+ IOMUX_PAD(0x04EC, 0x01E4, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT20__GPIO_3_8 \
+ IOMUX_PAD(0x04EC, 0x01E4, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT20__KITTEN_TRACE_20 \
+ IOMUX_PAD(0x04EC, 0x01E4, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT20__SRC_BT_CFG_28 \
+ IOMUX_PAD(0x04EC, 0x01E4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_LCD_DAT21__LCDIF_DAT_21 \
+ IOMUX_PAD(0x04F0, 0x01E8, 0, 0x07CC, 1, MX6SL_LCDIF_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT21__KPP_ROW_6 \
+ IOMUX_PAD(0x04F0, 0x01E8, 1, 0x076C, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT21__CSI_D_12 \
+ IOMUX_PAD(0x04F0, 0x01E8, 2, 0x0660, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT21__WEIM_WEIM_D_15 \
+ IOMUX_PAD(0x04F0, 0x01E8, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT21__GPT_CMPOUT2 \
+ IOMUX_PAD(0x04F0, 0x01E8, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT21__GPIO_3_9 \
+ IOMUX_PAD(0x04F0, 0x01E8, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT21__KITTEN_TRACE_21 \
+ IOMUX_PAD(0x04F0, 0x01E8, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT21__SRC_BT_CFG_29 \
+ IOMUX_PAD(0x04F0, 0x01E8, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_LCD_DAT22__LCDIF_DAT_22 \
+ IOMUX_PAD(0x04F4, 0x01EC, 0, 0x07D0, 1, MX6SL_LCDIF_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT22__KPP_COL_7 \
+ IOMUX_PAD(0x04F4, 0x01EC, 1, 0x0750, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT22__CSI_D_11 \
+ IOMUX_PAD(0x04F4, 0x01EC, 2, 0x065C, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT22__WEIM_WEIM_EB_3 \
+ IOMUX_PAD(0x04F4, 0x01EC, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT22__GPT_CMPOUT3 \
+ IOMUX_PAD(0x04F4, 0x01EC, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT22__GPIO_3_10 \
+ IOMUX_PAD(0x04F4, 0x01EC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT22__KITTEN_TRACE_22 \
+ IOMUX_PAD(0x04F4, 0x01EC, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT22__SRC_BT_CFG_30 \
+ IOMUX_PAD(0x04F4, 0x01EC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_LCD_DAT23__LCDIF_DAT_23 \
+ IOMUX_PAD(0x04F8, 0x01F0, 0, 0x07D4, 1, MX6SL_LCDIF_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT23__KPP_ROW_7 \
+ IOMUX_PAD(0x04F8, 0x01F0, 1, 0x0770, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT23__CSI_D_10 \
+ IOMUX_PAD(0x04F8, 0x01F0, 2, 0x0658, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT23__WEIM_WEIM_EB_2 \
+ IOMUX_PAD(0x04F8, 0x01F0, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT23__GPT_CLKIN \
+ IOMUX_PAD(0x04F8, 0x01F0, 4, 0x0718, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT23__GPIO_3_11 \
+ IOMUX_PAD(0x04F8, 0x01F0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT23__KITTEN_TRACE_23 \
+ IOMUX_PAD(0x04F8, 0x01F0, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT23__SRC_BT_CFG_31 \
+ IOMUX_PAD(0x04F8, 0x01F0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_LCD_DAT3__LCDIF_DAT_3 \
+ IOMUX_PAD(0x04FC, 0x01F4, 0, 0x0784, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT3__ECSPI1_SCLK \
+ IOMUX_PAD(0x04FC, 0x01F4, 1, 0x067C, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT3__UART5_DSR \
+ IOMUX_PAD(0x04FC, 0x01F4, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT3__PWM4_PWMO \
+ IOMUX_PAD(0x04FC, 0x01F4, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT3__AUDMUX_AUD4_RXD \
+ IOMUX_PAD(0x04FC, 0x01F4, 4, 0x05E4, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT3__GPIO_2_23 \
+ IOMUX_PAD(0x04FC, 0x01F4, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT3__KITTEN_TRACE_3 \
+ IOMUX_PAD(0x04FC, 0x01F4, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT3__SRC_BT_CFG_3 \
+ IOMUX_PAD(0x04FC, 0x01F4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_LCD_DAT4__LCDIF_DAT_4 \
+ IOMUX_PAD(0x0500, 0x01F8, 0, 0x0788, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT4__ECSPI1_SS1 \
+ IOMUX_PAD(0x0500, 0x01F8, 1, 0x0690, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT4__CSI_VSYNC \
+ IOMUX_PAD(0x0500, 0x01F8, 2, 0x0678, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT4__WDOG2_WDOG_RST_B_DEB \
+ IOMUX_PAD(0x0500, 0x01F8, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT4__AUDMUX_AUD4_TXC \
+ IOMUX_PAD(0x0500, 0x01F8, 4, 0x05F4, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT4__GPIO_2_24 \
+ IOMUX_PAD(0x0500, 0x01F8, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT4__KITTEN_TRACE_4 \
+ IOMUX_PAD(0x0500, 0x01F8, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT4__SRC_BT_CFG_4 \
+ IOMUX_PAD(0x0500, 0x01F8, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_LCD_DAT5__LCDIF_DAT_5 \
+ IOMUX_PAD(0x0504, 0x01FC, 0, 0x078C, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT5__ECSPI1_SS2 \
+ IOMUX_PAD(0x0504, 0x01FC, 1, 0x0694, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT5__CSI_HSYNC \
+ IOMUX_PAD(0x0504, 0x01FC, 2, 0x0670, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT5__WEIM_WEIM_CS_3 \
+ IOMUX_PAD(0x0504, 0x01FC, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT5__AUDMUX_AUD4_TXFS \
+ IOMUX_PAD(0x0504, 0x01FC, 4, 0x05F8, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT5__GPIO_2_25 \
+ IOMUX_PAD(0x0504, 0x01FC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT5__KITTEN_TRACE_5 \
+ IOMUX_PAD(0x0504, 0x01FC, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT5__SRC_BT_CFG_5 \
+ IOMUX_PAD(0x0504, 0x01FC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_LCD_DAT6__LCDIF_DAT_6 \
+ IOMUX_PAD(0x0508, 0x0200, 0, 0x0790, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT6__ECSPI1_SS3 \
+ IOMUX_PAD(0x0508, 0x0200, 1, 0x0698, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT6__CSI_PIXCLK \
+ IOMUX_PAD(0x0508, 0x0200, 2, 0x0674, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT6__WEIM_WEIM_D_0 \
+ IOMUX_PAD(0x0508, 0x0200, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT6__AUDMUX_AUD4_TXD \
+ IOMUX_PAD(0x0508, 0x0200, 4, 0x05E8, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT6__GPIO_2_26 \
+ IOMUX_PAD(0x0508, 0x0200, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT6__KITTEN_TRACE_6 \
+ IOMUX_PAD(0x0508, 0x0200, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT6__SRC_BT_CFG_6 \
+ IOMUX_PAD(0x0508, 0x0200, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_LCD_DAT7__LCDIF_DAT_7 \
+ IOMUX_PAD(0x050C, 0x0204, 0, 0x0794, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT7__ECSPI1_RDY \
+ IOMUX_PAD(0x050C, 0x0204, 1, 0x0680, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT7__CSI_MCLK \
+ IOMUX_PAD(0x050C, 0x0204, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT7__WEIM_WEIM_D_1 \
+ IOMUX_PAD(0x050C, 0x0204, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT7__AUDMUX_AUDIO_CLK_OUT \
+ IOMUX_PAD(0x050C, 0x0204, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT7__GPIO_2_27 \
+ IOMUX_PAD(0x050C, 0x0204, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT7__KITTEN_TRACE_7 \
+ IOMUX_PAD(0x050C, 0x0204, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT7__SRC_BT_CFG_7 \
+ IOMUX_PAD(0x050C, 0x0204, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_LCD_DAT8__LCDIF_DAT_8 \
+ IOMUX_PAD(0x0510, 0x0208, 0, 0x0798, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT8__KPP_COL_0 \
+ IOMUX_PAD(0x0510, 0x0208, 1, 0x0734, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT8__CSI_D_9 \
+ IOMUX_PAD(0x0510, 0x0208, 2, 0x0654, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT8__WEIM_WEIM_D_2 \
+ IOMUX_PAD(0x0510, 0x0208, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT8__ECSPI2_SCLK \
+ IOMUX_PAD(0x0510, 0x0208, 4, 0x069C, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT8__GPIO_2_28 \
+ IOMUX_PAD(0x0510, 0x0208, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT8__KITTEN_TRACE_8 \
+ IOMUX_PAD(0x0510, 0x0208, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT8__SRC_BT_CFG_8 \
+ IOMUX_PAD(0x0510, 0x0208, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_LCD_DAT9__LCDIF_DAT_9 \
+ IOMUX_PAD(0x0514, 0x020C, 0, 0x079C, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT9__KPP_ROW_0 \
+ IOMUX_PAD(0x0514, 0x020C, 1, 0x0754, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT9__CSI_D_8 \
+ IOMUX_PAD(0x0514, 0x020C, 2, 0x0650, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT9__WEIM_WEIM_D_3 \
+ IOMUX_PAD(0x0514, 0x020C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT9__ECSPI2_MOSI \
+ IOMUX_PAD(0x0514, 0x020C, 4, 0x06A4, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT9__GPIO_2_29 \
+ IOMUX_PAD(0x0514, 0x020C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT9__KITTEN_TRACE_9 \
+ IOMUX_PAD(0x0514, 0x020C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_DAT9__SRC_BT_CFG_9 \
+ IOMUX_PAD(0x0514, 0x020C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_LCD_ENABLE__LCDIF_ENABLE \
+ IOMUX_PAD(0x0518, 0x0210, 0, 0x0000, 0, MX6SL_LCDIF_PAD_CTRL)
+#define MX6SL_PAD_LCD_ENABLE__USDHC4_DAT5 \
+ IOMUX_PAD(0x0518, 0x0210, 1, 0x0870, 2, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_LCD_ENABLE__LCDIF_RD_E \
+ IOMUX_PAD(0x0518, 0x0210, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_ENABLE__WEIM_WEIM_OE \
+ IOMUX_PAD(0x0518, 0x0210, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_ENABLE__UART2_TXD \
+ IOMUX_PAD(0x0518, 0x0210, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_LCD_ENABLE__UART2_RXD \
+ IOMUX_PAD(0x0518, 0x0210, 4, 0x0804, 2, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_LCD_ENABLE__GPIO_2_16 \
+ IOMUX_PAD(0x0518, 0x0210, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_ENABLE__OCOTP_CTRL_WRAPPER_FUSE_LATCHED \
+ IOMUX_PAD(0x0518, 0x0210, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_ENABLE__TPSMP_HTRANS_1 \
+ IOMUX_PAD(0x0518, 0x0210, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_LCD_HSYNC__LCDIF_HSYNC \
+ IOMUX_PAD(0x051C, 0x0214, 0, 0x0774, 0, MX6SL_LCDIF_PAD_CTRL)
+#define MX6SL_PAD_LCD_HSYNC__USDHC4_DAT6 \
+ IOMUX_PAD(0x051C, 0x0214, 1, 0x0874, 2, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_LCD_HSYNC__LCDIF_CS \
+ IOMUX_PAD(0x051C, 0x0214, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_HSYNC__WEIM_WEIM_CS_0 \
+ IOMUX_PAD(0x051C, 0x0214, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_HSYNC__UART2_TXD \
+ IOMUX_PAD(0x051C, 0x0214, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_LCD_HSYNC__UART2_RXD \
+ IOMUX_PAD(0x051C, 0x0214, 4, 0x0804, 3, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_LCD_HSYNC__GPIO_2_17 \
+ IOMUX_PAD(0x051C, 0x0214, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_HSYNC__KITTEN_TRCLK \
+ IOMUX_PAD(0x051C, 0x0214, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_HSYNC__TPSMP_HDATA_16 \
+ IOMUX_PAD(0x051C, 0x0214, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_LCD_RESET__LCDIF_RESET \
+ IOMUX_PAD(0x0520, 0x0218, 0, 0x0000, 0, MX6SL_LCDIF_PAD_CTRL)
+#define MX6SL_PAD_LCD_RESET__WEIM_WEIM_DTACK_B \
+ IOMUX_PAD(0x0520, 0x0218, 1, 0x0880, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_RESET__LCDIF_BUSY \
+ IOMUX_PAD(0x0520, 0x0218, 2, 0x0774, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_RESET__WEIM_WEIM_WAIT \
+ IOMUX_PAD(0x0520, 0x0218, 3, 0x0884, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_RESET__UART2_CTS \
+ IOMUX_PAD(0x0520, 0x0218, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_LCD_RESET__UART2_RTS \
+ IOMUX_PAD(0x0520, 0x0218, 4, 0x0800, 2, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_LCD_RESET__GPIO_2_19 \
+ IOMUX_PAD(0x0520, 0x0218, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_RESET__CCM_PMIC_RDY \
+ IOMUX_PAD(0x0520, 0x0218, 6, 0x062C, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_RESET__TPSMP_HDATA_DIR \
+ IOMUX_PAD(0x0520, 0x0218, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_LCD_VSYNC__LCDIF_VSYNC \
+ IOMUX_PAD(0x0524, 0x021C, 0, 0x0000, 0, MX6SL_LCDIF_PAD_CTRL)
+#define MX6SL_PAD_LCD_VSYNC__USDHC4_DAT7 \
+ IOMUX_PAD(0x0524, 0x021C, 1, 0x0878, 2, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_LCD_VSYNC__LCDIF_RS \
+ IOMUX_PAD(0x0524, 0x021C, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_VSYNC__WEIM_WEIM_CS_1 \
+ IOMUX_PAD(0x0524, 0x021C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_VSYNC__UART2_CTS \
+ IOMUX_PAD(0x0524, 0x021C, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_LCD_VSYNC__UART2_RTS \
+ IOMUX_PAD(0x0524, 0x021C, 4, 0x0800, 3, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_LCD_VSYNC__GPIO_2_18 \
+ IOMUX_PAD(0x0524, 0x021C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_VSYNC__KITTEN_TRCTL \
+ IOMUX_PAD(0x0524, 0x021C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_LCD_VSYNC__TPSMP_HDATA_17 \
+ IOMUX_PAD(0x0524, 0x021C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_POR_B__SRC_POR_B \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_PWM1__PWM1_PWMO \
+ IOMUX_PAD(0x0528, 0x0220, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_PWM1__CCM_CLKO \
+ IOMUX_PAD(0x0528, 0x0220, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_PWM1__AUDMUX_AUDIO_CLK_OUT \
+ IOMUX_PAD(0x0528, 0x0220, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_PWM1__FEC_REF_OUT \
+ IOMUX_PAD(0x0528, 0x0220, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_PWM1__CSI_MCLK \
+ IOMUX_PAD(0x0528, 0x0220, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_PWM1__GPIO_3_23 \
+ IOMUX_PAD(0x0528, 0x0220, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_PWM1__EPIT1_EPITO \
+ IOMUX_PAD(0x0528, 0x0220, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_PWM1__OBSERVE_MUX_OUT_4 \
+ IOMUX_PAD(0x0528, 0x0220, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_REF_CLK_24M__ANATOP_ANATOP_24M_OUT \
+ IOMUX_PAD(0x052C, 0x0224, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_REF_CLK_24M__I2C3_SCL \
+ IOMUX_PAD(0x052C, 0x0224, 1 | IOMUX_CONFIG_SION, 0x072C, 2, MX6SL_I2C_PAD_CTRL)
+#define MX6SL_PAD_REF_CLK_24M__PWM3_PWMO \
+ IOMUX_PAD(0x052C, 0x0224, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_REF_CLK_24M__ANATOP_USBOTG2_ID \
+ IOMUX_PAD(0x052C, 0x0224, 3, 0x05E0, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_REF_CLK_24M__CCM_PMIC_RDY \
+ IOMUX_PAD(0x052C, 0x0224, 4, 0x062C, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_REF_CLK_24M__GPIO_3_21 \
+ IOMUX_PAD(0x052C, 0x0224, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_REF_CLK_24M__USDHC3_WP \
+ IOMUX_PAD(0x052C, 0x0224, 6, 0x084C, 3, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_REF_CLK_24M__TPSMP_HDATA_19 \
+ IOMUX_PAD(0x052C, 0x0224, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_REF_CLK_32K__ANATOP_ANATOP_32K_OUT \
+ IOMUX_PAD(0x0530, 0x0228, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_REF_CLK_32K__I2C3_SDA \
+ IOMUX_PAD(0x0530, 0x0228, 1 | IOMUX_CONFIG_SION, 0x0730, 2, MX6SL_I2C_PAD_CTRL)
+#define MX6SL_PAD_REF_CLK_32K__PWM4_PWMO \
+ IOMUX_PAD(0x0530, 0x0228, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_REF_CLK_32K__ANATOP_USBOTG1_ID \
+ IOMUX_PAD(0x0530, 0x0228, 3, 0x05DC, 3, NO_PAD_CTRL)
+#define MX6SL_PAD_REF_CLK_32K__USDHC1_LCTL \
+ IOMUX_PAD(0x0530, 0x0228, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_REF_CLK_32K__GPIO_3_22 \
+ IOMUX_PAD(0x0530, 0x0228, 5, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_REF_CLK_32K__USDHC3_CD \
+ IOMUX_PAD(0x0530, 0x0228, 6, 0x0838, 3, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_REF_CLK_32K__OBSERVE_MUX_OUT_3 \
+ IOMUX_PAD(0x0530, 0x0228, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_RESET_IN_B__SRC_RESET_B \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_SD1_CLK__USDHC1_CLK_50MHZ \
+ IOMUX_PAD(0x0534, 0x022C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_SD1_CLK__USDHC1_CLK_100MHZ \
+ IOMUX_PAD(0x0534, 0x022C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ)
+#define MX6SL_PAD_SD1_CLK__USDHC1_CLK_200MHZ \
+ IOMUX_PAD(0x0534, 0x022C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ)
+#define MX6SL_PAD_SD1_CLK__FEC_MDIO \
+ IOMUX_PAD(0x0534, 0x022C, 1, 0x06F4, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_CLK__KPP_COL_0 \
+ IOMUX_PAD(0x0534, 0x022C, 2, 0x0734, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_CLK__EPDC_SDCE_4 \
+ IOMUX_PAD(0x0534, 0x022C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_CLK__MSHC_SCLK \
+ IOMUX_PAD(0x0534, 0x022C, 4, 0x07E8, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_CLK__GPIO_5_15 \
+ IOMUX_PAD(0x0534, 0x022C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_CLK__ANATOP_ANATOP_TESTO_2 \
+ IOMUX_PAD(0x0534, 0x022C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_CLK__PL301_SIM_MX6SL_PER1_HADDR_25 \
+ IOMUX_PAD(0x0534, 0x022C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_SD1_CMD__USDHC1_CMD_50MHZ \
+ IOMUX_PAD(0x0538, 0x0230, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_SD1_CMD__USDHC1_CMD_100MHZ \
+ IOMUX_PAD(0x0538, 0x0230, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ)
+#define MX6SL_PAD_SD1_CMD__USDHC1_CMD_200MHZ \
+ IOMUX_PAD(0x0538, 0x0230, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ)
+#define MX6SL_PAD_SD1_CMD__FEC_TX_CLK \
+ IOMUX_PAD(0x0538, 0x0230, 1, 0x070C, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_CMD__KPP_ROW_0 \
+ IOMUX_PAD(0x0538, 0x0230, 2, 0x0754, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_CMD__EPDC_SDCE_5 \
+ IOMUX_PAD(0x0538, 0x0230, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_CMD__MSHC_BS \
+ IOMUX_PAD(0x0538, 0x0230, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_CMD__GPIO_5_14 \
+ IOMUX_PAD(0x0538, 0x0230, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_3 \
+ IOMUX_PAD(0x0538, 0x0230, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_CMD__PL301_SIM_MX6SL_PER1_HADDR_26 \
+ IOMUX_PAD(0x0538, 0x0230, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_SD1_DAT0__USDHC1_DAT0_50MHZ \
+ IOMUX_PAD(0x053C, 0x0234, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT0__USDHC1_DAT0_100MHZ \
+ IOMUX_PAD(0x053C, 0x0234, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ)
+#define MX6SL_PAD_SD1_DAT0__USDHC1_DAT0_200MHZ \
+ IOMUX_PAD(0x053C, 0x0234, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ)
+#define MX6SL_PAD_SD1_DAT0__FEC_RX_ER \
+ IOMUX_PAD(0x053C, 0x0234, 1, 0x0708, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT0__KPP_COL_1 \
+ IOMUX_PAD(0x053C, 0x0234, 2, 0x0738, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT0__EPDC_SDCE_6 \
+ IOMUX_PAD(0x053C, 0x0234, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT0__MSHC_DATA_0 \
+ IOMUX_PAD(0x053C, 0x0234, 4, 0x07D8, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT0__GPIO_5_11 \
+ IOMUX_PAD(0x053C, 0x0234, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_4 \
+ IOMUX_PAD(0x053C, 0x0234, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT0__PL301_SIM_MX6SL_PER1_HADDR_27 \
+ IOMUX_PAD(0x053C, 0x0234, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_SD1_DAT1__USDHC1_DAT1_50MHZ \
+ IOMUX_PAD(0x0540, 0x0238, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT1__USDHC1_DAT1_100MHZ \
+ IOMUX_PAD(0x0540, 0x0238, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ)
+#define MX6SL_PAD_SD1_DAT1__USDHC1_DAT1_200MHZ \
+ IOMUX_PAD(0x0540, 0x0238, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ)
+#define MX6SL_PAD_SD1_DAT1__FEC_RX_DV \
+ IOMUX_PAD(0x0540, 0x0238, 1, 0x0704, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT1__KPP_ROW_1 \
+ IOMUX_PAD(0x0540, 0x0238, 2, 0x0758, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT1__EPDC_SDCE_7 \
+ IOMUX_PAD(0x0540, 0x0238, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT1__MSHC_DATA_1 \
+ IOMUX_PAD(0x0540, 0x0238, 4, 0x07DC, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT1__GPIO_5_8 \
+ IOMUX_PAD(0x0540, 0x0238, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_5 \
+ IOMUX_PAD(0x0540, 0x0238, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT1__PL301_SIM_MX6SL_PER1_HADDR_28 \
+ IOMUX_PAD(0x0540, 0x0238, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_SD1_DAT2__USDHC1_DAT2_50MHZ \
+ IOMUX_PAD(0x0544, 0x023C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT2__USDHC1_DAT2_100MHZ \
+ IOMUX_PAD(0x0544, 0x023C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ)
+#define MX6SL_PAD_SD1_DAT2__USDHC1_DAT2_200MHZ \
+ IOMUX_PAD(0x0544, 0x023C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ)
+#define MX6SL_PAD_SD1_DAT2__FEC_RDATA_1 \
+ IOMUX_PAD(0x0544, 0x023C, 1, 0x06FC, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT2__KPP_COL_2 \
+ IOMUX_PAD(0x0544, 0x023C, 2, 0x073C, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT2__EPDC_SDCE_8 \
+ IOMUX_PAD(0x0544, 0x023C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT2__MSHC_DATA_2 \
+ IOMUX_PAD(0x0544, 0x023C, 4, 0x07E0, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT2__GPIO_5_13 \
+ IOMUX_PAD(0x0544, 0x023C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_6 \
+ IOMUX_PAD(0x0544, 0x023C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT2__PL301_SIM_MX6SL_PER1_HADDR_29 \
+ IOMUX_PAD(0x0544, 0x023C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_SD1_DAT3__USDHC1_DAT3_50MHZ \
+ IOMUX_PAD(0x0548, 0x0240, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT3__USDHC1_DAT3_100MHZ \
+ IOMUX_PAD(0x0548, 0x0240, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ)
+#define MX6SL_PAD_SD1_DAT3__USDHC1_DAT3_200MHZ \
+ IOMUX_PAD(0x0548, 0x0240, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ)
+#define MX6SL_PAD_SD1_DAT3__FEC_TDATA_0 \
+ IOMUX_PAD(0x0548, 0x0240, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT3__KPP_ROW_2 \
+ IOMUX_PAD(0x0548, 0x0240, 2, 0x075C, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT3__EPDC_SDCE_9 \
+ IOMUX_PAD(0x0548, 0x0240, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT3__MSHC_DATA_3 \
+ IOMUX_PAD(0x0548, 0x0240, 4, 0x07E4, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT3__GPIO_5_6 \
+ IOMUX_PAD(0x0548, 0x0240, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_7 \
+ IOMUX_PAD(0x0548, 0x0240, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT3__PL301_SIM_MX6SL_PER1_HADDR_30 \
+ IOMUX_PAD(0x0548, 0x0240, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_SD1_DAT4__USDHC1_DAT4_50MHZ \
+ IOMUX_PAD(0x054C, 0x0244, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT4__USDHC1_DAT4_100MHZ \
+ IOMUX_PAD(0x054C, 0x0244, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ)
+#define MX6SL_PAD_SD1_DAT4__USDHC1_DAT4_200MHZ \
+ IOMUX_PAD(0x054C, 0x0244, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ)
+#define MX6SL_PAD_SD1_DAT4__FEC_MDC \
+ IOMUX_PAD(0x054C, 0x0244, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT4__KPP_COL_3 \
+ IOMUX_PAD(0x054C, 0x0244, 2, 0x0740, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT4__EPDC_SDCLKN \
+ IOMUX_PAD(0x054C, 0x0244, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT4__UART4_TXD \
+ IOMUX_PAD(0x054C, 0x0244, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT4__UART4_RXD \
+ IOMUX_PAD(0x054C, 0x0244, 4, 0x0814, 4, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT4__GPIO_5_12 \
+ IOMUX_PAD(0x054C, 0x0244, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT4__ANATOP_ANATOP_TESTO_8 \
+ IOMUX_PAD(0x054C, 0x0244, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT4__PL301_SIM_MX6SL_PER1_HADDR_31 \
+ IOMUX_PAD(0x054C, 0x0244, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_SD1_DAT5__USDHC1_DAT5_50MHZ \
+ IOMUX_PAD(0x0550, 0x0248, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT5__USDHC1_DAT5_100MHZ \
+ IOMUX_PAD(0x0550, 0x0248, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ)
+#define MX6SL_PAD_SD1_DAT5__USDHC1_DAT5_200MHZ \
+ IOMUX_PAD(0x0550, 0x0248, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ)
+#define MX6SL_PAD_SD1_DAT5__FEC_RDATA_0 \
+ IOMUX_PAD(0x0550, 0x0248, 1, 0x06F8, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT5__KPP_ROW_3 \
+ IOMUX_PAD(0x0550, 0x0248, 2, 0x0760, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT5__EPDC_SDOED \
+ IOMUX_PAD(0x0550, 0x0248, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT5__UART4_TXD \
+ IOMUX_PAD(0x0550, 0x0248, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT5__UART4_RXD \
+ IOMUX_PAD(0x0550, 0x0248, 4, 0x0814, 5, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT5__GPIO_5_9 \
+ IOMUX_PAD(0x0550, 0x0248, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT5__ANATOP_ANATOP_TESTO_9 \
+ IOMUX_PAD(0x0550, 0x0248, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT5__PL301_SIM_MX6SL_PER1_HPROT_3 \
+ IOMUX_PAD(0x0550, 0x0248, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_SD1_DAT6__USDHC1_DAT6_50MHZ \
+ IOMUX_PAD(0x0554, 0x024C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT6__USDHC1_DAT6_100MHZ \
+ IOMUX_PAD(0x0554, 0x024C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ)
+#define MX6SL_PAD_SD1_DAT6__USDHC1_DAT6_200MHZ \
+ IOMUX_PAD(0x0554, 0x024C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ)
+#define MX6SL_PAD_SD1_DAT6__FEC_TX_EN \
+ IOMUX_PAD(0x0554, 0x024C, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT6__KPP_COL_4 \
+ IOMUX_PAD(0x0554, 0x024C, 2, 0x0744, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT6__EPDC_SDOEZ \
+ IOMUX_PAD(0x0554, 0x024C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT6__UART4_CTS \
+ IOMUX_PAD(0x0554, 0x024C, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT6__UART4_RTS \
+ IOMUX_PAD(0x0554, 0x024C, 4, 0x0810, 4, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT6__GPIO_5_7 \
+ IOMUX_PAD(0x0554, 0x024C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT6__ANATOP_ANATOP_TESTO_10 \
+ IOMUX_PAD(0x0554, 0x024C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT6__PL301_SIM_MX6SL_PER1_HPROT_2 \
+ IOMUX_PAD(0x0554, 0x024C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_SD1_DAT7__USDHC1_DAT7_50MHZ \
+ IOMUX_PAD(0x0558, 0x0250, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT7__USDHC1_DAT7_100MHZ \
+ IOMUX_PAD(0x0558, 0x0250, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ)
+#define MX6SL_PAD_SD1_DAT7__USDHC1_DAT7_200MHZ \
+ IOMUX_PAD(0x0558, 0x0250, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ)
+#define MX6SL_PAD_SD1_DAT7__FEC_TDATA_1 \
+ IOMUX_PAD(0x0558, 0x0250, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT7__KPP_ROW_4 \
+ IOMUX_PAD(0x0558, 0x0250, 2, 0x0764, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT7__CCM_PMIC_RDY \
+ IOMUX_PAD(0x0558, 0x0250, 3, 0x062C, 3, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT7__UART4_CTS \
+ IOMUX_PAD(0x0558, 0x0250, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT7__UART4_RTS \
+ IOMUX_PAD(0x0558, 0x0250, 4, 0x0810, 5, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT7__GPIO_5_10 \
+ IOMUX_PAD(0x0558, 0x0250, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT7__ANATOP_ANATOP_TESTO_11 \
+ IOMUX_PAD(0x0558, 0x0250, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD1_DAT7__PL301_SIM_MX6SL_PER1_HMASTLOCK \
+ IOMUX_PAD(0x0558, 0x0250, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_SD2_CLK__USDHC2_CLK_50MHZ \
+ IOMUX_PAD(0x055C, 0x0254, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_SD2_CLK__USDHC2_CLK_100MHZ \
+ IOMUX_PAD(0x055C, 0x0254, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ)
+#define MX6SL_PAD_SD2_CLK__USDHC2_CLK_200MHZ \
+ IOMUX_PAD(0x055C, 0x0254, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ)
+#define MX6SL_PAD_SD2_CLK__AUDMUX_AUD4_RXFS \
+ IOMUX_PAD(0x055C, 0x0254, 1, 0x05F0, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_CLK__ECSPI3_SCLK \
+ IOMUX_PAD(0x055C, 0x0254, 2, 0x06B0, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_CLK__CSI_D_0 \
+ IOMUX_PAD(0x055C, 0x0254, 3, 0x0630, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_CLK__OSC32K_32K_OUT \
+ IOMUX_PAD(0x055C, 0x0254, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_CLK__GPIO_5_5 \
+ IOMUX_PAD(0x055C, 0x0254, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_CLK__ANATOP_ANATOP_TESTO_13 \
+ IOMUX_PAD(0x055C, 0x0254, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_CLK__PL301_SIM_MX6SL_PER1_HPROT_1 \
+ IOMUX_PAD(0x055C, 0x0254, 7, 0x07EC, 1, NO_PAD_CTRL)
+
+#define MX6SL_PAD_SD2_CMD__USDHC2_CMD_50MHZ \
+ IOMUX_PAD(0x0560, 0x0258, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_SD2_CMD__USDHC2_CMD_100MHZ \
+ IOMUX_PAD(0x0560, 0x0258, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ)
+#define MX6SL_PAD_SD2_CMD__USDHC2_CMD_200MHZ \
+ IOMUX_PAD(0x0560, 0x0258, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ)
+#define MX6SL_PAD_SD2_CMD__AUDMUX_AUD4_RXC \
+ IOMUX_PAD(0x0560, 0x0258, 1, 0x05EC, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_CMD__ECSPI3_SS0 \
+ IOMUX_PAD(0x0560, 0x0258, 2, 0x06C0, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_CMD__CSI_D_1 \
+ IOMUX_PAD(0x0560, 0x0258, 3, 0x0634, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_CMD__EPIT1_EPITO \
+ IOMUX_PAD(0x0560, 0x0258, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_CMD__GPIO_5_4 \
+ IOMUX_PAD(0x0560, 0x0258, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_CMD__ANATOP_ANATOP_TESTO_14 \
+ IOMUX_PAD(0x0560, 0x0258, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_CMD__PL301_SIM_MX6SL_PER1_HADDR_21 \
+ IOMUX_PAD(0x0560, 0x0258, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_SD2_DAT0__USDHC2_DAT0_50MHZ \
+ IOMUX_PAD(0x0564, 0x025C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT0__USDHC2_DAT0_100MHZ \
+ IOMUX_PAD(0x0564, 0x025C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ)
+#define MX6SL_PAD_SD2_DAT0__USDHC2_DAT0_200MHZ \
+ IOMUX_PAD(0x0564, 0x025C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ)
+#define MX6SL_PAD_SD2_DAT0__AUDMUX_AUD4_RXD \
+ IOMUX_PAD(0x0564, 0x025C, 1, 0x05E4, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT0__ECSPI3_MOSI \
+ IOMUX_PAD(0x0564, 0x025C, 2, 0x06BC, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT0__CSI_D_2 \
+ IOMUX_PAD(0x0564, 0x025C, 3, 0x0638, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT0__UART5_CTS \
+ IOMUX_PAD(0x0564, 0x025C, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT0__UART5_RTS \
+ IOMUX_PAD(0x0564, 0x025C, 4, 0x0818, 4, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT0__GPIO_5_1 \
+ IOMUX_PAD(0x0564, 0x025C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_15 \
+ IOMUX_PAD(0x0564, 0x025C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT0__PL301_SIM_MX6SL_PER1_HPROT_0 \
+ IOMUX_PAD(0x0564, 0x025C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_SD2_DAT1__USDHC2_DAT1_50MHZ \
+ IOMUX_PAD(0x0568, 0x0260, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT1__USDHC2_DAT1_100MHZ \
+ IOMUX_PAD(0x0568, 0x0260, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ)
+#define MX6SL_PAD_SD2_DAT1__USDHC2_DAT1_200MHZ \
+ IOMUX_PAD(0x0568, 0x0260, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ)
+#define MX6SL_PAD_SD2_DAT1__AUDMUX_AUD4_TXC \
+ IOMUX_PAD(0x0568, 0x0260, 1, 0x05F4, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT1__ECSPI3_MISO \
+ IOMUX_PAD(0x0568, 0x0260, 2, 0x06B8, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT1__CSI_D_3 \
+ IOMUX_PAD(0x0568, 0x0260, 3, 0x063C, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT1__UART5_CTS \
+ IOMUX_PAD(0x0568, 0x0260, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT1__UART5_RTS \
+ IOMUX_PAD(0x0568, 0x0260, 4, 0x0818, 5, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT1__GPIO_4_30 \
+ IOMUX_PAD(0x0568, 0x0260, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT1__MMDC_MMDC_DEBUG_39 \
+ IOMUX_PAD(0x0568, 0x0260, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT1__PL301_SIM_MX6SL_PER1_HBURST_1 \
+ IOMUX_PAD(0x0568, 0x0260, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_SD2_DAT2__USDHC2_DAT2_50MHZ \
+ IOMUX_PAD(0x056C, 0x0264, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT2__USDHC2_DAT2_100MHZ \
+ IOMUX_PAD(0x056C, 0x0264, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ)
+#define MX6SL_PAD_SD2_DAT2__USDHC2_DAT2_200MHZ \
+ IOMUX_PAD(0x056C, 0x0264, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ)
+#define MX6SL_PAD_SD2_DAT2__AUDMUX_AUD4_TXFS \
+ IOMUX_PAD(0x056C, 0x0264, 1, 0x05F8, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT2__FEC_COL \
+ IOMUX_PAD(0x056C, 0x0264, 2, 0x06F0, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT2__CSI_D_4 \
+ IOMUX_PAD(0x056C, 0x0264, 3, 0x0640, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT2__UART5_TXD \
+ IOMUX_PAD(0x056C, 0x0264, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT2__UART5_RXD \
+ IOMUX_PAD(0x056C, 0x0264, 4, 0x081C, 4, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT2__GPIO_5_3 \
+ IOMUX_PAD(0x056C, 0x0264, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT2__MMDC_MMDC_DEBUG_38 \
+ IOMUX_PAD(0x056C, 0x0264, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT2__PL301_SIM_MX6SL_PER1_HADDR_22 \
+ IOMUX_PAD(0x056C, 0x0264, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_SD2_DAT3__USDHC2_DAT3_50MHZ \
+ IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT3__USDHC2_DAT3_100MHZ \
+ IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ)
+#define MX6SL_PAD_SD2_DAT3__USDHC2_DAT3_200MHZ \
+ IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ)
+#define MX6SL_PAD_SD2_DAT3__AUDMUX_AUD4_TXD \
+ IOMUX_PAD(0x0570, 0x0268, 1, 0x05E8, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT3__FEC_RX_CLK \
+ IOMUX_PAD(0x0570, 0x0268, 2, 0x0700, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT3__CSI_D_5 \
+ IOMUX_PAD(0x0570, 0x0268, 3, 0x0644, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT3__UART5_TXD \
+ IOMUX_PAD(0x0570, 0x0268, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT3__UART5_RXD \
+ IOMUX_PAD(0x0570, 0x0268, 4, 0x081C, 5, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT3__GPIO_4_28 \
+ IOMUX_PAD(0x0570, 0x0268, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT3__MMDC_MMDC_DEBUG_37 \
+ IOMUX_PAD(0x0570, 0x0268, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT3__PL301_SIM_MX6SL_PER1_HBURST_0 \
+ IOMUX_PAD(0x0570, 0x0268, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_SD2_DAT4__USDHC2_DAT4_50MHZ \
+ IOMUX_PAD(0x0574, 0x026C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT4__USDHC2_DAT4_100MHZ \
+ IOMUX_PAD(0x0574, 0x026C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ)
+#define MX6SL_PAD_SD2_DAT4__USDHC2_DAT4_200MHZ \
+ IOMUX_PAD(0x0574, 0x026C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ)
+#define MX6SL_PAD_SD2_DAT4__USDHC3_DAT4 \
+ IOMUX_PAD(0x0574, 0x026C, 1, 0x083C, 1, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT4__UART2_TXD \
+ IOMUX_PAD(0x0574, 0x026C, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT4__UART2_RXD \
+ IOMUX_PAD(0x0574, 0x026C, 2, 0x0804, 4, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT4__CSI_D_6 \
+ IOMUX_PAD(0x0574, 0x026C, 3, 0x0648, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT4__SPDIF_OUT1 \
+ IOMUX_PAD(0x0574, 0x026C, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT4__GPIO_5_2 \
+ IOMUX_PAD(0x0574, 0x026C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT4__MMDC_MMDC_DEBUG_36 \
+ IOMUX_PAD(0x0574, 0x026C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT4__PL301_SIM_MX6SL_PER1_HADDR_10 \
+ IOMUX_PAD(0x0574, 0x026C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_SD2_DAT5__USDHC2_DAT5_50MHZ \
+ IOMUX_PAD(0x0578, 0x0270, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT5__USDHC2_DAT5_100MHZ \
+ IOMUX_PAD(0x0578, 0x0270, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ)
+#define MX6SL_PAD_SD2_DAT5__USDHC2_DAT5_200MHZ \
+ IOMUX_PAD(0x0578, 0x0270, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ)
+#define MX6SL_PAD_SD2_DAT5__USDHC3_DAT5 \
+ IOMUX_PAD(0x0578, 0x0270, 1, 0x0840, 1, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT5__UART2_TXD \
+ IOMUX_PAD(0x0578, 0x0270, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT5__UART2_RXD \
+ IOMUX_PAD(0x0578, 0x0270, 2, 0x0804, 5, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT5__CSI_D_7 \
+ IOMUX_PAD(0x0578, 0x0270, 3, 0x064C, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT5__SPDIF_IN1 \
+ IOMUX_PAD(0x0578, 0x0270, 4, 0x07F0, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT5__GPIO_4_31 \
+ IOMUX_PAD(0x0578, 0x0270, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT5__MMDC_MMDC_DEBUG_35 \
+ IOMUX_PAD(0x0578, 0x0270, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT5__PL301_SIM_MX6SL_PER1_HADDR_20 \
+ IOMUX_PAD(0x0578, 0x0270, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_SD2_DAT6__USDHC2_DAT6_50MHZ \
+ IOMUX_PAD(0x057C, 0x0274, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT6__USDHC2_DAT6_100MHZ \
+ IOMUX_PAD(0x057C, 0x0274, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ)
+#define MX6SL_PAD_SD2_DAT6__USDHC2_DAT6_200MHZ \
+ IOMUX_PAD(0x057C, 0x0274, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ)
+#define MX6SL_PAD_SD2_DAT6__USDHC3_DAT6 \
+ IOMUX_PAD(0x057C, 0x0274, 1, 0x0844, 1, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT6__UART2_CTS \
+ IOMUX_PAD(0x057C, 0x0274, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT6__UART2_RTS \
+ IOMUX_PAD(0x057C, 0x0274, 2, 0x0800, 4, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT6__CSI_D_8 \
+ IOMUX_PAD(0x057C, 0x0274, 3, 0x0650, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT6__USDHC2_WP \
+ IOMUX_PAD(0x057C, 0x0274, 4, 0x0834, 2, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT6__GPIO_4_29 \
+ IOMUX_PAD(0x057C, 0x0274, 5, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT6__MMDC_MMDC_DEBUG_34 \
+ IOMUX_PAD(0x057C, 0x0274, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT6__PL301_SIM_MX6SL_PER1_HADDR_19 \
+ IOMUX_PAD(0x057C, 0x0274, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_SD2_DAT7__USDHC2_DAT7_50MHZ \
+ IOMUX_PAD(0x0580, 0x0278, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT7__USDHC2_DAT7_100MHZ \
+ IOMUX_PAD(0x0580, 0x0278, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ)
+#define MX6SL_PAD_SD2_DAT7__USDHC2_DAT7_200MHZ \
+ IOMUX_PAD(0x0580, 0x0278, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ)
+#define MX6SL_PAD_SD2_DAT7__USDHC3_DAT7 \
+ IOMUX_PAD(0x0580, 0x0278, 1, 0x0848, 1, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT7__UART2_CTS \
+ IOMUX_PAD(0x0580, 0x0278, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT7__UART2_RTS \
+ IOMUX_PAD(0x0580, 0x0278, 2, 0x0800, 5, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT7__CSI_D_9 \
+ IOMUX_PAD(0x0580, 0x0278, 3, 0x0654, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT7__USDHC2_CD \
+ IOMUX_PAD(0x0580, 0x0278, 4, 0x0830, 2, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT7__GPIO_5_0 \
+ IOMUX_PAD(0x0580, 0x0278, 5, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT7__MMDC_MMDC_DEBUG_33 \
+ IOMUX_PAD(0x0580, 0x0278, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_DAT7__PL301_SIM_MX6SL_PER1_HADDR_16 \
+ IOMUX_PAD(0x0580, 0x0278, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_SD2_RST__USDHC2_RST \
+ IOMUX_PAD(0x0584, 0x027C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_SD2_RST__FEC_REF_OUT \
+ IOMUX_PAD(0x0584, 0x027C, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_RST__WDOG2_WDOG_B \
+ IOMUX_PAD(0x0584, 0x027C, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_RST__SPDIF_OUT1 \
+ IOMUX_PAD(0x0584, 0x027C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_RST__CSI_MCLK \
+ IOMUX_PAD(0x0584, 0x027C, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_RST__GPIO_4_27 \
+ IOMUX_PAD(0x0584, 0x027C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_RST__ANATOP_ANATOP_TESTO_12 \
+ IOMUX_PAD(0x0584, 0x027C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD2_RST__PL301_SIM_MX6SL_PER1_HBURST_2 \
+ IOMUX_PAD(0x0584, 0x027C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_SD3_CLK__USDHC3_CLK_50MHZ \
+ IOMUX_PAD(0x0588, 0x0280, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_SD3_CLK__USDHC3_CLK_100MHZ \
+ IOMUX_PAD(0x0588, 0x0280, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ)
+#define MX6SL_PAD_SD3_CLK__USDHC3_CLK_200MHZ \
+ IOMUX_PAD(0x0588, 0x0280, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ)
+#define MX6SL_PAD_SD3_CLK__AUDMUX_AUD5_RXFS \
+ IOMUX_PAD(0x0588, 0x0280, 1, 0x0608, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_SD3_CLK__KPP_COL_5 \
+ IOMUX_PAD(0x0588, 0x0280, 2, 0x0748, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD3_CLK__CSI_D_10 \
+ IOMUX_PAD(0x0588, 0x0280, 3, 0x0658, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD3_CLK__WDOG1_WDOG_RST_B_DEB \
+ IOMUX_PAD(0x0588, 0x0280, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD3_CLK__GPIO_5_18 \
+ IOMUX_PAD(0x0588, 0x0280, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD3_CLK__USB_USBOTG1_PWR \
+ IOMUX_PAD(0x0588, 0x0280, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD3_CLK__PL301_SIM_MX6SL_PER1_HADDR_13 \
+ IOMUX_PAD(0x0588, 0x0280, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_SD3_CMD__USDHC3_CMD_50MHZ \
+ IOMUX_PAD(0x058C, 0x0284, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_SD3_CMD__USDHC3_CMD_100MHZ \
+ IOMUX_PAD(0x058C, 0x0284, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ)
+#define MX6SL_PAD_SD3_CMD__USDHC3_CMD_200MHZ \
+ IOMUX_PAD(0x058C, 0x0284, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ)
+#define MX6SL_PAD_SD3_CMD__AUDMUX_AUD5_RXC \
+ IOMUX_PAD(0x058C, 0x0284, 1, 0x0604, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_SD3_CMD__KPP_ROW_5 \
+ IOMUX_PAD(0x058C, 0x0284, 2, 0x0768, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD3_CMD__CSI_D_11 \
+ IOMUX_PAD(0x058C, 0x0284, 3, 0x065C, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD3_CMD__ANATOP_USBOTG2_ID \
+ IOMUX_PAD(0x058C, 0x0284, 4, 0x05E0, 3, NO_PAD_CTRL)
+#define MX6SL_PAD_SD3_CMD__GPIO_5_21 \
+ IOMUX_PAD(0x058C, 0x0284, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD3_CMD__USB_USBOTG2_PWR \
+ IOMUX_PAD(0x058C, 0x0284, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD3_CMD__PL301_SIM_MX6SL_PER1_HADDR_18 \
+ IOMUX_PAD(0x058C, 0x0284, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ \
+ IOMUX_PAD(0x0590, 0x0288, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_SD3_DAT0__USDHC3_DAT0_100MHZ \
+ IOMUX_PAD(0x0590, 0x0288, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ)
+#define MX6SL_PAD_SD3_DAT0__USDHC3_DAT0_200MHZ \
+ IOMUX_PAD(0x0590, 0x0288, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ)
+#define MX6SL_PAD_SD3_DAT0__AUDMUX_AUD5_RXD \
+ IOMUX_PAD(0x0590, 0x0288, 1, 0x05FC, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_SD3_DAT0__KPP_COL_6 \
+ IOMUX_PAD(0x0590, 0x0288, 2, 0x074C, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD3_DAT0__CSI_D_12 \
+ IOMUX_PAD(0x0590, 0x0288, 3, 0x0660, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_SD3_DAT0__ANATOP_USBOTG1_ID \
+ IOMUX_PAD(0x0590, 0x0288, 4, 0x05DC, 4, NO_PAD_CTRL)
+#define MX6SL_PAD_SD3_DAT0__GPIO_5_19 \
+ IOMUX_PAD(0x0590, 0x0288, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD3_DAT0__SJC_JTAG_ACT \
+ IOMUX_PAD(0x0590, 0x0288, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD3_DAT0__PL301_SIM_MX6SL_PER1_HADDR_11 \
+ IOMUX_PAD(0x0590, 0x0288, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ \
+ IOMUX_PAD(0x0594, 0x028C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_SD3_DAT1__USDHC3_DAT1_100MHZ \
+ IOMUX_PAD(0x0594, 0x028C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ)
+#define MX6SL_PAD_SD3_DAT1__USDHC3_DAT1_200MHZ \
+ IOMUX_PAD(0x0594, 0x028C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ)
+#define MX6SL_PAD_SD3_DAT1__AUDMUX_AUD5_TXC \
+ IOMUX_PAD(0x0594, 0x028C, 1, 0x060C, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_SD3_DAT1__KPP_ROW_6 \
+ IOMUX_PAD(0x0594, 0x028C, 2, 0x076C, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD3_DAT1__CSI_D_13 \
+ IOMUX_PAD(0x0594, 0x028C, 3, 0x0664, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_SD3_DAT1__USDHC1_VSELECT \
+ IOMUX_PAD(0x0594, 0x028C, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_SD3_DAT1__GPIO_5_20 \
+ IOMUX_PAD(0x0594, 0x028C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD3_DAT1__SJC_DE_B \
+ IOMUX_PAD(0x0594, 0x028C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD3_DAT1__PL301_SIM_MX6SL_PER1_HADDR_17 \
+ IOMUX_PAD(0x0594, 0x028C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ \
+ IOMUX_PAD(0x0598, 0x0290, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_SD3_DAT2__USDHC3_DAT2_100MHZ \
+ IOMUX_PAD(0x0598, 0x0290, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ)
+#define MX6SL_PAD_SD3_DAT2__USDHC3_DAT2_200MHZ \
+ IOMUX_PAD(0x0598, 0x0290, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ)
+#define MX6SL_PAD_SD3_DAT2__AUDMUX_AUD5_TXFS \
+ IOMUX_PAD(0x0598, 0x0290, 1, 0x0610, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_SD3_DAT2__KPP_COL_7 \
+ IOMUX_PAD(0x0598, 0x0290, 2, 0x0750, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD3_DAT2__CSI_D_14 \
+ IOMUX_PAD(0x0598, 0x0290, 3, 0x0668, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_SD3_DAT2__EPIT1_EPITO \
+ IOMUX_PAD(0x0598, 0x0290, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD3_DAT2__GPIO_5_16 \
+ IOMUX_PAD(0x0598, 0x0290, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD3_DAT2__USB_USBOTG2_OC \
+ IOMUX_PAD(0x0598, 0x0290, 6, 0x0820, 3, NO_PAD_CTRL)
+#define MX6SL_PAD_SD3_DAT2__PL301_SIM_MX6SL_PER1_HADDR_14 \
+ IOMUX_PAD(0x0598, 0x0290, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ \
+ IOMUX_PAD(0x059C, 0x0294, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL)
+#define MX6SL_PAD_SD3_DAT3__USDHC3_DAT3_100MHZ \
+ IOMUX_PAD(0x059C, 0x0294, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_100MHZ)
+#define MX6SL_PAD_SD3_DAT3__USDHC3_DAT3_200MHZ \
+ IOMUX_PAD(0x059C, 0x0294, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL_200MHZ)
+#define MX6SL_PAD_SD3_DAT3__AUDMUX_AUD5_TXD \
+ IOMUX_PAD(0x059C, 0x0294, 1, 0x0600, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_SD3_DAT3__KPP_ROW_7 \
+ IOMUX_PAD(0x059C, 0x0294, 2, 0x0770, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD3_DAT3__CSI_D_15 \
+ IOMUX_PAD(0x059C, 0x0294, 3, 0x066C, 1, NO_PAD_CTRL)
+#define MX6SL_PAD_SD3_DAT3__EPIT2_EPITO \
+ IOMUX_PAD(0x059C, 0x0294, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD3_DAT3__GPIO_5_17 \
+ IOMUX_PAD(0x059C, 0x0294, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_SD3_DAT3__USB_USBOTG1_OC \
+ IOMUX_PAD(0x059C, 0x0294, 6, 0x0824, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_SD3_DAT3__PL301_SIM_MX6SL_PER1_HADDR_12 \
+ IOMUX_PAD(0x059C, 0x0294, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_TEST_MODE__TCU_TEST_MODE \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_UART1_RXD__UART1_TXD \
+ IOMUX_PAD(0x05A0, 0x0298, 0, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_UART1_RXD__UART1_RXD \
+ IOMUX_PAD(0x05A0, 0x0298, 0, 0x07FC, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_UART1_RXD__PWM1_PWMO \
+ IOMUX_PAD(0x05A0, 0x0298, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_UART1_RXD__UART4_TXD \
+ IOMUX_PAD(0x05A0, 0x0298, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_UART1_RXD__UART4_RXD \
+ IOMUX_PAD(0x05A0, 0x0298, 2, 0x0814, 6, NO_PAD_CTRL)
+#define MX6SL_PAD_UART1_RXD__FEC_COL \
+ IOMUX_PAD(0x05A0, 0x0298, 3, 0x06F0, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_UART1_RXD__UART5_TXD \
+ IOMUX_PAD(0x05A0, 0x0298, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_UART1_RXD__UART5_RXD \
+ IOMUX_PAD(0x05A0, 0x0298, 4, 0x081C, 6, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_UART1_RXD__GPIO_3_16 \
+ IOMUX_PAD(0x05A0, 0x0298, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_UART1_RXD__ANATOP_ANATOP_TESTI_2 \
+ IOMUX_PAD(0x05A0, 0x0298, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_UART1_RXD__TPSMP_CLK \
+ IOMUX_PAD(0x05A0, 0x0298, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6SL_PAD_UART1_TXD__UART1_TXD \
+ IOMUX_PAD(0x05A4, 0x029C, 0, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_UART1_TXD__UART1_RXD \
+ IOMUX_PAD(0x05A4, 0x029C, 0, 0x07FC, 1, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_UART1_TXD__PWM2_PWMO \
+ IOMUX_PAD(0x05A4, 0x029C, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_UART1_TXD__UART4_TXD \
+ IOMUX_PAD(0x05A4, 0x029C, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_UART1_TXD__UART4_RXD \
+ IOMUX_PAD(0x05A4, 0x029C, 2, 0x0814, 7, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_UART1_TXD__FEC_RX_CLK \
+ IOMUX_PAD(0x05A4, 0x029C, 3, 0x0700, 2, NO_PAD_CTRL)
+#define MX6SL_PAD_UART1_TXD__UART5_TXD \
+ IOMUX_PAD(0x05A4, 0x029C, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_UART1_TXD__UART5_RXD \
+ IOMUX_PAD(0x05A4, 0x029C, 4, 0x081C, 7, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_UART1_TXD__GPIO_3_17 \
+ IOMUX_PAD(0x05A4, 0x029C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_UART1_TXD__ANATOP_ANATOP_TESTI_3 \
+ IOMUX_PAD(0x05A4, 0x029C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_UART1_TXD__UART5_DCD \
+ IOMUX_PAD(0x05A4, 0x029C, 7, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+
+#define MX6SL_PAD_WDOG_B__WDOG1_WDOG_B \
+ IOMUX_PAD(0x05A8, 0x02A0, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_WDOG_B__WDOG1_WDOG_RST_B_DEB \
+ IOMUX_PAD(0x05A8, 0x02A0, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_WDOG_B__UART5_RI \
+ IOMUX_PAD(0x05A8, 0x02A0, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL)
+#define MX6SL_PAD_WDOG_B__GPIO_3_18 \
+ IOMUX_PAD(0x05A8, 0x02A0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6SL_PAD_WDOG_B__OBSERVE_MUX_OUT_2 \
+ IOMUX_PAD(0x05A8, 0x02A0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#endif /* __MACH_IOMUX_MX6SL_H__*/
--- /dev/null
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ ARCH_CPU_DTS
+
+/ {
+ model = "Ka-Ro TX6Q module";
+ compatible = "karo,imx6q-tx6q", "fsl,imx6q";
+
+ memory {
+ reg = <0 0>; /* filled in by U-Boot */
+ };
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_3 &pinctrl_uart1_4>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2_5 &pinctrl_uart2_6>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3_1 &pinctrl_uart3_4>;
+ status = "okay";
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet_1>;
+ phy-mode = "rmii";
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1_2>;
+ cd-gpios = <&gpio7 2 0>;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2_2>;
+ cd-gpios = <&gpio7 3 0>;
+ status = "okay";
+};
--- /dev/null
+#
+# (C) Copyright 2009 DENX Software Engineering
+# Author: John Rigby <jcrigby@gmail.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := tx6dl.o
+SOBJS := lowlevel_init.o
+ifeq ($(CONFIG_CMD_ROMUPDATE),y)
+ COBJS += flash.o
+endif
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+# stack is allocated below CONFIG_SYS_TEXT_BASE
+CONFIG_SYS_TEXT_BASE := 0x27800000
+#CONFIG_SYS_TEXT_BASE := 0x17800000
+#CONFIG_SPL_TEXT_BASE := 0x00000000
+
+LOGO_BMP = logos/karo.bmp
+#PLATFORM_CPPFLAGS += -DDEBUG
+#PLATFORM_CPPFLAGS += -Wno-unused-but-set-variable
+
+# calculate U_BOOT_IMG_SIZE to be at least 3 eraseblocks larger than the maximum expected image size
+ifneq ($(CONFIG_SYS_NAND_ERASE_SIZE),)
+CONFIG_U_BOOT_IMG_SIZE = $(shell echo 'e=$(CONFIG_SYS_NAND_ERASE_SIZE);s=640*1024;s + e%s%e + 3*e' | bc)
+CONFIG_SYS_USERFS_SIZE = $(shell expr \( $(CONFIG_SYS_NAND_BLOCKS) - 9 \) \* $(CONFIG_SYS_NAND_ERASE_SIZE) - $(CONFIG_U_BOOT_IMG_SIZE) - 36 \* 1048576)
+CONFIG_SYS_USERFS_SIZE2 = $(shell expr \( $(CONFIG_SYS_NAND_BLOCKS) - 12 \) \* $(CONFIG_SYS_NAND_ERASE_SIZE) - $(CONFIG_U_BOOT_IMG_SIZE) - 36 \* 1048576)
+
+PLATFORM_CPPFLAGS += -DCONFIG_U_BOOT_IMG_SIZE=$(CONFIG_U_BOOT_IMG_SIZE)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_U_BOOT_PART_SIZE=$(shell printf "%uk" `expr $(CONFIG_U_BOOT_IMG_SIZE) / 1024`)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_U_BOOT_OFFSET=$(shell printf "0x%x" `expr $(CONFIG_SYS_NAND_ERASE_SIZE)`)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_ENV_PART_SIZE=$(shell printf "%uk" `expr 3 \* $(CONFIG_SYS_NAND_ERASE_SIZE) / 1024`)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_USERFS_PART_SIZE=$(shell printf "%uk" `expr $(CONFIG_SYS_USERFS_SIZE) / 1024`)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_USERFS_PART_SIZE2=$(shell printf "%uk" `expr $(CONFIG_SYS_USERFS_SIZE) / 1024`)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_DTB_PART_SIZE=$(shell printf "%uk" `expr $(CONFIG_SYS_NAND_ERASE_SIZE) / 1024`)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_NAND_BBT_SIZE=$(shell printf "%uk" `expr 4 \* $(CONFIG_SYS_NAND_ERASE_SIZE) / 1024`)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_NAND_BBT_OFFSET=$(shell printf "0x%x" `expr \( $(CONFIG_SYS_NAND_BLOCKS) - 4 \) \* $(CONFIG_SYS_NAND_ERASE_SIZE)`)
+endif
+
+PLATFORM_CPPFLAGS += -Werror
+PLATFORM_CPPFLAGS += -DDEBUG
+
+#ifneq ($(CONFIG_SPL_BUILD),y)
+# ALL-y += $(obj)u-boot.sb
+#endif
--- /dev/null
+#include <common.h>
+#include <malloc.h>
+#include <nand.h>
+#include <errno.h>
+
+#include <linux/err.h>
+
+#include <asm/io.h>
+#include <asm/sizes.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/regs-gpmi.h>
+#include <asm/arch/regs-bch.h>
+
+#if CONFIG_SYS_NAND_U_BOOT_OFFS < 0x20000
+#error CONFIG_SYS_NAND_U_BOOT_OFFS must be >= 128kIB
+#endif
+
+struct mx6_nand_timing {
+ u8 data_setup;
+ u8 data_hold;
+ u8 address_setup;
+ u8 dsample_time;
+ u8 nand_timing_state;
+ u8 tREA;
+ u8 tRLOH;
+ u8 tRHOH;
+};
+
+struct mx6_fcb {
+ u32 checksum;
+ u32 fingerprint;
+ u32 version;
+ struct mx6_nand_timing timing;
+ u32 page_data_size;
+ u32 total_page_size;
+ u32 sectors_per_block;
+ u32 number_of_nands; /* not used by ROM code */
+ u32 total_internal_die; /* not used by ROM code */
+ u32 cell_type; /* not used by ROM code */
+ u32 ecc_blockn_type;
+ u32 ecc_block0_size;
+ u32 ecc_blockn_size;
+ u32 ecc_block0_type;
+ u32 metadata_size;
+ u32 ecc_blocks_per_page;
+ u32 rsrvd1[6]; /* not used by ROM code */
+ u32 bch_mode; /* erase_threshold */
+ u32 rsrvd2[2];
+ u32 fw1_start_page;
+ u32 fw2_start_page;
+ u32 fw1_sectors;
+ u32 fw2_sectors;
+ u32 dbbt_search_area;
+ u32 bb_mark_byte;
+ u32 bb_mark_startbit;
+ u32 bb_mark_phys_offset;
+ u32 bch_type;
+ u32 rsrvd3[8]; /* Toggle NAND timing parameters */
+ u32 disbbm;
+ u32 bb_mark_spare_offset;
+ u32 rsrvd4[9]; /* ONFI NAND parameters */
+ u32 disbb_search;
+};
+
+struct mx6_dbbt_header {
+ u32 checksum;
+ u32 fingerprint;
+ u32 version;
+ u32 number_bb;
+ u32 number_pages;
+ u8 spare[492];
+};
+
+struct mx6_dbbt {
+ u32 nand_number;
+ u32 number_bb;
+ u32 bb_num[2040 / 4];
+};
+
+#define BF_VAL(v, bf) (((v) & bf##_MASK) >> bf##_OFFSET)
+
+static nand_info_t *mtd = &nand_info[0];
+
+extern void *_start;
+
+#define BIT(v,n) (((v) >> (n)) & 0x1)
+
+static inline void memdump(const void *addr, size_t len)
+{
+ const char *buf = addr;
+ int i;
+
+ for (i = 0; i < len; i++) {
+ if (i % 16 == 0) {
+ if (i > 0)
+ printf("\n");
+ printf("%p:", &buf[i]);
+ }
+ printf(" %02x", buf[i]);
+ }
+ printf("\n");
+}
+
+static u8 calculate_parity_13_8(u8 d)
+{
+ u8 p = 0;
+
+ p |= (BIT(d, 6) ^ BIT(d, 5) ^ BIT(d, 3) ^ BIT(d, 2)) << 0;
+ p |= (BIT(d, 7) ^ BIT(d, 5) ^ BIT(d, 4) ^ BIT(d, 2) ^ BIT(d, 1)) << 1;
+ p |= (BIT(d, 7) ^ BIT(d, 6) ^ BIT(d, 5) ^ BIT(d, 1) ^ BIT(d, 0)) << 2;
+ p |= (BIT(d, 7) ^ BIT(d, 4) ^ BIT(d, 3) ^ BIT(d, 0)) << 3;
+ p |= (BIT(d, 6) ^ BIT(d, 4) ^ BIT(d, 3) ^ BIT(d, 2) ^ BIT(d, 1) ^ BIT(d, 0)) << 4;
+ return p;
+}
+
+static void encode_hamming_13_8(void *_src, void *_ecc, size_t size)
+{
+ int i;
+ u8 *src = _src;
+ u8 *ecc = _ecc;
+
+ for (i = 0; i < size; i++)
+ ecc[i] = calculate_parity_13_8(src[i]);
+}
+
+static u32 calc_chksum(void *buf, size_t size)
+{
+ u32 chksum = 0;
+ u8 *bp = buf;
+ size_t i;
+
+ for (i = 0; i < size; i++) {
+ chksum += bp[i];
+ }
+ return ~chksum;
+}
+
+/*
+ Physical organisation of data in NAND flash:
+ metadata
+ payload chunk 0 (may be empty)
+ ecc for metadata + payload chunk 0
+ payload chunk 1
+ ecc for payload chunk 1
+...
+ payload chunk n
+ ecc for payload chunk n
+ */
+
+static int calc_bb_offset(nand_info_t *mtd, struct mx6_fcb *fcb)
+{
+ int bb_mark_offset;
+ int chunk_data_size = fcb->ecc_blockn_size * 8;
+ int chunk_ecc_size = (fcb->ecc_blockn_type << 1) * 13;
+ int chunk_total_size = chunk_data_size + chunk_ecc_size;
+ int bb_mark_chunk, bb_mark_chunk_offs;
+
+ bb_mark_offset = (mtd->writesize - fcb->metadata_size) * 8;
+ if (fcb->ecc_block0_size == 0)
+ bb_mark_offset -= (fcb->ecc_block0_type << 1) * 13;
+
+ bb_mark_chunk = bb_mark_offset / chunk_total_size;
+ bb_mark_chunk_offs = bb_mark_offset - (bb_mark_chunk * chunk_total_size);
+ if (bb_mark_chunk_offs > chunk_data_size) {
+ printf("Unsupported ECC layout; BB mark resides in ECC data: %u\n",
+ bb_mark_chunk_offs);
+ return -EINVAL;
+ }
+ bb_mark_offset -= bb_mark_chunk * chunk_ecc_size;
+ return bb_mark_offset;
+}
+
+#define pr_fcb_val(p, n) debug("%s=%08x(%d)\n", #n, (p)->n, (p)->n)
+
+static struct mx6_fcb *create_fcb(void *buf, int fw1_start_block,
+ int fw2_start_block, size_t fw_size)
+{
+ struct gpmi_regs *gpmi_base = (struct gpmi_regs *)GPMI_BASE_ADDRESS;
+ struct bch_regs *bch_base = (struct bch_regs *)BCH_BASE_ADDRESS;
+ u32 fl0, fl1;
+ u32 t0;
+ int metadata_size;
+ int bb_mark_bit_offs;
+ struct mx6_fcb *fcb;
+ int fcb_offs;
+
+ if (gpmi_base == NULL || bch_base == NULL) {
+ return ERR_PTR(-ENOMEM);
+ }
+
+ fl0 = readl(&bch_base->hw_bch_flash0layout0);
+ fl1 = readl(&bch_base->hw_bch_flash0layout1);
+ t0 = readl(&gpmi_base->hw_gpmi_timing0);
+
+ metadata_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_META_SIZE);
+
+ fcb = buf + ALIGN(metadata_size, 4);
+ fcb_offs = (void *)fcb - buf;
+
+ memset(buf, 0xff, fcb_offs);
+ memset(fcb, 0x00, sizeof(*fcb));
+ memset(fcb + 1, 0xff, mtd->erasesize - fcb_offs - sizeof(*fcb));
+
+ strncpy((char *)&fcb->fingerprint, "FCB ", 4);
+ fcb->version = cpu_to_be32(1);
+
+ fcb->disbb_search = 1;
+ fcb->disbbm = 1;
+
+ /* ROM code assumes GPMI clock of 25 MHz */
+ fcb->timing.data_setup = BF_VAL(t0, GPMI_TIMING0_DATA_SETUP) * 40;
+ fcb->timing.data_hold = BF_VAL(t0, GPMI_TIMING0_DATA_HOLD) * 40;
+ fcb->timing.address_setup = BF_VAL(t0, GPMI_TIMING0_ADDRESS_SETUP) * 40;
+
+ fcb->page_data_size = mtd->writesize;
+ fcb->total_page_size = mtd->writesize + mtd->oobsize;
+ fcb->sectors_per_block = mtd->erasesize / mtd->writesize;
+
+ fcb->ecc_block0_type = BF_VAL(fl0, BCH_FLASHLAYOUT0_ECC0);
+ fcb->ecc_block0_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_DATA0_SIZE) * 4;
+ fcb->ecc_blockn_type = BF_VAL(fl1, BCH_FLASHLAYOUT1_ECCN);
+ fcb->ecc_blockn_size = BF_VAL(fl1, BCH_FLASHLAYOUT1_DATAN_SIZE) * 4;
+
+ pr_fcb_val(fcb, ecc_block0_type);
+ pr_fcb_val(fcb, ecc_blockn_type);
+ pr_fcb_val(fcb, ecc_block0_size);
+ pr_fcb_val(fcb, ecc_blockn_size);
+
+ fcb->metadata_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_META_SIZE);
+ fcb->ecc_blocks_per_page = BF_VAL(fl0, BCH_FLASHLAYOUT0_NBLOCKS);
+ fcb->bch_mode = readl(&bch_base->hw_bch_mode);
+ fcb->bch_type = 0; /* BCH20 */
+
+ fcb->fw1_start_page = fw1_start_block * mtd->erasesize / mtd->writesize;
+ fcb->fw1_sectors = DIV_ROUND_UP(fw_size, mtd->writesize);
+
+ if (fw2_start_block != 0 && fw2_start_block < mtd->size / mtd->erasesize) {
+ fcb->fw2_start_page = fw2_start_block * mtd->erasesize / mtd->writesize;
+ fcb->fw2_sectors = fcb->fw1_sectors;
+ }
+
+ fcb->dbbt_search_area = 1;
+
+ bb_mark_bit_offs = calc_bb_offset(mtd, fcb);
+ if (bb_mark_bit_offs < 0)
+ return ERR_PTR(bb_mark_bit_offs);
+ fcb->bb_mark_byte = bb_mark_bit_offs / 8;
+ fcb->bb_mark_startbit = bb_mark_bit_offs % 8;
+ fcb->bb_mark_phys_offset = mtd->writesize;
+
+ pr_fcb_val(fcb, bb_mark_byte);
+ pr_fcb_val(fcb, bb_mark_startbit);
+ pr_fcb_val(fcb, bb_mark_phys_offset);
+
+ fcb->checksum = calc_chksum(&fcb->fingerprint, 512 - 4);
+ return fcb;
+}
+
+static inline int find_fcb(void *ref, int page)
+{
+ int ret = 0;
+ struct nand_chip *chip = mtd->priv;
+ void *buf = malloc(mtd->erasesize);
+
+ if (buf == NULL) {
+ return -ENOMEM;
+ }
+ chip->select_chip(mtd, 0);
+ chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
+ ret = chip->ecc.read_page_raw(mtd, chip, buf, page);
+ if (ret) {
+ printf("Failed to read FCB from page %u: %d\n", page, ret);
+ return ret;
+ }
+ chip->select_chip(mtd, -1);
+ if (memcmp(buf, ref, mtd->writesize) == 0) {
+ debug("Found FCB in page %u (%08x)\n",
+ page, page * mtd->writesize);
+ ret = 1;
+ }
+ free(buf);
+ return ret;
+}
+
+static int write_fcb(void *buf, int block)
+{
+ int ret;
+ struct nand_chip *chip = mtd->priv;
+ int page = block * mtd->erasesize / mtd->writesize;
+
+ ret = find_fcb(buf, page);
+ if (ret > 0) {
+ printf("FCB at block %d is up to date\n", block);
+ return 0;
+ }
+
+ ret = nand_erase(mtd, block * mtd->erasesize, mtd->erasesize);
+ if (ret) {
+ printf("Failed to erase FCB block %u\n", block);
+ return ret;
+ }
+
+ printf("Writing FCB to block %d @ %08x\n", block,
+ block * mtd->erasesize);
+ chip->select_chip(mtd, 0);
+ ret = chip->write_page(mtd, chip, buf, page, 0, 1);
+ if (ret) {
+ printf("Failed to write FCB to block %u: %d\n", block, ret);
+ }
+ chip->select_chip(mtd, -1);
+
+ return ret;
+}
+
+struct mx6_ivt {
+ u32 magic;
+ u32 entry;
+ u32 rsrvd1;
+ void *dcd;
+ void *boot_data;
+ void *self;
+ void *csf;
+ u32 rsrvd2;
+};
+
+struct mx6_boot_data {
+ u32 start;
+ u32 length;
+ u32 plugin;
+};
+
+static size_t count_good_blocks(int start, int end)
+{
+ size_t max_len = (end - start + 1);
+ int block;
+
+ for (block = start; block <= end; block++) {
+ if (nand_block_isbad(mtd, block * mtd->erasesize))
+ max_len--;
+ }
+ return max_len;
+}
+
+static int find_ivt(void *buf)
+{
+ struct mx6_ivt *ivt_hdr = buf + 0x400;
+
+ if ((ivt_hdr->magic & 0xff0000ff) != 0x400000d1)
+ return 0;
+
+ return 1;
+}
+
+static inline void *reloc(void *dst, void *base, void *ptr)
+{
+ return dst + (ptr - base);
+}
+
+static int patch_ivt(void *buf, size_t fsize)
+{
+ struct mx6_ivt *ivt_hdr = buf + 0x400;
+ struct mx6_boot_data *boot_data;
+
+ if (!find_ivt(buf)) {
+ printf("No IVT found in image at %p\n", buf);
+ return -EINVAL;
+ }
+ boot_data = reloc(ivt_hdr, ivt_hdr->self, ivt_hdr->boot_data);
+ boot_data->length = fsize;
+
+ return 0;
+}
+
+#define chk_overlap(a,b) \
+ ((a##_start_block <= b##_end_block && \
+ a##_end_block >= b##_start_block) || \
+ (b##_start_block <= a##_end_block && \
+ b##_end_block >= a##_start_block))
+
+#define fail_if_overlap(a,b,m1,m2) do { \
+ if (chk_overlap(a, b)) { \
+ printf("%s blocks %lu..%lu overlap %s in blocks %lu..%lu!\n", \
+ m1, a##_start_block, a##_end_block, \
+ m2, b##_start_block, b##_end_block); \
+ return -EINVAL; \
+ } \
+} while (0)
+
+#ifdef CONFIG_ENV_IS_IN_NAND
+#ifndef CONFIG_ENV_OFFSET_REDUND
+#define TOTAL_ENV_SIZE CONFIG_ENV_RANGE
+#else
+#define TOTAL_ENV_SIZE (CONFIG_ENV_RANGE * 2)
+#endif
+#endif
+
+#define pr_fcb_offset(n) printf("%s: %04x (%d)\n", #n, \
+ offsetof(struct mx6_fcb, n), offsetof(struct mx6_fcb, n))
+
+int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ int ret;
+ const unsigned long fcb_start_block = 0, fcb_end_block = 0;
+ int erase_size = mtd->erasesize;
+ int page_size = mtd->writesize;
+ void *buf;
+ char *load_addr;
+ char *file_size;
+ size_t size = 0;
+ void *addr = NULL;
+ struct mx6_fcb *fcb;
+ unsigned long mtd_num_blocks = mtd->size / mtd->erasesize;
+#ifdef CONFIG_ENV_IS_IN_NAND
+ unsigned long env_start_block = CONFIG_ENV_OFFSET / mtd->erasesize;
+ unsigned long env_end_block = env_start_block +
+ DIV_ROUND_UP(TOTAL_ENV_SIZE, mtd->erasesize) - 1;
+#endif
+ int optind;
+ int fw1_set = 0;
+ int fw2_set = 0;
+ unsigned long fw1_start_block = 0, fw1_end_block;
+ unsigned long fw2_start_block = 0, fw2_end_block;
+ unsigned long fw_num_blocks;
+ unsigned long extra_blocks = 2;
+ nand_erase_options_t erase_opts = { 0, };
+ size_t max_len1, max_len2;
+
+ for (optind = 1; optind < argc; optind++) {
+ if (strcmp(argv[optind], "-f") == 0) {
+ if (optind >= argc - 1) {
+ printf("Option %s requires an argument\n",
+ argv[optind]);
+ return -EINVAL;
+ }
+ optind++;
+ fw1_start_block = simple_strtoul(argv[optind], NULL, 0);
+ if (fw1_start_block >= mtd_num_blocks) {
+ printf("Block number %lu is out of range: 0..%lu\n",
+ fw1_start_block, mtd_num_blocks - 1);
+ return -EINVAL;
+ }
+ fw1_set = 1;
+ } else if (strcmp(argv[optind], "-r") == 0) {
+ if (optind < argc - 1 && argv[optind + 1][0] != '-') {
+ optind++;
+ fw2_start_block = simple_strtoul(argv[optind],
+ NULL, 0);
+ if (fw2_start_block >= mtd_num_blocks) {
+ printf("Block number %lu is out of range: 0..%lu\n",
+ fw2_start_block,
+ mtd_num_blocks - 1);
+ return -EINVAL;
+ }
+ }
+ fw2_set = 1;
+ } else if (strcmp(argv[optind], "-e") == 0) {
+ if (optind >= argc - 1) {
+ printf("Option %s requires an argument\n",
+ argv[optind]);
+ return -EINVAL;
+ }
+ optind++;
+ extra_blocks = simple_strtoul(argv[optind], NULL, 0);
+ if (extra_blocks >= mtd_num_blocks) {
+ printf("Extra block count %lu is out of range: 0..%lu\n",
+ extra_blocks,
+ mtd_num_blocks - 1);
+ return -EINVAL;
+ }
+ } else if (argv[optind][0] == '-') {
+ printf("Unrecognized option %s\n", argv[optind]);
+ return -EINVAL;
+ } else {
+ break;
+ }
+ }
+
+ load_addr = getenv("fileaddr");
+ file_size = getenv("filesize");
+
+ if (argc - optind < 1 && load_addr == NULL) {
+ printf("Load address not specified\n");
+ return -EINVAL;
+ }
+ if (argc - optind < 2 && file_size == NULL) {
+ printf("WARNING: Image size not specified; overwriting whole uboot partition\n");
+ }
+ if (argc > optind) {
+ load_addr = NULL;
+ addr = (void *)simple_strtoul(argv[optind], NULL, 16);
+ optind++;
+ }
+ if (argc > optind) {
+ file_size = NULL;
+ size = simple_strtoul(argv[optind], NULL, 16);
+ optind++;
+ }
+ if (load_addr != NULL) {
+ addr = (void *)simple_strtoul(load_addr, NULL, 16);
+ printf("Using default load address %p\n", addr);
+ }
+ if (file_size != NULL) {
+ size = simple_strtoul(file_size, NULL, 16);
+ printf("Using default file size %08x\n", size);
+ }
+ if (size > 0)
+ fw_num_blocks = DIV_ROUND_UP(size, mtd->erasesize);
+ else
+ fw_num_blocks = CONFIG_U_BOOT_IMG_SIZE / mtd->erasesize - extra_blocks;
+
+ if (!fw1_set) {
+ fw1_start_block = CONFIG_SYS_NAND_U_BOOT_OFFS / mtd->erasesize;
+ fw1_end_block = fw1_start_block + fw_num_blocks + extra_blocks - 1;
+ } else {
+ fw1_end_block = fw1_start_block + fw_num_blocks + extra_blocks - 1;
+ }
+
+ if (fw2_set && fw2_start_block == 0) {
+ fw2_start_block = fw1_end_block + 1;
+ fw2_end_block = fw2_start_block + fw_num_blocks + extra_blocks - 1;
+ } else {
+ fw2_end_block = fw2_start_block + fw_num_blocks + extra_blocks - 1;
+ }
+
+#ifdef CONFIG_ENV_IS_IN_NAND
+ fail_if_overlap(fcb, env, "FCB", "Environment");
+ fail_if_overlap(fw1, env, "FW1", "Environment");
+#endif
+ fail_if_overlap(fcb, fw1, "FCB", "FW1");
+ if (fw2_set) {
+ fail_if_overlap(fcb, fw2, "FCB", "FW2");
+#ifdef CONFIG_ENV_IS_IN_NAND
+ fail_if_overlap(fw2, env, "FW2", "Environment");
+#endif
+ fail_if_overlap(fw1, fw2, "FW1", "FW2");
+ }
+
+ buf = malloc(erase_size);
+ if (buf == NULL) {
+ printf("Failed to allocate buffer\n");
+ return -ENOMEM;
+ }
+
+ /* search for bad blocks in FW1 block range */
+ max_len1 = count_good_blocks(fw1_start_block, fw1_end_block);
+ printf("%u good blocks in %lu..%lu\n",
+ max_len1, fw1_start_block, fw1_end_block);
+ if (fw_num_blocks > max_len1) {
+ printf("Too many bad blocks in FW1 block range: %lu..%lu; max blocks: %u\n",
+ fw1_end_block + 1 - fw_num_blocks - extra_blocks,
+ fw1_end_block, max_len1);
+ return -EINVAL;
+ }
+
+ /* search for bad blocks in FW2 block range */
+ max_len2 = count_good_blocks(fw2_start_block, fw2_end_block);
+ if (fw2_start_block > 0 && fw_num_blocks > max_len2) {
+ printf("Too many bad blocks in FW2 block range: %lu..%lu\n",
+ fw2_end_block + 1 - fw_num_blocks - extra_blocks,
+ fw2_end_block);
+ return -EINVAL;
+ }
+
+ fcb = create_fcb(buf, fw1_start_block, fw2_start_block,
+ ALIGN(fw_num_blocks * mtd->erasesize, mtd->writesize));
+ if (IS_ERR(fcb)) {
+ printf("Failed to initialize FCB: %ld\n", PTR_ERR(fcb));
+ return PTR_ERR(fcb);
+ }
+ encode_hamming_13_8(fcb, (void *)fcb + 512, 512);
+
+ ret = write_fcb(buf, fcb_start_block);
+ if (ret) {
+ printf("Failed to write FCB to block %lu\n", fcb_start_block);
+ return ret;
+ }
+
+ if (ret) {
+ }
+
+ ret = patch_ivt(addr, size ?: fw_num_blocks * mtd->erasesize);
+ if (ret) {
+ return ret;
+ }
+
+ printf("Programming U-Boot image from %p to block %lu\n",
+ addr, fw1_start_block);
+ if (size & (page_size - 1)) {
+ memset(addr + size, 0xff, size & (page_size - 1));
+ size = ALIGN(size, page_size);
+ }
+
+ erase_opts.offset = fcb->fw1_start_page * page_size;
+ erase_opts.length = (fw1_end_block - fw1_start_block + 1) *
+ mtd->erasesize;
+ erase_opts.quiet = 1;
+
+ printf("Erasing flash @ %08llx..%08llx\n", erase_opts.offset,
+ erase_opts.offset + erase_opts.length - 1);
+
+ ret = nand_erase_opts(mtd, &erase_opts);
+ if (ret) {
+ printf("Failed to erase flash: %d\n", ret);
+ return ret;
+ }
+ if (size == 0)
+ max_len1 *= mtd->erasesize;
+ else
+ max_len1 = size;
+
+ printf("Programming flash @ %08x..%08x from %p\n",
+ fcb->fw1_start_page * page_size,
+ fcb->fw1_start_page * page_size + max_len1 - 1, addr);
+ ret = nand_write_skip_bad(mtd, fcb->fw1_start_page * page_size,
+ &max_len1, addr, WITH_DROP_FFS);
+ if (ret) {
+ printf("Failed to program flash: %d\n", ret);
+ return ret;
+ }
+ if (fw2_start_block == 0) {
+ return ret;
+ }
+
+ printf("Programming redundant U-Boot image to block %lu\n",
+ fw2_start_block);
+ erase_opts.offset = fcb->fw2_start_page * page_size;
+ erase_opts.length = (fw2_end_block - fw2_start_block + 1) *
+ mtd->erasesize;
+ printf("Erasing flash @ %08llx..%08llx\n", erase_opts.offset,
+ erase_opts.offset + erase_opts.length - 1);
+
+ ret = nand_erase_opts(mtd, &erase_opts);
+ if (ret) {
+ printf("Failed to erase flash: %d\n", ret);
+ return ret;
+ }
+ if (size == 0)
+ max_len2 *= mtd->erasesize;
+ else
+ max_len2 = size;
+ printf("Programming flash @ %08x..%08x from %p\n",
+ fcb->fw2_start_page * page_size,
+ fcb->fw2_start_page * page_size + max_len2 - 1, addr);
+ ret = nand_write_skip_bad(mtd, fcb->fw2_start_page * page_size,
+ &max_len2, addr, WITH_DROP_FFS);
+ if (ret) {
+ printf("Failed to program flash: %d\n", ret);
+ return ret;
+ }
+ return ret;
+}
+
+U_BOOT_CMD(romupdate, 11, 0, do_update,
+ "Creates an FCB data structure and writes an U-Boot image to flash\n",
+ "[-f #] [-r [#]] [-e #] [<address>] [<length>]\n"
+ "\t-f #\twrite bootloader image at block #\n"
+ "\t-r\twrite redundant bootloader image at next free block after first image\n"
+ "\t-r #\twrite redundant bootloader image at block #\n"
+ "\t-e #\tspecify number of redundant blocks per boot loader image (default 2)\n"
+ "\t<address>\tRAM address of bootloader image (default: ${fileaddr}\n"
+ "\t<length>\tlength of bootloader image in RAM (default: ${filesize}"
+ );
--- /dev/null
+#include <config.h>
+#include <configs/tx6dl.h>
+#include <asm/arch/imx-regs.h>
+
+#define DEBUG_LED_BIT 20
+#define LED_GPIO_BASE GPIO2_BASE_ADDR
+#define LED_MUX_OFFSET 0x0ec
+#define LED_MUX_MODE 0x15
+
+#define SDRAM_CLK CONFIG_SYS_SDRAM_CLK
+
+#ifdef PHYS_SDRAM_2_SIZE
+#define SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
+#else
+#define SDRAM_SIZE PHYS_SDRAM_1_SIZE
+#endif
+
+#define CPU_2_BE_32(l) \
+ ((((l) << 24) & 0xFF000000) | \
+ (((l) << 8) & 0x00FF0000) | \
+ (((l) >> 8) & 0x0000FF00) | \
+ (((l) >> 24) & 0x000000FF))
+
+#define CHECK_DCD_ADDR(a) ( \
+ ((a) >= 0x020E0000 && (a) <= 0x020E3FFF) /* IOMUXC */ || \
+ ((a) >= 0x020C4000 && (a) <= 0x020C7FFF) /* CCM */ || \
+ ((a) >= 0x020C8000 && (a) <= 0x020C8FFF) /* ANALOG */ || \
+ ((a) >= 0x021B0000 && (a) <= 0x021B7FFF) /* MMDC */ || \
+ ((a) >= 0x00907000 && (a) <= 0x00937FF0) /* OCRAM */ || \
+ ((a) >= 0x08000000 && (a) <= 0x0FFEFFFF) /* EIM (CS0) */ || \
+ ((a) >= 0x10000000 && (a) <= 0xFFFFFFFF) /* SDRAM */)
+
+ .macro mxc_dcd_item addr, val
+ .ifne CHECK_DCD_ADDR(\addr)
+ .word CPU_2_BE_32(\addr), CPU_2_BE_32(\val)
+ .else
+ .error "Address \addr not accessible from DCD"
+ .endif
+ .endm
+
+#define MXC_DCD_ITEM(addr, val) mxc_dcd_item addr, val
+
+#define MXC_DCD_CMD_SZ_BYTE 1
+#define MXC_DCD_CMD_SZ_SHORT 2
+#define MXC_DCD_CMD_SZ_WORD 4
+#define MXC_DCD_CMD_FLAG_WRITE 0x0
+#define MXC_DCD_CMD_FLAG_CLR 0x1
+#define MXC_DCD_CMD_FLAG_SET 0x3
+#define MXC_DCD_CMD_FLAG_CHK_ANY (1 << 0)
+#define MXC_DCD_CMD_FLAG_CHK_SET (1 << 1)
+#define MXC_DCD_CMD_FLAG_CHK_CLR (0 << 1)
+
+#define MXC_DCD_CMD_WRT(type, flags, next) \
+ .word CPU_2_BE_32((0xcc << 24) | (((next) - .) << 8) | ((flags) << 3) | (type))
+
+#define MXC_DCD_CMD_CHK(type, flags, addr, mask) \
+ .word CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)),\
+ CPU_2_BE_32(addr), CPU_2_BE_32(mask)
+
+#define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count) \
+ .word CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)),\
+ CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count)
+
+#define MXC_DCD_CMD_NOP \
+ .word CPU_2_BE_32((0xc0 << 24) | (4 << 8))
+
+#define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
+#define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
+
+ .macro CK_VAL, name, clks, offs, max
+ .iflt \clks - \offs
+ .set \name, 0
+ .else
+ .ifle \clks - \offs - \max
+ .set \name, \clks - \offs
+ .else
+ .error "Value \clks out of range for parameter \name"
+ .endif
+ .endif
+ .endm
+
+ .macro NS_VAL, name, ns, offs, max
+ .iflt \ns - \offs
+ .set \name, 0
+ .else
+ CK_VAL \name, NS_TO_CK(\ns), \offs, \max
+ .endif
+ .endm
+
+ .macro CK_MAX, name, ck1, ck2, offs, max
+ .ifgt \ck1 - \ck2
+ CK_VAL \name, \ck1, \offs, \max
+ .else
+ CK_VAL \name, \ck2, \offs, \max
+ .endif
+ .endm
+
+#define MDMISC_DDR_TYPE_DDR3 0
+#define MDMISC_DDR_TYPE_LPDDR2 1
+#define MDMISC_DDR_TYPE_DDR2 2
+
+#define DIV_ROUND_UP(m,d) (((m) + (d) - 1) / (d))
+
+#define MDOR_CLK_PERIOD_ns 15258 /* base clock for MDOR values */
+
+/* DDR3 SDRAM */
+#if SDRAM_SIZE > PHYS_SDRAM_1_SIZE
+#define BANK_ADDR_BITS 2
+#else
+#define BANK_ADDR_BITS 1
+#endif
+#define SDRAM_BURST_LENGTH 8
+#define RALAT 5
+#define WALAT 0
+#define BI_ON 1
+#define ADDR_MIRROR 1
+#define DDR_TYPE MDMISC_DDR_TYPE_DDR3
+
+/* 512/1024MiB SDRAM: NT5CB128M16P-CG */
+/* MDCFG0 0x0c */
+NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */
+CK_MAX tXS, tRFC + 1 + NS_TO_CK(10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
+CK_MAX tXP, 3, NS_TO_CK(6), 1, 7 /* clks - 1 (0..7) */ /* max(6ns, 3*CK) */
+CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */
+NS_VAL tFAW, 45, 1, 31 /* clks - 1 (0..31) */
+CK_VAL tCL, 8, 3, 8 /* clks - 3 (0..8) CAS Latency */
+
+/* MDCFG1 0x10 */
+NS_VAL tRCD, 14, 1, 7 /* clks - 1 (0..7) */
+NS_VAL tRP, 14, 1, 7 /* clks - 1 (0..7) */
+NS_VAL tRC, 50, 1, 31 /* clks - 1 (0..31) */
+NS_VAL tRAS, 36, 1, 31 /* clks - 1 (0..31) */
+CK_VAL tRPA, 0, 0, 1 /* clks (0..1) */
+NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tCWL, 6, 2, 6 /* clks - 2 (0..6) */
+
+/* MDCFG2 0x14 */
+CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */
+CK_MAX tRTP, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
+CK_MAX tWTR, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
+CK_MAX tRRD, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
+
+/* MDOR 0x30 */
+CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
+#define tSDE_RST (DIV_ROUND_UP(200000, MDOR_CLK_PERIOD_ns) + 2)
+#define tRST_CKE (DIV_ROUND_UP(500000, MDOR_CLK_PERIOD_ns) + 2)
+
+/* MDOTC 0x08 */
+NS_VAL tAOFPD, 9, 1, 7 /* clks - 1 (0..7) */
+NS_VAL tAONPD, 9, 1, 7 /* clks - 1 (0..7) */
+CK_VAL tANPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tAXPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tODTLon tCWL, 1, 7 /* clks - 1 (0..7) */
+CK_VAL tODTLoff tCWL, 1, 31 /* clks - 1 (0..31) */
+
+/* MDPDC 0x04 */
+CK_MAX tCKE, NS_TO_CK(6), 3, 1, 7
+CK_MAX tCKSRX, NS_TO_CK(10), 5, 0, 7
+CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7
+
+#define PRCT 0
+#define PWDT 5
+#define SLOW_PD 0
+#define BOTH_CS_PD 1
+
+#define MDPDC_VAL_0 ( \
+ (PRCT << 28) | \
+ (PRCT << 24) | \
+ (tCKE << 16) | \
+ (SLOW_PD << 7) | \
+ (BOTH_CS_PD << 6) | \
+ (tCKSRX << 3) | \
+ (tCKSRE << 0) \
+ )
+
+#define MDPDC_VAL_1 (MDPDC_VAL_0 | \
+ (PWDT << 12) | \
+ (PWDT << 8) \
+ )
+
+#define ROW_ADDR_BITS 14
+#define COL_ADDR_BITS 10
+
+ .iflt tWR - 7
+ .set mr0_val, ((1 << 8) /* DLL Reset */ | \
+ ((tWR + 1 - 4) << 9) | \
+ (((tCL + 3) - 4) << 4))
+ .else
+ .set mr0_val, ((1 << 8) /* DLL Reset */ | \
+ (((tWR + 1) / 2) << 9) | \
+ (((tCL + 3) - 4) << 4))
+ .endif
+
+#define MDSCR_MRS_VAL(cs, mr, val) (((val) << 16) | \
+ (1 << 15) /* CON REQ */ | \
+ (3 << 4) /* MRS command */ | \
+ ((cs) << 3) | \
+ ((mr) << 0))
+
+#define mr1_val 0x0040
+#define mr2_val 0x0408
+
+#define MDCFG0_VAL ( \
+ (tRFC << 24) | \
+ (tXS << 16) | \
+ (tXP << 13) | \
+ (tXPDLL << 9) | \
+ (tFAW << 4) | \
+ (tCL << 0)) \
+
+#define MDCFG1_VAL ( \
+ (tRCD << 29) | \
+ (tRP << 26) | \
+ (tRC << 21) | \
+ (tRAS << 16) | \
+ (tRPA << 15) | \
+ (tWR << 9) | \
+ (tMRD << 5) | \
+ (tCWL << 0)) \
+
+#define MDCFG2_VAL ( \
+ (tDLLK << 16) | \
+ (tRTP << 6) | \
+ (tWTR << 3) | \
+ (tRRD << 0))
+
+#define BURST_LEN (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */
+
+#if PHYS_SDRAM_1_WIDTH == 64
+#define MDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \
+ ((COL_ADDR_BITS - 9) << 20) | \
+ (BURST_LEN << 19) | \
+ (2 << 16) | /* SDRAM bus width */ \
+ ((-1) << (32 - BANK_ADDR_BITS)))
+#else
+#define MDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \
+ ((COL_ADDR_BITS - 9) << 20) | \
+ (BURST_LEN << 19) | \
+ (1 << 16) | /* SDRAM bus width */ \
+ ((-1) << (32 - BANK_ADDR_BITS)))
+#endif
+
+#define MDMISC_VAL ((ADDR_MIRROR << 19) | \
+ (WALAT << 16) | \
+ (BI_ON << 12) | \
+ (0x3 << 9) | \
+ (RALAT << 6) | \
+ (DDR_TYPE << 3))
+
+#define MDOR_VAL ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0))
+
+#define MDOTC_VAL ((tAOFPD << 27) | \
+ (tAONPD << 24) | \
+ (tANPD << 20) | \
+ (tAXPD << 16) | \
+ (tODTLon << 12) | \
+ (tODTLoff << 4))
+
+fcb_start:
+ b _start
+ .org 0x400
+ivt_header:
+ .word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40)
+app_start_addr:
+ .long _start
+ .long 0x0
+dcd_ptr:
+ .long dcd_hdr
+boot_data_ptr:
+ .word boot_data
+self_ptr:
+ .word ivt_header
+app_code_csf:
+ .word 0x0
+ .word 0x0
+boot_data:
+ .long fcb_start
+image_len:
+ .long CONFIG_U_BOOT_IMG_SIZE
+plugin:
+ .word 0
+ivt_end:
+#define DCD_VERSION 0x40
+
+#define CLKCTL_CCGR0 0x68
+#define CLKCTL_CCGR1 0x6c
+#define CLKCTL_CCGR2 0x70
+#define CLKCTL_CCGR3 0x74
+#define CLKCTL_CCGR4 0x78
+#define CLKCTL_CCGR5 0x7c
+#define CLKCTL_CCGR6 0x80
+#define CLKCTL_CCGR7 0x84
+#define CLKCTL_CMEOR 0x88
+
+#define DDR_SEL_VAL 3
+#define DSE_VAL 6
+#define ODT_VAL 2
+
+#define DDR_SEL_SHIFT 18
+#define DDR_MODE_SHIFT 17
+#define ODT_SHIFT 8
+#define DSE_SHIFT 3
+#define HYS_SHIFT 16
+#define PKE_SHIFT 12
+#define PUE_SHIFT 13
+#define PUS_SHIFT 14
+
+#define DDR_SEL_MASK (DDR_SEL_VAL << DDR_SEL_SHIFT)
+#define DDR_MODE_MASK (1 << DDR_MODE_SHIFT)
+#define DSE_MASK (DSE_VAL << DSE_SHIFT)
+#define ODT_MASK (ODT_VAL << ODT_SHIFT)
+
+#define DQM_MASK (DDR_MODE_MASK | DSE_MASK)
+#define SDQS_MASK DSE_MASK
+#define SDODT_MASK (DSE_MASK | (1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
+#define SDCLK_MASK (DDR_MODE_MASK | DSE_MASK)
+#define SDCKE_MASK ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
+#define DDR_ADDR_MASK 0
+#define DDR_CTRL_MASK (DDR_MODE_MASK | DSE_MASK)
+
+#define CCM_CCR 0x020c4000
+#define CCM_CS2CDR 0x020c402c
+#define CCM_CCGR0 0x020c4068
+#define CCM_CCGR1 0x020c406c
+#define CCM_CCGR2 0x020c4070
+#define CCM_CCGR3 0x020c4074
+#define CCM_CCGR4 0x020c4078
+#define CCM_CCGR5 0x020c407c
+#define CCM_CCGR6 0x020c4080
+#define CCM_ANALOG_PLL_ENET 0x020c80e0
+#define MMDC1_MDCTL 0x021b0000
+#define MMDC1_MDPDC 0x021b0004
+#define MMDC1_MDOTC 0x021b0008
+#define MMDC1_MDCFG0 0x021b000c
+#define MMDC1_MDCFG1 0x021b0010
+#define MMDC1_MDCFG2 0x021b0014
+#define MMDC1_MDMISC 0x021b0018
+#define MMDC1_MDSCR 0x021b001c
+#define MMDC1_MDREF 0x021b0020
+#define MMDC1_MDRWD 0x021b002c
+#define MMDC1_MDOR 0x021b0030
+#define MMDC1_MDASP 0x021b0040
+#define MMDC1_MAPSR 0x021b0404
+#define MMDC1_MPZQHWCTRL 0x021b0800
+#define MMDC1_MPWLGCR 0x021b0808
+#define MMDC1_MPODTCTRL 0x021b0818
+#define MMDC1_MPRDDQBY0DL 0x021b081c
+#define MMDC1_MPRDDQBY1DL 0x021b0820
+#define MMDC1_MPRDDQBY2DL 0x021b0824
+#define MMDC1_MPRDDQBY3DL 0x021b0828
+#define MMDC1_MPDGCTRL0 0x021b083c
+#define MMDC1_MPRDDLCTL 0x021b0848
+#define MMDC1_MPWRDLCTL 0x021b0850
+#define MMDC1_MPRDDLHWCTL 0x021b0860
+#define MMDC1_MPWRDLHWCTL 0x021b0864
+#define MMDC1_MPPDCMPR2 0x021b0890
+#define MMDC1_MPMUR0 0x021b08b8
+#define MMDC2_MPZQHWCTRL 0x021b4800
+#define MMDC2_MPWLGCR 0x021b4808
+#define MMDC2_MPODTCTRL 0x021b4818
+#define MMDC2_MPRDDQBY0DL 0x021b481c
+#define MMDC2_MPRDDQBY1DL 0x021b4820
+#define MMDC2_MPRDDQBY2DL 0x021b4824
+#define MMDC2_MPRDDQBY3DL 0x021b4828
+#define MMDC2_MPDGCTRL0 0x021b483c
+#define MMDC2_MPRDDLCTL 0x021b4848
+#define MMDC2_MPWRDLCTL 0x021b4850
+#define MMDC2_MPRDDLHWCTL 0x021b4860
+#define MMDC2_MPWRDLHWCTL 0x021b4864
+#define MMDC2_MPMUR0 0x021b48b8
+
+#ifdef CONFIG_MX6Q
+#define IOMUXC_GPR1 0x020e0004
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO17 0x020e024c
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7 0x020e02a8
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6 0x020e02ac
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0 0x020e02c0
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1 0x020e02c4
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE 0x020e02d4
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE 0x020e02d8
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B 0x020e02dc
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_READY 0x020e02e0
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B 0x020e02e4
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B 0x020e02ec
+#define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD 0x020e02f4
+#define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK 0x020e02f8
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 0x020e02fc
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 0x020e0300
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 0x020e0304
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 0x020e0308
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 0x020e030c
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 0x020e0310
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 0x020e0314
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 0x020e0318
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P 0x020e050c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 0x020e0510
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 0x020e0514
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P 0x020e0518
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P 0x020e051c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 0x020e0520
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P 0x020e0524
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 0x020e0528
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00 0x020e052c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01 0x020e0530
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 0x020e0534
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 0x020e0538
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 0x020e053c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 0x020e0540
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 0x020e0544
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 0x020e0548
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 0x020e054c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 0x020e0550
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10 0x020e0554
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11 0x020e0558
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12 0x020e055c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13 0x020e0560
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14 0x020e0564
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15 0x020e0568
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS 0x020e056c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS 0x020e0578
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET 0x020e057c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0 0x020e0580
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1 0x020e0584
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P 0x020e0588
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 0x020e058c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 0x020e0590
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P 0x020e0594
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 0x020e0598
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 0x020e059c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 0x020e05a0
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P 0x020e05a8
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 0x020e05ac
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P 0x020e05b0
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 0x020e05b4
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P 0x020e05b8
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 0x020e05bc
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P 0x020e05c0
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 0x020e05c4
+#define IOMUXC_SW_PAD_CTL_GRP_B7DS 0x020e0748
+#define IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x020e074c
+#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 0x020e0750
+#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0 0x020e0754
+#define IOMUXC_SW_PAD_CTL_GRP_DDRPKE 0x020e0758
+#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1 0x020e075c
+#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2 0x020e0760
+#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3 0x020e0764
+#define IOMUXC_SW_PAD_CTL_GRP_DDRPK 0x020e0768
+#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4 0x020e076c
+#define IOMUXC_SW_PAD_CTL_GRP_DDRHYS 0x020e0770
+#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE 0x020e0774
+#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5 0x020e0778
+#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6 0x020e077c
+#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7 0x020e0780
+#define IOMUXC_SW_PAD_CTL_GRP_B0DS 0x020e0784
+#define IOMUXC_SW_PAD_CTL_GRP_B1DS 0x020e0788
+#define IOMUXC_SW_PAD_CTL_GRP_CTLDS 0x020e078c
+#define IOMUXC_SW_PAD_CTL_GRP_B2DS 0x020e0794
+#define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE 0x020e0798
+#define IOMUXC_SW_PAD_CTL_GRP_B3DS 0x020e079c
+#define IOMUXC_SW_PAD_CTL_GRP_B4DS 0x020e07a0
+#define IOMUXC_SW_PAD_CTL_GRP_B5DS 0x020e07a4
+#define IOMUXC_SW_PAD_CTL_GRP_B6DS 0x020e07a8
+#define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT 0x020e091c
+#define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x020e0920
+#endif
+
+#ifdef CONFIG_MX6DL
+#define IOMUXC_GPR1 0x020e0004
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO17 0x020e0218
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7 0x020e0330
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6 0x020e032c
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0 0x020e0314
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1 0x020e0318
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE 0x020e0270
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE 0x020e026c
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B 0x020e02a8
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_READY 0x020e02a4
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B 0x020e0274
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B 0x020e027c
+#define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD 0x020e033c
+#define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK 0x020e0338
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 0x020e0284
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 0x020e0288
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 0x020e028c
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 0x020e0290
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 0x020e0294
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 0x020e0298
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 0x020e029c
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 0x020e02a0
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P 0x020e04d0
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 0x020e0484
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 0x020e0480
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P 0x020e04cc
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P 0x020e04c8
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 0x020e047c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P 0x020e04c4
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 0x020e0478
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00 0x020e0424
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01 0x020e0428
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 0x020e0444
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 0x020e0448
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 0x020e044c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 0x020e0450
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 0x020e0454
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 0x020e0458
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 0x020e045c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 0x020e0460
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10 0x020e042c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11 0x020e0430
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12 0x020e0434
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13 0x020e0438
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14 0x020e043c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15 0x020e0440
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS 0x020e0464
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS 0x020e0490
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET 0x020e0494
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0 0x020e0498
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1 0x020e049c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P 0x020e04ac
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 0x020e04a0
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 0x020e04a4
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P 0x020e04b0
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 0x020e04a8
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 0x020e04b4
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 0x020e04b8
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P 0x020e04bc
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 0x020e0470
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P 0x020e04c0
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 0x020e0474
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P 0x020e04d4
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 0x020e0488
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P 0x020e04d8
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 0x020e048c
+#define IOMUXC_SW_PAD_CTL_GRP_B7DS 0x020e0748
+#define IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x020e074c
+#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 0x020e0750
+#define IOMUXC_SW_PAD_CTL_GRP_DDRPKE 0x020e0754
+#define IOMUXC_SW_PAD_CTL_GRP_DDRPK 0x020e0754
+#define IOMUXC_SW_PAD_CTL_GRP_DDRHYS 0x020e075c
+#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE 0x020e0760
+#define IOMUXC_SW_PAD_CTL_GRP_B0DS 0x020e0784
+#define IOMUXC_SW_PAD_CTL_GRP_B1DS 0x020e0788
+#define IOMUXC_SW_PAD_CTL_GRP_CTLDS 0x020e078c
+#define IOMUXC_SW_PAD_CTL_GRP_B2DS 0x020e0794
+#define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE 0x020e0798
+#define IOMUXC_SW_PAD_CTL_GRP_B3DS 0x020e079c
+#define IOMUXC_SW_PAD_CTL_GRP_B4DS 0x020e07a0
+#define IOMUXC_SW_PAD_CTL_GRP_B5DS 0x020e07a4
+#define IOMUXC_SW_PAD_CTL_GRP_B6DS 0x020e07a8
+#define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT 0x020e091c
+#define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x020e0920
+#endif
+
+
+dcd_hdr:
+ .word CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION)
+dcd_start:
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, ddr_reset)
+ /* RESET_OUT GPIO_7_12 */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_GPIO17, 0x00000005)
+
+ MXC_DCD_ITEM(CCM_CS2CDR, 0x006336c1) /* CS2CDR default: 0x007236c1 */
+
+ MXC_DCD_ITEM(CCM_ANALOG_PLL_ENET, 0x00002001) /* ENET PLL */
+
+ /* enable all relevant clocks... */
+ MXC_DCD_ITEM(CCM_CCGR0, 0xf0c03f3f) /* default: 0xf0c03f0f APBH-DMA */
+ MXC_DCD_ITEM(CCM_CCGR1, 0xf0fc0c00) /* default: 0xf0fc0000 */
+ MXC_DCD_ITEM(CCM_CCGR2, 0xfc3ff0cc) /* default: 0xfc3ff00c I2C1 */
+ MXC_DCD_ITEM(CCM_CCGR3, 0x3ff00000) /* default: 0x3ff00000 */
+ MXC_DCD_ITEM(CCM_CCGR4, 0xff00ff00) /* default: 0x0000ff00 GPMI BCH */
+ MXC_DCD_ITEM(CCM_CCGR5, 0xff033f0f) /* default: 0xf0033f0f UART1 */
+ MXC_DCD_ITEM(CCM_CCGR6, 0xffff03ff) /* default: 0xffff0003 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) */
+
+ /* IOMUX: */
+ MXC_DCD_ITEM(IOMUXC_GPR1, 0x48640005) /* default: 0x48400005 ENET_CLK output */
+ /* UART1 pad config */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7, 0x00000001) /* UART1 TXD */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6, 0x00000001) /* UART1 RXD */
+ MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000003) /* UART1 RXD INPUT_SEL */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0, 0x00000001) /* UART1 CTS */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1, 0x00000001) /* UART1 RTS */
+ MXC_DCD_ITEM(IOMUXC_UART1_UART_RTS_B_SELECT_INPUT, 0x00000003) /* UART1 RTS INPUT_SEL */
+
+ /* NAND */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CLE, 0x00000000) /* NANDF_CLE: NANDF_CLE */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_ALE, 0x00000000) /* NANDF_ALE: NANDF_ALE */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B, 0x00000000) /* NANDF_WP_B: NANDF_WPn */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_READY, 0x00000000) /* NANDF_RB0: NANDF_READY0 */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B, 0x00000000) /* NANDF_CS0: NANDF_CS0 */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD4_CMD, 0x00000001) /* SD4_CMD: NANDF_RDn */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD4_CLK, 0x00000001) /* SD4_CLK: NANDF_WRn */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00, 0x00000000) /* NANDF_D0: NANDF_D0 */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01, 0x00000000) /* NANDF_D1: NANDF_D1 */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02, 0x00000000) /* NANDF_D2: NANDF_D2 */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03, 0x00000000) /* NANDF_D3: NANDF_D3 */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04, 0x00000000) /* NANDF_D4: NANDF_D4 */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05, 0x00000000) /* NANDF_D5: NANDF_D5 */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06, 0x00000000) /* NANDF_D6: NANDF_D6 */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07, 0x00000000) /* NANDF_D7: NANDF_D7 */
+
+ /* ext. mem CS */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B, 0x00000000) /* NANDF_CS2: NANDF_CS2 */
+ /* DRAM_DQM[0..7] */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, DQM_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, DQM_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, DQM_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, DQM_MASK)
+#if PHYS_SDRAM_1_WIDTH == 64
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4, DQM_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5, DQM_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6, DQM_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7, DQM_MASK)
+#endif
+
+ /* DRAM_A[0..15] */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15, DDR_ADDR_MASK)
+ /* DRAM_CAS */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS, DDR_CTRL_MASK)
+ /* DRAM_RAS */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS, DDR_CTRL_MASK)
+ /* DRAM_SDCLK[0..1] */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P, SDCLK_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P, SDCLK_MASK)
+ /* DRAM_RESET */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET, DDR_CTRL_MASK)
+ /* DRAM_SDCKE[0..1] */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0, SDCKE_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1, SDCKE_MASK)
+ /* DRAM_SDBA[0..2] */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0, 0x00000000)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1, 0x00000000)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2, 0x00000000)
+ /* DRAM_SDODT[0..1] */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0, SDODT_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1, SDODT_MASK)
+ /* DRAM_B[0..7]DS */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B0DS, DSE_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B1DS, DSE_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B2DS, DSE_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B3DS, DSE_MASK)
+#if PHYS_SDRAM_1_WIDTH == 64
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B4DS, DSE_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B5DS, DSE_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B6DS, DSE_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B7DS, DSE_MASK)
+#endif
+ /* ADDDS */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_ADDDS, DSE_MASK)
+ /* DDRMODE_CTL */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL, DDR_MODE_MASK)
+ /* DDRPKE */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPKE, 0x00000000)
+ /* DDRMODE */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE, DDR_MODE_MASK)
+ /* CTLDS */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_CTLDS, DSE_MASK)
+ /* DDR_TYPE */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE, DDR_SEL_MASK)
+ /* DDRPK */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPK, 1 << PUE_SHIFT)
+ /* DDRHYS */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRHYS, 0x00000000)
+
+#ifdef CONFIG_MX6Q
+ /* TERM_CTL[0..7] */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0, ODT_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1, ODT_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2, ODT_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3, ODT_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4, ODT_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5, ODT_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6, ODT_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7, ODT_MASK)
+#endif
+
+ /* SDRAM initialization */
+ /* MPRDDQBY[0..7]DL */
+ MXC_DCD_ITEM(MMDC1_MPRDDQBY0DL, 0x33333333)
+ MXC_DCD_ITEM(MMDC1_MPRDDQBY1DL, 0x33333333)
+ MXC_DCD_ITEM(MMDC1_MPRDDQBY2DL, 0x33333333)
+ MXC_DCD_ITEM(MMDC1_MPRDDQBY3DL, 0x33333333)
+#if PHYS_SDRAM_1_WIDTH == 64
+ MXC_DCD_ITEM(MMDC2_MPRDDQBY0DL, 0x33333333)
+ MXC_DCD_ITEM(MMDC2_MPRDDQBY1DL, 0x33333333)
+ MXC_DCD_ITEM(MMDC2_MPRDDQBY2DL, 0x33333333)
+ MXC_DCD_ITEM(MMDC2_MPRDDQBY3DL, 0x33333333)
+#endif
+ /* MDMISC */
+ MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL | 2) /* reset MMDC FSM */
+ddr_reset:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MDMISC, 0x00000002)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack)
+
+ /* MSDSCR Conf Req */
+ MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008000)
+con_ack:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDSCR, 0x00004000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, ddr_calib)
+ /* MDCTL */
+ MXC_DCD_ITEM(MMDC1_MDCTL, MDCTL_VAL)
+ddr_calib:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDMISC, 0x40000000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, zq_calib)
+
+ MXC_DCD_ITEM(MMDC1_MDCFG0, MDCFG0_VAL)
+ MXC_DCD_ITEM(MMDC1_MDCFG1, MDCFG1_VAL)
+ MXC_DCD_ITEM(MMDC1_MDCFG2, MDCFG2_VAL)
+ MXC_DCD_ITEM(MMDC1_MDRWD, 0x000026d2) /* MDRWD */
+ MXC_DCD_ITEM(MMDC1_MDOR, MDOR_VAL)
+ MXC_DCD_ITEM(MMDC1_MDOTC, MDOTC_VAL)
+ MXC_DCD_ITEM(MMDC1_MDPDC, MDPDC_VAL_0)
+ MXC_DCD_ITEM(MMDC1_MDASP, 0x00000017) /* MDASP */
+
+ /* CS0 MRS: */
+ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 0, mr0_val))
+ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 1, mr1_val))
+ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 2, mr2_val))
+ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0))
+#if BANK_ADDR_BITS > 1
+ /* CS1 MRS: MR2 */
+ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 0, mr0_val))
+ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 1, mr1_val))
+ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 2, mr2_val))
+ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */
+#endif
+
+ MXC_DCD_ITEM(MMDC1_MDREF, 0x0000c000) /* disable refresh */
+
+ MXC_DCD_ITEM(MMDC1_MPODTCTRL, 0x00011112) /* MPODTCTRL */
+#if PHYS_SDRAM_1_WIDTH == 64
+ MXC_DCD_ITEM(MMDC2_MPODTCTRL, 0x00011112)
+#endif
+
+ /* DDR3 calibration */
+ MXC_DCD_ITEM(MMDC1_MPPDCMPR2, 0x00000003) /* select default compare pattern for DQ calibration */
+ MXC_DCD_ITEM(MMDC1_MAPSR, 0x00011007)
+
+ /* ZQ calibration */
+ MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008010) /* precharge all */
+ MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008040) /* MRS: ZQ calibration */
+
+ MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa139002b)
+#if PHYS_SDRAM_1_WIDTH == 64
+ MXC_DCD_ITEM(MMDC2_MPZQHWCTRL, 0xa138002b)
+#endif
+
+zq_calib:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPZQHWCTRL, 0x00010000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wl_calib)
+
+ /* Write leveling */
+ MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1380000)
+#if PHYS_SDRAM_1_WIDTH == 64
+ MXC_DCD_ITEM(MMDC2_MPZQHWCTRL, 0xa1380000)
+#endif
+
+ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */
+ MXC_DCD_ITEM(MMDC1_MDSCR, 0x00808231) /* MRS: start write leveling */
+
+ MXC_DCD_ITEM(MMDC1_MPWLGCR, 0x00000001) /* initiate Write leveling */
+wl_calib:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWLGCR, 0x00000001)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWLGCR, 0x00000f00)
+#if PHYS_SDRAM_1_WIDTH == 64
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWLGCR, 0x00000001)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWLGCR, 0x00000f00)
+#endif
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_fifo_reset)
+
+ MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa138002b)
+#if PHYS_SDRAM_1_WIDTH == 64
+ MXC_DCD_ITEM(MMDC2_MPZQHWCTRL, 0xa138002b)
+#endif
+
+ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: end write leveling */
+
+ /* DQS gating calibration */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK | 0x7000) /* enable Pullups on DQS pads */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK | 0x7000)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK | 0x7000)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK | 0x7000)
+#if PHYS_SDRAM_1_WIDTH == 64
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, SDQS_MASK | 0x7000)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK | 0x7000)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK | 0x7000)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK | 0x7000)
+#endif
+ MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL | (7 << 6) | (3 << 16)) /* RALAT/WALAT max. */
+
+ MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008020) /* issue one refresh cycle */
+ MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
+
+ MXC_DCD_ITEM(MMDC1_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
+ MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
+ MXC_DCD_ITEM(MMDC1_MPMUR0, 0x00000800)
+#if PHYS_SDRAM_1_WIDTH == 64
+ MXC_DCD_ITEM(MMDC2_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
+ MXC_DCD_ITEM(MMDC2_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
+ MXC_DCD_ITEM(MMDC2_MPMUR0, 0x00000800)
+#endif
+
+ MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x80000000) /* issue fifo reset */
+dqs_fifo_reset:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_fifo_reset2)
+ MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x80000000) /* issue 2nd fifo reset */
+dqs_fifo_reset2:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_calib)
+ MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x50800000) /* choose 32 wait cycles and start DQS calib. */
+dqs_calib:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x10000000)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x00001000)
+#if PHYS_SDRAM_1_WIDTH == 64
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPDGCTRL0, 0x10000000)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPDGCTRL0, 0x00001000)
+#endif
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, rd_dl_calib)
+
+ /* DRAM_SDQS[0..7] pad config */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK)
+#if PHYS_SDRAM_1_WIDTH == 64
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, SDQS_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK)
+#endif
+
+ MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL)
+
+ /* Read delay calibration */
+ MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
+ MXC_DCD_ITEM(MMDC1_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_RD_DL_EN */
+rd_dl_calib:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x00000010)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x0000000f)
+#if PHYS_SDRAM_1_WIDTH == 64
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x00000010)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x0000000f)
+#endif
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib)
+
+ MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
+ MXC_DCD_ITEM(MMDC1_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */
+wr_dl_calib:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x00000010)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x0000000f)
+#if PHYS_SDRAM_1_WIDTH == 64
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x00000010)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x0000000f)
+#endif
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack_clr)
+
+ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
+ MXC_DCD_ITEM(MMDC1_MDREF, 0x00005800) /* MDREF */
+ MXC_DCD_ITEM(MMDC1_MAPSR, 0x00011006) /* MAPSR */
+ MXC_DCD_ITEM(MMDC1_MDPDC, MDPDC_VAL_1)
+
+ /* MDSCR: Normal operation */
+ MXC_DCD_ITEM(MMDC1_MDSCR, 0x00000000)
+
+con_ack_clr:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MDSCR, 0x00004000)
+dcd_end:
+ .ifgt dcd_end - dcd_start - 1768
+ .error "DCD too large!"
+ .endif
--- /dev/null
+/*
+ * Copyright (C) 2012 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef DEBUG
+#define DEBUG
+#endif
+//#define TIMER_TEST
+
+#include <common.h>
+#include <errno.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <lcd.h>
+#include <netdev.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <video_fb.h>
+#include <ipu.h>
+#include <mx2fb.h>
+#include <linux/fb.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/iomux-mx6dl.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/sys_proto.h>
+
+#include "../common/karo.h"
+
+#define TX6DL_FEC_RST_GPIO IMX_GPIO_NR(7, 6)
+#define TX6DL_FEC_PWR_GPIO IMX_GPIO_NR(3, 20)
+#define TX6DL_FEC_INT_GPIO IMX_GPIO_NR(2, 4)
+#define TX6DL_LED_GPIO IMX_GPIO_NR(2, 20)
+
+#define TX6DL_LCD_PWR_GPIO IMX_GPIO_NR(2, 31)
+#define TX6DL_LCD_RST_GPIO IMX_GPIO_NR(3, 29)
+#define TX6DL_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
+
+#define TX6DL_RESET_OUT_GPIO IMX_GPIO_NR(7, 12)
+
+#define TEMPERATURE_MIN -40
+#define TEMPERATURE_HOT 80
+#define TEMPERATURE_MAX 125
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MUX_CFG_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
+
+static const iomux_v3_cfg_t tx6dl_pads[] = {
+ /* NAND flash pads */
+ MX6DL_PAD_NANDF_CLE__RAWNAND_CLE,
+ MX6DL_PAD_NANDF_ALE__RAWNAND_ALE,
+ MX6DL_PAD_NANDF_WP_B__RAWNAND_RESETN,
+ MX6DL_PAD_NANDF_RB0__RAWNAND_READY0,
+ MX6DL_PAD_NANDF_CS0__RAWNAND_CE0N,
+ MX6DL_PAD_SD4_CMD__RAWNAND_RDN,
+ MX6DL_PAD_SD4_CLK__RAWNAND_WRN,
+ MX6DL_PAD_NANDF_D0__RAWNAND_D0,
+ MX6DL_PAD_NANDF_D1__RAWNAND_D1,
+ MX6DL_PAD_NANDF_D2__RAWNAND_D2,
+ MX6DL_PAD_NANDF_D3__RAWNAND_D3,
+ MX6DL_PAD_NANDF_D4__RAWNAND_D4,
+ MX6DL_PAD_NANDF_D5__RAWNAND_D5,
+ MX6DL_PAD_NANDF_D6__RAWNAND_D6,
+ MX6DL_PAD_NANDF_D7__RAWNAND_D7,
+
+ /* RESET_OUT */
+ MX6DL_PAD_GPIO_17__GPIO_7_12,
+
+ /* UART pads */
+#if CONFIG_MXC_UART_BASE == UART1_BASE
+ MX6DL_PAD_SD3_DAT7__UART1_TXD,
+ MX6DL_PAD_SD3_DAT6__UART1_RXD,
+ MX6DL_PAD_SD3_DAT1__UART1_RTS,
+ MX6DL_PAD_SD3_DAT0__UART1_CTS,
+#endif
+#if CONFIG_MXC_UART_BASE == UART2_BASE
+ MX6DL_PAD_SD4_DAT4__UART2_RXD,
+ MX6DL_PAD_SD4_DAT7__UART2_TXD,
+ MX6DL_PAD_SD4_DAT5__UART2_RTS,
+ MX6DL_PAD_SD4_DAT6__UART2_CTS,
+#endif
+#if CONFIG_MXC_UART_BASE == UART3_BASE
+ MX6DL_PAD_EIM_D24__UART3_TXD,
+ MX6DL_PAD_EIM_D25__UART3_RXD,
+ MX6DL_PAD_SD3_RST__UART3_RTS,
+ MX6DL_PAD_SD3_DAT3__UART3_CTS,
+#endif
+ /* internal I2C */
+ MX6DL_PAD_EIM_D28__I2C1_SDA,
+ MX6DL_PAD_EIM_D21__I2C1_SCL,
+
+ /* FEC PHY GPIO functions */
+ MX6DL_PAD_EIM_D20__GPIO_3_20 | MUX_CFG_SION, /* PHY POWER */
+ MX6DL_PAD_SD3_DAT2__GPIO_7_6 | MUX_CFG_SION, /* PHY RESET */
+ MX6DL_PAD_SD3_DAT4__GPIO_7_1, /* PHY INT */
+};
+
+static const iomux_v3_cfg_t tx6dl_fec_pads[] = {
+ /* FEC functions */
+ MX6DL_PAD_ENET_MDC__ENET_MDC,
+ MX6DL_PAD_ENET_MDIO__ENET_MDIO,
+ MX6DL_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT,
+ MX6DL_PAD_ENET_RX_ER__ENET_RX_ER,
+ MX6DL_PAD_ENET_CRS_DV__ENET_RX_EN,
+ MX6DL_PAD_ENET_RXD1__ENET_RDATA_1,
+ MX6DL_PAD_ENET_RXD0__ENET_RDATA_0,
+ MX6DL_PAD_ENET_TX_EN__ENET_TX_EN,
+ MX6DL_PAD_ENET_TXD1__ENET_TDATA_1,
+ MX6DL_PAD_ENET_TXD0__ENET_TDATA_0,
+};
+
+static const struct gpio tx6dl_gpios[] = {
+ { TX6DL_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
+ { TX6DL_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
+ { TX6DL_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
+ { TX6DL_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
+};
+
+/*
+ * Functions
+ */
+/* placed in section '.data' to prevent overwriting relocation info
+ * overlayed with bss
+ */
+static u32 wrsr __attribute__((section(".data")));
+
+#define WRSR_POR (1 << 4)
+#define WRSR_TOUT (1 << 1)
+#define WRSR_SFTW (1 << 0)
+
+static void print_reset_cause(void)
+{
+ struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+ void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
+ u32 srsr;
+ char *dlm = "";
+
+ printf("Reset cause: ");
+
+ srsr = readl(&src_regs->srsr);
+ wrsr = readw(wdt_base + 4);
+
+ if (wrsr & WRSR_POR) {
+ printf("%sPOR", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x00004) {
+ printf("%sCSU", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x00008) {
+ printf("%sIPP USER", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x00010) {
+ if (wrsr & WRSR_SFTW) {
+ printf("%sSOFT", dlm);
+ dlm = " | ";
+ }
+ if (wrsr & WRSR_TOUT) {
+ printf("%sWDOG", dlm);
+ dlm = " | ";
+ }
+ }
+ if (srsr & 0x00020) {
+ printf("%sJTAG HIGH-Z", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x00040) {
+ printf("%sJTAG SW", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x10000) {
+ printf("%sWARM BOOT", dlm);
+ dlm = " | ";
+ }
+ if (dlm[0] == '\0')
+ printf("unknown");
+
+ printf("\n");
+}
+
+int read_cpu_temperature(void);
+int check_cpu_temperature(int boot);
+
+static void print_cpuinfo(void)
+{
+ u32 cpurev = get_cpu_rev();
+ char *cpu_str = "?";
+
+ switch ((cpurev >> 12) & 0xff) {
+ case MXC_CPU_MX6SL:
+ cpu_str = "SL";
+ break;
+ case MXC_CPU_MX6DL:
+ cpu_str = "DL";
+ break;
+ case MXC_CPU_MX6SOLO:
+ cpu_str = "SOLO";
+ break;
+ case MXC_CPU_MX6Q:
+ cpu_str = "Q";
+ break;
+ }
+
+ printf("CPU: Freescale i.MX6%s rev%d.%d at %d MHz\n",
+ cpu_str,
+ (cpurev & 0x000F0) >> 4,
+ (cpurev & 0x0000F) >> 0,
+ mxc_get_clock(MXC_ARM_CLK) / 1000000);
+
+ print_reset_cause();
+ check_cpu_temperature(1);
+}
+
+#define LTC3676_DVB2A 0x0C
+#define LTC3676_DVB2B 0x0D
+#define LTC3676_DVB4A 0x10
+#define LTC3676_DVB4B 0x11
+
+#define VDD_SOC_mV (1375 + 50)
+#define VDD_CORE_mV (1375 + 50)
+
+#define mV_to_regval(mV) (((mV) * 360 / 330 - 825 + 1) / 25)
+#define regval_to_mV(v) (((v) * 25 + 825) * 330 / 360)
+
+static int setup_pmic_voltages(void)
+{
+ int ret;
+ unsigned char value;
+
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+ ret = i2c_probe(CONFIG_SYS_I2C_SLAVE);
+ if (ret != 0) {
+ printf("Failed to initialize I2C\n");
+ return ret;
+ }
+
+ ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1);
+ if (ret) {
+ printf("%s: i2c_read error: %d\n", __func__, ret);
+ return ret;
+ }
+
+ /* VDDCORE/VDDSOC default 1.375V is not enough, considering
+ pfuze tolerance and IR drop and ripple, need increase
+ to 1.425V for SabreSD */
+
+ value = 0x39; /* VB default value & PGOOD not forced when slewing */
+ ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB2B, 1, &value, 1);
+ if (ret) {
+ printf("%s: failed to write PMIC DVB2B register: %d\n",
+ __func__, ret);
+ return ret;
+ }
+ ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB4B, 1, &value, 1);
+ if (ret) {
+ printf("%s: failed to write PMIC DVB4B register: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ value = mV_to_regval(VDD_SOC_mV);
+ ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB2A, 1, &value, 1);
+ if (ret) {
+ printf("%s: failed to write PMIC DVB2A register: %d\n",
+ __func__, ret);
+ return ret;
+ }
+ printf("VDDSOC set to %dmV\n", regval_to_mV(value));
+
+ value = mV_to_regval(VDD_CORE_mV);
+ ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB4A, 1, &value, 1);
+ if (ret) {
+ printf("%s: failed to write PMIC DVB4A register: %d\n",
+ __func__, ret);
+ return ret;
+ }
+ printf("VDDCORE set to %dmV\n", regval_to_mV(value));
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ gpio_request_array(tx6dl_gpios, ARRAY_SIZE(tx6dl_gpios));
+ imx_iomux_v3_setup_multiple_pads(tx6dl_pads, ARRAY_SIZE(tx6dl_pads));
+
+ return 0;
+}
+
+int board_init(void)
+{
+ int ret;
+
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
+#if 1
+ gd->bd->bi_arch_number = 4429;
+#endif
+ ret = setup_pmic_voltages();
+ if (ret) {
+ printf("Failed to setup PMIC voltages\n");
+ hang();
+ }
+ return 0;
+}
+
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ PHYS_SDRAM_1_SIZE);
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
+#if CONFIG_NR_DRAM_BANKS > 1
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
+ PHYS_SDRAM_2_SIZE);
+#endif
+}
+
+#ifdef CONFIG_CMD_MMC
+static const iomux_v3_cfg_t mmc0_pads[] = {
+ MX6DL_PAD_SD1_CMD__USDHC1_CMD,
+ MX6DL_PAD_SD1_CLK__USDHC1_CLK,
+ MX6DL_PAD_SD1_DAT0__USDHC1_DAT0,
+ MX6DL_PAD_SD1_DAT1__USDHC1_DAT1,
+ MX6DL_PAD_SD1_DAT2__USDHC1_DAT2,
+ MX6DL_PAD_SD1_DAT3__USDHC1_DAT3,
+ /* SD1 CD */
+ MX6DL_PAD_SD3_CMD__GPIO_7_2,
+};
+
+static const iomux_v3_cfg_t mmc1_pads[] = {
+ MX6DL_PAD_SD2_CMD__USDHC2_CMD,
+ MX6DL_PAD_SD2_CLK__USDHC2_CLK,
+ MX6DL_PAD_SD2_DAT0__USDHC2_DAT0,
+ MX6DL_PAD_SD2_DAT1__USDHC2_DAT1,
+ MX6DL_PAD_SD2_DAT2__USDHC2_DAT2,
+ MX6DL_PAD_SD2_DAT3__USDHC2_DAT3,
+ /* SD2 CD */
+ MX6DL_PAD_SD3_CLK__GPIO_7_3,
+};
+
+static struct tx6dl_esdhc_cfg {
+ const iomux_v3_cfg_t *pads;
+ int num_pads;
+ enum mxc_clock clkid;
+ struct fsl_esdhc_cfg cfg;
+} tx6dl_esdhc_cfg[] = {
+ {
+ .pads = mmc0_pads,
+ .num_pads = ARRAY_SIZE(mmc0_pads),
+ .clkid = MXC_ESDHC_CLK,
+ .cfg = {
+ .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
+ .cd_gpio = IMX_GPIO_NR(7, 2),
+ .wp_gpio = -EINVAL,
+ },
+ },
+ {
+ .pads = mmc1_pads,
+ .num_pads = ARRAY_SIZE(mmc1_pads),
+ .clkid = MXC_ESDHC2_CLK,
+ .cfg = {
+ .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
+ .cd_gpio = IMX_GPIO_NR(7, 3),
+ .wp_gpio = -EINVAL,
+ },
+ },
+};
+
+static inline struct tx6dl_esdhc_cfg *to_tx6dl_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
+{
+ void *p = cfg;
+
+ return p - offsetof(struct tx6dl_esdhc_cfg, cfg);
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = mmc->priv;
+
+ if (cfg->cd_gpio < 0)
+ return cfg->cd_gpio;
+
+ debug("SD card %d is %spresent\n",
+ to_tx6dl_esdhc_cfg(cfg) - tx6dl_esdhc_cfg, gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
+ return !gpio_get_value(cfg->cd_gpio);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(tx6dl_esdhc_cfg); i++) {
+ struct mmc *mmc;
+ struct fsl_esdhc_cfg *cfg = &tx6dl_esdhc_cfg[i].cfg;
+
+ if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
+ break;
+
+ cfg->sdhc_clk = mxc_get_clock(tx6dl_esdhc_cfg[i].clkid);
+ imx_iomux_v3_setup_multiple_pads(tx6dl_esdhc_cfg[i].pads,
+ tx6dl_esdhc_cfg[i].num_pads);
+
+ debug("%s: Initializing MMC slot %d\n", __func__, i);
+ fsl_esdhc_initialize(bis, cfg);
+
+ mmc = find_mmc_device(i);
+ if (mmc == NULL)
+ continue;
+ if (board_mmc_getcd(mmc) > 0)
+ mmc_init(mmc);
+ }
+ return 0;
+}
+#endif /* CONFIG_CMD_MMC */
+
+#ifdef CONFIG_FEC_MXC
+
+#define FEC_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_SRE_FAST)
+#define FEC_PAD_CTL2 (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
+#define GPIO_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
+
+#ifndef ETH_ALEN
+#define ETH_ALEN 6
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int ret;
+
+ /* delay at least 21ms for the PHY internal POR signal to deassert */
+ udelay(22000);
+
+ imx_iomux_v3_setup_multiple_pads(tx6dl_fec_pads, ARRAY_SIZE(tx6dl_fec_pads));
+
+ /* Deassert RESET to the external phy */
+ gpio_set_value(TX6DL_FEC_RST_GPIO, 1);
+
+ ret = cpu_eth_init(bis);
+ if (ret)
+ printf("cpu_eth_init() failed: %d\n", ret);
+
+ return ret;
+}
+#endif /* CONFIG_FEC_MXC */
+
+enum {
+ LED_STATE_INIT = -1,
+ LED_STATE_OFF,
+ LED_STATE_ON,
+};
+
+static inline int calc_blink_rate(int tmp)
+{
+ return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
+ (tmp - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
+ (TEMPERATURE_HOT - TEMPERATURE_MIN);
+}
+
+void show_activity(int arg)
+{
+ static int led_state = LED_STATE_INIT;
+ static int blink_rate;
+ static ulong last;
+
+ if (led_state == LED_STATE_INIT) {
+ last = get_timer(0);
+ gpio_set_value(TX6DL_LED_GPIO, 1);
+ led_state = LED_STATE_ON;
+ blink_rate = calc_blink_rate(check_cpu_temperature(0));
+ } else {
+ if (get_timer(last) > blink_rate) {
+ blink_rate = calc_blink_rate(check_cpu_temperature(0));
+ last = get_timer_masked();
+ if (led_state == LED_STATE_ON) {
+ gpio_set_value(TX6DL_LED_GPIO, 0);
+ } else {
+ gpio_set_value(TX6DL_LED_GPIO, 1);
+ }
+ led_state = 1 - led_state;
+ }
+ }
+}
+
+static const iomux_v3_cfg_t stk5_pads[] = {
+ /* SW controlled LED on STK5 baseboard */
+ MX6DL_PAD_EIM_A18__GPIO_2_20,
+
+ /* LCD data pins */
+ MX6DL_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
+ MX6DL_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
+ MX6DL_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
+ MX6DL_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
+ MX6DL_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
+ MX6DL_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
+ MX6DL_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
+ MX6DL_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
+ MX6DL_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
+ MX6DL_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
+ MX6DL_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
+ MX6DL_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
+ MX6DL_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
+ MX6DL_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
+ MX6DL_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
+ MX6DL_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
+ MX6DL_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
+ MX6DL_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
+ MX6DL_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
+ MX6DL_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
+ MX6DL_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
+ MX6DL_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
+ MX6DL_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
+ MX6DL_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
+ MX6DL_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* HSYNC */
+ MX6DL_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* VSYNC */
+ MX6DL_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
+ MX6DL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
+
+ /* I2C bus on DIMM pins 40/41 */
+ MX6DL_PAD_GPIO_6__I2C3_SDA,
+ MX6DL_PAD_GPIO_3__I2C3_SCL,
+
+ /* TSC200x PEN IRQ */
+ MX6DL_PAD_EIM_D26__GPIO_3_26,
+
+ /* EDT-FT5x06 Polytouch panel */
+ MX6DL_PAD_NANDF_CS2__GPIO_6_15, /* IRQ */
+ MX6DL_PAD_EIM_A16__GPIO_2_22, /* RESET */
+ MX6DL_PAD_EIM_A17__GPIO_2_21, /* WAKE */
+
+ /* USBH1 */
+ MX6DL_PAD_EIM_D31__GPIO_3_31, /* VBUSEN */
+ MX6DL_PAD_EIM_D30__GPIO_3_30, /* OC */
+ /* USBOTG */
+ MX6DL_PAD_EIM_D23__GPIO_3_23, /* USBOTG ID */
+ MX6DL_PAD_GPIO_7__GPIO_1_7, /* VBUSEN */
+ MX6DL_PAD_GPIO_8__GPIO_1_8, /* OC */
+};
+
+static const struct gpio stk5_gpios[] = {
+ { TX6DL_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
+
+ { IMX_GPIO_NR(3, 23), GPIOF_INPUT, "USBOTG ID", },
+ { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
+ { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
+ { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
+ { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
+};
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+ /* set to max. size supported by SoC */
+ .vl_col = 1920,
+ .vl_row = 1080,
+
+ .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
+};
+
+static struct fb_videomode tx6dl_fb_mode = {
+ /* Standard VGA timing */
+ .name = "VGA",
+ .refresh = 60,
+ .xres = 640,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(25175),
+ .left_margin = 48,
+ .hsync_len = 96,
+ .right_margin = 16,
+ .upper_margin = 31,
+ .vsync_len = 2,
+ .lower_margin = 12,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ .vmode = FB_VMODE_NONINTERLACED,
+};
+
+static int lcd_enabled = 1;
+
+void lcd_enable(void)
+{
+ /* HACK ALERT:
+ * global variable from common/lcd.c
+ * Set to 0 here to prevent messages from going to LCD
+ * rather than serial console
+ */
+ lcd_is_enabled = 0;
+
+ karo_load_splashimage(1);
+ if (lcd_enabled) {
+ debug("Switching LCD on\n");
+ gpio_set_value(TX6DL_LCD_PWR_GPIO, 1);
+ udelay(100);
+ gpio_set_value(TX6DL_LCD_RST_GPIO, 1);
+ udelay(300000);
+ gpio_set_value(TX6DL_LCD_BACKLIGHT_GPIO, 0);
+ }
+}
+
+static const iomux_v3_cfg_t stk5_lcd_pads[] = {
+ /* LCD RESET */
+ MX6DL_PAD_EIM_D29__GPIO_3_29,
+ /* LCD POWER_ENABLE */
+ MX6DL_PAD_EIM_EB3__GPIO_2_31,
+ /* LCD Backlight (PWM) */
+ MX6DL_PAD_GPIO_1__GPIO_1_1,
+
+ /* Display */
+ MX6DL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
+ MX6DL_PAD_DI0_PIN15__IPU1_DI0_PIN15,
+ MX6DL_PAD_DI0_PIN2__IPU1_DI0_PIN2,
+ MX6DL_PAD_DI0_PIN3__IPU1_DI0_PIN3,
+ MX6DL_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
+ MX6DL_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
+ MX6DL_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
+ MX6DL_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
+ MX6DL_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
+ MX6DL_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
+ MX6DL_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
+ MX6DL_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
+ MX6DL_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
+ MX6DL_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
+ MX6DL_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
+ MX6DL_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
+ MX6DL_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
+ MX6DL_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
+ MX6DL_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
+ MX6DL_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
+ MX6DL_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
+ MX6DL_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
+ MX6DL_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
+ MX6DL_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
+ MX6DL_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
+ MX6DL_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
+ MX6DL_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
+ MX6DL_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
+};
+
+static const struct gpio stk5_lcd_gpios[] = {
+ { TX6DL_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
+ { TX6DL_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
+ { TX6DL_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
+};
+
+void lcd_ctrl_init(void *lcdbase)
+{
+ int color_depth = 24;
+ char *vm;
+ unsigned long val;
+ int refresh = 60;
+ struct fb_videomode *p = &tx6dl_fb_mode;
+ int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
+ int pix_fmt = 0;
+ ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3;
+ unsigned long di_clk_rate = 65000000;
+
+ if (!lcd_enabled) {
+ debug("LCD disabled\n");
+ return;
+ }
+
+ if (tstc() || (wrsr & WRSR_TOUT)) {
+ debug("Disabling LCD\n");
+ lcd_enabled = 0;
+ return;
+ }
+
+ vm = getenv("video_mode");
+ if (vm == NULL) {
+ debug("Disabling LCD\n");
+ lcd_enabled = 0;
+ return;
+ }
+ while (*vm != '\0') {
+ if (*vm >= '0' && *vm <= '9') {
+ char *end;
+
+ val = simple_strtoul(vm, &end, 0);
+ if (end > vm) {
+ if (!xres_set) {
+ if (val > panel_info.vl_col)
+ val = panel_info.vl_col;
+ p->xres = val;
+ panel_info.vl_col = val;
+ xres_set = 1;
+ } else if (!yres_set) {
+ if (val > panel_info.vl_row)
+ val = panel_info.vl_row;
+ p->yres = val;
+ panel_info.vl_row = val;
+ yres_set = 1;
+ } else if (!bpp_set) {
+ switch (val) {
+ case 24:
+ if (pix_fmt == IPU_PIX_FMT_LVDS666)
+ pix_fmt = IPU_PIX_FMT_LVDS888;
+ /* fallthru */
+ case 16:
+ case 8:
+ color_depth = val;
+ break;
+
+ case 18:
+ if (pix_fmt == IPU_PIX_FMT_LVDS666) {
+ color_depth = val;
+ break;
+ }
+ /* fallthru */
+ default:
+ printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
+ end - vm, vm, color_depth);
+ }
+ bpp_set = 1;
+ } else if (!refresh_set) {
+ refresh = val;
+ refresh_set = 1;
+ }
+ }
+ vm = end;
+ }
+ switch (*vm) {
+ case '@':
+ bpp_set = 1;
+ /* fallthru */
+ case '-':
+ yres_set = 1;
+ /* fallthru */
+ case 'x':
+ xres_set = 1;
+ /* fallthru */
+ case 'M':
+ case 'R':
+ vm++;
+ break;
+
+ default:
+ if (!pix_fmt) {
+ char *tmp;
+
+ if (strncmp(vm, "LVDS", 4) == 0) {
+ pix_fmt = IPU_PIX_FMT_LVDS666;
+ di_clk_parent = DI_PCLK_LDB;
+ } else {
+ pix_fmt = IPU_PIX_FMT_RGB24;
+ }
+ tmp = strchr(vm, ':');
+ if (tmp)
+ vm = tmp;
+ }
+ if (*vm != '\0')
+ vm++;
+ }
+ }
+ switch (color_depth) {
+ case 8:
+ panel_info.vl_bpix = 3;
+ break;
+
+ case 16:
+ panel_info.vl_bpix = 4;
+ break;
+
+ case 18:
+ case 24:
+ panel_info.vl_bpix = 5;
+ }
+
+ p->pixclock = KHZ2PICOS(refresh *
+ (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
+ (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
+ / 1000);
+ debug("Pixel clock set to %lu.%03lu MHz\n",
+ PICOS2KHZ(p->pixclock) / 1000,
+ PICOS2KHZ(p->pixclock) % 1000);
+
+ gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
+ imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
+ ARRAY_SIZE(stk5_lcd_pads));
+
+ debug("Initializing FB driver\n");
+ if (!pix_fmt)
+ pix_fmt = IPU_PIX_FMT_RGB24;
+ else if (pix_fmt == IPU_PIX_FMT_LVDS666) {
+ writel(0x01, IOMUXC_BASE_ADDR + 8);
+ } else if (pix_fmt == IPU_PIX_FMT_LVDS888) {
+ writel(0x21, IOMUXC_BASE_ADDR + 8);
+ }
+ if (pix_fmt != IPU_PIX_FMT_RGB24) {
+ struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ /* enable LDB & DI0 clock */
+ writel(readl(&ccm_regs->CCGR3) | (3 << 12) | (3 << 2),
+ &ccm_regs->CCGR3);
+ }
+
+ if (karo_load_splashimage(0) == 0) {
+ debug("Initializing LCD controller\n");
+ ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
+ } else {
+ debug("Skipping initialization of LCD controller\n");
+ }
+}
+#else
+#define lcd_enabled 0
+#endif /* CONFIG_LCD */
+
+static void stk5_board_init(void)
+{
+ gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
+ imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
+}
+
+static void stk5v3_board_init(void)
+{
+ stk5_board_init();
+}
+
+static void stk5v5_board_init(void)
+{
+ stk5_board_init();
+
+ gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
+ "Flexcan Transceiver");
+ imx_iomux_v3_setup_pad(MX6DL_PAD_DISP0_DAT0__GPIO_4_21);
+}
+
+static void tx6dl_set_cpu_clock(void)
+{
+ unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
+
+ if (tstc() || (wrsr & WRSR_TOUT))
+ return;
+
+ if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
+ return;
+
+ if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
+ cpu_clk = mxc_get_clock(MXC_ARM_CLK);
+ printf("CPU clock set to %lu.%03lu MHz\n",
+ cpu_clk / 1000000, cpu_clk / 1000 % 1000);
+ } else {
+ printf("Failed to set CPU clock to %lu MHz\n", cpu_clk);
+ }
+}
+
+static void tx6_init_mac(void)
+{
+ u8 mac[ETH_ALEN];
+ char mac_str[ETH_ALEN * 3] = "";
+
+ imx_get_mac_from_fuse(-1, mac);
+ if (!is_valid_ether_addr(mac)) {
+ printf("No valid MAC address programmed\n");
+ return;
+ }
+
+ snprintf(mac_str, sizeof(mac_str), "%02x:%02x:%02x:%02x:%02x:%02x",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ setenv("ethaddr", mac_str);
+ printf("MAC addr from fuse: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+}
+
+int board_late_init(void)
+{
+ int ret = 0;
+ const char *baseboard;
+
+ tx6dl_set_cpu_clock();
+ karo_fdt_move_fdt();
+
+ baseboard = getenv("baseboard");
+ if (!baseboard)
+ goto exit;
+
+ printf("Baseboard: %s\n", baseboard);
+
+ if (strncmp(baseboard, "stk5", 4) == 0) {
+ if ((strlen(baseboard) == 4) ||
+ strcmp(baseboard, "stk5-v3") == 0) {
+ stk5v3_board_init();
+ } else if (strcmp(baseboard, "stk5-v5") == 0) {
+ stk5v5_board_init();
+ } else {
+ printf("WARNING: Unsupported STK5 board rev.: %s\n",
+ baseboard + 4);
+ }
+ } else {
+ printf("WARNING: Unsupported baseboard: '%s'\n",
+ baseboard);
+ ret = -EINVAL;
+ }
+
+exit:
+ tx6_init_mac();
+
+ gpio_set_value(TX6DL_RESET_OUT_GPIO, 1);
+ return ret;
+}
+
+#define iomux_field(v,f) (((iomux_v3_cfg_t)(v) << f##_SHIFT) & f##_MASK)
+
+#define chk_iomux_field(f1,f2) ({ \
+ iomux_v3_cfg_t __c = iomux_field(~0, f1); \
+ if (__c & f2##_MASK) { \
+ printf("%18s[%016llx] overlaps with:\n%18s[%016llx]\n", \
+ #f1, f1##_MASK, \
+ #f2, f2##_MASK); \
+ } \
+ (__c & f2##_MASK) != 0; \
+})
+
+#define chk_iomux_bit(f1,f2) ({ \
+ iomux_v3_cfg_t __c = iomux_field(~0, f1); \
+ if (__c & f2) { \
+ printf("%18s[%016llx] overlaps with:\n%18s[%016llx]\n", \
+ #f1, f1##_MASK, \
+ #f2, (iomux_v3_cfg_t)f2); \
+ } \
+ (__c & f2) != 0; \
+})
+
+int checkboard(void)
+{
+ print_cpuinfo();
+
+ printf("Board: Ka-Ro TX6DL\n");
+
+ printf("mtdparts='%s'\n", MTDPARTS_DEFAULT);
+
+#ifdef TIMER_TEST
+ {
+ struct mxc_gpt {
+ unsigned int control;
+ unsigned int prescaler;
+ unsigned int status;
+ unsigned int nouse[6];
+ unsigned int counter;
+ };
+ const int us_delay = 10;
+ unsigned long start = get_timer(0);
+ unsigned long last = gd->arch.tbl;
+ unsigned long loop = 0;
+ unsigned long cnt = 0;
+ static struct mxc_gpt *timer_base = (struct mxc_gpt *)GPT1_BASE_ADDR;
+
+ printf("GPT prescaler=%u\n", readl(&timer_base->prescaler) + 1);
+ printf("clock tick rate: %lu.%03lukHz\n",
+ gd->arch.timer_rate_hz / 1000, gd->arch.timer_rate_hz % 1000);
+ printf("ticks/us=%lu\n", gd->arch.timer_rate_hz / CONFIG_SYS_HZ / 1000);
+
+ while (!tstc()) {
+ unsigned long elapsed = get_timer(start);
+ unsigned long diff = gd->arch.tbl - last;
+
+ loop++;
+ last = gd->arch.tbl;
+
+ printf("loop %4lu: t=%08lx diff=%08lx steps=%6lu elapsed time: %4lu",
+ loop, gd->arch.tbl, diff, cnt, elapsed / CONFIG_SYS_HZ);
+ cnt = 0;
+ while (get_timer(elapsed + start) < CONFIG_SYS_HZ) {
+ cnt++;
+ udelay(us_delay);
+ }
+ printf(" counter=%08x udelay(%u)=%lu.%03luus\n",
+ readl(&timer_base->counter), us_delay,
+ 1000000000 / cnt / 1000, 1000000000 / cnt % 1000);
+ }
+ }
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+ struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+ struct fuse_bank0_regs *fuse = (void *)iim->bank[0].fuse_regs;
+
+ serialnr->low = readl(&fuse->cfg0);
+ serialnr->high = readl(&fuse->cfg1);
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+#include <jffs2/jffs2.h>
+#include <mtd_node.h>
+struct node_info nodes[] = {
+ { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
+};
+
+#else
+#define fdt_fixup_mtdparts(b,n,c) do { } while (0)
+#endif
+
+static void tx6dl_fixup_flexcan(void *blob)
+{
+ const char *baseboard = getenv("baseboard");
+
+ if (baseboard && strcmp(baseboard, "stk5-v5") == 0)
+ return;
+ /* TODO: handle flexcan transceiver GPIO */
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+ fdt_fixup_ethernet(blob);
+
+ karo_fdt_fixup_touchpanel(blob);
+ karo_fdt_fixup_usb_otg(blob, "", 0);
+ tx6dl_fixup_flexcan(blob);
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2012 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ board/karo/tx6dl/lowlevel_init.o (.text*)
+ __image_copy_start = .;
+ CPUDIR/start.o (.text*)
+ *(.text*)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : {
+ *(.data*)
+ }
+
+ . = ALIGN(4);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
+
+ . = ALIGN(4);
+
+ __image_copy_end = .;
+
+ .rel.dyn : {
+ __rel_dyn_start = .;
+ *(.rel*)
+ __rel_dyn_end = .;
+ }
+
+ .dynsym : {
+ __dynsym_start = .;
+ *(.dynsym)
+ }
+
+ _end = .;
+ __u_boot_img_size = _end - _start;
+
+ .bss __rel_dyn_start (OVERLAY) : {
+ __bss_start = .;
+ *(.bss)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ }
+
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
+}
tx53-xx21 arm armv7 tx53 karo mx5 tx53:NR_DRAM_BANKS=2,SYS_TX53_HWREV_2
tx53-xx30 arm armv7 tx53 karo mx5 tx53:NR_DRAM_BANKS=1
tx53-xx31 arm armv7 tx53 karo mx5 tx53:NR_DRAM_BANKS=2
+tx6dl arm armv7 tx6dl karo mx6
+tx6dl_mfg arm armv7 tx6dl karo mx6 tx6dl:MFG
+tx6dl_noenv arm armv7 tx6dl karo mx6 tx6dl:ENV_IS_NOWHERE
tx6q arm armv7 tx6q karo mx6
tx6q_mfg arm armv7 tx6q karo mx6 tx6q:MFG
tx6q_noenv arm armv7 tx6q karo mx6 tx6q:ENV_IS_NOWHERE
--- /dev/null
+/*
+ * Copyright (C) 2012 <LW@KARO-electronics.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __TX6DL_H
+#define __TX6DL_H
+
+#include <asm/sizes.h>
+
+/*
+ * Ka-Ro TX6DL board - SoC configuration
+ */
+#define CONFIG_MX6
+#define CONFIG_MX6DL
+#define CONFIG_SYS_MX6_HCLK 24000000
+#define CONFIG_SYS_MX6_CLK32 32768
+#define CONFIG_SYS_HZ 1000 /* Ticks per second */
+#define CONFIG_SHOW_ACTIVITY
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#ifndef CONFIG_MFG
+/* LCD Logo and Splash screen support */
+#define CONFIG_LCD
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#ifdef CONFIG_LCD
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_IPU_CLKRATE 266000000
+#define CONFIG_LCD_LOGO
+#define LCD_BPP LCD_COLOR24
+#define CONFIG_CMD_BMP
+#define CONFIG_VIDEO_BMP_RLE8
+#endif /* CONFIG_LCD */
+#endif /* CONFIG_MFG */
+
+/*
+ * Memory configuration options
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* # of SDRAM banks */
+#define PHYS_SDRAM_1 0x10000000 /* Base address of bank 1 */
+#define PHYS_SDRAM_1_SIZE SZ_512M
+#define PHYS_SDRAM_1_WIDTH 32
+#define CONFIG_STACKSIZE SZ_128K
+#define CONFIG_SYS_MALLOC_LEN SZ_8M
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* Memtest start address */
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_4M)
+#define CONFIG_SYS_SDRAM_CLK 400
+
+/*
+ * U-Boot general configurations
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "TX6DL U-Boot > "
+#define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16) /* Print buffer size */
+#define CONFIG_SYS_MAXARGS 64 /* Max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+ /* Boot argument buffer size */
+#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
+#define CONFIG_AUTO_COMPLETE /* Command auto complete */
+#define CONFIG_CMDLINE_EDITING /* Command history etc */
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * Flattened Device Tree (FDT) support
+*/
+#ifndef CONFIG_MFG
+#define CONFIG_OF_LIBFDT
+#ifdef CONFIG_OF_LIBFDT
+#define CONFIG_FDT_FIXUP_PARTITIONS
+#define CONFIG_OF_EMBED
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_DEFAULT_DEVICE_TREE tx6dl
+#define CONFIG_ARCH_DEVICE_TREE mx6dl
+#define CONFIG_SYS_FDT_ADDR (PHYS_SDRAM_1 + SZ_16M)
+#endif /* CONFIG_OF_LIBFDT */
+#endif /* CONFIG_MFG */
+
+/*
+ * Boot Linux
+ */
+#define xstr(s) str(s)
+#define str(s) #s
+#define __pfx(x, s) (x##s)
+#define _pfx(x, s) __pfx(x, s)
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_SERIAL_TAG
+#ifndef CONFIG_MFG
+#define CONFIG_BOOTDELAY 1
+#else
+#define CONFIG_BOOTDELAY 0
+#endif
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_SYS_AUTOLOAD "no"
+#ifndef CONFIG_MFG
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_BOOTARGS "console=ttymxc0,115200 ro debug panic=1"
+#define CONFIG_BOOTCOMMAND "run bootcmd_nand"
+#else
+#define CONFIG_BOOTCOMMAND "env import " xstr(CONFIG_BOOTCMD_MFG_LOADADDR) ";run bootcmd_mfg"
+#define CONFIG_BOOTCMD_MFG_LOADADDR 10500000
+#define CONFIG_DELAY_ENVIRONMENT
+#endif /* CONFIG_MFG */
+#define CONFIG_LOADADDR 18000000
+#define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR)
+#define CONFIG_U_BOOT_IMG_SIZE SZ_1M
+#define CONFIG_IMX_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT_MSECS 3000
+
+/*
+ * Extra Environments
+ */
+#ifndef CONFIG_MFG
+#ifdef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "autostart=no\0" \
+ "autoload=no\0" \
+ "bootdelay=-1\0" \
+ "fdtaddr=11000000\0" \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0"
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "autostart=no\0" \
+ "baseboard=stk5-v3\0" \
+ "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}" \
+ " root=/dev/mmcblk0p3 rootwait\0" \
+ "bootargs_nand=run default_bootargs;set bootargs ${bootargs}" \
+ " root=/dev/mtdblock3 rootfstype=jffs2\0" \
+ "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \
+ " root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},nolock\0"\
+ "bootcmd_mmc=set autostart no;run bootargs_mmc;" \
+ "fatload mmc 0 ${loadaddr} uImage;run bootm_cmd\0" \
+ "bootcmd_nand=set autostart no;run bootargs_nand;" \
+ "nboot linux;run bootm_cmd\0" \
+ "bootcmd_net=set autostart no;run bootargs_nfs;dhcp;" \
+ "run bootm_cmd\0" \
+ "bootm_cmd=fdt boardsetup;bootm ${loadaddr} - ${fdtaddr}\0" \
+ "cpu_clk=800\0" \
+ "default_bootargs=set bootargs " CONFIG_BOOTARGS \
+ " video=${video_mode} ${append_bootargs}\0" \
+ "fdtaddr=11000000\0" \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "nfsroot=/tftpboot/rootfs\0" \
+ "otg_mode=device\0" \
+ "touchpanel=tsc2007\0" \
+ "video_mode=VGA-1:640x480MR-24@60\0"
+#endif /* CONFIG_ENV_IS_NOWHERE */
+#endif /* CONFIG_MFG */
+
+#define MTD_NAME "gpmi-nand"
+#define MTDIDS_DEFAULT "nand0=" MTD_NAME
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/*
+ * U-Boot Commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_BOOTCE
+#define CONFIG_CMD_TIME
+#define CONFIG_CMD_I2C
+
+/*
+ * Serial Driver
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, }
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+/*
+ * GPIO driver
+ */
+#define CONFIG_MXC_GPIO
+
+/*
+ * Ethernet Driver
+ */
+#define CONFIG_FEC_MXC
+#ifdef CONFIG_FEC_MXC
+/* This is required for the FEC driver to work with cache enabled */
+#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
+
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR 0
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC
+#define CONFIG_MII
+#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+/* Add for working with "strict" DHCP server */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+#endif
+
+/*
+ * I2C Configs
+ */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_HARD_I2C 1
+#define CONFIG_I2C_MXC 1
+#define CONFIG_SYS_I2C_BASE I2C1_BASE_ADDR
+#define CONFIG_SYS_I2C_MX6_PORT1
+#define CONFIG_SYS_I2C_SPEED 10000
+#define CONFIG_SYS_I2C_SLAVE 0x3c
+#define CONFIG_MX6_INTER_LDO_BYPASS 0
+#endif
+
+#ifndef CONFIG_ENV_IS_NOWHERE
+/* define one of the following options:
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_IS_IN_MMC
+*/
+#define CONFIG_ENV_IS_IN_NAND
+#endif
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * NAND flash driver
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_MTD_DEVICE
+#if 0
+#define CONFIG_MTD_DEBUG
+#define CONFIG_MTD_DEBUG_VERBOSE 4
+#endif
+#define CONFIG_NAND_MXS
+#define CONFIG_NAND_PAGE_SIZE 2048
+#define CONFIG_NAND_OOB_SIZE 64
+#define CONFIG_NAND_PAGES_PER_BLOCK 64
+#define CONFIG_APBH_DMA
+#define CONFIG_APBH_DMA_BURST
+#define CONFIG_APBH_DMA_BURST8
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
+#define CONFIG_CMD_NAND_TRIMFFS
+#define CONFIG_SYS_MXS_DMA_CHANNEL 4
+#define CONFIG_SYS_MAX_FLASH_SECT 1024
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_NAND_MAX_CHIPS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_BASE 0x00000000
+#define CONFIG_CMD_ROMUPDATE
+#else
+#undef CONFIG_ENV_IS_IN_NAND
+#endif /* CONFIG_CMD_NAND */
+
+#define CONFIG_ENV_OFFSET (CONFIG_U_BOOT_IMG_SIZE + CONFIG_SYS_NAND_U_BOOT_OFFS)
+#define CONFIG_ENV_SIZE SZ_128K
+#define CONFIG_ENV_RANGE 0x60000
+#ifdef CONFIG_ENV_OFFSET_REDUND
+#define CONFIG_SYS_ENV_PART_STR xstr(CONFIG_ENV_RANGE) \
+ "(env)," \
+ xstr(CONFIG_ENV_RANGE) \
+ "(env2),"
+#define CONFIG_SYS_USERFS_PART_STR "91520k(userfs)"
+#else
+#define CONFIG_SYS_ENV_PART_STR xstr(CONFIG_ENV_RANGE) \
+ "(env),"
+#define CONFIG_SYS_USERFS_PART_STR "91904k(userfs)"
+#endif /* CONFIG_ENV_OFFSET_REDUND */
+
+/*
+ * MMC Driver
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_FSL_ESDHC_NUM 2
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+
+/*
+ * Environments on MMC
+ */
+#ifdef CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#undef CONFIG_ENV_OFFSET
+#undef CONFIG_ENV_SIZE
+/* Associated with the MMC layout defined in mmcops.c */
+#define CONFIG_ENV_OFFSET SZ_1K
+#define CONFIG_ENV_SIZE (SZ_128K - CONFIG_ENV_OFFSET)
+#define CONFIG_DYNAMIC_MMC_DEVNO
+#endif /* CONFIG_ENV_IS_IN_MMC */
+#else
+#undef CONFIG_ENV_IS_IN_MMC
+#endif /* CONFIG_CMD_MMC */
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+#undef CONFIG_ENV_SIZE
+#define CONFIG_ENV_SIZE SZ_4K
+#endif
+
+#define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
+ "1m@" xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) "(u-boot)," \
+ CONFIG_SYS_ENV_PART_STR \
+ "4m(linux),32m(rootfs),256k(dtb)," \
+ CONFIG_SYS_USERFS_PART_STR ",512k@0x7f80000(bbt)ro"
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
+ GENERATED_GBL_DATA_SIZE)
+
+#ifdef CONFIG_CMD_IIM
+#define CONFIG_IMX_IIM
+#endif
+
+#endif /* __CONFIG_H */
projects / karo-tx-uboot.git / commitdiff