#
# Normal rules
#
-
-*.rej
-*.orig
-*.a
+.*
*.o
+*.o.*
+*.a
+*.s
*.su
-*~
+*.mod.c
+*.i
+*.lst
+*.order
+*.elf
*.swp
-*.patch
*.bin
+*.patch
*.cfgtmp
*.dts.tmp
#
# Top-level generic files
#
-
/MLO*
/SPL
/System.map
-/u-boot
-/u-boot.elf
-/u-boot.hex
-/u-boot.imx
-/u-boot-with-spl.imx
-/u-boot-with-nand-spl.imx
-/u-boot.map
-/u-boot.srec
-/u-boot.ldr
-/u-boot.ldr.hex
-/u-boot.ldr.srec
-/u-boot.img
-/u-boot.kwb
-/u-boot.sha1
-/u-boot.dis
-/u-boot.lds
-/u-boot.ubl
-/u-boot.ais
-/u-boot.dtb
-/u-boot.sb
+/u-boot*
+
+#
+# git files that we don't want to ignore even it they are dot-files
+#
+!.gitignore
+!.mailmap
#
# Generated files
#
-*.depend*
/LOG
/errlog
/reloc_off
/include/generated/
/include/spl-autoconf.mk
/include/tpl-autoconf.mk
-asm-offsets.s
# stgit generated dirs
patches-*
GRTAGS
GSYMS
GTAGS
+
+*.orig
+*~
+\#*#
--- /dev/null
+#
+# Kbuild for top-level directory of U-Boot
+# This file takes care of the following:
+# 1) Generate generic-asm-offsets.h
+# 2) Generate asm-offsets.h
+
+#####
+# 1) Generate generic-asm-offsets.h
+
+generic-offsets-file := include/generated/generic-asm-offsets.h
+
+always := $(generic-offsets-file)
+targets := $(generic-offsets-file) lib/asm-offsets.s
+
+quiet_cmd_generic-offsets = GEN $@
+define cmd_generic-offsets
+ (set -e; \
+ echo "#ifndef __GENERIC_ASM_OFFSETS_H__"; \
+ echo "#define __GENERIC_ASM_OFFSETS_H__"; \
+ echo "/*"; \
+ echo " * DO NOT MODIFY."; \
+ echo " *"; \
+ echo " * This file was generated by Kbuild"; \
+ echo " *"; \
+ echo " */"; \
+ echo ""; \
+ sed -ne $(sed-y) $<; \
+ echo ""; \
+ echo "#endif" ) > $@
+endef
+
+# We use internal kbuild rules to avoid the "is up to date" message from make
+lib/asm-offsets.s: lib/asm-offsets.c FORCE
+ $(Q)mkdir -p $(dir $@)
+ $(call if_changed_dep,cc_s_c)
+
+$(obj)/$(generic-offsets-file): lib/asm-offsets.s Kbuild
+ $(Q)mkdir -p $(dir $@)
+ $(call cmd,generic-offsets)
+
+#####
+# 2) Generate asm-offsets.h
+#
+
+ifneq ($(wildcard $(srctree)/$(CPUDIR)/$(SOC)/asm-offsets.c),)
+offsets-file := include/generated/asm-offsets.h
+endif
+
+always += $(offsets-file)
+targets += $(offsets-file)
+targets += $(CPUDIR)/$(SOC)/asm-offsets.s
+
+
+# Default sed regexp - multiline due to syntax constraints
+define sed-y
+ "/^->/{s:->#\(.*\):/* \1 */:; \
+ s:^->\([^ ]*\) [\$$#]*\([-0-9]*\) \(.*\):#define \1 \2 /* \3 */:; \
+ s:^->\([^ ]*\) [\$$#]*\([^ ]*\) \(.*\):#define \1 \2 /* \3 */:; \
+ s:->::; p;}"
+endef
+
+CFLAGS_asm-offsets.o := -DDO_DEPS_ONLY
+
+quiet_cmd_offsets = GEN $@
+define cmd_offsets
+ (set -e; \
+ echo "#ifndef __ASM_OFFSETS_H__"; \
+ echo "#define __ASM_OFFSETS_H__"; \
+ echo "/*"; \
+ echo " * DO NOT MODIFY."; \
+ echo " *"; \
+ echo " * This file was generated by Kbuild"; \
+ echo " *"; \
+ echo " */"; \
+ echo ""; \
+ sed -ne $(sed-y) $<; \
+ echo ""; \
+ echo "#endif" ) > $@
+endef
+
+# We use internal kbuild rules to avoid the "is up to date" message from make
+$(CPUDIR)/$(SOC)/asm-offsets.s: $(CPUDIR)/$(SOC)/asm-offsets.c FORCE
+ $(Q)mkdir -p $(dir $@)
+ $(call if_changed_dep,cc_s_c)
+
+$(obj)/$(offsets-file): $(CPUDIR)/$(SOC)/asm-offsets.s
+ $(call cmd,offsets)
LIST_pxa="$(targets_by_cpu pxa)"
-LIST_ixp="$(targets_by_cpu ixp)"
-
#########################################################################
## SPEAr Systems
#########################################################################
LIST_nds32="$(targets_by_arch nds32)"
+#########################################################################
+## ARC Systems
+#########################################################################
+
+LIST_arc="$(targets_by_arch arc)"
+
#-----------------------------------------------------------------------
get_target_location() {
output_dir="${OUTPUT_PREFIX}"
fi
- export BUILD_DIR="${output_dir}"
-
target_arch=$(get_target_arch ${target})
eval cross_toolchain=\$CROSS_COMPILE_`echo $target_arch | tr '[:lower:]' '[:upper:]'`
if [ "${cross_toolchain}" ] ; then
MAKE=make
fi
+ if [ "${output_dir}" != "." ] ; then
+ MAKE="${MAKE} O=${output_dir}"
+ fi
+
${MAKE} distclean >/dev/null
${MAKE} -s ${target}_config
if [ $BUILD_MANY == 1 ] ; then
trap - TERM
- ${MAKE} -s tidy
+ ${MAKE} -s clean
if [ -s ${LOG_DIR}/${target}.ERR ] ; then
cp ${LOG_DIR}/${target}.ERR ${OUTPUT_PREFIX}/ERR/${target}
#
VERSION = 2014
-PATCHLEVEL = 01
+PATCHLEVEL = 04
SUBLEVEL =
-EXTRAVERSION =
-ifneq "$(SUBLEVEL)" ""
-U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
+EXTRAVERSION = -rc1
+NAME =
+
+# *DOCUMENTATION*
+# To see a list of typical targets execute "make help"
+# More info can be located in ./README
+# Comments in this file are targeted only to the developer, do not
+# expect to learn how to build the kernel reading this file.
+
+# Do not:
+# o use make's built-in rules and variables
+# (this increases performance and avoids hard-to-debug behaviour);
+# o print "Entering directory ...";
+MAKEFLAGS += -rR --no-print-directory
+
+# Avoid funny character set dependencies
+unexport LC_ALL
+LC_COLLATE=C
+LC_NUMERIC=C
+export LC_COLLATE LC_NUMERIC
+
+# We are using a recursive build, so we need to do a little thinking
+# to get the ordering right.
+#
+# Most importantly: sub-Makefiles should only ever modify files in
+# their own directory. If in some directory we have a dependency on
+# a file in another dir (which doesn't happen often, but it's often
+# unavoidable when linking the built-in.o targets which finally
+# turn into vmlinux), we will call a sub make in that other dir, and
+# after that we are sure that everything which is in that other dir
+# is now up to date.
+#
+# The only cases where we need to modify files which have global
+# effects are thus separated out and done before the recursive
+# descending is started. They are now explicitly listed as the
+# prepare rule.
+
+# To put more focus on warnings, be less verbose as default
+# Use 'make V=1' to see the full commands
+
+ifeq ("$(origin V)", "command line")
+ KBUILD_VERBOSE = $(V)
+endif
+ifndef KBUILD_VERBOSE
+ KBUILD_VERBOSE = 0
+endif
+
+# Call a source code checker (by default, "sparse") as part of the
+# C compilation.
+#
+# Use 'make C=1' to enable checking of only re-compiled files.
+# Use 'make C=2' to enable checking of *all* source files, regardless
+# of whether they are re-compiled or not.
+#
+# See the file "Documentation/sparse.txt" for more details, including
+# where to get the "sparse" utility.
+
+ifeq ("$(origin C)", "command line")
+ KBUILD_CHECKSRC = $(C)
+endif
+ifndef KBUILD_CHECKSRC
+ KBUILD_CHECKSRC = 0
+endif
+
+# Use make M=dir to specify directory of external module to build
+# Old syntax make ... SUBDIRS=$PWD is still supported
+# Setting the environment variable KBUILD_EXTMOD take precedence
+ifdef SUBDIRS
+ KBUILD_EXTMOD ?= $(SUBDIRS)
+endif
+
+ifeq ("$(origin M)", "command line")
+ KBUILD_EXTMOD := $(M)
+endif
+
+# kbuild supports saving output files in a separate directory.
+# To locate output files in a separate directory two syntaxes are supported.
+# In both cases the working directory must be the root of the kernel src.
+# 1) O=
+# Use "make O=dir/to/store/output/files/"
+#
+# 2) Set KBUILD_OUTPUT
+# Set the environment variable KBUILD_OUTPUT to point to the directory
+# where the output files shall be placed.
+# export KBUILD_OUTPUT=dir/to/store/output/files/
+# make
+#
+# The O= assignment takes precedence over the KBUILD_OUTPUT environment
+# variable.
+
+
+# KBUILD_SRC is set on invocation of make in OBJ directory
+# KBUILD_SRC is not intended to be used by the regular user (for now)
+ifeq ($(KBUILD_SRC),)
+
+# OK, Make called in directory where kernel src resides
+# Do we want to locate output files in a separate directory?
+ifeq ("$(origin O)", "command line")
+ KBUILD_OUTPUT := $(O)
+endif
+
+ifeq ("$(origin W)", "command line")
+ export KBUILD_ENABLE_EXTRA_GCC_CHECKS := $(W)
+endif
+
+# That's our default target when none is given on the command line
+PHONY := _all
+_all:
+
+# Cancel implicit rules on top Makefile
+$(CURDIR)/Makefile Makefile: ;
+
+ifneq ($(KBUILD_OUTPUT),)
+# Invoke a second make in the output directory, passing relevant variables
+# check that the output directory actually exists
+saved-output := $(KBUILD_OUTPUT)
+KBUILD_OUTPUT := $(shell cd $(KBUILD_OUTPUT) && /bin/pwd)
+$(if $(KBUILD_OUTPUT),, \
+ $(error output directory "$(saved-output)" does not exist))
+
+PHONY += $(MAKECMDGOALS) sub-make
+
+$(filter-out _all sub-make $(CURDIR)/Makefile, $(MAKECMDGOALS)) _all: sub-make
+ @:
+
+sub-make: FORCE
+ $(if $(KBUILD_VERBOSE:1=),@)$(MAKE) -C $(KBUILD_OUTPUT) \
+ KBUILD_SRC=$(CURDIR) \
+ KBUILD_EXTMOD="$(KBUILD_EXTMOD)" -f $(CURDIR)/Makefile \
+ $(filter-out _all sub-make,$(MAKECMDGOALS))
+
+# Leave processing to above invocation of make
+skip-makefile := 1
+endif # ifneq ($(KBUILD_OUTPUT),)
+endif # ifeq ($(KBUILD_SRC),)
+
+# We process the rest of the Makefile if this is the final invocation of make
+ifeq ($(skip-makefile),)
+
+# If building an external module we do not care about the all: rule
+# but instead _all depend on modules
+PHONY += all
+ifeq ($(KBUILD_EXTMOD),)
+_all: all
else
-U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL)$(EXTRAVERSION)
+_all: modules
endif
-TIMESTAMP_FILE = $(obj)include/generated/timestamp_autogenerated.h
-VERSION_FILE = $(obj)include/generated/version_autogenerated.h
+
+srctree := $(if $(KBUILD_SRC),$(KBUILD_SRC),$(CURDIR))
+objtree := $(CURDIR)
+src := $(srctree)
+obj := $(objtree)
+
+VPATH := $(srctree)$(if $(KBUILD_EXTMOD),:$(KBUILD_EXTMOD))
+
+export srctree objtree VPATH
+
+OBJTREE := $(objtree)
+SPLTREE := $(OBJTREE)/spl
+TPLTREE := $(OBJTREE)/tpl
+SRCTREE := $(srctree)
+TOPDIR := $(SRCTREE)
+export TOPDIR SRCTREE OBJTREE SPLTREE TPLTREE
+
+MKCONFIG := $(SRCTREE)/mkconfig
+export MKCONFIG
+
+# Make sure CDPATH settings don't interfere
+unexport CDPATH
+
+#########################################################################
HOSTARCH := $(shell uname -m | \
sed -e s/i.86/x86/ \
VENDOR=
#########################################################################
-# Allow for silent builds
-ifeq (,$(findstring s,$(MAKEFLAGS)))
-XECHO = echo
-else
-XECHO = :
+
+# set default to nothing for native builds
+ifeq ($(HOSTARCH),$(ARCH))
+CROSS_COMPILE ?=
endif
-#########################################################################
+# SHELL used by kbuild
+CONFIG_SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \
+ else if [ -x /bin/bash ]; then echo /bin/bash; \
+ else echo sh; fi ; fi)
+
+HOSTCC = gcc
+HOSTCFLAGS = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer
+
+ifeq ($(HOSTOS),cygwin)
+HOSTCFLAGS += -ansi
+endif
+
+# Mac OS X / Darwin's C preprocessor is Apple specific. It
+# generates numerous errors and warnings. We want to bypass it
+# and use GNU C's cpp. To do this we pass the -traditional-cpp
+# option to the compiler. Note that the -traditional-cpp flag
+# DOES NOT have the same semantics as GNU C's flag, all it does
+# is invoke the GNU preprocessor in stock ANSI/ISO C fashion.
#
-# U-boot build supports generating object files in a separate external
-# directory. Two use cases are supported:
+# Apple's linker is similar, thanks to the new 2 stage linking
+# multiple symbol definitions are treated as errors, hence the
+# -multiply_defined suppress option to turn off this error.
#
-# 1) Add O= to the make command line
-# 'make O=/tmp/build all'
+ifeq ($(HOSTOS),darwin)
+# get major and minor product version (e.g. '10' and '6' for Snow Leopard)
+DARWIN_MAJOR_VERSION = $(shell sw_vers -productVersion | cut -f 1 -d '.')
+DARWIN_MINOR_VERSION = $(shell sw_vers -productVersion | cut -f 2 -d '.')
+
+os_x_before = $(shell if [ $(DARWIN_MAJOR_VERSION) -le $(1) -a \
+ $(DARWIN_MINOR_VERSION) -le $(2) ] ; then echo "$(3)"; else echo "$(4)"; fi ;)
+
+# Snow Leopards build environment has no longer restrictions as described above
+HOSTCC = $(call os_x_before, 10, 5, "cc", "gcc")
+HOSTCFLAGS += $(call os_x_before, 10, 4, "-traditional-cpp")
+HOSTLDFLAGS += $(call os_x_before, 10, 5, "-multiply_defined suppress")
+endif
+
+# Decide whether to build built-in, modular, or both.
+# Normally, just do built-in.
+
+KBUILD_MODULES :=
+KBUILD_BUILTIN := 1
+
+# If we have only "make modules", don't compile built-in objects.
+# When we're building modules with modversions, we need to consider
+# the built-in objects during the descend as well, in order to
+# make sure the checksums are up to date before we record them.
+
+ifeq ($(MAKECMDGOALS),modules)
+ KBUILD_BUILTIN := $(if $(CONFIG_MODVERSIONS),1)
+endif
+
+# If we have "make <whatever> modules", compile modules
+# in addition to whatever we do anyway.
+# Just "make" or "make all" shall build modules as well
+
+# U-Boot does not need modules
+#ifneq ($(filter all _all modules,$(MAKECMDGOALS)),)
+# KBUILD_MODULES := 1
+#endif
+
+#ifeq ($(MAKECMDGOALS),)
+# KBUILD_MODULES := 1
+#endif
+
+export KBUILD_MODULES KBUILD_BUILTIN
+export KBUILD_CHECKSRC KBUILD_SRC KBUILD_EXTMOD
+
+# Beautify output
+# ---------------------------------------------------------------------------
+#
+# Normally, we echo the whole command before executing it. By making
+# that echo $($(quiet)$(cmd)), we now have the possibility to set
+# $(quiet) to choose other forms of output instead, e.g.
#
-# 2) Set environment variable BUILD_DIR to point to the desired location
-# 'export BUILD_DIR=/tmp/build'
-# 'make'
+# quiet_cmd_cc_o_c = Compiling $(RELDIR)/$@
+# cmd_cc_o_c = $(CC) $(c_flags) -c -o $@ $<
#
-# The second approach can also be used with a MAKEALL script
-# 'export BUILD_DIR=/tmp/build'
-# './MAKEALL'
+# If $(quiet) is empty, the whole command will be printed.
+# If it is set to "quiet_", only the short version will be printed.
+# If it is set to "silent_", nothing will be printed at all, since
+# the variable $(silent_cmd_cc_o_c) doesn't exist.
#
-# Command line 'O=' setting overrides BUILD_DIR environment variable.
+# A simple variant is to prefix commands with $(Q) - that's useful
+# for commands that shall be hidden in non-verbose mode.
#
-# When none of the above methods is used the local build is performed and
-# the object files are placed in the source directory.
+# $(Q)ln $@ :<
#
+# If KBUILD_VERBOSE equals 0 then the above command will be hidden.
+# If KBUILD_VERBOSE equals 1 then the above command is displayed.
-ifeq ("$(origin O)", "command line")
-BUILD_DIR := $(O)
+ifeq ($(KBUILD_VERBOSE),1)
+ quiet =
+ Q =
+else
+ quiet=quiet_
+ Q = @
endif
-# Call a source code checker (by default, "sparse") as part of the
-# C compilation.
-#
-# Use 'make C=1' to enable checking of re-compiled files.
-#
-# See the linux kernel file "Documentation/sparse.txt" for more details,
-# including where to get the "sparse" utility.
+# If the user is running make -s (silent mode), suppress echoing of
+# commands
-ifdef C
-ifeq ("$(origin C)", "command line")
-CHECKSRC := $(C)
+ifneq ($(filter s% -s%,$(MAKEFLAGS)),)
+ quiet=silent_
endif
+
+export quiet Q KBUILD_VERBOSE
+
+
+# Look for make include files relative to root of kernel src
+MAKEFLAGS += --include-dir=$(srctree)
+
+# We need some generic definitions (do not try to remake the file).
+$(srctree)/scripts/Kbuild.include: ;
+include $(srctree)/scripts/Kbuild.include
+
+# Make variables (CC, etc...)
+
+AS = $(CROSS_COMPILE)as
+# Always use GNU ld
+ifneq ($(shell $(CROSS_COMPILE)ld.bfd -v 2> /dev/null),)
+LD = $(CROSS_COMPILE)ld.bfd
+else
+LD = $(CROSS_COMPILE)ld
endif
-ifndef CHECKSRC
- CHECKSRC = 0
+CC = $(CROSS_COMPILE)gcc
+CPP = $(CC) -E
+AR = $(CROSS_COMPILE)ar
+NM = $(CROSS_COMPILE)nm
+LDR = $(CROSS_COMPILE)ldr
+STRIP = $(CROSS_COMPILE)strip
+OBJCOPY = $(CROSS_COMPILE)objcopy
+OBJDUMP = $(CROSS_COMPILE)objdump
+AWK = awk
+RANLIB = $(CROSS_COMPILE)RANLIB
+DTC = dtc
+CHECK = sparse
+
+CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \
+ -Wbitwise -Wno-return-void -D__CHECK_ENDIAN__ $(CF)
+
+KBUILD_CPPFLAGS := -D__KERNEL__
+
+KBUILD_CFLAGS := -Wall -Wstrict-prototypes \
+ -Wno-format-security \
+ -fno-builtin -ffreestanding
+KBUILD_AFLAGS := -D__ASSEMBLY__
+
+# Read UBOOTRELEASE from include/config/uboot.release (if it exists)
+UBOOTRELEASE = $(shell cat include/config/uboot.release 2> /dev/null)
+UBOOTVERSION = $(VERSION)$(if $(PATCHLEVEL),.$(PATCHLEVEL)$(if $(SUBLEVEL),.$(SUBLEVEL)))$(EXTRAVERSION)
+
+export VERSION PATCHLEVEL SUBLEVEL UBOOTRELEASE UBOOTVERSION
+export ARCH CPU BOARD VENDOR SOC
+export CONFIG_SHELL HOSTCC HOSTCFLAGS HOSTLDFLAGS CROSS_COMPILE AS LD CC
+export CPP AR NM LDR STRIP OBJCOPY OBJDUMP
+export MAKE AWK
+export DTC CHECK CHECKFLAGS
+
+export KBUILD_CPPFLAGS NOSTDINC_FLAGS UBOOTINCLUDE
+export KBUILD_CFLAGS KBUILD_AFLAGS
+
+# When compiling out-of-tree modules, put MODVERDIR in the module
+# tree rather than in the kernel tree. The kernel tree might
+# even be read-only.
+export MODVERDIR := $(if $(KBUILD_EXTMOD),$(firstword $(KBUILD_EXTMOD))/).tmp_versions
+
+# Files to ignore in find ... statements
+
+RCS_FIND_IGNORE := \( -name SCCS -o -name BitKeeper -o -name .svn -o -name CVS \
+ -o -name .pc -o -name .hg -o -name .git \) -prune -o
+export RCS_TAR_IGNORE := --exclude SCCS --exclude BitKeeper --exclude .svn \
+ --exclude CVS --exclude .pc --exclude .hg --exclude .git
+
+# ===========================================================================
+# Rules shared between *config targets and build targets
+
+# Basic helpers built in scripts/
+PHONY += scripts_basic
+scripts_basic:
+ $(Q)$(MAKE) $(build)=scripts/basic
+ $(Q)rm -f .tmp_quiet_recordmcount
+
+# To avoid any implicit rule to kick in, define an empty command.
+scripts/basic/%: scripts_basic ;
+
+PHONY += outputmakefile
+# outputmakefile generates a Makefile in the output directory, if using a
+# separate output directory. This allows convenient use of make in the
+# output directory.
+outputmakefile:
+ifneq ($(KBUILD_SRC),)
+ $(Q)ln -fsn $(srctree) source
+ $(Q)$(CONFIG_SHELL) $(srctree)/scripts/mkmakefile \
+ $(srctree) $(objtree) $(VERSION) $(PATCHLEVEL)
endif
-export CHECKSRC
-ifneq ($(BUILD_DIR),)
-saved-output := $(BUILD_DIR)
+# To make sure we do not include .config for any of the *config targets
+# catch them early, and hand them over to scripts/kconfig/Makefile
+# It is allowed to specify more targets when calling make, including
+# mixing *config targets and build targets.
+# For example 'make oldconfig all'.
+# Detect when mixed targets is specified, and make a second invocation
+# of make so .config is not included in this case either (for *config).
-# Attempt to create a output directory.
-$(shell [ -d ${BUILD_DIR} ] || mkdir -p ${BUILD_DIR})
+version_h := include/generated/version_autogenerated.h
+timestamp_h := include/generated/timestamp_autogenerated.h
-# Verify if it was successful.
-BUILD_DIR := $(shell cd $(BUILD_DIR) && /bin/pwd)
-$(if $(BUILD_DIR),,$(error output directory "$(saved-output)" does not exist))
-endif # ifneq ($(BUILD_DIR),)
+no-dot-config-targets := clean clobber mrproper distclean \
+ help %docs check% coccicheck \
+ ubootversion backup
-OBJTREE := $(if $(BUILD_DIR),$(BUILD_DIR),$(CURDIR))
-SPLTREE := $(OBJTREE)/spl
-TPLTREE := $(OBJTREE)/tpl
-SRCTREE := $(CURDIR)
-TOPDIR := $(SRCTREE)
-LNDIR := $(OBJTREE)
-export TOPDIR SRCTREE OBJTREE SPLTREE TPLTREE
+config-targets := 0
+mixed-targets := 0
+dot-config := 1
-MKCONFIG := $(SRCTREE)/mkconfig
-export MKCONFIG
+ifneq ($(filter $(no-dot-config-targets), $(MAKECMDGOALS)),)
+ ifeq ($(filter-out $(no-dot-config-targets), $(MAKECMDGOALS)),)
+ dot-config := 0
+ endif
+endif
-# $(obj) and (src) are defined in config.mk but here in main Makefile
-# we also need them before config.mk is included which is the case for
-# some targets like unconfig, clean, clobber, distclean, etc.
-ifneq ($(OBJTREE),$(SRCTREE))
-obj := $(OBJTREE)/
-src := $(SRCTREE)/
-else
-obj :=
-src :=
+ifeq ($(KBUILD_EXTMOD),)
+ ifneq ($(filter config %config,$(MAKECMDGOALS)),)
+ config-targets := 1
+ ifneq ($(filter-out config %config,$(MAKECMDGOALS)),)
+ mixed-targets := 1
+ endif
+ endif
endif
-export obj src
-# Make sure CDPATH settings don't interfere
-unexport CDPATH
+ifeq ($(mixed-targets),1)
+# ===========================================================================
+# We're called with mixed targets (*config and build targets).
+# Handle them one by one.
-#########################################################################
+PHONY += $(MAKECMDGOALS) build-one-by-one
-# The "tools" are needed early, so put this first
-# Don't include stuff already done in $(LIBS)
-# The "examples" conditionally depend on U-Boot (say, when USE_PRIVATE_LIBGCC
-# is "yes"), so compile examples after U-Boot is compiled.
-SUBDIR_TOOLS = tools
-SUBDIRS = $(SUBDIR_TOOLS)
+$(MAKECMDGOALS): build-one-by-one
+ @:
-.PHONY : $(SUBDIRS) $(VERSION_FILE) $(TIMESTAMP_FILE)
+build-one-by-one:
+ $(Q)set -e; \
+ for i in $(MAKECMDGOALS); do \
+ $(MAKE) -f $(srctree)/Makefile $$i; \
+ done
-ifeq ($(obj)include/config.mk,$(wildcard $(obj)include/config.mk))
+else
+ifeq ($(config-targets),1)
+# ===========================================================================
+# *config targets only - make sure prerequisites are updated, and descend
+# in scripts/kconfig to make the *config target
-# Include autoconf.mk before config.mk so that the config options are available
-# to all top level build files. We need the dummy all: target to prevent the
-# dependency target in autoconf.mk.dep from being the default.
-all:
-sinclude $(obj)include/autoconf.mk.dep
-sinclude $(obj)include/autoconf.mk
+# Read arch specific Makefile to set KBUILD_DEFCONFIG as needed.
+# KBUILD_DEFCONFIG may point out an alternative default configuration
+# used for 'make defconfig'
-SUBDIR_EXAMPLES-y := examples/standalone
-SUBDIR_EXAMPLES-$(CONFIG_API) += examples/api
-ifndef CONFIG_SANDBOX
-SUBDIRS += $(SUBDIR_EXAMPLES-y)
-endif
+%_config:: outputmakefile
+ @$(MKCONFIG) -A $(@:_config=)
+
+else
+# ===========================================================================
+# Build targets only - this includes vmlinux, arch specific targets, clean
+# targets and others. In general all targets except *config targets.
# load ARCH, BOARD, and CPU configuration
-include $(obj)include/config.mk
-export ARCH CPU BOARD VENDOR SOC
+-include include/config.mk
-# set default to nothing for native builds
-ifeq ($(HOSTARCH),$(ARCH))
-CROSS_COMPILE ?=
-endif
+ifeq ($(dot-config),1)
+# Read in config
+-include include/autoconf.mk
+-include include/autoconf.mk.dep
# load other configuration
-include $(TOPDIR)/config.mk
-
-# Targets which don't build the source code
-NON_BUILD_TARGETS = backup clean clobber distclean mrproper tidy unconfig
+include $(srctree)/config.mk
-# Only do the generic board check when actually building, not configuring
-ifeq ($(filter $(NON_BUILD_TARGETS),$(MAKECMDGOALS)),)
-ifeq ($(findstring _config,$(MAKECMDGOALS)),)
-$(CHECK_GENERIC_BOARD)
-endif
+ifeq ($(wildcard include/config.mk),)
+$(error "System not configured - see README")
endif
# If board code explicitly specified LDSCRIPT or CONFIG_SYS_LDSCRIPT, use
#LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds.debug
ifdef CONFIG_SYS_LDSCRIPT
# need to strip off double quotes
- LDSCRIPT := $(CONFIG_SYS_LDSCRIPT:"%"=%)
+ LDSCRIPT := $(srctree)/$(CONFIG_SYS_LDSCRIPT:"%"=%)
endif
endif
# We don't expect a Makefile here
LDSCRIPT_MAKEFILE_DIR =
endif
- ifeq ($(wildcard $(LDSCRIPT)),)
-$(error could not find linker script)
- endif
endif
+else
+
+
+endif # $(dot-config)
+
+KBUILD_CFLAGS += -Os #-fomit-frame-pointer
+
+ifdef BUILD_TAG
+KBUILD_CFLAGS += -DBUILD_TAG='"$(BUILD_TAG)"'
+endif
+
+KBUILD_CFLAGS += $(call cc-option,-fno-stack-protector)
+
+KBUILD_CFLAGS += -g
+# $(KBUILD_AFLAGS) sets -g, which causes gcc to pass a suitable -g<format>
+# option to the assembler.
+KBUILD_AFLAGS += -g
+
+# Report stack usage if supported
+ifeq ($(shell $(CONFIG_SHELL) $(srctree)/scripts/gcc-stack-usage.sh $(CC)),y)
+ KBUILD_CFLAGS += -fstack-usage
+endif
+
+KBUILD_CFLAGS += $(call cc-option,-Wno-format-nonliteral)
+
+# turn jbsr into jsr for m68k
+ifeq ($(ARCH),m68k)
+ifeq ($(findstring 3.4,$(shell $(CC) --version)),3.4)
+KBUILD_AFLAGS += -Wa,-gstabs,-S
+endif
+endif
+
+ifneq ($(CONFIG_SYS_TEXT_BASE),)
+KBUILD_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
+endif
+
+export CONFIG_SYS_TEXT_BASE
+
+# Use UBOOTINCLUDE when you must reference the include/ directory.
+# Needed to be compatible with the O= option
+UBOOTINCLUDE :=
+ifneq ($(OBJTREE),$(SRCTREE))
+UBOOTINCLUDE += -I$(OBJTREE)/include
+endif
+UBOOTINCLUDE += -I$(srctree)/include \
+ -I$(srctree)/arch/$(ARCH)/include
+
+NOSTDINC_FLAGS += -nostdinc -isystem $(shell $(CC) -print-file-name=include)
+CHECKFLAGS += $(NOSTDINC_FLAGS)
+
+# FIX ME
+cpp_flags := $(KBUILD_CPPFLAGS) $(CPPFLAGS) $(UBOOTINCLUDE) $(NOSTDINC_FLAGS)
+c_flags := $(KBUILD_CFLAGS) $(cpp_flags)
+
#########################################################################
# U-Boot objects....order is important (i.e. start must be first)
head-$(CONFIG_4xx) += arch/powerpc/cpu/ppc4xx/resetvec.o
head-$(CONFIG_MPC85xx) += arch/powerpc/cpu/mpc85xx/resetvec.o
-OBJS := $(addprefix $(obj),$(head-y))
-
-HAVE_VENDOR_COMMON_LIB = $(if $(wildcard board/$(VENDOR)/common/Makefile),y,n)
+HAVE_VENDOR_COMMON_LIB = $(if $(wildcard $(srctree)/board/$(VENDOR)/common/Makefile),y,n)
-LIBS-y += lib/
-LIBS-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/
-LIBS-y += $(CPUDIR)/
+libs-y += lib/
+libs-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/
+libs-y += $(CPUDIR)/
ifdef SOC
-LIBS-y += $(CPUDIR)/$(SOC)/
-endif
-LIBS-$(CONFIG_IXP4XX_NPE) += drivers/net/npe/
-LIBS-$(CONFIG_OF_EMBED) += dts/
-LIBS-y += arch/$(ARCH)/lib/
-LIBS-y += fs/
-LIBS-y += net/
-LIBS-y += disk/
-LIBS-y += drivers/
-LIBS-y += drivers/dma/
-LIBS-y += drivers/gpio/
-LIBS-y += drivers/i2c/
-LIBS-y += drivers/input/
-LIBS-y += drivers/mmc/
-LIBS-y += drivers/mtd/
-LIBS-$(CONFIG_CMD_NAND) += drivers/mtd/nand/
-LIBS-y += drivers/mtd/onenand/
-LIBS-$(CONFIG_CMD_UBI) += drivers/mtd/ubi/
-LIBS-y += drivers/mtd/spi/
-LIBS-y += drivers/net/
-LIBS-y += drivers/net/phy/
-LIBS-y += drivers/pci/
-LIBS-y += drivers/power/ \
+libs-y += $(CPUDIR)/$(SOC)/
+endif
+libs-$(CONFIG_OF_EMBED) += dts/
+libs-y += arch/$(ARCH)/lib/
+libs-y += fs/
+libs-y += net/
+libs-y += disk/
+libs-y += drivers/
+libs-y += drivers/dma/
+libs-y += drivers/gpio/
+libs-y += drivers/i2c/
+libs-y += drivers/input/
+libs-y += drivers/mmc/
+libs-y += drivers/mtd/
+libs-$(CONFIG_CMD_NAND) += drivers/mtd/nand/
+libs-y += drivers/mtd/onenand/
+libs-$(CONFIG_CMD_UBI) += drivers/mtd/ubi/
+libs-y += drivers/mtd/spi/
+libs-y += drivers/net/
+libs-y += drivers/net/phy/
+libs-y += drivers/pci/
+libs-y += drivers/power/ \
drivers/power/fuel_gauge/ \
drivers/power/mfd/ \
drivers/power/pmic/ \
drivers/power/battery/
-LIBS-y += drivers/spi/
-LIBS-$(CONFIG_FMAN_ENET) += drivers/net/fm/
-LIBS-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/
-LIBS-y += drivers/serial/
-LIBS-y += drivers/usb/eth/
-LIBS-y += drivers/usb/gadget/
-LIBS-y += drivers/usb/host/
-LIBS-y += drivers/usb/musb/
-LIBS-y += drivers/usb/musb-new/
-LIBS-y += drivers/usb/phy/
-LIBS-y += drivers/usb/ulpi/
-LIBS-y += common/
-LIBS-y += lib/libfdt/
-LIBS-$(CONFIG_API) += api/
-LIBS-$(CONFIG_HAS_POST) += post/
-LIBS-y += test/
+libs-y += drivers/spi/
+libs-$(CONFIG_FMAN_ENET) += drivers/net/fm/
+libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/
+libs-y += drivers/serial/
+libs-y += drivers/usb/eth/
+libs-y += drivers/usb/gadget/
+libs-y += drivers/usb/host/
+libs-y += drivers/usb/musb/
+libs-y += drivers/usb/musb-new/
+libs-y += drivers/usb/phy/
+libs-y += drivers/usb/ulpi/
+libs-y += common/
+libs-y += lib/libfdt/
+libs-$(CONFIG_API) += api/
+libs-$(CONFIG_HAS_POST) += post/
+libs-y += test/
ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610))
-LIBS-y += arch/$(ARCH)/imx-common/
+libs-y += arch/$(ARCH)/imx-common/
endif
-LIBS-$(CONFIG_ARM) += arch/arm/cpu/
-LIBS-$(CONFIG_PPC) += arch/powerpc/cpu/
+libs-$(CONFIG_ARM) += arch/arm/cpu/
+libs-$(CONFIG_PPC) += arch/powerpc/cpu/
+
+libs-y += board/$(BOARDDIR)/
+
+libs-y := $(sort $(libs-y))
+
+u-boot-dirs := $(patsubst %/,%,$(filter %/, $(libs-y))) tools examples
+
+u-boot-alldirs := $(sort $(u-boot-dirs) $(patsubst %/,%,$(filter %/, $(libs-))))
+
+libs-y := $(patsubst %/, %/built-in.o, $(libs-y))
-LIBS-y += board/$(BOARDDIR)/
+u-boot-init := $(head-y)
+u-boot-main := $(libs-y)
-LIBS-y := $(patsubst %/, %/built-in.o, $(LIBS-y))
-LIBS := $(addprefix $(obj),$(sort $(LIBS-y)))
-.PHONY : $(LIBS)
# Add GCC lib
ifdef USE_PRIVATE_LIBGCC
ifeq ("$(USE_PRIVATE_LIBGCC)", "yes")
-PLATFORM_LIBGCC = $(OBJTREE)/arch/$(ARCH)/lib/libgcc.o
+PLATFORM_LIBGCC = $(OBJTREE)/arch/$(ARCH)/lib/lib.a
else
PLATFORM_LIBGCC = -L $(USE_PRIVATE_LIBGCC) -lgcc
endif
else
-PLATFORM_LIBGCC := -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc
+PLATFORM_LIBGCC := -L $(shell dirname `$(CC) $(c_flags) -print-libgcc-file-name`) -lgcc
endif
PLATFORM_LIBS += $(PLATFORM_LIBGCC)
export PLATFORM_LIBS
$(shell $(LD) --version | \
sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p')
-__OBJS := $(subst $(obj),,$(OBJS))
-__LIBS := $(subst $(obj),,$(LIBS))
-
#########################################################################
#########################################################################
DO_STATIC_RELA = \
start=$$($(NM) $(1) | grep __rel_dyn_start | cut -f 1 -d ' '); \
end=$$($(NM) $(1) | grep __rel_dyn_end | cut -f 1 -d ' '); \
- $(obj)tools/relocate-rela $(2) $(3) $$start $$end
+ tools/relocate-rela $(2) $(3) $$start $$end
else
DO_STATIC_RELA =
endif
# Always append ALL so that arch config.mk's can add custom ones
-ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map
-
-ALL-$(CONFIG_NAND_U_BOOT) += $(obj)u-boot-nand.bin
-ALL-$(CONFIG_ONENAND_U_BOOT) += $(obj)u-boot-onenand.bin
-ALL-$(CONFIG_RAMBOOT_PBL) += $(obj)u-boot.pbl
-ALL-$(CONFIG_SPL) += $(obj)spl/u-boot-spl.bin
-ALL-$(CONFIG_SPL_FRAMEWORK) += $(obj)u-boot.img
-ALL-$(CONFIG_TPL) += $(obj)tpl/u-boot-tpl.bin
-ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin
+ALL-y += u-boot.srec u-boot.bin System.map
+
+ALL-$(CONFIG_NAND_U_BOOT) += u-boot-nand.bin
+ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin
+ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl
+ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin
+ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img
+ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin
+ALL-$(CONFIG_OF_SEPARATE) += u-boot.dtb u-boot-dtb.bin
ifneq ($(CONFIG_SPL_TARGET),)
-ALL-$(CONFIG_SPL) += $(obj)$(CONFIG_SPL_TARGET:"%"=%)
+ALL-$(CONFIG_SPL) += $(CONFIG_SPL_TARGET:"%"=%)
endif
-ALL-$(CONFIG_REMAKE_ELF) += $(obj)u-boot.elf
+ALL-$(CONFIG_REMAKE_ELF) += u-boot.elf
# enable combined SPL/u-boot/dtb rules for tegra
ifneq ($(CONFIG_TEGRA),)
ifeq ($(CONFIG_SPL),y)
ifeq ($(CONFIG_OF_SEPARATE),y)
-ALL-y += $(obj)u-boot-dtb-tegra.bin
+ALL-y += u-boot-dtb-tegra.bin
else
-ALL-y += $(obj)u-boot-nodtb-tegra.bin
+ALL-y += u-boot-nodtb-tegra.bin
+endif
endif
endif
+
+LDFLAGS_u-boot += $(LDFLAGS_FINAL)
+ifneq ($(CONFIG_SYS_TEXT_BASE),)
+LDFLAGS_u-boot += -Ttext $(CONFIG_SYS_TEXT_BASE)
endif
-build := -f $(TOPDIR)/scripts/Makefile.build -C
+quiet_cmd_objcopy = OBJCOPY $@
+cmd_objcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@
-all: $(ALL-y) $(SUBDIR_EXAMPLES-y)
+quiet_cmd_mkimage = UIMAGE $@
+cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
+ $(if $(KBUILD_VERBOSE:1=), >/dev/null)
-$(obj)u-boot.dtb: checkdtc $(obj)u-boot
- $(MAKE) $(build) dts binary
- mv $(obj)dts/dt.dtb $@
+quiet_cmd_cat = CAT $@
+cmd_cat = cat $(filter-out $(PHONY), $^) > $@
-$(obj)u-boot-dtb.bin: $(obj)u-boot.bin $(obj)u-boot.dtb
- cat $^ >$@
+append = cat $(filter-out $< $(PHONY), $^) >> $@
-$(obj)u-boot.hex: $(obj)u-boot
- $(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@
+quiet_cmd_pad_cat = CAT $@
+cmd_pad_cat = $(cmd_objcopy) && $(append) || rm -f $@
-$(obj)u-boot.srec: $(obj)u-boot
- $(OBJCOPY) ${OBJCFLAGS} -O srec $< $@
+all: $(ALL-y)
-$(obj)u-boot.bin: $(obj)u-boot
- $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
- $(call DO_STATIC_RELA,$<,$@,$(CONFIG_SYS_TEXT_BASE))
- $(BOARD_SIZE_CHECK)
+PHONY += dtbs
+dtbs dts/dt.dtb: checkdtc u-boot
+ $(Q)$(MAKE) $(build)=dts dtbs
+
+u-boot-dtb.bin: u-boot.bin dts/dt.dtb FORCE
+ $(call if_changed,cat)
+
+quiet_cmd_copy = COPY $@
+ cmd_copy = cp $< $@
+
+u-boot.dtb: dts/dt.dtb
+ $(call cmd,copy)
-$(obj)u-boot.ldr: $(obj)u-boot
+OBJCOPYFLAGS_u-boot.hex := -O ihex
+
+OBJCOPYFLAGS_u-boot.srec := -O srec
+
+u-boot.hex u-boot.srec: u-boot FORCE
+ $(call if_changed,objcopy)
+
+OBJCOPYFLAGS_u-boot.bin := -O binary
+
+u-boot.bin: u-boot FORCE
+ $(call if_changed,objcopy)
+ $(call DO_STATIC_RELA,$<,$@,$(CONFIG_SYS_TEXT_BASE))
+ $(BOARD_SIZE_CHECK)
+
+u-boot.ldr: u-boot
$(CREATE_LDR_ENV)
$(LDR) -T $(CONFIG_BFIN_CPU) -c $@ $< $(LDR_FLAGS)
$(BOARD_SIZE_CHECK)
-$(obj)u-boot.ldr.hex: $(obj)u-boot.ldr
- $(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@ -I binary
+OBJCOPYFLAGS_u-boot.ldr.hex := -I binary -O ihex
+
+OBJCOPYFLAGS_u-boot.ldr.srec := -I binary -O srec
-$(obj)u-boot.ldr.srec: $(obj)u-boot.ldr
- $(OBJCOPY) ${OBJCFLAGS} -O srec $< $@ -I binary
+u-boot.ldr.hex u-boot.ldr.srec: u-boot.ldr FORCE
+ $(call if_changed,objcopy)
#
# U-Boot entry point, needed for booting of full-blown U-Boot
CONFIG_SYS_UBOOT_START := 0
endif
-$(obj)u-boot.img: $(obj)u-boot.bin
- $(obj)tools/mkimage -A $(ARCH) -T firmware -C none \
- -O u-boot -a $(CONFIG_SYS_TEXT_BASE) \
- -e $(CONFIG_SYS_UBOOT_START) \
- -n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \
- sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \
- -d $< $@
+MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \
+ -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
+ -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
-$(obj)u-boot.imx: $(obj)u-boot.bin depend
- $(MAKE) $(build) $(SRCTREE)/arch/arm/imx-common $(OBJTREE)/u-boot.imx
+MKIMAGEFLAGS_u-boot.kwb = -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \
+ -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE)
-$(obj)u-boot.kwb: $(obj)u-boot.bin
- $(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \
- -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
+MKIMAGEFLAGS_u-boot.pbl = -n $(CONFIG_SYS_FSL_PBL_RCW) \
+ -R $(CONFIG_SYS_FSL_PBL_PBI) -T pblimage
-$(obj)u-boot.pbl: $(obj)u-boot.bin
- $(obj)tools/mkimage -n $(CONFIG_SYS_FSL_PBL_RCW) \
- -R $(CONFIG_SYS_FSL_PBL_PBI) -T pblimage \
- -d $< $@
+u-boot.img u-boot.kwb u-boot.pbl: u-boot.bin FORCE
+ $(call if_changed,mkimage)
-$(obj)u-boot.sha1: $(obj)u-boot.bin
- $(obj)tools/ubsha1 $(obj)u-boot.bin
+u-boot.imx: u-boot.bin
+ $(Q)$(MAKE) $(build)=arch/arm/imx-common $@
-$(obj)u-boot.dis: $(obj)u-boot
- $(OBJDUMP) -d $< > $@
+u-boot.sha1: u-boot.bin
+ tools/ubsha1 u-boot.bin
-# $@ is output, $(1) and $(2) are inputs, $(3) is padded intermediate,
-# $(4) is pad-to
-SPL_PAD_APPEND = \
- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(4) -I binary -O binary \
- $(1) $(obj)$(3); \
- cat $(obj)$(3) $(2) > $@; \
- rm $(obj)$(3)
+u-boot.dis: u-boot
+ $(OBJDUMP) -d $< > $@
ifdef CONFIG_TPL
-SPL_PAYLOAD := $(obj)tpl/u-boot-with-tpl.bin
+SPL_PAYLOAD := tpl/u-boot-with-tpl.bin
else
-SPL_PAYLOAD := $(obj)u-boot.bin
+SPL_PAYLOAD := u-boot.bin
endif
-$(obj)u-boot-with-spl.bin: $(obj)spl/u-boot-spl.bin $(SPL_PAYLOAD)
- $(call SPL_PAD_APPEND,$<,$(SPL_PAYLOAD),spl/u-boot-spl-pad.bin,$(CONFIG_SPL_PAD_TO))
+OBJCOPYFLAGS_u-boot-with-spl.bin = -I binary -O binary \
+ --pad-to=$(CONFIG_SPL_PAD_TO)
+u-boot-with-spl.bin: spl/u-boot-spl.bin $(SPL_PAYLOAD) FORCE
+ $(call if_changed,pad_cat)
-$(obj)tpl/u-boot-with-tpl.bin: $(obj)tpl/u-boot-tpl.bin $(obj)u-boot.bin
- $(call SPL_PAD_APPEND,$<,$(obj)u-boot.bin,tpl/u-boot-tpl-pad.bin,$(CONFIG_TPL_PAD_TO))
+OBJCOPYFLAGS_u-boot-with-tpl.bin = -I binary -O binary \
+ --pad-to=$(CONFIG_TPL_PAD_TO)
+tpl/u-boot-with-tpl.bin: tpl/u-boot-tpl.bin u-boot.bin FORCE
+ $(call if_changed,pad_cat)
-$(obj)u-boot-with-spl.imx: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
- $(MAKE) $(build) $(SRCTREE)/arch/arm/imx-common \
- $(OBJTREE)/u-boot-with-spl.imx
+SPL: spl/u-boot-spl.bin FORCE
+ $(Q)$(MAKE) $(build)=arch/arm/imx-common $@
-$(obj)u-boot-with-nand-spl.imx: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
- $(MAKE) $(build) $(SRCTREE)/arch/arm/imx-common \
- $(OBJTREE)/u-boot-with-nand-spl.imx
+u-boot-with-spl.imx u-boot-with-nand-spl.imx: SPL u-boot.bin FORCE
+ $(Q)$(MAKE) $(build)=arch/arm/imx-common $@
-$(obj)u-boot.ubl: $(obj)u-boot-with-spl.bin
- $(obj)tools/mkimage -n $(UBL_CONFIG) -T ublimage \
- -e $(CONFIG_SYS_TEXT_BASE) -d $< $(obj)u-boot.ubl
+MKIMAGEFLAGS_u-boot.ubl = -n $(UBL_CONFIG) -T ublimage -e $(CONFIG_SYS_TEXT_BASE)
-$(obj)u-boot.ais: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
- $(obj)tools/mkimage -s -n $(if $(CONFIG_AIS_CONFIG_FILE),$(CONFIG_AIS_CONFIG_FILE),"/dev/null") \
- -T aisimage \
- -e $(CONFIG_SPL_TEXT_BASE) \
- -d $(obj)spl/u-boot-spl.bin \
- $(obj)spl/u-boot-spl.ais
- $(OBJCOPY) ${OBJCFLAGS} -I binary \
- --pad-to=$(CONFIG_SPL_MAX_SIZE) -O binary \
- $(obj)spl/u-boot-spl.ais $(obj)spl/u-boot-spl-pad.ais
- cat $(obj)spl/u-boot-spl-pad.ais $(obj)u-boot.img > \
- $(obj)u-boot.ais
+u-boot.ubl: u-boot-with-spl.bin FORCE
+ $(call if_changed,mkimage)
+MKIMAGEFLAGS_u-boot-spl.ais = -s -n $(if $(CONFIG_AIS_CONFIG_FILE), \
+ $(srctree)/$(CONFIG_AIS_CONFIG_FILE:"%"=%),"/dev/null") \
+ -T aisimage -e $(CONFIG_SPL_TEXT_BASE)
+spl/u-boot-spl.ais: spl/u-boot-spl.bin FORCE
+ $(call if_changed,mkimage)
-$(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin
- $(MAKE) $(build) $(SRCTREE)/$(CPUDIR)/$(SOC)/ $(OBJTREE)/u-boot.sb
+OBJCOPYFLAGS_u-boot.ais = -I binary -O binary --pad-to=$(CONFIG_SPL_MAX_SIZE)
+u-boot.ais: spl/u-boot-spl.ais u-boot.img FORCE
+ $(call if_changed,pad_cat)
+
+u-boot.sb: u-boot.bin spl/u-boot-spl.bin
+ $(Q)$(MAKE) $(build)=arch/arm/cpu/arm926ejs/mxs $(objtree)/u-boot.sb
# On x600 (SPEAr600) U-Boot is appended to U-Boot SPL.
# Both images are created using mkimage (crc etc), so that the ROM
# SPL image (with mkimage header) and not the binary. Otherwise the resulting image
# which is loaded/copied by the ROM bootloader to SRAM doesn't fit.
# The resulting image containing both U-Boot images is called u-boot.spr
-$(obj)u-boot.spr: $(obj)u-boot.img $(obj)spl/u-boot-spl.bin
- $(obj)tools/mkimage -A $(ARCH) -T firmware -C none \
- -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) -n XLOADER \
- -d $(obj)spl/u-boot-spl.bin $@
- $(OBJCOPY) -I binary -O binary \
- --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff $@
- cat $(obj)u-boot.img >> $@
+MKIMAGEFLAGS_u-boot-spl.img = -A $(ARCH) -T firmware -C none \
+ -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) -n XLOADER
+spl/u-boot-spl.img: spl/u-boot-spl.bin FORCE
+ $(call if_changed,mkimage)
+
+OBJCOPYFLAGS_u-boot.spr = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \
+ --gap-fill=0xff
+u-boot.spr: spl/u-boot-spl.img u-boot.img FORCE
+ $(call if_changed,pad_cat)
ifneq ($(CONFIG_TEGRA),)
-$(obj)u-boot-nodtb-tegra.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SYS_TEXT_BASE) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
- cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@
- rm $(obj)spl/u-boot-spl-pad.bin
+OBJCOPYFLAGS_u-boot-nodtb-tegra.bin = -O binary --pad-to=$(CONFIG_SYS_TEXT_BASE)
+u-boot-nodtb-tegra.bin: spl/u-boot-spl u-boot.bin FORCE
+ $(call if_changed,pad_cat)
ifeq ($(CONFIG_OF_SEPARATE),y)
-$(obj)u-boot-dtb-tegra.bin: $(obj)u-boot-nodtb-tegra.bin $(obj)u-boot.dtb
- cat $(obj)u-boot-nodtb-tegra.bin $(obj)u-boot.dtb > $@
+u-boot-dtb-tegra.bin: u-boot-nodtb-tegra.bin dts/dt.dtb FORCE
+ $(call if_changed,cat)
endif
endif
-$(obj)u-boot-img.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
- cat $(obj)spl/u-boot-spl.bin $(obj)u-boot.img > $@
+u-boot-img.bin: spl/u-boot-spl.bin u-boot.img FORCE
+ $(call if_changed,cat)
# PPC4xx needs the SPL at the end of the image, since the reset vector
# is located at 0xfffffffc. So we can't use the "u-boot-img.bin" target
# and need to introduce a new build target with the full blown U-Boot
# at the start padded up to the start of the SPL image. And then concat
# the SPL image to the end.
-$(obj)u-boot-img-spl-at-end.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
- $(OBJCOPY) -I binary -O binary --pad-to=$(CONFIG_UBOOT_PAD_TO) \
- --gap-fill=0xff $(obj)u-boot.img $@
- cat $(obj)spl/u-boot-spl.bin >> $@
+
+OBJCOPYFLAGS_u-boot-img-spl-at-end.bin := -I binary -O binary \
+ --pad-to=$(CONFIG_UBOOT_PAD_TO) --gap-fill=0xff
+u-boot-img-spl-at-end.bin: u-boot.img spl/u-boot-spl.bin FORCE
+ $(call if_changed,pad_cat)
# Create a new ELF from a raw binary file. This is useful for arm64
# where static relocation needs to be performed on the raw binary,
# but certain simulators only accept an ELF file (but don't do the
# relocation).
# FIXME refactor dts/Makefile to share target/arch detection
-$(obj)u-boot.elf: $(obj)u-boot.bin
+u-boot.elf: u-boot.bin
@$(OBJCOPY) -B aarch64 -I binary -O elf64-littleaarch64 \
- $< $(obj)u-boot-elf.o
- @$(LD) $(obj)u-boot-elf.o -o $@ \
+ $< u-boot-elf.o
+ @$(LD) u-boot-elf.o -o $@ \
--defsym=_start=$(CONFIG_SYS_TEXT_BASE) \
-Ttext=$(CONFIG_SYS_TEXT_BASE)
-ifeq ($(CONFIG_SANDBOX),y)
-GEN_UBOOT = \
- cd $(LNDIR) && $(CC) $(SYMS) -T $(obj)u-boot.lds \
- -Wl,--start-group $(__LIBS) -Wl,--end-group \
- $(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map -o u-boot
-else
-GEN_UBOOT = \
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) \
- $(__OBJS) \
- --start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \
- -Map u-boot.map -o u-boot
-endif
+# Rule to link u-boot
+# May be overridden by arch/$(ARCH)/config.mk
+quiet_cmd_u-boot__ ?= LD $@
+ cmd_u-boot__ ?= $(LD) $(LDFLAGS) $(LDFLAGS_u-boot) -o $@ \
+ -T u-boot.lds $(u-boot-init) \
+ --start-group $(u-boot-main) --end-group \
+ $(PLATFORM_LIBS) -Map u-boot.map
-$(obj)u-boot: depend \
- $(SUBDIR_TOOLS) $(OBJS) $(LIBS) $(obj)u-boot.lds
- $(GEN_UBOOT)
+u-boot: $(u-boot-init) $(u-boot-main) u-boot.lds
+ $(call if_changed,u-boot__)
ifeq ($(CONFIG_KALLSYMS),y)
- smap=`$(call SYSTEM_MAP,$(obj)u-boot) | \
- awk '$$2 ~ /[tTwW]/ {printf $$1 $$3 "\\\\000"}'` ; \
- $(CC) $(CFLAGS) -DSYSTEM_MAP="\"$${smap}\"" \
- -c common/system_map.c -o $(obj)common/system_map.o
- $(GEN_UBOOT) $(obj)common/system_map.o
+ smap=`$(call SYSTEM_MAP,u-boot) | \
+ awk '$$2 ~ /[tTwW]/ {printf $$1 $$3 "\\\\000"}'` ; \
+ $(CC) $(c_flags) -DSYSTEM_MAP="\"$${smap}\"" \
+ -c $(srctree)/common/system_map.c -o common/system_map.o
+ $(call cmd,u-boot__) common/system_map.o
endif
-$(OBJS):
- @:
+# The actual objects are generated when descending,
+# make sure no implicit rule kicks in
+$(sort $(u-boot-init) $(u-boot-main)): $(u-boot-dirs) ;
-$(LIBS): depend $(SUBDIR_TOOLS)
- $(MAKE) $(build) $(dir $(subst $(obj),,$@))
+# Handle descending into subdirectories listed in $(vmlinux-dirs)
+# Preset locale variables to speed up the build process. Limit locale
+# tweaks to this spot to avoid wrong language settings when running
+# make menuconfig etc.
+# Error messages still appears in the original language
-$(SUBDIRS): depend
- $(MAKE) -C $@ all
+PHONY += $(u-boot-dirs)
+$(u-boot-dirs): prepare scripts
+ $(Q)$(MAKE) $(build)=$@
-$(SUBDIR_EXAMPLES-y): $(obj)u-boot
+tools: prepare
+# The "tools" are needed early
+$(filter-out tools, $(u-boot-dirs)): tools
+# The "examples" conditionally depend on U-Boot (say, when USE_PRIVATE_LIBGCC
+# is "yes"), so compile examples after U-Boot is compiled.
+examples: $(filter-out examples, $(u-boot-dirs))
+
+define filechk_uboot.release
+ echo "$(UBOOTVERSION)$$($(CONFIG_SHELL) $(srctree)/scripts/setlocalversion $(srctree))"
+endef
+
+# Store (new) UBOOTRELEASE string in include/config/uboot.release
+include/config/uboot.release: Makefile FORCE
+ $(call filechk,uboot.release)
+
+
+# Things we need to do before we recursively start building the kernel
+# or the modules are listed in "prepare".
+# A multi level approach is used. prepareN is processed before prepareN-1.
+# archprepare is used in arch Makefiles and when processed asm symlink,
+# version.h and scripts_basic is processed / created.
+
+# Listed in dependency order
+PHONY += prepare archprepare prepare0 prepare1 prepare2 prepare3
+
+# prepare3 is used to check if we are building in a separate output directory,
+# and if so do:
+# 1) Check that make has not been executed in the kernel src $(srctree)
+prepare3: include/config/uboot.release
+ifneq ($(KBUILD_SRC),)
+ @$(kecho) ' Using $(srctree) as source for u-boot'
+ $(Q)if [ -f $(srctree)/include/config.mk ]; then \
+ echo >&2 " $(srctree) is not clean, please run 'make mrproper'"; \
+ echo >&2 " in the '$(srctree)' directory.";\
+ /bin/false; \
+ fi;
+endif
+
+# prepare2 creates a makefile if using a separate output directory
+prepare2: prepare3 outputmakefile
+
+prepare1: prepare2 $(version_h) $(timestamp_h)
+ifeq ($(__HAVE_ARCH_GENERIC_BOARD),)
+ifeq ($(CONFIG_SYS_GENERIC_BOARD),y)
+ @echo >&2 " Your architecture does not support generic board."
+ @echo >&2 " Please undefine CONFIG_SYS_GENERIC_BOARD in your board config file."
+ @/bin/false
+endif
+endif
+ifeq ($(wildcard $(LDSCRIPT)),)
+ @echo >&2 " Could not find linker script."
+ @/bin/false
+endif
+
+archprepare: prepare1 scripts_basic
+
+prepare0: archprepare FORCE
+ $(Q)$(MAKE) $(build)=.
-$(obj)u-boot.lds: $(LDSCRIPT) depend
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$< >$@
+# All the preparing..
+prepare: prepare0
-nand_spl: $(TIMESTAMP_FILE) $(VERSION_FILE) depend
- $(MAKE) -C nand_spl/board/$(BOARDDIR) all
+# Generate some files
+# ---------------------------------------------------------------------------
-$(obj)u-boot-nand.bin: nand_spl $(obj)u-boot.bin
- cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin
+define filechk_version.h
+ (echo \#define PLAIN_VERSION \"$(UBOOTRELEASE)\"; \
+ echo \#define U_BOOT_VERSION \"U-Boot \" PLAIN_VERSION; \
+ echo \#define CC_VERSION_STRING \"$$($(CC) --version | head -n 1)\"; \
+ echo \#define LD_VERSION_STRING \"$$($(LD) --version | head -n 1)\"; )
+endef
-$(obj)spl/u-boot-spl.bin: $(SUBDIR_TOOLS) depend
- $(MAKE) -C spl all
+define filechk_timestamp.h
+ (LC_ALL=C date +'#define U_BOOT_DATE "%b %d %C%y"'; \
+ LC_ALL=C date +'#define U_BOOT_TIME "%T"')
+endef
-$(obj)tpl/u-boot-tpl.bin: $(SUBDIR_TOOLS) depend
- $(MAKE) -C spl all CONFIG_TPL_BUILD=y
+$(version_h): $(srctree)/Makefile FORCE
+ $(call filechk,version.h)
-# Explicitly make _depend in subdirs containing multiple targets to prevent
-# parallel sub-makes creating .depend files simultaneously.
-depend dep: $(TIMESTAMP_FILE) $(VERSION_FILE) \
- $(obj)include/spl-autoconf.mk \
- $(obj)include/tpl-autoconf.mk \
- $(obj)include/autoconf.mk \
- $(obj)include/generated/generic-asm-offsets.h \
- $(obj)include/generated/asm-offsets.h
+$(timestamp_h): $(srctree)/Makefile FORCE
+ $(call filechk,timestamp.h)
+
+#
+# Auto-generate the autoconf.mk file (which is included by all makefiles)
+#
+# This target actually generates 2 files; autoconf.mk and autoconf.mk.dep.
+# the dep file is only include in this top level makefile to determine when
+# to regenerate the autoconf.mk file.
-TAG_SUBDIRS = $(SUBDIRS)
-TAG_SUBDIRS += $(dir $(__LIBS))
-TAG_SUBDIRS += include
+quiet_cmd_autoconf_dep = GEN $@
+ cmd_autoconf_dep = $(CC) -x c -DDO_DEPS_ONLY -M $(c_flags) \
+ -MQ include/autoconf.mk $(srctree)/include/common.h > $@ || rm $@
+
+include/autoconf.mk.dep: include/config.h include/common.h
+ $(call cmd,autoconf_dep)
+
+quiet_cmd_autoconf = GEN $@
+ cmd_autoconf = \
+ $(CPP) $(c_flags) -DDO_DEPS_ONLY -dM $(srctree)/include/common.h > $@.tmp && \
+ sed -n -f $(srctree)/tools/scripts/define2mk.sed $@.tmp > $@; \
+ rm $@.tmp
+
+include/autoconf.mk: include/config.h
+ $(call cmd,autoconf)
+
+# ---------------------------------------------------------------------------
+
+PHONY += depend dep
+depend dep:
+ @echo '*** Warning: make $@ is unnecessary now.'
+
+# ---------------------------------------------------------------------------
+quiet_cmd_cpp_lds = LDS $@
+cmd_cpp_lds = $(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ \
+ -x assembler-with-cpp -P -o $@ $<
+
+u-boot.lds: $(LDSCRIPT) prepare FORCE
+ $(call if_changed,cpp_lds)
+
+PHONY += nand_spl
+nand_spl: prepare
+ $(Q)$(MAKE) $(build)=nand_spl/board/$(BOARDDIR) all
+
+nand_spl/u-boot-spl-16k.bin: nand_spl
+ @:
+
+u-boot-nand.bin: nand_spl/u-boot-spl-16k.bin u-boot.bin FORCE
+ $(call if_changed,cat)
+
+spl/u-boot-spl.bin: spl/u-boot-spl
+ @:
+spl/u-boot-spl: tools prepare
+ $(Q)$(MAKE) obj=spl -f $(srctree)/spl/Makefile all
+
+tpl/u-boot-tpl.bin: tools prepare
+ $(Q)$(MAKE) obj=tpl -f $(srctree)/spl/Makefile all CONFIG_TPL_BUILD=y
+
+TAG_SUBDIRS := $(u-boot-dirs) include
FIND := find
FINDFLAGS := -L
-checkstack:
- $(CROSS_COMPILE)objdump -d $(obj)u-boot \
- `$(FIND) $(obj) -name u-boot-spl -print` | \
- perl $(src)scripts/checkstack.pl $(ARCH)
-
tags ctags:
- ctags -w -o $(obj)ctags `$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) \
+ ctags -w -o ctags `$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) \
-name '*.[chS]' -print`
etags:
$(NM) $1 | \
grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
LC_ALL=C sort
-$(obj)System.map: $(obj)u-boot
+System.map: u-boot
@$(call SYSTEM_MAP,$<) > $@
checkthumb:
false; \
fi
-#
-# Auto-generate the autoconf.mk file (which is included by all makefiles)
-#
-# This target actually generates 2 files; autoconf.mk and autoconf.mk.dep.
-# the dep file is only include in this top level makefile to determine when
-# to regenerate the autoconf.mk file.
-$(obj)include/autoconf.mk.dep: $(obj)include/config.h include/common.h
- @$(XECHO) Generating $@ ; \
- : Generate the dependancies ; \
- $(CC) -x c -DDO_DEPS_ONLY -M $(CFLAGS) $(CPPFLAGS) \
- -MQ $(obj)include/autoconf.mk include/common.h > $@ || \
- rm $@
-
-$(obj)include/autoconf.mk: $(obj)include/config.h
- @$(XECHO) Generating $@ ; \
- : Extract the config macros ; \
- $(CPP) $(CFLAGS) -DDO_DEPS_ONLY -dM include/common.h > $@.tmp && \
- sed -n -f tools/scripts/define2mk.sed $@.tmp > $@; \
- rm $@.tmp
-
-# Auto-generate the spl-autoconf.mk file (which is included by all makefiles for SPL)
-$(obj)include/tpl-autoconf.mk: $(obj)include/config.h
- @$(XECHO) Generating $@ ; \
- : Extract the config macros ; \
- $(CPP) $(CFLAGS) -DCONFIG_TPL_BUILD -DCONFIG_SPL_BUILD\
- -DDO_DEPS_ONLY -dM include/common.h > $@.tmp && \
- sed -n -f tools/scripts/define2mk.sed $@.tmp > $@; \
- rm $@.tmp
-
-$(obj)include/spl-autoconf.mk: $(obj)include/config.h
- @$(XECHO) Generating $@ ; \
- : Extract the config macros ; \
- $(CPP) $(CFLAGS) -DCONFIG_SPL_BUILD -DDO_DEPS_ONLY -dM include/common.h > $@.tmp && \
- sed -n -f tools/scripts/define2mk.sed $@.tmp > $@; \
- rm $@.tmp
-
-$(obj)include/generated/generic-asm-offsets.h: $(obj)lib/asm-offsets.s
- @$(XECHO) Generating $@
- tools/scripts/make-asm-offsets $(obj)lib/asm-offsets.s $@
-
-$(obj)lib/asm-offsets.s: $(obj)include/config.h $(src)lib/asm-offsets.c
- @mkdir -p $(obj)lib
- $(CC) -DDO_DEPS_ONLY \
- $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \
- -o $@ $(src)lib/asm-offsets.c -c -S
-
-$(obj)include/generated/asm-offsets.h: $(obj)$(CPUDIR)/$(SOC)/asm-offsets.s
- @$(XECHO) Generating $@
- tools/scripts/make-asm-offsets $(obj)$(CPUDIR)/$(SOC)/asm-offsets.s $@
-
-$(obj)$(CPUDIR)/$(SOC)/asm-offsets.s: $(obj)include/config.h
- @mkdir -p $(obj)$(CPUDIR)/$(SOC)
- if [ -f $(src)$(CPUDIR)/$(SOC)/asm-offsets.c ];then \
- $(CC) -DDO_DEPS_ONLY \
- $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \
- -o $@ $(src)$(CPUDIR)/$(SOC)/asm-offsets.c -c -S; \
- else \
- touch $@; \
- fi
-
#########################################################################
-else # !config.mk
-all $(obj)u-boot.hex $(obj)u-boot.srec $(obj)u-boot.bin \
-$(obj)u-boot.img $(obj)u-boot.dis $(obj)u-boot \
-$(filter-out tools,$(SUBDIRS)) \
-depend dep tags ctags etags cscope $(obj)System.map:
- @echo "System not configured - see README" >&2
- @ exit 1
-
-tools: $(VERSION_FILE) $(TIMESTAMP_FILE)
- $(MAKE) -C $@ all
-endif # config.mk
# ARM relocations should all be R_ARM_RELATIVE (32-bit) or
# R_AARCH64_RELATIVE (64-bit).
-checkarmreloc: $(obj)u-boot
+checkarmreloc: u-boot
@RELOC="`$(CROSS_COMPILE)readelf -r -W $< | cut -d ' ' -f 4 | \
grep R_A | sort -u`"; \
if test "$$RELOC" != "R_ARM_RELATIVE" -a \
false; \
fi
-$(VERSION_FILE):
- @mkdir -p $(dir $(VERSION_FILE))
- @( localvers='$(shell $(TOPDIR)/scripts/setlocalversion $(TOPDIR))' ; \
- printf '#define PLAIN_VERSION "%s%s"\n' \
- "$(U_BOOT_VERSION)" "$${localvers}" ; \
- printf '#define U_BOOT_VERSION "U-Boot %s%s"\n' \
- "$(U_BOOT_VERSION)" "$${localvers}" ; \
- ) > $@.tmp
- @( printf '#define CC_VERSION_STRING "%s"\n' \
- '$(shell $(CC) --version | head -n 1)' )>> $@.tmp
- @( printf '#define LD_VERSION_STRING "%s"\n' \
- '$(shell $(LD) -v | head -n 1)' )>> $@.tmp
- @cmp -s $@ $@.tmp && rm -f $@.tmp || mv -f $@.tmp $@
-
-$(TIMESTAMP_FILE):
- @mkdir -p $(dir $(TIMESTAMP_FILE))
- @LC_ALL=C date +'#define U_BOOT_DATE "%b %d %C%y"' > $@.tmp
- @LC_ALL=C date +'#define U_BOOT_TIME "%T"' >> $@.tmp
- @cmp -s $@ $@.tmp && rm -f $@.tmp || mv -f $@.tmp $@
-
-easylogo env gdb:
- $(MAKE) -C tools/$@ all MTD_VERSION=${MTD_VERSION}
-gdbtools: gdb
-
-xmldocs pdfdocs psdocs htmldocs mandocs: tools/kernel-doc/docproc
- $(MAKE) U_BOOT_VERSION=$(U_BOOT_VERSION) -C doc/DocBook/ $@
-
-tools-all: easylogo env gdb $(VERSION_FILE) $(TIMESTAMP_FILE)
- $(MAKE) -C tools HOST_TOOLS_ALL=y
+env: scripts_basic
+ $(Q)$(MAKE) $(build)=tools/$@
+
+tools-all: HOST_TOOLS_ALL=y
+tools-all: env tools ;
.PHONY : CHANGELOG
CHANGELOG:
cat COPYING | gzip -9 -c | ./tools/bin2header license_gzip > include/license.h
#########################################################################
-unconfig:
- @rm -f $(obj)include/config.h $(obj)include/config.mk \
- $(obj)board/*/config.tmp $(obj)board/*/*/config.tmp \
- $(obj)include/autoconf.mk $(obj)include/autoconf.mk.dep \
- $(obj)include/spl-autoconf.mk \
- $(obj)include/tpl-autoconf.mk
+###
+# Cleaning is done on three levels.
+# make clean Delete most generated files
+# Leave enough to build external modules
+# make mrproper Delete the current configuration, and all generated files
+# make distclean Remove editor backup files, patch leftover files and the like
+
+# Directories & files removed with 'make clean'
+CLEAN_DIRS += $(MODVERDIR)
+CLEAN_FILES += u-boot.lds include/bmp_logo.h include/bmp_logo_data.h \
+ board/*/config.tmp board/*/*/config.tmp \
+ include/autoconf.mk* include/spl-autoconf.mk \
+ include/tpl-autoconf.mk
+
+# Directories & files removed with 'make clobber'
+CLOBBER_DIRS += $(patsubst %,spl/%, $(filter-out Makefile, \
+ $(shell ls -1 spl 2>/dev/null))) \
+ tpl
+CLOBBER_FILES += u-boot* MLO* SPL System.map nand_spl/u-boot*
+
+# Directories & files removed with 'make mrproper'
+MRPROPER_DIRS += include/config include/generated
+MRPROPER_FILES += .config .config.old \
+ tags TAGS cscope* GPATH GTAGS GRTAGS GSYMS \
+ include/config.h include/config.mk
+
+# clean - Delete most, but leave enough to build external modules
+#
+clean: rm-dirs := $(CLEAN_DIRS)
+clean: rm-files := $(CLEAN_FILES)
+
+clean-dirs := $(foreach f,$(u-boot-alldirs),$(if $(wildcard $f/Makefile),$f))
+
+clean-dirs := $(addprefix _clean_, $(clean-dirs) doc/DocBook)
+
+PHONY += $(clean-dirs) clean archclean
+$(clean-dirs):
+ $(Q)$(MAKE) $(clean)=$(patsubst _clean_%,%,$@)
+
+# TODO: Do not use *.cfgtmp
+clean: $(clean-dirs)
+ $(call cmd,rmdirs)
+ $(call cmd,rmfiles)
+ @find $(if $(KBUILD_EXTMOD), $(KBUILD_EXTMOD), .) $(RCS_FIND_IGNORE) \
+ \( -name '*.[oas]' -o -name '*.ko' -o -name '.*.cmd' \
+ -o -name '*.ko.*' -o -name '*.su' -o -name '*.cfgtmp' \
+ -o -name '.*.d' -o -name '.*.tmp' -o -name '*.mod.c' \
+ -o -name '*.symtypes' -o -name 'modules.order' \
+ -o -name modules.builtin -o -name '.tmp_*.o.*' \
+ -o -name '*.gcno' \) -type f -print | xargs rm -f
+ @find $(if $(KBUILD_EXTMOD), $(KBUILD_EXTMOD), .) $(RCS_FIND_IGNORE) \
+ -path './nand_spl/*' -type l -print | xargs rm -f
+
+# clobber
+#
+clobber: rm-dirs := $(CLOBBER_DIRS)
+clobber: rm-files := $(CLOBBER_FILES)
-%_config:: unconfig
- @$(MKCONFIG) -A $(@:_config=)
+PHONY += clobber
-sinclude $(obj).boards.depend
-$(obj).boards.depend: boards.cfg
- @awk '(NF && $$1 !~ /^#/) { print $$7 ": " $$7 "_config; $$(MAKE)" }' $< > $@
+clobber: clean
+ $(call cmd,rmdirs)
+ $(call cmd,rmfiles)
-#########################################################################
-#########################################################################
+# mrproper - Delete all generated files, including .config
+#
+mrproper: rm-dirs := $(wildcard $(MRPROPER_DIRS))
+mrproper: rm-files := $(wildcard $(MRPROPER_FILES))
+mrproper-dirs := $(addprefix _mrproper_,scripts)
-clean:
- @rm -f $(obj)examples/standalone/atmel_df_pow2 \
- $(obj)examples/standalone/hello_world \
- $(obj)examples/standalone/interrupt \
- $(obj)examples/standalone/mem_to_mem_idma2intr \
- $(obj)examples/standalone/sched \
- $(obj)examples/standalone/smc911{11,x}_eeprom \
- $(obj)examples/standalone/test_burst \
- $(obj)examples/standalone/timer
- @rm -f $(obj)examples/api/demo{,.bin}
- @rm -f $(obj)tools/bmp_logo $(obj)tools/easylogo/easylogo \
- $(obj)tools/env/fw_printenv \
- $(obj)tools/envcrc \
- $(obj)tools/gdb/{gdbcont,gdbsend} \
- $(obj)tools/gen_eth_addr $(obj)tools/img2srec \
- $(obj)tools/dump{env,}image \
- $(obj)tools/mk{env,}image $(obj)tools/mpc86x_clk \
- $(obj)tools/mk{$(BOARD),}spl \
- $(obj)tools/mxsboot \
- $(obj)tools/ncb $(obj)tools/ubsha1 \
- $(obj)tools/kernel-doc/docproc \
- $(obj)tools/proftool
- @rm -f $(obj)board/cray/L1/{bootscript.c,bootscript.image} \
- $(obj)board/matrix_vision/*/bootscript.img \
- $(obj)u-boot.lds \
- $(obj)arch/blackfin/cpu/init.{lds,elf}
- @rm -f $(obj)include/bmp_logo.h
- @rm -f $(obj)include/bmp_logo_data.h
- @rm -f $(obj)lib/asm-offsets.s
- @rm -f $(obj)include/generated/asm-offsets.h
- @rm -f $(obj)$(CPUDIR)/$(SOC)/asm-offsets.s
- @rm -f $(TIMESTAMP_FILE) $(VERSION_FILE)
- @$(MAKE) -s -C doc/DocBook/ cleandocs
- @find $(OBJTREE) -type f \
- \( -name 'core' -o -name '*.bak' -o -name '*~' -o -name '*.su' \
- -o -name '*.o' -o -name '*.a' -o -name '*.exe' \
- -o -name '*.cfgtmp' \) -print \
- | xargs rm -f
-
-# Removes everything not needed for testing u-boot
-tidy: clean
- @find $(OBJTREE) -type f \( -name '*.depend*' \) -print | xargs rm -f
-
-clobber: tidy
- @find $(OBJTREE) -type f \( -name '*.srec' \
- -o -name '*.bin' -o -name u-boot.img \) \
- -print0 | xargs -0 rm -f
- @rm -f $(OBJS) $(obj)*.bak $(obj)ctags $(obj)etags $(obj)TAGS \
- $(obj)cscope.* $(obj)*.*~
- @rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL-y)
- @rm -f $(obj)u-boot.kwb
- @rm -f $(obj)u-boot.pbl
- @rm -f $(obj)u-boot.imx
- @rm -f $(obj)u-boot-with-spl.imx
- @rm -f $(obj)u-boot-with-nand-spl.imx
- @rm -f $(obj)u-boot.ubl
- @rm -f $(obj)u-boot.ais
- @rm -f $(obj)u-boot.dtb
- @rm -f $(obj)u-boot.sb
- @rm -f $(obj)u-boot.spr
- @rm -f $(obj)nand_spl/{u-boot.{lds,lst},System.map}
- @rm -f $(obj)nand_spl/{u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map}
- @rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.map}
- @rm -f $(obj)spl/u-boot-spl.lds
- @rm -f $(obj)tpl/{u-boot-tpl,u-boot-tpl.bin,u-boot-tpl.map}
- @rm -f $(obj)tpl/u-boot-spl.lds
- @rm -f $(obj)MLO MLO.byteswap
- @rm -f $(obj)SPL
- @rm -f $(obj)tools/xway-swap-bytes
- @rm -fr $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
- @rm -fr $(obj)include/generated
- @[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f
- @rm -f $(obj)dts/*.tmp
- @rm -f $(obj)spl/u-boot-spl{,-pad}.ais
-
-mrproper \
-distclean: clobber unconfig
-ifneq ($(OBJTREE),$(SRCTREE))
- rm -rf $(obj)*
-endif
+PHONY += $(mrproper-dirs) mrproper archmrproper
+$(mrproper-dirs):
+ $(Q)$(MAKE) $(clean)=$(patsubst _mrproper_%,%,$@)
+
+mrproper: clobber $(mrproper-dirs)
+ $(call cmd,rmdirs)
+ $(call cmd,rmfiles)
+ @rm -f arch/*/include/asm/arch arch/*/include/asm/proc
+
+# distclean
+#
+PHONY += distclean
+
+distclean: mrproper
+ @find $(srctree) $(RCS_FIND_IGNORE) \
+ \( -name '*.orig' -o -name '*.rej' -o -name '*~' \
+ -o -name '*.bak' -o -name '#*#' -o -name '.*.orig' \
+ -o -name '.*.rej' \
+ -o -name '*%' -o -name '.*.cmd' -o -name 'core' \) \
+ -type f -print | xargs rm -f
backup:
F=`basename $(TOPDIR)` ; cd .. ; \
gtar --force-local -zcvf `LC_ALL=C date "+$$F-%Y-%m-%d-%T.tar.gz"` $$F
-#########################################################################
+help:
+ @echo 'Cleaning targets:'
+ @echo ' clean - Remove most generated files but keep the config and'
+ @echo ' necessities for testing u-boot'
+ @echo ' clobber - Remove most generated files but keep the config'
+ @echo ' mrproper - Remove all generated files + config + various backup files'
+ @echo ' distclean - mrproper + remove editor backup and patch files'
+ @echo ''
+# uncomment after adding Kconfig feature
+# @echo 'Configuration targets:'
+# @$(MAKE) -f $(srctree)/scripts/kconfig/Makefile help
+# @echo ''
+ @echo 'Other generic targets:'
+ @echo ' all - Build all necessary images depending on configuration'
+ @echo ' u-boot - Build the bare u-boot'
+ @echo ' dir/ - Build all files in dir and below'
+ @echo ' dir/file.[oisS] - Build specified target only'
+ @echo ' dir/file.lst - Build specified mixed source/assembly target only'
+ @echo ' (requires a recent binutils and recent build (System.map))'
+ @echo ' tags/TAGS - Generate tags file for editors'
+ @echo ' cscope - Generate cscope index'
+ @echo ' ubootrelease - Output the release version string'
+ @echo ' ubootversion - Output the version stored in Makefile'
+ @echo ''
+ @echo 'Static analysers'
+ @echo ' checkstack - Generate a list of stack hogs'
+ @echo ''
+ @echo 'Documentation targets:'
+ @$(MAKE) -f $(srctree)/doc/DocBook/Makefile dochelp
+ @echo ''
+ @echo ' make V=0|1 [targets] 0 => quiet build (default), 1 => verbose build'
+ @echo ' make V=2 [targets] 2 => give reason for rebuild of target'
+ @echo ' make O=dir [targets] Locate all output files in "dir", including .config'
+ @echo ' make C=1 [targets] Check all c source with $$CHECK (sparse by default)'
+ @echo ' make C=2 [targets] Force check of all c source with $$CHECK'
+ @echo ' make RECORDMCOUNT_WARN=1 [targets] Warn about ignored mcount sections'
+ @echo ' make W=n [targets] Enable extra gcc checks, n=1,2,3 where'
+ @echo ' 1: warnings which may be relevant and do not occur too often'
+ @echo ' 2: warnings which occur quite often but may still be relevant'
+ @echo ' 3: more obscure warnings, can most likely be ignored'
+ @echo ' Multiple levels can be combined with W=12 or W=123'
+ @echo ''
+ @echo 'Execute "make" or "make all" to build all targets marked with [*] '
+ @echo 'For further info see the ./README file'
+
+
+# Documentation targets
+# ---------------------------------------------------------------------------
+%docs: scripts_basic FORCE
+ $(Q)$(MAKE) $(build)=scripts build_docproc
+ $(Q)$(MAKE) $(build)=doc/DocBook $@
+
+# Dummies...
+PHONY += prepare scripts
+prepare: ;
+scripts: ;
+
+endif #ifeq ($(config-targets),1)
+endif #ifeq ($(mixed-targets),1)
+
+PHONY += checkstack ubootrelease ubootversion
+
+checkstack:
+ $(OBJDUMP) -d u-boot $$(find . -name u-boot-spl) | \
+ $(PERL) $(src)/scripts/checkstack.pl $(ARCH)
+
+ubootrelease:
+ @echo "$(UBOOTVERSION)$$($(CONFIG_SHELL) $(srctree)/scripts/setlocalversion $(srctree))"
+
+ubootversion:
+ @echo $(UBOOTVERSION)
+
+# Single targets
+# ---------------------------------------------------------------------------
+# Single targets are compatible with:
+# - build with mixed source and output
+# - build with separate output dir 'make O=...'
+# - external modules
+#
+# target-dir => where to store outputfile
+# build-dir => directory in kernel source tree to use
+
+ifeq ($(KBUILD_EXTMOD),)
+ build-dir = $(patsubst %/,%,$(dir $@))
+ target-dir = $(dir $@)
+else
+ zap-slash=$(filter-out .,$(patsubst %/,%,$(dir $@)))
+ build-dir = $(KBUILD_EXTMOD)$(if $(zap-slash),/$(zap-slash))
+ target-dir = $(if $(KBUILD_EXTMOD),$(dir $<),$(dir $@))
+endif
+
+%.s: %.c prepare scripts FORCE
+ $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@)
+%.i: %.c prepare scripts FORCE
+ $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@)
+%.o: %.c prepare scripts FORCE
+ $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@)
+%.lst: %.c prepare scripts FORCE
+ $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@)
+%.s: %.S prepare scripts FORCE
+ $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@)
+%.o: %.S prepare scripts FORCE
+ $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@)
+%.symtypes: %.c prepare scripts FORCE
+ $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@)
+
+# Modules
+/: prepare scripts FORCE
+ $(cmd_crmodverdir)
+ $(Q)$(MAKE) KBUILD_MODULES=$(if $(CONFIG_MODULES),1) \
+ $(build)=$(build-dir)
+%/: prepare scripts FORCE
+ $(cmd_crmodverdir)
+ $(Q)$(MAKE) KBUILD_MODULES=$(if $(CONFIG_MODULES),1) \
+ $(build)=$(build-dir)
+%.ko: prepare scripts FORCE
+ $(cmd_crmodverdir)
+ $(Q)$(MAKE) KBUILD_MODULES=$(if $(CONFIG_MODULES),1) \
+ $(build)=$(build-dir) $(@:.ko=.o)
+ $(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modpost
+
+# FIXME Should go into a make.lib or something
+# ===========================================================================
+
+quiet_cmd_rmdirs = $(if $(wildcard $(rm-dirs)),CLEAN $(wildcard $(rm-dirs)))
+ cmd_rmdirs = rm -rf $(rm-dirs)
+
+quiet_cmd_rmfiles = $(if $(wildcard $(rm-files)),CLEAN $(wildcard $(rm-files)))
+ cmd_rmfiles = rm -f $(rm-files)
+
+# read all saved command lines
+
+targets := $(wildcard $(sort $(targets)))
+cmd_files := $(wildcard .*.cmd $(foreach f,$(targets),$(dir $(f)).$(notdir $(f)).cmd))
+
+ifneq ($(cmd_files),)
+ $(cmd_files): ; # Do not try to update included dependency files
+ include $(cmd_files)
+endif
+
+# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.clean obj=dir
+# Usage:
+# $(Q)$(MAKE) $(clean)=dir
+clean := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.clean obj
+
+endif # skip-makefile
+
+PHONY += FORCE
+FORCE:
+
+# Declare the contents of the .PHONY variable as phony. We keep that
+# information in a variable so we can use it in if_changed and friends.
+.PHONY: $(PHONY)
/s3c24x0 Files specific to Samsung S3C24X0 CPUs
/arm926ejs Files specific to ARM 926 CPUs
/arm1136 Files specific to ARM 1136 CPUs
- /ixp Files specific to Intel XScale IXP CPUs
/pxa Files specific to Intel XScale PXA CPUs
/sa1100 Files specific to Intel StrongARM SA1100 CPUs
/lib Architecture specific library files
Board config to use DDR3. It can be enabled for SoCs with
Freescale DDR3 controllers.
+ CONFIG_SYS_FSL_IFC_BE
+ Defines the IFC controller register space as Big Endian
+
+ CONFIG_SYS_FSL_IFC_LE
+ Defines the IFC controller register space as Little Endian
+
CONFIG_SYS_FSL_PBL_PBI
It enables addition of RCW (Power on reset configuration) in built image.
Please refer doc/README.pblimage for more details
PBI commands can be used to configure SoC before it starts the execution.
Please refer doc/README.pblimage for more details
+ CONFIG_SYS_FSL_DDR_BE
+ Defines the DDR controller register space as Big Endian
+
+ CONFIG_SYS_FSL_DDR_LE
+ Defines the DDR controller register space as Little Endian
+
+ CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
+ Physical address from the view of DDR controllers. It is the
+ same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But
+ it could be different for ARM SoCs.
+
+ CONFIG_SYS_FSL_DDR_INTLV_256B
+ DDR controller interleaving on 256-byte. This is a special
+ interleaving mode, handled by Dickens for Freescale layerscape
+ SoCs with ARM core.
+
- Intel Monahans options:
CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
CONFIG_CMD_BSP * Board specific commands
CONFIG_CMD_BOOTD bootd
CONFIG_CMD_CACHE * icache, dcache
+ CONFIG_CMD_CLK * clock command support
CONFIG_CMD_CONSOLE coninfo
CONFIG_CMD_CRC32 * crc32
CONFIG_CMD_DATE * support for RTC, date/time...
CONFIG_CMD_EXPORTENV * export the environment
CONFIG_CMD_EXT2 * ext2 command support
CONFIG_CMD_EXT4 * ext4 command support
+ CONFIG_CMD_FS_GENERIC * filesystem commands (e.g. load, ls)
+ that work for multiple fs types
CONFIG_CMD_SAVEENV saveenv
CONFIG_CMD_FDC * Floppy Disk Support
CONFIG_CMD_FAT * FAT command support
- CONFIG_CMD_FDOS * Dos diskette Support
CONFIG_CMD_FLASH flinfo, erase, protect
CONFIG_CMD_FPGA FPGA device initialization support
CONFIG_CMD_FUSE * Device fuse support
If this option is set, then U-Boot will prevent the environment
variable "splashimage" from being set to a problematic address
- (see README.displaying-bmps and README.arm-unaligned-accesses).
+ (see README.displaying-bmps).
This option is useful for targets where, due to alignment
restrictions, an improperly aligned BMP image will cause a data
abort. If you think you will not have problems with unaligned
CONFIG_RSA
This enables the RSA algorithm used for FIT image verification
- in U-Boot. See doc/uImage/signature for more information.
+ in U-Boot. See doc/uImage.FIT/signature.txt for more information.
The signing part is build into mkimage regardless of this
option.
+- bootcount support:
+ CONFIG_BOOTCOUNT_LIMIT
+
+ This enables the bootcounter support, see:
+ http://www.denx.de/wiki/DULG/UBootBootCountLimit
+
+ CONFIG_AT91SAM9XE
+ enable special bootcounter support on at91sam9xe based boards.
+ CONFIG_BLACKFIN
+ enable special bootcounter support on blackfin based boards.
+ CONFIG_SOC_DA8XX
+ enable special bootcounter support on da850 based boards.
+ CONFIG_BOOTCOUNT_RAM
+ enable support for the bootcounter in RAM
+ CONFIG_BOOTCOUNT_I2C
+ enable support for the bootcounter on an i2c (like RTC) device.
+ CONFIG_SYS_I2C_RTC_ADDR = i2c chip address
+ CONFIG_SYS_BOOTCOUNT_ADDR = i2c addr which is used for
+ the bootcounter.
+ CONFIG_BOOTCOUNT_ALEN = address len
- Show boot progress:
CONFIG_SHOW_BOOT_PROGRESS
its config.mk file). If you find problems enabling this option on
your board please report the problem and send patches!
-- CONFIG_SYS_SYM_OFFSETS
- This is set by architectures that use offsets for link symbols
- instead of absolute values. So bss_start is obtained using an
- offset _bss_start_ofs from CONFIG_SYS_TEXT_BASE, rather than
- directly. You should not need to touch this setting.
-
- CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC (OMAP only)
This is set by OMAP boards for the max time that reset should
be asserted. See doc/README.omap-reset-time for details on how
--- /dev/null
+#
+# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifndef CONFIG_SYS_BIG_ENDIAN
+CONFIG_SYS_LITTLE_ENDIAN = 1
+endif
+
+ifdef CONFIG_SYS_LITTLE_ENDIAN
+CROSS_COMPILE ?= arc-buildroot-linux-uclibc-
+endif
+
+ifdef CONFIG_SYS_BIG_ENDIAN
+CROSS_COMPILE ?= arceb-buildroot-linux-uclibc-
+PLATFORM_LDFLAGS += -EB
+endif
+
+PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -DCONFIG_ARC -gdwarf-2
+
+LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
+
+# Needed for relocation
+LDFLAGS_FINAL += -pie
+
+# Load address for standalone apps
+CONFIG_STANDALONE_LOAD_ADDR ?= 0x82000000
+
+# Support generic board on ARC
+__HAVE_ARCH_GENERIC_BOARD := y
--- /dev/null
+#
+# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+extra-y += start.o
+
+obj-y += cache.o
+obj-y += cpu.o
+obj-y += interrupts.o
+obj-y += reset.o
+obj-y += timer.o
--- /dev/null
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/arcregs.h>
+
+/* Bit values in IC_CTRL */
+#define IC_CTRL_CACHE_DISABLE (1 << 0)
+
+/* Bit values in DC_CTRL */
+#define DC_CTRL_CACHE_DISABLE (1 << 0)
+#define DC_CTRL_INV_MODE_FLUSH (1 << 6)
+#define DC_CTRL_FLUSH_STATUS (1 << 8)
+
+int icache_status(void)
+{
+ return (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE) !=
+ IC_CTRL_CACHE_DISABLE;
+}
+
+void icache_enable(void)
+{
+ write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) &
+ ~IC_CTRL_CACHE_DISABLE);
+}
+
+void icache_disable(void)
+{
+ write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
+ IC_CTRL_CACHE_DISABLE);
+}
+
+void invalidate_icache_all(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+ /* Any write to IC_IVIC register triggers invalidation of entire I$ */
+ write_aux_reg(ARC_AUX_IC_IVIC, 1);
+#endif /* CONFIG_SYS_ICACHE_OFF */
+}
+
+int dcache_status(void)
+{
+ return (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE) !=
+ DC_CTRL_CACHE_DISABLE;
+}
+
+void dcache_enable(void)
+{
+ write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) &
+ ~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE));
+}
+
+void dcache_disable(void)
+{
+ write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) |
+ DC_CTRL_CACHE_DISABLE);
+}
+
+void flush_dcache_all(void)
+{
+ /* Do flush of entire cache */
+ write_aux_reg(ARC_AUX_DC_FLSH, 1);
+
+ /* Wait flush end */
+ while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
+ ;
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+static void dcache_flush_line(unsigned addr)
+{
+#if (CONFIG_ARC_MMU_VER > 2)
+ write_aux_reg(ARC_AUX_DC_PTAG, addr);
+#endif
+ write_aux_reg(ARC_AUX_DC_FLDL, addr);
+
+ /* Wait flush end */
+ while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
+ ;
+
+#ifndef CONFIG_SYS_ICACHE_OFF
+ /*
+ * Invalidate I$ for addresses range just flushed from D$.
+ * If we try to execute data flushed above it will be valid/correct
+ */
+#if (CONFIG_ARC_MMU_VER > 2)
+ write_aux_reg(ARC_AUX_IC_PTAG, addr);
+#endif
+ write_aux_reg(ARC_AUX_IC_IVIL, addr);
+#endif /* CONFIG_SYS_ICACHE_OFF */
+}
+#endif /* CONFIG_SYS_DCACHE_OFF */
+
+void flush_dcache_range(unsigned long start, unsigned long end)
+{
+#ifndef CONFIG_SYS_DCACHE_OFF
+ unsigned int addr;
+
+ start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
+ end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
+
+ for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE)
+ dcache_flush_line(addr);
+#endif /* CONFIG_SYS_DCACHE_OFF */
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long end)
+{
+#ifndef CONFIG_SYS_DCACHE_OFF
+ unsigned int addr;
+
+ start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
+ end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
+
+ for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) {
+#if (CONFIG_ARC_MMU_VER > 2)
+ write_aux_reg(ARC_AUX_DC_PTAG, addr);
+#endif
+ write_aux_reg(ARC_AUX_DC_IVDL, addr);
+ }
+#endif /* CONFIG_SYS_DCACHE_OFF */
+}
+
+void invalidate_dcache_all(void)
+{
+#ifndef CONFIG_SYS_DCACHE_OFF
+ /* Write 1 to DC_IVDC register triggers invalidation of entire D$ */
+ write_aux_reg(ARC_AUX_DC_IVDC, 1);
+#endif /* CONFIG_SYS_DCACHE_OFF */
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+ flush_dcache_range(start, start + size);
+}
--- /dev/null
+#
+# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -mA7
--- /dev/null
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arcregs.h>
+#include <asm/cache.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int arch_cpu_init(void)
+{
+#ifdef CONFIG_SYS_ICACHE_OFF
+ icache_disable();
+#else
+ icache_enable();
+ invalidate_icache_all();
+#endif
+
+ flush_dcache_all();
+#ifdef CONFIG_SYS_DCACHE_OFF
+ dcache_disable();
+#else
+ dcache_enable();
+#endif
+ timer_init();
+
+/* In simulation (ISS) "CHIPID" and "ARCNUM" are all "ff" */
+ if ((read_aux_reg(ARC_AUX_IDENTITY) & 0xffffff00) == 0xffffff00)
+ gd->arch.running_on_hw = 0;
+ else
+ gd->arch.running_on_hw = 1;
+
+ gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+int arch_early_init_r(void)
+{
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arcregs.h>
+#include <asm/ptrace.h>
+
+/* Bit values in STATUS32 */
+#define E1_MASK (1 << 1) /* Level 1 interrupts enable */
+#define E2_MASK (1 << 2) /* Level 2 interrupts enable */
+
+int interrupt_init(void)
+{
+ return 0;
+}
+
+/*
+ * returns true if interrupts had been enabled before we disabled them
+ */
+int disable_interrupts(void)
+{
+ int status = read_aux_reg(ARC_AUX_STATUS32);
+ int state = (status | E1_MASK | E2_MASK) ? 1 : 0;
+
+ status &= ~(E1_MASK | E2_MASK);
+ /* STATUS32 register is updated indirectly with "FLAG" instruction */
+ __asm__("flag %0" : : "r" (status));
+ return state;
+}
+
+void enable_interrupts(void)
+{
+ unsigned int status = read_aux_reg(ARC_AUX_STATUS32);
+
+ status |= E1_MASK | E2_MASK;
+ /* STATUS32 register is updated indirectly with "FLAG" instruction */
+ __asm__("flag %0" : : "r" (status));
+}
+
+static void print_reg_file(long *reg_rev, int start_num)
+{
+ unsigned int i;
+
+ /* Print 3 registers per line */
+ for (i = start_num; i < start_num + 25; i++) {
+ printf("r%02u: 0x%08lx\t", i, (unsigned long)*reg_rev);
+ if (((i + 1) % 3) == 0)
+ printf("\n");
+
+ /* Because pt_regs has registers reversed */
+ reg_rev--;
+ }
+
+ /* Add new-line if none was inserted in the end of loop above */
+ if (((i + 1) % 3) != 0)
+ printf("\n");
+}
+
+void show_regs(struct pt_regs *regs)
+{
+ printf("RET:\t0x%08lx\nBLINK:\t0x%08lx\nSTAT32:\t0x%08lx\n",
+ regs->ret, regs->blink, regs->status32);
+ printf("GP: 0x%08lx\t r25: 0x%08lx\t\n", regs->r26, regs->r25);
+ printf("BTA: 0x%08lx\t SP: 0x%08lx\t FP: 0x%08lx\n", regs->bta,
+ regs->sp, regs->fp);
+ printf("LPS: 0x%08lx\tLPE: 0x%08lx\tLPC: 0x%08lx\n", regs->lp_start,
+ regs->lp_end, regs->lp_count);
+
+ print_reg_file(&(regs->r0), 0);
+}
+
+void bad_mode(struct pt_regs *regs)
+{
+ if (regs)
+ show_regs(regs);
+
+ panic("Resetting CPU ...\n");
+}
+
+void do_memory_error(unsigned long address, struct pt_regs *regs)
+{
+ printf("Memory error exception @ 0x%lx\n", address);
+ bad_mode(regs);
+}
+
+void do_instruction_error(unsigned long address, struct pt_regs *regs)
+{
+ printf("Instruction error exception @ 0x%lx\n", address);
+ bad_mode(regs);
+}
+
+void do_machine_check_fault(unsigned long address, struct pt_regs *regs)
+{
+ printf("Machine check exception @ 0x%lx\n", address);
+ bad_mode(regs);
+}
+
+void do_interrupt_handler(void)
+{
+ printf("Interrupt fired\n");
+ bad_mode(0);
+}
+
+void do_itlb_miss(struct pt_regs *regs)
+{
+ printf("I TLB miss exception\n");
+ bad_mode(regs);
+}
+
+void do_dtlb_miss(struct pt_regs *regs)
+{
+ printf("D TLB miss exception\n");
+ bad_mode(regs);
+}
+
+void do_tlb_prot_violation(unsigned long address, struct pt_regs *regs)
+{
+ printf("TLB protection violation or misaligned access @ 0x%lx\n",
+ address);
+ bad_mode(regs);
+}
+
+void do_privilege_violation(struct pt_regs *regs)
+{
+ printf("Privilege violation exception\n");
+ bad_mode(regs);
+}
+
+void do_trap(struct pt_regs *regs)
+{
+ printf("Trap exception\n");
+ bad_mode(regs);
+}
+
+void do_extension(struct pt_regs *regs)
+{
+ printf("Extension instruction exception\n");
+ bad_mode(regs);
+}
--- /dev/null
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <command.h>
+#include <common.h>
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ printf("Put your restart handler here\n");
+
+#ifdef DEBUG
+ /* Stop debug session here */
+ __asm__("brk");
+#endif
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/arcregs.h>
+
+/*
+ * Note on the LD/ST addressing modes with address register write-back
+ *
+ * LD.a same as LD.aw
+ *
+ * LD.a reg1, [reg2, x] => Pre Incr
+ * Eff Addr for load = [reg2 + x]
+ *
+ * LD.ab reg1, [reg2, x] => Post Incr
+ * Eff Addr for load = [reg2]
+ */
+
+.macro PUSH reg
+ st.a \reg, [%sp, -4]
+.endm
+
+.macro PUSHAX aux
+ lr %r9, [\aux]
+ PUSH %r9
+.endm
+
+.macro SAVE_R1_TO_R24
+ PUSH %r1
+ PUSH %r2
+ PUSH %r3
+ PUSH %r4
+ PUSH %r5
+ PUSH %r6
+ PUSH %r7
+ PUSH %r8
+ PUSH %r9
+ PUSH %r10
+ PUSH %r11
+ PUSH %r12
+ PUSH %r13
+ PUSH %r14
+ PUSH %r15
+ PUSH %r16
+ PUSH %r17
+ PUSH %r18
+ PUSH %r19
+ PUSH %r20
+ PUSH %r21
+ PUSH %r22
+ PUSH %r23
+ PUSH %r24
+.endm
+
+.macro SAVE_ALL_SYS
+
+ st %r0, [%sp]
+ lr %r0, [%ecr]
+ st %r0, [%sp, 8] /* ECR */
+ st %sp, [%sp, 4]
+
+ SAVE_R1_TO_R24
+ PUSH %r25
+ PUSH %gp
+ PUSH %fp
+ PUSH %blink
+ PUSHAX %eret
+ PUSHAX %erstatus
+ PUSH %lp_count
+ PUSHAX %lp_end
+ PUSHAX %lp_start
+ PUSHAX %erbta
+.endm
+
+.align 4
+.globl _start
+_start:
+ /* Critical system events */
+ j reset /* 0 - 0x000 */
+ j memory_error /* 1 - 0x008 */
+ j instruction_error /* 2 - 0x010 */
+
+ /* Device interrupts */
+.rept 29
+ j interrupt_handler /* 3:31 - 0x018:0xF8 */
+.endr
+ /* Exceptions */
+ j EV_MachineCheck /* 0x100, Fatal Machine check (0x20) */
+ j EV_TLBMissI /* 0x108, Intruction TLB miss (0x21) */
+ j EV_TLBMissD /* 0x110, Data TLB miss (0x22) */
+ j EV_TLBProtV /* 0x118, Protection Violation (0x23)
+ or Misaligned Access */
+ j EV_PrivilegeV /* 0x120, Privilege Violation (0x24) */
+ j EV_Trap /* 0x128, Trap exception (0x25) */
+ j EV_Extension /* 0x130, Extn Intruction Excp (0x26) */
+
+memory_error:
+ SAVE_ALL_SYS
+ lr %r0, [%efa]
+ mov %r1, %sp
+ j do_memory_error
+
+instruction_error:
+ SAVE_ALL_SYS
+ lr %r0, [%efa]
+ mov %r1, %sp
+ j do_instruction_error
+
+interrupt_handler:
+ /* Todo - save and restore CPU context when interrupts will be in use */
+ bl do_interrupt_handler
+ rtie
+
+EV_MachineCheck:
+ SAVE_ALL_SYS
+ lr %r0, [%efa]
+ mov %r1, %sp
+ j do_machine_check_fault
+
+EV_TLBMissI:
+ SAVE_ALL_SYS
+ mov %r0, %sp
+ j do_itlb_miss
+
+EV_TLBMissD:
+ SAVE_ALL_SYS
+ mov %r0, %sp
+ j do_dtlb_miss
+
+EV_TLBProtV:
+ SAVE_ALL_SYS
+ lr %r0, [%efa]
+ mov %r1, %sp
+ j do_tlb_prot_violation
+
+EV_PrivilegeV:
+ SAVE_ALL_SYS
+ mov %r0, %sp
+ j do_privilege_violation
+
+EV_Trap:
+ SAVE_ALL_SYS
+ mov %r0, %sp
+ j do_trap
+
+EV_Extension:
+ SAVE_ALL_SYS
+ mov %r0, %sp
+ j do_extension
+
+
+reset:
+ /* Setup interrupt vector base that matches "__text_start" */
+ sr __text_start, [ARC_AUX_INTR_VEC_BASE]
+
+ /* Setup stack pointer */
+ mov %sp, CONFIG_SYS_INIT_SP_ADDR
+ mov %fp, %sp
+
+ /* Clear bss */
+ mov %r0, __bss_start
+ mov %r1, __bss_end
+
+clear_bss:
+ st.ab 0, [%r0, 4]
+ brlt %r0, %r1, clear_bss
+
+ /* Zero the one and only argument of "board_init_f" */
+ mov_s %r0, 0
+ j board_init_f
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * r0 = start_addr_sp
+ * r1 = new__gd
+ * r2 = relocaddr
+ */
+.align 4
+.globl relocate_code
+relocate_code:
+ /*
+ * r0-r12 might be clobbered by C functions
+ * so we use r13-r16 for storage here
+ */
+ mov %r13, %r0 /* save addr_sp */
+ mov %r14, %r1 /* save addr of gd */
+ mov %r15, %r2 /* save addr of destination */
+
+ mov %r16, %r2 /* %r9 - relocation offset */
+ sub %r16, %r16, __image_copy_start
+
+/* Set up the stack */
+stack_setup:
+ mov %sp, %r13
+ mov %fp, %sp
+
+/* Check if monitor is loaded right in place for relocation */
+ mov %r0, __image_copy_start
+ cmp %r0, %r15 /* skip relocation if code loaded */
+ bz do_board_init_r /* in target location already */
+
+/* Copy data (__image_copy_start - __image_copy_end) to new location */
+ mov %r1, %r15
+ mov %r2, __image_copy_end
+ sub %r2, %r2, %r0 /* r3 <- amount of bytes to copy */
+ asr %r2, %r2, 2 /* r3 <- amount of words to copy */
+ mov %lp_count, %r2
+ lp copy_end
+ ld.ab %r2,[%r0,4]
+ st.ab %r2,[%r1,4]
+copy_end:
+
+/* Fix relocations related issues */
+ bl do_elf_reloc_fixups
+#ifndef CONFIG_SYS_ICACHE_OFF
+ bl invalidate_icache_all
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+ bl flush_dcache_all
+#endif
+
+/* Update position of intterupt vector table */
+ lr %r0, [ARC_AUX_INTR_VEC_BASE] /* Read current position */
+ add %r0, %r0, %r16 /* Update address */
+ sr %r0, [ARC_AUX_INTR_VEC_BASE] /* Write new position */
+
+do_board_init_r:
+/* Prepare for exection of "board_init_r" in relocated monitor */
+ mov %r2, board_init_r /* old address of "board_init_r()" */
+ add %r2, %r2, %r16 /* new address of "board_init_r()" */
+ mov %r0, %r14 /* 1-st parameter: gd_t */
+ mov %r1, %r15 /* 2-nd parameter: dest_addr */
+ j [%r2]
--- /dev/null
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arcregs.h>
+
+#define NH_MODE (1 << 1) /* Disable timer if CPU is halted */
+
+int timer_init(void)
+{
+ write_aux_reg(ARC_AUX_TIMER0_CTRL, NH_MODE);
+ /* Set max value for counter/timer */
+ write_aux_reg(ARC_AUX_TIMER0_LIMIT, 0xffffffff);
+ /* Set initial count value and restart counter/timer */
+ write_aux_reg(ARC_AUX_TIMER0_CNT, 0);
+ return 0;
+}
+
+unsigned long timer_read_counter(void)
+{
+ return read_aux_reg(ARC_AUX_TIMER0_CNT);
+}
--- /dev/null
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-littlearc", "elf32-littlearc", "elf32-littlearc")
+OUTPUT_ARCH(arc)
+ENTRY(_start)
+SECTIONS
+{
+ . = ALIGN(4);
+ .text : {
+ *(.__text_start)
+ *(.__image_copy_start)
+ CPUDIR/start.o (.text*)
+ *(.text*)
+ }
+
+ . = ALIGN(4);
+ .text_end :
+ {
+ *(.__text_end)
+ }
+
+ . = ALIGN(4);
+ .rodata : {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ . = ALIGN(4);
+ .data : {
+ *(.data*)
+ }
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = ALIGN(4);
+ .rel_dyn_start : {
+ *(.__rel_dyn_start)
+ }
+
+ .rela.dyn : {
+ *(.rela.dyn)
+ }
+
+ .rel_dyn_end : {
+ *(.__rel_dyn_end)
+ }
+
+ . = ALIGN(4);
+ .bss_start : {
+ *(.__bss_start);
+ }
+
+ .bss : {
+ *(.bss*)
+ }
+
+ .bss_end : {
+ *(.__bss_end);
+ }
+
+ . = ALIGN(4);
+ .image_copy_end : {
+ *(.__image_copy_end)
+ *(.__init_end)
+ }
+}
--- /dev/null
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARC_ARCREGS_H
+#define _ASM_ARC_ARCREGS_H
+
+/*
+ * ARC architecture has additional address space - auxiliary registers.
+ * These registers are mostly used for configuration purposes.
+ * These registers are not memory mapped and special commands are used for
+ * access: "lr"/"sr".
+ */
+
+#define ARC_AUX_IDENTITY 0x04
+#define ARC_AUX_STATUS32 0x0a
+
+/* Instruction cache related auxiliary registers */
+#define ARC_AUX_IC_IVIC 0x10
+#define ARC_AUX_IC_CTRL 0x11
+#define ARC_AUX_IC_IVIL 0x19
+#if (CONFIG_ARC_MMU_VER > 2)
+#define ARC_AUX_IC_PTAG 0x1E
+#endif
+
+/* Timer related auxiliary registers */
+#define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */
+#define ARC_AUX_TIMER0_CTRL 0x22 /* Timer 0 control */
+#define ARC_AUX_TIMER0_LIMIT 0x23 /* Timer 0 limit */
+
+#define ARC_AUX_INTR_VEC_BASE 0x25
+
+/* Data cache related auxiliary registers */
+#define ARC_AUX_DC_IVDC 0x47
+#define ARC_AUX_DC_CTRL 0x48
+
+#define ARC_AUX_DC_IVDL 0x4A
+#define ARC_AUX_DC_FLSH 0x4B
+#define ARC_AUX_DC_FLDL 0x4C
+#if (CONFIG_ARC_MMU_VER > 2)
+#define ARC_AUX_DC_PTAG 0x5C
+#endif
+
+#ifndef __ASSEMBLY__
+/* Accessors for auxiliary registers */
+#define read_aux_reg(reg) __builtin_arc_lr(reg)
+
+/* gcc builtin sr needs reg param to be long immediate */
+#define write_aux_reg(reg_immed, val) \
+ __builtin_arc_sr((unsigned int)val, reg_immed)
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_ARC_ARCREGS_H */
--- /dev/null
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_BITOPS_H
+#define __ASM_ARC_BITOPS_H
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+#endif /* __ASM_ARC_BITOPS_H */
--- /dev/null
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_BYTEORDER_H
+#define __ASM_ARC_BYTEORDER_H
+
+#include <asm/types.h>
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+ #define __BYTEORDER_HAS_U64__
+ #define __SWAB_64_THRU_32__
+#endif
+
+#ifdef __LITTLE_ENDIAN__
+ #include <linux/byteorder/little_endian.h>
+#else
+ #include <linux/byteorder/big_endian.h>
+#endif /* CONFIG_SYS_BIG_ENDIAN */
+
+#endif /* ASM_ARC_BYTEORDER_H */
--- /dev/null
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_CACHE_H
+#define __ASM_ARC_CACHE_H
+
+#include <config.h>
+
+/*
+ * The current upper bound for ARC L1 data cache line sizes is 128 bytes.
+ * We use that value for aligning DMA buffers unless the board config has
+ * specified an alternate cache line size.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN 128
+#endif
+
+#endif /* __ASM_ARC_CACHE_H */
--- /dev/null
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_CONFIG_H_
+#define __ASM_ARC_CONFIG_H_
+
+#define CONFIG_LMB
+
+#endif /*__ASM_ARC_CONFIG_H_ */
--- /dev/null
+#include <asm-generic/errno.h>
--- /dev/null
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_GLOBAL_DATA_H
+#define __ASM_ARC_GLOBAL_DATA_H
+
+/* Architecture-specific global data */
+struct arch_global_data {
+ int running_on_hw;
+};
+
+#include <asm-generic/global_data.h>
+
+#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r25")
+
+#endif /* __ASM_ARC_GLOBAL_DATA_H */
--- /dev/null
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_IO_H
+#define __ASM_ARC_IO_H
+
+#include <linux/types.h>
+#include <asm/byteorder.h>
+
+static inline void sync(void)
+{
+ /* Not yet implemented */
+}
+
+static inline u8 __raw_readb(const volatile void __iomem *addr)
+{
+ u8 b;
+
+ __asm__ __volatile__("ldb%U1 %0, %1\n"
+ : "=r" (b)
+ : "m" (*(volatile u8 __force *)addr)
+ : "memory");
+ return b;
+}
+
+static inline u16 __raw_readw(const volatile void __iomem *addr)
+{
+ u16 s;
+
+ __asm__ __volatile__("ldw%U1 %0, %1\n"
+ : "=r" (s)
+ : "m" (*(volatile u16 __force *)addr)
+ : "memory");
+ return s;
+}
+
+static inline u32 __raw_readl(const volatile void __iomem *addr)
+{
+ u32 w;
+
+ __asm__ __volatile__("ld%U1 %0, %1\n"
+ : "=r" (w)
+ : "m" (*(volatile u32 __force *)addr)
+ : "memory");
+ return w;
+}
+
+#define readb __raw_readb
+
+static inline u16 readw(const volatile void __iomem *addr)
+{
+ return __le16_to_cpu(__raw_readw(addr));
+}
+
+static inline u32 readl(const volatile void __iomem *addr)
+{
+ return __le32_to_cpu(__raw_readl(addr));
+}
+
+static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
+{
+ __asm__ __volatile__("stb%U1 %0, %1\n"
+ :
+ : "r" (b), "m" (*(volatile u8 __force *)addr)
+ : "memory");
+}
+
+static inline void __raw_writew(u16 s, volatile void __iomem *addr)
+{
+ __asm__ __volatile__("stw%U1 %0, %1\n"
+ :
+ : "r" (s), "m" (*(volatile u16 __force *)addr)
+ : "memory");
+}
+
+static inline void __raw_writel(u32 w, volatile void __iomem *addr)
+{
+ __asm__ __volatile__("st%U1 %0, %1\n"
+ :
+ : "r" (w), "m" (*(volatile u32 __force *)addr)
+ : "memory");
+}
+
+#define writeb __raw_writeb
+#define writew(b, addr) __raw_writew(__cpu_to_le16(b), addr)
+#define writel(b, addr) __raw_writel(__cpu_to_le32(b), addr)
+
+static inline int __raw_readsb(unsigned int addr, void *data, int bytelen)
+{
+ __asm__ __volatile__ ("1:ld.di r8, [r0]\n"
+ "sub.f r2, r2, 1\n"
+ "bnz.d 1b\n"
+ "stb.ab r8, [r1, 1]\n"
+ :
+ : "r" (addr), "r" (data), "r" (bytelen)
+ : "r8");
+ return bytelen;
+}
+
+static inline int __raw_readsw(unsigned int addr, void *data, int wordlen)
+{
+ __asm__ __volatile__ ("1:ld.di r8, [r0]\n"
+ "sub.f r2, r2, 1\n"
+ "bnz.d 1b\n"
+ "stw.ab r8, [r1, 2]\n"
+ :
+ : "r" (addr), "r" (data), "r" (wordlen)
+ : "r8");
+ return wordlen;
+}
+
+static inline int __raw_readsl(unsigned int addr, void *data, int longlen)
+{
+ __asm__ __volatile__ ("1:ld.di r8, [r0]\n"
+ "sub.f r2, r2, 1\n"
+ "bnz.d 1b\n"
+ "st.ab r8, [r1, 4]\n"
+ :
+ : "r" (addr), "r" (data), "r" (longlen)
+ : "r8");
+ return longlen;
+}
+
+static inline int __raw_writesb(unsigned int addr, void *data, int bytelen)
+{
+ __asm__ __volatile__ ("1:ldb.ab r8, [r1, 1]\n"
+ "sub.f r2, r2, 1\n"
+ "bnz.d 1b\n"
+ "st.di r8, [r0, 0]\n"
+ :
+ : "r" (addr), "r" (data), "r" (bytelen)
+ : "r8");
+ return bytelen;
+}
+
+static inline int __raw_writesw(unsigned int addr, void *data, int wordlen)
+{
+ __asm__ __volatile__ ("1:ldw.ab r8, [r1, 2]\n"
+ "sub.f r2, r2, 1\n"
+ "bnz.d 1b\n"
+ "st.ab.di r8, [r0, 0]\n"
+ :
+ : "r" (addr), "r" (data), "r" (wordlen)
+ : "r8");
+ return wordlen;
+}
+
+static inline int __raw_writesl(unsigned int addr, void *data, int longlen)
+{
+ __asm__ __volatile__ ("1:ld.ab r8, [r1, 4]\n"
+ "sub.f r2, r2, 1\n"
+ "bnz.d 1b\n"
+ "st.ab.di r8, [r0, 0]\n"
+ :
+ : "r" (addr), "r" (data), "r" (longlen)
+ : "r8");
+ return longlen;
+}
+
+#define out_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v), a)
+#define in_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a))
+
+#define out_le32(a, v) out_arch(l, le32, a, v)
+#define out_le16(a, v) out_arch(w, le16, a, v)
+
+#define in_le32(a) in_arch(l, le32, a)
+#define in_le16(a) in_arch(w, le16, a)
+
+#define out_be32(a, v) out_arch(l, be32, a, v)
+#define out_be16(a, v) out_arch(w, be16, a, v)
+
+#define in_be32(a) in_arch(l, be32, a)
+#define in_be16(a) in_arch(w, be16, a)
+
+#define out_8(a, v) __raw_writeb(v, a)
+#define in_8(a) __raw_readb(a)
+
+/*
+ * Clear and set bits in one shot. These macros can be used to clear and
+ * set multiple bits in a register using a single call. These macros can
+ * also be used to set a multiple-bit bit pattern using a mask, by
+ * specifying the mask in the 'clear' parameter and the new bit pattern
+ * in the 'set' parameter.
+ */
+
+#define clrbits(type, addr, clear) \
+ out_##type((addr), in_##type(addr) & ~(clear))
+
+#define setbits(type, addr, set) \
+ out_##type((addr), in_##type(addr) | (set))
+
+#define clrsetbits(type, addr, clear, set) \
+ out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
+
+#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
+#define setbits_be32(addr, set) setbits(be32, addr, set)
+#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
+
+#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
+#define setbits_le32(addr, set) setbits(le32, addr, set)
+#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
+
+#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
+#define setbits_be16(addr, set) setbits(be16, addr, set)
+#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
+
+#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
+#define setbits_le16(addr, set) setbits(le16, addr, set)
+#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
+
+#define clrbits_8(addr, clear) clrbits(8, addr, clear)
+#define setbits_8(addr, set) setbits(8, addr, set)
+#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
+
+#endif /* __ASM_ARC_IO_H */
--- /dev/null
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_POSIX_TYPES_H
+#define __ASM_ARC_POSIX_TYPES_H
+
+typedef unsigned short __kernel_dev_t;
+typedef unsigned long __kernel_ino_t;
+typedef unsigned short __kernel_mode_t;
+typedef unsigned short __kernel_nlink_t;
+typedef long __kernel_off_t;
+typedef int __kernel_pid_t;
+typedef unsigned short __kernel_ipc_pid_t;
+typedef unsigned short __kernel_uid_t;
+typedef unsigned short __kernel_gid_t;
+typedef unsigned int __kernel_size_t;
+typedef int __kernel_ssize_t;
+typedef int __kernel_ptrdiff_t;
+typedef long __kernel_time_t;
+typedef long __kernel_suseconds_t;
+typedef long __kernel_clock_t;
+typedef int __kernel_daddr_t;
+typedef char *__kernel_caddr_t;
+typedef unsigned short __kernel_uid16_t;
+typedef unsigned short __kernel_gid16_t;
+typedef unsigned int __kernel_uid32_t;
+typedef unsigned int __kernel_gid32_t;
+
+typedef unsigned short __kernel_old_uid_t;
+typedef unsigned short __kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long __kernel_loff_t;
+#endif
+
+#endif /* __ASM_ARC_POSIX_TYPES_H */
--- /dev/null
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_PTRACE_H
+#define __ASM_ARC_PTRACE_H
+
+struct pt_regs {
+ long bta;
+ long lp_start;
+ long lp_end;
+ long lp_count;
+ long status32;
+ long ret;
+ long blink;
+ long fp;
+ long r26; /* gp */
+ long r25;
+ long r24;
+ long r23;
+ long r22;
+ long r21;
+ long r20;
+ long r19;
+ long r18;
+ long r17;
+ long r16;
+ long r15;
+ long r14;
+ long r13;
+ long r12;
+ long r11;
+ long r10;
+ long r9;
+ long r8;
+ long r7;
+ long r6;
+ long r5;
+ long r4;
+ long r3;
+ long r2;
+ long r1;
+ long r0;
+ long sp;
+ long ecr;
+};
+
+#endif /* __ASM_ARC_PTRACE_H */
--- /dev/null
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_SECTIONS_H
+#define __ASM_ARC_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+extern ulong __text_end;
+
+#endif /* __ASM_ARC_SECTIONS_H */
--- /dev/null
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_STRING_H
+#define __ASM_ARC_STRING_H
+
+#define __HAVE_ARCH_MEMSET
+#define __HAVE_ARCH_MEMCPY
+#define __HAVE_ARCH_MEMCMP
+#define __HAVE_ARCH_STRCHR
+#define __HAVE_ARCH_STRCPY
+#define __HAVE_ARCH_STRCMP
+#define __HAVE_ARCH_STRLEN
+
+extern void *memset(void *ptr, int, __kernel_size_t);
+extern void *memcpy(void *, const void *, __kernel_size_t);
+extern void memzero(void *ptr, __kernel_size_t n);
+extern int memcmp(const void *, const void *, __kernel_size_t);
+extern char *strchr(const char *s, int c);
+extern char *strcpy(char *dest, const char *src);
+extern int strcmp(const char *cs, const char *ct);
+extern __kernel_size_t strlen(const char *);
+
+#endif /* __ASM_ARC_STRING_H */
--- /dev/null
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_TYPES_H
+#define __ASM_ARC_TYPES_H
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+#define BITS_PER_LONG 32
+
+/* Dma addresses are 32-bits wide. */
+
+typedef u32 dma_addr_t;
+
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+
+#endif /* __ASM_ARC_TYPES_H */
--- /dev/null
+/*
+ * Copyright (C) 2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_U_BOOT_ARC_H__
+#define __ASM_ARC_U_BOOT_ARC_H__
+
+int arch_early_init_r(void);
+
+#endif /* __ASM_ARC_U_BOOT_ARC_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_U_BOOT_H__
+#define __ASM_ARC_U_BOOT_H__
+
+#include <asm-generic/u-boot.h>
+
+/* For image.h:image_check_target_arch() */
+#define IH_ARCH_DEFAULT IH_ARCH_ARC
+
+#endif /* __ASM_ARC_U_BOOT_H__ */
--- /dev/null
+#include <asm-generic/unaligned.h>
--- /dev/null
+#
+# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += sections.o
+obj-y += relocate.o
+obj-y += strchr-700.o
+obj-y += strcmp.o
+obj-y += strcpy-700.o
+obj-y += strlen.o
+obj-y += memcmp.o
+obj-y += memcpy-700.o
+obj-y += memset.o
+obj-$(CONFIG_CMD_BOOTM) += bootm.o
--- /dev/null
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static ulong get_sp(void)
+{
+ ulong ret;
+
+ asm("mov %0, sp" : "=r"(ret) : );
+ return ret;
+}
+
+void arch_lmb_reserve(struct lmb *lmb)
+{
+ ulong sp;
+
+ /*
+ * Booting a (Linux) kernel image
+ *
+ * Allocate space for command line and board info - the
+ * address should be as high as possible within the reach of
+ * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused
+ * memory, which means far enough below the current stack
+ * pointer.
+ */
+ sp = get_sp();
+ debug("## Current stack ends at 0x%08lx ", sp);
+
+ /* adjust sp by 4K to be safe */
+ sp -= 4096;
+ lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + gd->ram_size - sp));
+}
+
+static int cleanup_before_linux(void)
+{
+ disable_interrupts();
+ flush_dcache_all();
+ invalidate_icache_all();
+
+ return 0;
+}
+
+/* Subcommand: PREP */
+static void boot_prep_linux(bootm_headers_t *images)
+{
+ if (image_setup_linux(images))
+ hang();
+}
+
+/* Subcommand: GO */
+static void boot_jump_linux(bootm_headers_t *images, int flag)
+{
+ void (*kernel_entry)(int zero, int arch, uint params);
+ unsigned int r0, r2;
+ int fake = (flag & BOOTM_STATE_OS_FAKE_GO);
+
+ kernel_entry = (void (*)(int, int, uint))images->ep;
+
+ debug("## Transferring control to Linux (at address %08lx)...\n",
+ (ulong) kernel_entry);
+ bootstage_mark(BOOTSTAGE_ID_RUN_OS);
+
+ printf("\nStarting kernel ...%s\n\n", fake ?
+ "(fake run for tracing)" : "");
+ bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
+
+ cleanup_before_linux();
+
+ if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
+ r0 = 2;
+ r2 = (unsigned int)images->ft_addr;
+ } else {
+ r0 = 1;
+ r2 = (unsigned int)getenv("bootargs");
+ }
+
+ if (!fake)
+ kernel_entry(r0, 0, r2);
+}
+
+int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
+{
+ /* No need for those on ARC */
+ if ((flag & BOOTM_STATE_OS_BD_T) || (flag & BOOTM_STATE_OS_CMDLINE))
+ return -1;
+
+ if (flag & BOOTM_STATE_OS_PREP) {
+ boot_prep_linux(images);
+ return 0;
+ }
+
+ if (flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO)) {
+ boot_jump_linux(images, flag);
+ return 0;
+ }
+
+ boot_prep_linux(images);
+ boot_jump_linux(images, flag);
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifdef __LITTLE_ENDIAN__
+#define WORD2 r2
+#define SHIFT r3
+#else /* __BIG_ENDIAN__ */
+#define WORD2 r3
+#define SHIFT r2
+#endif /* _ENDIAN__ */
+
+.global memcmp
+.align 4
+memcmp:
+ or %r12, %r0, %r1
+ asl_s %r12, %r12, 30
+ sub %r3, %r2, 1
+ brls %r2, %r12, .Lbytewise
+ ld %r4, [%r0, 0]
+ ld %r5, [%r1, 0]
+ lsr.f %lp_count, %r3, 3
+ lpne .Loop_end
+ ld_s WORD2, [%r0, 4]
+ ld_s %r12, [%r1, 4]
+ brne %r4, %r5, .Leven
+ ld.a %r4, [%r0, 8]
+ ld.a %r5, [%r1, 8]
+ brne WORD2, %r12, .Lodd
+.Loop_end:
+ asl_s SHIFT, SHIFT, 3
+ bhs_s .Last_cmp
+ brne %r4, %r5, .Leven
+ ld %r4, [%r0, 4]
+ ld %r5, [%r1, 4]
+#ifdef __LITTLE_ENDIAN__
+ nop_s
+ /* one more load latency cycle */
+.Last_cmp:
+ xor %r0, %r4, %r5
+ bset %r0, %r0, SHIFT
+ sub_s %r1, %r0, 1
+ bic_s %r1, %r1, %r0
+ norm %r1, %r1
+ b.d .Leven_cmp
+ and %r1, %r1, 24
+.Leven:
+ xor %r0, %r4, %r5
+ sub_s %r1, %r0, 1
+ bic_s %r1, %r1, %r0
+ norm %r1, %r1
+ /* slow track insn */
+ and %r1, %r1, 24
+.Leven_cmp:
+ asl %r2, %r4, %r1
+ asl %r12, %r5, %r1
+ lsr_s %r2, %r2, 1
+ lsr_s %r12, %r12, 1
+ j_s.d [%blink]
+ sub %r0, %r2, %r12
+ .balign 4
+.Lodd:
+ xor %r0, WORD2, %r12
+ sub_s %r1, %r0, 1
+ bic_s %r1, %r1, %r0
+ norm %r1, %r1
+ /* slow track insn */
+ and %r1, %r1, 24
+ asl_s %r2, %r2, %r1
+ asl_s %r12, %r12, %r1
+ lsr_s %r2, %r2, 1
+ lsr_s %r12, %r12, 1
+ j_s.d [%blink]
+ sub %r0, %r2, %r12
+#else /* __BIG_ENDIAN__ */
+.Last_cmp:
+ neg_s SHIFT, SHIFT
+ lsr %r4, %r4, SHIFT
+ lsr %r5, %r5, SHIFT
+ /* slow track insn */
+.Leven:
+ sub.f %r0, %r4, %r5
+ mov.ne %r0, 1
+ j_s.d [%blink]
+ bset.cs %r0, %r0, 31
+.Lodd:
+ cmp_s WORD2, %r12
+
+ mov_s %r0, 1
+ j_s.d [%blink]
+ bset.cs %r0, %r0, 31
+#endif /* _ENDIAN__ */
+ .balign 4
+.Lbytewise:
+ breq %r2, 0, .Lnil
+ ldb %r4, [%r0, 0]
+ ldb %r5, [%r1, 0]
+ lsr.f %lp_count, %r3
+ lpne .Lbyte_end
+ ldb_s %r3, [%r0, 1]
+ ldb %r12, [%r1, 1]
+ brne %r4, %r5, .Lbyte_even
+ ldb.a %r4, [%r0, 2]
+ ldb.a %r5, [%r1, 2]
+ brne %r3, %r12, .Lbyte_odd
+.Lbyte_end:
+ bcc .Lbyte_even
+ brne %r4, %r5, .Lbyte_even
+ ldb_s %r3, [%r0, 1]
+ ldb_s %r12, [%r1, 1]
+.Lbyte_odd:
+ j_s.d [%blink]
+ sub %r0, %r3, %r12
+.Lbyte_even:
+ j_s.d [%blink]
+ sub %r0, %r4, %r5
+.Lnil:
+ j_s.d [%blink]
+ mov %r0, 0
--- /dev/null
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+.global memcpy
+.align 4
+memcpy:
+ or %r3, %r0, %r1
+ asl_s %r3, %r3, 30
+ mov_s %r5, %r0
+ brls.d %r2, %r3, .Lcopy_bytewise
+ sub.f %r3, %r2, 1
+ ld_s %r12, [%r1, 0]
+ asr.f %lp_count, %r3, 3
+ bbit0.d %r3, 2, .Lnox4
+ bmsk_s %r2, %r2, 1
+ st.ab %r12, [%r5, 4]
+ ld.a %r12, [%r1, 4]
+.Lnox4:
+ lppnz .Lendloop
+ ld_s %r3, [%r1, 4]
+ st.ab %r12, [%r5, 4]
+ ld.a %r12, [%r1, 8]
+ st.ab %r3, [%r5, 4]
+.Lendloop:
+ breq %r2, 0, .Last_store
+ ld %r3, [%r5, 0]
+#ifdef __LITTLE_ENDIAN__
+ add3 %r2, -1, %r2
+ /* uses long immediate */
+ xor_s %r12, %r12, %r3
+ bmsk %r12, %r12, %r2
+ xor_s %r12, %r12, %r3
+#else /* __BIG_ENDIAN__ */
+ sub3 %r2, 31, %r2
+ /* uses long immediate */
+ xor_s %r3, %r3, %r12
+ bmsk %r3, %r3, %r2
+ xor_s %r12, %r12, %r3
+#endif /* _ENDIAN__ */
+.Last_store:
+ j_s.d [%blink]
+ st %r12, [%r5, 0]
+
+ .balign 4
+.Lcopy_bytewise:
+ jcs [%blink]
+ ldb_s %r12, [%r1, 0]
+ lsr.f %lp_count, %r3
+ bhs_s .Lnox1
+ stb.ab %r12, [%r5, 1]
+ ldb.a %r12, [%r1, 1]
+.Lnox1:
+ lppnz .Lendbloop
+ ldb_s %r3, [%r1, 1]
+ stb.ab %r12, [%r5, 1]
+ ldb.a %r12, [%r1, 2]
+ stb.ab %r3, [%r5, 1]
+.Lendbloop:
+ j_s.d [%blink]
+ stb %r12, [%r5, 0]
--- /dev/null
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define SMALL 7 /* Must be at least 6 to deal with alignment/loop issues. */
+
+.global memset
+.align 4
+memset:
+ mov_s %r4, %r0
+ or %r12, %r0, %r2
+ bmsk.f %r12, %r12, 1
+ extb_s %r1, %r1
+ asl %r3, %r1, 8
+ beq.d .Laligned
+ or_s %r1, %r1, %r3
+ brls %r2, SMALL, .Ltiny
+ add %r3, %r2, %r0
+ stb %r1, [%r3, -1]
+ bclr_s %r3, %r3, 0
+ stw %r1, [%r3, -2]
+ bmsk.f %r12, %r0, 1
+ add_s %r2, %r2, %r12
+ sub.ne %r2, %r2, 4
+ stb.ab %r1, [%r4, 1]
+ and %r4, %r4, -2
+ stw.ab %r1, [%r4, 2]
+ and %r4, %r4, -4
+
+ .balign 4
+.Laligned:
+ asl %r3, %r1, 16
+ lsr.f %lp_count, %r2, 2
+ or_s %r1, %r1, %r3
+ lpne .Loop_end
+ st.ab %r1, [%r4, 4]
+.Loop_end:
+ j_s [%blink]
+
+ .balign 4
+.Ltiny:
+ mov.f %lp_count, %r2
+ lpne .Ltiny_end
+ stb.ab %r1, [%r4, 1]
+.Ltiny_end:
+ j_s [%blink]
+
+/*
+ * memzero: @r0 = mem, @r1 = size_t
+ * memset: @r0 = mem, @r1 = char, @r2 = size_t
+ */
+
+.global memzero
+.align 4
+memzero:
+ /* adjust bzero args to memset args */
+ mov %r2, %r1
+ mov %r1, 0
+ /* tail call so need to tinker with blink */
+ b memset
--- /dev/null
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <elf.h>
+#include <asm/sections.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Base functionality is taken from x86 version with added ARC-specifics
+ */
+int do_elf_reloc_fixups(void)
+{
+ Elf32_Rela *re_src = (Elf32_Rela *)(&__rel_dyn_start);
+ Elf32_Rela *re_end = (Elf32_Rela *)(&__rel_dyn_end);
+
+ Elf32_Addr *offset_ptr_rom, *last_offset = NULL;
+ Elf32_Addr *offset_ptr_ram;
+
+ do {
+ /* Get the location from the relocation entry */
+ offset_ptr_rom = (Elf32_Addr *)re_src->r_offset;
+
+ /* Check that the location of the relocation is in .text */
+ if (offset_ptr_rom >= (Elf32_Addr *)CONFIG_SYS_TEXT_BASE &&
+ offset_ptr_rom > last_offset) {
+ unsigned int val;
+ /* Switch to the in-RAM version */
+ offset_ptr_ram = (Elf32_Addr *)((ulong)offset_ptr_rom +
+ gd->reloc_off);
+
+ /*
+ * Use "memcpy" because target location might be
+ * 16-bit aligned on ARC so we may need to read
+ * byte-by-byte. On attempt to read entire word by
+ * CPU throws an exception
+ */
+ memcpy(&val, offset_ptr_ram, sizeof(int));
+
+#ifdef __LITTLE_ENDIAN__
+ /* If location in ".text" section swap value */
+ if ((unsigned int)offset_ptr_rom <
+ (unsigned int)&__text_end)
+ val = (val << 16) | (val >> 16);
+#endif
+
+ /* Check that the target points into .text */
+ if (val >= CONFIG_SYS_TEXT_BASE && val <=
+ (unsigned int)&__bss_end) {
+ val += gd->reloc_off;
+#ifdef __LITTLE_ENDIAN__
+ /* If location in ".text" section swap value */
+ if ((unsigned int)offset_ptr_rom <
+ (unsigned int)&__text_end)
+ val = (val << 16) | (val >> 16);
+#endif
+ memcpy(offset_ptr_ram, &val, sizeof(int));
+ } else {
+ debug(" %p: rom reloc %x, ram %p, value %x, limit %x\n",
+ re_src, re_src->r_offset, offset_ptr_ram,
+ val, (unsigned int)&__bss_end);
+ }
+ } else {
+ debug(" %p: rom reloc %x, last %p\n", re_src,
+ re_src->r_offset, last_offset);
+ }
+ last_offset = offset_ptr_rom;
+
+ } while (++re_src < re_end);
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * For some reason linker sets linker-generated symbols to zero in PIE mode.
+ * A work-around is substitution of linker-generated symbols with
+ * compiler-generated symbols which are properly handled by linker in PAE mode.
+ */
+
+char __bss_start[0] __attribute__((section(".__bss_start")));
+char __bss_end[0] __attribute__((section(".__bss_end")));
+char __image_copy_start[0] __attribute__((section(".__image_copy_start")));
+char __image_copy_end[0] __attribute__((section(".__image_copy_end")));
+char __rel_dyn_start[0] __attribute__((section(".__rel_dyn_start")));
+char __rel_dyn_end[0] __attribute__((section(".__rel_dyn_end")));
+char __text_start[0] __attribute__((section(".__text_start")));
+char __text_end[0] __attribute__((section(".__text_end")));
+char __init_end[0] __attribute__((section(".__init_end")));
--- /dev/null
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * ARC700 has a relatively long pipeline and branch prediction, so we want
+ * to avoid branches that are hard to predict. On the other hand, the
+ * presence of the norm instruction makes it easier to operate on whole
+ * words branch-free.
+ */
+
+.global strchr
+.align 4
+strchr:
+ extb_s %r1, %r1
+ asl %r5, %r1, 8
+ bmsk %r2, %r0, 1
+ or %r5, %r5, %r1
+ mov_s %r3, 0x01010101
+ breq.d %r2, %r0, .Laligned
+ asl %r4, %r5, 16
+ sub_s %r0, %r0, %r2
+ asl %r7, %r2, 3
+ ld_s %r2, [%r0]
+#ifdef __LITTLE_ENDIAN__
+ asl %r7, %r3, %r7
+#else /* __BIG_ENDIAN__ */
+ lsr %r7, %r3, %r7
+#endif /* _ENDIAN__ */
+ or %r5, %r5, %r4
+ ror %r4, %r3
+ sub %r12, %r2, %r7
+ bic_s %r12, %r12, %r2
+ and %r12, %r12, %r4
+ brne.d %r12, 0, .Lfound0_ua
+ xor %r6, %r2, %r5
+ ld.a %r2, [%r0, 4]
+ sub %r12, %r6, %r7
+ bic %r12, %r12, %r6
+#ifdef __LITTLE_ENDIAN__
+ and %r7, %r12, %r4
+ /* For speed, we want this branch to be unaligned. */
+ breq %r7, 0, .Loop
+ /* Likewise this one */
+ b .Lfound_char
+#else /* __BIG_ENDIAN__ */
+ and %r12, %r12, %r4
+ /* For speed, we want this branch to be unaligned. */
+ breq %r12, 0, .Loop
+ lsr_s %r12, %r12, 7
+ bic %r2, %r7, %r6
+ b.d .Lfound_char_b
+ and_s %r2, %r2, %r12
+#endif /* _ENDIAN__ */
+ /* We require this code address to be unaligned for speed... */
+.Laligned:
+ ld_s %r2, [%r0]
+ or %r5, %r5, %r4
+ ror %r4, %r3
+ /* ... so that this code address is aligned, for itself and ... */
+.Loop:
+ sub %r12, %r2, %r3
+ bic_s %r12, %r12, %r2
+ and %r12, %r12, %r4
+ brne.d %r12, 0, .Lfound0
+ xor %r6, %r2, %r5
+ ld.a %r2, [%r0, 4]
+ sub %r12, %r6, %r3
+ bic %r12, %r12, %r6
+ and %r7, %r12, %r4
+ breq %r7, 0, .Loop
+ /*
+ *... so that this branch is unaligned.
+ * Found searched-for character.
+ * r0 has already advanced to next word.
+ */
+#ifdef __LITTLE_ENDIAN__
+ /*
+ * We only need the information about the first matching byte
+ * (i.e. the least significant matching byte) to be exact,
+ * hence there is no problem with carry effects.
+ */
+.Lfound_char:
+ sub %r3, %r7, 1
+ bic %r3, %r3, %r7
+ norm %r2, %r3
+ sub_s %r0, %r0, 1
+ asr_s %r2, %r2, 3
+ j.d [%blink]
+ sub_s %r0, %r0, %r2
+
+ .balign 4
+.Lfound0_ua:
+ mov %r3, %r7
+.Lfound0:
+ sub %r3, %r6, %r3
+ bic %r3, %r3, %r6
+ and %r2, %r3, %r4
+ or_s %r12, %r12, %r2
+ sub_s %r3, %r12, 1
+ bic_s %r3, %r3, %r12
+ norm %r3, %r3
+ add_s %r0, %r0, 3
+ asr_s %r12, %r3, 3
+ asl.f 0, %r2, %r3
+ sub_s %r0, %r0, %r12
+ j_s.d [%blink]
+ mov.pl %r0, 0
+#else /* __BIG_ENDIAN__ */
+.Lfound_char:
+ lsr %r7, %r7, 7
+
+ bic %r2, %r7, %r6
+.Lfound_char_b:
+ norm %r2, %r2
+ sub_s %r0, %r0, 4
+ asr_s %r2, %r2, 3
+ j.d [%blink]
+ add_s %r0, %r0, %r2
+
+.Lfound0_ua:
+ mov_s %r3, %r7
+.Lfound0:
+ asl_s %r2, %r2, 7
+ or %r7, %r6, %r4
+ bic_s %r12, %r12, %r2
+ sub %r2, %r7, %r3
+ or %r2, %r2, %r6
+ bic %r12, %r2, %r12
+ bic.f %r3, %r4, %r12
+ norm %r3, %r3
+
+ add.pl %r3, %r3, 1
+ asr_s %r12, %r3, 3
+ asl.f 0, %r2, %r3
+ add_s %r0, %r0, %r12
+ j_s.d [%blink]
+ mov.mi %r0, 0
+#endif /* _ENDIAN__ */
--- /dev/null
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * This is optimized primarily for the ARC700.
+ * It would be possible to speed up the loops by one cycle / word
+ * respective one cycle / byte by forcing double source 1 alignment, unrolling
+ * by a factor of two, and speculatively loading the second word / byte of
+ * source 1; however, that would increase the overhead for loop setup / finish,
+ * and strcmp might often terminate early.
+ */
+
+.global strcmp
+.align 4
+strcmp:
+ or %r2, %r0, %r1
+ bmsk_s %r2, %r2, 1
+ brne %r2, 0, .Lcharloop
+ mov_s %r12, 0x01010101
+ ror %r5, %r12
+.Lwordloop:
+ ld.ab %r2, [%r0, 4]
+ ld.ab %r3, [%r1, 4]
+ nop_s
+ sub %r4, %r2, %r12
+ bic %r4, %r4, %r2
+ and %r4, %r4, %r5
+ brne %r4, 0, .Lfound0
+ breq %r2 ,%r3, .Lwordloop
+#ifdef __LITTLE_ENDIAN__
+ xor %r0, %r2, %r3 /* mask for difference */
+ sub_s %r1, %r0, 1
+ bic_s %r0, %r0, %r1 /* mask for least significant difference bit */
+ sub %r1, %r5, %r0
+ xor %r0, %r5, %r1 /* mask for least significant difference byte */
+ and_s %r2, %r2, %r0
+ and_s %r3, %r3, %r0
+#endif /* _ENDIAN__ */
+ cmp_s %r2, %r3
+ mov_s %r0, 1
+ j_s.d [%blink]
+ bset.lo %r0, %r0, 31
+
+ .balign 4
+#ifdef __LITTLE_ENDIAN__
+.Lfound0:
+ xor %r0, %r2, %r3 /* mask for difference */
+ or %r0, %r0, %r4 /* or in zero indicator */
+ sub_s %r1, %r0, 1
+ bic_s %r0, %r0, %r1 /* mask for least significant difference bit */
+ sub %r1, %r5, %r0
+ xor %r0, %r5, %r1 /* mask for least significant difference byte */
+ and_s %r2, %r2, %r0
+ and_s %r3, %r3, %r0
+ sub.f %r0, %r2, %r3
+ mov.hi %r0, 1
+ j_s.d [%blink]
+ bset.lo %r0, %r0, 31
+#else /* __BIG_ENDIAN__ */
+ /*
+ * The zero-detection above can mis-detect 0x01 bytes as zeroes
+ * because of carry-propagateion from a lower significant zero byte.
+ * We can compensate for this by checking that bit0 is zero.
+ * This compensation is not necessary in the step where we
+ * get a low estimate for r2, because in any affected bytes
+ * we already have 0x00 or 0x01, which will remain unchanged
+ * when bit 7 is cleared.
+ */
+ .balign 4
+.Lfound0:
+ lsr %r0, %r4, 8
+ lsr_s %r1, %r2
+ bic_s %r2, %r2, %r0 /* get low estimate for r2 and get ... */
+ bic_s %r0, %r0, %r1 /* <this is the adjusted mask for zeros> */
+ or_s %r3, %r3, %r0 /* ... high estimate r3 so that r2 > r3 will */
+ cmp_s %r3, %r2 /* ... be independent of trailing garbage */
+ or_s %r2, %r2, %r0 /* likewise for r3 > r2 */
+ bic_s %r3, %r3, %r0
+ rlc %r0, 0 /* r0 := r2 > r3 ? 1 : 0 */
+ cmp_s %r2, %r3
+ j_s.d [%blink]
+ bset.lo %r0, %r0, 31
+#endif /* _ENDIAN__ */
+
+ .balign 4
+.Lcharloop:
+ ldb.ab %r2,[%r0,1]
+ ldb.ab %r3,[%r1,1]
+ nop_s
+ breq %r2, 0, .Lcmpend
+ breq %r2, %r3, .Lcharloop
+.Lcmpend:
+ j_s.d [%blink]
+ sub %r0, %r2, %r3
--- /dev/null
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * If dst and src are 4 byte aligned, copy 8 bytes at a time.
+ * If the src is 4, but not 8 byte aligned, we first read 4 bytes to get
+ * it 8 byte aligned. Thus, we can do a little read-ahead, without
+ * dereferencing a cache line that we should not touch.
+ * Note that short and long instructions have been scheduled to avoid
+ * branch stalls.
+ * The beq_s to r3z could be made unaligned & long to avoid a stall
+ * there, but it is not likely to be taken often, and it would also be likely
+ * to cost an unaligned mispredict at the next call.
+ */
+
+.global strcpy
+.align 4
+strcpy:
+ or %r2, %r0, %r1
+ bmsk_s %r2, %r2, 1
+ brne.d %r2, 0, charloop
+ mov_s %r10, %r0
+ ld_s %r3, [%r1, 0]
+ mov %r8, 0x01010101
+ bbit0.d %r1, 2, loop_start
+ ror %r12, %r8
+ sub %r2, %r3, %r8
+ bic_s %r2, %r2, %r3
+ tst_s %r2,%r12
+ bne r3z
+ mov_s %r4,%r3
+ .balign 4
+loop:
+ ld.a %r3, [%r1, 4]
+ st.ab %r4, [%r10, 4]
+loop_start:
+ ld.a %r4, [%r1, 4]
+ sub %r2, %r3, %r8
+ bic_s %r2, %r2, %r3
+ tst_s %r2, %r12
+ bne_s r3z
+ st.ab %r3, [%r10, 4]
+ sub %r2, %r4, %r8
+ bic %r2, %r2, %r4
+ tst %r2, %r12
+ beq loop
+ mov_s %r3, %r4
+#ifdef __LITTLE_ENDIAN__
+r3z: bmsk.f %r1, %r3, 7
+ lsr_s %r3, %r3, 8
+#else /* __BIG_ENDIAN__ */
+r3z: lsr.f %r1, %r3, 24
+ asl_s %r3, %r3, 8
+#endif /* _ENDIAN__ */
+ bne.d r3z
+ stb.ab %r1, [%r10, 1]
+ j_s [%blink]
+
+ .balign 4
+charloop:
+ ldb.ab %r3, [%r1, 1]
+ brne.d %r3, 0, charloop
+ stb.ab %r3, [%r10, 1]
+ j [%blink]
--- /dev/null
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+.global strlen
+.align 4
+strlen:
+ or %r3, %r0, 7
+ ld %r2, [%r3, -7]
+ ld.a %r6, [%r3, -3]
+ mov %r4, 0x01010101
+ /* uses long immediate */
+#ifdef __LITTLE_ENDIAN__
+ asl_s %r1, %r0, 3
+ btst_s %r0, 2
+ asl %r7, %r4, %r1
+ ror %r5, %r4
+ sub %r1, %r2, %r7
+ bic_s %r1, %r1, %r2
+ mov.eq %r7, %r4
+ sub %r12, %r6, %r7
+ bic %r12, %r12, %r6
+ or.eq %r12, %r12, %r1
+ and %r12, %r12, %r5
+ brne %r12, 0, .Learly_end
+#else /* __BIG_ENDIAN__ */
+ ror %r5, %r4
+ btst_s %r0, 2
+ mov_s %r1, 31
+ sub3 %r7, %r1, %r0
+ sub %r1, %r2, %r4
+ bic_s %r1, %r1, %r2
+ bmsk %r1, %r1, %r7
+ sub %r12, %r6, %r4
+ bic %r12, %r12, %r6
+ bmsk.ne %r12, %r12, %r7
+ or.eq %r12, %r12, %r1
+ and %r12, %r12, %r5
+ brne %r12, 0, .Learly_end
+#endif /* _ENDIAN__ */
+
+.Loop:
+ ld_s %r2, [%r3, 4]
+ ld.a %r6, [%r3, 8]
+ /* stall for load result */
+ sub %r1, %r2, %r4
+ bic_s %r1, %r1, %r2
+ sub %r12, %r6, %r4
+ bic %r12, %r12, %r6
+ or %r12, %r12, %r1
+ and %r12, %r12, %r5
+ breq %r12, 0, .Loop
+.Lend:
+ and.f %r1, %r1, %r5
+ sub.ne %r3, %r3, 4
+ mov.eq %r1, %r12
+#ifdef __LITTLE_ENDIAN__
+ sub_s %r2, %r1, 1
+ bic_s %r2, %r2, %r1
+ norm %r1, %r2
+ sub_s %r0, %r0, 3
+ lsr_s %r1, %r1, 3
+ sub %r0, %r3, %r0
+ j_s.d [%blink]
+ sub %r0, %r0, %r1
+#else /* __BIG_ENDIAN__ */
+ lsr_s %r1, %r1, 7
+ mov.eq %r2, %r6
+ bic_s %r1, %r1, %r2
+ norm %r1, %r1
+ sub %r0, %r3, %r0
+ lsr_s %r1, %r1, 3
+ j_s.d [%blink]
+ add %r0, %r0, %r1
+#endif /* _ENDIAN */
+.Learly_end:
+ b.d .Lend
+ sub_s.ne %r1, %r1, %r1
# limit ourselves to the sections we want in the .bin.
ifdef CONFIG_ARM64
-OBJCFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn
+OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn
else
-OBJCFLAGS += -j .text -j .rodata -j .hash -j .data -j .got.plt -j .u_boot_list -j .rel.dyn
+OBJCOPYFLAGS += -j .text -j .rodata -j .hash -j .data -j .got.plt -j .u_boot_list -j .rel.dyn
+endif
+
+ifneq ($(CONFIG_IMX_CONFIG),)
+ifdef CONFIG_SPL
+ifndef CONFIG_SPL_BUILD
+ALL-y += SPL
+endif
+else
+ALL-y += u-boot.imx
+endif
endif
# Make ARMv5 to allow more compilers to work, even though its v6.
PLATFORM_CPPFLAGS += -march=armv5
-
-ifneq ($(CONFIG_IMX_CONFIG),)
-ifdef CONFIG_SPL
-ifdef CONFIG_SPL_BUILD
-ALL-y += $(OBJTREE)/SPL
-endif
-else
-ALL-y += $(obj)u-boot.imx
-endif
-endif
*************************************************************************
*/
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
- .word CONFIG_SPL_TEXT_BASE
-#else
- .word CONFIG_SYS_TEXT_BASE
-#endif
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
- .word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
- .word __bss_end - _start
-
-.globl _end_ofs
-_end_ofs:
- .word _end - _start
-
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
#ifdef CONFIG_SPL_BUILD
.align 5
do_hang:
- ldr sp, _TEXT_BASE /* use 32 words about stack */
bl hang /* hang and never return */
#else /* !CONFIG_SPL_BUILD */
.align 5
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
. = ALIGN(4);
__image_copy_end = .;
- _end = .;
+
+ .end :
+ {
+ *(.__end)
+ }
.bss :
{
+++ /dev/null
-#
-# (C) Copyright 2012 Stephen Warren
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# version 2 as published by the Free Software Foundation.
-#
-# This program is distributed in the hope that it will be useful, but
-# WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-
-# Don't attempt to override the target CPU/ABI options;
-# the Raspberry Pi toolchain does the right thing by default.
-PLATFORM_RELFLAGS := $(filter-out -msoft-float,$(PLATFORM_RELFLAGS))
-PLATFORM_CPPFLAGS := $(filter-out -march=armv5t,$(PLATFORM_CPPFLAGS))
*************************************************************************
*/
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
- .word CONFIG_SPL_TEXT_BASE
-#else
- .word CONFIG_SYS_TEXT_BASE
-#endif
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-
-.globl _bss_start_ofs
-_bss_start_ofs:
- .word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
- .word __bss_end - _start
-
-.globl _end_ofs
-_end_ofs:
- .word _end - _start
-
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
*************************************************************************
*/
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
- .word CONFIG_SPL_TEXT_BASE
-#else
- .word CONFIG_SYS_TEXT_BASE
-#endif
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
- .word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
- .word __bss_end - _start
-
-.globl _end_ofs
-_end_ofs:
- .word _end - _start
-
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
/*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
},
+
+ /*
+ * T124: 700 MHz
+ *
+ * Register Field Bits Width
+ * ------------------------------
+ * PLLX_BASE p 23:20 4
+ * PLLX_BASE n 15: 8 8
+ * PLLX_BASE m 7: 0 8
+ */
+ {
+ { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
+ { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
+ { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
+ { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
+ },
};
-void adjust_pllp_out_freqs(void)
+static inline void pllx_set_iddq(void)
{
+#if defined(CONFIG_TEGRA124)
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_PERIPH];
u32 reg;
- /* Set T30 PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
- reg = readl(&pll->pll_out[0]); /* OUTA, contains OUT2 / OUT1 */
- reg |= (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO) | PLLP_OUT2_OVR
- | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO) | PLLP_OUT1_OVR;
- writel(reg, &pll->pll_out[0]);
-
- reg = readl(&pll->pll_out[1]); /* OUTB, contains OUT4 / OUT3 */
- reg |= (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) | PLLP_OUT4_OVR
- | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) | PLLP_OUT3_OVR;
- writel(reg, &pll->pll_out[1]);
+ /* Disable IDDQ */
+ reg = readl(&clkrst->crc_pllx_misc3);
+ reg &= ~PLLX_IDDQ_MASK;
+ writel(reg, &clkrst->crc_pllx_misc3);
+ udelay(2);
+ debug("%s: IDDQ: PLLX IDDQ = 0x%08X\n", __func__,
+ readl(&clkrst->crc_pllx_misc3));
+#endif
}
int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
debug(" pllx_set_rate entry\n");
+ pllx_set_iddq();
+
/* Set BYPASS, m, n and p to PLLX_BASE */
reg = PLL_BYPASS_MASK | (divm << PLL_DIVM_SHIFT);
reg |= ((divn << PLL_DIVN_SHIFT) | (divp << PLL_DIVP_SHIFT));
reg |= (1 << PLL_DCCON_SHIFT);
writel(reg, &pll->pll_misc);
- /* Enable PLLX */
- reg = readl(&pll->pll_base);
- reg |= PLL_ENABLE_MASK;
-
/* Disable BYPASS */
+ reg = readl(&pll->pll_base);
reg &= ~PLL_BYPASS_MASK;
writel(reg, &pll->pll_base);
+ debug("pllx_set_rate: base = 0x%08X\n", reg);
/* Set lock_enable to PLLX_MISC */
reg = readl(&pll->pll_misc);
reg |= PLL_LOCK_ENABLE_MASK;
writel(reg, &pll->pll_misc);
+ debug("pllx_set_rate: misc = 0x%08X\n", reg);
+
+ /* Enable PLLX last, once it's all configured */
+ reg = readl(&pll->pll_base);
+ reg |= PLL_ENABLE_MASK;
+ writel(reg, &pll->pll_base);
+ debug("pllx_set_rate: base final = 0x%08X\n", reg);
return 0;
}
/* set pllx */
sel = &tegra_pll_x_table[chip_sku][osc];
pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
-
- /* adjust PLLP_out1-4 on T3x/T114 */
- if (soc_type >= CHIPID_TEGRA30) {
- debug(" init_pllx: adjusting PLLP out freqs\n");
- adjust_pllp_out_freqs();
- }
}
void enable_cpu_clock(int enable)
void clock_enable_coresight(int enable)
{
u32 rst, src = 2;
- int soc_type;
debug("clock_enable_coresight entry\n");
clock_set_enable(PERIPH_ID_CORESIGHT, enable);
if (enable) {
/*
* Put CoreSight on PLLP_OUT0 and divide it down as per
- * PLLP base frequency based on SoC type (T20/T30/T114).
+ * PLLP base frequency based on SoC type (T20/T30+).
* Clock divider request would setup CSITE clock as 144MHz
* for PLLP base 216MHz and 204MHz for PLLP base 408MHz
*/
-
- soc_type = tegra_get_chip();
- if (soc_type == CHIPID_TEGRA30 || soc_type == CHIPID_TEGRA114)
- src = CLK_DIVIDER(NVBL_PLLP_KHZ, 204000);
- else if (soc_type == CHIPID_TEGRA20)
- src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);
- else
- printf("%s: Unknown SoC type %X!\n",
- __func__, soc_type);
-
+ src = CLK_DIVIDER(NVBL_PLLP_KHZ, CSITE_KHZ);
clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
/* Unlock the CPU CoreSight interfaces */
/*
- * (C) Copyright 2010-2011
+ * (C) Copyright 2010-2014
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
#define IO_STABILIZATION_DELAY (1000)
#if defined(CONFIG_TEGRA20)
-#define NVBL_PLLP_KHZ (216000)
-#elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
-#define NVBL_PLLP_KHZ (408000)
+#define NVBL_PLLP_KHZ 216000
+#define CSITE_KHZ 144000
+#elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) || \
+ defined(CONFIG_TEGRA124)
+#define NVBL_PLLP_KHZ 408000
+#define CSITE_KHZ 204000
#else
#error "Unknown Tegra chip!"
#endif
int tegra_get_sku_info(void);
int tegra_get_chip_sku(void);
void adjust_pllp_out_freqs(void);
+void pmic_enable_cpu_vdd(void);
/*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
/* Wait for PLL-X to lock */
do {
reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
- } while ((reg & (1 << 27)) == 0);
+ } while ((reg & PLL_LOCK_MASK) == 0);
/* Wait until all clocks are stable */
udelay(PLL_STABILIZATION_DELAY);
/* Set active CPU cluster to G */
clrbits_le32(&flow->cluster_control, 1);
- /*
- * Switch system clock to PLLP_OUT4 (108 MHz), AVP will now run
- * at 108 MHz. This is glitch free as only the source is changed, no
- * special precaution needed.
- */
- val = (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
- (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
- (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
- (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
- (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
- writel(val, &clkrst->crc_sclk_brst_pol);
-
writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
debug("Setting up PLLX\n");
debug("t114_init_clocks exit\n");
}
-static int is_partition_powered(u32 mask)
+static bool is_partition_powered(u32 partid)
{
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
u32 reg;
/* Get power gate status */
reg = readl(&pmc->pmc_pwrgate_status);
- return (reg & mask) == mask;
+ return !!(reg & (1 << partid));
}
-static int is_clamp_enabled(u32 mask)
+static bool is_clamp_enabled(u32 partid)
{
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
u32 reg;
- /* Get clamp status. TODO: Add pmc_clamp_status alias to pmc.h */
- reg = readl(&pmc->pmc_pwrgate_timer_on);
- return (reg & mask) == mask;
+ /* Get clamp status. */
+ reg = readl(&pmc->pmc_clamp_status);
+ return !!(reg & (1 << partid));
}
-static void power_partition(u32 status, u32 partid)
+static void power_partition(u32 partid)
{
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
- debug("%s: status = %08X, part ID = %08X\n", __func__, status, partid);
+ debug("%s: part ID = %08X\n", __func__, partid);
/* Is the partition already on? */
- if (!is_partition_powered(status)) {
+ if (!is_partition_powered(partid)) {
/* No, toggle the partition power state (OFF -> ON) */
debug("power_partition, toggling state\n");
- clrbits_le32(&pmc->pmc_pwrgate_toggle, 0x1F);
- setbits_le32(&pmc->pmc_pwrgate_toggle, partid);
- setbits_le32(&pmc->pmc_pwrgate_toggle, START_CP);
+ writel(START_CP | partid, &pmc->pmc_pwrgate_toggle);
/* Wait for the power to come up */
- while (!is_partition_powered(status))
+ while (!is_partition_powered(partid))
;
/* Wait for the clamp status to be cleared */
- while (is_clamp_enabled(status))
+ while (is_clamp_enabled(partid))
;
/* Give I/O signals time to stabilize */
/* We boot to the fast cluster */
debug("powerup_cpus entry: G cluster\n");
/* Power up the fast cluster rail partition */
- power_partition(CRAIL, CRAILID);
+ power_partition(CRAIL);
/* Power up the fast cluster non-CPU partition */
- power_partition(C0NC, C0NCID);
+ power_partition(C0NC);
/* Power up the fast cluster CPU0 partition */
- power_partition(CE0, CE0ID);
+ power_partition(CE0);
}
void start_cpu(u32 reset_vector)
--- /dev/null
+#
+# (C) Copyright 2013-2014
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += cpu.o
--- /dev/null
+#
+# (C) Copyright 2010-2013
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#/
+USE_PRIVATE_LIBGCC = yes
--- /dev/null
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/ahb.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/flow.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/ap.h>
+#include "../tegra-common/cpu.h"
+
+/* Tegra124-specific CPU init code */
+
+static void enable_cpu_power_rail(void)
+{
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+ debug("enable_cpu_power_rail entry\n");
+
+ /* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */
+ pinmux_tristate_disable(PINGRP_PWR_I2C_SCL);
+ pinmux_tristate_disable(PINGRP_PWR_I2C_SDA);
+
+ pmic_enable_cpu_vdd();
+
+ /*
+ * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz),
+ * set it for 5ms as per SysEng (102MHz*5ms = 510000 (7C830h).
+ */
+ writel(0x7C830, &pmc->pmc_cpupwrgood_timer);
+
+ /* Set polarity to 0 (normal) and enable CPUPWRREQ_OE */
+ clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL);
+ setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE);
+}
+
+static void enable_cpu_clocks(void)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 reg;
+
+ debug("enable_cpu_clocks entry\n");
+
+ /* Wait for PLL-X to lock */
+ do {
+ reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
+ debug("%s: PLLX base = 0x%08X\n", __func__, reg);
+ } while ((reg & PLL_LOCK_MASK) == 0);
+
+ debug("%s: PLLX locked, delay for stable clocks\n", __func__);
+ /* Wait until all clocks are stable */
+ udelay(PLL_STABILIZATION_DELAY);
+
+ debug("%s: Setting CCLK_BURST and DIVIDER\n", __func__);
+ writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
+ writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
+
+ debug("%s: Enabling clock to all CPUs\n", __func__);
+ /* Enable the clock to all CPUs */
+ reg = CLR_CPU3_CLK_STP | CLR_CPU2_CLK_STP | CLR_CPU1_CLK_STP |
+ CLR_CPU0_CLK_STP;
+ writel(reg, &clkrst->crc_clk_cpu_cmplx_clr);
+
+ debug("%s: Enabling main CPU complex clocks\n", __func__);
+ /* Always enable the main CPU complex clocks */
+ clock_enable(PERIPH_ID_CPU);
+ clock_enable(PERIPH_ID_CPULP);
+ clock_enable(PERIPH_ID_CPUG);
+
+ debug("%s: Done\n", __func__);
+}
+
+static void remove_cpu_resets(void)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 reg;
+
+ debug("remove_cpu_resets entry\n");
+
+ /* Take the slow and fast partitions out of reset */
+ reg = CLR_NONCPURESET;
+ writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);
+ writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
+
+ /* Clear the SW-controlled reset of the slow cluster */
+ reg = CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 |
+ CLR_L2RESET | CLR_PRESETDBG;
+ writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);
+
+ /* Clear the SW-controlled reset of the fast cluster */
+ reg = CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 |
+ CLR_CPURESET1 | CLR_DBGRESET1 | CLR_CORERESET1 | CLR_CXRESET1 |
+ CLR_CPURESET2 | CLR_DBGRESET2 | CLR_CORERESET2 | CLR_CXRESET2 |
+ CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3 |
+ CLR_L2RESET | CLR_PRESETDBG;
+ writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
+}
+
+/**
+ * The Tegra124 requires some special clock initialization, including setting up
+ * the DVC I2C, turning on MSELECT and selecting the G CPU cluster
+ */
+void tegra124_init_clocks(void)
+{
+ struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 val;
+
+ debug("tegra124_init_clocks entry\n");
+
+ /* Set active CPU cluster to G */
+ clrbits_le32(&flow->cluster_control, 1);
+
+ /* Change the oscillator drive strength */
+ val = readl(&clkrst->crc_osc_ctrl);
+ val &= ~OSC_XOFS_MASK;
+ val |= (OSC_DRIVE_STRENGTH << OSC_XOFS_SHIFT);
+ writel(val, &clkrst->crc_osc_ctrl);
+
+ /* Update same value in PMC_OSC_EDPD_OVER XOFS field for warmboot */
+ val = readl(&pmc->pmc_osc_edpd_over);
+ val &= ~PMC_XOFS_MASK;
+ val |= (OSC_DRIVE_STRENGTH << PMC_XOFS_SHIFT);
+ writel(val, &pmc->pmc_osc_edpd_over);
+
+ /* Set HOLD_CKE_LOW_EN to 1 */
+ setbits_le32(&pmc->pmc_cntrl2, HOLD_CKE_LOW_EN);
+
+ debug("Setting up PLLX\n");
+ init_pllx();
+
+ val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT);
+ writel(val, &clkrst->crc_clk_sys_rate);
+
+ /* Enable clocks to required peripherals. TBD - minimize this list */
+ debug("Enabling clocks\n");
+
+ clock_set_enable(PERIPH_ID_CACHE2, 1);
+ clock_set_enable(PERIPH_ID_GPIO, 1);
+ clock_set_enable(PERIPH_ID_TMR, 1);
+ clock_set_enable(PERIPH_ID_CPU, 1);
+ clock_set_enable(PERIPH_ID_EMC, 1);
+ clock_set_enable(PERIPH_ID_I2C5, 1);
+ clock_set_enable(PERIPH_ID_APBDMA, 1);
+ clock_set_enable(PERIPH_ID_MEM, 1);
+ clock_set_enable(PERIPH_ID_CORESIGHT, 1);
+ clock_set_enable(PERIPH_ID_MSELECT, 1);
+ clock_set_enable(PERIPH_ID_DVFS, 1);
+
+ /*
+ * Set MSELECT clock source as PLLP (00), and ask for a clock
+ * divider that would set the MSELECT clock at 102MHz for a
+ * PLLP base of 408MHz.
+ */
+ clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0,
+ CLK_DIVIDER(NVBL_PLLP_KHZ, 102000));
+
+ /* Give clock time to stabilize */
+ udelay(IO_STABILIZATION_DELAY);
+
+ /* I2C5 (DVC) gets CLK_M and a divisor of 17 */
+ clock_ll_set_source_divisor(PERIPH_ID_I2C5, 3, 16);
+
+ /* Give clock time to stabilize */
+ udelay(IO_STABILIZATION_DELAY);
+
+ /* Take required peripherals out of reset */
+ debug("Taking periphs out of reset\n");
+ reset_set_enable(PERIPH_ID_CACHE2, 0);
+ reset_set_enable(PERIPH_ID_GPIO, 0);
+ reset_set_enable(PERIPH_ID_TMR, 0);
+ reset_set_enable(PERIPH_ID_COP, 0);
+ reset_set_enable(PERIPH_ID_EMC, 0);
+ reset_set_enable(PERIPH_ID_I2C5, 0);
+ reset_set_enable(PERIPH_ID_APBDMA, 0);
+ reset_set_enable(PERIPH_ID_MEM, 0);
+ reset_set_enable(PERIPH_ID_CORESIGHT, 0);
+ reset_set_enable(PERIPH_ID_MSELECT, 0);
+ reset_set_enable(PERIPH_ID_DVFS, 0);
+
+ debug("tegra124_init_clocks exit\n");
+}
+
+static bool is_partition_powered(u32 partid)
+{
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+ u32 reg;
+
+ /* Get power gate status */
+ reg = readl(&pmc->pmc_pwrgate_status);
+ return !!(reg & (1 << partid));
+}
+
+static void power_partition(u32 partid)
+{
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+ debug("%s: part ID = %08X\n", __func__, partid);
+ /* Is the partition already on? */
+ if (!is_partition_powered(partid)) {
+ /* No, toggle the partition power state (OFF -> ON) */
+ debug("power_partition, toggling state\n");
+ writel(START_CP | partid, &pmc->pmc_pwrgate_toggle);
+
+ /* Wait for the power to come up */
+ while (!is_partition_powered(partid))
+ ;
+
+ /* Give I/O signals time to stabilize */
+ udelay(IO_STABILIZATION_DELAY);
+ }
+}
+
+void powerup_cpus(void)
+{
+ debug("powerup_cpus entry\n");
+
+ /* We boot to the fast cluster */
+ debug("powerup_cpus entry: G cluster\n");
+
+ /* Power up the fast cluster rail partition */
+ debug("powerup_cpus: CRAIL\n");
+ power_partition(CRAIL);
+
+ /* Power up the fast cluster non-CPU partition */
+ debug("powerup_cpus: C0NC\n");
+ power_partition(C0NC);
+
+ /* Power up the fast cluster CPU0 partition */
+ debug("powerup_cpus: CE0\n");
+ power_partition(CE0);
+
+ debug("powerup_cpus: done\n");
+}
+
+void start_cpu(u32 reset_vector)
+{
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+ debug("start_cpu entry, reset_vector = %x\n", reset_vector);
+
+ tegra124_init_clocks();
+
+ /* Set power-gating timer multiplier */
+ clrbits_le32(&pmc->pmc_pwrgate_timer_mult, TIMER_MULT_MASK);
+ setbits_le32(&pmc->pmc_pwrgate_timer_mult, MULT_8);
+
+ enable_cpu_power_rail();
+ enable_cpu_clocks();
+ clock_enable_coresight(1);
+ remove_cpu_resets();
+ writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
+ powerup_cpus();
+ debug("start_cpu exit, should continue @ reset_vector\n");
+}
/*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
/* Set active CPU cluster to G */
clrbits_le32(flow->cluster_control, 1 << 0);
- /*
- * Switch system clock to PLLP_OUT4 (108 MHz), AVP will now run
- * at 108 MHz. This is glitch free as only the source is changed, no
- * special precaution needed.
- */
- val = (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
- (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
- (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
- (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
- (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
- writel(val, &clkrst->crc_sclk_brst_pol);
-
writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
val = (0 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) |
.bss : { *(.bss*) }
__bss_end = .;
- _end = .;
+ .end :
+ {
+ *(.__end)
+ }
}
*************************************************************************
*/
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
- .word CONFIG_SPL_TEXT_BASE
-#else
- .word CONFIG_SYS_TEXT_BASE
-#endif
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
- .word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
- .word __bss_end - _start
-
-.globl _end_ofs
-_end_ofs:
- .word _end - _start
-
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
#define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL
#endif
-_TEXT_BASE:
- .word CONFIG_SYS_TEXT_BASE
-
.globl lowlevel_init
.type lowlevel_init,function
lowlevel_init:
- mov r5, pc /* r5 = POS1 + 4 current */
POS1:
+ adr r5, POS1 /* r5 = POS1 run time */
ldr r0, =POS1 /* r0 = POS1 compile */
- ldr r2, _TEXT_BASE
- sub r0, r0, r2 /* r0 = POS1-_TEXT_BASE (POS1 relative) */
sub r5, r5, r0 /* r0 = CONFIG_SYS_TEXT_BASE-1 */
- sub r5, r5, #4 /* r1 = text base - current */
/* memory control configuration 1 */
ldr r0, =SMRDATA
ldr r2, =SMRDATA1
- ldr r1, _TEXT_BASE
- sub r0, r0, r1
- sub r2, r2, r1
add r0, r0, r5
add r2, r2, r5
0:
ldr r0, =SMRDATA1
ldr r2, =SMRDATA2
- ldr r1, _TEXT_BASE
- sub r0, r0, r1
- sub r2, r2, r1
add r0, r0, r5
add r2, r2, r5
2:
#
PLATFORM_CPPFLAGS += -march=armv5te
-
-ifneq ($(CONFIG_IMX_CONFIG),)
-ifdef CONFIG_SPL
-ifdef CONFIG_SPL_BUILD
-ALL-y += $(OBJTREE)/SPL
-endif
-else
-ALL-y += $(obj)u-boot.imx
-endif
-endif
# SPDX-License-Identifier: GPL-2.0+
#
ifndef CONFIG_SPL_BUILD
-ALL-$(CONFIG_SPL_FRAMEWORK) += $(obj)u-boot.ais
+ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.ais
endif
*************************************************************************
*/
-.globl _TEXT_BASE
-_TEXT_BASE:
-#ifdef CONFIG_SPL_TEXT_BASE
- .word CONFIG_SPL_TEXT_BASE
-#else
- .word CONFIG_SYS_TEXT_BASE
-#endif
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
- .word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
- .word __bss_end - _start
-
-.globl _end_ofs
-_end_ofs:
- .word _end - _start
-
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
bx lr
_hang:
- ldr sp, _TEXT_BASE /* switch to abort stack */
1:
bl 1b /* hang and never return */
__bss_end = .;
}
- _end = .;
+ .end :
+ {
+ *(.__end)
+ }
+
+ _image_binary_end = .;
- .dynsym _end : { *(.dynsym) }
+ .dynsym _image_binary_end : { *(.dynsym) }
.dynbss : { *(.dynbss) }
.dynstr : { *(.dynstr*) }
.dynamic : { *(.dynamic*) }
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y = timer.o cpuinfo.o
+obj-y = timer.o
+obj-$(CONFIG_DISPLAY_CPUINFO) += cpuinfo.o
obj-y += reset.o
#include <command.h>
#include <linux/compiler.h>
-#if defined(CONFIG_DISPLAY_CPUINFO) && defined(CONFIG_OMAP)
+#if defined(CONFIG_OMAP)
#define omap_readw(x) *(volatile unsigned short *)(x)
#define omap_readl(x) *(volatile unsigned long *)(x)
return 0;
}
-#endif /* #if defined(CONFIG_DISPLAY_CPUINFO) && defined(CONFIG_OMAP) */
+#endif /* #if defined(CONFIG_OMAP) */
__bss_end = .;
}
- _end = .;
+ .end :
+ {
+ *(.__end)
+ }
+
+ _image_binary_end = .;
- .dynsym _end : { *(.dynsym) }
+ .dynsym _image_binary_end : { *(.dynsym) }
.dynbss : { *(.dynbss) }
.dynstr : { *(.dynstr*) }
.dynamic : { *(.dynamic*) }
*************************************************************************
*/
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
- .word CONFIG_SPL_TEXT_BASE
-#else
- .word CONFIG_SYS_TEXT_BASE
-#endif
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
- .word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
- .word __bss_end - _start
-
-.globl _end_ofs
-_end_ofs:
- .word _end - _start
-
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
#ifdef CONFIG_SPL_BUILD
.align 5
do_hang:
- ldr sp, _TEXT_BASE /* switch to abort stack */
1:
bl 1b /* hang and never return */
#else /* !CONFIG_SPL_BUILD */
*************************************************************************
*/
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
- .word CONFIG_SPL_TEXT_BASE
-#else
- .word CONFIG_SYS_TEXT_BASE
-#endif
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
- .word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
- .word __bss_end - _start
-
-.globl _end_ofs
-_end_ofs:
- .word _end - _start
-
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
*************************************************************************
*/
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
- .word CONFIG_SPL_TEXT_BASE
-#else
- .word CONFIG_SYS_TEXT_BASE
-#endif
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
- .word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
- .word __bss_end - _start
-
-.globl _end_ofs
-_end_ofs:
- .word _end - _start
-
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
obj-y += virt-v7.o
endif
+obj-$(CONFIG_KONA) += kona-common/
obj-$(CONFIG_OMAP_COMMON) += omap-common/
obj-$(CONFIG_TEGRA) += tegra-common/
DECLARE_GLOBAL_DATA_PTR;
-static const struct gpio_bank gpio_bank_am33xx[4] = {
+static const struct gpio_bank gpio_bank_am33xx[] = {
{ (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
{ (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
{ (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
{ (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
+#ifdef CONFIG_AM43XX
+ { (void *)AM33XX_GPIO4_BASE, METHOD_GPIO_24XX },
+ { (void *)AM33XX_GPIO5_BASE, METHOD_GPIO_24XX },
+#endif
};
const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
&cmper->gpio1clkctrl,
&cmper->gpio2clkctrl,
&cmper->gpio3clkctrl,
+ &cmper->gpio4clkctrl,
+ &cmper->gpio5clkctrl,
&cmper->i2c1clkctrl,
+ &cmper->cpgmac0clkctrl,
&cmper->emiffwclkctrl,
&cmper->emifclkctrl,
&cmper->otfaemifclkctrl,
+ &cmper->qspiclkctrl,
0
};
static u32 pll_sigma_delta_val(u32 clkout_dco)
{
u32 sig_val = 0;
- float frac_div;
- frac_div = (float) clkout_dco / 250;
- frac_div = frac_div + 0.90;
- sig_val = (int)frac_div;
+ sig_val = (clkout_dco + 225) / 250;
sig_val = sig_val << 24;
return sig_val;
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_SPL_BUILD
-ALL-y += $(OBJTREE)/MLO
-ALL-$(CONFIG_SPL_SPI_SUPPORT) += $(OBJTREE)/MLO.byteswap
+ALL-y += MLO
+ALL-$(CONFIG_SPL_SPI_SUPPORT) += MLO.byteswap
else
-ALL-y += $(obj)u-boot.img
+ALL-y += u-boot.img
endif
*/
void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
{
- writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
- writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
+ writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
+ writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
writel(0x1, &emif_reg[nr]->emif_iodft_tlgc);
writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
+ writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) {
configure_mr(nr, 0);
writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
while ((readl(&cm_device->cm_dll_ctrl) && CM_DLL_READYST) == 0)
;
- writel(0x0, &ddrctrl->ddrioctrl);
+ writel(0x80000000, &ddrctrl->ddrioctrl);
config_io_ctrl(ioregs);
. = ALIGN(4);
__image_copy_end = .;
- _end = .;
+
+ .end :
+ {
+ *(.__end)
+ } >.sram
.bss :
{
--- /dev/null
+#
+# Copyright 2013 Broadcom Corporation.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += reset.o
+obj-y += clk-core.o
+obj-y += clk-bcm281xx.o
+obj-y += clk-sdio.o
+obj-y += clk-bsc.o
--- /dev/null
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ *
+ * bcm281xx-specific clock tables
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+#define CLOCK_1K 1000
+#define CLOCK_1M (CLOCK_1K * 1000)
+
+/* declare a reference clock */
+#define DECLARE_REF_CLK(clk_name, clk_parent, clk_rate, clk_div) \
+static struct refclk clk_name = { \
+ .clk = { \
+ .name = #clk_name, \
+ .parent = clk_parent, \
+ .rate = clk_rate, \
+ .div = clk_div, \
+ .ops = &ref_clk_ops, \
+ }, \
+}
+
+/*
+ * Reference clocks
+ */
+
+/* Declare a list of reference clocks */
+DECLARE_REF_CLK(ref_crystal, 0, 26 * CLOCK_1M, 1);
+DECLARE_REF_CLK(var_96m, 0, 96 * CLOCK_1M, 1);
+DECLARE_REF_CLK(ref_96m, 0, 96 * CLOCK_1M, 1);
+DECLARE_REF_CLK(ref_312m, 0, 312 * CLOCK_1M, 0);
+DECLARE_REF_CLK(ref_104m, &ref_312m.clk, 104 * CLOCK_1M, 3);
+DECLARE_REF_CLK(ref_52m, &ref_104m.clk, 52 * CLOCK_1M, 2);
+DECLARE_REF_CLK(ref_13m, &ref_52m.clk, 13 * CLOCK_1M, 4);
+DECLARE_REF_CLK(var_312m, 0, 312 * CLOCK_1M, 0);
+DECLARE_REF_CLK(var_104m, &var_312m.clk, 104 * CLOCK_1M, 3);
+DECLARE_REF_CLK(var_52m, &var_104m.clk, 52 * CLOCK_1M, 2);
+DECLARE_REF_CLK(var_13m, &var_52m.clk, 13 * CLOCK_1M, 4);
+
+struct refclk_lkup {
+ struct refclk *procclk;
+ const char *name;
+};
+
+/* Lookup table for string to clk tranlation */
+#define MKSTR(x) {&x, #x}
+static struct refclk_lkup refclk_str_tbl[] = {
+ MKSTR(ref_crystal), MKSTR(var_96m), MKSTR(ref_96m),
+ MKSTR(ref_312m), MKSTR(ref_104m), MKSTR(ref_52m),
+ MKSTR(ref_13m), MKSTR(var_312m), MKSTR(var_104m),
+ MKSTR(var_52m), MKSTR(var_13m),
+};
+
+int refclk_entries = sizeof(refclk_str_tbl)/sizeof(refclk_str_tbl[0]);
+
+/* convert ref clock string to clock structure pointer */
+struct refclk *refclk_str_to_clk(const char *name)
+{
+ int i;
+ struct refclk_lkup *tblp = refclk_str_tbl;
+ for (i = 0; i < refclk_entries; i++, tblp++) {
+ if (!(strcmp(name, tblp->name)))
+ return tblp->procclk;
+ }
+ return NULL;
+}
+
+/* frequency tables indexed by freq_id */
+unsigned long master_axi_freq_tbl[8] = {
+ 26 * CLOCK_1M,
+ 52 * CLOCK_1M,
+ 104 * CLOCK_1M,
+ 156 * CLOCK_1M,
+ 156 * CLOCK_1M,
+ 208 * CLOCK_1M,
+ 312 * CLOCK_1M,
+ 312 * CLOCK_1M
+};
+
+unsigned long master_ahb_freq_tbl[8] = {
+ 26 * CLOCK_1M,
+ 52 * CLOCK_1M,
+ 52 * CLOCK_1M,
+ 52 * CLOCK_1M,
+ 78 * CLOCK_1M,
+ 104 * CLOCK_1M,
+ 104 * CLOCK_1M,
+ 156 * CLOCK_1M
+};
+
+unsigned long slave_axi_freq_tbl[8] = {
+ 26 * CLOCK_1M,
+ 52 * CLOCK_1M,
+ 78 * CLOCK_1M,
+ 104 * CLOCK_1M,
+ 156 * CLOCK_1M,
+ 156 * CLOCK_1M
+};
+
+unsigned long slave_apb_freq_tbl[8] = {
+ 26 * CLOCK_1M,
+ 26 * CLOCK_1M,
+ 39 * CLOCK_1M,
+ 52 * CLOCK_1M,
+ 52 * CLOCK_1M,
+ 78 * CLOCK_1M
+};
+
+static struct bus_clk_data bsc1_apb_data = {
+ .gate = HW_SW_GATE_AUTO(0x0458, 16, 0, 1),
+};
+
+static struct bus_clk_data bsc2_apb_data = {
+ .gate = HW_SW_GATE_AUTO(0x045c, 16, 0, 1),
+};
+
+static struct bus_clk_data bsc3_apb_data = {
+ .gate = HW_SW_GATE_AUTO(0x0484, 16, 0, 1),
+};
+
+/* * Master CCU clocks */
+static struct peri_clk_data sdio1_data = {
+ .gate = HW_SW_GATE(0x0358, 18, 2, 3),
+ .clocks = CLOCKS("ref_crystal",
+ "var_52m",
+ "ref_52m",
+ "var_96m",
+ "ref_96m"),
+ .sel = SELECTOR(0x0a28, 0, 3),
+ .div = DIVIDER(0x0a28, 4, 14),
+ .trig = TRIGGER(0x0afc, 9),
+};
+
+static struct peri_clk_data sdio2_data = {
+ .gate = HW_SW_GATE(0x035c, 18, 2, 3),
+ .clocks = CLOCKS("ref_crystal",
+ "var_52m",
+ "ref_52m",
+ "var_96m",
+ "ref_96m"),
+ .sel = SELECTOR(0x0a2c, 0, 3),
+ .div = DIVIDER(0x0a2c, 4, 14),
+ .trig = TRIGGER(0x0afc, 10),
+};
+
+static struct peri_clk_data sdio3_data = {
+ .gate = HW_SW_GATE(0x0364, 18, 2, 3),
+ .clocks = CLOCKS("ref_crystal",
+ "var_52m",
+ "ref_52m",
+ "var_96m",
+ "ref_96m"),
+ .sel = SELECTOR(0x0a34, 0, 3),
+ .div = DIVIDER(0x0a34, 4, 14),
+ .trig = TRIGGER(0x0afc, 12),
+};
+
+static struct peri_clk_data sdio4_data = {
+ .gate = HW_SW_GATE(0x0360, 18, 2, 3),
+ .clocks = CLOCKS("ref_crystal",
+ "var_52m",
+ "ref_52m",
+ "var_96m",
+ "ref_96m"),
+ .sel = SELECTOR(0x0a30, 0, 3),
+ .div = DIVIDER(0x0a30, 4, 14),
+ .trig = TRIGGER(0x0afc, 11),
+};
+
+static struct peri_clk_data sdio1_sleep_data = {
+ .clocks = CLOCKS("ref_32k"),
+ .gate = SW_ONLY_GATE(0x0358, 20, 4),
+};
+
+static struct peri_clk_data sdio2_sleep_data = {
+ .clocks = CLOCKS("ref_32k"),
+ .gate = SW_ONLY_GATE(0x035c, 20, 4),
+};
+
+static struct peri_clk_data sdio3_sleep_data = {
+ .clocks = CLOCKS("ref_32k"),
+ .gate = SW_ONLY_GATE(0x0364, 20, 4),
+};
+
+static struct peri_clk_data sdio4_sleep_data = {
+ .clocks = CLOCKS("ref_32k"),
+ .gate = SW_ONLY_GATE(0x0360, 20, 4),
+};
+
+static struct bus_clk_data sdio1_ahb_data = {
+ .gate = HW_SW_GATE_AUTO(0x0358, 16, 0, 1),
+};
+
+static struct bus_clk_data sdio2_ahb_data = {
+ .gate = HW_SW_GATE_AUTO(0x035c, 16, 0, 1),
+};
+
+static struct bus_clk_data sdio3_ahb_data = {
+ .gate = HW_SW_GATE_AUTO(0x0364, 16, 0, 1),
+};
+
+static struct bus_clk_data sdio4_ahb_data = {
+ .gate = HW_SW_GATE_AUTO(0x0360, 16, 0, 1),
+};
+
+/* * Slave CCU clocks */
+static struct peri_clk_data bsc1_data = {
+ .gate = HW_SW_GATE(0x0458, 18, 2, 3),
+ .clocks = CLOCKS("ref_crystal",
+ "var_104m",
+ "ref_104m",
+ "var_13m",
+ "ref_13m"),
+ .sel = SELECTOR(0x0a64, 0, 3),
+ .trig = TRIGGER(0x0afc, 23),
+};
+
+static struct peri_clk_data bsc2_data = {
+ .gate = HW_SW_GATE(0x045c, 18, 2, 3),
+ .clocks = CLOCKS("ref_crystal",
+ "var_104m",
+ "ref_104m",
+ "var_13m",
+ "ref_13m"),
+ .sel = SELECTOR(0x0a68, 0, 3),
+ .trig = TRIGGER(0x0afc, 24),
+};
+
+static struct peri_clk_data bsc3_data = {
+ .gate = HW_SW_GATE(0x0484, 18, 2, 3),
+ .clocks = CLOCKS("ref_crystal",
+ "var_104m",
+ "ref_104m",
+ "var_13m",
+ "ref_13m"),
+ .sel = SELECTOR(0x0a84, 0, 3),
+ .trig = TRIGGER(0x0b00, 2),
+};
+
+/*
+ * CCU clocks
+ */
+
+static struct ccu_clock kpm_ccu_clk = {
+ .clk = {
+ .name = "kpm_ccu_clk",
+ .ops = &ccu_clk_ops,
+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+ },
+ .num_policy_masks = 1,
+ .policy_freq_offset = 0x00000008,
+ .freq_bit_shift = 8,
+ .policy_ctl_offset = 0x0000000c,
+ .policy0_mask_offset = 0x00000010,
+ .policy1_mask_offset = 0x00000014,
+ .policy2_mask_offset = 0x00000018,
+ .policy3_mask_offset = 0x0000001c,
+ .lvm_en_offset = 0x00000034,
+ .freq_id = 2,
+ .freq_tbl = master_axi_freq_tbl,
+};
+
+static struct ccu_clock kps_ccu_clk = {
+ .clk = {
+ .name = "kps_ccu_clk",
+ .ops = &ccu_clk_ops,
+ .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+ },
+ .num_policy_masks = 2,
+ .policy_freq_offset = 0x00000008,
+ .freq_bit_shift = 8,
+ .policy_ctl_offset = 0x0000000c,
+ .policy0_mask_offset = 0x00000010,
+ .policy1_mask_offset = 0x00000014,
+ .policy2_mask_offset = 0x00000018,
+ .policy3_mask_offset = 0x0000001c,
+ .policy0_mask2_offset = 0x00000048,
+ .policy1_mask2_offset = 0x0000004c,
+ .policy2_mask2_offset = 0x00000050,
+ .policy3_mask2_offset = 0x00000054,
+ .lvm_en_offset = 0x00000034,
+ .freq_id = 2,
+ .freq_tbl = slave_axi_freq_tbl,
+};
+
+/*
+ * Bus clocks
+ */
+
+/* KPM bus clocks */
+static struct bus_clock sdio1_ahb_clk = {
+ .clk = {
+ .name = "sdio1_ahb_clk",
+ .parent = &kpm_ccu_clk.clk,
+ .ops = &bus_clk_ops,
+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+ },
+ .freq_tbl = master_ahb_freq_tbl,
+ .data = &sdio1_ahb_data,
+};
+
+static struct bus_clock sdio2_ahb_clk = {
+ .clk = {
+ .name = "sdio2_ahb_clk",
+ .parent = &kpm_ccu_clk.clk,
+ .ops = &bus_clk_ops,
+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+ },
+ .freq_tbl = master_ahb_freq_tbl,
+ .data = &sdio2_ahb_data,
+};
+
+static struct bus_clock sdio3_ahb_clk = {
+ .clk = {
+ .name = "sdio3_ahb_clk",
+ .parent = &kpm_ccu_clk.clk,
+ .ops = &bus_clk_ops,
+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+ },
+ .freq_tbl = master_ahb_freq_tbl,
+ .data = &sdio3_ahb_data,
+};
+
+static struct bus_clock sdio4_ahb_clk = {
+ .clk = {
+ .name = "sdio4_ahb_clk",
+ .parent = &kpm_ccu_clk.clk,
+ .ops = &bus_clk_ops,
+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+ },
+ .freq_tbl = master_ahb_freq_tbl,
+ .data = &sdio4_ahb_data,
+};
+
+static struct bus_clock bsc1_apb_clk = {
+ .clk = {
+ .name = "bsc1_apb_clk",
+ .parent = &kps_ccu_clk.clk,
+ .ops = &bus_clk_ops,
+ .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+ },
+ .freq_tbl = slave_apb_freq_tbl,
+ .data = &bsc1_apb_data,
+};
+
+static struct bus_clock bsc2_apb_clk = {
+ .clk = {
+ .name = "bsc2_apb_clk",
+ .parent = &kps_ccu_clk.clk,
+ .ops = &bus_clk_ops,
+ .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+ },
+ .freq_tbl = slave_apb_freq_tbl,
+ .data = &bsc2_apb_data,
+};
+
+static struct bus_clock bsc3_apb_clk = {
+ .clk = {
+ .name = "bsc3_apb_clk",
+ .parent = &kps_ccu_clk.clk,
+ .ops = &bus_clk_ops,
+ .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+ },
+ .freq_tbl = slave_apb_freq_tbl,
+ .data = &bsc3_apb_data,
+};
+
+/* KPM peripheral */
+static struct peri_clock sdio1_clk = {
+ .clk = {
+ .name = "sdio1_clk",
+ .parent = &ref_52m.clk,
+ .ops = &peri_clk_ops,
+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+ },
+ .data = &sdio1_data,
+};
+
+static struct peri_clock sdio2_clk = {
+ .clk = {
+ .name = "sdio2_clk",
+ .parent = &ref_52m.clk,
+ .ops = &peri_clk_ops,
+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+ },
+ .data = &sdio2_data,
+};
+
+static struct peri_clock sdio3_clk = {
+ .clk = {
+ .name = "sdio3_clk",
+ .parent = &ref_52m.clk,
+ .ops = &peri_clk_ops,
+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+ },
+ .data = &sdio3_data,
+};
+
+static struct peri_clock sdio4_clk = {
+ .clk = {
+ .name = "sdio4_clk",
+ .parent = &ref_52m.clk,
+ .ops = &peri_clk_ops,
+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+ },
+ .data = &sdio4_data,
+};
+
+static struct peri_clock sdio1_sleep_clk = {
+ .clk = {
+ .name = "sdio1_sleep_clk",
+ .parent = &kpm_ccu_clk.clk,
+ .ops = &bus_clk_ops,
+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+ },
+ .data = &sdio1_sleep_data,
+};
+
+static struct peri_clock sdio2_sleep_clk = {
+ .clk = {
+ .name = "sdio2_sleep_clk",
+ .parent = &kpm_ccu_clk.clk,
+ .ops = &bus_clk_ops,
+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+ },
+ .data = &sdio2_sleep_data,
+};
+
+static struct peri_clock sdio3_sleep_clk = {
+ .clk = {
+ .name = "sdio3_sleep_clk",
+ .parent = &kpm_ccu_clk.clk,
+ .ops = &bus_clk_ops,
+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+ },
+ .data = &sdio3_sleep_data,
+};
+
+static struct peri_clock sdio4_sleep_clk = {
+ .clk = {
+ .name = "sdio4_sleep_clk",
+ .parent = &kpm_ccu_clk.clk,
+ .ops = &bus_clk_ops,
+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+ },
+ .data = &sdio4_sleep_data,
+};
+
+/* KPS peripheral clock */
+static struct peri_clock bsc1_clk = {
+ .clk = {
+ .name = "bsc1_clk",
+ .parent = &ref_13m.clk,
+ .rate = 13 * CLOCK_1M,
+ .div = 1,
+ .ops = &peri_clk_ops,
+ .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+ },
+ .data = &bsc1_data,
+};
+
+static struct peri_clock bsc2_clk = {
+ .clk = {
+ .name = "bsc2_clk",
+ .parent = &ref_13m.clk,
+ .rate = 13 * CLOCK_1M,
+ .div = 1,
+ .ops = &peri_clk_ops,
+ .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+ },
+ .data = &bsc2_data,
+};
+
+static struct peri_clock bsc3_clk = {
+ .clk = {
+ .name = "bsc3_clk",
+ .parent = &ref_13m.clk,
+ .rate = 13 * CLOCK_1M,
+ .div = 1,
+ .ops = &peri_clk_ops,
+ .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+ },
+ .data = &bsc3_data,
+};
+
+/* public table for registering clocks */
+struct clk_lookup arch_clk_tbl[] = {
+ /* Peripheral clocks */
+ CLK_LK(sdio1),
+ CLK_LK(sdio2),
+ CLK_LK(sdio3),
+ CLK_LK(sdio4),
+ CLK_LK(sdio1_sleep),
+ CLK_LK(sdio2_sleep),
+ CLK_LK(sdio3_sleep),
+ CLK_LK(sdio4_sleep),
+ CLK_LK(bsc1),
+ CLK_LK(bsc2),
+ CLK_LK(bsc3),
+ /* Bus clocks */
+ CLK_LK(sdio1_ahb),
+ CLK_LK(sdio2_ahb),
+ CLK_LK(sdio3_ahb),
+ CLK_LK(sdio4_ahb),
+ CLK_LK(bsc1_apb),
+ CLK_LK(bsc2_apb),
+ CLK_LK(bsc3_apb),
+};
+
+/* public array size */
+unsigned int arch_clk_tbl_array_size = ARRAY_SIZE(arch_clk_tbl);
--- /dev/null
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+/* Enable appropriate clocks for a BSC/I2C port */
+int clk_bsc_enable(void *base)
+{
+ int ret;
+ char *bscstr, *apbstr;
+
+ switch ((u32) base) {
+ case PMU_BSC_BASE_ADDR:
+ /* PMU clock is always enabled */
+ return 0;
+ case BSC1_BASE_ADDR:
+ bscstr = "bsc1_clk";
+ apbstr = "bsc1_apb_clk";
+ break;
+ case BSC2_BASE_ADDR:
+ bscstr = "bsc2_clk";
+ apbstr = "bsc2_apb_clk";
+ break;
+ case BSC3_BASE_ADDR:
+ bscstr = "bsc3_clk";
+ apbstr = "bsc3_apb_clk";
+ break;
+ default:
+ printf("%s: base 0x%p not found\n", __func__, base);
+ return -EINVAL;
+ }
+
+ /* Note that the bus clock must be enabled first */
+
+ ret = clk_get_and_enable(apbstr);
+ if (ret)
+ return ret;
+
+ ret = clk_get_and_enable(bscstr);
+ if (ret)
+ return ret;
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ *
+ * bcm281xx architecture clock framework
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <bitfield.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+#define CLK_WR_ACCESS_PASSWORD 0x00a5a501
+#define WR_ACCESS_OFFSET 0 /* common to all clock blocks */
+#define POLICY_CTL_GO 1 /* Load and refresh policy masks */
+#define POLICY_CTL_GO_ATL 4 /* Active Load */
+
+/* Helper function */
+int clk_get_and_enable(char *clkstr)
+{
+ int ret = 0;
+ struct clk *c;
+
+ debug("%s: %s\n", __func__, clkstr);
+
+ c = clk_get(clkstr);
+ if (c) {
+ ret = clk_enable(c);
+ if (ret)
+ return ret;
+ } else {
+ printf("%s: Couldn't find %s\n", __func__, clkstr);
+ return -EINVAL;
+ }
+ return ret;
+}
+
+/*
+ * Poll a register in a CCU's address space, returning when the
+ * specified bit in that register's value is set (or clear). Delay
+ * a microsecond after each read of the register. Returns true if
+ * successful, or false if we gave up trying.
+ *
+ * Caller must ensure the CCU lock is held.
+ */
+#define CLK_GATE_DELAY_USEC 2000
+static inline int wait_bit(void *base, u32 offset, u32 bit, bool want)
+{
+ unsigned int tries;
+ u32 bit_mask = 1 << bit;
+
+ for (tries = 0; tries < CLK_GATE_DELAY_USEC; tries++) {
+ u32 val;
+ bool bit_val;
+
+ val = readl(base + offset);
+ bit_val = (val & bit_mask) ? 1 : 0;
+ if (bit_val == want)
+ return 0; /* success */
+ udelay(1);
+ }
+
+ debug("%s: timeout on addr 0x%p, waiting for bit %d to go to %d\n",
+ __func__, base + offset, bit, want);
+
+ return -ETIMEDOUT;
+}
+
+/* Enable a peripheral clock */
+static int peri_clk_enable(struct clk *c, int enable)
+{
+ int ret = 0;
+ u32 reg;
+ struct peri_clock *peri_clk = to_peri_clk(c);
+ struct peri_clk_data *cd = peri_clk->data;
+ struct bcm_clk_gate *gate = &cd->gate;
+ void *base = (void *)c->ccu_clk_mgr_base;
+
+
+ debug("%s: %s\n", __func__, c->name);
+
+ clk_get_rate(c); /* Make sure rate and sel are filled in */
+
+ /* enable access */
+ writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
+
+ if (enable) {
+ debug("%s %s set rate %lu div %lu sel %d parent %lu\n",
+ __func__, c->name, c->rate, c->div, c->sel,
+ c->parent->rate);
+
+ /*
+ * clkgate - only software controllable gates are
+ * supported by u-boot which includes all clocks
+ * that matter. This avoids bringing in a lot of extra
+ * complexity as done in the kernel framework.
+ */
+ if (gate_exists(gate)) {
+ reg = readl(base + cd->gate.offset);
+ reg |= (1 << cd->gate.en_bit);
+ writel(reg, base + cd->gate.offset);
+ }
+
+ /* div and pll select */
+ if (divider_exists(&cd->div)) {
+ reg = readl(base + cd->div.offset);
+ bitfield_replace(reg, cd->div.shift, cd->div.width,
+ c->div - 1);
+ writel(reg, base + cd->div.offset);
+ }
+
+ /* frequency selector */
+ if (selector_exists(&cd->sel)) {
+ reg = readl(base + cd->sel.offset);
+ bitfield_replace(reg, cd->sel.shift, cd->sel.width,
+ c->sel);
+ writel(reg, base + cd->sel.offset);
+ }
+
+ /* trigger */
+ if (trigger_exists(&cd->trig)) {
+ writel((1 << cd->trig.bit), base + cd->trig.offset);
+
+ /* wait for trigger status bit to go to 0 */
+ ret = wait_bit(base, cd->trig.offset, cd->trig.bit, 0);
+ if (ret)
+ return ret;
+ }
+
+ /* wait for running (status_bit = 1) */
+ ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 1);
+ if (ret)
+ return ret;
+ } else {
+ debug("%s disable clock %s\n", __func__, c->name);
+
+ /* clkgate */
+ reg = readl(base + cd->gate.offset);
+ reg &= ~(1 << cd->gate.en_bit);
+ writel(reg, base + cd->gate.offset);
+
+ /* wait for stop (status_bit = 0) */
+ ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 0);
+ }
+
+ /* disable access */
+ writel(0, base + WR_ACCESS_OFFSET);
+
+ return ret;
+}
+
+/* Set the rate of a peripheral clock */
+static int peri_clk_set_rate(struct clk *c, unsigned long rate)
+{
+ int ret = 0;
+ int i;
+ unsigned long diff;
+ unsigned long new_rate = 0, div = 1;
+ struct peri_clock *peri_clk = to_peri_clk(c);
+ struct peri_clk_data *cd = peri_clk->data;
+ const char **clock;
+
+ debug("%s: %s\n", __func__, c->name);
+ diff = rate;
+
+ i = 0;
+ for (clock = cd->clocks; *clock; clock++, i++) {
+ struct refclk *ref = refclk_str_to_clk(*clock);
+ if (!ref) {
+ printf("%s: Lookup of %s failed\n", __func__, *clock);
+ return -EINVAL;
+ }
+
+ /* round to the new rate */
+ div = ref->clk.rate / rate;
+ if (div == 0)
+ div = 1;
+
+ new_rate = ref->clk.rate / div;
+
+ /* get the min diff */
+ if (abs(new_rate - rate) < diff) {
+ diff = abs(new_rate - rate);
+ c->sel = i;
+ c->parent = &ref->clk;
+ c->rate = new_rate;
+ c->div = div;
+ }
+ }
+
+ debug("%s %s set rate %lu div %lu sel %d parent %lu\n", __func__,
+ c->name, c->rate, c->div, c->sel, c->parent->rate);
+ return ret;
+}
+
+/* Get the rate of a peripheral clock */
+static unsigned long peri_clk_get_rate(struct clk *c)
+{
+ struct peri_clock *peri_clk = to_peri_clk(c);
+ struct peri_clk_data *cd = peri_clk->data;
+ void *base = (void *)c->ccu_clk_mgr_base;
+ int div = 1;
+ const char **clock;
+ struct refclk *ref;
+ u32 reg;
+
+ debug("%s: %s\n", __func__, c->name);
+ if (selector_exists(&cd->sel)) {
+ reg = readl(base + cd->sel.offset);
+ c->sel = bitfield_extract(reg, cd->sel.shift, cd->sel.width);
+ } else {
+ /*
+ * For peri clocks that don't have a selector, the single
+ * reference clock will always exist at index 0.
+ */
+ c->sel = 0;
+ }
+
+ if (divider_exists(&cd->div)) {
+ reg = readl(base + cd->div.offset);
+ div = bitfield_extract(reg, cd->div.shift, cd->div.width);
+ div += 1;
+ }
+
+ clock = cd->clocks;
+ ref = refclk_str_to_clk(clock[c->sel]);
+ if (!ref) {
+ printf("%s: Can't lookup %s\n", __func__, clock[c->sel]);
+ return 0;
+ }
+
+ c->parent = &ref->clk;
+ c->div = div;
+ c->rate = c->parent->rate / c->div;
+ debug("%s parent rate %lu div %d sel %d rate %lu\n", __func__,
+ c->parent->rate, div, c->sel, c->rate);
+
+ return c->rate;
+}
+
+/* Peripheral clock operations */
+struct clk_ops peri_clk_ops = {
+ .enable = peri_clk_enable,
+ .set_rate = peri_clk_set_rate,
+ .get_rate = peri_clk_get_rate,
+};
+
+/* Enable a CCU clock */
+static int ccu_clk_enable(struct clk *c, int enable)
+{
+ struct ccu_clock *ccu_clk = to_ccu_clk(c);
+ void *base = (void *)c->ccu_clk_mgr_base;
+ int ret = 0;
+ u32 reg;
+
+ debug("%s: %s\n", __func__, c->name);
+ if (!enable)
+ return -EINVAL; /* CCU clock cannot shutdown */
+
+ /* enable access */
+ writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
+
+ /* config enable for policy engine */
+ writel(1, base + ccu_clk->lvm_en_offset);
+
+ /* wait for bit to go to 0 */
+ ret = wait_bit(base, ccu_clk->lvm_en_offset, 0, 0);
+ if (ret)
+ return ret;
+
+ /* freq ID */
+ if (!ccu_clk->freq_bit_shift)
+ ccu_clk->freq_bit_shift = 8;
+
+ /* Set frequency id for each of the 4 policies */
+ reg = ccu_clk->freq_id |
+ (ccu_clk->freq_id << (ccu_clk->freq_bit_shift)) |
+ (ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 2)) |
+ (ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 3));
+ writel(reg, base + ccu_clk->policy_freq_offset);
+
+ /* enable all clock mask */
+ writel(0x7fffffff, base + ccu_clk->policy0_mask_offset);
+ writel(0x7fffffff, base + ccu_clk->policy1_mask_offset);
+ writel(0x7fffffff, base + ccu_clk->policy2_mask_offset);
+ writel(0x7fffffff, base + ccu_clk->policy3_mask_offset);
+
+ if (ccu_clk->num_policy_masks == 2) {
+ writel(0x7fffffff, base + ccu_clk->policy0_mask2_offset);
+ writel(0x7fffffff, base + ccu_clk->policy1_mask2_offset);
+ writel(0x7fffffff, base + ccu_clk->policy2_mask2_offset);
+ writel(0x7fffffff, base + ccu_clk->policy3_mask2_offset);
+ }
+
+ /* start policy engine */
+ reg = readl(base + ccu_clk->policy_ctl_offset);
+ reg |= (POLICY_CTL_GO + POLICY_CTL_GO_ATL);
+ writel(reg, base + ccu_clk->policy_ctl_offset);
+
+ /* wait till started */
+ ret = wait_bit(base, ccu_clk->policy_ctl_offset, 0, 0);
+ if (ret)
+ return ret;
+
+ /* disable access */
+ writel(0, base + WR_ACCESS_OFFSET);
+
+ return ret;
+}
+
+/* Get the CCU clock rate */
+static unsigned long ccu_clk_get_rate(struct clk *c)
+{
+ struct ccu_clock *ccu_clk = to_ccu_clk(c);
+ debug("%s: %s\n", __func__, c->name);
+ c->rate = ccu_clk->freq_tbl[ccu_clk->freq_id];
+ return c->rate;
+}
+
+/* CCU clock operations */
+struct clk_ops ccu_clk_ops = {
+ .enable = ccu_clk_enable,
+ .get_rate = ccu_clk_get_rate,
+};
+
+/* Enable a bus clock */
+static int bus_clk_enable(struct clk *c, int enable)
+{
+ struct bus_clock *bus_clk = to_bus_clk(c);
+ struct bus_clk_data *cd = bus_clk->data;
+ void *base = (void *)c->ccu_clk_mgr_base;
+ int ret = 0;
+ u32 reg;
+
+ debug("%s: %s\n", __func__, c->name);
+ /* enable access */
+ writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
+
+ /* enable gating */
+ reg = readl(base + cd->gate.offset);
+ if (!!(reg & (1 << cd->gate.status_bit)) == !!enable)
+ debug("%s already %s\n", c->name,
+ enable ? "enabled" : "disabled");
+ else {
+ int want = (enable) ? 1 : 0;
+ reg |= (1 << cd->gate.hw_sw_sel_bit);
+
+ if (enable)
+ reg |= (1 << cd->gate.en_bit);
+ else
+ reg &= ~(1 << cd->gate.en_bit);
+
+ writel(reg, base + cd->gate.offset);
+ ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit,
+ want);
+ if (ret)
+ return ret;
+ }
+
+ /* disable access */
+ writel(0, base + WR_ACCESS_OFFSET);
+
+ return ret;
+}
+
+/* Get the rate of a bus clock */
+static unsigned long bus_clk_get_rate(struct clk *c)
+{
+ struct bus_clock *bus_clk = to_bus_clk(c);
+ struct ccu_clock *ccu_clk;
+
+ debug("%s: %s\n", __func__, c->name);
+ ccu_clk = to_ccu_clk(c->parent);
+
+ c->rate = bus_clk->freq_tbl[ccu_clk->freq_id];
+ c->div = ccu_clk->freq_tbl[ccu_clk->freq_id] / c->rate;
+ return c->rate;
+}
+
+/* Bus clock operations */
+struct clk_ops bus_clk_ops = {
+ .enable = bus_clk_enable,
+ .get_rate = bus_clk_get_rate,
+};
+
+/* Enable a reference clock */
+static int ref_clk_enable(struct clk *c, int enable)
+{
+ debug("%s: %s\n", __func__, c->name);
+ return 0;
+}
+
+/* Reference clock operations */
+struct clk_ops ref_clk_ops = {
+ .enable = ref_clk_enable,
+};
+
+/*
+ * clk.h implementation follows
+ */
+
+/* Initialize the clock framework */
+int clk_init(void)
+{
+ debug("%s:\n", __func__);
+ return 0;
+}
+
+/* Get a clock handle, give a name string */
+struct clk *clk_get(const char *con_id)
+{
+ int i;
+ struct clk_lookup *clk_tblp;
+
+ debug("%s: %s\n", __func__, con_id);
+
+ clk_tblp = arch_clk_tbl;
+ for (i = 0; i < arch_clk_tbl_array_size; i++, clk_tblp++) {
+ if (clk_tblp->con_id) {
+ if (!con_id || strcmp(clk_tblp->con_id, con_id))
+ continue;
+ return clk_tblp->clk;
+ }
+ }
+ return NULL;
+}
+
+/* Enable a clock */
+int clk_enable(struct clk *c)
+{
+ int ret = 0;
+
+ debug("%s: %s\n", __func__, c->name);
+ if (!c->ops || !c->ops->enable)
+ return -1;
+
+ /* enable parent clock first */
+ if (c->parent)
+ ret = clk_enable(c->parent);
+
+ if (ret)
+ return ret;
+
+ if (!c->use_cnt) {
+ c->use_cnt++;
+ ret = c->ops->enable(c, 1);
+ }
+
+ return ret;
+}
+
+/* Disable a clock */
+void clk_disable(struct clk *c)
+{
+ debug("%s: %s\n", __func__, c->name);
+ if (!c->ops || !c->ops->enable)
+ return;
+
+ if (c->use_cnt) {
+ c->use_cnt--;
+ c->ops->enable(c, 0);
+ }
+
+ /* disable parent */
+ if (c->parent)
+ clk_disable(c->parent);
+}
+
+/* Get the clock rate */
+unsigned long clk_get_rate(struct clk *c)
+{
+ unsigned long rate;
+
+ debug("%s: %s\n", __func__, c->name);
+ if (!c || !c->ops || !c->ops->get_rate)
+ return 0;
+
+ rate = c->ops->get_rate(c);
+ debug("%s: rate = %ld\n", __func__, rate);
+ return rate;
+}
+
+/* Set the clock rate */
+int clk_set_rate(struct clk *c, unsigned long rate)
+{
+ int ret;
+
+ debug("%s: %s rate=%ld\n", __func__, c->name, rate);
+ if (!c || !c->ops || !c->ops->set_rate)
+ return -EINVAL;
+
+ if (c->use_cnt)
+ return -EINVAL;
+
+ ret = c->ops->set_rate(c, rate);
+
+ return ret;
+}
+
+/* Not required for this arch */
+/*
+long clk_round_rate(struct clk *clk, unsigned long rate);
+int clk_set_parent(struct clk *clk, struct clk *parent);
+struct clk *clk_get_parent(struct clk *clk);
+*/
--- /dev/null
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/stddef.h>
+
+#ifdef CONFIG_CLK_DEBUG
+#undef writel
+#undef readl
+static inline void writel(u32 val, void *addr)
+{
+ printf("Write [0x%p] = 0x%08x\n", addr, val);
+ *(u32 *)addr = val;
+}
+
+static inline u32 readl(void *addr)
+{
+ u32 val = *(u32 *)addr;
+ printf("Read [0x%p] = 0x%08x\n", addr, val);
+ return val;
+}
+#endif
+
+struct clk;
+
+struct clk_lookup {
+ const char *dev_id;
+ const char *con_id;
+ struct clk *clk;
+};
+
+extern struct clk_lookup arch_clk_tbl[];
+extern unsigned int arch_clk_tbl_array_size;
+
+/**
+ * struct clk_ops - standard clock operations
+ * @enable: enable/disable clock, see clk_enable() and clk_disable()
+ * @set_rate: set the clock rate, see clk_set_rate().
+ * @get_rate: get the clock rate, see clk_get_rate().
+ * @round_rate: round a given clock rate, see clk_round_rate().
+ * @set_parent: set the clock's parent, see clk_set_parent().
+ *
+ * Group the common clock implementations together so that we
+ * don't have to keep setting the same fiels again. We leave
+ * enable in struct clk.
+ *
+ */
+struct clk_ops {
+ int (*enable) (struct clk *c, int enable);
+ int (*set_rate) (struct clk *c, unsigned long rate);
+ unsigned long (*get_rate) (struct clk *c);
+ unsigned long (*round_rate) (struct clk *c, unsigned long rate);
+ int (*set_parent) (struct clk *c, struct clk *parent);
+};
+
+struct clk {
+ struct clk *parent;
+ const char *name;
+ int use_cnt;
+ unsigned long rate; /* in HZ */
+
+ /* programmable divider. 0 means fixed ratio to parent clock */
+ unsigned long div;
+
+ struct clk_src *src;
+ struct clk_ops *ops;
+
+ unsigned long ccu_clk_mgr_base;
+ int sel;
+};
+
+struct refclk *refclk_str_to_clk(const char *name);
+
+#define U8_MAX ((u8)~0U)
+#define U32_MAX ((u32)~0U)
+#define U64_MAX ((u64)~0U)
+
+/* The common clock framework uses u8 to represent a parent index */
+#define PARENT_COUNT_MAX ((u32)U8_MAX)
+
+#define BAD_CLK_INDEX U8_MAX /* Can't ever be valid */
+#define BAD_CLK_NAME ((const char *)-1)
+
+#define BAD_SCALED_DIV_VALUE U64_MAX
+
+/*
+ * Utility macros for object flag management. If possible, flags
+ * should be defined such that 0 is the desired default value.
+ */
+#define FLAG(type, flag) BCM_CLK_ ## type ## _FLAGS_ ## flag
+#define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag))
+#define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag)))
+#define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag))
+#define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag)))
+
+/* Clock field state tests */
+
+#define gate_exists(gate) FLAG_TEST(gate, GATE, EXISTS)
+#define gate_is_enabled(gate) FLAG_TEST(gate, GATE, ENABLED)
+#define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW)
+#define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW)
+#define gate_is_sw_managed(gate) FLAG_TEST(gate, GATE, SW_MANAGED)
+#define gate_is_no_disable(gate) FLAG_TEST(gate, GATE, NO_DISABLE)
+
+#define gate_flip_enabled(gate) FLAG_FLIP(gate, GATE, ENABLED)
+
+#define divider_exists(div) FLAG_TEST(div, DIV, EXISTS)
+#define divider_is_fixed(div) FLAG_TEST(div, DIV, FIXED)
+#define divider_has_fraction(div) (!divider_is_fixed(div) && \
+ (div)->frac_width > 0)
+
+#define selector_exists(sel) ((sel)->width != 0)
+#define trigger_exists(trig) FLAG_TEST(trig, TRIG, EXISTS)
+
+/* Clock type, used to tell common block what it's part of */
+enum bcm_clk_type {
+ bcm_clk_none, /* undefined clock type */
+ bcm_clk_bus,
+ bcm_clk_core,
+ bcm_clk_peri
+};
+
+/*
+ * Gating control and status is managed by a 32-bit gate register.
+ *
+ * There are several types of gating available:
+ * - (no gate)
+ * A clock with no gate is assumed to be always enabled.
+ * - hardware-only gating (auto-gating)
+ * Enabling or disabling clocks with this type of gate is
+ * managed automatically by the hardware. Such clocks can be
+ * considered by the software to be enabled. The current status
+ * of auto-gated clocks can be read from the gate status bit.
+ * - software-only gating
+ * Auto-gating is not available for this type of clock.
+ * Instead, software manages whether it's enabled by setting or
+ * clearing the enable bit. The current gate status of a gate
+ * under software control can be read from the gate status bit.
+ * To ensure a change to the gating status is complete, the
+ * status bit can be polled to verify that the gate has entered
+ * the desired state.
+ * - selectable hardware or software gating
+ * Gating for this type of clock can be configured to be either
+ * under software or hardware control. Which type is in use is
+ * determined by the hw_sw_sel bit of the gate register.
+ */
+struct bcm_clk_gate {
+ u32 offset; /* gate register offset */
+ u32 status_bit; /* 0: gate is disabled; 0: gatge is enabled */
+ u32 en_bit; /* 0: disable; 1: enable */
+ u32 hw_sw_sel_bit; /* 0: hardware gating; 1: software gating */
+ u32 flags; /* BCM_CLK_GATE_FLAGS_* below */
+};
+
+/*
+ * Gate flags:
+ * HW means this gate can be auto-gated
+ * SW means the state of this gate can be software controlled
+ * NO_DISABLE means this gate is (only) enabled if under software control
+ * SW_MANAGED means the status of this gate is under software control
+ * ENABLED means this software-managed gate is *supposed* to be enabled
+ */
+#define BCM_CLK_GATE_FLAGS_EXISTS ((u32)1 << 0) /* Gate is valid */
+#define BCM_CLK_GATE_FLAGS_HW ((u32)1 << 1) /* Can auto-gate */
+#define BCM_CLK_GATE_FLAGS_SW ((u32)1 << 2) /* Software control */
+#define BCM_CLK_GATE_FLAGS_NO_DISABLE ((u32)1 << 3) /* HW or enabled */
+#define BCM_CLK_GATE_FLAGS_SW_MANAGED ((u32)1 << 4) /* SW now in control */
+#define BCM_CLK_GATE_FLAGS_ENABLED ((u32)1 << 5) /* If SW_MANAGED */
+
+/*
+ * Gate initialization macros.
+ *
+ * Any gate initially under software control will be enabled.
+ */
+
+/* A hardware/software gate initially under software control */
+#define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \
+ { \
+ .offset = (_offset), \
+ .status_bit = (_status_bit), \
+ .en_bit = (_en_bit), \
+ .hw_sw_sel_bit = (_hw_sw_sel_bit), \
+ .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
+ FLAG(GATE, SW_MANAGED)|FLAG(GATE, ENABLED)| \
+ FLAG(GATE, EXISTS), \
+ }
+
+/* A hardware/software gate initially under hardware control */
+#define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \
+ { \
+ .offset = (_offset), \
+ .status_bit = (_status_bit), \
+ .en_bit = (_en_bit), \
+ .hw_sw_sel_bit = (_hw_sw_sel_bit), \
+ .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
+ FLAG(GATE, EXISTS), \
+ }
+
+/* A hardware-or-enabled gate (enabled if not under hardware control) */
+#define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \
+ { \
+ .offset = (_offset), \
+ .status_bit = (_status_bit), \
+ .en_bit = (_en_bit), \
+ .hw_sw_sel_bit = (_hw_sw_sel_bit), \
+ .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
+ FLAG(GATE, NO_DISABLE)|FLAG(GATE, EXISTS), \
+ }
+
+/* A software-only gate */
+#define SW_ONLY_GATE(_offset, _status_bit, _en_bit) \
+ { \
+ .offset = (_offset), \
+ .status_bit = (_status_bit), \
+ .en_bit = (_en_bit), \
+ .flags = FLAG(GATE, SW)|FLAG(GATE, SW_MANAGED)| \
+ FLAG(GATE, ENABLED)|FLAG(GATE, EXISTS), \
+ }
+
+/* A hardware-only gate */
+#define HW_ONLY_GATE(_offset, _status_bit) \
+ { \
+ .offset = (_offset), \
+ .status_bit = (_status_bit), \
+ .flags = FLAG(GATE, HW)|FLAG(GATE, EXISTS), \
+ }
+
+/*
+ * Each clock can have zero, one, or two dividers which change the
+ * output rate of the clock. Each divider can be either fixed or
+ * variable. If there are two dividers, they are the "pre-divider"
+ * and the "regular" or "downstream" divider. If there is only one,
+ * there is no pre-divider.
+ *
+ * A fixed divider is any non-zero (positive) value, and it
+ * indicates how the input rate is affected by the divider.
+ *
+ * The value of a variable divider is maintained in a sub-field of a
+ * 32-bit divider register. The position of the field in the
+ * register is defined by its offset and width. The value recorded
+ * in this field is always 1 less than the value it represents.
+ *
+ * In addition, a variable divider can indicate that some subset
+ * of its bits represent a "fractional" part of the divider. Such
+ * bits comprise the low-order portion of the divider field, and can
+ * be viewed as representing the portion of the divider that lies to
+ * the right of the decimal point. Most variable dividers have zero
+ * fractional bits. Variable dividers with non-zero fraction width
+ * still record a value 1 less than the value they represent; the
+ * added 1 does *not* affect the low-order bit in this case, it
+ * affects the bits above the fractional part only. (Often in this
+ * code a divider field value is distinguished from the value it
+ * represents by referring to the latter as a "divisor".)
+ *
+ * In order to avoid dealing with fractions, divider arithmetic is
+ * performed using "scaled" values. A scaled value is one that's
+ * been left-shifted by the fractional width of a divider. Dividing
+ * a scaled value by a scaled divisor produces the desired quotient
+ * without loss of precision and without any other special handling
+ * for fractions.
+ *
+ * The recorded value of a variable divider can be modified. To
+ * modify either divider (or both), a clock must be enabled (i.e.,
+ * using its gate). In addition, a trigger register (described
+ * below) must be used to commit the change, and polled to verify
+ * the change is complete.
+ */
+struct bcm_clk_div {
+ union {
+ struct { /* variable divider */
+ u32 offset; /* divider register offset */
+ u32 shift; /* field shift */
+ u32 width; /* field width */
+ u32 frac_width; /* field fraction width */
+
+ u64 scaled_div; /* scaled divider value */
+ };
+ u32 fixed; /* non-zero fixed divider value */
+ };
+ u32 flags; /* BCM_CLK_DIV_FLAGS_* below */
+};
+
+/*
+ * Divider flags:
+ * EXISTS means this divider exists
+ * FIXED means it is a fixed-rate divider
+ */
+#define BCM_CLK_DIV_FLAGS_EXISTS ((u32)1 << 0) /* Divider is valid */
+#define BCM_CLK_DIV_FLAGS_FIXED ((u32)1 << 1) /* Fixed-value */
+
+/* Divider initialization macros */
+
+/* A fixed (non-zero) divider */
+#define FIXED_DIVIDER(_value) \
+ { \
+ .fixed = (_value), \
+ .flags = FLAG(DIV, EXISTS)|FLAG(DIV, FIXED), \
+ }
+
+/* A divider with an integral divisor */
+#define DIVIDER(_offset, _shift, _width) \
+ { \
+ .offset = (_offset), \
+ .shift = (_shift), \
+ .width = (_width), \
+ .scaled_div = BAD_SCALED_DIV_VALUE, \
+ .flags = FLAG(DIV, EXISTS), \
+ }
+
+/* A divider whose divisor has an integer and fractional part */
+#define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \
+ { \
+ .offset = (_offset), \
+ .shift = (_shift), \
+ .width = (_width), \
+ .frac_width = (_frac_width), \
+ .scaled_div = BAD_SCALED_DIV_VALUE, \
+ .flags = FLAG(DIV, EXISTS), \
+ }
+
+/*
+ * Clocks may have multiple "parent" clocks. If there is more than
+ * one, a selector must be specified to define which of the parent
+ * clocks is currently in use. The selected clock is indicated in a
+ * sub-field of a 32-bit selector register. The range of
+ * representable selector values typically exceeds the number of
+ * available parent clocks. Occasionally the reset value of a
+ * selector field is explicitly set to a (specific) value that does
+ * not correspond to a defined input clock.
+ *
+ * We register all known parent clocks with the common clock code
+ * using a packed array (i.e., no empty slots) of (parent) clock
+ * names, and refer to them later using indexes into that array.
+ * We maintain an array of selector values indexed by common clock
+ * index values in order to map between these common clock indexes
+ * and the selector values used by the hardware.
+ *
+ * Like dividers, a selector can be modified, but to do so a clock
+ * must be enabled, and a trigger must be used to commit the change.
+ */
+struct bcm_clk_sel {
+ u32 offset; /* selector register offset */
+ u32 shift; /* field shift */
+ u32 width; /* field width */
+
+ u32 parent_count; /* number of entries in parent_sel[] */
+ u32 *parent_sel; /* array of parent selector values */
+ u8 clk_index; /* current selected index in parent_sel[] */
+};
+
+/* Selector initialization macro */
+#define SELECTOR(_offset, _shift, _width) \
+ { \
+ .offset = (_offset), \
+ .shift = (_shift), \
+ .width = (_width), \
+ .clk_index = BAD_CLK_INDEX, \
+ }
+
+/*
+ * Making changes to a variable divider or a selector for a clock
+ * requires the use of a trigger. A trigger is defined by a single
+ * bit within a register. To signal a change, a 1 is written into
+ * that bit. To determine when the change has been completed, that
+ * trigger bit is polled; the read value will be 1 while the change
+ * is in progress, and 0 when it is complete.
+ *
+ * Occasionally a clock will have more than one trigger. In this
+ * case, the "pre-trigger" will be used when changing a clock's
+ * selector and/or its pre-divider.
+ */
+struct bcm_clk_trig {
+ u32 offset; /* trigger register offset */
+ u32 bit; /* trigger bit */
+ u32 flags; /* BCM_CLK_TRIG_FLAGS_* below */
+};
+
+/*
+ * Trigger flags:
+ * EXISTS means this trigger exists
+ */
+#define BCM_CLK_TRIG_FLAGS_EXISTS ((u32)1 << 0) /* Trigger is valid */
+
+/* Trigger initialization macro */
+#define TRIGGER(_offset, _bit) \
+ { \
+ .offset = (_offset), \
+ .bit = (_bit), \
+ .flags = FLAG(TRIG, EXISTS), \
+ }
+
+struct bus_clk_data {
+ struct bcm_clk_gate gate;
+};
+
+struct core_clk_data {
+ struct bcm_clk_gate gate;
+};
+
+struct peri_clk_data {
+ struct bcm_clk_gate gate;
+ struct bcm_clk_trig pre_trig;
+ struct bcm_clk_div pre_div;
+ struct bcm_clk_trig trig;
+ struct bcm_clk_div div;
+ struct bcm_clk_sel sel;
+ const char *clocks[]; /* must be last; use CLOCKS() to declare */
+};
+#define CLOCKS(...) { __VA_ARGS__, NULL, }
+#define NO_CLOCKS { NULL, } /* Must use of no parent clocks */
+
+struct refclk {
+ struct clk clk;
+};
+
+struct peri_clock {
+ struct clk clk;
+ struct peri_clk_data *data;
+};
+
+struct ccu_clock {
+ struct clk clk;
+
+ int num_policy_masks;
+ unsigned long policy_freq_offset;
+ int freq_bit_shift; /* 8 for most CCUs */
+ unsigned long policy_ctl_offset;
+ unsigned long policy0_mask_offset;
+ unsigned long policy1_mask_offset;
+ unsigned long policy2_mask_offset;
+ unsigned long policy3_mask_offset;
+ unsigned long policy0_mask2_offset;
+ unsigned long policy1_mask2_offset;
+ unsigned long policy2_mask2_offset;
+ unsigned long policy3_mask2_offset;
+ unsigned long lvm_en_offset;
+
+ int freq_id;
+ unsigned long *freq_tbl;
+};
+
+struct bus_clock {
+ struct clk clk;
+ struct bus_clk_data *data;
+ unsigned long *freq_tbl;
+};
+
+struct ref_clock {
+ struct clk clk;
+};
+
+static inline int is_same_clock(struct clk *a, struct clk *b)
+{
+ return (a == b);
+}
+
+#define to_clk(p) (&((p)->clk))
+#define name_to_clk(name) (&((name##_clk).clk))
+/* declare a struct clk_lookup */
+#define CLK_LK(name) \
+{.con_id = __stringify(name##_clk), .clk = name_to_clk(name),}
+
+static inline struct refclk *to_refclk(struct clk *clock)
+{
+ return container_of(clock, struct refclk, clk);
+}
+
+static inline struct peri_clock *to_peri_clk(struct clk *clock)
+{
+ return container_of(clock, struct peri_clock, clk);
+}
+
+static inline struct ccu_clock *to_ccu_clk(struct clk *clock)
+{
+ return container_of(clock, struct ccu_clock, clk);
+}
+
+static inline struct bus_clock *to_bus_clk(struct clk *clock)
+{
+ return container_of(clock, struct bus_clock, clk);
+}
+
+static inline struct ref_clock *to_ref_clk(struct clk *clock)
+{
+ return container_of(clock, struct ref_clock, clk);
+}
+
+extern struct clk_ops peri_clk_ops;
+extern struct clk_ops ccu_clk_ops;
+extern struct clk_ops bus_clk_ops;
+extern struct clk_ops ref_clk_ops;
+
+extern int clk_get_and_enable(char *clkstr);
--- /dev/null
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+/* Enable appropriate clocks for an SDIO port */
+int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep)
+{
+ int ret;
+ struct clk *c;
+
+ char *clkstr;
+ char *slpstr;
+ char *ahbstr;
+
+ switch ((u32) base) {
+ case CONFIG_SYS_SDIO_BASE0:
+ clkstr = CONFIG_SYS_SDIO0 "_clk";
+ ahbstr = CONFIG_SYS_SDIO0 "_ahb_clk";
+ slpstr = CONFIG_SYS_SDIO0 "_sleep_clk";
+ break;
+ case CONFIG_SYS_SDIO_BASE1:
+ clkstr = CONFIG_SYS_SDIO1 "_clk";
+ ahbstr = CONFIG_SYS_SDIO1 "_ahb_clk";
+ slpstr = CONFIG_SYS_SDIO1 "_sleep_clk";
+ break;
+ case CONFIG_SYS_SDIO_BASE2:
+ clkstr = CONFIG_SYS_SDIO2 "_clk";
+ ahbstr = CONFIG_SYS_SDIO2 "_ahb_clk";
+ slpstr = CONFIG_SYS_SDIO2 "_sleep_clk";
+ break;
+ case CONFIG_SYS_SDIO_BASE3:
+ clkstr = CONFIG_SYS_SDIO3 "_clk";
+ ahbstr = CONFIG_SYS_SDIO3 "_ahb_clk";
+ slpstr = CONFIG_SYS_SDIO3 "_sleep_clk";
+ break;
+ default:
+ printf("%s: base 0x%p not found\n", __func__, base);
+ return -EINVAL;
+ }
+
+ ret = clk_get_and_enable(ahbstr);
+ if (ret)
+ return ret;
+
+ ret = clk_get_and_enable(slpstr);
+ if (ret)
+ return ret;
+
+ c = clk_get(clkstr);
+ if (c) {
+ ret = clk_set_rate(c, rate);
+ if (ret)
+ return ret;
+
+ ret = clk_enable(c);
+ if (ret)
+ return ret;
+ } else {
+ printf("%s: Couldn't find %s\n", __func__, clkstr);
+ return -EINVAL;
+ }
+ *actual_ratep = rate;
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sysmap.h>
+
+#define EN_MASK 0x08000000 /* Enable timer */
+#define SRSTEN_MASK 0x04000000 /* Enable soft reset */
+#define CLKS_SHIFT 20 /* Clock period shift */
+#define LD_SHIFT 0 /* Reload value shift */
+
+void reset_cpu(ulong ignored)
+{
+ /*
+ * Set WD enable, RST enable,
+ * 3.9 msec clock period (8), reload value (8*3.9ms)
+ */
+ u32 reg = EN_MASK + SRSTEN_MASK + (8 << CLKS_SHIFT) + (8 << LD_SHIFT);
+ writel(reg, SECWD2_BASE_ADDR);
+
+ while (1)
+ ; /* loop forever till reset */
+}
PF_CPPFLAGS_ARMV7 := $(call cc-option, -march=armv7-a, -march=armv5)
PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARMV7)
-# SEE README.arm-unaligned-accesses
+# On supported platforms we set the bit which causes us to trap on unaligned
+# memory access. This is the opposite of what the compiler expects to be
+# the default so we must pass in -mno-unaligned-access so that it is aware
+# of our decision.
PF_NO_UNALIGNED := $(call cc-option, -mno-unaligned-access,)
-PLATFORM_NO_UNALIGNED := $(PF_NO_UNALIGNED)
-
-ifneq ($(CONFIG_IMX_CONFIG),)
-ifdef CONFIG_SPL
-ifdef CONFIG_SPL_BUILD
-ALL-y += $(OBJTREE)/SPL
-endif
-else
-ALL-y += $(obj)u-boot.imx
-endif
-endif
+PLATFORM_CPPFLAGS += $(PF_NO_UNALIGNED)
};
/* src_bit div_bit prediv_bit */
-static struct clk_bit_info clk_bit_info[PERIPH_ID_COUNT] = {
+static struct clk_bit_info clk_bit_info[] = {
{0, 0, -1},
{4, 4, -1},
{8, 8, -1},
struct exynos4_clock *clk =
(struct exynos4_clock *)samsung_get_base_clock();
unsigned int addr;
- unsigned int val;
/*
* CLK_DIV_FSYS1
dev_index -= 2;
}
- val = readl(addr);
- val &= ~(0xff << ((dev_index << 4) + 8));
- val |= (div & 0xff) << ((dev_index << 4) + 8);
- writel(val, addr);
+ clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
+ (div & 0xff) << ((dev_index << 4) + 8));
}
/* exynos4x12: set the mmc clock */
struct exynos4x12_clock *clk =
(struct exynos4x12_clock *)samsung_get_base_clock();
unsigned int addr;
- unsigned int val;
/*
* CLK_DIV_FSYS1
dev_index -= 2;
}
- val = readl(addr);
- val &= ~(0xff << ((dev_index << 4) + 8));
- val |= (div & 0xff) << ((dev_index << 4) + 8);
- writel(val, addr);
+ clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
+ (div & 0xff) << ((dev_index << 4) + 8));
}
/* exynos5: set the mmc clock */
struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock();
unsigned int addr;
- unsigned int val;
/*
* CLK_DIV_FSYS1
dev_index -= 2;
}
- val = readl(addr);
- val &= ~(0xff << ((dev_index << 4) + 8));
- val |= (div & 0xff) << ((dev_index << 4) + 8);
- writel(val, addr);
+ clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
+ (div & 0xff) << ((dev_index << 4) + 8));
}
/* exynos5: set the mmc clock */
struct exynos5420_clock *clk =
(struct exynos5420_clock *)samsung_get_base_clock();
unsigned int addr;
- unsigned int val, shift;
+ unsigned int shift;
/*
* CLK_DIV_FSYS1
addr = (unsigned int)&clk->div_fsys1;
shift = dev_index * 10;
- val = readl(addr);
- val &= ~(0x3ff << shift);
- val |= (div & 0x3ff) << shift;
- writel(val, addr);
+ clrsetbits_le32(addr, 0x3ff << shift, (div & 0x3ff) << shift);
}
/* get_lcd_clk: return lcd clock frequency */
{
struct exynos4_clock *clk =
(struct exynos4_clock *)samsung_get_base_clock();
- unsigned int cfg = 0;
/*
* CLK_GATE_BLOCK
* CLK_LCD1 [5]
* CLK_GPS [7]
*/
- cfg = readl(&clk->gate_block);
- cfg |= 1 << 4;
- writel(cfg, &clk->gate_block);
+ setbits_le32(&clk->gate_block, 1 << 4);
/*
* CLK_SRC_LCD0
* MIPI0_SEL [12:15]
* set lcd0 src clock 0x6: SCLK_MPLL
*/
- cfg = readl(&clk->src_lcd0);
- cfg &= ~(0xf);
- cfg |= 0x6;
- writel(cfg, &clk->src_lcd0);
+ clrsetbits_le32(&clk->src_lcd0, 0xf, 0x6);
/*
* CLK_GATE_IP_LCD0
* CLK_PPMULCD0 [5]
* Gating all clocks for FIMD0
*/
- cfg = readl(&clk->gate_ip_lcd0);
- cfg |= 1 << 0;
- writel(cfg, &clk->gate_ip_lcd0);
+ setbits_le32(&clk->gate_ip_lcd0, 1 << 0);
/*
* CLK_DIV_LCD0
* MIPI0_PRE_RATIO [23:20]
* set fimd ratio
*/
- cfg &= ~(0xf);
- cfg |= 0x1;
- writel(cfg, &clk->div_lcd0);
+ clrsetbits_le32(&clk->div_lcd0, 0xf, 0x1);
}
void exynos5_set_lcd_clk(void)
{
struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock();
- unsigned int cfg = 0;
/*
* CLK_GATE_BLOCK
* CLK_LCD1 [5]
* CLK_GPS [7]
*/
- cfg = readl(&clk->gate_block);
- cfg |= 1 << 4;
- writel(cfg, &clk->gate_block);
+ setbits_le32(&clk->gate_block, 1 << 4);
/*
* CLK_SRC_LCD0
* MIPI0_SEL [12:15]
* set lcd0 src clock 0x6: SCLK_MPLL
*/
- cfg = readl(&clk->src_disp1_0);
- cfg &= ~(0xf);
- cfg |= 0x6;
- writel(cfg, &clk->src_disp1_0);
+ clrsetbits_le32(&clk->src_disp1_0, 0xf, 0x6);
/*
* CLK_GATE_IP_LCD0
* CLK_PPMULCD0 [5]
* Gating all clocks for FIMD0
*/
- cfg = readl(&clk->gate_ip_disp1);
- cfg |= 1 << 0;
- writel(cfg, &clk->gate_ip_disp1);
+ setbits_le32(&clk->gate_ip_disp1, 1 << 0);
/*
* CLK_DIV_LCD0
* MIPI0_PRE_RATIO [23:20]
* set fimd ratio
*/
- cfg &= ~(0xf);
- cfg |= 0x0;
- writel(cfg, &clk->div_disp1_0);
+ clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0);
}
void exynos4_set_mipi_clk(void)
{
struct exynos4_clock *clk =
(struct exynos4_clock *)samsung_get_base_clock();
- unsigned int cfg = 0;
/*
* CLK_SRC_LCD0
* MIPI0_SEL [12:15]
* set mipi0 src clock 0x6: SCLK_MPLL
*/
- cfg = readl(&clk->src_lcd0);
- cfg &= ~(0xf << 12);
- cfg |= (0x6 << 12);
- writel(cfg, &clk->src_lcd0);
+ clrsetbits_le32(&clk->src_lcd0, 0xf << 12, 0x6 << 12);
/*
* CLK_SRC_MASK_LCD0
* MIPI0_MASK [12]
* set src mask mipi0 0x1: Unmask
*/
- cfg = readl(&clk->src_mask_lcd0);
- cfg |= (0x1 << 12);
- writel(cfg, &clk->src_mask_lcd0);
+ setbits_le32(&clk->src_mask_lcd0, 0x1 << 12);
/*
* CLK_GATE_IP_LCD0
* CLK_PPMULCD0 [5]
* Gating all clocks for MIPI0
*/
- cfg = readl(&clk->gate_ip_lcd0);
- cfg |= 1 << 3;
- writel(cfg, &clk->gate_ip_lcd0);
+ setbits_le32(&clk->gate_ip_lcd0, 1 << 3);
/*
* CLK_DIV_LCD0
* MIPI0_PRE_RATIO [23:20]
* set mipi ratio
*/
- cfg &= ~(0xf << 16);
- cfg |= (0x1 << 16);
- writel(cfg, &clk->div_lcd0);
+ clrsetbits_le32(&clk->div_lcd0, 0xf << 16, 0x1 << 16);
}
/*
if (err)
return PERIPH_ID_NONE;
- /* check for invalid peripheral id */
- if ((PERIPH_ID_SDMMC4 > cell[1]) || (cell[1] < PERIPH_ID_UART0))
- return cell[1];
-
- debug(" invalid peripheral id\n");
- return PERIPH_ID_NONE;
+ return cell[1];
}
int pinmux_decode_periph_id(const void *blob, int node)
--- /dev/null
+#
+# Copyright 2013 Broadcom Corporation.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += s_init.o
+obj-y += hwinit-common.o
+obj-y += clk-stubs.o
--- /dev/null
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+/*
+ * These weak functions are available to kona architectures that don't
+ * require clock enables from the driver code.
+ */
+int __weak clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep)
+{
+ return 0;
+}
+
+int __weak clk_bsc_enable(void *base, u32 rate, u32 *actual_ratep)
+{
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/sizes.h>
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+}
+#endif
--- /dev/null
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Early system init. Currently empty.
+ */
+void s_init(void)
+{
+}
u32 spl_boot_mode(void)
{
- return gd->arch.omap_boot_params.omap_bootmode;
+ u32 val = gd->arch.omap_boot_params.omap_bootmode;
+
+ if (val == MMCSD_MODE_RAW)
+ return MMCSD_MODE_RAW;
+ else if (val == MMCSD_MODE_FAT)
+ return MMCSD_MODE_FAT;
+ else
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+ return MMCSD_MODE_EMMCBOOT;
+#else
+ return MMCSD_MODE_UNDEFINED;
+#endif
}
void spl_board_init(void)
+++ /dev/null
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# Make ARMv5 to allow more compilers to work, even though its v7a.
-PLATFORM_CPPFLAGS += -march=armv5
(DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT;
}
+#if defined(CONFIG_DISPLAY_CPUINFO)
/*
* Print CPU information
*/
return 0;
}
+#endif
+
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
#include <scsi.h>
#include <asm/arch/clock.h>
#include <asm/arch/sata.h>
+#include <sata.h>
#include <asm/io.h>
#include "pipe3-phy.h"
.dpll_map = dpll_map_sata,
};
-int omap_sata_init(void)
+int init_sata(int dev)
{
int ret;
u32 val;
. = ALIGN(4);
__image_copy_end = .;
- _end = .;
+
+ .end :
+ {
+ *(.__end)
+ }
.bss :
{
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_SPL_BUILD
-ALL-y += $(OBJTREE)/MLO
+ALL-y += MLO
else
-ALL-y += $(obj)u-boot.img
+ALL-y += u-boot.img
endif
#include <asm/arch/clocks_omap3.h>
#include <linux/linkage.h>
-_TEXT_BASE:
- .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
-
#ifdef CONFIG_SPL_BUILD
ENTRY(save_boot_params)
ldr r4, =omap3_boot_device
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_SPL_BUILD
-ALL-y += $(OBJTREE)/MLO
+ALL-y += MLO
else
-ALL-y += $(obj)u-boot.img
+ALL-y += u-boot.img
endif
.ddr = NULL
};
+struct dplls omap4430_dplls_es20 = {
+ .mpu = mpu_dpll_params_1200mhz,
+ .core = core_dpll_params_es2_1600mhz_ddr200mhz,
+ .per = per_dpll_params_1536mhz,
+ .iva = iva_dpll_params_1862mhz,
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+ .abe = abe_dpll_params_sysclk_196608khz,
+#else
+ .abe = &abe_dpll_params_32k_196608khz,
+#endif
+ .usb = usb_dpll_params_1920mhz,
+ .ddr = NULL
+};
+
struct dplls omap4430_dplls = {
.mpu = mpu_dpll_params_1200mhz,
.core = core_dpll_params_1600mhz,
break;
case OMAP4430_ES2_0:
+ *dplls_data = &omap4430_dplls_es20;
+ *omap_vcores = &omap4430_volts;
+ break;
+
case OMAP4430_ES2_1:
case OMAP4430_ES2_2:
case OMAP4430_ES2_3:
#
ifdef CONFIG_SPL_BUILD
-ALL-y += $(OBJTREE)/MLO
+ALL-y += MLO
else
-ALL-y += $(obj)u-boot.img
+ALL-y += u-boot.img
endif
.control_srcomp_code_latch = 0x4A002E84,
.control_ddr_control_ext_0 = 0x4A002E88,
.control_padconf_core_base = 0x4A003400,
- .control_std_fuse_opp_vdd_mpu_2 = 0x4A003B24,
+ .control_std_fuse_opp_vdd_mpu_2 = 0x4A003B20,
.control_port_emif1_sdram_config = 0x4AE0C110,
.control_port_emif1_lpddr2_nvm_config = 0x4AE0C114,
.control_port_emif2_sdram_config = 0x4AE0C118,
# SPDX-License-Identifier: GPL-2.0+
#
ifndef CONFIG_SPL_BUILD
-ALL-y += $(obj)u-boot.img
+ALL-y += u-boot.img
endif
. = ALIGN(4);
__image_copy_end = .;
- _end = .;
+
+ .end :
+ {
+ *(.__end)
+ }
.bss : {
. = ALIGN(4);
*
*************************************************************************/
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
- .word CONFIG_SPL_TEXT_BASE
-#else
- .word CONFIG_SYS_TEXT_BASE
-#endif
-
-/*
- * These are defined in the board-specific linker script.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
- .word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
- .word __bss_end - _start
-
-.globl _end_ofs
-_end_ofs:
- .word _end - _start
-
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
-obj- :=
+# necessary to create built-in.o
+obj- := __dummy__.o
--- /dev/null
+#
+# (C) Copyright 2013-2014
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+# necessary to create built-in.o
+obj- := __dummy__.o
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
-obj- :=
+# necessary to create built-in.o
+obj- := __dummy__.o
obj-y += cpu.o
obj-y += ddrc.o
obj-y += slcr.o
+obj-y += clk.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
--- /dev/null
+/*
+ * Copyright (C) 2013 Soren Brinkmann <soren.brinkmann@xilinx.com>
+ * Copyright (C) 2013 Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <errno.h>
+#include <clk.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/clk.h>
+
+/* Board oscillator frequency */
+#ifndef CONFIG_ZYNQ_PS_CLK_FREQ
+# define CONFIG_ZYNQ_PS_CLK_FREQ 33333333UL
+#endif
+
+/* Register bitfield defines */
+#define PLLCTRL_FBDIV_MASK 0x7f000
+#define PLLCTRL_FBDIV_SHIFT 12
+#define PLLCTRL_BPFORCE_MASK (1 << 4)
+#define PLLCTRL_PWRDWN_MASK 2
+#define PLLCTRL_PWRDWN_SHIFT 1
+#define PLLCTRL_RESET_MASK 1
+#define PLLCTRL_RESET_SHIFT 0
+
+#define ZYNQ_CLK_MAXDIV 0x3f
+#define CLK_CTRL_DIV1_SHIFT 20
+#define CLK_CTRL_DIV1_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT)
+#define CLK_CTRL_DIV0_SHIFT 8
+#define CLK_CTRL_DIV0_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT)
+#define CLK_CTRL_SRCSEL_SHIFT 4
+#define CLK_CTRL_SRCSEL_MASK (0x3 << CLK_CTRL_SRCSEL_SHIFT)
+
+#define CLK_CTRL_DIV2X_SHIFT 26
+#define CLK_CTRL_DIV2X_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV2X_SHIFT)
+#define CLK_CTRL_DIV3X_SHIFT 20
+#define CLK_CTRL_DIV3X_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV3X_SHIFT)
+
+#define ZYNQ_CLKMUX_SEL_0 0
+#define ZYNQ_CLKMUX_SEL_1 1
+#define ZYNQ_CLKMUX_SEL_2 2
+#define ZYNQ_CLKMUX_SEL_3 3
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct clk;
+
+/**
+ * struct clk_ops:
+ * @set_rate: Function pointer to set_rate() implementation
+ * @get_rate: Function pointer to get_rate() implementation
+ */
+struct clk_ops {
+ int (*set_rate)(struct clk *clk, unsigned long rate);
+ unsigned long (*get_rate)(struct clk *clk);
+};
+
+/**
+ * struct clk:
+ * @name: Clock name
+ * @frequency: Currenct frequency
+ * @parent: Parent clock
+ * @flags: Clock flags
+ * @reg: Clock control register
+ * @ops: Clock operations
+ */
+struct clk {
+ char *name;
+ unsigned long frequency;
+ enum zynq_clk parent;
+ unsigned int flags;
+ u32 *reg;
+ struct clk_ops ops;
+};
+#define ZYNQ_CLK_FLAGS_HAS_2_DIVS 1
+
+static struct clk clks[clk_max];
+
+/**
+ * __zynq_clk_cpu_get_parent() - Decode clock multiplexer
+ * @srcsel: Mux select value
+ * Returns the clock identifier associated with the selected mux input.
+ */
+static int __zynq_clk_cpu_get_parent(unsigned int srcsel)
+{
+ unsigned int ret;
+
+ switch (srcsel) {
+ case ZYNQ_CLKMUX_SEL_0:
+ case ZYNQ_CLKMUX_SEL_1:
+ ret = armpll_clk;
+ break;
+ case ZYNQ_CLKMUX_SEL_2:
+ ret = ddrpll_clk;
+ break;
+ case ZYNQ_CLKMUX_SEL_3:
+ ret = iopll_clk;
+ break;
+ default:
+ ret = armpll_clk;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * ddr2x_get_rate() - Get clock rate of DDR2x clock
+ * @clk: Clock handle
+ * Returns the current clock rate of @clk.
+ */
+static unsigned long ddr2x_get_rate(struct clk *clk)
+{
+ u32 clk_ctrl = readl(clk->reg);
+ u32 div = (clk_ctrl & CLK_CTRL_DIV2X_MASK) >> CLK_CTRL_DIV2X_SHIFT;
+
+ return DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div);
+}
+
+/**
+ * ddr3x_get_rate() - Get clock rate of DDR3x clock
+ * @clk: Clock handle
+ * Returns the current clock rate of @clk.
+ */
+static unsigned long ddr3x_get_rate(struct clk *clk)
+{
+ u32 clk_ctrl = readl(clk->reg);
+ u32 div = (clk_ctrl & CLK_CTRL_DIV3X_MASK) >> CLK_CTRL_DIV3X_SHIFT;
+
+ return DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div);
+}
+
+static void init_ddr_clocks(void)
+{
+ u32 div0, div1;
+ unsigned long prate = zynq_clk_get_rate(ddrpll_clk);
+ u32 clk_ctrl = readl(&slcr_base->ddr_clk_ctrl);
+
+ /* DDR2x */
+ clks[ddr2x_clk].reg = &slcr_base->ddr_clk_ctrl;
+ clks[ddr2x_clk].parent = ddrpll_clk;
+ clks[ddr2x_clk].name = "ddr_2x";
+ clks[ddr2x_clk].frequency = ddr2x_get_rate(&clks[ddr2x_clk]);
+ clks[ddr2x_clk].ops.get_rate = ddr2x_get_rate;
+
+ /* DDR3x */
+ clks[ddr3x_clk].reg = &slcr_base->ddr_clk_ctrl;
+ clks[ddr3x_clk].parent = ddrpll_clk;
+ clks[ddr3x_clk].name = "ddr_3x";
+ clks[ddr3x_clk].frequency = ddr3x_get_rate(&clks[ddr3x_clk]);
+ clks[ddr3x_clk].ops.get_rate = ddr3x_get_rate;
+
+ /* DCI */
+ clk_ctrl = readl(&slcr_base->dci_clk_ctrl);
+ div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
+ div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
+ clks[dci_clk].reg = &slcr_base->dci_clk_ctrl;
+ clks[dci_clk].parent = ddrpll_clk;
+ clks[dci_clk].frequency = DIV_ROUND_CLOSEST(
+ DIV_ROUND_CLOSEST(prate, div0), div1);
+ clks[dci_clk].name = "dci";
+
+ gd->bd->bi_ddr_freq = clks[ddr3x_clk].frequency / 1000000;
+}
+
+static void init_cpu_clocks(void)
+{
+ int clk_621;
+ u32 reg, div, srcsel;
+ enum zynq_clk parent;
+
+ reg = readl(&slcr_base->arm_clk_ctrl);
+ clk_621 = readl(&slcr_base->clk_621_true) & 1;
+ div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
+ srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
+ parent = __zynq_clk_cpu_get_parent(srcsel);
+
+ /* cpu clocks */
+ clks[cpu_6or4x_clk].reg = &slcr_base->arm_clk_ctrl;
+ clks[cpu_6or4x_clk].parent = parent;
+ clks[cpu_6or4x_clk].frequency = DIV_ROUND_CLOSEST(
+ zynq_clk_get_rate(parent), div);
+ clks[cpu_6or4x_clk].name = "cpu_6or4x";
+
+ clks[cpu_3or2x_clk].reg = &slcr_base->arm_clk_ctrl;
+ clks[cpu_3or2x_clk].parent = cpu_6or4x_clk;
+ clks[cpu_3or2x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) / 2;
+ clks[cpu_3or2x_clk].name = "cpu_3or2x";
+
+ clks[cpu_2x_clk].reg = &slcr_base->arm_clk_ctrl;
+ clks[cpu_2x_clk].parent = cpu_6or4x_clk;
+ clks[cpu_2x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) /
+ (2 + clk_621);
+ clks[cpu_2x_clk].name = "cpu_2x";
+
+ clks[cpu_1x_clk].reg = &slcr_base->arm_clk_ctrl;
+ clks[cpu_1x_clk].parent = cpu_6or4x_clk;
+ clks[cpu_1x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) /
+ (4 + 2 * clk_621);
+ clks[cpu_1x_clk].name = "cpu_1x";
+}
+
+/**
+ * periph_calc_two_divs() - Calculate clock dividers
+ * @cur_rate: Current clock rate
+ * @tgt_rate: Target clock rate
+ * @prate: Parent clock rate
+ * @div0: First divider (output)
+ * @div1: Second divider (output)
+ * Returns the actual clock rate possible.
+ *
+ * Calculates clock dividers for clocks with two 6-bit dividers.
+ */
+static unsigned long periph_calc_two_divs(unsigned long cur_rate,
+ unsigned long tgt_rate, unsigned long prate, u32 *div0,
+ u32 *div1)
+{
+ long err, best_err = (long)(~0UL >> 1);
+ unsigned long rate, best_rate = 0;
+ u32 d0, d1;
+
+ for (d0 = 1; d0 <= ZYNQ_CLK_MAXDIV; d0++) {
+ for (d1 = 1; d1 <= ZYNQ_CLK_MAXDIV >> 1; d1++) {
+ rate = DIV_ROUND_CLOSEST(DIV_ROUND_CLOSEST(prate, d0),
+ d1);
+ err = abs(rate - tgt_rate);
+
+ if (err < best_err) {
+ *div0 = d0;
+ *div1 = d1;
+ best_err = err;
+ best_rate = rate;
+ }
+ }
+ }
+
+ return best_rate;
+}
+
+/**
+ * zynq_clk_periph_set_rate() - Set clock rate
+ * @clk: Handle of the peripheral clock
+ * @rate: New clock rate
+ * Sets the clock frequency of @clk to @rate. Returns zero on success.
+ */
+static int zynq_clk_periph_set_rate(struct clk *clk,
+ unsigned long rate)
+{
+ u32 ctrl, div0 = 0, div1 = 0;
+ unsigned long prate, new_rate, cur_rate = clk->frequency;
+
+ ctrl = readl(clk->reg);
+ prate = zynq_clk_get_rate(clk->parent);
+ ctrl &= ~CLK_CTRL_DIV0_MASK;
+
+ if (clk->flags & ZYNQ_CLK_FLAGS_HAS_2_DIVS) {
+ ctrl &= ~CLK_CTRL_DIV1_MASK;
+ new_rate = periph_calc_two_divs(cur_rate, rate, prate, &div0,
+ &div1);
+ ctrl |= div1 << CLK_CTRL_DIV1_SHIFT;
+ } else {
+ div0 = DIV_ROUND_CLOSEST(prate, rate);
+ div0 &= ZYNQ_CLK_MAXDIV;
+ new_rate = DIV_ROUND_CLOSEST(rate, div0);
+ }
+
+ /* write new divs to hardware */
+ ctrl |= div0 << CLK_CTRL_DIV0_SHIFT;
+ writel(ctrl, clk->reg);
+
+ /* update frequency in clk framework */
+ clk->frequency = new_rate;
+
+ return 0;
+}
+
+/**
+ * zynq_clk_periph_get_rate() - Get clock rate
+ * @clk: Handle of the peripheral clock
+ * Returns the current clock rate of @clk.
+ */
+static unsigned long zynq_clk_periph_get_rate(struct clk *clk)
+{
+ u32 clk_ctrl = readl(clk->reg);
+ u32 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
+ u32 div1 = 1;
+
+ if (clk->flags & ZYNQ_CLK_FLAGS_HAS_2_DIVS)
+ div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
+
+ /* a register value of zero == division by 1 */
+ if (!div0)
+ div0 = 1;
+ if (!div1)
+ div1 = 1;
+
+ return
+ DIV_ROUND_CLOSEST(
+ DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div0),
+ div1);
+}
+
+/**
+ * __zynq_clk_periph_get_parent() - Decode clock multiplexer
+ * @srcsel: Mux select value
+ * Returns the clock identifier associated with the selected mux input.
+ */
+static enum zynq_clk __zynq_clk_periph_get_parent(u32 srcsel)
+{
+ switch (srcsel) {
+ case ZYNQ_CLKMUX_SEL_0:
+ case ZYNQ_CLKMUX_SEL_1:
+ return iopll_clk;
+ case ZYNQ_CLKMUX_SEL_2:
+ return armpll_clk;
+ case ZYNQ_CLKMUX_SEL_3:
+ return ddrpll_clk;
+ default:
+ return 0;
+ }
+}
+
+/**
+ * zynq_clk_periph_get_parent() - Decode clock multiplexer
+ * @clk: Clock handle
+ * Returns the clock identifier associated with the selected mux input.
+ */
+static enum zynq_clk zynq_clk_periph_get_parent(struct clk *clk)
+{
+ u32 clk_ctrl = readl(clk->reg);
+ u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
+
+ return __zynq_clk_periph_get_parent(srcsel);
+}
+
+/**
+ * zynq_clk_register_periph_clk() - Set up a peripheral clock with the framework
+ * @clk: Pointer to struct clk for the clock
+ * @ctrl: Clock control register
+ * @name: PLL name
+ * @two_divs: Indicates whether the clock features one or two dividers
+ */
+static int zynq_clk_register_periph_clk(struct clk *clk, u32 *ctrl, char *name,
+ bool two_divs)
+{
+ clk->name = name;
+ clk->reg = ctrl;
+ if (two_divs)
+ clk->flags = ZYNQ_CLK_FLAGS_HAS_2_DIVS;
+ clk->parent = zynq_clk_periph_get_parent(clk);
+ clk->frequency = zynq_clk_periph_get_rate(clk);
+ clk->ops.get_rate = zynq_clk_periph_get_rate;
+ clk->ops.set_rate = zynq_clk_periph_set_rate;
+
+ return 0;
+}
+
+static void init_periph_clocks(void)
+{
+ zynq_clk_register_periph_clk(&clks[gem0_clk], &slcr_base->gem0_clk_ctrl,
+ "gem0", 1);
+ zynq_clk_register_periph_clk(&clks[gem1_clk], &slcr_base->gem1_clk_ctrl,
+ "gem1", 1);
+
+ zynq_clk_register_periph_clk(&clks[smc_clk], &slcr_base->smc_clk_ctrl,
+ "smc", 0);
+
+ zynq_clk_register_periph_clk(&clks[lqspi_clk],
+ &slcr_base->lqspi_clk_ctrl, "lqspi", 0);
+
+ zynq_clk_register_periph_clk(&clks[sdio0_clk],
+ &slcr_base->sdio_clk_ctrl, "sdio0", 0);
+ zynq_clk_register_periph_clk(&clks[sdio1_clk],
+ &slcr_base->sdio_clk_ctrl, "sdio1", 0);
+
+ zynq_clk_register_periph_clk(&clks[spi0_clk], &slcr_base->spi_clk_ctrl,
+ "spi0", 0);
+ zynq_clk_register_periph_clk(&clks[spi1_clk], &slcr_base->spi_clk_ctrl,
+ "spi1", 0);
+
+ zynq_clk_register_periph_clk(&clks[uart0_clk],
+ &slcr_base->uart_clk_ctrl, "uart0", 0);
+ zynq_clk_register_periph_clk(&clks[uart1_clk],
+ &slcr_base->uart_clk_ctrl, "uart1", 0);
+
+ zynq_clk_register_periph_clk(&clks[dbg_trc_clk],
+ &slcr_base->dbg_clk_ctrl, "dbg_trc", 0);
+ zynq_clk_register_periph_clk(&clks[dbg_apb_clk],
+ &slcr_base->dbg_clk_ctrl, "dbg_apb", 0);
+
+ zynq_clk_register_periph_clk(&clks[pcap_clk],
+ &slcr_base->pcap_clk_ctrl, "pcap", 0);
+
+ zynq_clk_register_periph_clk(&clks[fclk0_clk],
+ &slcr_base->fpga0_clk_ctrl, "fclk0", 1);
+ zynq_clk_register_periph_clk(&clks[fclk1_clk],
+ &slcr_base->fpga1_clk_ctrl, "fclk1", 1);
+ zynq_clk_register_periph_clk(&clks[fclk2_clk],
+ &slcr_base->fpga2_clk_ctrl, "fclk2", 1);
+ zynq_clk_register_periph_clk(&clks[fclk3_clk],
+ &slcr_base->fpga3_clk_ctrl, "fclk3", 1);
+}
+
+/**
+ * zynq_clk_register_aper_clk() - Set up a APER clock with the framework
+ * @clk: Pointer to struct clk for the clock
+ * @ctrl: Clock control register
+ * @name: PLL name
+ */
+static void zynq_clk_register_aper_clk(struct clk *clk, u32 *ctrl, char *name)
+{
+ clk->name = name;
+ clk->reg = ctrl;
+ clk->parent = cpu_1x_clk;
+ clk->frequency = zynq_clk_get_rate(clk->parent);
+}
+
+static void init_aper_clocks(void)
+{
+ zynq_clk_register_aper_clk(&clks[usb0_aper_clk],
+ &slcr_base->aper_clk_ctrl, "usb0_aper");
+ zynq_clk_register_aper_clk(&clks[usb1_aper_clk],
+ &slcr_base->aper_clk_ctrl, "usb1_aper");
+
+ zynq_clk_register_aper_clk(&clks[gem0_aper_clk],
+ &slcr_base->aper_clk_ctrl, "gem0_aper");
+ zynq_clk_register_aper_clk(&clks[gem1_aper_clk],
+ &slcr_base->aper_clk_ctrl, "gem1_aper");
+
+ zynq_clk_register_aper_clk(&clks[sdio0_aper_clk],
+ &slcr_base->aper_clk_ctrl, "sdio0_aper");
+ zynq_clk_register_aper_clk(&clks[sdio1_aper_clk],
+ &slcr_base->aper_clk_ctrl, "sdio1_aper");
+
+ zynq_clk_register_aper_clk(&clks[spi0_aper_clk],
+ &slcr_base->aper_clk_ctrl, "spi0_aper");
+ zynq_clk_register_aper_clk(&clks[spi1_aper_clk],
+ &slcr_base->aper_clk_ctrl, "spi1_aper");
+
+ zynq_clk_register_aper_clk(&clks[can0_aper_clk],
+ &slcr_base->aper_clk_ctrl, "can0_aper");
+ zynq_clk_register_aper_clk(&clks[can1_aper_clk],
+ &slcr_base->aper_clk_ctrl, "can1_aper");
+
+ zynq_clk_register_aper_clk(&clks[i2c0_aper_clk],
+ &slcr_base->aper_clk_ctrl, "i2c0_aper");
+ zynq_clk_register_aper_clk(&clks[i2c1_aper_clk],
+ &slcr_base->aper_clk_ctrl, "i2c1_aper");
+
+ zynq_clk_register_aper_clk(&clks[uart0_aper_clk],
+ &slcr_base->aper_clk_ctrl, "uart0_aper");
+ zynq_clk_register_aper_clk(&clks[uart1_aper_clk],
+ &slcr_base->aper_clk_ctrl, "uart1_aper");
+
+ zynq_clk_register_aper_clk(&clks[gpio_aper_clk],
+ &slcr_base->aper_clk_ctrl, "gpio_aper");
+
+ zynq_clk_register_aper_clk(&clks[lqspi_aper_clk],
+ &slcr_base->aper_clk_ctrl, "lqspi_aper");
+
+ zynq_clk_register_aper_clk(&clks[smc_aper_clk],
+ &slcr_base->aper_clk_ctrl, "smc_aper");
+}
+
+/**
+ * __zynq_clk_pll_get_rate() - Get PLL rate
+ * @addr: Address of the PLL's control register
+ * Returns the current PLL output rate.
+ */
+static unsigned long __zynq_clk_pll_get_rate(u32 *addr)
+{
+ u32 reg, mul, bypass;
+
+ reg = readl(addr);
+ bypass = reg & PLLCTRL_BPFORCE_MASK;
+ if (bypass)
+ mul = 1;
+ else
+ mul = (reg & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT;
+
+ return CONFIG_ZYNQ_PS_CLK_FREQ * mul;
+}
+
+/**
+ * zynq_clk_pll_get_rate() - Get PLL rate
+ * @pll: Handle of the PLL
+ * Returns the current clock rate of @pll.
+ */
+static unsigned long zynq_clk_pll_get_rate(struct clk *pll)
+{
+ return __zynq_clk_pll_get_rate(pll->reg);
+}
+
+/**
+ * zynq_clk_register_pll() - Set up a PLL with the framework
+ * @clk: Pointer to struct clk for the PLL
+ * @ctrl: PLL control register
+ * @name: PLL name
+ * @prate: PLL input clock rate
+ */
+static void zynq_clk_register_pll(struct clk *clk, u32 *ctrl, char *name,
+ unsigned long prate)
+{
+ clk->name = name;
+ clk->reg = ctrl;
+ clk->frequency = zynq_clk_pll_get_rate(clk);
+ clk->ops.get_rate = zynq_clk_pll_get_rate;
+}
+
+/**
+ * clkid_2_register() - Get clock control register
+ * @id: Clock identifier of one of the PLLs
+ * Returns the address of the requested PLL's control register.
+ */
+static u32 *clkid_2_register(enum zynq_clk id)
+{
+ switch (id) {
+ case armpll_clk:
+ return &slcr_base->arm_pll_ctrl;
+ case ddrpll_clk:
+ return &slcr_base->ddr_pll_ctrl;
+ case iopll_clk:
+ return &slcr_base->io_pll_ctrl;
+ default:
+ return &slcr_base->io_pll_ctrl;
+ }
+}
+
+/* API */
+/**
+ * zynq_clk_early_init() - Early init for the clock framework
+ *
+ * This function is called from before relocation and sets up the CPU clock
+ * frequency in the global data struct.
+ */
+void zynq_clk_early_init(void)
+{
+ u32 reg = readl(&slcr_base->arm_clk_ctrl);
+ u32 div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
+ u32 srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
+ enum zynq_clk parent = __zynq_clk_cpu_get_parent(srcsel);
+ u32 *pllreg = clkid_2_register(parent);
+ unsigned long prate = __zynq_clk_pll_get_rate(pllreg);
+
+ if (!div)
+ div = 1;
+
+ gd->cpu_clk = DIV_ROUND_CLOSEST(prate, div);
+}
+
+/**
+ * get_uart_clk() - Get UART input frequency
+ * @dev_index: UART ID
+ * Returns UART input clock frequency in Hz.
+ *
+ * Compared to zynq_clk_get_rate() this function is designed to work before
+ * relocation and can be called when the serial UART is set up.
+ */
+unsigned long get_uart_clk(int dev_index)
+{
+ u32 reg = readl(&slcr_base->uart_clk_ctrl);
+ u32 div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
+ u32 srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
+ enum zynq_clk parent = __zynq_clk_periph_get_parent(srcsel);
+ u32 *pllreg = clkid_2_register(parent);
+ unsigned long prate = __zynq_clk_pll_get_rate(pllreg);
+
+ if (!div)
+ div = 1;
+
+ return DIV_ROUND_CLOSEST(prate, div);
+}
+
+/**
+ * set_cpu_clk_info() - Initialize clock framework
+ * Always returns zero.
+ *
+ * This function is called from common code after relocation and sets up the
+ * clock framework. The framework must not be used before this function had been
+ * called.
+ */
+int set_cpu_clk_info(void)
+{
+ zynq_clk_register_pll(&clks[armpll_clk], &slcr_base->arm_pll_ctrl,
+ "armpll", CONFIG_ZYNQ_PS_CLK_FREQ);
+ zynq_clk_register_pll(&clks[ddrpll_clk], &slcr_base->ddr_pll_ctrl,
+ "ddrpll", CONFIG_ZYNQ_PS_CLK_FREQ);
+ zynq_clk_register_pll(&clks[iopll_clk], &slcr_base->io_pll_ctrl,
+ "iopll", CONFIG_ZYNQ_PS_CLK_FREQ);
+
+ init_ddr_clocks();
+ init_cpu_clocks();
+ init_periph_clocks();
+ init_aper_clocks();
+
+ gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
+ gd->bd->bi_dsp_freq = 0;
+
+ return 0;
+}
+
+/**
+ * zynq_clk_get_rate() - Get clock rate
+ * @clk: Clock identifier
+ * Returns the current clock rate of @clk on success or zero for an invalid
+ * clock id.
+ */
+unsigned long zynq_clk_get_rate(enum zynq_clk clk)
+{
+ if (clk < 0 || clk >= clk_max)
+ return 0;
+
+ return clks[clk].frequency;
+}
+
+/**
+ * zynq_clk_set_rate() - Set clock rate
+ * @clk: Clock identifier
+ * @rate: Requested clock rate
+ * Passes on the return value from the clock's set_rate() function or negative
+ * errno.
+ */
+int zynq_clk_set_rate(enum zynq_clk clk, unsigned long rate)
+{
+ if (clk < 0 || clk >= clk_max)
+ return -ENODEV;
+
+ if (clks[clk].ops.set_rate)
+ return clks[clk].ops.set_rate(&clks[clk], rate);
+
+ return -ENXIO;
+}
+
+/**
+ * zynq_clk_get_name() - Get clock name
+ * @clk: Clock identifier
+ * Returns the name of @clk.
+ */
+const char *zynq_clk_get_name(enum zynq_clk clk)
+{
+ return clks[clk].name;
+}
+
+/**
+ * soc_clk_dump() - Print clock frequencies
+ * Returns zero on success
+ *
+ * Implementation for the clk dump command.
+ */
+int soc_clk_dump(void)
+{
+ int i;
+
+ printf("clk\t\tfrequency\n");
+ for (i = 0; i < clk_max; i++) {
+ const char *name = zynq_clk_get_name(i);
+ if (name)
+ printf("%10s%20lu\n", name, zynq_clk_get_rate(i));
+ }
+
+ return 0;
+}
*/
#include <common.h>
#include <asm/io.h>
+#include <asm/arch/clk.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
int arch_cpu_init(void)
{
zynq_slcr_unlock();
-
+#ifndef CONFIG_SPL_BUILD
/* Device config APB, unlock the PCAP */
writel(0x757BDF0D, &devcfg_base->unlock);
writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
/* Urgent write, ports S2/S3 */
writel(0xC, &slcr_base->ddr_urgent);
#endif
-
+#endif
+ zynq_clk_early_init();
zynq_slcr_lock();
return 0;
while (1)
;
}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+}
+#endif
#include <asm/io.h>
#include <malloc.h>
#include <asm/arch/hardware.h>
+#include <asm/arch/clk.h>
#define SLCR_LOCK_MAGIC 0x767B
#define SLCR_UNLOCK_MAGIC 0xDF0D
}
/* Setup clk for network */
-void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk)
+void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate)
{
+ int ret;
+
zynq_slcr_unlock();
if (gem_id > 1) {
goto out;
}
+ ret = zynq_clk_set_rate(gem0_clk + gem_id, clk_rate);
+ if (ret)
+ goto out;
+
if (gem_id) {
- /* Set divisors for appropriate frequency in GEM_CLK_CTRL */
- writel(clk, &slcr_base->gem1_clk_ctrl);
/* Configure GEM_RCLK_CTRL */
- writel(rclk, &slcr_base->gem1_rclk_ctrl);
+ writel(1, &slcr_base->gem1_rclk_ctrl);
} else {
- /* Set divisors for appropriate frequency in GEM_CLK_CTRL */
- writel(clk, &slcr_base->gem0_clk_ctrl);
/* Configure GEM_RCLK_CTRL */
- writel(rclk, &slcr_base->gem0_rclk_ctrl);
+ writel(1, &slcr_base->gem0_rclk_ctrl);
}
udelay(100000);
out:
--- /dev/null
+/*
+ * (C) Copyright 2014 Xilinx, Inc. Michal Simek
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <spl.h>
+
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spl.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_init_f(ulong dummy)
+{
+ ps7_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* Set global data pointer. */
+ gd = &gdata;
+
+ preloader_console_init();
+ arch_cpu_init();
+ board_init_r(NULL, 0);
+}
+
+u32 spl_boot_device(void)
+{
+ u32 mode;
+
+ switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
+#ifdef CONFIG_SPL_SPI_SUPPORT
+ case ZYNQ_BM_QSPI:
+ puts("qspi boot\n");
+ mode = BOOT_DEVICE_SPI;
+ break;
+#endif
+#ifdef CONFIG_SPL_MMC_SUPPORT
+ case ZYNQ_BM_SD:
+ puts("mmc boot\n");
+ mode = BOOT_DEVICE_MMC1;
+ break;
+#endif
+ default:
+ puts("Unsupported boot mode selected\n");
+ hang();
+ }
+
+ return mode;
+}
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+u32 spl_boot_mode(void)
+{
+ return MMCSD_MODE_FAT;
+}
+#endif
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+ /* boot linux */
+ return 0;
+}
+#endif
#include <div64.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
+#include <asm/arch/clk.h>
DECLARE_GLOBAL_DATA_PTR;
#define TIMER_LOAD_VAL 0xFFFFFFFF
#define TIMER_PRESCALE 255
-#define TIMER_TICK_HZ (CONFIG_CPU_FREQ_HZ / 2 / TIMER_PRESCALE)
int timer_init(void)
{
(TIMER_PRESCALE << SCUTIMER_CONTROL_PRESCALER_SHIFT) |
SCUTIMER_CONTROL_ENABLE_MASK;
+ gd->arch.timer_rate_hz = (gd->cpu_clk / 2) / (TIMER_PRESCALE + 1);
+
/* Load the timer counter register */
writel(0xFFFFFFFF, &timer_base->load);
/* Reset time */
gd->arch.lastinc = readl(&timer_base->counter) /
- (TIMER_TICK_HZ / CONFIG_SYS_HZ);
+ (gd->arch.timer_rate_hz / CONFIG_SYS_HZ);
gd->arch.tbl = 0;
return 0;
{
ulong now;
- now = readl(&timer_base->counter) / (TIMER_TICK_HZ / CONFIG_SYS_HZ);
+ now = readl(&timer_base->counter) /
+ (gd->arch.timer_rate_hz / CONFIG_SYS_HZ);
if (gd->arch.lastinc >= now) {
/* Normal mode */
gd->arch.tbl += gd->arch.lastinc - now;
} else {
/* We have an overflow ... */
- gd->arch.tbl += gd->arch.lastinc + TIMER_LOAD_VAL - now;
+ gd->arch.tbl += gd->arch.lastinc + TIMER_LOAD_VAL - now + 1;
}
gd->arch.lastinc = now;
if (usec == 0)
return;
- countticks = lldiv(TIMER_TICK_HZ * usec, 1000000);
+ countticks = lldiv(((unsigned long long)gd->arch.timer_rate_hz * usec),
+ 1000000);
/* decrementing timer */
timeend = readl(&timer_base->counter) - countticks;
--- /dev/null
+/*
+ * Copyright (c) 2014 Xilinx, Inc. Michal Simek
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+ LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+ LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = ALIGN(4);
+ .text :
+ {
+ __image_copy_start = .;
+ CPUDIR/start.o (.text*)
+ *(.text*)
+ } > .sram
+
+ . = ALIGN(4);
+ .rodata : {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ } > .sram
+
+ . = ALIGN(4);
+ .data : {
+ *(.data*)
+ } > .sram
+
+ . = ALIGN(4);
+
+ . = .;
+
+ __image_copy_end = .;
+
+ _end = .;
+
+ /* Move BSS section to RAM because of FAT */
+ .bss (NOLOAD) : {
+ __bss_start = .;
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_end = .;
+ } > .sdram
+
+ /DISCARD/ : { *(.dynsym) }
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
+}
/*
- * (C) Copyright 2000-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
-OUTPUT_FORMAT("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
.text :
{
*(.__image_copy_start)
- arch/arm/cpu/ixp/start.o(.text*)
+ CPUDIR/start.o (.text*)
*(.text*)
}
*(.__rel_dyn_end)
}
- _end = .;
+ .end :
+ {
+ *(.__end)
+ }
+
+ _image_binary_end = .;
/*
* Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
. = ALIGN(4);
__bss_limit = .;
}
+
.bss_end __bss_limit (OVERLAY) : {
KEEP(*(.__bss_end));
}
- .dynsym _end : { *(.dynsym) }
- .dynbss : { *(.dynbss) }
- .dynstr : { *(.dynstr*) }
- .dynamic : { *(.dynamic*) }
- .hash : { *(.hash*) }
- .plt : { *(.plt*) }
- .interp : { *(.interp*) }
- .gnu : { *(.gnu*) }
- .ARM.exidx : { *(.ARM.exidx*) }
+ /*
+ * Zynq needs to discard more sections because the user
+ * is expected to pass this image on to tools for boot.bin
+ * generation that require them to be dropped.
+ */
+ /DISCARD/ : { *(.dynsym) }
+ /DISCARD/ : { *(.dynbss*) }
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
+ /DISCARD/ : { *(.ARM.exidx*) }
+ /DISCARD/ : { *(.gnu.linkonce.armexidx.*) }
}
#
PLATFORM_RELFLAGS += -fno-common -ffixed-x18
-# SEE README.arm-unaligned-accesses
-PF_NO_UNALIGNED := $(call cc-option, -mstrict-align)
-PLATFORM_NO_UNALIGNED := $(PF_NO_UNALIGNED)
-
PF_CPPFLAGS_ARMV8 := $(call cc-option, -march=armv8-a)
+PF_NO_UNALIGNED := $(call cc-option, -mstrict-align)
PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARMV8)
PLATFORM_CPPFLAGS += $(PF_NO_UNALIGNED)
. = ALIGN(4);
__image_copy_end = .;
- _end = .;
+
+ .end :
+ {
+ *(.__end)
+ } >.sram
.bss :
{
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-extra-y = start.o
-
-obj-y += cpu.o
-obj-$(CONFIG_USE_IRQ) += interrupts.o
-obj-y += timer.o
+++ /dev/null
-#
-# (C) Copyright 2002
-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
-# Marius Groeger <mgroeger@sysgo.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-BIG_ENDIAN = y
-
-PLATFORM_RELFLAGS += -mbig-endian
-
-PLATFORM_CPPFLAGS += -mbig-endian -march=armv5te -mtune=strongarm1100
-
-PLATFORM_LDFLAGS += -EB
-USE_PRIVATE_LIBGCC = yes
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * CPU specific code
- */
-
-#include <common.h>
-#include <command.h>
-#include <netdev.h>
-#include <asm/arch/ixp425.h>
-#include <asm/system.h>
-
-static void cache_flush(void);
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo (void)
-{
- unsigned long id;
- int speed = 0;
-
- asm ("mrc p15, 0, %0, c0, c0, 0":"=r" (id));
-
- puts("CPU: Intel IXP425 at ");
- switch ((id & 0x000003f0) >> 4) {
- case 0x1c:
- speed = 533;
- break;
-
- case 0x1d:
- speed = 400;
- break;
-
- case 0x1f:
- speed = 266;
- break;
- }
-
- if (speed)
- printf("%d MHz\n", speed);
- else
- puts("unknown revision\n");
-
- return 0;
-}
-#endif /* CONFIG_DISPLAY_CPUINFO */
-
-int cleanup_before_linux (void)
-{
- /*
- * this function is called just before we call linux
- * it prepares the processor for linux
- *
- * just disable everything that can disturb booting linux
- */
-
- disable_interrupts ();
-
- /* turn off I-cache */
- icache_disable();
- dcache_disable();
-
- /* flush I-cache */
- cache_flush();
-
- return 0;
-}
-
-/* flush I/D-cache */
-static void cache_flush (void)
-{
- unsigned long i = 0;
-
- asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
-}
-
-/* FIXME */
-/*
-void pci_init(void)
-{
- return;
-}
-*/
-
-int cpu_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_IXP4XX_NPE
- npe_initialize(bis);
-#endif
- return 0;
-}
+++ /dev/null
-/*
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/ixp425.h>
-#include <asm/proc-armv/ptrace.h>
-
-struct _irq_handler {
- void *m_data;
- void (*m_func)( void *data);
-};
-
-static struct _irq_handler IRQ_HANDLER[N_IRQS];
-
-static void default_isr(void *data)
-{
- printf("default_isr(): called for IRQ %d, Interrupt Status=%x PR=%x\n",
- (int)data, *IXP425_ICIP, *IXP425_ICIH);
-}
-
-static int next_irq(void)
-{
- return (((*IXP425_ICIH & 0x000000fc) >> 2) - 1);
-}
-
-void do_irq (struct pt_regs *pt_regs)
-{
- int irq = next_irq();
-
- IRQ_HANDLER[irq].m_func(IRQ_HANDLER[irq].m_data);
-}
-
-void irq_install_handler (int irq, interrupt_handler_t handle_irq, void *data)
-{
- if (irq >= N_IRQS || !handle_irq)
- return;
-
- IRQ_HANDLER[irq].m_data = data;
- IRQ_HANDLER[irq].m_func = handle_irq;
-}
-
-int arch_interrupt_init (void)
-{
- int i;
-
- /* install default interrupt handlers */
- for (i = 0; i < N_IRQS; i++)
- irq_install_handler(i, default_isr, (void *)i);
-
- /* configure interrupts for IRQ mode */
- *IXP425_ICLR = 0x00000000;
-
- return (0);
-}
+++ /dev/null
-/* vi: set ts=8 sw=8 noet: */
-/*
- * u-boot - Startup Code for XScale IXP
- *
- * Copyright (C) 2003 Kyle Harris <kharris@nexus-tech.net>
- *
- * Based on startup code example contained in the
- * Intel IXP4xx Programmer's Guide and past u-boot Start.S
- * samples.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <version.h>
-#include <asm/arch/ixp425.h>
-
-#define MMU_Control_M 0x001 /* Enable MMU */
-#define MMU_Control_A 0x002 /* Enable address alignment faults */
-#define MMU_Control_C 0x004 /* Enable cache */
-#define MMU_Control_W 0x008 /* Enable write-buffer */
-#define MMU_Control_P 0x010 /* Compatability: 32 bit code */
-#define MMU_Control_D 0x020 /* Compatability: 32 bit data */
-#define MMU_Control_L 0x040 /* Compatability: */
-#define MMU_Control_B 0x080 /* Enable Big-Endian */
-#define MMU_Control_S 0x100 /* Enable system protection */
-#define MMU_Control_R 0x200 /* Enable ROM protection */
-#define MMU_Control_I 0x1000 /* Enable Instruction cache */
-#define MMU_Control_X 0x2000 /* Set interrupt vectors at 0xFFFF0000 */
-#define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L)
-
-
-/*
- * Macro definitions
- */
- /* Delay a bit */
- .macro DELAY_FOR cycles, reg0
- ldr \reg0, =\cycles
- subs \reg0, \reg0, #1
- subne pc, pc, #0xc
- .endm
-
- /* wait for coprocessor write complete */
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
-
-.globl _start
-_start:
- ldr pc, _reset
- ldr pc, _undefined_instruction
- ldr pc, _software_interrupt
- ldr pc, _prefetch_abort
- ldr pc, _data_abort
- ldr pc, _not_used
- ldr pc, _irq
- ldr pc, _fiq
-
-_reset: .word reset
-_undefined_instruction: .word undefined_instruction
-_software_interrupt: .word software_interrupt
-_prefetch_abort: .word prefetch_abort
-_data_abort: .word data_abort
-_not_used: .word not_used
-_irq: .word irq
-_fiq: .word fiq
-
- .balignl 16,0xdeadbeef
-
-
-/*
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from memory!
- * - relocate armboot to ram
- * - setup stack
- * - jump to second stage
- */
-
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
- .word CONFIG_SPL_TEXT_BASE
-#else
- .word CONFIG_SYS_TEXT_BASE
-#endif
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
- .word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
- .word __bss_end - _start
-
-.globl _end_ofs
-_end_ofs:
- .word _end - _start
-
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
- .word 0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
- .word 0x0badc0de
-#endif
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
- .word 0x0badc0de
-
-/*
- * the actual reset code
- */
-
-reset:
- /* disable mmu, set big-endian */
- mov r0, #0xf8
- mcr p15, 0, r0, c1, c0, 0
- CPWAIT r0
-
- /* invalidate I & D caches & BTB */
- mcr p15, 0, r0, c7, c7, 0
- CPWAIT r0
-
- /* invalidate I & Data TLB */
- mcr p15, 0, r0, c8, c7, 0
- CPWAIT r0
-
- /* drain write and fill buffers */
- mcr p15, 0, r0, c7, c10, 4
- CPWAIT r0
-
- /* disable write buffer coalescing */
- mrc p15, 0, r0, c1, c0, 1
- orr r0, r0, #1
- mcr p15, 0, r0, c1, c0, 1
- CPWAIT r0
-
- /* set EXP CS0 to the optimum timing */
- ldr r1, =CONFIG_SYS_EXP_CS0
- ldr r2, =IXP425_EXP_CS0
- str r1, [r2]
-
- /* make sure flash is visible at 0 */
- mov r1, #CONFIG_SYS_SDR_CONFIG
- ldr r2, =IXP425_SDR_CONFIG
- str r1, [r2]
-
- /* disable refresh cycles */
- mov r1, #0
- ldr r3, =IXP425_SDR_REFRESH
- str r1, [r3]
-
- /* send nop command */
- mov r1, #3
- ldr r4, =IXP425_SDR_IR
- str r1, [r4]
- DELAY_FOR 0x4000, r0
-
- /* set SDRAM internal refresh val */
- ldr r1, =CONFIG_SYS_SDRAM_REFRESH_CNT
- str r1, [r3]
- DELAY_FOR 0x4000, r0
-
- /* send precharge-all command to close all open banks */
- mov r1, #2
- str r1, [r4]
- DELAY_FOR 0x4000, r0
-
- /* provide 8 auto-refresh cycles */
- mov r1, #4
- mov r5, #8
-111: str r1, [r4]
- DELAY_FOR 0x100, r0
- subs r5, r5, #1
- bne 111b
-
- /* set mode register in sdram */
- mov r1, #CONFIG_SYS_SDR_MODE_CONFIG
- str r1, [r4]
- DELAY_FOR 0x4000, r0
-
- /* send normal operation command */
- mov r1, #6
- str r1, [r4]
- DELAY_FOR 0x4000, r0
-
- /* invalidate I & D caches & BTB */
- mcr p15, 0, r0, c7, c7, 0
- CPWAIT r0
-
- /* invalidate I & Data TLB */
- mcr p15, 0, r0, c8, c7, 0
- CPWAIT r0
-
- /* drain write and fill buffers */
- mcr p15, 0, r0, c7, c10, 4
- CPWAIT r0
-
- /* remove flash mirror at 0x00000000 */
- ldr r2, =IXP425_EXP_CFG0
- ldr r1, [r2]
- bic r1, r1, #0x80000000
- str r1, [r2]
-
- /* invalidate I & Data TLB */
- mcr p15, 0, r0, c8, c7, 0
- CPWAIT r0
-
- /* enable I cache */
- mrc p15, 0, r0, c1, c0, 0
- orr r0, r0, #MMU_Control_I
- mcr p15, 0, r0, c1, c0, 0
- CPWAIT r0
-
- mrs r0,cpsr /* set the cpu to SVC32 mode */
- bic r0,r0,#0x1f /* (superviser mode, M=10011) */
- orr r0,r0,#0x13
- msr cpsr,r0
-
- bl _main
-
-/*------------------------------------------------------------------------------*/
-
- .globl c_runtime_cpu_setup
-c_runtime_cpu_setup:
-
- bx lr
-
-/****************************************************************************/
-/* */
-/* Interrupt handling */
-/* */
-/****************************************************************************/
-
-/* IRQ stack frame */
-
-#define S_FRAME_SIZE 72
-
-#define S_OLD_R0 68
-#define S_PSR 64
-#define S_PC 60
-#define S_LR 56
-#define S_SP 52
-
-#define S_IP 48
-#define S_FP 44
-#define S_R10 40
-#define S_R9 36
-#define S_R8 32
-#define S_R7 28
-#define S_R6 24
-#define S_R5 20
-#define S_R4 16
-#define S_R3 12
-#define S_R2 8
-#define S_R1 4
-#define S_R0 0
-
-#define MODE_SVC 0x13
-
- /* use bad_save_user_regs for abort/prefetch/undef/swi ... */
-
- .macro bad_save_user_regs
- sub sp, sp, #S_FRAME_SIZE
- stmia sp, {r0 - r12} /* Calling r0-r12 */
- add r8, sp, #S_PC
-
- ldr r2, IRQ_STACK_START_IN
- ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
- add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
-
- add r5, sp, #S_SP
- mov r1, lr
- stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
- mov r0, sp
- .endm
-
-
- /* use irq_save_user_regs / irq_restore_user_regs for */
- /* IRQ/FIQ handling */
-
- .macro irq_save_user_regs
- sub sp, sp, #S_FRAME_SIZE
- stmia sp, {r0 - r12} /* Calling r0-r12 */
- add r8, sp, #S_PC
- stmdb r8, {sp, lr}^ /* Calling SP, LR */
- str lr, [r8, #0] /* Save calling PC */
- mrs r6, spsr
- str r6, [r8, #4] /* Save CPSR */
- str r0, [r8, #8] /* Save OLD_R0 */
- mov r0, sp
- .endm
-
- .macro irq_restore_user_regs
- ldmia sp, {r0 - lr}^ @ Calling r0 - lr
- mov r0, r0
- ldr lr, [sp, #S_PC] @ Get PC
- add sp, sp, #S_FRAME_SIZE
- subs pc, lr, #4 @ return & move spsr_svc into cpsr
- .endm
-
- .macro get_bad_stack
- ldr r13, IRQ_STACK_START_IN @ setup our mode stack
-
- str lr, [r13] @ save caller lr / spsr
- mrs lr, spsr
- str lr, [r13, #4]
-
- mov r13, #MODE_SVC @ prepare SVC-Mode
- msr spsr_c, r13
- mov lr, pc
- movs pc, lr
- .endm
-
- .macro get_irq_stack @ setup IRQ stack
- ldr sp, IRQ_STACK_START
- .endm
-
- .macro get_fiq_stack @ setup FIQ stack
- ldr sp, FIQ_STACK_START
- .endm
-
-
-/****************************************************************************/
-/* */
-/* exception handlers */
-/* */
-/****************************************************************************/
-
- .align 5
-undefined_instruction:
- get_bad_stack
- bad_save_user_regs
- bl do_undefined_instruction
-
- .align 5
-software_interrupt:
- get_bad_stack
- bad_save_user_regs
- bl do_software_interrupt
-
- .align 5
-prefetch_abort:
- get_bad_stack
- bad_save_user_regs
- bl do_prefetch_abort
-
- .align 5
-data_abort:
- get_bad_stack
- bad_save_user_regs
- bl do_data_abort
-
- .align 5
-not_used:
- get_bad_stack
- bad_save_user_regs
- bl do_not_used
-
-#ifdef CONFIG_USE_IRQ
-
- .align 5
-irq:
- get_irq_stack
- irq_save_user_regs
- bl do_irq
- irq_restore_user_regs
-
- .align 5
-fiq:
- get_fiq_stack
- irq_save_user_regs /* someone ought to write a more */
- bl do_fiq /* effiction fiq_save_user_regs */
- irq_restore_user_regs
-
-#else
-
- .align 5
-irq:
- get_bad_stack
- bad_save_user_regs
- bl do_irq
-
- .align 5
-fiq:
- get_bad_stack
- bad_save_user_regs
- bl do_fiq
-
-#endif
-
-/****************************************************************************/
-/* */
-/* Reset function: Use Watchdog to reset */
-/* */
-/****************************************************************************/
-
- .align 5
-.globl reset_cpu
-
-reset_cpu:
- ldr r1, =0x482e
- ldr r2, =IXP425_OSWK
- str r1, [r2]
- ldr r1, =0x0fff
- ldr r2, =IXP425_OSWT
- str r1, [r2]
- ldr r1, =0x5
- ldr r2, =IXP425_OSWE
- str r1, [r2]
- b reset_endless
-
-reset_endless:
- b reset_endless
+++ /dev/null
-/*
- * (C) Copyright 2010
- * Michael Schwingen, michael@schwingen.org
- *
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/ixp425.h>
-#include <asm/io.h>
-#include <div64.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * The IXP42x time-stamp timer runs at 2*OSC_IN (66.666MHz when using a
- * 33.333MHz crystal).
- */
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
- tick *= CONFIG_SYS_HZ;
- do_div(tick, CONFIG_IXP425_TIMER_CLK);
- return tick;
-}
-
-static inline unsigned long long time_to_tick(unsigned long long time)
-{
- time *= CONFIG_IXP425_TIMER_CLK;
- do_div(time, CONFIG_SYS_HZ);
- return time;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long us)
-{
- us = us * CONFIG_IXP425_TIMER_CLK + 999999;
- do_div(us, 1000000);
- return us;
-}
-
-unsigned long long get_ticks(void)
-{
- ulong now = readl(IXP425_OSTS_B);
-
- if (readl(IXP425_OSST) & IXP425_OSST_TIMER_TS_PEND) {
- /* rollover of timestamp timer register */
- gd->arch.timestamp += (0xFFFFFFFF - gd->arch.lastinc) + now + 1;
- writel(IXP425_OSST_TIMER_TS_PEND, IXP425_OSST);
- } else {
- /* move stamp forward with absolut diff ticks */
- gd->arch.timestamp += (now - gd->arch.lastinc);
- }
- gd->arch.lastinc = now;
- return gd->arch.timestamp;
-}
-
-
-void reset_timer_masked(void)
-{
- /* capture current timestamp counter */
- gd->arch.lastinc = readl(IXP425_OSTS_B);
- /* start "advancing" time stamp from 0 */
- gd->arch.timestamp = 0;
-}
-
-ulong get_timer_masked(void)
-{
- return tick_to_time(get_ticks());
-}
-
-ulong get_timer(ulong base)
-{
- return get_timer_masked() - base;
-}
-
-/* delay x useconds AND preserve advance timestamp value */
-void __udelay(unsigned long usec)
-{
- unsigned long long tmp;
-
- tmp = get_ticks() + us_to_tick(usec);
-
- while (get_ticks() < tmp)
- ;
-}
-
-int timer_init(void)
-{
- writel(IXP425_OSST_TIMER_TS_PEND, IXP425_OSST);
- return 0;
-}
#
#ifdef CONFIG_SPL_BUILD
-OBJCFLAGS += -j .text.0 -j .text.1
+OBJCOPYFLAGS += -j .text.0 -j .text.1
#endif
*************************************************************************
*/
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
- .word CONFIG_SPL_TEXT_BASE
-#else
- .word CONFIG_SYS_TEXT_BASE
-#endif
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
- .word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
- .word __bss_end - _start
-
-.globl _end_ofs
-_end_ofs:
- .word _end - _start
-
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
#ifdef CONFIG_SPL_BUILD
.align 5
do_hang:
- ldr sp, _TEXT_BASE /* use 32 words about stack */
bl hang /* hang and never return */
#else /* !CONFIG_SPL_BUILD */
.align 5
*************************************************************************
*/
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
- .word CONFIG_SPL_TEXT_BASE
-#else
- .word CONFIG_SYS_TEXT_BASE
-#endif
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
- .word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
- .word __bss_end - _start
-
-.globl _end_ofs
-_end_ofs:
- .word _end - _start
-
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
#
obj-y += lowlevel_init.o
-obj-y += ap.o board.o sys_info.o clock.o cache.o
+obj-y += ap.o board.o clock.o cache.o
+obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o
/*
-* (C) Copyright 2010-2011
+* (C) Copyright 2010-2014
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
/*
* This is undocumented, Chip ID is bits 15:8 of the register
* APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
- * Tegra30, and 0x35 for T114.
+ * Tegra30, 0x35 for T114, and 0x40 for Tegra124.
*/
rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
debug("%s: CHIPID is 0x%02X\n", __func__, rev);
case SKU_ID_T33:
case SKU_ID_T30:
case SKU_ID_TM30MQS_P_A3:
+ default:
return TEGRA_SOC_T30;
}
break;
switch (sku_id) {
case SKU_ID_T114_ENG:
case SKU_ID_T114_1:
+ default:
return TEGRA_SOC_T114;
}
break;
+ case CHIPID_TEGRA124:
+ switch (sku_id) {
+ case SKU_ID_T124_ENG:
+ default:
+ return TEGRA_SOC_T124;
+ }
+ break;
}
+
/* unknown chip/sku id */
printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n",
__func__, chip_id, sku_id);
* ODMDATA is stored in the BCT in IRAM by the BootROM.
* The BCT start and size are stored in the BIT in IRAM.
* Read the data @ bct_start + (bct_size - 12). This works
- * on T20 and T30 BCTs, which are locked down. If this changes
- * in new chips (T114, etc.), we can revisit this algorithm.
+ * on BCTs for currently supported SoCs, which are locked down.
+ * If this changes in new chips, we can revisit this algorithm.
*/
u32 bct_start, odmdata;
/*
- * (C) Copyright 2010,2011
+ * (C) Copyright 2010-2014
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
-1,
-1,
-1,
-#else /* Tegra114 */
+#elif defined(CONFIG_TEGRA114)
-1,
-1,
-1,
FUNCMUX_UART4_GMI, /* UARTD */
-1,
+#else /* Tegra124 */
+ FUNCMUX_UART1_KBC, /* UARTA */
+ -1,
+ -1,
+ FUNCMUX_UART4_GPIO, /* UARTD */
+ -1,
#endif
};
/*
- * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
void config_cache(void)
{
- struct apb_misc_gp_ctlr *gp =
- (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
u32 reg = 0;
/* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */
"orr r0, r0, #0x41\n"
"mcr p15, 0, r0, c1, c0, 1\n");
- /* Currently, only T114 needs this L2 cache change to boot Linux */
- reg = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK);
- if (reg != (CHIPID_TEGRA114 << HIDREV_CHIPID_SHIFT))
+ /* Currently, only Tegra114+ needs this L2 cache change to boot Linux */
+ if (tegra_get_chip() < CHIPID_TEGRA114)
return;
+
/*
* Systems with an architectural L2 cache must not use the PL310.
* Config L2CTLR here for a data RAM latency of 3 cycles.
/*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
value = readl(reg);
- value &= ~OUT_CLK_SOURCE_MASK;
- value |= source << OUT_CLK_SOURCE_SHIFT;
+ value &= ~OUT_CLK_SOURCE_31_30_MASK;
+ value |= source << OUT_CLK_SOURCE_31_30_SHIFT;
value &= ~OUT_CLK_DIVISOR_MASK;
value |= divisor << OUT_CLK_DIVISOR_SHIFT;
{
u32 *reg = get_periph_source_reg(periph_id);
- clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK,
- source << OUT_CLK_SOURCE_SHIFT);
+ clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
+ source << OUT_CLK_SOURCE_31_30_SHIFT);
}
/**
/* work out the source clock and set it */
if (source < 0)
return -1;
- if (mux_bits == 4) {
- clrsetbits_le32(reg, OUT_CLK_SOURCE4_MASK,
- source << OUT_CLK_SOURCE4_SHIFT);
- } else {
- clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK,
- source << OUT_CLK_SOURCE_SHIFT);
+
+ switch (mux_bits) {
+ case MASK_BITS_31_30:
+ clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
+ source << OUT_CLK_SOURCE_31_30_SHIFT);
+ break;
+
+ case MASK_BITS_31_29:
+ clrsetbits_le32(reg, OUT_CLK_SOURCE_31_29_MASK,
+ source << OUT_CLK_SOURCE_31_29_SHIFT);
+ break;
+
+ case MASK_BITS_31_28:
+ clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK,
+ source << OUT_CLK_SOURCE_31_28_SHIFT);
+ break;
+
+ default:
+ return -1;
}
+
udelay(2);
return 0;
}
/* Do any special system timer/TSC setup */
arch_timer_init();
}
+
+static void set_avp_clock_source(u32 src)
+{
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 val;
+
+ val = (src << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
+ (src << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
+ (src << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
+ (src << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
+ (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
+ writel(val, &clkrst->crc_sclk_brst_pol);
+ udelay(3);
+}
+
+/*
+ * This function is useful on Tegra30, and any later SoCs that have compatible
+ * PLLP configuration registers.
+ */
+void tegra30_set_up_pllp(void)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 reg;
+
+ /*
+ * Based on the Tegra TRM, the system clock (which is the AVP clock) can
+ * run up to 275MHz. On power on, the default sytem clock source is set
+ * to PLLP_OUT0. This function sets PLLP's (hence PLLP_OUT0's) rate to
+ * 408MHz which is beyond system clock's upper limit.
+ *
+ * The fix is to set the system clock to CLK_M before initializing PLLP,
+ * and then switch back to PLLP_OUT4, which has an appropriate divider
+ * configured, after PLLP has been configured
+ */
+ set_avp_clock_source(SCLK_SOURCE_CLKM);
+
+ /*
+ * PLLP output frequency set to 408Mhz
+ * PLLC output frequency set to 228Mhz
+ */
+ switch (clock_get_osc_freq()) {
+ case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
+ clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
+ clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
+ break;
+
+ case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
+ clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
+ clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
+ break;
+
+ case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
+ clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
+ clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
+ break;
+ case CLOCK_OSC_FREQ_19_2:
+ default:
+ /*
+ * These are not supported. It is too early to print a
+ * message and the UART likely won't work anyway due to the
+ * oscillator being wrong.
+ */
+ break;
+ }
+
+ /* Set PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
+
+ /* OUT1, 2 */
+ /* Assert RSTN before enable */
+ reg = PLLP_OUT2_RSTN_EN | PLLP_OUT1_RSTN_EN;
+ writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
+ /* Set divisor and reenable */
+ reg = (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO)
+ | PLLP_OUT2_OVR | PLLP_OUT2_CLKEN | PLLP_OUT2_RSTN_DIS
+ | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO)
+ | PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS;
+ writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
+
+ /* OUT3, 4 */
+ /* Assert RSTN before enable */
+ reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN;
+ writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
+ /* Set divisor and reenable */
+ reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO)
+ | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS
+ | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO)
+ | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS;
+ writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
+
+ set_avp_clock_source(SCLK_SOURCE_PLLP_OUT4);
+}
#include <common.h>
#include <linux/ctype.h>
-#ifdef CONFIG_DISPLAY_CPUINFO
void upstring(char *s)
{
while (*s) {
/* TBD: Add printf of major/minor rev info, stepping, etc. */
return 0;
}
-#endif /* CONFIG_DISPLAY_CPUINFO */
/*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
CLOCK_MAX_MUX = 8 /* number of source options for each clock */
};
-enum {
- MASK_BITS_31_30 = 2, /* num of bits used to specify clock source */
- MASK_BITS_31_29,
- MASK_BITS_29_28,
-};
-
/*
* Clock source mux for each clock type. This just converts our enum into
* a list of mux sources for use by the code.
MASK_BITS_31_29},
{ CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_29_28}
+ MASK_BITS_31_28}
};
/*
struct clk_rst_ctlr *clkrst =
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ tegra30_set_up_pllp();
+
/*
- * PLLP output frequency set to 408Mhz
* PLLC output frequency set to 600Mhz
* PLLD output frequency set to 925Mhz
*/
switch (clock_get_osc_freq()) {
case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
- clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
break;
case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
- clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
break;
case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
- clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
break;
--- /dev/null
+#
+# (C) Copyright 2013-2014
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += clock.o
+obj-y += funcmux.o
+obj-y += pinmux.o
--- /dev/null
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Tegra124 Clock control functions */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sysctr.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/timer.h>
+#include <div64.h>
+#include <fdtdec.h>
+
+/*
+ * Clock types that we can use as a source. The Tegra124 has muxes for the
+ * peripheral clocks, and in most cases there are four options for the clock
+ * source. This gives us a clock 'type' and exploits what commonality exists
+ * in the device.
+ *
+ * Letters are obvious, except for T which means CLK_M, and S which means the
+ * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
+ * datasheet) and PLL_M are different things. The former is the basic
+ * clock supplied to the SOC from an external oscillator. The latter is the
+ * memory clock PLL.
+ *
+ * See definitions in clock_id in the header file.
+ */
+enum clock_type_id {
+ CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
+ CLOCK_TYPE_MCPA, /* and so on */
+ CLOCK_TYPE_MCPT,
+ CLOCK_TYPE_PCM,
+ CLOCK_TYPE_PCMT,
+ CLOCK_TYPE_PDCT,
+ CLOCK_TYPE_ACPT,
+ CLOCK_TYPE_ASPTE,
+ CLOCK_TYPE_PMDACD2T,
+ CLOCK_TYPE_PCST,
+
+ CLOCK_TYPE_PC2CC3M,
+ CLOCK_TYPE_PC2CC3S_T,
+ CLOCK_TYPE_PC2CC3M_T,
+ CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */
+ CLOCK_TYPE_MC2CC3P_A,
+ CLOCK_TYPE_M,
+ CLOCK_TYPE_MCPTM2C2C3,
+ CLOCK_TYPE_PC2CC3T_S,
+ CLOCK_TYPE_AC2CC3P_TS2,
+
+ CLOCK_TYPE_COUNT,
+ CLOCK_TYPE_NONE = -1, /* invalid clock type */
+};
+
+enum {
+ CLOCK_MAX_MUX = 8 /* number of source options for each clock */
+};
+
+/*
+ * Clock source mux for each clock type. This just converts our enum into
+ * a list of mux sources for use by the code.
+ *
+ * Note:
+ * The extra column in each clock source array is used to store the mask
+ * bits in its register for the source.
+ */
+#define CLK(x) CLOCK_ID_ ## x
+static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
+ { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
+ CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_29},
+ { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO),
+ CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
+ MASK_BITS_31_29},
+ { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_28},
+
+ /* Additional clock types on Tegra114+ */
+ /* CLOCK_TYPE_PC2CC3M */
+ { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
+ CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_29},
+ /* CLOCK_TYPE_PC2CC3S_T */
+ { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
+ CLK(SFROM32KHZ), CLK(NONE), CLK(OSC), CLK(NONE),
+ MASK_BITS_31_29},
+ /* CLOCK_TYPE_PC2CC3M_T */
+ { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
+ CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
+ MASK_BITS_31_29},
+ /* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */
+ { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
+ CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
+ MASK_BITS_31_29},
+ /* CLOCK_TYPE_MC2CC3P_A */
+ { CLK(MEMORY), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
+ CLK(PERIPH), CLK(NONE), CLK(AUDIO), CLK(NONE),
+ MASK_BITS_31_29},
+ /* CLOCK_TYPE_M */
+ { CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ /* CLOCK_TYPE_MCPTM2C2C3 */
+ { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
+ CLK(MEMORY2), CLK(CGENERAL2), CLK(CGENERAL3), CLK(NONE),
+ MASK_BITS_31_29},
+ /* CLOCK_TYPE_PC2CC3T_S */
+ { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
+ CLK(OSC), CLK(NONE), CLK(SFROM32KHZ), CLK(NONE),
+ MASK_BITS_31_29},
+ /* CLOCK_TYPE_AC2CC3P_TS2 */
+ { CLK(AUDIO), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
+ CLK(PERIPH), CLK(NONE), CLK(OSC), CLK(SRC2),
+ MASK_BITS_31_29},
+};
+
+/*
+ * Clock type for each peripheral clock source. We put the name in each
+ * record just so it is easy to match things up
+ */
+#define TYPE(name, type) type
+static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
+ /* 0x00 */
+ TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
+ TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
+ TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
+ TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PC2CC3M),
+ TYPE(PERIPHC_PWM, CLOCK_TYPE_PC2CC3S_T),
+ TYPE(PERIPHC_05h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_SBC2, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_SBC3, CLOCK_TYPE_PC2CC3M_T),
+
+ /* 0x08 */
+ TYPE(PERIPHC_08h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_I2C1, CLOCK_TYPE_PC2CC3M_T16),
+ TYPE(PERIPHC_I2C5, CLOCK_TYPE_PC2CC3M_T16),
+ TYPE(PERIPHC_0bh, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_0ch, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_SBC1, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T),
+ TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T),
+
+ /* 0x10 */
+ TYPE(PERIPHC_10h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_11h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_VI, CLOCK_TYPE_MC2CC3P_A),
+ TYPE(PERIPHC_13h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_16h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_17h, CLOCK_TYPE_NONE),
+
+ /* 0x18 */
+ TYPE(PERIPHC_18h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_VFIR, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_1Bh, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_1Ch, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_HSI, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_UART1, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_UART2, CLOCK_TYPE_PC2CC3M_T),
+
+ /* 0x20 */
+ TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MC2CC3P_A),
+ TYPE(PERIPHC_21h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_22h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_HDMI, CLOCK_TYPE_PMDACD2T),
+ TYPE(PERIPHC_24h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_25h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_I2C2, CLOCK_TYPE_PC2CC3M_T16),
+ TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPTM2C2C3),
+
+ /* 0x28 */
+ TYPE(PERIPHC_UART3, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_29h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_VI_SENSOR, CLOCK_TYPE_MC2CC3P_A),
+ TYPE(PERIPHC_2bh, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_2ch, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_SBC4, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_I2C3, CLOCK_TYPE_PC2CC3M_T16),
+ TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PC2CC3M_T),
+
+ /* 0x30 */
+ TYPE(PERIPHC_UART4, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_UART5, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_VDE, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_OWR, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_NOR, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_CSITE, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT),
+ TYPE(PERIPHC_DTV, CLOCK_TYPE_NONE),
+
+ /* 0x38 */
+ TYPE(PERIPHC_38h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_39h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_3ah, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_3bh, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_MSENC, CLOCK_TYPE_MC2CC3P_A),
+ TYPE(PERIPHC_TSEC, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_3eh, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_OSC, CLOCK_TYPE_NONE),
+
+ /* 0x40 */
+ TYPE(PERIPHC_40h, CLOCK_TYPE_NONE), /* start with 0x3b0 */
+ TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PC2CC3T_S),
+ TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT),
+ TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT),
+ TYPE(PERIPHC_I2C4, CLOCK_TYPE_PC2CC3M_T16),
+ TYPE(PERIPHC_SBC5, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_SBC6, CLOCK_TYPE_PC2CC3M_T),
+
+ /* 0x48 */
+ TYPE(PERIPHC_AUDIO, CLOCK_TYPE_AC2CC3P_TS2),
+ TYPE(PERIPHC_49h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_DAM0, CLOCK_TYPE_AC2CC3P_TS2),
+ TYPE(PERIPHC_DAM1, CLOCK_TYPE_AC2CC3P_TS2),
+ TYPE(PERIPHC_DAM2, CLOCK_TYPE_AC2CC3P_TS2),
+ TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PC2CC3S_T),
+ TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
+
+ /* 0x50 */
+ TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
+ TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
+ TYPE(PERIPHC_52h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PC2CC3S_T),
+ TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_55h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_56h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_57h, CLOCK_TYPE_NONE),
+
+ /* 0x58 */
+ TYPE(PERIPHC_58h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_59h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_5ah, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_5bh, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_HDA, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_5fh, CLOCK_TYPE_NONE),
+
+ /* 0x60 */
+ TYPE(PERIPHC_XUSB_CORE_HOST, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_XUSB_FALCON, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_XUSB_FS, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_XUSB_CORE_DEV, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_XUSB_SS, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_CILAB, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_CILCD, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_CILE, CLOCK_TYPE_NONE),
+
+ /* 0x68 */
+ TYPE(PERIPHC_DSIA_LP, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_DSIB_LP, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_ENTROPY, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_DVFS_REF, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_DVFS_SOC, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_TRACECLKIN, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_ADX0, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_AMX0, CLOCK_TYPE_NONE),
+
+ /* 0x70 */
+ TYPE(PERIPHC_EMC_LATENCY, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_SOC_THERM, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_72h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_73h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_74h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_75h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_VI_SENSOR2, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_I2C6, CLOCK_TYPE_PC2CC3M_T16),
+
+ /* 0x78 */
+ TYPE(PERIPHC_78h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_EMC_DLL, CLOCK_TYPE_MCPTM2C2C3),
+ TYPE(PERIPHC_HDMI_AUDIO, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_CLK72MHZ, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_ADX1, CLOCK_TYPE_AC2CC3P_TS2),
+ TYPE(PERIPHC_AMX1, CLOCK_TYPE_AC2CC3P_TS2),
+ TYPE(PERIPHC_VIC, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_7Fh, CLOCK_TYPE_NONE),
+};
+
+/*
+ * This array translates a periph_id to a periphc_internal_id
+ *
+ * Not present/matched up:
+ * uint vi_sensor; _VI_SENSOR_0, 0x1A8
+ * SPDIF - which is both 0x08 and 0x0c
+ *
+ */
+#define NONE(name) (-1)
+#define OFFSET(name, value) PERIPHC_ ## name
+static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
+ /* Low word: 31:0 */
+ NONE(CPU),
+ NONE(COP),
+ NONE(TRIGSYS),
+ NONE(ISPB),
+ NONE(RESERVED4),
+ NONE(TMR),
+ PERIPHC_UART1,
+ PERIPHC_UART2, /* and vfir 0x68 */
+
+ /* 8 */
+ NONE(GPIO),
+ PERIPHC_SDMMC2,
+ PERIPHC_SPDIF_IN,
+ PERIPHC_I2S1,
+ PERIPHC_I2C1,
+ NONE(RESERVED13),
+ PERIPHC_SDMMC1,
+ PERIPHC_SDMMC4,
+
+ /* 16 */
+ NONE(TCW),
+ PERIPHC_PWM,
+ PERIPHC_I2S2,
+ NONE(RESERVED19),
+ PERIPHC_VI,
+ NONE(RESERVED21),
+ NONE(USBD),
+ NONE(ISP),
+
+ /* 24 */
+ NONE(RESERVED24),
+ NONE(RESERVED25),
+ PERIPHC_DISP2,
+ PERIPHC_DISP1,
+ PERIPHC_HOST1X,
+ NONE(VCP),
+ PERIPHC_I2S0,
+ NONE(CACHE2),
+
+ /* Middle word: 63:32 */
+ NONE(MEM),
+ NONE(AHBDMA),
+ NONE(APBDMA),
+ NONE(RESERVED35),
+ NONE(RESERVED36),
+ NONE(STAT_MON),
+ NONE(RESERVED38),
+ NONE(FUSE),
+
+ /* 40 */
+ NONE(KFUSE),
+ PERIPHC_SBC1, /* SBCx = SPIx */
+ PERIPHC_NOR,
+ NONE(RESERVED43),
+ PERIPHC_SBC2,
+ NONE(XIO),
+ PERIPHC_SBC3,
+ PERIPHC_I2C5,
+
+ /* 48 */
+ NONE(DSI),
+ NONE(RESERVED49),
+ PERIPHC_HSI,
+ PERIPHC_HDMI,
+ NONE(CSI),
+ NONE(RESERVED53),
+ PERIPHC_I2C2,
+ PERIPHC_UART3,
+
+ /* 56 */
+ NONE(MIPI_CAL),
+ PERIPHC_EMC,
+ NONE(USB2),
+ NONE(USB3),
+ NONE(RESERVED60),
+ PERIPHC_VDE,
+ NONE(BSEA),
+ NONE(BSEV),
+
+ /* Upper word 95:64 */
+ NONE(RESERVED64),
+ PERIPHC_UART4,
+ PERIPHC_UART5,
+ PERIPHC_I2C3,
+ PERIPHC_SBC4,
+ PERIPHC_SDMMC3,
+ NONE(PCIE),
+ PERIPHC_OWR,
+
+ /* 72 */
+ NONE(AFI),
+ PERIPHC_CSITE,
+ NONE(PCIEXCLK),
+ NONE(AVPUCQ),
+ NONE(LA),
+ NONE(TRACECLKIN),
+ NONE(SOC_THERM),
+ NONE(DTV),
+
+ /* 80 */
+ NONE(RESERVED80),
+ PERIPHC_I2CSLOW,
+ NONE(DSIB),
+ PERIPHC_TSEC,
+ NONE(RESERVED84),
+ NONE(RESERVED85),
+ NONE(RESERVED86),
+ NONE(EMUCIF),
+
+ /* 88 */
+ NONE(RESERVED88),
+ NONE(XUSB_HOST),
+ NONE(RESERVED90),
+ PERIPHC_MSENC,
+ NONE(RESERVED92),
+ NONE(RESERVED93),
+ NONE(RESERVED94),
+ NONE(XUSB_DEV),
+
+ /* V word: 31:0 */
+ NONE(CPUG),
+ NONE(CPULP),
+ NONE(V_RESERVED2),
+ PERIPHC_MSELECT,
+ NONE(V_RESERVED4),
+ PERIPHC_I2S3,
+ PERIPHC_I2S4,
+ PERIPHC_I2C4,
+
+ /* 104 */
+ PERIPHC_SBC5,
+ PERIPHC_SBC6,
+ PERIPHC_AUDIO,
+ NONE(APBIF),
+ PERIPHC_DAM0,
+ PERIPHC_DAM1,
+ PERIPHC_DAM2,
+ PERIPHC_HDA2CODEC2X,
+
+ /* 112 */
+ NONE(ATOMICS),
+ NONE(V_RESERVED17),
+ NONE(V_RESERVED18),
+ NONE(V_RESERVED19),
+ NONE(V_RESERVED20),
+ NONE(V_RESERVED21),
+ NONE(V_RESERVED22),
+ PERIPHC_ACTMON,
+
+ /* 120 */
+ NONE(EXTPERIPH1),
+ NONE(EXTPERIPH2),
+ NONE(EXTPERIPH3),
+ NONE(OOB),
+ PERIPHC_SATA,
+ PERIPHC_HDA,
+ NONE(TZRAM),
+ NONE(SE),
+
+ /* W word: 31:0 */
+ NONE(HDA2HDMICODEC),
+ NONE(SATACOLD),
+ NONE(W_RESERVED2),
+ NONE(W_RESERVED3),
+ NONE(W_RESERVED4),
+ NONE(W_RESERVED5),
+ NONE(W_RESERVED6),
+ NONE(W_RESERVED7),
+
+ /* 136 */
+ NONE(CEC),
+ NONE(W_RESERVED9),
+ NONE(W_RESERVED10),
+ NONE(W_RESERVED11),
+ NONE(W_RESERVED12),
+ NONE(W_RESERVED13),
+ NONE(XUSB_PADCTL),
+ NONE(W_RESERVED15),
+
+ /* 144 */
+ NONE(W_RESERVED16),
+ NONE(W_RESERVED17),
+ NONE(W_RESERVED18),
+ NONE(W_RESERVED19),
+ NONE(W_RESERVED20),
+ NONE(ENTROPY),
+ NONE(DDS),
+ NONE(W_RESERVED23),
+
+ /* 152 */
+ NONE(DP2),
+ NONE(AMX0),
+ NONE(ADX0),
+ NONE(DVFS),
+ NONE(XUSB_SS),
+ NONE(W_RESERVED29),
+ NONE(W_RESERVED30),
+ NONE(W_RESERVED31),
+
+ /* X word: 31:0 */
+ NONE(SPARE),
+ NONE(X_RESERVED1),
+ NONE(X_RESERVED2),
+ NONE(X_RESERVED3),
+ NONE(CAM_MCLK),
+ NONE(CAM_MCLK2),
+ PERIPHC_I2C6,
+ NONE(X_RESERVED7),
+
+ /* 168 */
+ NONE(X_RESERVED8),
+ NONE(X_RESERVED9),
+ NONE(X_RESERVED10),
+ NONE(VIM2_CLK),
+ NONE(X_RESERVED12),
+ NONE(X_RESERVED13),
+ NONE(EMC_DLL),
+ NONE(X_RESERVED15),
+
+ /* 176 */
+ NONE(HDMI_AUDIO),
+ NONE(CLK72MHZ),
+ NONE(VIC),
+ NONE(X_RESERVED19),
+ NONE(ADX1),
+ NONE(DPAUX),
+ NONE(SOR0),
+ NONE(X_RESERVED23),
+
+ /* 184 */
+ NONE(GPU),
+ NONE(AMX1),
+ NONE(X_RESERVED26),
+ NONE(X_RESERVED27),
+ NONE(X_RESERVED28),
+ NONE(X_RESERVED29),
+ NONE(X_RESERVED30),
+ NONE(X_RESERVED31),
+};
+
+/*
+ * Get the oscillator frequency, from the corresponding hardware configuration
+ * field. Note that Tegra30+ support 3 new higher freqs, but we map back
+ * to the old T20 freqs. Support for the higher oscillators is TBD.
+ */
+enum clock_osc_freq clock_get_osc_freq(void)
+{
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 reg;
+
+ reg = readl(&clkrst->crc_osc_ctrl);
+ reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
+
+ if (reg & 1) /* one of the newer freqs */
+ printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
+
+ return reg >> 2; /* Map to most common (T20) freqs */
+}
+
+/* Returns a pointer to the clock source register for a peripheral */
+u32 *get_periph_source_reg(enum periph_id periph_id)
+{
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ enum periphc_internal_id internal_id;
+
+ /* Coresight is a special case */
+ if (periph_id == PERIPH_ID_CSI)
+ return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
+
+ assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
+ internal_id = periph_id_to_internal_id[periph_id];
+ assert(internal_id != -1);
+ if (internal_id >= PERIPHC_VW_FIRST) {
+ internal_id -= PERIPHC_VW_FIRST;
+ return &clkrst->crc_clk_src_vw[internal_id];
+ } else {
+ return &clkrst->crc_clk_src[internal_id];
+ }
+}
+
+/**
+ * Given a peripheral ID and the required source clock, this returns which
+ * value should be programmed into the source mux for that peripheral.
+ *
+ * There is special code here to handle the one source type with 5 sources.
+ *
+ * @param periph_id peripheral to start
+ * @param source PLL id of required parent clock
+ * @param mux_bits Set to number of bits in mux register: 2 or 4
+ * @param divider_bits Set to number of divider bits (8 or 16)
+ * @return mux value (0-4, or -1 if not found)
+ */
+int get_periph_clock_source(enum periph_id periph_id,
+ enum clock_id parent, int *mux_bits, int *divider_bits)
+{
+ enum clock_type_id type;
+ enum periphc_internal_id internal_id;
+ int mux;
+
+ assert(clock_periph_id_isvalid(periph_id));
+
+ internal_id = periph_id_to_internal_id[periph_id];
+ assert(periphc_internal_id_isvalid(internal_id));
+
+ type = clock_periph_type[internal_id];
+ assert(clock_type_id_isvalid(type));
+
+ *mux_bits = clock_source[type][CLOCK_MAX_MUX];
+
+ if (type == CLOCK_TYPE_PC2CC3M_T16)
+ *divider_bits = 16;
+ else
+ *divider_bits = 8;
+
+ for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
+ if (clock_source[type][mux] == parent)
+ return mux;
+
+ /* if we get here, either us or the caller has made a mistake */
+ printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
+ parent);
+ return -1;
+}
+
+void clock_set_enable(enum periph_id periph_id, int enable)
+{
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 *clk;
+ u32 reg;
+
+ /* Enable/disable the clock to this peripheral */
+ assert(clock_periph_id_isvalid(periph_id));
+ if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
+ clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
+ else
+ clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
+ reg = readl(clk);
+ if (enable)
+ reg |= PERIPH_MASK(periph_id);
+ else
+ reg &= ~PERIPH_MASK(periph_id);
+ writel(reg, clk);
+}
+
+void reset_set_enable(enum periph_id periph_id, int enable)
+{
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 *reset;
+ u32 reg;
+
+ /* Enable/disable reset to the peripheral */
+ assert(clock_periph_id_isvalid(periph_id));
+ if (periph_id < PERIPH_ID_VW_FIRST)
+ reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
+ else
+ reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
+ reg = readl(reset);
+ if (enable)
+ reg |= PERIPH_MASK(periph_id);
+ else
+ reg &= ~PERIPH_MASK(periph_id);
+ writel(reg, reset);
+}
+
+#ifdef CONFIG_OF_CONTROL
+/*
+ * Convert a device tree clock ID to our peripheral ID. They are mostly
+ * the same but we are very cautious so we check that a valid clock ID is
+ * provided.
+ *
+ * @param clk_id Clock ID according to tegra124 device tree binding
+ * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
+ */
+enum periph_id clk_id_to_periph_id(int clk_id)
+{
+ if (clk_id > PERIPH_ID_COUNT)
+ return PERIPH_ID_NONE;
+
+ switch (clk_id) {
+ case PERIPH_ID_RESERVED4:
+ case PERIPH_ID_RESERVED25:
+ case PERIPH_ID_RESERVED35:
+ case PERIPH_ID_RESERVED36:
+ case PERIPH_ID_RESERVED38:
+ case PERIPH_ID_RESERVED43:
+ case PERIPH_ID_RESERVED49:
+ case PERIPH_ID_RESERVED53:
+ case PERIPH_ID_RESERVED64:
+ case PERIPH_ID_RESERVED84:
+ case PERIPH_ID_RESERVED85:
+ case PERIPH_ID_RESERVED86:
+ case PERIPH_ID_RESERVED88:
+ case PERIPH_ID_RESERVED90:
+ case PERIPH_ID_RESERVED92:
+ case PERIPH_ID_RESERVED93:
+ case PERIPH_ID_RESERVED94:
+ case PERIPH_ID_V_RESERVED2:
+ case PERIPH_ID_V_RESERVED4:
+ case PERIPH_ID_V_RESERVED17:
+ case PERIPH_ID_V_RESERVED18:
+ case PERIPH_ID_V_RESERVED19:
+ case PERIPH_ID_V_RESERVED20:
+ case PERIPH_ID_V_RESERVED21:
+ case PERIPH_ID_V_RESERVED22:
+ case PERIPH_ID_W_RESERVED2:
+ case PERIPH_ID_W_RESERVED3:
+ case PERIPH_ID_W_RESERVED4:
+ case PERIPH_ID_W_RESERVED5:
+ case PERIPH_ID_W_RESERVED6:
+ case PERIPH_ID_W_RESERVED7:
+ case PERIPH_ID_W_RESERVED9:
+ case PERIPH_ID_W_RESERVED10:
+ case PERIPH_ID_W_RESERVED11:
+ case PERIPH_ID_W_RESERVED12:
+ case PERIPH_ID_W_RESERVED13:
+ case PERIPH_ID_W_RESERVED15:
+ case PERIPH_ID_W_RESERVED16:
+ case PERIPH_ID_W_RESERVED17:
+ case PERIPH_ID_W_RESERVED18:
+ case PERIPH_ID_W_RESERVED19:
+ case PERIPH_ID_W_RESERVED20:
+ case PERIPH_ID_W_RESERVED23:
+ case PERIPH_ID_W_RESERVED29:
+ case PERIPH_ID_W_RESERVED30:
+ case PERIPH_ID_W_RESERVED31:
+ return PERIPH_ID_NONE;
+ default:
+ return clk_id;
+ }
+}
+#endif /* CONFIG_OF_CONTROL */
+
+void clock_early_init(void)
+{
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+
+ tegra30_set_up_pllp();
+
+ /*
+ * PLLC output frequency set to 600Mhz
+ * PLLD output frequency set to 925Mhz
+ */
+ switch (clock_get_osc_freq()) {
+ case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
+ clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
+ clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
+ break;
+
+ case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
+ clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
+ clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
+ break;
+
+ case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
+ clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
+ clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
+ break;
+ case CLOCK_OSC_FREQ_19_2:
+ default:
+ /*
+ * These are not supported. It is too early to print a
+ * message and the UART likely won't work anyway due to the
+ * oscillator being wrong.
+ */
+ break;
+ }
+
+ /* PLLC_MISC2: Set dynramp_stepA/B. MISC2 maps to pll_out[1] */
+ writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]);
+
+ /* PLLC_MISC: Set LOCK_ENABLE */
+ writel(0x01000000, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc);
+ udelay(2);
+
+ /* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1 */
+ writel(0x40000C10, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);
+ udelay(2);
+}
+
+void arch_timer_init(void)
+{
+ struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
+ u32 freq, val;
+
+ freq = clock_get_rate(CLOCK_ID_OSC);
+ debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq);
+
+ /* ARM CNTFRQ */
+ asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
+
+ /* Only Tegra114+ has the System Counter regs */
+ debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq);
+ writel(freq, &sysctr->cntfid0);
+
+ val = readl(&sysctr->cntcr);
+ val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG;
+ writel(val, &sysctr->cntcr);
+ debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
+}
--- /dev/null
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Tegra124 high-level function multiplexing */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+
+int funcmux_select(enum periph_id id, int config)
+{
+ int bad_config = config != FUNCMUX_DEFAULT;
+
+ switch (id) {
+ case PERIPH_ID_UART4:
+ switch (config) {
+ case FUNCMUX_UART4_GPIO: /* TXD,RXD,CTS,RTS */
+ pinmux_set_func(PINGRP_GPIO_PJ7, PMUX_FUNC_UARTD);
+ pinmux_set_func(PINGRP_GPIO_PB0, PMUX_FUNC_UARTD);
+ pinmux_set_func(PINGRP_GPIO_PB1, PMUX_FUNC_UARTD);
+ pinmux_set_func(PINGRP_GPIO_PK7, PMUX_FUNC_UARTD);
+
+ pinmux_set_io(PINGRP_GPIO_PJ7, PMUX_PIN_OUTPUT);
+ pinmux_set_io(PINGRP_GPIO_PB0, PMUX_PIN_INPUT);
+ pinmux_set_io(PINGRP_GPIO_PB1, PMUX_PIN_INPUT);
+ pinmux_set_io(PINGRP_GPIO_PK7, PMUX_PIN_OUTPUT);
+
+ pinmux_tristate_disable(PINGRP_GPIO_PJ7);
+ pinmux_tristate_disable(PINGRP_GPIO_PB0);
+ pinmux_tristate_disable(PINGRP_GPIO_PB1);
+ pinmux_tristate_disable(PINGRP_GPIO_PK7);
+ break;
+ }
+ break;
+
+ case PERIPH_ID_UART1:
+ switch (config) {
+ case FUNCMUX_UART1_KBC:
+ pinmux_set_func(PINGRP_KB_ROW9, PMUX_FUNC_UARTA);
+ pinmux_set_func(PINGRP_KB_ROW10, PMUX_FUNC_UARTA);
+
+ pinmux_set_io(PINGRP_KB_ROW9, PMUX_PIN_OUTPUT);
+ pinmux_set_io(PINGRP_KB_ROW10, PMUX_PIN_INPUT);
+
+ pinmux_tristate_disable(PINGRP_KB_ROW9);
+ pinmux_tristate_disable(PINGRP_KB_ROW10);
+ break;
+ }
+ break;
+
+ /* Add other periph IDs here as needed */
+
+ default:
+ debug("%s: invalid periph_id %d", __func__, id);
+ return -1;
+ }
+
+ if (bad_config) {
+ debug("%s: invalid config %d for periph_id %d", __func__,
+ config, id);
+ return -1;
+ }
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Tegra124 pin multiplexing functions */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch/pinmux.h>
+
+struct tegra_pingroup_desc {
+ const char *name;
+ enum pmux_func funcs[4];
+ enum pmux_func func_safe;
+ enum pmux_vddio vddio;
+ enum pmux_pin_io io;
+};
+
+#define PMUX_MUXCTL_SHIFT 0
+#define PMUX_PULL_SHIFT 2
+#define PMUX_TRISTATE_SHIFT 4
+#define PMUX_TRISTATE_MASK (1 << PMUX_TRISTATE_SHIFT)
+#define PMUX_IO_SHIFT 5
+#define PMUX_OD_SHIFT 6
+#define PMUX_LOCK_SHIFT 7
+#define PMUX_IO_RESET_SHIFT 8
+#define PMUX_RCV_SEL_SHIFT 9
+
+#define PGRP_HSM_SHIFT 2
+#define PGRP_SCHMT_SHIFT 3
+#define PGRP_LPMD_SHIFT 4
+#define PGRP_LPMD_MASK (3 << PGRP_LPMD_SHIFT)
+#define PGRP_DRVDN_SHIFT 12
+#define PGRP_DRVDN_MASK (0x7F << PGRP_DRVDN_SHIFT)
+#define PGRP_DRVUP_SHIFT 20
+#define PGRP_DRVUP_MASK (0x7F << PGRP_DRVUP_SHIFT)
+#define PGRP_SLWR_SHIFT 28
+#define PGRP_SLWR_MASK (3 << PGRP_SLWR_SHIFT)
+#define PGRP_SLWF_SHIFT 30
+#define PGRP_SLWF_MASK (3 << PGRP_SLWF_SHIFT)
+
+/* Convenient macro for defining pin group properties */
+#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
+ { \
+ .vddio = PMUX_VDDIO_ ## vdd, \
+ .funcs = { \
+ PMUX_FUNC_ ## f0, \
+ PMUX_FUNC_ ## f1, \
+ PMUX_FUNC_ ## f2, \
+ PMUX_FUNC_ ## f3, \
+ }, \
+ .func_safe = PMUX_FUNC_RSVD1, \
+ .io = PMUX_PIN_ ## iod, \
+ }
+
+/* Input and output pins */
+#define PINI(pg_name, vdd, f0, f1, f2, f3) \
+ PIN(pg_name, vdd, f0, f1, f2, f3, INPUT)
+#define PINO(pg_name, vdd, f0, f1, f2, f3) \
+ PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
+
+/* A pin group number which is not used */
+#define PIN_RESERVED \
+ PIN(NONE, NONE, INVALID, INVALID, INVALID, INVALID, NONE)
+
+const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
+ /* NAME VDD f0 f1 f2 f3 */
+ PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI),
+ PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI),
+ PINI(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI),
+ PINI(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI),
+ PINI(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI),
+ PINI(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI),
+ PINI(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI),
+ PINI(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI),
+ PINI(ULPI_CLK, BB, SPI1, SPI5, UARTD, ULPI),
+ PINI(ULPI_DIR, BB, SPI1, SPI5, UARTD, ULPI),
+ PINI(ULPI_NXT, BB, SPI1, SPI5, UARTD, ULPI),
+ PINI(ULPI_STP, BB, SPI1, SPI5, UARTD, ULPI),
+ PINI(DAP3_FS, BB, I2S2, SPI5, DISPA, DISPB),
+ PINI(DAP3_DIN, BB, I2S2, SPI5, DISPA, DISPB),
+ PINI(DAP3_DOUT, BB, I2S2, SPI5, DISPA, DISPB),
+ PINI(DAP3_SCLK, BB, I2S2, SPI5, DISPA, DISPB),
+ PINI(GPIO_PV0, BB, USB, RSVD2, RSVD3, RSVD4),
+ PINI(GPIO_PV1, BB, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(SDMMC1_CLK, SDMMC1, SDMMC1, CLK12, RSVD3, RSVD4),
+ PINI(SDMMC1_CMD, SDMMC1, SDMMC1, SPDIF, SPI4, UARTA),
+ PINI(SDMMC1_DAT3, SDMMC1, SDMMC1, SPDIF, SPI4, UARTA),
+ PINI(SDMMC1_DAT2, SDMMC1, SDMMC1, PWM0, SPI4, UARTA),
+ PINI(SDMMC1_DAT1, SDMMC1, SDMMC1, PWM1, SPI4, UARTA),
+ PINI(SDMMC1_DAT0, SDMMC1, SDMMC1, RSVD2, SPI4, UARTA),
+ PIN_RESERVED, /* Reserved: 0x3060 - 0x3064 */
+ PIN_RESERVED,
+ PINI(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
+ PINI(CLK2_REQ, SDMMC1, DAP, RSVD2, RSVD3, RSVD4),
+ PIN_RESERVED, /* Reserved: 0x3070 - 0x310c */
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PINI(HDMI_INT, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(DDC_SCL, LCD, I2C4, RSVD2, RSVD3, RSVD4),
+ PINI(DDC_SDA, LCD, I2C4, RSVD2, RSVD3, RSVD4),
+ PIN_RESERVED, /* Reserved: 0x311c - 0x3160 */
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PINI(UART2_RXD, UART, UARTB, SPDIF, UARTA, SPI4),
+ PINI(UART2_TXD, UART, UARTB, SPDIF, UARTA, SPI4),
+ PINI(UART2_RTS_N, UART, UARTA, UARTB, RSVD3, SPI4),
+ PINI(UART2_CTS_N, UART, UARTA, UARTB, RSVD3, SPI4),
+ PINI(UART3_TXD, UART, UARTC, RSVD2, RSVD3, SPI4),
+ PINI(UART3_RXD, UART, UARTC, RSVD2, RSVD3, SPI4),
+ PINI(UART3_CTS_N, UART, UARTC, SDMMC1, DTV, SPI4),
+ PINI(UART3_RTS_N, UART, UARTC, PWM0, DTV, DISPA),
+ PINI(GPIO_PU0, UART, OWR, UARTA, RSVD3, RSVD4),
+ PINI(GPIO_PU1, UART, RSVD1, UARTA, RSVD3, RSVD4),
+ PINI(GPIO_PU2, UART, RSVD1, UARTA, RSVD3, RSVD4),
+ PINI(GPIO_PU3, UART, PWM0, UARTA, DISPA, DISPB),
+ PINI(GPIO_PU4, UART, PWM1, UARTA, DISPA, DISPB),
+ PINI(GPIO_PU5, UART, PWM2, UARTA, DISPA, DISPB),
+ PINI(GPIO_PU6, UART, PWM3, UARTA, USB, DISPB),
+ PINI(GEN1_I2C_SDA, UART, I2C1, RSVD2, RSVD3, RSVD4),
+ PINI(GEN1_I2C_SCL, UART, I2C1, RSVD2, RSVD3, RSVD4),
+ PINI(DAP4_FS, UART, I2S3, RSVD2, DTV, RSVD4),
+ PINI(DAP4_DIN, UART, I2S3, RSVD2, RSVD3, RSVD4),
+ PINI(DAP4_DOUT, UART, I2S3, RSVD2, DTV, RSVD4),
+ PINI(DAP4_SCLK, UART, I2S3, RSVD2, RSVD3, RSVD4),
+ PINI(CLK3_OUT, UART, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
+ PINI(CLK3_REQ, UART, DEV3, RSVD2, RSVD3, RSVD4),
+ PINI(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT),
+ PINI(GMI_IORDY, GMI, SDMMC2, RSVD2, GMI, TRACE),
+ PINI(GMI_WAIT, GMI, SPI4, NAND, GMI, DTV),
+ PINI(GMI_ADV_N, GMI, RSVD1, NAND, GMI, TRACE),
+ PINI(GMI_CLK, GMI, SDMMC2, NAND, GMI, TRACE),
+ PINI(GMI_CS0_N, GMI, RSVD1, NAND, GMI, USB),
+ PINI(GMI_CS1_N, GMI, RSVD1, NAND, GMI, SOC),
+ PINI(GMI_CS2_N, GMI, SDMMC2, NAND, GMI, TRACE),
+ PINI(GMI_CS3_N, GMI, SDMMC2, NAND, GMI, GMI_ALT),
+ PINI(GMI_CS4_N, GMI, USB, NAND, GMI, TRACE),
+ PINI(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SPI4),
+ PINI(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, SDMMC2),
+ PINI(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_AD5, GMI, RSVD1, NAND, GMI, SPI4),
+ PINI(GMI_AD6, GMI, RSVD1, NAND, GMI, SPI4),
+ PINI(GMI_AD7, GMI, RSVD1, NAND, GMI, SPI4),
+ PINI(GMI_AD8, GMI, PWM0, NAND, GMI, DTV),
+ PINI(GMI_AD9, GMI, PWM1, NAND, GMI, CLDVFS),
+ PINI(GMI_AD10, GMI, PWM2, NAND, GMI, CLDVFS),
+ PINI(GMI_AD11, GMI, PWM3, NAND, GMI, USB),
+ PINI(GMI_AD12, GMI, SDMMC2, NAND, GMI, RSVD4),
+ PINI(GMI_AD13, GMI, SDMMC2, NAND, GMI, RSVD4),
+ PINI(GMI_AD14, GMI, SDMMC2, NAND, GMI, DTV),
+ PINI(GMI_AD15, GMI, SDMMC2, NAND, GMI, DTV),
+ PINI(GMI_A16, GMI, UARTD, TRACE, GMI, GMI_ALT),
+ PINI(GMI_A17, GMI, UARTD, RSVD2, GMI, TRACE),
+ PINI(GMI_A18, GMI, UARTD, RSVD2, GMI, TRACE),
+ PINI(GMI_A19, GMI, UARTD, SPI4, GMI, TRACE),
+ PINI(GMI_WR_N, GMI, RSVD1, NAND, GMI, SPI4),
+ PINI(GMI_OE_N, GMI, RSVD1, NAND, GMI, SOC),
+ PINI(GMI_DQS, GMI, SDMMC2, NAND, GMI, TRACE),
+ PINI(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD4),
+ PINI(GEN2_I2C_SCL, GMI, I2C2, RSVD2, GMI, RSVD4),
+ PINI(GEN2_I2C_SDA, GMI, I2C2, RSVD2, GMI, RSVD4),
+ PINI(SDMMC4_CLK, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
+ PINI(SDMMC4_CMD, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
+ PINI(SDMMC4_DAT0, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
+ PINI(SDMMC4_DAT1, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
+ PINI(SDMMC4_DAT2, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
+ PINI(SDMMC4_DAT3, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
+ PINI(SDMMC4_DAT4, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
+ PINI(SDMMC4_DAT5, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
+ PINI(SDMMC4_DAT6, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
+ PINI(SDMMC4_DAT7, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
+ PIN_RESERVED, /* Reserved: 0x3280 */
+ PINI(CAM_MCLK, CAM, VI, VI_ALT1, VI_ALT3, RSVD4),
+ PINI(GPIO_PCC1, CAM, I2S4, RSVD2, RSVD3, RSVD4),
+ PINI(GPIO_PBB0, CAM, I2S4, VI, VI_ALT1, VI_ALT3),
+ PINI(CAM_I2C_SCL, CAM, VGP1, I2C3, RSVD3, RSVD4),
+ PINI(CAM_I2C_SDA, CAM, VGP2, I2C3, RSVD3, RSVD4),
+ PINI(GPIO_PBB3, CAM, VGP3, DISPA, DISPB, RSVD4),
+ PINI(GPIO_PBB4, CAM, VGP4, DISPA, DISPB, RSVD4),
+ PINI(GPIO_PBB5, CAM, VGP5, DISPA, DISPB, RSVD4),
+ PINI(GPIO_PBB6, CAM, VGP6, DISPA, DISPB, RSVD4),
+ PINI(GPIO_PBB7, CAM, I2S4, RSVD2, RSVD3, RSVD4),
+ PINI(GPIO_PCC2, CAM, I2S4, RSVD2, RSVD3, RSVD4),
+ PINI(JTAG_RTCK, SYS, RTCK, RSVD2, RSVD3, RSVD4),
+ PINI(PWR_I2C_SCL, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
+ PINI(PWR_I2C_SDA, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
+ PINI(KB_ROW0, SYS, KBC, RSVD2, DTV, RSVD4),
+ PINI(KB_ROW1, SYS, KBC, RSVD2, DTV, RSVD4),
+ PINI(KB_ROW2, SYS, KBC, RSVD2, DTV, SOC),
+ PINI(KB_ROW3, SYS, KBC, DISPA, RSVD3, DISPB),
+ PINI(KB_ROW4, SYS, KBC, DISPA, SPI2, DISPB),
+ PINI(KB_ROW5, SYS, KBC, DISPA, SPI2, DISPB),
+ PINI(KB_ROW6, SYS, KBC, DISPA, RSVD3, DISPB),
+ PINI(KB_ROW7, SYS, KBC, RSVD2, CLDVFS, UARTA),
+ PINI(KB_ROW8, SYS, KBC, RSVD2, RSVD3, UARTA),
+ PINI(KB_ROW9, SYS, KBC, RSVD2, RSVD3, UARTA),
+ PINI(KB_ROW10, SYS, KBC, RSVD2, RSVD3, UARTA),
+ PIN_RESERVED, /* Reserved: 0x32e8 - 0x32f8 */
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PINI(KB_COL0, SYS, KBC, USB, SPI2, EMC_DLL),
+ PINI(KB_COL1, SYS, KBC, RSVD2, SPI2, EMC_DLL),
+ PINI(KB_COL2, SYS, KBC, RSVD2, SPI2, RSVD4),
+ PINI(KB_COL3, SYS, KBC, DISPA, PWM2, UARTA),
+ PINI(KB_COL4, SYS, KBC, OWR, SDMMC3, UARTA),
+ PINI(KB_COL5, SYS, KBC, RSVD2, SDMMC1, RSVD4),
+ PINI(KB_COL6, SYS, KBC, RSVD2, SPI2, RSVD4),
+ PINI(KB_COL7, SYS, KBC, RSVD2, SPI2, RSVD4),
+ PINI(CLK_32K_OUT, SYS, BLINK, SOC, RSVD3, RSVD4),
+ PINI(SYS_CLK_REQ, SYS, SYSCLK, RSVD2, RSVD3, RSVD4),
+ PINI(CORE_PWR_REQ, SYS, PWRON, RSVD2, RSVD3, RSVD4),
+ PINI(CPU_PWR_REQ, SYS, CPU, RSVD2, RSVD3, RSVD4),
+ PINI(PWR_INT_N, SYS, PMI, RSVD2, RSVD3, RSVD4),
+ PINI(CLK_32K_IN, SYS, CLK, RSVD2, RSVD3, RSVD4),
+ PINI(OWR, SYS, OWR, RSVD2, RSVD3, RSVD4),
+ PINI(DAP1_FS, AUDIO, I2S0, HDA, GMI, RSVD4),
+ PINI(DAP1_DIN, AUDIO, I2S0, HDA, GMI, RSVD4),
+ PINI(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, RSVD4),
+ PINI(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, RSVD4),
+ PINI(CLK1_REQ, AUDIO, DAP, DAP1, RSVD3, RSVD4),
+ PINI(CLK1_OUT, AUDIO, EXTPERIPH1, DAP2, RSVD3, RSVD4),
+ PINI(SPDIF_IN, AUDIO, SPDIF, USB, RSVD3, RSVD4),
+ PINI(SPDIF_OUT, AUDIO, SPDIF, RSVD2, RSVD3, RSVD4),
+ PINI(DAP2_FS, AUDIO, I2S1, HDA, RSVD3, RSVD4),
+ PINI(DAP2_DIN, AUDIO, I2S1, HDA, RSVD3, RSVD4),
+ PINI(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD3, RSVD4),
+ PINI(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD3, RSVD4),
+ PINI(DVFS_PWM, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
+ PINI(GPIO_X1_AUD, AUDIO, SPI6, RSVD2, RSVD3, RSVD4),
+ PINI(GPIO_X3_AUD, AUDIO, SPI6, SPI1, RSVD3, RSVD4),
+ PINI(DVFS_CLK, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
+ PINI(GPIO_X4_AUD, AUDIO, RSVD1, SPI1, SPI2, DAP2),
+ PINI(GPIO_X5_AUD, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
+ PINI(GPIO_X6_AUD, AUDIO, SPI6, SPI1, SPI2, RSVD4),
+ PINI(GPIO_X7_AUD, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
+ PIN_RESERVED, /* Reserved: 0x3388 - 0x338c */
+ PIN_RESERVED,
+ PINI(SDMMC3_CLK, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3),
+ PINI(SDMMC3_CMD, SDMMC3, SDMMC3, PWM3, UARTA, SPI3),
+ PINI(SDMMC3_DAT0, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3),
+ PINI(SDMMC3_DAT1, SDMMC3, SDMMC3, PWM2, UARTA, SPI3),
+ PINI(SDMMC3_DAT2, SDMMC3, SDMMC3, PWM1, DISPA, SPI3),
+ PINI(SDMMC3_DAT3, SDMMC3, SDMMC3, PWM0, DISPB, SPI3),
+ PIN_RESERVED, /* Reserved: 0x33a8 - 0x33dc */
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PINI(HDMI_CEC, SYS, CEC, SDMMC3, RSVD3, SOC),
+ PINI(SDMMC1_WP_N, SDMMC1, SDMMC1, CLK12, SPI4, UARTA),
+ PINI(SDMMC3_CD_N, SYS, SDMMC3, OWR, RSVD3, RSVD4),
+ PINI(GPIO_W2_AUD, AUDIO, SPI6, RSVD2, SPI2, I2C1),
+ PINI(GPIO_W3_AUD, AUDIO, SPI6, SPI1, SPI2, I2C1),
+ PINI(USB_VBUS_EN0, LCD, USB, RSVD2, RSVD3, RSVD4),
+ PINI(USB_VBUS_EN1, LCD, USB, RSVD2, RSVD3, RSVD4),
+ PINI(SDMMC3_CLK_LB_IN, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4),
+ PINI(SDMMC3_CLK_LB_OUT, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4),
+ PIN_RESERVED, /* Reserved: 0x3404 */
+ PINO(RESET_OUT_N, SYS, RSVD1, RSVD2, RSVD3, RESET_OUT_N),
+};
+
+void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *tri = &pmt->pmt_ctl[pin];
+ u32 reg;
+
+ /* Error check on pin */
+ assert(pmux_pingrp_isvalid(pin));
+
+ reg = readl(tri);
+ if (enable)
+ reg |= PMUX_TRISTATE_MASK;
+ else
+ reg &= ~PMUX_TRISTATE_MASK;
+ writel(reg, tri);
+}
+
+void pinmux_tristate_enable(enum pmux_pingrp pin)
+{
+ pinmux_set_tristate(pin, 1);
+}
+
+void pinmux_tristate_disable(enum pmux_pingrp pin)
+{
+ pinmux_set_tristate(pin, 0);
+}
+
+void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pull = &pmt->pmt_ctl[pin];
+ u32 reg;
+
+ /* Error check on pin and pupd */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_pupd_isvalid(pupd));
+
+ reg = readl(pull);
+ reg &= ~(0x3 << PMUX_PULL_SHIFT);
+ reg |= (pupd << PMUX_PULL_SHIFT);
+ writel(reg, pull);
+}
+
+void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *muxctl = &pmt->pmt_ctl[pin];
+ int i, mux = -1;
+ u32 reg;
+
+ /* Error check on pin and func */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_func_isvalid(func));
+
+ /* Handle special values */
+ if (func == PMUX_FUNC_SAFE)
+ func = tegra_soc_pingroups[pin].func_safe;
+
+ if (func & PMUX_FUNC_RSVD1) {
+ mux = func & 0x3;
+ } else {
+ /* Search for the appropriate function */
+ for (i = 0; i < 4; i++) {
+ if (tegra_soc_pingroups[pin].funcs[i] == func) {
+ mux = i;
+ break;
+ }
+ }
+ }
+ assert(mux != -1);
+
+ reg = readl(muxctl);
+ reg &= ~(0x3 << PMUX_MUXCTL_SHIFT);
+ reg |= (mux << PMUX_MUXCTL_SHIFT);
+ writel(reg, muxctl);
+}
+
+void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pin_io = &pmt->pmt_ctl[pin];
+ u32 reg;
+
+ /* Error check on pin and io */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_io_isvalid(io));
+
+ reg = readl(pin_io);
+ reg &= ~(0x1 << PMUX_IO_SHIFT);
+ reg |= (io & 0x1) << PMUX_IO_SHIFT;
+ writel(reg, pin_io);
+}
+
+static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pin_lock = &pmt->pmt_ctl[pin];
+ u32 reg;
+
+ /* Error check on pin and lock */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_lock_isvalid(lock));
+
+ if (lock == PMUX_PIN_LOCK_DEFAULT)
+ return 0;
+
+ reg = readl(pin_lock);
+ reg &= ~(0x1 << PMUX_LOCK_SHIFT);
+ if (lock == PMUX_PIN_LOCK_ENABLE) {
+ reg |= (0x1 << PMUX_LOCK_SHIFT);
+ } else {
+ /* lock == DISABLE, which isn't possible */
+ printf("%s: Warning: lock == %d, DISABLE is not allowed!\n",
+ __func__, lock);
+ }
+ writel(reg, pin_lock);
+
+ return 0;
+}
+
+static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pin_od = &pmt->pmt_ctl[pin];
+ u32 reg;
+
+ /* Error check on pin and od */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_od_isvalid(od));
+
+ if (od == PMUX_PIN_OD_DEFAULT)
+ return 0;
+
+ reg = readl(pin_od);
+ reg &= ~(0x1 << PMUX_OD_SHIFT);
+ if (od == PMUX_PIN_OD_ENABLE)
+ reg |= (0x1 << PMUX_OD_SHIFT);
+ writel(reg, pin_od);
+
+ return 0;
+}
+
+static int pinmux_set_ioreset(enum pmux_pingrp pin,
+ enum pmux_pin_ioreset ioreset)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pin_ioreset = &pmt->pmt_ctl[pin];
+ u32 reg;
+
+ /* Error check on pin and ioreset */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_ioreset_isvalid(ioreset));
+
+ if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
+ return 0;
+
+ reg = readl(pin_ioreset);
+ reg &= ~(0x1 << PMUX_IO_RESET_SHIFT);
+ if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
+ reg |= (0x1 << PMUX_IO_RESET_SHIFT);
+ writel(reg, pin_ioreset);
+
+ return 0;
+}
+
+static int pinmux_set_rcv_sel(enum pmux_pingrp pin,
+ enum pmux_pin_rcv_sel rcv_sel)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pin_rcv_sel = &pmt->pmt_ctl[pin];
+ u32 reg;
+
+ /* Error check on pin and rcv_sel */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
+
+ if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
+ return 0;
+
+ reg = readl(pin_rcv_sel);
+ reg &= ~(0x1 << PMUX_RCV_SEL_SHIFT);
+ if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
+ reg |= (0x1 << PMUX_RCV_SEL_SHIFT);
+ writel(reg, pin_rcv_sel);
+
+ return 0;
+}
+
+void pinmux_config_pingroup(struct pingroup_config *config)
+{
+ enum pmux_pingrp pin = config->pingroup;
+
+ pinmux_set_func(pin, config->func);
+ pinmux_set_pullupdown(pin, config->pull);
+ pinmux_set_tristate(pin, config->tristate);
+ pinmux_set_io(pin, config->io);
+ pinmux_set_lock(pin, config->lock);
+ pinmux_set_od(pin, config->od);
+ pinmux_set_ioreset(pin, config->ioreset);
+ pinmux_set_rcv_sel(pin, config->rcv_sel);
+}
+
+void pinmux_config_table(struct pingroup_config *config, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++)
+ pinmux_config_pingroup(&config[i]);
+}
+
+static int padgrp_set_drvup_slwf(enum pdrive_pingrp pad, int slwf)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pad_slwf = &pmt->pmt_drive[pad];
+ u32 reg;
+
+ /* Error check on pad and slwf */
+ assert(pmux_padgrp_isvalid(pad));
+ assert(pmux_pad_slw_isvalid(slwf));
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (slwf == PGRP_SLWF_NONE)
+ return 0;
+
+ reg = readl(pad_slwf);
+ reg &= ~PGRP_SLWF_MASK;
+ reg |= (slwf << PGRP_SLWF_SHIFT);
+ writel(reg, pad_slwf);
+
+ return 0;
+}
+
+static int padgrp_set_drvdn_slwr(enum pdrive_pingrp pad, int slwr)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pad_slwr = &pmt->pmt_drive[pad];
+ u32 reg;
+
+ /* Error check on pad and slwr */
+ assert(pmux_padgrp_isvalid(pad));
+ assert(pmux_pad_slw_isvalid(slwr));
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (slwr == PGRP_SLWR_NONE)
+ return 0;
+
+ reg = readl(pad_slwr);
+ reg &= ~PGRP_SLWR_MASK;
+ reg |= (slwr << PGRP_SLWR_SHIFT);
+ writel(reg, pad_slwr);
+
+ return 0;
+}
+
+static int padgrp_set_drvup(enum pdrive_pingrp pad, int drvup)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pad_drvup = &pmt->pmt_drive[pad];
+ u32 reg;
+
+ /* Error check on pad and drvup */
+ assert(pmux_padgrp_isvalid(pad));
+ assert(pmux_pad_drv_isvalid(drvup));
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (drvup == PGRP_DRVUP_NONE)
+ return 0;
+
+ reg = readl(pad_drvup);
+ reg &= ~PGRP_DRVUP_MASK;
+ reg |= (drvup << PGRP_DRVUP_SHIFT);
+ writel(reg, pad_drvup);
+
+ return 0;
+}
+
+static int padgrp_set_drvdn(enum pdrive_pingrp pad, int drvdn)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pad_drvdn = &pmt->pmt_drive[pad];
+ u32 reg;
+
+ /* Error check on pad and drvdn */
+ assert(pmux_padgrp_isvalid(pad));
+ assert(pmux_pad_drv_isvalid(drvdn));
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (drvdn == PGRP_DRVDN_NONE)
+ return 0;
+
+ reg = readl(pad_drvdn);
+ reg &= ~PGRP_DRVDN_MASK;
+ reg |= (drvdn << PGRP_DRVDN_SHIFT);
+ writel(reg, pad_drvdn);
+
+ return 0;
+}
+
+static int padgrp_set_lpmd(enum pdrive_pingrp pad, enum pgrp_lpmd lpmd)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pad_lpmd = &pmt->pmt_drive[pad];
+ u32 reg;
+
+ /* Error check pad and lpmd value */
+ assert(pmux_padgrp_isvalid(pad));
+ assert(pmux_pad_lpmd_isvalid(lpmd));
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (lpmd == PGRP_LPMD_NONE)
+ return 0;
+
+ reg = readl(pad_lpmd);
+ reg &= ~PGRP_LPMD_MASK;
+ reg |= (lpmd << PGRP_LPMD_SHIFT);
+ writel(reg, pad_lpmd);
+
+ return 0;
+}
+
+static int padgrp_set_schmt(enum pdrive_pingrp pad, enum pgrp_schmt schmt)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pad_schmt = &pmt->pmt_drive[pad];
+ u32 reg;
+
+ /* Error check pad */
+ assert(pmux_padgrp_isvalid(pad));
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (schmt == PGRP_SCHMT_NONE)
+ return 0;
+
+ reg = readl(pad_schmt);
+ reg &= ~(1 << PGRP_SCHMT_SHIFT);
+ if (schmt == PGRP_SCHMT_ENABLE)
+ reg |= (0x1 << PGRP_SCHMT_SHIFT);
+ writel(reg, pad_schmt);
+
+ return 0;
+}
+static int padgrp_set_hsm(enum pdrive_pingrp pad, enum pgrp_hsm hsm)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pad_hsm = &pmt->pmt_drive[pad];
+ u32 reg;
+
+ /* Error check pad */
+ assert(pmux_padgrp_isvalid(pad));
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (hsm == PGRP_HSM_NONE)
+ return 0;
+
+ reg = readl(pad_hsm);
+ reg &= ~(1 << PGRP_HSM_SHIFT);
+ if (hsm == PGRP_HSM_ENABLE)
+ reg |= (0x1 << PGRP_HSM_SHIFT);
+ writel(reg, pad_hsm);
+
+ return 0;
+}
+
+void padctrl_config_pingroup(struct padctrl_config *config)
+{
+ enum pdrive_pingrp pad = config->padgrp;
+
+ padgrp_set_drvup_slwf(pad, config->slwf);
+ padgrp_set_drvdn_slwr(pad, config->slwr);
+ padgrp_set_drvup(pad, config->drvup);
+ padgrp_set_drvdn(pad, config->drvdn);
+ padgrp_set_lpmd(pad, config->lpmd);
+ padgrp_set_schmt(pad, config->schmt);
+ padgrp_set_hsm(pad, config->hsm);
+}
+
+void padgrp_config_table(struct padctrl_config *config, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++)
+ padctrl_config_pingroup(&config[i]);
+}
* with its 16-bit divisor
*/
if (type == CLOCK_TYPE_PCXTS)
- *mux_bits = 4;
+ *mux_bits = MASK_BITS_31_28;
else
- *mux_bits = 2;
+ *mux_bits = MASK_BITS_31_30;
if (type == CLOCK_TYPE_PCMT16)
*divider_bits = 16;
else
/*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
CLOCK_MAX_MUX = 8 /* number of source options for each clock */
};
-enum {
- MASK_BITS_31_30 = 2, /* num of bits used to specify clock source */
- MASK_BITS_31_29,
- MASK_BITS_29_28,
-};
-
/*
* Clock source mux for each clock type. This just converts our enum into
* a list of mux sources for use by the code.
MASK_BITS_31_29},
{ CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_29_28}
+ MASK_BITS_31_28}
};
/*
void clock_early_init(void)
{
- /*
- * PLLP output frequency set to 408Mhz
- * PLLC output frequency set to 228Mhz
- */
- switch (clock_get_osc_freq()) {
- case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
- clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
- clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
- break;
-
- case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
- clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
- clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
- break;
-
- case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
- clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
- clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
- break;
- case CLOCK_OSC_FREQ_19_2:
- default:
- /*
- * These are not supported. It is too early to print a
- * message and the UART likely won't work anyway due to the
- * oscillator being wrong.
- */
- break;
- }
+ tegra30_set_up_pllp();
}
void arch_timer_init(void)
__rel_dyn_end = .;
}
- _end = .;
+ .end :
+ {
+ *(.__end)
+ }
+
+ _image_binary_end = .;
.bss __rel_dyn_start (OVERLAY) : {
__bss_start = .;
__bss_end = .;
}
- .dynsym _end : { *(.dynsym) }
+ .dynsym _image_binary_end : { *(.dynsym) }
.dynbss : { *(.dynbss) }
.dynstr : { *(.dynstr*) }
.dynamic : { *(.dynamic*) }
*(.__rel_dyn_end)
}
- _end = .;
+ .end :
+ {
+ *(.__end)
+ }
+
+ _image_binary_end = .;
/*
* Deprecated: this MMU section is used by pxa at present but
KEEP(*(.__bss_end));
}
- .dynsym _end : { *(.dynsym) }
+ .dynsym _image_binary_end : { *(.dynsym) }
.dynbss : { *(.dynbss) }
.dynstr : { *(.dynstr*) }
.dynamic : { *(.dynamic*) }
--- /dev/null
+dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
+ exynos5250-snow.dtb \
+ exynos5250-smdk5250.dtb \
+ exynos5420-smdk5420.dtb
+dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
+ tegra20-medcom-wide.dtb \
+ tegra20-paz00.dtb \
+ tegra20-plutux.dtb \
+ tegra20-seaboard.dtb \
+ tegra20-tec.dtb \
+ tegra20-trimslice.dtb \
+ tegra20-ventana.dtb \
+ tegra20-whistler.dtb \
+ tegra20-colibri_t20_iris.dtb \
+ tegra30-beaver.dtb \
+ tegra30-cardhu.dtb \
+ tegra30-tec-ng.dtb \
+ tegra114-dalmore.dtb \
+ tegra124-venice2.dtb
+dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
+ zynq-zc706.dtb \
+ zynq-zed.dtb \
+ zynq-microzed.dtb \
+ zynq-zc770-xm010.dtb \
+ zynq-zc770-xm012.dtb \
+ zynq-zc770-xm013.dtb
+
+targets += $(dtb-y)
+
+DTC_FLAGS += -R 4 -p 0x1000
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+ @:
+
+clean-files := *.dtb
};
ehci@12110000 {
- samsung,vbus-gpio = <&gpio 0xbe 0>; /* X26 */
+ samsung,vbus-gpio = <&gpio 0x316 0>; /* X26 */
};
};
};
ehci@12110000 {
- samsung,vbus-gpio = <&gpio 0xb1 0>; /* X11 */
+ samsung,vbus-gpio = <&gpio 0x309 0>; /* X11 */
};
xhci@12000000 {
- samsung,vbus-gpio = <&gpio 0xbf 0>; /* X27 */
+ samsung,vbus-gpio = <&gpio 0x317 0>; /* X27 */
};
tmu@10060000 {
spi@7000d800 {
compatible = "nvidia,tegra114-spi";
- reg = <0x7000d480 0x200>;
+ reg = <0x7000d800 0x200>;
interrupts = <0 83 0x04>;
nvidia,dma-request-selector = <&apbdma 17>;
#address-cells = <1>;
--- /dev/null
+/dts-v1/;
+
+#include "tegra124.dtsi"
+
+/ {
+ model = "NVIDIA Venice2";
+ compatible = "nvidia,venice2", "nvidia,tegra124";
+
+ aliases {
+ i2c0 = "/i2c@7000d000";
+ i2c1 = "/i2c@7000c000";
+ i2c2 = "/i2c@7000c400";
+ i2c3 = "/i2c@7000c500";
+ i2c4 = "/i2c@7000c700";
+ i2c5 = "/i2c@7000d100";
+ sdhci0 = "/sdhci@700b0600";
+ sdhci1 = "/sdhci@700b0400";
+ spi0 = "/spi@7000d400";
+ spi1 = "/spi@7000da00";
+ usb0 = "/usb@7d008000";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
+
+ i2c@7000c000 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ i2c@7000c400 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ i2c@7000c500 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ i2c@7000c700 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <400000>;
+ };
+
+ i2c@7000d100 {
+ status = "okay";
+ clock-frequency = <400000>;
+ };
+
+ spi@7000d400 {
+ status = "okay";
+ spi-max-frequency = <25000000>;
+ };
+
+ spi@7000da00 {
+ status = "okay";
+ spi-max-frequency = <25000000>;
+ };
+
+ sdhci@700b0400 {
+ status = "okay";
+ cd-gpios = <&gpio 170 0>; /* gpio PV2 */
+ power-gpios = <&gpio 136 0>; /* gpio PR0 */
+ bus-width = <4>;
+ };
+
+ sdhci@700b0600 {
+ status = "okay";
+ bus-width = <8>;
+ };
+
+ usb@7d008000 {
+ status = "okay";
+ nvidia,vbus-gpio = <&gpio 109 0>; /* gpio PN5, USB_VBUS_EN1 */
+ };
+};
--- /dev/null
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "nvidia,tegra124";
+
+ tegra_car: clock@60006000 {
+ compatible = "nvidia,tegra124-car";
+ reg = <0x60006000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ apbdma: dma@60020000 {
+ compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
+ reg = <0x60020000 0x1400>;
+ interrupts = <0 104 0x04
+ 0 105 0x04
+ 0 106 0x04
+ 0 107 0x04
+ 0 108 0x04
+ 0 109 0x04
+ 0 110 0x04
+ 0 111 0x04
+ 0 112 0x04
+ 0 113 0x04
+ 0 114 0x04
+ 0 115 0x04
+ 0 116 0x04
+ 0 117 0x04
+ 0 118 0x04
+ 0 119 0x04
+ 0 128 0x04
+ 0 129 0x04
+ 0 130 0x04
+ 0 131 0x04
+ 0 132 0x04
+ 0 133 0x04
+ 0 134 0x04
+ 0 135 0x04
+ 0 136 0x04
+ 0 137 0x04
+ 0 138 0x04
+ 0 139 0x04
+ 0 140 0x04
+ 0 141 0x04
+ 0 142 0x04
+ 0 143 0x04>;
+ };
+
+ gpio: gpio@6000d000 {
+ compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
+ reg = <0x6000d000 0x1000>;
+ interrupts = <0 32 0x04
+ 0 33 0x04
+ 0 34 0x04
+ 0 35 0x04
+ 0 55 0x04
+ 0 87 0x04
+ 0 89 0x04
+ 0 125 0x04>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ };
+
+ i2c@7000c000 {
+ compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+ reg = <0x7000c000 0x100>;
+ interrupts = <0 38 0x04>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 12>;
+ status = "disabled";
+ };
+
+ i2c@7000c400 {
+ compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+ reg = <0x7000c400 0x100>;
+ interrupts = <0 84 0x04>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 54>;
+ status = "disabled";
+ };
+
+ i2c@7000c500 {
+ compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+ reg = <0x7000c500 0x100>;
+ interrupts = <0 92 0x04>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 67>;
+ status = "disabled";
+ };
+
+ i2c@7000c700 {
+ compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+ reg = <0x7000c700 0x100>;
+ interrupts = <0 120 0x04>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 103>;
+ status = "disabled";
+ };
+
+ i2c@7000d000 {
+ compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+ reg = <0x7000d000 0x100>;
+ interrupts = <0 53 0x04>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 47>;
+ status = "disabled";
+ };
+
+ i2c@7000d100 {
+ compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+ reg = <0x7000d100 0x100>;
+ interrupts = <0 53 0x04>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 47>;
+ status = "disabled";
+ };
+
+ spi@7000d400 {
+ compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+ reg = <0x7000d400 0x200>;
+ interrupts = <0 59 0x04>;
+ nvidia,dma-request-selector = <&apbdma 15>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ clocks = <&tegra_car 41>;
+ };
+
+ spi@7000d600 {
+ compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+ reg = <0x7000d600 0x200>;
+ interrupts = <0 82 0x04>;
+ nvidia,dma-request-selector = <&apbdma 16>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ clocks = <&tegra_car 44>;
+ };
+
+ spi@7000d800 {
+ compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+ reg = <0x7000d800 0x200>;
+ interrupts = <0 83 0x04>;
+ nvidia,dma-request-selector = <&apbdma 17>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ clocks = <&tegra_car 46>;
+ };
+
+ spi@7000da00 {
+ compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+ reg = <0x7000da00 0x200>;
+ interrupts = <0 93 0x04>;
+ nvidia,dma-request-selector = <&apbdma 18>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ clocks = <&tegra_car 68>;
+ };
+
+ spi@7000dc00 {
+ compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+ reg = <0x7000dc00 0x200>;
+ interrupts = <0 94 0x04>;
+ nvidia,dma-request-selector = <&apbdma 27>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ clocks = <&tegra_car 104>;
+ };
+
+ spi@7000de00 {
+ compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+ reg = <0x7000de00 0x200>;
+ interrupts = <0 79 0x04>;
+ nvidia,dma-request-selector = <&apbdma 28>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ clocks = <&tegra_car 105>;
+ };
+
+ sdhci@700b0000 {
+ compatible = "nvidia,tegra124-sdhci";
+ reg = <0x700b0000 0x200>;
+ interrupts = <0 14 0x04>;
+ clocks = <&tegra_car 14>;
+ status = "disabled";
+ };
+
+ sdhci@700b0200 {
+ compatible = "nvidia,tegra124-sdhci";
+ reg = <0x700b0200 0x200>;
+ interrupts = <0 15 0x04>;
+ clocks = <&tegra_car 9>;
+ status = "disabled";
+ };
+
+ sdhci@700b0400 {
+ compatible = "nvidia,tegra124-sdhci";
+ reg = <0x700b0400 0x200>;
+ interrupts = <0 19 0x04>;
+ clocks = <&tegra_car 69>;
+ status = "disabled";
+ };
+
+ sdhci@700b0600 {
+ compatible = "nvidia,tegra124-sdhci";
+ reg = <0x700b0600 0x200>;
+ interrupts = <0 31 0x04>;
+ clocks = <&tegra_car 15>;
+ status = "disabled";
+ };
+
+ usb@7d000000 {
+ compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
+ reg = <0x7d000000 0x4000>;
+ interrupts = < 52 >;
+ phy_type = "utmi";
+ clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */
+ status = "disabled";
+ };
+
+ usb@7d004000 {
+ compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
+ reg = <0x7d004000 0x4000>;
+ interrupts = < 53 >;
+ phy_type = "hsic";
+ clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */
+ status = "disabled";
+ };
+
+ usb@7d008000 {
+ compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
+ reg = <0x7d008000 0x4000>;
+ interrupts = < 129 >;
+ phy_type = "utmi";
+ clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */
+ status = "disabled";
+ };
+};
obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o
obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
-$(OBJTREE)/$(patsubst "%",%,$(CONFIG_IMX_CONFIG)).cfgtmp: $(OBJTREE)/%.cfgtmp : $(SRCTREE)/%
- mkdir -p $(dir $@)
- $(CC) -E -x c $< $(CPPFLAGS) -o $@
-
-$(OBJTREE)/u-boot.imx: $(OBJTREE)/u-boot.bin $(OBJTREE)/$(patsubst "%",%,$(CONFIG_IMX_CONFIG)).cfgtmp
- $(OBJTREE)/tools/mkimage -n $(filter-out %.bin,$^) -T imximage \
- -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
-
-$(OBJTREE)/SPL: $(OBJTREE)/spl/u-boot-spl.bin $(OBJTREE)/$(patsubst "%",%,$(CONFIG_IMX_CONFIG)).cfgtmp
- $(OBJTREE)/tools/mkimage -n $(filter-out %.bin,$^) -T imximage \
- -e $(CONFIG_SPL_TEXT_BASE) -d $< $@
-
-$(OBJTREE)/u-boot-with-spl.imx: $(OBJTREE)/SPL $(OBJTREE)/u-boot.bin
- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_PAD_TO) \
- -I binary -O binary $< $(OBJTREE)/spl/u-boot-spl-pad.imx
- $(OBJTREE)/tools/mkimage -A arm -O U-Boot -a $(CONFIG_SYS_TEXT_BASE) \
- -e $(CONFIG_SYS_TEXT_BASE) -C none -d $(OBJTREE)/u-boot.bin \
- $(OBJTREE)/u-boot.uim
- cat $(OBJTREE)/spl/u-boot-spl-pad.imx $(OBJTREE)/u-boot.uim > $@
- rm $(OBJTREE)/spl/u-boot-spl-pad.imx $(OBJTREE)/u-boot.uim
-
-$(OBJTREE)/u-boot-with-nand-spl.imx: $(OBJTREE)/SPL $(OBJTREE)/u-boot.bin
- (echo -ne '\x00\x00\x00\x00\x46\x43\x42\x20\x01' && \
- dd bs=1015 count=1 if=/dev/zero 2>/dev/null) | \
- cat - $< > $(OBJTREE)/spl/u-boot-nand-spl.imx
- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_PAD_TO) \
- -I binary -O binary $(OBJTREE)/spl/u-boot-nand-spl.imx \
- $(OBJTREE)/spl/u-boot-nand-spl-pad.imx
- rm $(OBJTREE)/spl/u-boot-nand-spl.imx
- $(OBJTREE)/tools/mkimage -A arm -O U-Boot -a $(CONFIG_SYS_TEXT_BASE) \
- -e $(CONFIG_SYS_TEXT_BASE) -C none -d $(OBJTREE)/u-boot.bin \
- $(OBJTREE)/u-boot.uim
- cat $(OBJTREE)/spl/u-boot-nand-spl-pad.imx $(OBJTREE)/u-boot.uim > $@
- rm $(OBJTREE)/spl/u-boot-nand-spl-pad.imx $(OBJTREE)/u-boot.uim
+quiet_cmd_cpp_cfg = CFGS $@
+ cmd_cpp_cfg = $(CPP) $(cpp_flags) -x c -o $@ $<
+
+IMX_CONFIG = $(CONFIG_IMX_CONFIG:"%"=%).cfgtmp
+
+$(IMX_CONFIG): %.cfgtmp: % FORCE
+ $(Q)mkdir -p $(dir $@)
+ $(call if_changed_dep,cpp_cfg)
+
+quiet_cmd_mkimage = UIMAGE $@
+cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
+ $(if $(KBUILD_VERBOSE:1=), >/dev/null)
+
+MKIMAGEFLAGS_u-boot.imx = -n $(filter-out $< $(PHONY),$^) -T imximage \
+ -e $(CONFIG_SYS_TEXT_BASE)
+
+u-boot.imx: u-boot.bin $(IMX_CONFIG) FORCE
+ $(call if_changed,mkimage)
+
+MKIMAGEFLAGS_SPL = -n $(filter-out $< $(PHONY),$^) -T imximage \
+ -e $(CONFIG_SPL_TEXT_BASE)
+
+SPL: spl/u-boot-spl.bin $(IMX_CONFIG) FORCE
+ $(call if_changed,mkimage)
+
+MKIMAGEFLAGS_u-boot.uim = -A arm -O U-Boot -a $(CONFIG_SYS_TEXT_BASE) \
+ -e $(CONFIG_SYS_TEXT_BASE) -C none
+
+u-boot.uim: u-boot.bin FORCE
+ $(call if_changed,mkimage)
+
+OBJCOPYFLAGS += -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO)
+append = cat $(filter-out $< $(PHONY), $^) >> $@
+
+quiet_cmd_pad_cat = CAT $@
+cmd_pad_cat = $(cmd_objcopy) && $(append) || rm -f $@
+
+u-boot-with-spl.imx: SPL u-boot.uim FORCE
+ $(call if_changed,pad_cat)
+
+u-boot-with-nand-spl.imx: spl/u-boot-nand-spl.imx u-boot.uim FORCE
+ $(call if_changed,pad_cat)
+
+quiet_cmd_u-boot-nand-spl_imx = GEN $@
+cmd_u-boot-nand-spl_imx = (echo -ne '\x00\x00\x00\x00\x46\x43\x42\x20\x01' && \
+ dd bs=1015 count=1 if=/dev/zero 2>/dev/null) | cat - $< > $@
+
+spl/u-boot-nand-spl.imx: SPL FORCE
+ $(call if_changed,u-boot-nand-spl_imx)
+
+targets += $(addprefix ../../../,$(IMX_CONFIG) SPL u-boot.uim spl/u-boot-nand-spl.imx)
unsigned int resv11[1];
unsigned int wkup_uart0ctrl; /* offset 0xB4 */
unsigned int wkup_i2c0ctrl; /* offset 0xB8 */
- unsigned int resv12[7];
+ unsigned int wkup_adctscctrl; /* offset 0xBC */
+ unsigned int resv12[6];
unsigned int divm6dpllcore; /* offset 0xD8 */
};
unsigned int tpccclkctrl; /* offset 0xBC */
unsigned int dcan0clkctrl; /* offset 0xC0 */
unsigned int dcan1clkctrl; /* offset 0xC4 */
- unsigned int resv6[2];
+ unsigned int resv6;
+ unsigned int epwmss1clkctrl; /* offset 0xCC */
unsigned int emiffwclkctrl; /* offset 0xD0 */
unsigned int epwmss0clkctrl; /* offset 0xD4 */
unsigned int epwmss2clkctrl; /* offset 0xD8 */
unsigned int mcasp1clkctrl; /* offset 0x240 */
unsigned int resv11;
unsigned int mmc2clkctrl; /* offset 0x248 */
- unsigned int resv12[5];
+ unsigned int resv12[3];
+ unsigned int qspiclkctrl; /* offset 0x258 */
+ unsigned int resv121;
unsigned int usb0clkctrl; /* offset 0x260 */
unsigned int resv13[103];
unsigned int l4lsclkstctrl; /* offset 0x400 */
unsigned int gpio2clkctrl; /* offset 0x480 */
unsigned int resv20;
unsigned int gpio3clkctrl; /* offset 0x488 */
- unsigned int resv21[7];
+ unsigned int resv41;
+ unsigned int gpio4clkctrl; /* offset 0x490 */
+ unsigned int resv42;
+ unsigned int gpio5clkctrl; /* offset 0x498 */
+ unsigned int resv21[3];
unsigned int i2c1clkctrl; /* offset 0x4A8 */
unsigned int resv22;
#define MT41J128MJT125_PHY_FIFO_WE 0x100
#define MT41J128MJT125_IOCTRL_VALUE 0x18B
+/* Micron MT41K128M16JT-187E */
+#define MT41K128MJT187E_EMIF_READ_LATENCY 0x06
+#define MT41K128MJT187E_EMIF_TIM1 0x0888B3DB
+#define MT41K128MJT187E_EMIF_TIM2 0x36337FDA
+#define MT41K128MJT187E_EMIF_TIM3 0x501F830F
+#define MT41K128MJT187E_EMIF_SDCFG 0x61C04AB2
+#define MT41K128MJT187E_EMIF_SDREF 0x0000093B
+#define MT41K128MJT187E_ZQ_CFG 0x50074BE4
+#define MT41K128MJT187E_RATIO 0x40
+#define MT41K128MJT187E_INVERT_CLKOUT 0x1
+#define MT41K128MJT187E_RD_DQS 0x3B
+#define MT41K128MJT187E_WR_DQS 0x85
+#define MT41K128MJT187E_PHY_WR_DATA 0xC1
+#define MT41K128MJT187E_PHY_FIFO_WE 0x100
+#define MT41K128MJT187E_IOCTRL_VALUE 0x18B
+
/* Micron MT41J64M16JT-125 */
#define MT41J64MJT125_EMIF_SDCFG 0x61C04A32
#define AM33XX_GPIO1_BASE 0x4804C000
#define AM33XX_GPIO2_BASE 0x481AC000
#define AM33XX_GPIO3_BASE 0x481AE000
-
-#define GPIO_22 22
+#define AM33XX_GPIO4_BASE 0x48320000
+#define AM33XX_GPIO5_BASE 0x48322000
/* GPIO CTRL register */
#define GPIO_CTRL_DISABLEMODULE_SHIFT 0
#define SRAM_SCRATCH_SPACE_ADDR 0x40337C00
#define AM4372_BOARD_NAME_START SRAM_SCRATCH_SPACE_ADDR
#define AM4372_BOARD_NAME_END SRAM_SCRATCH_SPACE_ADDR + 0xC
+#define QSPI_BASE 0x47900000
#endif
#endif
u32 get_cpu_rev(void);
u32 get_sysboot_value(void);
-#ifdef CONFIG_DISPLAY_CPUINFO
-int print_cpuinfo(void);
-#endif
-
extern struct ctrl_stat *cstat;
u32 get_device_type(void);
void save_omap_boot_params(void);
--- /dev/null
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ARCH_BCM281XX_GPIO_H
+#define __ARCH_BCM281XX_GPIO_H
+
+/*
+ * Empty file - cmd_gpio.c requires this. The implementation
+ * is in drivers/gpio/kona_gpio.c instead of inlined here.
+ */
+
+#endif
--- /dev/null
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ARCH_BCM281XX_SYSMAP_H
+
+#define BSC1_BASE_ADDR 0x3e016000
+#define BSC2_BASE_ADDR 0x3e017000
+#define BSC3_BASE_ADDR 0x3e018000
+#define GPIO2_BASE_ADDR 0x35003000
+#define KONA_MST_CLK_BASE_ADDR 0x3f001000
+#define KONA_SLV_CLK_BASE_ADDR 0x3e011000
+#define PMU_BSC_BASE_ADDR 0x3500d000
+#define PWRMGR_BASE_ADDR 0x35010000
+#define SDIO1_BASE_ADDR 0x3f180000
+#define SDIO2_BASE_ADDR 0x3f190000
+#define SDIO3_BASE_ADDR 0x3f1a0000
+#define SDIO4_BASE_ADDR 0x3f1b0000
+#define SECWD_BASE_ADDR 0x3500c000
+#define SECWD2_BASE_ADDR 0x35002f40
+#define TIMER_BASE_ADDR 0x3e00d000
+
+#endif
#define BCM2835_MBOX_POWER_DEVID_SPI 7
#define BCM2835_MBOX_POWER_DEVID_CCP2TX 8
-#define BCM2835_MBOX_POWER_STATE_RESP_ON (1 << 1)
+#define BCM2835_MBOX_POWER_STATE_RESP_ON (1 << 0)
/* Device doesn't exist */
#define BCM2835_MBOX_POWER_STATE_RESP_NODEV (1 << 1)
static inline void s5p_set_cpu_id(void)
{
- unsigned int pro_id = (readl(EXYNOS4_PRO_ID) & 0x00FFF000) >> 12;
+ unsigned int pro_id = readl(EXYNOS4_PRO_ID);
+ unsigned int cpu_id = (pro_id & 0x00FFF000) >> 12;
+ unsigned int cpu_rev = pro_id & 0x000000FF;
- switch (pro_id) {
+ switch (cpu_id) {
case 0x200:
/* Exynos4210 EVT0 */
s5p_cpu_id = 0x4210;
case 0x210:
/* Exynos4210 EVT1 */
s5p_cpu_id = 0x4210;
+ s5p_cpu_rev = cpu_rev;
break;
case 0x412:
/* Exynos4412 */
s5p_cpu_id = 0x4412;
+ s5p_cpu_rev = cpu_rev;
break;
case 0x520:
/* Exynos5250 */
#define MPSCTRL_ENCRYPTION (0x1<<1)
#define MPSCTRL_VALID (0x1<<0)
+/* CLKSEL Register */
+#define DWMCI_DIVRATIO_BIT 24
+#define DWMCI_DIVRATIO_MASK 0x7
+
#ifdef CONFIG_OF_CONTROL
int exynos_dwmmc_init(const void *blob);
#endif
/* GPIO pins per bank */
#define GPIO_PER_BANK 8
-
-#define exynos4_gpio_part1_get_nr(bank, pin) \
- ((((((unsigned int) &(((struct exynos4_gpio_part1 *) \
- EXYNOS4_GPIO_PART1_BASE)->bank)) \
- - EXYNOS4_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
- * GPIO_PER_BANK) + pin)
-
-#define EXYNOS4_GPIO_PART1_MAX ((sizeof(struct exynos4_gpio_part1) \
- / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
-
-#define exynos4_gpio_part2_get_nr(bank, pin) \
- (((((((unsigned int) &(((struct exynos4_gpio_part2 *) \
- EXYNOS4_GPIO_PART2_BASE)->bank)) \
- - EXYNOS4_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
- * GPIO_PER_BANK) + pin) + EXYNOS4_GPIO_PART1_MAX)
-
-#define exynos4x12_gpio_part1_get_nr(bank, pin) \
- ((((((unsigned int) &(((struct exynos4x12_gpio_part1 *) \
- EXYNOS4X12_GPIO_PART1_BASE)->bank)) \
- - EXYNOS4X12_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
- * GPIO_PER_BANK) + pin)
-
-#define EXYNOS4X12_GPIO_PART1_MAX ((sizeof(struct exynos4x12_gpio_part1) \
- / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
-
-#define exynos4x12_gpio_part2_get_nr(bank, pin) \
- (((((((unsigned int) &(((struct exynos4x12_gpio_part2 *) \
- EXYNOS4X12_GPIO_PART2_BASE)->bank)) \
- - EXYNOS4X12_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
- * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART1_MAX)
-
-#define EXYNOS4X12_GPIO_PART2_MAX ((sizeof(struct exynos4x12_gpio_part2) \
- / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
-
-#define exynos4x12_gpio_part3_get_nr(bank, pin) \
- (((((((unsigned int) &(((struct exynos4x12_gpio_part3 *) \
- EXYNOS4X12_GPIO_PART3_BASE)->bank)) \
- - EXYNOS4X12_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
- * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART2_MAX)
-
-#define exynos5_gpio_part1_get_nr(bank, pin) \
- ((((((unsigned int) &(((struct exynos5_gpio_part1 *) \
- EXYNOS5_GPIO_PART1_BASE)->bank)) \
- - EXYNOS5_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
- * GPIO_PER_BANK) + pin)
-
-#define EXYNOS5_GPIO_PART1_MAX ((sizeof(struct exynos5_gpio_part1) \
- / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
-
-#define exynos5_gpio_part2_get_nr(bank, pin) \
- (((((((unsigned int) &(((struct exynos5_gpio_part2 *) \
- EXYNOS5_GPIO_PART2_BASE)->bank)) \
- - EXYNOS5_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
- * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART1_MAX)
-
-#define EXYNOS5_GPIO_PART2_MAX ((sizeof(struct exynos5_gpio_part2) \
- / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
-
-#define exynos5_gpio_part3_get_nr(bank, pin) \
- (((((((unsigned int) &(((struct exynos5_gpio_part3 *) \
- EXYNOS5_GPIO_PART3_BASE)->bank)) \
- - EXYNOS5_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
- * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART2_MAX)
-
-
-/* EXYNOS5420 */
-#define exynos5420_gpio_part1_get_nr(bank, pin) \
- ((((((unsigned int) &(((struct exynos5420_gpio_part1 *)\
- EXYNOS5420_GPIO_PART1_BASE)->bank)) \
- - EXYNOS5420_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
- * GPIO_PER_BANK) + pin)
-
-#define EXYNOS5420_GPIO_PART1_MAX ((sizeof(struct exynos5420_gpio_part1) \
- / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
-
-#define exynos5420_gpio_part2_get_nr(bank, pin) \
- (((((((unsigned int) &(((struct exynos5420_gpio_part2 *)\
- EXYNOS5420_GPIO_PART2_BASE)->bank)) \
- - EXYNOS5420_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
- * GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART1_MAX)
-
-#define EXYNOS5420_GPIO_PART2_MAX ((sizeof(struct exynos5420_gpio_part2) \
- / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
-
-#define exynos5420_gpio_part3_get_nr(bank, pin) \
- (((((((unsigned int) &(((struct exynos5420_gpio_part3 *)\
- EXYNOS5420_GPIO_PART3_BASE)->bank)) \
- - EXYNOS5420_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
- * GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART2_MAX)
-
-#define EXYNOS5420_GPIO_PART3_MAX ((sizeof(struct exynos5420_gpio_part3) \
- / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
-
-#define exynos5420_gpio_part4_get_nr(bank, pin) \
- (((((((unsigned int) &(((struct exynos5420_gpio_part4 *)\
- EXYNOS5420_GPIO_PART4_BASE)->bank)) \
- - EXYNOS5420_GPIO_PART4_BASE) / sizeof(struct s5p_gpio_bank)) \
- * GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART3_MAX)
-
-#define EXYNOS5420_GPIO_PART4_MAX ((sizeof(struct exynos5420_gpio_part4) \
- / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
-
-#define EXYNOS5420_GPIO_PART5_MAX ((sizeof(struct exynos5420_gpio_part5) \
- / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
-
-static inline unsigned int s5p_gpio_base(int nr)
+#define S5P_GPIO_PART_SHIFT (24)
+#define S5P_GPIO_PART_MASK (0xff)
+#define S5P_GPIO_BANK_SHIFT (8)
+#define S5P_GPIO_BANK_MASK (0xffff)
+#define S5P_GPIO_PIN_MASK (0xff)
+
+#define S5P_GPIO_SET_PART(x) \
+ (((x) & S5P_GPIO_PART_MASK) << S5P_GPIO_PART_SHIFT)
+
+#define S5P_GPIO_GET_PART(x) \
+ (((x) >> S5P_GPIO_PART_SHIFT) & S5P_GPIO_PART_MASK)
+
+#define S5P_GPIO_SET_PIN(x) \
+ ((x) & S5P_GPIO_PIN_MASK)
+
+#define EXYNOS4_GPIO_SET_BANK(part, bank) \
+ ((((unsigned)&(((struct exynos4_gpio_part##part *) \
+ EXYNOS4_GPIO_PART##part##_BASE)->bank) \
+ - EXYNOS4_GPIO_PART##part##_BASE) \
+ & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
+
+#define EXYNOS4X12_GPIO_SET_BANK(part, bank) \
+ ((((unsigned)&(((struct exynos4x12_gpio_part##part *) \
+ EXYNOS4X12_GPIO_PART##part##_BASE)->bank) \
+ - EXYNOS4X12_GPIO_PART##part##_BASE) \
+ & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
+
+#define EXYNOS5_GPIO_SET_BANK(part, bank) \
+ ((((unsigned)&(((struct exynos5420_gpio_part##part *) \
+ EXYNOS5420_GPIO_PART##part##_BASE)->bank) \
+ - EXYNOS5_GPIO_PART##part##_BASE) \
+ & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
+
+#define EXYNOS5420_GPIO_SET_BANK(part, bank) \
+ ((((unsigned)&(((struct exynos5420_gpio_part##part *) \
+ EXYNOS5420_GPIO_PART##part##_BASE)->bank) \
+ - EXYNOS5420_GPIO_PART##part##_BASE) \
+ & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
+
+#define exynos4_gpio_get(part, bank, pin) \
+ (S5P_GPIO_SET_PART(part) | \
+ EXYNOS4_GPIO_SET_BANK(part, bank) | \
+ S5P_GPIO_SET_PIN(pin))
+
+#define exynos4x12_gpio_get(part, bank, pin) \
+ (S5P_GPIO_SET_PART(part) | \
+ EXYNOS4X12_GPIO_SET_BANK(part, bank) | \
+ S5P_GPIO_SET_PIN(pin))
+
+#define exynos5420_gpio_get(part, bank, pin) \
+ (S5P_GPIO_SET_PART(part) | \
+ EXYNOS5420_GPIO_SET_BANK(part, bank) | \
+ S5P_GPIO_SET_PIN(pin))
+
+#define exynos5_gpio_get(part, bank, pin) \
+ (S5P_GPIO_SET_PART(part) | \
+ EXYNOS5_GPIO_SET_BANK(part, bank) | \
+ S5P_GPIO_SET_PIN(pin))
+
+static inline unsigned int s5p_gpio_base(int gpio)
{
- if (cpu_is_exynos5()) {
- if (proid_is_exynos5420()) {
- if (nr < EXYNOS5420_GPIO_PART1_MAX)
- return EXYNOS5420_GPIO_PART1_BASE;
- else if (nr < EXYNOS5420_GPIO_PART2_MAX)
- return EXYNOS5420_GPIO_PART2_BASE;
- else if (nr < EXYNOS5420_GPIO_PART3_MAX)
- return EXYNOS5420_GPIO_PART3_BASE;
- else
- return EXYNOS5420_GPIO_PART4_BASE;
- } else {
- if (nr < EXYNOS5_GPIO_PART1_MAX)
- return EXYNOS5_GPIO_PART1_BASE;
- else if (nr < EXYNOS5_GPIO_PART2_MAX)
- return EXYNOS5_GPIO_PART2_BASE;
- else
- return EXYNOS5_GPIO_PART3_BASE;
- }
- } else if (cpu_is_exynos4()) {
- if (nr < EXYNOS4_GPIO_PART1_MAX)
- return EXYNOS4_GPIO_PART1_BASE;
- else
- return EXYNOS4_GPIO_PART2_BASE;
+ unsigned gpio_part = S5P_GPIO_GET_PART(gpio);
+
+ switch (gpio_part) {
+ case 1:
+ return samsung_get_base_gpio_part1();
+ case 2:
+ return samsung_get_base_gpio_part2();
+ case 3:
+ return samsung_get_base_gpio_part3();
+ case 4:
+ return samsung_get_base_gpio_part4();
+ default:
+ return 0;
}
-
- return 0;
-}
-
-static inline unsigned int s5p_gpio_part_max(int nr)
-{
- if (cpu_is_exynos5()) {
- if (proid_is_exynos5420()) {
- if (nr < EXYNOS5420_GPIO_PART1_MAX)
- return 0;
- else if (nr < EXYNOS5420_GPIO_PART2_MAX)
- return EXYNOS5420_GPIO_PART1_MAX;
- else if (nr < EXYNOS5420_GPIO_PART3_MAX)
- return EXYNOS5420_GPIO_PART2_MAX;
- else if (nr < EXYNOS5420_GPIO_PART4_MAX)
- return EXYNOS5420_GPIO_PART3_MAX;
- else
- return EXYNOS5420_GPIO_PART4_MAX;
- } else {
- if (nr < EXYNOS5_GPIO_PART1_MAX)
- return 0;
- else if (nr < EXYNOS5_GPIO_PART2_MAX)
- return EXYNOS5_GPIO_PART1_MAX;
- else
- return EXYNOS5_GPIO_PART2_MAX;
- }
- } else if (cpu_is_exynos4()) {
- if (proid_is_exynos4412()) {
- if (nr < EXYNOS4X12_GPIO_PART1_MAX)
- return 0;
- else if (nr < EXYNOS4X12_GPIO_PART2_MAX)
- return EXYNOS4X12_GPIO_PART1_MAX;
- else
- return EXYNOS4X12_GPIO_PART2_MAX;
- } else {
- if (nr < EXYNOS4_GPIO_PART1_MAX)
- return 0;
- else
- return EXYNOS4_GPIO_PART1_MAX;
- }
- }
-
- return 0;
}
#endif
PERIPH_ID_SDMMC3,
PERIPH_ID_I2C8 = 87,
PERIPH_ID_I2C9,
- PERIPH_ID_I2C10 = 203,
PERIPH_ID_I2S0 = 98,
PERIPH_ID_I2S1 = 99,
PERIPH_ID_PWM2,
PERIPH_ID_PWM3,
PERIPH_ID_PWM4,
+ PERIPH_ID_I2C10 = 203,
- PERIPH_ID_COUNT,
PERIPH_ID_NONE = -1,
};
+++ /dev/null
-/*
- * include/asm-arm/arch-ixp425/ixp425.h
- *
- * Register definitions for IXP425
- *
- * Copyright (C) 2002 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef _ASM_ARM_IXP425_H_
-#define _ASM_ARM_IXP425_H_
-
-#define BIT(x) (1<<(x))
-
-/* FIXME: Only this does work for u-boot... find out why... [RS] */
-#define UBOOT_REG_FIX 1
-#ifdef UBOOT_REG_FIX
-# undef io_p2v
-# undef __REG
-# ifndef __ASSEMBLY__
-# define io_p2v(PhAdd) (PhAdd)
-# define __REG(x) (*((volatile u32 *)io_p2v(x)))
-# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y)))
-# else
-# define __REG(x) (x)
-# endif
-#endif /* UBOOT_REG_FIX */
-
-/*
- *
- * IXP425 Memory map:
- *
- * Phy Phy Size Map Size Virt Description
- * =========================================================================
- *
- * 0x00000000 0x10000000 SDRAM 1
- *
- * 0x10000000 0x10000000 SDRAM 2
- *
- * 0x20000000 0x10000000 SDRAM 3
- *
- * 0x30000000 0x10000000 SDRAM 4
- *
- * The above four are aliases to the same memory location (0x00000000)
- *
- * 0x48000000 0x4000000 PCI Memory
- *
- * 0x50000000 0x10000000 Not Mapped EXP BUS
- *
- * 0x6000000 0x00004000 0x4000 0xFFFEB000 QMgr
- *
- * 0xC0000000 0x100 0x1000 0xFFFDD000 PCI CFG
- *
- * 0xC4000000 0x100 0x1000 0xFFFDE000 EXP CFG
- *
- * 0xC8000000 0xC000 0xC000 0xFFFDF000 PERIPHERAL
- *
- * 0xCC000000 0x100 0x1000 Not Mapped SDRAM CFG
- */
-
-/*
- * SDRAM
- */
-#define IXP425_SDRAM_BASE (0x00000000)
-#define IXP425_SDRAM_BASE_ALT (0x10000000)
-
-
-/*
- * PCI Configuration space
- */
-#define IXP425_PCI_CFG_BASE_PHYS (0xC0000000)
-#define IXP425_PCI_CFG_REGION_SIZE (0x00001000)
-
-/*
- * Expansion BUS Configuration registers
- */
-#define IXP425_EXP_CFG_BASE_PHYS (0xC4000000)
-#define IXP425_EXP_CFG_REGION_SIZE (0x00001000)
-
-/*
- * Peripheral space
- */
-#define IXP425_PERIPHERAL_BASE_PHYS (0xC8000000)
-#define IXP425_PERIPHERAL_REGION_SIZE (0x0000C000)
-
-/*
- * SDRAM configuration registers
- */
-#define IXP425_SDRAM_CFG_BASE_PHYS (0xCC000000)
-
-/*
- * Q Manager space .. not static mapped
- */
-#define IXP425_QMGR_BASE_PHYS (0x60000000)
-#define IXP425_QMGR_REGION_SIZE (0x00004000)
-
-/*
- * Expansion BUS
- *
- * Expansion Bus 'lives' at either base1 or base 2 depending on the value of
- * Exp Bus config registers:
- *
- * Setting bit 31 of IXP425_EXP_CFG0 puts SDRAM at zero,
- * and The expansion bus to IXP425_EXP_BUS_BASE2
- */
-#define IXP425_EXP_BUS_BASE1_PHYS (0x00000000)
-#define IXP425_EXP_BUS_BASE2_PHYS (0x50000000)
-
-#define IXP425_EXP_BUS_BASE_PHYS IXP425_EXP_BUS_BASE2_PHYS
-
-#define IXP425_EXP_BUS_REGION_SIZE (0x08000000)
-#define IXP425_EXP_BUS_CSX_REGION_SIZE (0x01000000)
-
-#define IXP425_EXP_BUS_CS0_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x00000000)
-#define IXP425_EXP_BUS_CS1_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x01000000)
-#define IXP425_EXP_BUS_CS2_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x02000000)
-#define IXP425_EXP_BUS_CS3_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x03000000)
-#define IXP425_EXP_BUS_CS4_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x04000000)
-#define IXP425_EXP_BUS_CS5_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x05000000)
-#define IXP425_EXP_BUS_CS6_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x06000000)
-#define IXP425_EXP_BUS_CS7_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x07000000)
-
-#define IXP425_FLASH_WRITABLE (0x2)
-#define IXP425_FLASH_DEFAULT (0xbcd23c40)
-#define IXP425_FLASH_WRITE (0xbcd23c42)
-
-#define IXP425_EXP_CS0_OFFSET 0x00
-#define IXP425_EXP_CS1_OFFSET 0x04
-#define IXP425_EXP_CS2_OFFSET 0x08
-#define IXP425_EXP_CS3_OFFSET 0x0C
-#define IXP425_EXP_CS4_OFFSET 0x10
-#define IXP425_EXP_CS5_OFFSET 0x14
-#define IXP425_EXP_CS6_OFFSET 0x18
-#define IXP425_EXP_CS7_OFFSET 0x1C
-#define IXP425_EXP_CFG0_OFFSET 0x20
-#define IXP425_EXP_CFG1_OFFSET 0x24
-#define IXP425_EXP_CFG2_OFFSET 0x28
-#define IXP425_EXP_CFG3_OFFSET 0x2C
-
-/*
- * Expansion Bus Controller registers.
- */
-#ifndef __ASSEMBLY__
-#define IXP425_EXP_REG(x) ((volatile u32 *)(IXP425_EXP_CFG_BASE_PHYS+(x)))
-#else
-#define IXP425_EXP_REG(x) (IXP425_EXP_CFG_BASE_PHYS+(x))
-#endif
-
-#define IXP425_EXP_CS0 IXP425_EXP_REG(IXP425_EXP_CS0_OFFSET)
-#define IXP425_EXP_CS1 IXP425_EXP_REG(IXP425_EXP_CS1_OFFSET)
-#define IXP425_EXP_CS2 IXP425_EXP_REG(IXP425_EXP_CS2_OFFSET)
-#define IXP425_EXP_CS3 IXP425_EXP_REG(IXP425_EXP_CS3_OFFSET)
-#define IXP425_EXP_CS4 IXP425_EXP_REG(IXP425_EXP_CS4_OFFSET)
-#define IXP425_EXP_CS5 IXP425_EXP_REG(IXP425_EXP_CS5_OFFSET)
-#define IXP425_EXP_CS6 IXP425_EXP_REG(IXP425_EXP_CS6_OFFSET)
-#define IXP425_EXP_CS7 IXP425_EXP_REG(IXP425_EXP_CS7_OFFSET)
-
-#define IXP425_EXP_CFG0 IXP425_EXP_REG(IXP425_EXP_CFG0_OFFSET)
-#define IXP425_EXP_CFG1 IXP425_EXP_REG(IXP425_EXP_CFG1_OFFSET)
-#define IXP425_EXP_CFG2 IXP425_EXP_REG(IXP425_EXP_CFG2_OFFSET)
-#define IXP425_EXP_CFG3 IXP425_EXP_REG(IXP425_EXP_CFG3_OFFSET)
-
-/*
- * SDRAM Controller registers.
- */
-#define IXP425_SDR_CONFIG_OFFSET 0x00
-#define IXP425_SDR_REFRESH_OFFSET 0x04
-#define IXP425_SDR_IR_OFFSET 0x08
-
-#define IXP425_SDRAM_REG(x) (IXP425_SDRAM_CFG_BASE_PHYS+(x))
-
-#define IXP425_SDR_CONFIG IXP425_SDRAM_REG(IXP425_SDR_CONFIG_OFFSET)
-#define IXP425_SDR_REFRESH IXP425_SDRAM_REG(IXP425_SDR_REFRESH_OFFSET)
-#define IXP425_SDR_IR IXP425_SDRAM_REG(IXP425_SDR_IR_OFFSET)
-
-/*
- * UART registers
- */
-#define IXP425_UART1 0
-#define IXP425_UART2 0x1000
-
-#define IXP425_UART_RBR_OFFSET 0x00
-#define IXP425_UART_THR_OFFSET 0x00
-#define IXP425_UART_DLL_OFFSET 0x00
-#define IXP425_UART_IER_OFFSET 0x04
-#define IXP425_UART_DLH_OFFSET 0x04
-#define IXP425_UART_IIR_OFFSET 0x08
-#define IXP425_UART_FCR_OFFSET 0x00
-#define IXP425_UART_LCR_OFFSET 0x0c
-#define IXP425_UART_MCR_OFFSET 0x10
-#define IXP425_UART_LSR_OFFSET 0x14
-#define IXP425_UART_MSR_OFFSET 0x18
-#define IXP425_UART_SPR_OFFSET 0x1c
-#define IXP425_UART_ISR_OFFSET 0x20
-
-#define IXP425_UART_CFG_BASE_PHYS (0xc8000000)
-
-#define RBR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_RBR_OFFSET)
-#define THR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_THR_OFFSET)
-#define DLL(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLL_OFFSET)
-#define IER(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IER_OFFSET)
-#define DLH(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLH_OFFSET)
-#define IIR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IIR_OFFSET)
-#define FCR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_FCR_OFFSET)
-#define LCR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LCR_OFFSET)
-#define MCR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MCR_OFFSET)
-#define LSR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LSR_OFFSET)
-#define MSR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MSR_OFFSET)
-#define SPR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_SPR_OFFSET)
-#define ISR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_ISR_OFFSET)
-
-#define IER_DMAE (1 << 7) /* DMA Requests Enable */
-#define IER_UUE (1 << 6) /* UART Unit Enable */
-#define IER_NRZE (1 << 5) /* NRZ coding Enable */
-#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */
-#define IER_MIE (1 << 3) /* Modem Interrupt Enable */
-#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */
-#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */
-#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */
-
-#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */
-#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */
-#define IIR_TOD (1 << 3) /* Time Out Detected */
-#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */
-#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */
-#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */
-
-#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */
-#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */
-#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */
-#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */
-#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */
-#define FCR_ITL_1 (0)
-#define FCR_ITL_8 (FCR_ITL1)
-#define FCR_ITL_16 (FCR_ITL2)
-#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
-
-#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
-#define LCR_SB (1 << 6) /* Set Break */
-#define LCR_STKYP (1 << 5) /* Sticky Parity */
-#define LCR_EPS (1 << 4) /* Even Parity Select */
-#define LCR_PEN (1 << 3) /* Parity Enable */
-#define LCR_STB (1 << 2) /* Stop Bit */
-#define LCR_WLS1 (1 << 1) /* Word Length Select */
-#define LCR_WLS0 (1 << 0) /* Word Length Select */
-
-#define LSR_FIFOE (1 << 7) /* FIFO Error Status */
-#define LSR_TEMT (1 << 6) /* Transmitter Empty */
-#define LSR_TDRQ (1 << 5) /* Transmit Data Request */
-#define LSR_BI (1 << 4) /* Break Interrupt */
-#define LSR_FE (1 << 3) /* Framing Error */
-#define LSR_PE (1 << 2) /* Parity Error */
-#define LSR_OE (1 << 1) /* Overrun Error */
-#define LSR_DR (1 << 0) /* Data Ready */
-
-#define MCR_LOOP (1 << 4) */
-#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
-#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
-#define MCR_RTS (1 << 1) /* Request to Send */
-#define MCR_DTR (1 << 0) /* Data Terminal Ready */
-
-#define MSR_DCD (1 << 7) /* Data Carrier Detect */
-#define MSR_RI (1 << 6) /* Ring Indicator */
-#define MSR_DSR (1 << 5) /* Data Set Ready */
-#define MSR_CTS (1 << 4) /* Clear To Send */
-#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */
-#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */
-#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
-#define MSR_DCTS (1 << 0) /* Delta Clear To Send */
-
-#define IXP425_CONSOLE_UART_BASE_PHYS IXP425_UART1_BASE_PHYS
-/*
- * Peripheral Space Registers
- */
-#define IXP425_UART1_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x0000)
-#define IXP425_UART2_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x1000)
-#define IXP425_PMU_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x2000)
-#define IXP425_INTC_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x3000)
-#define IXP425_GPIO_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x4000)
-#define IXP425_TIMER_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x5000)
-#define IXP425_NPEA_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x6000)
-#define IXP425_NPEB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x7000)
-#define IXP425_NPEC_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x8000)
-#define IXP425_EthA_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x9000)
-#define IXP425_EthB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0xA000)
-#define IXP425_USB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0xB000)
-
-/*
- * UART Register Definitions , Offsets only as there are 2 UARTS.
- * IXP425_UART1_BASE , IXP425_UART2_BASE.
- */
-
-#undef UART_NO_RX_INTERRUPT
-
-#define IXP425_UART_XTAL 14745600
-
-/*
- * Constants to make it easy to access Interrupt Controller registers
- */
-#define IXP425_ICPR_OFFSET 0x00 /* Interrupt Status */
-#define IXP425_ICMR_OFFSET 0x04 /* Interrupt Enable */
-#define IXP425_ICLR_OFFSET 0x08 /* Interrupt IRQ/FIQ Select */
-#define IXP425_ICIP_OFFSET 0x0C /* IRQ Status */
-#define IXP425_ICFP_OFFSET 0x10 /* FIQ Status */
-#define IXP425_ICHR_OFFSET 0x14 /* Interrupt Priority */
-#define IXP425_ICIH_OFFSET 0x18 /* IRQ Highest Pri Int */
-#define IXP425_ICFH_OFFSET 0x1C /* FIQ Highest Pri Int */
-
-#define N_IRQS 32
-#define IXP425_TIMER_2_IRQ 11
-
-/*
- * Interrupt Controller Register Definitions.
- */
-#ifndef __ASSEMBLY__
-#define IXP425_INTC_REG(x) ((volatile u32 *)(IXP425_INTC_BASE_PHYS+(x)))
-#else
-#define IXP425_INTC_REG(x) (IXP425_INTC_BASE_PHYS+(x))
-#endif
-
-#define IXP425_ICPR IXP425_INTC_REG(IXP425_ICPR_OFFSET)
-#define IXP425_ICMR IXP425_INTC_REG(IXP425_ICMR_OFFSET)
-#define IXP425_ICLR IXP425_INTC_REG(IXP425_ICLR_OFFSET)
-#define IXP425_ICIP IXP425_INTC_REG(IXP425_ICIP_OFFSET)
-#define IXP425_ICFP IXP425_INTC_REG(IXP425_ICFP_OFFSET)
-#define IXP425_ICHR IXP425_INTC_REG(IXP425_ICHR_OFFSET)
-#define IXP425_ICIH IXP425_INTC_REG(IXP425_ICIH_OFFSET)
-#define IXP425_ICFH IXP425_INTC_REG(IXP425_ICFH_OFFSET)
-
-/*
- * Constants to make it easy to access GPIO registers
- */
-#define IXP425_GPIO_GPOUTR_OFFSET 0x00
-#define IXP425_GPIO_GPOER_OFFSET 0x04
-#define IXP425_GPIO_GPINR_OFFSET 0x08
-#define IXP425_GPIO_GPISR_OFFSET 0x0C
-#define IXP425_GPIO_GPIT1R_OFFSET 0x10
-#define IXP425_GPIO_GPIT2R_OFFSET 0x14
-#define IXP425_GPIO_GPCLKR_OFFSET 0x18
-#define IXP425_GPIO_GPDBSELR_OFFSET 0x1C
-
-/*
- * GPIO Register Definitions.
- * [Only perform 32bit reads/writes]
- */
-#define IXP425_GPIO_REG(x) ((volatile u32 *)(IXP425_GPIO_BASE_PHYS+(x)))
-
-#define IXP425_GPIO_GPOUTR IXP425_GPIO_REG(IXP425_GPIO_GPOUTR_OFFSET)
-#define IXP425_GPIO_GPOER IXP425_GPIO_REG(IXP425_GPIO_GPOER_OFFSET)
-#define IXP425_GPIO_GPINR IXP425_GPIO_REG(IXP425_GPIO_GPINR_OFFSET)
-#define IXP425_GPIO_GPISR IXP425_GPIO_REG(IXP425_GPIO_GPISR_OFFSET)
-#define IXP425_GPIO_GPIT1R IXP425_GPIO_REG(IXP425_GPIO_GPIT1R_OFFSET)
-#define IXP425_GPIO_GPIT2R IXP425_GPIO_REG(IXP425_GPIO_GPIT2R_OFFSET)
-#define IXP425_GPIO_GPCLKR IXP425_GPIO_REG(IXP425_GPIO_GPCLKR_OFFSET)
-#define IXP425_GPIO_GPDBSELR IXP425_GPIO_REG(IXP425_GPIO_GPDBSELR_OFFSET)
-
-#define IXP425_GPIO_GPITR(line) (((line) >= 8) ? \
- IXP425_GPIO_GPIT2R : IXP425_GPIO_GPIT1R)
-
-/*
- * Macros to make it easy to access the GPIO registers
- */
-#define GPIO_OUTPUT_ENABLE(line) *IXP425_GPIO_GPOER &= ~(1 << (line))
-#define GPIO_OUTPUT_DISABLE(line) *IXP425_GPIO_GPOER |= (1 << (line))
-#define GPIO_OUTPUT_SET(line) *IXP425_GPIO_GPOUTR |= (1 << (line))
-#define GPIO_OUTPUT_CLEAR(line) *IXP425_GPIO_GPOUTR &= ~(1 << (line))
-#define GPIO_INT_ACT_LOW_SET(line) \
- *IXP425_GPIO_GPITR(line) = \
- (*IXP425_GPIO_GPITR(line) & \
- ~(0x7 << (((line) & 0x7) * 3))) | \
- (0x1 << (((line) & 0x7) * 3)) \
-
-/*
- * Constants to make it easy to access Timer Control/Status registers
- */
-#define IXP425_OSTS_OFFSET 0x00 /* Continious TimeStamp */
-#define IXP425_OST1_OFFSET 0x04 /* Timer 1 Timestamp */
-#define IXP425_OSRT1_OFFSET 0x08 /* Timer 1 Reload */
-#define IXP425_OST2_OFFSET 0x0C /* Timer 2 Timestamp */
-#define IXP425_OSRT2_OFFSET 0x10 /* Timer 2 Reload */
-#define IXP425_OSWT_OFFSET 0x14 /* Watchdog Timer */
-#define IXP425_OSWE_OFFSET 0x18 /* Watchdog Enable */
-#define IXP425_OSWK_OFFSET 0x1C /* Watchdog Key */
-#define IXP425_OSST_OFFSET 0x20 /* Timer Status */
-
-/*
- * Operating System Timer Register Definitions.
- */
-
-#ifndef __ASSEMBLY__
-#define IXP425_TIMER_REG(x) ((volatile u32 *)(IXP425_TIMER_BASE_PHYS+(x)))
-#else
-#define IXP425_TIMER_REG(x) (IXP425_TIMER_BASE_PHYS+(x))
-#endif
-
-/* _B to avoid collision: also defined in npe/include/... */
-#define IXP425_OSTS_B IXP425_TIMER_REG(IXP425_OSTS_OFFSET)
-#define IXP425_OST1 IXP425_TIMER_REG(IXP425_OST1_OFFSET)
-#define IXP425_OSRT1 IXP425_TIMER_REG(IXP425_OSRT1_OFFSET)
-#define IXP425_OST2 IXP425_TIMER_REG(IXP425_OST2_OFFSET)
-#define IXP425_OSRT2 IXP425_TIMER_REG(IXP425_OSRT2_OFFSET)
-#define IXP425_OSWT IXP425_TIMER_REG(IXP425_OSWT_OFFSET)
-#define IXP425_OSWE IXP425_TIMER_REG(IXP425_OSWE_OFFSET)
-#define IXP425_OSWK IXP425_TIMER_REG(IXP425_OSWK_OFFSET)
-#define IXP425_OSST IXP425_TIMER_REG(IXP425_OSST_OFFSET)
-
-/*
- * Timer register values and bit definitions
- */
-#define IXP425_OST_ENABLE BIT(0)
-#define IXP425_OST_ONE_SHOT BIT(1)
-/* Low order bits of reload value ignored */
-#define IXP425_OST_RELOAD_MASK (0x3)
-#define IXP425_OST_DISABLED (0x0)
-#define IXP425_OSST_TIMER_1_PEND BIT(0)
-#define IXP425_OSST_TIMER_2_PEND BIT(1)
-#define IXP425_OSST_TIMER_TS_PEND BIT(2)
-#define IXP425_OSST_TIMER_WDOG_PEND BIT(3)
-#define IXP425_OSST_TIMER_WARM_RESET BIT(4)
-
-/*
- * Constants to make it easy to access PCI Control/Status registers
- */
-#define PCI_NP_AD_OFFSET 0x00
-#define PCI_NP_CBE_OFFSET 0x04
-#define PCI_NP_WDATA_OFFSET 0x08
-#define PCI_NP_RDATA_OFFSET 0x0c
-#define PCI_CRP_AD_CBE_OFFSET 0x10
-#define PCI_CRP_WDATA_OFFSET 0x14
-#define PCI_CRP_RDATA_OFFSET 0x18
-#define PCI_CSR_OFFSET 0x1c
-#define PCI_ISR_OFFSET 0x20
-#define PCI_INTEN_OFFSET 0x24
-#define PCI_DMACTRL_OFFSET 0x28
-#define PCI_AHBMEMBASE_OFFSET 0x2c
-#define PCI_AHBIOBASE_OFFSET 0x30
-#define PCI_PCIMEMBASE_OFFSET 0x34
-#define PCI_AHBDOORBELL_OFFSET 0x38
-#define PCI_PCIDOORBELL_OFFSET 0x3C
-#define PCI_ATPDMA0_AHBADDR_OFFSET 0x40
-#define PCI_ATPDMA0_PCIADDR_OFFSET 0x44
-#define PCI_ATPDMA0_LENADDR_OFFSET 0x48
-#define PCI_ATPDMA1_AHBADDR_OFFSET 0x4C
-#define PCI_ATPDMA1_PCIADDR_OFFSET 0x50
-#define PCI_ATPDMA1_LENADDR_OFFSET 0x54
-
-/*
- * PCI Control/Status Registers
- */
-#define IXP425_PCI_CSR(x) ((volatile u32 *)(IXP425_PCI_CFG_BASE_PHYS+(x)))
-
-#define PCI_NP_AD IXP425_PCI_CSR(PCI_NP_AD_OFFSET)
-#define PCI_NP_CBE IXP425_PCI_CSR(PCI_NP_CBE_OFFSET)
-#define PCI_NP_WDATA IXP425_PCI_CSR(PCI_NP_WDATA_OFFSET)
-#define PCI_NP_RDATA IXP425_PCI_CSR(PCI_NP_RDATA_OFFSET)
-#define PCI_CRP_AD_CBE IXP425_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)
-#define PCI_CRP_WDATA IXP425_PCI_CSR(PCI_CRP_WDATA_OFFSET)
-#define PCI_CRP_RDATA IXP425_PCI_CSR(PCI_CRP_RDATA_OFFSET)
-#define PCI_CSR IXP425_PCI_CSR(PCI_CSR_OFFSET)
-#define PCI_ISR IXP425_PCI_CSR(PCI_ISR_OFFSET)
-#define PCI_INTEN IXP425_PCI_CSR(PCI_INTEN_OFFSET)
-#define PCI_DMACTRL IXP425_PCI_CSR(PCI_DMACTRL_OFFSET)
-#define PCI_AHBMEMBASE IXP425_PCI_CSR(PCI_AHBMEMBASE_OFFSET)
-#define PCI_AHBIOBASE IXP425_PCI_CSR(PCI_AHBIOBASE_OFFSET)
-#define PCI_PCIMEMBASE IXP425_PCI_CSR(PCI_PCIMEMBASE_OFFSET)
-#define PCI_AHBDOORBELL IXP425_PCI_CSR(PCI_AHBDOORBELL_OFFSET)
-#define PCI_PCIDOORBELL IXP425_PCI_CSR(PCI_PCIDOORBELL_OFFSET)
-#define PCI_ATPDMA0_AHBADDR IXP425_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET)
-#define PCI_ATPDMA0_PCIADDR IXP425_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET)
-#define PCI_ATPDMA0_LENADDR IXP425_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET)
-#define PCI_ATPDMA1_AHBADDR IXP425_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)
-#define PCI_ATPDMA1_PCIADDR IXP425_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)
-#define PCI_ATPDMA1_LENADDR IXP425_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)
-
-/*
- * PCI register values and bit definitions
- */
-
-/* CSR bit definitions */
-#define PCI_CSR_HOST BIT(0)
-#define PCI_CSR_ARBEN BIT(1)
-#define PCI_CSR_ADS BIT(2)
-#define PCI_CSR_PDS BIT(3)
-#define PCI_CSR_ABE BIT(4)
-#define PCI_CSR_DBT BIT(5)
-#define PCI_CSR_ASE BIT(8)
-#define PCI_CSR_IC BIT(15)
-
-/* ISR (Interrupt status) Register bit definitions */
-#define PCI_ISR_PSE BIT(0)
-#define PCI_ISR_PFE BIT(1)
-#define PCI_ISR_PPE BIT(2)
-#define PCI_ISR_AHBE BIT(3)
-#define PCI_ISR_APDC BIT(4)
-#define PCI_ISR_PADC BIT(5)
-#define PCI_ISR_ADB BIT(6)
-#define PCI_ISR_PDB BIT(7)
-
-/* INTEN (Interrupt Enable) Register bit definitions */
-#define PCI_INTEN_PSE BIT(0)
-#define PCI_INTEN_PFE BIT(1)
-#define PCI_INTEN_PPE BIT(2)
-#define PCI_INTEN_AHBE BIT(3)
-#define PCI_INTEN_APDC BIT(4)
-#define PCI_INTEN_PADC BIT(5)
-#define PCI_INTEN_ADB BIT(6)
-#define PCI_INTEN_PDB BIT(7)
-
-/*
- * Shift value for byte enable on NP cmd/byte enable register
- */
-#define IXP425_PCI_NP_CBE_BESL 4
-
-/*
- * PCI commands supported by NP access unit
- */
-#define NP_CMD_IOREAD 0x2
-#define NP_CMD_IOWRITE 0x3
-#define NP_CMD_CONFIGREAD 0xa
-#define NP_CMD_CONFIGWRITE 0xb
-#define NP_CMD_MEMREAD 0x6
-#define NP_CMD_MEMWRITE 0x7
-
-#if 0
-#ifndef __ASSEMBLY__
-extern int ixp425_pci_read(u32 addr, u32 cmd, u32* data);
-extern int ixp425_pci_write(u32 addr, u32 cmd, u32 data);
-extern void ixp425_pci_init(void *);
-#endif
-#endif
-
-/*
- * Constants for CRP access into local config space
- */
-#define CRP_AD_CBE_BESL 20
-#define CRP_AD_CBE_WRITE BIT(16)
-
-/*
- * Clock Speed Definitions.
- */
-#define IXP425_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS */
-
-
-#endif
+++ /dev/null
-/*
- * IXP PCI Init
- * (C) Copyright 2004 eslab.whut.edu.cn
- * Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _IXP425PCI_H
-#define _IXP425PCI_H
-
-#define OK 0
-#define ERROR -1
-
-struct pci_controller;
-extern void pci_ixp_init(struct pci_controller *hose);
-
-/* Mask definitions*/
-#define IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK 0x0000000f
-
-#define PCI_NP_CBE_BESL (4)
-#define PCI_NP_AD_FUNCSL (8)
-
-/*Register addressing definitions for PCI controller configuration
- and status registers*/
-
-#define PCI_CSR_BASE (0xC0000000)
-/*
-#define PCI_NP_AD_OFFSET (0x00)
-#define PCI_NP_CBE_OFFSET (0x04)
-#define PCI_NP_WDATA_OFFSET (0x08)
-#define PCI_NP_RDATA_OFFSET (0x0C)
-#define PCI_CRP_OFFSET (0x10)
-#define PCI_CRP_WDATA_OFFSET (0x14)
-#define PCI_CRP_RDATA_OFFSET (0x18)
-#define PCI_CSR_OFFSET (0x1C)
-#define PCI_ISR_OFFSET (0x20)
-#define PCI_INTEN_OFFSET (0x24)
-#define PCI_DMACTRL_OFFSET (0x28)
-#define PCI_AHBMEMBASE_OFFSET (0x2C)
-#define PCI_AHBIOBASE_OFFSET (0x30)
-#define PCI_PCIMEMBASE_OFFSET (0x34)
-#define PCI_AHBDOORBELL_OFFSET (0x38)
-#define PCI_PCIDOORBELL_OFFSET (0x3C)
-#define PCI_ATPDMA0_AHBADDR (0x40)
-#define PCI_ATPDMA0_PCIADDR (0x44)
-#define PCI_ATPDMA0_LENADDR (0x48)
-#define PCI_ATPDMA1_AHBADDR (0x4C)
-#define PCI_ATPDMA1_PCIADDR (0x50)
-#define PCI_ATPDMA1_LENADDR (0x54)
-#define PCI_PTADMA0_AHBADDR (0x58)
-#define PCI_PTADMA0_PCIADDR (0x5C)
-#define PCI_PTADMA0_LENADDR (0x60)
-#define PCI_PTADMA1_AHBADDR (0x64)
-#define PCI_PTADMA1_PCIADDR (0x68)
-#define PCI_PTADMA1_LENADDR (0x6C)
-*/
-/*Non prefetch registers bit definitions*/
-/*
-#define NP_CMD_INTACK (0x0)
-#define NP_CMD_SPECIAL (0x1)
-#define NP_CMD_IOREAD (0x2)
-#define NP_CMD_IOWRITE (0x3)
-#define NP_CMD_MEMREAD (0x6)
-#define NP_CMD_MEMWRITE (0x7)
-#define NP_CMD_CONFIGREAD (0xa)
-#define NP_CMD_CONFIGWRITE (0xb)
-*/
-
-/*Configuration Port register bit definitions*/
-#define PCI_CRP_WRITE BIT(16)
-
-/*ISR (Interrupt status) Register bit definitions*/
-#define PCI_ISR_PSE BIT(0)
-#define PCI_ISR_PFE BIT(1)
-#define PCI_ISR_PPE BIT(2)
-#define PCI_ISR_AHBE BIT(3)
-#define PCI_ISR_APDC BIT(4)
-#define PCI_ISR_PADC BIT(5)
-#define PCI_ISR_ADB BIT(6)
-#define PCI_ISR_PDB BIT(7)
-
-/*INTEN (Interrupt Enable) Register bit definitions*/
-#define PCI_INTEN_PSE BIT(0)
-#define PCI_INTEN_PFE BIT(1)
-#define PCI_INTEN_PPE BIT(2)
-#define PCI_INTEN_AHBE BIT(3)
-#define PCI_INTEN_APDC BIT(4)
-#define PCI_INTEN_PADC BIT(5)
-#define PCI_INTEN_ADB BIT(6)
-#define PCI_INTEN_PDB BIT(7)
-
-/*PCI configuration regs.*/
-
-#define PCI_CFG_VENDOR_ID 0x00
-#define PCI_CFG_DEVICE_ID 0x02
-#define PCI_CFG_COMMAND 0x04
-#define PCI_CFG_STATUS 0x06
-#define PCI_CFG_REVISION 0x08
-#define PCI_CFG_PROGRAMMING_IF 0x09
-#define PCI_CFG_SUBCLASS 0x0a
-#define PCI_CFG_CLASS 0x0b
-#define PCI_CFG_CACHE_LINE_SIZE 0x0c
-#define PCI_CFG_LATENCY_TIMER 0x0d
-#define PCI_CFG_HEADER_TYPE 0x0e
-#define PCI_CFG_BIST 0x0f
-#define PCI_CFG_BASE_ADDRESS_0 0x10
-#define PCI_CFG_BASE_ADDRESS_1 0x14
-#define PCI_CFG_BASE_ADDRESS_2 0x18
-#define PCI_CFG_BASE_ADDRESS_3 0x1c
-#define PCI_CFG_BASE_ADDRESS_4 0x20
-#define PCI_CFG_BASE_ADDRESS_5 0x24
-#define PCI_CFG_CIS 0x28
-#define PCI_CFG_SUB_VENDOR_ID 0x2c
-#define PCI_CFG_SUB_SYSTEM_ID 0x2e
-#define PCI_CFG_EXPANSION_ROM 0x30
-#define PCI_CFG_RESERVED_0 0x34
-#define PCI_CFG_RESERVED_1 0x38
-#define PCI_CFG_DEV_INT_LINE 0x3c
-#define PCI_CFG_DEV_INT_PIN 0x3d
-#define PCI_CFG_MIN_GRANT 0x3e
-#define PCI_CFG_MAX_LATENCY 0x3f
-#define PCI_CFG_SPECIAL_USE 0x41
-#define PCI_CFG_MODE 0x43
-
-#define PCI_CMD_IO_ENABLE 0x0001 /* IO access enable */
-#define PCI_CMD_MEM_ENABLE 0x0002 /* memory access enable */
-#define PCI_CMD_MASTER_ENABLE 0x0004 /* bus master enable */
-#define PCI_CMD_MON_ENABLE 0x0008 /* monitor special cycles enable */
-#define PCI_CMD_WI_ENABLE 0x0010 /* write and invalidate enable */
-#define PCI_CMD_SNOOP_ENABLE 0x0020 /* palette snoop enable */
-#define PCI_CMD_PERR_ENABLE 0x0040 /* parity error enable */
-#define PCI_CMD_WC_ENABLE 0x0080 /* wait cycle enable */
-#define PCI_CMD_SERR_ENABLE 0x0100 /* system error enable */
-#define PCI_CMD_FBTB_ENABLE 0x0200 /* fast back to back enable */
-
-
-/*CSR Register bit definitions*/
-#define PCI_CSR_HOST BIT(0)
-#define PCI_CSR_ARBEN BIT(1)
-#define PCI_CSR_ADS BIT(2)
-#define PCI_CSR_PDS BIT(3)
-#define PCI_CSR_ABE BIT(4)
-#define PCI_CSR_DBT BIT(5)
-#define PCI_CSR_ASE BIT(8)
-#define PCI_CSR_IC BIT(15)
-
-/*Configuration command bit definitions*/
-#define PCI_CFG_CMD_IOAE BIT(0)
-#define PCI_CFG_CMD_MAE BIT(1)
-#define PCI_CFG_CMD_BME BIT(2)
-#define PCI_CFG_CMD_MWIE BIT(4)
-#define PCI_CFG_CMD_SER BIT(8)
-#define PCI_CFG_CMD_FBBE BIT(9)
-#define PCI_CFG_CMD_MDPE BIT(24)
-#define PCI_CFG_CMD_STA BIT(27)
-#define PCI_CFG_CMD_RTA BIT(28)
-#define PCI_CFG_CMD_RMA BIT(29)
-#define PCI_CFG_CMD_SSE BIT(30)
-#define PCI_CFG_CMD_DPE BIT(31)
-
-/*DMACTRL DMA Control and status Register*/
-#define PCI_DMACTRL_APDCEN BIT(0)
-#define PCI_DMACTRL_APDC0 BIT(4)
-#define PCI_DMACTRL_APDE0 BIT(5)
-#define PCI_DMACTRL_APDC1 BIT(6)
-#define PCI_DMACTRL_APDE1 BIT(7)
-#define PCI_DMACTRL_PADCEN BIT(8)
-#define PCI_DMACTRL_PADC0 BIT(12)
-#define PCI_DMACTRL_PADE0 BIT(13)
-#define PCI_DMACTRL_PADC1 BIT(14)
-#define PCI_DMACTRL_PADE1 BIT(15)
-
-#endif
#define MXC_CSPICTRL_CHAN 18
/* Bit position inside CON register to be associated with SS */
-#define MXC_CSPICON_POL 4
-#define MXC_CSPICON_PHA 0
-#define MXC_CSPICON_SSPOL 12
+#define MXC_CSPICON_PHA 0 /* SCLK phase control */
+#define MXC_CSPICON_POL 4 /* SCLK polarity */
+#define MXC_CSPICON_SSPOL 12 /* SS polarity */
+#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
#define MXC_SPI_BASE_ADDRESSES \
CSPI1_BASE_ADDR, \
CSPI2_BASE_ADDR, \
#define MXC_CSPICTRL_CHAN 18
/* Bit position inside CON register to be associated with SS */
-#define MXC_CSPICON_POL 4
-#define MXC_CSPICON_PHA 0
-#define MXC_CSPICON_SSPOL 12
-#ifdef CONFIG_MX6SL
+#define MXC_CSPICON_PHA 0 /* SCLK phase control */
+#define MXC_CSPICON_POL 4 /* SCLK polarity */
+#define MXC_CSPICON_SSPOL 12 /* SS polarity */
+#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
+#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL)
#define MXC_SPI_BASE_ADDRESSES \
ECSPI1_BASE_ADDR, \
ECSPI2_BASE_ADDR, \
#define TI_SATA_IDLE_SMART_WAKE (0x3 << 2)
#define TI_SATA_IDLE_SMART (0x2 << 2)
-#ifdef CONFIG_SCSI_AHCI_PLAT
-int omap_sata_init(void);
-#else
-static inline int omap_sata_init(void)
-{
- return 0;
-}
-#endif /* CONFIG_SCSI_AHCI_PLAT */
-
#endif /* _TI_SATA_H */
#define BOOT_DEVICE_MMC1 5
#define BOOT_DEVICE_MMC2 6
#define BOOT_DEVICE_MMC2_2 7
+#define BOOT_DEVICE_SATA 9
#define BOOT_DEVICE_SPI 10
#define BOOT_DEVICE_UART 0x43
#include <asm/io.h>
/* CPU detection macros */
extern unsigned int s5p_cpu_id;
+extern unsigned int s5p_cpu_rev;
+
+static inline int s5p_get_cpu_rev(void)
+{
+ return s5p_cpu_rev;
+}
static inline void s5p_set_cpu_id(void)
{
s5p_cpu_id = readl(S5PC100_PRO_ID);
+ s5p_cpu_rev = s5p_cpu_id & 0x000000FF;
s5p_cpu_id = 0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12);
}
/* GPIO pins per bank */
#define GPIO_PER_BANK 8
-static inline unsigned int s5p_gpio_base(int nr)
-{
- return S5PC110_GPIO_BASE;
-}
+#define S5P_GPIO_PART_SHIFT (24)
+#define S5P_GPIO_PART_MASK (0xff)
+#define S5P_GPIO_BANK_SHIFT (8)
+#define S5P_GPIO_BANK_MASK (0xffff)
+#define S5P_GPIO_PIN_MASK (0xff)
+
+#define S5P_GPIO_SET_PART(x) \
+ (((x) & S5P_GPIO_PART_MASK) << S5P_GPIO_PART_SHIFT)
+
+#define S5P_GPIO_GET_PART(x) \
+ (((x) >> S5P_GPIO_PART_SHIFT) & S5P_GPIO_PART_MASK)
+
+#define S5P_GPIO_SET_PIN(x) \
+ ((x) & S5P_GPIO_PIN_MASK)
-static inline unsigned int s5p_gpio_part_max(int nr)
+#define S5PC100_SET_BANK(bank) \
+ (((unsigned)&(((struct s5pc100_gpio *) \
+ S5PC100_GPIO_BASE)->bank) - S5PC100_GPIO_BASE) \
+ & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
+
+#define S5PC110_SET_BANK(bank) \
+ ((((unsigned)&(((struct s5pc110_gpio *) \
+ S5PC110_GPIO_BASE)->bank) - S5PC110_GPIO_BASE) \
+ & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
+
+#define s5pc100_gpio_get(bank, pin) \
+ (S5P_GPIO_SET_PART(0) | \
+ S5PC100_SET_BANK(bank) | \
+ S5P_GPIO_SET_PIN(pin))
+
+#define s5pc110_gpio_get(bank, pin) \
+ (S5P_GPIO_SET_PART(0) | \
+ S5PC110_SET_BANK(bank) | \
+ S5P_GPIO_SET_PIN(pin))
+
+static inline unsigned int s5p_gpio_base(int nr)
{
- return 0;
+ return samsung_get_base_gpio();
}
-
-#define s5pc110_gpio_get_nr(bank, pin) \
- ((((((unsigned int)&(((struct s5pc110_gpio *)S5PC110_GPIO_BASE)->bank))\
- - S5PC110_GPIO_BASE) / sizeof(struct s5p_gpio_bank)) \
- * GPIO_PER_BANK) + pin)
#endif
/* Pin configurations */
#define CONFIG_SYS_NAND_ALE (1 << 17)
#if defined(CONFIG_SPEAR600)
-#define CONFIG_SYS_I2C_BASE 0xD0200000
#define CONFIG_SYS_FSMC_BASE 0xD1800000
#define CONFIG_FSMC_NAND_BASE 0xD2000000
#define CONFIG_SPEAR_MPMCREGS 100
#elif defined(CONFIG_SPEAR300)
-#define CONFIG_SYS_I2C_BASE 0xD0180000
#define CONFIG_SYS_FSMC_BASE 0x94000000
#elif defined(CONFIG_SPEAR310)
-#define CONFIG_SYS_I2C_BASE 0xD0180000
#define CONFIG_SYS_FSMC_BASE 0x44000000
#undef CONFIG_SYS_NAND_CLE
#define CONFIG_SYS_MACB3_BASE 0xB1800000
#elif defined(CONFIG_SPEAR320)
-#define CONFIG_SYS_I2C_BASE 0xD0180000
#define CONFIG_SYS_FSMC_BASE 0x4C000000
#define CONFIG_SPEAR_EMIBASE 0x40000000
/*
- * (C) Copyright 2010,2011
+ * (C) Copyright 2010-2014
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
/* PLL registers - there are several PLLs in the clock controller */
struct clk_pll {
uint pll_base; /* the control register */
- uint pll_out[2]; /* output control */
+ /* pll_out[0] is output A control, pll_out[1] is output B control */
+ uint pll_out[2];
uint pll_misc; /* other misc things */
};
uint pll_misc; /* other misc things */
};
+struct clk_pllm {
+ uint pllm_base; /* the control register */
+ uint pllm_out; /* output control */
+ uint pllm_misc1; /* misc1 */
+ uint pllm_misc2; /* misc2 */
+};
+
/* RST_DEV_(L,H,U,V,W)_(SET,CLR) and CLK_ENB_(L,H,U,V,W)_(SET,CLR) */
struct clk_set_clr {
uint set;
TEGRA_CLK_REGS = 3, /* Number of clock enable regs L/H/U */
TEGRA_CLK_SOURCES = 64, /* Number of ppl clock sources L/H/U */
TEGRA_CLK_REGS_VW = 2, /* Number of clock enable regs V/W */
- TEGRA_CLK_SOURCES_VW = 32, /* Number of ppl clock sources V/W*/
+ TEGRA_CLK_SOURCES_VW = 32, /* Number of ppl clock sources V/W */
+ TEGRA_CLK_SOURCES_X = 32, /* Number of ppl clock sources X */
};
/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
uint crc_rst_dev[TEGRA_CLK_REGS]; /* _RST_DEVICES_L/H/U_0 */
uint crc_clk_out_enb[TEGRA_CLK_REGS]; /* _CLK_OUT_ENB_L/H/U_0 */
uint crc_reserved0; /* reserved_0, 0x1C */
- uint crc_cclk_brst_pol; /* _CCLK_BURST_POLICY_0,0x20 */
+ uint crc_cclk_brst_pol; /* _CCLK_BURST_POLICY_0, 0x20 */
uint crc_super_cclk_div; /* _SUPER_CCLK_DIVIDER_0,0x24 */
uint crc_sclk_brst_pol; /* _SCLK_BURST_POLICY_0, 0x28 */
uint crc_super_sclk_div; /* _SUPER_SCLK_DIVIDER_0,0x2C */
uint crc_clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0... 0x100-1fc */
- uint crc_reserved20[64]; /* _reserved_20, 0x200-2fc */
+ uint crc_reserved20[32]; /* _reserved_20, 0x200-27c */
+
+ uint crc_clk_out_enb_x; /* _CLK_OUT_ENB_X_0, 0x280 */
+ uint crc_clk_enb_x_set; /* _CLK_ENB_X_SET_0, 0x284 */
+ uint crc_clk_enb_x_clr; /* _CLK_ENB_X_CLR_0, 0x288 */
+
+ uint crc_rst_devices_x; /* _RST_DEVICES_X_0, 0x28c */
+ uint crc_rst_dev_x_set; /* _RST_DEV_X_SET_0, 0x290 */
+ uint crc_rst_dev_x_clr; /* _RST_DEV_X_CLR_0, 0x294 */
+
+ uint crc_reserved21[23]; /* _reserved_21, 0x298-2f0 */
+
+ uint crc_dfll_base; /* _DFLL_BASE_0, 0x2f4 */
+
+ uint crc_reserved22[2]; /* _reserved_22, 0x2f8-2fc */
/* _RST_DEV_L/H/U_SET_0 0x300 ~ 0x314 */
struct clk_set_clr crc_rst_dev_ex[TEGRA_CLK_REGS];
uint crc_clk_cpug_cmplx; /* _CLK_CPUG_CMPLX_0, 0x378 */
uint crc_clk_cpulp_cmplx; /* _CLK_CPULP_CMPLX_0, 0x37C */
uint crc_cpu_softrst_ctrl; /* _CPU_SOFTRST_CTRL_0, 0x380 */
- uint crc_cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTR1L_0, 0x384 */
+ uint crc_cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTRL1_0, 0x384 */
uint crc_cpu_softrst_ctrl2; /* _CPU_SOFTRST_CTRL2_0, 0x388 */
uint crc_reserved33[9]; /* _reserved_33, 0x38c-3ac */
- uint crc_clk_src_vw[TEGRA_CLK_SOURCES_VW]; /* _G3D2_0..., 0x3b0-0x42c */
+ uint crc_clk_src_vw[TEGRA_CLK_SOURCES_VW]; /* 0x3B0-0x42C */
/* _RST_DEV_V/W_SET_0 0x430 ~ 0x43c */
struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW];
/* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */
uint crc_audio_sync_clk_i2s3; /* _AUDIO_SYNC_CLK_I2S3_0, 0x4AC */
uint crc_audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4_0, 0x4B0 */
uint crc_audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF_0, 0x4B4 */
+
+ uint crc_plld2_base; /* _PLLD2_BASE_0, 0x4B8 */
+ uint crc_plld2_misc; /* _PLLD2_MISC_0, 0x4BC */
+ uint crc_utmip_pll_cfg3; /* _UTMIP_PLL_CFG3_0, 0x4C0 */
+ uint crc_pllrefe_base; /* _PLLREFE_BASE_0, 0x4C4 */
+ uint crc_pllrefe_misc; /* _PLLREFE_MISC_0, 0x4C8 */
+ uint crs_reserved_50[7]; /* _reserved_50, 0x4CC-0x4E4 */
+ uint crc_pllc2_base; /* _PLLC2_BASE_0, 0x4E8 */
+ uint crc_pllc2_misc0; /* _PLLC2_MISC_0_0, 0x4EC */
+ uint crc_pllc2_misc1; /* _PLLC2_MISC_1_0, 0x4F0 */
+ uint crc_pllc2_misc2; /* _PLLC2_MISC_2_0, 0x4F4 */
+ uint crc_pllc2_misc3; /* _PLLC2_MISC_3_0, 0x4F8 */
+ uint crc_pllc3_base; /* _PLLC3_BASE_0, 0x4FC */
+ uint crc_pllc3_misc0; /* _PLLC3_MISC_0_0, 0x500 */
+ uint crc_pllc3_misc1; /* _PLLC3_MISC_1_0, 0x504 */
+ uint crc_pllc3_misc2; /* _PLLC3_MISC_2_0, 0x508 */
+ uint crc_pllc3_misc3; /* _PLLC3_MISC_3_0, 0x50C */
+ uint crc_pllx_misc1; /* _PLLX_MISC_1_0, 0x510 */
+ uint crc_pllx_misc2; /* _PLLX_MISC_2_0, 0x514 */
+ uint crc_pllx_misc3; /* _PLLX_MISC_3_0, 0x518 */
+ uint crc_xusbio_pll_cfg0; /* _XUSBIO_PLL_CFG0_0, 0x51C */
+ uint crc_xusbio_pll_cfg1; /* _XUSBIO_PLL_CFG0_1, 0x520 */
+ uint crc_plle_aux1; /* _PLLE_AUX1_0, 0x524 */
+ uint crc_pllp_reshift; /* _PLLP_RESHIFT_0, 0x528 */
+ uint crc_utmipll_hw_pwrdn_cfg0; /* _UTMIPLL_HW_PWRDN_CFG0_0, 0x52C */
+ uint crc_pllu_hw_pwrdn_cfg0; /* _PLLU_HW_PWRDN_CFG0_0, 0x530 */
+ uint crc_xusb_pll_cfg0; /* _XUSB_PLL_CFG0_0, 0x534 */
+ uint crc_reserved51[1]; /* _reserved_51, 0x538 */
+ uint crc_clk_cpu_misc; /* _CLK_CPU_MISC_0, 0x53C */
+ uint crc_clk_cpug_misc; /* _CLK_CPUG_MISC_0, 0x540 */
+ uint crc_clk_cpulp_misc; /* _CLK_CPULP_MISC_0, 0x544 */
+ uint crc_pllx_hw_ctrl_cfg; /* _PLLX_HW_CTRL_CFG_0, 0x548 */
+ uint crc_pllx_sw_ramp_cfg; /* _PLLX_SW_RAMP_CFG_0, 0x54C */
+ uint crc_pllx_hw_ctrl_status; /* _PLLX_HW_CTRL_STATUS_0, 0x550 */
+ uint crc_reserved52[1]; /* _reserved_52, 0x554 */
+ uint crc_super_gr3d_clk_div; /* _SUPER_GR3D_CLK_DIVIDER_0, 0x558 */
+ uint crc_spare_reg0; /* _SPARE_REG0_0, 0x55C */
+
+ /* Tegra124 - skip to 0x600 here for new CLK_SOURCE_ regs */
+ uint crc_reserved60[40]; /* _reserved_60, 0x560 - 0x5FC */
+ uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x678 */
};
/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */
#define PLL_BASE_OVRRIDE_MASK (1U << 28)
+#define PLL_LOCK_SHIFT 27
+#define PLL_LOCK_MASK (1U << PLL_LOCK_SHIFT)
+
#define PLL_DIVP_SHIFT 20
#define PLL_DIVP_MASK (7U << PLL_DIVP_SHIFT)
IN_408_OUT_9_6_DIVISOR = 83,
};
+#define PLLP_OUT1_RSTN_DIS (1 << 0)
+#define PLLP_OUT1_RSTN_EN (0 << 0)
+#define PLLP_OUT1_CLKEN (1 << 1)
+#define PLLP_OUT2_RSTN_DIS (1 << 16)
+#define PLLP_OUT2_RSTN_EN (0 << 16)
+#define PLLP_OUT2_CLKEN (1 << 17)
+
+#define PLLP_OUT3_RSTN_DIS (1 << 0)
+#define PLLP_OUT3_RSTN_EN (0 << 0)
+#define PLLP_OUT3_CLKEN (1 << 1)
+#define PLLP_OUT4_RSTN_DIS (1 << 16)
+#define PLLP_OUT4_RSTN_EN (0 << 16)
+#define PLLP_OUT4_CLKEN (1 << 17)
+
/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 */
#define PLLU_POWERDOWN (1 << 16)
#define PLL_ENABLE_POWERDOWN (1 << 14)
#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN (1 << 2)
#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN (1 << 0)
-/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
-#define OSC_XOBP_SHIFT 1
-#define OSC_XOBP_MASK (1U << OSC_XOBP_SHIFT)
+/* CLK_RST_CONTROLLER_OSC_CTRL_0 0x50 */
+#define OSC_XOE_SHIFT 0
+#define OSC_XOE_MASK (1 << OSC_XOE_SHIFT)
+#define OSC_XOE_ENABLE (1 << OSC_XOE_SHIFT)
+#define OSC_XOBP_SHIFT 1
+#define OSC_XOBP_MASK (1U << OSC_XOBP_SHIFT)
+#define OSC_XOFS_SHIFT 4
+#define OSC_XOFS_MASK (0x3F << OSC_XOFS_SHIFT)
+#define OSC_DRIVE_STRENGTH 7
/*
* CLK_RST_CONTROLLER_CLK_SOURCE_x_OUT_0 - the mask here is normally 8 bits
#define OUT_CLK_DIVISOR_SHIFT 0
#define OUT_CLK_DIVISOR_MASK (0xffff << OUT_CLK_DIVISOR_SHIFT)
-#define OUT_CLK_SOURCE_SHIFT 30
-#define OUT_CLK_SOURCE_MASK (3U << OUT_CLK_SOURCE_SHIFT)
+#define OUT_CLK_SOURCE_31_30_SHIFT 30
+#define OUT_CLK_SOURCE_31_30_MASK (3U << OUT_CLK_SOURCE_31_30_SHIFT)
+
+#define OUT_CLK_SOURCE_31_29_SHIFT 29
+#define OUT_CLK_SOURCE_31_29_MASK (7U << OUT_CLK_SOURCE_31_29_SHIFT)
-#define OUT_CLK_SOURCE4_SHIFT 28
-#define OUT_CLK_SOURCE4_MASK (15U << OUT_CLK_SOURCE4_SHIFT)
+/* Note: See comment for MASK_BITS_31_28 in arch-tegra/clock.h */
+#define OUT_CLK_SOURCE_31_28_SHIFT 28
+#define OUT_CLK_SOURCE_31_28_MASK (15U << OUT_CLK_SOURCE_31_28_SHIFT)
/* CLK_RST_CONTROLLER_SCLK_BURST_POLICY */
#define SCLK_SYS_STATE_SHIFT 28U
#define SUPER_SCLK_DIVISOR_SHIFT 0
#define SUPER_SCLK_DIVISOR_MASK (0xff << SUPER_SCLK_DIVISOR_SHIFT)
-/* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE */
+/* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30 */
#define CLK_SYS_RATE_HCLK_DISABLE_SHIFT 7
#define CLK_SYS_RATE_HCLK_DISABLE_MASK (1 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT)
#define CLK_SYS_RATE_AHB_RATE_SHIFT 4
#define CLK_SYS_RATE_APB_RATE_SHIFT 0
#define CLK_SYS_RATE_APB_RATE_MASK (3 << CLK_SYS_RATE_AHB_RATE_SHIFT)
-/* CLK_RST_CONTROLLER_RST_CPUxx_CMPLX_CLR */
-#define CLR_CPURESET0 (1 << 0)
-#define CLR_CPURESET1 (1 << 1)
-#define CLR_CPURESET2 (1 << 2)
-#define CLR_CPURESET3 (1 << 3)
-#define CLR_DBGRESET0 (1 << 12)
-#define CLR_DBGRESET1 (1 << 13)
-#define CLR_DBGRESET2 (1 << 14)
-#define CLR_DBGRESET3 (1 << 15)
-#define CLR_CORERESET0 (1 << 16)
-#define CLR_CORERESET1 (1 << 17)
-#define CLR_CORERESET2 (1 << 18)
-#define CLR_CORERESET3 (1 << 19)
-#define CLR_CXRESET0 (1 << 20)
-#define CLR_CXRESET1 (1 << 21)
-#define CLR_CXRESET2 (1 << 22)
-#define CLR_CXRESET3 (1 << 23)
-#define CLR_NONCPURESET (1 << 29)
+/* CLK_RST_CONTROLLER_RST_CPUxx_CMPLX_CLR 0x344 */
+#define CLR_CPURESET0 (1 << 0)
+#define CLR_CPURESET1 (1 << 1)
+#define CLR_CPURESET2 (1 << 2)
+#define CLR_CPURESET3 (1 << 3)
+#define CLR_DBGRESET0 (1 << 12)
+#define CLR_DBGRESET1 (1 << 13)
+#define CLR_DBGRESET2 (1 << 14)
+#define CLR_DBGRESET3 (1 << 15)
+#define CLR_CORERESET0 (1 << 16)
+#define CLR_CORERESET1 (1 << 17)
+#define CLR_CORERESET2 (1 << 18)
+#define CLR_CORERESET3 (1 << 19)
+#define CLR_CXRESET0 (1 << 20)
+#define CLR_CXRESET1 (1 << 21)
+#define CLR_CXRESET2 (1 << 22)
+#define CLR_CXRESET3 (1 << 23)
+#define CLR_L2RESET (1 << 24)
+#define CLR_NONCPURESET (1 << 29)
+#define CLR_PRESETDBG (1 << 30)
+
+/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c */
+#define CLR_CPU0_CLK_STP (1 << 8)
+#define CLR_CPU1_CLK_STP (1 << 9)
+#define CLR_CPU2_CLK_STP (1 << 10)
+#define CLR_CPU3_CLK_STP (1 << 11)
+
+/* CRC_CLK_SOURCE_MSELECT_0 0x3b4 */
+#define MSELECT_CLK_SRC_PLLP_OUT0 (0 << 29)
+
+/* CRC_CLK_ENB_V_SET_0 0x440 */
+#define SET_CLK_ENB_CPUG_ENABLE (1 << 0)
+#define SET_CLK_ENB_CPULP_ENABLE (1 << 1)
+#define SET_CLK_ENB_MSELECT_ENABLE (1 << 3)
+
+/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 0x484 */
+#define PLL_ACTIVE_POWERDOWN (1 << 12)
+#define PLL_ENABLE_POWERDOWN (1 << 14)
+#define PLLU_POWERDOWN (1 << 16)
+
+/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 0x488 */
+#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN (1 << 0)
+#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN (1 << 2)
+#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN (1 << 4)
+
+/* CLK_RST_CONTROLLER_PLLX_MISC_3 */
+#define PLLX_IDDQ_SHIFT 3
+#define PLLX_IDDQ_MASK (1U << PLLX_IDDQ_SHIFT)
#endif /* _TEGRA_CLK_RST_H_ */
CLOCK_OSC_FREQ_COUNT,
};
+/*
+ * Note that no Tegra clock register actually uses all of bits 31:28 as
+ * the mux field. Rather, bits 30:28, 29:28, or 28 are used. However, in
+ * those cases, nothing is stored in the bits about the mux field, so it's
+ * safe to pretend that the mux field extends all the way to the end of the
+ * register. As such, the U-Boot clock driver is currently a bit lazy, and
+ * doesn't distinguish between 31:28, 30:28, 29:28 and 28; it just lumps
+ * them all together and pretends they're all 31:28.
+ */
+enum {
+ MASK_BITS_31_30,
+ MASK_BITS_31_29,
+ MASK_BITS_31_28,
+};
+
#include <asm/arch/clock-tables.h>
/* PLL stabilization delay in usec */
#define CLOCK_PLL_STABLE_DELAY_US 300
/* SoC-specific TSC init */
void arch_timer_init(void);
+void tegra30_set_up_pllp(void);
+
#endif /* _TEGRA_CLOCK_H_ */
#define CHIPID_TEGRA20 0x20
#define CHIPID_TEGRA30 0x30
#define CHIPID_TEGRA114 0x35
+#define CHIPID_TEGRA124 0x40
#endif /* _TEGRA_GP_PADCTRL_H_ */
/*
- * (C) Copyright 2010,2011
+ * (C) Copyright 2010,2011,2014
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
uint pmc_dpd_sample; /* _DPD_PADS_SAMPLE_0, offset 20 */
uint pmc_dpd_enable; /* _DPD_PADS_ENABLE_0, offset 24 */
uint pmc_pwrgate_timer_off; /* _PWRGATE_TIMER_OFF_0, offset 28 */
+#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30)
uint pmc_pwrgate_timer_on; /* _PWRGATE_TIMER_ON_0, offset 2C */
+#else
+ uint pmc_clamp_status; /* _CLAMP_STATUS_0, offset 2C */
+#endif
uint pmc_pwrgate_toggle; /* _PWRGATE_TOGGLE_0, offset 30 */
uint pmc_remove_clamping; /* _REMOVE_CLAMPING_CMD_0, offset 34 */
uint pmc_pwrgate_status; /* _PWRGATE_STATUS_0, offset 38 */
uint pmc_sys_33v_en; /* _SYS_33V_EN_0, offset 154 */
uint pmc_bo_mirror_access; /* _BOUNDOUT_MIRROR_ACCESS_0, off158 */
uint pmc_gate; /* _GATE_0, offset 15C */
+ /* The following fields are in Tegra124 and later only */
+ uint pmc_wake2_mask; /* _WAKE2_MASK_0, offset 160 */
+ uint pmc_wake2_lvl; /* _WAKE2_LVL_0, offset 164 */
+ uint pmc_wake2_stat; /* _WAKE2_STATUS_0, offset 168 */
+ uint pmc_sw_wake2_stat; /* _SW_WAKE2_STATUS_0, offset 16C */
+ uint pmc_auto_wake2_lvl_mask; /* _AUTO_WAKE2_LVL_MASK_0, offset 170 */
+ uint pmc_pg_mask2; /* _PG_MASK_2_0, offset 174 */
+ uint pmc_pg_mask_ce1; /* _PG_MASK_CE1_0, offset 178 */
+ uint pmc_pg_mask_ce2; /* _PG_MASK_CE2_0, offset 17C */
+ uint pmc_pg_mask_ce3; /* _PG_MASK_CE3_0, offset 180 */
+ uint pmc_pwrgate_timer_ce0; /* _PWRGATE_TIMER_CE_0_0, offset 184 */
+ uint pmc_pwrgate_timer_ce1; /* _PWRGATE_TIMER_CE_1_0, offset 188 */
+ uint pmc_pwrgate_timer_ce2; /* _PWRGATE_TIMER_CE_2_0, offset 18C */
+ uint pmc_pwrgate_timer_ce3; /* _PWRGATE_TIMER_CE_3_0, offset 190 */
+ uint pmc_pwrgate_timer_ce4; /* _PWRGATE_TIMER_CE_4_0, offset 194 */
+ uint pmc_pwrgate_timer_ce5; /* _PWRGATE_TIMER_CE_5_0, offset 198 */
+ uint pmc_pwrgate_timer_ce6; /* _PWRGATE_TIMER_CE_6_0, offset 19C */
+ uint pmc_pcx_edpd_cntrl; /* _PCX_EDPD_CNTRL_0, offset 1A0 */
+ uint pmc_osc_edpd_over; /* _OSC_EDPD_OVER_0, offset 1A4 */
+ uint pmc_clk_out_cntrl; /* _CLK_OUT_CNTRL_0, offset 1A8 */
+ uint pmc_sata_pwrgate; /* _SATA_PWRGT_0, offset 1AC */
+ uint pmc_sensor_ctrl; /* _SENSOR_CTRL_0, offset 1B0 */
+ uint pmc_reset_status; /* _RTS_STATUS_0, offset 1B4 */
+ uint pmc_io_dpd_req; /* _IO_DPD_REQ_0, offset 1B8 */
+ uint pmc_io_dpd_stat; /* _IO_DPD_STATUS_0, offset 1BC */
+ uint pmc_io_dpd2_req; /* _IO_DPD2_REQ_0, offset 1C0 */
+ uint pmc_io_dpd2_stat; /* _IO_DPD2_STATUS_0, offset 1C4 */
+ uint pmc_sel_dpd_tim; /* _SEL_DPD_TIM_0, offset 1C8 */
+ uint pmc_vddp_sel; /* _VDDP_SEL_0, offset 1CC */
+
+ uint pmc_ddr_cfg; /* _DDR_CFG_0, offset 1D0 */
+ uint pmc_e_no_vttgen; /* _E_NO_VTTGEN_0, offset 1D4 */
+ uint pmc_reserved0; /* _RESERVED, offset 1D8 */
+ uint pmc_pllm_wb0_ovrride_frq; /* _PLLM_WB0_OVERRIDE_FREQ_0, off 1DC */
+ uint pmc_test_pwrgate; /* _TEST_PWRGATE_0, offset 1E0 */
+ uint pmc_pwrgate_timer_mult; /* _PWRGATE_TIMER_MULT_0, offset 1E4 */
+ uint pmc_dsi_sel_dpd; /* _DSI_SEL_DPD_0, offset 1E8 */
+ uint pmc_utmip_uhsic_triggers; /* _UTMIP_UHSIC_TRIGGERS_0, off 1EC */
+ uint pmc_utmip_uhsic_saved_st; /* _UTMIP_UHSIC_SAVED_STATE_0, off1F0 */
+ uint pmc_utmip_pad_cfg; /* _UTMIP_PAD_CFG_0, offset 1F4 */
+ uint pmc_utmip_term_pad_cfg; /* _UTMIP_TERM_PAD_CFG_0, offset 1F8 */
+ uint pmc_utmip_uhsic_sleep_cfg; /* _UTMIP_UHSIC_SLEEP_CFG_0, off 1FC */
+
+ uint pmc_todo_0[9]; /* offset 200-220 */
+ uint pmc_secure_scratch6; /* _SECURE_SCRATCH6_0, offset 224 */
+ uint pmc_secure_scratch7; /* _SECURE_SCRATCH7_0, offset 228 */
+ uint pmc_scratch43; /* _SCRATCH43_0, offset 22C */
+ uint pmc_scratch44; /* _SCRATCH44_0, offset 230 */
+ uint pmc_scratch45;
+ uint pmc_scratch46;
+ uint pmc_scratch47;
+ uint pmc_scratch48;
+ uint pmc_scratch49;
+ uint pmc_scratch50;
+ uint pmc_scratch51;
+ uint pmc_scratch52;
+ uint pmc_scratch53;
+ uint pmc_scratch54;
+ uint pmc_scratch55; /* _SCRATCH55_0, offset 25C */
+ uint pmc_scratch0_eco; /* _SCRATCH0_ECO_0, offset 260 */
+ uint pmc_por_dpd_ctrl; /* _POR_DPD_CTRL_0, offset 264 */
+ uint pmc_scratch2_eco; /* _SCRATCH2_ECO_0, offset 268 */
+ uint pmc_todo_1[17]; /* TODO: 26C ~ 2AC */
+ uint pmc_pllm_wb0_override2; /* _PLLM_WB0_OVERRIDE2, offset 2B0 */
+ uint pmc_tsc_mult; /* _TSC_MULT_0, offset 2B4 */
+ uint pmc_cpu_vsense_override; /* _CPU_VSENSE_OVERRIDE_0, offset 2B8 */
+ uint pmc_glb_amap_cfg; /* _GLB_AMAP_CFG_0, offset 2BC */
+ uint pmc_sticky_bits; /* _STICKY_BITS_0, offset 2C0 */
+ uint pmc_sec_disable2; /* _SEC_DISALBE2, offset 2C4 */
+ uint pmc_weak_bias; /* _WEAK_BIAS_0, offset 2C8 */
+ uint pmc_todo_3[13]; /* TODO: 2CC ~ 2FC */
+ uint pmc_secure_scratch8; /* _SECURE_SCRATCH8_0, offset 300 */
+ uint pmc_secure_scratch9;
+ uint pmc_secure_scratch10;
+ uint pmc_secure_scratch11;
+ uint pmc_secure_scratch12;
+ uint pmc_secure_scratch13;
+ uint pmc_secure_scratch14;
+ uint pmc_secure_scratch15;
+ uint pmc_secure_scratch16;
+ uint pmc_secure_scratch17;
+ uint pmc_secure_scratch18;
+ uint pmc_secure_scratch19;
+ uint pmc_secure_scratch20;
+ uint pmc_secure_scratch21;
+ uint pmc_secure_scratch22;
+ uint pmc_secure_scratch23;
+ uint pmc_secure_scratch24; /* _SECURE_SCRATCH24_0, offset 340 */
+ uint pmc_secure_scratch25;
+ uint pmc_secure_scratch26;
+ uint pmc_secure_scratch27;
+ uint pmc_secure_scratch28;
+ uint pmc_secure_scratch29;
+ uint pmc_secure_scratch30;
+ uint pmc_secure_scratch31;
+ uint pmc_secure_scratch32;
+ uint pmc_secure_scratch33;
+ uint pmc_secure_scratch34;
+ uint pmc_secure_scratch35; /* _SECURE_SCRATCH35_0, offset 36C */
+
+ uint pmc_reserved1[52]; /* RESERVED: 370 ~ 43C */
+ uint pmc_cntrl2; /* _CNTRL2_0, offset 440 */
+ uint pmc_reserved2[6]; /* RESERVED: 444 ~ 458 */
+ uint pmc_io_dpd3_req; /* _IO_DPD3_REQ_0, offset 45c */
+ uint pmc_io_dpd3_stat; /* _IO_DPD3_STATUS_0, offset 460 */
+ uint pmc_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 464 */
+ uint pmc_reserved3[102]; /* RESERVED: 468 ~ 5FC */
+
+ uint pmc_scratch56; /* _SCRATCH56_0, offset 600 */
+ uint pmc_scratch57;
+ uint pmc_scratch58;
+ uint pmc_scratch59;
+ uint pmc_scratch60;
+ uint pmc_scratch61;
+ uint pmc_scratch62;
+ uint pmc_scratch63;
+ uint pmc_scratch64;
+ uint pmc_scratch65;
+ uint pmc_scratch66;
+ uint pmc_scratch67;
+ uint pmc_scratch68;
+ uint pmc_scratch69;
+ uint pmc_scratch70;
+ uint pmc_scratch71;
+ uint pmc_scratch72;
+ uint pmc_scratch73;
+ uint pmc_scratch74;
+ uint pmc_scratch75;
+ uint pmc_scratch76;
+ uint pmc_scratch77;
+ uint pmc_scratch78;
+ uint pmc_scratch79;
+ uint pmc_scratch80;
+ uint pmc_scratch81;
+ uint pmc_scratch82;
+ uint pmc_scratch83;
+ uint pmc_scratch84;
+ uint pmc_scratch85;
+ uint pmc_scratch86;
+ uint pmc_scratch87;
+ uint pmc_scratch88;
+ uint pmc_scratch89;
+ uint pmc_scratch90;
+ uint pmc_scratch91;
+ uint pmc_scratch92;
+ uint pmc_scratch93;
+ uint pmc_scratch94;
+ uint pmc_scratch95;
+ uint pmc_scratch96;
+ uint pmc_scratch97;
+ uint pmc_scratch98;
+ uint pmc_scratch99;
+ uint pmc_scratch100;
+ uint pmc_scratch101;
+ uint pmc_scratch102;
+ uint pmc_scratch103;
+ uint pmc_scratch104;
+ uint pmc_scratch105;
+ uint pmc_scratch106;
+ uint pmc_scratch107;
+ uint pmc_scratch108;
+ uint pmc_scratch109;
+ uint pmc_scratch110;
+ uint pmc_scratch111;
+ uint pmc_scratch112;
+ uint pmc_scratch113;
+ uint pmc_scratch114;
+ uint pmc_scratch115;
+ uint pmc_scratch116;
+ uint pmc_scratch117;
+ uint pmc_scratch118;
+ uint pmc_scratch119;
+ uint pmc_scratch1_eco; /* offset 700 */
};
#define CPU_PWRED 1
#define CPUPWRREQ_OE (1 << 16)
#define CPUPWRREQ_POL (1 << 15)
-#define CRAILID (0)
-#define CE0ID (14)
-#define C0NCID (15)
-#define CRAIL (1 << CRAILID)
-#define CE0 (1 << CE0ID)
-#define C0NC (1 << C0NCID)
+#define CRAIL 0
+#define CE0 14
+#define C0NC 15
+
+#define PMC_XOFS_SHIFT 1
+#define PMC_XOFS_MASK (0x3F << PMC_XOFS_SHIFT)
+
+#define TIMER_MULT_SHIFT 0
+#define TIMER_MULT_MASK (3 << TIMER_MULT_SHIFT)
+#define TIMER_MULT_CPU_SHIFT 2
+#define TIMER_MULT_CPU_MASK (3 << TIMER_MULT_CPU_SHIFT)
+#define MULT_1 0
+#define MULT_2 1
+#define MULT_4 2
+#define MULT_8 3
+
+#define AMAP_WRITE_SHIFT 20
+#define AMAP_WRITE_ON (1 << AMAP_WRITE_SHIFT)
+
+/* SEC_DISABLE_0, 0x04 */
+#define SEC_DISABLE_WRITE0_ON (1 << 4)
+#define SEC_DISABLE_READ0_ON (1 << 5)
+#define SEC_DISABLE_WRITE1_ON (1 << 6)
+#define SEC_DISABLE_READ1_ON (1 << 7)
+#define SEC_DISABLE_WRITE2_ON (1 << 8)
+#define SEC_DISABLE_READ2_ON (1 << 9)
+#define SEC_DISABLE_WRITE3_ON (1 << 10)
+#define SEC_DISABLE_READ3_ON (1 << 11)
+#define SEC_DISABLE_AMAP_WRITE_ON (1 << 20)
+
+/* APBDEV_PMC_PWRGATE_TOGGLE_0 0x30 */
+#define PWRGATE_TOGGLE_PARTID_CRAIL 0
+#define PWRGATE_TOGGLE_PARTID_TD 1
+#define PWRGATE_TOGGLE_PARTID_VE 2
+#define PWRGATE_TOGGLE_PARTID_PCX 3
+#define PWRGATE_TOGGLE_PARTID_VDE 4
+#define PWRGATE_TOGGLE_PARTID_L2C 5
+#define PWRGATE_TOGGLE_PARTID_MPE 6
+#define PWRGATE_TOGGLE_PARTID_HEG 7
+#define PWRGATE_TOGGLE_PARTID_SAX 8
+#define PWRGATE_TOGGLE_PARTID_CE1 9
+#define PWRGATE_TOGGLE_PARTID_CE2 10
+#define PWRGATE_TOGGLE_PARTID_CE3 11
+#define PWRGATE_TOGGLE_PARTID_CELP 12
+#define PWRGATE_TOGGLE_PARTID_CE0 14
+#define PWRGATE_TOGGLE_PARTID_C0NC 15
+#define PWRGATE_TOGGLE_PARTID_C1NC 16
+#define PWRGATE_TOGGLE_PARTID_SOR 17
+#define PWRGATE_TOGGLE_PARTID_DIS 18
+#define PWRGATE_TOGGLE_PARTID_DISB 19
+#define PWRGATE_TOGGLE_PARTID_XUSBA 20
+#define PWRGATE_TOGGLE_PARTID_XUSBB 21
+#define PWRGATE_TOGGLE_PARTID_XUSBC 22
+#define PWRGATE_TOGGLE_PARTID_VIC 23
+#define PWRGATE_TOGGLE_PARTID_IRAM 24
+#define PWRGATE_TOGGLE_START (1 << 8)
+
+/* APBDEV_PMC_PWRGATE_STATUS_0 0x38 */
+#define PWRGATE_STATUS_CRAIL_ENABLE (1 << 0)
+#define PWRGATE_STATUS_TD_ENABLE (1 << 1)
+#define PWRGATE_STATUS_VE_ENABLE (1 << 2)
+#define PWRGATE_STATUS_PCX_ENABLE (1 << 3)
+#define PWRGATE_STATUS_VDE_ENABLE (1 << 4)
+#define PWRGATE_STATUS_L2C_ENABLE (1 << 5)
+#define PWRGATE_STATUS_MPE_ENABLE (1 << 6)
+#define PWRGATE_STATUS_HEG_ENABLE (1 << 7)
+#define PWRGATE_STATUS_SAX_ENABLE (1 << 8)
+#define PWRGATE_STATUS_CE1_ENABLE (1 << 9)
+#define PWRGATE_STATUS_CE2_ENABLE (1 << 10)
+#define PWRGATE_STATUS_CE3_ENABLE (1 << 11)
+#define PWRGATE_STATUS_CELP_ENABLE (1 << 12)
+#define PWRGATE_STATUS_CE0_ENABLE (1 << 14)
+#define PWRGATE_STATUS_C0NC_ENABLE (1 << 15)
+#define PWRGATE_STATUS_C1NC_ENABLE (1 << 16)
+#define PWRGATE_STATUS_SOR_ENABLE (1 << 17)
+#define PWRGATE_STATUS_DIS_ENABLE (1 << 18)
+#define PWRGATE_STATUS_DISB_ENABLE (1 << 19)
+#define PWRGATE_STATUS_XUSBA_ENABLE (1 << 20)
+#define PWRGATE_STATUS_XUSBB_ENABLE (1 << 21)
+#define PWRGATE_STATUS_XUSBC_ENABLE (1 << 22)
+#define PWRGATE_STATUS_VIC_ENABLE (1 << 23)
+#define PWRGATE_STATUS_IRAM_ENABLE (1 << 24)
+
+/* APBDEV_PMC_CNTRL2_0 0x440 */
+#define HOLD_CKE_LOW_EN (1 << 12)
#endif /* PMC_H */
SKU_ID_TM30MQS_P_A3 = 0xb1,
SKU_ID_T114_ENG = 0x00, /* Dalmore value, unfused */
SKU_ID_T114_1 = 0x01,
+ SKU_ID_T124_ENG = 0x00, /* Venice2 value, unfused */
};
/*
TEGRA_SOC_T25,
TEGRA_SOC_T30,
TEGRA_SOC_T114,
+ TEGRA_SOC_T124,
TEGRA_SOC_CNT,
TEGRA_SOC_UNKNOWN = -1,
--- /dev/null
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA124_AHB_H_
+#define _TEGRA124_AHB_H_
+
+struct ahb_ctlr {
+ u32 reserved0; /* 00h */
+ u32 arbitration_disable; /* _ARBITRATION_DISABLE_0, 04h */
+ u32 arbitration_priority_ctrl; /* _ARBITRATION_PRIORITY_CTRL_0,08h */
+ u32 arbitration_usr_protect; /* _ARBITRATION_USR_PROTECT_0, 0ch */
+ u32 gizmo_ahb_mem; /* _GIZMO_AHB_MEM_0, 10h */
+ u32 gizmo_apb_dma; /* _GIZMO_APB_DMA_0, 14h */
+ u32 reserved6[2]; /* 18h, 1ch */
+ u32 gizmo_usb; /* _GIZMO_USB_0, 20h */
+ u32 gizmo_ahb_xbar_bridge; /* _GIZMO_AHB_XBAR_BRIDGE_0, 24h */
+ u32 gizmo_cpu_ahb_bridge; /* _GIZMO_CPU_AHB_BRIDGE_0, 28h */
+ u32 gizmo_cop_ahb_bridge; /* _GIZMO_COP_AHB_BRIDGE_0, 2ch */
+ u32 gizmo_xbar_apb_ctlr; /* _GIZMO_XBAR_APB_CTLR_0, 30h */
+ u32 gizmo_vcp_ahb_bridge; /* _GIZMO_VCP_AHB_BRIDGE_0, 34h */
+ u32 reserved13[2]; /* 38h, 3ch */
+ u32 gizmo_nand; /* _GIZMO_NAND_0, 40h */
+ u32 reserved15; /* 44h */
+ u32 gizmo_sdmmc4; /* _GIZMO_SDMMC4_0, 48h */
+ u32 reserved17; /* 4ch */
+ u32 gizmo_se; /* _GIZMO_SE_0, 50h */
+ u32 gizmo_tzram; /* _GIZMO_TZRAM_0, 54h */
+ u32 reserved20[3]; /* 58h, 5ch, 60h */
+ u32 gizmo_bsev; /* _GIZMO_BSEV_0, 64h */
+ u32 reserved22[3]; /* 68h, 6ch, 70h */
+ u32 gizmo_bsea; /* _GIZMO_BSEA_0, 74h */
+ u32 gizmo_nor; /* _GIZMO_NOR_0, 78h */
+ u32 gizmo_usb2; /* _GIZMO_USB2_0, 7ch */
+ u32 gizmo_usb3; /* _GIZMO_USB3_0, 80h */
+ u32 gizmo_sdmmc1; /* _GIZMO_SDMMC1_0, 84h */
+ u32 gizmo_sdmmc2; /* _GIZMO_SDMMC2_0, 88h */
+ u32 gizmo_sdmmc3; /* _GIZMO_SDMMC3_0, 8ch */
+ u32 reserved30[13]; /* 90h ~ c0h */
+ u32 ahb_wrq_empty; /* _AHB_WRQ_EMPTY_0, c4h */
+ u32 reserved32[5]; /* c8h ~ d8h */
+ u32 ahb_mem_prefetch_cfg_x; /* _AHB_MEM_PREFETCH_CFG_X_0, dch */
+ u32 arbitration_xbar_ctrl; /* _ARBITRATION_XBAR_CTRL_0, e0h */
+ u32 ahb_mem_prefetch_cfg3; /* _AHB_MEM_PREFETCH_CFG3_0, e4h */
+ u32 ahb_mem_prefetch_cfg4; /* _AHB_MEM_PREFETCH_CFG3_0, e8h */
+ u32 avp_ppcs_rd_coh_status; /* _AVP_PPCS_RD_COH_STATUS_0, ech */
+ u32 ahb_mem_prefetch_cfg1; /* _AHB_MEM_PREFETCH_CFG1_0, f0h */
+ u32 ahb_mem_prefetch_cfg2; /* _AHB_MEM_PREFETCH_CFG2_0, f4h */
+ u32 ahbslvmem_status; /* _AHBSLVMEM_STATUS_0, f8h */
+ /* _ARBITRATION_AHB_MEM_WRQUE_MST_ID_0, fch */
+ u32 arbitration_ahb_mem_wrque_mst_id;
+ u32 arbitration_cpu_abort_addr; /* _ARBITRATION_CPU_ABORT_ADDR_0,100h */
+ u32 arbitration_cpu_abort_info; /* _ARBITRATION_CPU_ABORT_INFO_0,104h */
+ u32 arbitration_cop_abort_addr; /* _ARBITRATION_COP_ABORT_ADDR_0,108h */
+ u32 arbitration_cop_abort_info; /* _ARBITRATION_COP_ABORT_INFO_0,10ch */
+ u32 reserved46[4]; /* 110h ~ 11ch */
+ u32 avpc_mccif_fifoctrl; /* _AVPC_MCCIF_FIFOCTRL_0, 120h */
+ u32 timeout_wcoal_avpc; /* _TIMEOUT_WCOAL_AVPC_0, 124h */
+ u32 mpcorelp_mccif_fifoctrl; /* _MPCORELP_MCCIF_FIFOCTRL_0, 128h */
+ u32 mpcore_mccif_fifoctrl; /* _MPCORE_MCCIF_FIFOCTRL_0, 12ch */
+ u32 axicif_fastsync_ctrl; /* AXICIF_FASTSYNC_CTRL_0, 130h */
+ u32 axicif_fastsync_statistics; /* _AXICIF_FASTSYNC_STATISTICS_0,134h */
+ /* _AXICIF_FASTSYNC0_CPUCLK_TO_MCCLK_0, 138h */
+ u32 axicif_fastsync0_cpuclk_to_mcclk;
+ /* _AXICIF_FASTSYNC1_CPUCLK_TO_MCCLK_0, 13ch */
+ u32 axicif_fastsync1_cpuclk_to_mcclk;
+ /* _AXICIF_FASTSYNC2_CPUCLK_TO_MCCLK_0, 140h */
+ u32 axicif_fastsync2_cpuclk_to_mcclk;
+ /* _AXICIF_FASTSYNC0_MCCLK_TO_CPUCLK_0, 144h */
+ u32 axicif_fastsync0_mcclk_to_cpuclk;
+ /* _AXICIF_FASTSYNC1_MCCLK_TO_CPUCLK_0, 148h */
+ u32 axicif_fastsync1_mcclk_to_cpuclk;
+ /* _AXICIF_FASTSYNC2_MCCLK_TO_CPUCLK_0, 14ch */
+ u32 axicif_fastsync2_mcclk_to_cpuclk;
+};
+
+#define PPSB_STOPCLK_ENABLE (1 << 2)
+
+#define GIZ_ENABLE_SPLIT (1 << 0)
+#define GIZ_ENB_FAST_REARB (1 << 2)
+#define GIZ_DONT_SPLIT_AHB_WR (1 << 7)
+
+#define GIZ_USB_IMMEDIATE (1 << 18)
+
+/* AHB_ARBITRATION_XBAR_CTRL_0 0xe0 */
+#define ARBITRATION_XBAR_CTRL_PPSB_ENABLE (1 << 2)
+
+#endif /* _TEGRA124_AHB_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Tegra124 clock PLL tables */
+
+#ifndef _TEGRA124_CLOCK_TABLES_H_
+#define _TEGRA124_CLOCK_TABLES_H_
+
+/* The PLLs supported by the hardware */
+enum clock_id {
+ CLOCK_ID_FIRST,
+ CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
+ CLOCK_ID_MEMORY,
+ CLOCK_ID_PERIPH,
+ CLOCK_ID_AUDIO,
+ CLOCK_ID_USB,
+ CLOCK_ID_DISPLAY,
+
+ /* now the simple ones */
+ CLOCK_ID_FIRST_SIMPLE,
+ CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
+ CLOCK_ID_EPCI,
+ CLOCK_ID_SFROM32KHZ,
+
+ /* These are the base clocks (inputs to the Tegra SoC) */
+ CLOCK_ID_32KHZ,
+ CLOCK_ID_OSC,
+
+ CLOCK_ID_COUNT, /* number of PLLs */
+
+ /*
+ * These are clock IDs that are used in table clock_source[][]
+ * but will not be assigned as a clock source for any peripheral.
+ */
+ CLOCK_ID_DISPLAY2,
+ CLOCK_ID_CGENERAL2,
+ CLOCK_ID_CGENERAL3,
+ CLOCK_ID_MEMORY2,
+ CLOCK_ID_SRC2,
+
+ CLOCK_ID_NONE = -1,
+};
+
+/* The clocks supported by the hardware */
+enum periph_id {
+ PERIPH_ID_FIRST,
+
+ /* Low word: 31:0 (DEVICES_L) */
+ PERIPH_ID_CPU = PERIPH_ID_FIRST,
+ PERIPH_ID_COP,
+ PERIPH_ID_TRIGSYS,
+ PERIPH_ID_ISPB,
+ PERIPH_ID_RESERVED4,
+ PERIPH_ID_TMR,
+ PERIPH_ID_UART1,
+ PERIPH_ID_UART2,
+
+ /* 8 */
+ PERIPH_ID_GPIO,
+ PERIPH_ID_SDMMC2,
+ PERIPH_ID_SPDIF,
+ PERIPH_ID_I2S1,
+ PERIPH_ID_I2C1,
+ PERIPH_ID_RESERVED13,
+ PERIPH_ID_SDMMC1,
+ PERIPH_ID_SDMMC4,
+
+ /* 16 */
+ PERIPH_ID_TCW,
+ PERIPH_ID_PWM,
+ PERIPH_ID_I2S2,
+ PERIPH_ID_RESERVED19,
+ PERIPH_ID_VI,
+ PERIPH_ID_RESERVED21,
+ PERIPH_ID_USBD,
+ PERIPH_ID_ISP,
+
+ /* 24 */
+ PERIPH_ID_RESERVED24,
+ PERIPH_ID_RESERVED25,
+ PERIPH_ID_DISP2,
+ PERIPH_ID_DISP1,
+ PERIPH_ID_HOST1X,
+ PERIPH_ID_VCP,
+ PERIPH_ID_I2S0,
+ PERIPH_ID_CACHE2,
+
+ /* Middle word: 63:32 (DEVICES_H) */
+ PERIPH_ID_MEM,
+ PERIPH_ID_AHBDMA,
+ PERIPH_ID_APBDMA,
+ PERIPH_ID_RESERVED35,
+ PERIPH_ID_RESERVED36,
+ PERIPH_ID_STAT_MON,
+ PERIPH_ID_RESERVED38,
+ PERIPH_ID_FUSE,
+
+ /* 40 */
+ PERIPH_ID_KFUSE,
+ PERIPH_ID_SBC1,
+ PERIPH_ID_SNOR,
+ PERIPH_ID_RESERVED43,
+ PERIPH_ID_SBC2,
+ PERIPH_ID_XIO,
+ PERIPH_ID_SBC3,
+ PERIPH_ID_I2C5,
+
+ /* 48 */
+ PERIPH_ID_DSI,
+ PERIPH_ID_RESERVED49,
+ PERIPH_ID_HSI,
+ PERIPH_ID_HDMI,
+ PERIPH_ID_CSI,
+ PERIPH_ID_RESERVED53,
+ PERIPH_ID_I2C2,
+ PERIPH_ID_UART3,
+
+ /* 56 */
+ PERIPH_ID_MIPI_CAL,
+ PERIPH_ID_EMC,
+ PERIPH_ID_USB2,
+ PERIPH_ID_USB3,
+ PERIPH_ID_RESERVED60,
+ PERIPH_ID_VDE,
+ PERIPH_ID_BSEA,
+ PERIPH_ID_BSEV,
+
+ /* Upper word 95:64 (DEVICES_U) */
+ PERIPH_ID_RESERVED64,
+ PERIPH_ID_UART4,
+ PERIPH_ID_UART5,
+ PERIPH_ID_I2C3,
+ PERIPH_ID_SBC4,
+ PERIPH_ID_SDMMC3,
+ PERIPH_ID_PCIE,
+ PERIPH_ID_OWR,
+
+ /* 72 */
+ PERIPH_ID_AFI,
+ PERIPH_ID_CORESIGHT,
+ PERIPH_ID_PCIEXCLK,
+ PERIPH_ID_AVPUCQ,
+ PERIPH_ID_LA,
+ PERIPH_ID_TRACECLKIN,
+ PERIPH_ID_SOC_THERM,
+ PERIPH_ID_DTV,
+
+ /* 80 */
+ PERIPH_ID_RESERVED80,
+ PERIPH_ID_I2CSLOW,
+ PERIPH_ID_DSIB,
+ PERIPH_ID_TSEC,
+ PERIPH_ID_RESERVED84,
+ PERIPH_ID_RESERVED85,
+ PERIPH_ID_RESERVED86,
+ PERIPH_ID_EMUCIF,
+
+ /* 88 */
+ PERIPH_ID_RESERVED88,
+ PERIPH_ID_XUSB_HOST,
+ PERIPH_ID_RESERVED90,
+ PERIPH_ID_MSENC,
+ PERIPH_ID_RESERVED92,
+ PERIPH_ID_RESERVED93,
+ PERIPH_ID_RESERVED94,
+ PERIPH_ID_XUSB_DEV,
+
+ PERIPH_ID_VW_FIRST,
+ /* V word: 31:0 */
+ PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
+ PERIPH_ID_CPULP,
+ PERIPH_ID_V_RESERVED2,
+ PERIPH_ID_MSELECT,
+ PERIPH_ID_V_RESERVED4,
+ PERIPH_ID_I2S3,
+ PERIPH_ID_I2S4,
+ PERIPH_ID_I2C4,
+
+ /* 104 */
+ PERIPH_ID_SBC5,
+ PERIPH_ID_SBC6,
+ PERIPH_ID_AUDIO,
+ PERIPH_ID_APBIF,
+ PERIPH_ID_DAM0,
+ PERIPH_ID_DAM1,
+ PERIPH_ID_DAM2,
+ PERIPH_ID_HDA2CODEC2X,
+
+ /* 112 */
+ PERIPH_ID_ATOMICS,
+ PERIPH_ID_V_RESERVED17,
+ PERIPH_ID_V_RESERVED18,
+ PERIPH_ID_V_RESERVED19,
+ PERIPH_ID_V_RESERVED20,
+ PERIPH_ID_V_RESERVED21,
+ PERIPH_ID_V_RESERVED22,
+ PERIPH_ID_ACTMON,
+
+ /* 120 */
+ PERIPH_ID_EXTPERIPH1,
+ PERIPH_ID_EXTPERIPH2,
+ PERIPH_ID_EXTPERIPH3,
+ PERIPH_ID_OOB,
+ PERIPH_ID_SATA,
+ PERIPH_ID_HDA,
+ PERIPH_ID_V_RESERVED30,
+ PERIPH_ID_V_RESERVED31,
+
+ /* W word: 31:0 */
+ PERIPH_ID_HDA2HDMICODEC,
+ PERIPH_ID_SATACOLD,
+ PERIPH_ID_W_RESERVED2,
+ PERIPH_ID_W_RESERVED3,
+ PERIPH_ID_W_RESERVED4,
+ PERIPH_ID_W_RESERVED5,
+ PERIPH_ID_W_RESERVED6,
+ PERIPH_ID_W_RESERVED7,
+
+ /* 136 */
+ PERIPH_ID_CEC,
+ PERIPH_ID_W_RESERVED9,
+ PERIPH_ID_W_RESERVED10,
+ PERIPH_ID_W_RESERVED11,
+ PERIPH_ID_W_RESERVED12,
+ PERIPH_ID_W_RESERVED13,
+ PERIPH_ID_XUSB_PADCTL,
+ PERIPH_ID_W_RESERVED15,
+
+ /* 144 */
+ PERIPH_ID_W_RESERVED16,
+ PERIPH_ID_W_RESERVED17,
+ PERIPH_ID_W_RESERVED18,
+ PERIPH_ID_W_RESERVED19,
+ PERIPH_ID_W_RESERVED20,
+ PERIPH_ID_ENTROPY,
+ PERIPH_ID_DDS,
+ PERIPH_ID_W_RESERVED23,
+
+ /* 152 */
+ PERIPH_ID_DP2,
+ PERIPH_ID_AMX0,
+ PERIPH_ID_ADX0,
+ PERIPH_ID_DVFS,
+ PERIPH_ID_XUSB_SS,
+ PERIPH_ID_W_RESERVED29,
+ PERIPH_ID_W_RESERVED30,
+ PERIPH_ID_W_RESERVED31,
+
+ PERIPH_ID_X_FIRST,
+ /* X word: 31:0 */
+ PERIPH_ID_SPARE = PERIPH_ID_X_FIRST,
+ PERIPH_ID_X_RESERVED1,
+ PERIPH_ID_X_RESERVED2,
+ PERIPH_ID_X_RESERVED3,
+ PERIPH_ID_CAM_MCLK,
+ PERIPH_ID_CAM_MCLK2,
+ PERIPH_ID_I2C6,
+ PERIPH_ID_X_RESERVED7,
+
+ /* 168 */
+ PERIPH_ID_X_RESERVED8,
+ PERIPH_ID_X_RESERVED9,
+ PERIPH_ID_X_RESERVED10,
+ PERIPH_ID_VIM2_CLK,
+ PERIPH_ID_X_RESERVED12,
+ PERIPH_ID_X_RESERVED13,
+ PERIPH_ID_EMC_DLL,
+ PERIPH_ID_X_RESERVED15,
+
+ /* 176 */
+ PERIPH_ID_HDMI_AUDIO,
+ PERIPH_ID_CLK72MHZ,
+ PERIPH_ID_VIC,
+ PERIPH_ID_X_RESERVED19,
+ PERIPH_ID_ADX1,
+ PERIPH_ID_DPAUX,
+ PERIPH_ID_SOR0,
+ PERIPH_ID_X_RESERVED23,
+
+ /* 184 */
+ PERIPH_ID_GPU,
+ PERIPH_ID_AMX1,
+ PERIPH_ID_X_RESERVED26,
+ PERIPH_ID_X_RESERVED27,
+ PERIPH_ID_X_RESERVED28,
+ PERIPH_ID_X_RESERVED29,
+ PERIPH_ID_X_RESERVED30,
+ PERIPH_ID_X_RESERVED31,
+
+ PERIPH_ID_COUNT,
+ PERIPH_ID_NONE = -1,
+};
+
+enum pll_out_id {
+ PLL_OUT1,
+ PLL_OUT2,
+ PLL_OUT3,
+ PLL_OUT4
+};
+
+/*
+ * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
+ * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
+ * confusion bewteen PERIPH_ID_... and PERIPHC_...
+ *
+ * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
+ * confusing.
+ */
+enum periphc_internal_id {
+ /* 0x00 */
+ PERIPHC_I2S1,
+ PERIPHC_I2S2,
+ PERIPHC_SPDIF_OUT,
+ PERIPHC_SPDIF_IN,
+ PERIPHC_PWM,
+ PERIPHC_05h,
+ PERIPHC_SBC2,
+ PERIPHC_SBC3,
+
+ /* 0x08 */
+ PERIPHC_08h,
+ PERIPHC_I2C1,
+ PERIPHC_I2C5,
+ PERIPHC_0bh,
+ PERIPHC_0ch,
+ PERIPHC_SBC1,
+ PERIPHC_DISP1,
+ PERIPHC_DISP2,
+
+ /* 0x10 */
+ PERIPHC_10h,
+ PERIPHC_11h,
+ PERIPHC_VI,
+ PERIPHC_13h,
+ PERIPHC_SDMMC1,
+ PERIPHC_SDMMC2,
+ PERIPHC_G3D,
+ PERIPHC_G2D,
+
+ /* 0x18 */
+ PERIPHC_18h,
+ PERIPHC_SDMMC4,
+ PERIPHC_VFIR,
+ PERIPHC_1Bh,
+ PERIPHC_1Ch,
+ PERIPHC_HSI,
+ PERIPHC_UART1,
+ PERIPHC_UART2,
+
+ /* 0x20 */
+ PERIPHC_HOST1X,
+ PERIPHC_21h,
+ PERIPHC_22h,
+ PERIPHC_HDMI,
+ PERIPHC_24h,
+ PERIPHC_25h,
+ PERIPHC_I2C2,
+ PERIPHC_EMC,
+
+ /* 0x28 */
+ PERIPHC_UART3,
+ PERIPHC_29h,
+ PERIPHC_VI_SENSOR,
+ PERIPHC_2bh,
+ PERIPHC_2ch,
+ PERIPHC_SBC4,
+ PERIPHC_I2C3,
+ PERIPHC_SDMMC3,
+
+ /* 0x30 */
+ PERIPHC_UART4,
+ PERIPHC_UART5,
+ PERIPHC_VDE,
+ PERIPHC_OWR,
+ PERIPHC_NOR,
+ PERIPHC_CSITE,
+ PERIPHC_I2S0,
+ PERIPHC_DTV,
+
+ /* 0x38 */
+ PERIPHC_38h,
+ PERIPHC_39h,
+ PERIPHC_3ah,
+ PERIPHC_3bh,
+ PERIPHC_MSENC,
+ PERIPHC_TSEC,
+ PERIPHC_3eh,
+ PERIPHC_OSC,
+
+ PERIPHC_VW_FIRST,
+ /* 0x40 */
+ PERIPHC_40h = PERIPHC_VW_FIRST,
+ PERIPHC_MSELECT,
+ PERIPHC_TSENSOR,
+ PERIPHC_I2S3,
+ PERIPHC_I2S4,
+ PERIPHC_I2C4,
+ PERIPHC_SBC5,
+ PERIPHC_SBC6,
+
+ /* 0x48 */
+ PERIPHC_AUDIO,
+ PERIPHC_49h,
+ PERIPHC_DAM0,
+ PERIPHC_DAM1,
+ PERIPHC_DAM2,
+ PERIPHC_HDA2CODEC2X,
+ PERIPHC_ACTMON,
+ PERIPHC_EXTPERIPH1,
+
+ /* 0x50 */
+ PERIPHC_EXTPERIPH2,
+ PERIPHC_EXTPERIPH3,
+ PERIPHC_52h,
+ PERIPHC_I2CSLOW,
+ PERIPHC_SYS,
+ PERIPHC_55h,
+ PERIPHC_56h,
+ PERIPHC_57h,
+
+ /* 0x58 */
+ PERIPHC_58h,
+ PERIPHC_59h,
+ PERIPHC_5ah,
+ PERIPHC_5bh,
+ PERIPHC_SATAOOB,
+ PERIPHC_SATA,
+ PERIPHC_HDA, /* 0x428 */
+ PERIPHC_5fh,
+
+ PERIPHC_X_FIRST,
+ /* 0x60 */
+ PERIPHC_XUSB_CORE_HOST = PERIPHC_X_FIRST, /* 0x600 */
+ PERIPHC_XUSB_FALCON,
+ PERIPHC_XUSB_FS,
+ PERIPHC_XUSB_CORE_DEV,
+ PERIPHC_XUSB_SS,
+ PERIPHC_CILAB,
+ PERIPHC_CILCD,
+ PERIPHC_CILE,
+
+ /* 0x68 */
+ PERIPHC_DSIA_LP,
+ PERIPHC_DSIB_LP,
+ PERIPHC_ENTROPY,
+ PERIPHC_DVFS_REF,
+ PERIPHC_DVFS_SOC,
+ PERIPHC_TRACECLKIN,
+ PERIPHC_ADX0,
+ PERIPHC_AMX0,
+
+ /* 0x70 */
+ PERIPHC_EMC_LATENCY,
+ PERIPHC_SOC_THERM,
+ PERIPHC_72h,
+ PERIPHC_73h,
+ PERIPHC_74h,
+ PERIPHC_75h,
+ PERIPHC_VI_SENSOR2,
+ PERIPHC_I2C6,
+
+ /* 0x78 */
+ PERIPHC_78h,
+ PERIPHC_EMC_DLL,
+ PERIPHC_HDMI_AUDIO,
+ PERIPHC_CLK72MHZ,
+ PERIPHC_ADX1,
+ PERIPHC_AMX1,
+ PERIPHC_VIC,
+ PERIPHC_7fh,
+
+ PERIPHC_COUNT,
+
+ PERIPHC_NONE = -1,
+};
+
+/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
+#define PERIPH_REG(id) \
+ (id < PERIPH_ID_VW_FIRST) ? \
+ ((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
+
+/* Mask value for a clock (within PERIPH_REG(id)) */
+#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
+
+/* return 1 if a PLL ID is in range */
+#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
+
+/* return 1 if a peripheral ID is in range */
+#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
+ (id) < PERIPH_ID_COUNT)
+
+#endif /* _TEGRA124_CLOCK_TABLES_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Tegra124 clock control definitions */
+
+#ifndef _TEGRA124_CLOCK_H_
+#define _TEGRA124_CLOCK_H_
+
+#include <asm/arch-tegra/clock.h>
+
+/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
+#define OSC_FREQ_SHIFT 28
+#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT)
+
+#endif /* _TEGRA124_CLOCK_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA124_FLOW_H_
+#define _TEGRA124_FLOW_H_
+
+struct flow_ctlr {
+ u32 halt_cpu_events; /* offset 0x00 */
+ u32 halt_cop_events; /* offset 0x04 */
+ u32 cpu_csr; /* offset 0x08 */
+ u32 cop_csr; /* offset 0x0c */
+ u32 xrq_events; /* offset 0x10 */
+ u32 halt_cpu1_events; /* offset 0x14 */
+ u32 cpu1_csr; /* offset 0x18 */
+ u32 halt_cpu2_events; /* offset 0x1c */
+ u32 cpu2_csr; /* offset 0x20 */
+ u32 halt_cpu3_events; /* offset 0x24 */
+ u32 cpu3_csr; /* offset 0x28 */
+ u32 cluster_control; /* offset 0x2c */
+ u32 halt_cop1_events; /* offset 0x30 */
+ u32 halt_cop1_csr; /* offset 0x34 */
+ u32 cpu_pwr_csr; /* offset 0x38 */
+ u32 mpid; /* offset 0x3c */
+ u32 ram_repair; /* offset 0x40 */
+};
+
+/* HALT_COP_EVENTS_0, 0x04 */
+#define EVENT_MSEC (1 << 24)
+#define EVENT_USEC (1 << 25)
+#define EVENT_JTAG (1 << 28)
+#define EVENT_MODE_STOP (2 << 29)
+
+/* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */
+#define ACTIVE_LP (1 << 0)
+
+#endif /* _TEGRA124_FLOW_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Tegra124 high-level function multiplexing */
+
+#ifndef _TEGRA124_FUNCMUX_H_
+#define _TEGRA124_FUNCMUX_H_
+
+#include <asm/arch-tegra/funcmux.h>
+
+/* Configs supported by the func mux */
+enum {
+ FUNCMUX_DEFAULT = 0, /* default config */
+
+ /* UART configs */
+ FUNCMUX_UART1_KBC = 0,
+ FUNCMUX_UART4_GPIO = 0,
+};
+#endif /* _TEGRA124_FUNCMUX_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA124_GP_PADCTRL_H_
+#define _TEGRA124_GP_PADCTRL_H_
+
+#include <asm/arch-tegra/gp_padctrl.h>
+
+/* APB_MISC_GP and padctrl registers */
+struct apb_misc_gp_ctlr {
+ u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */
+ u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */
+ u32 reserved0[22]; /* 0x08 - 0x5C: */
+ u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
+ u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
+ u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
+ u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */
+ u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
+ u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
+ u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
+ u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */
+ u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */
+ u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */
+ u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */
+ u32 reserved1; /* 0x8C: */
+ u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */
+ u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */
+ u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */
+ u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */
+ u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */
+ u32 reserved2[3]; /* 0xA4 - 0xAC: */
+ u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */
+ u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */
+ u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */
+ u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */
+ u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */
+ u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */
+ u32 reserved3[9]; /* 0xC8-0xE8: */
+ u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
+ u32 reserved4[3]; /* 0xF0-0xF8: */
+ u32 ddccfg; /* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */
+ u32 gmacfg; /* 0x100: APB_MISC_GP_GMACFGPADCTRL */
+ u32 reserved5[3]; /* 0x104-0x10C: */
+ u32 gmecfg; /* 0x110: APB_MISC_GP_GMECFGPADCTRL */
+ u32 gmfcfg; /* 0x114: APB_MISC_GP_GMFCFGPADCTRL */
+ u32 gmgcfg; /* 0x118: APB_MISC_GP_GMGCFGPADCTRL */
+ u32 gmhcfg; /* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */
+ u32 owrcfg; /* 0x120: APB_MISC_GP_OWRCFGPADCTRL */
+ u32 uadcfg; /* 0x124: APB_MISC_GP_UADCFGPADCTRL */
+ u32 reserved6; /* 0x128: */
+ u32 dev3cfg; /* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */
+ u32 reserved7[2]; /* 0x130 - 0x134: */
+ u32 ceccfg; /* 0x138: APB_MISC_GP_CECCFGPADCTRL */
+ u32 reserved8[22]; /* 0x13C - 0x190: */
+ u32 atcfg6; /* 0x194: APB_MISC_GP_ATCFG6PADCTRL */
+ u32 dap5cfg; /* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */
+ u32 vbuscfg; /* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */
+ u32 aocfg3; /* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */
+ u32 hvccfg0; /* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */
+ u32 sdio4cfg; /* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */
+ u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */
+};
+
+/* SDMMC1/3 settings from section 27.5 of T114 TRM */
+#define SDIOCFG_DRVUP_SLWF 0
+#define SDIOCFG_DRVDN_SLWR 0
+#define SDIOCFG_DRVUP 0x24
+#define SDIOCFG_DRVDN 0x14
+
+#endif /* _TEGRA124_GP_PADCTRL_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA124_GPIO_H_
+#define _TEGRA124_GPIO_H_
+
+/*
+ * The Tegra124 GPIO controller has 256 GPIOS in 8 banks of 4 ports,
+ * each with 8 GPIOs.
+ */
+#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */
+#define TEGRA_GPIO_BANKS 8 /* number of banks */
+
+#include <asm/arch-tegra/gpio.h>
+
+/* GPIO Controller registers for a single bank */
+struct gpio_ctlr_bank {
+ uint gpio_config[TEGRA_GPIO_PORTS];
+ uint gpio_dir_out[TEGRA_GPIO_PORTS];
+ uint gpio_out[TEGRA_GPIO_PORTS];
+ uint gpio_in[TEGRA_GPIO_PORTS];
+ uint gpio_int_status[TEGRA_GPIO_PORTS];
+ uint gpio_int_enable[TEGRA_GPIO_PORTS];
+ uint gpio_int_level[TEGRA_GPIO_PORTS];
+ uint gpio_int_clear[TEGRA_GPIO_PORTS];
+ uint gpio_masked_config[TEGRA_GPIO_PORTS];
+ uint gpio_masked_dir_out[TEGRA_GPIO_PORTS];
+ uint gpio_masked_out[TEGRA_GPIO_PORTS];
+ uint gpio_masked_in[TEGRA_GPIO_PORTS];
+ uint gpio_masked_int_status[TEGRA_GPIO_PORTS];
+ uint gpio_masked_int_enable[TEGRA_GPIO_PORTS];
+ uint gpio_masked_int_level[TEGRA_GPIO_PORTS];
+ uint gpio_masked_int_clear[TEGRA_GPIO_PORTS];
+};
+
+struct gpio_ctlr {
+ struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
+};
+
+enum gpio_pin {
+ GPIO_PA0 = 0, /* pin 0 */
+ GPIO_PA1,
+ GPIO_PA2,
+ GPIO_PA3,
+ GPIO_PA4,
+ GPIO_PA5,
+ GPIO_PA6,
+ GPIO_PA7,
+ GPIO_PB0, /* pin 8 */
+ GPIO_PB1,
+ GPIO_PB2,
+ GPIO_PB3,
+ GPIO_PB4,
+ GPIO_PB5,
+ GPIO_PB6,
+ GPIO_PB7,
+ GPIO_PC0, /* pin 16 */
+ GPIO_PC1,
+ GPIO_PC2,
+ GPIO_PC3,
+ GPIO_PC4,
+ GPIO_PC5,
+ GPIO_PC6,
+ GPIO_PC7,
+ GPIO_PD0, /* pin 24 */
+ GPIO_PD1,
+ GPIO_PD2,
+ GPIO_PD3,
+ GPIO_PD4,
+ GPIO_PD5,
+ GPIO_PD6,
+ GPIO_PD7,
+ GPIO_PE0, /* pin 32 */
+ GPIO_PE1,
+ GPIO_PE2,
+ GPIO_PE3,
+ GPIO_PE4,
+ GPIO_PE5,
+ GPIO_PE6,
+ GPIO_PE7,
+ GPIO_PF0, /* pin 40 */
+ GPIO_PF1,
+ GPIO_PF2,
+ GPIO_PF3,
+ GPIO_PF4,
+ GPIO_PF5,
+ GPIO_PF6,
+ GPIO_PF7,
+ GPIO_PG0, /* pin 48 */
+ GPIO_PG1,
+ GPIO_PG2,
+ GPIO_PG3,
+ GPIO_PG4,
+ GPIO_PG5,
+ GPIO_PG6,
+ GPIO_PG7,
+ GPIO_PH0, /* pin 56 */
+ GPIO_PH1,
+ GPIO_PH2,
+ GPIO_PH3,
+ GPIO_PH4,
+ GPIO_PH5,
+ GPIO_PH6,
+ GPIO_PH7,
+ GPIO_PI0, /* pin 64 */
+ GPIO_PI1,
+ GPIO_PI2,
+ GPIO_PI3,
+ GPIO_PI4,
+ GPIO_PI5,
+ GPIO_PI6,
+ GPIO_PI7,
+ GPIO_PJ0, /* pin 72 */
+ GPIO_PJ1,
+ GPIO_PJ2,
+ GPIO_PJ3,
+ GPIO_PJ4,
+ GPIO_PJ5,
+ GPIO_PJ6,
+ GPIO_PJ7,
+ GPIO_PK0, /* pin 80 */
+ GPIO_PK1,
+ GPIO_PK2,
+ GPIO_PK3,
+ GPIO_PK4,
+ GPIO_PK5,
+ GPIO_PK6,
+ GPIO_PK7,
+ GPIO_PL0, /* pin 88 */
+ GPIO_PL1,
+ GPIO_PL2,
+ GPIO_PL3,
+ GPIO_PL4,
+ GPIO_PL5,
+ GPIO_PL6,
+ GPIO_PL7,
+ GPIO_PM0, /* pin 96 */
+ GPIO_PM1,
+ GPIO_PM2,
+ GPIO_PM3,
+ GPIO_PM4,
+ GPIO_PM5,
+ GPIO_PM6,
+ GPIO_PM7,
+ GPIO_PN0, /* pin 104 */
+ GPIO_PN1,
+ GPIO_PN2,
+ GPIO_PN3,
+ GPIO_PN4,
+ GPIO_PN5,
+ GPIO_PN6,
+ GPIO_PN7,
+ GPIO_PO0, /* pin 112 */
+ GPIO_PO1,
+ GPIO_PO2,
+ GPIO_PO3,
+ GPIO_PO4,
+ GPIO_PO5,
+ GPIO_PO6,
+ GPIO_PO7,
+ GPIO_PP0, /* pin 120 */
+ GPIO_PP1,
+ GPIO_PP2,
+ GPIO_PP3,
+ GPIO_PP4,
+ GPIO_PP5,
+ GPIO_PP6,
+ GPIO_PP7,
+ GPIO_PQ0, /* pin 128 */
+ GPIO_PQ1,
+ GPIO_PQ2,
+ GPIO_PQ3,
+ GPIO_PQ4,
+ GPIO_PQ5,
+ GPIO_PQ6,
+ GPIO_PQ7,
+ GPIO_PR0, /* pin 136 */
+ GPIO_PR1,
+ GPIO_PR2,
+ GPIO_PR3,
+ GPIO_PR4,
+ GPIO_PR5,
+ GPIO_PR6,
+ GPIO_PR7,
+ GPIO_PS0, /* pin 144 */
+ GPIO_PS1,
+ GPIO_PS2,
+ GPIO_PS3,
+ GPIO_PS4,
+ GPIO_PS5,
+ GPIO_PS6,
+ GPIO_PS7,
+ GPIO_PT0, /* pin 152 */
+ GPIO_PT1,
+ GPIO_PT2,
+ GPIO_PT3,
+ GPIO_PT4,
+ GPIO_PT5,
+ GPIO_PT6,
+ GPIO_PT7,
+ GPIO_PU0, /* pin 160 */
+ GPIO_PU1,
+ GPIO_PU2,
+ GPIO_PU3,
+ GPIO_PU4,
+ GPIO_PU5,
+ GPIO_PU6,
+ GPIO_PU7,
+ GPIO_PV0, /* pin 168 */
+ GPIO_PV1,
+ GPIO_PV2,
+ GPIO_PV3,
+ GPIO_PV4,
+ GPIO_PV5,
+ GPIO_PV6,
+ GPIO_PV7,
+ GPIO_PW0, /* pin 176 */
+ GPIO_PW1,
+ GPIO_PW2,
+ GPIO_PW3,
+ GPIO_PW4,
+ GPIO_PW5,
+ GPIO_PW6,
+ GPIO_PW7,
+ GPIO_PX0, /* pin 184 */
+ GPIO_PX1,
+ GPIO_PX2,
+ GPIO_PX3,
+ GPIO_PX4,
+ GPIO_PX5,
+ GPIO_PX6,
+ GPIO_PX7,
+ GPIO_PY0, /* pin 192 */
+ GPIO_PY1,
+ GPIO_PY2,
+ GPIO_PY3,
+ GPIO_PY4,
+ GPIO_PY5,
+ GPIO_PY6,
+ GPIO_PY7,
+ GPIO_PZ0, /* pin 200 */
+ GPIO_PZ1,
+ GPIO_PZ2,
+ GPIO_PZ3,
+ GPIO_PZ4,
+ GPIO_PZ5,
+ GPIO_PZ6,
+ GPIO_PZ7,
+ GPIO_PAA0, /* pin 208 */
+ GPIO_PAA1,
+ GPIO_PAA2,
+ GPIO_PAA3,
+ GPIO_PAA4,
+ GPIO_PAA5,
+ GPIO_PAA6,
+ GPIO_PAA7,
+ GPIO_PBB0, /* pin 216 */
+ GPIO_PBB1,
+ GPIO_PBB2,
+ GPIO_PBB3,
+ GPIO_PBB4,
+ GPIO_PBB5,
+ GPIO_PBB6,
+ GPIO_PBB7,
+ GPIO_PCC0, /* pin 224 */
+ GPIO_PCC1,
+ GPIO_PCC2,
+ GPIO_PCC3,
+ GPIO_PCC4,
+ GPIO_PCC5,
+ GPIO_PCC6,
+ GPIO_PCC7,
+ GPIO_PDD0, /* pin 232 */
+ GPIO_PDD1,
+ GPIO_PDD2,
+ GPIO_PDD3,
+ GPIO_PDD4,
+ GPIO_PDD5,
+ GPIO_PDD6,
+ GPIO_PDD7,
+ GPIO_PEE0, /* pin 240 */
+ GPIO_PEE1,
+ GPIO_PEE2,
+ GPIO_PEE3,
+ GPIO_PEE4,
+ GPIO_PEE5,
+ GPIO_PEE6,
+ GPIO_PEE7,
+ GPIO_PFF0, /* pin 248 */
+ GPIO_PFF1,
+ GPIO_PFF2,
+ GPIO_PFF3,
+ GPIO_PFF4,
+ GPIO_PFF5,
+ GPIO_PFF6,
+ GPIO_PFF7, /* pin 255 */
+};
+
+#endif /* _TEGRA124_GPIO_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA124_HARDWARE_H_
+#define _TEGRA124_HARDWARE_H_
+
+/*
+ * Include Tegra-specific hardware definitions
+ * Nothing needed currently for Tegra124
+ */
+
+#endif /* _TEGRA124_HARDWARE_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA124_PINMUX_H_
+#define _TEGRA124_PINMUX_H_
+
+/*
+ * Pin groups which we adjust. There are three basic attributes of each pin
+ * group which use this enum:
+ *
+ * - function
+ * - pullup / pulldown
+ * - tristate or normal
+ */
+enum pmux_pingrp {
+ PINGRP_ULPI_DATA0 = 0, /* offset 0x3000 */
+ PINGRP_ULPI_DATA1,
+ PINGRP_ULPI_DATA2,
+ PINGRP_ULPI_DATA3,
+ PINGRP_ULPI_DATA4,
+ PINGRP_ULPI_DATA5,
+ PINGRP_ULPI_DATA6,
+ PINGRP_ULPI_DATA7,
+ PINGRP_ULPI_CLK,
+ PINGRP_ULPI_DIR,
+ PINGRP_ULPI_NXT,
+ PINGRP_ULPI_STP,
+ PINGRP_DAP3_FS,
+ PINGRP_DAP3_DIN,
+ PINGRP_DAP3_DOUT,
+ PINGRP_DAP3_SCLK,
+ PINGRP_GPIO_PV0,
+ PINGRP_GPIO_PV1,
+ PINGRP_SDMMC1_CLK,
+ PINGRP_SDMMC1_CMD,
+ PINGRP_SDMMC1_DAT3,
+ PINGRP_SDMMC1_DAT2,
+ PINGRP_SDMMC1_DAT1,
+ PINGRP_SDMMC1_DAT0,
+ PINGRP_CLK2_OUT = PINGRP_SDMMC1_DAT0 + 3,
+ PINGRP_CLK2_REQ,
+ PINGRP_HDMI_INT = PINGRP_CLK2_REQ + 41,
+ PINGRP_DDC_SCL,
+ PINGRP_DDC_SDA,
+ PINGRP_UART2_RXD = PINGRP_DDC_SDA + 19,
+ PINGRP_UART2_TXD,
+ PINGRP_UART2_RTS_N,
+ PINGRP_UART2_CTS_N,
+ PINGRP_UART3_TXD,
+ PINGRP_UART3_RXD,
+ PINGRP_UART3_CTS_N,
+ PINGRP_UART3_RTS_N,
+ PINGRP_GPIO_PU0,
+ PINGRP_GPIO_PU1,
+ PINGRP_GPIO_PU2,
+ PINGRP_GPIO_PU3,
+ PINGRP_GPIO_PU4,
+ PINGRP_GPIO_PU5,
+ PINGRP_GPIO_PU6,
+ PINGRP_GEN1_I2C_SDA,
+ PINGRP_GEN1_I2C_SCL,
+ PINGRP_DAP4_FS,
+ PINGRP_DAP4_DIN,
+ PINGRP_DAP4_DOUT,
+ PINGRP_DAP4_SCLK,
+ PINGRP_CLK3_OUT,
+ PINGRP_CLK3_REQ,
+ /* Renamed on Tegra124, from GMI_xx to GPIO_Pxx */
+ PINGRP_GPIO_PC7, /* offset 0x31c0 */
+ PINGRP_GPIO_PI5,
+ PINGRP_GPIO_PI7,
+ PINGRP_GPIO_PK0,
+ PINGRP_GPIO_PK1,
+ PINGRP_GPIO_PJ0,
+ PINGRP_GPIO_PJ2,
+ PINGRP_GPIO_PK3,
+ PINGRP_GPIO_PK4,
+ PINGRP_GPIO_PK2,
+ PINGRP_GPIO_PI3,
+ PINGRP_GPIO_PI6,
+ PINGRP_GPIO_PG0,
+ PINGRP_GPIO_PG1,
+ PINGRP_GPIO_PG2,
+ PINGRP_GPIO_PG3,
+ PINGRP_GPIO_PG4,
+ PINGRP_GPIO_PG5,
+ PINGRP_GPIO_PG6,
+ PINGRP_GPIO_PG7,
+ PINGRP_GPIO_PH0,
+ PINGRP_GPIO_PH1,
+ PINGRP_GPIO_PH2,
+ PINGRP_GPIO_PH3,
+ PINGRP_GPIO_PH4,
+ PINGRP_GPIO_PH5,
+ PINGRP_GPIO_PH6,
+ PINGRP_GPIO_PH7,
+ PINGRP_GPIO_PJ7,
+ PINGRP_GPIO_PB0,
+ PINGRP_GPIO_PB1,
+ PINGRP_GPIO_PK7,
+ PINGRP_GPIO_PI0,
+ PINGRP_GPIO_PI1,
+ PINGRP_GPIO_PI2,
+ PINGRP_GPIO_PI4, /* offset 0x324c */
+ PINGRP_GEN2_I2C_SCL,
+ PINGRP_GEN2_I2C_SDA,
+ PINGRP_SDMMC4_CLK,
+ PINGRP_SDMMC4_CMD,
+ PINGRP_SDMMC4_DAT0,
+ PINGRP_SDMMC4_DAT1,
+ PINGRP_SDMMC4_DAT2,
+ PINGRP_SDMMC4_DAT3,
+ PINGRP_SDMMC4_DAT4,
+ PINGRP_SDMMC4_DAT5,
+ PINGRP_SDMMC4_DAT6,
+ PINGRP_SDMMC4_DAT7,
+ PINGRP_CAM_MCLK = PINGRP_SDMMC4_DAT7 + 2,
+ PINGRP_GPIO_PCC1,
+ PINGRP_GPIO_PBB0,
+ PINGRP_CAM_I2C_SCL,
+ PINGRP_CAM_I2C_SDA,
+ PINGRP_GPIO_PBB3,
+ PINGRP_GPIO_PBB4,
+ PINGRP_GPIO_PBB5,
+ PINGRP_GPIO_PBB6,
+ PINGRP_GPIO_PBB7,
+ PINGRP_GPIO_PCC2,
+ PINGRP_JTAG_RTCK,
+ PINGRP_PWR_I2C_SCL,
+ PINGRP_PWR_I2C_SDA,
+ PINGRP_KB_ROW0,
+ PINGRP_KB_ROW1,
+ PINGRP_KB_ROW2,
+ PINGRP_KB_ROW3,
+ PINGRP_KB_ROW4,
+ PINGRP_KB_ROW5,
+ PINGRP_KB_ROW6,
+ PINGRP_KB_ROW7,
+ PINGRP_KB_ROW8,
+ PINGRP_KB_ROW9,
+ PINGRP_KB_ROW10,
+ PINGRP_KB_ROW11,
+ PINGRP_KB_ROW12,
+ PINGRP_KB_ROW13,
+ PINGRP_KB_ROW14,
+ PINGRP_KB_ROW15,
+ PINGRP_KB_COL0, /* offset 0x32fc */
+ PINGRP_KB_COL1,
+ PINGRP_KB_COL2,
+ PINGRP_KB_COL3,
+ PINGRP_KB_COL4,
+ PINGRP_KB_COL5,
+ PINGRP_KB_COL6,
+ PINGRP_KB_COL7,
+ PINGRP_CLK_32K_OUT,
+ PINGRP_CORE_PWR_REQ = PINGRP_CLK_32K_OUT + 2, /* offset 0x3324 */
+ PINGRP_CPU_PWR_REQ,
+ PINGRP_PWR_INT_N,
+ PINGRP_CLK_32K_IN,
+ PINGRP_OWR,
+ PINGRP_DAP1_FS,
+ PINGRP_DAP1_DIN,
+ PINGRP_DAP1_DOUT,
+ PINGRP_DAP1_SCLK,
+ PINGRP_CLK1_REQ,
+ PINGRP_CLK1_OUT,
+ PINGRP_SPDIF_IN,
+ PINGRP_SPDIF_OUT,
+ PINGRP_DAP2_FS,
+ PINGRP_DAP2_DIN,
+ PINGRP_DAP2_DOUT,
+ PINGRP_DAP2_SCLK,
+ PINGRP_DVFS_PWM,
+ PINGRP_GPIO_X1_AUD,
+ PINGRP_GPIO_X3_AUD,
+ PINGRP_DVFS_CLK,
+ PINGRP_GPIO_X4_AUD,
+ PINGRP_GPIO_X5_AUD,
+ PINGRP_GPIO_X6_AUD,
+ PINGRP_GPIO_X7_AUD,
+ PINGRP_SDMMC3_CLK = PINGRP_GPIO_X7_AUD + 3,
+ PINGRP_SDMMC3_CMD,
+ PINGRP_SDMMC3_DAT0,
+ PINGRP_SDMMC3_DAT1,
+ PINGRP_SDMMC3_DAT2,
+ PINGRP_SDMMC3_DAT3,
+ PINGRP_PEX_L0_RST = PINGRP_SDMMC3_DAT3 + 6, /* offset 0x33bc */
+ PINGRP_PEX_L0_CLKREQ,
+ PINGRP_PEX_WAKE,
+ PINGRP_PEX_L1_RST = PINGRP_PEX_WAKE + 2,
+ PINGRP_PEX_L1_CLKREQ,
+ PINGRP_HDMI_CEC = PINGRP_PEX_L1_CLKREQ + 4, /* offset 0x33e0 */
+ PINGRP_SDMMC1_WP_N,
+ PINGRP_SDMMC3_CD_N,
+ PINGRP_GPIO_W2_AUD,
+ PINGRP_GPIO_W3_AUD,
+ PINGRP_USB_VBUS_EN0,
+ PINGRP_USB_VBUS_EN1,
+ PINGRP_SDMMC3_CLK_LB_IN,
+ PINGRP_SDMMC3_CLK_LB_OUT,
+ PINGRP_GMI_CLK_LB,
+ PINGRP_RESET_OUT_N,
+ PINGRP_KB_ROW16, /* offset 0x340c */
+ PINGRP_KB_ROW17,
+ PINGRP_USB_VBUS_EN2,
+ PINGRP_GPIO_PFF2,
+ PINGRP_DP_HPD, /* last reg offset = 0x3430 */
+ PINGRP_COUNT,
+};
+
+enum pdrive_pingrp {
+ PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
+ PDRIVE_PINGROUP_AO2,
+ PDRIVE_PINGROUP_AT1,
+ PDRIVE_PINGROUP_AT2,
+ PDRIVE_PINGROUP_AT3,
+ PDRIVE_PINGROUP_AT4,
+ PDRIVE_PINGROUP_AT5,
+ PDRIVE_PINGROUP_CDEV1,
+ PDRIVE_PINGROUP_CDEV2,
+ PDRIVE_PINGROUP_DAP1 = 10, /* offset 0x890 */
+ PDRIVE_PINGROUP_DAP2,
+ PDRIVE_PINGROUP_DAP3,
+ PDRIVE_PINGROUP_DAP4,
+ PDRIVE_PINGROUP_DBG,
+ PDRIVE_PINGROUP_SDIO3 = 18, /* offset 0x8B0 */
+ PDRIVE_PINGROUP_SPI,
+ PDRIVE_PINGROUP_UAA,
+ PDRIVE_PINGROUP_UAB,
+ PDRIVE_PINGROUP_UART2,
+ PDRIVE_PINGROUP_UART3,
+ PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8EC */
+ PDRIVE_PINGROUP_DDC = 37, /* offset 0x8FC */
+ PDRIVE_PINGROUP_GMA,
+ PDRIVE_PINGROUP_GME = 42, /* offset 0x910 */
+ PDRIVE_PINGROUP_GMF,
+ PDRIVE_PINGROUP_GMG,
+ PDRIVE_PINGROUP_GMH,
+ PDRIVE_PINGROUP_OWR,
+ PDRIVE_PINGROUP_UAD,
+ PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */
+ PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */
+ PDRIVE_PINGROUP_AT6 = 75, /* offset 0x994 */
+ PDRIVE_PINGROUP_DAP5,
+ PDRIVE_PINGROUP_VBUS,
+ PDRIVE_PINGROUP_AO3,
+ PDRIVE_PINGROUP_HVC,
+ PDRIVE_PINGROUP_SDIO4,
+ PDRIVE_PINGROUP_AO0,
+ PDRIVE_PINGROUP_COUNT,
+};
+
+/*
+ * Functions which can be assigned to each of the pin groups. The values here
+ * bear no relation to the values programmed into pinmux registers and are
+ * purely a convenience. The translation is done through a table search.
+ */
+enum pmux_func {
+ PMUX_FUNC_AHB_CLK,
+ PMUX_FUNC_APB_CLK,
+ PMUX_FUNC_AUDIO_SYNC,
+ PMUX_FUNC_CRT,
+ PMUX_FUNC_DAP1,
+ PMUX_FUNC_DAP2,
+ PMUX_FUNC_DAP3,
+ PMUX_FUNC_DAP4,
+ PMUX_FUNC_DAP5,
+ PMUX_FUNC_DISPA,
+ PMUX_FUNC_DISPB,
+ PMUX_FUNC_EMC_TEST0_DLL,
+ PMUX_FUNC_EMC_TEST1_DLL,
+ PMUX_FUNC_GMI,
+ PMUX_FUNC_GMI_INT,
+ PMUX_FUNC_HDMI,
+ PMUX_FUNC_I2C1,
+ PMUX_FUNC_I2C2,
+ PMUX_FUNC_I2C3,
+ PMUX_FUNC_IDE,
+ PMUX_FUNC_KBC,
+ PMUX_FUNC_MIO,
+ PMUX_FUNC_MIPI_HS,
+ PMUX_FUNC_NAND,
+ PMUX_FUNC_OSC,
+ PMUX_FUNC_OWR,
+ PMUX_FUNC_PCIE,
+ PMUX_FUNC_PLLA_OUT,
+ PMUX_FUNC_PLLC_OUT1,
+ PMUX_FUNC_PLLM_OUT1,
+ PMUX_FUNC_PLLP_OUT2,
+ PMUX_FUNC_PLLP_OUT3,
+ PMUX_FUNC_PLLP_OUT4,
+ PMUX_FUNC_PWM,
+ PMUX_FUNC_PWR_INTR,
+ PMUX_FUNC_PWR_ON,
+ PMUX_FUNC_RTCK,
+ PMUX_FUNC_SDMMC1,
+ PMUX_FUNC_SDMMC2,
+ PMUX_FUNC_SDMMC3,
+ PMUX_FUNC_SDMMC4,
+ PMUX_FUNC_SFLASH,
+ PMUX_FUNC_SPDIF,
+ PMUX_FUNC_SPI1,
+ PMUX_FUNC_SPI2,
+ PMUX_FUNC_SPI2_ALT,
+ PMUX_FUNC_SPI3,
+ PMUX_FUNC_SPI4,
+ PMUX_FUNC_TRACE,
+ PMUX_FUNC_TWC,
+ PMUX_FUNC_UARTA,
+ PMUX_FUNC_UARTB,
+ PMUX_FUNC_UARTC,
+ PMUX_FUNC_UARTD,
+ PMUX_FUNC_UARTE,
+ PMUX_FUNC_ULPI,
+ PMUX_FUNC_VI,
+ PMUX_FUNC_VI_SENSOR_CLK,
+ PMUX_FUNC_XIO,
+ /* End of Tegra2 MUX selectors */
+ PMUX_FUNC_BLINK,
+ PMUX_FUNC_CEC,
+ PMUX_FUNC_CLK12,
+ PMUX_FUNC_DAP,
+ PMUX_FUNC_DAPSDMMC2,
+ PMUX_FUNC_DDR,
+ PMUX_FUNC_DEV3,
+ PMUX_FUNC_DTV,
+ PMUX_FUNC_VI_ALT1,
+ PMUX_FUNC_VI_ALT2,
+ PMUX_FUNC_VI_ALT3,
+ PMUX_FUNC_EMC_DLL,
+ PMUX_FUNC_EXTPERIPH1,
+ PMUX_FUNC_EXTPERIPH2,
+ PMUX_FUNC_EXTPERIPH3,
+ PMUX_FUNC_GMI_ALT,
+ PMUX_FUNC_HDA,
+ PMUX_FUNC_HSI,
+ PMUX_FUNC_I2C4,
+ PMUX_FUNC_I2C5,
+ PMUX_FUNC_I2CPWR,
+ PMUX_FUNC_I2S0,
+ PMUX_FUNC_I2S1,
+ PMUX_FUNC_I2S2,
+ PMUX_FUNC_I2S3,
+ PMUX_FUNC_I2S4,
+ PMUX_FUNC_NAND_ALT,
+ PMUX_FUNC_POPSDIO4,
+ PMUX_FUNC_POPSDMMC4,
+ PMUX_FUNC_PWM0,
+ PMUX_FUNC_PWM1,
+ PMUX_FUNC_PWM2,
+ PMUX_FUNC_PWM3,
+ PMUX_FUNC_SATA,
+ PMUX_FUNC_SPI5,
+ PMUX_FUNC_SPI6,
+ PMUX_FUNC_SYSCLK,
+ PMUX_FUNC_VGP1,
+ PMUX_FUNC_VGP2,
+ PMUX_FUNC_VGP3,
+ PMUX_FUNC_VGP4,
+ PMUX_FUNC_VGP5,
+ PMUX_FUNC_VGP6,
+ /* End of Tegra3 MUX selectors */
+ PMUX_FUNC_USB,
+ PMUX_FUNC_SOC,
+ PMUX_FUNC_CPU,
+ PMUX_FUNC_CLK,
+ PMUX_FUNC_PWRON,
+ PMUX_FUNC_PMI,
+ PMUX_FUNC_CLDVFS,
+ PMUX_FUNC_RESET_OUT_N,
+ /* End of Tegra114 MUX selectors */
+
+ PMUX_FUNC_SAFE,
+ PMUX_FUNC_MAX,
+
+ PMUX_FUNC_INVALID = 0x4000,
+ PMUX_FUNC_RSVD1 = 0x8000,
+ PMUX_FUNC_RSVD2 = 0x8001,
+ PMUX_FUNC_RSVD3 = 0x8002,
+ PMUX_FUNC_RSVD4 = 0x8003,
+};
+
+/* return 1 if a pmux_func is in range */
+#define pmux_func_isvalid(func) \
+ ((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) || \
+ (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
+
+/* return 1 if a pingrp is in range */
+#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT))
+
+/* The pullup/pulldown state of a pin group */
+enum pmux_pull {
+ PMUX_PULL_NORMAL = 0,
+ PMUX_PULL_DOWN,
+ PMUX_PULL_UP,
+};
+/* return 1 if a pin_pupd_is in range */
+#define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \
+ ((pupd) <= PMUX_PULL_UP))
+
+/* Defines whether a pin group is tristated or in normal operation */
+enum pmux_tristate {
+ PMUX_TRI_NORMAL = 0,
+ PMUX_TRI_TRISTATE = 1,
+};
+/* return 1 if a pin_tristate_is in range */
+#define pmux_pin_tristate_isvalid(tristate) \
+ (((tristate) >= PMUX_TRI_NORMAL) && \
+ ((tristate) <= PMUX_TRI_TRISTATE))
+
+enum pmux_pin_io {
+ PMUX_PIN_OUTPUT = 0,
+ PMUX_PIN_INPUT = 1,
+ PMUX_PIN_NONE,
+};
+/* return 1 if a pin_io_is in range */
+#define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \
+ ((io) <= PMUX_PIN_INPUT))
+
+enum pmux_pin_lock {
+ PMUX_PIN_LOCK_DEFAULT = 0,
+ PMUX_PIN_LOCK_DISABLE,
+ PMUX_PIN_LOCK_ENABLE,
+};
+/* return 1 if a pin_lock is in range */
+#define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \
+ ((lock) <= PMUX_PIN_LOCK_ENABLE))
+
+enum pmux_pin_od {
+ PMUX_PIN_OD_DEFAULT = 0,
+ PMUX_PIN_OD_DISABLE,
+ PMUX_PIN_OD_ENABLE,
+};
+/* return 1 if a pin_od is in range */
+#define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \
+ ((od) <= PMUX_PIN_OD_ENABLE))
+
+enum pmux_pin_ioreset {
+ PMUX_PIN_IO_RESET_DEFAULT = 0,
+ PMUX_PIN_IO_RESET_DISABLE,
+ PMUX_PIN_IO_RESET_ENABLE,
+};
+/* return 1 if a pin_ioreset_is in range */
+#define pmux_pin_ioreset_isvalid(ioreset) \
+ (((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
+ ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
+
+enum pmux_pin_rcv_sel {
+ PMUX_PIN_RCV_SEL_DEFAULT = 0,
+ PMUX_PIN_RCV_SEL_NORMAL,
+ PMUX_PIN_RCV_SEL_HIGH,
+};
+/* return 1 if a pin_rcv_sel_is in range */
+#define pmux_pin_rcv_sel_isvalid(rcv_sel) \
+ (((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \
+ ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
+
+/* Available power domains used by pin groups */
+enum pmux_vddio {
+ PMUX_VDDIO_BB = 0,
+ PMUX_VDDIO_LCD,
+ PMUX_VDDIO_VI,
+ PMUX_VDDIO_UART,
+ PMUX_VDDIO_DDR,
+ PMUX_VDDIO_NAND,
+ PMUX_VDDIO_SYS,
+ PMUX_VDDIO_AUDIO,
+ PMUX_VDDIO_SD,
+ PMUX_VDDIO_CAM,
+ PMUX_VDDIO_GMI,
+ PMUX_VDDIO_PEXCTL,
+ PMUX_VDDIO_SDMMC1,
+ PMUX_VDDIO_SDMMC3,
+ PMUX_VDDIO_SDMMC4,
+
+ PMUX_VDDIO_NONE
+};
+
+#define PGRP_SLWF_NONE -1
+#define PGRP_SLWF_MAX 3
+#define PGRP_SLWR_NONE PGRP_SLWF_NONE
+#define PGRP_SLWR_MAX PGRP_SLWF_MAX
+
+#define PGRP_DRVUP_NONE -1
+#define PGRP_DRVUP_MAX 127
+#define PGRP_DRVDN_NONE PGRP_DRVUP_NONE
+#define PGRP_DRVDN_MAX PGRP_DRVUP_MAX
+
+#define PGRP_SCHMT_NONE -1
+#define PGRP_HSM_NONE PGRP_SCHMT_NONE
+
+/* return 1 if a padgrp is in range */
+#define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT))
+
+/* return 1 if a slew-rate rising/falling edge value is in range */
+#define pmux_pad_slw_isvalid(slw) (((slw) == PGRP_SLWF_NONE) || \
+ (((slw) >= 0) && ((slw) <= PGRP_SLWF_MAX)))
+
+/* return 1 if a driver output pull-up/down strength code value is in range */
+#define pmux_pad_drv_isvalid(drv) (((drv) == PGRP_DRVUP_NONE) || \
+ (((drv) >= 0) && ((drv) <= PGRP_DRVUP_MAX)))
+
+/* return 1 if a low-power mode value is in range */
+#define pmux_pad_lpmd_isvalid(lpm) (((lpm) == PGRP_LPMD_NONE) || \
+ (((lpm) >= 0) && ((lpm) <= PGRP_LPMD_X)))
+
+/* Defines a pin group cfg's low-power mode select */
+enum pgrp_lpmd {
+ PGRP_LPMD_X8 = 0,
+ PGRP_LPMD_X4,
+ PGRP_LPMD_X2,
+ PGRP_LPMD_X,
+ PGRP_LPMD_NONE = -1,
+};
+
+/* Defines whether a pin group cfg's schmidt is enabled or not */
+enum pgrp_schmt {
+ PGRP_SCHMT_DISABLE = 0,
+ PGRP_SCHMT_ENABLE = 1,
+};
+
+/* Defines whether a pin group cfg's high-speed mode is enabled or not */
+enum pgrp_hsm {
+ PGRP_HSM_DISABLE = 0,
+ PGRP_HSM_ENABLE = 1,
+};
+
+/*
+ * This defines the configuration for a pin group's pad control config
+ */
+struct padctrl_config {
+ enum pdrive_pingrp padgrp; /* pin group PDRIVE_PINGRP_x */
+ int slwf; /* falling edge slew */
+ int slwr; /* rising edge slew */
+ int drvup; /* pull-up drive strength */
+ int drvdn; /* pull-down drive strength */
+ enum pgrp_lpmd lpmd; /* low-power mode selection */
+ enum pgrp_schmt schmt; /* schmidt enable */
+ enum pgrp_hsm hsm; /* high-speed mode enable */
+};
+
+/* Tegra124 pin drive group and pin mux registers */
+#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2)
+#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
+ PDRIVE_PINGROUP_COUNT)
+struct pmux_tri_ctlr {
+ uint pmt_reserved0[9]; /* ABP_MISC_PP_ offsets 00-20 */
+ uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */
+
+ uint pmt_reserved[528]; /* ABP_MISC_PP_ reserved offs 28-864 */
+
+ uint pmt_drive[PDRIVE_PINGROUP_COUNT]; /* pin drive grps offs 868 */
+ uint pmt_reserved5[PMUX_OFFSET];
+ uint pmt_ctl[PINGRP_COUNT]; /* mux/pupd/tri regs, offset 0x3000 */
+};
+
+/*
+ * This defines the configuration for a pin, including the function assigned,
+ * pull up/down settings and tristate settings. Having set up one of these
+ * you can call pinmux_config_pingroup() to configure a pin in one step. Also
+ * available is pinmux_config_table() to configure a list of pins.
+ */
+struct pingroup_config {
+ enum pmux_pingrp pingroup; /* pin group PINGRP_... */
+ enum pmux_func func; /* function to assign FUNC_... */
+ enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/
+ enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */
+ enum pmux_pin_io io; /* input or output PMUX_PIN_... */
+ enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */
+ enum pmux_pin_od od; /* open-drain or push-pull driver */
+ enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */
+ enum pmux_pin_rcv_sel rcv_sel; /* select between High and Normal */
+ /* VIL/VIH receivers */
+};
+
+/* Set a pin group to tristate */
+void pinmux_tristate_enable(enum pmux_pingrp pin);
+
+/* Set a pin group to normal (non tristate) */
+void pinmux_tristate_disable(enum pmux_pingrp pin);
+
+/* Set the pull up/down feature for a pin group */
+void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
+
+/* Set the mux function for a pin group */
+void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
+
+/* Set the complete configuration for a pin group */
+void pinmux_config_pingroup(struct pingroup_config *config);
+
+/* Set a pin group to tristate or normal */
+void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
+
+/* Set a pin group as input or output */
+void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
+
+/**
+ * Configure a list of pin groups
+ *
+ * @param config List of config items
+ * @param len Number of config items in list
+ */
+void pinmux_config_table(struct pingroup_config *config, int len);
+
+/* Set a group of pins from a table */
+void pinmux_init(void);
+
+/**
+ * Set the GP pad configs
+ *
+ * @param config List of config items
+ * @param len Number of config items in list
+ */
+void padgrp_config_table(struct padctrl_config *config, int len);
+
+#endif /* _TEGRA124_PINMUX_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA124_PMU_H_
+#define _TEGRA124_PMU_H_
+
+/* Set core and CPU voltages to nominal levels */
+int pmu_set_nominal(void);
+
+#endif /* _TEGRA124_PMU_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_SPL_H_
+#define _ASM_ARCH_SPL_H_
+
+#define BOOT_DEVICE_RAM 1
+
+#endif /* _ASM_ARCH_SPL_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA124_SYSCTR_H_
+#define _TEGRA124_SYSCTR_H_
+
+struct sysctr_ctlr {
+ u32 cntcr; /* 0x00: SYSCTR0_CNTCR Counter Control */
+ u32 cntsr; /* 0x04: SYSCTR0_CNTSR Counter Status */
+ u32 cntcv0; /* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */
+ u32 cntcv1; /* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */
+ u32 reserved1[4]; /* 0x10 - 0x1C */
+ u32 cntfid0; /* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */
+ u32 cntfid1; /* 0x24: SYSCTR0_CNTFID1 Freq Table End */
+ u32 reserved2[1002]; /* 0x28 - 0xFCC */
+ u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */
+};
+
+#define TSC_CNTCR_ENABLE (1 << 0) /* Enable */
+#define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */
+
+#endif /* _TEGRA124_SYSCTR_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA124_H_
+#define _TEGRA124_H_
+
+#define NV_PA_SDRAM_BASE 0x80000000
+#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */
+#define NV_PA_MC_BASE 0x70019000 /* Mem Ctlr regs (MCB, etc.) */
+#define NV_PA_AHB_BASE 0x6000C000 /* System regs (AHB, etc.) */
+
+#include <asm/arch-tegra/tegra.h>
+
+#define BCT_ODMDATA_OFFSET 1704 /* offset to ODMDATA word */
+
+#undef NVBOOTINFOTABLE_BCTSIZE
+#undef NVBOOTINFOTABLE_BCTPTR
+#define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */
+#define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */
+
+#define MAX_NUM_CPU 4
+#define MCB_EMEM_ARB_OVERRIDE (NV_PA_MC_BASE + 0xE8)
+
+#define TEGRA_USB1_BASE 0x7D000000
+
+#endif /* _TEGRA124_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA124_USB_H_
+#define _TEGRA124_USB_H_
+
+
+/* USB Controller (USBx_CONTROLLER_) regs */
+struct usb_ctlr {
+ /* 0x000 */
+ uint id;
+ uint reserved0;
+ uint host;
+ uint device;
+
+ /* 0x010 */
+ uint txbuf;
+ uint rxbuf;
+ uint reserved1[2];
+
+ /* 0x020 */
+ uint reserved2[56];
+
+ /* 0x100 */
+ u16 cap_length;
+ u16 hci_version;
+ uint hcs_params;
+ uint hcc_params;
+ uint reserved3[5];
+
+ /* 0x120 */
+ uint dci_version;
+ uint dcc_params;
+ uint reserved4[2];
+
+ /* 0x130 */
+ uint usb_cmd;
+ uint usb_sts;
+ uint usb_intr;
+ uint frindex;
+
+ /* 0x140 */
+ uint reserved5;
+ uint periodic_list_base;
+ uint async_list_addr;
+ uint reserved5_1;
+
+ /* 0x150 */
+ uint burst_size;
+ uint tx_fill_tuning;
+ uint reserved6;
+ uint icusb_ctrl;
+
+ /* 0x160 */
+ uint ulpi_viewport;
+ uint reserved7;
+ uint reserved7_0;
+ uint reserved7_1;
+
+ /* 0x170 */
+ uint reserved;
+ uint port_sc1;
+ uint reserved8[6];
+
+ /* 0x190 */
+ uint reserved9[8];
+
+ /* 0x1b0 */
+ uint reserved10;
+ uint hostpc1_devlc;
+ uint reserved10_1[2];
+
+ /* 0x1c0 */
+ uint reserved10_2[4];
+
+ /* 0x1d0 */
+ uint reserved10_3[4];
+
+ /* 0x1e0 */
+ uint reserved10_4[4];
+
+ /* 0x1f0 */
+ uint reserved10_5;
+ uint otgsc;
+ uint usb_mode;
+ uint reserved10_6;
+
+ /* 0x200 */
+ uint endpt_nak;
+ uint endpt_nak_enable;
+ uint endpt_setup_stat;
+ uint reserved11_1[0x7D];
+
+ /* 0x400 */
+ uint susp_ctrl;
+ uint phy_vbus_sensors;
+ uint phy_vbus_wakeup_id;
+ uint phy_alt_vbus_sys;
+
+ /* 0x410 */
+ uint usb1_legacy_ctrl;
+ uint reserved12[3];
+
+ /* 0x420 */
+ uint reserved13[56];
+
+ /* 0x500 */
+ uint reserved14[64 * 3];
+
+ /* 0x800 */
+ uint utmip_pll_cfg0;
+ uint utmip_pll_cfg1;
+ uint utmip_xcvr_cfg0;
+ uint utmip_bias_cfg0;
+
+ /* 0x810 */
+ uint utmip_hsrx_cfg0;
+ uint utmip_hsrx_cfg1;
+ uint utmip_fslsrx_cfg0;
+ uint utmip_fslsrx_cfg1;
+
+ /* 0x820 */
+ uint utmip_tx_cfg0;
+ uint utmip_misc_cfg0;
+ uint utmip_misc_cfg1;
+ uint utmip_debounce_cfg0;
+
+ /* 0x830 */
+ uint utmip_bat_chrg_cfg0;
+ uint utmip_spare_cfg0;
+ uint utmip_xcvr_cfg1;
+ uint utmip_bias_cfg1;
+};
+
+/* USB1_LEGACY_CTRL */
+#define USB1_NO_LEGACY_MODE 1
+
+#define VBUS_SENSE_CTL_SHIFT 1
+#define VBUS_SENSE_CTL_MASK (3 << VBUS_SENSE_CTL_SHIFT)
+#define VBUS_SENSE_CTL_VBUS_WAKEUP 0
+#define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP 1
+#define VBUS_SENSE_CTL_AB_SESS_VLD 2
+#define VBUS_SENSE_CTL_A_SESS_VLD 3
+
+/* USBx_IF_USB_SUSP_CTRL_0 */
+#define UTMIP_PHY_ENB (1 << 12)
+#define UTMIP_RESET (1 << 11)
+#define USB_PHY_CLK_VALID (1 << 7)
+#define USB_SUSP_CLR (1 << 5)
+
+/* USBx_UTMIP_MISC_CFG0 */
+#define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22)
+
+/* USBx_UTMIP_MISC_CFG1 */
+#define UTMIP_PHY_XTAL_CLOCKEN (1 << 30)
+
+/* Moved to Clock and Reset register space */
+#define UTMIP_PLLU_STABLE_COUNT_SHIFT 6
+#define UTMIP_PLLU_STABLE_COUNT_MASK \
+ (0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT)
+/* Moved to Clock and Reset register space */
+#define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT 18
+#define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK \
+ (0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
+
+/* USBx_UTMIP_PLL_CFG1_0 */
+/* Moved to Clock and Reset register space */
+#define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT 27
+#define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK \
+ (0x1f << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
+#define UTMIP_XTAL_FREQ_COUNT_SHIFT 0
+#define UTMIP_XTAL_FREQ_COUNT_MASK 0xfff
+
+/* USBx_UTMIP_BIAS_CFG0_0 */
+#define UTMIP_HSDISCON_LEVEL_MSB (1 << 24)
+#define UTMIP_OTGPD (1 << 11)
+#define UTMIP_BIASPD (1 << 10)
+#define UTMIP_HSDISCON_LEVEL_SHIFT 2
+#define UTMIP_HSDISCON_LEVEL_MASK \
+ (0x3 << UTMIP_HSDISCON_LEVEL_SHIFT)
+#define UTMIP_HSSQUELCH_LEVEL_SHIFT 0
+#define UTMIP_HSSQUELCH_LEVEL_MASK \
+ (0x3 << UTMIP_HSSQUELCH_LEVEL_SHIFT)
+
+/* USBx_UTMIP_BIAS_CFG1_0 */
+#define UTMIP_FORCE_PDTRK_POWERDOWN 1
+#define UTMIP_BIAS_PDTRK_COUNT_SHIFT 3
+#define UTMIP_BIAS_PDTRK_COUNT_MASK \
+ (0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT)
+
+/* USBx_UTMIP_DEBOUNCE_CFG0_0 */
+#define UTMIP_DEBOUNCE_CFG0_SHIFT 0
+#define UTMIP_DEBOUNCE_CFG0_MASK 0xffff
+
+/* USBx_UTMIP_TX_CFG0_0 */
+#define UTMIP_FS_PREAMBLE_J (1 << 19)
+
+/* USBx_UTMIP_BAT_CHRG_CFG0_0 */
+#define UTMIP_PD_CHRG 1
+
+/* USBx_UTMIP_SPARE_CFG0_0 */
+#define FUSE_SETUP_SEL (1 << 3)
+
+/* USBx_UTMIP_HSRX_CFG0_0 */
+#define UTMIP_IDLE_WAIT_SHIFT 15
+#define UTMIP_IDLE_WAIT_MASK (0x1f << UTMIP_IDLE_WAIT_SHIFT)
+#define UTMIP_ELASTIC_LIMIT_SHIFT 10
+#define UTMIP_ELASTIC_LIMIT_MASK \
+ (0x1f << UTMIP_ELASTIC_LIMIT_SHIFT)
+
+/* USBx_UTMIP_HSRX_CFG0_1 */
+#define UTMIP_HS_SYNC_START_DLY_SHIFT 1
+#define UTMIP_HS_SYNC_START_DLY_MASK \
+ (0x1f << UTMIP_HS_SYNC_START_DLY_SHIFT)
+
+/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */
+#define IC_ENB1 (1 << 3)
+
+/* PORTSC1, USB1, defined for Tegra20 to avoid compiling error */
+#define PTS1_SHIFT 31
+#define PTS1_MASK (1 << PTS1_SHIFT)
+#define STS1 (1 << 30)
+
+/* USB2D_HOSTPC1_DEVLC_0 */
+#define PTS_SHIFT 29
+#define PTS_MASK (0x7U << PTS_SHIFT)
+#define PTS_UTMI 0
+#define PTS_RESERVED 1
+#define PTS_ULPI 2
+#define PTS_ICUSB_SER 3
+#define PTS_HSIC 4
+
+#define STS (1 << 28)
+
+/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */
+#define WKOC (1 << 22)
+#define WKDS (1 << 21)
+#define WKCN (1 << 20)
+
+/* USBx_UTMIP_XCVR_CFG0_0 */
+#define UTMIP_FORCE_PD_POWERDOWN (1 << 14)
+#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16)
+#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18)
+#define UTMIP_XCVR_LSBIAS_SE (1 << 21)
+#define UTMIP_XCVR_HSSLEW_MSB_SHIFT 25
+#define UTMIP_XCVR_HSSLEW_MSB_MASK \
+ (0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT)
+#define UTMIP_XCVR_SETUP_MSB_SHIFT 22
+#define UTMIP_XCVR_SETUP_MSB_MASK (0x7 << UTMIP_XCVR_SETUP_MSB_SHIFT)
+#define UTMIP_XCVR_SETUP_SHIFT 0
+#define UTMIP_XCVR_SETUP_MASK (0xf << UTMIP_XCVR_SETUP_SHIFT)
+
+/* USBx_UTMIP_XCVR_CFG1_0 */
+#define UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT 18
+#define UTMIP_XCVR_TERM_RANGE_ADJ_MASK \
+ (0xf << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT)
+#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0)
+#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2)
+#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4)
+
+/* USB3_IF_USB_PHY_VBUS_SENSORS_0 */
+#define VBUS_VLD_STS (1 << 26)
+
+#endif /* _TEGRA124_USB_H_ */
--- /dev/null
+/*
+ * Copyright (c) 2013 Xilinx Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ZYNQ_CLK_H_
+#define _ZYNQ_CLK_H_
+
+enum zynq_clk {
+ armpll_clk, ddrpll_clk, iopll_clk,
+ cpu_6or4x_clk, cpu_3or2x_clk, cpu_2x_clk, cpu_1x_clk,
+ ddr2x_clk, ddr3x_clk, dci_clk,
+ lqspi_clk, smc_clk, pcap_clk, gem0_clk, gem1_clk,
+ fclk0_clk, fclk1_clk, fclk2_clk, fclk3_clk, can0_clk, can1_clk,
+ sdio0_clk, sdio1_clk, uart0_clk, uart1_clk, spi0_clk, spi1_clk, dma_clk,
+ usb0_aper_clk, usb1_aper_clk, gem0_aper_clk, gem1_aper_clk,
+ sdio0_aper_clk, sdio1_aper_clk, spi0_aper_clk, spi1_aper_clk,
+ can0_aper_clk, can1_aper_clk, i2c0_aper_clk, i2c1_aper_clk,
+ uart0_aper_clk, uart1_aper_clk, gpio_aper_clk, lqspi_aper_clk,
+ smc_aper_clk, swdt_clk, dbg_trc_clk, dbg_apb_clk, clk_max};
+
+void zynq_clk_early_init(void);
+int zynq_clk_set_rate(enum zynq_clk clk, unsigned long rate);
+unsigned long zynq_clk_get_rate(enum zynq_clk clk);
+const char *zynq_clk_get_name(enum zynq_clk clk);
+unsigned long get_uart_clk(int dev_id);
+
+#endif
#ifndef _ASM_ARCH_HARDWARE_H
#define _ASM_ARCH_HARDWARE_H
+#define ZYNQ_SERIAL_BASEADDR0 0xE0000000
+#define ZYNQ_SERIAL_BASEADDR1 0xE0001000
#define ZYNQ_SYS_CTRL_BASEADDR 0xF8000000
#define ZYNQ_DEV_CFG_APB_BASEADDR 0xF8007000
#define ZYNQ_SCU_BASEADDR 0xF8F00000
#define ZYNQ_SPI_BASEADDR1 0xE0007000
#define ZYNQ_DDRC_BASEADDR 0xF8006000
+/* Bootmode setting values */
+#define ZYNQ_BM_MASK 0xF
+#define ZYNQ_BM_NOR 0x2
+#define ZYNQ_BM_SD 0x5
+#define ZYNQ_BM_JTAG 0x0
+
/* Reflect slcr offsets */
struct slcr_regs {
u32 scl; /* 0x0 */
u32 slcr_lock; /* 0x4 */
u32 slcr_unlock; /* 0x8 */
- u32 reserved0[75];
+ u32 reserved0_1[61];
+ u32 arm_pll_ctrl; /* 0x100 */
+ u32 ddr_pll_ctrl; /* 0x104 */
+ u32 io_pll_ctrl; /* 0x108 */
+ u32 reserved0_2[5];
+ u32 arm_clk_ctrl; /* 0x120 */
+ u32 ddr_clk_ctrl; /* 0x124 */
+ u32 dci_clk_ctrl; /* 0x128 */
+ u32 aper_clk_ctrl; /* 0x12c */
+ u32 reserved0_3[2];
u32 gem0_rclk_ctrl; /* 0x138 */
u32 gem1_rclk_ctrl; /* 0x13c */
u32 gem0_clk_ctrl; /* 0x140 */
u32 gem1_clk_ctrl; /* 0x144 */
- u32 reserved1[46];
+ u32 smc_clk_ctrl; /* 0x148 */
+ u32 lqspi_clk_ctrl; /* 0x14c */
+ u32 sdio_clk_ctrl; /* 0x150 */
+ u32 uart_clk_ctrl; /* 0x154 */
+ u32 spi_clk_ctrl; /* 0x158 */
+ u32 can_clk_ctrl; /* 0x15c */
+ u32 can_mioclk_ctrl; /* 0x160 */
+ u32 dbg_clk_ctrl; /* 0x164 */
+ u32 pcap_clk_ctrl; /* 0x168 */
+ u32 reserved0_4[1];
+ u32 fpga0_clk_ctrl; /* 0x170 */
+ u32 reserved0_5[3];
+ u32 fpga1_clk_ctrl; /* 0x180 */
+ u32 reserved0_6[3];
+ u32 fpga2_clk_ctrl; /* 0x190 */
+ u32 reserved0_7[3];
+ u32 fpga3_clk_ctrl; /* 0x1a0 */
+ u32 reserved0_8[8];
+ u32 clk_621_true; /* 0x1c4 */
+ u32 reserved1[14];
u32 pss_rst_ctrl; /* 0x200 */
u32 reserved2[15];
u32 fpga_rst_ctrl; /* 0x240 */
--- /dev/null
+/*
+ * (C) Copyright 2014 Xilinx, Inc. Michal Simek
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _ASM_ARCH_SPL_H_
+#define _ASM_ARCH_SPL_H_
+
+extern void ps7_init(void);
+
+#define BOOT_DEVICE_NONE 0
+#define BOOT_DEVICE_RAM 1
+#define BOOT_DEVICE_SPI 2
+#define BOOT_DEVICE_MMC1 3
+#define BOOT_DEVICE_MMC2 4
+#define BOOT_DEVICE_MMC2_2 5
+
+#endif
extern void zynq_slcr_lock(void);
extern void zynq_slcr_unlock(void);
extern void zynq_slcr_cpu_reset(void);
-extern void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk);
+extern void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate);
extern void zynq_slcr_devcfg_disable(void);
extern void zynq_slcr_devcfg_enable(void);
extern u32 zynq_slcr_get_boot_mode(void);
unsigned long tbl;
unsigned long lastinc;
unsigned long long timer_reset_value;
-#ifdef CONFIG_IXP425
- unsigned long timestamp;
-#endif
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
unsigned long tlb_addr;
unsigned long tlb_size;
--- /dev/null
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* This API file is loosely based on u-boot/drivers/video/ipu.h and linux */
+
+#ifndef __KONA_COMMON_CLK_H
+#define __KONA_COMMON_CLK_H
+
+#include <linux/types.h>
+
+struct clk;
+
+/* Only implement required functions for your specific architecture */
+int clk_init(void);
+struct clk *clk_get(const char *id);
+int clk_enable(struct clk *clk);
+void clk_disable(struct clk *clk);
+unsigned long clk_get_rate(struct clk *clk);
+long clk_round_rate(struct clk *clk, unsigned long rate);
+int clk_set_rate(struct clk *clk, unsigned long rate);
+int clk_set_parent(struct clk *clk, struct clk *parent);
+struct clk *clk_get_parent(struct clk *clk);
+int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep);
+int clk_bsc_enable(void *base);
+
+#endif
--- /dev/null
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __KONA_SDHCI_H
+#define __KONA_SDHCI_H
+
+int kona_sdhci_init(int dev_index, u32 min_clk, u32 quirks);
+
+#endif
ifndef CONFIG_SYS_GENERIC_BOARD
obj-y += board.o
endif
-obj-y += sections.o
obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-$(CONFIG_SPL_FRAMEWORK) += spl.o
endif
+obj-y += sections.o
ifdef CONFIG_ARM64
obj-y += interrupts_64.o
else
{
printf("\n\n%s\n\n", version_string);
debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
- _TEXT_BASE,
- _bss_start_ofs + _TEXT_BASE, _bss_end_ofs + _TEXT_BASE);
+ (ulong)&_start,
+ (ulong)&__bss_start, (ulong)&__bss_end);
#ifdef CONFIG_MODEM_SUPPORT
debug("Modem Support enabled\n");
#endif
*/
typedef int (init_fnc_t) (void);
-int print_cpuinfo(void);
-
void __dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
serial_init, /* serial communications setup */
console_init_f, /* stage 1 init of console */
display_banner, /* say that we are here */
-#if defined(CONFIG_DISPLAY_CPUINFO)
print_cpuinfo, /* display cpu info (and speed) */
-#endif
#if defined(CONFIG_DISPLAY_BOARDINFO)
checkboard, /* display board info */
#endif
memset((void *)gd, 0, sizeof(gd_t));
- gd->mon_len = _bss_end_ofs;
+ gd->mon_len = (ulong)&__bss_end - (ulong)_start;
#ifdef CONFIG_OF_EMBED
/* Get a pointer to the FDT */
- gd->fdt_blob = _binary_dt_dtb_start;
+ gd->fdt_blob = __dtb_db_begin;
#elif defined CONFIG_OF_SEPARATE
/* FDT is at end of image */
- gd->fdt_blob = (void *)(_end_ofs + _TEXT_BASE);
+ gd->fdt_blob = &_end;
#endif
/* Allow the early environment to override the fdt address */
gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16,
gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
#endif
- addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size;
+ addr = CONFIG_SYS_SDRAM_BASE + get_effective_memsize();
#ifdef CONFIG_LOGBUFFER
#ifndef CONFIG_ALT_LB_ADDR
gd->relocaddr = addr;
gd->start_addr_sp = addr_sp;
- gd->reloc_off = addr - _TEXT_BASE;
+ gd->reloc_off = addr - (ulong)&_start;
debug("relocation Offset is: %08lx\n", gd->reloc_off);
if (new_fdt) {
memcpy(new_fdt, gd->fdt_blob, fdt_size);
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_R, "board_init_r");
- monitor_flash_len = _end_ofs;
+ monitor_flash_len = (ulong)&__rel_dyn_end - (ulong)_start;
/* Enable caches */
enable_caches();
void do_data_abort (struct pt_regs *pt_regs)
{
- printf ("data abort\n\n MAYBE you should read doc/README.arm-unaligned-accesses\n\n");
+ printf ("data abort\n");
show_regs (pt_regs);
bad_mode ();
}
char __image_copy_end[0] __attribute__((section(".__image_copy_end")));
char __rel_dyn_start[0] __attribute__((section(".__rel_dyn_start")));
char __rel_dyn_end[0] __attribute__((section(".__rel_dyn_end")));
+char _end[0] __attribute__((section(".__end")));
ifeq ($(CONFIG_BFIN_CPU),)
CONFIG_BFIN_CPU := \
$(shell awk '$$2 == "CONFIG_BFIN_CPU" { print $$3 }' \
- $(src)include/configs/$(BOARD).h)
+ $(srctree)/include/configs/$(BOARD).h)
else
CONFIG_BFIN_CPU := $(strip $(CONFIG_BFIN_CPU:"%"=%))
endif
PLATFORM_RELFLAGS += -mcpu=$(CONFIG_BFIN_CPU)
ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS)
-ALL-y += $(obj)u-boot.ldr
+ALL-y += u-boot.ldr
endif
ifeq ($(CONFIG_ENV_IS_EMBEDDED_IN_LDR),y)
-CREATE_LDR_ENV = $(obj)tools/envcrc --binary > $(obj)env-ldr.o
+CREATE_LDR_ENV = tools/envcrc --binary > env-ldr.o
HOSTCFLAGS_NOPED_ADSP := \
$(shell $(CPP) -dD - -mcpu=$(CONFIG_BFIN_CPU) </dev/null \
| awk '$$2 ~ /ADSP/ { print "-D" $$2 }')
LDR_FLAGS += --bmode $(subst BFIN_BOOT_,,$(CONFIG_BFIN_BOOT_MODE))
LDR_FLAGS += --use-vmas
-LDR_FLAGS += --initcode $(obj)$(CPUDIR)/initcode.o
+LDR_FLAGS += --initcode $(CPUDIR)/initcode.o
ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_UART)
LDR_FLAGS-$(CONFIG_ENV_IS_EMBEDDED_IN_LDR) += \
- --punchit $$(($(CONFIG_ENV_OFFSET))):$$(($(CONFIG_ENV_SIZE))):$(obj)env-ldr.o
+ --punchit $$(($(CONFIG_ENV_OFFSET))):$$(($(CONFIG_ENV_SIZE))):env-ldr.o
endif
ifneq (,$(findstring s,$(MAKEFLAGS)))
LDR_FLAGS += --quiet
obj-y += traps.o
extra-y += check_initcode
+clean-files := init.lds
# make sure our initcode (which goes into LDR) does not
# have relocs or external references
-$(obj)initcode.o: CFLAGS += -fno-function-sections -fno-data-sections
+CFLAGS_REMOVE_initcode.o := -ffunction-sections -fdata-sections
READINIT = env LC_ALL=C $(CROSS_COMPILE)readelf -s $<
-$(obj)check_initcode: $(obj)initcode.o
+$(obj)/check_initcode: $(obj)/initcode.o
ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS)
@if $(READINIT) | grep '\<GLOBAL\>.*\<UND\>' ; then \
echo "$< contains external references!" 1>&2 ; \
fi
endif
-$(obj)init.lds: init.lds.S
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P $^ -o $@
-$(obj)init.elf: $(obj)init.lds $(obj)init.o $(obj)initcode.o
- $(LD) $(LDFLAGS) -T $^ -o $@
+CPPFLAGS_init.lds := -ansi
+
+quiet_cmd_link_init = LD $@
+ cmd_link_init = $(LD) $(LDFLAGS) -T $^ -o $@
+$(obj)/init.elf: $(obj)/init.lds $(obj)/init.o $(obj)/initcode.o
+ $(call if_changed,link_init)
+targets += init.lds init.o
serial_putc('a');
-#ifdef __ADSPBF60x__
+#ifndef __ADSPBF60x__
/* Program the async banks controller. */
#ifdef EBIU_AMGCTL
bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL);
serial_putc('c');
-#else /* __ADSPBF60x__ */
+#else /* __ADSPBF60x__ */
/* Program the static memory controller. */
# ifdef CONFIG_SMC_GCTL_VAL
bfin_write_SMC_GCTL(CONFIG_SMC_GCTL_VAL);
bfin_write_SMC_B3ETIM(CONFIG_SMC_B3ETIM_VAL);
# endif
-#endif
+#endif /* __ADSPBF60x__ */
serial_putc('d');
}
call _memcpy_ASM;
#endif
+.Lnorelocate:
/* Initialize BSS section ... we know that memset() does not
* use the BSS, so it is safe to call here. The bootrom LDR
* takes care of clearing things for us.
r2.h = __bss_len;
call _memset;
-.Lnorelocate:
/* Setup the actual stack in external memory */
sp.h = HI(CONFIG_STACKBASE);
# include <linux/types.h>
-extern u_long get_vco(void);
-extern u_long get_cclk(void);
-extern u_long get_sclk(void);
-extern u_long get_sclk0(void);
-extern u_long get_sclk1(void);
-extern u_long get_dclk(void);
-
# define bfin_revid() (bfin_read_CHIPID() >> 28)
extern int bfin_os_log_check(void);
return uclk;
}
+extern u_long get_vco(void);
+extern u_long get_cclk(void);
+extern u_long get_sclk(void);
+
#ifdef CGU_DIV
+extern u_long get_sclk0(void);
+extern u_long get_sclk1(void);
+extern u_long get_dclk(void);
# define get_uart_clk get_sclk0
+# define get_i2c_clk get_sclk0
+# define get_spi_clk get_sclk0
#else
# define get_uart_clk get_sclk
+# define get_i2c_clk get_sclk
+# define get_spi_clk get_sclk
#endif
#endif
#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
+/*default value for EMAC_VLANx reg*/
+#define EMAC_VLANX_DEF_VAL 0xFFFF
+
#endif
--- /dev/null
+/*
+ * i2c.c - driver for Blackfin on-chip TWI/I2C
+ *
+ * Copyright (c) 2006-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __ARCH_TWI_H
+#define __ARCH_TWI_H
+
+#include <asm/blackfin.h>
+#include <asm/mach-common/bits/twi.h>
+
+#endif
# SPDX-License-Identifier: GPL-2.0+
#
-CFLAGS += -DBFIN_BOARD_NAME='"$(BOARD)"'
+# Unnecessary.
+# Use CONFIG_SYS_BOARD instead of BFIN_BOARD_NAME
+# and delete this.
+ccflags-y += -DBFIN_BOARD_NAME='"$(BOARD)"'
obj-y += ins.o
obj-y += memcmp.o
#include <asm/cplb.h>
#include <asm/mach-common/bits/mpu.h>
+#include <asm/clock.h>
#include <kgdb.h>
#ifdef CONFIG_CMD_NAND
++i;
#if defined(__ADSPBF60x__)
icplb_add(0x0, 0x0);
- dcplb_add(CONFIG_SYS_FLASH_BASE, SDRAM_EBIU);
+ dcplb_add(CONFIG_SYS_FLASH_BASE, PAGE_SIZE_16MB | CPLB_DIRTY |
+ CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID);
++i;
#endif
# SPDX-License-Identifier: GPL-2.0+
#
-# CFLAGS += -DET_DEBUG
+# ccflags-y += -DET_DEBUG
extra-y = start.o
obj-y = cpu.o speed.o cpu_init.o interrupts.o
# SPDX-License-Identifier: GPL-2.0+
#
-# CFLAGS += -DET_DEBUG
+# ccflags-y += -DET_DEBUG
extra-y = start.o
obj-y = cpu.o speed.o cpu_init.o interrupts.o
# SPDX-License-Identifier: GPL-2.0+
#
-# CFLAGS += -DET_DEBUG
+# ccflags-y += -DET_DEBUG
extra-y = start.o
obj-y = interrupts.o cpu.o speed.o cpu_init.o
# SPDX-License-Identifier: GPL-2.0+
#
-# CFLAGS += -DET_DEBUG
+# ccflags-y += -DET_DEBUG
extra-y := start.o
obj-y = cpu.o speed.o cpu_init.o interrupts.o
# SPDX-License-Identifier: GPL-2.0+
#
-# CFLAGS += -DET_DEBUG
+# ccflags-y += -DET_DEBUG
extra-y = start.o
obj-y = cpu.o speed.o cpu_init.o interrupts.o pci.o
# SPDX-License-Identifier: GPL-2.0+
#
-# CFLAGS += -DET_DEBUG
+# ccflags-y += -DET_DEBUG
extra-y = start.o
obj-y = cpu.o speed.o cpu_init.o pci.o interrupts.o slicetimer.o
extra-y = start.o
obj-y = irq.o
obj-y += cpu.o interrupts.o cache.o exception.o timer.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
puts ("Divide by zero exception\n");
break;
#ifdef MICROBLAZE_V5
+ case 0x7:
+ puts("Priviledged or stack protection violation exception\n");
+ break;
case 0x1000:
puts ("Exception in delay slot\n");
break;
--- /dev/null
+/*
+ * (C) Copyright 2013 - 2014 Xilinx, Inc
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <image.h>
+#include <spl.h>
+#include <version.h>
+#include <asm/io.h>
+#include <asm/u-boot.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+bool boot_linux;
+
+u32 spl_boot_device(void)
+{
+ return BOOT_DEVICE_NOR;
+}
+
+/* Board initialization after bss clearance */
+void spl_board_init(void)
+{
+ gd = (gd_t *)CONFIG_SPL_STACK_ADDR;
+
+ /* enable console uart printing */
+ preloader_console_init();
+}
+
+#ifdef CONFIG_SPL_OS_BOOT
+void __noreturn jump_to_image_linux(void *arg)
+{
+ debug("Entering kernel arg pointer: 0x%p\n", arg);
+ typedef void (*image_entry_arg_t)(char *, ulong, ulong)
+ __attribute__ ((noreturn));
+ image_entry_arg_t image_entry =
+ (image_entry_arg_t)spl_image.entry_point;
+
+ image_entry(NULL, 0, (ulong)arg);
+}
+#endif /* CONFIG_SPL_OS_BOOT */
+
+int spl_start_uboot(void)
+{
+#ifdef CONFIG_SPL_OS_BOOT
+ if (boot_linux)
+ return 0;
+#endif
+
+ return 1;
+}
*/
mts rmsr, r0 /* disable cache */
+
+#if defined(CONFIG_SPL_BUILD)
+ addi r1, r0, CONFIG_SPL_STACK_ADDR
+ addi r1, r1, -4 /* Decrement SP to top of memory */
+#else
addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET
addi r1, r1, -4 /* Decrement SP to top of memory */
sh r7, r0, r8
rsubi r8, r10, 0x26
sh r6, r0, r8
+#endif /* BUILD_SPL */
/* Flush cache before enable cache */
addik r5, r0, 0
cmp r6, r5, r4 /* check if we have reach the end */
bnei r6, 2b
3: /* jumping to board_init */
+#ifndef CONFIG_SPL_BUILD
brai board_init_f
+#else
+ brai board_init_r
+#endif
1: bri 1b
+#ifndef CONFIG_SPL_BUILD
/*
* Read 16bit little endian
*/
rtsd r15, 8
or r0, r0, r0
.end out16
+#endif
}
}
+#ifndef CONFIG_SPL_BUILD
static void timer_isr(void *arg)
{
timestamp++;
if (ret)
tmr = NULL;
}
-
/* No problem if timer is not found/initialized */
return 0;
}
+#else
+int timer_init(void)
+{
+ return 0;
+}
+#endif
/*
* This function is derived from PowerPC code (read timebase as long long).
--- /dev/null
+/*
+ * (C) Copyright 2013 - 2014 Xilinx, Inc
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+
+OUTPUT_ARCH(microblaze)
+ENTRY(_start)
+
+SECTIONS
+{
+ .text ALIGN(0x4):
+ {
+ __text_start = .;
+ arch/microblaze/cpu/start.o (.text)
+ *(.text)
+ *(.text.*)
+ __text_end = .;
+ }
+
+ .rodata ALIGN(0x4):
+ {
+ __rodata_start = .;
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ __rodata_end = .;
+ }
+
+ .data ALIGN(0x4):
+ {
+ __data_start = .;
+ *(.data)
+ *(.data.*)
+ __data_end = .;
+ }
+
+ .bss ALIGN(0x4):
+ {
+ __bss_start = .;
+ *(.sbss)
+ *(.scommon)
+ *(.bss)
+ *(.bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end = .;
+ }
+ __end = . ;
+}
+
+#if defined(CONFIG_SPL_MAX_FOOTPRINT)
+ASSERT(__end - _start < (CONFIG_SPL_MAX_FOOTPRINT), \
+ "SPL image plus BSS too big");
+#endif
--- /dev/null
+dtb-y += microblaze-generic.dtb
+
+targets += $(dtb-y)
+
+DTC_FLAGS += -R 4 -p 0x1000
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+ @:
+
+clean-files := *.dtb
--- /dev/null
+/*
+ * (C) Copyright 2013 - 2014 Xilinx, Inc
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_MICROBLAZE_SPL_H_
+#define _ASM_MICROBLAZE_SPL_H_
+
+#define BOOT_DEVICE_RAM 1
+#define BOOT_DEVICE_NOR 2
+#define BOOT_DEVICE_SPI 3
+
+#endif
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
unsigned int bi_baudrate; /* Console Baudrate */
+ ulong bi_boot_params; /* where this board expects params */
} bd_t;
/* For image.h:image_check_target_arch() */
DECLARE_GLOBAL_DATA_PTR;
+static int display_banner(void)
+{
+ printf("\n\n%s\n\n", version_string);
+ return 0;
+}
+
/*
* All attempts to come up with a "common" initialization sequence
* that works for all boards and architectures failed: some of the
fdtdec_check_fdt,
#endif
serial_init,
+#ifndef CONFIG_SPL_BUILD
console_init_f,
+#endif
+ display_banner,
+#ifndef CONFIG_SPL_BUILD
interrupts_init,
timer_init,
+#endif
NULL,
};
gd = (gd_t *)(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET);
bd = (bd_t *)(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET
- GENERATED_BD_INFO_SIZE);
-#if defined(CONFIG_CMD_FLASH)
+#if defined(CONFIG_CMD_FLASH) && !defined(CONFIG_SPL_BUILD)
ulong flash_size = 0;
#endif
asm ("nop"); /* FIXME gd is not initialize - wait */
#ifdef CONFIG_OF_EMBED
/* Get a pointer to the FDT */
- gd->fdt_blob = _binary_dt_dtb_start;
+ gd->fdt_blob = __dtb_dt_begin;
#elif defined CONFIG_OF_SEPARATE
/* FDT is at end of image */
gd->fdt_blob = (void *)__end;
#endif
+
+#ifndef CONFIG_SPL_BUILD
/* Allow the early environment to override the fdt address */
gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16,
(uintptr_t)gd->fdt_blob);
+#endif
/*
* The Malloc area is immediately below the monitor copy in DRAM
hang();
}
+#ifndef CONFIG_SPL_BUILD
#ifdef CONFIG_OF_CONTROL
/* For now, put this check after the console is ready */
if (fdtdec_prepare_fdt())
WATCHDOG_RESET();
main_loop();
}
+#endif /* CONFIG_SPL_BUILD */
}
PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib $(ENDIANNESS)
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
LDFLAGS_FINAL += --gc-sections -pie
-OBJCFLAGS += --remove-section=.dynsym
+OBJCOPYFLAGS += --remove-section=.dynsym
PLATFORM_LDFLAGS += -m elf32ltsmip
endif
-CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds
+CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T $(srctree)/$(src)/mips.lds
PLATFORM_LDFLAGS += -m elf64ltsmip
endif
-CONFIG_STANDALONE_LOAD_ADDR ?= 0xffffffff80200000 -T mips64.lds
+CONFIG_STANDALONE_LOAD_ADDR ?= 0xffffffff80200000 -T $(srctree)/$(src)/mips64.lds
PLATFORM_LDFLAGS += -m elf32ltsmip
endif
-CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds
+CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T $(srctree)/$(src)/mips.lds
CROSS_COMPILE ?= nds32le-linux-
-CONFIG_STANDALONE_LOAD_ADDR = 0x300000 -T nds32.lds
+CONFIG_STANDALONE_LOAD_ADDR = 0x300000 -T $(srctree)/$(src)/nds32.lds
PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -mrelax
PLATFORM_RELFLAGS += -gdwarf-2
# SPDX-License-Identifier: GPL-2.0+
#
+# necessary to create built-in.o
+obj- := __dummy__.o
+
extra-y = start.o
#endif
BLANK();
#ifdef CONFIG_FTAHBC020S
+ OFFSET(FTAHBC020S_SLAVE_BSR_4, ftahbc02s, s_bsr[4]);
OFFSET(FTAHBC020S_SLAVE_BSR_6, ftahbc02s, s_bsr[6]);
OFFSET(FTAHBC020S_CR, ftahbc02s, cr);
#endif
#define SDMC_B0_BSR_D CONFIG_SYS_FTSDMC021_BANK0_BSR
#define SDMC_B1_BSR_D CONFIG_SYS_FTSDMC021_BANK1_BSR
+
+/*
+ * for Orca and Emerald
+ */
+#define BOARD_ID_REG 0x104
+#define BOARD_ID_FAMILY_MASK 0xfff000
+#define BOARD_ID_FAMILY_V5 0x556000
+#define BOARD_ID_FAMILY_K7 0x74b000
+
/*
* parameters for the static memory controller
*/
#define AHBC_CR_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR)
#define AHBC_BSR6_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6)
+/*
+ * for Orca and Emerald
+ */
+#define AHBC_BSR4_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_4)
#define AHBC_BSR6_D CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
/*
* we need to set onboard SDRAM before remap and relocation.
*/
led 0x01
- write32 SMC_BANK0_CR_A, SMC_BANK0_CR_D ! 0x10000052
- write32 SMC_BANK0_TPR_A, SMC_BANK0_TPR_D ! 0x00151151
+
+ /*
+ * for Orca and Emerald
+ * disable write protection and reset bank size
+ */
+ li $r0, SMC_BANK0_CR_A
+ lwi $r1, [$r0+#0x00]
+ ori $r1, $r1, 0x8f0
+ xori $r1, $r1, 0x8f0
+ /*
+ * check board
+ */
+ li $r3, CONFIG_FTPMU010_BASE + BOARD_ID_REG
+ lwi $r3, [$r3]
+ li $r4, BOARD_ID_FAMILY_MASK
+ and $r3, $r3, $r4
+ li $r4, BOARD_ID_FAMILY_K7
+ xor $r4, $r3, $r4
+ beqz $r4, use_flash_16bit_boot
+ /*
+ * 32-bit mode
+ */
+use_flash_32bit_boot:
+ ori $r1, $r1, 0x50
+ li $r2, 0x00151151
+ j sdram_b0_cr
+ /*
+ * 16-bit mode
+ */
+use_flash_16bit_boot:
+ ori $r1, $r1, 0x60
+ li $r2, 0x00153153
+ /*
+ * SRAM bank0 config
+ */
+sdram_b0_cr:
+ swi $r1, [$r0+#0x00]
+ swi $r2, [$r0+#0x04]
/*
* config AHB Controller
*/
led 0x02
- write32 AHBC_BSR6_A, AHBC_BSR6_D
/*
* config PMU controller
* a FLASH connected to bank0.
*/
led 0x11
- li $r4, PHYS_SDRAM_0_AT_INIT /* 0x10000000 */
+ /*
+ * for Orca and Emerald
+ * read sdram base address automatically
+ */
+ li $r5, AHBC_BSR6_A
+ lwi $r8, [$r5]
+ li $r4, 0xfff00000
+ and $r4, $r4, $r8
+
+
li $r5, 0x0
la $r1, relo_base /* get $pc or $lp */
sub $r2, $r0, $r1
write32 SDMC_B1_BSR_A, 0x00001040
setbf15 AHBC_CR_A, FTAHBC020S_CR_REMAP ! 0x1
+ /*
+ * for Orca and Emerald
+ * extend sdram size from 256MB to 2GB
+ */
+ li $r5, AHBC_BSR6_A
+ lwi $r6, [$r5]
+ li $r4, 0xfff0ffff
+ and $r6 ,$r4 , $r6
+ li $r4, 0x000b0000
+ or $r6, $r4, $r6
+ swi $r6, [$r5]
+
+ /*
+ * for Orca and Emerald
+ * extend rom base from 256MB to 2GB
+ */
+ li $r4, AHBC_BSR4_A
+ lwi $r5, [$r4]
+ li $r6, 0xffffff
+ and $r5, $r5, $r6
+ li $r6, 0x80000000
+ or $r5, $r5, $r6
+ swi $r5, [$r4]
#endif /* #ifdef CONFIG_MEM_REMAP */
move $lp, $r11
2:
* amount of memory on the system if we're unable to keep all
* the memory mapped in.
*/
-extern ulong get_effective_memsize(void);
#define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize())
/*
[XFI_FM2_MAC9] = "XFI_FM2_MAC9",
[XFI_FM2_MAC10] = "XFI_FM2_MAC10",
[INTERLAKEN] = "INTERLAKEN",
+ [QSGMII_SW1_A] = "QSGMII_SW1_A",
+ [QSGMII_SW1_B] = "QSGMII_SW1_B",
};
#endif
sys_info->freq_processor[cpu] =
freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
}
-#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_T2080)
+#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_T2080) || \
+ defined(CONFIG_PPC_T2081)
#define FM1_CLK_SEL 0xe0000000
#define FM1_CLK_SHIFT 29
#else
SET_QP_INFO(8, 34, 1, 3),
SET_QP_INFO(9, 35, 1, 0),
SET_QP_INFO(10, 36, 1, 0),
- SET_QP_INFO(11, 37, 1, 1),
- SET_QP_INFO(12, 38, 1, 1),
- SET_QP_INFO(13, 39, 1, 2),
- SET_QP_INFO(14, 40, 1, 2),
- SET_QP_INFO(15, 41, 1, 3),
- SET_QP_INFO(16, 42, 1, 3),
- SET_QP_INFO(17, 43, 1, 0),
- SET_QP_INFO(18, 44, 1, 0),
- SET_QP_INFO(19, 45, 1, 1),
- SET_QP_INFO(20, 46, 1, 1),
- SET_QP_INFO(21, 47, 1, 2),
- SET_QP_INFO(22, 48, 1, 2),
- SET_QP_INFO(23, 49, 1, 3),
- SET_QP_INFO(24, 50, 1, 3),
- SET_QP_INFO(25, 51, 1, 0),
};
#endif
SET_DMA_LIODN(1, 147),
SET_DMA_LIODN(2, 227),
- SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
- SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
- SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
- SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
-
/* SET_NEXUS_LIODN(557), -- not yet implemented */
};
int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
SET_FMAN_RX_1G_LIODN(1, 3, 91),
SET_FMAN_RX_1G_LIODN(1, 4, 92),
SET_FMAN_RX_1G_LIODN(1, 5, 93),
- SET_FMAN_RX_10G_LIODN(1, 0, 94),
- SET_FMAN_RX_10G_LIODN(1, 1, 95),
};
int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
#endif
};
int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
-#ifdef CONFIG_SYS_DPAA_RMAN
-struct liodn_id_table rman_liodn_tbl[] = {
- /* Set RMan block 0-3 liodn offset */
- SET_RMAN_LIODN(0, 678),
- SET_RMAN_LIODN(1, 679),
- SET_RMAN_LIODN(2, 680),
- SET_RMAN_LIODN(3, 681),
-};
-int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl);
-#endif
-
struct liodn_id_table liodn_bases[] = {
[FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(462, 558),
#ifdef CONFIG_SYS_DPAA_FMAN
[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973),
#endif
-#ifdef CONFIG_SYS_DPAA_RMAN
- [FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(922),
-#endif
};
#include <asm/fsl_serdes.h>
#include <asm/processor.h>
#include <asm/io.h>
-#include "fsl_corenet2_serdes.h"
-static u8 serdes_cfg_tbl[MAX_SERDES][0xC4][SRDS_MAX_LANES] = {
- { /* SerDes 1 */
- [0x69] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
- PCIE2, PCIE3, SGMII_FM1_DTSEC4, SATA1},
+
+static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
+ [0x00] = {PCIE1, PCIE1, PCIE1, PCIE1,
+ PCIE2, PCIE2, PCIE2, PCIE2},
+ [0x06] = {PCIE1, PCIE1, PCIE1, PCIE1,
+ PCIE2, PCIE3, PCIE4, SATA1},
+ [0x08] = {PCIE1, PCIE1, PCIE1, PCIE1,
+ PCIE2, PCIE3, SATA2, SATA1},
+ [0x40] = {PCIE1, PCIE1, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ PCIE2, PCIE2, PCIE2, PCIE2},
+ [0x60] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
+ PCIE2, PCIE2, PCIE2, PCIE2},
[0x66] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
PCIE2, PCIE3, PCIE4, SATA1},
[0x67] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
- [0x60] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
- PCIE2, PCIE2, PCIE2, PCIE2},
- [0x8D] = {PCIE1, SGMII_SW1_DTSEC3, SGMII_SW1_DTSEC1, SGMII_SW1_DTSEC2,
- PCIE2, SGMII_SW1_DTSEC6, SGMII_SW1_DTSEC4, SGMII_SW1_DTSEC5},
- [0x89] = {PCIE1, SGMII_SW1_DTSEC3, SGMII_SW1_DTSEC1, SGMII_SW1_DTSEC2,
- PCIE2, PCIE3, SGMII_SW1_DTSEC4, SATA1},
+ [0x69] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
+ PCIE2, PCIE3, SGMII_FM1_DTSEC4, SATA1},
[0x86] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
PCIE2, PCIE3, PCIE4, SATA1},
+ [0x85] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
[0x87] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
- [0xA7] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
- [0xAA] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- PCIE2, PCIE3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
- [0x40] = {PCIE1, PCIE1, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- PCIE2, PCIE2, PCIE2, PCIE2},
- [0x06] = {PCIE1, PCIE1, PCIE1, PCIE1,
- PCIE2, PCIE3, PCIE4, SATA1},
- [0x08] = {PCIE1, PCIE1, PCIE1, PCIE1,
- PCIE2, PCIE3, SATA2, SATA1},
+ [0x89] = {PCIE1, QSGMII_SW1_A, QSGMII_SW1_A, QSGMII_SW1_A,
+ PCIE2, PCIE3, QSGMII_SW1_B, SATA1},
+ [0x8D] = {PCIE1, QSGMII_SW1_A, QSGMII_SW1_A, QSGMII_SW1_A,
+ PCIE2, QSGMII_SW1_B, QSGMII_SW1_B, QSGMII_SW1_B},
[0x8F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
AURORA, NONE, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
- [0x85] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
[0xA5] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
- [0x00] = {PCIE1, PCIE1, PCIE1, PCIE1,
- PCIE2, PCIE2, PCIE2, PCIE2},
- },
- {
- },
- {
- },
- {
- },
+ [0xA7] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
+ [0xAA] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ PCIE2, PCIE3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
};
-
enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
{
- return serdes_cfg_tbl[serdes][cfg][lane];
+ return serdes_cfg_tbl[cfg][lane];
}
int is_serdes_prtcl_valid(int serdes, u32 prtcl)
{
int i;
- if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl[serdes]))
+ if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
return 0;
for (i = 0; i < SRDS_MAX_LANES; i++) {
- if (serdes_cfg_tbl[serdes][prtcl][i] != NONE)
+ if (serdes_cfg_tbl[prtcl][i] != NONE)
return 1;
}
SET_USB_LIODN(1, "fsl-usb2-mph", 553),
SET_USB_LIODN(2, "fsl-usb2-dr", 554),
+#ifdef CONFIG_FSL_SATA_V2
SET_SATA_LIODN(1, 555),
SET_SATA_LIODN(2, 556),
+#endif
SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228),
{0x6C, {XFI_FM1_MAC9, XFI_FM1_MAC10,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
PCIE4, PCIE4, PCIE4, PCIE4} },
-#if defined(CONFIG_PPC_T2080)
{0x1C, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
XFI_FM1_MAC1, XFI_FM1_MAC2,
PCIE4, PCIE4, PCIE4, PCIE4} },
-#elif defined(CONFIG_PPC_T2081)
+#if defined(CONFIG_PPC_T2081)
{0xAA, {PCIE3, PCIE3, PCIE3, PCIE3,
PCIE4, PCIE4, PCIE4, PCIE4} },
{0xCA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
* amount of memory on the system if we're unable to keep all
* the memory mapped in.
*/
-extern ulong get_effective_memsize(void);
#define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize())
static __inline__ void set_tsr(unsigned long val)
* amount of memory on the system if we're unable to keep all
* the memory mapped in.
*/
-extern ulong get_effective_memsize(void);
#define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize())
/*
# SPDX-License-Identifier: GPL-2.0+
#
-# CFLAGS += -DET_DEBUG
+# ccflags-y += -DET_DEBUG
extra-y += start.o
extra-y += traps.o
#define FSL_DDR_VER_4_7 47
#define FSL_DDR_VER_5_0 50
+/* IP endianness */
+#define CONFIG_SYS_FSL_IFC_BE
+
/* Number of TLB CAM entries we have on FSL Book-E chips */
#if defined(CONFIG_E500MC)
#define CONFIG_SYS_NUM_TLBCAMS 64
#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
#define CONFIG_SYS_FSL_TBCLK_DIV 16
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
-#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
-#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
XFI_FM2_MAC9,
XFI_FM2_MAC10,
INTERLAKEN,
- SGMII_SW1_DTSEC1, /* SW indicates on L2 switch */
- SGMII_SW1_DTSEC2,
- SGMII_SW1_DTSEC3,
- SGMII_SW1_DTSEC4,
- SGMII_SW1_DTSEC5,
- SGMII_SW1_DTSEC6,
- QSGMII_SW1_A, /* SW indicates on L2 swtich */
+ QSGMII_SW1_A, /* Indicates ports on L2 Switch */
QSGMII_SW1_B,
};
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17
+#define FSL_CORENET_RCWSR13_EC1 0x30000000 /* bits 418..419 */
+#define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII 0x00000000
+#define FSL_CORENET_RCWSR13_EC1_FM1_GPIO 0x10000000
+#define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII 0x20000000
+#define FSL_CORENET_RCWSR13_EC2 0x0c000000 /* bits 420..421 */
+#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
+#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
+#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII 0x20000000
+#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL 0x00000080
+#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH 0x00000000
+#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x80000000
#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
# Workaround for local bus unaligned access problems
# on MPC512x and MPC5200
ifdef CONFIG_MPC512X
-$(obj)ppcstring.o: AFLAGS += -Dmemcpy=__memcpy
+AFLAGS_ppcstring.o += -Dmemcpy=__memcpy
obj-y += memcpy_mpc5200.o
endif
ifdef CONFIG_MPC5200
-$(obj)ppcstring.o: AFLAGS += -Dmemcpy=__memcpy
+AFLAGS_ppcstring.o += -Dmemcpy=__memcpy
obj-y += memcpy_mpc5200.o
endif
endif
NULL, /* Terminate this list */
};
-ulong get_effective_memsize(void)
-{
-#ifndef CONFIG_VERY_BIG_RAM
- return gd->ram_size;
-#else
- /* limit stack to what we can reasonable map */
- return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
- CONFIG_MAX_MEM_MAPPED : gd->ram_size);
-#endif
-}
-
static int __fixup_cpu(void)
{
return 0;
* initialized, and stack space is limited to a few kB.
*/
-#ifdef CONFIG_LOGBUFFER
-unsigned long logbuffer_base(void)
-{
- return CONFIG_SYS_SDRAM_BASE + get_effective_memsize() - LOGBUFF_LEN;
-}
-#endif
-
void board_init_f(ulong bootflag)
{
bd_t *bd;
DECLARE_GLOBAL_DATA_PTR;
-extern ulong get_effective_memsize(void);
static ulong get_sp (void);
extern void ft_fixup_num_cores(void *blob);
static void set_clocks_in_mhz (bd_t *kbd);
# Support generic board on sandbox
__HAVE_ARCH_GENERIC_BOARD := y
+
+cmd_u-boot__ = $(CC) -o $@ -T u-boot.lds \
+ -Wl,--start-group $(u-boot-main) -Wl,--end-group \
+ $(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map
obj-y := cpu.o os.o start.o state.o
# os.c is build in the system environment, so needs standard includes
-$(obj)os.o: ALL_CFLAGS := $(BASE_CPPFLAGS) \
- $(patsubst %, -idirafter %, $(BASE_INCLUDE_DIRS))
-$(obj).depend.os: CPPFLAGS := $(BASE_CPPFLAGS) \
- $(patsubst %, -idirafter %, $(BASE_INCLUDE_DIRS))
+# CFLAGS_REMOVE_os.o cannot be used to drop header include path
+quiet_cmd_cc_os.o = CC $(quiet_modtag) $@
+cmd_cc_os.o = $(CC) $(filter-out -nostdinc, \
+ $(patsubst -I%,-idirafter%,$(c_flags))) -c -o $@ $<
+
+$(obj)/os.o: $(src)/os.c FORCE
+ $(call if_changed_dep,cc_os.o)
CROSS_COMPILE ?= sparc-elf-
-CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000 -L $(gcclibdir) -T sparc.lds
+CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000 -L $(gcclibdir) \
+ -T $(srctree)/$(src)/sparc.lds
PLATFORM_CPPFLAGS += -DCONFIG_SPARC -D__sparc__
--- /dev/null
+dtb-y += link.dtb \
+ alex.dtb
+
+targets += $(dtb-y)
+
+DTC_FLAGS += -R 4 -p 0x1000
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+ @:
+
+clean-files := *.dtb
LIBGCC := $(notdir $(NORMAL_LIBGCC))
extra-y := $(LIBGCC)
-$(obj)$(LIBGCC): $(NORMAL_LIBGCC)
+$(obj)/$(LIBGCC): $(NORMAL_LIBGCC)
$(OBJCOPY) $< $@ --prefix-symbols=__normal_
{
#ifdef CONFIG_OF_EMBED
/* Get a pointer to the FDT */
- gd->fdt_blob = _binary_dt_dtb_start;
+ gd->fdt_blob = __dtb_dt_begin;
#elif defined CONFIG_OF_SEPARATE
/* FDT is at end of image */
gd->fdt_blob = (ulong *)&_end;
} >.sram
__image_copy_end = .;
- _end = .;
+
+ .end :
+ {
+ *(.__end)
+ } >.sram
}
--- /dev/null
+/*
+ * bur_comon.h
+ *
+ * common board information header for B&R boards
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BUR_COMMON_H_
+#define _BUR_COMMON_H_
+
+void blink(u32 blinks, u32 intervall, u32 pin);
+void pmicsetup(u32 mpupll);
+void enable_uart0_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_board_pin_mux(void);
+int board_eth_init(bd_t *bis);
+
+#endif
--- /dev/null
+/*
+ * common.c
+ *
+ * common board functions for B&R boards
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <power/tps65217.h>
+#include "bur_common.h"
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+/* --------------------------------------------------------------------------*/
+void blink(u32 blinks, u32 intervall, u32 pin)
+{
+ gpio_direction_output(pin, 0);
+ int val = 0;
+
+ do {
+ val ^= 0x01;
+ gpio_set_value(pin, val);
+ mdelay(intervall);
+ } while (blinks--);
+
+ gpio_set_value(pin, 0);
+}
+#ifdef CONFIG_SPL_BUILD
+void pmicsetup(u32 mpupll)
+{
+ int mpu_vdd;
+ int usb_cur_lim;
+
+ /* setup I2C */
+ enable_i2c0_pin_mux();
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+
+ if (i2c_probe(TPS65217_CHIP_PM)) {
+ puts("PMIC (0x24) not found! skip further initalization.\n");
+ return;
+ }
+
+ /* Get the frequency which is defined by device fuses */
+ dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+ printf("detected max. frequency: %d - ", dpll_mpu_opp100.m);
+
+ if (0 != mpupll) {
+ dpll_mpu_opp100.m = MPUPLL_M_1000;
+ printf("retuning MPU-PLL to: %d MHz.\n", dpll_mpu_opp100.m);
+ } else {
+ puts("ok.\n");
+ }
+ /*
+ * Increase USB current limit to 1300mA or 1800mA and set
+ * the MPU voltage controller as needed.
+ */
+ if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
+ usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
+ mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
+ } else {
+ usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
+ mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
+ }
+
+ if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_POWER_PATH,
+ usb_cur_lim, TPS65217_USB_INPUT_CUR_LIMIT_MASK))
+ puts("tps65217_reg_write failure\n");
+
+ /* Set DCDC3 (CORE) voltage to 1.125V */
+ if (tps65217_voltage_update(TPS65217_DEFDCDC3,
+ TPS65217_DCDC_VOLT_SEL_1125MV)) {
+ puts("tps65217_voltage_update failure\n");
+ return;
+ }
+
+ /* Set CORE Frequencies to OPP100 */
+ do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+ /* Set DCDC2 (MPU) voltage */
+ if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
+ puts("tps65217_voltage_update failure\n");
+ return;
+ }
+
+ /* Set LDO3 to 1.8V */
+ if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+ TPS65217_DEFLS1,
+ TPS65217_LDO_VOLTAGE_OUT_1_8,
+ TPS65217_LDO_MASK))
+ puts("tps65217_reg_write failure\n");
+ /* Set LDO4 to 3.3V */
+ if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+ TPS65217_DEFLS2,
+ TPS65217_LDO_VOLTAGE_OUT_3_3,
+ TPS65217_LDO_MASK))
+ puts("tps65217_reg_write failure\n");
+
+ /* Set MPU Frequency to what we detected now that voltages are set */
+ do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+}
+
+void set_uart_mux_conf(void)
+{
+ enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+ enable_board_pin_mux();
+}
+
+#endif /* CONFIG_SPL_BUILD */
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static void cpsw_control(int enabled)
+{
+ /* VTP can be added here */
+ return;
+}
+
+/* describing port offsets of TI's CPSW block */
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_addr = 0,
+ },
+ {
+ .slave_reg_ofs = 0x308,
+ .sliver_reg_ofs = 0xdc0,
+ .phy_addr = 1,
+ },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 1,
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .bd_ram_ofs = 0x2000,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+#endif /* CONFIG_DRIVER_TI_CPSW, ... */
+
+#if defined(CONFIG_DRIVER_TI_CPSW)
+
+int board_eth_init(bd_t *bis)
+{
+ int rv = 0;
+ uint8_t mac_addr[6];
+ uint32_t mac_hi, mac_lo;
+
+ /* try reading mac address from efuse */
+ mac_lo = readl(&cdev->macid0l);
+ mac_hi = readl(&cdev->macid0h);
+ mac_addr[0] = mac_hi & 0xFF;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+ mac_addr[4] = mac_lo & 0xFF;
+ mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+ if (!getenv("ethaddr")) {
+ printf("<ethaddr> not set. Validating first E-fuse MAC ... ");
+
+ if (is_valid_ether_addr(mac_addr)) {
+ printf("using: %02X:%02X:%02X:%02X:%02X:%02X.\n",
+ mac_addr[0], mac_addr[1], mac_addr[2],
+ mac_addr[3], mac_addr[4], mac_addr[5]
+ );
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ }
+ }
+ writel(MII_MODE_ENABLE, &cdev->miisel);
+ cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII;
+ cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII;
+
+ rv = cpsw_register(&cpsw_data);
+ if (rv < 0) {
+ printf("Error %d registering CPSW switch\n", rv);
+ return 0;
+ }
+#endif /* CONFIG_DRIVER_TI_CPSW, ... */
+ return rv;
+}
+#endif /* CONFIG_DRIVER_TI_CPSW */
--- /dev/null
+#
+# Makefile
+#
+# Copyright (C) 2014 Hannes Petermaier <oe5hpm@oevsv.at> -
+# Bernecker & Rainer Industrielektronik GmbH - http://www.br-automation.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_SPL_BUILD) += mux.o
+obj-y += ../common/common.o
+obj-y += board.o
--- /dev/null
+/*
+ * board.c
+ *
+ * Board functions for B&R KWB Board
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <power/tps65217.h>
+#include "../common/bur_common.h"
+
+/* -------------------------------------------------------------------------*/
+/* -- defines for used GPIO Hardware -- */
+#define KEY (0+4)
+#define LCD_PWR (0+5)
+#define PUSH_KEY (0+31)
+#define USB2SD_NRST (32+29)
+#define USB2SD_PWR (96+13)
+/* -------------------------------------------------------------------------*/
+/* -- PSOC Resetcontroller Register defines -- */
+
+/* I2C Address of controller */
+#define RSTCTRL_ADDR 0x75
+/* Register for CTRL-word */
+#define RSTCTRL_CTRLREG 0x01
+/* Register for giving some information to VxWorks OS */
+#define RSTCTRL_SCRATCHREG 0x04
+
+/* -- defines for RSTCTRL_CTRLREG -- */
+#define RSTCTRL_FORCE_PWR_NEN 0x0404
+
+#if defined(CONFIG_SPL_BUILD)
+/* TODO: check ram-timing ! */
+static const struct ddr_data ddr3_data = {
+ .datardsratio0 = MT41K256M16HA125E_RD_DQS,
+ .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+ .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+ .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+ .cmd0csratio = MT41K256M16HA125E_RATIO,
+ .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+ .cmd1csratio = MT41K256M16HA125E_RATIO,
+ .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+ .cmd2csratio = MT41K256M16HA125E_RATIO,
+ .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+static struct emif_regs ddr3_emif_reg_data = {
+ .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+ .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+ .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+ .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+ .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+ .zq_config = MT41K256M16HA125E_ZQ_CFG,
+ .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+static const struct ctrl_ioregs ddr3_ioregs = {
+ .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+#define OSC (V_OSCK/1000000)
+const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+ unsigned int oldspeed;
+ unsigned short buf;
+
+ struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
+ struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
+ /*
+ * enable additional clocks of modules which are accessed later from
+ * VxWorks OS
+ */
+ u32 *const clk_domains[] = { 0 };
+
+ u32 *const clk_modules_kwbspecific[] = {
+ &cmwkup->wkup_adctscctrl,
+ &cmper->spi1clkctrl,
+ &cmper->dcan0clkctrl,
+ &cmper->dcan1clkctrl,
+ &cmper->epwmss0clkctrl,
+ &cmper->epwmss1clkctrl,
+ &cmper->epwmss2clkctrl,
+ 0
+ };
+ do_enable_clocks(clk_domains, clk_modules_kwbspecific, 1);
+
+ /* power-OFF LCD-Display */
+ gpio_direction_output(LCD_PWR, 0);
+
+ /* setup I2C */
+ enable_i2c0_pin_mux();
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+
+ /* power-ON 3V3 via Resetcontroller */
+ oldspeed = i2c_get_bus_speed();
+ if (0 != i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC)) {
+ buf = RSTCTRL_FORCE_PWR_NEN;
+ i2c_write(RSTCTRL_ADDR, RSTCTRL_CTRLREG, 1,
+ (uint8_t *)&buf, sizeof(buf));
+ i2c_set_bus_speed(oldspeed);
+ } else {
+ puts("ERROR: i2c_set_bus_speed failed! (turn on PWR_nEN)\n");
+ }
+
+#if defined(CONFIG_AM335X_USB0)
+ /* power on USB2SD Controller */
+ gpio_direction_output(USB2SD_PWR, 1);
+ mdelay(1);
+ /* give a reset Pulse to USB2SD Controller */
+ gpio_direction_output(USB2SD_NRST, 0);
+ mdelay(1);
+ gpio_set_value(USB2SD_NRST, 1);
+#endif
+ pmicsetup(0);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+ return &dpll_ddr3;
+}
+
+void sdram_init(void)
+{
+ config_ddr(400, &ddr3_ioregs,
+ &ddr3_data,
+ &ddr3_cmd_ctrl_data,
+ &ddr3_emif_reg_data, 0);
+}
+#endif /* CONFIG_SPL_BUILD */
+/*
+ * Basic board specific setup. Pinmux has been handled already.
+ */
+int board_init(void)
+{
+ gpmc_init();
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ const unsigned int ton = 250;
+ const unsigned int toff = 1000;
+ unsigned int cnt = 3;
+ unsigned short buf = 0xAAAA;
+ unsigned int oldspeed;
+
+ tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+ TPS65217_WLEDCTRL2, 0x32, 0xFF); /* 50% dimlevel */
+
+ if (gpio_get_value(KEY)) {
+ do {
+ /* turn on light */
+ tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+ TPS65217_WLEDCTRL1, 0x09, 0xFF);
+ mdelay(ton);
+ /* turn off light */
+ tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+ TPS65217_WLEDCTRL1, 0x01, 0xFF);
+ mdelay(toff);
+ cnt--;
+ if (!gpio_get_value(KEY) &&
+ gpio_get_value(PUSH_KEY) && 1 == cnt) {
+ puts("updating from USB ...\n");
+ setenv("bootcmd", "run usbupdate");
+ break;
+ } else if (!gpio_get_value(KEY)) {
+ break;
+ }
+ } while (cnt);
+ }
+
+ switch (cnt) {
+ case 0:
+ puts("3 blinks ... entering BOOT mode.\n");
+ buf = 0x0000;
+ break;
+ case 1:
+ puts("2 blinks ... entering DIAGNOSE mode.\n");
+ buf = 0x0F0F;
+ break;
+ case 2:
+ puts("1 blinks ... entering SERVICE mode.\n");
+ buf = 0xB4B4;
+ break;
+ case 3:
+ puts("0 blinks ... entering RUN mode.\n");
+ buf = 0x0404;
+ break;
+ }
+ mdelay(ton);
+ /* turn on light */
+ tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+ TPS65217_WLEDCTRL1, 0x09, 0xFF);
+ /* write bootinfo into scratchregister of resetcontroller */
+ oldspeed = i2c_get_bus_speed();
+ if (0 != i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC)) {
+ i2c_write(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1,
+ (uint8_t *)&buf, sizeof(buf));
+ i2c_set_bus_speed(oldspeed);
+ } else {
+ puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n");
+ }
+ /*
+ * reset VBAR registers to its reset location, VxWorks 6.9.3.2 does
+ * expect that vectors are there, original u-boot moves them to _start
+ */
+ __asm__("ldr r0,=0x20000");
+ __asm__("mcr p15, 0, r0, c12, c0, 0"); /* Set VBAR */
+
+ return 0;
+}
+#endif /* CONFIG_BOARD_LATE_INIT */
--- /dev/null
+/*
+ * mux.c
+ *
+ * Pinmux Setting for B&R LEIT Board(s)
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+
+static struct module_pin_mux usb0_pin_mux[] = {
+ {OFFSET(usb0_id), (MODE(0) | RXACTIVE)},
+ /* USB0 DrvBus Receiver disable (from romcode 0x20) */
+ {OFFSET(usb0_drvvbus), (MODE(0))},
+ /* USB1 DrvBus as GPIO due to HW-Workaround */
+ {OFFSET(usb1_drvvbus), (MODE(7))},
+ {-1},
+};
+static struct module_pin_mux spi1_pin_mux[] = {
+ /* SPI1_SCLK */
+ {OFFSET(mcasp0_aclkx), MODE(3) | PULLUDEN | RXACTIVE},
+ /* SPI1_D0 */
+ {OFFSET(mcasp0_fsx), MODE(3) | PULLUDEN | RXACTIVE},
+ /* SPI1_D1 */
+ {OFFSET(mcasp0_axr0), MODE(3) | PULLUDEN | RXACTIVE},
+ /* SPI1_CS0 */
+ {OFFSET(mcasp0_ahclkr), MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE},
+ {-1},
+};
+
+static struct module_pin_mux dcan0_pin_mux[] = {
+ /* DCAN0 TX */
+ {OFFSET(uart1_ctsn), MODE(2) | PULLUDEN | PULLUP_EN},
+ /* DCAN0 RX */
+ {OFFSET(uart1_rtsn), MODE(2) | RXACTIVE},
+ {-1},
+};
+
+static struct module_pin_mux dcan1_pin_mux[] = {
+ /* DCAN1 TX */
+ {OFFSET(uart1_rxd), MODE(2) | PULLUDEN | PULLUP_EN},
+ /* DCAN1 RX */
+ {OFFSET(uart1_txd), MODE(2) | RXACTIVE},
+ {-1},
+};
+
+static struct module_pin_mux gpios[] = {
+ /* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
+ {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS)},
+ /* GPIO0_4 (SPI D1) - TA602 */
+ {OFFSET(spi0_d1), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO0_5 (SPI CS0) - DISPLAY_ON_OFF */
+ {OFFSET(spi0_cs0), (MODE(7) | PULLUDDIS)},
+ /* GPIO0_7 (PWW0 OUT) - CAN TERM */
+ {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO0_19 (DMA_INTR0) - CLKOUT SYS */
+ {OFFSET(xdma_event_intr0), (MODE(7) | RXACTIVE)},
+ /* GPIO0_20 (DMA_INTR1) - SPI1 nCS1 */
+ {OFFSET(xdma_event_intr1), (MODE(7) | PULLUDEN | PULLUP_EN)},
+ /* GPIO0_30 (GPMC_WAIT0) - TA601 */
+ {OFFSET(gpmc_wait0), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO0_31 (GPMC_nWP) - SW601 PushButton */
+ {OFFSET(gpmc_wpn), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO1_28 (GPMC_nWE) - FRAM_nWP */
+ {OFFSET(gpmc_be1n), (MODE(7) | PULLUDDIS)},
+ /* GPIO2_0 (GPMC_nCS3) - VBAT_OK */
+ {OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) },
+ /* GPIO2_2 (GPMC_nADV_ALE) - DCOK */
+ {OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO2_4 (GPMC_nWE) - TST_BAST */
+ {OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)},
+ /* GPIO3_18 (MCASP0_ACLKR) - SW601 CNTup, mapped to Counter eQEB0A_in */
+ {OFFSET(mcasp0_aclkr), (MODE(1) | PULLUDDIS | RXACTIVE)},
+ /* GPIO3_19 (MCASP0_FSR) - SW601 CNTdown, mapped to Counter eQEB0B_in */
+ {OFFSET(mcasp0_fsr), (MODE(1) | PULLUDDIS | RXACTIVE)},
+ /* GPIO3_20 (MCASP0_AXR1) - SW601 CNTdown, map to Counter eQEB0_index */
+ {OFFSET(mcasp0_axr1), (MODE(1) | PULLUDDIS | RXACTIVE)},
+ {-1},
+};
+
+static struct module_pin_mux uart0_pin_mux[] = {
+ /* UART0_CTS */
+ {OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+ /* UART0_RXD */
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+ /* UART0_TXD */
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
+ {-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+ /* I2C_DATA */
+ {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+ /* I2C_SCLK */
+ {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+ {-1},
+};
+
+static struct module_pin_mux mii1_pin_mux[] = {
+ {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
+ {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
+ {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
+ {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
+ {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
+ {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
+ {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
+ {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
+ {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
+ {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
+ {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
+ {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
+ {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {-1},
+};
+
+static struct module_pin_mux mmc1_pin_mux[] = {
+ {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
+ {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
+ {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
+ {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
+ {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
+ {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
+ {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
+ {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
+
+ {-1},
+};
+
+static struct module_pin_mux lcd_pin_mux[] = {
+ {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */
+ {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */
+ {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */
+ {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */
+ {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */
+ {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */
+ {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */
+ {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */
+ {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */
+ {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */
+ {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */
+ {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */
+ {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */
+ {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */
+ {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */
+ {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */
+
+ {OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */
+ {OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */
+ {OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */
+ {OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */
+ {OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */
+ {OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */
+ {OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */
+ {OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */
+
+ {OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */
+ {OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */
+ {OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
+ {OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */
+
+ {-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+ configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+ configure_module_pin_mux(i2c0_pin_mux);
+ configure_module_pin_mux(mii1_pin_mux);
+ configure_module_pin_mux(usb0_pin_mux);
+ configure_module_pin_mux(spi1_pin_mux);
+ configure_module_pin_mux(dcan0_pin_mux);
+ configure_module_pin_mux(dcan1_pin_mux);
+ configure_module_pin_mux(mmc1_pin_mux);
+ configure_module_pin_mux(lcd_pin_mux);
+ configure_module_pin_mux(gpios);
+}
--- /dev/null
+#
+# Makefile
+#
+# Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
+# Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifeq ($(CONFIG_SPL_BUILD),y)
+obj-y := mux.o
+endif
+obj-y += ../common/common.o
+obj-y += board.o
--- /dev/null
+/*
+ * board.c
+ *
+ * Board functions for B&R LEIT Board
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <power/tps65217.h>
+#include "../common/bur_common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* --------------------------------------------------------------------------*/
+/* -- defines for GPIO -- */
+#define ETHLED_ORANGE (96+16) /* GPIO3_16 */
+#define REPSWITCH (0+20) /* GPIO0_20 */
+
+
+#if defined(CONFIG_SPL_BUILD)
+/* TODO: check ram-timing ! */
+static const struct ddr_data ddr3_data = {
+ .datardsratio0 = MT41K256M16HA125E_RD_DQS,
+ .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+ .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+ .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+ .cmd0csratio = MT41K256M16HA125E_RATIO,
+ .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+ .cmd1csratio = MT41K256M16HA125E_RATIO,
+ .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+ .cmd2csratio = MT41K256M16HA125E_RATIO,
+ .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+ .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+ .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+ .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+ .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+ .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+ .zq_config = MT41K256M16HA125E_ZQ_CFG,
+ .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+static const struct ctrl_ioregs ddr3_ioregs = {
+ .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+#ifdef CONFIG_SPL_OS_BOOT
+/*
+ * called from spl_nand.c
+ * return 0 for loading linux, return 1 for loading u-boot
+ */
+int spl_start_uboot(void)
+{
+ if (0 == gpio_get_value(REPSWITCH)) {
+ blink(5, 125, ETHLED_ORANGE);
+ mdelay(1000);
+ printf("SPL: entering u-boot instead kernel image.\n");
+ return 1;
+ }
+ return 0;
+}
+#endif /* CONFIG_SPL_OS_BOOT */
+
+#define OSC (V_OSCK/1000000)
+static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+ pmicsetup(1000);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+ return &dpll_ddr3;
+}
+
+void sdram_init(void)
+{
+ config_ddr(400, &ddr3_ioregs,
+ &ddr3_data,
+ &ddr3_cmd_ctrl_data,
+ &ddr3_emif_reg_data, 0);
+}
+#endif /* CONFIG_SPL_BUILD */
+
+/* Basic board specific setup. Pinmux has been handled already. */
+int board_init(void)
+{
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gpmc_init();
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ gpio_direction_output(ETHLED_ORANGE, 0);
+
+ if (0 == gpio_get_value(REPSWITCH)) {
+ printf("\n\n\n"
+ "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"
+ "!!!!!!! recovery switch activated !!!!!!!\n"
+ "!!!!!!! running usbupdate !!!!!!!\n"
+ "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n\n\n");
+ setenv("bootcmd", "sleep 2; run netupdate;");
+ }
+
+ printf("turning on display power+backlight ... ");
+ tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_WLEDCTRL1,
+ 0x09, TPS65217_MASK_ALL_BITS); /* 200 Hz, ON */
+ tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_WLEDCTRL2,
+ 0x62, TPS65217_MASK_ALL_BITS); /* 100% */
+ printf("ok.\n");
+
+ return 0;
+}
+#endif /* CONFIG_BOARD_LATE_INIT */
--- /dev/null
+/*
+ * mux.c
+ *
+ * Pinmux Setting for B&R LEIT Board(s)
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+
+static struct module_pin_mux uart0_pin_mux[] = {
+ /* UART0_CTS */
+ {OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+ /* UART0_RXD */
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+ /* UART0_TXD */
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
+ {-1},
+};
+#ifdef CONFIG_MMC
+static struct module_pin_mux mmc1_pin_mux[] = {
+ {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
+ {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
+ {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
+ {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
+ {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
+ {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
+ {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
+ {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
+ {-1},
+};
+#endif
+static struct module_pin_mux i2c0_pin_mux[] = {
+ /* I2C_DATA */
+ {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+ /* I2C_SCLK */
+ {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+ {-1},
+};
+
+static struct module_pin_mux spi0_pin_mux[] = {
+ /* SPI0_SCLK */
+ {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
+ /* SPI0_D0 */
+ {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
+ /* SPI0_D1 */
+ {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
+ /* SPI0_CS0 */
+ {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
+ {-1},
+};
+
+static struct module_pin_mux mii1_pin_mux[] = {
+ {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
+ {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
+ {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
+ {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
+ {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
+ {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
+ {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
+ {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
+ {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
+ {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
+ {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
+ {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
+ {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {-1},
+};
+
+static struct module_pin_mux mii2_pin_mux[] = {
+ {OFFSET(gpmc_a0), MODE(1)}, /* MII2_TXEN */
+ {OFFSET(gpmc_a1), MODE(1) | RXACTIVE}, /* MII2_RXDV */
+ {OFFSET(gpmc_a2), MODE(1)}, /* MII2_TXD3 */
+ {OFFSET(gpmc_a3), MODE(1)}, /* MII2_TXD2 */
+ {OFFSET(gpmc_a4), MODE(1)}, /* MII2_TXD1 */
+ {OFFSET(gpmc_a5), MODE(1)}, /* MII2_TXD0 */
+ {OFFSET(gpmc_a6), MODE(1) | RXACTIVE}, /* MII2_TXCLK */
+ {OFFSET(gpmc_a7), MODE(1) | RXACTIVE}, /* MII2_RXCLK */
+ {OFFSET(gpmc_a8), MODE(1) | RXACTIVE}, /* MII2_RXD3 */
+ {OFFSET(gpmc_a9), MODE(1) | RXACTIVE}, /* MII2_RXD2 */
+ {OFFSET(gpmc_a10), MODE(1) | RXACTIVE}, /* MII2_RXD1 */
+ {OFFSET(gpmc_a11), MODE(1) | RXACTIVE}, /* MII2_RXD0 */
+ {OFFSET(gpmc_wpn), (MODE(1) | RXACTIVE)},/* MII2_RXERR */
+ /*
+ * MII2_CRS is shared with
+ * NAND_WAIT0
+ */
+ {OFFSET(gpmc_be1n), (MODE(1) | RXACTIVE)},/* MII1_COL */
+ {-1},
+};
+#ifdef CONFIG_NAND
+static struct module_pin_mux nand_pin_mux[] = {
+ {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
+ {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
+ {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
+ {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
+ {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
+ {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
+ {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
+ {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
+ {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+ {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
+ {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
+ {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
+ {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
+ {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
+ {-1},
+};
+#endif
+static struct module_pin_mux gpIOs[] = {
+ /* GPIO0_6 (SPI0_CS1) - 3v3_PWR_nEN (Display Power Supply) */
+ {OFFSET(spi0_cs1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+ /* TIMER5 (MMC0_DAT3) - TIMER5 (Buzzer) */
+ {OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | RXACTIVE)},
+ /* TIMER6 (MMC0_DAT2) - PWM_BACK_3V3, later used as MODE3 for PWM */
+ {OFFSET(mmc0_dat2), (MODE(7) | PULLUDEN | RXACTIVE)},
+ /* GPIO2_28 (MMC0_DAT1) - MII_nNAND */
+ {OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | RXACTIVE)},
+ /* GPIO2_29 (MMC0_DAT0) - NAND_1n0 */
+ {OFFSET(mmc0_dat0), (MODE(7) | PULLUDEN | RXACTIVE)},
+ /* GPIO2_30 (MMC0_CLK) - nRESET (PHY) */
+ {OFFSET(mmc0_clk), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+ /* GPIO3_18 (MCASP0_ACLKR) - CPLD JTAG TDI */
+ {OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+ /* GPIO3_19 (MCASP0_FSR) - CPLD JTAG TMS */
+ {OFFSET(mcasp0_fsr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+ /* GPIO3_20 (MCASP0_AXR1) - CPLD JTAG TCK */
+ {OFFSET(mcasp0_axr1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+ /* GPIO3_21 (MCASP0_AHCLKX) - CPLD JTAG TDO */
+ {OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+ /* GPIO2_0 (GPMC_nCS3) - DCOK */
+ {OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) },
+ /* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
+ {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS | RXACTIVE) },
+ /*
+ * GPIO0_7 (PWW0 OUT)
+ * DISPLAY_ONOFF (Backlight Enable at LVDS Versions)
+ */
+ {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | RXACTIVE)},
+ /* GPIO0_19 (DMA_INTR0) - ISPLAY_MODE (CPLD) */
+ {OFFSET(xdma_event_intr0), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+ /* GPIO0_20 (DMA_INTR1) - REP-Switch */
+ {OFFSET(xdma_event_intr1), (MODE(7) | PULLUP_EN | RXACTIVE)},
+ /* GPIO3_14 (MCASP0_ACLKX) - frei / PP709 */
+ {OFFSET(mcasp0_aclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) },
+ /* GPIO3_15 (MCASP0_FSX) - PMIC_nRESET */
+ {OFFSET(mcasp0_fsx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) },
+ /* GPIO3_16 (MCASP0_AXR0) - ETH1_LEDY */
+ {OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS) },
+ /* GPIO3_17 (MCASP0_AHCLKR) - ETH2_LEDY */
+ {OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS) },
+
+ {-1},
+};
+
+static struct module_pin_mux lcd_pin_mux[] = {
+ {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */
+ {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */
+ {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */
+ {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */
+ {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */
+ {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */
+ {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */
+ {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */
+ {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */
+ {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */
+ {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */
+ {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */
+ {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */
+ {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */
+ {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */
+ {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */
+
+ {OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */
+ {OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */
+ {OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */
+ {OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */
+ {OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */
+ {OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */
+ {OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */
+ {OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */
+
+ {OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */
+ {OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */
+ {OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
+ {OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */
+
+ {-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+ configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+ configure_module_pin_mux(i2c0_pin_mux);
+ configure_module_pin_mux(mii1_pin_mux);
+ configure_module_pin_mux(mii2_pin_mux);
+#ifdef CONFIG_NAND
+ configure_module_pin_mux(nand_pin_mux);
+#elif defined(CONFIG_MMC)
+ configure_module_pin_mux(mmc1_pin_mux);
+#endif
+ configure_module_pin_mux(spi0_pin_mux);
+ configure_module_pin_mux(lcd_pin_mux);
+ configure_module_pin_mux(gpIOs);
+}
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := actux1.o
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <malloc.h>
-#include <asm/arch/ixp425.h>
-#include <asm/io.h>
-#include <miiphy.h>
-#ifdef CONFIG_PCI
-#include <pci.h>
-#include <asm/arch/ixp425pci.h>
-#endif
-
-#include "actux1_hw.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- /* CS5: Debug port */
- writel(0x9d520003, IXP425_EXP_CS5);
- /* CS6: HwRel */
- writel(0x81860001, IXP425_EXP_CS6);
- /* CS7: LEDs */
- writel(0x80900003, IXP425_EXP_CS7);
- return 0;
-}
-
-int board_init(void)
-{
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0x00000100;
-
- GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);
-
- /* Setup GPIOs for PCI INTA */
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI1_INTA);
- GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI1_INTA);
-
- /* Setup GPIOs for 33MHz clock output */
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
- writel(0x011001FF, IXP425_GPIO_GPCLKR);
-
- udelay(533);
- GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
-
- ACTUX1_LED1(2);
- ACTUX1_LED2(2);
- ACTUX1_LED3(0);
- ACTUX1_LED4(0);
- ACTUX1_LED5(0);
- ACTUX1_LED6(0);
- ACTUX1_LED7(0);
-
- ACTUX1_HS(ACTUX1_HS_DCD);
-
- return 0;
-}
-
-/*
- * Check Board Identity
- */
-int checkboard(void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
-
- puts("Board: AcTux-1 rev.");
- putc(ACTUX1_BOARDREL + 'A' - 1);
-
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- putc('\n');
-
- return 0;
-}
-
-/*************************************************************************
- * get_board_rev() - setup to pass kernel board revision information
- * 0 = reserved
- * 1 = Rev. A
- * 2 = Rev. B
- *************************************************************************/
-u32 get_board_rev(void)
-{
- return ACTUX1_BOARDREL;
-}
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
- return 0;
-}
-
-
-#ifdef CONFIG_PCI
-struct pci_controller hose;
-
-void pci_init_board(void)
-{
- pci_ixp_init(&hose);
-}
-#endif
-
-void reset_phy(void)
-{
- u16 id1, id2;
-
- /* initialize the PHY */
- miiphy_reset("NPE0", CONFIG_PHY_ADDR);
-
- miiphy_read("NPE0", CONFIG_PHY_ADDR, MII_PHYSID1, &id1);
- miiphy_read("NPE0", CONFIG_PHY_ADDR, MII_PHYSID2, &id2);
-
- id2 &= 0xFFF0; /* mask out revision bits */
-
- if (id1 == 0x13 && id2 == 0x78e0) {
- /*
- * LXT971/LXT972 PHY: set LED outputs:
- * LED1(green) = Link/ACT,
- * LED2 (unused) = LINK,
- * LED3(red) = Coll
- */
- miiphy_write("NPE0", CONFIG_PHY_ADDR, 20, 0xD432);
- } else if (id1 == 0x143 && id2 == 0xbc30) {
- /* BCM5241: default values are OK */
- } else
- printf("unknown ethernet PHY ID: %x %x\n", id1, id2);
-}
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * hardware register definitions for the AcTux-1 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ACTUX1_HW_H
-#define _ACTUX1_HW_H
-
-/* 0 = LED off,1 = green, 2 = red, 3 = orange */
-#define ACTUX1_LED1(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 0)
-#define ACTUX1_LED2(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 1)
-#define ACTUX1_LED3(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 2)
-#define ACTUX1_LED4(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 3)
-#define ACTUX1_LED5(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 4)
-#define ACTUX1_LED6(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 5)
-#define ACTUX1_LED7(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 6)
-#define ACTUX1_HS(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 7)
-#define ACTUX1_HS_DCD 0x01
-#define ACTUX1_HS_DSR 0x02
-
-#define ACTUX1_DBG_PORT IXP425_EXP_BUS_CS5_BASE_PHYS
-#define ACTUX1_BOARDREL (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F)
-
-/* GPIO settings */
-#define CONFIG_SYS_GPIO_PCI1_INTA 2
-#define CONFIG_SYS_GPIO_PCI2_INTA 3
-#define CONFIG_SYS_GPIO_I2C_SDA 4
-#define CONFIG_SYS_GPIO_I2C_SCL 5
-#define CONFIG_SYS_GPIO_DBGJUMPER 9
-#define CONFIG_SYS_GPIO_BUTTON1 10
-#define CONFIG_SYS_GPIO_DBGSENSE 11
-#define CONFIG_SYS_GPIO_DTR 12
-#define CONFIG_SYS_GPIO_IORST 13 /* Out */
-#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */
-#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
-OUTPUT_ARCH (arm)
-ENTRY (_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN (4);
- .text : {
- *(.__image_copy_start)
- arch/arm/cpu/ixp/start.o(.text*)
- net/built-in.o(.text*)
- board/actux1/built-in.o(.text*)
- arch/arm/cpu/ixp/built-in.o(.text*)
- drivers/input/built-in.o(.text*)
-
- . = env_offset;
- common/env_embedded.o(.ppcenv)
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- . = ALIGN(4);
- .data : {
- *(.data*)
- }
- . = ALIGN(4);
- .got : {
- *(.got)
- }
- . =.;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = ALIGN (4);
-
- .image_copy_end :
- {
- *(.__image_copy_end)
- }
-
- .rel_dyn_start :
- {
- *(.__rel_dyn_start)
- }
-
- .rel.dyn : {
- *(.rel*)
- }
-
- .rel_dyn_end :
- {
- *(.__rel_dyn_end)
- }
-
- _end = .;
-
-/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
- */
-
- .bss_start __rel_dyn_start (OVERLAY) : {
- KEEP(*(.__bss_start));
- __bss_base = .;
- }
-
- .bss __bss_base (OVERLAY) : {
- *(.bss*)
- . = ALIGN(4);
- __bss_limit = .;
- }
- .bss_end __bss_limit (OVERLAY) : {
- KEEP(*(.__bss_end));
- }
-
- .dynsym _end : { *(.dynsym) }
- .dynbss : { *(.dynbss) }
- .dynstr : { *(.dynstr*) }
- .dynamic : { *(.dynamic*) }
- .hash : { *(.hash*) }
- .plt : { *(.plt*) }
- .interp : { *(.interp*) }
- .gnu : { *(.gnu*) }
- .ARM.exidx : { *(.ARM.exidx*) }
-}
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := actux2.o
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <malloc.h>
-#include <asm/arch/ixp425.h>
-#include <asm/io.h>
-
-#include <miiphy.h>
-
-#include "actux2_hw.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- /* CS1: IPAC-X */
- writel(0x94d10013, IXP425_EXP_CS1);
- /* CS5: Debug port */
- writel(0x9d520003, IXP425_EXP_CS5);
- /* CS6: HW release register */
- writel(0x81860001, IXP425_EXP_CS6);
- /* CS7: LEDs */
- writel(0x80900003, IXP425_EXP_CS7);
-
- return 0;
-}
-
-int board_init(void)
-{
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0x00000100;
-
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_ETHRST);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DSR);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DCD);
-
- GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
- GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_ETHRST);
-
- GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DSR);
- GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DCD);
-
- /* Setup GPIOs for Interrupt inputs */
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DBGINT);
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_ETHINT);
-
- /* Setup GPIOs for 33MHz clock output */
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
- writel(0x011001FF, IXP425_GPIO_GPCLKR);
-
- udelay(533);
- GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
- GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_ETHRST);
-
- ACTUX2_LED1(1);
- ACTUX2_LED2(0);
- ACTUX2_LED3(0);
- ACTUX2_LED4(0);
-
- return 0;
-}
-
-/*
- * Check Board Identity
- */
-int checkboard(void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
-
- puts("Board: AcTux-2 rev.");
- putc(ACTUX2_BOARDREL + 'A' - 1);
-
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- putc('\n');
-
- return 0;
-}
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
- return 0;
-}
-
-/*************************************************************************
- * get_board_rev() - setup to pass kernel board revision information
- * 0 = reserved
- * 1 = Rev. A
- * 2 = Rev. B
- *************************************************************************/
-u32 get_board_rev(void)
-{
- return ACTUX2_BOARDREL;
-}
-
-void reset_phy(void)
-{
- /* init IcPlus IP175C ethernet switch to native IP175C mode */
- miiphy_write("NPE0", 29, 31, 0x175C);
-}
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * hardware register definitions for the AcTux-2 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ACTUX2_HW_H
-#define _ACTUX2_HW_H
-
-/* 0 = LED off,1 = green, 2 = red, 3 = orange */
-#define ACTUX2_LED1(a) writeb((a ? 2 : 0), IXP425_EXP_BUS_CS7_BASE_PHYS + 0)
-#define ACTUX2_LED2(a) writeb((a ? 2 : 0), IXP425_EXP_BUS_CS7_BASE_PHYS + 1)
-#define ACTUX2_LED3(a) writeb((a ? 0 : 2), IXP425_EXP_BUS_CS7_BASE_PHYS + 2)
-#define ACTUX2_LED4(a) writeb((a ? 0 : 2), IXP425_EXP_BUS_CS7_BASE_PHYS + 3)
-
-#define ACTUX2_DBG_PORT IXP425_EXP_BUS_CS5_BASE_PHYS
-#define ACTUX2_BOARDREL (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F)
-#define ACTUX2_OPTION (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0xF0)
-
-/*
- * GPIO settings
- */
-#define CONFIG_SYS_GPIO_DBGINT 0
-#define CONFIG_SYS_GPIO_ETHINT 1
-#define CONFIG_SYS_GPIO_ETHRST 2 /* Out */
-#define CONFIG_SYS_GPIO_LED5_GN 3 /* Out */
-#define CONFIG_SYS_GPIO_UNUSED4 4
-#define CONFIG_SYS_GPIO_UNUSED5 5
-#define CONFIG_SYS_GPIO_DSR 6 /* Out */
-#define CONFIG_SYS_GPIO_DCD 7 /* Out */
-#define CONFIG_SYS_GPIO_IPAC_INT 8
-#define CONFIG_SYS_GPIO_DBGJUMPER 9
-#define CONFIG_SYS_GPIO_BUTTON1 10
-#define CONFIG_SYS_GPIO_DBGSENSE 11
-#define CONFIG_SYS_GPIO_DTR 12
-#define CONFIG_SYS_GPIO_IORST 13 /* Out */
-#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */
-#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
-OUTPUT_ARCH (arm)
-ENTRY (_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN (4);
- .text : {
- *(.__image_copy_start)
- arch/arm/cpu/ixp/start.o(.text*)
- net/built-in.o(.text*)
- board/actux2/built-in.o(.text*)
- arch/arm/cpu/ixp/built-in.o(.text*)
- drivers/input/built-in.o(.text*)
-
- . = env_offset;
- common/env_embedded.o(.ppcenv)
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- . = ALIGN(4);
- .data : {
- *(.data*)
- }
- . = ALIGN(4);
- .got : {
- *(.got)
- }
- . =.;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = ALIGN (4);
-
- .image_copy_end :
- {
- *(.__image_copy_end)
- }
-
- .rel_dyn_start :
- {
- *(.__rel_dyn_start)
- }
-
- .rel.dyn : {
- *(.rel*)
- }
-
- .rel_dyn_end :
- {
- *(.__rel_dyn_end)
- }
-
- _end = .;
-
-/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
- */
-
- .bss_start __rel_dyn_start (OVERLAY) : {
- KEEP(*(.__bss_start));
- __bss_base = .;
- }
-
- .bss __bss_base (OVERLAY) : {
- *(.bss*)
- . = ALIGN(4);
- __bss_limit = .;
- }
- .bss_end __bss_limit (OVERLAY) : {
- KEEP(*(.__bss_end));
- }
-
- .dynsym _end : { *(.dynsym) }
- .dynbss : { *(.dynbss) }
- .dynstr : { *(.dynstr*) }
- .dynamic : { *(.dynamic*) }
- .hash : { *(.hash*) }
- .plt : { *(.plt*) }
- .interp : { *(.interp*) }
- .gnu : { *(.gnu*) }
- .ARM.exidx : { *(.ARM.exidx*) }
-}
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := actux3.o
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <malloc.h>
-#include <asm/arch/ixp425.h>
-#include <asm/io.h>
-#include <miiphy.h>
-#include "actux3_hw.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- /* CS1: IPAC-X */
- writel(0x94d10013, IXP425_EXP_CS1);
- /* CS5: Debug port */
- writel(0x9d520003, IXP425_EXP_CS5);
- /* CS6: Release/Option register */
- writel(0x81860001, IXP425_EXP_CS6);
- /* CS7: LEDs */
- writel(0x80900003, IXP425_EXP_CS7);
-
- return 0;
-}
-
-int board_init(void)
-{
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0x00000100;
-
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_ETHRST);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DSR);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DCD);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED5_GN);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED6_RT);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED6_GN);
-
- GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
- GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_ETHRST);
-
- GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DSR);
- GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DCD);
-
- GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED5_GN);
- GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED6_RT);
- GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED6_GN);
-
- /*
- * Setup GPIO's for Interrupt inputs
- */
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DBGINT);
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_ETHINT);
-
- /*
- * Setup GPIO's for 33MHz clock output
- */
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
- writel(0x011001FF, IXP425_GPIO_GPCLKR);
-
- /* we need a minimum PCI reset pulse width after enabling the clock */
- udelay(533);
- GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
- GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_ETHRST);
-
- ACTUX3_LED1_RT(1);
- ACTUX3_LED1_GN(0);
- ACTUX3_LED2_RT(0);
- ACTUX3_LED2_GN(0);
- ACTUX3_LED3_RT(0);
- ACTUX3_LED3_GN(0);
- ACTUX3_LED4_GN(0);
- ACTUX3_LED5_RT(0);
-
- return 0;
-}
-
-/*
- * Check Board Identity
- */
-int checkboard(void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
-
- puts("Board: AcTux-3 rev.");
- putc(ACTUX3_BOARDREL + 'A' - 1);
-
- if (i > 0) {
- puts (", serial# ");
- puts (buf);
- }
- putc('\n');
-
- return 0;
-}
-
-/*************************************************************************
- * get_board_rev() - setup to pass kernel board revision information
- * 0 = reserved
- * 1 = Rev. A
- * 2 = Rev. B
- *************************************************************************/
-u32 get_board_rev(void)
-{
- return ACTUX3_BOARDREL;
-}
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
- return 0;
-}
-
-void reset_phy(void)
-{
- int i;
-
- /* initialize the PHY */
- miiphy_reset("NPE0", CONFIG_PHY_ADDR);
-
- /* all LED outputs = Link/Act */
- miiphy_write("NPE0", CONFIG_PHY_ADDR, 0x16, 0x0AAA);
-
- /*
- * The Marvell 88E6060 switch comes up with all ports disabled.
- * set all ethernet switch ports to forwarding state
- */
- for (i = 1; i <= 5; i++)
- miiphy_write("NPE0", CONFIG_PHY_ADDR + 8 + i, 0x04, 0x03);
-
-}
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * hardware register definitions for the AcTux-3 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ACTUX3_HW_H
-#define _ACTUX3_HW_H
-
-/* 0 = LED off,1 = ON */
-#define ACTUX3_LED1_RT(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 0)
-#define ACTUX3_LED1_GN(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 1)
-#define ACTUX3_LED2_RT(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 2)
-#define ACTUX3_LED2_GN(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 3)
-#define ACTUX3_LED3_RT(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 4)
-#define ACTUX3_LED3_GN(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 5)
-#define ACTUX3_LED4_GN(a) writeb((a)^1, IXP425_EXP_BUS_CS7_BASE_PHYS + 6)
-#define ACTUX3_LED5_RT(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 7)
-
-#define ACTUX3_DBG_PORT IXP425_EXP_BUS_CS5_BASE_PHYS
-#define ACTUX3_BOARDREL (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F)
-#define ACTUX3_OPTION (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0xF0)
-
-/* GPIO settings */
-#define CONFIG_SYS_GPIO_DBGINT 0
-#define CONFIG_SYS_GPIO_ETHINT 1
-#define CONFIG_SYS_GPIO_ETHRST 2 /* Out */
-#define CONFIG_SYS_GPIO_LED5_GN 3 /* Out */
-#define CONFIG_SYS_GPIO_LED6_RT 4 /* Out */
-#define CONFIG_SYS_GPIO_LED6_GN 5 /* Out */
-#define CONFIG_SYS_GPIO_DSR 6 /* Out */
-#define CONFIG_SYS_GPIO_DCD 7 /* Out */
-#define CONFIG_SYS_GPIO_DBGJUMPER 9
-#define CONFIG_SYS_GPIO_BUTTON1 10
-#define CONFIG_SYS_GPIO_DBGSENSE 11
-#define CONFIG_SYS_GPIO_DTR 12
-#define CONFIG_SYS_GPIO_IORST 13 /* Out */
-#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */
-#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
-OUTPUT_ARCH (arm)
-ENTRY (_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN (4);
- .text : {
- *(.__image_copy_start)
- arch/arm/cpu/ixp/start.o(.text*)
- net/built-in.o(.text*)
- board/actux3/built-in.o(.text*)
- arch/arm/cpu/ixp/built-in.o(.text*)
- drivers/input/built-in.o(.text*)
-
- . = env_offset;
- common/env_embedded.o(.ppcenv)
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- . = ALIGN(4);
- .data : {
- *(.data*)
- }
- . = ALIGN(4);
- .got : {
- *(.got)
- }
- . =.;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = ALIGN (4);
-
- .image_copy_end :
- {
- *(.__image_copy_end)
- }
-
- .rel_dyn_start :
- {
- *(.__rel_dyn_start)
- }
-
- .rel.dyn : {
- *(.rel*)
- }
-
- .rel_dyn_end :
- {
- *(.__rel_dyn_end)
- }
-
- _end = .;
-
-/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
- */
-
- .bss_start __rel_dyn_start (OVERLAY) : {
- KEEP(*(.__bss_start));
- __bss_base = .;
- }
-
- .bss __bss_base (OVERLAY) : {
- *(.bss*)
- . = ALIGN(4);
- __bss_limit = .;
- }
- .bss_end __bss_limit (OVERLAY) : {
- KEEP(*(.__bss_end));
- }
-
- .dynsym _end : { *(.dynsym) }
- .dynbss : { *(.dynbss) }
- .dynstr : { *(.dynstr*) }
- .dynamic : { *(.dynamic*) }
- .hash : { *(.hash*) }
- .plt : { *(.plt*) }
- .interp : { *(.interp*) }
- .gnu : { *(.gnu*) }
- .ARM.exidx : { *(.ARM.exidx*) }
-}
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := actux4.o
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <malloc.h>
-#include <asm/arch/ixp425.h>
-#include <asm/io.h>
-#include <miiphy.h>
-#ifdef CONFIG_PCI
-#include <pci.h>
-#include <asm/arch/ixp425pci.h>
-#endif
-
-#include "actux4_hw.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- writel(0xbd113c42, IXP425_EXP_CS1);
- return 0;
-}
-
-int board_init(void)
-{
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0x00000100;
-
- GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_nPWRON);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_nPWRON);
-
- GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);
-
- /* led not populated on board*/
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED3);
- GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED3);
-
- /* middle LED */
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED2);
- GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED2);
-
- /* right LED */
- /* weak pulldown = LED weak on */
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_LED1);
- GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED1);
-
- /* Setup GPIO's for Interrupt inputs */
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTA);
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTB);
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTC);
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RTCINT);
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA);
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB);
-
- GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTA);
- GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTB);
- GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTC);
- GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RTCINT);
- GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA);
- GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB);
-
- /* Setup GPIO's for 33MHz clock output */
- writel(0x011001FF, IXP425_GPIO_GPCLKR);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
-
- udelay(10000);
- GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
- udelay(10000);
- GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
- udelay(10000);
- GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
-
- return 0;
-}
-
-/* Check Board Identity */
-int checkboard(void)
-{
- puts("Board: AcTux-4\n");
- return 0;
-}
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
- return 0;
-}
-
-#ifdef CONFIG_PCI
-struct pci_controller hose;
-
-void pci_init_board(void)
-{
- pci_ixp_init(&hose);
-}
-#endif
-
-/*
- * Hardcoded flash setup:
- * Flash 0 is a non-CFI SST 39VF020 flash, 8 bit flash / 8 bit bus.
- * Flash 1 is an Intel *16 flash using the CFI driver.
- */
-ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
-{
- if (banknum == 0) { /* non-CFI boot flash */
- info->portwidth = 1;
- info->chipwidth = 1;
- info->interface = FLASH_CFI_X8;
- return 1;
- } else
- return 0;
-}
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * hardware register definitions for the AcTux-4 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ACTUX4_HW_H
-#define _ACTUX4_HW_H
-
-/*
- * GPIO settings
- */
-#define CONFIG_SYS_GPIO_USBINTA 0
-#define CONFIG_SYS_GPIO_USBINTB 1
-#define CONFIG_SYS_GPIO_USBINTC 2
-#define CONFIG_SYS_GPIO_nPWRON 3 /* Out */
-#define CONFIG_SYS_GPIO_I2C_SCL 4
-#define CONFIG_SYS_GPIO_I2C_SDA 5
-#define CONFIG_SYS_GPIO_PCI_INTB 6
-#define CONFIG_SYS_GPIO_BUTTON1 7
-#define CONFIG_SYS_GPIO_LED1 8 /* Out */
-#define CONFIG_SYS_GPIO_RTCINT 9
-#define CONFIG_SYS_GPIO_LED2 10 /* Out */
-#define CONFIG_SYS_GPIO_PCI_INTA 11
-#define CONFIG_SYS_GPIO_IORST 12 /* Out */
-#define CONFIG_SYS_GPIO_LED3 13 /* Out */
-#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */
-#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */
-
-#endif
UBL_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/ublimage.cfg
ifndef CONFIG_SPL_BUILD
-ALL-y += $(obj)u-boot.ubl
+ALL-y += u-boot.ubl
else
# as SPL_TEXT_BASE is not page-aligned, we need for some
# linkers the -n flag (Do not page align data), to prevent
} >.sram
__image_copy_end = .;
- _end = .;
+
+ .end :
+ {
+ *(.__end)
+ }
}
void text_base_hook(void); /* nop hook for text_base.S */
-#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
+#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) && \
+ defined(CONFIG_CFI_FLASH_MTD)
static void __early_flash_cmd_reset(void)
{
/* reset flash before we read env */
"led");
#endif
#endif
-#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
+#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) && \
+ defined(CONFIG_CFI_FLASH_MTD)
early_flash_cmd_reset();
#endif
return 0;
DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_DISPLAY_CPUINFO)
/*
* Print CPU information
*/
puts("CPU : Altera SOCFPGA Platform\n");
return 0;
}
+#endif
/*
* Print Board information
/* Now 0x00000000 is writeable, replace the vectors */
ldr r0, =_start /* r0 <- start of vectors */
- ldr r2, =_TEXT_BASE /* r2 <- past vectors */
+ add r2, r0, #64 /* r2 <- past vectors */
sub r1,r1,r1 /* destination 0x00000000 */
copy_vec:
obj-y := ../common/tamonten.o
-include ../../nvidia/common/common.mk
+include $(srctree)/board/nvidia/common/common.mk
obj-y := ../common/tamonten.o
-include ../../nvidia/common/common.mk
+include $(srctree)/board/nvidia/common/common.mk
obj-y := ../common/tamonten-ng.o
-include ../../nvidia/common/common.mk
+include $(srctree)/board/nvidia/common/common.mk
obj-y := ../common/tamonten.o
-include ../../nvidia/common/common.mk
+include $(srctree)/board/nvidia/common/common.mk
# SPDX-License-Identifier: GPL-2.0+
#
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
# SPDX-License-Identifier: GPL-2.0+
#
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
# SPDX-License-Identifier: GPL-2.0+
#
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
# SPDX-License-Identifier: GPL-2.0+
#
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
# SPDX-License-Identifier: GPL-2.0+
#
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
# SPDX-License-Identifier: GPL-2.0+
#
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 6
# SPDX-License-Identifier: GPL-2.0+
#
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
# SPDX-License-Identifier: GPL-2.0+
#
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
# SPDX-License-Identifier: GPL-2.0+
#
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
# SPDX-License-Identifier: GPL-2.0+
#
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
# SPDX-License-Identifier: GPL-2.0+
#
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --dma 6
# SPDX-License-Identifier: GPL-2.0+
#
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
# SPDX-License-Identifier: GPL-2.0+
#
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
if (CONFIG_DW_PORTS & 1) {
static const unsigned short pins[] = P_RMII0;
if (!peripheral_request_list(pins, "emac0"))
- ret += designware_initialize(0, EMAC0_MACCFG, 1, 0);
+ ret += designware_initialize(EMAC0_MACCFG, 0);
}
if (CONFIG_DW_PORTS & 2) {
static const unsigned short pins[] = P_RMII1;
if (!peripheral_request_list(pins, "emac1"))
- ret += designware_initialize(1, EMAC1_MACCFG, 1, 0);
+ ret += designware_initialize(EMAC1_MACCFG, 0);
}
return ret;
}
#endif
-#ifdef CONFIG_MV_UDC
+#ifdef CONFIG_CI_UDC
/* For otg ethernet*/
usb_eth_initialize(bis);
#endif
# SPDX-License-Identifier: GPL-2.0+
#
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
--- /dev/null
+#
+# Copyright 2013 Broadcom Corporation.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += $(BOARD).o
--- /dev/null
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include <mmc.h>
+#include <asm/kona-common/kona_sdhci.h>
+#include <asm/kona-common/clk.h>
+#include <asm/arch/sysmap.h>
+
+#define SECWATCHDOG_SDOGCR_OFFSET 0x00000000
+#define SECWATCHDOG_SDOGCR_EN_SHIFT 27
+#define SECWATCHDOG_SDOGCR_SRSTEN_SHIFT 26
+#define SECWATCHDOG_SDOGCR_CLKS_SHIFT 20
+#define SECWATCHDOG_SDOGCR_LD_SHIFT 0
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * board_init - early hardware init
+ */
+int board_init(void)
+{
+ printf("Relocation Offset is: %08lx\n", gd->reloc_off);
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ clk_init();
+
+ return 0;
+}
+
+/*
+ * misc_init_r - miscellaneous platform dependent initializations
+ */
+int misc_init_r(void)
+{
+ /* Disable watchdog reset - watchdog unused */
+ writel((0 << SECWATCHDOG_SDOGCR_EN_SHIFT) |
+ (0 << SECWATCHDOG_SDOGCR_SRSTEN_SHIFT) |
+ (4 << SECWATCHDOG_SDOGCR_CLKS_SHIFT) |
+ (0x5a0 << SECWATCHDOG_SDOGCR_LD_SHIFT),
+ (SECWD_BASE_ADDR + SECWATCHDOG_SDOGCR_OFFSET));
+
+ return 0;
+}
+
+/*
+ * dram_init - sets uboots idea of sdram size
+ */
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+/* This is called after dram_init() so use get_ram_size result */
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+}
+
+#ifdef CONFIG_KONA_SDHCI
+/*
+ * mmc_init - Initializes mmc
+ */
+int board_mmc_init(bd_t *bis)
+{
+ int ret = 0;
+
+ /* Register eMMC - SDIO2 */
+ ret = kona_sdhci_init(1, 400000, 0);
+ if (ret)
+ return ret;
+
+ /* Register SD Card - SDIO4 kona_mmc_init assumes 0 based index */
+ ret = kona_sdhci_init(3, 400000, 0);
+ return ret;
+}
+#endif
+++ /dev/null
-#
-# Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
-#
-# SPDX-License-Identifier: GPL-2.0 BSD-3-Clause
-#
-
-HOSTCFLAGS_autoconf.mk.dep = -Wno-variadic-macros
# SPDX-License-Identifier: GPL-2.0+
#
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
# SPDX-License-Identifier: GPL-2.0+
#
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
# SPDX-License-Identifier: GPL-2.0+
#
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
# SPDX-License-Identifier: GPL-2.0+
#
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
# SPDX-License-Identifier: GPL-2.0+
#
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --dma 6
#include <config.h>
#include <malloc.h>
#include <asm/blackfin.h>
+#include <asm/clock.h>
#include <asm/gpio.h>
#include <asm/portmux.h>
#include <asm/mach-common/bits/dma.h>
# SPDX-License-Identifier: GPL-2.0+
#
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
*/
flash_protect (FLAG_PROTECT_SET,
CONFIG_SYS_FLASH_BASE,
- CONFIG_SYS_FLASH_BASE + _bss_start_ofs,
+ CONFIG_SYS_FLASH_BASE + (__bss_end - __bss_start),
&flash_info[0]);
return size;
*/
flash_protect (FLAG_PROTECT_SET,
CONFIG_SYS_FLASH_BASE,
- CONFIG_SYS_FLASH_BASE + _bss_start_ofs,
+ CONFIG_SYS_FLASH_BASE + (__bss_end - __bss_start),
&flash_info[0]);
return size;
obj-y := paz00.o
-include ../../nvidia/common/common.mk
+include $(srctree)/board/nvidia/common/common.mk
static struct cpsw_slave_data cpsw_slave = {
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
- .phy_id = 0,
+ .phy_addr = 0,
.phy_if = PHY_INTERFACE_MODE_RGMII,
};
*(.__rel_dyn_end)
}
- _end = .;
+ .end :
+ {
+ *(.__end)
+ }
+
+ _image_binary_end = .;
/*
* Deprecated: this MMU section is used by pxa at present but
KEEP(*(.__bss_end));
}
- /DISCARD/ : { *(.dynsym) }
- /DISCARD/ : { *(.dynstr*) }
- /DISCARD/ : { *(.dynamic*) }
- /DISCARD/ : { *(.plt*) }
- /DISCARD/ : { *(.interp*) }
- /DISCARD/ : { *(.gnu*) }
+ .dynsym _image_binary_end : { *(.dynsym) }
+ .hash : { *(.hash) }
+ .got.plt : { *(.got.plt) }
+ .dynbss : { *(.dynbss) }
+ .dynstr : { *(.dynstr*) }
+ .dynamic : { *(.dynamic*) }
+ .plt : { *(.plt*) }
+ .interp : { *(.interp*) }
+ .gnu : { *(.gnu*) }
+ .ARM.exidx : { *(.ARM.exidx*) }
}
obj-y := trimslice.o
-include ../../nvidia/common/common.mk
+include $(srctree)/board/nvidia/common/common.mk
obj-y += init.o
obj-y += bootscript.o
-$(obj)bootscript.c: $(obj)bootscript.image
- od -t x1 -v -A x $^ | awk -f x2c.awk > $@
+$(obj)/bootscript.c: $(obj)/bootscript.image
+ od -t x1 -v -A x $^ | awk -f $(srctree)/$(src)/x2c.awk > $@
-$(obj)bootscript.image: $(src)bootscript.hush $(src)Makefile
- -$(OBJTREE)/tools/mkimage -A ppc -O linux -T script -C none -a 0 -e 0 -n bootscript -d $(src)bootscript.hush $@
+$(obj)/bootscript.image: $(src)/bootscript.hush
+ -$(OBJTREE)/tools/mkimage -A ppc -O linux -T script -C none -a 0 -e 0 -n bootscript -d $< $@
+
+clean-files := bootscript.c bootscript.image
\ No newline at end of file
} >.sram
__image_copy_end = .;
- _end = .;
+
+ .end :
+ {
+ *(.__end)
+ }
}
__bss_end = .;
}
- _end = .;
+ .end :
+ {
+ *(.__end)
+ }
}
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := dvlhost.o watchdog.o
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Michael Schwingen, michael@schwingen.org
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <malloc.h>
-#include <asm/arch/ixp425.h>
-#include <asm/io.h>
-#include <miiphy.h>
-#ifdef CONFIG_PCI
-#include <pci.h>
-#include <asm/arch/ixp425pci.h>
-#endif
-
-#include "dvlhost_hw.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- /* CS1: LED Latch */
- writel(0xBFFF0002, IXP425_EXP_CS1);
- return 0;
-}
-
-int board_init(void)
-{
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0x00000100;
-
- /* Setup GPIOs used as output */
- GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_WDGTRIGGER);
- GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DLAN_PAIRING);
- GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PCIRST);
-
- /*
- * LED latch enable and watchdog enable are tied to the same GPIO,
- * so we need to trigger the watchdog if we want to enable the LEDs.
- */
-#ifdef CONFIG_HW_WATCHDOG
- GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_WDG_LED_EN);
-#else
- GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_WDG_LED_EN);
-#endif
-
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_WDGTRIGGER);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DLAN_PAIRING);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_WDG_LED_EN);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCIRST);
-
- /* Setup GPIOs for Interrupt inputs */
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_BTN_WLAN);
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_BTN_PAIRING);
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_BTN_RESET);
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_IRQA);
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_IRQB);
-
- /* Setup GPIO's for 33MHz clock output */
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
- writel(0x01FF01FF, IXP425_GPIO_GPCLKR);
-
- /* turn off all LEDs */
- writew(0x0000, DVLHOST_LED_LATCH);
-
- udelay(533);
- GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_PCIRST);
-
- return 0;
-}
-
-/* Check Board Identity */
-int checkboard(void)
-{
- char *s = getenv("serial#");
-
- puts("Board: dLAN 200AV (dvlhost)");
-
- if (s != NULL) {
- puts(", serial# ");
- puts(s);
- }
- putc('\n');
-
- return 0;
-}
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
- return 0;
-}
-
-#ifdef CONFIG_PCI
-struct pci_controller hose;
-
-void pci_init_board(void)
-{
- pci_ixp_init(&hose);
-}
-#endif
-
-void reset_phy(void)
-{
- /* init IcPlus IP175C ethernet switch to native IP175C mode */
- miiphy_write("NPE1", 29, 31, 0x175C);
-}
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Michael Schwingen, michael@schwingen.org
- *
- * hardware register definitions for the
- * dLAN200 AV Wireless G ("dvlhost") board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _DVLHOST_HW_H
-#define _DVLHOST_HW_H
-
-/*
- * GPIO settings
- */
-#define CONFIG_SYS_GPIO_WDGTRIGGER 0 /* Out */
-#define CONFIG_SYS_GPIO_BTN_WLAN 1
-#define CONFIG_SYS_GPIO_BTN_PAIRING 6
-#define CONFIG_SYS_GPIO_DLAN_PAIRING 7 /* Out */
-#define CONFIG_SYS_GPIO_BTN_RESET 9
-#define CONFIG_SYS_GPIO_IRQB 10
-#define CONFIG_SYS_GPIO_IRQA 11
-#define CONFIG_SYS_GPIO_WDG_LED_EN 12 /* Out */
-#define CONFIG_SYS_GPIO_PCIRST 13 /* Out */
-#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */
-#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */
-
-#define DVLHOST_LED_LATCH IXP425_EXP_BUS_CS1_BASE_PHYS
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
-OUTPUT_ARCH (arm)
-ENTRY (_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN (4);
- .text : {
- *(.__image_copy_start)
- arch/arm/cpu/ixp/start.o(.text*)
- net/built-in.o(.text*)
- board/dvlhost/built-in.o(.text*)
- arch/arm/cpu/ixp/built-in.o(.text*)
- drivers/serial/built-in.o(.text*)
-
- . = env_offset;
- common/env_embedded.o(.ppcenv)
- *(.text*)
- }
-
- . = ALIGN (4);
- .rodata : {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- . = ALIGN (4);
- .data : {
- *(.data*)
- }
- . = ALIGN (4);
- .got : {
- *(.got)
- }
- . =.;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = ALIGN (4);
-
- .image_copy_end :
- {
- *(.__image_copy_end)
- }
-
- .rel_dyn_start :
- {
- *(.__rel_dyn_start)
- }
-
- .rel.dyn : {
- *(.rel*)
- }
-
- .rel_dyn_end :
- {
- *(.__rel_dyn_end)
- }
-
- _end = .;
-
-/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
- */
-
- .bss_start __rel_dyn_start (OVERLAY) : {
- KEEP(*(.__bss_start));
- __bss_base = .;
- }
-
- .bss __bss_base (OVERLAY) : {
- *(.bss*)
- . = ALIGN(4);
- __bss_limit = .;
- }
- .bss_end __bss_limit (OVERLAY) : {
- KEEP(*(.__bss_end));
- }
-
- .dynsym _end : { *(.dynsym) }
- .dynbss : { *(.dynbss) }
- .dynstr : { *(.dynstr*) }
- .dynamic : { *(.dynamic*) }
- .hash : { *(.hash*) }
- .plt : { *(.plt*) }
- .interp : { *(.interp*) }
- .gnu : { *(.gnu*) }
- .ARM.exidx : { *(.ARM.exidx*) }
-}
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Michael Schwingen, michael@schwingen.org
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/io.h>
-#include "dvlhost_hw.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_HW_WATCHDOG
-#include <watchdog.h>
-#include <asm/arch/ixp425.h>
-
-void hw_watchdog_reset(void)
-{
- unsigned int x;
- x = readl(IXP425_GPIO_GPOUTR);
- x ^= (1 << (CONFIG_SYS_GPIO_WDGTRIGGER));
- writel(x, IXP425_GPIO_GPOUTR);
-}
-
-#endif /* CONFIG_HW_WATCHDOG */
#define CONFIG_SYS_LOAD_ADDR 0x00100000
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
DECLARE_GLOBAL_DATA_PTR;
-ulong get_effective_memsize(void)
+phys_size_t get_effective_memsize(void)
{
return CONFIG_SYS_L2_SIZE;
}
endif
endif
-ifndef MINIMAL
+ifdef MINIMAL
+# necessary to create built-in.o
+obj- := __dummy__.o
+else
obj-$(CONFIG_FSL_CADMUS) += cadmus.o
obj-$(CONFIG_FSL_VIA) += cds_via.o
obj-$(CONFIG_FMAN_ENET) += fman.o
*(.__rel_dyn_end)
}
- _end = .;
+ .end :
+ {
+ *(.__end)
+ }
+
+ _image_binary_end = .;
/*
* Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
KEEP(*(.__bss_end));
}
- .dynsym _end : { *(.dynsym) }
+ .dynsym _image_binary_end : { *(.dynsym) }
.dynbss : { *(.dynbss) }
.dynstr : { *(.dynstr*) }
.dynamic : { *(.dynamic*) }
return 0;
}
+#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
u32 cpurev;
printf("Reset cause: %s\n", get_reset_cause());
return 0;
}
+#endif
/*
* Do not overwrite the console
else
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
+
obj-y += p1010rdb.o
obj-y += ddr.o
obj-y += law.o
--- /dev/null
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+#include <i2c.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+ return CONFIG_SYS_L2_SIZE;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;
+
+ console_init_f();
+
+ /* Clock configuration to access CPLD using IFC(GPCM) */
+ setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
+
+#ifdef CONFIG_P1010RDB_PB
+ setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
+#endif
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+#ifdef CONFIG_SPL_MMC_BOOT
+ puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ puts("\nSPI Flash boot...\n");
+#endif
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ /* Pointer is writable since we allocated a register for it */
+ gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+ bd_t *bd;
+
+ memset(gd, 0, sizeof(gd_t));
+ bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd->bd = bd;
+ bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
+ bd->bi_memsize = CONFIG_SYS_L2_SIZE;
+
+ probecpu();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifndef CONFIG_SPL_NAND_BOOT
+ env_init();
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_initialize(bd);
+#endif
+
+ /* relocate environment function pointers etc. */
+#ifdef CONFIG_SPL_NAND_BOOT
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd->env_valid = 1;
+#else
+ env_relocate();
+#endif
+
+ i2c_init_all();
+
+ gd->ram_size = initdram(0);
+#ifdef CONFIG_SPL_NAND_BOOT
+ puts("\nTertiary program loader running in sram...");
+#else
+ puts("\nSecond program loader running in sram...");
+#endif
+
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+ nand_boot();
+#endif
+}
DECLARE_GLOBAL_DATA_PTR;
-
-void sdram_init(void)
-{
- struct ccsr_ddr __iomem *ddr =
- (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
- u32 ddr_ratio;
- unsigned long ddr_freq_mhz;
-
- ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
- ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
- ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 1000000;
-
- /* mask off E bit */
- u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR));
-
- __raw_writel(CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE, &ddr->sdram_cfg);
- __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
- __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
- __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
- __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
-
- if (ddr_freq_mhz < 700) {
- __raw_writel(CONFIG_SYS_DDR_TIMING_3_667, &ddr->timing_cfg_3);
- __raw_writel(CONFIG_SYS_DDR_TIMING_0_667, &ddr->timing_cfg_0);
- __raw_writel(CONFIG_SYS_DDR_TIMING_1_667, &ddr->timing_cfg_1);
- __raw_writel(CONFIG_SYS_DDR_TIMING_2_667, &ddr->timing_cfg_2);
- __raw_writel(CONFIG_SYS_DDR_MODE_1_667, &ddr->sdram_mode);
- __raw_writel(CONFIG_SYS_DDR_MODE_2_667, &ddr->sdram_mode_2);
- __raw_writel(CONFIG_SYS_DDR_INTERVAL_667, &ddr->sdram_interval);
- __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_667, &ddr->sdram_clk_cntl);
- __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_667, &ddr->ddr_wrlvl_cntl);
- } else {
- __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
- __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
- __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
- __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
- __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode);
- __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2);
- __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval);
- __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl);
- __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl);
- }
-
- __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
- __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
- __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
-
- /* P1014 and it's derivatives support max 16bit DDR width */
- if (svr == SVR_P1014) {
- __raw_writel(ddr->sdram_cfg & ~SDRAM_CFG_DBW_MASK, &ddr->sdram_cfg);
- __raw_writel(ddr->sdram_cfg | SDRAM_CFG_16_BE, &ddr->sdram_cfg);
- /* For CS0_BNDS we divide the start and end address by 2, so we can just
- * shift the entire register to achieve the desired result and the mask
- * the value so we don't write reserved fields */
- __raw_writel((CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff, &ddr->cs0_bnds);
- }
-
- asm volatile("sync;isync");
- udelay(500);
-
- /* Let the controller go */
- out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
-
- set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1);
-}
-
void board_init_f(ulong bootflag)
{
u32 plat_ratio;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+ set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+ set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#endif
+
/* initialize selected port with appropriate baud rate */
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
plat_ratio >>= 1;
puts("\nNAND boot... ");
- /* Initialize the DDR3 */
- sdram_init();
-
/* copy code to RAM and jump to it - this should not return */
/* NOTE - code has to be copied out of NAND buffer before
* other blocks can be read.
void board_init_r(gd_t *gd, ulong dest_addr)
{
+ puts("\nSecond program loader running in sram...");
nand_boot();
}
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_1M, 1),
-#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
+#if defined(CONFIG_SYS_RAMBOOT) || \
+ (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 8, BOOKE_PAGESZ_1G, 1)
+ 0, 8, BOOKE_PAGESZ_1G, 1),
+#endif
+
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+ /* *I*G - L2SRAM */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+ 0, 11, BOOKE_PAGESZ_256K, 1)
#endif
};
99999000, 11111000, 12499800, 13333200
};
-ulong get_effective_memsize(void)
+phys_size_t get_effective_memsize(void)
{
return CONFIG_SYS_L2_SIZE;
}
99999000, 11111000, 12499800, 13333200
};
-ulong get_effective_memsize(void)
+phys_size_t get_effective_memsize(void)
{
return CONFIG_SYS_L2_SIZE;
}
obj-$(CONFIG_PCI) += pci.o
obj-y += law.o
obj-y += tlb.o
+obj-y += eth.o
0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB
0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB
0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
-0xED300000 0xEFF3FFFF rootfs (alt bank) 44MB + 256KB
-0xEC800000 0xEC8FFFF Hardware device tree (alt bank) 1MB
+0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
+0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB
0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB
0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
-0xE9300000 0xEBF3FFFF rootfs (current bank) 44MB + 256KB
+0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB
0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
0xE8000000 0xE801FFFF RCW (current bank) 128KB
--- /dev/null
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * The RGMII PHYs are provided by the two on-board PHY connected to
+ * dTSEC instances 4 and 5. The SGMII PHYs are provided by one on-board
+ * PHY or by the standard four-port SGMII riser card (VSC).
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/fsl_serdes.h>
+#include <asm/immap_85xx.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <asm/fsl_dtsec.h>
+
+#include "../common/fman.h"
+#include "../common/qixis.h"
+
+#include "t1040qds_qixis.h"
+
+#ifdef CONFIG_FMAN_ENET
+ /* - In T1040 there are only 8 SERDES lanes, spread across 2 SERDES banks.
+ * Bank 1 -> Lanes A, B, C, D
+ * Bank 2 -> Lanes E, F, G, H
+ */
+
+ /* Mapping of 8 SERDES lanes to T1040 QDS board slots. A value of '0' here
+ * means that the mapping must be determined dynamically, or that the lane
+ * maps to something other than a board slot.
+ */
+static u8 lane_to_slot[] = {
+ 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
+ * housed.
+ */
+static int riser_phy_addr[] = {
+ CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR,
+ CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR,
+ CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR,
+ CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR,
+};
+
+/* Slot2 does not have EMI connections */
+#define EMI_NONE 0xFFFFFFFF
+#define EMI1_RGMII0 0
+#define EMI1_RGMII1 1
+#define EMI1_SLOT1 2
+#define EMI1_SLOT3 3
+#define EMI1_SLOT4 4
+#define EMI1_SLOT5 5
+#define EMI1_SLOT6 6
+#define EMI1_SLOT7 7
+#define EMI2 8
+
+static int mdio_mux[NUM_FM_PORTS];
+
+static const char * const mdio_names[] = {
+ "T1040_QDS_MDIO0",
+ "T1040_QDS_MDIO1",
+ "T1040_QDS_MDIO2",
+ "T1040_QDS_MDIO3",
+ "T1040_QDS_MDIO4",
+ "T1040_QDS_MDIO5",
+ "T1040_QDS_MDIO6",
+ "T1040_QDS_MDIO7",
+};
+
+struct t1040_qds_mdio {
+ u8 muxval;
+ struct mii_dev *realbus;
+};
+
+static const char *t1040_qds_mdio_name_for_muxval(u8 muxval)
+{
+ return mdio_names[muxval];
+}
+
+struct mii_dev *mii_dev_for_muxval(u8 muxval)
+{
+ struct mii_dev *bus;
+ const char *name = t1040_qds_mdio_name_for_muxval(muxval);
+
+ if (!name) {
+ printf("No bus for muxval %x\n", muxval);
+ return NULL;
+ }
+
+ bus = miiphy_get_dev_by_name(name);
+
+ if (!bus) {
+ printf("No bus by name %s\n", name);
+ return NULL;
+ }
+
+ return bus;
+}
+
+static void t1040_qds_mux_mdio(u8 muxval)
+{
+ u8 brdcfg4;
+ if (muxval <= 7) {
+ brdcfg4 = QIXIS_READ(brdcfg[4]);
+ brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
+ brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
+ QIXIS_WRITE(brdcfg[4], brdcfg4);
+ }
+}
+
+static int t1040_qds_mdio_read(struct mii_dev *bus, int addr, int devad,
+ int regnum)
+{
+ struct t1040_qds_mdio *priv = bus->priv;
+
+ t1040_qds_mux_mdio(priv->muxval);
+
+ return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int t1040_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
+ int regnum, u16 value)
+{
+ struct t1040_qds_mdio *priv = bus->priv;
+
+ t1040_qds_mux_mdio(priv->muxval);
+
+ return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int t1040_qds_mdio_reset(struct mii_dev *bus)
+{
+ struct t1040_qds_mdio *priv = bus->priv;
+
+ return priv->realbus->reset(priv->realbus);
+}
+
+static int t1040_qds_mdio_init(char *realbusname, u8 muxval)
+{
+ struct t1040_qds_mdio *pmdio;
+ struct mii_dev *bus = mdio_alloc();
+
+ if (!bus) {
+ printf("Failed to allocate t1040_qds MDIO bus\n");
+ return -1;
+ }
+
+ pmdio = malloc(sizeof(*pmdio));
+ if (!pmdio) {
+ printf("Failed to allocate t1040_qds private data\n");
+ free(bus);
+ return -1;
+ }
+
+ bus->read = t1040_qds_mdio_read;
+ bus->write = t1040_qds_mdio_write;
+ bus->reset = t1040_qds_mdio_reset;
+ sprintf(bus->name, t1040_qds_mdio_name_for_muxval(muxval));
+
+ pmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+ if (!pmdio->realbus) {
+ printf("No bus with name %s\n", realbusname);
+ free(bus);
+ free(pmdio);
+ return -1;
+ }
+
+ pmdio->muxval = muxval;
+ bus->priv = pmdio;
+
+ return mdio_register(bus);
+}
+
+/*
+ * Initialize the lane_to_slot[] array.
+ *
+ * On the T1040QDS board the mapping is controlled by ?? register.
+ */
+static void initialize_lane_to_slot(void)
+{
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ int serdes1_prtcl = (in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL)
+ >> FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+ QIXIS_WRITE(cms[0], 0x07);
+
+ switch (serdes1_prtcl) {
+ case 0x60:
+ case 0x66:
+ case 0x67:
+ case 0x69:
+ lane_to_slot[1] = 7;
+ lane_to_slot[2] = 6;
+ lane_to_slot[3] = 5;
+ break;
+ case 0x86:
+ lane_to_slot[1] = 7;
+ lane_to_slot[2] = 7;
+ lane_to_slot[3] = 7;
+ break;
+ case 0x87:
+ lane_to_slot[1] = 7;
+ lane_to_slot[2] = 7;
+ lane_to_slot[3] = 7;
+ lane_to_slot[7] = 7;
+ break;
+ case 0x89:
+ lane_to_slot[1] = 7;
+ lane_to_slot[2] = 7;
+ lane_to_slot[3] = 7;
+ lane_to_slot[7] = 7;
+ break;
+ case 0x8d:
+ lane_to_slot[1] = 7;
+ lane_to_slot[2] = 7;
+ lane_to_slot[3] = 7;
+ lane_to_slot[5] = 3;
+ lane_to_slot[6] = 3;
+ lane_to_slot[7] = 3;
+ break;
+ case 0x8F:
+ case 0x85:
+ lane_to_slot[1] = 7;
+ lane_to_slot[2] = 6;
+ lane_to_slot[3] = 5;
+ lane_to_slot[6] = 3;
+ lane_to_slot[7] = 3;
+ break;
+ case 0xA5:
+ lane_to_slot[1] = 7;
+ lane_to_slot[6] = 3;
+ lane_to_slot[7] = 3;
+ break;
+ case 0xA7:
+ lane_to_slot[1] = 7;
+ lane_to_slot[7] = 7;
+ break;
+ case 0xAA:
+ lane_to_slot[1] = 7;
+ lane_to_slot[6] = 7;
+ lane_to_slot[7] = 7;
+ break;
+ case 0x40:
+ lane_to_slot[2] = 7;
+ lane_to_slot[3] = 7;
+ break;
+ default:
+ printf("qds: Fman: Unsupported SerDes Protocol 0x%02x\n",
+ serdes1_prtcl);
+ break;
+ }
+}
+
+/*
+ * Given the following ...
+ *
+ * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
+ * compatible string and 'addr' physical address)
+ *
+ * 2) An Fman port
+ *
+ * ... update the phy-handle property of the Ethernet node to point to the
+ * right PHY. This assumes that we already know the PHY for each port.
+ *
+ * The offset of the Fman Ethernet node is also passed in for convenience, but
+ * it is not used, and we recalculate the offset anyway.
+ *
+ * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
+ * Inside the Fman, "ports" are things that connect to MACs. We only call them
+ * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
+ * and ports are the same thing.
+ *
+ */
+void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
+ enum fm_port port, int offset)
+{
+ phy_interface_t intf = fm_info_get_enet_if(port);
+ char phy[16];
+
+ /* The RGMII PHY is identified by the MAC connected to it */
+ if (intf == PHY_INTERFACE_MODE_RGMII) {
+ sprintf(phy, "rgmii_phy%u", port == FM1_DTSEC4 ? 1 : 2);
+ fdt_set_phy_handle(fdt, compat, addr, phy);
+ }
+
+ /* The SGMII PHY is identified by the MAC connected to it */
+ if (intf == PHY_INTERFACE_MODE_SGMII) {
+ int lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1
+ + port);
+ u8 slot;
+ if (lane < 0)
+ return;
+ slot = lane_to_slot[lane];
+ if (slot) {
+ /* Slot housing a SGMII riser card */
+ sprintf(phy, "phy_s%x_%02x", slot,
+ (fm_info_get_phy_address(port - FM1_DTSEC1)-
+ CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + 1));
+ fdt_set_phy_handle(fdt, compat, addr, phy);
+ }
+ }
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+ int i, lane, idx;
+
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ idx = i - FM1_DTSEC1;
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_SGMII:
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ SGMII_FM1_DTSEC1 + idx);
+ if (lane < 0)
+ break;
+
+ switch (mdio_mux[i]) {
+ case EMI1_SLOT3:
+ fdt_status_okay_by_alias(fdt, "emi1_slot3");
+ break;
+ case EMI1_SLOT5:
+ fdt_status_okay_by_alias(fdt, "emi1_slot5");
+ break;
+ case EMI1_SLOT6:
+ fdt_status_okay_by_alias(fdt, "emi1_slot6");
+ break;
+ case EMI1_SLOT7:
+ fdt_status_okay_by_alias(fdt, "emi1_slot7");
+ break;
+ }
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ if (i == FM1_DTSEC4)
+ fdt_status_okay_by_alias(fdt, "emi1_rgmii0");
+
+ if (i == FM1_DTSEC5)
+ fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
+ break;
+ default:
+ break;
+ }
+ }
+}
+#endif /* #ifdef CONFIG_FMAN_ENET */
+
+static void set_brdcfg9_for_gtx_clk(void)
+{
+ u8 brdcfg9;
+ brdcfg9 = QIXIS_READ(brdcfg[9]);
+ brdcfg9 |= (1 << 5);
+ QIXIS_WRITE(brdcfg[9], brdcfg9);
+}
+
+void t1040_handle_phy_interface_sgmii(int i)
+{
+ int lane, idx, slot;
+ idx = i - FM1_DTSEC1;
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ SGMII_FM1_DTSEC1 + idx);
+
+ if (lane < 0)
+ return;
+ slot = lane_to_slot[lane];
+
+ switch (slot) {
+ case 1:
+ mdio_mux[i] = EMI1_SLOT1;
+ fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ case 3:
+ if (FM1_DTSEC4 == i)
+ fm_info_set_phy_address(i, riser_phy_addr[0]);
+ if (FM1_DTSEC5 == i)
+ fm_info_set_phy_address(i, riser_phy_addr[1]);
+
+ mdio_mux[i] = EMI1_SLOT3;
+
+ fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ case 4:
+ mdio_mux[i] = EMI1_SLOT4;
+ fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ case 5:
+ /* Slot housing a SGMII riser card? */
+ fm_info_set_phy_address(i, riser_phy_addr[0]);
+ mdio_mux[i] = EMI1_SLOT5;
+ fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ case 6:
+ /* Slot housing a SGMII riser card? */
+ fm_info_set_phy_address(i, riser_phy_addr[0]);
+ mdio_mux[i] = EMI1_SLOT6;
+ fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ case 7:
+ if (FM1_DTSEC1 == i)
+ fm_info_set_phy_address(i, riser_phy_addr[0]);
+ if (FM1_DTSEC2 == i)
+ fm_info_set_phy_address(i, riser_phy_addr[1]);
+ if (FM1_DTSEC3 == i)
+ fm_info_set_phy_address(i, riser_phy_addr[2]);
+
+ mdio_mux[i] = EMI1_SLOT7;
+ fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ default:
+ break;
+ }
+ fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+}
+void t1040_handle_phy_interface_rgmii(int i)
+{
+ fm_info_set_phy_address(i, i == FM1_DTSEC5 ?
+ CONFIG_SYS_FM1_DTSEC5_PHY_ADDR :
+ CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
+ mdio_mux[i] = (i == FM1_DTSEC5) ? EMI1_RGMII1 :
+ EMI1_RGMII0;
+ fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+}
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+ struct memac_mdio_info memac_mdio_info;
+ unsigned int i;
+
+ printf("Initializing Fman\n");
+ set_brdcfg9_for_gtx_clk();
+
+ initialize_lane_to_slot();
+
+ /* Initialize the mdio_mux array so we can recognize empty elements */
+ for (i = 0; i < NUM_FM_PORTS; i++)
+ mdio_mux[i] = EMI_NONE;
+
+ memac_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+ memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+ /* Register the real 1G MDIO bus */
+ fm_memac_mdio_init(bis, &memac_mdio_info);
+
+ /* Register the muxing front-ends to the MDIO buses */
+ t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII0);
+ t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
+ t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
+ t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
+ t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
+ t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
+ t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
+ t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
+
+ /*
+ * Program on board RGMII PHY addresses. If the SGMII Riser
+ * card used, we'll override the PHY address later. For any DTSEC that
+ * is RGMII, we'll also override its PHY address later. We assume that
+ * DTSEC4 and DTSEC5 are used for RGMII.
+ */
+ fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
+
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_QSGMII:
+ break;
+ case PHY_INTERFACE_MODE_SGMII:
+ t1040_handle_phy_interface_sgmii(i);
+ break;
+
+ case PHY_INTERFACE_MODE_RGMII:
+ /* Only DTSEC4 and DTSEC5 can be routed to RGMII */
+ t1040_handle_phy_interface_rgmii(i);
+ break;
+ default:
+ break;
+ }
+ }
+
+ cpu_eth_init(bis);
+#endif
+
+ return pci_eth_init(bis);
+}
#ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_ethernet(blob);
+ fdt_fixup_board_enet(blob);
#endif
}
obj-y += t104xrdb.o
obj-y += ddr.o
+obj-y += eth.o
obj-$(CONFIG_PCI) += pci.o
obj-y += law.o
obj-y += tlb.o
0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB
0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB
0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
-0xED300000 0xEFF3FFFF rootfs (alt bank) 44MB + 256KB
-0xEC800000 0xEC8FFFF Hardware device tree (alt bank) 1MB
+0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
+0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB
0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB
0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
-0xE9300000 0xEBF3FFFF rootfs (current bank) 44MB + 256KB
+0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB
0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
0xE8000000 0xE801FFFF RCW (current bank) 128KB
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/immap_85xx.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <asm/fsl_dtsec.h>
+
+#include "../common/fman.h"
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+ struct memac_mdio_info memac_mdio_info;
+ unsigned int i;
+ int phy_addr = 0;
+ printf("Initializing Fman\n");
+
+ memac_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+ memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+ /* Register the real 1G MDIO bus */
+ fm_memac_mdio_init(bis, &memac_mdio_info);
+
+ /*
+ * Program on board RGMII, SGMII PHY addresses.
+ */
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ int idx = i - FM1_DTSEC1;
+
+ switch (fm_info_get_enet_if(i)) {
+#ifdef CONFIG_T1040RDB
+ case PHY_INTERFACE_MODE_SGMII:
+ /* T1040RDB only supports SGMII on DTSEC3 */
+ fm_info_set_phy_address(FM1_DTSEC3,
+ CONFIG_SYS_SGMII1_PHY_ADDR);
+#endif
+ case PHY_INTERFACE_MODE_RGMII:
+ if (FM1_DTSEC4 == i)
+ phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR;
+ if (FM1_DTSEC5 == i)
+ phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR;
+ fm_info_set_phy_address(i, phy_addr);
+ break;
+ case PHY_INTERFACE_MODE_QSGMII:
+ fm_info_set_phy_address(i, 0);
+ break;
+ case PHY_INTERFACE_MODE_NONE:
+ fm_info_set_phy_address(i, 0);
+ break;
+ default:
+ printf("Fman1: DTSEC%u set to unknown interface %i\n",
+ idx + 1, fm_info_get_enet_if(i));
+ fm_info_set_phy_address(i, 0);
+ break;
+ }
+ fm_info_set_mdio(i,
+ miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+ }
+
+ cpu_eth_init(bis);
+#endif
+
+ return pci_eth_init(bis);
+}
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_T2080QDS) += t2080qds.o
-obj-$(CONFIG_T2080QDS) += eth_t2080qds.o
+obj-$(CONFIG_T2080QDS) += t208xqds.o
+obj-$(CONFIG_T2080QDS) += eth_t208xqds.o
+obj-$(CONFIG_T2081QDS) += t208xqds.o
+obj-$(CONFIG_T2081QDS) += eth_t208xqds.o
obj-$(CONFIG_PCI) += pci.o
obj-y += ddr.o
obj-y += law.o
#include <asm/fsl_serdes.h>
#include "../common/qixis.h"
#include "../common/fman.h"
-#include "t2080qds_qixis.h"
+#include "t208xqds_qixis.h"
#define EMI_NONE 0xFFFFFFFF
#define EMI1_RGMII1 0
#define EMI1_RGMII2 1
#define EMI1_SLOT1 2
+#if defined(CONFIG_T2080QDS)
#define EMI1_SLOT2 6
#define EMI1_SLOT3 3
#define EMI1_SLOT4 4
#define EMI1_SLOT5 5
-#define EMI2 7
+#elif defined(CONFIG_T2081QDS)
+#define EMI1_SLOT2 3
+#define EMI1_SLOT3 4
+#define EMI1_SLOT5 5
+#define EMI1_SLOT6 6
+#define EMI1_SLOT7 7
+#endif
+#define EMI2 8
static int mdio_mux[NUM_FM_PORTS];
static const char * const mdio_names[] = {
+#if defined(CONFIG_T2080QDS)
"T2080QDS_MDIO_RGMII1",
"T2080QDS_MDIO_RGMII2",
"T2080QDS_MDIO_SLOT1",
"T2080QDS_MDIO_SLOT5",
"T2080QDS_MDIO_SLOT2",
"T2080QDS_MDIO_10GC",
+#elif defined(CONFIG_T2081QDS)
+ "T2081QDS_MDIO_RGMII1",
+ "T2081QDS_MDIO_RGMII2",
+ "T2081QDS_MDIO_SLOT1",
+ "T2081QDS_MDIO_SLOT2",
+ "T2081QDS_MDIO_SLOT3",
+ "T2081QDS_MDIO_SLOT5",
+ "T2081QDS_MDIO_SLOT6",
+ "T2081QDS_MDIO_SLOT7",
+ "T2081QDS_MDIO_10GC",
+#endif
};
/* Map SerDes1 8 lanes to default slot, will be initialized dynamically */
+#if defined(CONFIG_T2080QDS)
static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1};
+#elif defined(CONFIG_T2081QDS)
+static u8 lane_to_slot[] = {2, 2, 2, 2, 1, 1, 1, 1};
+#endif
-static const char *T2080qds_mdio_name_for_muxval(u8 muxval)
+static const char *t208xqds_mdio_name_for_muxval(u8 muxval)
{
return mdio_names[muxval];
}
struct mii_dev *mii_dev_for_muxval(u8 muxval)
{
struct mii_dev *bus;
- const char *name = T2080qds_mdio_name_for_muxval(muxval);
+ const char *name = t208xqds_mdio_name_for_muxval(muxval);
if (!name) {
printf("No bus for muxval %x\n", muxval);
return bus;
}
-struct T2080qds_mdio {
+struct t208xqds_mdio {
u8 muxval;
struct mii_dev *realbus;
};
-static void T2080qds_mux_mdio(u8 muxval)
+static void t208xqds_mux_mdio(u8 muxval)
{
u8 brdcfg4;
- if (muxval < 7) {
+ if (muxval < 8) {
brdcfg4 = QIXIS_READ(brdcfg[4]);
brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
}
}
-static int T2080qds_mdio_read(struct mii_dev *bus, int addr, int devad,
+static int t208xqds_mdio_read(struct mii_dev *bus, int addr, int devad,
int regnum)
{
- struct T2080qds_mdio *priv = bus->priv;
+ struct t208xqds_mdio *priv = bus->priv;
- T2080qds_mux_mdio(priv->muxval);
+ t208xqds_mux_mdio(priv->muxval);
return priv->realbus->read(priv->realbus, addr, devad, regnum);
}
-static int T2080qds_mdio_write(struct mii_dev *bus, int addr, int devad,
+static int t208xqds_mdio_write(struct mii_dev *bus, int addr, int devad,
int regnum, u16 value)
{
- struct T2080qds_mdio *priv = bus->priv;
+ struct t208xqds_mdio *priv = bus->priv;
- T2080qds_mux_mdio(priv->muxval);
+ t208xqds_mux_mdio(priv->muxval);
return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
}
-static int T2080qds_mdio_reset(struct mii_dev *bus)
+static int t208xqds_mdio_reset(struct mii_dev *bus)
{
- struct T2080qds_mdio *priv = bus->priv;
+ struct t208xqds_mdio *priv = bus->priv;
return priv->realbus->reset(priv->realbus);
}
-static int T2080qds_mdio_init(char *realbusname, u8 muxval)
+static int t208xqds_mdio_init(char *realbusname, u8 muxval)
{
- struct T2080qds_mdio *pmdio;
+ struct t208xqds_mdio *pmdio;
struct mii_dev *bus = mdio_alloc();
if (!bus) {
- printf("Failed to allocate T2080QDS MDIO bus\n");
+ printf("Failed to allocate t208xqds MDIO bus\n");
return -1;
}
pmdio = malloc(sizeof(*pmdio));
if (!pmdio) {
- printf("Failed to allocate T2080QDS private data\n");
+ printf("Failed to allocate t208xqds private data\n");
free(bus);
return -1;
}
- bus->read = T2080qds_mdio_read;
- bus->write = T2080qds_mdio_write;
- bus->reset = T2080qds_mdio_reset;
- sprintf(bus->name, T2080qds_mdio_name_for_muxval(muxval));
+ bus->read = t208xqds_mdio_read;
+ bus->write = t208xqds_mdio_write;
+ bus->reset = t208xqds_mdio_reset;
+ sprintf(bus->name, t208xqds_mdio_name_for_muxval(muxval));
pmdio->realbus = miiphy_get_dev_by_name(realbusname);
pmdio->muxval = muxval;
bus->priv = pmdio;
-
return mdio_register(bus);
}
if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
phy = fm_info_get_phy_address(port);
switch (port) {
+#if defined(CONFIG_T2080QDS)
case FM1_DTSEC1:
case FM1_DTSEC2:
case FM1_DTSEC9:
case FM1_DTSEC10:
- sprintf(alias, "phy_sgmii_s3_%x", phy);
- fdt_set_phy_handle(fdt, compat, addr, alias);
- fdt_status_okay_by_alias(fdt, "emi1_slot3");
+ if (mdio_mux[port] == EMI1_SLOT2) {
+ sprintf(alias, "phy_sgmii_s2_%x", phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, "emi1_slot2");
+ } else if (mdio_mux[port] == EMI1_SLOT3) {
+ sprintf(alias, "phy_sgmii_s3_%x", phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, "emi1_slot3");
+ }
break;
case FM1_DTSEC5:
case FM1_DTSEC6:
fdt_status_okay_by_alias(fdt, "emi1_slot2");
}
break;
+#elif defined(CONFIG_T2081QDS)
+ case FM1_DTSEC1:
+ case FM1_DTSEC2:
+ case FM1_DTSEC5:
+ case FM1_DTSEC6:
+ case FM1_DTSEC9:
+ case FM1_DTSEC10:
+ if (mdio_mux[port] == EMI1_SLOT2) {
+ sprintf(alias, "phy_sgmii_s2_%x", phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, "emi1_slot2");
+ } else if (mdio_mux[port] == EMI1_SLOT3) {
+ sprintf(alias, "phy_sgmii_s3_%x", phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, "emi1_slot3");
+ } else if (mdio_mux[port] == EMI1_SLOT5) {
+ sprintf(alias, "phy_sgmii_s5_%x", phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, "emi1_slot5");
+ } else if (mdio_mux[port] == EMI1_SLOT6) {
+ sprintf(alias, "phy_sgmii_s6_%x", phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, "emi1_slot6");
+ } else if (mdio_mux[port] == EMI1_SLOT7) {
+ sprintf(alias, "phy_sgmii_s7_%x", phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, "emi1_slot7");
+ }
+ break;
+#endif
default:
break;
}
}
/*
- * This function reads RCW to check if Serdes1{E,F,G,H} is configured
- * as slot 1/2/3 and update the lane_to_slot[] array accordingly
+ * This function reads RCW to check if Serdes1{A:H} is configured
+ * to slot 1/2/3/4/5/6/7 and update the lane_to_slot[] array accordingly
*/
static void initialize_lane_to_slot(void)
{
srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
switch (srds_s1) {
+#if defined(CONFIG_T2080QDS)
case 0x51:
case 0x5f:
case 0x65:
lane_to_slot[6] = 3;
lane_to_slot[7] = 3;
break;
+#elif defined(CONFIG_T2081QDS)
+ case 0x6b:
+ lane_to_slot[4] = 1;
+ lane_to_slot[5] = 3;
+ lane_to_slot[6] = 3;
+ lane_to_slot[7] = 3;
+ break;
+ case 0xca:
+ case 0xcb:
+ lane_to_slot[1] = 7;
+ lane_to_slot[2] = 6;
+ lane_to_slot[3] = 5;
+ lane_to_slot[5] = 3;
+ lane_to_slot[6] = 3;
+ lane_to_slot[7] = 3;
+ break;
+ case 0xf2:
+ lane_to_slot[1] = 7;
+ lane_to_slot[2] = 7;
+ lane_to_slot[3] = 7;
+ lane_to_slot[5] = 4;
+ lane_to_slot[6] = 3;
+ lane_to_slot[7] = 7;
+ break;
+#endif
default:
break;
}
fm_memac_mdio_init(bis, &tgec_mdio_info);
/* Register the muxing front-ends to the MDIO buses */
- T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
- T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
- T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
- T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
- T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
- T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
- T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
- T2080qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
+ t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
+ t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
+ t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
+ t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
+ t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
+#if defined(CONFIG_T2080QDS)
+ t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
+#endif
+ t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
+#if defined(CONFIG_T2081QDS)
+ t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
+ t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
+#endif
+ t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
/* Set the two on-board RGMII PHY address */
fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
case 0x95:
case 0xa2:
case 0x94:
- /* SGMII in Slot3 */
+ /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot2 */
fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
- /* SGMII in Slot2 */
+ /* T2080QDS: SGMII in Slot2; T2081QDS: SGMII in Slot1 */
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
break;
case 0x51:
case 0x5f:
case 0x65:
- /* XAUI/HiGig in Slot3 */
+ /* T2080QDS: XAUI/HiGig in Slot3; T2081QDS: in Slot2 */
fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
- /* SGMII in Slot2 */
+ /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
break;
fm_info_set_phy_address(FM1_10GEC2, 5);
fm_info_set_phy_address(FM1_10GEC3, 6);
fm_info_set_phy_address(FM1_10GEC4, 7);
- /* SGMII in Slot2 */
+ /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
break;
case 0x6d:
fm_info_set_phy_address(FM1_10GEC1, 4);
fm_info_set_phy_address(FM1_10GEC2, 5);
- /* SGMII in Slot3 */
+ /* T2080QDS: SGMII in Slot3; T2081QDS: in Slot2 */
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
break;
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
break;
+#if defined(CONFIG_T2080QDS)
case 0xd9:
case 0xd3:
case 0xcb:
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
break;
+#elif defined(CONFIG_T2081QDS)
+ case 0xca:
+ case 0xcb:
+ /* SGMII in Slot3 */
+ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+ /* SGMII in Slot5 */
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
+ /* SGMII in Slot6 */
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
+ /* SGMII in Slot7 */
+ fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
+ break;
+#endif
+ case 0xf2:
+ /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
+ break;
default:
break;
}
case 3:
mdio_mux[i] = EMI1_SLOT3;
fm_info_set_mdio(i, mii_dev_for_muxval(
- mdio_mux[i]));
+ mdio_mux[i]));
+ break;
+#if defined(CONFIG_T2081QDS)
+ case 5:
+ mdio_mux[i] = EMI1_SLOT5;
+ fm_info_set_mdio(i, mii_dev_for_muxval(
+ mdio_mux[i]));
+ break;
+ case 6:
+ mdio_mux[i] = EMI1_SLOT6;
+ fm_info_set_mdio(i, mii_dev_for_muxval(
+ mdio_mux[i]));
+ break;
+ case 7:
+ mdio_mux[i] = EMI1_SLOT7;
+ fm_info_set_mdio(i, mii_dev_for_muxval(
+ mdio_mux[i]));
break;
+#endif
}
break;
case PHY_INTERFACE_MODE_RGMII:
--- /dev/null
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#Default SerDes Protocol: 0x6C
+#Core/DDR: 1533Mhz/2133MT/s
+12100017 15000000 00000000 00000000
+6c000002 00008000 e8104000 c1000000
+00000000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004
#include "../common/qixis.h"
#include "../common/vsc3316_3308.h"
-#include "t2080qds.h"
-#include "t2080qds_qixis.h"
+#include "t208xqds.h"
+#include "t208xqds_qixis.h"
DECLARE_GLOBAL_DATA_PTR;
int brd_mux_lane_to_slot(void)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 srds_prtcl_s1, srds_prtcl_s2;
+ u32 srds_prtcl_s1;
srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
- srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
+#if defined(CONFIG_T2080QDS)
+ u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+#endif
switch (srds_prtcl_s1) {
case 0:
/* SerDes1 is not enabled */
break;
+#if defined(CONFIG_T2080QDS)
case 0x1c:
case 0xa2:
/* SD1(A:D) => SLOT3 SGMII
*/
QIXIS_WRITE(brdcfg[12], 0x1a);
break;
+#elif defined(CONFIG_T2081QDS)
+ case 0x51:
+ /* SD1(A:D) => SLOT2 XAUI
+ * SD1(E) => SLOT1 PCIe4 x1
+ * SD1(F:H) => SLOT3 SGMII
+ */
+ QIXIS_WRITE(brdcfg[12], 0x98);
+ QIXIS_WRITE(brdcfg[13], 0x70);
+ break;
+ case 0x6b:
+ /* SD1(A:D) => XFI SFP Module
+ * SD1(E) => SLOT1 PCIe4 x1
+ * SD1(F:H) => SLOT3 SGMII
+ */
+ QIXIS_WRITE(brdcfg[12], 0x80);
+ QIXIS_WRITE(brdcfg[13], 0x70);
+ break;
+ case 0x6c:
+ /* SD1(A:B) => XFI SFP Module
+ * SD1(C:D) => SLOT2 SGMII
+ * SD1(E:H) => SLOT1 PCIe4 x4
+ */
+ QIXIS_WRITE(brdcfg[12], 0xe8);
+ QIXIS_WRITE(brdcfg[13], 0x0);
+ break;
+ case 0x6d:
+ /* SD1(A:B) => XFI SFP Module
+ * SD1(C:D) => SLOT2 SGMII
+ * SD1(E:H) => SLOT1 PCIe4 x4
+ */
+ QIXIS_WRITE(brdcfg[12], 0xe8);
+ QIXIS_WRITE(brdcfg[13], 0x0);
+ break;
+ case 0xaa:
+ case 0xab:
+ /* SD1(A:D) => SLOT2 PCIe3 x4
+ * SD1(F:H) => SLOT1 SGMI4 x4
+ */
+ QIXIS_WRITE(brdcfg[12], 0xf8);
+ QIXIS_WRITE(brdcfg[13], 0x0);
+ break;
+ case 0xca:
+ case 0xcb:
+ /* SD1(A) => SLOT2 PCIe3 x1
+ * SD1(B) => SLOT7 SGMII
+ * SD1(C) => SLOT6 SGMII
+ * SD1(D) => SLOT5 SGMII
+ * SD1(E) => SLOT1 PCIe4 x1
+ * SD1(F:H) => SLOT3 SGMII
+ */
+ QIXIS_WRITE(brdcfg[12], 0x80);
+ QIXIS_WRITE(brdcfg[13], 0x70);
+ break;
+ case 0xde:
+ case 0xdf:
+ /* SD1(A:D) => SLOT2 PCIe3 x4
+ * SD1(E) => SLOT1 PCIe4 x1
+ * SD1(F) => SLOT4 PCIe1 x1
+ * SD1(G) => SLOT3 PCIe2 x1
+ * SD1(H) => SLOT7 SGMII
+ */
+ QIXIS_WRITE(brdcfg[12], 0x98);
+ QIXIS_WRITE(brdcfg[13], 0x25);
+ break;
+ case 0xf2:
+ /* SD1(A) => SLOT2 PCIe3 x1
+ * SD1(B:D) => SLOT7 SGMII
+ * SD1(E) => SLOT1 PCIe4 x1
+ * SD1(F) => SLOT4 PCIe1 x1
+ * SD1(G) => SLOT3 PCIe2 x1
+ * SD1(H) => SLOT7 SGMII
+ */
+ QIXIS_WRITE(brdcfg[12], 0x81);
+ QIXIS_WRITE(brdcfg[13], 0xa5);
+ break;
+#endif
default:
printf("WARNING: unsupported for SerDes1 Protocol %d\n",
srds_prtcl_s1);
return -1;
}
+#ifdef CONFIG_T2080QDS
switch (srds_prtcl_s2) {
case 0:
/* SerDes2 is not enabled */
srds_prtcl_s2);
return -1;
}
+#endif
return 0;
}
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __T2080QDS_QIXIS_H__
-#define __T2080QDS_QIXIS_H__
+#ifndef __T208xQDS_QIXIS_H__
+#define __T208xQDS_QIXIS_H__
-/* Definitions of QIXIS Registers for T2080QDS */
+/* Definitions of QIXIS Registers for T208xQDS */
#define QIXIS_SRDS1CLK_122 0x5a
#define QIXIS_SRDS1CLK_125 0x5e
#define BRDCFG5_IRE 0x20 /* i2c Remote i2c1 enable */
+#define BRDCFG9_SFP_TX_EN 0x10
+
#define BRDCFG12_SD3EN_MASK 0x20
#define BRDCFG12_SD3MX_MASK 0x08
#define BRDCFG12_SD3MX_SLOT5 0x08
extra-y := h2200-header.bin
-$(obj)h2200-header.bin: $(obj)h2200-header.o
+$(obj)/h2200-header.bin: $(obj)/h2200-header.o
$(OBJCOPY) -O binary $< $@
MUX_VAL(CP(SYS_32K), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SYS_NIRQ), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(SYS_NRESWARM), (IEN | PTU | DIS | M4)) \
- /* SYS_nRESWARM */\
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) \
MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) \
MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) \
PLATFORM_CPPFLAGS += -I$(TOPDIR)
-OBJCFLAGS = --remove-section=.ppcenv
+OBJCOPYFLAGS = --remove-section=.ppcenv
# SPDX-License-Identifier: GPL-2.0+
#
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
- .phy_id = 0,
+ .phy_addr = 0,
.phy_if = PHY_INTERFACE_MODE_RMII,
},
};
return 0;
}
+#if defined(KM_PCIE_RESET_MPP7)
+
+#define KM_PEX_RST_GPIO_PIN 7
+int fpga_reset(void)
+{
+ if (!check_boco2()) {
+ /* we do not have BOCO2, this is not really used */
+ return 0;
+ }
+
+ printf("PCIe reset through GPIO7: ");
+ /* apply PCIe reset via GPIO */
+ kw_gpio_set_valid(KM_PEX_RST_GPIO_PIN, 1);
+ kw_gpio_direction_output(KM_PEX_RST_GPIO_PIN, 1);
+ kw_gpio_set_value(KM_PEX_RST_GPIO_PIN, 0);
+ udelay(1000*10);
+ kw_gpio_set_value(KM_PEX_RST_GPIO_PIN, 1);
+
+ printf(" done\n");
+
+ return 0;
+}
+
+#else
+
#define PRST1 0x4
#define PCIE_RST 0x10
#define TRAFFIC_RST 0x04
return 0;
}
+#endif
/* the FPGA was configured, we configure the BOCO2 so that the EEPROM
* is available from the Bobcat SPI bus */
MPP4_NF_IO6,
MPP5_NF_IO7,
MPP6_SYSRST_OUTn,
+#if defined(KM_PCIE_RESET_MPP7)
+ MPP7_GPO,
+#else
MPP7_PEX_RST_OUTn,
+#endif
#if defined(CONFIG_SYS_I2C_SOFT)
MPP8_GPIO, /* SDA */
MPP9_GPIO, /* SCL */
/*
* Wait for startup OK from mgcoge3ne
*/
-int startup_allowed(void)
+static int startup_allowed(void)
{
unsigned char buf;
return 0;
}
-#if defined(CONFIG_BOOTCOUNT_LIMIT)
static void set_bootcount_addr(void)
{
uchar buf[32];
sprintf((char *)buf, "0x%x", bootcountaddr);
setenv("bootcountaddr", (char *)buf);
}
-#endif
int misc_init_r(void)
{
initialize_unit_leds();
set_km_env();
-#if defined(CONFIG_BOOTCOUNT_LIMIT)
set_bootcount_addr();
-#endif
return 0;
}
return;
/* RGMII clk transition on data stable */
- if (!miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®))
+ if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®))
printf("Error reading PHY spec ctrl reg\n");
- if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG,
- reg | PHY_RGMII_CLK_STABLE | PHY_CLSA))
+ if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG,
+ reg | PHY_RGMII_CLK_STABLE | PHY_CLSA))
printf("Error writing PHY spec ctrl reg\n");
/* leds setup */
- if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG,
- PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT))
+ if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG,
+ PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT))
printf("Error writing PHY LED reg\n");
/* reset the phy */
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := kmp204x.o ddr.o eth.o tlb.o pci.o law.o \
+obj-y := kmp204x.o ddr.o eth.o tlb.o pci.o law.o qrio.o \
../common/common.o ../common/ivm.o
return 0;
}
-/* TODO: implement the I2C deblocking function */
-int i2c_make_abort(void)
+/* I2C deblocking uses the algorithm defined in board/keymile/common/common.c
+ * 2 dedicated QRIO GPIOs externally pull the SCL and SDA lines
+ * For I2C only the low state is activly driven and high state is pulled-up
+ * by a resistor. Therefore the deblock GPIOs are used
+ * -> as an active output to drive a low state
+ * -> as an open-drain input to have a pulled-up high state
+ */
+
+/* QRIO GPIOs used for deblocking */
+#define DEBLOCK_PORT1 GPIO_A
+#define DEBLOCK_SCL1 20
+#define DEBLOCK_SDA1 21
+
+/* By default deblock GPIOs are floating */
+static void i2c_deblock_gpio_cfg(void)
+{
+ /* set I2C bus 1 deblocking GPIOs input, but 0 value for open drain */
+ qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SCL1);
+ qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SDA1);
+
+ qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, 0);
+ qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, 0);
+}
+
+void set_sda(int state)
+{
+ qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, state);
+}
+
+void set_scl(int state)
+{
+ qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, state);
+}
+
+int get_sda(void)
+{
+ return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1);
+}
+
+int get_scl(void)
{
- return 1;
+ return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1);
}
+
#define ZL30158_RST 8
#define ZL30343_RST 9
int board_early_init_r(void)
{
+ int ret = 0;
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
set_liodns();
setup_portals();
- return 0;
+ ret = trigger_fpga_config();
+ if (ret)
+ printf("error triggering PCIe FPGA config\n");
+
+ return ret;
}
unsigned long get_board_sys_clk(unsigned long dummy)
return 66666666;
}
-#define WDMASK_OFF 0x16
-
-static void qrio_wdmask(u8 bit, bool wden)
-{
- u16 wdmask;
- void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
-
- wdmask = in_be16(qrio_base + WDMASK_OFF);
-
- if (wden)
- wdmask |= (1 << bit);
- else
- wdmask &= ~(1 << bit);
-
- out_be16(qrio_base + WDMASK_OFF, wdmask);
-}
-
-#define PRST_OFF 0x1a
-
-void qrio_prst(u8 bit, bool en, bool wden)
-{
- u16 prst;
- void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
-
- qrio_wdmask(bit, wden);
-
- prst = in_be16(qrio_base + PRST_OFF);
-
- if (en)
- prst &= ~(1 << bit);
- else
- prst |= (1 << bit);
-
- out_be16(qrio_base + PRST_OFF, prst);
-}
-
-#define PRSTCFG_OFF 0x1c
-
-void qrio_prstcfg(u8 bit, u8 mode)
-{
- u32 prstcfg;
- u8 i;
- void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
-
- prstcfg = in_be32(qrio_base + PRSTCFG_OFF);
-
- for (i = 0; i < 2; i++) {
- if (mode & (1<<i))
- set_bit(2*bit+i, &prstcfg);
- else
- clear_bit(2*bit+i, &prstcfg);
- }
-
- out_be32(qrio_base + PRSTCFG_OFF, prstcfg);
-}
-
-
-#define BOOTCOUNT_OFF 0x12
-
-void bootcount_store(ulong counter)
+int misc_init_f(void)
{
- u8 val;
- void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
-
- val = (counter <= 255) ? (u8)counter : 255;
- out_8(qrio_base + BOOTCOUNT_OFF, val);
-}
+ /* configure QRIO pis for i2c deblocking */
+ i2c_deblock_gpio_cfg();
-ulong bootcount_load(void)
-{
- u8 val;
- void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
- val = in_8(qrio_base + BOOTCOUNT_OFF);
- return val;
+ return 0;
}
#define NUM_SRDS_BANKS 2
* SPDX-License-Identifier: GPL-2.0+
*/
+/* QRIO GPIO ports */
+#define GPIO_A 0x40
+#define GPIO_B 0x60
+
+int qrio_get_gpio(u8 port_off, u8 gpio_nr);
+void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val);
+void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value);
+void qrio_gpio_direction_output(u8 port_off, u8 gpio_nr, bool value);
+void qrio_gpio_direction_input(u8 port_off, u8 gpio_nr);
+
#define PRSTCFG_POWUP_UNIT_CORE_RST 0x0
#define PRSTCFG_POWUP_UNIT_RST 0x1
#define PRSTCFG_POWUP_RST 0x3
#
#PBI commands
+#Workaround for A-006559 needed for rev 2.0 of P2041 silicon
+#Freescale's errarta sheet suggests it may be done with PBI
+09000010 00000000
+09000014 00000000
+09000018 81d00000
+09021008 0000f000
+09021028 0000f000
+09021048 0000f000
+09021068 0000f000
+09000018 00000000
#Initialize CPC1 as 1MB SRAM
09010000 00200400
09138000 00000000
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/fsl_serdes.h>
+#include <asm/errno.h>
#include "kmp204x.h"
+#define PROM_SEL_L 11
+/* control the PROM_SEL_L signal*/
+static void toggle_fpga_eeprom_bus(bool cpu_own)
+{
+ qrio_gpio_direction_output(GPIO_A, PROM_SEL_L, !cpu_own);
+}
+
+#define CONF_SEL_L 10
+#define FPGA_PROG_L 19
+#define FPGA_DONE 18
+#define FPGA_INIT_L 17
+
+int trigger_fpga_config(void)
+{
+ int ret = 0, init_l;
+ /* approx 10ms */
+ u32 timeout = 10000;
+
+ /* make sure the FPGA_can access the EEPROM */
+ toggle_fpga_eeprom_bus(false);
+
+ /* assert CONF_SEL_L to be able to drive FPGA_PROG_L */
+ qrio_gpio_direction_output(GPIO_A, CONF_SEL_L, 0);
+
+ /* trigger the config start */
+ qrio_gpio_direction_output(GPIO_A, FPGA_PROG_L, 0);
+
+ /* small delay for INIT_L line */
+ udelay(10);
+
+ /* wait for FPGA_INIT to be asserted */
+ do {
+ init_l = qrio_get_gpio(GPIO_A, FPGA_INIT_L);
+ if (timeout-- == 0) {
+ printf("FPGA_INIT timeout\n");
+ ret = -EFAULT;
+ break;
+ }
+ udelay(10);
+ } while (init_l);
+
+ /* deassert FPGA_PROG, config should start */
+ qrio_set_gpio(GPIO_A, FPGA_PROG_L, 1);
+
+ return ret;
+}
+
+/* poll the FPGA_DONE signal and give the EEPROM back to the QorIQ */
+static int wait_for_fpga_config(void)
+{
+ int ret = 0, done;
+ /* approx 5 s */
+ u32 timeout = 500000;
+
+ printf("PCIe FPGA config:");
+ do {
+ done = qrio_get_gpio(GPIO_A, FPGA_DONE);
+ if (timeout-- == 0) {
+ printf(" FPGA_DONE timeout\n");
+ ret = -EFAULT;
+ goto err_out;
+ }
+ udelay(10);
+ } while (!done);
+
+ printf(" done\n");
+
+err_out:
+ /* deactive CONF_SEL and give the CPU conf EEPROM access */
+ qrio_set_gpio(GPIO_A, CONF_SEL_L, 1);
+ toggle_fpga_eeprom_bus(true);
+
+ return ret;
+}
+
#define PCIE_SW_RST 14
+#define PEXHC_SW_RST 13
#define HOOPER_SW_RST 12
void pci_init_board(void)
{
+ /* first wait for the PCIe FPGA to be configured
+ * it has been triggered earlier in board_early_init_r */
+ int ret = wait_for_fpga_config();
+ if (ret)
+ printf("error finishing PCIe FPGA config\n");
+
qrio_prst(PCIE_SW_RST, false, false);
+ qrio_prst(PEXHC_SW_RST, false, false);
qrio_prst(HOOPER_SW_RST, false, false);
/* Hooper is not direcly PCIe capable */
mdelay(50);
+
fsl_pcie_init_board(0);
}
--- /dev/null
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#include "../common/common.h"
+#include "kmp204x.h"
+
+/* QRIO GPIO register offsets */
+#define DIRECT_OFF 0x18
+#define GPRT_OFF 0x1c
+
+int qrio_get_gpio(u8 port_off, u8 gpio_nr)
+{
+ u32 gprt;
+
+ void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+ gprt = in_be32(qrio_base + port_off + GPRT_OFF);
+
+ return (gprt >> gpio_nr) & 1U;
+}
+
+void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value)
+{
+ u32 gprt, mask;
+
+ void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+ mask = 1U << gpio_nr;
+
+ gprt = in_be32(qrio_base + port_off + GPRT_OFF);
+ if (value)
+ gprt |= mask;
+ else
+ gprt &= ~mask;
+
+ out_be32(qrio_base + port_off + GPRT_OFF, gprt);
+}
+
+void qrio_gpio_direction_output(u8 port_off, u8 gpio_nr, bool value)
+{
+ u32 direct, mask;
+
+ void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+ mask = 1U << gpio_nr;
+
+ direct = in_be32(qrio_base + port_off + DIRECT_OFF);
+ direct |= mask;
+ out_be32(qrio_base + port_off + DIRECT_OFF, direct);
+
+ qrio_set_gpio(port_off, gpio_nr, value);
+}
+
+void qrio_gpio_direction_input(u8 port_off, u8 gpio_nr)
+{
+ u32 direct, mask;
+
+ void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+ mask = 1U << gpio_nr;
+
+ direct = in_be32(qrio_base + port_off + DIRECT_OFF);
+ direct &= ~mask;
+ out_be32(qrio_base + port_off + DIRECT_OFF, direct);
+}
+
+void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val)
+{
+ u32 direct, mask;
+
+ void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+ mask = 1U << gpio_nr;
+
+ direct = in_be32(qrio_base + port_off + DIRECT_OFF);
+ if (val == 0)
+ /* set to output -> GPIO drives low */
+ direct |= mask;
+ else
+ /* set to input -> GPIO floating */
+ direct &= ~mask;
+
+ out_be32(qrio_base + port_off + DIRECT_OFF, direct);
+}
+
+#define WDMASK_OFF 0x16
+
+static void qrio_wdmask(u8 bit, bool wden)
+{
+ u16 wdmask;
+ void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+ wdmask = in_be16(qrio_base + WDMASK_OFF);
+
+ if (wden)
+ wdmask |= (1 << bit);
+ else
+ wdmask &= ~(1 << bit);
+
+ out_be16(qrio_base + WDMASK_OFF, wdmask);
+}
+
+#define PRST_OFF 0x1a
+
+void qrio_prst(u8 bit, bool en, bool wden)
+{
+ u16 prst;
+ void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+ qrio_wdmask(bit, wden);
+
+ prst = in_be16(qrio_base + PRST_OFF);
+
+ if (en)
+ prst &= ~(1 << bit);
+ else
+ prst |= (1 << bit);
+
+ out_be16(qrio_base + PRST_OFF, prst);
+}
+
+#define PRSTCFG_OFF 0x1c
+
+void qrio_prstcfg(u8 bit, u8 mode)
+{
+ u32 prstcfg;
+ u8 i;
+ void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+ prstcfg = in_be32(qrio_base + PRSTCFG_OFF);
+
+ for (i = 0; i < 2; i++) {
+ if (mode & (1<<i))
+ set_bit(2*bit+i, &prstcfg);
+ else
+ clear_bit(2*bit+i, &prstcfg);
+ }
+
+ out_be32(qrio_base + PRSTCFG_OFF, prstcfg);
+}
#64 bytes RCW data
14600000 00000000 28200000 00000000
148E70CF CFC02000 58000000 41000000
-00000000 00000000 00000000 F4428002
+00000000 00000000 00000000 F0428002
00000000 00000000 00000000 00000000
setup_debug_env=tftpboot 0x200000 scripts/develop-common.txt && env import -t 0x200000 ${filesize} && run configure
-tftpfdt=true
configure=run set_uimage; km_setboardid && saveenv && reset
subbootcmds=tftpfdt tftpkernel nfsargs add_default boot
nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${toolchain}/${arch}
+tftpfdt=if run set_fdthigh || test ${arch} != arm; then tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb; else true; fi
tftpkernel=tftpboot ${load_addr_r} ${hostname}/${uimage}
toolchain=/opt/eldk
rootfssize=0
setup_debug_env=tftpboot 0x200000 scripts/develop-common.txt && env import -t 0x200000 ${filesize} && run configure
-tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb
setup_debug_env=tftpboot 0x200000 scripts/develop-common.txt && env import -t 0x200000 ${filesize} && run configure
-tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb
setup_debug_env=tftpboot 0x200000 scripts/ramfs-common.txt && env import -t 0x200000 ${filesize} && run configure
-tftpfdt=true
configure=run set_uimage; km_setboardid && saveenv && reset
rootfsfile=${hostname}/rootfsImage
setrootfsaddr=setexpr value ${pnvramaddr} - ${rootfssize} && setenv rootfsaddr 0x${value}
+tftpfdt=if run set_fdthigh || test ${arch} != arm; then tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb; else true; fi
tftpkernel=tftpboot ${load_addr_r} ${hostname}/${uimage}
tftpramfs=tftpboot ${rootfsaddr} ${hostname}/rootfsImage
set_uimage=printenv uimage || setenv uimage uImage
setup_debug_env=tftpboot 0x200000 scripts/ramfs-common.txt && env import -t 0x200000 ${filesize} && run configure
-tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb
setup_debug_env=tftpboot 0x200000 scripts/ramfs-common.txt && env import -t 0x200000 ${filesize} && run configure
-tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb
extra-y := bootscript.img
-$(obj)bootscript.img:
- @mkimage -T script -C none -n M7_script -d bootscript $@
+$(obj)/bootscript.img: $(src)/bootscript
+ @mkimage -T script -C none -n M7_script -d $< $@
obj-y += mvblx.o fpga.o
obj-$(CONFIG_ID_EEPROM) += sys_eeprom.o
-CFLAGS += -Werror
+ccflags-y += -Werror
extra-y := bootscript.img
-$(obj)bootscript.img: bootscript
+$(obj)/bootscript.img: $(src)/bootscript
@mkimage -T script -C none -n mvSMR_Script -d $< $@
#define REFCNT_266 0
/**************************************/
-_TEXT_BASE:
- .word CONFIG_SYS_TEXT_BASE
-
.globl lowlevel_init
lowlevel_init:
/* use r0 to relocate DATA read/write to flash rather than memory ! */
- ldr r0, _TEXT_BASE
+ ldr r0, =CONFIG_SYS_TEXT_BASE
ldr r13, =BWSCON
/* enable minimal access to PLD */
u32 param4;
};
-int print_cpuinfo(void);
-
/*
* IEN - Input Enable
* IDIS - Input Disable
# Copyright (c) 2011 The Chromium OS Authors.
# SPDX-License-Identifier: GPL-2.0+
-include common.mk
+include $(src)/common.mk
void gpio_early_init_uart(void)
__attribute__((weak, alias("__gpio_early_init_uart")));
+#if defined(CONFIG_TEGRA_NAND)
void __pin_mux_nand(void)
{
funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT);
}
void pin_mux_nand(void) __attribute__((weak, alias("__pin_mux_nand")));
+#endif
void __pin_mux_display(void)
{
--- /dev/null
+#
+# (C) Copyright 2013-2014
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += as3722_init.o
+obj-y += venice2.o
--- /dev/null
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include "as3722_init.h"
+
+/* AS3722-PMIC-specific early init code - get CPU rails up, etc */
+
+void tegra_i2c_ll_write_addr(uint addr, uint config)
+{
+ struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+ writel(addr, ®->cmd_addr0);
+ writel(config, ®->cnfg);
+}
+
+void tegra_i2c_ll_write_data(uint data, uint config)
+{
+ struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+ writel(data, ®->cmd_data1);
+ writel(config, ®->cnfg);
+}
+
+void pmic_enable_cpu_vdd(void)
+{
+ debug("%s entry\n", __func__);
+
+ /* Don't need to set up VDD_CORE - already done - by OTP */
+
+ debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__);
+ /*
+ * Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.
+ * First set VDD to 1.0V, then enable the VDD regulator.
+ */
+ tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+ tegra_i2c_ll_write_data(AS3722_SD0VOLTAGE_DATA, I2C_SEND_2_BYTES);
+ /*
+ * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
+ * tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES);
+ */
+ udelay(10 * 1000);
+
+ debug("%s: Setting VDD_GPU to 1.0V via AS3722 reg 6/4D\n", __func__);
+ /*
+ * Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus.
+ * First set VDD to 1.0V, then enable the VDD regulator.
+ */
+ tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+ tegra_i2c_ll_write_data(AS3722_SD6VOLTAGE_DATA, I2C_SEND_2_BYTES);
+ /*
+ * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
+ * tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES);
+ */
+ udelay(10 * 1000);
+
+ debug("%s: Set VPP_FUSE to 1.2V via AS3722 reg 0x12/4E\n", __func__);
+ /*
+ * Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus.
+ * First set VDD to 1.2V, then enable the VDD regulator.
+ */
+ tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+ tegra_i2c_ll_write_data(AS3722_LDO2VOLTAGE_DATA, I2C_SEND_2_BYTES);
+ /*
+ * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
+ * tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES);
+ */
+ udelay(10 * 1000);
+
+ debug("%s: Set VDD_SDMMC to 3.3V via AS3722 reg 0x16/4E\n", __func__);
+ /*
+ * Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus.
+ * First set it to bypass 3.3V straight thru, then enable the regulator
+ *
+ * NOTE: We do this early because doing it later seems to hose the CPU
+ * power rail/partition startup. Need to debug.
+ */
+ tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+ tegra_i2c_ll_write_data(AS3722_LDO6VOLTAGE_DATA, I2C_SEND_2_BYTES);
+ /*
+ * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
+ * tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES);
+ */
+ udelay(10 * 1000);
+}
--- /dev/null
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* AS3722-PMIC-specific early init regs */
+
+#define AS3722_I2C_ADDR 0x80
+
+#define AS3722_SD0VOLTAGE_REG 0x00 /* CPU */
+#define AS3722_SD1VOLTAGE_REG 0x01 /* CORE, already set by OTP */
+#define AS3722_SD6VOLTAGE_REG 0x06 /* GPU */
+#define AS3722_SDCONTROL_REG 0x4D
+
+#define AS3722_LDO2VOLTAGE_REG 0x12 /* VPP_FUSE */
+#define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC */
+#define AS3722_LDCONTROL_REG 0x4E
+
+#define AS3722_SD0VOLTAGE_DATA (0x2800 | AS3722_SD0VOLTAGE_REG)
+#define AS3722_SD0CONTROL_DATA (0x0100 | AS3722_SDCONTROL_REG)
+
+#define AS3722_SD1VOLTAGE_DATA (0x3200 | AS3722_SD1VOLTAGE_REG)
+#define AS3722_SD1CONTROL_DATA (0x0200 | AS3722_SDCONTROL_REG)
+
+#define AS3722_SD6CONTROL_DATA (0x4000 | AS3722_SDCONTROL_REG)
+#define AS3722_SD6VOLTAGE_DATA (0x2800 | AS3722_SD6VOLTAGE_REG)
+
+#define AS3722_LDO2CONTROL_DATA (0x0400 | AS3722_LDCONTROL_REG)
+#define AS3722_LDO2VOLTAGE_DATA (0x1000 | AS3722_LDO2VOLTAGE_REG)
+
+#define AS3722_LDO6CONTROL_DATA (0x4000 | AS3722_LDCONTROL_REG)
+#define AS3722_LDO6VOLTAGE_DATA (0x3F00 | AS3722_LDO6VOLTAGE_REG)
+
+#define I2C_SEND_2_BYTES 0x0A02
+
+void pmic_enable_cpu_vdd(void);
--- /dev/null
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _PINMUX_CONFIG_VENICE2_H_
+#define _PINMUX_CONFIG_VENICE2_H_
+
+#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io) \
+ { \
+ .pingroup = PINGRP_##_pingroup, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_DEFAULT, \
+ .od = PMUX_PIN_OD_DEFAULT, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
+ { \
+ .pingroup = PINGRP_##_pingroup, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_##_lock, \
+ .od = PMUX_PIN_OD_##_od, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+#define DDC_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _rcv_sel) \
+ { \
+ .pingroup = PINGRP_##_pingroup, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_##_lock, \
+ .rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+#define VI_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
+ { \
+ .pingroup = PINGRP_##_pingroup, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_##_lock, \
+ .od = PMUX_PIN_OD_DEFAULT, \
+ .ioreset = PMUX_PIN_IO_RESET_##_ioreset \
+ }
+
+#define CEC_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
+ { \
+ .pingroup = PINGRP_##_pingroup, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_##_lock, \
+ .od = PMUX_PIN_OD_##_od, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+#define USB_PINMUX CEC_PINMUX
+
+#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+ { \
+ .padgrp = PDRIVE_PINGROUP_##_padgrp, \
+ .slwf = _slwf, \
+ .slwr = _slwr, \
+ .drvup = _drvup, \
+ .drvdn = _drvdn, \
+ .lpmd = PGRP_LPMD_##_lpmd, \
+ .schmt = PGRP_SCHMT_##_schmt, \
+ .hsm = PGRP_HSM_##_hsm, \
+ }
+
+static struct pingroup_config tegra124_pinmux_common[] = {
+ /* EXTPERIPH1 pinmux */
+ DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, OUTPUT),
+
+ /* I2S0 pinmux */
+ DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT),
+
+ /* I2S1 pinmux */
+ DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT),
+
+ /* I2S3 pinmux */
+ DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT),
+
+ /* CLDVFS pinmux */
+ DEFAULT_PINMUX(DVFS_PWM, CLDVFS, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DVFS_CLK, CLDVFS, NORMAL, NORMAL, OUTPUT),
+
+ /* ULPI pinmux */
+ DEFAULT_PINMUX(ULPI_DATA0, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA1, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA2, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA3, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA4, ULPI, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA5, ULPI, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA6, ULPI, NORMAL, NORMAL, INPUT),
+
+ /* EC KBC/SPI */
+ DEFAULT_PINMUX(ULPI_CLK, SPI1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DIR, SPI1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_NXT, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_STP, SPI1, NORMAL, NORMAL, INPUT),
+
+ /* I2C3 (TPM) pinmux */
+ I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+ I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+
+ /* I2C2 pinmux */
+ I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+ I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+
+ /* UARTD pinmux (UART4 on Servo board, unused) */
+ DEFAULT_PINMUX(GPIO_PJ7, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GPIO_PB0, UARTD, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GPIO_PB1, UARTD, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GPIO_PK7, UARTD, NORMAL, NORMAL, OUTPUT),
+
+ /* SPI4 (Winbond 'boot ROM') */
+ DEFAULT_PINMUX(GPIO_PG5, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PG6, SPI4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PG7, SPI4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PI3, SPI4, NORMAL, NORMAL, INPUT),
+
+ /* Touch IRQ */
+ DEFAULT_PINMUX(GPIO_W3_AUD, RSVD1, NORMAL, NORMAL, INPUT),
+
+ /* PWM1 pinmux */
+ DEFAULT_PINMUX(GPIO_PH1, PWM1, NORMAL, NORMAL, OUTPUT),
+
+ /* SDMMC1 pinmux */
+ DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP, NORMAL, INPUT),
+
+ /* SDMMC3 pinmux */
+ DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CLK_LB_IN, SDMMC3, UP, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT, SDMMC3, DOWN, NORMAL, INPUT),
+
+ /* SDMMC4 pinmux */
+ DEFAULT_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_CMD, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT0, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT1, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT2, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT3, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT4, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT5, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT6, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT7, SDMMC4, UP, NORMAL, INPUT),
+
+ /* BLINK pinmux */
+ DEFAULT_PINMUX(CLK_32K_OUT, BLINK, NORMAL, NORMAL, OUTPUT),
+
+ /* KBC pinmux */
+ DEFAULT_PINMUX(KB_COL0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW1, KBC, UP, NORMAL, INPUT),
+
+ /* Misc */
+ DEFAULT_PINMUX(GPIO_PV0, RSVD1, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(KB_ROW7, RSVD1, UP, NORMAL, INPUT),
+
+ /* UARTA pinmux (BR_UART_TXD/RXD on Servo board) */
+ DEFAULT_PINMUX(KB_ROW9, UARTA, UP, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_ROW10, UARTA, UP, TRISTATE, INPUT),
+
+ /* I2CPWR pinmux (I2C5) */
+ I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+ I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+
+ /* RTCK pinmux */
+ DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, INPUT),
+
+ /* CLK pinmux */
+ DEFAULT_PINMUX(CLK_32K_IN, CLK, NORMAL, TRISTATE, INPUT),
+
+ /* PWRON pinmux */
+ DEFAULT_PINMUX(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT),
+
+ /* CPU pinmux */
+ DEFAULT_PINMUX(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT),
+
+ /* PMI pinmux */
+ DEFAULT_PINMUX(PWR_INT_N, PMI, NORMAL, TRISTATE, INPUT),
+
+ /* RESET_OUT_N pinmux */
+ DEFAULT_PINMUX(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT),
+
+ /* EXTPERIPH3 pinmux */
+ DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
+
+ /* I2C1 pinmux */
+ I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+ I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+
+ /* UARTB, GPS */
+ DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART2_RXD, UARTB, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(UART2_TXD, UARTB, NORMAL, NORMAL, OUTPUT),
+
+ /* UARTC (WIFI/BT) */
+ DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT),
+
+ /* CEC pinmux */
+ CEC_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+
+ /* I2C4 (HDMI_DDC) pinmux */
+ DDC_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
+ DDC_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
+
+ /* USB pinmux */
+ USB_PINMUX(USB_VBUS_EN0, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ USB_PINMUX(USB_VBUS_EN1, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+
+ /* Unused, marked SNN_ on schematic, TRISTATE 'em */
+ DEFAULT_PINMUX(GPIO_PBB0, RSVD3, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GPIO_PBB3, RSVD3, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GPIO_PBB4, RSVD3, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GPIO_PBB5, RSVD2, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GPIO_PBB6, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GPIO_PBB7, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GPIO_PCC2, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GPIO_PH3, GMI, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GPIO_PI7, GMI, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GPIO_PJ2, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GPIO_X5_AUD, RSVD3, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GPIO_X6_AUD, GMI, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GPIO_W2_AUD, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GPIO_PFF2, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(USB_VBUS_EN2, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_COL5, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW2, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW3, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW5, RSVD2, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW6, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW13, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW14, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW16, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(OWR, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA7, ULPI, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(DAP3_DIN, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(DAP3_FS, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(DAP3_SCLK, RSVD2, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(CLK2_OUT, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SDMMC1_WP_N, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(CAM_MCLK, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(CLK3_REQ, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SPDIF_OUT, RSVD1, NORMAL, TRISTATE, INPUT),
+};
+
+static struct pingroup_config unused_pins_lowpower[] = {
+ DEFAULT_PINMUX(CLK1_REQ, RSVD3, DOWN, TRISTATE, OUTPUT),
+};
+
+/* Initially setting all used GPIO's to non-TRISTATE */
+static struct pingroup_config tegra124_pinmux_set_nontristate[] = {
+ DEFAULT_PINMUX(GPIO_X4_AUD, RSVD1, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GPIO_X7_AUD, RSVD1, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GPIO_W2_AUD, RSVD1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_X3_AUD, RSVD3, UP, NORMAL, INPUT),
+
+ /* EN_VDD_BL */
+ DEFAULT_PINMUX(DAP3_DOUT, I2S2, DOWN, NORMAL, OUTPUT),
+
+ /* MODEM */
+ DEFAULT_PINMUX(GPIO_PV0, RSVD3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PV1, RSVD1, NORMAL, NORMAL, INPUT),
+
+ /* BOOT_SEL0-3 */
+ DEFAULT_PINMUX(GPIO_PG0, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PG1, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PG2, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PG3, GMI, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(CLK2_REQ, RSVD3, NORMAL, NORMAL, OUTPUT),
+
+ DEFAULT_PINMUX(KB_COL3, KBC, UP, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_COL4, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL6, KBC, UP, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_COL7, KBC, UP, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_ROW4, KBC, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(GPIO_PU4, RSVD3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PU5, RSVD3, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GPIO_PU6, RSVD3, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(HDMI_INT, RSVD1, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPDIF_IN, USB, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CD_N, SDMMC3, UP, NORMAL, INPUT),
+
+ /* TS_SHDN_L */
+ DEFAULT_PINMUX(GPIO_PK1, GMI, NORMAL, NORMAL, OUTPUT),
+};
+
+static struct padctrl_config venice2_padctrl[] = {
+ /* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
+ DEFAULT_PADCFG(SDIO3, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR,
+ SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, NONE, NONE),
+};
+#endif /* PINMUX_CONFIG_VENICE2_H */
--- /dev/null
+/*
+ * (C) Copyright 2013-2014
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm-generic/gpio.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/gp_padctrl.h>
+#include <asm/arch/pinmux.h>
+#include "pinmux-config-venice2.h"
+#include <i2c.h>
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+ pinmux_config_table(tegra124_pinmux_set_nontristate,
+ ARRAY_SIZE(tegra124_pinmux_set_nontristate));
+
+ pinmux_config_table(tegra124_pinmux_common,
+ ARRAY_SIZE(tegra124_pinmux_common));
+
+ pinmux_config_table(unused_pins_lowpower,
+ ARRAY_SIZE(unused_pins_lowpower));
+
+ /* Initialize any non-default pad configs (APB_MISC_GP regs) */
+ padgrp_config_table(venice2_padctrl, ARRAY_SIZE(venice2_padctrl));
+}
#
# Check the U-Boot Image with a SHA1 checksum
-ALL-y += $(obj)u-boot.sha1
+ALL-y += u-boot.sha1
PLATFORM_CPPFLAGS += -DCONFIG_440=1
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
- .phy_id = 0,
+ .phy_addr = 0,
.phy_if = PHY_INTERFACE_MODE_RGMII,
},
{
.slave_reg_ofs = 0x308,
.sliver_reg_ofs = 0xdc0,
- .phy_id = 1,
+ .phy_addr = 1,
.phy_if = PHY_INTERFACE_MODE_RGMII,
},
};
# SPDX-License-Identifier: GPL-2.0+
#
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
obj-$(CONFIG_SOFT_I2C_MULTI_BUS) += multi_i2c.o
obj-$(CONFIG_THOR_FUNCTION) += thor.o
obj-$(CONFIG_CMD_USB_MASS_STORAGE) += ums.o
+obj-$(CONFIG_MISC_COMMON) += misc.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_BOARD_COMMON) += board.o
--- /dev/null
+mmcboot=setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} ${rootfstype} rootwait ${console}; run loaduimage; bootm 0x40007FC0
+rootfstype=ext4
+loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage
+mmcdev=0
+mmcbootpart=2
+mmcrootpart=5
+console=console=ttySAC2,115200n8
+bootcmd=run mmcboot
+dfu_alt_info=u-boot mmc 80 800;params.bin mmc 0x38 0x8;uImage ext4 0 2
. = ALIGN(4);
__image_copy_end = .;
- _end = .;
+
+ .end :
+ {
+ *(.__end)
+ } >.sram
.bss :
{
--- /dev/null
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ * Przemyslaw Marczak <p.marczak@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <lcd.h>
+#include <libtizen.h>
+#include <samsung/misc.h>
+#include <errno.h>
+#include <version.h>
+#include <asm/sizes.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
+#include <linux/input.h>
+#include <power/pmic.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+void set_board_info(void)
+{
+ char info[64];
+
+ snprintf(info, ARRAY_SIZE(info), "%d.%d", s5p_cpu_rev & 0x0f,
+ (s5p_cpu_rev & 0xf0) >> 0x04);
+ setenv("soc_rev", info);
+
+ snprintf(info, ARRAY_SIZE(info), "%x", s5p_cpu_id);
+ setenv("soc_id", info);
+
+#ifdef CONFIG_REVISION_TAG
+ snprintf(info, ARRAY_SIZE(info), "%x", get_board_rev());
+ setenv("board_rev", info);
+#endif
+#ifdef CONFIG_OF_LIBFDT
+ snprintf(info, ARRAY_SIZE(info), "%s%x-%s.dtb",
+ CONFIG_SYS_SOC, s5p_cpu_id, CONFIG_SYS_BOARD);
+ setenv("fdtfile", info);
+#endif
+}
+#endif /* CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG */
+
+#ifdef CONFIG_LCD_MENU
+static int power_key_pressed(u32 reg)
+{
+ struct pmic *pmic;
+ u32 status;
+ u32 mask;
+
+ pmic = pmic_get(KEY_PWR_PMIC_NAME);
+ if (!pmic) {
+ printf("%s: Not found\n", KEY_PWR_PMIC_NAME);
+ return 0;
+ }
+
+ if (pmic_probe(pmic))
+ return 0;
+
+ if (reg == KEY_PWR_STATUS_REG)
+ mask = KEY_PWR_STATUS_MASK;
+ else
+ mask = KEY_PWR_INTERRUPT_MASK;
+
+ if (pmic_reg_read(pmic, reg, &status))
+ return 0;
+
+ return !!(status & mask);
+}
+
+static int key_pressed(int key)
+{
+ int value;
+
+ switch (key) {
+ case KEY_POWER:
+ value = power_key_pressed(KEY_PWR_INTERRUPT_REG);
+ break;
+ case KEY_VOLUMEUP:
+ value = !gpio_get_value(KEY_VOL_UP_GPIO);
+ break;
+ case KEY_VOLUMEDOWN:
+ value = !gpio_get_value(KEY_VOL_DOWN_GPIO);
+ break;
+ default:
+ value = 0;
+ break;
+ }
+
+ return value;
+}
+
+static int check_keys(void)
+{
+ int keys = 0;
+
+ if (key_pressed(KEY_POWER))
+ keys += KEY_POWER;
+ if (key_pressed(KEY_VOLUMEUP))
+ keys += KEY_VOLUMEUP;
+ if (key_pressed(KEY_VOLUMEDOWN))
+ keys += KEY_VOLUMEDOWN;
+
+ return keys;
+}
+
+/*
+ * 0 BOOT_MODE_INFO
+ * 1 BOOT_MODE_THOR
+ * 2 BOOT_MODE_UMS
+ * 3 BOOT_MODE_DFU
+ * 4 BOOT_MODE_EXIT
+ */
+static char *
+mode_name[BOOT_MODE_EXIT + 1] = {
+ "DEVICE",
+ "THOR",
+ "UMS",
+ "DFU",
+ "EXIT"
+};
+
+static char *
+mode_info[BOOT_MODE_EXIT + 1] = {
+ "info",
+ "downloader",
+ "mass storage",
+ "firmware update",
+ "and run normal boot"
+};
+
+#define MODE_CMD_ARGC 4
+
+static char *
+mode_cmd[BOOT_MODE_EXIT + 1][MODE_CMD_ARGC] = {
+ {"", "", "", ""},
+ {"thor", "0", "mmc", "0"},
+ {"ums", "0", "mmc", "0"},
+ {"dfu", "0", "mmc", "0"},
+ {"", "", "", ""},
+};
+
+static void display_board_info(void)
+{
+#ifdef CONFIG_GENERIC_MMC
+ struct mmc *mmc = find_mmc_device(0);
+#endif
+ vidinfo_t *vid = &panel_info;
+
+ lcd_position_cursor(4, 4);
+
+ lcd_printf("%s\n\t", U_BOOT_VERSION);
+ lcd_puts("\n\t\tBoard Info:\n");
+#ifdef CONFIG_SYS_BOARD
+ lcd_printf("\tBoard name: %s\n", CONFIG_SYS_BOARD);
+#endif
+#ifdef CONFIG_REVISION_TAG
+ lcd_printf("\tBoard rev: %u\n", get_board_rev());
+#endif
+ lcd_printf("\tDRAM banks: %u\n", CONFIG_NR_DRAM_BANKS);
+ lcd_printf("\tDRAM size: %u MB\n", gd->ram_size / SZ_1M);
+
+#ifdef CONFIG_GENERIC_MMC
+ if (mmc) {
+ if (!mmc->capacity)
+ mmc_init(mmc);
+
+ lcd_printf("\teMMC size: %llu MB\n", mmc->capacity / SZ_1M);
+ }
+#endif
+ if (vid)
+ lcd_printf("\tDisplay resolution: %u x % u\n",
+ vid->vl_col, vid->vl_row);
+
+ lcd_printf("\tDisplay BPP: %u\n", 1 << vid->vl_bpix);
+}
+
+static int mode_leave_menu(int mode)
+{
+ char *exit_option;
+ char *exit_boot = "boot";
+ char *exit_back = "back";
+ cmd_tbl_t *cmd;
+ int cmd_result;
+ int cmd_repeatable;
+ int leave;
+
+ lcd_clear();
+
+ switch (mode) {
+ case BOOT_MODE_EXIT:
+ return 1;
+ case BOOT_MODE_INFO:
+ display_board_info();
+ exit_option = exit_back;
+ leave = 0;
+ break;
+ default:
+ cmd = find_cmd(mode_cmd[mode][0]);
+ if (cmd) {
+ printf("Enter: %s %s\n", mode_name[mode],
+ mode_info[mode]);
+ lcd_printf("\n\n\t%s %s\n", mode_name[mode],
+ mode_info[mode]);
+ lcd_puts("\n\tDo not turn off device before finish!\n");
+
+ cmd_result = cmd_process(0, MODE_CMD_ARGC,
+ *(mode_cmd + mode),
+ &cmd_repeatable, NULL);
+
+ if (cmd_result == CMD_RET_SUCCESS) {
+ printf("Command finished\n");
+ lcd_clear();
+ lcd_printf("\n\n\t%s finished\n",
+ mode_name[mode]);
+
+ exit_option = exit_boot;
+ leave = 1;
+ } else {
+ printf("Command error\n");
+ lcd_clear();
+ lcd_printf("\n\n\t%s command error\n",
+ mode_name[mode]);
+
+ exit_option = exit_back;
+ leave = 0;
+ }
+ } else {
+ lcd_puts("\n\n\tThis mode is not supported.\n");
+ exit_option = exit_back;
+ leave = 0;
+ }
+ }
+
+ lcd_printf("\n\n\tPress POWER KEY to %s\n", exit_option);
+
+ /* Clear PWR button Rising edge interrupt status flag */
+ power_key_pressed(KEY_PWR_INTERRUPT_REG);
+
+ /* Wait for PWR key */
+ while (!key_pressed(KEY_POWER))
+ mdelay(1);
+
+ lcd_clear();
+ return leave;
+}
+
+static void display_download_menu(int mode)
+{
+ char *selection[BOOT_MODE_EXIT + 1];
+ int i;
+
+ for (i = 0; i <= BOOT_MODE_EXIT; i++)
+ selection[i] = "[ ]";
+
+ selection[mode] = "[=>]";
+
+ lcd_clear();
+ lcd_printf("\n\t\tDownload Mode Menu\n");
+
+ for (i = 0; i <= BOOT_MODE_EXIT; i++)
+ lcd_printf("\t%s %s - %s\n\n", selection[i],
+ mode_name[i],
+ mode_info[i]);
+}
+
+static void download_menu(void)
+{
+ int mode = 0;
+ int last_mode = 0;
+ int run;
+ int key;
+
+ display_download_menu(mode);
+
+ while (1) {
+ run = 0;
+
+ if (mode != last_mode)
+ display_download_menu(mode);
+
+ last_mode = mode;
+ mdelay(100);
+
+ key = check_keys();
+ switch (key) {
+ case KEY_POWER:
+ run = 1;
+ break;
+ case KEY_VOLUMEUP:
+ if (mode > 0)
+ mode--;
+ break;
+ case KEY_VOLUMEDOWN:
+ if (mode < BOOT_MODE_EXIT)
+ mode++;
+ break;
+ default:
+ break;
+ }
+
+ if (run) {
+ if (mode_leave_menu(mode))
+ break;
+
+ display_download_menu(mode);
+ }
+ }
+
+ lcd_clear();
+}
+
+static void display_mode_info(void)
+{
+ lcd_position_cursor(4, 4);
+ lcd_printf("%s\n", U_BOOT_VERSION);
+ lcd_puts("\nDownload Mode Menu\n");
+#ifdef CONFIG_SYS_BOARD
+ lcd_printf("Board name: %s\n", CONFIG_SYS_BOARD);
+#endif
+ lcd_printf("Press POWER KEY to display MENU options.");
+}
+
+static int boot_menu(void)
+{
+ int key = 0;
+ int timeout = 10;
+
+ display_mode_info();
+
+ while (timeout--) {
+ lcd_printf("\rNormal boot will start in: %d seconds.", timeout);
+ mdelay(1000);
+
+ key = key_pressed(KEY_POWER);
+ if (key)
+ break;
+ }
+
+ lcd_clear();
+
+ /* If PWR pressed - show download menu */
+ if (key) {
+ printf("Power pressed - go to download menu\n");
+ download_menu();
+ printf("Download mode exit.\n");
+ }
+
+ return 0;
+}
+
+void check_boot_mode(void)
+{
+ int pwr_key;
+
+ pwr_key = power_key_pressed(KEY_PWR_STATUS_REG);
+ if (!pwr_key)
+ return;
+
+ /* Clear PWR button Rising edge interrupt status flag */
+ power_key_pressed(KEY_PWR_INTERRUPT_REG);
+
+ if (key_pressed(KEY_VOLUMEUP))
+ boot_menu();
+ else if (key_pressed(KEY_VOLUMEDOWN))
+ mode_leave_menu(BOOT_MODE_THOR);
+}
+
+void keys_init(void)
+{
+ /* Set direction to input */
+ gpio_direction_input(KEY_VOL_UP_GPIO);
+ gpio_direction_input(KEY_VOL_DOWN_GPIO);
+}
+#endif /* CONFIG_LCD_MENU */
+
+#ifdef CONFIG_CMD_BMP
+void draw_logo(void)
+{
+ int x, y;
+ ulong addr;
+
+ addr = panel_info.logo_addr;
+ if (!addr) {
+ error("There is no logo data.");
+ return;
+ }
+
+ if (panel_info.vl_width >= panel_info.logo_width) {
+ x = ((panel_info.vl_width - panel_info.logo_width) >> 1);
+ x += panel_info.logo_x_offset; /* For X center align */
+ } else {
+ x = 0;
+ printf("Warning: image width is bigger than display width\n");
+ }
+
+ if (panel_info.vl_height >= panel_info.logo_height) {
+ y = ((panel_info.vl_height - panel_info.logo_height) >> 1);
+ y += panel_info.logo_y_offset; /* For Y center align */
+ } else {
+ y = 0;
+ printf("Warning: image height is bigger than display height\n");
+ }
+
+ bmp_display(addr, x, y);
+}
+#endif /* CONFIG_CMD_BMP */
#include <usb/s3c_udc.h>
#include <asm/arch/cpu.h>
#include <power/max8998_pmic.h>
+#include <samsung/misc.h>
+
DECLARE_GLOBAL_DATA_PTR;
static struct s5pc110_gpio *s5pc110_gpio;
+u32 get_board_rev(void)
+{
+ return 0;
+}
+
int board_init(void)
{
/* Set Initial global variables */
.usb_phy_ctrl = S5PC110_USB_PHY_CONTROL,
};
#endif
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ set_board_info();
+#endif
+ return 0;
+}
+#endif
* r9 has Mobile DDR size, 1 means 1GiB, 2 means 2GiB and so on
*/
-_TEXT_BASE:
- .word CONFIG_SYS_TEXT_BASE
-
.globl lowlevel_init
lowlevel_init:
mov r11, lr
# SPDX-License-Identifier: GPL-2.0+
#
-ifndef CONFIG_SPL_BUILD
-obj-y += origen.o
-endif
-
ifdef CONFIG_SPL_BUILD
-all: $(OBJTREE)/tools/mk$(BOARD)spl
-endif
+# necessary to create built-in.o
+obj- := __dummy__.o
-# Fix ME after we implement hostprogs-y.
-ifdef CONFIG_SPL_BUILD
-$(OBJTREE)/tools/mk$(BOARD)spl: tools/mkv310_image.c
- $(HOSTCC) tools/mkv310_image.c -o $(OBJTREE)/tools/mk$(BOARD)spl
+hostprogs-y := tools/mkorigenspl
+always := $(hostprogs-y)
+
+# omit -O2 option to suppress
+# warning: dereferencing type-punned pointer will break strict-aliasing rules
+#
+# TODO:
+# Fix the root cause in tools/mkorigenspl.c and delete the following work-around
+$(obj)/tools/mkorigenspl: HOSTCFLAGS:=$(filter-out -O2,$(HOSTCFLAGS))
+else
+obj-y += origen.o
endif
#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
/**************************************/
-_TEXT_BASE:
- .word CONFIG_SYS_TEXT_BASE
-
.globl lowlevel_init
lowlevel_init:
/* memory control configuration */
/* make r0 relative the current location so that it */
/* reads SMRDATA out of FLASH rather than memory ! */
ldr r0, =SMRDATA
- ldr r1, _TEXT_BASE
+ ldr r1, =CONFIG_SYS_TEXT_BASE
sub r0, r0, r1
ldr r1, =BWSCON /* Bus Width Status Controller */
add r2, r0, #13*4
+++ /dev/null
-/*
- * Lowlevel setup for SMDK5250 board based on S5PC520
- *
- * Copyright (C) 2012 Samsung Electronics
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/cpu.h>
-
-_TEXT_BASE:
- .word CONFIG_SYS_TEXT_BASE
-
- .globl lowlevel_init
-lowlevel_init:
-
- /* use iRAM stack in bl2 */
- ldr sp, =CONFIG_IRAM_STACK
- stmdb r13!, {ip,lr}
-
- /* check reset status */
- ldr r0, =(EXYNOS5_POWER_BASE + INFORM1_OFFSET)
- ldr r1, [r0]
-
- /* AFTR wakeup reset */
- ldr r2, =S5P_CHECK_DIDLE
- cmp r1, r2
- beq exit_wakeup
-
- /* LPA wakeup reset */
- ldr r2, =S5P_CHECK_LPA
- cmp r1, r2
- beq exit_wakeup
-
- /* Sleep wakeup reset */
- ldr r2, =S5P_CHECK_SLEEP
- cmp r1, r2
- beq wakeup_reset
-
- /*
- * If U-boot is already running in RAM, no need to relocate U-Boot.
- * Memory controller must be configured before relocating U-Boot
- * in ram.
- */
- ldr r0, =0x0ffffff /* r0 <- Mask Bits*/
- bic r1, pc, r0 /* pc <- current addr of code */
- /* r1 <- unmasked bits of pc */
- ldr r2, _TEXT_BASE /* r2 <- original base addr in ram */
- bic r2, r2, r0 /* r2 <- unmasked bits of r2*/
- cmp r1, r2 /* compare r1, r2 */
- beq 1f /* r0 == r1 then skip sdram init */
-
- /* init system clock */
- bl system_clock_init
-
- /* Memory initialize */
- bl mem_ctrl_init
-
-1:
- bl arch_cpu_init
- bl tzpc_init
- ldmia r13!, {ip,pc}
-
-wakeup_reset:
- bl system_clock_init
- bl mem_ctrl_init
- bl arch_cpu_init
- bl tzpc_init
-
-exit_wakeup:
- /* Load return address and jump to kernel */
- ldr r0, =(EXYNOS5_POWER_BASE + INFORM0_OFFSET)
-
- /* r1 = physical address of exynos5_cpu_resume function*/
- ldr r1, [r0]
-
- /* Jump to kernel */
- mov pc, r1
- nop
- nop
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_USB_EHCI_EXYNOS
-static int board_usb_vbus_init(void)
-{
- struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
- samsung_get_base_gpio_part1();
-
- /* Enable VBUS power switch */
- s5p_gpio_direction_output(&gpio1->x2, 6, 1);
-
- /* VBUS turn ON time */
- mdelay(3);
-
- return 0;
-}
-#endif
-
#ifdef CONFIG_SOUND_MAX98095
static void board_enable_audio_codec(void)
{
int exynos_init(void)
{
-#ifdef CONFIG_USB_EHCI_EXYNOS
- board_usb_vbus_init();
-#endif
#ifdef CONFIG_SOUND_MAX98095
board_enable_audio_codec();
#endif
* r5 has zero always
*/
-_TEXT_BASE:
- .word CONFIG_SYS_TEXT_BASE
-
.globl lowlevel_init
lowlevel_init:
mov r9, lr
# SPDX-License-Identifier: GPL-2.0+
#
-ifndef CONFIG_SPL_BUILD
-obj-y += smdkv310.o
-endif
-
ifdef CONFIG_SPL_BUILD
-all: $(OBJTREE)/tools/mk$(BOARD)spl
-endif
+# necessary to create built-in.o
+obj- := __dummy__.o
-# Fix ME after we implement hostprogs-y.
-ifdef CONFIG_SPL_BUILD
-$(OBJTREE)/tools/mk$(BOARD)spl: tools/mkv310_image.c
- $(HOSTCC) tools/mkv310_image.c -o $(OBJTREE)/tools/mk$(BOARD)spl
+hostprogs-y := tools/mksmdkv310spl
+always := $(hostprogs-y)
+else
+obj-y += smdkv310.o
endif
#include <power/max17042_fg.h>
#include <usb.h>
#include <usb_mass_storage.h>
+#include <samsung/misc.h>
#include "setup.h"
.vl_hsp = CONFIG_SYS_LOW,
.vl_vsp = CONFIG_SYS_LOW,
.vl_dp = CONFIG_SYS_LOW,
- .vl_bpix = 5, /* Bits per pixel, 2^5 = 32 */
+ .vl_bpix = 4, /* Bits per pixel, 2^4 = 16 */
/* s6e8ax0 Panel infomation */
.vl_hspw = 5,
setenv("lcdinfo", "lcd=s6e8ax0");
}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ set_board_info();
+#endif
+#ifdef CONFIG_LCD_MENU
+ keys_init();
+ check_boot_mode();
+#endif
+#ifdef CONFIG_CMD_BMP
+ if (panel_info.logo_on)
+ draw_logo();
+#endif
+ return 0;
+}
+#endif
#include <usb.h>
#include <usb/s3c_udc.h>
#include <usb_mass_storage.h>
+#include <samsung/misc.h>
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
puts("Board:\tTRATS2\n");
+ printf("HW Revision:\t0x%04x\n", board_rev);
+
return 0;
}
#endif
-static void show_hw_revision(void)
-{
- printf("HW Revision:\t0x%04x\n", board_rev);
-}
-
u32 get_board_rev(void)
{
return board_rev;
int get_soft_i2c_scl_pin(void)
{
if (I2C_ADAP_HWNR)
- return exynos4x12_gpio_part2_get_nr(m2, 1); /* I2C9 */
+ return exynos4x12_gpio_get(2, m2, 1); /* I2C9 */
else
- return exynos4x12_gpio_part1_get_nr(f1, 4); /* I2C8 */
+ return exynos4x12_gpio_get(1, f1, 4); /* I2C8 */
}
int get_soft_i2c_sda_pin(void)
{
if (I2C_ADAP_HWNR)
- return exynos4x12_gpio_part2_get_nr(m2, 0); /* I2C9 */
+ return exynos4x12_gpio_get(2, m2, 0); /* I2C9 */
else
- return exynos4x12_gpio_part1_get_nr(f1, 5); /* I2C8 */
+ return exynos4x12_gpio_get(1, f1, 5); /* I2C8 */
}
#endif
.vl_hsp = CONFIG_SYS_LOW,
.vl_vsp = CONFIG_SYS_LOW,
.vl_dp = CONFIG_SYS_LOW,
- .vl_bpix = 5, /* Bits per pixel, 2^5 = 32 */
+ .vl_bpix = 4, /* Bits per pixel, 2^4 = 16 */
/* s6e8ax0 Panel infomation */
.vl_hspw = 5,
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
- setenv("model", "GT-I8800");
- setenv("board", "TRATS2");
-
- show_hw_revision();
-
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ set_board_info();
+#endif
+#ifdef CONFIG_LCD_MENU
+ keys_init();
+ check_boot_mode();
+#endif
+#ifdef CONFIG_CMD_BMP
+ if (panel_info.logo_on)
+ draw_logo();
+#endif
return 0;
}
#endif
#include <usb/s3c_udc.h>
#include <asm/arch/cpu.h>
#include <power/max8998_pmic.h>
+#include <samsung/misc.h>
DECLARE_GLOBAL_DATA_PTR;
.vl_vsp = CONFIG_SYS_HIGH,
.vl_dp = CONFIG_SYS_HIGH,
- .vl_bpix = 5, /* Bits per pixel */
+ .vl_bpix = 4, /* Bits per pixel */
/* LD9040 LCD Panel */
.vl_hspw = 2,
return 0;
}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ set_board_info();
+#endif
+#ifdef CONFIG_LCD_MENU
+ keys_init();
+ check_boot_mode();
+#endif
+#ifdef CONFIG_CMD_BMP
+ if (panel_info.logo_on)
+ draw_logo();
+#endif
+ return 0;
+}
+#endif
#
# TBS: add for debugging purposes
-BUILDUSER := $(shell whoami)
-FORCEBUILD := $(shell rm -f karef.o)
-
-CFLAGS += -DBUILDUSER='"$(BUILDUSER)"'
-# TBS: end debugging
+ccflags-y += -DBUILDUSER='"$(shell whoami)"'
obj-y = karef.o ../common/flash.o ../common/sb_common.o
extra-y += init.o
#
# TBS: add for debugging purposes
-BUILDUSER := $(shell whoami)
-FORCEBUILD := $(shell rm -f metrobox.o)
-
-CFLAGS += -DBUILDUSER='"$(BUILDUSER)"'
-# TBS: end debugging
+ccflags-y += -DBUILDUSER='"$(shell whoami)"'
obj-y = metrobox.o ../common/flash.o ../common/sb_common.o
extra-y += init.o
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
- .phy_id = 0,
+ .phy_addr = 0,
.phy_if = PHY_INTERFACE_MODE_MII,
},
};
factoryset_setenv();
+ /* Reset SMSC LAN9303 switch for default configuration */
+ gpio_request(GPIO_LAN9303_NRST, "nRST");
+ gpio_direction_output(GPIO_LAN9303_NRST, 0);
+ /* assert active low reset for 200us */
+ udelay(200);
+ gpio_set_value(GPIO_LAN9303_NRST, 1);
+
/* Set rgmii mode and enable rmii clock to be sourced from chip */
writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
{OFFSET(ain0), MODE(7) | RXACTIVE | PULLUDDIS},
{OFFSET(vrefp), MODE(7) | RXACTIVE | PULLUDDIS},
{OFFSET(vrefn), MODE(7) | RXACTIVE | PULLUDDIS},
+ /* nRST for SMSC LAN9303 switch - GPIO2_24 */
+ {OFFSET(lcd_pclk), MODE(7) }, /* LAN9303 nRST */
{-1},
};
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
- .phy_id = 0,
+ .phy_addr = 0,
.phy_if = PHY_INTERFACE_MODE_RMII,
},
{
.slave_reg_ofs = 0x308,
.sliver_reg_ofs = 0xdc0,
- .phy_id = 1,
+ .phy_addr = 1,
.phy_if = PHY_INTERFACE_MODE_RMII,
},
};
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
- .phy_id = 1,
+ .phy_addr = 1,
.phy_if = PHY_INTERFACE_MODE_RMII,
},
{
.slave_reg_ofs = 0x308,
.sliver_reg_ofs = 0xdc0,
- .phy_id = 0,
+ .phy_addr = 0,
.phy_if = PHY_INTERFACE_MODE_RMII,
},
};
--- /dev/null
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_NOR_BOOT),y)
+obj-y := mux.o
+endif
+
+obj-y += board.o
--- /dev/null
+/*
+ * board.c
+ *
+ * Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <i2c.h>
+#include <phy.h>
+#include <cpsw.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+#if defined(CONFIG_SPL_BUILD)
+
+/* DDR3 RAM timings */
+static const struct ddr_data ddr3_data = {
+ .datardsratio0 = MT41K128MJT187E_RD_DQS,
+ .datawdsratio0 = MT41K128MJT187E_WR_DQS,
+ .datafwsratio0 = MT41K128MJT187E_PHY_FIFO_WE,
+ .datawrsratio0 = MT41K128MJT187E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+ .cmd0csratio = MT41K128MJT187E_RATIO,
+ .cmd0iclkout = MT41K128MJT187E_INVERT_CLKOUT,
+ .cmd1csratio = MT41K128MJT187E_RATIO,
+ .cmd1iclkout = MT41K128MJT187E_INVERT_CLKOUT,
+ .cmd2csratio = MT41K128MJT187E_RATIO,
+ .cmd2iclkout = MT41K128MJT187E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+ .sdram_config = MT41K128MJT187E_EMIF_SDCFG,
+ .ref_ctrl = MT41K128MJT187E_EMIF_SDREF,
+ .sdram_tim1 = MT41K128MJT187E_EMIF_TIM1,
+ .sdram_tim2 = MT41K128MJT187E_EMIF_TIM2,
+ .sdram_tim3 = MT41K128MJT187E_EMIF_TIM3,
+ .zq_config = MT41K128MJT187E_ZQ_CFG,
+ .emif_ddr_phy_ctlr_1 = MT41K128MJT187E_EMIF_READ_LATENCY |
+ PHY_EN_DYN_PWRDN,
+};
+
+const struct ctrl_ioregs ddr3_ioregs = {
+ .cm0ioctl = MT41K128MJT187E_IOCTRL_VALUE,
+ .cm1ioctl = MT41K128MJT187E_IOCTRL_VALUE,
+ .cm2ioctl = MT41K128MJT187E_IOCTRL_VALUE,
+ .dt0ioctl = MT41K128MJT187E_IOCTRL_VALUE,
+ .dt1ioctl = MT41K128MJT187E_IOCTRL_VALUE,
+};
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+ /* break into full u-boot on 'c' */
+ return serial_tstc() && serial_getc() == 'c';
+}
+#endif
+
+#define OSC (V_OSCK/1000000)
+const struct dpll_params dpll_ddr_266 = {
+ 266, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_ddr_303 = {
+ 303, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_ddr_400 = {
+ 400, OSC-1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+ /*
+ * The pengwyn board uses the TPS650250 PMIC without I2C
+ * interface and will output the following fixed voltages:
+ * DCDC1=3V3 (IO) DCDC2=1V5 (DDR) DCDC3=1V26 (Vmpu)
+ * VLDO1=1V8 (IO) VLDO2=1V8(IO)
+ * Vcore=1V1 is fixed, generated by TPS62231
+ */
+
+ /* Get the frequency */
+ dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+
+ /* Set CORE Frequencies to OPP100 */
+ do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+ /* 720MHz cpu, this might change on newer board revisions */
+ dpll_mpu_opp100.m = MPUPLL_M_720;
+ do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+ /* future configs can return other clock settings */
+ return &dpll_ddr_303;
+}
+
+void set_uart_mux_conf(void)
+{
+ enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+ enable_board_pin_mux();
+}
+
+void sdram_init(void)
+{
+ config_ddr(303, &ddr3_ioregs, &ddr3_data,
+ &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
+}
+#endif /* if CONFIG_SPL_BUILD */
+
+/*
+ * Basic board specific setup. Pinmux has been handled already.
+ */
+int board_init(void)
+{
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gpmc_init();
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+static void cpsw_control(int enabled)
+{
+ /* VTP can be added here */
+ return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_addr = 0,
+ .phy_if = PHY_INTERFACE_MODE_MII,
+ },
+ {
+ .slave_reg_ofs = 0x308,
+ .sliver_reg_ofs = 0xdc0,
+ .phy_addr = 1,
+ .phy_if = PHY_INTERFACE_MODE_MII,
+ },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 1,
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .bd_ram_ofs = 0x2000,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+
+int board_eth_init(bd_t *bis)
+{
+ int rv, n = 0;
+ uint8_t mac_addr[6];
+ uint32_t mac_hi, mac_lo;
+
+ if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
+ printf("<ethaddr> not set. Reading from E-fuse\n");
+ /* try reading mac address from efuse */
+ mac_lo = readl(&cdev->macid0l);
+ mac_hi = readl(&cdev->macid0h);
+ mac_addr[0] = mac_hi & 0xFF;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+ mac_addr[4] = mac_lo & 0xFF;
+ mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+ if (is_valid_ether_addr(mac_addr))
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ else
+ return n;
+ }
+
+ writel(MII_MODE_ENABLE, &cdev->miisel);
+
+ rv = cpsw_register(&cpsw_data);
+ if (rv < 0)
+ printf("Error %d registering CPSW switch\n", rv);
+ else
+ n += rv;
+ return n;
+}
+#endif /* if CONFIG_DRIVER_TI_CPSW */
--- /dev/null
+/*
+ * board.h
+ *
+ * Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+void enable_uart0_pin_mux(void);
+void enable_board_pin_mux(void);
+
+#endif
--- /dev/null
+/*
+ * mux.c
+ *
+ * Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include "board.h"
+
+/* UART0 pins E15(rx),E16(tx) [E17(rts),E18(cts)] */
+static struct module_pin_mux uart0_pin_mux[] = {
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
+ {-1},
+};
+
+/* unused: UART1 pins D15(tx),D16(rx),D17(cts),D18(rts) */
+
+/* I2C pins C16(scl)/C17(sda) */
+static struct module_pin_mux i2c0_pin_mux[] = {
+ {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C0_DATA */
+ {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C0_SCLK */
+ {-1},
+};
+
+/* MMC0 pins */
+static struct module_pin_mux mmc0_pin_mux[] = {
+ {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
+ {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
+ {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
+ {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
+ {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
+ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
+ {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
+ {-1},
+};
+
+/* MII pins */
+static struct module_pin_mux mii1_pin_mux[] = {
+ {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
+ {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
+ {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
+ {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
+ {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
+ {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
+ {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
+ {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
+ {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
+ {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
+ {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
+ {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
+ {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {-1},
+};
+
+/* NAND pins */
+static struct module_pin_mux nand_pin_mux[] = {
+ {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
+ {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
+ {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
+ {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
+ {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
+ {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
+ {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
+ {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
+ {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+ {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
+ {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
+ {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
+ {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
+ {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
+ {-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_board_pin_mux()
+{
+ configure_module_pin_mux(i2c0_pin_mux);
+ configure_module_pin_mux(uart0_pin_mux);
+ configure_module_pin_mux(mii1_pin_mux);
+ configure_module_pin_mux(mmc0_pin_mux);
+ configure_module_pin_mux(nand_pin_mux);
+}
# SPDX-License-Identifier: GPL-2.0+
#
-ifndef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_BUILD
+# necessary to create built-in.o
+obj- := __dummy__.o
+else
obj-y := spr_misc.o
obj-y += spr_lowlevel_init.o
endif
#if defined(CONFIG_DESIGNWARE_ETH)
u32 interface = PHY_INTERFACE_MODE_MII;
- if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY,
- interface) >= 0)
+ if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
ret++;
#endif
return ret;
#if defined(CONFIG_DESIGNWARE_ETH)
u32 interface = PHY_INTERFACE_MODE_MII;
- if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY,
- interface) >= 0)
+ if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
ret++;
#endif
#if defined(CONFIG_MACB)
#if defined(CONFIG_DESIGNWARE_ETH)
u32 interface = PHY_INTERFACE_MODE_MII;
- if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY,
- interface) >= 0)
+ if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
ret++;
#endif
#if defined(CONFIG_MACB)
#if defined(CONFIG_DW_AUTONEG)
interface = PHY_INTERFACE_MODE_GMII;
#endif
- if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY,
- interface) >= 0)
+ if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
ret++;
#endif
return ret;
# SPDX-License-Identifier: GPL-2.0+
#
-ifndef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_BUILD
+# necessary to create built-in.o
+obj- := __dummy__.o
+else
obj-y := fpga.o x600.o
endif
fsmc_nand_init(nand);
}
-int designware_board_phy_init(struct eth_device *dev, int phy_addr,
- int (*mii_write)(struct eth_device *, u8, u8, u16),
- int dw_reset_phy(struct eth_device *))
+int board_phy_config(struct phy_device *phydev)
{
/* Extended PHY control 1, select GMII */
- mii_write(dev, phy_addr, 23, 0x0020);
+ phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020);
/* Software reset necessary after GMII mode selction */
- dw_reset_phy(dev);
+ phy_reset(phydev);
/* Enable extended page register access */
- mii_write(dev, phy_addr, 31, 0x0001);
+ phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001);
/* 17e: Enhanced LED behavior, needs to be written twice */
- mii_write(dev, phy_addr, 17, 0x09ff);
- mii_write(dev, phy_addr, 17, 0x09ff);
+ phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
+ phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
/* 16e: Enhanced LED method select */
- mii_write(dev, phy_addr, 16, 0xe0ea);
+ phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea);
/* Disable extended page register access */
- mii_write(dev, phy_addr, 31, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000);
/* Enable clock output pin */
- mii_write(dev, phy_addr, 18, 0x0049);
+ phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
return 0;
}
{
int ret = 0;
- if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_PHY_ADDR,
+ if (designware_initialize(CONFIG_SPEAR_ETHBASE,
PHY_INTERFACE_MODE_GMII) >= 0)
ret++;
# SPDX-License-Identifier: GPL-2.0+
#
-CFLAGS += -D__RELEASE -D__STN_8500
+ccflags-y += -D__RELEASE -D__STN_8500
obj-y := snowball.o
# SPDX-License-Identifier: GPL-2.0+
#
-CFLAGS += -D__RELEASE -D__STN_8500
+ccflags-y += -D__RELEASE -D__STN_8500
obj-y := u8500_href.o gpio.o
--- /dev/null
+#
+# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+# This board is mostly used for debugging U-Boot in simulation (ISS).
+# The only peripheral which is used on this board is a serial port which
+# requires no initialization except those in "include/configs/arcangel4.h".
+# And now there's no specific initializations for this board.
+# So this Makefile is only required for satisfaction of U-Boot build system.
--- /dev/null
+#
+# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += axs101.o
+obj-$(CONFIG_CMD_NAND) += nand.o
--- /dev/null
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dwmmc.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <phy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_mmc_init(bd_t *bis)
+{
+ struct dwmci_host *host = NULL;
+
+ host = malloc(sizeof(struct dwmci_host));
+ if (!host) {
+ printf("dwmci_host malloc fail!\n");
+ return 1;
+ }
+
+ memset(host, 0, sizeof(struct dwmci_host));
+ host->name = "Synopsys Mobile storage";
+ host->ioaddr = (void *)ARC_DWMMC_BASE;
+ host->buswidth = 4;
+ host->dev_index = 0;
+ host->bus_hz = 25000000;
+
+ add_dwmci(host, 52000000, 400000);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ if (designware_initialize(ARC_DWGMAC_BASE,
+ PHY_INTERFACE_MODE_RGMII) >= 0)
+ return 1;
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <bouncebuf.h>
+#include <common.h>
+#include <malloc.h>
+#include <nand.h>
+#include <asm/io.h>
+
+#define BUS_WIDTH 8 /* AXI data bus width in bytes */
+
+/* DMA buffer descriptor bits & masks */
+#define BD_STAT_OWN (1 << 31)
+#define BD_STAT_BD_FIRST (1 << 3)
+#define BD_STAT_BD_LAST (1 << 2)
+#define BD_SIZES_BUFFER1_MASK 0xfff
+
+#define BD_STAT_BD_COMPLETE (BD_STAT_BD_FIRST | BD_STAT_BD_LAST)
+
+/* Controller command flags */
+#define B_WFR (1 << 19) /* 1b - Wait for ready */
+#define B_LC (1 << 18) /* 1b - Last cycle */
+#define B_IWC (1 << 13) /* 1b - Interrupt when complete */
+
+/* NAND cycle types */
+#define B_CT_ADDRESS (0x0 << 16) /* Address operation */
+#define B_CT_COMMAND (0x1 << 16) /* Command operation */
+#define B_CT_WRITE (0x2 << 16) /* Write operation */
+#define B_CT_READ (0x3 << 16) /* Write operation */
+
+enum nand_isr_t {
+ NAND_ISR_DATAREQUIRED = 0,
+ NAND_ISR_TXUNDERFLOW,
+ NAND_ISR_TXOVERFLOW,
+ NAND_ISR_DATAAVAILABLE,
+ NAND_ISR_RXUNDERFLOW,
+ NAND_ISR_RXOVERFLOW,
+ NAND_ISR_TXDMACOMPLETE,
+ NAND_ISR_RXDMACOMPLETE,
+ NAND_ISR_DESCRIPTORUNAVAILABLE,
+ NAND_ISR_CMDDONE,
+ NAND_ISR_CMDAVAILABLE,
+ NAND_ISR_CMDERROR,
+ NAND_ISR_DATATRANSFEROVER,
+ NAND_ISR_NONE
+};
+
+enum nand_regs_t {
+ AC_FIFO = 0, /* address and command fifo */
+ IDMAC_BDADDR = 0x18, /* idmac descriptor list base address */
+ INT_STATUS = 0x118, /* interrupt status register */
+ INT_CLR_STATUS = 0x120, /* interrupt clear status register */
+};
+
+struct nand_bd {
+ uint32_t status; /* DES0 */
+ uint32_t sizes; /* DES1 */
+ uint32_t buffer_ptr0; /* DES2 */
+ uint32_t buffer_ptr1; /* DES3 */
+};
+
+#define NAND_REG_WRITE(r, v) writel(v, CONFIG_SYS_NAND_BASE + r)
+#define NAND_REG_READ(r) readl(CONFIG_SYS_NAND_BASE + r)
+
+static struct nand_bd *bd; /* DMA buffer descriptors */
+
+/**
+ * axs101_nand_write_buf - write buffer to chip
+ * @mtd: MTD device structure
+ * @buf: data buffer
+ * @len: number of bytes to write
+ */
+static uint32_t nand_flag_is_set(uint32_t flag)
+{
+ uint32_t reg = NAND_REG_READ(INT_STATUS);
+
+ if (reg & (1 << NAND_ISR_CMDERROR))
+ return 0;
+
+ if (reg & (1 << flag)) {
+ NAND_REG_WRITE(INT_CLR_STATUS, 1 << flag);
+ return 1;
+ }
+
+ return 0;
+}
+
+/**
+ * axs101_nand_write_buf - write buffer to chip
+ * @mtd: MTD device structure
+ * @buf: data buffer
+ * @len: number of bytes to write
+ */
+static void axs101_nand_write_buf(struct mtd_info *mtd, const u_char *buf,
+ int len)
+{
+ struct bounce_buffer bbstate;
+
+ bounce_buffer_start(&bbstate, (void *)buf, len, GEN_BB_READ);
+
+ /* Setup buffer descriptor */
+ writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, &bd->status);
+ writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, &bd->sizes);
+ writel(bbstate.bounce_buffer, &bd->buffer_ptr0);
+ writel(0, &bd->buffer_ptr1);
+
+ /* Issue "write" command */
+ NAND_REG_WRITE(AC_FIFO, B_CT_WRITE | B_WFR | B_IWC | B_LC | (len-1));
+
+ /* Wait for NAND command and DMA to complete */
+ while (!nand_flag_is_set(NAND_ISR_CMDDONE))
+ ;
+ while (!nand_flag_is_set(NAND_ISR_TXDMACOMPLETE))
+ ;
+
+ bounce_buffer_stop(&bbstate);
+}
+
+/**
+ * axs101_nand_read_buf - read chip data into buffer
+ * @mtd: MTD device structure
+ * @buf: buffer to store data
+ * @len: number of bytes to read
+ */
+static void axs101_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+ struct bounce_buffer bbstate;
+
+ bounce_buffer_start(&bbstate, buf, len, GEN_BB_WRITE);
+
+ /* Setup buffer descriptor */
+ writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, &bd->status);
+ writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, &bd->sizes);
+ writel(bbstate.bounce_buffer, &bd->buffer_ptr0);
+ writel(0, &bd->buffer_ptr1);
+
+ /* Issue "read" command */
+ NAND_REG_WRITE(AC_FIFO, B_CT_READ | B_WFR | B_IWC | B_LC | (len - 1));
+
+ /* Wait for NAND command and DMA to complete */
+ while (!nand_flag_is_set(NAND_ISR_CMDDONE))
+ ;
+ while (!nand_flag_is_set(NAND_ISR_RXDMACOMPLETE))
+ ;
+
+ bounce_buffer_stop(&bbstate);
+}
+
+/**
+ * axs101_nand_read_byte - read one byte from the chip
+ * @mtd: MTD device structure
+ */
+static u_char axs101_nand_read_byte(struct mtd_info *mtd)
+{
+ u8 byte;
+
+ axs101_nand_read_buf(mtd, (uchar *)&byte, sizeof(byte));
+ return byte;
+}
+
+/**
+ * axs101_nand_read_word - read one word from the chip
+ * @mtd: MTD device structure
+ */
+static u16 axs101_nand_read_word(struct mtd_info *mtd)
+{
+ u16 word;
+
+ axs101_nand_read_buf(mtd, (uchar *)&word, sizeof(word));
+ return word;
+}
+
+/**
+ * axs101_nand_hwcontrol - NAND control functions wrapper.
+ * @mtd: MTD device structure
+ * @cmd: Command
+ */
+static void axs101_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd,
+ unsigned int ctrl)
+{
+ if (cmd == NAND_CMD_NONE)
+ return;
+
+ cmd = cmd & 0xff;
+
+ switch (ctrl & (NAND_ALE | NAND_CLE)) {
+ /* Address */
+ case NAND_ALE:
+ cmd |= B_CT_ADDRESS;
+ break;
+
+ /* Command */
+ case NAND_CLE:
+ cmd |= B_CT_COMMAND | B_WFR;
+
+ break;
+
+ default:
+ debug("%s: unknown ctrl %#x\n", __func__, ctrl);
+ }
+
+ NAND_REG_WRITE(AC_FIFO, cmd | B_LC);
+ while (!nand_flag_is_set(NAND_ISR_CMDDONE))
+ ;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+ bd = (struct nand_bd *)memalign(ARCH_DMA_MINALIGN,
+ sizeof(struct nand_bd));
+
+ /* Set buffer descriptor address in IDMAC */
+ NAND_REG_WRITE(IDMAC_BDADDR, bd);
+
+ nand->ecc.mode = NAND_ECC_SOFT;
+ nand->cmd_ctrl = axs101_nand_hwcontrol;
+ nand->read_byte = axs101_nand_read_byte;
+ nand->read_word = axs101_nand_read_word;
+ nand->write_buf = axs101_nand_write_buf;
+ nand->read_buf = axs101_nand_read_buf;
+
+ return 0;
+}
# SPDX-License-Identifier: GPL-2.0+
#
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
# SPDX-License-Identifier: GPL-2.0+
#
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
+# FIX ME
+ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
+ccflags-y := -O2
+endif
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
- .phy_id = 0,
+ .phy_addr = 0,
},
{
.slave_reg_ofs = 0x308,
.sliver_reg_ofs = 0xdc0,
- .phy_id = 1,
+ .phy_addr = 1,
},
};
}
#ifdef CONFIG_DRIVER_TI_CPSW
+
+ mac_lo = readl(&cdev->macid1l);
+ mac_hi = readl(&cdev->macid1h);
+ mac_addr[0] = mac_hi & 0xFF;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+ mac_addr[4] = mac_lo & 0xFF;
+ mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+ if (!getenv("eth1addr")) {
+ if (is_valid_ether_addr(mac_addr))
+ eth_setenv_enetaddr("eth1addr", mac_addr);
+ }
+
if (read_eeprom(&header) < 0)
puts("Could not get board ID.\n");
*(.__rel_dyn_end)
}
- _end = .;
+ .end :
+ {
+ *(.__end)
+ }
+
+ _image_binary_end = .;
/*
* Deprecated: this MMU section is used by pxa at present but
KEEP(*(.__bss_end));
}
- .dynsym _end : { *(.dynsym) }
+ .dynsym _image_binary_end : { *(.dynsym) }
.dynbss : { *(.dynbss) }
.dynstr : { *(.dynstr*) }
.dynamic : { *(.dynamic*) }
#include <asm/arch/gpio.h>
#include <asm/emif.h>
#include "board.h"
+#include <miiphy.h>
+#include <cpsw.h>
DECLARE_GLOBAL_DATA_PTR;
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
/*
* Read header information from EEPROM into global structure.
*/
.read_idle_ctrl = 0x00050000,
.zq_config = 0x50074BE4,
.temp_alert_config = 0x0,
- .emif_ddr_phy_ctlr_1 = 0x0E084008,
+ .emif_ddr_phy_ctlr_1 = 0x0E004008,
.emif_ddr_ext_phy_ctrl_1 = 0x08020080,
.emif_ddr_ext_phy_ctrl_2 = 0x00400040,
.emif_ddr_ext_phy_ctrl_3 = 0x00400040,
u32 temp;
/* enable module */
- writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO0_BASE + OMAP_GPIO_CTRL);
-
- /* enable output for GPIO0_22 */
- writel(GPIO_SETDATAOUT(GPIO_22),
- AM33XX_GPIO0_BASE + OMAP_GPIO_SETDATAOUT);
- temp = readl(AM33XX_GPIO0_BASE + OMAP_GPIO_OE);
- temp = temp & ~(GPIO_OE_ENABLE(GPIO_22));
- writel(temp, AM33XX_GPIO0_BASE + OMAP_GPIO_OE);
+ writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
+
+ /* enable output for GPIO5_7 */
+ writel(GPIO_SETDATAOUT(7),
+ AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
+ temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
+ temp = temp & ~(GPIO_OE_ENABLE(7));
+ writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
}
void sdram_init(void)
return 0;
}
#endif
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+
+static void cpsw_control(int enabled)
+{
+ /* Additional controls can be added here */
+ return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_addr = 16,
+ },
+ {
+ .slave_reg_ofs = 0x308,
+ .sliver_reg_ofs = 0xdc0,
+ .phy_addr = 1,
+ },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 1,
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .bd_ram_ofs = 0x2000,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+
+int board_eth_init(bd_t *bis)
+{
+ int rv;
+ uint8_t mac_addr[6];
+ uint32_t mac_hi, mac_lo;
+
+ /* try reading mac address from efuse */
+ mac_lo = readl(&cdev->macid0l);
+ mac_hi = readl(&cdev->macid0h);
+ mac_addr[0] = mac_hi & 0xFF;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+ mac_addr[4] = mac_lo & 0xFF;
+ mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+ if (!getenv("ethaddr")) {
+ puts("<ethaddr> not set. Validating first E-fuse MAC\n");
+ if (is_valid_ether_addr(mac_addr))
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ }
+
+ mac_lo = readl(&cdev->macid1l);
+ mac_hi = readl(&cdev->macid1h);
+ mac_addr[0] = mac_hi & 0xFF;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+ mac_addr[4] = mac_lo & 0xFF;
+ mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+ if (!getenv("eth1addr")) {
+ if (is_valid_ether_addr(mac_addr))
+ eth_setenv_enetaddr("eth1addr", mac_addr);
+ }
+
+ if (board_is_eposevm()) {
+ writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
+ cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
+ cpsw_slaves[0].phy_addr = 16;
+ } else {
+ writel(RGMII_MODE_ENABLE, &cdev->miisel);
+ cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
+ cpsw_slaves[0].phy_addr = 0;
+ }
+
+ rv = cpsw_register(&cpsw_data);
+ if (rv < 0)
+ printf("Error %d registering CPSW switch\n", rv);
+
+ return rv;
+}
+#endif
#include <asm/arch/mux.h>
#include "board.h"
+static struct module_pin_mux rmii1_pin_mux[] = {
+ {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
+ {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TD1 */
+ {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TD0 */
+ {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RD1 */
+ {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RD0 */
+ {OFFSET(mii1_rxdv), MODE(1) | RXACTIVE}, /* RMII1_RXDV */
+ {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS_DV */
+ {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
+ {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_refclk */
+ {-1},
+};
+
+static struct module_pin_mux rgmii1_pin_mux[] = {
+ {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
+ {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
+ {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
+ {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
+ {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
+ {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
+ {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
+ {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
+ {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
+ {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
+ {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
+ {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
+ {-1},
+};
+
+static struct module_pin_mux mdio_pin_mux[] = {
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {-1},
+};
+
static struct module_pin_mux uart0_pin_mux[] = {
{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
{OFFSET(uart0_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)},
{-1},
};
-static struct module_pin_mux gpio0_22_pin_mux[] = {
- {OFFSET(ddr_ba2), (MODE(9) | PULLUP_EN)}, /* GPIO0_22 */
+static struct module_pin_mux gpio5_7_pin_mux[] = {
+ {OFFSET(spi0_cs0), (MODE(7) | PULLUP_EN)}, /* GPIO5_7 */
+ {-1},
+};
+
+static struct module_pin_mux qspi_pin_mux[] = {
+ {OFFSET(gpmc_csn0), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_CS0 */
+ {OFFSET(gpmc_csn3), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* QSPI_CLK */
+ {OFFSET(gpmc_advn_ale), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D0 */
+ {OFFSET(gpmc_oen_ren), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D1 */
+ {OFFSET(gpmc_wen), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D2 */
+ {OFFSET(gpmc_be0n_cle), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D3 */
{-1},
};
{
configure_module_pin_mux(mmc0_pin_mux);
configure_module_pin_mux(i2c0_pin_mux);
+ configure_module_pin_mux(mdio_pin_mux);
- if (board_is_gpevm())
- configure_module_pin_mux(gpio0_22_pin_mux);
+ if (board_is_gpevm()) {
+ configure_module_pin_mux(gpio5_7_pin_mux);
+ configure_module_pin_mux(rgmii1_pin_mux);
+ } else if (board_is_eposevm()) {
+ configure_module_pin_mux(rmii1_pin_mux);
+ configure_module_pin_mux(qspi_pin_mux);
+ }
}
void enable_i2c0_pin_mux(void)
--- /dev/null
+Summary
+=======
+
+This document covers various features of the 'dra7xx_evm' build and some
+related uses.
+
+eMMC boot partition use
+=======================
+
+It is possible, depending on SYSBOOT configuration to boot from the eMMC
+boot partitions using (name depending on documentation referenced)
+Alternative Boot operation mode or Boot Sequence Option 1/2. In this
+example we load MLO and u-boot.img from the build into DDR and then use
+'mmc bootbus' to set the required rate (see TRM) and 'mmc partconfig' to
+set boot0 as the boot device.
+U-Boot # setenv autoload no
+U-Boot # usb start
+U-Boot # dhcp
+U-Boot # mmc dev 1 1
+U-Boot # tftp ${loadaddr} dra7xx/MLO
+U-Boot # mmc write ${loadaddr} 0 100
+U-Boot # tftp ${loadaddr} dra7xx/u-boot.img
+U-Boot # mmc write ${loadaddr} 300 400
+U-Boot # mmc bootbus 1 2 0 2
+U-Boot # mmc partconf 1 1 1 0
*/
#include <common.h>
#include <palmas.h>
+#include <sata.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sata.h>
int board_late_init(void)
{
- omap_sata_init();
+ init_sata(0);
return 0;
}
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
- .phy_id = 0,
+ .phy_addr = 2,
},
{
.slave_reg_ofs = 0x308,
.sliver_reg_ofs = 0xdc0,
- .phy_id = 1,
+ .phy_addr = 3,
},
};
if (is_valid_ether_addr(mac_addr))
eth_setenv_enetaddr("ethaddr", mac_addr);
}
+
+ mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
+ mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
+ mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = mac_hi & 0xFF;
+ mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
+ mac_addr[4] = (mac_lo & 0xFF00) >> 8;
+ mac_addr[5] = mac_lo & 0xFF;
+
+ if (!getenv("eth1addr")) {
+ if (is_valid_ether_addr(mac_addr))
+ eth_setenv_enetaddr("eth1addr", mac_addr);
+ }
+
ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
ctrl_val |= 0x22;
writel(ctrl_val, (*ctrl)->control_core_control_io1);
#include <./configs/omap1510.h>
#endif
-
-_TEXT_BASE:
- .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
-
.globl lowlevel_init
lowlevel_init:
--- /dev/null
+Summary
+=======
+
+This document covers various features of the 'omap5_uevm' build and some
+related uses.
+
+eMMC boot partition use
+=======================
+
+It is possible, depending on SYSBOOT configuration to boot from the eMMC
+boot partitions using (name depending on documentation referenced)
+Alternative Boot operation mode or Boot Sequence Option 1/2. In this
+example we load MLO and u-boot.img from the build into DDR and then use
+'mmc bootbus' to set the required rate (see TRM) and 'mmc partconfig' to
+set boot0 as the boot device.
+U-Boot # setenv autoload no
+U-Boot # usb start
+U-Boot # dhcp
+U-Boot # mmc dev 1 1
+U-Boot # tftp ${loadaddr} omap5uevm/MLO
+U-Boot # mmc write ${loadaddr} 0 100
+U-Boot # tftp ${loadaddr} omap5uevm/u-boot.img
+U-Boot # mmc write ${loadaddr} 300 400
+U-Boot # mmc bootbus 1 2 0 2
+U-Boot # mmc partconf 1 1 1 0
#include "mux_data.h"
#if defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_XHCI_OMAP)
+#include <sata.h>
#include <usb.h>
#include <asm/gpio.h>
#include <asm/arch/clock.h>
int board_late_init(void)
{
- omap_sata_init();
+ init_sata(0);
return 0;
}
{
.slave_reg_ofs = 0x50,
.sliver_reg_ofs = 0x700,
- .phy_id = 1,
+ .phy_addr = 1,
},
{
.slave_reg_ofs = 0x90,
.sliver_reg_ofs = 0x740,
- .phy_id = 0,
+ .phy_addr = 0,
},
};
. = ALIGN(0x800);
- _end = .;
+ .end :
+ {
+ *(.__end)
+ }
+
+ _image_binary_end = .;
.bss __rel_dyn_start (OVERLAY) : {
__bss_start = .;
__bss_end = .;
}
- .dynsym _end : { *(.dynsym) }
+ .dynsym _image_binary_end : { *(.dynsym) }
.dynbss : { *(.dynbss) }
.dynstr : { *(.dynstr*) }
.dynamic : { *(.dynamic*) }
#
obj-y := board.o
+obj-$(CONFIG_SPL_BUILD) += ps7_init.o
DECLARE_GLOBAL_DATA_PTR;
-/* Bootmode setting values */
-#define ZYNQ_BM_MASK 0x0F
-#define ZYNQ_BM_NOR 0x02
-#define ZYNQ_BM_SD 0x05
-#define ZYNQ_BM_JTAG 0x0
-
#ifdef CONFIG_FPGA
Xilinx_desc fpga;
/* It can be done differently */
Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
+Xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
case XILINX_ZYNQ_7010:
fpga = fpga010;
break;
+ case XILINX_ZYNQ_7015:
+ fpga = fpga015;
+ break;
case XILINX_ZYNQ_7020:
fpga = fpga020;
break;
}
#endif
- icache_enable();
-
#ifdef CONFIG_FPGA
fpga_init();
fpga_add(fpga_xilinx, &fpga);
return 0;
}
-#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
u32 ret = 0;
#endif
return ret;
}
-#endif
#ifdef CONFIG_CMD_MMC
int board_mmc_init(bd_t *bd)
--- /dev/null
+/*
+ * (C) Copyright 2014 Xilinx, Inc. Michal Simek
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/arch/spl.h>
+
+__weak void ps7_init(void)
+{
+ puts("Please copy ps7_init.c/h from hw project\n");
+}
###########################################################################################################
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+Active arm arm926ejs mxs freescale mx23evk mx23evk - Otavio Salvador <otavio@ossystems.com.br>
Active arm arm926ejs mxs freescale mx28evk mx28evk mx28evk:ENV_IS_IN_MMC Fabio Estevam <fabio.estevam@freescale.com>
Active arm arm926ejs mxs freescale mx28evk mx28evk_auart_console mx28evk:MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_MMC Fabio Estevam <fabio.estevam@freescale.com>
Active arm arm926ejs mxs freescale mx28evk mx28evk_nand mx28evk:ENV_IS_IN_NAND Fabio Estevam <fabio.estevam@freescale.com>
-Active arm arm926ejs mxs olimex mx23_olinuxino mx23_olinuxino mx23_olinuxino Marek Vasut <marek.vasut@gmail.com>
-Active arm arm926ejs mxs ppcag bg0900 bg0900 bg0900 Marek Vasut <marex@denx.de>
+Active arm arm926ejs mxs olimex mx23_olinuxino mx23_olinuxino - Marek Vasut <marek.vasut@gmail.com>
+Active arm arm926ejs mxs ppcag bg0900 bg0900 - Marek Vasut <marex@denx.de>
Active arm arm926ejs mxs sandisk sansa_fuze_plus sansa_fuze_plus - Marek Vasut <marek.vasut@gmail.com>
Active arm arm926ejs mxs schulercontrol sc_sps_1 sc_sps_1 - Marek Vasut <marek.vasut@gmail.com>
Active arm arm926ejs nomadik st nhk8815 nhk8815 - Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>:Alessandro Rubini <rubini@unipv.it>
Active arm arm926ejs omap ti - omap5912osk - Rishi Bhattacharya <rishi@ti.com>
Active arm arm926ejs orion5x LaCie - edminiv2 - Albert ARIBAUD <albert.u.boot@aribaud.net>
Active arm arm926ejs pantheon Marvell - dkb - Lei Wen <leiwen@marvell.com>
-Active arm arm926ejs spear spear - x600 x600 Stefan Roese <sr@denx.de>
+Active arm arm926ejs spear spear - x600 - Stefan Roese <sr@denx.de>
Active arm arm926ejs spear spear spear300 spear300 spear3xx_evb:spear300 Vipin Kumar <vipin.kumar@st.com>
Active arm arm926ejs spear spear spear300 spear300_nand spear3xx_evb:spear300,nand -
Active arm arm926ejs spear spear spear300 spear300_usbtty spear3xx_evb:spear300,usbtty -
Active arm armv7 - armltd vexpress vexpress_ca15_tc2 - -
Active arm armv7 - armltd vexpress vexpress_ca5x2 - Matt Waddel <matt.waddel@linaro.org>
Active arm armv7 - armltd vexpress vexpress_ca9x4 - Matt Waddel <matt.waddel@linaro.org>
-Active arm armv7 am33xx compulab cm_t335 cm_t335 cm_t335 Igor Grinberg <grinberg@compulab.co.il>
+Active arm armv7 am33xx compulab cm_t335 cm_t335 - Igor Grinberg <grinberg@compulab.co.il>
Active arm armv7 am33xx isee igep0033 am335x_igep0033 - Enric Balletbo i Serra <eballetbo@iseebcn.com>
Active arm armv7 am33xx phytec pcm051 pcm051_rev1 pcm051:REV1 Lars Poeschel <poeschel@lemonage.de>
Active arm armv7 am33xx phytec pcm051 pcm051_rev3 pcm051:REV3 Lars Poeschel <poeschel@lemonage.de>
Active arm armv7 am33xx siemens dxr2 dxr2 - Roger Meier <r.meier@siemens.com>
Active arm armv7 am33xx siemens pxm2 pxm2 - Roger Meier <r.meier@siemens.com>
Active arm armv7 am33xx siemens rut rut - Roger Meier <r.meier@siemens.com>
+Active arm armv7 am33xx silica pengwyn pengwyn - Lothar Felten <lothar.felten@gmail.com>
+Active arm armv7 am33xx BuR tseries tseries_nand tseries:SERIAL1,CONS_INDEX=1,NAND Hannes Petermaier <hannes.petermaier@br-automation.com>
+Active arm armv7 am33xx BuR tseries tseries_mmc tseries:SERIAL1,CONS_INDEX=1,EMMC_BOOT Hannes Petermaier <hannes.petermaier@br-automation.com>
+Active arm armv7 am33xx BuR tseries tseries_spi tseries:SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT Hannes Petermaier <hannes.petermaier@br-automation.com>
+Active arm armv7 am33xx BuR kwb kwb kwb:SERIAL1,CONS_INDEX=1 Hannes Petermaier <hannes.petermaier@br-automation.com>
Active arm armv7 am33xx ti am335x am335x_boneblack am335x_evm:SERIAL1,CONS_INDEX=1,EMMC_BOOT Tom Rini <trini@ti.com>
Active arm armv7 am33xx ti am335x am335x_evm am335x_evm:SERIAL1,CONS_INDEX=1,NAND Tom Rini <trini@ti.com>
Active arm armv7 am33xx ti am335x am335x_evm_nor am335x_evm:SERIAL1,CONS_INDEX=1,NAND,NOR Tom Rini <trini@ti.com>
Active arm armv7 at91 atmel sama5d3xek sama5d3xek_mmc sama5d3xek:SAMA5D3,SYS_USE_MMC Bo Shen <voice.shen@atmel.com>
Active arm armv7 at91 atmel sama5d3xek sama5d3xek_nandflash sama5d3xek:SAMA5D3,SYS_USE_NANDFLASH Bo Shen <voice.shen@atmel.com>
Active arm armv7 at91 atmel sama5d3xek sama5d3xek_spiflash sama5d3xek:SAMA5D3,SYS_USE_SERIALFLASH Bo Shen <voice.shen@atmel.com>
+Active arm armv7 bcm281xx broadcom bcm28155_ap bcm28155_ap bcm28155_ap Tim Kryger <tim.kryger@linaro.org>
Active arm armv7 exynos samsung arndale arndale - Inderpal Singh <inderpal.singh@linaro.org>
Active arm armv7 exynos samsung origen origen - Chander Kashyap <k.chander@samsung.com>
Active arm armv7 exynos samsung smdk5250 smdk5250 - Chander Kashyap <k.chander@samsung.com>
Active arm armv7 zynq xilinx zynq zynq_zc770_xm013 zynq_zc770:ZC770_XM013 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Active arm armv7 zynq xilinx zynq zynq_zed - Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Active arm armv7:arm720t tegra114 nvidia dalmore dalmore - Tom Warren <twarren@nvidia.com>
+Active arm armv7:arm720t tegra124 nvidia venice2 venice2 - Tom Warren <twarren@nvidia.com>
Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Alban Bedel <alban.bedel@avionic-design.de>
Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Alban Bedel <alban.bedel@avionic-design.de>
Active arm armv7:arm720t tegra20 avionic-design tec tec - Alban Bedel <alban.bedel@avionic-design.de>
Active arm armv7:arm720t tegra30 avionic-design tec-ng tec-ng - Alban Bedel <alban.bedel@avionic-design.de>
Active arm armv7:arm720t tegra30 nvidia beaver beaver - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
Active arm armv7:arm720t tegra30 nvidia cardhu cardhu - Tom Warren <twarren@nvidia.com>
-Active arm ixp - - - actux2 - Michael Schwingen <michael@schwingen.org>
-Active arm ixp - - - actux3 - Michael Schwingen <michael@schwingen.org>
-Active arm ixp - - - actux4 - Michael Schwingen <michael@schwingen.org>
-Active arm ixp - - - dvlhost - Michael Schwingen <michael@schwingen.org>
-Active arm ixp - - actux1 actux1_4_16 actux1:FLASH2X2 Michael Schwingen <michael@schwingen.org>
-Active arm ixp - - actux1 actux1_4_32 actux1:FLASH2X2,RAM_32MB Michael Schwingen <michael@schwingen.org>
-Active arm ixp - - actux1 actux1_8_16 actux1:FLASH1X8 Michael Schwingen <michael@schwingen.org>
-Active arm ixp - - actux1 actux1_8_32 actux1:FLASH1X8,RAM_32MB Michael Schwingen <michael@schwingen.org>
Active arm pxa - - - balloon3 - Marek Vasut <marek.vasut@gmail.com>
Active arm pxa - - - h2200 - Lukasz Dalek <luk0104@gmail.com>
Active arm pxa - - - palmld - Marek Vasut <marek.vasut@gmail.com>
Active powerpc mpc5xxx - - icecube lite5200b IceCube:MPC5200_DDR,LITE5200B -
Active powerpc mpc5xxx - - icecube lite5200b_LOWBOOT IceCube:MPC5200_DDR,LITE5200B,SYS_TEXT_BASE=0xFF000000 -
Active powerpc mpc5xxx - - icecube lite5200b_PM IceCube:MPC5200_DDR,LITE5200B,LITE5200B_PM -
-Active powerpc mpc5xxx - - mcc200 mcc200 mcc200 -
+Active powerpc mpc5xxx - - mcc200 mcc200 - -
Active powerpc mpc5xxx - - mcc200 mcc200_COM12 mcc200:CONSOLE_COM12 -
Active powerpc mpc5xxx - - mcc200 mcc200_COM12_highboot mcc200:CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000 -
Active powerpc mpc5xxx - - mcc200 mcc200_COM12_highboot_SDRAM mcc200:CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM -
Active powerpc mpc5xxx - manroland - uc101 - Heiko Schocher <hs@denx.de>
Active powerpc mpc5xxx - matrix_vision mvbc_p MVBC_P MVBC_P:MVBC_P Andre Schwarz <andre.schwarz@matrix-vision.de>
Active powerpc mpc5xxx - matrix_vision mvsmr MVSMR - Andre Schwarz <andre.schwarz@matrix-vision.de>
-Active powerpc mpc5xxx - phytec pcm030 pcm030 pcm030 Jon Smirl <jonsmirl@gmail.com>
+Active powerpc mpc5xxx - phytec pcm030 pcm030 - Jon Smirl <jonsmirl@gmail.com>
Active powerpc mpc5xxx - phytec pcm030 pcm030_LOWBOOT pcm030:SYS_TEXT_BASE=0xFF000000 Jon Smirl <jonsmirl@gmail.com>
Active powerpc mpc5xxx - tqc tqm5200 aev - -
Active powerpc mpc5xxx - tqc tqm5200 cam5200 TQM5200:CAM5200,TQM5200S,TQM5200_B -
Active powerpc mpc5xxx - tqc tqm5200 cam5200_niosflash TQM5200:CAM5200,TQM5200S,TQM5200_B,CAM5200_NIOSFLASH -
-Active powerpc mpc5xxx - tqc tqm5200 charon charon Heiko Schocher <hs@denx.de>
+Active powerpc mpc5xxx - tqc tqm5200 charon - Heiko Schocher <hs@denx.de>
Active powerpc mpc5xxx - tqc tqm5200 fo300 TQM5200:FO300 -
Active powerpc mpc5xxx - tqc tqm5200 MiniFAP TQM5200:MINIFAP -
Active powerpc mpc5xxx - tqc tqm5200 TB5200 - -
Active powerpc mpc5xxx - tqc tqm5200 TB5200_B TB5200:TQM5200_B -
-Active powerpc mpc5xxx - tqc tqm5200 TQM5200 TQM5200: -
+Active powerpc mpc5xxx - tqc tqm5200 TQM5200 - -
Active powerpc mpc5xxx - tqc tqm5200 TQM5200_B TQM5200:TQM5200_B -
Active powerpc mpc5xxx - tqc tqm5200 TQM5200_B_HIGHBOOT TQM5200:TQM5200_B,SYS_TEXT_BASE=0xFFF00000 -
Active powerpc mpc5xxx - tqc tqm5200 TQM5200_STK100 TQM5200:STK52XX_REV100 -
Active powerpc mpc5xxx - tqc tqm5200 TQM5200S_HIGHBOOT TQM5200:TQM5200_B,TQM5200S,SYS_TEXT_BASE=0xFFF00000 -
Active powerpc mpc824x - - - utx8245 - Greg Allen <gallen@arlut.utexas.edu>
Active powerpc mpc824x - - a3000 A3000 - -
-Active powerpc mpc824x - - cpc45 CPC45 CPC45 Josef Wagner <Wagner@Microsys.de>
+Active powerpc mpc824x - - cpc45 CPC45 - Josef Wagner <Wagner@Microsys.de>
Active powerpc mpc824x - - cpc45 CPC45_ROMBOOT CPC45:BOOT_ROM Josef Wagner <Wagner@Microsys.de>
Active powerpc mpc824x - - cu824 CU824 - Wolfgang Denk <wd@denx.de>
Active powerpc mpc824x - - eXalion eXalion - Torsten Demke <torsten.demke@fci.com>
Active powerpc mpc8260 - - - ppmc8260 - Brad Kemp <Brad.Kemp@seranoa.com>
Active powerpc mpc8260 - - - sacsng - Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
Active powerpc mpc8260 - - cogent cogent_mpc8260 - Murray Jensen <Murray.Jensen@csiro.au>
-Active powerpc mpc8260 - - cpu86 CPU86 CPU86 Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - - cpu86 CPU86 - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8260 - - cpu86 CPU86_ROMBOOT CPU86:BOOT_ROM Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8260 - - cpu87 CPU87 CPU87 -
+Active powerpc mpc8260 - - cpu87 CPU87 - -
Active powerpc mpc8260 - - cpu87 CPU87_ROMBOOT CPU87:BOOT_ROM -
Active powerpc mpc8260 - - ep8248 ep8248 - Yuli Barcohen <yuli@arabellasw.com>
-Active powerpc mpc8260 - - ep8248 ep8248E ep8248 Yuli Barcohen <yuli@arabellasw.com>
Active powerpc mpc8260 - - ids8247 IDS8247 - Heiko Schocher <hs@denx.de>
Active powerpc mpc8260 - - iphase4539 IPHASE4539 - Wolfgang Grandegger <wg@denx.de>
Active powerpc mpc8260 - - ispan ISPAN - Yuli Barcohen <yuli@arabellasw.com>
Active powerpc mpc8260 - - pm826 PM826_BIGFLASH PM826:FLASH_32MB,SYS_TEXT_BASE=0x40000000 Wolfgang Denk <wd@denx.de>
Active powerpc mpc8260 - - pm826 PM826_ROMBOOT PM826:BOOT_ROM,SYS_TEXT_BASE=0xFF800000 Wolfgang Denk <wd@denx.de>
Active powerpc mpc8260 - - pm826 PM826_ROMBOOT_BIGFLASH PM826:BOOT_ROM,FLASH_32MB,SYS_TEXT_BASE=0xFF800000 Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8260 - - pm828 PM828 PM828 -
+Active powerpc mpc8260 - - pm828 PM828 - -
Active powerpc mpc8260 - - pm828 PM828_PCI PM828:PCI -
Active powerpc mpc8260 - - pm828 PM828_ROMBOOT PM828:BOOT_ROM,SYS_TEXT_BASE=0xFF800000 -
Active powerpc mpc8260 - - pm828 PM828_ROMBOOT_PCI PM828:PCI,BOOT_ROM,SYS_TEXT_BASE=0xFF800000 -
-Active powerpc mpc8260 - - rattler Rattler Rattler Yuli Barcohen <yuli@arabellasw.com>
+Active powerpc mpc8260 - - rattler Rattler - Yuli Barcohen <yuli@arabellasw.com>
Active powerpc mpc8260 - - rattler Rattler8248 Rattler:MPC8248 Yuli Barcohen <yuli@arabellasw.com>
Active powerpc mpc8260 - - zpc1900 ZPC1900 - Yuli Barcohen <yuli@arabellasw.com>
Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS Yuli Barcohen <yuli@arabellasw.com>
Active powerpc mpc8260 - tqc tqm8260 TQM8265_AA TQM8260:MPC8265,300MHz,BUSMODE_60x Wolfgang Denk <wd@denx.de>
Active powerpc mpc8260 - tqc tqm8272 TQM8272 - -
Active powerpc mpc83xx - - - mpc8308_p1m - Ilya Yanok <yanok@emcraft.com>
-Active powerpc mpc83xx - - sbc8349 sbc8349
sbc8349 Paul Gortmaker <paul.gortmaker@windriver.com>
+Active powerpc mpc83xx - - sbc8349 sbc8349
- Paul Gortmaker <paul.gortmaker@windriver.com>
Active powerpc mpc83xx - - sbc8349 sbc8349_PCI_33 sbc8349:PCI,PCI_33M Paul Gortmaker <paul.gortmaker@windriver.com>
Active powerpc mpc83xx - - sbc8349 sbc8349_PCI_66 sbc8349:PCI,PCI_66M Paul Gortmaker <paul.gortmaker@windriver.com>
Active powerpc mpc83xx - - ve8313 ve8313 - Heiko Schocher <hs@denx.de>
Active powerpc mpc83xx - esd vme8349 caddy2 vme8349:CADDY2 Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-Active powerpc mpc83xx - esd vme8349 vme8349 vme8349 Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+Active powerpc mpc83xx - esd vme8349 vme8349 - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
Active powerpc mpc83xx - freescale mpc8308rdb MPC8308RDB - Ilya Yanok <yanok@emcraft.com>
Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_33 MPC8313ERDB:SYS_33MHZ -
Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_66 MPC8313ERDB:SYS_66MHZ -
Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_NAND_33 MPC8313ERDB:SYS_33MHZ,NAND -
Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_NAND_66 MPC8313ERDB:SYS_66MHZ,NAND -
-Active powerpc mpc83xx - freescale mpc8315erdb MPC8315ERDB MPC8315ERDB Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc8315erdb MPC8315ERDB - Dave Liu <daveliu@freescale.com>
Active powerpc mpc83xx - freescale mpc8315erdb MPC8315ERDB_NAND MPC8315ERDB:NAND_U_BOOT Dave Liu <daveliu@freescale.com>
Active powerpc mpc83xx - freescale mpc8323erdb MPC8323ERDB - Michael Barkowski <michael.barkowski@freescale.com>
-Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS MPC832XEMDS: Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS - Dave Liu <daveliu@freescale.com>
Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_ATM MPC832XEMDS:PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1 Dave Liu <daveliu@freescale.com>
Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_HOST_33 MPC832XEMDS:PCI,PCI_33M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com>
Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_HOST_66 MPC832XEMDS:PCI,PCI_66M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com>
Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_HOST_33 MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_33M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com>
Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_HOST_66 MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_66M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com>
Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_SLAVE MPC8360EMDS:CLKIN_66MHZ,PCI,PCISLAVE Dave Liu <daveliu@freescale.com>
-Active powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK
MPC8360ERDK Anton Vorontsov <avorontsov@ru.mvista.com>
+Active powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK
- Anton Vorontsov <avorontsov@ru.mvista.com>
Active powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK_33 MPC8360ERDK:CLKIN_33MHZ Anton Vorontsov <avorontsov@ru.mvista.com>
-Active powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK_66 MPC8360ERDK Anton Vorontsov <avorontsov@ru.mvista.com>
-Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS MPC837XEMDS Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS - Dave Liu <daveliu@freescale.com>
Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS_HOST MPC837XEMDS:PCI Dave Liu <daveliu@freescale.com>
Active powerpc mpc83xx - freescale mpc837xerdb MPC837XERDB - Joe D'Abbraccio <ljd015@freescale.com>
Active powerpc mpc83xx - keymile km83xx kmcoge5ne km8360:KMCOGE5NE Holger Brunck <holger.brunck@keymile.com>
Active powerpc mpc83xx - sheldon simpc8313 SIMPC8313_LP SIMPC8313:NAND_LP Ron Madrid <info@sheldoninst.com>
Active powerpc mpc83xx - sheldon simpc8313 SIMPC8313_SP SIMPC8313:NAND_SP Ron Madrid <info@sheldoninst.com>
Active powerpc mpc83xx - tqc tqm834x TQM834x - -
-Active powerpc mpc85xx - - sbc8548 sbc8548
sbc8548 Paul Gortmaker <paul.gortmaker@windriver.com>
+Active powerpc mpc85xx - - sbc8548 sbc8548
- Paul Gortmaker <paul.gortmaker@windriver.com>
Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_33 sbc8548:PCI,33 Paul Gortmaker <paul.gortmaker@windriver.com>
Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_33_PCIE sbc8548:PCI,33,PCIE Paul Gortmaker <paul.gortmaker@windriver.com>
Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_66 sbc8548:PCI,66 Paul Gortmaker <paul.gortmaker@windriver.com>
Active powerpc mpc85xx - freescale corenet_ds P5040DS_NAND P5040DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale corenet_ds P5040DS_SDCARD P5040DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale corenet_ds P5040DS_SPIFLASH P5040DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS MPC8536DS -
+Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS - -
Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_36BIT MPC8536DS:36BIT -
Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_NAND MPC8536DS:NAND -
Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_SDCARD MPC8536DS:SDCARD -
Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_SPIFLASH MPC8536DS:SPIFLASH -
Active powerpc mpc85xx - freescale mpc8540ads MPC8540ADS - Kumar Gala <kumar.gala@freescale.com>
-Active powerpc mpc85xx - freescale mpc8541cds MPC8541CDS MPC8541CDS Kumar Gala <kumar.gala@freescale.com>
+Active powerpc mpc85xx - freescale mpc8541cds MPC8541CDS - Kumar Gala <kumar.gala@freescale.com>
Active powerpc mpc85xx - freescale mpc8541cds MPC8541CDS_legacy MPC8541CDS:LEGACY Kumar Gala <kumar.gala@freescale.com>
Active powerpc mpc85xx - freescale mpc8544ds MPC8544DS - -
-Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS MPC8548CDS -
+Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS - -
Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS_36BIT MPC8548CDS:36BIT -
Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS_legacy MPC8548CDS:LEGACY -
-Active powerpc mpc85xx - freescale mpc8555cds MPC8555CDS MPC8555CDS Kumar Gala <kumar.gala@freescale.com>
+Active powerpc mpc85xx - freescale mpc8555cds MPC8555CDS - Kumar Gala <kumar.gala@freescale.com>
Active powerpc mpc85xx - freescale mpc8555cds MPC8555CDS_legacy MPC8555CDS:LEGACY Kumar Gala <kumar.gala@freescale.com>
Active powerpc mpc85xx - freescale mpc8560ads MPC8560ADS - Kumar Gala <kumar.gala@freescale.com>
Active powerpc mpc85xx - freescale mpc8568mds MPC8568MDS - -
-Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS MPC8569MDS -
+Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS - -
Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS_ATM MPC8569MDS:ATM -
Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS_NAND MPC8569MDS:NAND -
-Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS MPC8572DS -
+Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS - -
Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS_36BIT MPC8572DS:36BIT -
Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS_NAND MPC8572DS:NAND -
Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NAND P1010RDB:P1010RDB_PA,36BIT,NAND -
Active powerpc mpc85xx - freescale p1022ds P1022DS_NAND P1022DS:NAND Timur Tabi <timur@freescale.com>
Active powerpc mpc85xx - freescale p1022ds P1022DS_SDCARD P1022DS:SDCARD Timur Tabi <timur@freescale.com>
Active powerpc mpc85xx - freescale p1022ds P1022DS_SPIFLASH P1022DS:SPIFLASH Timur Tabi <timur@freescale.com>
-Active powerpc mpc85xx - freescale p1023rdb P1023RDB P1023RDB -
-Active powerpc mpc85xx - freescale p1023rds P1023RDS P1023RDS Roy Zang <tie-fei.zang@freescale.com>
+Active powerpc mpc85xx - freescale p1023rdb P1023RDB - -
+Active powerpc mpc85xx - freescale p1023rds P1023RDS - Roy Zang <tie-fei.zang@freescale.com>
Active powerpc mpc85xx - freescale p1023rds P1023RDS_NAND P1023RDS:NAND Roy Zang <tie-fei.zang@freescale.com>
Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB P1_P2_RDB:P1011RDB -
Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_36BIT P1_P2_RDB:P1011RDB,36BIT -
Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Poonam Aggrwal <poonam.aggrwal@freescale.com>
Active powerpc mpc85xx - freescale t104xrdb T1040RDB T1040RDB:PPC_T1040 Poonam Aggrwal <poonam.aggrwal@freescale.com>
Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T1042RDB_PI:PPC_T1042 Poonam Aggrwal <poonam.aggrwal@freescale.com>
-Active powerpc mpc85xx - freescale t2080qds T2080QDS T2080QDS:PPC_T2080 -
-Active powerpc mpc85xx - freescale t2080qds T2080QDS_NAND T2080QDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale t2080qds T2080QDS_SDCARD T2080QDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale t2080qds T2080QDS_SPIFLASH T2080QDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale t2080qds T2080QDS_SRIO_PCIE_BOOT T2080QDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale t208xqds T2080QDS T208xQDS:PPC_T2080
+Active powerpc mpc85xx - freescale t208xqds T2080QDS_SDCARD T208xQDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000
+Active powerpc mpc85xx - freescale t208xqds T2080QDS_SPIFLASH T208xQDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000
+Active powerpc mpc85xx - freescale t208xqds T2080QDS_NAND T208xQDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000
+Active powerpc mpc85xx - freescale t208xqds T2080QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000
+Active powerpc mpc85xx - freescale t208xqds T2081QDS T208xQDS:PPC_T2081
+Active powerpc mpc85xx - freescale t208xqds T2081QDS_SDCARD T208xQDS:PPC_T2081,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000
+Active powerpc mpc85xx - freescale t208xqds T2081QDS_SPIFLASH T208xQDS:PPC_T2081,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000
+Active powerpc mpc85xx - freescale t208xqds T2081QDS_NAND T208xQDS:PPC_T2081,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000
+Active powerpc mpc85xx - freescale t208xqds T2081QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000
Active powerpc mpc85xx - freescale t4qds T4160QDS T4240QDS:PPC_T4160 -
Active powerpc mpc85xx - freescale t4qds T4160QDS_SDCARD T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale t4qds T4160QDS_SPIFLASH T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach <eibach@gdsys.de>
Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER controlcenterd:TRAILBLAZER,SPIFLASH Dirk Eibach <eibach@gdsys.de>
Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER_DEVELOP controlcenterd:TRAILBLAZER,SPIFLASH,DEVELOP Dirk Eibach <eibach@gdsys.de>
+Active powerpc mpc85xx - keymile kmp204x kmcoge4 kmp204x:KMCOGE4 Valentin Longchamp <valentin.longchamp@keymile.com>
Active powerpc mpc85xx - keymile kmp204x kmlion1 kmp204x:KMLION1 Valentin Longchamp <valentin.longchamp@keymile.com>
Active powerpc mpc85xx - stx stxgp3 stxgp3 - Dan Malek <dan@embeddedalley.com>
-Active powerpc mpc85xx - stx stxssa stxssa stxssa Dan Malek <dan@embeddedalley.com>
+Active powerpc mpc85xx - stx stxssa stxssa - Dan Malek <dan@embeddedalley.com>
Active powerpc mpc85xx - stx stxssa stxssa_4M stxssa:STXSSA_4M Dan Malek <dan@embeddedalley.com>
Active powerpc mpc85xx - xes - xpedite520x - -
Active powerpc mpc85xx - xes - xpedite537x - -
Active powerpc mpc85xx - xes - xpedite550x - -
Active powerpc mpc86xx - - - sbc8641d - Paul Gortmaker <paul.gortmaker@windriver.com>
Active powerpc mpc86xx - freescale mpc8610hpcd MPC8610HPCD - -
-Active powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN MPC8641HPCN Kumar Gala <kumar.gala@freescale.com>
+Active powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN - Kumar Gala <kumar.gala@freescale.com>
Active powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN_36BIT MPC8641HPCN:PHYS_64BIT Kumar Gala <kumar.gala@freescale.com>
Active powerpc mpc86xx - xes - xpedite517x - -
Active powerpc mpc8xx - - - hermes - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - - - svm_sc8xx - John Zhan <zhanz@sinovee.com>
Active powerpc mpc8xx - - - v37 - -
Active powerpc mpc8xx - - adder Adder - Yuli Barcohen <yuli@arabellasw.com>
-Active powerpc mpc8xx - - adder Adder87x Adder Yuli Barcohen <yuli@arabellasw.com>
Active powerpc mpc8xx - - adder AdderII Adder:MPC852T Yuli Barcohen <yuli@arabellasw.com>
-Active powerpc mpc8xx - - adder AdderUSB Adder Yuli Barcohen <yuli@arabellasw.com>
Active powerpc mpc8xx - - cogent cogent_mpc8xx - Murray Jensen <Murray.Jensen@csiro.au>
Active powerpc mpc8xx - - esteem192e ESTEEM192E - Conn Clark <clark@esteem.com>
Active powerpc mpc8xx - - fads MPC86xADS - -
Active powerpc mpc8xx - - ivm IVMS8_256 IVMS8:IVMS8_64M Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - - netphone NETPHONE NETPHONE:NETPHONE_VERSION=1 -
Active powerpc mpc8xx - - netphone NETPHONE_V2 NETPHONE:NETPHONE_VERSION=2 -
-Active powerpc mpc8xx - - netta NETTA NETTA -
+Active powerpc mpc8xx - - netta NETTA - -
Active powerpc mpc8xx - - netta NETTA_6412 NETTA:NETTA_6412=1 -
Active powerpc mpc8xx - - netta NETTA_6412_SWAPHOOK NETTA:NETTA_6412=1,NETTA_SWAPHOOK=1 -
Active powerpc mpc8xx - - netta NETTA_ISDN NETTA:NETTA_ISDN=1 -
Active powerpc mpc8xx - - netvia NETVIA_V2 NETVIA:NETVIA_VERSION=2 Pantelis Antoniou <panto@intracom.gr>
Active powerpc mpc8xx - - r360mpi R360MPI - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - - rbc823 RBC823 - -
-Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW RPXlite_DW -
+Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW - -
Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_64 RPXlite_DW:RPXlite_64MHz -
Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_64_LCD RPXlite_DW:RPXlite_64MHz,LCD,NEC_NL6448BC20 -
Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_LCD RPXlite_DW:LCD,NEC_NL6448BC20 -
Orphan arm arm1136 mx31 - imx31_phycore imx31_phycore_eet imx31_phycore:IMX31_PHYCORE_EET (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Orphan arm arm1136 mx31 freescale - mx31ads - (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Orphan arm pxa - - - lubbock - (dead address) Kyle Harris <kharris@nexus-tech.net>
-Orphan powerpc 74xx_7xx - - evb64260 EVB64260 EVB64260 -
-Orphan powerpc 74xx_7xx - - evb64260 EVB64260_750CX EVB64260 Eran Man <eran@nbase.co.il>
+Orphan powerpc 74xx_7xx - - evb64260 EVB64260 - -
Orphan powerpc mpc824x - - mousse MOUSSE - -
Orphan powerpc mpc8260 - - - rsdproto - -
Orphan powerpc mpc8260 - - rpxsuper RPXsuper - -
obj-$(CONFIG_CMD_BOOTSTAGE) += cmd_bootstage.o
obj-$(CONFIG_CMD_CACHE) += cmd_cache.o
obj-$(CONFIG_CMD_CBFS) += cmd_cbfs.o
+obj-$(CONFIG_CMD_CLK) += cmd_clk.o
obj-$(CONFIG_CMD_CONSOLE) += cmd_console.o
obj-$(CONFIG_CMD_CPLBINFO) += cmd_cplbinfo.o
obj-$(CONFIG_DATAFLASH_MMC_SELECT) += cmd_dataflash_mmc_mux.o
obj-$(CONFIG_CMD_EXT4) += cmd_ext4.o
obj-$(CONFIG_CMD_EXT2) += cmd_ext2.o
obj-$(CONFIG_CMD_FAT) += cmd_fat.o
-obj-$(CONFIG_CMD_FDC)$(CONFIG_CMD_FDOS) += cmd_fdc.o
+obj-$(CONFIG_CMD_FDC) += cmd_fdc.o
obj-$(CONFIG_OF_LIBFDT) += cmd_fdt.o fdt_support.o
-obj-$(CONFIG_CMD_FDOS) += cmd_fdos.o
obj-$(CONFIG_CMD_FITUPD) += cmd_fitupd.o
obj-$(CONFIG_CMD_FLASH) += cmd_flash.o
ifdef CONFIG_FPGA
obj-$(CONFIG_SPL_USB_SUPPORT) += usb.o usb_hub.o
obj-$(CONFIG_USB_STORAGE) += usb_storage.o
endif
+ifdef CONFIG_SPL_SATA_SUPPORT
+obj-$(CONFIG_CMD_SCSI) += cmd_scsi.o
+endif
ifneq ($(CONFIG_SPL_NET_SUPPORT),y)
obj-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o
obj-$(CONFIG_ENV_IS_IN_MMC) += env_mmc.o
obj-y += memsize.o
obj-y += stdio.o
-$(obj)env_embedded.o: $(src)env_embedded.c
- $(CC) $(AFLAGS) -Wa,--no-warn \
- -DENV_CRC=$(shell $(obj)../tools/envcrc) \
- -c -o $@ $(src)env_embedded.c
-
-# SEE README.arm-unaligned-accesses
-$(obj)hush.o: CFLAGS += $(PLATFORM_NO_UNALIGNED)
-$(obj)fdt_support.o: CFLAGS += $(PLATFORM_NO_UNALIGNED)
+CFLAGS_env_embedded.o := -Wa,--no-warn -DENV_CRC=$(shell tools/envcrc 2>/dev/null)
#ifndef CONFIG_SANDBOX
ulong bss_start, bss_end;
-#ifdef CONFIG_SYS_SYM_OFFSETS
- bss_start = _bss_start_ofs + _TEXT_BASE;
- bss_end = _bss_end_ofs + _TEXT_BASE;
-#else
bss_start = (ulong)&__bss_start;
bss_end = (ulong)&__bss_end;
-#endif
+
debug("U-Boot code: %08X -> %08lX BSS: -> %08lX\n",
CONFIG_SYS_TEXT_BASE, bss_start, bss_end);
#endif
return 0;
}
-ulong get_effective_memsize(void)
-{
-#ifndef CONFIG_VERY_BIG_RAM
- return gd->ram_size;
-#else
- /* limit stack to what we can reasonable map */
- return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
- CONFIG_MAX_MEM_MAPPED : gd->ram_size);
-#endif
-}
-
void __dram_init_banksize(void)
{
#if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
static int setup_mon_len(void)
{
-#ifdef CONFIG_SYS_SYM_OFFSETS
- gd->mon_len = _bss_end_ofs;
+#ifdef __ARM__
+ gd->mon_len = (ulong)&__bss_end - (ulong)_start;
#elif defined(CONFIG_SANDBOX)
gd->mon_len = (ulong)&_end - (ulong)_init;
#else
{
#ifdef CONFIG_OF_EMBED
/* Get a pointer to the FDT */
- gd->fdt_blob = _binary_dt_dtb_start;
+ gd->fdt_blob = __dtb_dt_begin;
#elif defined CONFIG_OF_SEPARATE
/* FDT is at end of image */
-# ifdef CONFIG_SYS_SYM_OFFSETS
- gd->fdt_blob = (void *)(_end_ofs + CONFIG_SYS_TEXT_BASE);
-# else
gd->fdt_blob = (ulong *)&_end;
-# endif
#elif defined(CONFIG_OF_HOSTFILE)
if (read_fdt_from_file()) {
puts("Failed to read control FDT\n");
#ifdef CONFIG_PPC
checkcpu,
#endif
-#if defined(CONFIG_DISPLAY_CPUINFO)
print_cpuinfo, /* display cpu info (and speed) */
-#endif
#if defined(CONFIG_MPC5xxx)
prt_mpc5xxx_clks,
#endif /* CONFIG_MPC5xxx */
static int initr_reloc_global_data(void)
{
-#ifdef CONFIG_SYS_SYM_OFFSETS
- monitor_flash_len = _end_ofs;
+#ifdef __ARM__
+ monitor_flash_len = _end - __image_copy_start;
#elif !defined(CONFIG_SANDBOX)
monitor_flash_len = (ulong)&__init_end - gd->relocaddr;
#endif
return 0;
}
+#elif defined(CONFIG_ARC700)
+
+int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ bd_t *bd = gd->bd;
+
+ print_num("mem start", bd->bi_memstart);
+ print_lnum("mem size", bd->bi_memsize);
+
+#if defined(CONFIG_CMD_NET)
+ print_eth(0);
+ printf("ip_addr = %s\n", getenv("ipaddr"));
+#endif
+ printf("baudrate = %d bps\n", bd->bi_baudrate);
+
+ return 0;
+}
+
#else
#error "a case for this architecture does not exist!"
#endif
setenv_hex("filesize", images->os.image_len);
return 0;
}
- appl = (int (*)(int, char * const []))(ulong)ntohl(images->ep);
- (*appl)(argc, argv);
+ appl = (int (*)(int, char * const []))images->ep;
+ appl(argc, argv);
return 0;
}
--- /dev/null
+/*
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <command.h>
+#include <clk.h>
+
+int __weak soc_clk_dump(void)
+{
+ puts("Not implemented\n");
+ return 1;
+}
+
+static int do_clk_dump(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ return soc_clk_dump();
+}
+
+static cmd_tbl_t cmd_clk_sub[] = {
+ U_BOOT_CMD_MKENT(dump, 1, 1, do_clk_dump, "", ""),
+};
+
+static int do_clk(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ cmd_tbl_t *c;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ /* Strip off leading 'clk' command argument */
+ argc--;
+ argv++;
+
+ c = find_cmd_tbl(argv[0], &cmd_clk_sub[0], ARRAY_SIZE(cmd_clk_sub));
+
+ if (c)
+ return c->cmd(cmdtp, flag, argc, argv);
+ else
+ return CMD_RET_USAGE;
+}
+
+#ifdef CONFIG_SYS_LONGHELP
+static char clk_help_text[] =
+ "dump - Print clock frequencies";
+#endif
+
+U_BOOT_CMD(clk, 2, 1, do_clk, "CLK sub-system", clk_help_text);
/* get the address in hexadecimal format (string to int) */
ram_address = simple_strtoul(argv[3], NULL, 16);
- /* get the filesize in base 10 format */
- file_size = simple_strtoul(argv[5], NULL, 10);
+ /* get the filesize in hexadecimal format */
+ file_size = simple_strtoul(argv[5], NULL, 16);
/* set the device as block device */
ext4fs_set_blk_dev(dev_desc, &info);
return true;
}
-#if defined(CONFIG_CMD_FDOS)
-
-/* Low level functions for the Floppy-DOS layer */
-
-/**************************************************************************
-* int fdc_fdos_init
-* initialize the FDC layer
-*
-*/
-int fdc_fdos_init (int drive)
-{
- FD_GEO_STRUCT *pFG = (FD_GEO_STRUCT *)floppy_type;
- FDC_COMMAND_STRUCT *pCMD = &cmd;
-
- /* setup FDC and scan for drives */
- if (fdc_setup(drive, pCMD, pFG) == false) {
- printf("\n** Error in setup FDC **\n");
- return false;
- }
- if (fdc_check_drive(pCMD, pFG) == false) {
- printf("\n** Error in check_drives **\n");
- return false;
- }
- if((pCMD->flags&(1<<drive))==0) {
- /* drive not available */
- printf("\n** Drive %d not available **\n",drive);
- return false;
- }
- if((pCMD->flags&(0x10<<drive))==0) {
- /* no disk inserted */
- printf("\n** No disk inserted in drive %d **\n",drive);
- return false;
- }
- /* ok, we have a valid source */
- pCMD->drive=drive;
-
- /* read first block */
- pCMD->blnr=0;
- return true;
-}
-/**************************************************************************
-* int fdc_fdos_seek
-* parameter is a block number
-*/
-int fdc_fdos_seek (int where)
-{
- FD_GEO_STRUCT *pFG = (FD_GEO_STRUCT *)floppy_type;
- FDC_COMMAND_STRUCT *pCMD = &cmd;
-
- pCMD -> blnr = where ;
- return (fdc_seek (pCMD, pFG));
-}
-/**************************************************************************
-* int fdc_fdos_read
-* the length is in block number
-*/
-int fdc_fdos_read (void *buffer, int len)
-{
- FD_GEO_STRUCT *pFG = (FD_GEO_STRUCT *)floppy_type;
- FDC_COMMAND_STRUCT *pCMD = &cmd;
-
- return (fdc_read_data (buffer, len, pCMD, pFG));
-}
-#endif
-
-#if defined(CONFIG_CMD_FDC)
/****************************************************************************
* main routine do_fdcboot
*/
"boot from floppy device",
"loadAddr drive"
);
-#endif
/* if the parameter starts with a * then assume a string pointer else its a literal */
if (s[0] == '*') {
return (char *)simple_strtoul(&s[1], NULL, 16);
+ } else if (s[0] == '$') {
+ int i = 2;
+
+ if (s[1] != '{')
+ return NULL;
+
+ while (s[i] != '}') {
+ if (s[i] == 0)
+ return NULL;
+ i++;
+ }
+ s[i] = 0;
+ return getenv((const char *)&s[2]);
} else {
return s;
}
unsigned long __logbuffer_base(void)
{
- return CONFIG_SYS_SDRAM_BASE + gd->ram_size - LOGBUFF_LEN;
+ return CONFIG_SYS_SDRAM_BASE + get_effective_memsize() - LOGBUFF_LEN;
}
unsigned long logbuffer_base(void)
__attribute__((weak, alias("__logbuffer_base")));
buf = map_sysmem(addr, bytes);
while (count-- > 0) {
if (size == 4)
- *((ulong *)buf) = (ulong)writeval;
+ *((u32 *)buf) = (u32)writeval;
else if (size == 2)
- *((ushort *)buf) = (ushort)writeval;
+ *((u16 *)buf) = (u16)writeval;
else
- *((u_char *)buf) = (u_char)writeval;
+ *((u8 *)buf) = (u8)writeval;
buf += size;
}
unmap_sysmem(buf);
for (ngood = 0; ngood < count; ++ngood) {
ulong word1, word2;
if (size == 4) {
- word1 = *(ulong *)buf1;
- word2 = *(ulong *)buf2;
+ word1 = *(u32 *)buf1;
+ word2 = *(u32 *)buf2;
} else if (size == 2) {
- word1 = *(ushort *)buf1;
- word2 = *(ushort *)buf2;
+ word1 = *(u16 *)buf1;
+ word2 = *(u16 *)buf2;
} else {
- word1 = *(u_char *)buf1;
- word2 = *(u_char *)buf2;
+ word1 = *(u8 *)buf1;
+ word2 = *(u8 *)buf2;
}
if (word1 != word2) {
ulong offset = buf1 - base;
src = map_sysmem(addr, bytes);
while (count-- > 0) {
if (size == 4)
- *((ulong *)buf) = *((ulong *)src);
+ *((u32 *)buf) = *((u32 *)src);
else if (size == 2)
- *((ushort *)buf) = *((ushort *)src);
+ *((u16 *)buf) = *((u16 *)src);
else
- *((u_char *)buf) = *((u_char *)src);
+ *((u8 *)buf) = *((u8 *)src);
src += size;
buf += size;
{
ulong addr, length, i, bytes;
int size;
- volatile uint *longp;
- volatile ushort *shortp;
- volatile u_char *cp;
+ volatile u32 *longp;
+ volatile u16 *shortp;
+ volatile u8 *cp;
const void *buf;
if (argc < 3)
*/
if (length == 1) {
if (size == 4) {
- longp = (uint *)buf;
+ longp = (u32 *)buf;
for (;;)
i = *longp;
}
if (size == 2) {
- shortp = (ushort *)buf;
+ shortp = (u16 *)buf;
for (;;)
i = *shortp;
}
- cp = (u_char *)buf;
+ cp = (u8 *)buf;
for (;;)
i = *cp;
}
if (size == 4) {
for (;;) {
- longp = (uint *)buf;
+ longp = (u32 *)buf;
i = length;
while (i-- > 0)
*longp++;
}
if (size == 2) {
for (;;) {
- shortp = (ushort *)buf;
+ shortp = (u16 *)buf;
i = length;
while (i-- > 0)
*shortp++;
}
}
for (;;) {
- cp = (u_char *)buf;
+ cp = (u8 *)buf;
i = length;
while (i-- > 0)
*cp++;
{
ulong addr, length, i, data, bytes;
int size;
- volatile uint *longp;
- volatile ushort *shortp;
- volatile u_char *cp;
+ volatile u32 *longp;
+ volatile u16 *shortp;
+ volatile u8 *cp;
void *buf;
if (argc < 4)
*/
if (length == 1) {
if (size == 4) {
- longp = (uint *)buf;
+ longp = (u32 *)buf;
for (;;)
*longp = data;
}
if (size == 2) {
- shortp = (ushort *)buf;
+ shortp = (u16 *)buf;
for (;;)
*shortp = data;
}
- cp = (u_char *)buf;
+ cp = (u8 *)buf;
for (;;)
*cp = data;
}
if (size == 4) {
for (;;) {
- longp = (uint *)buf;
+ longp = (u32 *)buf;
i = length;
while (i-- > 0)
*longp++ = data;
}
if (size == 2) {
for (;;) {
- shortp = (ushort *)buf;
+ shortp = (u16 *)buf;
i = length;
while (i-- > 0)
*shortp++ = data;
}
}
for (;;) {
- cp = (u_char *)buf;
+ cp = (u8 *)buf;
i = length;
while (i-- > 0)
*cp++ = data;
if (temp != pattern) {
printf("\nFAILURE: Address bit stuck high @ 0x%.8lx:"
" expected 0x%.8lx, actual 0x%.8lx\n",
- start_addr + offset, pattern, temp);
+ start_addr + offset*sizeof(vu_long),
+ pattern, temp);
errs++;
if (ctrlc())
return -1;
printf("\nFAILURE: Address bit stuck low or"
" shorted @ 0x%.8lx: expected 0x%.8lx,"
" actual 0x%.8lx\n",
- start_addr + offset, pattern, temp);
+ start_addr + offset*sizeof(vu_long),
+ pattern, temp);
errs++;
if (ctrlc())
return -1;
if (temp != pattern) {
printf("\nFAILURE (read/write) @ 0x%.8lx:"
" expected 0x%.8lx, actual 0x%.8lx)\n",
- start_addr + offset, pattern, temp);
+ start_addr + offset*sizeof(vu_long),
+ pattern, temp);
errs++;
if (ctrlc())
return -1;
if (temp != anti_pattern) {
printf("\nFAILURE (read/write): @ 0x%.8lx:"
" expected 0x%.8lx, actual 0x%.8lx)\n",
- start_addr + offset, anti_pattern, temp);
+ start_addr + offset*sizeof(vu_long),
+ anti_pattern, temp);
errs++;
if (ctrlc())
return -1;
printf("\nMem error @ 0x%08X: "
"found %08lX, expected %08lX\n",
- (uint)(uintptr_t)(start_addr + offset),
+ (uint)(uintptr_t)(start_addr + offset*sizeof(vu_long)),
readback, val);
errs++;
if (ctrlc())
ptr = map_sysmem(addr, size);
printf("%08lx:", addr);
if (size == 4)
- printf(" %08x", *((uint *)ptr));
+ printf(" %08x", *((u32 *)ptr));
else if (size == 2)
- printf(" %04x", *((ushort *)ptr));
+ printf(" %04x", *((u16 *)ptr));
else
- printf(" %02x", *((u_char *)ptr));
+ printf(" %02x", *((u8 *)ptr));
nbytes = readline (" ? ");
if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) {
reset_cmd_timeout();
#endif
if (size == 4)
- *((uint *)ptr) = i;
+ *((u32 *)ptr) = i;
else if (size == 2)
- *((ushort *)ptr) = i;
+ *((u16 *)ptr) = i;
else
- *((u_char *)ptr) = i;
+ *((u8 *)ptr) = i;
if (incrflag)
addr += size;
}
"- display info of the current MMC device"
);
-#ifdef CONFIG_SUPPORT_EMMC_BOOT
-static int boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access)
-{
- int err;
- err = mmc_boot_part_access(mmc, ack, part_num, access);
-
- if ((err == 0) && (access != 0)) {
- printf("\t\t\t!!!Notice!!!\n");
-
- printf("!You must close EMMC boot Partition");
- printf("after all images are written\n");
-
- printf("!EMMC boot partition has continuity");
- printf("at image writing time.\n");
-
- printf("!So, do not close the boot partition");
- printf("before all images are written.\n");
- return 0;
- } else if ((err == 0) && (access == 0))
- return 0;
- else if ((err != 0) && (access != 0)) {
- printf("EMMC boot partition-%d OPEN Failed.\n", part_num);
- return 1;
- } else {
- printf("EMMC boot partition-%d CLOSE Failed.\n", part_num);
- return 1;
- }
-}
-#endif
-
static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
enum mmc_state state;
return 1;
else
return 0;
- } else if (strncmp(argv[1], "part", 4) == 0) {
+ } else if (strcmp(argv[1], "part") == 0) {
block_dev_desc_t *mmc_dev;
struct mmc *mmc;
return 0;
#ifdef CONFIG_SUPPORT_EMMC_BOOT
- } else if ((strcmp(argv[1], "open") == 0) ||
- (strcmp(argv[1], "close") == 0)) {
+ } else if (strcmp(argv[1], "partconf") == 0) {
int dev;
struct mmc *mmc;
- u8 part_num, access = 0;
+ u8 ack, part_num, access;
- if (argc == 4) {
+ if (argc == 6) {
dev = simple_strtoul(argv[2], NULL, 10);
- part_num = simple_strtoul(argv[3], NULL, 10);
+ ack = simple_strtoul(argv[3], NULL, 10);
+ part_num = simple_strtoul(argv[4], NULL, 10);
+ access = simple_strtoul(argv[5], NULL, 10);
} else {
return CMD_RET_USAGE;
}
}
if (IS_SD(mmc)) {
- printf("SD device cannot be opened/closed\n");
+ puts("PARTITION_CONFIG only exists on eMMC\n");
return 1;
}
- if ((part_num <= 0) || (part_num > MMC_NUM_BOOT_PARTITION)) {
- printf("Invalid boot partition number:\n");
- printf("Boot partition number cannot be <= 0\n");
- printf("EMMC44 supports only 2 boot partitions\n");
+ /* acknowledge to be sent during boot operation */
+ return mmc_set_part_conf(mmc, ack, part_num, access);
+ } else if (strcmp(argv[1], "bootbus") == 0) {
+ int dev;
+ struct mmc *mmc;
+ u8 width, reset, mode;
+
+ if (argc == 6) {
+ dev = simple_strtoul(argv[2], NULL, 10);
+ width = simple_strtoul(argv[3], NULL, 10);
+ reset = simple_strtoul(argv[4], NULL, 10);
+ mode = simple_strtoul(argv[5], NULL, 10);
+ } else {
+ return CMD_RET_USAGE;
+ }
+
+ mmc = find_mmc_device(dev);
+ if (!mmc) {
+ printf("no mmc device at slot %x\n", dev);
return 1;
}
- if (strcmp(argv[1], "open") == 0)
- access = part_num; /* enable R/W access to boot part*/
- else
- access = 0; /* No access to boot partition */
+ if (IS_SD(mmc)) {
+ puts("BOOT_BUS_WIDTH only exists on eMMC\n");
+ return 1;
+ }
/* acknowledge to be sent during boot operation */
- return boot_part_access(mmc, 1, part_num, access);
-
- } else if (strcmp(argv[1], "bootpart") == 0) {
+ return mmc_set_boot_bus_width(mmc, width, reset, mode);
+ } else if (strcmp(argv[1], "bootpart-resize") == 0) {
int dev;
- dev = simple_strtoul(argv[2], NULL, 10);
+ struct mmc *mmc;
+ u32 bootsize, rpmbsize;
- u32 bootsize = simple_strtoul(argv[3], NULL, 10);
- u32 rpmbsize = simple_strtoul(argv[4], NULL, 10);
- struct mmc *mmc = find_mmc_device(dev);
+ if (argc == 5) {
+ dev = simple_strtoul(argv[2], NULL, 10);
+ bootsize = simple_strtoul(argv[3], NULL, 10);
+ rpmbsize = simple_strtoul(argv[4], NULL, 10);
+ } else {
+ return CMD_RET_USAGE;
+ }
+
+ mmc = find_mmc_device(dev);
if (!mmc) {
printf("no mmc device at slot %x\n", dev);
return 1;
"mmc dev [dev] [part] - show or set current mmc device [partition]\n"
"mmc list - lists available devices\n"
#ifdef CONFIG_SUPPORT_EMMC_BOOT
- "mmc open <dev> <boot_partition>\n"
- " - Enable boot_part for booting and enable R/W access of boot_part\n"
- "mmc close <dev> <boot_partition>\n"
- " - Enable boot_part for booting and disable access to boot_part\n"
- "mmc bootpart <device num> <boot part size MB> <RPMB part size MB>\n"
- " - change sizes of boot and RPMB partitions of specified device\n"
+ "mmc bootbus dev boot_bus_width reset_boot_bus_width boot_mode\n"
+ " - Set the BOOT_BUS_WIDTH field of the specified device\n"
+ "mmc bootpart-resize <dev> <boot part size MB> <RPMB part size MB>\n"
+ " - Change sizes of boot and RPMB partitions of specified device\n"
+ "mmc partconf dev boot_ack boot_partition partition_access\n"
+ " - Change the bits of the PARTITION_CONFIG field of the specified device\n"
#endif
"mmc setdsr - set DSR register value\n"
);
#include <command.h>
#include <asm/blackfin.h>
+#include <asm/clock.h>
#include <asm/mach-common/bits/otp.h>
static const char *otp_strerror(uint32_t err)
#include <linux/ctype.h>
#include <errno.h>
#include <linux/list.h>
+#include <fs.h>
#include "menu.h"
return ret;
}
+#ifdef CONFIG_CMD_NET
/*
* Convert an ethaddr from the environment to the format used by pxelinux
* filenames based on mac addresses. Convert's ':' to '-', and adds "01-" to
return 1;
}
+#endif
/*
* Returns the directory the file specified in the bootfile env variable is
static int (*do_getfile)(cmd_tbl_t *cmdtp, const char *file_path, char *file_addr);
+#ifdef CONFIG_CMD_NET
static int do_get_tftp(cmd_tbl_t *cmdtp, const char *file_path, char *file_addr)
{
char *tftp_argv[] = {"tftp", NULL, NULL, NULL};
return 1;
}
+#endif
static char *fs_argv[5];
return -ENOENT;
}
+static int do_get_any(cmd_tbl_t *cmdtp, const char *file_path, char *file_addr)
+{
+#ifdef CONFIG_CMD_FS_GENERIC
+ fs_argv[0] = "load";
+ fs_argv[3] = file_addr;
+ fs_argv[4] = (void *)file_path;
+
+ if (!do_load(cmdtp, 0, 5, fs_argv, FS_TYPE_ANY))
+ return 1;
+#endif
+ return -ENOENT;
+}
+
/*
* As in pxelinux, paths to files referenced from files we retrieve are
* relative to the location of bootfile. get_relfile takes such a path and
return 1;
}
+#ifdef CONFIG_CMD_NET
+
#define PXELINUX_DIR "pxelinux.cfg/"
/*
return 1;
}
+#endif
/*
* Wrapper to make it easier to store the file at file_path in the location
char *append;
char *initrd;
char *fdt;
+ char *fdtdir;
int ipappend;
int attempted;
int localboot;
if (label->fdt)
free(label->fdt);
+ if (label->fdtdir)
+ free(label->fdtdir);
+
free(label);
}
len += strlen(ip_str);
}
+#ifdef CONFIG_CMD_NET
if (label->ipappend & 0x2) {
int err;
strcpy(mac_str, " BOOTIF=");
mac_str[0] = '\0';
len += strlen(mac_str);
}
+#endif
if (label->append)
len += strlen(label->append);
bootm_argv[3] = getenv("fdt_addr_r");
/* if fdt label is defined then get fdt from server */
- if (bootm_argv[3] && label->fdt) {
- if (get_relfile_envaddr(cmdtp, label->fdt, "fdt_addr_r") < 0) {
- printf("Skipping %s for failure retrieving fdt\n",
- label->name);
- return 1;
+ if (bootm_argv[3]) {
+ char *fdtfile = NULL;
+ char *fdtfilefree = NULL;
+
+ if (label->fdt) {
+ fdtfile = label->fdt;
+ } else if (label->fdtdir) {
+ char *f1, *f2, *f3, *f4, *slash;
+
+ f1 = getenv("fdtfile");
+ if (f1) {
+ f2 = "";
+ f3 = "";
+ f4 = "";
+ } else {
+ /*
+ * For complex cases where this code doesn't
+ * generate the correct filename, the board
+ * code should set $fdtfile during early boot,
+ * or the boot scripts should set $fdtfile
+ * before invoking "pxe" or "sysboot".
+ */
+ f1 = getenv("soc");
+ f2 = "-";
+ f3 = getenv("board");
+ f4 = ".dtb";
+ }
+
+ len = strlen(label->fdtdir);
+ if (!len)
+ slash = "./";
+ else if (label->fdtdir[len - 1] != '/')
+ slash = "/";
+ else
+ slash = "";
+
+ len = strlen(label->fdtdir) + strlen(slash) +
+ strlen(f1) + strlen(f2) + strlen(f3) +
+ strlen(f4) + 1;
+ fdtfilefree = malloc(len);
+ if (!fdtfilefree) {
+ printf("malloc fail (FDT filename)\n");
+ return 1;
+ }
+
+ snprintf(fdtfilefree, len, "%s%s%s%s%s%s",
+ label->fdtdir, slash, f1, f2, f3, f4);
+ fdtfile = fdtfilefree;
+ }
+
+ if (fdtfile) {
+ int err = get_relfile_envaddr(cmdtp, fdtfile, "fdt_addr_r");
+ free(fdtfilefree);
+ if (err < 0) {
+ printf("Skipping %s for failure retrieving fdt\n",
+ label->name);
+ return 1;
+ }
+ } else {
+ bootm_argv[3] = NULL;
}
- } else
+ }
+
+ if (!bootm_argv[3])
bootm_argv[3] = getenv("fdt_addr");
if (bootm_argv[3])
T_PROMPT,
T_INCLUDE,
T_FDT,
+ T_FDTDIR,
T_ONTIMEOUT,
T_IPAPPEND,
T_INVALID
{"append", T_APPEND},
{"initrd", T_INITRD},
{"include", T_INCLUDE},
+ {"devicetree", T_FDT},
{"fdt", T_FDT},
+ {"devicetreedir", T_FDTDIR},
+ {"fdtdir", T_FDTDIR},
{"ontimeout", T_ONTIMEOUT,},
{"ipappend", T_IPAPPEND,},
{NULL, T_INVALID}
err = parse_sliteral(c, &label->fdt);
break;
+ case T_FDTDIR:
+ if (!label->fdtdir)
+ err = parse_sliteral(c, &label->fdtdir);
+ break;
+
case T_LOCALBOOT:
label->localboot = 1;
err = parse_integer(c, &label->localboot_val);
boot_unattempted_labels(cmdtp, cfg);
}
+#ifdef CONFIG_CMD_NET
/*
* Boots a system using a pxe file
*
"get - try to retrieve a pxe file using tftp\npxe "
"boot [pxefile_addr_r] - boot from the pxe file at pxefile_addr_r\n"
);
+#endif
/*
* Boots a system using a local disk syslinux/extlinux file
do_getfile = do_get_ext2;
else if (strstr(argv[3], "fat"))
do_getfile = do_get_fat;
+ else if (strstr(argv[3], "any"))
+ do_getfile = do_get_any;
else {
printf("Invalid filesystem: %s\n", argv[3]);
return 1;
U_BOOT_CMD(
sysboot, 7, 1, do_sysboot,
"command to get and boot from syslinux files",
- "[-p] <interface> <dev[:part]> <ext2|fat> [addr] [filename]\n"
- " - load and parse syslinux menu file 'filename' from ext2 or fat\n"
- " filesystem on 'dev' on 'interface' to address 'addr'"
+ "[-p] <interface> <dev[:part]> <ext2|fat|any> [addr] [filename]\n"
+ " - load and parse syslinux menu file 'filename' from ext2, fat\n"
+ " or any filesystem on 'dev' on 'interface' to address 'addr'"
);
scsi_curr_dev = -1;
printf("Found %d device(s).\n", scsi_max_devs);
+#ifndef CONFIG_SPL_BUILD
setenv_ulong("scsidevs", scsi_max_devs);
+#endif
}
int scsi_get_disk_count(void)
#include <common.h>
#include <command.h>
+#include <fs.h>
+
+#define OP_INVALID 0
+#define OP_NOT 1
+#define OP_OR 2
+#define OP_AND 3
+#define OP_STR_EMPTY 4
+#define OP_STR_NEMPTY 5
+#define OP_STR_EQ 6
+#define OP_STR_NEQ 7
+#define OP_STR_LT 8
+#define OP_STR_GT 9
+#define OP_INT_EQ 10
+#define OP_INT_NEQ 11
+#define OP_INT_LT 12
+#define OP_INT_LE 13
+#define OP_INT_GT 14
+#define OP_INT_GE 15
+#define OP_FILE_EXISTS 16
+
+const struct {
+ int arg;
+ const char *str;
+ int op;
+ int adv;
+} op_adv[] = {
+ {1, "=", OP_STR_EQ, 3},
+ {1, "!=", OP_STR_NEQ, 3},
+ {1, "<", OP_STR_LT, 3},
+ {1, ">", OP_STR_GT, 3},
+ {1, "-eq", OP_INT_EQ, 3},
+ {1, "-ne", OP_INT_NEQ, 3},
+ {1, "-lt", OP_INT_LT, 3},
+ {1, "-le", OP_INT_LE, 3},
+ {1, "-gt", OP_INT_GT, 3},
+ {1, "-ge", OP_INT_GE, 3},
+ {0, "!", OP_NOT, 1},
+ {0, "-o", OP_OR, 1},
+ {0, "-a", OP_AND, 1},
+ {0, "-z", OP_STR_EMPTY, 2},
+ {0, "-n", OP_STR_NEMPTY, 2},
+ {0, "-e", OP_FILE_EXISTS, 4},
+};
static int do_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
char * const *ap;
- int left, adv, expr, last_expr, neg, last_cmp;
+ int i, op, left, adv, expr, last_expr, last_unop, last_binop;
/* args? */
if (argc < 3)
}
#endif
- last_expr = 0;
- left = argc - 1; ap = argv + 1;
- if (left > 0 && strcmp(ap[0], "!") == 0) {
- neg = 1;
- ap++;
- left--;
- } else
- neg = 0;
-
- expr = -1;
- last_cmp = -1;
+ left = argc - 1;
+ ap = argv + 1;
+ expr = 0;
+ last_unop = OP_INVALID;
+ last_binop = OP_INVALID;
last_expr = -1;
while (left > 0) {
-
- if (strcmp(ap[0], "-o") == 0 || strcmp(ap[0], "-a") == 0)
- adv = 1;
- else if (strcmp(ap[0], "-z") == 0 || strcmp(ap[0], "-n") == 0)
- adv = 2;
- else
- adv = 3;
-
+ for (i = 0; i < ARRAY_SIZE(op_adv); i++) {
+ if (left <= op_adv[i].arg)
+ continue;
+ if (!strcmp(ap[op_adv[i].arg], op_adv[i].str)) {
+ op = op_adv[i].op;
+ adv = op_adv[i].adv;
+ break;
+ }
+ }
+ if (i == ARRAY_SIZE(op_adv)) {
+ expr = 1;
+ break;
+ }
if (left < adv) {
expr = 1;
break;
}
- if (adv == 1) {
- if (strcmp(ap[0], "-o") == 0) {
- last_expr = expr;
- last_cmp = 0;
- } else if (strcmp(ap[0], "-a") == 0) {
- last_expr = expr;
- last_cmp = 1;
- } else {
- expr = 1;
- break;
- }
+ switch (op) {
+ case OP_STR_EMPTY:
+ expr = strlen(ap[1]) == 0 ? 1 : 0;
+ break;
+ case OP_STR_NEMPTY:
+ expr = strlen(ap[1]) == 0 ? 0 : 1;
+ break;
+ case OP_STR_EQ:
+ expr = strcmp(ap[0], ap[2]) == 0;
+ break;
+ case OP_STR_NEQ:
+ expr = strcmp(ap[0], ap[2]) != 0;
+ break;
+ case OP_STR_LT:
+ expr = strcmp(ap[0], ap[2]) < 0;
+ break;
+ case OP_STR_GT:
+ expr = strcmp(ap[0], ap[2]) > 0;
+ break;
+ case OP_INT_EQ:
+ expr = simple_strtol(ap[0], NULL, 10) ==
+ simple_strtol(ap[2], NULL, 10);
+ break;
+ case OP_INT_NEQ:
+ expr = simple_strtol(ap[0], NULL, 10) !=
+ simple_strtol(ap[2], NULL, 10);
+ break;
+ case OP_INT_LT:
+ expr = simple_strtol(ap[0], NULL, 10) <
+ simple_strtol(ap[2], NULL, 10);
+ break;
+ case OP_INT_LE:
+ expr = simple_strtol(ap[0], NULL, 10) <=
+ simple_strtol(ap[2], NULL, 10);
+ break;
+ case OP_INT_GT:
+ expr = simple_strtol(ap[0], NULL, 10) >
+ simple_strtol(ap[2], NULL, 10);
+ break;
+ case OP_INT_GE:
+ expr = simple_strtol(ap[0], NULL, 10) >=
+ simple_strtol(ap[2], NULL, 10);
+ break;
+ case OP_FILE_EXISTS:
+ expr = file_exists(ap[1], ap[2], ap[3], FS_TYPE_ANY);
+ break;
}
- if (adv == 2) {
- if (strcmp(ap[0], "-z") == 0)
- expr = strlen(ap[1]) == 0 ? 1 : 0;
- else if (strcmp(ap[0], "-n") == 0)
- expr = strlen(ap[1]) == 0 ? 0 : 1;
- else {
- expr = 1;
- break;
+ switch (op) {
+ case OP_OR:
+ last_expr = expr;
+ last_binop = OP_OR;
+ break;
+ case OP_AND:
+ last_expr = expr;
+ last_binop = OP_AND;
+ break;
+ case OP_NOT:
+ if (last_unop == OP_NOT)
+ last_unop = OP_INVALID;
+ else
+ last_unop = OP_NOT;
+ break;
+ default:
+ if (last_unop == OP_NOT) {
+ expr = !expr;
+ last_unop = OP_INVALID;
}
- if (last_cmp == 0)
+ if (last_binop == OP_OR)
expr = last_expr || expr;
- else if (last_cmp == 1)
+ else if (last_binop == OP_AND)
expr = last_expr && expr;
- last_cmp = -1;
- }
-
- if (adv == 3) {
- if (strcmp(ap[1], "=") == 0)
- expr = strcmp(ap[0], ap[2]) == 0;
- else if (strcmp(ap[1], "!=") == 0)
- expr = strcmp(ap[0], ap[2]) != 0;
- else if (strcmp(ap[1], ">") == 0)
- expr = strcmp(ap[0], ap[2]) > 0;
- else if (strcmp(ap[1], "<") == 0)
- expr = strcmp(ap[0], ap[2]) < 0;
- else if (strcmp(ap[1], "-eq") == 0)
- expr = simple_strtol(ap[0], NULL, 10) == simple_strtol(ap[2], NULL, 10);
- else if (strcmp(ap[1], "-ne") == 0)
- expr = simple_strtol(ap[0], NULL, 10) != simple_strtol(ap[2], NULL, 10);
- else if (strcmp(ap[1], "-lt") == 0)
- expr = simple_strtol(ap[0], NULL, 10) < simple_strtol(ap[2], NULL, 10);
- else if (strcmp(ap[1], "-le") == 0)
- expr = simple_strtol(ap[0], NULL, 10) <= simple_strtol(ap[2], NULL, 10);
- else if (strcmp(ap[1], "-gt") == 0)
- expr = simple_strtol(ap[0], NULL, 10) > simple_strtol(ap[2], NULL, 10);
- else if (strcmp(ap[1], "-ge") == 0)
- expr = simple_strtol(ap[0], NULL, 10) >= simple_strtol(ap[2], NULL, 10);
- else {
- expr = 1;
- break;
- }
+ last_binop = OP_INVALID;
- if (last_cmp == 0)
- expr = last_expr || expr;
- else if (last_cmp == 1)
- expr = last_expr && expr;
- last_cmp = -1;
+ break;
}
ap += adv; left -= adv;
}
- if (neg)
- expr = !expr;
-
expr = !expr;
debug (": returns %d\n", expr);
return 0;
}
+static int ubi_check_volumename(const struct ubi_volume *vol, char *name)
+{
+ return strcmp(vol->name, name);
+}
+
+static int ubi_check(char *name)
+{
+ int i;
+
+ for (i = 0; i < (ubi->vtbl_slots + 1); i++) {
+ if (!ubi->volumes[i])
+ continue; /* Empty record */
+
+ if (!ubi_check_volumename(ubi->volumes[i], name))
+ return 0;
+ }
+
+ return -EEXIST;
+}
+
+
static int verify_mkvol_req(const struct ubi_device *ubi,
const struct ubi_mkvol_req *req)
{
return ubi_info(layout);
}
+ if (strcmp(argv[1], "check") == 0) {
+ if (argc > 2)
+ return ubi_check(argv[2]);
+
+ printf("Error, no volume name passed\n");
+ return 1;
+ }
+
if (strncmp(argv[1], "create", 6) == 0) {
int dynamic = 1; /* default: dynamic volume */
" header offset)\n"
"ubi info [l[ayout]]"
" - Display volume and ubi layout information\n"
+ "ubi check volumename"
+ " - check if volumename exists\n"
"ubi create[vol] volume [size] [type]"
" - create volume name with size\n"
"ubi write[vol] address volume size"
static int ubifs_initialized;
static int ubifs_mounted;
-extern struct super_block *ubifs_sb;
-
-/* Prototypes */
-int ubifs_init(void);
-int ubifs_mount(char *vol_name);
-void ubifs_umount(struct ubifs_info *c);
-int ubifs_ls(char *dir_name);
-int ubifs_load(char *filename, u32 addr, u32 size);
-
int do_ubifs_mount(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
char *vol_name;
void env_relocate_spec(void)
{
- char buf[CONFIG_ENV_SIZE];
int ret;
+ char *buf = NULL;
+ buf = (char *)malloc(CONFIG_ENV_SIZE);
env_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
if (!env_flash) {
set_default_env("!spi_flash_probe() failed");
+ if (buf)
+ free(buf);
return;
}
gd->env_valid = 1;
out:
spi_flash_free(env_flash);
+ if (buf)
+ free(buf);
env_flash = NULL;
}
#endif
return -1;
}
arch_fixup_memory_node(blob);
- if (IMAAGE_OF_BOARD_SETUP)
+ if (IMAGE_OF_BOARD_SETUP)
ft_board_setup(blob, gd->bd);
fdt_fixup_ethernet(blob);
}
bootstage_mark(bootstage_id + BOOTSTAGE_SUB_FORMAT_OK);
if (fit_uname) {
- /* get ramdisk component image node offset */
+ /* get FIT component image node offset */
bootstage_mark(bootstage_id + BOOTSTAGE_SUB_UNIT_NAME);
noffset = fit_image_get_node(fit, fit_uname);
} else {
{ IH_ARCH_OPENRISC, "or1k", "OpenRISC 1000",},
{ IH_ARCH_SANDBOX, "sandbox", "Sandbox", },
{ IH_ARCH_ARM64, "arm64", "AArch64", },
+ { IH_ARCH_ARC, "arc", "ARC", },
{ -1, "", "", },
};
#endif
#include <lcd.h>
#include <watchdog.h>
-
+#include <asm/unaligned.h>
#include <splash.h>
#if defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \
int x, y;
int decode = 1;
- width = le32_to_cpu(bmp->header.width);
- height = le32_to_cpu(bmp->header.height);
- bmap = (uchar *)bmp + le32_to_cpu(bmp->header.data_offset);
+ width = get_unaligned_le32(&bmp->header.width);
+ height = get_unaligned_le32(&bmp->header.height);
+ bmap = (uchar *)bmp + get_unaligned_le32(&bmp->header.data_offset);
x = 0;
y = height - 1;
return 1;
}
- width = le32_to_cpu(bmp->header.width);
- height = le32_to_cpu(bmp->header.height);
- bmp_bpix = le16_to_cpu(bmp->header.bit_count);
+ width = get_unaligned_le32(&bmp->header.width);
+ height = get_unaligned_le32(&bmp->header.height);
+ bmp_bpix = get_unaligned_le16(&bmp->header.bit_count);
+
colors = 1 << bmp_bpix;
bpix = NBITS(panel_info.vl_bpix);
/* We support displaying 8bpp BMPs on 16bpp LCDs */
if (bpix != bmp_bpix && !(bmp_bpix == 8 && bpix == 16)) {
printf ("Error: %d bit/pixel mode, but BMP has %d bit/pixel\n",
- bpix,
- le16_to_cpu(bmp->header.bit_count));
-
+ bpix, get_unaligned_le16(&bmp->header.bit_count));
return 1;
}
}
}
#endif
-
/*
* BMP format for Monochrome assumes that the state of a
* pixel is described on a per Bit basis, not per Byte.
if ((y + height) > panel_info.vl_row)
height = panel_info.vl_row - y;
- bmap = (uchar *) bmp + le32_to_cpu(bmp->header.data_offset);
- fb = (uchar *) (lcd_base +
+ bmap = (uchar *)bmp + get_unaligned_le32(&bmp->header.data_offset);
+ fb = (uchar *)(lcd_base +
(y + height - 1) * lcd_line_length + x * bpix / 8);
switch (bmp_bpix) {
case 1: /* pass through */
case 8:
#ifdef CONFIG_LCD_BMP_RLE8
- if (le32_to_cpu(bmp->header.compression) == BMP_BI_RLE8) {
+ u32 compression = get_unaligned_le32(&bmp->header.compression);
+ if (compression == BMP_BI_RLE8) {
if (bpix != 16) {
/* TODO implement render code for bpix != 16 */
printf("Error: only support 16 bpix");
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <config.h>
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
#ifdef __PPC__
/*
* At least on G2 PowerPC cores, sequential accesses to non-existent
return (maxsize);
}
+
+phys_size_t __weak get_effective_memsize(void)
+{
+#ifndef CONFIG_VERY_BIG_RAM
+ return gd->ram_size;
+#else
+ /* limit stack to what we can reasonable map */
+ return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
+ CONFIG_MAX_MEM_MAPPED : gd->ram_size);
+#endif
+}
obj-$(CONFIG_SPL_MMC_SUPPORT) += spl_mmc.o
obj-$(CONFIG_SPL_USB_SUPPORT) += spl_usb.o
obj-$(CONFIG_SPL_FAT_SUPPORT) += spl_fat.o
+obj-$(CONFIG_SPL_SATA_SUPPORT) += spl_sata.o
endif
case BOOT_DEVICE_USB:
spl_usb_load_image();
break;
+#endif
+#ifdef CONFIG_SPL_SATA_SUPPORT
+ case BOOT_DEVICE_SATA:
+ spl_sata_load_image();
+ break;
#endif
default:
debug("SPL: Un-supported Boot Device\n");
err = spl_load_image_fat(&mmc->block_dev,
CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION,
CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME);
+#endif
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+ } else if (boot_mode == MMCSD_MODE_EMMCBOOT) {
+ /*
+ * We need to check what the partition is configured to.
+ * 1 and 2 match up to boot0 / boot1 and 7 is user data
+ * which is the first physical partition (0).
+ */
+ int part = (mmc->part_config >> 3) & PART_ACCESS_MASK;
+
+ if (part == 7)
+ part = 0;
+
+ if (mmc_switch_part(0, part)) {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+ puts("MMC partition switch failed\n");
+#endif
+ hang();
+ }
+#ifdef CONFIG_SPL_OS_BOOT
+ if (spl_start_uboot() || mmc_load_image_raw_os(mmc))
+#endif
+ err = mmc_load_image_raw(mmc,
+ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR);
#endif
} else {
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
--- /dev/null
+/*
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * Dan Murphy <dmurphy@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Derived work from spl_usb.c
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/u-boot.h>
+#include <sata.h>
+#include <fat.h>
+#include <version.h>
+#include <image.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void spl_sata_load_image(void)
+{
+ int err;
+ block_dev_desc_t *stor_dev;
+
+ err = init_sata(CONFIG_SPL_SATA_BOOT_DEVICE);
+ if (err) {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+ printf("spl: sata init failed: err - %d\n", err);
+#endif
+ hang();
+ } else {
+ /* try to recognize storage devices immediately */
+ stor_dev = scsi_get_dev(0);
+ }
+
+#ifdef CONFIG_SPL_OS_BOOT
+ if (spl_start_uboot() || spl_load_image_fat_os(stor_dev,
+ CONFIG_SYS_SATA_FAT_BOOT_PARTITION))
+#endif
+ err = spl_load_image_fat(stor_dev,
+ CONFIG_SYS_SATA_FAT_BOOT_PARTITION,
+ CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME);
+ if (err) {
+ puts("Error loading sata device\n");
+ hang();
+ }
+}
#
#########################################################################
-# Set shell to bash if possible, otherwise fall back to sh
-SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \
- else if [ -x /bin/bash ]; then echo /bin/bash; \
- else echo sh; fi; fi)
-
-export SHELL
-
-ifeq ($(CURDIR),$(SRCTREE))
-dir :=
-else
-dir := $(subst $(SRCTREE)/,,$(CURDIR))
-endif
-
-ifneq ($(OBJTREE),$(SRCTREE))
-# Create object files for SPL in a separate directory
-ifeq ($(CONFIG_SPL_BUILD),y)
-ifeq ($(CONFIG_TPL_BUILD),y)
-obj := $(if $(dir),$(TPLTREE)/$(dir)/,$(TPLTREE)/)
-else
-obj := $(if $(dir),$(SPLTREE)/$(dir)/,$(SPLTREE)/)
-endif
-else
-obj := $(if $(dir),$(OBJTREE)/$(dir)/,$(OBJTREE)/)
-endif
-src := $(if $(dir),$(SRCTREE)/$(dir)/,$(SRCTREE)/)
-
-$(shell mkdir -p $(obj))
-else
-# Create object files for SPL in a separate directory
-ifeq ($(CONFIG_SPL_BUILD),y)
-ifeq ($(CONFIG_TPL_BUILD),y)
-obj := $(if $(dir),$(TPLTREE)/$(dir)/,$(TPLTREE)/)
-else
-obj := $(if $(dir),$(SPLTREE)/$(dir)/,$(SPLTREE)/)
-
-endif
-$(shell mkdir -p $(obj))
-else
-obj :=
-endif
-src :=
-endif
-
# clean the slate ...
PLATFORM_RELFLAGS =
PLATFORM_CPPFLAGS =
#########################################################################
-HOSTCFLAGS = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer \
- $(HOSTCPPFLAGS)
-HOSTSTRIP = strip
-
-#
-# Mac OS X / Darwin's C preprocessor is Apple specific. It
-# generates numerous errors and warnings. We want to bypass it
-# and use GNU C's cpp. To do this we pass the -traditional-cpp
-# option to the compiler. Note that the -traditional-cpp flag
-# DOES NOT have the same semantics as GNU C's flag, all it does
-# is invoke the GNU preprocessor in stock ANSI/ISO C fashion.
-#
-# Apple's linker is similar, thanks to the new 2 stage linking
-# multiple symbol definitions are treated as errors, hence the
-# -multiply_defined suppress option to turn off this error.
-#
-
-ifeq ($(HOSTOS),darwin)
-# get major and minor product version (e.g. '10' and '6' for Snow Leopard)
-DARWIN_MAJOR_VERSION = $(shell sw_vers -productVersion | cut -f 1 -d '.')
-DARWIN_MINOR_VERSION = $(shell sw_vers -productVersion | cut -f 2 -d '.')
-
-os_x_before = $(shell if [ $(DARWIN_MAJOR_VERSION) -le $(1) -a \
- $(DARWIN_MINOR_VERSION) -le $(2) ] ; then echo "$(3)"; else echo "$(4)"; fi ;)
-
-# Snow Leopards build environment has no longer restrictions as described above
-HOSTCC = $(call os_x_before, 10, 5, "cc", "gcc")
-HOSTCFLAGS += $(call os_x_before, 10, 4, "-traditional-cpp")
-HOSTLDFLAGS += $(call os_x_before, 10, 5, "-multiply_defined suppress")
-else
-HOSTCC = gcc
-endif
-
-ifeq ($(HOSTOS),cygwin)
-HOSTCFLAGS += -ansi
-endif
-
-# We build some files with extra pedantic flags to try to minimize things
-# that won't build on some weird host compiler -- though there are lots of
-# exceptions for files that aren't complaint.
-
-HOSTCFLAGS_NOPED = $(filter-out -pedantic,$(HOSTCFLAGS))
-HOSTCFLAGS += -pedantic
-
-#########################################################################
-#
-# Option checker, gcc version (courtesy linux kernel) to ensure
-# only supported compiler options are used
-#
-CC_OPTIONS_CACHE_FILE := $(OBJTREE)/include/generated/cc_options.mk
-CC_TEST_OFILE := $(OBJTREE)/include/generated/cc_test_file.o
-
--include $(CC_OPTIONS_CACHE_FILE)
-
-cc-option-sys = $(shell mkdir -p $(dir $(CC_TEST_OFILE)); \
- if $(CC) $(CFLAGS) $(1) -S -xc /dev/null -o $(CC_TEST_OFILE) \
- > /dev/null 2>&1; then \
- echo 'CC_OPTIONS += $(strip $1)' >> $(CC_OPTIONS_CACHE_FILE); \
- echo "$(1)"; fi)
-
-ifeq ($(CONFIG_CC_OPT_CACHE_DISABLE),y)
-cc-option = $(strip $(if $(call cc-option-sys,$1),$1,$2))
-else
-cc-option = $(strip $(if $(findstring $1,$(CC_OPTIONS)),$1,\
- $(if $(call cc-option-sys,$1),$1,$2)))
-endif
-
-# cc-version
-# Usage gcc-ver := $(call cc-version)
-cc-version = $(shell $(SHELL) $(SRCTREE)/scripts/gcc-version.sh $(CC))
-binutils-version = $(shell $(SHELL) $(SRCTREE)/scripts/binutils-version.sh $(AS))
-dtc-version = $(shell $(SHELL) $(SRCTREE)/scripts/dtc-version.sh $(DTC))
-
-#
-# Include the make variables (CC, etc...)
-#
-AS = $(CROSS_COMPILE)as
-
-# Always use GNU ld
-LD = $(shell if $(CROSS_COMPILE)ld.bfd -v > /dev/null 2>&1; \
- then echo "$(CROSS_COMPILE)ld.bfd"; else echo "$(CROSS_COMPILE)ld"; fi;)
-
-CC = $(CROSS_COMPILE)gcc
-CPP = $(CC) -E
-AR = $(CROSS_COMPILE)ar
-NM = $(CROSS_COMPILE)nm
-LDR = $(CROSS_COMPILE)ldr
-STRIP = $(CROSS_COMPILE)strip
-OBJCOPY = $(CROSS_COMPILE)objcopy
-OBJDUMP = $(CROSS_COMPILE)objdump
-RANLIB = $(CROSS_COMPILE)RANLIB
-DTC = dtc
-CHECK = sparse
-
-#########################################################################
-
-# Load generated board configuration
-ifeq ($(CONFIG_TPL_BUILD),y)
-# Include TPL autoconf
-sinclude $(OBJTREE)/include/tpl-autoconf.mk
-else
-ifeq ($(CONFIG_SPL_BUILD),y)
-# Include SPL autoconf
-sinclude $(OBJTREE)/include/spl-autoconf.mk
-else
-# Include normal autoconf
-sinclude $(OBJTREE)/include/autoconf.mk
-endif
-endif
-sinclude $(OBJTREE)/include/config.mk
-
# Some architecture config.mk files need to know what CPUDIR is set to,
# so calculate CPUDIR before including ARCH/SOC/CPU config.mk files.
# Check if arch/$ARCH/cpu/$CPU exists, otherwise assume arch/$ARCH/cpu contains
#########################################################################
-# We don't actually use $(ARFLAGS) anywhere anymore, so catch people
-# who are porting old code to latest mainline but not updating $(AR).
-ARFLAGS = $(error update your Makefile to use cmd_link_o_target and not AR)
RELFLAGS= $(PLATFORM_RELFLAGS)
-DBGFLAGS= -g # -DDEBUG
-OPTFLAGS= -Os #-fomit-frame-pointer
-
-OBJCFLAGS += --gap-fill=0xff
-gccincdir := $(shell $(CC) -print-file-name=include)
-
-CPPFLAGS := $(DBGFLAGS) $(OPTFLAGS) $(RELFLAGS) \
- -D__KERNEL__
-
-# Enable garbage collection of un-used sections for SPL
-ifeq ($(CONFIG_SPL_BUILD),y)
-CPPFLAGS += -ffunction-sections -fdata-sections
-LDFLAGS_FINAL += --gc-sections
-endif
+OBJCOPYFLAGS += --gap-fill=0xff
-# TODO(sjg@chromium.org): Is this correct on Mac OS?
-
-# MXSImage needs LibSSL
-ifneq ($(CONFIG_MX23)$(CONFIG_MX28),)
-HOSTLIBS += -lssl -lcrypto
-# Add CONFIG_MXS into host CFLAGS, so we can check whether or not register
-# the mxsimage support within tools/mxsimage.c .
-HOSTCFLAGS += -DCONFIG_MXS
-endif
-
-ifdef CONFIG_FIT_SIGNATURE
-HOSTLIBS += -lssl -lcrypto
-
-# This affects include/image.h, but including the board config file
-# is tricky, so manually define this options here.
-HOSTCFLAGS += -DCONFIG_FIT_SIGNATURE
-endif
-
-ifneq ($(CONFIG_SYS_TEXT_BASE),)
-CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
-endif
-
-ifeq ($(CONFIG_SPL_BUILD),y)
-CPPFLAGS += -DCONFIG_SPL_BUILD
-ifeq ($(CONFIG_TPL_BUILD),y)
-CPPFLAGS += -DCONFIG_TPL_BUILD
-endif
-endif
-
-# Does this architecture support generic board init?
-ifeq ($(__HAVE_ARCH_GENERIC_BOARD),)
-ifneq ($(CONFIG_SYS_GENERIC_BOARD),)
-CHECK_GENERIC_BOARD = $(error Your architecture does not support generic board. \
-Please undefined CONFIG_SYS_GENERIC_BOARD in your board config file)
-endif
-endif
-
-# Sandbox needs the base flags and includes, so keep them around
-BASE_CPPFLAGS := $(CPPFLAGS)
-
-ifneq ($(OBJTREE),$(SRCTREE))
-BASE_INCLUDE_DIRS := $(OBJTREE)/include
-endif
-
-BASE_INCLUDE_DIRS += $(TOPDIR)/include $(SRCTREE)/arch/$(ARCH)/include
-
-CPPFLAGS += $(patsubst %, -I%, $(BASE_INCLUDE_DIRS))
-CPPFLAGS += -fno-builtin -ffreestanding -nostdinc \
- -isystem $(gccincdir) -pipe $(PLATFORM_CPPFLAGS)
-
-CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes
-
-ifdef BUILD_TAG
-CFLAGS += -DBUILD_TAG='"$(BUILD_TAG)"'
-endif
-
-CFLAGS_SSP := $(call cc-option,-fno-stack-protector)
-CFLAGS += $(CFLAGS_SSP)
-# Some toolchains enable security related warning flags by default,
-# but they don't make much sense in the u-boot world, so disable them.
-CFLAGS_WARN := $(call cc-option,-Wno-format-nonliteral) \
- $(call cc-option,-Wno-format-security)
-CFLAGS += $(CFLAGS_WARN)
-
-# Report stack usage if supported
-CFLAGS_STACK := $(call cc-option,-fstack-usage)
-CFLAGS += $(CFLAGS_STACK)
+CPPFLAGS = $(RELFLAGS)
+CPPFLAGS += -pipe $(PLATFORM_CPPFLAGS)
BCURDIR = $(subst $(SRCTREE)/,,$(CURDIR:$(obj)%=%))
-ifeq ($(findstring examples/,$(BCURDIR)),)
-ifeq ($(CONFIG_SPL_BUILD),)
-ifdef FTRACE
-CFLAGS += -finstrument-functions -DFTRACE
-endif
-endif
-endif
-
-# $(CPPFLAGS) sets -g, which causes gcc to pass a suitable -g<format>
-# option to the assembler.
-AFLAGS_DEBUG :=
-
-# turn jbsr into jsr for m68k
-ifeq ($(ARCH),m68k)
-ifeq ($(findstring 3.4,$(shell $(CC) --version)),3.4)
-AFLAGS_DEBUG := -Wa,-gstabs,-S
-endif
-endif
-
-AFLAGS := $(AFLAGS_DEBUG) -D__ASSEMBLY__ $(CPPFLAGS)
-
LDFLAGS += $(PLATFORM_LDFLAGS)
LDFLAGS_FINAL += -Bstatic
-
-LDFLAGS_u-boot += -T $(obj)u-boot.lds $(LDFLAGS_FINAL)
-ifneq ($(CONFIG_SYS_TEXT_BASE),)
-LDFLAGS_u-boot += -Ttext $(CONFIG_SYS_TEXT_BASE)
-endif
-
-LDFLAGS_$(SPL_BIN) += -T $(obj)u-boot-spl.lds $(LDFLAGS_FINAL)
-ifneq ($(CONFIG_SPL_TEXT_BASE),)
-LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_SPL_TEXT_BASE)
-endif
-
-# Linus' kernel sanity checking tool
-CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \
- -Wbitwise -Wno-return-void -D__CHECK_ENDIAN__ $(CF)
-
-# Location of a usable BFD library, where we define "usable" as
-# "built for ${HOST}, supports ${TARGET}". Sensible values are
-# - When cross-compiling: the root of the cross-environment
-# - Linux/ppc (native): /usr
-# - NetBSD/ppc (native): you lose ... (must extract these from the
-# binutils build directory, plus the native and U-Boot include
-# files don't like each other)
-#
-# So far, this is used only by tools/gdb/Makefile.
-
-ifeq ($(HOSTOS),darwin)
-BFD_ROOT_DIR = /usr/local/tools
-else
-ifeq ($(HOSTARCH),$(ARCH))
-# native
-BFD_ROOT_DIR = /usr
-else
-#BFD_ROOT_DIR = /LinuxPPC/CDK # Linux/i386
-#BFD_ROOT_DIR = /usr/pkg/cross # NetBSD/i386
-BFD_ROOT_DIR = /opt/powerpc
-endif
-endif
-
-#########################################################################
-
-export HOSTCC HOSTCFLAGS HOSTLDFLAGS PEDCFLAGS HOSTSTRIP CROSS_COMPILE \
- AS LD CC CPP AR NM STRIP OBJCOPY OBJDUMP MAKE
-export CONFIG_SYS_TEXT_BASE PLATFORM_CPPFLAGS PLATFORM_RELFLAGS CPPFLAGS CFLAGS AFLAGS
-
-#########################################################################
-
-# Allow boards to use custom optimize flags on a per dir/file basis
-ALL_AFLAGS = $(AFLAGS) $(AFLAGS_$(BCURDIR)/$(@F)) $(AFLAGS_$(BCURDIR))
-ALL_CFLAGS = $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR))
-EXTRA_CPPFLAGS = $(CPPFLAGS_$(BCURDIR)/$(@F)) $(CPPFLAGS_$(BCURDIR))
-ALL_CFLAGS += $(EXTRA_CPPFLAGS)
-
-# The _DEP version uses the $< file target (for dependency generation)
-# See rules.mk
-EXTRA_CPPFLAGS_DEP = $(CPPFLAGS_$(BCURDIR)/$(addsuffix .o,$(basename $<))) \
- $(CPPFLAGS_$(BCURDIR))
-$(obj)%.s: %.S
- $(CPP) $(ALL_AFLAGS) -o $@ $<
-$(obj)%.o: %.S
- $(CC) $(ALL_AFLAGS) -o $@ $< -c
-$(obj)%.o: %.c
-ifneq ($(CHECKSRC),0)
- $(CHECK) $(CHECKFLAGS) $(ALL_CFLAGS) $<
-endif
- $(CC) $(ALL_CFLAGS) -o $@ $< -c
-$(obj)%.i: %.c
- $(CPP) $(ALL_CFLAGS) -o $@ $< -c
-$(obj)%.s: %.c
- $(CC) $(ALL_CFLAGS) -o $@ $< -c -S
-
-#########################################################################
-
-# If the list of objects to link is empty, just create an empty built-in.o
-cmd_link_o_target = $(if $(strip $1),\
- $(LD) $(LDFLAGS) -r -o $@ $1,\
- rm -f $@; $(AR) rcs $@ )
-
-#########################################################################
# SPDX-License-Identifier: GPL-2.0+
#
-#CFLAGS += -DET_DEBUG -DDEBUG
+#ccflags-y += -DET_DEBUG -DDEBUG
obj-$(CONFIG_PARTITIONS) += part.o
obj-$(CONFIG_MAC_PARTITION) += part_mac.o
*/
static int set_protective_mbr(block_dev_desc_t *dev_desc)
{
- legacy_mbr *p_mbr;
-
/* Setup the Protective MBR */
- p_mbr = calloc(1, sizeof(p_mbr));
+ ALLOC_CACHE_ALIGN_BUFFER(legacy_mbr, p_mbr, 1);
+ memset(p_mbr, 0, sizeof(*p_mbr));
+
if (p_mbr == NULL) {
printf("%s: calloc failed!\n", __func__);
return -1;
if (dev_desc->block_write(dev_desc->dev, 0, 1, p_mbr) != 1) {
printf("** Can't write to device %d **\n",
dev_desc->dev);
- free(p_mbr);
return -1;
}
- free(p_mbr);
return 0;
}
###
# This makefile is used to generate the kernel documentation,
# primarily based on in-line comments in various source files.
-# See doc/kernel-doc-nano-HOWTO.txt for instruction in how
+# See Documentation/kernel-doc-nano-HOWTO.txt for instruction in how
# to document the SRC - and how to read it.
# To add a new book the only step required is to add the book to the
# list of DOCBOOKS.
-include $(TOPDIR)/config.mk
-
-DOCBOOKS := fs.xml linker_lists.xml stdio.xml
+DOCBOOKS := linker_lists.xml stdio.xml
###
# The build process is as follows (targets):
###
# The targets that may be used.
-PHONY += $(obj).depend xmldocs sgmldocs psdocs pdfdocs htmldocs mandocs installmandocs cleandocs
+PHONY += xmldocs sgmldocs psdocs pdfdocs htmldocs mandocs installmandocs cleandocs
-BOOKS := $(addprefix $(OBJTREE)/doc/DocBook/,$(DOCBOOKS))
+BOOKS := $(addprefix $(obj)/,$(DOCBOOKS))
xmldocs: $(BOOKS)
sgmldocs: xmldocs
###
#External programs used
-KERNELDOC = $(SRCTREE)/tools/kernel-doc/kernel-doc
-DOCPROC = $(OBJTREE)/tools/kernel-doc/docproc
+KERNELDOC = $(srctree)/scripts/kernel-doc
+DOCPROC = $(objtree)/scripts/docproc
-XMLTOFLAGS = -m $(SRCTREE)/doc/DocBook/stylesheet.xsl
+XMLTOFLAGS = -m $(srctree)/doc/DocBook/stylesheet.xsl
XMLTOFLAGS += --skip-validation
###
# appropriate parameters.
# The following rules are used to generate the .xml documentation
# required to generate the final targets. (ps, pdf, html).
-%.xml: %.tmpl
- $(DOCPROC) doc $< >$@
-
-ifeq ($@, "cleandocs")
-sinclude $(obj).depend
-$(obj).depend: $(patsubst %.xml, %.tmpl, $(DOCBOOKS))
- rm -f $(obj).depend ; \
- touch $(obj).depend ; \
- for file in $^ ; do \
- xmlfile=`echo "$${file}" | \
- sed "s/tmpl$$/xml/"` ; \
- echo -n "$${xmlfile}: ">> $(obj).depend ; \
- $(DOCPROC) depend $$file >> $(obj).depend ; \
- echo -e "\n\t$(DOCPROC) doc $< >$${xmlfile} " >> \
- $(obj).depend ; \
- done
+quiet_cmd_docproc = DOCPROC $@
+ cmd_docproc = SRCTREE=$(srctree)/ $(DOCPROC) doc $< >$@
+define rule_docproc
+ set -e; \
+ $(if $($(quiet)cmd_$(1)),echo ' $($(quiet)cmd_$(1))';) \
+ $(cmd_$(1)); \
+ ( \
+ echo 'cmd_$@ := $(cmd_$(1))'; \
+ echo $@: `SRCTREE=$(srctree) $(DOCPROC) depend $<`; \
+ ) > $(dir $@).$(notdir $@).cmd
+endef
+
+%.xml: %.tmpl FORCE
+ $(call if_changed_rule,docproc)
+
+###
+#Read in all saved dependency files
+cmd_files := $(wildcard $(foreach f,$(BOOKS),$(dir $(f)).$(notdir $(f)).cmd))
+
+ifneq ($(cmd_files),)
+ include $(cmd_files)
endif
###
# Changes in kernel-doc force a rebuild of all documentation
$(BOOKS): $(KERNELDOC)
+# Tell kbuild to always build the programs
+always := $(hostprogs-y)
+
notfoundtemplate = echo "*** You have to install docbook-utils or xmlto ***"; \
exit 1
db2xtemplate = db2TYPE -o $(dir $@) $<
quiet_cmd_db2ps = PS $@
cmd_db2ps = $(subst TYPE,ps, $($(PS_METHOD)template))
%.ps : %.xml
- $(call cmd_db2ps)
+ $(call cmd,db2ps)
quiet_cmd_db2pdf = PDF $@
cmd_db2pdf = $(subst TYPE,pdf, $($(PDF_METHOD)template))
%.pdf : %.xml
- $(call cmd_db2pdf)
+ $(call cmd,db2pdf)
index = index.html
-main_idx = $(index)
+main_idx = doc/DocBook/$(index)
build_main_index = rm -rf $(main_idx); \
echo '<h1>U-Boot Bootloader HTML Documentation</h1>' >> $(main_idx) && \
- echo '<h2>U-Boot Version: $(U_BOOT_VERSION)</h2>' >> $(main_idx) && \
+ echo '<h2>U-Boot Version: $(UBOOTVERSION)</h2>' >> $(main_idx) && \
cat $(HTML) >> $(main_idx)
-# To work around bug [1] in docbook-xsl-stylesheets 1.76.1 , generate only html
-# docs instead of xhtml with xmlto.
-# [1] http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=654338
quiet_cmd_db2html = HTML $@
- cmd_db2html = xmlto html $(XMLTOFLAGS) -o $(patsubst %.html,%,$@) $< && \
+ cmd_db2html = xmlto xhtml $(XMLTOFLAGS) -o $(patsubst %.html,%,$@) $< && \
echo '<a HREF="$(patsubst %.html,%,$(notdir $@))/index.html"> \
- $(patsubst %.html,%,$(notdir $@))</a><p>' > $@
+
$(patsubst %.html,%,$(notdir $@))</a><p>' > $@
%.html: %.xml
@(which xmlto > /dev/null 2>&1) || \
(echo "*** You need to install xmlto ***"; \
exit 1)
@rm -rf $@ $(patsubst %.html,%,$@)
- $(call cmd_db2html)
+ $(call cmd,db2html)
@if [ ! -z "$(PNG-$(basename $(notdir $@)))" ]; then \
- cp $(PNG-$(basename $(notdir $@))) $(patsubst %.html,%,$@); fi
+ cp $(PNG-$(basename $(notdir $@))) $(patsubst %.html,%,$@); fi
quiet_cmd_db2man = MAN $@
cmd_db2man = if grep -q refentry $<; then xmlto man $(XMLTOFLAGS) -o $(obj)/man $< ; gzip -f $(obj)/man/*.9; fi
@(which xmlto > /dev/null 2>&1) || \
(echo "*** You need to install xmlto ***"; \
exit 1)
- $(Q)mkdir -p $(obj)man
- $(call cmd_db2man)
+ $(Q)mkdir -p $(obj)/man
+ $(call cmd,db2man)
@touch $@
###
@(which fig2dev > /dev/null 2>&1) || \
(echo "*** You need to install transfig ***"; \
exit 1)
- $(call cmd_fig2eps)
+ $(call cmd,fig2eps)
quiet_cmd_fig2png = FIG2PNG $@
cmd_fig2png = fig2dev -Lpng $< $@
@(which fig2dev > /dev/null 2>&1) || \
(echo "*** You need to install transfig ***"; \
exit 1)
- $(call cmd_fig2png)
+ $(call cmd,fig2png)
###
# Rule to convert a .c file to inline XML documentation
clean-dirs := $(patsubst %.xml,%,$(DOCBOOKS)) man
cleandocs:
- @rm -f $(obj).depend
- @$(Q)rm -f $(call objectify, $(clean-files))
- @$(Q)rm -rf $(call objectify, $(clean-dirs))
+ $(Q)rm -f $(call objectify, $(clean-files))
+ $(Q)rm -rf $(call objectify, $(clean-dirs))
# Declare the contents of the .PHONY variable as phony. We keep that
# information in a variable se we can use it in if_changed and friends.
<!-- <param name="paper.type">A4</param> -->
<param name="generate.section.toc.level">2</param>
<param name="use.id.as.filename">1</param>
-<param name="html.stylesheet">../docbook.css</param>
</stylesheet>
--- /dev/null
+Synopsys' DesignWare(r) ARC(r) Processors are a family of 32-bit CPUs
+that SoC designers can optimize for a wide range of uses, from deeply embedded
+to high-performance host applications.
+
+More information on ARC cores avaialble here:
+http://www.synopsys.com/IP/ProcessorIP/ARCProcessors/Pages/default.aspx
+
+Designers can differentiate their products by using patented configuration
+technology to tailor each ARC processor instance to meet specific performance,
+power and area requirements.
+
+The DesignWare ARC processors are also extendable, allowing designers to add
+their own custom instructions that dramatically increase performance.
+
+Synopsys' ARC processors have been used by over 170 customers worldwide who
+collectively ship more than 1 billion ARC-based chips annually.
+
+All DesignWare ARC processors utilize a 16-/32-bit ISA that provides excellent
+performance and code density for embedded and host SoC applications.
+
+The RISC microprocessors are synthesizable and can be implemented in any foundry
+or process, and are supported by a complete suite of development tools.
+
+The ARC GNU toolchain with support for all ARC Processors can be downloaded
+from here (available pre-built toolchains as well):
+
+https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases
+++ /dev/null
-If you are reading this because of a data abort: the following MIGHT
-be relevant to your abort, if it was caused by an alignment violation.
-In order to determine this, use the PC from the abort dump along with
-an objdump -s -S of the u-boot ELF binary to locate the function where
-the abort happened; then compare this function with the examples below.
-If they match, then you've been hit with a compiler generated unaligned
-access, and you should rewrite your code or add -mno-unaligned-access
-to the command line of the offending file.
-
-Note that the PC shown in the abort message is relocated. In order to
-be able to match it to an address in the ELF binary dump, you will need
-to know the relocation offset. If your target defines CONFIG_CMD_BDI
-and if you can get to the prompt and enter commands before the abort
-happens, then command "bdinfo" will give you the offset. Otherwise you
-will need to try a build with DEBUG set, which will display the offset,
-or use a debugger and set a breakpoint at relocate_code() to see the
-offset (passed as an argument).
-
-*
-
-Since U-Boot runs on a variety of hardware, some only able to perform
-unaligned accesses with a strong penalty, some unable to perform them
-at all, the policy regarding unaligned accesses is to not perform any,
-unless absolutely necessary because of hardware or standards.
-
-Also, on hardware which permits it, the core is configured to throw
-data abort exceptions on unaligned accesses in order to catch these
-unallowed accesses as early as possible.
-
-Until version 4.7, the gcc default for performing unaligned accesses
-(-mno-unaligned-access) is to emulate unaligned accesses using aligned
-loads and stores plus shifts and masks. Emulated unaligned accesses
-will not be caught by hardware. These accesses may be costly and may
-be actually unnecessary. In order to catch these accesses and remove
-or optimize them, option -munaligned-access is explicitly set for all
-versions of gcc which support it.
-
-From gcc 4.7 onward starting at armv7 architectures, the default for
-performing unaligned accesses is to use unaligned native loads and
-stores (-munaligned-access), because the cost of unaligned accesses
-has dropped on armv7 and beyond. This should not affect U-Boot's
-policy of controlling unaligned accesses, however the compiler may
-generate uncontrolled unaligned accesses on its own in at least one
-known case: when declaring a local initialized char array, e.g.
-
-function foo()
-{
- char buffer[] = "initial value";
-/* or */
- char buffer[] = { 'i', 'n', 'i', 't', 0 };
- ...
-}
-
-Under -munaligned-accesses with optimizations on, this declaration
-causes the compiler to generate native loads from the literal string
-and native stores to the buffer, and the literal string alignment
-cannot be controlled. If it is misaligned, then the core will throw
-a data abort exception.
-
-Quite probably the same might happen for 16-bit array initializations
-where the constant is aligned on a boundary which is a multiple of 2
-but not of 4:
-
-function foo()
-{
- u16 buffer[] = { 1, 2, 3 };
- ...
-}
-
-The long term solution to this issue is to add an option to gcc to
-allow controlling the general alignment of data, including constant
-initialization values.
-
-However this will only apply to the version of gcc which will have such
-an option. For other versions, there are four workarounds:
-
-a) Enforce as a rule that array initializations as described above
- are forbidden. This is generally not acceptable as they are valid,
- and usual, C constructs. The only case where they could be rejected
- is when they actually equate to a const char* declaration, i.e. the
- array is initialized and never modified in the function's scope.
-
-b) Drop the requirement on unaligned accesses at least for ARMv7,
- i.e. do not throw a data abort exception upon unaligned accesses.
- But that will allow adding badly aligned code to U-Boot, only for
- it to fail when re-used with a stricter target, possibly once the
- bad code is already in mainline.
-
-c) Relax the -munaligned-access rule globally. This will prevent native
- unaligned accesses of course, but that will also hide any bug caused
- by a bad unaligned access, making it much harder to diagnose it. It
- is actually what already happens when building ARM targets with a
- pre-4.7 gcc, and it may actually already hide some bugs yet unseen
- until the target gets compiled with -munaligned-access.
-
-d) Relax the -munaligned-access rule only for for files susceptible to
- the local initialized array issue and for armv7 architectures and
- beyond. This minimizes the quantity of code which can hide unwanted
- misaligned accesses.
-
-The option retained is d).
-
-Considering that actual occurrences of the issue are rare (as of this
-writing, 5 files out of 7840 in U-Boot, or .3%, contain an initialized
-local char array which cannot actually be replaced with a const char*),
-contributors should not be required to systematically try and detect
-the issue in their patches.
-
-Detecting files susceptible to the issue can be automated through a
-filter installed as a hook in .git which recognizes local char array
-initializations. Automation should err on the false positive side, for
-instance flagging non-local arrays as if they were local if they cannot
-be told apart.
-
-In any case, detection shall not prevent committing the patch, but
-shall pre-populate the commit message with a note to the effect that
-this patch contains an initialized local char or 16-bit array and thus
-should be protected from the gcc 4.7 issue.
-
-Upon a positive detection, either $(PLATFORM_NO_UNALIGNED) should be
-added to CFLAGS for the affected file(s), or if the array is a pseudo
-const char*, it should be replaced by an actual one.
0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB
0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB
0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
-0xEF300000 0xEFF3FFFF rootfs (alternate bank) 12MB + 256KB
+0xEF300000 0xEFEFFFFF rootfs (alternate bank) 12MB
0xEE800000 0xEE8FFFFF device tree (alternate bank) 1MB
0xEE020000 0xEE6FFFFF Linux.uImage (alternate bank) 6MB+896KB
0xEE000000 0xEE01FFFF RCW (alternate bank) 128KB
0xEDF40000 0xEDFFFFFF u-boot (alternate bank) 768KB
0xEDF20000 0xEDF3FFFF u-boot env (alternate bank) 128KB
0xEDF00000 0xEDF1FFFF FMAN ucode (alternate bank) 128KB
-0xED300000 0xEDF3FFFF rootfs (current bank) 12MB+256MB
+0xED300000 0xEDEFFFFF rootfs (current bank) 12MB
0xEC800000 0xEC8FFFFF device tree (current bank) 1MB
0xEC020000 0xEC6FFFFF Linux.uImage (current bank) 6MB+896KB
0xEC000000 0xEC01FFFF RCW (current bank) 128KB
+++ /dev/null
-This driver supports Designware Ethernet Controller provided by Synopsis.
-
-The driver is enabled by CONFIG_DESIGNWARE_ETH.
-
-The driver has been developed and tested on SPEAr platforms. By default, the
-MDIO interface works at 100/Full. #defining the below options in board
-configuration file changes this behavior.
-
-Call an subroutine from respective board/.../board.c
-designware_initialize(u32 id, ulong base_addr, u32 phy_addr);
-
-The various options suported by the driver are
-1. CONFIG_DW_ALTDESCRIPTOR
- Define this to use the Alternate/Enhanced Descriptor configurations.
-1. CONFIG_DW_AUTONEG
- Define this to autonegotiate with the host before proceeding with mac
- level configuration. This obviates the definitions of CONFIG_DW_SPEED10M
- and CONFIG_DW_DUPLEXHALF.
-2. CONFIG_DW_SPEED10M
- Define this to change the default behavior from 100Mbps to 10Mbps.
-3. CONFIG_DW_DUPLEXHALF
- Define this to change the default behavior from Full Duplex to Half.
-4. CONFIG_DW_SEARCH_PHY
- Define this to search the phy address. This would overwrite the value
- passed as 3rd arg from designware_initialize routine.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+dvl_host arm ixp - 2014-01-28 Michael Schwingen <michael@schwingen.org>
+actux4 arm ixp - 2014-01-28 Michael Schwingen <michael@schwingen.org>
+actux3 arm ixp - 2014-01-28 Michael Schwingen <michael@schwingen.org>
+actux2 arm ixp - 2014-01-28 Michael Schwingen <michael@schwingen.org>
+actux1 arm ixp - 2014-01-28 Michael Schwingen <michael@schwingen.org>
mx1ads arm arm920t - 2014-01-13
mini2440 arm arm920t - 2014-01-13 Gabriel Huau <contact@huau-gabriel.fr>
omap730p2 arm arm926ejs 79c5c08d 2013-11-11
--- /dev/null
+Editors note: This document is _heavily_ cribbed from the Linux Kernel, with
+really only the section about "Alignment vs. Networking" removed.
+
+UNALIGNED MEMORY ACCESSES
+=========================
+
+Linux runs on a wide variety of architectures which have varying behaviour
+when it comes to memory access. This document presents some details about
+unaligned accesses, why you need to write code that doesn't cause them,
+and how to write such code!
+
+
+The definition of an unaligned access
+=====================================
+
+Unaligned memory accesses occur when you try to read N bytes of data starting
+from an address that is not evenly divisible by N (i.e. addr % N != 0).
+For example, reading 4 bytes of data from address 0x10004 is fine, but
+reading 4 bytes of data from address 0x10005 would be an unaligned memory
+access.
+
+The above may seem a little vague, as memory access can happen in different
+ways. The context here is at the machine code level: certain instructions read
+or write a number of bytes to or from memory (e.g. movb, movw, movl in x86
+assembly). As will become clear, it is relatively easy to spot C statements
+which will compile to multiple-byte memory access instructions, namely when
+dealing with types such as u16, u32 and u64.
+
+
+Natural alignment
+=================
+
+The rule mentioned above forms what we refer to as natural alignment:
+When accessing N bytes of memory, the base memory address must be evenly
+divisible by N, i.e. addr % N == 0.
+
+When writing code, assume the target architecture has natural alignment
+requirements.
+
+In reality, only a few architectures require natural alignment on all sizes
+of memory access. However, we must consider ALL supported architectures;
+writing code that satisfies natural alignment requirements is the easiest way
+to achieve full portability.
+
+
+Why unaligned access is bad
+===========================
+
+The effects of performing an unaligned memory access vary from architecture
+to architecture. It would be easy to write a whole document on the differences
+here; a summary of the common scenarios is presented below:
+
+ - Some architectures are able to perform unaligned memory accesses
+ transparently, but there is usually a significant performance cost.
+ - Some architectures raise processor exceptions when unaligned accesses
+ happen. The exception handler is able to correct the unaligned access,
+ at significant cost to performance.
+ - Some architectures raise processor exceptions when unaligned accesses
+ happen, but the exceptions do not contain enough information for the
+ unaligned access to be corrected.
+ - Some architectures are not capable of unaligned memory access, but will
+ silently perform a different memory access to the one that was requested,
+ resulting in a subtle code bug that is hard to detect!
+
+It should be obvious from the above that if your code causes unaligned
+memory accesses to happen, your code will not work correctly on certain
+platforms and will cause performance problems on others.
+
+
+Code that does not cause unaligned access
+=========================================
+
+At first, the concepts above may seem a little hard to relate to actual
+coding practice. After all, you don't have a great deal of control over
+memory addresses of certain variables, etc.
+
+Fortunately things are not too complex, as in most cases, the compiler
+ensures that things will work for you. For example, take the following
+structure:
+
+ struct foo {
+ u16 field1;
+ u32 field2;
+ u8 field3;
+ };
+
+Let us assume that an instance of the above structure resides in memory
+starting at address 0x10000. With a basic level of understanding, it would
+not be unreasonable to expect that accessing field2 would cause an unaligned
+access. You'd be expecting field2 to be located at offset 2 bytes into the
+structure, i.e. address 0x10002, but that address is not evenly divisible
+by 4 (remember, we're reading a 4 byte value here).
+
+Fortunately, the compiler understands the alignment constraints, so in the
+above case it would insert 2 bytes of padding in between field1 and field2.
+Therefore, for standard structure types you can always rely on the compiler
+to pad structures so that accesses to fields are suitably aligned (assuming
+you do not cast the field to a type of different length).
+
+Similarly, you can also rely on the compiler to align variables and function
+parameters to a naturally aligned scheme, based on the size of the type of
+the variable.
+
+At this point, it should be clear that accessing a single byte (u8 or char)
+will never cause an unaligned access, because all memory addresses are evenly
+divisible by one.
+
+On a related topic, with the above considerations in mind you may observe
+that you could reorder the fields in the structure in order to place fields
+where padding would otherwise be inserted, and hence reduce the overall
+resident memory size of structure instances. The optimal layout of the
+above example is:
+
+ struct foo {
+ u32 field2;
+ u16 field1;
+ u8 field3;
+ };
+
+For a natural alignment scheme, the compiler would only have to add a single
+byte of padding at the end of the structure. This padding is added in order
+to satisfy alignment constraints for arrays of these structures.
+
+Another point worth mentioning is the use of __attribute__((packed)) on a
+structure type. This GCC-specific attribute tells the compiler never to
+insert any padding within structures, useful when you want to use a C struct
+to represent some data that comes in a fixed arrangement 'off the wire'.
+
+You might be inclined to believe that usage of this attribute can easily
+lead to unaligned accesses when accessing fields that do not satisfy
+architectural alignment requirements. However, again, the compiler is aware
+of the alignment constraints and will generate extra instructions to perform
+the memory access in a way that does not cause unaligned access. Of course,
+the extra instructions obviously cause a loss in performance compared to the
+non-packed case, so the packed attribute should only be used when avoiding
+structure padding is of importance.
+
+
+Code that causes unaligned access
+=================================
+
+With the above in mind, let's move onto a real life example of a function
+that can cause an unaligned memory access. The following function taken
+from the Linux Kernel's include/linux/etherdevice.h is an optimized routine
+to compare two ethernet MAC addresses for equality.
+
+bool ether_addr_equal(const u8 *addr1, const u8 *addr2)
+{
+#ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
+ u32 fold = ((*(const u32 *)addr1) ^ (*(const u32 *)addr2)) |
+ ((*(const u16 *)(addr1 + 4)) ^ (*(const u16 *)(addr2 + 4)));
+
+ return fold == 0;
+#else
+ const u16 *a = (const u16 *)addr1;
+ const u16 *b = (const u16 *)addr2;
+ return ((a[0] ^ b[0]) | (a[1] ^ b[1]) | (a[2] ^ b[2])) != 0;
+#endif
+}
+
+In the above function, when the hardware has efficient unaligned access
+capability, there is no issue with this code. But when the hardware isn't
+able to access memory on arbitrary boundaries, the reference to a[0] causes
+2 bytes (16 bits) to be read from memory starting at address addr1.
+
+Think about what would happen if addr1 was an odd address such as 0x10003.
+(Hint: it'd be an unaligned access.)
+
+Despite the potential unaligned access problems with the above function, it
+is included in the kernel anyway but is understood to only work normally on
+16-bit-aligned addresses. It is up to the caller to ensure this alignment or
+not use this function at all. This alignment-unsafe function is still useful
+as it is a decent optimization for the cases when you can ensure alignment,
+which is true almost all of the time in ethernet networking context.
+
+
+Here is another example of some code that could cause unaligned accesses:
+ void myfunc(u8 *data, u32 value)
+ {
+ [...]
+ *((u32 *) data) = cpu_to_le32(value);
+ [...]
+ }
+
+This code will cause unaligned accesses every time the data parameter points
+to an address that is not evenly divisible by 4.
+
+In summary, the 2 main scenarios where you may run into unaligned access
+problems involve:
+ 1. Casting variables to types of different lengths
+ 2. Pointer arithmetic followed by access to at least 2 bytes of data
+
+
+Avoiding unaligned accesses
+===========================
+
+The easiest way to avoid unaligned access is to use the get_unaligned() and
+put_unaligned() macros provided by the <asm/unaligned.h> header file.
+
+Going back to an earlier example of code that potentially causes unaligned
+access:
+
+ void myfunc(u8 *data, u32 value)
+ {
+ [...]
+ *((u32 *) data) = cpu_to_le32(value);
+ [...]
+ }
+
+To avoid the unaligned memory access, you would rewrite it as follows:
+
+ void myfunc(u8 *data, u32 value)
+ {
+ [...]
+ value = cpu_to_le32(value);
+ put_unaligned(value, (u32 *) data);
+ [...]
+ }
+
+The get_unaligned() macro works similarly. Assuming 'data' is a pointer to
+memory and you wish to avoid unaligned access, its usage is as follows:
+
+ u32 value = get_unaligned((u32 *) data);
+
+These macros work for memory accesses of any length (not just 32 bits as
+in the examples above). Be aware that when compared to standard access of
+aligned memory, using these macros to access unaligned memory can be costly in
+terms of performance.
+
+If use of such macros is not convenient, another option is to use memcpy(),
+where the source or destination (or both) are of type u8* or unsigned char*.
+Due to the byte-wise nature of this operation, unaligned accesses are avoided.
+
+--
+In the Linux Kernel,
+Authors: Daniel Drake <dsd@gentoo.org>,
+ Johannes Berg <johannes@sipsolutions.net>
+With help from: Alan Cox, Avuton Olrich, Heikki Orsila, Jan Engelhardt,
+Kyle McMartin, Kyle Moffett, Randy Dunlap, Robert Hancock, Uli Kunitz,
+Vadim Lobanov
--- /dev/null
+Testing details-
+----------------
+
+This doc simply illustrated the testing details of qspi flash
+driver with Macronix M25L51235 flash device.
+
+The test includes
+- probing the flash device
+- erasing the flash device
+- Writing to flash
+- Reading the contents of the flash.
+
+Test Log
+--------
+
+Hit any key to stop autoboot: 0
+U-Boot# sf probe 0
+SF: Detected MX25L51235F with page size 256 Bytes, erase size 64 KiB, total 64 MiB, mapped at 30000000
+U-Boot# sf erase 0 0x80000
+SF: 524288 bytes @ 0x0 Erased: OK
+U-Boot# mw 81000000 0xdededede 0x40000
+U-Boot# sf write 81000000 0 0x40000
+SF: 262144 bytes @ 0x0 Written: OK
+U-Boot# sf read 82000000 0 0x40000
+SF: 262144 bytes @ 0x0 Read: OK
+U-Boot# md 0x82000000
+82000000: dededede dededede dededede dededede ................
+82000010: dededede dededede dededede dededede ................
+82000020: dededede dededede dededede dededede ................
+82000030: dededede dededede dededede dededede ................
+82000040: dededede dededede dededede dededede ................
+82000050: dededede dededede dededede dededede ................
+82000060: dededede dededede dededede dededede ................
+82000070: dededede dededede dededede dededede ................
+82000080: dededede dededede dededede dededede ................
+82000090: dededede dededede dededede dededede ................
+820000a0: dededede dededede dededede dededede ................
+820000b0: dededede dededede dededede dededede ................
+820000c0: dededede dededede dededede dededede ................
+820000d0: dededede dededede dededede dededede ................
+820000e0: dededede dededede dededede dededede ................
+820000f0: dededede dededede dededede dededede ................
+U-Boot# md 0x82010000
+82010000: dededede dededede dededede dededede ................
+82010010: dededede dededede dededede dededede ................
+82010020: dededede dededede dededede dededede ................
+82010030: dededede dededede dededede dededede ................
+82010040: dededede dededede dededede dededede ................
+82010050: dededede dededede dededede dededede ................
+82010060: dededede dededede dededede dededede ................
+82010070: dededede dededede dededede dededede ................
+82010080: dededede dededede dededede dededede ................
+82010090: dededede dededede dededede dededede ................
+820100a0: dededede dededede dededede dededede ................
+820100b0: dededede dededede dededede dededede ................
+820100c0: dededede dededede dededede dededede ................
+820100d0: dededede dededede dededede dededede ................
+820100e0: dededede dededede dededede dededede ................
+820100f0: dededede dededede dededede dededede ................
+U-Boot# md 0x82030000
+82030000: dededede dededede dededede dededede ................
+82030010: dededede dededede dededede dededede ................
+82030020: dededede dededede dededede dededede ................
+82030030: dededede dededede dededede dededede ................
+82030040: dededede dededede dededede dededede ................
+82030050: dededede dededede dededede dededede ................
+82030060: dededede dededede dededede dededede ................
+82030070: dededede dededede dededede dededede ................
+82030080: dededede dededede dededede dededede ................
+82030090: dededede dededede dededede dededede ................
+820300a0: dededede dededede dededede dededede ................
+820300b0: dededede dededede dededede dededede ................
+820300c0: dededede dededede dededede dededede ................
+820300d0: dededede dededede dededede dededede ................
+820300e0: dededede dededede dededede dededede ................
+820300f0: dededede dededede dededede dededede ................
Shared driver for indirect PCI bridges, several CONFIG macros - will
require significant cleanup.
- pci_ixp.c
- ---------
- Standard driver, specifies all read/write functions separately.
-
pci_sh4.c
---------
Shared init function for SH4 drivers, uses dword for read/write ops.
No support for CONFIG_SERIAL_MULTI. Simple conversion possible. This driver
might be removed in favor of serial_mxc.c .
- serial_ixp.c
- ------------
- No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
-
serial_ks8695.c
---------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
$(X86DIR)/sys.o \
$(X86DIR)/debug.o
-EXTRA_CFLAGS += -I. -I./include \
+ccflags-y := -I$(srctree)/$(src) -I$(srctree)/$(src)/include \
-D__PPC__ -D__BIG_ENDIAN__
-
-CFLAGS += $(EXTRA_CFLAGS)
-CPPFLAGS += $(EXTRA_CFLAGS)
#include <command.h>
#include <config.h>
#include <asm/byteorder.h>
+#include <asm/clock.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/portmux.h>
obj-$(CONFIG_BOOTCOUNT_AM33XX) += bootcount_davinci.o
obj-$(CONFIG_BOOTCOUNT_RAM) += bootcount_ram.o
obj-$(CONFIG_BOOTCOUNT_ENV) += bootcount_env.o
+obj-$(CONFIG_BOOTCOUNT_I2C) += bootcount_i2c.o
--- /dev/null
+/*
+ * (C) Copyright 2013
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <bootcount.h>
+#include <linux/compiler.h>
+#include <i2c.h>
+
+#define BC_MAGIC 0xbc
+
+void bootcount_store(ulong a)
+{
+ unsigned char buf[3];
+ int ret;
+
+ buf[0] = BC_MAGIC;
+ buf[1] = (a & 0xff);
+ ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR,
+ CONFIG_BOOTCOUNT_ALEN, buf, 2);
+ if (ret != 0)
+ puts("Error writing bootcount\n");
+}
+
+ulong bootcount_load(void)
+{
+ unsigned char buf[3];
+ int ret;
+
+ ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR,
+ CONFIG_BOOTCOUNT_ALEN, buf, 2);
+ if (ret != 0) {
+ puts("Error loading bootcount\n");
+ return 0;
+ }
+ if (buf[0] == BC_MAGIC)
+ return buf[1];
+
+ bootcount_store(0);
+
+ return 0;
+}
#include <fsl_ddr_sdram.h>
#include <asm/processor.h>
#include <fsl_immap.h>
+#include <fsl_ddr.h>
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
goto step2;
if (regs->ddr_eor)
- out_be32(&ddr->eor, regs->ddr_eor);
+ ddr_out32(&ddr->eor, regs->ddr_eor);
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
if (i == 0) {
- out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
- out_be32(&ddr->cs0_config, regs->cs[i].config);
- out_be32(&ddr->cs0_config_2, regs->cs[i].config_2);
+ ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds);
+ ddr_out32(&ddr->cs0_config, regs->cs[i].config);
+ ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2);
} else if (i == 1) {
- out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
- out_be32(&ddr->cs1_config, regs->cs[i].config);
- out_be32(&ddr->cs1_config_2, regs->cs[i].config_2);
+ ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds);
+ ddr_out32(&ddr->cs1_config, regs->cs[i].config);
+ ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2);
} else if (i == 2) {
- out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
- out_be32(&ddr->cs2_config, regs->cs[i].config);
- out_be32(&ddr->cs2_config_2, regs->cs[i].config_2);
+ ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds);
+ ddr_out32(&ddr->cs2_config, regs->cs[i].config);
+ ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2);
} else if (i == 3) {
- out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
- out_be32(&ddr->cs3_config, regs->cs[i].config);
- out_be32(&ddr->cs3_config_2, regs->cs[i].config_2);
+ ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds);
+ ddr_out32(&ddr->cs3_config, regs->cs[i].config);
+ ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2);
}
}
- out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
- out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
- out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
- out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
- out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
- out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
- out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
- out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
- out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
- out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
- out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
- out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
- out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
- out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
- out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
- out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
- out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
- out_be32(&ddr->init_addr, regs->ddr_init_addr);
- out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
-
- out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
- out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
- out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
- out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
+ ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3);
+ ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0);
+ ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1);
+ ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2);
+ ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
+ ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode);
+ ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
+ ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
+ ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
+ ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
+ ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
+ ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
+ ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
+ ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
+ ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
+ ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init);
+ ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
+ ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
+ ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
+
+ ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4);
+ ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5);
+ ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
+ ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
#ifndef CONFIG_SYS_FSL_DDR_EMU
/*
* Skip these two registers if running on emulator
*/
if (regs->ddr_wrlvl_cntl_2)
- out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
+ ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
if (regs->ddr_wrlvl_cntl_3)
- out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
+ ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
#endif
- out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
- out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
- out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
- out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1);
- out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
- out_be32(&ddr->err_disable, regs->err_disable);
- out_be32(&ddr->err_int_en, regs->err_int_en);
+ ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
+ ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
+ ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
+ ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
+ ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
+ ddr_out32(&ddr->err_disable, regs->err_disable);
+ ddr_out32(&ddr->err_int_en, regs->err_int_en);
for (i = 0; i < 32; i++) {
if (regs->debug[i]) {
debug("Write to debug_%d as %08x\n", i + 1,
regs->debug[i]);
- out_be32(&ddr->debug[i], regs->debug[i]);
+ ddr_out32(&ddr->debug[i], regs->debug[i]);
}
}
/* Set, but do not enable the memory */
temp_sdram_cfg = regs->ddr_sdram_cfg;
temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
- out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
+ ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg);
/*
* 500 painful micro-seconds must elapse between
asm volatile("dsb sy;isb");
/* Let the controller go */
- temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
- out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
+ temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
+ ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
asm volatile("dsb sy;isb");
total_gb_size_per_controller = 0;
debug("Need to wait up to %d * 10ms\n", timeout);
/* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
- while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
+ while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
(timeout >= 0)) {
udelay(10000); /* throttle polling rate */
timeout--;
u32 ver_major_minor_errata;
ddr = (void *)_DDR_ADDR;
- ver_major_minor_errata = (in_be32(&ddr->ip_rev1) & 0xFFFF) << 8;
- ver_major_minor_errata |= (in_be32(&ddr->ip_rev2) & 0xFF00) >> 8;
+ ver_major_minor_errata = (ddr_in32(&ddr->ip_rev1) & 0xFFFF) << 8;
+ ver_major_minor_errata |= (ddr_in32(&ddr->ip_rev2) & 0xFF00) >> 8;
return ver_major_minor_errata;
}
if (!popts->memctl_interleaving)
break;
switch (popts->memctl_interleaving_mode) {
+ case FSL_DDR_256B_INTERLEAVING:
case FSL_DDR_CACHE_LINE_INTERLEAVING:
case FSL_DDR_PAGE_INTERLEAVING:
case FSL_DDR_BANK_INTERLEAVING:
#include <fsl_ddr_sdram.h>
#include <fsl_ddr.h>
+/*
+ * CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view
+ * of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for
+ * all Power SoCs. But it could be different for ARM SoCs. For example,
+ * fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of
+ * 0x00_8000_0000 ~ 0x00_ffff_ffff
+ * 0x80_8000_0000 ~ 0xff_ffff_ffff
+ */
+#ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE
+#endif
+
#ifdef CONFIG_PPC
#include <asm/fsl_law.h>
debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]);
}
- current_mem_base = CONFIG_SYS_DDR_SDRAM_BASE;
+ current_mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
total_mem = 0;
if (pinfo->memctl_opts[0].memctl_interleaving) {
rank_density = pinfo->dimm_params[0][0].rank_density >>
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
if (pinfo->memctl_opts[i].memctl_interleaving) {
switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
+ case FSL_DDR_256B_INTERLEAVING:
case FSL_DDR_CACHE_LINE_INTERLEAVING:
case FSL_DDR_PAGE_INTERLEAVING:
case FSL_DDR_BANK_INTERLEAVING:
}
total_mem = 1 + (((unsigned long long)max_end << 24ULL) |
- 0xFFFFFFULL) - CONFIG_SYS_DDR_SDRAM_BASE;
+ 0xFFFFFFULL) - CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
}
return total_mem;
* If memory controller interleaving is enabled, then the data
* bus widths must be programmed identically for all memory controllers.
*
- * XXX: Attempt to set all controllers to the same chip select
+ * Attempt to set all controllers to the same chip select
* interleaving mode. It will do a best effort to get the
* requested ranks interleaved together such that the result
* should be a subset of the requested configuration.
+ *
+ * if CONFIG_SYS_FSL_DDR_INTLV_256B is defined, mandatory interleaving
+ * with 256 Byte is enabled.
*/
#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf))
+#ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
+ ;
+#else
goto done;
-
+#endif
if (pdimm[0].n_ranks == 0) {
printf("There is no rank on CS0 for controller %d.\n", ctrl_num);
popts->memctl_interleaving = 0;
goto done;
}
popts->memctl_interleaving = 1;
+#ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
+ popts->memctl_interleaving_mode = FSL_DDR_256B_INTERLEAVING;
+ popts->memctl_interleaving = 1;
+ debug("256 Byte interleaving\n");
+ goto done;
+#endif
/*
* test null first. if CONFIG_HWCONFIG is not defined
* hwconfig_arg_cmp returns non-zero
"Memory controller interleaving disabled.\n");
} else {
switch (check_intlv) {
+ case FSL_DDR_256B_INTERLEAVING:
case FSL_DDR_CACHE_LINE_INTERLEAVING:
case FSL_DDR_PAGE_INTERLEAVING:
case FSL_DDR_BANK_INTERLEAVING:
u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
#endif
#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
- uint32_t cs0_config = in_be32(&ddr->cs0_config);
+ uint32_t cs0_config = ddr_in32(&ddr->cs0_config);
#endif
- uint32_t sdram_cfg = in_be32(&ddr->sdram_cfg);
+ uint32_t sdram_cfg = ddr_in32(&ddr->sdram_cfg);
int cas_lat;
#if CONFIG_NUM_DDR_CONTROLLERS >= 2
if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR;
- sdram_cfg = in_be32(&ddr->sdram_cfg);
+ sdram_cfg = ddr_in32(&ddr->sdram_cfg);
}
#endif
#if CONFIG_NUM_DDR_CONTROLLERS >= 3
if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR;
- sdram_cfg = in_be32(&ddr->sdram_cfg);
+ sdram_cfg = ddr_in32(&ddr->sdram_cfg);
}
#endif
puts(" (DDR");
puts(", 64-bit");
/* Calculate CAS latency based on timing cfg values */
- cas_lat = ((in_be32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1;
- if ((in_be32(&ddr->timing_cfg_3) >> 12) & 1)
+ cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1;
+ if ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 1)
cas_lat += (8 << 1);
printf(", CL=%d", cas_lat >> 1);
if (cas_lat & 0x1)
puts(" DDR Controller Interleaving Mode: ");
switch ((cs0_config >> 24) & 0xf) {
+ case FSL_DDR_256B_INTERLEAVING:
+ puts("256B");
+ break;
case FSL_DDR_CACHE_LINE_INTERLEAVING:
puts("cache line");
break;
op == DFU_OP_READ ? "load" : "write",
dfu->data.mmc.dev, dfu->data.mmc.part,
(unsigned int) buf, dfu->name);
- if (op == DFU_OP_WRITE)
- sprintf(cmd_buf + strlen(cmd_buf), " %lx", *len);
break;
case DFU_FS_EXT4:
sprintf(cmd_buf, "ext4%s mmc %d:%d 0x%x /%s",
op == DFU_OP_READ ? "load" : "write",
dfu->data.mmc.dev, dfu->data.mmc.part,
(unsigned int) buf, dfu->name);
- if (op == DFU_OP_WRITE)
- sprintf(cmd_buf + strlen(cmd_buf), " %ld", *len);
break;
default:
printf("%s: Layout (%s) not (yet) supported!\n", __func__,
return -1;
}
+ if (op == DFU_OP_WRITE)
+ sprintf(cmd_buf + strlen(cmd_buf), " %lx", *len);
+
debug("%s: %s 0x%p\n", __func__, cmd_buf, cmd_buf);
ret = run_command(cmd_buf, 0);
if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) {
u32 *new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN);
+ /*
+ * This might be dangerous but permits to flash if
+ * ARCH_DMA_MINALIGN is greater than header size
+ */
+ if (new_buf > buf_start) {
+ debug("%s: Aligned buffer is after buffer start\n",
+ __func__);
+ new_buf -= ARCH_DMA_MINALIGN;
+ }
+
printf("%s: Align buffer at %x to %x(swap %d)\n", __func__,
(u32)buf_start, (u32)new_buf, swap);
obj-$(CONFIG_AT91_GPIO) += at91_gpio.o
obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o
obj-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o
+obj-$(CONFIG_KONA_GPIO) += kona_gpio.o
obj-$(CONFIG_MARVELL_GPIO) += mvgpio.o
obj-$(CONFIG_MARVELL_MFP) += mvmfp.o
obj-$(CONFIG_MXC_GPIO) += mxc_gpio.o
--- /dev/null
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sysmap.h>
+
+#define GPIO_BASE (void *)GPIO2_BASE_ADDR
+
+#define GPIO_PASSWD 0x00a5a501
+#define GPIO_PER_BANK 32
+#define GPIO_MAX_BANK_NUM 8
+
+#define GPIO_BANK(gpio) ((gpio) >> 5)
+#define GPIO_BITMASK(gpio) \
+ (1UL << ((gpio) & (GPIO_PER_BANK - 1)))
+
+#define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2))
+#define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2))
+#define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2))
+#define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2))
+#define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2))
+#define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2))
+#define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2))
+#define GPIO_CONTROL(bank) (0x00000100 + ((bank) << 2))
+#define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2))
+
+#define GPIO_GPPWR_OFFSET 0x00000520
+
+#define GPIO_GPCTR0_DBR_SHIFT 5
+#define GPIO_GPCTR0_DBR_MASK 0x000001e0
+
+#define GPIO_GPCTR0_ITR_SHIFT 3
+#define GPIO_GPCTR0_ITR_MASK 0x00000018
+#define GPIO_GPCTR0_ITR_CMD_RISING_EDGE 0x00000001
+#define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE 0x00000002
+#define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE 0x00000003
+
+#define GPIO_GPCTR0_IOTR_MASK 0x00000001
+#define GPIO_GPCTR0_IOTR_CMD_0UTPUT 0x00000000
+#define GPIO_GPCTR0_IOTR_CMD_INPUT 0x00000001
+
+int gpio_request(unsigned gpio, const char *label)
+{
+ unsigned int value, off;
+
+ writel(GPIO_PASSWD, GPIO_BASE + GPIO_GPPWR_OFFSET);
+ off = GPIO_PWD_STATUS(GPIO_BANK(gpio));
+ value = readl(GPIO_BASE + off) & ~GPIO_BITMASK(gpio);
+ writel(value, GPIO_BASE + off);
+
+ return 0;
+}
+
+int gpio_free(unsigned gpio)
+{
+ unsigned int value, off;
+
+ writel(GPIO_PASSWD, GPIO_BASE + GPIO_GPPWR_OFFSET);
+ off = GPIO_PWD_STATUS(GPIO_BANK(gpio));
+ value = readl(GPIO_BASE + off) | GPIO_BITMASK(gpio);
+ writel(value, GPIO_BASE + off);
+
+ return 0;
+}
+
+int gpio_direction_input(unsigned gpio)
+{
+ u32 val;
+
+ val = readl(GPIO_BASE + GPIO_CONTROL(gpio));
+ val &= ~GPIO_GPCTR0_IOTR_MASK;
+ val |= GPIO_GPCTR0_IOTR_CMD_INPUT;
+ writel(val, GPIO_BASE + GPIO_CONTROL(gpio));
+
+ return 0;
+}
+
+int gpio_direction_output(unsigned gpio, int value)
+{
+ int bank_id = GPIO_BANK(gpio);
+ int bitmask = GPIO_BITMASK(gpio);
+ u32 val, off;
+
+ val = readl(GPIO_BASE + GPIO_CONTROL(gpio));
+ val &= ~GPIO_GPCTR0_IOTR_MASK;
+ val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT;
+ writel(val, GPIO_BASE + GPIO_CONTROL(gpio));
+ off = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
+
+ val = readl(GPIO_BASE + off);
+ val |= bitmask;
+ writel(val, GPIO_BASE + off);
+
+ return 0;
+}
+
+int gpio_get_value(unsigned gpio)
+{
+ int bank_id = GPIO_BANK(gpio);
+ int bitmask = GPIO_BITMASK(gpio);
+ u32 val, off;
+
+ /* determine the GPIO pin direction */
+ val = readl(GPIO_BASE + GPIO_CONTROL(gpio));
+ val &= GPIO_GPCTR0_IOTR_MASK;
+
+ /* read the GPIO bank status */
+ off = (GPIO_GPCTR0_IOTR_CMD_INPUT == val) ?
+ GPIO_IN_STATUS(bank_id) : GPIO_OUT_STATUS(bank_id);
+ val = readl(GPIO_BASE + off);
+
+ /* return the specified bit status */
+ return !!(val & bitmask);
+}
+
+void gpio_set_value(unsigned gpio, int value)
+{
+ int bank_id = GPIO_BANK(gpio);
+ int bitmask = GPIO_BITMASK(gpio);
+ u32 val, off;
+
+ /* determine the GPIO pin direction */
+ val = readl(GPIO_BASE + GPIO_CONTROL(gpio));
+ val &= GPIO_GPCTR0_IOTR_MASK;
+
+ /* this function only applies to output pin */
+ if (GPIO_GPCTR0_IOTR_CMD_INPUT == val) {
+ printf("%s: Cannot set an input pin %d\n", __func__, gpio);
+ return;
+ }
+
+ off = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
+
+ val = readl(GPIO_BASE + off);
+ val |= bitmask;
+ writel(val, GPIO_BASE + off);
+}
#include <asm/io.h>
#include <asm/gpio.h>
+#define S5P_GPIO_GET_BANK(x) ((x >> S5P_GPIO_BANK_SHIFT) \
+ & S5P_GPIO_BANK_MASK)
+
+#define S5P_GPIO_GET_PIN(x) (x & S5P_GPIO_PIN_MASK)
+
#define CON_MASK(x) (0xf << ((x) << 2))
#define CON_SFR(x, v) ((v) << ((x) << 2))
struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio)
{
- int bank;
- unsigned g = gpio - s5p_gpio_part_max(gpio);
+ unsigned bank = S5P_GPIO_GET_BANK(gpio);
+ unsigned base = s5p_gpio_base(gpio);
- bank = g / GPIO_PER_BANK;
- bank *= sizeof(struct s5p_gpio_bank);
- return (struct s5p_gpio_bank *) (s5p_gpio_base(gpio) + bank);
+ return (struct s5p_gpio_bank *)(base + bank);
}
int s5p_gpio_get_pin(unsigned gpio)
{
- return gpio % GPIO_PER_BANK;
+ return S5P_GPIO_GET_PIN(gpio);
}
/* Common GPIO API */
# SPDX-License-Identifier: GPL-2.0+
#
-#CFLAGS += -DDEBUG
+#ccflags-y += -DDEBUG
obj-$(CONFIG_DTT_ADM1021) += adm1021.o
obj-$(CONFIG_DTT_ADT7460) += adt7460.o
obj-$(CONFIG_SYS_I2C) += i2c_core.o
obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
+obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o
obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
obj-$(CONFIG_SYS_I2C_OMAP34XX) += omap24xx_i2c.o
--- /dev/null
+/*
+ * i2c.c - driver for ADI TWI/I2C
+ *
+ * Copyright (c) 2006-2013 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/clock.h>
+#include <asm/twi.h>
+#include <asm/io.h>
+
+/* Every register is 32bit aligned, but only 16bits in size */
+#define ureg(name) u16 name; u16 __pad_##name;
+struct twi_regs {
+ ureg(clkdiv);
+ ureg(control);
+ ureg(slave_ctl);
+ ureg(slave_stat);
+ ureg(slave_addr);
+ ureg(master_ctl);
+ ureg(master_stat);
+ ureg(master_addr);
+ ureg(int_stat);
+ ureg(int_mask);
+ ureg(fifo_ctl);
+ ureg(fifo_stat);
+ char __pad[0x50];
+ ureg(xmt_data8);
+ ureg(xmt_data16);
+ ureg(rcv_data8);
+ ureg(rcv_data16);
+};
+#undef ureg
+
+/* U-Boot I2C framework allows only one active device at a time. */
+#ifdef TWI_CLKDIV
+#define TWI0_CLKDIV TWI_CLKDIV
+#endif
+static struct twi_regs *twi = (void *)TWI0_CLKDIV;
+
+#ifdef DEBUG
+# define dmemset(s, c, n) memset(s, c, n)
+#else
+# define dmemset(s, c, n)
+#endif
+#define debugi(fmt, args...) \
+ debug( \
+ "MSTAT:0x%03x FSTAT:0x%x ISTAT:0x%02x\t%-20s:%-3i: " fmt "\n", \
+ twi->master_stat, twi->fifo_stat, twi->int_stat, \
+ __func__, __LINE__, ## args)
+
+#ifdef CONFIG_TWICLK_KHZ
+# error do not define CONFIG_TWICLK_KHZ ... use CONFIG_SYS_I2C_SPEED
+#endif
+
+/*
+ * The way speed is changed into duty often results in integer truncation
+ * with 50% duty, so we'll force rounding up to the next duty by adding 1
+ * to the max. In practice this will get us a speed of something like
+ * 385 KHz. The other limit is easy to handle as it is only 8 bits.
+ */
+#define I2C_SPEED_MAX 400000
+#define I2C_SPEED_TO_DUTY(speed) (5000000 / (speed))
+#define I2C_DUTY_MAX (I2C_SPEED_TO_DUTY(I2C_SPEED_MAX) + 1)
+#define I2C_DUTY_MIN 0xff /* 8 bit limited */
+#define SYS_I2C_DUTY I2C_SPEED_TO_DUTY(CONFIG_SYS_I2C_SPEED)
+/* Note: duty is inverse of speed, so the comparisons below are correct */
+#if SYS_I2C_DUTY < I2C_DUTY_MAX || SYS_I2C_DUTY > I2C_DUTY_MIN
+# error "The Blackfin I2C hardware can only operate 20KHz - 400KHz"
+#endif
+
+/* All transfers are described by this data structure */
+struct i2c_msg {
+ u8 flags;
+#define I2C_M_COMBO 0x4
+#define I2C_M_STOP 0x2
+#define I2C_M_READ 0x1
+ int len; /* msg length */
+ u8 *buf; /* pointer to msg data */
+ int alen; /* addr length */
+ u8 *abuf; /* addr buffer */
+};
+
+/* Allow msec timeout per ~byte transfer */
+#define I2C_TIMEOUT 10
+
+/**
+ * wait_for_completion - manage the actual i2c transfer
+ * @msg: the i2c msg
+ */
+static int wait_for_completion(struct i2c_msg *msg)
+{
+ u16 int_stat, ctl;
+ ulong timebase = get_timer(0);
+
+ do {
+ int_stat = readw(&twi->int_stat);
+
+ if (int_stat & XMTSERV) {
+ debugi("processing XMTSERV");
+ writew(XMTSERV, &twi->int_stat);
+ if (msg->alen) {
+ writew(*(msg->abuf++), &twi->xmt_data8);
+ --msg->alen;
+ } else if (!(msg->flags & I2C_M_COMBO) && msg->len) {
+ writew(*(msg->buf++), &twi->xmt_data8);
+ --msg->len;
+ } else {
+ ctl = readw(&twi->master_ctl);
+ if (msg->flags & I2C_M_COMBO)
+ writew(ctl | RSTART | MDIR,
+ &twi->master_ctl);
+ else
+ writew(ctl | STOP, &twi->master_ctl);
+ }
+ }
+ if (int_stat & RCVSERV) {
+ debugi("processing RCVSERV");
+ writew(RCVSERV, &twi->int_stat);
+ if (msg->len) {
+ *(msg->buf++) = readw(&twi->rcv_data8);
+ --msg->len;
+ } else if (msg->flags & I2C_M_STOP) {
+ ctl = readw(&twi->master_ctl);
+ writew(ctl | STOP, &twi->master_ctl);
+ }
+ }
+ if (int_stat & MERR) {
+ debugi("processing MERR");
+ writew(MERR, &twi->int_stat);
+ return msg->len;
+ }
+ if (int_stat & MCOMP) {
+ debugi("processing MCOMP");
+ writew(MCOMP, &twi->int_stat);
+ if (msg->flags & I2C_M_COMBO && msg->len) {
+ ctl = readw(&twi->master_ctl);
+ ctl = (ctl & ~RSTART) |
+ (min(msg->len, 0xff) << 6) | MEN | MDIR;
+ writew(ctl, &twi->master_ctl);
+ } else
+ break;
+ }
+
+ /* If we were able to do something, reset timeout */
+ if (int_stat)
+ timebase = get_timer(0);
+
+ } while (get_timer(timebase) < I2C_TIMEOUT);
+
+ return msg->len;
+}
+
+/**
+ * i2c_transfer - setup an i2c transfer
+ * @return: 0 if things worked, non-0 if things failed
+ *
+ * Here we just get the i2c stuff all prepped and ready, and then tail off
+ * into wait_for_completion() for all the bits to go.
+ */
+static int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer,
+ int len, u8 flags)
+{
+ int ret;
+ u16 ctl;
+ uchar addr_buffer[] = {
+ (addr >> 0),
+ (addr >> 8),
+ (addr >> 16),
+ };
+ struct i2c_msg msg = {
+ .flags = flags | (len >= 0xff ? I2C_M_STOP : 0),
+ .buf = buffer,
+ .len = len,
+ .abuf = addr_buffer,
+ .alen = alen,
+ };
+
+ dmemset(buffer, 0xff, len);
+ debugi("chip=0x%x addr=0x%02x alen=%i buf[0]=0x%02x len=%i ",
+ chip, addr, alen, buffer[0], len);
+ debugi("flags=0x%02x[%s] ", flags,
+ (flags & I2C_M_READ ? "rd" : "wr"));
+
+ /* wait for things to settle */
+ while (readw(&twi->master_stat) & BUSBUSY)
+ if (ctrlc())
+ return 1;
+
+ /* Set Transmit device address */
+ writew(chip, &twi->master_addr);
+
+ /* Clear the FIFO before starting things */
+ writew(XMTFLUSH | RCVFLUSH, &twi->fifo_ctl);
+ writew(0, &twi->fifo_ctl);
+
+ /* prime the pump */
+ if (msg.alen) {
+ len = (msg.flags & I2C_M_COMBO) ? msg.alen : msg.alen + len;
+ debugi("first byte=0x%02x", *msg.abuf);
+ writew(*(msg.abuf++), &twi->xmt_data8);
+ --msg.alen;
+ } else if (!(msg.flags & I2C_M_READ) && msg.len) {
+ debugi("first byte=0x%02x", *msg.buf);
+ writew(*(msg.buf++), &twi->xmt_data8);
+ --msg.len;
+ }
+
+ /* clear int stat */
+ writew(-1, &twi->master_stat);
+ writew(-1, &twi->int_stat);
+ writew(0, &twi->int_mask);
+
+ /* Master enable */
+ ctl = readw(&twi->master_ctl);
+ ctl = (ctl & FAST) | (min(len, 0xff) << 6) | MEN |
+ ((msg.flags & I2C_M_READ) ? MDIR : 0);
+ writew(ctl, &twi->master_ctl);
+
+ /* process the rest */
+ ret = wait_for_completion(&msg);
+ debugi("ret=%d", ret);
+
+ if (ret) {
+ ctl = readw(&twi->master_ctl) & ~MEN;
+ writew(ctl, &twi->master_ctl);
+ ctl = readw(&twi->control) & ~TWI_ENA;
+ writew(ctl, &twi->control);
+ ctl = readw(&twi->control) | TWI_ENA;
+ writew(ctl, &twi->control);
+ }
+
+ return ret;
+}
+
+/**
+ * i2c_set_bus_speed - set i2c bus speed
+ * @speed: bus speed (in HZ)
+ */
+int i2c_set_bus_speed(unsigned int speed)
+{
+ u16 clkdiv = I2C_SPEED_TO_DUTY(speed);
+
+ /* Set TWI interface clock */
+ if (clkdiv < I2C_DUTY_MAX || clkdiv > I2C_DUTY_MIN)
+ return -1;
+ clkdiv = (clkdiv << 8) | (clkdiv & 0xff);
+ writew(clkdiv, &twi->clkdiv);
+
+ /* Don't turn it on */
+ writew(speed > 100000 ? FAST : 0, &twi->master_ctl);
+
+ return 0;
+}
+
+/**
+ * i2c_get_bus_speed - get i2c bus speed
+ * @speed: bus speed (in HZ)
+ */
+unsigned int i2c_get_bus_speed(void)
+{
+ u16 clkdiv = readw(&twi->clkdiv) & 0xff;
+ /* 10 MHz / (2 * CLKDIV) -> 5 MHz / CLKDIV */
+ return 5000000 / clkdiv;
+}
+
+/**
+ * i2c_init - initialize the i2c bus
+ * @speed: bus speed (in HZ)
+ * @slaveaddr: address of device in slave mode (0 - not slave)
+ *
+ * Slave mode isn't actually implemented. It'll stay that way until
+ * we get a real request for it.
+ */
+void i2c_init(int speed, int slaveaddr)
+{
+ u16 prescale = ((get_i2c_clk() / 1000 / 1000 + 5) / 10) & 0x7F;
+
+ /* Set TWI internal clock as 10MHz */
+ writew(prescale, &twi->control);
+
+ /* Set TWI interface clock as specified */
+ i2c_set_bus_speed(speed);
+
+ /* Enable it */
+ writew(TWI_ENA | prescale, &twi->control);
+
+ debugi("CONTROL:0x%04x CLKDIV:0x%04x", readw(&twi->control),
+ readw(&twi->clkdiv));
+
+#if CONFIG_SYS_I2C_SLAVE
+# error I2C slave support not tested/supported
+#endif
+}
+
+/**
+ * i2c_probe - test if a chip exists at a given i2c address
+ * @chip: i2c chip addr to search for
+ * @return: 0 if found, non-0 if not found
+ */
+int i2c_probe(uchar chip)
+{
+ u8 byte;
+ return i2c_read(chip, 0, 0, &byte, 1);
+}
+
+/**
+ * i2c_read - read data from an i2c device
+ * @chip: i2c chip addr
+ * @addr: memory (register) address in the chip
+ * @alen: byte size of address
+ * @buffer: buffer to store data read from chip
+ * @len: how many bytes to read
+ * @return: 0 on success, non-0 on failure
+ */
+int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
+{
+ return i2c_transfer(chip, addr, alen, buffer,
+ len, (alen ? I2C_M_COMBO : I2C_M_READ));
+}
+
+/**
+ * i2c_write - write data to an i2c device
+ * @chip: i2c chip addr
+ * @addr: memory (register) address in the chip
+ * @alen: byte size of address
+ * @buffer: buffer holding data to write to chip
+ * @len: how many bytes to write
+ * @return: 0 on success, non-0 on failure
+ */
+int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
+{
+ return i2c_transfer(chip, addr, alen, buffer, len, 0);
+}
+
+/**
+ * i2c_set_bus_num - change active I2C bus
+ * @bus: bus index, zero based
+ * @returns: 0 on success, non-0 on failure
+ */
+int i2c_set_bus_num(unsigned int bus)
+{
+ switch (bus) {
+#if CONFIG_SYS_MAX_I2C_BUS > 0
+ case 0:
+ twi = (void *)TWI0_CLKDIV;
+ return 0;
+#endif
+#if CONFIG_SYS_MAX_I2C_BUS > 1
+ case 1:
+ twi = (void *)TWI1_CLKDIV;
+ return 0;
+#endif
+#if CONFIG_SYS_MAX_I2C_BUS > 2
+ case 2:
+ twi = (void *)TWI2_CLKDIV;
+ return 0;
+#endif
+ default: return -1;
+ }
+}
+
+/**
+ * i2c_get_bus_num - returns index of active I2C bus
+ */
+unsigned int i2c_get_bus_num(void)
+{
+ switch ((unsigned long)twi) {
+#if CONFIG_SYS_MAX_I2C_BUS > 0
+ case TWI0_CLKDIV:
+ return 0;
+#endif
+#if CONFIG_SYS_MAX_I2C_BUS > 1
+ case TWI1_CLKDIV:
+ return 1;
+#endif
+#if CONFIG_SYS_MAX_I2C_BUS > 2
+ case TWI2_CLKDIV:
+ return 2;
+#endif
+ default: return -1;
+ }
+}
#include <i2c.h>
#include <asm/blackfin.h>
+#include <asm/clock.h>
#include <asm/mach-common/bits/twi.h>
/* Every register is 32bit aligned, but only 16bits in size */
*/
void i2c_init(int speed, int slaveaddr)
{
- uint8_t prescale = ((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F;
+ uint8_t prescale = ((get_i2c_clk() / 1000 / 1000 + 5) / 10) & 0x7F;
/* Set TWI internal clock as 10MHz */
twi->control = prescale;
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/hardware.h>
#include "designware_i2c.h"
#ifdef CONFIG_I2C_MULTI_BUS
return 0;
}
-/* check parameters for i2c_read and i2c_write */
-static int check_params(uint addr, int alen, uchar *buffer, int len)
-{
- if (buffer == NULL) {
- printf("Buffer is invalid\n");
- return 1;
- }
-
- if (alen > 1) {
- printf("addr len %d not supported\n", alen);
- return 1;
- }
-
- if (addr + len > 256) {
- printf("address out of range\n");
- return 1;
- }
-
- return 0;
-}
-
-static int i2c_xfer_init(uchar chip, uint addr)
+static int i2c_xfer_init(uchar chip, uint addr, int alen)
{
if (i2c_wait_for_bb())
return 1;
i2c_setaddress(chip);
- writel(addr, &i2c_regs_p->ic_cmd_data);
-
+ while (alen) {
+ alen--;
+ /* high byte address going out first */
+ writel((addr >> (alen * 8)) & 0xff,
+ &i2c_regs_p->ic_cmd_data);
+ }
return 0;
}
addr);
#endif
- if (check_params(addr, alen, buffer, len))
- return 1;
-
- if (i2c_xfer_init(chip, addr))
+ if (i2c_xfer_init(chip, addr, alen))
return 1;
start_time_rx = get_timer(0);
addr);
#endif
- if (check_params(addr, alen, buffer, len))
- return 1;
-
- if (i2c_xfer_init(chip, addr))
+ if (i2c_xfer_init(chip, addr, alen))
return 1;
start_time_tx = get_timer(0);
--- /dev/null
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include <i2c.h>
+
+/* Hardware register offsets and field defintions */
+#define CS_OFFSET 0x00000020
+#define CS_ACK_SHIFT 3
+#define CS_ACK_MASK 0x00000008
+#define CS_ACK_CMD_GEN_START 0x00000000
+#define CS_ACK_CMD_GEN_RESTART 0x00000001
+#define CS_CMD_SHIFT 1
+#define CS_CMD_CMD_NO_ACTION 0x00000000
+#define CS_CMD_CMD_START_RESTART 0x00000001
+#define CS_CMD_CMD_STOP 0x00000002
+#define CS_EN_SHIFT 0
+#define CS_EN_CMD_ENABLE_BSC 0x00000001
+
+#define TIM_OFFSET 0x00000024
+#define TIM_PRESCALE_SHIFT 6
+#define TIM_P_SHIFT 3
+#define TIM_NO_DIV_SHIFT 2
+#define TIM_DIV_SHIFT 0
+
+#define DAT_OFFSET 0x00000028
+
+#define TOUT_OFFSET 0x0000002c
+
+#define TXFCR_OFFSET 0x0000003c
+#define TXFCR_FIFO_FLUSH_MASK 0x00000080
+#define TXFCR_FIFO_EN_MASK 0x00000040
+
+#define IER_OFFSET 0x00000044
+#define IER_READ_COMPLETE_INT_MASK 0x00000010
+#define IER_I2C_INT_EN_MASK 0x00000008
+#define IER_FIFO_INT_EN_MASK 0x00000002
+#define IER_NOACK_EN_MASK 0x00000001
+
+#define ISR_OFFSET 0x00000048
+#define ISR_RESERVED_MASK 0xffffff60
+#define ISR_CMDBUSY_MASK 0x00000080
+#define ISR_READ_COMPLETE_MASK 0x00000010
+#define ISR_SES_DONE_MASK 0x00000008
+#define ISR_ERR_MASK 0x00000004
+#define ISR_TXFIFOEMPTY_MASK 0x00000002
+#define ISR_NOACK_MASK 0x00000001
+
+#define CLKEN_OFFSET 0x0000004c
+#define CLKEN_AUTOSENSE_OFF_MASK 0x00000080
+#define CLKEN_M_SHIFT 4
+#define CLKEN_N_SHIFT 1
+#define CLKEN_CLKEN_MASK 0x00000001
+
+#define FIFO_STATUS_OFFSET 0x00000054
+#define FIFO_STATUS_RXFIFO_EMPTY_MASK 0x00000004
+#define FIFO_STATUS_TXFIFO_EMPTY_MASK 0x00000010
+
+#define HSTIM_OFFSET 0x00000058
+#define HSTIM_HS_MODE_MASK 0x00008000
+#define HSTIM_HS_HOLD_SHIFT 10
+#define HSTIM_HS_HIGH_PHASE_SHIFT 5
+#define HSTIM_HS_SETUP_SHIFT 0
+
+#define PADCTL_OFFSET 0x0000005c
+#define PADCTL_PAD_OUT_EN_MASK 0x00000004
+
+#define RXFCR_OFFSET 0x00000068
+#define RXFCR_NACK_EN_SHIFT 7
+#define RXFCR_READ_COUNT_SHIFT 0
+#define RXFIFORDOUT_OFFSET 0x0000006c
+
+/* Locally used constants */
+#define MAX_RX_FIFO_SIZE 64U /* bytes */
+#define MAX_TX_FIFO_SIZE 64U /* bytes */
+
+#define I2C_TIMEOUT 100000 /* usecs */
+
+#define WAIT_INT_CHK 100 /* usecs */
+#if I2C_TIMEOUT % WAIT_INT_CHK
+#error I2C_TIMEOUT must be a multiple of WAIT_INT_CHK
+#endif
+
+/* Operations that can be commanded to the controller */
+enum bcm_kona_cmd_t {
+ BCM_CMD_NOACTION = 0,
+ BCM_CMD_START,
+ BCM_CMD_RESTART,
+ BCM_CMD_STOP,
+};
+
+enum bus_speed_index {
+ BCM_SPD_100K = 0,
+ BCM_SPD_400K,
+ BCM_SPD_1MHZ,
+};
+
+/* Internal divider settings for standard mode, fast mode and fast mode plus */
+struct bus_speed_cfg {
+ uint8_t time_m; /* Number of cycles for setup time */
+ uint8_t time_n; /* Number of cycles for hold time */
+ uint8_t prescale; /* Prescale divider */
+ uint8_t time_p; /* Timing coefficient */
+ uint8_t no_div; /* Disable clock divider */
+ uint8_t time_div; /* Post-prescale divider */
+};
+
+static const struct bus_speed_cfg std_cfg_table[] = {
+ [BCM_SPD_100K] = {0x01, 0x01, 0x03, 0x06, 0x00, 0x02},
+ [BCM_SPD_400K] = {0x05, 0x01, 0x03, 0x05, 0x01, 0x02},
+ [BCM_SPD_1MHZ] = {0x01, 0x01, 0x03, 0x01, 0x01, 0x03},
+};
+
+struct bcm_kona_i2c_dev {
+ void *base;
+ uint speed;
+ const struct bus_speed_cfg *std_cfg;
+};
+
+/* Keep these two defines in sync */
+#define DEF_SPD 100000
+#define DEF_SPD_ENUM BCM_SPD_100K
+
+#define DEF_DEVICE(num) \
+{(void *)CONFIG_SYS_I2C_BASE##num, DEF_SPD, &std_cfg_table[DEF_SPD_ENUM]}
+
+static struct bcm_kona_i2c_dev g_i2c_devs[CONFIG_SYS_MAX_I2C_BUS] = {
+#ifdef CONFIG_SYS_I2C_BASE0
+ DEF_DEVICE(0),
+#endif
+#ifdef CONFIG_SYS_I2C_BASE1
+ DEF_DEVICE(1),
+#endif
+#ifdef CONFIG_SYS_I2C_BASE2
+ DEF_DEVICE(2),
+#endif
+#ifdef CONFIG_SYS_I2C_BASE3
+ DEF_DEVICE(3),
+#endif
+#ifdef CONFIG_SYS_I2C_BASE4
+ DEF_DEVICE(4),
+#endif
+#ifdef CONFIG_SYS_I2C_BASE5
+ DEF_DEVICE(5),
+#endif
+};
+
+#define I2C_M_TEN 0x0010 /* ten bit address */
+#define I2C_M_RD 0x0001 /* read data */
+#define I2C_M_NOSTART 0x4000 /* no restart between msgs */
+
+struct i2c_msg {
+ uint16_t addr;
+ uint16_t flags;
+ uint16_t len;
+ uint8_t *buf;
+};
+
+static void bcm_kona_i2c_send_cmd_to_ctrl(struct bcm_kona_i2c_dev *dev,
+ enum bcm_kona_cmd_t cmd)
+{
+ debug("%s, %d\n", __func__, cmd);
+
+ switch (cmd) {
+ case BCM_CMD_NOACTION:
+ writel((CS_CMD_CMD_NO_ACTION << CS_CMD_SHIFT) |
+ (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
+ dev->base + CS_OFFSET);
+ break;
+
+ case BCM_CMD_START:
+ writel((CS_ACK_CMD_GEN_START << CS_ACK_SHIFT) |
+ (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) |
+ (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
+ dev->base + CS_OFFSET);
+ break;
+
+ case BCM_CMD_RESTART:
+ writel((CS_ACK_CMD_GEN_RESTART << CS_ACK_SHIFT) |
+ (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) |
+ (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
+ dev->base + CS_OFFSET);
+ break;
+
+ case BCM_CMD_STOP:
+ writel((CS_CMD_CMD_STOP << CS_CMD_SHIFT) |
+ (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
+ dev->base + CS_OFFSET);
+ break;
+
+ default:
+ printf("Unknown command %d\n", cmd);
+ }
+}
+
+static void bcm_kona_i2c_enable_clock(struct bcm_kona_i2c_dev *dev)
+{
+ writel(readl(dev->base + CLKEN_OFFSET) | CLKEN_CLKEN_MASK,
+ dev->base + CLKEN_OFFSET);
+}
+
+static void bcm_kona_i2c_disable_clock(struct bcm_kona_i2c_dev *dev)
+{
+ writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_CLKEN_MASK,
+ dev->base + CLKEN_OFFSET);
+}
+
+/* Wait until at least one of the mask bit(s) are set */
+static unsigned long wait_for_int_timeout(struct bcm_kona_i2c_dev *dev,
+ unsigned long time_left,
+ uint32_t mask)
+{
+ uint32_t status;
+
+ while (time_left) {
+ status = readl(dev->base + ISR_OFFSET);
+
+ if ((status & ~ISR_RESERVED_MASK) == 0) {
+ debug("Bogus I2C interrupt 0x%x\n", status);
+ continue;
+ }
+
+ /* Must flush the TX FIFO when NAK detected */
+ if (status & ISR_NOACK_MASK)
+ writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK,
+ dev->base + TXFCR_OFFSET);
+
+ writel(status & ~ISR_RESERVED_MASK, dev->base + ISR_OFFSET);
+
+ if (status & mask) {
+ /* We are done since one of the mask bits are set */
+ return time_left;
+ }
+ udelay(WAIT_INT_CHK);
+ time_left -= WAIT_INT_CHK;
+ }
+ return 0;
+}
+
+/* Send command to I2C bus */
+static int bcm_kona_send_i2c_cmd(struct bcm_kona_i2c_dev *dev,
+ enum bcm_kona_cmd_t cmd)
+{
+ int rc = 0;
+ unsigned long time_left = I2C_TIMEOUT;
+
+ /* Send the command */
+ bcm_kona_i2c_send_cmd_to_ctrl(dev, cmd);
+
+ /* Wait for transaction to finish or timeout */
+ time_left = wait_for_int_timeout(dev, time_left, IER_I2C_INT_EN_MASK);
+
+ if (!time_left) {
+ printf("controller timed out\n");
+ rc = -ETIMEDOUT;
+ }
+
+ /* Clear command */
+ bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION);
+
+ return rc;
+}
+
+/* Read a single RX FIFO worth of data from the i2c bus */
+static int bcm_kona_i2c_read_fifo_single(struct bcm_kona_i2c_dev *dev,
+ uint8_t *buf, unsigned int len,
+ unsigned int last_byte_nak)
+{
+ unsigned long time_left = I2C_TIMEOUT;
+
+ /* Start the RX FIFO */
+ writel((last_byte_nak << RXFCR_NACK_EN_SHIFT) |
+ (len << RXFCR_READ_COUNT_SHIFT), dev->base + RXFCR_OFFSET);
+
+ /* Wait for FIFO read to complete */
+ time_left =
+ wait_for_int_timeout(dev, time_left, IER_READ_COMPLETE_INT_MASK);
+
+ if (!time_left) {
+ printf("RX FIFO time out\n");
+ return -EREMOTEIO;
+ }
+
+ /* Read data from FIFO */
+ for (; len > 0; len--, buf++)
+ *buf = readl(dev->base + RXFIFORDOUT_OFFSET);
+
+ return 0;
+}
+
+/* Read any amount of data using the RX FIFO from the i2c bus */
+static int bcm_kona_i2c_read_fifo(struct bcm_kona_i2c_dev *dev,
+ struct i2c_msg *msg)
+{
+ unsigned int bytes_to_read = MAX_RX_FIFO_SIZE;
+ unsigned int last_byte_nak = 0;
+ unsigned int bytes_read = 0;
+ int rc;
+
+ uint8_t *tmp_buf = msg->buf;
+
+ while (bytes_read < msg->len) {
+ if (msg->len - bytes_read <= MAX_RX_FIFO_SIZE) {
+ last_byte_nak = 1; /* NAK last byte of transfer */
+ bytes_to_read = msg->len - bytes_read;
+ }
+
+ rc = bcm_kona_i2c_read_fifo_single(dev, tmp_buf, bytes_to_read,
+ last_byte_nak);
+ if (rc < 0)
+ return -EREMOTEIO;
+
+ bytes_read += bytes_to_read;
+ tmp_buf += bytes_to_read;
+ }
+
+ return 0;
+}
+
+/* Write a single byte of data to the i2c bus */
+static int bcm_kona_i2c_write_byte(struct bcm_kona_i2c_dev *dev, uint8_t data,
+ unsigned int nak_expected)
+{
+ unsigned long time_left = I2C_TIMEOUT;
+ unsigned int nak_received;
+
+ /* Clear pending session done interrupt */
+ writel(ISR_SES_DONE_MASK, dev->base + ISR_OFFSET);
+
+ /* Send one byte of data */
+ writel(data, dev->base + DAT_OFFSET);
+
+ time_left = wait_for_int_timeout(dev, time_left, IER_I2C_INT_EN_MASK);
+
+ if (!time_left) {
+ debug("controller timed out\n");
+ return -ETIMEDOUT;
+ }
+
+ nak_received = readl(dev->base + CS_OFFSET) & CS_ACK_MASK ? 1 : 0;
+
+ if (nak_received ^ nak_expected) {
+ debug("unexpected NAK/ACK\n");
+ return -EREMOTEIO;
+ }
+
+ return 0;
+}
+
+/* Write a single TX FIFO worth of data to the i2c bus */
+static int bcm_kona_i2c_write_fifo_single(struct bcm_kona_i2c_dev *dev,
+ uint8_t *buf, unsigned int len)
+{
+ int k;
+ unsigned long time_left = I2C_TIMEOUT;
+ unsigned int fifo_status;
+
+ /* Write data into FIFO */
+ for (k = 0; k < len; k++)
+ writel(buf[k], (dev->base + DAT_OFFSET));
+
+ /* Wait for FIFO to empty */
+ do {
+ time_left =
+ wait_for_int_timeout(dev, time_left,
+ (IER_FIFO_INT_EN_MASK |
+ IER_NOACK_EN_MASK));
+ fifo_status = readl(dev->base + FIFO_STATUS_OFFSET);
+ } while (time_left && !(fifo_status & FIFO_STATUS_TXFIFO_EMPTY_MASK));
+
+ /* Check if there was a NAK */
+ if (readl(dev->base + CS_OFFSET) & CS_ACK_MASK) {
+ printf("unexpected NAK\n");
+ return -EREMOTEIO;
+ }
+
+ /* Check if a timeout occured */
+ if (!time_left) {
+ printf("completion timed out\n");
+ return -EREMOTEIO;
+ }
+
+ return 0;
+}
+
+/* Write any amount of data using TX FIFO to the i2c bus */
+static int bcm_kona_i2c_write_fifo(struct bcm_kona_i2c_dev *dev,
+ struct i2c_msg *msg)
+{
+ unsigned int bytes_to_write = MAX_TX_FIFO_SIZE;
+ unsigned int bytes_written = 0;
+ int rc;
+
+ uint8_t *tmp_buf = msg->buf;
+
+ while (bytes_written < msg->len) {
+ if (msg->len - bytes_written <= MAX_TX_FIFO_SIZE)
+ bytes_to_write = msg->len - bytes_written;
+
+ rc = bcm_kona_i2c_write_fifo_single(dev, tmp_buf,
+ bytes_to_write);
+ if (rc < 0)
+ return -EREMOTEIO;
+
+ bytes_written += bytes_to_write;
+ tmp_buf += bytes_to_write;
+ }
+
+ return 0;
+}
+
+/* Send i2c address */
+static int bcm_kona_i2c_do_addr(struct bcm_kona_i2c_dev *dev,
+ struct i2c_msg *msg)
+{
+ unsigned char addr;
+
+ if (msg->flags & I2C_M_TEN) {
+ /* First byte is 11110XX0 where XX is upper 2 bits */
+ addr = 0xf0 | ((msg->addr & 0x300) >> 7);
+ if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
+ return -EREMOTEIO;
+
+ /* Second byte is the remaining 8 bits */
+ addr = msg->addr & 0xff;
+ if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
+ return -EREMOTEIO;
+
+ if (msg->flags & I2C_M_RD) {
+ /* For read, send restart command */
+ if (bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART) < 0)
+ return -EREMOTEIO;
+
+ /* Then re-send the first byte with the read bit set */
+ addr = 0xf0 | ((msg->addr & 0x300) >> 7) | 0x01;
+ if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
+ return -EREMOTEIO;
+ }
+ } else {
+ addr = msg->addr << 1;
+
+ if (msg->flags & I2C_M_RD)
+ addr |= 1;
+
+ if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
+ return -EREMOTEIO;
+ }
+
+ return 0;
+}
+
+static void bcm_kona_i2c_enable_autosense(struct bcm_kona_i2c_dev *dev)
+{
+ writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_AUTOSENSE_OFF_MASK,
+ dev->base + CLKEN_OFFSET);
+}
+
+static void bcm_kona_i2c_config_timing(struct bcm_kona_i2c_dev *dev)
+{
+ writel(readl(dev->base + HSTIM_OFFSET) & ~HSTIM_HS_MODE_MASK,
+ dev->base + HSTIM_OFFSET);
+
+ writel((dev->std_cfg->prescale << TIM_PRESCALE_SHIFT) |
+ (dev->std_cfg->time_p << TIM_P_SHIFT) |
+ (dev->std_cfg->no_div << TIM_NO_DIV_SHIFT) |
+ (dev->std_cfg->time_div << TIM_DIV_SHIFT),
+ dev->base + TIM_OFFSET);
+
+ writel((dev->std_cfg->time_m << CLKEN_M_SHIFT) |
+ (dev->std_cfg->time_n << CLKEN_N_SHIFT) |
+ CLKEN_CLKEN_MASK, dev->base + CLKEN_OFFSET);
+}
+
+/* Master transfer function */
+static int bcm_kona_i2c_xfer(struct bcm_kona_i2c_dev *dev,
+ struct i2c_msg msgs[], int num)
+{
+ struct i2c_msg *pmsg;
+ int rc = 0;
+ int i;
+
+ /* Enable pad output */
+ writel(0, dev->base + PADCTL_OFFSET);
+
+ /* Enable internal clocks */
+ bcm_kona_i2c_enable_clock(dev);
+
+ /* Send start command */
+ rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_START);
+ if (rc < 0) {
+ printf("Start command failed rc = %d\n", rc);
+ goto xfer_disable_pad;
+ }
+
+ /* Loop through all messages */
+ for (i = 0; i < num; i++) {
+ pmsg = &msgs[i];
+
+ /* Send restart for subsequent messages */
+ if ((i != 0) && ((pmsg->flags & I2C_M_NOSTART) == 0)) {
+ rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART);
+ if (rc < 0) {
+ printf("restart cmd failed rc = %d\n", rc);
+ goto xfer_send_stop;
+ }
+ }
+
+ /* Send slave address */
+ if (!(pmsg->flags & I2C_M_NOSTART)) {
+ rc = bcm_kona_i2c_do_addr(dev, pmsg);
+ if (rc < 0) {
+ debug("NAK from addr %2.2x msg#%d rc = %d\n",
+ pmsg->addr, i, rc);
+ goto xfer_send_stop;
+ }
+ }
+
+ /* Perform data transfer */
+ if (pmsg->flags & I2C_M_RD) {
+ rc = bcm_kona_i2c_read_fifo(dev, pmsg);
+ if (rc < 0) {
+ printf("read failure\n");
+ goto xfer_send_stop;
+ }
+ } else {
+ rc = bcm_kona_i2c_write_fifo(dev, pmsg);
+ if (rc < 0) {
+ printf("write failure");
+ goto xfer_send_stop;
+ }
+ }
+ }
+
+ rc = num;
+
+xfer_send_stop:
+ /* Send a STOP command */
+ bcm_kona_send_i2c_cmd(dev, BCM_CMD_STOP);
+
+xfer_disable_pad:
+ /* Disable pad output */
+ writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);
+
+ /* Stop internal clock */
+ bcm_kona_i2c_disable_clock(dev);
+
+ return rc;
+}
+
+static uint bcm_kona_i2c_assign_bus_speed(struct bcm_kona_i2c_dev *dev,
+ uint speed)
+{
+ switch (speed) {
+ case 100000:
+ dev->std_cfg = &std_cfg_table[BCM_SPD_100K];
+ break;
+ case 400000:
+ dev->std_cfg = &std_cfg_table[BCM_SPD_400K];
+ break;
+ case 1000000:
+ dev->std_cfg = &std_cfg_table[BCM_SPD_1MHZ];
+ break;
+ default:
+ printf("%d hz bus speed not supported\n", speed);
+ return -EINVAL;
+ }
+ dev->speed = speed;
+ return 0;
+}
+
+static void bcm_kona_i2c_init(struct bcm_kona_i2c_dev *dev)
+{
+ /* Parse bus speed */
+ bcm_kona_i2c_assign_bus_speed(dev, dev->speed);
+
+ /* Enable internal clocks */
+ bcm_kona_i2c_enable_clock(dev);
+
+ /* Configure internal dividers */
+ bcm_kona_i2c_config_timing(dev);
+
+ /* Disable timeout */
+ writel(0, dev->base + TOUT_OFFSET);
+
+ /* Enable autosense */
+ bcm_kona_i2c_enable_autosense(dev);
+
+ /* Enable TX FIFO */
+ writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK,
+ dev->base + TXFCR_OFFSET);
+
+ /* Mask all interrupts */
+ writel(0, dev->base + IER_OFFSET);
+
+ /* Clear all pending interrupts */
+ writel(ISR_CMDBUSY_MASK |
+ ISR_READ_COMPLETE_MASK |
+ ISR_SES_DONE_MASK |
+ ISR_ERR_MASK |
+ ISR_TXFIFOEMPTY_MASK | ISR_NOACK_MASK, dev->base + ISR_OFFSET);
+
+ /* Enable the controller but leave it idle */
+ bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION);
+
+ /* Disable pad output */
+ writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);
+}
+
+/*
+ * uboot layer
+ */
+struct bcm_kona_i2c_dev *kona_get_dev(struct i2c_adapter *adap)
+{
+ return &g_i2c_devs[adap->hwadapnr];
+}
+
+static void kona_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
+{
+ struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
+
+ if (clk_bsc_enable(dev->base))
+ return;
+
+ bcm_kona_i2c_init(dev);
+}
+
+static int kona_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
+ int alen, uchar *buffer, int len)
+{
+ /* msg[0] writes the addr, msg[1] reads the data */
+ struct i2c_msg msg[2];
+ unsigned char msgbuf0[64];
+ struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
+
+ msg[0].addr = chip;
+ msg[0].flags = 0;
+ msg[0].len = 1;
+ msg[0].buf = msgbuf0; /* msgbuf0 contains incrementing reg addr */
+
+ msg[1].addr = chip;
+ msg[1].flags = I2C_M_RD;
+ /* msg[1].buf dest ptr increments each read */
+
+ msgbuf0[0] = (unsigned char)addr;
+ msg[1].buf = buffer;
+ msg[1].len = len;
+ if (bcm_kona_i2c_xfer(dev, msg, 2) < 0) {
+ /* Sending 2 i2c messages */
+ kona_i2c_init(adap, adap->speed, adap->slaveaddr);
+ debug("I2C read: I/O error\n");
+ return -EIO;
+ }
+ return 0;
+}
+
+static int kona_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
+ int alen, uchar *buffer, int len)
+{
+ struct i2c_msg msg[0];
+ unsigned char msgbuf0[64];
+ unsigned int i;
+ struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
+
+ msg[0].addr = chip;
+ msg[0].flags = 0;
+ msg[0].len = 2; /* addr byte plus data */
+ msg[0].buf = msgbuf0;
+
+ for (i = 0; i < len; i++) {
+ msgbuf0[0] = addr++;
+ msgbuf0[1] = buffer[i];
+ if (bcm_kona_i2c_xfer(dev, msg, 1) < 0) {
+ kona_i2c_init(adap, adap->speed, adap->slaveaddr);
+ debug("I2C write: I/O error\n");
+ return -EIO;
+ }
+ }
+ return 0;
+}
+
+static int kona_i2c_probe(struct i2c_adapter *adap, uchar chip)
+{
+ uchar tmp;
+
+ /*
+ * read addr 0x0 of the given chip.
+ */
+ return kona_i2c_read(adap, chip, 0x0, 1, &tmp, 1);
+}
+
+static uint kona_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
+{
+ struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
+ return bcm_kona_i2c_assign_bus_speed(dev, speed);
+}
+
+/*
+ * Register kona i2c adapters. Keep the order below so
+ * that the bus number matches the adapter number.
+ */
+#define DEF_ADAPTER(num) \
+U_BOOT_I2C_ADAP_COMPLETE(kona##num, kona_i2c_init, kona_i2c_probe, \
+ kona_i2c_read, kona_i2c_write, \
+ kona_i2c_set_bus_speed, DEF_SPD, 0x00, num)
+
+#ifdef CONFIG_SYS_I2C_BASE0
+ DEF_ADAPTER(0)
+#endif
+#ifdef CONFIG_SYS_I2C_BASE1
+ DEF_ADAPTER(1)
+#endif
+#ifdef CONFIG_SYS_I2C_BASE2
+ DEF_ADAPTER(2)
+#endif
+#ifdef CONFIG_SYS_I2C_BASE3
+ DEF_ADAPTER(3)
+#endif
+#ifdef CONFIG_SYS_I2C_BASE4
+ DEF_ADAPTER(4)
+#endif
+#ifdef CONFIG_SYS_I2C_BASE5
+ DEF_ADAPTER(5)
+#endif
writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set);
}
-static void mxs_i2c_write(uchar chip, uint addr, int alen,
+static int mxs_i2c_write(uchar chip, uint addr, int alen,
uchar *buf, int blen, int stop)
{
struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
- uint32_t data;
+ uint32_t data, tmp;
int i, remain, off;
+ int timeout = MXS_I2C_MAX_TIMEOUT;
if ((alen > 4) || (alen == 0)) {
debug("MXS I2C: Invalid address length\n");
- return;
+ return -EINVAL;
}
if (stop)
writel(data >> remain, &i2c_regs->hw_i2c_data);
writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set);
+
+ while (--timeout) {
+ tmp = readl(&i2c_regs->hw_i2c_queuestat);
+ if (tmp & I2C_QUEUESTAT_WR_QUEUE_EMPTY)
+ break;
+ }
+
+ if (!timeout) {
+ debug("MXS I2C: Failed transmitting data!\n");
+ return -EINVAL;
+ }
+
+ return 0;
}
static int mxs_i2c_wait_for_ack(void)
int ret;
int i;
- mxs_i2c_write(chip, addr, alen, NULL, 0, 0);
+ ret = mxs_i2c_write(chip, addr, alen, NULL, 0, 0);
+ if (ret) {
+ debug("MXS I2C: Failed writing address\n");
+ return ret;
+ }
+
ret = mxs_i2c_wait_for_ack();
if (ret) {
debug("MXS I2C: Failed writing address\n");
int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
{
int ret;
- mxs_i2c_write(chip, addr, alen, buffer, len, 1);
+ ret = mxs_i2c_write(chip, addr, alen, buffer, len, 1);
+ if (ret) {
+ debug("MXS I2C: Failed writing address\n");
+ return ret;
+ }
+
ret = mxs_i2c_wait_for_ack();
if (ret)
debug("MXS I2C: Failed writing address\n");
int i2c_probe(uchar chip)
{
int ret;
- mxs_i2c_write(chip, 0, 1, NULL, 0, 1);
- ret = mxs_i2c_wait_for_ack();
+ ret = mxs_i2c_write(chip, 0, 1, NULL, 0, 1);
+ if (!ret)
+ ret = mxs_i2c_wait_for_ack();
mxs_i2c_reset();
return ret;
}
* - Status functions now read irqstatus_raw as per TRM guidelines
* (except for OMAP243X and OMAP34XX).
* - Driver now supports up to I2C5 (OMAP5).
+ *
+ * Copyright (c) 2014 Hannes Petermaier <oe5hpm@oevsv.at>, B&R
+ * - Added support for set_speed
+ *
*/
#include <common.h>
static struct i2c *omap24_get_base(struct i2c_adapter *adap);
static u16 wait_for_event(struct i2c_adapter *adap);
static void flush_fifo(struct i2c_adapter *adap);
-
-static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
+static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed)
{
- struct i2c *i2c_base = omap24_get_base(adap);
- int psc, fsscll, fssclh;
- int hsscll = 0, hssclh = 0;
- u32 scll, sclh;
- int timeout = I2C_TIMEOUT;
+ unsigned int sampleclk, prescaler;
+ int fsscll, fssclh;
- /* Only handle standard, fast and high speeds */
- if ((speed != OMAP_I2C_STANDARD) &&
- (speed != OMAP_I2C_FAST_MODE) &&
- (speed != OMAP_I2C_HIGH_SPEED)) {
- printf("Error : I2C unsupported speed %d\n", speed);
- return;
- }
+ speed <<= 1;
+ prescaler = 0;
+ /*
+ * some divisors may cause a precission loss, but shouldn't
+ * be a big thing, because i2c_clk is then allready very slow.
+ */
+ while (prescaler <= 0xFF) {
+ sampleclk = I2C_IP_CLK / (prescaler+1);
- psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
- psc -= 1;
- if (psc < I2C_PSC_MIN) {
- printf("Error : I2C unsupported prescalar %d\n", psc);
- return;
+ fsscll = sampleclk / speed;
+ fssclh = fsscll;
+ fsscll -= I2C_FASTSPEED_SCLL_TRIM;
+ fssclh -= I2C_FASTSPEED_SCLH_TRIM;
+
+ if (((fsscll > 0) && (fssclh > 0)) &&
+ ((fsscll <= (255-I2C_FASTSPEED_SCLL_TRIM)) &&
+ (fssclh <= (255-I2C_FASTSPEED_SCLH_TRIM)))) {
+ if (pscl)
+ *pscl = fsscll;
+ if (psch)
+ *psch = fssclh;
+
+ return prescaler;
+ }
+ prescaler++;
}
+ return -1;
+}
+static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed)
+{
+ struct i2c *i2c_base = omap24_get_base(adap);
+ int psc, fsscll = 0, fssclh = 0;
+ int hsscll = 0, hssclh = 0;
+ u32 scll = 0, sclh = 0;
- if (speed == OMAP_I2C_HIGH_SPEED) {
+ if (speed >= OMAP_I2C_HIGH_SPEED) {
/* High speed */
+ psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
+ psc -= 1;
+ if (psc < I2C_PSC_MIN) {
+ printf("Error : I2C unsupported prescaler %d\n", psc);
+ return -1;
+ }
/* For first phase of HS mode */
- fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK /
- (2 * OMAP_I2C_FAST_MODE);
+ fsscll = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
+
+ fssclh = fsscll;
fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
if (((fsscll < 0) || (fssclh < 0)) ||
((fsscll > 255) || (fssclh > 255))) {
puts("Error : I2C initializing first phase clock\n");
- return;
+ return -1;
}
/* For second phase of HS mode */
if (((fsscll < 0) || (fssclh < 0)) ||
((fsscll > 255) || (fssclh > 255))) {
puts("Error : I2C initializing second phase clock\n");
- return;
+ return -1;
}
scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
} else {
/* Standard and fast speed */
- fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
-
- fsscll -= I2C_FASTSPEED_SCLL_TRIM;
- fssclh -= I2C_FASTSPEED_SCLH_TRIM;
- if (((fsscll < 0) || (fssclh < 0)) ||
- ((fsscll > 255) || (fssclh > 255))) {
+ psc = omap24_i2c_findpsc(&scll, &sclh, speed);
+ if (0 > psc) {
puts("Error : I2C initializing clock\n");
- return;
+ return -1;
}
-
- scll = (unsigned int)fsscll;
- sclh = (unsigned int)fssclh;
}
+ adap->speed = speed;
+ adap->waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */
+ writew(0, &i2c_base->con);
+ writew(psc, &i2c_base->psc);
+ writew(scll, &i2c_base->scll);
+ writew(sclh, &i2c_base->sclh);
+ writew(I2C_CON_EN, &i2c_base->con);
+ writew(0xFFFF, &i2c_base->stat); /* clear all pending status */
+
+ return 0;
+}
+static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
+{
+ struct i2c *i2c_base = omap24_get_base(adap);
+ int timeout = I2C_TIMEOUT;
+
if (readw(&i2c_base->con) & I2C_CON_EN) {
writew(0, &i2c_base->con);
udelay(50000);
udelay(1000);
}
- writew(0, &i2c_base->con);
- writew(psc, &i2c_base->psc);
- writew(scll, &i2c_base->scll);
- writew(sclh, &i2c_base->sclh);
+ if (0 != omap24_i2c_setspeed(adap, speed)) {
+ printf("ERROR: failed to setup I2C bus-speed!\n");
+ return;
+ }
/* own address */
writew(slaveadd, &i2c_base->oa);
- writew(I2C_CON_EN, &i2c_base->con);
+
#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
/*
* Have to enable interrupts for OMAP2/3, these IPs don't have
struct i2c *i2c_base = omap24_get_base(adap);
u16 stat;
- /* note: if you try and read data when its not there or ready
+ /*
+ * note: if you try and read data when its not there or ready
* you get a bus error
*/
while (1) {
/* Check for ACK (!NAK) */
if (!(status & I2C_STAT_NACK)) {
- res = 0; /* Device found */
- udelay(I2C_WAIT); /* Required by AM335X in SPL */
+ res = 0; /* Device found */
+ udelay(adap->waitdelay);/* Required by AM335X in SPL */
/* Abort transfer (force idle state) */
writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */
udelay(1000);
adap->hwadapnr, status);
goto rd_exit;
}
- if (status == 0 || status & I2C_STAT_NACK) {
+ if (status == 0 || (status & I2C_STAT_NACK)) {
i2c_error = 1;
printf("i2c_read: error waiting for addr ACK (status=0x%x)\n",
status);
adap->hwadapnr, status);
goto rd_exit;
}
- if (status == 0 || status & I2C_STAT_NACK) {
+ if (status == 0 || (status & I2C_STAT_NACK)) {
i2c_error = 1;
goto rd_exit;
}
int i;
u16 status;
int i2c_error = 0;
+ int timeout = I2C_TIMEOUT;
if (alen < 0) {
puts("I2C write: addr len < 0\n");
adap->hwadapnr, status);
goto wr_exit;
}
- if (status == 0 || status & I2C_STAT_NACK) {
+ if (status == 0 || (status & I2C_STAT_NACK)) {
i2c_error = 1;
printf("i2c_write: error waiting for addr ACK (status=0x%x)\n",
status);
/* Address phase is over, now write data */
for (i = 0; i < len; i++) {
status = wait_for_event(adap);
- if (status == 0 || status & I2C_STAT_NACK) {
+ if (status == 0 || (status & I2C_STAT_NACK)) {
i2c_error = 1;
printf("i2c_write: error waiting for data ACK (status=0x%x)\n",
status);
goto wr_exit;
}
}
+ /*
+ * poll ARDY bit for making sure that last byte really has been
+ * transferred on the bus.
+ */
+ do {
+ status = wait_for_event(adap);
+ } while (!(status & I2C_STAT_ARDY) && timeout--);
+ if (timeout <= 0)
+ printf("i2c_write: timed out writig last byte!\n");
wr_exit:
flush_fifo(adap);
I2C_STAT_BB) && timeout--) {
#endif
writew(stat, &i2c_base->stat);
- udelay(I2C_WAIT);
+ udelay(adap->waitdelay);
}
if (timeout <= 0) {
int timeout = I2C_TIMEOUT;
do {
- udelay(I2C_WAIT);
+ udelay(adap->waitdelay);
#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
status = readw(&i2c_base->stat);
#else
#endif
U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe,
- omap24_i2c_read, omap24_i2c_write, NULL,
+ omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
CONFIG_SYS_OMAP24_I2C_SPEED,
CONFIG_SYS_OMAP24_I2C_SLAVE,
0)
U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe,
- omap24_i2c_read, omap24_i2c_write, NULL,
+ omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
CONFIG_SYS_OMAP24_I2C_SPEED1,
CONFIG_SYS_OMAP24_I2C_SLAVE1,
1)
#include <asm/arch/gpio.h>
#endif
#endif
-#ifdef CONFIG_IXP425 /* only valid for IXP425 */
-#include <asm/arch/ixp425.h>
-#endif
#if defined(CONFIG_MPC852T) || defined(CONFIG_MPC866)
#include <asm/io.h>
#endif
#define ZYNQ_I2C_FIFO_DEPTH 16
#define ZYNQ_I2C_TRANSFERT_SIZE_MAX 255 /* Controller transfer limit */
-#if defined(CONFIG_ZYNQ_I2C0)
-# define ZYNQ_I2C_BASE ZYNQ_I2C_BASEADDR0
-#else
-# define ZYNQ_I2C_BASE ZYNQ_I2C_BASEADDR1
-#endif
-
-static struct zynq_i2c_registers *zynq_i2c =
- (struct zynq_i2c_registers *)ZYNQ_I2C_BASE;
+static struct zynq_i2c_registers *i2c_select(struct i2c_adapter *adap)
+{
+ return adap->hwadapnr ?
+ /* Zynq PS I2C1 */
+ (struct zynq_i2c_registers *)ZYNQ_I2C_BASEADDR1 :
+ /* Zynq PS I2C0 */
+ (struct zynq_i2c_registers *)ZYNQ_I2C_BASEADDR0;
+}
/* I2C init called by cmd_i2c when doing 'i2c reset'. */
static void zynq_i2c_init(struct i2c_adapter *adap, int requested_speed,
int slaveadd)
{
+ struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);
+
/* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */
writel((16 << ZYNQ_I2C_CONTROL_DIV_B_SHIFT) |
(2 << ZYNQ_I2C_CONTROL_DIV_A_SHIFT), &zynq_i2c->control);
}
#ifdef DEBUG
-static void zynq_i2c_debug_status(void)
+static void zynq_i2c_debug_status(struct zynq_i2c_registers *zynq_i2c)
{
int int_status;
int status;
#endif
/* Wait for an interrupt */
-static u32 zynq_i2c_wait(u32 mask)
+static u32 zynq_i2c_wait(struct zynq_i2c_registers *zynq_i2c, u32 mask)
{
int timeout, int_status;
break;
}
#ifdef DEBUG
- zynq_i2c_debug_status();
+ zynq_i2c_debug_status(zynq_i2c));
#endif
/* Clear interrupt status flags */
writel(int_status & mask, &zynq_i2c->interrupt_status);
*/
static int zynq_i2c_probe(struct i2c_adapter *adap, u8 dev)
{
+ struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);
+
/* Attempt to read a byte */
setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
ZYNQ_I2C_CONTROL_RW);
writel(dev, &zynq_i2c->address);
writel(1, &zynq_i2c->transfer_size);
- return (zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP |
+ return (zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP |
ZYNQ_I2C_INTERRUPT_NACK) &
ZYNQ_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT;
}
u32 status;
u32 i = 0;
u8 *cur_data = data;
+ struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);
/* Check the hardware can handle the requested bytes */
if ((length < 0) || (length > ZYNQ_I2C_TRANSFERT_SIZE_MAX))
* Temporarily disable restart (by clearing hold)
* It doesn't seem to work.
*/
- clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW |
- ZYNQ_I2C_CONTROL_HOLD);
+ clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
writel(0xFF, &zynq_i2c->interrupt_status);
- while (alen--)
- writel(addr >> (8*alen), &zynq_i2c->data);
- writel(dev, &zynq_i2c->address);
+ if (alen) {
+ clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW);
+ writel(dev, &zynq_i2c->address);
+ while (alen--)
+ writel(addr >> (8 * alen), &zynq_i2c->data);
- /* Wait for the address to be sent */
- if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) {
- /* Release the bus */
- clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
- return -ETIMEDOUT;
+ /* Wait for the address to be sent */
+ if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) {
+ /* Release the bus */
+ clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
+ return -ETIMEDOUT;
+ }
+ debug("Device acked address\n");
}
- debug("Device acked address\n");
setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
ZYNQ_I2C_CONTROL_RW);
/* Wait for data */
do {
- status = zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP |
+ status = zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP |
ZYNQ_I2C_INTERRUPT_DATA);
if (!status) {
/* Release the bus */
int alen, u8 *data, int length)
{
u8 *cur_data = data;
+ struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);
/* Write the register address */
setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
ZYNQ_I2C_CONTROL_HOLD);
clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW);
writel(0xFF, &zynq_i2c->interrupt_status);
- while (alen--)
- writel(addr >> (8*alen), &zynq_i2c->data);
- /* Start the tranfer */
writel(dev, &zynq_i2c->address);
- if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) {
- /* Release the bus */
- clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
- return -ETIMEDOUT;
+ if (alen) {
+ while (alen--)
+ writel(addr >> (8 * alen), &zynq_i2c->data);
+ /* Start the tranfer */
+ if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) {
+ /* Release the bus */
+ clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
+ return -ETIMEDOUT;
+ }
+ debug("Device acked address\n");
}
- debug("Device acked address\n");
while (length--) {
writel(*(cur_data++), &zynq_i2c->data);
if (readl(&zynq_i2c->transfer_size) == ZYNQ_I2C_FIFO_DEPTH) {
- if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) {
+ if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) {
/* Release the bus */
clrbits_le32(&zynq_i2c->control,
ZYNQ_I2C_CONTROL_HOLD);
/* All done... release the bus */
clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
/* Wait for the address and data to be sent */
- if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP))
+ if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP))
return -ETIMEDOUT;
return 0;
}
zynq_i2c_write, zynq_i2c_set_bus_speed,
CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE,
0)
+U_BOOT_I2C_ADAP_COMPLETE(zynq_1, zynq_i2c_init, zynq_i2c_probe, zynq_i2c_read,
+ zynq_i2c_write, zynq_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE,
+ 1)
obj-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o
obj-$(CONFIG_SDHCI) += sdhci.o
obj-$(CONFIG_BCM2835_SDHCI) += bcm2835_sdhci.o
+obj-$(CONFIG_KONA_SDHCI) += kona_sdhci.o
obj-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o
obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o
obj-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o
#include <asm/errno.h>
#include <asm/byteorder.h>
#include <asm/blackfin.h>
+#include <asm/clock.h>
#include <asm/portmux.h>
#include <asm/mach-common/bits/sdh.h>
#include <asm/mach-common/bits/dma.h>
* host->bus_hz should be set from user.
*/
if (host->get_mmc_clk)
- sclk = host->get_mmc_clk(host->dev_index);
+ sclk = host->get_mmc_clk(host);
else if (host->bus_hz)
sclk = host->bus_hz;
else {
dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val);
}
-unsigned int exynos_dwmci_get_clk(int dev_index)
+unsigned int exynos_dwmci_get_clk(struct dwmci_host *host)
{
- return get_mmc_clk(dev_index);
+ unsigned long sclk;
+ int8_t clk_div;
+
+ /*
+ * Since SDCLKIN is divided inside controller by the DIVRATIO
+ * value set in the CLKSEL register, we need to use the same output
+ * clock value to calculate the CLKDIV value.
+ * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1)
+ */
+ clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT)
+ & DWMCI_DIVRATIO_MASK) + 1;
+ sclk = get_mmc_clk(host->dev_index);
+
+ return sclk / clk_div;
}
static void exynos_dwmci_board_init(struct dwmci_host *host)
--- /dev/null
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <sdhci.h>
+#include <asm/errno.h>
+#include <asm/kona-common/clk.h>
+
+#define SDHCI_CORECTRL_OFFSET 0x00008000
+#define SDHCI_CORECTRL_EN 0x01
+#define SDHCI_CORECTRL_RESET 0x02
+
+#define SDHCI_CORESTAT_OFFSET 0x00008004
+#define SDHCI_CORESTAT_CD_SW 0x01
+
+#define SDHCI_COREIMR_OFFSET 0x00008008
+#define SDHCI_COREIMR_IP 0x01
+
+static int init_kona_mmc_core(struct sdhci_host *host)
+{
+ unsigned int mask;
+ unsigned int timeout;
+
+ if (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & SDHCI_RESET_ALL) {
+ printf("%s: sd host controller reset error\n", __func__);
+ return 1;
+ }
+
+ /* For kona a hardware reset before anything else. */
+ mask = sdhci_readl(host, SDHCI_CORECTRL_OFFSET) | SDHCI_CORECTRL_RESET;
+ sdhci_writel(host, mask, SDHCI_CORECTRL_OFFSET);
+
+ /* Wait max 100 ms */
+ timeout = 1000;
+ do {
+ if (timeout == 0) {
+ printf("%s: reset timeout error\n", __func__);
+ return 1;
+ }
+ timeout--;
+ udelay(100);
+ } while (0 ==
+ (sdhci_readl(host, SDHCI_CORECTRL_OFFSET) &
+ SDHCI_CORECTRL_RESET));
+
+ /* Clear the reset bit. */
+ mask = mask & ~SDHCI_CORECTRL_RESET;
+ sdhci_writel(host, mask, SDHCI_CORECTRL_OFFSET);
+
+ /* Enable AHB clock */
+ mask = sdhci_readl(host, SDHCI_CORECTRL_OFFSET);
+ sdhci_writel(host, mask | SDHCI_CORECTRL_EN, SDHCI_CORECTRL_OFFSET);
+
+ /* Enable interrupts */
+ sdhci_writel(host, SDHCI_COREIMR_IP, SDHCI_COREIMR_OFFSET);
+
+ /* Make sure Card is detected in controller */
+ mask = sdhci_readl(host, SDHCI_CORESTAT_OFFSET);
+ sdhci_writel(host, mask | SDHCI_CORESTAT_CD_SW, SDHCI_CORESTAT_OFFSET);
+
+ /* Wait max 100 ms */
+ timeout = 1000;
+ while (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
+ if (timeout == 0) {
+ printf("%s: CARD DETECT timeout error\n", __func__);
+ return 1;
+ }
+ timeout--;
+ udelay(100);
+ }
+ return 0;
+}
+
+int kona_sdhci_init(int dev_index, u32 min_clk, u32 quirks)
+{
+ int ret = 0;
+ u32 max_clk;
+ void *reg_base;
+ struct sdhci_host *host = NULL;
+
+ host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
+ if (!host) {
+ printf("%s: sdhci host malloc fail!\n", __func__);
+ return -ENOMEM;
+ }
+ switch (dev_index) {
+ case 0:
+ reg_base = (void *)CONFIG_SYS_SDIO_BASE0;
+ ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO0_MAX_CLK,
+ &max_clk);
+ break;
+ case 1:
+ reg_base = (void *)CONFIG_SYS_SDIO_BASE1;
+ ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO1_MAX_CLK,
+ &max_clk);
+ break;
+ case 2:
+ reg_base = (void *)CONFIG_SYS_SDIO_BASE2;
+ ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO2_MAX_CLK,
+ &max_clk);
+ break;
+ case 3:
+ reg_base = (void *)CONFIG_SYS_SDIO_BASE3;
+ ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO3_MAX_CLK,
+ &max_clk);
+ break;
+ default:
+ printf("%s: sdio dev index %d not supported\n",
+ __func__, dev_index);
+ ret = -EINVAL;
+ }
+ if (ret)
+ return ret;
+
+ host->name = "kona-sdhci";
+ host->ioaddr = reg_base;
+ host->quirks = quirks;
+ host->host_caps = MMC_MODE_HC;
+
+ if (init_kona_mmc_core(host))
+ return -EINVAL;
+
+ if (quirks & SDHCI_QUIRK_REG32_RW)
+ host->version = sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
+ else
+ host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
+
+ add_sdhci(host, max_clk, min_clk);
+ return ret;
+}
mmc->ocr = cmd.response[0];
mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
- mmc->rca = 0;
+ mmc->rca = 1;
return 0;
}
}
/*
- * This function shall form and send the commands to open / close the
- * boot partition specified by user.
- *
- * Input Parameters:
- * ack: 0x0 - No boot acknowledge sent (default)
- * 0x1 - Boot acknowledge sent during boot operation
- * part_num: User selects boot data that will be sent to master
- * 0x0 - Device not boot enabled (default)
- * 0x1 - Boot partition 1 enabled for boot
- * 0x2 - Boot partition 2 enabled for boot
- * access: User selects partitions to access
- * 0x0 : No access to boot partition (default)
- * 0x1 : R/W boot partition 1
- * 0x2 : R/W boot partition 2
- * 0x3 : R/W Replay Protected Memory Block (RPMB)
+ * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH
+ * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH
+ * and BOOT_MODE.
*
* Returns 0 on success.
*/
-int mmc_boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access)
+int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode)
{
int err;
- struct mmc_cmd cmd;
- /* Boot ack enable, boot partition enable , boot partition access */
- cmd.cmdidx = MMC_CMD_SWITCH;
- cmd.resp_type = MMC_RSP_R1b;
-
- cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
- (EXT_CSD_PART_CONF << 16) |
- ((EXT_CSD_BOOT_ACK(ack) |
- EXT_CSD_BOOT_PART_NUM(part_num) |
- EXT_CSD_PARTITION_ACCESS(access)) << 8);
+ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH,
+ EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) |
+ EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) |
+ EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width));
- err = mmc_send_cmd(mmc, &cmd, NULL);
- if (err) {
- if (access) {
- debug("mmc boot partition#%d open fail:Error1 = %d\n",
- part_num, err);
- } else {
- debug("mmc boot partition#%d close fail:Error = %d\n",
- part_num, err);
- }
+ if (err)
return err;
- }
+ return 0;
+}
- if (access) {
- /* 4bit transfer mode at booting time. */
- cmd.cmdidx = MMC_CMD_SWITCH;
- cmd.resp_type = MMC_RSP_R1b;
+/*
+ * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG)
+ * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and
+ * PARTITION_ACCESS.
+ *
+ * Returns 0 on success.
+ */
+int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access)
+{
+ int err;
- cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
- (EXT_CSD_BOOT_BUS_WIDTH << 16) |
- ((1 << 0) << 8);
+ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
+ EXT_CSD_BOOT_ACK(ack) |
+ EXT_CSD_BOOT_PART_NUM(part_num) |
+ EXT_CSD_PARTITION_ACCESS(access));
- err = mmc_send_cmd(mmc, &cmd, NULL);
- if (err) {
- debug("mmc boot partition#%d open fail:Error2 = %d\n",
- part_num, err);
- return err;
- }
- }
+ if (err)
+ return err;
return 0;
}
#endif
const void *blob = gd->fdt_blob;
debug("%s entry\n", __func__);
+ /* See if any Tegra124 MMC controllers are present */
+ count = fdtdec_find_aliases_for_id(blob, "sdhci",
+ COMPAT_NVIDIA_TEGRA124_SDMMC, node_list, MAX_HOSTS);
+ debug("%s: count of Tegra124 sdhci nodes is %d\n", __func__, count);
+ if (process_nodes(blob, node_list, count)) {
+ printf("%s: Error processing T30 mmc node(s)!\n", __func__);
+ return;
+ }
+
/* See if any Tegra30 MMC controllers are present */
count = fdtdec_find_aliases_for_id(blob, "sdhci",
COMPAT_NVIDIA_TEGRA30_SDMMC, node_list, MAX_HOSTS);
host->name = "zynq_sdhci";
host->ioaddr = (void *)regbase;
- host->quirks = SDHCI_QUIRK_NO_CD | SDHCI_QUIRK_WAIT_SEND_CMD;
+ host->quirks = SDHCI_QUIRK_NO_CD | SDHCI_QUIRK_WAIT_SEND_CMD |
+ SDHCI_QUIRK_BROKEN_R1B;
host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
host->host_caps = MMC_MODE_HC;
ctrl->page = page_addr;
/* Program ROW0/COL0 */
- out_be32(&ifc->ifc_nand.row0, page_addr);
- out_be32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);
+ ifc_out32(&ifc->ifc_nand.row0, page_addr);
+ ifc_out32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);
buf_num = page_addr & priv->bufnum_mask;
int i;
/* set the chip select for NAND Transaction */
- out_be32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
+ ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
/* start read/write seq */
- out_be32(&ifc->ifc_nand.nandseq_strt,
- IFC_NAND_SEQ_STRT_FIR_STRT);
+ ifc_out32(&ifc->ifc_nand.nandseq_strt,
+ IFC_NAND_SEQ_STRT_FIR_STRT);
/* wait for NAND Machine complete flag or timeout */
end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
while (end_tick > get_ticks()) {
- ctrl->status = in_be32(&ifc->ifc_nand.nand_evter_stat);
+ ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
if (ctrl->status & IFC_NAND_EVTER_STAT_OPC)
break;
}
- out_be32(&ifc->ifc_nand.nand_evter_stat, ctrl->status);
+ ifc_out32(&ifc->ifc_nand.nand_evter_stat, ctrl->status);
if (ctrl->status & IFC_NAND_EVTER_STAT_FTOER)
printf("%s: Flash Time Out Error\n", __func__);
int sector_end = sector + chip->ecc.steps - 1;
for (i = sector / 4; i <= sector_end / 4; i++)
- eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]);
+ eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]);
for (i = sector; i <= sector_end; i++) {
errors = check_read_ecc(mtd, ctrl, eccstat, i);
/* Program FIR/IFC_NAND_FCR0 for Small/Large page */
if (mtd->writesize > 512) {
- out_be32(&ifc->ifc_nand.nand_fir0,
- (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
- (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
- (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
- (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
- (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT));
- out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
-
- out_be32(&ifc->ifc_nand.nand_fcr0,
- (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
- (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
+ ifc_out32(&ifc->ifc_nand.nand_fir0,
+ (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+ (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
+ (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
+ (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
+ (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT));
+ ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
+
+ ifc_out32(&ifc->ifc_nand.nand_fcr0,
+ (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
+ (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
} else {
- out_be32(&ifc->ifc_nand.nand_fir0,
- (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
- (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
- (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
- (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT));
+ ifc_out32(&ifc->ifc_nand.nand_fir0,
+ (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+ (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
+ (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
+ (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT));
if (oob)
- out_be32(&ifc->ifc_nand.nand_fcr0,
- NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT);
+ ifc_out32(&ifc->ifc_nand.nand_fcr0,
+ NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT);
else
- out_be32(&ifc->ifc_nand.nand_fcr0,
- NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
+ ifc_out32(&ifc->ifc_nand.nand_fcr0,
+ NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
}
}
switch (command) {
/* READ0 read the entire buffer to use hardware ECC. */
case NAND_CMD_READ0: {
- out_be32(&ifc->ifc_nand.nand_fbcr, 0);
+ ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
set_addr(mtd, 0, page_addr, 0);
ctrl->read_bytes = mtd->writesize + mtd->oobsize;
/* READOOB reads only the OOB because no ECC is performed. */
case NAND_CMD_READOOB:
- out_be32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column);
+ ifc_out32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column);
set_addr(mtd, column, page_addr, 1);
ctrl->read_bytes = mtd->writesize + mtd->oobsize;
if (command == NAND_CMD_PARAM)
timing = IFC_FIR_OP_RBCD;
- out_be32(&ifc->ifc_nand.nand_fir0,
- (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
- (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
- (timing << IFC_NAND_FIR0_OP2_SHIFT));
- out_be32(&ifc->ifc_nand.nand_fcr0,
- command << IFC_NAND_FCR0_CMD0_SHIFT);
- out_be32(&ifc->ifc_nand.row3, column);
+ ifc_out32(&ifc->ifc_nand.nand_fir0,
+ (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+ (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
+ (timing << IFC_NAND_FIR0_OP2_SHIFT));
+ ifc_out32(&ifc->ifc_nand.nand_fcr0,
+ command << IFC_NAND_FCR0_CMD0_SHIFT);
+ ifc_out32(&ifc->ifc_nand.row3, column);
/*
* although currently it's 8 bytes for READID, we always read
* the maximum 256 bytes(for PARAM)
*/
- out_be32(&ifc->ifc_nand.nand_fbcr, 256);
+ ifc_out32(&ifc->ifc_nand.nand_fbcr, 256);
ctrl->read_bytes = 256;
set_addr(mtd, 0, 0, 0);
/* ERASE2 uses the block and page address from ERASE1 */
case NAND_CMD_ERASE2:
- out_be32(&ifc->ifc_nand.nand_fir0,
- (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
- (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
- (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT));
+ ifc_out32(&ifc->ifc_nand.nand_fir0,
+ (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+ (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
+ (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT));
- out_be32(&ifc->ifc_nand.nand_fcr0,
- (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
- (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT));
+ ifc_out32(&ifc->ifc_nand.nand_fcr0,
+ (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
+ (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT));
- out_be32(&ifc->ifc_nand.nand_fbcr, 0);
+ ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
ctrl->read_bytes = 0;
fsl_ifc_run_command(mtd);
return;
(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) |
(NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
- out_be32(&ifc->ifc_nand.nand_fir0,
- (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
- (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
- (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
- (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) |
- (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT));
- out_be32(&ifc->ifc_nand.nand_fir1,
- (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
- (IFC_FIR_OP_RDSTAT <<
+ ifc_out32(&ifc->ifc_nand.nand_fir0,
+ (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+ (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
+ (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
+ (IFC_FIR_OP_WBCD <<
+ IFC_NAND_FIR0_OP3_SHIFT) |
+ (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT));
+ ifc_out32(&ifc->ifc_nand.nand_fir1,
+ (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
+ (IFC_FIR_OP_RDSTAT <<
IFC_NAND_FIR1_OP6_SHIFT) |
- (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT));
+ (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT));
} else {
nand_fcr0 = ((NAND_CMD_PAGEPROG <<
IFC_NAND_FCR0_CMD1_SHIFT) |
(NAND_CMD_STATUS <<
IFC_NAND_FCR0_CMD3_SHIFT));
- out_be32(&ifc->ifc_nand.nand_fir0,
- (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
- (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
- (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
- (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
- (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT));
- out_be32(&ifc->ifc_nand.nand_fir1,
- (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
- (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
- (IFC_FIR_OP_RDSTAT <<
+ ifc_out32(&ifc->ifc_nand.nand_fir0,
+ (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+ (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
+ (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
+ (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
+ (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT));
+ ifc_out32(&ifc->ifc_nand.nand_fir1,
+ (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
+ (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
+ (IFC_FIR_OP_RDSTAT <<
IFC_NAND_FIR1_OP7_SHIFT) |
- (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT));
+ (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT));
if (column >= mtd->writesize)
nand_fcr0 |=
column -= mtd->writesize;
ctrl->oob = 1;
}
- out_be32(&ifc->ifc_nand.nand_fcr0, nand_fcr0);
+ ifc_out32(&ifc->ifc_nand.nand_fcr0, nand_fcr0);
set_addr(mtd, column, page_addr, ctrl->oob);
return;
}
/* PAGEPROG reuses all of the setup from SEQIN and adds the length */
case NAND_CMD_PAGEPROG:
if (ctrl->oob)
- out_be32(&ifc->ifc_nand.nand_fbcr,
- ctrl->index - ctrl->column);
+ ifc_out32(&ifc->ifc_nand.nand_fbcr,
+ ctrl->index - ctrl->column);
else
- out_be32(&ifc->ifc_nand.nand_fbcr, 0);
+ ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
fsl_ifc_run_command(mtd);
return;
case NAND_CMD_STATUS:
- out_be32(&ifc->ifc_nand.nand_fir0,
- (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
- (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT));
- out_be32(&ifc->ifc_nand.nand_fcr0,
- NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT);
- out_be32(&ifc->ifc_nand.nand_fbcr, 1);
+ ifc_out32(&ifc->ifc_nand.nand_fir0,
+ (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+ (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT));
+ ifc_out32(&ifc->ifc_nand.nand_fcr0,
+ NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT);
+ ifc_out32(&ifc->ifc_nand.nand_fbcr, 1);
set_addr(mtd, 0, 0, 0);
ctrl->read_bytes = 1;
return;
case NAND_CMD_RESET:
- out_be32(&ifc->ifc_nand.nand_fir0,
- IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT);
- out_be32(&ifc->ifc_nand.nand_fcr0,
- NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT);
+ ifc_out32(&ifc->ifc_nand.nand_fir0,
+ IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT);
+ ifc_out32(&ifc->ifc_nand.nand_fcr0,
+ NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT);
fsl_ifc_run_command(mtd);
return;
* next byte.
*/
if (ctrl->index < ctrl->read_bytes) {
- data = in_be16((uint16_t *)&ctrl->
- addr[ctrl->index]);
+ data = ifc_in16((uint16_t *)&ctrl->
+ addr[ctrl->index]);
ctrl->index += 2;
return (uint8_t)data;
}
return NAND_STATUS_FAIL;
/* Use READ_STATUS command, but wait for the device to be ready */
- out_be32(&ifc->ifc_nand.nand_fir0,
- (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
- (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT));
- out_be32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS <<
- IFC_NAND_FCR0_CMD0_SHIFT);
- out_be32(&ifc->ifc_nand.nand_fbcr, 1);
+ ifc_out32(&ifc->ifc_nand.nand_fir0,
+ (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+ (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT));
+ ifc_out32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS <<
+ IFC_NAND_FCR0_CMD0_SHIFT);
+ ifc_out32(&ifc->ifc_nand.nand_fbcr, 1);
set_addr(mtd, 0, 0, 0);
ctrl->read_bytes = 1;
if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
return NAND_STATUS_FAIL;
- nand_fsr = in_be32(&ifc->ifc_nand.nand_fsr);
+ nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
/* Chip sometimes reporting write protect even when it's not */
nand_fsr = nand_fsr | NAND_STATUS_WP;
ifc_ctrl->regs = IFC_BASE_ADDR;
/* clear event registers */
- out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_stat, ~0U);
- out_be32(&ifc_ctrl->regs->ifc_nand.pgrdcmpl_evt_stat, ~0U);
+ ifc_out32(&ifc_ctrl->regs->ifc_nand.nand_evter_stat, ~0U);
+ ifc_out32(&ifc_ctrl->regs->ifc_nand.pgrdcmpl_evt_stat, ~0U);
/* Enable error and event for any detected errors */
- out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_en,
- IFC_NAND_EVTER_EN_OPC_EN |
- IFC_NAND_EVTER_EN_PGRDCMPL_EN |
- IFC_NAND_EVTER_EN_FTOER_EN |
- IFC_NAND_EVTER_EN_WPER_EN);
+ ifc_out32(&ifc_ctrl->regs->ifc_nand.nand_evter_en,
+ IFC_NAND_EVTER_EN_OPC_EN |
+ IFC_NAND_EVTER_EN_PGRDCMPL_EN |
+ IFC_NAND_EVTER_EN_FTOER_EN |
+ IFC_NAND_EVTER_EN_WPER_EN);
- out_be32(&ifc_ctrl->regs->ifc_nand.ncfgr, 0x0);
+ ifc_out32(&ifc_ctrl->regs->ifc_nand.ncfgr, 0x0);
}
static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
cs = ifc_ctrl->cs_nand >> IFC_NAND_CSEL_SHIFT;
/* Save CSOR and CSOR_ext */
- csor = in_be32(&ifc_ctrl->regs->csor_cs[cs].csor);
- csor_ext = in_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext);
+ csor = ifc_in32(&ifc_ctrl->regs->csor_cs[cs].csor);
+ csor_ext = ifc_in32(&ifc_ctrl->regs->csor_cs[cs].csor_ext);
/* chage PageSize 8K and SpareSize 1K*/
csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
- out_be32(&ifc_ctrl->regs->csor_cs[cs].csor, csor_8k);
- out_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, 0x0000400);
+ ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor_8k);
+ ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, 0x0000400);
/* READID */
- out_be32(&ifc->ifc_nand.nand_fir0,
- (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
- (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
- (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
- out_be32(&ifc->ifc_nand.nand_fcr0,
- NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT);
- out_be32(&ifc->ifc_nand.row3, 0x0);
+ ifc_out32(&ifc->ifc_nand.nand_fir0,
+ (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+ (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
+ (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
+ ifc_out32(&ifc->ifc_nand.nand_fcr0,
+ NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT);
+ ifc_out32(&ifc->ifc_nand.row3, 0x0);
- out_be32(&ifc->ifc_nand.nand_fbcr, 0x0);
+ ifc_out32(&ifc->ifc_nand.nand_fbcr, 0x0);
/* Program ROW0/COL0 */
- out_be32(&ifc->ifc_nand.row0, 0x0);
- out_be32(&ifc->ifc_nand.col0, 0x0);
+ ifc_out32(&ifc->ifc_nand.row0, 0x0);
+ ifc_out32(&ifc->ifc_nand.col0, 0x0);
/* set the chip select for NAND Transaction */
- out_be32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
+ ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
/* start read seq */
- out_be32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
+ ifc_out32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
/* wait for NAND Machine complete flag or timeout */
end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
while (end_tick > get_ticks()) {
- ifc_ctrl->status = in_be32(&ifc->ifc_nand.nand_evter_stat);
+ ifc_ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
if (ifc_ctrl->status & IFC_NAND_EVTER_STAT_OPC)
break;
}
- out_be32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status);
+ ifc_out32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status);
/* Restore CSOR and CSOR_ext */
- out_be32(&ifc_ctrl->regs->csor_cs[cs].csor, csor);
- out_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext);
+ ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor);
+ ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext);
}
static int fsl_ifc_chip_init(int devnum, u8 *addr)
for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
phys_addr_t phys_addr = virt_to_phys(addr);
- cspr = in_be32(&ifc_ctrl->regs->cspr_cs[priv->bank].cspr);
- csor = in_be32(&ifc_ctrl->regs->csor_cs[priv->bank].csor);
+ cspr = ifc_in32(&ifc_ctrl->regs->cspr_cs[priv->bank].cspr);
+ csor = ifc_in32(&ifc_ctrl->regs->csor_cs[priv->bank].csor);
if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND &&
(cspr & CSPR_BA) == CSPR_PHYS_ADDR(phys_addr)) {
nand->ecc.mode = NAND_ECC_SOFT;
}
- ver = in_be32(&ifc_ctrl->regs->ifc_rev);
+ ver = ifc_in32(&ifc_ctrl->regs->ifc_rev);
if (ver == FSL_IFC_V1_1_0)
fsl_ifc_sram_init();
bufnum_end = bufnum + bufperpage - 1;
do {
- status = in_be32(&ifc->ifc_nand.nand_evter_stat);
+ status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
} while (!(status & IFC_NAND_EVTER_STAT_OPC));
if (status & IFC_NAND_EVTER_STAT_FTOER) {
}
for (i = bufnum / 4; i <= bufnum_end / 4; i++)
- eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]);
+ eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]);
for (i = bufnum; i <= bufnum_end; i++) {
if (check_read_ecc(buf, eccstat, i, page_size))
break;
}
- out_be32(&ifc->ifc_nand.nand_evter_stat, status);
+ ifc_out32(&ifc->ifc_nand.nand_evter_stat, status);
}
static inline int bad_block(uchar *marker, int port_size)
blk_size = pages_per_blk * page_size;
/* Open Full SRAM mapping for spare are access */
- out_be32(&ifc->ifc_nand.ncfgr, 0x0);
+ ifc_out32(&ifc->ifc_nand.ncfgr, 0x0);
/* Clear Boot events */
- out_be32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff);
+ ifc_out32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff);
/* Program FIR/FCR for Large/Small page */
if (page_size > 512) {
- out_be32(&ifc->ifc_nand.nand_fir0,
- (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
- (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
- (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
- (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
- (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT));
- out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
-
- out_be32(&ifc->ifc_nand.nand_fcr0,
- (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
- (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
+ ifc_out32(&ifc->ifc_nand.nand_fir0,
+ (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+ (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
+ (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
+ (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
+ (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT));
+ ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
+
+ ifc_out32(&ifc->ifc_nand.nand_fcr0,
+ (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
+ (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
} else {
- out_be32(&ifc->ifc_nand.nand_fir0,
- (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
- (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
- (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
- (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT));
- out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
-
- out_be32(&ifc->ifc_nand.nand_fcr0,
- NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
+ ifc_out32(&ifc->ifc_nand.nand_fir0,
+ (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+ (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
+ (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
+ (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT));
+ ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
+
+ ifc_out32(&ifc->ifc_nand.nand_fcr0,
+ NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
}
/* Program FBCR = 0 for full page read */
- out_be32(&ifc->ifc_nand.nand_fbcr, 0);
+ ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
/* Read and copy u-boot on SDRAM from NAND device, In parallel
* check for Bad block if found skip it and read continue to
bufnum = pg_no & bufnum_mask;
sram_addr = bufnum * page_size * 2;
- out_be32(&ifc->ifc_nand.row0, pg_no);
- out_be32(&ifc->ifc_nand.col0, 0);
+ ifc_out32(&ifc->ifc_nand.row0, pg_no);
+ ifc_out32(&ifc->ifc_nand.col0, 0);
/* start read */
- out_be32(&ifc->ifc_nand.nandseq_strt,
- IFC_NAND_SEQ_STRT_FIR_STRT);
+ ifc_out32(&ifc->ifc_nand.nandseq_strt,
+ IFC_NAND_SEQ_STRT_FIR_STRT);
/* wait for read to complete */
nand_wait(&buf[sram_addr], bufnum, page_size);
#include <linux/mii.h>
#include <asm/blackfin.h>
+#include <asm/clock.h>
#include <asm/portmux.h>
#include <asm/mach-common/bits/dma.h>
#include <asm/mach-common/bits/emac.h>
*opmode = 0;
bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
+ bfin_write_EMAC_VLAN1(EMAC_VLANX_DEF_VAL);
+ bfin_write_EMAC_VLAN2(EMAC_VLANX_DEF_VAL);
/* Initialize the TX DMA channel registers */
bfin_write_DMA2_X_COUNT(0);
cpsw_ale_add_mcast(priv, NetBcastAddr, 1 << slave_port);
- priv->phy_mask |= 1 << slave->data->phy_id;
+ priv->phy_mask |= 1 << slave->data->phy_addr;
}
static struct cpdma_desc *cpdma_desc_alloc(struct cpsw_priv *priv)
SUPPORTED_1000baseT_Full);
phydev = phy_connect(priv->bus,
- CONFIG_PHY_ADDR,
+ slave->data->phy_addr,
dev,
slave->data->phy_if);
#include <asm/io.h>
#include "designware.h"
-static int configure_phy(struct eth_device *dev);
+#if !defined(CONFIG_PHYLIB)
+# error "DesignWare Ether MAC requires PHYLIB - missing CONFIG_PHYLIB"
+#endif
+
+static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
+{
+ struct eth_mac_regs *mac_p = bus->priv;
+ ulong start;
+ u16 miiaddr;
+ int timeout = CONFIG_MDIO_TIMEOUT;
+
+ miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
+ ((reg << MIIREGSHIFT) & MII_REGMSK);
+
+ writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
+
+ start = get_timer(0);
+ while (get_timer(start) < timeout) {
+ if (!(readl(&mac_p->miiaddr) & MII_BUSY))
+ return readl(&mac_p->miidata);
+ udelay(10);
+ };
+
+ return -1;
+}
+
+static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
+ u16 val)
+{
+ struct eth_mac_regs *mac_p = bus->priv;
+ ulong start;
+ u16 miiaddr;
+ int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
+
+ writel(val, &mac_p->miidata);
+ miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
+ ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
+
+ writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
+
+ start = get_timer(0);
+ while (get_timer(start) < timeout) {
+ if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
+ ret = 0;
+ break;
+ }
+ udelay(10);
+ };
+
+ return ret;
+}
+
+static int dw_mdio_init(char *name, struct eth_mac_regs *mac_regs_p)
+{
+ struct mii_dev *bus = mdio_alloc();
+
+ if (!bus) {
+ printf("Failed to allocate MDIO bus\n");
+ return -1;
+ }
+
+ bus->read = dw_mdio_read;
+ bus->write = dw_mdio_write;
+ sprintf(bus->name, name);
+
+ bus->priv = (void *)mac_regs_p;
+
+ return mdio_register(bus);
+}
static void tx_descs_init(struct eth_device *dev)
{
/* Correcting the last pointer of the chain */
desc_p->dmamac_next = &desc_table_p[0];
+ /* Flush all Tx buffer descriptors at once */
+ flush_dcache_range((unsigned int)priv->tx_mac_descrtable,
+ (unsigned int)priv->tx_mac_descrtable +
+ sizeof(priv->tx_mac_descrtable));
+
writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
+ priv->tx_currdescnum = 0;
}
static void rx_descs_init(struct eth_device *dev)
struct dmamacdescr *desc_p;
u32 idx;
+ /* Before passing buffers to GMAC we need to make sure zeros
+ * written there right after "priv" structure allocation were
+ * flushed into RAM.
+ * Otherwise there's a chance to get some of them flushed in RAM when
+ * GMAC is already pushing data to RAM via DMA. This way incoming from
+ * GMAC data will be corrupted. */
+ flush_dcache_range((unsigned int)rxbuffs, (unsigned int)rxbuffs +
+ RX_TOTAL_BUFSIZE);
+
for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
desc_p = &desc_table_p[idx];
desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE];
/* Correcting the last pointer of the chain */
desc_p->dmamac_next = &desc_table_p[0];
+ /* Flush all Rx buffer descriptors at once */
+ flush_dcache_range((unsigned int)priv->rx_mac_descrtable,
+ (unsigned int)priv->rx_mac_descrtable +
+ sizeof(priv->rx_mac_descrtable));
+
writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
+ priv->rx_currdescnum = 0;
}
-static void descs_init(struct eth_device *dev)
+static int dw_write_hwaddr(struct eth_device *dev)
{
- tx_descs_init(dev);
- rx_descs_init(dev);
+ struct dw_eth_dev *priv = dev->priv;
+ struct eth_mac_regs *mac_p = priv->mac_regs_p;
+ u32 macid_lo, macid_hi;
+ u8 *mac_id = &dev->enetaddr[0];
+
+ macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
+ (mac_id[3] << 24);
+ macid_hi = mac_id[4] + (mac_id[5] << 8);
+
+ writel(macid_hi, &mac_p->macaddr0hi);
+ writel(macid_lo, &mac_p->macaddr0lo);
+
+ return 0;
}
-static int mac_reset(struct eth_device *dev)
+static void dw_adjust_link(struct eth_mac_regs *mac_p,
+ struct phy_device *phydev)
{
- struct dw_eth_dev *priv = dev->priv;
- struct eth_mac_regs *mac_p = priv->mac_regs_p;
- struct eth_dma_regs *dma_p = priv->dma_regs_p;
+ u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN;
- ulong start;
- int timeout = CONFIG_MACRESET_TIMEOUT;
+ if (!phydev->link) {
+ printf("%s: No link.\n", phydev->dev->name);
+ return;
+ }
- writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
+ if (phydev->speed != 1000)
+ conf |= MII_PORTSELECT;
- if (priv->interface != PHY_INTERFACE_MODE_RGMII)
- writel(MII_PORTSELECT, &mac_p->conf);
+ if (phydev->speed == 100)
+ conf |= FES_100;
- start = get_timer(0);
- while (get_timer(start) < timeout) {
- if (!(readl(&dma_p->busmode) & DMAMAC_SRST))
- return 0;
+ if (phydev->duplex)
+ conf |= FULLDPLXMODE;
- /* Try again after 10usec */
- udelay(10);
- };
+ writel(conf, &mac_p->conf);
- return -1;
+ printf("Speed: %d, %s duplex%s\n", phydev->speed,
+ (phydev->duplex) ? "full" : "half",
+ (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
}
-static int dw_write_hwaddr(struct eth_device *dev)
+static void dw_eth_halt(struct eth_device *dev)
{
struct dw_eth_dev *priv = dev->priv;
struct eth_mac_regs *mac_p = priv->mac_regs_p;
- u32 macid_lo, macid_hi;
- u8 *mac_id = &dev->enetaddr[0];
-
- macid_lo = mac_id[0] + (mac_id[1] << 8) + \
- (mac_id[2] << 16) + (mac_id[3] << 24);
- macid_hi = mac_id[4] + (mac_id[5] << 8);
+ struct eth_dma_regs *dma_p = priv->dma_regs_p;
- writel(macid_hi, &mac_p->macaddr0hi);
- writel(macid_lo, &mac_p->macaddr0lo);
+ writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf);
+ writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode);
- return 0;
+ phy_shutdown(priv->phydev);
}
static int dw_eth_init(struct eth_device *dev, bd_t *bis)
struct dw_eth_dev *priv = dev->priv;
struct eth_mac_regs *mac_p = priv->mac_regs_p;
struct eth_dma_regs *dma_p = priv->dma_regs_p;
- u32 conf;
+ unsigned int start;
- if (priv->phy_configured != 1)
- configure_phy(dev);
+ writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
- /* Print link status only once */
- if (!priv->link_printed) {
- printf("ENET Speed is %d Mbps - %s duplex connection\n",
- priv->speed, (priv->duplex == HALF) ? "HALF" : "FULL");
- priv->link_printed = 1;
- }
+ start = get_timer(0);
+ while (readl(&dma_p->busmode) & DMAMAC_SRST) {
+ if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT)
+ return -1;
- /* Reset ethernet hardware */
- if (mac_reset(dev) < 0)
- return -1;
+ mdelay(100);
+ };
- /* Resore the HW MAC address as it has been lost during MAC reset */
+ /* Soft reset above clears HW address registers.
+ * So we have to set it here once again */
dw_write_hwaddr(dev);
- writel(FIXEDBURST | PRIORXTX_41 | BURST_16,
- &dma_p->busmode);
-
- writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD |
- TXSECONDFRAME, &dma_p->opmode);
+ rx_descs_init(dev);
+ tx_descs_init(dev);
- conf = FRAMEBURSTENABLE | DISABLERXOWN;
+ writel(FIXEDBURST | PRIORXTX_41 | BURST_16, &dma_p->busmode);
- if (priv->speed != 1000)
- conf |= MII_PORTSELECT;
+ writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
+ &dma_p->opmode);
- if ((priv->interface != PHY_INTERFACE_MODE_MII) &&
- (priv->interface != PHY_INTERFACE_MODE_GMII)) {
+ writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);
- if (priv->speed == 100)
- conf |= FES_100;
+ /* Start up the PHY */
+ if (phy_startup(priv->phydev)) {
+ printf("Could not initialize PHY %s\n",
+ priv->phydev->dev->name);
+ return -1;
}
- if (priv->duplex == FULL)
- conf |= FULLDPLXMODE;
-
- writel(conf, &mac_p->conf);
-
- descs_init(dev);
+ dw_adjust_link(mac_p, priv->phydev);
- /*
- * Start/Enable xfer at dma as well as mac level
- */
- writel(readl(&dma_p->opmode) | RXSTART, &dma_p->opmode);
- writel(readl(&dma_p->opmode) | TXSTART, &dma_p->opmode);
+ if (!priv->phydev->link)
+ return -1;
writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
u32 desc_num = priv->tx_currdescnum;
struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
+ /* Invalidate only "status" field for the following check */
+ invalidate_dcache_range((unsigned long)&desc_p->txrx_status,
+ (unsigned long)&desc_p->txrx_status +
+ sizeof(desc_p->txrx_status));
+
/* Check if the descriptor is owned by CPU */
if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
printf("CPU not owner of tx frame\n");
memcpy((void *)desc_p->dmamac_addr, packet, length);
+ /* Flush data to be sent */
+ flush_dcache_range((unsigned long)desc_p->dmamac_addr,
+ (unsigned long)desc_p->dmamac_addr + length);
+
#if defined(CONFIG_DW_ALTDESCRIPTOR)
desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \
desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
#endif
+ /* Flush modified buffer descriptor */
+ flush_dcache_range((unsigned long)desc_p,
+ (unsigned long)desc_p + sizeof(struct dmamacdescr));
+
/* Test the wrap-around condition. */
if (++desc_num >= CONFIG_TX_DESCR_NUM)
desc_num = 0;
static int dw_eth_recv(struct eth_device *dev)
{
struct dw_eth_dev *priv = dev->priv;
- u32 desc_num = priv->rx_currdescnum;
+ u32 status, desc_num = priv->rx_currdescnum;
struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
-
- u32 status = desc_p->txrx_status;
int length = 0;
+ /* Invalidate entire buffer descriptor */
+ invalidate_dcache_range((unsigned long)desc_p,
+ (unsigned long)desc_p +
+ sizeof(struct dmamacdescr));
+
+ status = desc_p->txrx_status;
+
/* Check if the owner is the CPU */
if (!(status & DESC_RXSTS_OWNBYDMA)) {
length = (status & DESC_RXSTS_FRMLENMSK) >> \
DESC_RXSTS_FRMLENSHFT;
+ /* Invalidate received data */
+ invalidate_dcache_range((unsigned long)desc_p->dmamac_addr,
+ (unsigned long)desc_p->dmamac_addr +
+ length);
+
NetReceive(desc_p->dmamac_addr, length);
/*
*/
desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
+ /* Flush only status field - others weren't changed */
+ flush_dcache_range((unsigned long)&desc_p->txrx_status,
+ (unsigned long)&desc_p->txrx_status +
+ sizeof(desc_p->txrx_status));
+
/* Test the wrap-around condition. */
if (++desc_num >= CONFIG_RX_DESCR_NUM)
desc_num = 0;
return length;
}
-static void dw_eth_halt(struct eth_device *dev)
-{
- struct dw_eth_dev *priv = dev->priv;
-
- mac_reset(dev);
- priv->tx_currdescnum = priv->rx_currdescnum = 0;
-}
-
-static int eth_mdio_read(struct eth_device *dev, u8 addr, u8 reg, u16 *val)
-{
- struct dw_eth_dev *priv = dev->priv;
- struct eth_mac_regs *mac_p = priv->mac_regs_p;
- ulong start;
- u32 miiaddr;
- int timeout = CONFIG_MDIO_TIMEOUT;
-
- miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \
- ((reg << MIIREGSHIFT) & MII_REGMSK);
-
- writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
-
- start = get_timer(0);
- while (get_timer(start) < timeout) {
- if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
- *val = readl(&mac_p->miidata);
- return 0;
- }
-
- /* Try again after 10usec */
- udelay(10);
- };
-
- return -1;
-}
-
-static int eth_mdio_write(struct eth_device *dev, u8 addr, u8 reg, u16 val)
+static int dw_phy_init(struct eth_device *dev)
{
struct dw_eth_dev *priv = dev->priv;
- struct eth_mac_regs *mac_p = priv->mac_regs_p;
- ulong start;
- u32 miiaddr;
- int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
- u16 value;
-
- writel(val, &mac_p->miidata);
- miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \
- ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
-
- writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
-
- start = get_timer(0);
- while (get_timer(start) < timeout) {
- if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
- ret = 0;
- break;
- }
+ struct phy_device *phydev;
+ int mask = 0xffffffff;
- /* Try again after 10usec */
- udelay(10);
- };
-
- /* Needed as a fix for ST-Phy */
- eth_mdio_read(dev, addr, reg, &value);
-
- return ret;
-}
-
-#if defined(CONFIG_DW_SEARCH_PHY)
-static int find_phy(struct eth_device *dev)
-{
- int phy_addr = 0;
- u16 ctrl, oldctrl;
-
- do {
- eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
- oldctrl = ctrl & BMCR_ANENABLE;
-
- ctrl ^= BMCR_ANENABLE;
- eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl);
- eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
- ctrl &= BMCR_ANENABLE;
-
- if (ctrl == oldctrl) {
- phy_addr++;
- } else {
- ctrl ^= BMCR_ANENABLE;
- eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl);
-
- return phy_addr;
- }
- } while (phy_addr < 32);
-
- return -1;
-}
+#ifdef CONFIG_PHY_ADDR
+ mask = 1 << CONFIG_PHY_ADDR;
#endif
-static int dw_reset_phy(struct eth_device *dev)
-{
- struct dw_eth_dev *priv = dev->priv;
- u16 ctrl;
- ulong start;
- int timeout = CONFIG_PHYRESET_TIMEOUT;
- u32 phy_addr = priv->address;
-
- eth_mdio_write(dev, phy_addr, MII_BMCR, BMCR_RESET);
-
- start = get_timer(0);
- while (get_timer(start) < timeout) {
- eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
- if (!(ctrl & BMCR_RESET))
- break;
-
- /* Try again after 10usec */
- udelay(10);
- };
-
- if (get_timer(start) >= CONFIG_PHYRESET_TIMEOUT)
+ phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
+ if (!phydev)
return -1;
-#ifdef CONFIG_PHY_RESET_DELAY
- udelay(CONFIG_PHY_RESET_DELAY);
-#endif
- return 0;
-}
+ phydev->supported &= PHY_GBIT_FEATURES;
+ phydev->advertising = phydev->supported;
-/*
- * Add weak default function for board specific PHY configuration
- */
-int __weak designware_board_phy_init(struct eth_device *dev, int phy_addr,
- int (*mii_write)(struct eth_device *, u8, u8, u16),
- int dw_reset_phy(struct eth_device *))
-{
- return 0;
-}
-
-static int configure_phy(struct eth_device *dev)
-{
- struct dw_eth_dev *priv = dev->priv;
- int phy_addr;
- u16 bmcr;
-#if defined(CONFIG_DW_AUTONEG)
- u16 bmsr;
- u32 timeout;
- ulong start;
-#endif
-
-#if defined(CONFIG_DW_SEARCH_PHY)
- phy_addr = find_phy(dev);
- if (phy_addr >= 0)
- priv->address = phy_addr;
- else
- return -1;
-#else
- phy_addr = priv->address;
-#endif
-
- /*
- * Some boards need board specific PHY initialization. This is
- * after the main driver init code but before the auto negotiation
- * is run.
- */
- if (designware_board_phy_init(dev, phy_addr,
- eth_mdio_write, dw_reset_phy) < 0)
- return -1;
-
- if (dw_reset_phy(dev) < 0)
- return -1;
-
-#if defined(CONFIG_DW_AUTONEG)
- /* Set Auto-Neg Advertisement capabilities to 10/100 half/full */
- eth_mdio_write(dev, phy_addr, MII_ADVERTISE, 0x1E1);
-
- bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
-#else
- bmcr = BMCR_SPEED100 | BMCR_FULLDPLX;
-
-#if defined(CONFIG_DW_SPEED10M)
- bmcr &= ~BMCR_SPEED100;
-#endif
-#if defined(CONFIG_DW_DUPLEXHALF)
- bmcr &= ~BMCR_FULLDPLX;
-#endif
-#endif
- if (eth_mdio_write(dev, phy_addr, MII_BMCR, bmcr) < 0)
- return -1;
-
- /* Read the phy status register and populate priv structure */
-#if defined(CONFIG_DW_AUTONEG)
- timeout = CONFIG_AUTONEG_TIMEOUT;
- start = get_timer(0);
- puts("Waiting for PHY auto negotiation to complete");
- while (get_timer(start) < timeout) {
- eth_mdio_read(dev, phy_addr, MII_BMSR, &bmsr);
- if (bmsr & BMSR_ANEGCOMPLETE) {
- priv->phy_configured = 1;
- break;
- }
+ priv->phydev = phydev;
+ phy_config(phydev);
- /* Print dot all 1s to show progress */
- if ((get_timer(start) % 1000) == 0)
- putc('.');
-
- /* Try again after 1msec */
- udelay(1000);
- };
-
- if (!(bmsr & BMSR_ANEGCOMPLETE))
- puts(" TIMEOUT!\n");
- else
- puts(" done\n");
-#else
- priv->phy_configured = 1;
-#endif
-
- priv->speed = miiphy_speed(dev->name, phy_addr);
- priv->duplex = miiphy_duplex(dev->name, phy_addr);
-
- return 0;
-}
-
-#if defined(CONFIG_MII)
-static int dw_mii_read(const char *devname, u8 addr, u8 reg, u16 *val)
-{
- struct eth_device *dev;
-
- dev = eth_get_dev_by_name(devname);
- if (dev)
- eth_mdio_read(dev, addr, reg, val);
-
- return 0;
-}
-
-static int dw_mii_write(const char *devname, u8 addr, u8 reg, u16 val)
-{
- struct eth_device *dev;
-
- dev = eth_get_dev_by_name(devname);
- if (dev)
- eth_mdio_write(dev, addr, reg, val);
-
- return 0;
+ return 1;
}
-#endif
-int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface)
+int designware_initialize(ulong base_addr, u32 interface)
{
struct eth_device *dev;
struct dw_eth_dev *priv;
memset(dev, 0, sizeof(struct eth_device));
memset(priv, 0, sizeof(struct dw_eth_dev));
- sprintf(dev->name, "mii%d", id);
+ sprintf(dev->name, "dwmac.%lx", base_addr);
dev->iobase = (int)base_addr;
dev->priv = priv;
- eth_getenv_enetaddr_by_index("eth", id, &dev->enetaddr[0]);
-
priv->dev = dev;
priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
DW_DMA_BASE_OFFSET);
- priv->address = phy_addr;
- priv->phy_configured = 0;
- priv->interface = interface;
dev->init = dw_eth_init;
dev->send = dw_eth_send;
eth_register(dev);
-#if defined(CONFIG_MII)
- miiphy_register(dev->name, dw_mii_read, dw_mii_write);
-#endif
- return 1;
+ priv->interface = interface;
+
+ dw_mdio_init(dev->name, priv->mac_regs_p);
+ priv->bus = miiphy_get_dev_by_name(dev->name);
+
+ return dw_phy_init(dev);
}
#define CONFIG_MACRESET_TIMEOUT (3 * CONFIG_SYS_HZ)
#define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
-#define CONFIG_PHYRESET_TIMEOUT (3 * CONFIG_SYS_HZ)
-#define CONFIG_AUTONEG_TIMEOUT (5 * CONFIG_SYS_HZ)
struct eth_mac_regs {
u32 conf; /* 0x00 */
#endif
struct dw_eth_dev {
- u32 address;
u32 interface;
- u32 speed;
- u32 duplex;
u32 tx_currdescnum;
u32 rx_currdescnum;
- u32 phy_configured;
- u32 link_printed;
struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
struct eth_dma_regs *dma_regs_p;
struct eth_device *dev;
+ struct phy_device *phydev;
+ struct mii_dev *bus;
};
-/* Speed specific definitions */
-#define SPEED_10M 1
-#define SPEED_100M 2
-#define SPEED_1000M 3
-
-/* Duplex mode specific definitions */
-#define HALF_DUPLEX 1
-#define FULL_DUPLEX 2
-
#endif
phy_interface_t fman_port_enet_if(enum fm_port port)
{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
+
+ /* handle RGMII first */
+ if ((port == FM1_DTSEC2) &&
+ ((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) ==
+ FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT)) {
+ if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
+ FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII)
+ return PHY_INTERFACE_MODE_RGMII;
+ else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
+ FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII)
+ return PHY_INTERFACE_MODE_MII;
+ else
+ return PHY_INTERFACE_MODE_NONE;
+ }
+
+ if ((port == FM1_DTSEC4) &&
+ ((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) ==
+ FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH)) {
+ if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
+ FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII)
+ return PHY_INTERFACE_MODE_RGMII;
+ else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
+ FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII)
+ return PHY_INTERFACE_MODE_MII;
+ else
+ return PHY_INTERFACE_MODE_NONE;
+ }
+
+ if (port == FM1_DTSEC5) {
+ if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
+ FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII)
+ return PHY_INTERFACE_MODE_RGMII;
+ else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
+ FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII)
+ return PHY_INTERFACE_MODE_MII;
+ else
+ return PHY_INTERFACE_MODE_NONE;
+ }
+
+ switch (port) {
+ case FM1_DTSEC1:
+ case FM1_DTSEC2:
+ if (is_serdes_configured(QSGMII_SW1_A + port - FM1_DTSEC1))
+ return PHY_INTERFACE_MODE_QSGMII;
+ case FM1_DTSEC3:
+ case FM1_DTSEC4:
+ case FM1_DTSEC5:
+ if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
+ return PHY_INTERFACE_MODE_SGMII;
+ break;
+ default:
+ return PHY_INTERFACE_MODE_NONE;
+ }
+
return PHY_INTERFACE_MODE_NONE;
}
+++ /dev/null
-/**
- * @file IxEthAcc.c
- *
- * @author Intel Corporation
- * @date 20-Feb-2001
- *
- * @brief This file contains the implementation of the IXP425 Ethernet Access Component
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-
-
-#include "IxEthAcc.h"
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
-#include "IxEthDB.h"
-#endif
-#include "IxFeatureCtrl.h"
-
-#include "IxEthAcc_p.h"
-#include "IxEthAccMac_p.h"
-#include "IxEthAccMii_p.h"
-
-/**
- * @addtogroup IxEthAcc
- *@{
- */
-
-
-/**
- * @brief System-wide information data strucure.
- *
- * @ingroup IxEthAccPri
- *
- */
-
-IxEthAccInfo ixEthAccDataInfo;
-extern PUBLIC IxEthAccMacState ixEthAccMacState[];
-extern PUBLIC IxOsalMutex ixEthAccControlInterfaceMutex;
-
-/**
- * @brief System-wide information
- *
- * @ingroup IxEthAccPri
- *
- */
-BOOL ixEthAccServiceInit = false;
-
-/* global filtering bit mask */
-PUBLIC UINT32 ixEthAccNewSrcMask;
-
-/**
- * @brief Per port information data strucure.
- *
- * @ingroup IxEthAccPri
- *
- */
-
-IxEthAccPortDataInfo ixEthAccPortData[IX_ETH_ACC_NUMBER_OF_PORTS];
-
-PUBLIC IxEthAccStatus ixEthAccInit()
-{
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
- /*
- * Initialize Control plane
- */
- if (ixEthDBInit() != IX_ETH_DB_SUCCESS)
- {
- IX_ETH_ACC_WARNING_LOG("ixEthAccInit: EthDB init failed\n", 0, 0, 0, 0, 0, 0);
-
- return IX_ETH_ACC_FAIL;
- }
-#endif
-
- if (IX_FEATURE_CTRL_SWCONFIG_ENABLED == ixFeatureCtrlSwConfigurationCheck (IX_FEATURECTRL_ETH_LEARNING))
- {
- ixEthAccNewSrcMask = (~0); /* want all the bits */
- }
- else
- {
- ixEthAccNewSrcMask = (~IX_ETHACC_NE_NEWSRCMASK); /* want all but the NewSrc bit */
- }
-
- /*
- * Initialize Data plane
- */
- if ( ixEthAccInitDataPlane() != IX_ETH_ACC_SUCCESS )
- {
- IX_ETH_ACC_WARNING_LOG("ixEthAccInit: data plane init failed\n", 0, 0, 0, 0, 0, 0);
-
- return IX_ETH_ACC_FAIL;
- }
-
-
- if ( ixEthAccQMgrQueuesConfig() != IX_ETH_ACC_SUCCESS )
- {
- IX_ETH_ACC_WARNING_LOG("ixEthAccInit: queue config failed\n", 0, 0, 0, 0, 0, 0);
-
- return IX_ETH_ACC_FAIL;
- }
-
- /*
- * Initialize MII
- */
- if ( ixEthAccMiiInit() != IX_ETH_ACC_SUCCESS )
- {
- IX_ETH_ACC_WARNING_LOG("ixEthAccInit: Mii init failed\n", 0, 0, 0, 0, 0, 0);
-
- return IX_ETH_ACC_FAIL;
- }
-
- /*
- * Initialize MAC I/O memory
- */
- if (ixEthAccMacMemInit() != IX_ETH_ACC_SUCCESS)
- {
- IX_ETH_ACC_WARNING_LOG("ixEthAccInit: Mac init failed\n", 0, 0, 0, 0, 0, 0);
-
- return IX_ETH_ACC_FAIL;
- }
-
- /*
- * Initialize control plane interface lock
- */
- if (ixOsalMutexInit(&ixEthAccControlInterfaceMutex) != IX_SUCCESS)
- {
- IX_ETH_ACC_WARNING_LOG("ixEthAccInit: Control plane interface lock initialization failed\n", 0, 0, 0, 0, 0, 0);
-
- return IX_ETH_ACC_FAIL;
- }
-
- /* initialiasation is complete */
- ixEthAccServiceInit = true;
-
- return IX_ETH_ACC_SUCCESS;
-
-}
-
-PUBLIC void ixEthAccUnload(void)
-{
- IxEthAccPortId portId;
-
- if ( IX_ETH_ACC_IS_SERVICE_INITIALIZED() )
- {
- /* check none of the port is still active */
- for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
- {
- if ( IX_ETH_IS_PORT_INITIALIZED(portId) )
- {
- if (ixEthAccMacState[portId].portDisableState == ACTIVE)
- {
- IX_ETH_ACC_WARNING_LOG("ixEthAccUnload: port %u still active, bail out\n", portId, 0, 0, 0, 0, 0);
- return;
- }
- }
- }
-
- /* unmap the memory areas */
- ixEthAccMiiUnload();
- ixEthAccMacUnload();
-
- /* set all ports as uninitialized */
- for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
- {
- ixEthAccPortData[portId].portInitialized = false;
- }
-
- /* uninitialize the service */
- ixEthAccServiceInit = false;
- }
-}
-
-PUBLIC IxEthAccStatus ixEthAccPortInit( IxEthAccPortId portId)
-{
-
- IxEthAccStatus ret=IX_ETH_ACC_SUCCESS;
-
- if ( ! IX_ETH_ACC_IS_SERVICE_INITIALIZED() )
- {
- return(IX_ETH_ACC_FAIL);
- }
-
- /*
- * Check for valid port
- */
-
- if ( ! IX_ETH_ACC_IS_PORT_VALID(portId) )
- {
- return (IX_ETH_ACC_INVALID_PORT);
- }
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot initialize Eth port.\n",(INT32) portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if ( IX_ETH_IS_PORT_INITIALIZED(portId) )
- {
- /* Already initialized */
- return(IX_ETH_ACC_FAIL);
- }
-
- if(ixEthAccMacInit(portId)!=IX_ETH_ACC_SUCCESS)
- {
- return IX_ETH_ACC_FAIL;
- }
-
- /*
- * Set the port init flag.
- */
-
- ixEthAccPortData[portId].portInitialized = true;
-
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
- /* init learning/filtering database structures for this port */
- ixEthDBPortInit(portId);
-#endif
-
- return(ret);
-}
-
-
+++ /dev/null
-/**
- * @file IxEthAccCommon.c
- *
- * @author Intel Corporation
- * @date 12-Feb-2002
- *
- * @brief This file contains the implementation common support routines for the component
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/*
- * Component header files
- */
-
-#include "IxOsal.h"
-#include "IxEthAcc.h"
-#include "IxEthDB.h"
-#include "IxNpeMh.h"
-#include "IxEthDBPortDefs.h"
-#include "IxFeatureCtrl.h"
-#include "IxEthAcc_p.h"
-#include "IxEthAccQueueAssign_p.h"
-
-#include "IxEthAccDataPlane_p.h"
-#include "IxEthAccMii_p.h"
-
-/**
- * @addtogroup IxEthAccPri
- *@{
- */
-
-extern IxEthAccInfo ixEthAccDataInfo;
-
-/**
- *
- * @brief Maximum number of RX queues set to be the maximum number
- * of traffic calsses.
- *
- */
-#define IX_ETHACC_MAX_RX_QUEUES \
- (IX_ETH_DB_QOS_TRAFFIC_CLASS_7_RX_QUEUE_PROPERTY \
- - IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY \
- + 1)
-
-/**
- *
- * @brief Maximum number of 128 entry RX queues
- *
- */
-#define IX_ETHACC_MAX_LARGE_RX_QUEUES 4
-
-/**
- *
- * @brief Data structure template for Default RX Queues
- *
- */
-IX_ETH_ACC_PRIVATE
-IxEthAccQregInfo ixEthAccQmgrRxDefaultTemplate =
- {
- IX_ETH_ACC_RX_FRAME_ETH_Q, /**< Queue ID */
- "Eth Rx Q",
- ixEthRxFrameQMCallback, /**< Functional callback */
- (IxQMgrCallbackId) 0, /**< Callback tag */
- IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */
- IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */
- true, /**< Enable Q notification at startup */
- IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE,/**< Q Condition to drive callback */
- IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */
- IX_QMGR_Q_WM_LEVEL1, /**< Q High water mark - needed by NPE */
- };
-
-/**
- *
- * @brief Data structure template for Small RX Queues
- *
- */
-IX_ETH_ACC_PRIVATE
-IxEthAccQregInfo ixEthAccQmgrRxSmallTemplate =
- {
- IX_ETH_ACC_RX_FRAME_ETH_Q, /**< Queue ID */
- "Eth Rx Q",
- ixEthRxFrameQMCallback, /**< Functional callback */
- (IxQMgrCallbackId) 0, /**< Callback tag */
- IX_QMGR_Q_SIZE64, /**< Allocate Smaller Q */
- IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */
- true, /**< Enable Q notification at startup */
- IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE,/**< Q Condition to drive callback */
- IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */
- IX_QMGR_Q_WM_LEVEL1, /**< Q High water mark - needed by NPE */
- };
-
-
-/**
- *
- * @brief Data structure used to register & initialize the Queues
- *
- */
-IX_ETH_ACC_PRIVATE
-IxEthAccQregInfo ixEthAccQmgrStaticInfo[]=
-{
- {
- IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q,
- "Eth Rx Fr Q 1",
- ixEthRxFreeQMCallback,
- (IxQMgrCallbackId) IX_ETH_PORT_1,
- IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */
- IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */
- false, /**< Disable Q notification at startup */
- IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q_SOURCE, /**< Q Condition to drive callback */
- IX_QMGR_Q_WM_LEVEL0, /***< Q Low water mark */
- IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */
- },
-
- {
- IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q,
- "Eth Rx Fr Q 2",
- ixEthRxFreeQMCallback,
- (IxQMgrCallbackId) IX_ETH_PORT_2,
- IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */
- IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */
- false, /**< Disable Q notification at startup */
- IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q_SOURCE, /**< Q Condition to drive callback */
- IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */
- IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */
- },
-#ifdef __ixp46X
- {
- IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q,
- "Eth Rx Fr Q 3",
- ixEthRxFreeQMCallback,
- (IxQMgrCallbackId) IX_ETH_PORT_3,
- IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */
- IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */
- false, /**< Disable Q notification at startup */
- IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q_SOURCE, /**< Q Condition to drive callback */
- IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */
- IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */
- },
-#endif
- {
- IX_ETH_ACC_TX_FRAME_ENET0_Q,
- "Eth Tx Q 1",
- ixEthTxFrameQMCallback,
- (IxQMgrCallbackId) IX_ETH_PORT_1,
- IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */
- IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */
- false, /**< Disable Q notification at startup */
- IX_ETH_ACC_TX_FRAME_ENET0_Q_SOURCE, /**< Q Condition to drive callback */
- IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */
- IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */
- },
-
- {
- IX_ETH_ACC_TX_FRAME_ENET1_Q,
- "Eth Tx Q 2",
- ixEthTxFrameQMCallback,
- (IxQMgrCallbackId) IX_ETH_PORT_2,
- IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */
- IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */
- false, /**< Disable Q notification at startup */
- IX_ETH_ACC_TX_FRAME_ENET1_Q_SOURCE, /**< Q Condition to drive callback */
- IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */
- IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */
- },
-#ifdef __ixp46X
- {
- IX_ETH_ACC_TX_FRAME_ENET2_Q,
- "Eth Tx Q 3",
- ixEthTxFrameQMCallback,
- (IxQMgrCallbackId) IX_ETH_PORT_3,
- IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */
- IX_QMGR_Q_ENTRY_SIZE1, /** Queue Entry Sizes - all Q entries are single ord entries */
- false, /** Disable Q notification at startup */
- IX_ETH_ACC_TX_FRAME_ENET2_Q_SOURCE, /** Q Condition to drive callback */
- IX_QMGR_Q_WM_LEVEL0, /* No queues use almost empty */
- IX_QMGR_Q_WM_LEVEL64, /** Q High water mark - needed used */
- },
-#endif
- {
- IX_ETH_ACC_TX_FRAME_DONE_ETH_Q,
- "Eth Tx Done Q",
- ixEthTxFrameDoneQMCallback,
- (IxQMgrCallbackId) 0,
- IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */
- IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */
- true, /**< Enable Q notification at startup */
- IX_ETH_ACC_TX_FRAME_DONE_ETH_Q_SOURCE, /**< Q Condition to drive callback */
- IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */
- IX_QMGR_Q_WM_LEVEL2, /**< Q High water mark - needed by NPE */
- },
-
- { /* Null Termination entry
- */
- (IxQMgrQId)0,
- (char *) NULL,
- (IxQMgrCallback) NULL,
- (IxQMgrCallbackId) 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- }
-
-};
-
-/**
- *
- * @brief Data structure used to register & initialize the Queues
- *
- * The structure will be filled at run time depending on the NPE
- * image already loaded and the QoS configured in ethDB.
- *
- */
-IX_ETH_ACC_PRIVATE
-IxEthAccQregInfo ixEthAccQmgrRxQueuesInfo[IX_ETHACC_MAX_RX_QUEUES+1]=
-{
- { /* PlaceHolder for rx queues
- * depending on the QoS configured
- */
- (IxQMgrQId)0,
- (char *) NULL,
- (IxQMgrCallback) NULL,
- (IxQMgrCallbackId) 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- },
-
- { /* PlaceHolder for rx queues
- * depending on the QoS configured
- */
- (IxQMgrQId)0,
- (char *) NULL,
- (IxQMgrCallback) NULL,
- (IxQMgrCallbackId) 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- },
-
- { /* PlaceHolder for rx queues
- * depending on the QoS configured
- */
- (IxQMgrQId)0,
- (char *) NULL,
- (IxQMgrCallback) NULL,
- (IxQMgrCallbackId) 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- },
-
- { /* PlaceHolder for rx queues
- * depending on the QoS configured
- */
- (IxQMgrQId)0,
- (char *) NULL,
- (IxQMgrCallback) NULL,
- (IxQMgrCallbackId) 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- },
-
- { /* PlaceHolder for rx queues
- * depending on the QoS configured
- */
- (IxQMgrQId)0,
- (char *) NULL,
- (IxQMgrCallback) NULL,
- (IxQMgrCallbackId) 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- },
-
- { /* PlaceHolder for rx queues
- * depending on the QoS configured
- */
- (IxQMgrQId)0,
- (char *) NULL,
- (IxQMgrCallback) NULL,
- (IxQMgrCallbackId) 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- },
-
- { /* PlaceHolder for rx queues
- * depending on the QoS configured
- */
- (IxQMgrQId)0,
- (char *) NULL,
- (IxQMgrCallback) NULL,
- (IxQMgrCallbackId) 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- },
-
- { /* PlaceHolder for rx queues
- * depending on the QoS configured
- */
- (IxQMgrQId)0,
- (char *) NULL,
- (IxQMgrCallback) NULL,
- (IxQMgrCallbackId) 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- },
-
- { /* Null Termination entry
- */
- (IxQMgrQId)0,
- (char *) NULL,
- (IxQMgrCallback) NULL,
- (IxQMgrCallbackId) 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- }
-
-};
-
-/* forward declarations */
-IX_ETH_ACC_PRIVATE IxEthAccStatus
-ixEthAccQMgrQueueSetup(IxEthAccQregInfo *qInfoDes);
-
-/**
- * @fn ixEthAccQMgrQueueSetup(void)
- *
- * @brief Setup one queue and its event, and register the callback required
- * by this component to the QMgr
- *
- * @internal
- */
-IX_ETH_ACC_PRIVATE IxEthAccStatus
-ixEthAccQMgrQueueSetup(IxEthAccQregInfo *qInfoDes)
-{
- /*
- * Configure each Q.
- */
- if ( ixQMgrQConfig( qInfoDes->qName,
- qInfoDes->qId,
- qInfoDes->qSize,
- qInfoDes->qWords) != IX_SUCCESS)
- {
- return IX_ETH_ACC_FAIL;
- }
-
- if ( ixQMgrWatermarkSet( qInfoDes->qId,
- qInfoDes->AlmostEmptyThreshold,
- qInfoDes->AlmostFullThreshold
- ) != IX_SUCCESS)
- {
- return IX_ETH_ACC_FAIL;
- }
-
- /*
- * Set dispatcher priority.
- */
- if ( ixQMgrDispatcherPrioritySet( qInfoDes->qId,
- IX_ETH_ACC_QM_QUEUE_DISPATCH_PRIORITY)
- != IX_SUCCESS)
- {
- return IX_ETH_ACC_FAIL;
- }
-
- /*
- * Register callbacks for each Q.
- */
- if ( ixQMgrNotificationCallbackSet(qInfoDes->qId,
- qInfoDes->qCallback,
- qInfoDes->callbackTag)
- != IX_SUCCESS )
- {
- return IX_ETH_ACC_FAIL;
- }
-
- /*
- * Set notification condition for Q
- */
- if (qInfoDes->qNotificationEnableAtStartup == true)
- {
- if ( ixQMgrNotificationEnable(qInfoDes->qId,
- qInfoDes->qConditionSource)
- != IX_SUCCESS )
- {
- return IX_ETH_ACC_FAIL;
- }
- }
-
- return(IX_ETH_ACC_SUCCESS);
-}
-
-/**
- * @fn ixEthAccQMgrQueuesConfig(void)
- *
- * @brief Setup all the queues and register all callbacks required
- * by this component to the QMgr
- *
- * The RxFree queues, tx queues, rx queues are configured statically
- *
- * Rx queues configuration is driven by QoS setup.
- * Many Rx queues may be required when QoS is enabled (this depends
- * on IxEthDB setup and the images being downloaded). The configuration
- * of the rxQueues is done in many steps as follows:
- *
- * @li select all Rx queues as configured by ethDB for all ports
- * @li sort the queues by traffic class
- * @li build the priority dependency for all queues
- * @li fill the configuration for all rx queues
- * @li configure all statically configured queues
- * @li configure all dynamically configured queues
- *
- * @param none
- *
- * @return IxEthAccStatus
- *
- * @internal
- */
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccQMgrQueuesConfig(void)
-{
- struct
- {
- int npeCount;
- UINT32 npeId;
- IxQMgrQId qId;
- IxEthDBProperty trafficClass;
- } rxQueues[IX_ETHACC_MAX_RX_QUEUES];
-
- UINT32 rxQueue = 0;
- UINT32 rxQueueCount = 0;
- IxQMgrQId ixQId =IX_QMGR_MAX_NUM_QUEUES;
- IxEthDBStatus ixEthDBStatus = IX_ETH_DB_SUCCESS;
- IxEthDBPortId ixEthDbPortId = 0;
- IxEthAccPortId ixEthAccPortId = 0;
- UINT32 ixNpeId = 0;
- UINT32 ixHighestNpeId = 0;
- UINT32 sortIterations = 0;
- IxEthAccStatus ret = IX_ETH_ACC_SUCCESS;
- IxEthAccQregInfo *qInfoDes = NULL;
- IxEthDBProperty ixEthDBTrafficClass = IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY;
- IxEthDBPropertyType ixEthDBPropertyType = IX_ETH_DB_INTEGER_PROPERTY;
- UINT32 ixEthDBParameter = 0;
- BOOL completelySorted = false;
-
- /* Fill the corspondance between ports and queues
- * This defines the mapping from port to queue Ids.
- */
-
- ixEthAccPortData[IX_ETH_PORT_1].ixEthAccRxData.rxFreeQueue
- = IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q;
- ixEthAccPortData[IX_ETH_PORT_2].ixEthAccRxData.rxFreeQueue
- = IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q;
-#ifdef __ixp46X
- ixEthAccPortData[IX_ETH_PORT_3].ixEthAccRxData.rxFreeQueue
- = IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q;
-#endif
- ixEthAccPortData[IX_ETH_PORT_1].ixEthAccTxData.txQueue
- = IX_ETH_ACC_TX_FRAME_ENET0_Q;
- ixEthAccPortData[IX_ETH_PORT_2].ixEthAccTxData.txQueue
- = IX_ETH_ACC_TX_FRAME_ENET1_Q;
-#ifdef __ixp46X
- ixEthAccPortData[IX_ETH_PORT_3].ixEthAccTxData.txQueue
- = IX_ETH_ACC_TX_FRAME_ENET2_Q;
-#endif
- /* Fill the corspondance between ports and NPEs
- * This defines the mapping from port to npeIds.
- */
-
- ixEthAccPortData[IX_ETH_PORT_1].npeId = IX_NPEMH_NPEID_NPEB;
- ixEthAccPortData[IX_ETH_PORT_2].npeId = IX_NPEMH_NPEID_NPEC;
-#ifdef __ixp46X
- ixEthAccPortData[IX_ETH_PORT_3].npeId = IX_NPEMH_NPEID_NPEA;
-#endif
- /* set the default rx scheduling discipline */
- ixEthAccDataInfo.schDiscipline = FIFO_NO_PRIORITY;
-
- /*
- * Queue Selection step:
- *
- * The following code selects all the queues and build
- * a temporary array which contains for each queue
- * - the queue Id,
- * - the highest traffic class (in case of many
- * priorities configured for the same queue on different
- * ports)
- * - the number of different Npes which are
- * configured to write to this queue.
- *
- * The output of this loop is a temporary array of RX queues
- * in any order.
- *
- */
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
- for (ixEthAccPortId = 0;
- (ixEthAccPortId < IX_ETH_ACC_NUMBER_OF_PORTS)
- && (ret == IX_ETH_ACC_SUCCESS);
- ixEthAccPortId++)
- {
- /* map between ethDb and ethAcc port Ids */
- ixEthDbPortId = (IxEthDBPortId)ixEthAccPortId;
-
- /* map between npeId and ethAcc port Ids */
- ixNpeId = IX_ETH_ACC_PORT_TO_NPE_ID(ixEthAccPortId);
-
- /* Iterate thru the different priorities */
- for (ixEthDBTrafficClass = IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY;
- ixEthDBTrafficClass <= IX_ETH_DB_QOS_TRAFFIC_CLASS_7_RX_QUEUE_PROPERTY;
- ixEthDBTrafficClass++)
- {
- ixEthDBStatus = ixEthDBFeaturePropertyGet(
- ixEthDbPortId,
- IX_ETH_DB_VLAN_QOS,
- ixEthDBTrafficClass,
- &ixEthDBPropertyType,
- (void *)&ixEthDBParameter);
-
- if (ixEthDBStatus == IX_ETH_DB_SUCCESS)
- {
- /* This port and QoS class are mapped to
- * a RX queue.
- */
- if (ixEthDBPropertyType == IX_ETH_DB_INTEGER_PROPERTY)
- {
- /* remember the highest npe Id supporting ethernet */
- if (ixNpeId > ixHighestNpeId)
- {
- ixHighestNpeId = ixNpeId;
- }
-
- /* search the queue in the list of queues
- * already used by an other port or QoS
- */
- for (rxQueue = 0;
- rxQueue < rxQueueCount;
- rxQueue++)
- {
- if (rxQueues[rxQueue].qId == (IxQMgrQId)ixEthDBParameter)
- {
- /* found an existing setup, update the number of ports
- * for this queue if the port maps to
- * a different NPE.
- */
- if (rxQueues[rxQueue].npeId != ixNpeId)
- {
- rxQueues[rxQueue].npeCount++;
- rxQueues[rxQueue].npeId = ixNpeId;
- }
- /* get the highest traffic class for this queue */
- if (rxQueues[rxQueue].trafficClass > ixEthDBTrafficClass)
- {
- rxQueues[rxQueue].trafficClass = ixEthDBTrafficClass;
- }
- break;
- }
- }
- if (rxQueue == rxQueueCount)
- {
- /* new queue not found in the current list,
- * add a new entry.
- */
- IX_OSAL_ASSERT(rxQueueCount < IX_ETHACC_MAX_RX_QUEUES);
- rxQueues[rxQueueCount].qId = ixEthDBParameter;
- rxQueues[rxQueueCount].npeCount = 1;
- rxQueues[rxQueueCount].npeId = ixNpeId;
- rxQueues[rxQueueCount].trafficClass = ixEthDBTrafficClass;
- rxQueueCount++;
- }
- }
- else
- {
- /* unexpected property type (not Integer) */
- ret = IX_ETH_ACC_FAIL;
-
- IX_ETH_ACC_WARNING_LOG("ixEthAccQMgrQueuesConfig: unexpected property type returned by EthDB\n", 0, 0, 0, 0, 0, 0);
-
- /* no point to continue to iterate */
- break;
- }
- }
- else
- {
- /* No Rx queue configured for this port
- * and this traffic class. Do nothing.
- */
- }
- }
-
- /* notify EthDB that queue initialization is complete and traffic class allocation is frozen */
- ixEthDBFeaturePropertySet(ixEthDbPortId,
- IX_ETH_DB_VLAN_QOS,
- IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE,
- NULL /* ignored */);
- }
-
-#else
-
- ixNpeId = IX_ETH_ACC_PORT_TO_NPE_ID(ixEthAccPortId);
- rxQueues[0].qId = 4;
- rxQueues[0].npeCount = 1;
- rxQueues[0].npeId = ixNpeId;
- rxQueues[0].trafficClass = IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY;
- rxQueueCount++;
-
-#endif
-
- /* check there is at least 1 rx queue : there is no point
- * to continue if there is no rx queue configured
- */
- if ((rxQueueCount == 0) || (ret == IX_ETH_ACC_FAIL))
- {
- IX_ETH_ACC_WARNING_LOG("ixEthAccQMgrQueuesConfig: no queues configured, bailing out\n", 0, 0, 0, 0, 0, 0);
- return (IX_ETH_ACC_FAIL);
- }
-
- /* Queue sort step:
- *
- * Re-order the array of queues by decreasing traffic class
- * using a bubble sort. (trafficClass 0 is the lowest
- * priority traffic, trafficClass 7 is the highest priority traffic)
- *
- * Primary sort order is traffic class
- * Secondary sort order is npeId
- *
- * Note that a bubble sort algorithm is not very efficient when
- * the number of queues grows . However, this is not a very bad choice
- * considering the very small number of entries to sort. Also, bubble
- * sort is extremely fast when the list is already sorted.
- *
- * The output of this loop is a sorted array of queues.
- *
- */
- sortIterations = 0;
- do
- {
- sortIterations++;
- completelySorted = true;
- for (rxQueue = 0;
- rxQueue < rxQueueCount - sortIterations;
- rxQueue++)
- {
- /* compare adjacent elements */
- if ((rxQueues[rxQueue].trafficClass <
- rxQueues[rxQueue+1].trafficClass)
- || ((rxQueues[rxQueue].trafficClass ==
- rxQueues[rxQueue+1].trafficClass)
- &&(rxQueues[rxQueue].npeId <
- rxQueues[rxQueue+1].npeId)))
- {
- /* swap adjacent elements */
- int npeCount = rxQueues[rxQueue].npeCount;
- UINT32 npeId = rxQueues[rxQueue].npeId;
- IxQMgrQId qId = rxQueues[rxQueue].qId;
- IxEthDBProperty trafficClass = rxQueues[rxQueue].trafficClass;
- rxQueues[rxQueue].npeCount = rxQueues[rxQueue+1].npeCount;
- rxQueues[rxQueue].npeId = rxQueues[rxQueue+1].npeId;
- rxQueues[rxQueue].qId = rxQueues[rxQueue+1].qId;
- rxQueues[rxQueue].trafficClass = rxQueues[rxQueue+1].trafficClass;
- rxQueues[rxQueue+1].npeCount = npeCount;
- rxQueues[rxQueue+1].npeId = npeId;
- rxQueues[rxQueue+1].qId = qId;
- rxQueues[rxQueue+1].trafficClass = trafficClass;
- completelySorted = false;
- }
- }
- }
- while (!completelySorted);
-
- /* Queue traffic class list:
- *
- * Fill an array of rx queues linked by ascending traffic classes.
- *
- * If the queues are configured as follows
- * qId 6 -> traffic class 0 (lowest)
- * qId 7 -> traffic class 0
- * qId 8 -> traffic class 6
- * qId 12 -> traffic class 7 (highest)
- *
- * Then the output of this loop will be
- *
- * higherPriorityQueue[6] = 8
- * higherPriorityQueue[7] = 8
- * higherPriorityQueue[8] = 12
- * higherPriorityQueue[12] = Invalid queueId
- * higherPriorityQueue[...] = Invalid queueId
- *
- * Note that this queue ordering does not handle all possibilities
- * that could result from different rules associated with different
- * ports, and inconsistencies in the rules. In all cases, the
- * output of this algorithm is a simple linked list of queues,
- * without closed circuit.
-
- * This list is implemented as an array with invalid values initialized
- * with an "invalid" queue id which is the maximum number of queues.
- *
- */
-
- /*
- * Initialise the rx queue list.
- */
- for (rxQueue = 0; rxQueue < IX_QMGR_MAX_NUM_QUEUES; rxQueue++)
- {
- ixEthAccDataInfo.higherPriorityQueue[rxQueue] = IX_QMGR_MAX_NUM_QUEUES;
- }
-
- /* build the linked list for this NPE.
- */
- for (ixNpeId = 0;
- ixNpeId <= ixHighestNpeId;
- ixNpeId++)
- {
- /* iterate thru the sorted list of queues
- */
- ixQId = IX_QMGR_MAX_NUM_QUEUES;
- for (rxQueue = 0;
- rxQueue < rxQueueCount;
- rxQueue++)
- {
- if (rxQueues[rxQueue].npeId == ixNpeId)
- {
- ixEthAccDataInfo.higherPriorityQueue[rxQueues[rxQueue].qId] = ixQId;
- /* iterate thru queues with the same traffic class
- * than the current queue. (queues are ordered by descending
- * traffic classes and npeIds).
- */
- while ((rxQueue < rxQueueCount - 1)
- && (rxQueues[rxQueue].trafficClass
- == rxQueues[rxQueue+1].trafficClass)
- && (ixNpeId == rxQueues[rxQueue].npeId))
- {
- rxQueue++;
- ixEthAccDataInfo.higherPriorityQueue[rxQueues[rxQueue].qId] = ixQId;
- }
- ixQId = rxQueues[rxQueue].qId;
- }
- }
- }
-
- /* point on the first dynamic queue description */
- qInfoDes = ixEthAccQmgrRxQueuesInfo;
-
- /* update the list of queues with the rx queues */
- for (rxQueue = 0;
- (rxQueue < rxQueueCount) && (ret == IX_ETH_ACC_SUCCESS);
- rxQueue++)
- {
- /* Don't utilize more than IX_ETHACC_MAX_LARGE_RX_QUEUES queues
- * with the full 128 entries. For the lower priority queues, use
- * a smaller number of entries. This ensures queue resources
- * remain available for other components.
- */
- if( (rxQueueCount > IX_ETHACC_MAX_LARGE_RX_QUEUES) &&
- (rxQueue < rxQueueCount - IX_ETHACC_MAX_LARGE_RX_QUEUES) )
- {
- /* add the small RX Queue setup template to the list of queues */
- memcpy(qInfoDes, &ixEthAccQmgrRxSmallTemplate, sizeof(*qInfoDes));
- } else {
- /* add the default RX Queue setup template to the list of queues */
- memcpy(qInfoDes, &ixEthAccQmgrRxDefaultTemplate, sizeof(*qInfoDes));
- }
-
- /* setup the RxQueue ID */
- qInfoDes->qId = rxQueues[rxQueue].qId;
-
- /* setup the RxQueue watermark level
- *
- * Each queue can be filled by many NPEs. To avoid the
- * NPEs to write to a full queue, need to set the
- * high watermark level for nearly full condition.
- * (the high watermark level are a power of 2
- * starting from the top of the queue)
- *
- * Number of watermark
- * ports level
- * 1 0
- * 2 1
- * 3 2
- * 4 4
- * 5 4
- * 6 8
- * n approx. 2**ceil(log2(n))
- */
- if (rxQueues[rxQueue].npeCount == 1)
- {
- qInfoDes->AlmostFullThreshold = IX_QMGR_Q_WM_LEVEL0;
- }
- else if (rxQueues[rxQueue].npeCount == 2)
- {
- qInfoDes->AlmostFullThreshold = IX_QMGR_Q_WM_LEVEL1;
- }
- else if (rxQueues[rxQueue].npeCount == 3)
- {
- qInfoDes->AlmostFullThreshold = IX_QMGR_Q_WM_LEVEL2;
- }
- else
- {
- /* reach the maximum number for CSR 2.0 */
- IX_ETH_ACC_WARNING_LOG("ixEthAccQMgrQueuesConfig: maximum number of NPEs per queue reached, bailing out\n", 0, 0, 0, 0, 0, 0);
- ret = IX_ETH_ACC_FAIL;
- break;
- }
-
- /* move to next queue entry */
- ++qInfoDes;
- }
-
- /* configure the static list (RxFree, Tx and TxDone queues) */
- for (qInfoDes = ixEthAccQmgrStaticInfo;
- (qInfoDes->qCallback != (IxQMgrCallback) NULL )
- && (ret == IX_ETH_ACC_SUCCESS);
- ++qInfoDes)
- {
- ret = ixEthAccQMgrQueueSetup(qInfoDes);
- }
-
- /* configure the dynamic list (Rx queues) */
- for (qInfoDes = ixEthAccQmgrRxQueuesInfo;
- (qInfoDes->qCallback != (IxQMgrCallback) NULL )
- && (ret == IX_ETH_ACC_SUCCESS);
- ++qInfoDes)
- {
- ret = ixEthAccQMgrQueueSetup(qInfoDes);
- }
-
- return(ret);
-}
-
-/**
- * @fn ixEthAccQMgrRxQEntryGet(UINT32 *rxQueueEntries)
- *
- * @brief Add and return the total number of entries in all Rx queues
- *
- * @param UINT32 rxQueueEntries[in] number of entries in all queues
- *
- * @return void
- *
- * @note Rx queues configuration is driven by Qos Setup. There is a
- * variable number of rx queues which are set at initialisation.
- *
- * @internal
- */
-IX_ETH_ACC_PUBLIC
-void ixEthAccQMgrRxQEntryGet(UINT32 *numRxQueueEntries)
-{
- UINT32 rxQueueLevel;
- IxEthAccQregInfo *qInfoDes;;
-
- *numRxQueueEntries = 0;
-
- /* iterate thru rx queues */
- for (qInfoDes = ixEthAccQmgrRxQueuesInfo;
- qInfoDes->qCallback != (IxQMgrCallback)NULL;
- ++qInfoDes)
- {
- /* retrieve the rx queue level */
- rxQueueLevel = 0;
- ixQMgrQNumEntriesGet(qInfoDes->qId, &rxQueueLevel);
- (*numRxQueueEntries) += rxQueueLevel;
- }
-}
-
-/**
- * @fn ixEthAccQMgrRxCallbacksRegister(IxQMgrCallback ixQMgrCallback)
- *
- * @brief Change the callback registered to all rx queues.
- *
- * @param IxQMgrCallback ixQMgrCallback[in] QMgr callback to register
- *
- * @return IxEthAccStatus
- *
- * @note The user may decide to use different Rx mechanisms
- * (e.g. receive many frames at the same time , or receive
- * one frame at a time, depending on the overall application
- * performances). A different QMgr callback is registered. This
- * way, there is no excessive pointer checks in the datapath.
- *
- * @internal
- */
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccQMgrRxCallbacksRegister(IxQMgrCallback ixQMgrCallback)
-{
- IxEthAccQregInfo *qInfoDes;
- IxEthAccStatus ret = IX_ETH_ACC_SUCCESS;
-
- /* parameter check */
- if (NULL == ixQMgrCallback)
- {
- ret = IX_ETH_ACC_FAIL;
- }
-
- /* iterate thru rx queues */
- for (qInfoDes = ixEthAccQmgrRxQueuesInfo;
- (qInfoDes->qCallback != (IxQMgrCallback) NULL )
- && (ret == IX_ETH_ACC_SUCCESS);
- ++qInfoDes)
- {
- /* register the rx callback for all queues */
- if (ixQMgrNotificationCallbackSet(qInfoDes->qId,
- ixQMgrCallback,
- qInfoDes->callbackTag
- ) != IX_SUCCESS)
- {
- ret = IX_ETH_ACC_FAIL;
- }
- }
- return(ret);
-}
-
-/**
- * @fn ixEthAccSingleEthNpeCheck(IxEthAccPortId portId)
- *
- * @brief Check the npe exists for this port
- *
- * @param IxEthAccPortId portId[in] port
- *
- * @return IxEthAccStatus
- *
- * @internal
- */
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccSingleEthNpeCheck(IxEthAccPortId portId)
-{
-
- /* If not IXP42X A0 stepping, proceed to check for existence of coprocessors */
- if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
- (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
- || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
- {
- if ((IX_ETH_PORT_1 == portId) &&
- (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) ==
- IX_FEATURE_CTRL_COMPONENT_ENABLED))
- {
- return IX_ETH_ACC_SUCCESS;
- }
-
- if ((IX_ETH_PORT_2 == portId) &&
- (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) ==
- IX_FEATURE_CTRL_COMPONENT_ENABLED))
- {
- return IX_ETH_ACC_SUCCESS;
- }
-
- if ((IX_ETH_PORT_3 == portId) &&
- (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA_ETH) ==
- IX_FEATURE_CTRL_COMPONENT_ENABLED))
- {
- return IX_ETH_ACC_SUCCESS;
- }
-
- return IX_ETH_ACC_FAIL;
- }
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-/**
- * @fn ixEthAccStatsShow(void)
- *
- * @brief Displays all EthAcc stats
- *
- * @return void
- *
- */
-void ixEthAccStatsShow(IxEthAccPortId portId)
-{
- ixEthAccMdioShow();
-
- printf("\nPort %u\nUnicast MAC : ", portId);
- ixEthAccPortUnicastAddressShow(portId);
- ixEthAccPortMulticastAddressShow(portId);
- printf("\n");
-
- ixEthAccDataPlaneShow();
-}
-
-
-
+++ /dev/null
-/**
- * @file IxEthAccControlInterface.c
- *
- * @author Intel Corporation
- * @date
- *
- * @brief IX_ETH_ACC_PUBLIC wrappers for control plane functions
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxOsal.h"
-#include "IxEthAcc.h"
-#include "IxEthAcc_p.h"
-
-PUBLIC IxOsalMutex ixEthAccControlInterfaceMutex;
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortEnable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- printf("EthAcc: (Mac) cannot enable port %d, service not initialized\n", portId);
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortEnablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortDisable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- /* check the context is iinitialized */
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortDisablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortEnabledQuery(IxEthAccPortId portId, BOOL *enabled)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortEnabledQueryPriv(portId, enabled);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortPromiscuousModeClear(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortPromiscuousModeClearPriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortPromiscuousModeSet(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortPromiscuousModeSetPriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortUnicastMacAddressSet(IxEthAccPortId portId, IxEthAccMacAddr *macAddr)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortUnicastMacAddressSetPriv(portId, macAddr);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortUnicastMacAddressGet(IxEthAccPortId portId, IxEthAccMacAddr *macAddr)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortUnicastMacAddressGetPriv(portId, macAddr);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortMulticastAddressJoin(IxEthAccPortId portId, IxEthAccMacAddr *macAddr)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortMulticastAddressJoinPriv(portId, macAddr);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortMulticastAddressJoinAll(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortMulticastAddressJoinAllPriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortMulticastAddressLeave(IxEthAccPortId portId, IxEthAccMacAddr *macAddr)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortMulticastAddressLeavePriv(portId, macAddr);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortMulticastAddressLeaveAll(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortMulticastAddressLeaveAllPriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortUnicastAddressShow(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortUnicastAddressShowPriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC void
-ixEthAccPortMulticastAddressShow(IxEthAccPortId portId)
-{
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return;
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- ixEthAccPortMulticastAddressShowPriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortDuplexModeSet(IxEthAccPortId portId, IxEthAccDuplexMode mode)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortDuplexModeSetPriv(portId, mode);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortDuplexModeGet(IxEthAccPortId portId, IxEthAccDuplexMode *mode)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortDuplexModeGetPriv(portId, mode);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortTxFrameAppendPaddingEnable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortTxFrameAppendPaddingEnablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortTxFrameAppendPaddingDisable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortTxFrameAppendPaddingDisablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortTxFrameAppendFCSEnable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortTxFrameAppendFCSEnablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortTxFrameAppendFCSDisable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortTxFrameAppendFCSDisablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortRxFrameAppendFCSEnable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortRxFrameAppendFCSEnablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortRxFrameAppendFCSDisable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortRxFrameAppendFCSDisablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccTxSchedulingDisciplineSet(IxEthAccPortId portId, IxEthAccSchedulerDiscipline sched)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccTxSchedulingDisciplineSetPriv(portId, sched);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccRxSchedulingDisciplineSet(IxEthAccSchedulerDiscipline sched)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccRxSchedulingDisciplineSetPriv(sched);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortNpeLoopbackEnable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccNpeLoopbackEnablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortTxEnable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortTxEnablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortRxEnable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortRxEnablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortNpeLoopbackDisable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccNpeLoopbackDisablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortTxDisable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortTxDisablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortRxDisable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortRxDisablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortMacReset(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortMacResetPriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
+++ /dev/null
-/**
- * @file IxEthDataPlane.c
- *
- * @author Intel Corporation
- * @date 12-Feb-2002
- *
- * @brief This file contains the implementation of the IXPxxx
- * Ethernet Access Data plane component
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxNpeMh.h"
-#include "IxEthAcc.h"
-#include "IxEthDB.h"
-#include "IxOsal.h"
-#include "IxEthDBPortDefs.h"
-#include "IxFeatureCtrl.h"
-#include "IxEthAcc_p.h"
-#include "IxEthAccQueueAssign_p.h"
-
-extern PUBLIC IxEthAccMacState ixEthAccMacState[];
-extern PUBLIC UINT32 ixEthAccNewSrcMask;
-
-/**
- * private functions prototype
- */
-PRIVATE IX_OSAL_MBUF *
-ixEthAccEntryFromQConvert(UINT32 qEntry, UINT32 mask);
-
-PRIVATE UINT32
-ixEthAccMbufRxQPrepare(IX_OSAL_MBUF *mbuf);
-
-PRIVATE UINT32
-ixEthAccMbufTxQPrepare(IX_OSAL_MBUF *mbuf);
-
-PRIVATE IxEthAccStatus
-ixEthAccTxSwQHighestPriorityGet(IxEthAccPortId portId,
- IxEthAccTxPriority *priorityPtr);
-
-PRIVATE IxEthAccStatus
-ixEthAccTxFromSwQ(IxEthAccPortId portId,
- IxEthAccTxPriority priority);
-
-PRIVATE IxEthAccStatus
-ixEthAccRxFreeFromSwQ(IxEthAccPortId portId);
-
-PRIVATE void
-ixEthAccMbufFromTxQ(IX_OSAL_MBUF *mbuf);
-
-PRIVATE void
-ixEthAccMbufFromRxQ(IX_OSAL_MBUF *mbuf);
-
-PRIVATE IX_STATUS
-ixEthAccQmgrLockTxWrite(IxEthAccPortId portId,
- UINT32 qBuffer);
-
-PRIVATE IX_STATUS
-ixEthAccQmgrLockRxWrite(IxEthAccPortId portId,
- UINT32 qBuffer);
-
-PRIVATE IX_STATUS
-ixEthAccQmgrTxWrite(IxEthAccPortId portId,
- UINT32 qBuffer,
- UINT32 priority);
-
-/**
- * @addtogroup IxEthAccPri
- *@{
- */
-
-/* increment a counter only when stats are enabled */
-#define TX_STATS_INC(port,field) \
- IX_ETH_ACC_STATS_INC(ixEthAccPortData[port].ixEthAccTxData.stats.field)
-#define RX_STATS_INC(port,field) \
- IX_ETH_ACC_STATS_INC(ixEthAccPortData[port].ixEthAccRxData.stats.field)
-
-/* always increment the counter (mainly used for unexpected errors) */
-#define TX_INC(port,field) \
- ixEthAccPortData[port].ixEthAccTxData.stats.field++
-#define RX_INC(port,field) \
- ixEthAccPortData[port].ixEthAccRxData.stats.field++
-
-PRIVATE IxEthAccDataPlaneStats ixEthAccDataStats;
-
-extern IxEthAccPortDataInfo ixEthAccPortData[];
-extern IxEthAccInfo ixEthAccDataInfo;
-
-PRIVATE IxOsalFastMutex txWriteMutex[IX_ETH_ACC_NUMBER_OF_PORTS];
-PRIVATE IxOsalFastMutex rxWriteMutex[IX_ETH_ACC_NUMBER_OF_PORTS];
-
-/**
- *
- * @brief Mbuf header conversion macros : they implement the
- * different conversions using a temporary value. They also double-check
- * that the parameters can be converted to/from NPE format.
- *
- */
-#if defined(__wince) && !defined(IN_KERNEL)
-#define PTR_VIRT2NPE(ptrSrc,dst) \
- do { UINT32 temp; \
- IX_OSAL_ENSURE(sizeof(ptrSrc) == sizeof(UINT32), "Wrong parameter type"); \
- IX_OSAL_ENSURE(sizeof(dst) == sizeof(UINT32), "Wrong parameter type"); \
- temp = (UINT32)IX_OSAL_MBUF_MBUF_VIRTUAL_TO_PHYSICAL_TRANSLATION((IX_OSAL_MBUF*)ptrSrc); \
- (dst) = IX_OSAL_SWAP_BE_SHARED_LONG(temp); } \
- while(0)
-
-#define PTR_NPE2VIRT(type,src,ptrDst) \
- do { void *temp; \
- IX_OSAL_ENSURE(sizeof(type) == sizeof(UINT32), "Wrong parameter type"); \
- IX_OSAL_ENSURE(sizeof(src) == sizeof(UINT32), "Wrong parameter type"); \
- IX_OSAL_ENSURE(sizeof(ptrDst) == sizeof(UINT32), "Wrong parameter type"); \
- temp = (void *)IX_OSAL_SWAP_BE_SHARED_LONG(src); \
- (ptrDst) = (type)IX_OSAL_MBUF_MBUF_PHYSICAL_TO_VIRTUAL_TRANSLATION(temp); } \
- while(0)
-#else
-#define PTR_VIRT2NPE(ptrSrc,dst) \
- do { UINT32 temp; \
- IX_OSAL_ENSURE(sizeof(ptrSrc) == sizeof(UINT32), "Wrong parameter type"); \
- IX_OSAL_ENSURE(sizeof(dst) == sizeof(UINT32), "Wrong parameter type"); \
- temp = (UINT32)IX_OSAL_MMU_VIRT_TO_PHYS(ptrSrc); \
- (dst) = IX_OSAL_SWAP_BE_SHARED_LONG(temp); } \
- while(0)
-
-#define PTR_NPE2VIRT(type,src,ptrDst) \
- do { void *temp; \
- IX_OSAL_ENSURE(sizeof(type) == sizeof(UINT32), "Wrong parameter type"); \
- IX_OSAL_ENSURE(sizeof(src) == sizeof(UINT32), "Wrong parameter type"); \
- IX_OSAL_ENSURE(sizeof(ptrDst) == sizeof(UINT32), "Wrong parameter type"); \
- temp = (void *)IX_OSAL_SWAP_BE_SHARED_LONG(src); \
- (ptrDst) = (type)IX_OSAL_MMU_PHYS_TO_VIRT(temp); } \
- while(0)
-#endif
-
-/**
- *
- * @brief Mbuf payload pointer conversion macros : Wince has its own
- * method to convert the buffer pointers
- */
-#if defined(__wince) && !defined(IN_KERNEL)
-#define DATAPTR_VIRT2NPE(ptrSrc,dst) \
- do { UINT32 temp; \
- temp = (UINT32)IX_OSAL_MBUF_DATA_VIRTUAL_TO_PHYSICAL_TRANSLATION(ptrSrc); \
- (dst) = IX_OSAL_SWAP_BE_SHARED_LONG(temp); } \
- while(0)
-
-#else
-#define DATAPTR_VIRT2NPE(ptrSrc,dst) PTR_VIRT2NPE(IX_OSAL_MBUF_MDATA(ptrSrc),dst)
-#endif
-
-
-/* Flush the shared part of the mbuf header */
-#define IX_ETHACC_NE_CACHE_FLUSH(mbufPtr) \
- do { \
- IX_OSAL_CACHE_FLUSH(IX_ETHACC_NE_SHARED(mbufPtr), \
- sizeof(IxEthAccNe)); \
- } \
- while(0)
-
-/* Invalidate the shared part of the mbuf header */
-#define IX_ETHACC_NE_CACHE_INVALIDATE(mbufPtr) \
- do { \
- IX_OSAL_CACHE_INVALIDATE(IX_ETHACC_NE_SHARED(mbufPtr), \
- sizeof(IxEthAccNe)); \
- } \
- while(0)
-
-/* Preload one cache line (shared mbuf headers are aligned
- * and their size is 1 cache line)
- *
- * IX_OSAL_CACHED is defined when the mbuf headers are
- * allocated from cached memory.
- *
- * Other processor on emulation environment may not implement
- * preload function
- */
-#ifdef IX_OSAL_CACHED
- #if (CPU!=SIMSPARCSOLARIS) && !defined (__wince)
- #define IX_ACC_DATA_CACHE_PRELOAD(ptr) \
- do { /* preload a cache line (Xscale Processor) */ \
- __asm__ (" pld [%0]\n": : "r" (ptr)); \
- } \
- while(0)
- #else
- /* preload not implemented on different processor */
- #define IX_ACC_DATA_CACHE_PRELOAD(mbufPtr) \
- do { /* nothing */ } while (0)
- #endif
-#else
- /* preload not needed if cache is not enabled */
- #define IX_ACC_DATA_CACHE_PRELOAD(mbufPtr) \
- do { /* nothing */ } while (0)
-#endif
-
-/**
- *
- * @brief function to retrieve the correct pointer from
- * a queue entry posted by the NPE
- *
- * @param qEntry : entry from qmgr queue
- * mask : applicable mask for this queue
- * (4 most significant bits are used for additional informations)
- *
- * @return IX_OSAL_MBUF * pointer to mbuf header
- *
- * @internal
- */
-PRIVATE IX_OSAL_MBUF *
-ixEthAccEntryFromQConvert(UINT32 qEntry, UINT32 mask)
-{
- IX_OSAL_MBUF *mbufPtr;
-
- if (qEntry != 0)
- {
- /* mask NPE bits (e.g. priority, port ...) */
- qEntry &= mask;
-
-#if IX_ACC_DRAM_PHYS_OFFSET != 0
- /* restore the original address pointer (if PHYS_OFFSET is not 0) */
- qEntry |= (IX_ACC_DRAM_PHYS_OFFSET & ~IX_ETHNPE_QM_Q_RXENET_ADDR_MASK);
-#endif
- /* get the mbuf pointer address from the npe-shared address */
- qEntry -= offsetof(IX_OSAL_MBUF,ix_ne);
-
- /* phys2virt mbuf */
- mbufPtr = (IX_OSAL_MBUF *)IX_OSAL_MMU_PHYS_TO_VIRT(qEntry);
-
- /* preload the cacheline shared with NPE */
- IX_ACC_DATA_CACHE_PRELOAD(IX_ETHACC_NE_SHARED(mbufPtr));
-
- /* preload the cacheline used by xscale */
- IX_ACC_DATA_CACHE_PRELOAD(mbufPtr);
- }
- else
- {
- mbufPtr = NULL;
- }
-
- return mbufPtr;
-}
-
-/* Convert the mbuf header for NPE transmission */
-PRIVATE UINT32
-ixEthAccMbufTxQPrepare(IX_OSAL_MBUF *mbuf)
-{
- UINT32 qbuf;
- UINT32 len;
-
- /* endianess swap for tci and flags
- note: this is done only once, even for chained buffers */
- IX_ETHACC_NE_FLAGS(mbuf) = IX_OSAL_SWAP_BE_SHARED_SHORT(IX_ETHACC_NE_FLAGS(mbuf));
- IX_ETHACC_NE_VLANTCI(mbuf) = IX_OSAL_SWAP_BE_SHARED_SHORT(IX_ETHACC_NE_VLANTCI(mbuf));
-
- /* test for unchained mbufs */
- if (IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mbuf) == NULL)
- {
- /* "best case" scenario : unchained mbufs */
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.unchainedTxMBufs);
-
- /* payload pointer conversion */
- DATAPTR_VIRT2NPE(mbuf, IX_ETHACC_NE_DATA(mbuf));
-
- /* unchained mbufs : the frame length is the mbuf length
- * and the 2 identical lengths are stored in the same
- * word.
- */
- len = IX_OSAL_MBUF_MLEN(mbuf);
-
- /* set the length in both length and pktLen 16-bits fields */
- len |= (len << IX_ETHNPE_ACC_LENGTH_OFFSET);
- IX_ETHACC_NE_LEN(mbuf) = IX_OSAL_SWAP_BE_SHARED_LONG(len);
-
- /* unchained mbufs : next contains 0 */
- IX_ETHACC_NE_NEXT(mbuf) = 0;
-
- /* flush shared header after all address conversions */
- IX_ETHACC_NE_CACHE_FLUSH(mbuf);
- }
- else
- {
- /* chained mbufs */
- IX_OSAL_MBUF *ptr = mbuf;
- IX_OSAL_MBUF *nextPtr;
- UINT32 frmLen;
-
- /* get the frame length from the header of the first buffer */
- frmLen = IX_OSAL_MBUF_PKT_LEN(mbuf);
-
- do
- {
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.chainedTxMBufs);
-
- /* payload pointer */
- DATAPTR_VIRT2NPE(ptr,IX_ETHACC_NE_DATA(ptr));
- /* Buffer length and frame length are stored in the same word */
- len = IX_OSAL_MBUF_MLEN(ptr);
- len = frmLen | (len << IX_ETHNPE_ACC_LENGTH_OFFSET);
- IX_ETHACC_NE_LEN(ptr) = IX_OSAL_SWAP_BE_SHARED_LONG(len);
-
- /* get the virtual next chain pointer */
- nextPtr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(ptr);
- if (nextPtr != NULL)
- {
- /* shared pointer of the next buffer is chained */
- PTR_VIRT2NPE(IX_ETHACC_NE_SHARED(nextPtr),
- IX_ETHACC_NE_NEXT(ptr));
- }
- else
- {
- IX_ETHACC_NE_NEXT(ptr) = 0;
- }
-
- /* flush shared header after all address conversions */
- IX_ETHACC_NE_CACHE_FLUSH(ptr);
-
- /* move to next buffer */
- ptr = nextPtr;
-
- /* the frame length field is set only in the first buffer
- * and is zeroed in the next buffers
- */
- frmLen = 0;
- }
- while(ptr != NULL);
-
- }
-
- /* virt2phys mbuf itself */
- qbuf = (UINT32)IX_OSAL_MMU_VIRT_TO_PHYS(
- IX_ETHACC_NE_SHARED(mbuf));
-
- /* Ensure the bits which are reserved to exchange information with
- * the NPE are cleared
- *
- * If the mbuf address is not correctly aligned, or from an
- * incompatible memory range, there is no point to continue
- */
- IX_OSAL_ENSURE(((qbuf & ~IX_ETHNPE_QM_Q_TXENET_ADDR_MASK) == 0),
- "Invalid address range");
-
- return qbuf;
-}
-
-/* Convert the mbuf header for NPE reception */
-PRIVATE UINT32
-ixEthAccMbufRxQPrepare(IX_OSAL_MBUF *mbuf)
-{
- UINT32 len;
- UINT32 qbuf;
-
- if (IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mbuf) == NULL)
- {
- /* "best case" scenario : unchained mbufs */
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.unchainedRxFreeMBufs);
-
- /* unchained mbufs : payload pointer */
- DATAPTR_VIRT2NPE(mbuf, IX_ETHACC_NE_DATA(mbuf));
-
- /* unchained mbufs : set the buffer length
- * and the frame length field is zeroed
- */
- len = (IX_OSAL_MBUF_MLEN(mbuf) << IX_ETHNPE_ACC_LENGTH_OFFSET);
- IX_ETHACC_NE_LEN(mbuf) = IX_OSAL_SWAP_BE_SHARED_LONG(len);
-
- /* unchained mbufs : next pointer is null */
- IX_ETHACC_NE_NEXT(mbuf) = 0;
-
- /* flush shared header after all address conversions */
- IX_ETHACC_NE_CACHE_FLUSH(mbuf);
-
- /* remove shared header cache line */
- IX_ETHACC_NE_CACHE_INVALIDATE(mbuf);
- }
- else
- {
- /* chained mbufs */
- IX_OSAL_MBUF *ptr = mbuf;
- IX_OSAL_MBUF *nextPtr;
-
- do
- {
- /* chained mbufs */
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.chainedRxFreeMBufs);
-
- /* we must save virtual next chain pointer */
- nextPtr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(ptr);
-
- if (nextPtr != NULL)
- {
- /* chaining pointer for NPE */
- PTR_VIRT2NPE(IX_ETHACC_NE_SHARED(nextPtr),
- IX_ETHACC_NE_NEXT(ptr));
- }
- else
- {
- IX_ETHACC_NE_NEXT(ptr) = 0;
- }
-
- /* payload pointer */
- DATAPTR_VIRT2NPE(ptr,IX_ETHACC_NE_DATA(ptr));
-
- /* buffer length */
- len = (IX_OSAL_MBUF_MLEN(ptr) << IX_ETHNPE_ACC_LENGTH_OFFSET);
- IX_ETHACC_NE_LEN(ptr) = IX_OSAL_SWAP_BE_SHARED_LONG(len);
-
- /* flush shared header after all address conversions */
- IX_ETHACC_NE_CACHE_FLUSH(ptr);
-
- /* remove shared header cache line */
- IX_ETHACC_NE_CACHE_INVALIDATE(ptr);
-
- /* next mbuf in the chain */
- ptr = nextPtr;
- }
- while(ptr != NULL);
- }
-
- /* virt2phys mbuf itself */
- qbuf = (UINT32)IX_OSAL_MMU_VIRT_TO_PHYS(
- IX_ETHACC_NE_SHARED(mbuf));
-
- /* Ensure the bits which are reserved to exchange information with
- * the NPE are cleared
- *
- * If the mbuf address is not correctly aligned, or from an
- * incompatible memory range, there is no point to continue
- */
- IX_OSAL_ENSURE(((qbuf & ~IX_ETHNPE_QM_Q_RXENET_ADDR_MASK) == 0),
- "Invalid address range");
-
- return qbuf;
-}
-
-/* Convert the mbuf header after NPE transmission
- * Since there is nothing changed by the NPE, there is no need
- * to process anything but the update of internal stats
- * when they are enabled
-*/
-PRIVATE void
-ixEthAccMbufFromTxQ(IX_OSAL_MBUF *mbuf)
-{
-#ifndef NDEBUG
- /* test for unchained mbufs */
- if (IX_ETHACC_NE_NEXT(mbuf) == 0)
- {
- /* unchained mbufs : update the stats */
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.unchainedTxDoneMBufs);
- }
- else
- {
- /* chained mbufs : walk the chain and update the stats */
- IX_OSAL_MBUF *ptr = mbuf;
-
- do
- {
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.chainedTxDoneMBufs);
- ptr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(ptr);
- }
- while (ptr != NULL);
- }
-#endif
-}
-
-/* Convert the mbuf header after NPE reception */
-PRIVATE void
-ixEthAccMbufFromRxQ(IX_OSAL_MBUF *mbuf)
-{
- UINT32 len;
-
- /* endianess swap for tci and flags
- note: this is done only once, even for chained buffers */
- IX_ETHACC_NE_FLAGS(mbuf) = IX_OSAL_SWAP_BE_SHARED_SHORT(IX_ETHACC_NE_FLAGS(mbuf));
- IX_ETHACC_NE_VLANTCI(mbuf) = IX_OSAL_SWAP_BE_SHARED_SHORT(IX_ETHACC_NE_VLANTCI(mbuf));
-
- /* test for unchained mbufs */
- if (IX_ETHACC_NE_NEXT(mbuf) == 0)
- {
- /* unchained mbufs */
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.unchainedRxMBufs);
-
- /* get the frame length. it is the same than the buffer length */
- len = IX_OSAL_SWAP_BE_SHARED_LONG(IX_ETHACC_NE_LEN(mbuf));
- len &= IX_ETHNPE_ACC_PKTLENGTH_MASK;
- IX_OSAL_MBUF_PKT_LEN(mbuf) = IX_OSAL_MBUF_MLEN(mbuf) = len;
-
- /* clears the next packet field */
- IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mbuf) = NULL;
- }
- else
- {
- IX_OSAL_MBUF *ptr = mbuf;
- IX_OSAL_MBUF *nextPtr;
- UINT32 frmLen;
-
- /* convert the frame length */
- frmLen = IX_OSAL_SWAP_BE_SHARED_LONG(IX_ETHACC_NE_LEN(mbuf));
- IX_OSAL_MBUF_PKT_LEN(mbuf) = (frmLen & IX_ETHNPE_ACC_PKTLENGTH_MASK);
-
- /* chained mbufs */
- do
- {
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.chainedRxMBufs);
-
- /* convert the length */
- len = IX_OSAL_SWAP_BE_SHARED_LONG(IX_ETHACC_NE_LEN(ptr));
- IX_OSAL_MBUF_MLEN(ptr) = (len >> IX_ETHNPE_ACC_LENGTH_OFFSET);
-
- /* get the next pointer */
- PTR_NPE2VIRT(IX_OSAL_MBUF *,IX_ETHACC_NE_NEXT(ptr), nextPtr);
- if (nextPtr != NULL)
- {
- nextPtr = (IX_OSAL_MBUF *)((UINT8 *)nextPtr - offsetof(IX_OSAL_MBUF,ix_ne));
- }
- /* set the next pointer */
- IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(ptr) = nextPtr;
-
- /* move to the next buffer */
- ptr = nextPtr;
- }
- while (ptr != NULL);
- }
-}
-
-/* write to qmgr if possible and report an overflow if not possible
- * Use a fast lock to protect the queue write.
- * This way, the tx feature is reentrant.
- */
-PRIVATE IX_STATUS
-ixEthAccQmgrLockTxWrite(IxEthAccPortId portId, UINT32 qBuffer)
-{
- IX_STATUS qStatus;
- if (ixOsalFastMutexTryLock(&txWriteMutex[portId]) == IX_SUCCESS)
- {
- qStatus = ixQMgrQWrite(
- IX_ETH_ACC_PORT_TO_TX_Q_ID(portId),
- &qBuffer);
-#ifndef NDEBUG
- if (qStatus != IX_SUCCESS)
- {
- TX_STATS_INC(portId, txOverflow);
- }
-#endif
- ixOsalFastMutexUnlock(&txWriteMutex[portId]);
- }
- else
- {
- TX_STATS_INC(portId, txLock);
- qStatus = IX_QMGR_Q_OVERFLOW;
- }
- return qStatus;
-}
-
-/* write to qmgr if possible and report an overflow if not possible
- * Use a fast lock to protect the queue write.
- * This way, the Rx feature is reentrant.
- */
-PRIVATE IX_STATUS
-ixEthAccQmgrLockRxWrite(IxEthAccPortId portId, UINT32 qBuffer)
-{
- IX_STATUS qStatus;
- if (ixOsalFastMutexTryLock(&rxWriteMutex[portId]) == IX_SUCCESS)
- {
- qStatus = ixQMgrQWrite(
- IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(portId),
- &qBuffer);
-#ifndef NDEBUG
- if (qStatus != IX_SUCCESS)
- {
- RX_STATS_INC(portId, rxFreeOverflow);
- }
-#endif
- ixOsalFastMutexUnlock(&rxWriteMutex[portId]);
- }
- else
- {
- RX_STATS_INC(portId, rxFreeLock);
- qStatus = IX_QMGR_Q_OVERFLOW;
- }
- return qStatus;
-}
-
-/*
- * Set the priority and write to a qmgr queue.
- */
-PRIVATE IX_STATUS
-ixEthAccQmgrTxWrite(IxEthAccPortId portId, UINT32 qBuffer, UINT32 priority)
-{
- /* fill the priority field */
- qBuffer |= (priority << IX_ETHNPE_QM_Q_FIELD_PRIOR_R);
-
- return ixEthAccQmgrLockTxWrite(portId, qBuffer);
-}
-
-/**
- *
- * @brief This function will discover the highest priority S/W Tx Q that
- * has entries in it
- *
- * @param portId - (in) the id of the port whose S/W Tx queues are to be searched
- * priorityPtr - (out) the priority of the highest priority occupied q will be written
- * here
- *
- * @return IX_ETH_ACC_SUCCESS if an occupied Q is found
- * IX_ETH_ACC_FAIL if no Q has entries
- *
- * @internal
- */
-PRIVATE IxEthAccStatus
-ixEthAccTxSwQHighestPriorityGet(IxEthAccPortId portId,
- IxEthAccTxPriority *priorityPtr)
-{
- if (ixEthAccPortData[portId].ixEthAccTxData.schDiscipline
- == FIFO_NO_PRIORITY)
- {
- if(IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(ixEthAccPortData[portId].
- ixEthAccTxData.txQ[IX_ETH_ACC_TX_DEFAULT_PRIORITY]))
- {
- return IX_ETH_ACC_FAIL;
- }
- else
- {
- *priorityPtr = IX_ETH_ACC_TX_DEFAULT_PRIORITY;
- TX_STATS_INC(portId,txPriority[*priorityPtr]);
- return IX_ETH_ACC_SUCCESS;
- }
- }
- else
- {
- IxEthAccTxPriority highestPriority = IX_ETH_ACC_TX_PRIORITY_7;
- while(1)
- {
- if(!IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(ixEthAccPortData[portId].
- ixEthAccTxData.txQ[highestPriority]))
- {
-
- *priorityPtr = highestPriority;
- TX_STATS_INC(portId,txPriority[highestPriority]);
- return IX_ETH_ACC_SUCCESS;
-
- }
- if (highestPriority == IX_ETH_ACC_TX_PRIORITY_0)
- {
- return IX_ETH_ACC_FAIL;
- }
- highestPriority--;
- }
- }
-}
-
-/**
- *
- * @brief This function will take a buffer from a TX S/W Q and attempt
- * to add it to the relevant TX H/W Q
- *
- * @param portId - the port whose TX queue is to be written to
- * priority - identifies the queue from which the entry is to be read
- *
- * @internal
- */
-PRIVATE IxEthAccStatus
-ixEthAccTxFromSwQ(IxEthAccPortId portId,
- IxEthAccTxPriority priority)
-{
- IX_OSAL_MBUF *mbuf;
- IX_STATUS qStatus;
-
- IX_OSAL_ENSURE((UINT32)priority <= (UINT32)7, "Invalid priority");
-
- IX_ETH_ACC_DATAPLANE_REMOVE_MBUF_FROM_Q_HEAD(
- ixEthAccPortData[portId].ixEthAccTxData.txQ[priority],
- mbuf);
-
- if (mbuf != NULL)
- {
- /*
- * Add the Tx buffer to the H/W Tx Q
- * We do not need to flush here as it is already done
- * in TxFrameSubmit().
- */
- qStatus = ixEthAccQmgrTxWrite(
- portId,
- IX_OSAL_MMU_VIRT_TO_PHYS((UINT32)IX_ETHACC_NE_SHARED(mbuf)),
- priority);
-
- if (qStatus == IX_SUCCESS)
- {
- TX_STATS_INC(portId,txFromSwQOK);
- return IX_SUCCESS;
- }
- else if (qStatus == IX_QMGR_Q_OVERFLOW)
- {
- /*
- * H/W Q overflow, need to save the buffer
- * back on the s/w Q.
- * we must put it back on the head of the q to avoid
- * reordering packet tx
- */
- TX_STATS_INC(portId,txFromSwQDelayed);
- IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD(
- ixEthAccPortData[portId].ixEthAccTxData.txQ[priority],
- mbuf);
-
- /*enable Q notification*/
- qStatus = ixQMgrNotificationEnable(
- IX_ETH_ACC_PORT_TO_TX_Q_ID(portId),
- IX_ETH_ACC_PORT_TO_TX_Q_SOURCE(portId));
-
- if (qStatus != IX_SUCCESS && qStatus != IX_QMGR_WARNING)
- {
- TX_INC(portId,txUnexpectedError);
- IX_ETH_ACC_FATAL_LOG(
- "ixEthAccTxFromSwQ:Unexpected Error: %u\n",
- qStatus, 0, 0, 0, 0, 0);
- }
- }
- else
- {
- TX_INC(portId,txUnexpectedError);
-
- /* recovery attempt */
- IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD(
- ixEthAccPortData[portId].ixEthAccTxData.txQ[priority],
- mbuf);
-
- IX_ETH_ACC_FATAL_LOG(
- "ixEthAccTxFromSwQ:Error: unexpected QM status 0x%08X\n",
- qStatus, 0, 0, 0, 0, 0);
- }
- }
- else
- {
- /* sw queue is empty */
- }
- return IX_ETH_ACC_FAIL;
-}
-
-/**
- *
- * @brief This function will take a buffer from a RXfree S/W Q and attempt
- * to add it to the relevant RxFree H/W Q
- *
- * @param portId - the port whose RXFree queue is to be written to
- *
- * @internal
- */
-PRIVATE IxEthAccStatus
-ixEthAccRxFreeFromSwQ(IxEthAccPortId portId)
-{
- IX_OSAL_MBUF *mbuf;
- IX_STATUS qStatus = IX_SUCCESS;
-
- IX_ETH_ACC_DATAPLANE_REMOVE_MBUF_FROM_Q_HEAD(
- ixEthAccPortData[portId].ixEthAccRxData.freeBufferList,
- mbuf);
- if (mbuf != NULL)
- {
- /*
- * Add The Rx Buffer to the H/W Free buffer Q if possible
- */
- qStatus = ixEthAccQmgrLockRxWrite(portId,
- IX_OSAL_MMU_VIRT_TO_PHYS(
- (UINT32)IX_ETHACC_NE_SHARED(mbuf)));
-
- if (qStatus == IX_SUCCESS)
- {
- RX_STATS_INC(portId,rxFreeRepFromSwQOK);
- /*
- * Buffer added to h/w Q.
- */
- return IX_SUCCESS;
- }
- else if (qStatus == IX_QMGR_Q_OVERFLOW)
- {
- /*
- * H/W Q overflow, need to save the buffer back on the s/w Q.
- */
- RX_STATS_INC(portId,rxFreeRepFromSwQDelayed);
-
- IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD(
- ixEthAccPortData[portId].ixEthAccRxData.freeBufferList,
- mbuf);
- }
- else
- {
- /* unexpected qmgr error */
- RX_INC(portId,rxUnexpectedError);
-
- IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD(
- ixEthAccPortData[portId].ixEthAccRxData.freeBufferList,
- mbuf);
-
- IX_ETH_ACC_FATAL_LOG("IxEthAccRxFreeFromSwQ:Error: unexpected QM status 0x%08X\n",
- qStatus, 0, 0, 0, 0, 0);
- }
- }
- else
- {
- /* sw queue is empty */
- }
- return IX_ETH_ACC_FAIL;
-}
-
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccInitDataPlane()
-{
- UINT32 portId;
-
- /*
- * Initialize the service and register callback to other services.
- */
-
- IX_ETH_ACC_MEMSET(&ixEthAccDataStats,
- 0,
- sizeof(ixEthAccDataStats));
-
- for(portId=0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
- {
- ixOsalFastMutexInit(&txWriteMutex[portId]);
- ixOsalFastMutexInit(&rxWriteMutex[portId]);
-
- IX_ETH_ACC_MEMSET(&ixEthAccPortData[portId],
- 0,
- sizeof(ixEthAccPortData[portId]));
-
- ixEthAccPortData[portId].ixEthAccTxData.schDiscipline = FIFO_NO_PRIORITY;
- }
-
- return (IX_ETH_ACC_SUCCESS);
-}
-
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccPortTxDoneCallbackRegister(IxEthAccPortId portId,
- IxEthAccPortTxDoneCallback
- txCallbackFn,
- UINT32 callbackTag)
-{
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
- if (!IX_ETH_ACC_IS_PORT_VALID(portId))
- {
- return (IX_ETH_ACC_INVALID_PORT);
- }
-
-/* HACK: removing this code to enable NPE-A preliminary testing
- * if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- * {
- * IX_ETH_ACC_WARNING_LOG("ixEthAccPortTxDoneCallbackRegister: Unavailable Eth %d: Cannot register TxDone Callback.\n",(INT32)portId,0,0,0,0,0);
- * return IX_ETH_ACC_SUCCESS ;
- * }
- */
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
- if (txCallbackFn == 0)
- /* Check for null function pointer here. */
- {
- return (IX_ETH_ACC_INVALID_ARG);
- }
- ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn = txCallbackFn;
- ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag = callbackTag;
- return (IX_ETH_ACC_SUCCESS);
-}
-
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccPortRxCallbackRegister(IxEthAccPortId portId,
- IxEthAccPortRxCallback
- rxCallbackFn,
- UINT32 callbackTag)
-{
- IxEthAccPortId port;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
- if (!IX_ETH_ACC_IS_PORT_VALID(portId))
- {
- return (IX_ETH_ACC_INVALID_PORT);
- }
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("ixEthAccPortRxCallbackRegister: Unavailable Eth %d: Cannot register Rx Callback.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /* Check for null function pointer here. */
- if (rxCallbackFn == NULL)
- {
- return (IX_ETH_ACC_INVALID_ARG);
- }
-
- /* Check the user is not changing the callback type
- * when the port is enabled.
- */
- if (ixEthAccMacState[portId].portDisableState == ACTIVE)
- {
- for (port = 0; port < IX_ETH_ACC_NUMBER_OF_PORTS; port++)
- {
- if ((ixEthAccMacState[port].portDisableState == ACTIVE)
- && (ixEthAccPortData[port].ixEthAccRxData.rxMultiBufferCallbackInUse == true))
- {
- /* one of the active ports has a different rx callback type.
- * Changing the callback type when the port is enabled
- * is not safe
- */
- return (IX_ETH_ACC_INVALID_ARG);
- }
- }
- }
-
- /* update the callback pointer : this is done before
- * registering the new qmgr callback
- */
- ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn = rxCallbackFn;
- ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag = callbackTag;
-
- /* update the qmgr callback for rx queues */
- if (ixEthAccQMgrRxCallbacksRegister(ixEthRxFrameQMCallback)
- != IX_ETH_ACC_SUCCESS)
- {
- /* unexpected qmgr error */
- IX_ETH_ACC_FATAL_LOG("ixEthAccPortRxCallbackRegister: unexpected QMgr error, " \
- "could not register Rx single-buffer callback\n", 0, 0, 0, 0, 0, 0);
-
- RX_INC(portId,rxUnexpectedError);
- return (IX_ETH_ACC_INVALID_ARG);
- }
-
- ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackInUse = false;
-
- return (IX_ETH_ACC_SUCCESS);
-}
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccPortMultiBufferRxCallbackRegister(
- IxEthAccPortId portId,
- IxEthAccPortMultiBufferRxCallback
- rxCallbackFn,
- UINT32 callbackTag)
-{
- IxEthAccPortId port;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
- if (!IX_ETH_ACC_IS_PORT_VALID(portId))
- {
- return (IX_ETH_ACC_INVALID_PORT);
- }
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("ixEthAccPortMultiBufferRxCallbackRegister: Unavailable Eth %d: Cannot register Rx Callback.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /* Check for null function pointer here. */
- if (rxCallbackFn == NULL)
- {
- return (IX_ETH_ACC_INVALID_ARG);
- }
-
- /* Check the user is not changing the callback type
- * when the port is enabled.
- */
- if (ixEthAccMacState[portId].portDisableState == ACTIVE)
- {
- for (port = 0; port < IX_ETH_ACC_NUMBER_OF_PORTS; port++)
- {
- if ((ixEthAccMacState[port].portDisableState == ACTIVE)
- && (ixEthAccPortData[port].ixEthAccRxData.rxMultiBufferCallbackInUse == false))
- {
- /* one of the active ports has a different rx callback type.
- * Changing the callback type when the port is enabled
- * is not safe
- */
- return (IX_ETH_ACC_INVALID_ARG);
- }
- }
- }
-
- /* update the callback pointer : this is done before
- * registering the new qmgr callback
- */
- ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn = rxCallbackFn;
- ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackTag = callbackTag;
-
- /* update the qmgr callback for rx queues */
- if (ixEthAccQMgrRxCallbacksRegister(ixEthRxMultiBufferQMCallback)
- != IX_ETH_ACC_SUCCESS)
- {
- /* unexpected qmgr error */
- RX_INC(portId,rxUnexpectedError);
-
- IX_ETH_ACC_FATAL_LOG("ixEthAccPortMultiBufferRxCallbackRegister: unexpected QMgr error, " \
- "could not register Rx multi-buffer callback\n", 0, 0, 0, 0, 0, 0);
-
- return (IX_ETH_ACC_INVALID_ARG);
- }
-
- ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackInUse = true;
-
- return (IX_ETH_ACC_SUCCESS);
-}
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccPortTxFrameSubmit(IxEthAccPortId portId,
- IX_OSAL_MBUF *buffer,
- IxEthAccTxPriority priority)
-{
- IX_STATUS qStatus = IX_SUCCESS;
- UINT32 qBuffer;
- IxEthAccTxPriority highestPriority;
- IxQMgrQStatus txQStatus;
-
-#ifndef NDEBUG
- if (buffer == NULL)
- {
- return (IX_ETH_ACC_FAIL);
- }
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
- if (!IX_ETH_ACC_IS_PORT_VALID(portId))
- {
- return (IX_ETH_ACC_INVALID_PORT);
- }
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_FATAL_LOG("ixEthAccPortTxFrameSubmit: Unavailable Eth %d: Cannot submit Tx Frame.\n",
- (INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_PORT_UNINITIALIZED ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
- if ((UINT32)priority > (UINT32)IX_ETH_ACC_TX_PRIORITY_7)
- {
- return (IX_ETH_ACC_INVALID_ARG);
- }
-#endif
-
- /*
- * Need to Flush the MBUF and its contents (data) as it may be
- * read from the NPE. Convert virtual addresses to physical addresses also.
- */
- qBuffer = ixEthAccMbufTxQPrepare(buffer);
-
- /*
- * If no fifo priority set on Xscale ...
- */
- if (ixEthAccPortData[portId].ixEthAccTxData.schDiscipline ==
- FIFO_NO_PRIORITY)
- {
- /*
- * Add The Tx Buffer to the H/W Tx Q if possible
- * (the priority is passed to the NPE, because
- * the NPE is able to reorder the frames
- * before transmission to the underlying hardware)
- */
- qStatus = ixEthAccQmgrTxWrite(portId,
- qBuffer,
- IX_ETH_ACC_TX_DEFAULT_PRIORITY);
-
- if (qStatus == IX_SUCCESS)
- {
- TX_STATS_INC(portId,txQOK);
-
- /*
- * "best case" scenario : Buffer added to h/w Q.
- */
- return (IX_SUCCESS);
- }
- else if (qStatus == IX_QMGR_Q_OVERFLOW)
- {
- /*
- * We were unable to write the buffer to the
- * appropriate H/W Q, Save it in the sw Q.
- * (use the default priority queue regardless of
- * input parameter)
- */
- priority = IX_ETH_ACC_TX_DEFAULT_PRIORITY;
- }
- else
- {
- /* unexpected qmgr error */
- TX_INC(portId,txUnexpectedError);
- IX_ETH_ACC_FATAL_LOG(
- "ixEthAccPortTxFrameSubmit:Error: qStatus = %u\n",
- (UINT32)qStatus, 0, 0, 0, 0, 0);
- return (IX_ETH_ACC_FAIL);
- }
- }
- else if (ixEthAccPortData[portId].ixEthAccTxData.schDiscipline ==
- FIFO_PRIORITY)
- {
-
- /*
- * For priority transmission, put the frame directly on the H/W queue
- * if the H/W queue is empty, otherwise, put it in a S/W Q
- */
- ixQMgrQStatusGet(IX_ETH_ACC_PORT_TO_TX_Q_ID(portId), &txQStatus);
- if((txQStatus & IX_QMGR_Q_STATUS_E_BIT_MASK) != 0)
- {
- /*The tx queue is empty, check whether there are buffers on the s/w queues*/
- if(ixEthAccTxSwQHighestPriorityGet(portId, &highestPriority)
- !=IX_ETH_ACC_FAIL)
- {
- /*there are buffers on the s/w queues, submit them*/
- ixEthAccTxFromSwQ(portId, highestPriority);
-
- /* the queue was empty, 1 buffer is already supplied
- * but is likely to be immediately transmitted and the
- * hw queue is likely to be empty again, so submit
- * more from the sw queues
- */
- if(ixEthAccTxSwQHighestPriorityGet(portId, &highestPriority)
- !=IX_ETH_ACC_FAIL)
- {
- ixEthAccTxFromSwQ(portId, highestPriority);
- /*
- * and force the buffer supplied to be placed
- * on a priority queue
- */
- qStatus = IX_QMGR_Q_OVERFLOW;
- }
- else
- {
- /*there are no buffers in the s/w queues, submit directly*/
- qStatus = ixEthAccQmgrTxWrite(portId, qBuffer, priority);
- }
- }
- else
- {
- /*there are no buffers in the s/w queues, submit directly*/
- qStatus = ixEthAccQmgrTxWrite(portId, qBuffer, priority);
- }
- }
- else
- {
- qStatus = IX_QMGR_Q_OVERFLOW;
- }
- }
- else
- {
- TX_INC(portId,txUnexpectedError);
- IX_ETH_ACC_FATAL_LOG(
- "ixEthAccPortTxFrameSubmit:Error: wrong schedule discipline setup\n",
- 0, 0, 0, 0, 0, 0);
- return (IX_ETH_ACC_FAIL);
- }
-
- if(qStatus == IX_SUCCESS )
- {
- TX_STATS_INC(portId,txQOK);
- return IX_ETH_ACC_SUCCESS;
- }
- else if(qStatus == IX_QMGR_Q_OVERFLOW)
- {
- TX_STATS_INC(portId,txQDelayed);
- /*
- * We were unable to write the buffer to the
- * appropriate H/W Q, Save it in a s/w Q.
- */
- IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_TAIL(
- ixEthAccPortData[portId].
- ixEthAccTxData.txQ[priority],
- buffer);
-
- qStatus = ixQMgrNotificationEnable(
- IX_ETH_ACC_PORT_TO_TX_Q_ID(portId),
- IX_ETH_ACC_PORT_TO_TX_Q_SOURCE(portId));
-
- if (qStatus != IX_SUCCESS)
- {
- if (qStatus == IX_QMGR_WARNING)
- {
- /* notification is enabled for a queue
- * which is already empty (the condition is already met)
- * and there will be no more queue event to drain the sw queue
- */
- TX_STATS_INC(portId,txLateNotificationEnabled);
-
- /* pull a buffer from the sw queue */
- if(ixEthAccTxSwQHighestPriorityGet(portId, &highestPriority)
- !=IX_ETH_ACC_FAIL)
- {
- /*there are buffers on the s/w queues, submit from them*/
- ixEthAccTxFromSwQ(portId, highestPriority);
- }
- }
- else
- {
- TX_INC(portId,txUnexpectedError);
- IX_ETH_ACC_FATAL_LOG(
- "ixEthAccPortTxFrameSubmit: unexpected Error: %u\n",
- qStatus, 0, 0, 0, 0, 0);
- }
- }
- }
- else
- {
- TX_INC(portId,txUnexpectedError);
- IX_ETH_ACC_FATAL_LOG(
- "ixEthAccPortTxFrameSubmit: unexpected Error: %u\n",
- qStatus, 0, 0, 0, 0, 0);
- return (IX_ETH_ACC_FAIL);
- }
-
- return (IX_ETH_ACC_SUCCESS);
-}
-
-
-/**
- *
- * @brief replenish: convert a chain of mbufs to the format
- * expected by the NPE
- *
- */
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccPortRxFreeReplenish(IxEthAccPortId portId,
- IX_OSAL_MBUF *buffer)
-{
- IX_STATUS qStatus = IX_SUCCESS;
- UINT32 qBuffer;
-
- /*
- * Check buffer is valid.
- */
-
-#ifndef NDEBUG
- /* check parameter value */
- if (buffer == 0)
- {
- return (IX_ETH_ACC_FAIL);
- }
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
- if (!IX_ETH_ACC_IS_PORT_VALID(portId))
- {
- return (IX_ETH_ACC_INVALID_PORT);
- }
-
- /* check initialisation is done */
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_FATAL_LOG(" ixEthAccPortRxFreeReplenish: Unavailable Eth %d: Cannot replenish Rx Free Q.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_PORT_UNINITIALIZED ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
- /* check boundaries and constraints */
- if (IX_OSAL_MBUF_MLEN(buffer) < IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN)
- {
- return (IX_ETH_ACC_FAIL);
- }
-#endif
-
- qBuffer = ixEthAccMbufRxQPrepare(buffer);
-
- /*
- * Add The Rx Buffer to the H/W Free buffer Q if possible
- */
- qStatus = ixEthAccQmgrLockRxWrite(portId, qBuffer);
-
- if (qStatus == IX_SUCCESS)
- {
- RX_STATS_INC(portId,rxFreeRepOK);
- /*
- * Buffer added to h/w Q.
- */
- return (IX_SUCCESS);
- }
- else if (qStatus == IX_QMGR_Q_OVERFLOW)
- {
- RX_STATS_INC(portId,rxFreeRepDelayed);
- /*
- * We were unable to write the buffer to the approprate H/W Q,
- * Save it in a s/w Q.
- */
- IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_TAIL(
- ixEthAccPortData[portId].ixEthAccRxData.freeBufferList,
- buffer);
-
- qStatus = ixQMgrNotificationEnable(
- IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(portId),
- IX_ETH_ACC_PORT_TO_RX_FREE_Q_SOURCE(portId));
-
- if (qStatus != IX_SUCCESS)
- {
- if (qStatus == IX_QMGR_WARNING)
- {
- /* notification is enabled for a queue
- * which is already empty (the condition is already met)
- * and there will be no more queue event to drain the sw queue
- * move an entry from the sw queue to the hw queue */
- RX_STATS_INC(portId,rxFreeLateNotificationEnabled);
- ixEthAccRxFreeFromSwQ(portId);
- }
- else
- {
- RX_INC(portId,rxUnexpectedError);
- IX_ETH_ACC_FATAL_LOG(
- "ixEthAccRxPortFreeReplenish:Error: %u\n",
- qStatus, 0, 0, 0, 0, 0);
- }
- }
- }
- else
- {
- RX_INC(portId,rxUnexpectedError);
- IX_ETH_ACC_FATAL_LOG(
- "ixEthAccRxPortFreeReplenish:Error: qStatus = %u\n",
- (UINT32)qStatus, 0, 0, 0, 0, 0);
- return(IX_ETH_ACC_FAIL);
- }
- return (IX_ETH_ACC_SUCCESS);
-}
-
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccTxSchedulingDisciplineSetPriv(IxEthAccPortId portId,
- IxEthAccSchedulerDiscipline
- sched)
-{
- if (!IX_ETH_ACC_IS_PORT_VALID(portId))
- {
- return (IX_ETH_ACC_INVALID_PORT);
- }
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("ixEthAccTxSchedulingDisciplineSet: Unavailable Eth %d: Cannot set Tx Scheduling Discipline.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- if (sched != FIFO_PRIORITY && sched != FIFO_NO_PRIORITY)
- {
- return (IX_ETH_ACC_INVALID_ARG);
- }
-
- ixEthAccPortData[portId].ixEthAccTxData.schDiscipline = sched;
- return (IX_ETH_ACC_SUCCESS);
-}
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccRxSchedulingDisciplineSetPriv(IxEthAccSchedulerDiscipline
- sched)
-{
- if (sched != FIFO_PRIORITY && sched != FIFO_NO_PRIORITY)
- {
- return (IX_ETH_ACC_INVALID_ARG);
- }
-
- ixEthAccDataInfo.schDiscipline = sched;
-
- return (IX_ETH_ACC_SUCCESS);
-}
-
-
-/**
- * @fn ixEthRxFrameProcess(IxEthAccPortId portId, IX_OSAL_MBUF *mbufPtr)
- *
- * @brief process incoming frame :
- *
- * @param @ref IxQMgrCallback IxQMgrMultiBufferCallback
- *
- * @return none
- *
- * @internal
- *
- */
-IX_ETH_ACC_PRIVATE BOOL
-ixEthRxFrameProcess(IxEthAccPortId portId, IX_OSAL_MBUF *mbufPtr)
-{
- UINT32 flags;
- IxEthDBStatus result;
-
-#ifndef NDEBUG
- /* Prudent to at least check the port is within range */
- if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS)
- {
- ixEthAccDataStats.unexpectedError++;
- IX_ETH_ACC_FATAL_LOG(
- "ixEthRxFrameProcess: Illegal port: %u\n",
- (UINT32)portId, 0, 0, 0, 0, 0);
- return false;
- }
-#endif
-
- /* convert fields from mbuf header */
- ixEthAccMbufFromRxQ(mbufPtr);
-
- /* check about any special processing for this frame */
- flags = IX_ETHACC_NE_FLAGS(mbufPtr);
- if ((flags & (IX_ETHACC_NE_FILTERMASK | IX_ETHACC_NE_NEWSRCMASK)) == 0)
- {
- /* "best case" scenario : nothing special to do for this frame */
- return true;
- }
-
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
- /* if a new source MAC address is detected by the NPE,
- * update IxEthDB with the portId and the MAC address.
- */
- if ((flags & IX_ETHACC_NE_NEWSRCMASK & ixEthAccNewSrcMask) != 0)
- {
- result = ixEthDBFilteringDynamicEntryProvision(portId,
- (IxEthDBMacAddr *) IX_ETHACC_NE_SOURCEMAC(mbufPtr));
-
- if (result != IX_ETH_DB_SUCCESS && result != IX_ETH_DB_FEATURE_UNAVAILABLE)
- {
- if ((ixEthAccMacState[portId].portDisableState == ACTIVE) && (result != IX_ETH_DB_BUSY))
- {
- RX_STATS_INC(portId, rxUnexpectedError);
- IX_ETH_ACC_FATAL_LOG("ixEthRxFrameProcess: Failed to add source MAC \
- to the Learning/Filtering database\n", 0, 0, 0, 0, 0, 0);
- }
- else
- {
- /* we expect this to fail during PortDisable, as EthDB is disabled for
- * that port and will refuse to learn new addresses
- */
- }
- }
- else
- {
- RX_STATS_INC(portId, rxUnlearnedMacAddress);
- }
- }
-#endif
-
- /* check if this frame should have been filtered
- * by the NPE and take the appropriate action
- */
- if (((flags & IX_ETHACC_NE_FILTERMASK) != 0)
- && (ixEthAccMacState[portId].portDisableState == ACTIVE))
- {
- /* If the mbuf was allocated with a small data size, or the current data pointer is not
- * within the allocated data area, then the buffer is non-standard and has to be
- * replenished with the minimum size only
- */
- if( (IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(mbufPtr) < IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN)
- || ((UINT8 *)IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(mbufPtr) > IX_OSAL_MBUF_MDATA(mbufPtr))
- || ((UINT8 *)(IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(mbufPtr) +
- IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(mbufPtr))
- < IX_OSAL_MBUF_MDATA(mbufPtr)) )
- {
- /* set to minimum length */
- IX_OSAL_MBUF_MLEN(mbufPtr) = IX_OSAL_MBUF_PKT_LEN(mbufPtr) =
- IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN;
- }
- else
- {
- /* restore original length */
- IX_OSAL_MBUF_MLEN(mbufPtr) = IX_OSAL_MBUF_PKT_LEN(mbufPtr) =
- ( IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(mbufPtr) -
- (IX_OSAL_MBUF_MDATA(mbufPtr) - (UINT8 *)IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(mbufPtr)) );
- }
-
- /* replenish from here */
- if (ixEthAccPortRxFreeReplenish(portId, mbufPtr) != IX_ETH_ACC_SUCCESS)
- {
- IX_ETH_ACC_FATAL_LOG("ixEthRxFrameProcess: Failed to replenish with filtered frame\
- on port %d\n", portId, 0, 0, 0, 0, 0);
- }
-
- RX_STATS_INC(portId, rxFiltered);
-
- /* indicate that frame should not be subjected to further processing */
- return false;
- }
-
- return true;
-}
-
-
-/**
- * @fn ixEthRxFrameQMCallback
- *
- * @brief receive callback for Frame receive Q from NPE
- *
- * Frames are passed one-at-a-time to the user
- *
- * @param @ref IxQMgrCallback
- *
- * @return none
- *
- * @internal
- *
- * Design note : while processing the entry X, entry X+1 is preloaded
- * into memory to reduce the number of stall cycles
- *
- */
-void ixEthRxFrameQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId)
-{
- IX_OSAL_MBUF *mbufPtr;
- IX_OSAL_MBUF *nextMbufPtr;
- UINT32 qEntry;
- UINT32 nextQEntry;
- UINT32 *qEntryPtr;
- UINT32 portId;
- UINT32 destPortId;
- UINT32 npeId;
- UINT32 rxQReadStatus;
-
- /*
- * Design note : entries are read in a buffer, This buffer contains
- * an extra zeroed entry so the loop will
- * always terminate on a null entry, whatever the result of Burst read is.
- */
- UINT32 rxQEntry[IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK + 1];
-
- /*
- * Indication of the number of times the callback is used.
- */
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.rxCallbackCounter);
-
- do
- {
- /*
- * Indication of the number of times the queue is drained
- */
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.rxCallbackBurstRead);
-
- /* ensure the last entry of the array contains a zeroed value */
- qEntryPtr = rxQEntry;
- qEntryPtr[IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK] = 0;
-
- rxQReadStatus = ixQMgrQBurstRead(qId,
- IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK,
- qEntryPtr);
-
-#ifndef NDEBUG
- if ((rxQReadStatus != IX_QMGR_Q_UNDERFLOW)
- && (rxQReadStatus != IX_SUCCESS))
- {
- ixEthAccDataStats.unexpectedError++;
- /*major error*/
- IX_ETH_ACC_FATAL_LOG(
- "ixEthRxFrameQMCallback:Error: %u\n",
- (UINT32)rxQReadStatus, 0, 0, 0, 0, 0);
- return;
- }
-#endif
-
- /* convert and preload the next entry
- * (the conversion function takes care about null pointers which
- * are used to mark the end of the loop)
- */
- nextQEntry = *qEntryPtr;
- nextMbufPtr = ixEthAccEntryFromQConvert(nextQEntry,
- IX_ETHNPE_QM_Q_RXENET_ADDR_MASK);
-
- while(nextQEntry != 0)
- {
- /* get the next entry */
- qEntry = nextQEntry;
- mbufPtr = nextMbufPtr;
-
-#ifndef NDEBUG
- if (mbufPtr == NULL)
- {
- ixEthAccDataStats.unexpectedError++;
- IX_ETH_ACC_FATAL_LOG(
- "ixEthRxFrameQMCallback: Null Mbuf Ptr\n",
- 0, 0, 0, 0, 0, 0);
- return;
- }
-#endif
-
- /* convert the next entry
- * (the conversion function takes care about null pointers which
- * are used to mark the end of the loop)
- */
- nextQEntry = *(++qEntryPtr);
- nextMbufPtr = ixEthAccEntryFromQConvert(nextQEntry,
- IX_ETHNPE_QM_Q_RXENET_ADDR_MASK);
-
- /*
- * Get Port and Npe ID from message.
- */
- npeId = ((IX_ETHNPE_QM_Q_RXENET_NPEID_MASK &
- qEntry) >> IX_ETHNPE_QM_Q_FIELD_NPEID_R);
- portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId);
-
- /* process frame, check the return code and skip the remaining of
- * the loop if the frame is to be filtered out
- */
- if (ixEthRxFrameProcess(portId, mbufPtr))
- {
- /* destination portId for this packet */
- destPortId = IX_ETHACC_NE_DESTPORTID(mbufPtr);
-
- if (destPortId != IX_ETH_DB_UNKNOWN_PORT)
- {
- destPortId = IX_ETH_DB_NPE_LOGICAL_ID_TO_PORT_ID(destPortId);
- }
-
- /* test if QoS is enabled in ethAcc
- */
- if (ixEthAccDataInfo.schDiscipline == FIFO_PRIORITY)
- {
- /* check if there is a higher priority queue
- * which may require processing and then process it.
- */
- if (ixEthAccDataInfo.higherPriorityQueue[qId] < IX_QMGR_MAX_NUM_QUEUES)
- {
- ixEthRxFrameQMCallback(ixEthAccDataInfo.higherPriorityQueue[qId],
- callbackId);
- }
- }
-
- /*
- * increment priority stats
- */
- RX_STATS_INC(portId,rxPriority[IX_ETHACC_NE_QOS(mbufPtr)]);
-
- /*
- * increment callback count stats
- */
- RX_STATS_INC(portId,rxFrameClientCallback);
-
- /*
- * Call user level callback.
- */
- ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn(
- ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag,
- mbufPtr,
- destPortId);
- }
- }
- } while (rxQReadStatus == IX_SUCCESS);
-}
-
-/**
- * @fn ixEthRxMultiBufferQMCallback
- *
- * @brief receive callback for Frame receive Q from NPE
- *
- * Frames are passed as an array to the user
- *
- * @param @ref IxQMgrCallback
- *
- * @return none
- *
- * @internal
- *
- * Design note : while processing the entry X, entry X+1 is preloaded
- * into memory to reduce the number of stall cycles
- *
- */
-void ixEthRxMultiBufferQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId)
-{
- IX_OSAL_MBUF *mbufPtr;
- IX_OSAL_MBUF *nextMbufPtr;
- UINT32 qEntry;
- UINT32 nextQEntry;
- UINT32 *qEntryPtr;
- UINT32 portId;
- UINT32 npeId;
- UINT32 rxQReadStatus;
- /*
- * Design note : entries are read in a static buffer, This buffer contains
- * an extra zeroed entry so the loop will
- * always terminate on a null entry, whatever the result of Burst read is.
- */
- static UINT32 rxQEntry[IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK + 1];
- static IX_OSAL_MBUF *rxMbufPortArray[IX_ETH_ACC_NUMBER_OF_PORTS][IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK + 1];
- IX_OSAL_MBUF **rxMbufPtr[IX_ETH_ACC_NUMBER_OF_PORTS];
-
- for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
- {
- rxMbufPtr[portId] = rxMbufPortArray[portId];
- }
-
- /*
- * Indication of the number of times the callback is used.
- */
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.rxCallbackCounter);
-
- do
- {
- /*
- * Indication of the number of times the queue is drained
- */
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.rxCallbackBurstRead);
-
- /* ensure the last entry of the array contains a zeroed value */
- qEntryPtr = rxQEntry;
- qEntryPtr[IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK] = 0;
-
- rxQReadStatus = ixQMgrQBurstRead(qId,
- IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK,
- qEntryPtr);
-
-#ifndef NDEBUG
- if ((rxQReadStatus != IX_QMGR_Q_UNDERFLOW)
- && (rxQReadStatus != IX_SUCCESS))
- {
- ixEthAccDataStats.unexpectedError++;
- /*major error*/
- IX_ETH_ACC_FATAL_LOG(
- "ixEthRxFrameMultiBufferQMCallback:Error: %u\n",
- (UINT32)rxQReadStatus, 0, 0, 0, 0, 0);
- return;
- }
-#endif
-
- /* convert and preload the next entry
- * (the conversion function takes care about null pointers which
- * are used to mark the end of the loop)
- */
- nextQEntry = *qEntryPtr;
- nextMbufPtr = ixEthAccEntryFromQConvert(nextQEntry,
- IX_ETHNPE_QM_Q_RXENET_ADDR_MASK);
-
- while(nextQEntry != 0)
- {
- /* get the next entry */
- qEntry = nextQEntry;
- mbufPtr = nextMbufPtr;
-
-#ifndef NDEBUG
- if (mbufPtr == NULL)
- {
- ixEthAccDataStats.unexpectedError++;
- IX_ETH_ACC_FATAL_LOG(
- "ixEthRxFrameMultiBufferQMCallback:Error: Null Mbuf Ptr\n",
- 0, 0, 0, 0, 0, 0);
- return;
- }
-#endif
-
- /* convert the next entry
- * (the conversion function takes care about null pointers which
- * are used to mark the end of the loop)
- */
- nextQEntry = *(++qEntryPtr);
- nextMbufPtr = ixEthAccEntryFromQConvert(nextQEntry,
- IX_ETHNPE_QM_Q_RXENET_ADDR_MASK);
-
- /*
- * Get Port and Npe ID from message.
- */
- npeId = ((IX_ETHNPE_QM_Q_RXENET_NPEID_MASK &
- qEntry) >>
- IX_ETHNPE_QM_Q_FIELD_NPEID_R);
- portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId);
-
- /* skip the remaining of the loop if the frame is
- * to be filtered out
- */
- if (ixEthRxFrameProcess(portId, mbufPtr))
- {
- /* store a mbuf pointer in an array */
- *rxMbufPtr[portId]++ = mbufPtr;
-
- /*
- * increment priority stats
- */
- RX_STATS_INC(portId,rxPriority[IX_ETHACC_NE_QOS(mbufPtr)]);
- }
-
- /* test for QoS enabled in ethAcc */
- if (ixEthAccDataInfo.schDiscipline == FIFO_PRIORITY)
- {
- /* check if there is a higher priority queue
- * which may require processing and then process it.
- */
- if (ixEthAccDataInfo.higherPriorityQueue[qId] < IX_QMGR_MAX_NUM_QUEUES)
- {
- ixEthRxMultiBufferQMCallback(ixEthAccDataInfo.higherPriorityQueue[qId],
- callbackId);
- }
- }
- }
-
- /* check if any of the the arrays contains any entry */
- for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
- {
- if (rxMbufPtr[portId] != rxMbufPortArray[portId])
- {
- /* add a last NULL pointer at the end of the
- * array of mbuf pointers
- */
- *rxMbufPtr[portId] = NULL;
-
- /*
- * increment callback count stats
- */
- RX_STATS_INC(portId,rxFrameClientCallback);
-
- /*
- * Call user level callback with an array of
- * buffers (NULL terminated)
- */
- ixEthAccPortData[portId].ixEthAccRxData.
- rxMultiBufferCallbackFn(
- ixEthAccPortData[portId].ixEthAccRxData.
- rxMultiBufferCallbackTag,
- rxMbufPortArray[portId]);
-
- /* reset the buffer pointer to the beginning of
- * the array
- */
- rxMbufPtr[portId] = rxMbufPortArray[portId];
- }
- }
-
- } while (rxQReadStatus == IX_SUCCESS);
-}
-
-
-/**
- * @brief rxFree low event handler
- *
- */
-void ixEthRxFreeQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId)
-{
- IxEthAccPortId portId = (IxEthAccPortId) callbackId;
- int lockVal;
- UINT32 maxQWritesToPerform = IX_ETH_ACC_MAX_RX_FREE_BUFFERS_LOAD;
- IX_STATUS qStatus = IX_SUCCESS;
-
- /*
- * We have reached a low threshold on one of the Rx Free Qs
- */
-
- /*note that due to the fact that we are working off an Empty threshold, this callback
- need only write a single entry to the Rx Free queue in order to re-arm the notification
- */
-
- RX_STATS_INC(portId,rxFreeLowCallback);
-
- /*
- * Get buffers from approprite S/W Rx freeBufferList Q.
- */
-
-#ifndef NDEBUG
- if (!IX_ETH_ACC_IS_PORT_VALID(portId))
- {
- ixEthAccDataStats.unexpectedError++;
- IX_ETH_ACC_FATAL_LOG(
- "ixEthRxFreeQMCallback:Error: Invalid Port 0x%08X\n",
- portId, 0, 0, 0, 0, 0);
- return;
- }
-#endif
- IX_ETH_ACC_DATA_PLANE_LOCK(lockVal);
- if (IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(ixEthAccPortData[portId].
- ixEthAccRxData.freeBufferList))
- {
- /*
- * Turn off Q callback notification for Q in Question.
- */
- qStatus = ixQMgrNotificationDisable(
- IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(portId));
-
-
- IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal);
-
- if (qStatus != IX_SUCCESS)
- {
- RX_INC(portId,rxUnexpectedError);
- IX_ETH_ACC_FATAL_LOG(
- "ixEthRxFreeQMCallback:Error: unexpected QM status 0x%08X\n",
- qStatus, 0, 0, 0, 0, 0);
- return;
- }
- }
- else
- {
- IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal);
- /*
- * Load the H/W Q with buffers from the s/w Q.
- */
-
- do
- {
- /*
- * Consume Q entries. - Note Q contains Physical addresss,
- * and have already been flushed to memory,
- * And endianess converted if required.
- */
- if (ixEthAccRxFreeFromSwQ(portId) != IX_SUCCESS)
- {
- /*
- * No more entries in s/w Q.
- * Turn off Q callback indication
- */
-
- IX_ETH_ACC_DATA_PLANE_LOCK(lockVal);
- if (IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(ixEthAccPortData[portId].
- ixEthAccRxData.freeBufferList))
- {
- qStatus = ixQMgrNotificationDisable(
- IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(portId));
- }
- IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal);
- break;
- }
- }
- while (--maxQWritesToPerform);
- }
-}
-/**
- * @fn Tx queue low event handler
- *
- */
-void
-ixEthTxFrameQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId)
-{
- IxEthAccPortId portId = (IxEthAccPortId) callbackId;
- int lockVal;
- UINT32 maxQWritesToPerform = IX_ETH_ACC_MAX_TX_FRAME_TX_CONSUME_PER_CALLBACK;
- IX_STATUS qStatus = IX_SUCCESS;
- IxEthAccTxPriority highestPriority;
-
-
- /*
- * We have reached a low threshold on the Tx Q, and are being asked to
- * supply a buffer for transmission from our S/W TX queues
- */
- TX_STATS_INC(portId,txLowThreshCallback);
-
- /*
- * Get buffers from approprite Q.
- */
-
-#ifndef NDEBUG
- if (!IX_ETH_ACC_IS_PORT_VALID(portId))
- {
- ixEthAccDataStats.unexpectedError++;
- IX_ETH_ACC_FATAL_LOG(
- "ixEthTxFrameQMCallback:Error: Invalid Port 0x%08X\n",
- portId, 0, 0, 0, 0, 0);
- return;
- }
-#endif
-
- do
- {
- /*
- * Consume Q entries. - Note Q contains Physical addresss,
- * and have already been flushed to memory,
- * and endianess already sone if required.
- */
-
- IX_ETH_ACC_DATA_PLANE_LOCK(lockVal);
-
- if(ixEthAccTxSwQHighestPriorityGet(portId, &highestPriority) ==
- IX_ETH_ACC_FAIL)
- {
- /*
- * No more entries in s/w Q.
- * Turn off Q callback indication
- */
- qStatus = ixQMgrNotificationDisable(
- IX_ETH_ACC_PORT_TO_TX_Q_ID(portId));
-
- IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal);
-
- if (qStatus != IX_SUCCESS)
- {
- ixEthAccDataStats.unexpectedError++;
- IX_ETH_ACC_FATAL_LOG(
- "ixEthTxFrameQMCallback:Error: unexpected QM status 0x%08X\n",
- qStatus, 0, 0, 0, 0, 0);
- }
-
- return;
- }
- else
- {
- IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal);
- if (ixEthAccTxFromSwQ(portId,highestPriority)!=IX_SUCCESS)
- {
- /* nothing left in the sw queue or the hw queues are
- * full. There is no point to continue to drain the
- * sw queues
- */
- return;
- }
- }
- }
- while (--maxQWritesToPerform);
-}
-
-/**
- * @brief TxDone event handler
- *
- * Design note : while processing the entry X, entry X+1 is preloaded
- * into memory to reduce the number of stall cycles
- *
- */
-
-void
-ixEthTxFrameDoneQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId)
-{
- IX_OSAL_MBUF *mbufPtr;
- UINT32 qEntry;
- UINT32 *qEntryPtr;
- UINT32 txDoneQReadStatus;
- UINT32 portId;
- UINT32 npeId;
-
- /*
- * Design note : entries are read in a static buffer, This buffer contains
- * an extra entyry (which is zeroed by the compiler), so the loop will
- * always terminate on a null entry, whatever the result of Burst read is.
- */
- static UINT32 txDoneQEntry[IX_ETH_ACC_MAX_TX_FRAME_DONE_CONSUME_PER_CALLBACK + 1];
-
- /*
- * Indication that Tx frames have been transmitted from the NPE.
- */
-
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.txDoneCallbackCounter);
-
- do{
- qEntryPtr = txDoneQEntry;
- txDoneQReadStatus = ixQMgrQBurstRead(IX_ETH_ACC_TX_FRAME_DONE_ETH_Q,
- IX_ETH_ACC_MAX_TX_FRAME_DONE_CONSUME_PER_CALLBACK,
- qEntryPtr);
-
-#ifndef NDEBUG
- if (txDoneQReadStatus != IX_QMGR_Q_UNDERFLOW
- && (txDoneQReadStatus != IX_SUCCESS))
- {
- /*major error*/
- ixEthAccDataStats.unexpectedError++;
- IX_ETH_ACC_FATAL_LOG(
- "ixEthTxFrameDoneQMCallback:Error: %u\n",
- (UINT32)txDoneQReadStatus, 0, 0, 0, 0, 0);
- return;
- }
-#endif
-
- qEntry = *qEntryPtr;
-
- while(qEntry != 0)
- {
- mbufPtr = ixEthAccEntryFromQConvert(qEntry,
- IX_ETHNPE_QM_Q_TXENET_ADDR_MASK);
-
-#ifndef NDEBUG
- if (mbufPtr == NULL)
- {
- ixEthAccDataStats.unexpectedError++;
- IX_ETH_ACC_FATAL_LOG(
- "ixEthTxFrameDoneQMCallback:Error: Null Mbuf Ptr\n",
- 0, 0, 0, 0, 0, 0);
- return;
- }
-#endif
-
- /* endianness conversions and stats updates */
- ixEthAccMbufFromTxQ(mbufPtr);
-
- /*
- * Get NPE id from message, then convert to portId.
- */
- npeId = ((IX_ETHNPE_QM_Q_TXENETDONE_NPEID_MASK &
- qEntry) >>
- IX_ETHNPE_QM_Q_FIELD_NPEID_R);
- portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId);
-
-#ifndef NDEBUG
- /* Prudent to at least check the port is within range */
- if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS)
- {
- ixEthAccDataStats.unexpectedError++;
- IX_ETH_ACC_FATAL_LOG(
- "ixEthTxFrameDoneQMCallback: Illegal port: %u\n",
- (UINT32)portId, 0, 0, 0, 0, 0);
- return;
- }
-#endif
-
- TX_STATS_INC(portId,txDoneClientCallback);
-
- /*
- * Call user level callback.
- */
- ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn(
- ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag,
- mbufPtr);
-
- /* move to next queue entry */
- qEntry = *(++qEntryPtr);
-
- }
- } while( txDoneQReadStatus == IX_SUCCESS );
-}
-
-IX_ETH_ACC_PUBLIC
-void ixEthAccDataPlaneShow(void)
-{
- UINT32 numTx0Entries;
- UINT32 numTx1Entries;
- UINT32 numTxDoneEntries;
- UINT32 numRxEntries;
- UINT32 numRxFree0Entries;
- UINT32 numRxFree1Entries;
- UINT32 portId;
-#ifdef __ixp46X
- UINT32 numTx2Entries;
- UINT32 numRxFree2Entries;
-#endif
-#ifndef NDEBUG
- UINT32 priority;
- UINT32 numBuffersInRx=0;
- UINT32 numBuffersInTx=0;
- UINT32 numBuffersInSwQ=0;
- UINT32 totalBuffers=0;
- UINT32 rxFreeCallbackCounter = 0;
- UINT32 txCallbackCounter = 0;
-#endif
- UINT32 key;
-
- /* snapshot of stats */
- IxEthAccTxDataStats tx[IX_ETH_ACC_NUMBER_OF_PORTS];
- IxEthAccRxDataStats rx[IX_ETH_ACC_NUMBER_OF_PORTS];
- IxEthAccDataPlaneStats stats;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return;
- }
-
- /* get a reliable snapshot */
- key = ixOsalIrqLock();
-
- numTx0Entries = 0;
- ixQMgrQNumEntriesGet(IX_ETH_ACC_TX_FRAME_ENET0_Q, &numTx0Entries);
- numTx1Entries = 0;
- ixQMgrQNumEntriesGet(IX_ETH_ACC_TX_FRAME_ENET1_Q, &numTx1Entries);
- numTxDoneEntries = 0;
- ixQMgrQNumEntriesGet( IX_ETH_ACC_TX_FRAME_DONE_ETH_Q, &numTxDoneEntries);
- numRxEntries = 0;
- ixEthAccQMgrRxQEntryGet(&numRxEntries);
- numRxFree0Entries = 0;
- ixQMgrQNumEntriesGet(IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q, &numRxFree0Entries);
- numRxFree1Entries = 0;
- ixQMgrQNumEntriesGet(IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q, &numRxFree1Entries);
-
-#ifdef __ixp46X
- numTx2Entries = 0;
- ixQMgrQNumEntriesGet(IX_ETH_ACC_TX_FRAME_ENET2_Q, &numTx2Entries);
- numRxFree2Entries = 0;
- ixQMgrQNumEntriesGet(IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q, &numRxFree2Entries);
-#endif
-
- for(portId=IX_ETH_PORT_1; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
- {
- memcpy(&tx[portId],
- &ixEthAccPortData[portId].ixEthAccTxData.stats,
- sizeof(tx[portId]));
- memcpy(&rx[portId],
- &ixEthAccPortData[portId].ixEthAccRxData.stats,
- sizeof(rx[portId]));
- }
- memcpy(&stats, &ixEthAccDataStats, sizeof(stats));
-
- ixOsalIrqUnlock(key);
-
-#ifdef NDEBUG
- printf("Detailed statistics collection not supported in this load\n");
-#endif
-
- /* print snapshot */
- for(portId=0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
- {
- /* If not IXP42X A0 stepping, proceed to check for existence of coprocessors */
- if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
- (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
- || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
- {
- if ((IX_ETH_PORT_1 == portId) &&
- (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) ==
- IX_FEATURE_CTRL_COMPONENT_DISABLED))
- {
- continue ;
- }
- if ((IX_ETH_PORT_2 == portId) &&
- (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) ==
- IX_FEATURE_CTRL_COMPONENT_DISABLED))
- {
- continue ;
- }
- if ((IX_ETH_PORT_3 == portId) &&
- (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA_ETH) ==
- IX_FEATURE_CTRL_COMPONENT_DISABLED))
- {
- continue ;
- }
- }
-
- printf("PORT %u --------------------------------\n",
- portId);
-#ifndef NDEBUG
- printf("Tx Done Frames : %u\n",
- tx[portId].txDoneClientCallback +
- tx[portId].txDoneSwQDuringDisable +
- tx[portId].txDoneDuringDisable);
- printf("Tx Frames : %u\n",
- tx[portId].txQOK + tx[portId].txQDelayed);
- printf("Tx H/W Q Added OK : %u\n",
- tx[portId].txQOK);
- printf("Tx H/W Q Delayed : %u\n",
- tx[portId].txQDelayed);
- printf("Tx From S/W Q Added OK : %u\n",
- tx[portId].txFromSwQOK);
- printf("Tx From S/W Q Delayed : %u\n",
- tx[portId].txFromSwQDelayed);
- printf("Tx Overflow : %u\n",
- tx[portId].txOverflow);
- printf("Tx Mutual Lock : %u\n",
- tx[portId].txLock);
- printf("Tx Late Ntf Enabled : %u\n",
- tx[portId].txLateNotificationEnabled);
- printf("Tx Low Thresh CB : %u\n",
- tx[portId].txLowThreshCallback);
- printf("Tx Done from H/W Q (Disable) : %u\n",
- tx[portId].txDoneDuringDisable);
- printf("Tx Done from S/W Q (Disable) : %u\n",
- tx[portId].txDoneSwQDuringDisable);
- for (priority = IX_ETH_ACC_TX_PRIORITY_0;
- priority <= IX_ETH_ACC_TX_PRIORITY_7;
- priority++)
- {
- if (tx[portId].txPriority[priority])
- {
- printf("Tx Priority %u : %u\n",
- priority,
- tx[portId].txPriority[priority]);
- }
- }
-#endif
- printf("Tx unexpected errors : %u (should be 0)\n",
- tx[portId].txUnexpectedError);
-
-#ifndef NDEBUG
- printf("Rx Frames : %u\n",
- rx[portId].rxFrameClientCallback +
- rx[portId].rxSwQDuringDisable+
- rx[portId].rxDuringDisable);
- printf("Rx Free Replenish : %u\n",
- rx[portId].rxFreeRepOK + rx[portId].rxFreeRepDelayed);
- printf("Rx Free H/W Q Added OK : %u\n",
- rx[portId].rxFreeRepOK);
- printf("Rx Free H/W Q Delayed : %u\n",
- rx[portId].rxFreeRepDelayed);
- printf("Rx Free From S/W Q Added OK : %u\n",
- rx[portId].rxFreeRepFromSwQOK);
- printf("Rx Free From S/W Q Delayed : %u\n",
- rx[portId].rxFreeRepFromSwQDelayed);
- printf("Rx Free Overflow : %u\n",
- rx[portId].rxFreeOverflow);
- printf("Rx Free Mutual Lock : %u\n",
- rx[portId].rxFreeLock);
- printf("Rx Free Late Ntf Enabled : %u\n",
- rx[portId].rxFreeLateNotificationEnabled);
- printf("Rx Free Low CB : %u\n",
- rx[portId].rxFreeLowCallback);
- printf("Rx From H/W Q (Disable) : %u\n",
- rx[portId].rxDuringDisable);
- printf("Rx From S/W Q (Disable) : %u\n",
- rx[portId].rxSwQDuringDisable);
- printf("Rx unlearned Mac Address : %u\n",
- rx[portId].rxUnlearnedMacAddress);
- printf("Rx Filtered (Rx => RxFree) : %u\n",
- rx[portId].rxFiltered);
-
- for (priority = IX_ETH_ACC_TX_PRIORITY_0;
- priority <= IX_ETH_ACC_TX_PRIORITY_7;
- priority++)
- {
- if (rx[portId].rxPriority[priority])
- {
- printf("Rx Priority %u : %u\n",
- priority,
- rx[portId].rxPriority[priority]);
- }
- }
-#endif
- printf("Rx unexpected errors : %u (should be 0)\n",
- rx[portId].rxUnexpectedError);
-
-#ifndef NDEBUG
- numBuffersInTx = tx[portId].txQOK +
- tx[portId].txQDelayed -
- tx[portId].txDoneClientCallback -
- tx[portId].txDoneSwQDuringDisable -
- tx[portId].txDoneDuringDisable;
-
- printf("# Tx Buffers currently for transmission : %u\n",
- numBuffersInTx);
-
- numBuffersInRx = rx[portId].rxFreeRepOK +
- rx[portId].rxFreeRepDelayed -
- rx[portId].rxFrameClientCallback -
- rx[portId].rxSwQDuringDisable -
- rx[portId].rxDuringDisable;
-
- printf("# Rx Buffers currently for reception : %u\n",
- numBuffersInRx);
-
- totalBuffers += numBuffersInRx + numBuffersInTx;
-#endif
- }
-
- printf("---------------------------------------\n");
-
-#ifndef NDEBUG
- printf("\n");
- printf("Mbufs :\n");
- printf("Tx Unchained mbufs : %u\n",
- stats.unchainedTxMBufs);
- printf("Tx Chained bufs : %u\n",
- stats.chainedTxMBufs);
- printf("TxDone Unchained mbufs : %u\n",
- stats.unchainedTxDoneMBufs);
- printf("TxDone Chained bufs : %u\n",
- stats.chainedTxDoneMBufs);
- printf("RxFree Unchained mbufs : %u\n",
- stats.unchainedRxFreeMBufs);
- printf("RxFree Chained bufs : %u\n",
- stats.chainedRxFreeMBufs);
- printf("Rx Unchained mbufs : %u\n",
- stats.unchainedRxMBufs);
- printf("Rx Chained bufs : %u\n",
- stats.chainedRxMBufs);
-
- printf("\n");
- printf("Software queue usage :\n");
- printf("Buffers added to S/W Q : %u\n",
- stats.addToSwQ);
- printf("Buffers removed from S/W Q : %u\n",
- stats.removeFromSwQ);
-
- printf("\n");
- printf("Hardware queues callbacks :\n");
-
- for(portId=0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
- {
- rxFreeCallbackCounter += rx[portId].rxFreeLowCallback;
- txCallbackCounter += tx[portId].txLowThreshCallback;
- }
- printf("Tx Done QM Callback invoked : %u\n",
- stats.txDoneCallbackCounter);
- printf("Tx QM Callback invoked : %u\n",
- txCallbackCounter);
- printf("Rx QM Callback invoked : %u\n",
- stats.rxCallbackCounter);
- printf("Rx QM Callback burst read : %u\n",
- stats.rxCallbackBurstRead);
- printf("Rx Free QM Callback invoked : %u\n",
- rxFreeCallbackCounter);
-#endif
- printf("Unexpected errors in CB : %u (should be 0)\n",
- stats.unexpectedError);
- printf("\n");
-
- printf("Hardware queues levels :\n");
- printf("Transmit Port 1 Q : %u \n",numTx0Entries);
- printf("Transmit Port 2 Q : %u \n",numTx1Entries);
-#ifdef __ixp46X
- printf("Transmit Port 3 Q : %u \n",numTx2Entries);
-#endif
- printf("Transmit Done Q : %u \n",numTxDoneEntries);
- printf("Receive Q : %u \n",numRxEntries);
- printf("Receive Free Port 1 Q : %u \n",numRxFree0Entries);
- printf("Receive Free Port 2 Q : %u \n",numRxFree1Entries);
-#ifdef __ixp46X
- printf("Receive Free Port 3 Q : %u \n",numRxFree2Entries);
-#endif
-
-#ifndef NDEBUG
- printf("\n");
- printf("# Total Buffers accounted for : %u\n",
- totalBuffers);
-
- numBuffersInSwQ = ixEthAccDataStats.addToSwQ -
- ixEthAccDataStats.removeFromSwQ;
-
- printf(" Buffers in S/W Qs : %u\n",
- numBuffersInSwQ);
- printf(" Buffers in H/W Qs or NPEs : %u\n",
- totalBuffers - numBuffersInSwQ);
-#endif
-
- printf("Rx QoS Discipline : %s\n",
- (ixEthAccDataInfo.schDiscipline ==
- FIFO_PRIORITY ) ? "Enabled" : "Disabled");
-
- for(portId=0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
- {
- printf("Tx QoS Discipline port %u : %s\n",
- portId,
- (ixEthAccPortData[portId].ixEthAccTxData.schDiscipline ==
- FIFO_PRIORITY ) ? "Enabled" : "Disabled");
- }
- printf("\n");
-}
-
-
-
-
-
+++ /dev/null
-/**
- * @file IxEthAccMac.c
- *
- * @author Intel Corporation
- * @date
- *
- * @brief MAC control functions
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxOsal.h"
-#include "IxNpeMh.h"
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
-#include "IxEthDB.h"
-#endif
-#include "IxEthDBPortDefs.h"
-#include "IxEthNpe.h"
-#include "IxEthAcc.h"
-#include "IxEthAccDataPlane_p.h"
-#include "IxEthAcc_p.h"
-#include "IxEthAccMac_p.h"
-
-/* Maximum number of retries during ixEthAccPortDisable, which
- * is approximately 10 seconds
-*/
-#define IX_ETH_ACC_MAX_RETRY 500
-
-/* Maximum number of retries during ixEthAccPortDisable when expecting
- * timeout
- */
-#define IX_ETH_ACC_MAX_RETRY_TIMEOUT 5
-
-#define IX_ETH_ACC_VALIDATE_PORT_ID(portId) \
- do \
- { \
- if(!IX_ETH_ACC_IS_PORT_VALID(portId)) \
- { \
- return IX_ETH_ACC_INVALID_PORT; \
- } \
- } while(0)
-
-PUBLIC IxEthAccMacState ixEthAccMacState[IX_ETH_ACC_NUMBER_OF_PORTS];
-
-PRIVATE UINT32 ixEthAccMacBase[IX_ETH_ACC_NUMBER_OF_PORTS];
-
-/*Forward function declarations*/
-PRIVATE void
-ixEthAccPortDisableRx (IxEthAccPortId portId,
- IX_OSAL_MBUF * mBufPtr,
- BOOL useMultiBufferCallback);
-
-PRIVATE void
-ixEthAccPortDisableRxAndReplenish (IxEthAccPortId portId,
- IX_OSAL_MBUF * mBufPtr,
- BOOL useMultiBufferCallback);
-
-PRIVATE void
-ixEthAccPortDisableTxDone (UINT32 cbTag,
- IX_OSAL_MBUF *mbuf);
-
-PRIVATE void
-ixEthAccPortDisableTxDoneAndSubmit (UINT32 cbTag,
- IX_OSAL_MBUF *mbuf);
-
-PRIVATE void
-ixEthAccPortDisableRxCallback (UINT32 cbTag,
- IX_OSAL_MBUF * mBufPtr,
- UINT32 learnedPortId);
-
-PRIVATE void
-ixEthAccPortDisableMultiBufferRxCallback (UINT32 cbTag,
- IX_OSAL_MBUF **mBufPtr);
-
-PRIVATE IxEthAccStatus
-ixEthAccPortDisableTryTransmit(UINT32 portId);
-
-PRIVATE IxEthAccStatus
-ixEthAccPortDisableTryReplenish(UINT32 portId);
-
-PRIVATE IxEthAccStatus
-ixEthAccPortMulticastMacAddressGet (IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr);
-
-PRIVATE IxEthAccStatus
-ixEthAccPortMulticastMacFilterGet (IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr);
-
-PRIVATE void
-ixEthAccMacNpeStatsMessageCallback (IxNpeMhNpeId npeId,
- IxNpeMhMessage msg);
-
-PRIVATE void
-ixEthAccMacNpeStatsResetMessageCallback (IxNpeMhNpeId npeId,
- IxNpeMhMessage msg);
-
-PRIVATE void
-ixEthAccNpeLoopbackMessageCallback (IxNpeMhNpeId npeId,
- IxNpeMhMessage msg);
-
-PRIVATE void
-ixEthAccMulticastAddressSet(IxEthAccPortId portId);
-
-PRIVATE BOOL
-ixEthAccMacEqual(IxEthAccMacAddr *macAddr1,
- IxEthAccMacAddr *macAddr2);
-
-PRIVATE void
-ixEthAccMacPrint(IxEthAccMacAddr *m);
-
-PRIVATE void
-ixEthAccMacStateUpdate(IxEthAccPortId portId);
-
-IxEthAccStatus
-ixEthAccMacMemInit(void)
-{
- ixEthAccMacBase[IX_ETH_PORT_1] =
- (UINT32) IX_OSAL_MEM_MAP(IX_ETH_ACC_MAC_0_BASE,
- IX_OSAL_IXP400_ETHA_MAP_SIZE);
- ixEthAccMacBase[IX_ETH_PORT_2] =
- (UINT32) IX_OSAL_MEM_MAP(IX_ETH_ACC_MAC_1_BASE,
- IX_OSAL_IXP400_ETHB_MAP_SIZE);
-#ifdef __ixp46X
- ixEthAccMacBase[IX_ETH_PORT_3] =
- (UINT32) IX_OSAL_MEM_MAP(IX_ETH_ACC_MAC_2_BASE,
- IX_OSAL_IXP400_ETH_NPEA_MAP_SIZE);
- if (ixEthAccMacBase[IX_ETH_PORT_3] == 0)
- {
- ixOsalLog(IX_OSAL_LOG_LVL_FATAL,
- IX_OSAL_LOG_DEV_STDOUT,
- "EthAcc: Could not map MAC I/O memory\n",
- 0, 0, 0, 0, 0 ,0);
-
- return IX_ETH_ACC_FAIL;
- }
-#endif
-
- if (ixEthAccMacBase[IX_ETH_PORT_1] == 0
- || ixEthAccMacBase[IX_ETH_PORT_2] == 0)
- {
- ixOsalLog(IX_OSAL_LOG_LVL_FATAL,
- IX_OSAL_LOG_DEV_STDOUT,
- "EthAcc: Could not map MAC I/O memory\n",
- 0, 0, 0, 0, 0 ,0);
-
- return IX_ETH_ACC_FAIL;
- }
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-void
-ixEthAccMacUnload(void)
-{
- IX_OSAL_MEM_UNMAP(ixEthAccMacBase[IX_ETH_PORT_1]);
- IX_OSAL_MEM_UNMAP(ixEthAccMacBase[IX_ETH_PORT_2]);
-#ifdef __ixp46X
- IX_OSAL_MEM_UNMAP(ixEthAccMacBase[IX_ETH_PORT_3]);
- ixEthAccMacBase[IX_ETH_PORT_3] = 0;
-#endif
- ixEthAccMacBase[IX_ETH_PORT_2] = 0;
- ixEthAccMacBase[IX_ETH_PORT_1] = 0;
-}
-
-IxEthAccStatus
-ixEthAccPortEnablePriv(IxEthAccPortId portId)
-{
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot enable port.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- printf("EthAcc: (Mac) cannot enable port %d, port not initialized\n", portId);
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- if (ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn == NULL)
- {
- /* TxDone callback not registered */
- printf("EthAcc: (Mac) cannot enable port %d, TxDone callback not registered\n", portId);
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- if ((ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn == NULL)
- && (ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn == NULL))
- {
- /* Receive callback not registered */
- printf("EthAcc: (Mac) cannot enable port %d, Rx callback not registered\n", portId);
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- if(!ixEthAccMacState[portId].initDone)
- {
- printf("EthAcc: (Mac) cannot enable port %d, MAC address not set\n", portId);
- return (IX_ETH_ACC_MAC_UNINITIALIZED);
- }
-
- /* if the state is being set to what it is already at, do nothing*/
- if (ixEthAccMacState[portId].enabled)
- {
- return IX_ETH_ACC_SUCCESS;
- }
-
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
- /* enable ethernet database for this port */
- if (ixEthDBPortEnable(portId) != IX_ETH_DB_SUCCESS)
- {
- printf("EthAcc: (Mac) cannot enable port %d, EthDB failure\n", portId);
- return IX_ETH_ACC_FAIL;
- }
-#endif
-
- /* set the MAC core registers */
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL2,
- IX_ETH_ACC_TX_CNTRL2_RETRIES_MASK);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RANDOM_SEED,
- IX_ETH_ACC_RANDOM_SEED_DEFAULT);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_THRESH_P_EMPTY,
- IX_ETH_ACC_MAC_THRESH_P_EMPTY_DEFAULT);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_THRESH_P_FULL,
- IX_ETH_ACC_MAC_THRESH_P_FULL_DEFAULT);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_DEFER,
- IX_ETH_ACC_MAC_TX_DEFER_DEFAULT);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_TWO_DEFER_1,
- IX_ETH_ACC_MAC_TX_TWO_DEFER_1_DEFAULT);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_TWO_DEFER_2,
- IX_ETH_ACC_MAC_TX_TWO_DEFER_2_DEFAULT);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_SLOT_TIME,
- IX_ETH_ACC_MAC_SLOT_TIME_DEFAULT);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_INT_CLK_THRESH,
- IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_BUF_SIZE_TX,
- IX_ETH_ACC_MAC_BUF_SIZE_TX_DEFAULT);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- IX_ETH_ACC_TX_CNTRL1_DEFAULT);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- IX_ETH_ACC_RX_CNTRL1_DEFAULT);
-
- /* set the global state */
- ixEthAccMacState[portId].portDisableState = ACTIVE;
- ixEthAccMacState[portId].enabled = true;
-
- /* rewrite the setup (including mac filtering) depending
- * on current options
- */
- ixEthAccMacStateUpdate(portId);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-/*
- * PortDisable local variables. They contain the intermediate steps
- * while the port is being disabled and the buffers being drained out
- * of the NPE.
- */
-typedef void (*IxEthAccPortDisableRx)(IxEthAccPortId portId,
- IX_OSAL_MBUF * mBufPtr,
- BOOL useMultiBufferCallback);
-static IxEthAccPortRxCallback
-ixEthAccPortDisableFn[IX_ETH_ACC_NUMBER_OF_PORTS];
-static IxEthAccPortMultiBufferRxCallback
-ixEthAccPortDisableMultiBufferFn[IX_ETH_ACC_NUMBER_OF_PORTS];
-static IxEthAccPortDisableRx
-ixEthAccPortDisableRxTable[IX_ETH_ACC_NUMBER_OF_PORTS];
-static UINT32
-ixEthAccPortDisableCbTag[IX_ETH_ACC_NUMBER_OF_PORTS];
-static UINT32
-ixEthAccPortDisableMultiBufferCbTag[IX_ETH_ACC_NUMBER_OF_PORTS];
-
-static IxEthAccPortTxDoneCallback
-ixEthAccPortDisableTxDoneFn[IX_ETH_ACC_NUMBER_OF_PORTS];
-static UINT32
-ixEthAccPortDisableTxDoneCbTag[IX_ETH_ACC_NUMBER_OF_PORTS];
-
-static UINT32
-ixEthAccPortDisableUserBufferCount[IX_ETH_ACC_NUMBER_OF_PORTS];
-
-/*
- * PortDisable private callbacks functions. They handle the user
- * traffic, and the special buffers (one for tx, one for rx) used
- * in portDisable.
- */
-PRIVATE void
-ixEthAccPortDisableTxDone(UINT32 cbTag,
- IX_OSAL_MBUF *mbuf)
-{
- IxEthAccPortId portId = (IxEthAccPortId)cbTag;
- volatile IxEthAccPortDisableState *txState = &ixEthAccMacState[portId].txState;
-
- /* check for the special mbuf used in portDisable */
- if (mbuf == ixEthAccMacState[portId].portDisableTxMbufPtr)
- {
- *txState = TRANSMIT_DONE;
- }
- else
- {
- /* increment the count of user traffic during portDisable */
- ixEthAccPortDisableUserBufferCount[portId]++;
-
- /* call client TxDone function */
- ixEthAccPortDisableTxDoneFn[portId](ixEthAccPortDisableTxDoneCbTag[portId], mbuf);
- }
-}
-
-PRIVATE IxEthAccStatus
-ixEthAccPortDisableTryTransmit(UINT32 portId)
-{
- int key;
- IxEthAccStatus status = IX_ETH_ACC_SUCCESS;
- volatile IxEthAccPortDisableState *txState = &ixEthAccMacState[portId].txState;
- /* transmit the special buffer again if it is transmitted
- * and update the txState
- * This section is protected because the portDisable context
- * run an identical code, so the system keeps transmitting at the
- * maximum rate.
- */
- key = ixOsalIrqLock();
- if (*txState == TRANSMIT_DONE)
- {
- IX_OSAL_MBUF *mbufTxPtr = ixEthAccMacState[portId].portDisableTxMbufPtr;
- *txState = TRANSMIT;
- status = ixEthAccPortTxFrameSubmit(portId,
- mbufTxPtr,
- IX_ETH_ACC_TX_DEFAULT_PRIORITY);
- }
- ixOsalIrqUnlock(key);
-
- return status;
-}
-
-PRIVATE void
-ixEthAccPortDisableTxDoneAndSubmit(UINT32 cbTag,
- IX_OSAL_MBUF *mbuf)
-{
- IxEthAccPortId portId = (IxEthAccPortId)cbTag;
-
- /* call the callback which forwards the traffic to the client */
- ixEthAccPortDisableTxDone(cbTag, mbuf);
-
- /* try to transmit the buffer used in portDisable
- * if seen in TxDone
- */
- ixEthAccPortDisableTryTransmit(portId);
-}
-
-PRIVATE void
-ixEthAccPortDisableRx (IxEthAccPortId portId,
- IX_OSAL_MBUF * mBufPtr,
- BOOL useMultiBufferCallback)
-{
- volatile IxEthAccPortDisableState *rxState = &ixEthAccMacState[portId].rxState;
- IX_OSAL_MBUF *mNextPtr;
-
- while (mBufPtr)
- {
- mNextPtr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mBufPtr);
- IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mBufPtr) = NULL;
-
- /* check for the special mbuf used in portDisable */
- if (mBufPtr == ixEthAccMacState[portId].portDisableRxMbufPtr)
- {
- *rxState = RECEIVE;
- }
- else
- {
- /* increment the count of user traffic during portDisable */
- ixEthAccPortDisableUserBufferCount[portId]++;
-
- /* reset the received payload length during portDisable */
- IX_OSAL_MBUF_MLEN(mBufPtr) = 0;
- IX_OSAL_MBUF_PKT_LEN(mBufPtr) = 0;
-
- if (useMultiBufferCallback)
- {
- /* call the user callback with one unchained
- * buffer, without payload. A small array is built
- * to be used as a parameter (the user callback expects
- * to receive an array ended by a NULL pointer.
- */
- IX_OSAL_MBUF *mBufPtrArray[2];
-
- mBufPtrArray[0] = mBufPtr;
- mBufPtrArray[1] = NULL;
- ixEthAccPortDisableMultiBufferFn[portId](
- ixEthAccPortDisableMultiBufferCbTag[portId],
- mBufPtrArray);
- }
- else
- {
- /* call the user callback with a unchained
- * buffer, without payload and the destination port is
- * unknown.
- */
- ixEthAccPortDisableFn[portId](
- ixEthAccPortDisableCbTag[portId],
- mBufPtr,
- IX_ETH_DB_UNKNOWN_PORT /* port not found */);
- }
- }
-
- mBufPtr = mNextPtr;
- }
-}
-
-PRIVATE IxEthAccStatus
-ixEthAccPortDisableTryReplenish(UINT32 portId)
-{
- int key;
- IxEthAccStatus status = IX_ETH_ACC_SUCCESS;
- volatile IxEthAccPortDisableState *rxState = &ixEthAccMacState[portId].rxState;
- /* replenish with the special buffer again if it is received
- * and update the rxState
- * This section is protected because the portDisable context
- * run an identical code, so the system keeps replenishing at the
- * maximum rate.
- */
- key = ixOsalIrqLock();
- if (*rxState == RECEIVE)
- {
- IX_OSAL_MBUF *mbufRxPtr = ixEthAccMacState[portId].portDisableRxMbufPtr;
- *rxState = REPLENISH;
- IX_OSAL_MBUF_MLEN(mbufRxPtr) = IX_ETHACC_RX_MBUF_MIN_SIZE;
- status = ixEthAccPortRxFreeReplenish(portId, mbufRxPtr);
- }
- ixOsalIrqUnlock(key);
-
- return status;
-}
-
-PRIVATE void
-ixEthAccPortDisableRxAndReplenish (IxEthAccPortId portId,
- IX_OSAL_MBUF * mBufPtr,
- BOOL useMultiBufferCallback)
-{
- /* call the callback which forwards the traffic to the client */
- ixEthAccPortDisableRx(portId, mBufPtr, useMultiBufferCallback);
-
- /* try to replenish with the buffer used in portDisable
- * if seen in Rx
- */
- ixEthAccPortDisableTryReplenish(portId);
-}
-
-PRIVATE void
-ixEthAccPortDisableRxCallback (UINT32 cbTag,
- IX_OSAL_MBUF * mBufPtr,
- UINT32 learnedPortId)
-{
- IxEthAccPortId portId = (IxEthAccPortId)cbTag;
-
- /* call the portDisable receive callback */
- (ixEthAccPortDisableRxTable[portId])(portId, mBufPtr, false);
-}
-
-PRIVATE void
-ixEthAccPortDisableMultiBufferRxCallback (UINT32 cbTag,
- IX_OSAL_MBUF **mBufPtr)
-{
- IxEthAccPortId portId = (IxEthAccPortId)cbTag;
-
- while (*mBufPtr)
- {
- /* call the portDisable receive callback with one buffer at a time */
- (ixEthAccPortDisableRxTable[portId])(portId, *mBufPtr++, true);
- }
-}
-
-IxEthAccStatus
-ixEthAccPortDisablePriv(IxEthAccPortId portId)
-{
- IxEthAccStatus status = IX_ETH_ACC_SUCCESS;
- int key;
- int retry, retryTimeout;
- volatile IxEthAccPortDisableState *state = &ixEthAccMacState[portId].portDisableState;
- volatile IxEthAccPortDisableState *rxState = &ixEthAccMacState[portId].rxState;
- volatile IxEthAccPortDisableState *txState = &ixEthAccMacState[portId].txState;
-
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot disable port.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /* if the state is being set to what it is already at, do nothing */
- if (!ixEthAccMacState[portId].enabled)
- {
- return IX_ETH_ACC_SUCCESS;
- }
-
- *state = DISABLED;
-
- /* disable MAC receive first */
- ixEthAccPortRxDisablePriv(portId);
-
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
- /* disable ethernet database for this port - It is done now to avoid
- * issuing ELT maintenance after requesting 'port disable' in an NPE
- */
- if (ixEthDBPortDisable(portId) != IX_ETH_DB_SUCCESS)
- {
- status = IX_ETH_ACC_FAIL;
- IX_ETH_ACC_FATAL_LOG("ixEthAccPortDisable: failed to disable EthDB for this port\n", 0, 0, 0, 0, 0, 0);
- }
-#endif
-
- /* enter the critical section */
- key = ixOsalIrqLock();
-
- /* swap the Rx and TxDone callbacks */
- ixEthAccPortDisableFn[portId] = ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn;
- ixEthAccPortDisableMultiBufferFn[portId] = ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn;
- ixEthAccPortDisableCbTag[portId] = ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag;
- ixEthAccPortDisableMultiBufferCbTag[portId] = ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackTag;
- ixEthAccPortDisableTxDoneFn[portId] = ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn;
- ixEthAccPortDisableTxDoneCbTag[portId] = ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag;
- ixEthAccPortDisableRxTable[portId] = ixEthAccPortDisableRx;
-
- /* register temporary callbacks */
- ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn = ixEthAccPortDisableRxCallback;
- ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag = portId;
-
- ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn = ixEthAccPortDisableMultiBufferRxCallback;
- ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackTag = portId;
-
- ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn = ixEthAccPortDisableTxDone;
- ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag = portId;
-
- /* initialise the Rx state and Tx states */
- *txState = TRANSMIT_DONE;
- *rxState = RECEIVE;
-
- /* exit the critical section */
- ixOsalIrqUnlock(key);
-
- /* enable a NPE loopback */
- if (ixEthAccNpeLoopbackEnablePriv(portId) != IX_ETH_ACC_SUCCESS)
- {
- status = IX_ETH_ACC_FAIL;
- }
-
- if (status == IX_ETH_ACC_SUCCESS)
- {
- retry = 0;
-
- /* Step 1 : Drain Tx traffic and TxDone queues :
- *
- * Transmit and replenish at least once with the
- * special buffers until both of them are seen
- * in the callback hook
- *
- * (the receive callback keeps replenishing, so once we see
- * the special Tx buffer, we can be sure that Tx drain is complete)
- */
- ixEthAccPortDisableRxTable[portId]
- = ixEthAccPortDisableRxAndReplenish;
- ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn
- = ixEthAccPortDisableTxDone;
-
- do
- {
- /* keep replenishing */
- status = ixEthAccPortDisableTryReplenish(portId);
- if (status == IX_ETH_ACC_SUCCESS)
- {
- /* keep transmitting */
- status = ixEthAccPortDisableTryTransmit(portId);
- }
- if (status == IX_ETH_ACC_SUCCESS)
- {
- /* wait for some traffic being processed */
- ixOsalSleep(IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS);
- }
- }
- while ((status == IX_ETH_ACC_SUCCESS)
- && (retry++ < IX_ETH_ACC_MAX_RETRY)
- && (*txState == TRANSMIT));
-
- /* Step 2 : Drain Rx traffic, RxFree and Rx queues :
- *
- * Transmit and replenish at least once with the
- * special buffers until both of them are seen
- * in the callback hook
- * (the transmit callback keeps transmitting, and when we see
- * the special Rx buffer, we can be sure that rxFree drain
- * is complete)
- *
- * The nested loop helps to retry if the user was keeping
- * replenishing or transmitting during portDisable.
- *
- * The 2 nested loops ensure more retries if user traffic is
- * seen during portDisable : the user should not replenish
- * or transmit while portDisable is running. However, because of
- * the queueing possibilities in ethAcc dataplane, it is possible
- * that a lot of traffic is left in the queues (e.g. when
- * transmitting over a low speed link) and therefore, more
- * retries are allowed to help flushing the buffers out.
- */
- ixEthAccPortDisableRxTable[portId]
- = ixEthAccPortDisableRx;
- ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn
- = ixEthAccPortDisableTxDoneAndSubmit;
-
- do
- {
- do
- {
- ixEthAccPortDisableUserBufferCount[portId] = 0;
-
- /* keep replenishing */
- status = ixEthAccPortDisableTryReplenish(portId);
- if (status == IX_ETH_ACC_SUCCESS)
- {
- /* keep transmitting */
- status = ixEthAccPortDisableTryTransmit(portId);
- }
- if (status == IX_ETH_ACC_SUCCESS)
- {
- /* wait for some traffic being processed */
- ixOsalSleep(IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS);
- }
- }
- while ((status == IX_ETH_ACC_SUCCESS)
- && (retry++ < IX_ETH_ACC_MAX_RETRY)
- && ((ixEthAccPortDisableUserBufferCount[portId] != 0)
- || (*rxState == REPLENISH)));
-
- /* After the first iteration, change the receive callbacks,
- * to process only 1 buffer at a time
- */
- ixEthAccPortDisableRxTable[portId]
- = ixEthAccPortDisableRx;
- ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn
- = ixEthAccPortDisableTxDone;
-
- /* repeat the whole process while user traffic is seen in TxDone
- *
- * The conditions to stop the loop are
- * - Xscale has both Rx and Tx special buffers
- * (txState = transmit, rxState = receive)
- * - any error in txSubmit or rxReplenish
- * - no user traffic seen
- * - an excessive amount of retries
- */
- }
- while ((status == IX_ETH_ACC_SUCCESS)
- && (retry < IX_ETH_ACC_MAX_RETRY)
- && (*txState == TRANSMIT));
-
- /* check the loop exit conditions. The NPE should not hold
- * the special buffers.
- */
- if ((*rxState == REPLENISH) || (*txState == TRANSMIT))
- {
- status = IX_ETH_ACC_FAIL;
- }
-
- if (status == IX_ETH_ACC_SUCCESS)
- {
- /* Step 3 : Replenish without transmitting until a timeout
- * occurs, in order to drain the internal NPE fifos
- *
- * we can expect a few frames srill held
- * in the NPE.
- *
- * The 2 nested loops take care about the NPE dropping traffic
- * (including loopback traffic) when the Rx queue is full.
- *
- * The timeout value is very conservative
- * since the loopback used keeps replenishhing.
- *
- */
- do
- {
- ixEthAccPortDisableRxTable[portId] = ixEthAccPortDisableRxAndReplenish;
- ixEthAccPortDisableUserBufferCount[portId] = 0;
- retryTimeout = 0;
- do
- {
- /* keep replenishing */
- status = ixEthAccPortDisableTryReplenish(portId);
- if (status == IX_ETH_ACC_SUCCESS)
- {
- /* wait for some traffic being processed */
- ixOsalSleep(IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS);
- }
- }
- while ((status == IX_ETH_ACC_SUCCESS)
- && (retryTimeout++ < IX_ETH_ACC_MAX_RETRY_TIMEOUT));
-
- /* Step 4 : Transmit once. Stop replenish
- *
- * After the Rx timeout, we are sure that the NPE does not
- * hold any frame in its internal NPE fifos.
- *
- * At this point, the NPE still holds the last rxFree buffer.
- * By transmitting a single frame, this should unblock the
- * last rxFree buffer. This code just transmit once and
- * wait for both frames seen in TxDone and in rxFree.
- *
- */
- ixEthAccPortDisableRxTable[portId] = ixEthAccPortDisableRx;
- status = ixEthAccPortDisableTryTransmit(portId);
-
- /* the NPE should immediatelyt release
- * the last Rx buffer and the last transmitted buffer
- * unless the last Tx frame was dropped (rx queue full)
- */
- if (status == IX_ETH_ACC_SUCCESS)
- {
- retryTimeout = 0;
- do
- {
- ixOsalSleep(IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS);
- }
- while ((*rxState == REPLENISH)
- && (retryTimeout++ < IX_ETH_ACC_MAX_RETRY_TIMEOUT));
- }
-
- /* the NPE may have dropped the traffic because of Rx
- * queue being full. This code ensures that the last
- * Tx and Rx frames are both received.
- */
- }
- while ((status == IX_ETH_ACC_SUCCESS)
- && (retry++ < IX_ETH_ACC_MAX_RETRY)
- && ((*txState == TRANSMIT)
- || (*rxState == REPLENISH)
- || (ixEthAccPortDisableUserBufferCount[portId] != 0)));
-
- /* Step 5 : check the final states : the NPE has
- * no buffer left, nor in Tx , nor in Rx directions.
- */
- if ((*rxState == REPLENISH) || (*txState == TRANSMIT))
- {
- status = IX_ETH_ACC_FAIL;
- }
- }
-
- /* now all the buffers are drained, disable NPE loopback
- * This is done regardless of the logic to drain the queues and
- * the internal buffers held by the NPE.
- */
- if (ixEthAccNpeLoopbackDisablePriv(portId) != IX_ETH_ACC_SUCCESS)
- {
- status = IX_ETH_ACC_FAIL;
- }
- }
-
- /* disable MAC Tx and Rx services */
- ixEthAccMacState[portId].enabled = false;
- ixEthAccMacStateUpdate(portId);
-
- /* restore the Rx and TxDone callbacks (within a critical section) */
- key = ixOsalIrqLock();
-
- ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn = ixEthAccPortDisableFn[portId];
- ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag = ixEthAccPortDisableCbTag[portId];
- ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn = ixEthAccPortDisableMultiBufferFn[portId];
- ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackTag = ixEthAccPortDisableMultiBufferCbTag[portId];
- ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn = ixEthAccPortDisableTxDoneFn[portId];
- ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag = ixEthAccPortDisableTxDoneCbTag[portId];
-
- ixOsalIrqUnlock(key);
-
- /* the MAC core rx/tx disable may left the MAC hardware in an
- * unpredictable state. A hw reset is executed before resetting
- * all the MAC parameters to a known value.
- */
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_CORE_CNTRL,
- IX_ETH_ACC_CORE_RESET);
-
- ixOsalSleep(IX_ETH_ACC_MAC_RESET_DELAY);
-
- /* rewrite all parameters to their current value */
- ixEthAccMacStateUpdate(portId);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_INT_CLK_THRESH,
- IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_CORE_CNTRL,
- IX_ETH_ACC_CORE_MDC_EN);
-
- return status;
-}
-
-IxEthAccStatus
-ixEthAccPortEnabledQueryPriv(IxEthAccPortId portId, BOOL *enabled)
-{
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot enable port.\n",(INT32)portId,0,0,0,0,0);
-
- /* Since Eth NPE is not available, port must be disabled */
- *enabled = false ;
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- /* Since Eth NPE is not available, port must be disabled */
- *enabled = false ;
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- *enabled = ixEthAccMacState[portId].enabled;
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortMacResetPriv(IxEthAccPortId portId)
-{
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot reset Ethernet coprocessor.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_CORE_CNTRL,
- IX_ETH_ACC_CORE_RESET);
-
- ixOsalSleep(IX_ETH_ACC_MAC_RESET_DELAY);
-
- /* rewrite all parameters to their current value */
- ixEthAccMacStateUpdate(portId);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_INT_CLK_THRESH,
- IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_CORE_CNTRL,
- IX_ETH_ACC_CORE_MDC_EN);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortLoopbackEnable(IxEthAccPortId portId)
-{
- UINT32 regval;
-
- /* Turn off promiscuous mode */
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable loopback.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /* read register */
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval);
-
- /* update register */
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval | IX_ETH_ACC_RX_CNTRL1_LOOP_EN);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-PRIVATE void
-ixEthAccNpeLoopbackMessageCallback (IxNpeMhNpeId npeId,
- IxNpeMhMessage msg)
-{
- IxEthAccPortId portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId);
-
-#ifndef NDEBUG
- /* Prudent to at least check the port is within range */
- if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS)
- {
- IX_ETH_ACC_FATAL_LOG("IXETHACC:ixEthAccPortDisableMessageCallback: Illegal port: %u\n",
- (UINT32) portId, 0, 0, 0, 0, 0);
-
- return;
- }
-#endif
-
- /* unlock message reception mutex */
- ixOsalMutexUnlock(&ixEthAccMacState[portId].npeLoopbackMessageLock);
-}
-
-IxEthAccStatus
-ixEthAccNpeLoopbackEnablePriv(IxEthAccPortId portId)
-{
- IX_STATUS npeMhStatus;
- IxNpeMhMessage message;
- IxEthAccStatus status = IX_ETH_ACC_SUCCESS;
-
- /* Turn off promiscuous mode */
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable NPE loopback.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /* enable NPE loopback (lsb of the message contains the value 1) */
- message.data[0] = (IX_ETHNPE_SETLOOPBACK_MODE << IX_ETH_ACC_MAC_MSGID_SHL)
- | 0x01;
- message.data[1] = 0;
-
- npeMhStatus = ixNpeMhMessageWithResponseSend(IX_ETH_ACC_PORT_TO_NPE_ID(portId),
- message,
- IX_ETHNPE_SETLOOPBACK_MODE_ACK,
- ixEthAccNpeLoopbackMessageCallback,
- IX_NPEMH_SEND_RETRIES_DEFAULT);
-
- if (npeMhStatus != IX_SUCCESS)
- {
- status = IX_ETH_ACC_FAIL;
- }
- else
- {
- /* wait for NPE loopbackEnable response */
- if (ixOsalMutexLock(&ixEthAccMacState[portId]. npeLoopbackMessageLock,
- IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS)
- != IX_SUCCESS)
- {
- status = IX_ETH_ACC_FAIL;
- }
- }
-
- return status;
-}
-
-IxEthAccStatus
-ixEthAccPortTxEnablePriv(IxEthAccPortId portId)
-{
- UINT32 regval;
-
- /* Turn off promiscuous mode */
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable TX.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /* read register */
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval);
-
- /* update register */
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval | IX_ETH_ACC_TX_CNTRL1_TX_EN);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortRxEnablePriv(IxEthAccPortId portId)
-{
- UINT32 regval;
-
- /* Turn off promiscuous mode */
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable RX.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /* read register */
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval);
-
- /* update register */
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval | IX_ETH_ACC_RX_CNTRL1_RX_EN);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortLoopbackDisable(IxEthAccPortId portId)
-{
- UINT32 regval;
-
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot disable loopback.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /*disable MAC loopabck */
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- (regval & ~IX_ETH_ACC_RX_CNTRL1_LOOP_EN));
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccNpeLoopbackDisablePriv(IxEthAccPortId portId)
-{
- IX_STATUS npeMhStatus;
- IxNpeMhMessage message;
- IxEthAccStatus status = IX_ETH_ACC_SUCCESS;
-
- /* Turn off promiscuous mode */
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable NPE loopback.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /* disable NPE loopback (lsb of the message contains the value 0) */
- message.data[0] = (IX_ETHNPE_SETLOOPBACK_MODE << IX_ETH_ACC_MAC_MSGID_SHL);
- message.data[1] = 0;
-
- npeMhStatus = ixNpeMhMessageWithResponseSend(IX_ETH_ACC_PORT_TO_NPE_ID(portId),
- message,
- IX_ETHNPE_SETLOOPBACK_MODE_ACK,
- ixEthAccNpeLoopbackMessageCallback,
- IX_NPEMH_SEND_RETRIES_DEFAULT);
-
- if (npeMhStatus != IX_SUCCESS)
- {
- status = IX_ETH_ACC_FAIL;
- }
- else
- {
- /* wait for NPE loopbackEnable response */
- if (ixOsalMutexLock(&ixEthAccMacState[portId].npeLoopbackMessageLock,
- IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS)
- != IX_SUCCESS)
- {
- status = IX_ETH_ACC_FAIL;
- }
- }
-
- return status;
-}
-
-IxEthAccStatus
-ixEthAccPortTxDisablePriv(IxEthAccPortId portId)
-{
- UINT32 regval;
-
- /* Turn off promiscuous mode */
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot disable TX.\n", (INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /* read register */
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval);
-
- /* update register */
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- (regval & ~IX_ETH_ACC_TX_CNTRL1_TX_EN));
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortRxDisablePriv(IxEthAccPortId portId)
-{
- UINT32 regval;
-
- /* Turn off promiscuous mode */
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot disable RX.\n", (INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /* read register */
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval);
-
- /* update register */
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- (regval & ~IX_ETH_ACC_RX_CNTRL1_RX_EN));
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortPromiscuousModeClearPriv(IxEthAccPortId portId)
-{
- UINT32 regval;
-
- /* Turn off promiscuous mode */
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot clear promiscuous mode.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /*set bit 5 of Rx control 1 - enable address filtering*/
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval | IX_ETH_ACC_RX_CNTRL1_ADDR_FLTR_EN);
-
- ixEthAccMacState[portId].promiscuous = false;
-
- ixEthAccMulticastAddressSet(portId);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortPromiscuousModeSetPriv(IxEthAccPortId portId)
-{
- UINT32 regval;
-
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot set promiscuous mode.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /*
- * Set bit 5 of Rx control 1 - We enable address filtering even in
- * promiscuous mode because we want the MAC to set the appropriate
- * bits in m_flags which doesn't happen if we turn off filtering.
- */
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval | IX_ETH_ACC_RX_CNTRL1_ADDR_FLTR_EN);
-
- ixEthAccMacState[portId].promiscuous = true;
-
- ixEthAccMulticastAddressSet(portId);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortUnicastMacAddressSetPriv (IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr)
-{
- UINT32 i;
-
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot set Unicast Mac Address.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
-
- if (macAddr == NULL)
- {
- return IX_ETH_ACC_FAIL;
- }
-
- if ( macAddr->macAddress[0] & IX_ETH_ACC_ETH_MAC_BCAST_MCAST_BIT )
- {
- /* This is a multicast/broadcast address cant set it ! */
- return IX_ETH_ACC_FAIL;
- }
-
- if ( macAddr->macAddress[0] == 0 &&
- macAddr->macAddress[1] == 0 &&
- macAddr->macAddress[2] == 0 &&
- macAddr->macAddress[3] == 0 &&
- macAddr->macAddress[4] == 0 &&
- macAddr->macAddress[5] == 0 )
- {
- /* This is an invalid mac address cant set it ! */
- return IX_ETH_ACC_FAIL;
- }
-
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
- /* update the MAC address in the ethernet database */
- if (ixEthDBPortAddressSet(portId, (IxEthDBMacAddr *) macAddr) != IX_ETH_DB_SUCCESS)
- {
- return IX_ETH_ACC_FAIL;
- }
-#endif
-
- /*Set the Unicast MAC to the specified value*/
- for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE;i++)
- {
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_UNI_ADDR_1 + i*sizeof(UINT32),
- macAddr->macAddress[i]);
- }
- ixEthAccMacState[portId].initDone = true;
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortUnicastMacAddressGetPriv (IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr)
-{
- /*Return the current value of the Unicast MAC from h/w
- for the specified port*/
- UINT32 i;
-
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot get Unicast Mac Address.\n",(INT32)portId,0,0,0,0,0);
- /* Since Eth Npe is unavailable, return invalid MAC Address = 00:00:00:00:00:00 */
- for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE;i++)
- {
- macAddr->macAddress[i] = 0;
- }
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if(!ixEthAccMacState[portId].initDone)
- {
- return (IX_ETH_ACC_MAC_UNINITIALIZED);
- }
-
- if (macAddr == NULL)
- {
- return IX_ETH_ACC_FAIL;
- }
-
-
- for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE;i++)
- {
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_UNI_ADDR_1 + i*sizeof(UINT32),
- macAddr->macAddress[i]);
- }
- return IX_ETH_ACC_SUCCESS;
-}
-
-PRIVATE IxEthAccStatus
-ixEthAccPortMulticastMacAddressGet (IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr)
-{
- /*Return the current value of the Multicast MAC from h/w
- for the specified port*/
- UINT32 i;
-
- for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE;i++)
- {
-
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_ADDR_1 + i*sizeof(UINT32),
- macAddr->macAddress[i]);
- }
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-PRIVATE IxEthAccStatus
-ixEthAccPortMulticastMacFilterGet (IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr)
-{
- /*Return the current value of the Multicast MAC from h/w
- for the specified port*/
- UINT32 i;
-
- for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE;i++)
- {
-
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_ADDR_MASK_1 + i*sizeof(UINT32),
- macAddr->macAddress[i]);
- }
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortMulticastAddressJoinPriv (IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr)
-{
- UINT32 i;
- IxEthAccMacAddr broadcastAddr = {{0xff,0xff,0xff,0xff,0xff,0xff}};
-
- /*Check that the port parameter is valid*/
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot join Multicast Mac Address.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /*Check that the mac address is valid*/
- if(macAddr == NULL)
- {
- return IX_ETH_ACC_FAIL;
- }
-
- /* Check that this is a multicast address */
- if (!(macAddr->macAddress[0] & IX_ETH_ACC_ETH_MAC_BCAST_MCAST_BIT))
- {
- return IX_ETH_ACC_FAIL;
- }
-
- /* We don't add the Broadcast address */
- if(ixEthAccMacEqual(&broadcastAddr, macAddr))
- {
- return IX_ETH_ACC_FAIL;
- }
-
- for (i = 0;
- i<ixEthAccMacState[portId].mcastAddrIndex;
- i++)
- {
- /*Check if the current entry already match an existing matches*/
- if(ixEthAccMacEqual(&ixEthAccMacState[portId].mcastAddrsTable[i], macAddr))
- {
- /* Address found in the list and already configured,
- * return a success status
- */
- return IX_ETH_ACC_SUCCESS;
- }
- }
-
- /* check for availability at the end of the current table */
- if(ixEthAccMacState[portId].mcastAddrIndex >= IX_ETH_ACC_MAX_MULTICAST_ADDRESSES)
- {
- return IX_ETH_ACC_FAIL;
- }
-
- /*First add the address to the multicast table for the
- specified port*/
- i=ixEthAccMacState[portId].mcastAddrIndex;
-
- memcpy(&ixEthAccMacState[portId].mcastAddrsTable[i],
- &macAddr->macAddress,
- IX_IEEE803_MAC_ADDRESS_SIZE);
-
- /*Increment the index into the table, this must be done here
- as MulticastAddressSet below needs to know about the latest
- entry.
- */
- ixEthAccMacState[portId].mcastAddrIndex++;
-
- /*Then calculate the new value to be written to the address and
- address mask registers*/
- ixEthAccMulticastAddressSet(portId);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-
-IxEthAccStatus
-ixEthAccPortMulticastAddressJoinAllPriv (IxEthAccPortId portId)
-{
- IxEthAccMacAddr mcastMacAddr = {{0x1,0x0,0x0,0x0,0x0,0x0}};
-
- /*Check that the port parameter is valid*/
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot join all Multicast Address.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /* remove all entries from the database and
- * insert a multicast entry
- */
- memcpy(&ixEthAccMacState[portId].mcastAddrsTable[0],
- &mcastMacAddr.macAddress,
- IX_IEEE803_MAC_ADDRESS_SIZE);
-
- ixEthAccMacState[portId].mcastAddrIndex = 1;
- ixEthAccMacState[portId].joinAll = true;
-
- ixEthAccMulticastAddressSet(portId);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortMulticastAddressLeavePriv (IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr)
-{
- UINT32 i;
- IxEthAccMacAddr mcastMacAddr = {{0x1,0x0,0x0,0x0,0x0,0x0}};
-
- /*Check that the port parameter is valid*/
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot leave Multicast Address.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /*Check that the mac address is valid*/
- if(macAddr == NULL)
- {
- return IX_ETH_ACC_FAIL;
- }
- /* Remove this mac address from the mask for the specified port
- * we copy down all entries above the blanked entry, and
- * decrement the index
- */
- i=0;
-
- while(i<ixEthAccMacState[portId].mcastAddrIndex)
- {
- /*Check if the current entry matches*/
- if(ixEthAccMacEqual(&ixEthAccMacState[portId].mcastAddrsTable[i],
- macAddr))
- {
- if(ixEthAccMacEqual(macAddr, &mcastMacAddr))
- {
- ixEthAccMacState[portId].joinAll = false;
- }
- /*Decrement the index into the multicast address table
- for the current port*/
- ixEthAccMacState[portId].mcastAddrIndex--;
-
- /*Copy down all entries above the current entry*/
- while(i<ixEthAccMacState[portId].mcastAddrIndex)
- {
- memcpy(&ixEthAccMacState[portId].mcastAddrsTable[i],
- &ixEthAccMacState[portId].mcastAddrsTable[i+1],
- IX_IEEE803_MAC_ADDRESS_SIZE);
- i++;
- }
- /*recalculate the mask and write it to the MAC*/
- ixEthAccMulticastAddressSet(portId);
-
- return IX_ETH_ACC_SUCCESS;
- }
- /* search the next entry */
- i++;
- }
- /* no matching entry found */
- return IX_ETH_ACC_NO_SUCH_ADDR;
-}
-
-IxEthAccStatus
-ixEthAccPortMulticastAddressLeaveAllPriv (IxEthAccPortId portId)
-{
- /*Check that the port parameter is valid*/
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot leave all Multicast Address.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- ixEthAccMacState[portId].mcastAddrIndex = 0;
- ixEthAccMacState[portId].joinAll = false;
-
- ixEthAccMulticastAddressSet(portId);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-
-IxEthAccStatus
-ixEthAccPortUnicastAddressShowPriv (IxEthAccPortId portId)
-{
- IxEthAccMacAddr macAddr;
-
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot show Unicast Address.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /*Get the MAC (UINICAST) address from hardware*/
- if(ixEthAccPortUnicastMacAddressGetPriv(portId, &macAddr) != IX_ETH_ACC_SUCCESS)
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: MAC address uninitialised port %u\n",
- (INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_MAC_UNINITIALIZED;
- }
-
- /*print it out*/
- ixEthAccMacPrint(&macAddr);
- printf("\n");
- return IX_ETH_ACC_SUCCESS;
-}
-
-
-
-void
-ixEthAccPortMulticastAddressShowPriv(IxEthAccPortId portId)
-{
- IxEthAccMacAddr macAddr;
- UINT32 i;
-
- if(!IX_ETH_ACC_IS_PORT_VALID(portId))
- {
- return;
- }
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot show Multicast Address.\n",(INT32)portId,0,0,0,0,0);
- return ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return;
- }
-
- printf("Multicast MAC: ");
- /*Get the MAC (MULTICAST) address from hardware*/
- ixEthAccPortMulticastMacAddressGet(portId, &macAddr);
- /*print it out*/
- ixEthAccMacPrint(&macAddr);
- /*Get the MAC (MULTICAST) filter from hardware*/
- ixEthAccPortMulticastMacFilterGet(portId, &macAddr);
- /*print it out*/
- printf(" ( ");
- ixEthAccMacPrint(&macAddr);
- printf(" )\n");
- printf("Constituent Addresses:\n");
- for(i=0;i<ixEthAccMacState[portId].mcastAddrIndex;i++)
- {
- ixEthAccMacPrint(&ixEthAccMacState[portId].mcastAddrsTable[i]);
- printf("\n");
- }
- return;
-}
-
-/*Set the duplex mode*/
-IxEthAccStatus
-ixEthAccPortDuplexModeSetPriv (IxEthAccPortId portId,
- IxEthAccDuplexMode mode)
-{
- UINT32 txregval;
- UINT32 rxregval;
-
- /*This is bit 1 of the transmit control reg, set to 1 for half
- duplex, 0 for full duplex*/
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot set Duplex Mode.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- txregval);
-
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- rxregval);
-
- if (mode == IX_ETH_ACC_FULL_DUPLEX)
- {
- /*Clear half duplex bit in TX*/
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- txregval & ~IX_ETH_ACC_TX_CNTRL1_DUPLEX);
-
- /*We must set the pause enable in the receive logic when in
- full duplex mode*/
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- rxregval | IX_ETH_ACC_RX_CNTRL1_PAUSE_EN);
- ixEthAccMacState[portId].fullDuplex = true;
-
- }
- else if (mode == IX_ETH_ACC_HALF_DUPLEX)
- {
- /*Set half duplex bit in TX*/
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- txregval | IX_ETH_ACC_TX_CNTRL1_DUPLEX);
-
- /*We must clear pause enable in the receive logic when in
- half duplex mode*/
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- rxregval & ~IX_ETH_ACC_RX_CNTRL1_PAUSE_EN);
-
- ixEthAccMacState[portId].fullDuplex = false;
- }
- else
- {
- return IX_ETH_ACC_FAIL;
- }
-
-
- return IX_ETH_ACC_SUCCESS;
-
-}
-
-
-
-IxEthAccStatus
-ixEthAccPortDuplexModeGetPriv (IxEthAccPortId portId,
- IxEthAccDuplexMode *mode)
-{
- /*Return the duplex mode for the specified port*/
- UINT32 regval;
-
- /*This is bit 1 of the transmit control reg, set to 1 for half
- duplex, 0 for full duplex*/
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot get Duplex Mode.\n",(INT32)portId,0,0,0,0,0);
- /* return hald duplex */
- *mode = IX_ETH_ACC_HALF_DUPLEX ;
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- if (mode == NULL)
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval);
-
- if( regval & IX_ETH_ACC_TX_CNTRL1_DUPLEX)
- {
- *mode = IX_ETH_ACC_HALF_DUPLEX;
- }
- else
- {
- *mode = IX_ETH_ACC_FULL_DUPLEX;
- }
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-
-
-IxEthAccStatus
-ixEthAccPortTxFrameAppendPaddingEnablePriv (IxEthAccPortId portId)
-{
- UINT32 regval;
- /*Enable FCS computation by the MAC and appending to the
- frame*/
-
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot enable Tx Frame Append Padding.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval |
- IX_ETH_ACC_TX_CNTRL1_PAD_EN);
-
- ixEthAccMacState[portId].txPADAppend = true;
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortTxFrameAppendPaddingDisablePriv (IxEthAccPortId portId)
-{
- UINT32 regval;
-
- /*disable FCS computation and appending*/
- /*Set bit 4 of Tx control register one to zero*/
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot disble Tx Frame Append Padding.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval & ~IX_ETH_ACC_TX_CNTRL1_PAD_EN);
-
- ixEthAccMacState[portId].txPADAppend = false;
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortTxFrameAppendFCSEnablePriv (IxEthAccPortId portId)
-{
- UINT32 regval;
-
- /*Enable FCS computation by the MAC and appending to the
- frame*/
-
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot enable Tx Frame Append FCS.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval | IX_ETH_ACC_TX_CNTRL1_FCS_EN);
-
- ixEthAccMacState[portId].txFCSAppend = true;
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortTxFrameAppendFCSDisablePriv (IxEthAccPortId portId)
-{
- UINT32 regval;
-
- /*disable FCS computation and appending*/
- /*Set bit 4 of Tx control register one to zero*/
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot disable Tx Frame Append FCS.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval & ~IX_ETH_ACC_TX_CNTRL1_FCS_EN);
-
- ixEthAccMacState[portId].txFCSAppend = false;
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortRxFrameAppendFCSEnablePriv (IxEthAccPortId portId)
-{
- /*Set bit 2 of Rx control 1*/
- UINT32 regval;
-
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot enable Rx Frame Append FCS.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval | IX_ETH_ACC_RX_CNTRL1_CRC_EN);
-
- ixEthAccMacState[portId].rxFCSAppend = true;
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortRxFrameAppendFCSDisablePriv (IxEthAccPortId portId)
-{
- UINT32 regval;
-
- /*Clear bit 2 of Rx control 1*/
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot disable Rx Frame Append FCS.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval & ~IX_ETH_ACC_RX_CNTRL1_CRC_EN);
-
- ixEthAccMacState[portId].rxFCSAppend = false;
- return IX_ETH_ACC_SUCCESS;
-}
-
-
-
-PRIVATE void
-ixEthAccMacNpeStatsMessageCallback (IxNpeMhNpeId npeId,
- IxNpeMhMessage msg)
-{
- IxEthAccPortId portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId);
-
-#ifndef NDEBUG
- /* Prudent to at least check the port is within range */
- if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS)
- {
- IX_ETH_ACC_FATAL_LOG(
- "IXETHACC:ixEthAccMacNpeStatsMessageCallback: Illegal port: %u\n",
- (UINT32)portId, 0, 0, 0, 0, 0);
- return;
- }
-#endif
-
- /*Unblock Stats Get call*/
- ixOsalMutexUnlock(&ixEthAccMacState[portId].ackMIBStatsLock);
-
-}
-
-PRIVATE void
-ixEthAccMibIIStatsEndianConvert (IxEthEthObjStats *retStats)
-{
- /* endianness conversion */
-
- /* Rx stats */
- retStats->dot3StatsAlignmentErrors =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsAlignmentErrors);
- retStats->dot3StatsFCSErrors =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsFCSErrors);
- retStats->dot3StatsInternalMacReceiveErrors =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsInternalMacReceiveErrors);
- retStats->RxOverrunDiscards =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxOverrunDiscards);
- retStats->RxLearnedEntryDiscards =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxLearnedEntryDiscards);
- retStats->RxLargeFramesDiscards =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxLargeFramesDiscards);
- retStats->RxSTPBlockedDiscards =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxSTPBlockedDiscards);
- retStats->RxVLANTypeFilterDiscards =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxVLANTypeFilterDiscards);
- retStats->RxVLANIdFilterDiscards =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxVLANIdFilterDiscards);
- retStats->RxInvalidSourceDiscards =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxInvalidSourceDiscards);
- retStats->RxBlackListDiscards =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxBlackListDiscards);
- retStats->RxWhiteListDiscards =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxWhiteListDiscards);
- retStats->RxUnderflowEntryDiscards =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxUnderflowEntryDiscards);
-
- /* Tx stats */
- retStats->dot3StatsSingleCollisionFrames =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsSingleCollisionFrames);
- retStats->dot3StatsMultipleCollisionFrames =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsMultipleCollisionFrames);
- retStats->dot3StatsDeferredTransmissions =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsDeferredTransmissions);
- retStats->dot3StatsLateCollisions =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsLateCollisions);
- retStats->dot3StatsExcessiveCollsions =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsExcessiveCollsions);
- retStats->dot3StatsInternalMacTransmitErrors =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsInternalMacTransmitErrors);
- retStats->dot3StatsCarrierSenseErrors =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsCarrierSenseErrors);
- retStats->TxLargeFrameDiscards =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->TxLargeFrameDiscards);
- retStats->TxVLANIdFilterDiscards =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->TxVLANIdFilterDiscards);
-}
-
-IxEthAccStatus
-ixEthAccMibIIStatsGet (IxEthAccPortId portId,
- IxEthEthObjStats *retStats )
-{
- IxNpeMhMessage message;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- printf("EthAcc: ixEthAccMibIIStatsGet (Mac) EthAcc service is not initialized\n");
- return (IX_ETH_ACC_FAIL);
- }
-
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (retStats == NULL)
- {
- printf("EthAcc: ixEthAccMibIIStatsGet (Mac) NULL argument\n");
- return (IX_ETH_ACC_FAIL);
- }
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- printf("EthAcc: ixEthAccMibIIStatsGet (Mac) NPE for port %d is not available\n", portId);
-
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot get MIB II Stats.\n",(INT32)portId,0,0,0,0,0);
-
- /* Return all zero stats */
- IX_ETH_ACC_MEMSET(retStats, 0, sizeof(IxEthEthObjStats));
-
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- printf("EthAcc: ixEthAccMibIIStatsGet (Mac) port %d is not initialized\n", portId);
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- IX_OSAL_CACHE_INVALIDATE(retStats, sizeof(IxEthEthObjStats));
-
- message.data[0] = IX_ETHNPE_GETSTATS << IX_ETH_ACC_MAC_MSGID_SHL;
- message.data[1] = (UINT32) IX_OSAL_MMU_VIRT_TO_PHYS(retStats);
-
- /* Permit only one task to request MIB statistics Get operation
- at a time */
- ixOsalMutexLock(&ixEthAccMacState[portId].MIBStatsGetAccessLock, IX_OSAL_WAIT_FOREVER);
-
- if(ixNpeMhMessageWithResponseSend(IX_ETH_ACC_PORT_TO_NPE_ID(portId),
- message,
- IX_ETHNPE_GETSTATS,
- ixEthAccMacNpeStatsMessageCallback,
- IX_NPEMH_SEND_RETRIES_DEFAULT)
- != IX_SUCCESS)
- {
- ixOsalMutexUnlock(&ixEthAccMacState[portId].MIBStatsGetAccessLock);
-
- printf("EthAcc: (Mac) StatsGet failed to send NPE message\n");
-
- return IX_ETH_ACC_FAIL;
- }
-
- /* Wait for callback invocation indicating response to
- this request - we need this mutex in order to ensure
- that the return from this function is synchronous */
- ixOsalMutexLock(&ixEthAccMacState[portId].ackMIBStatsLock, IX_ETH_ACC_MIB_STATS_DELAY_MSECS);
-
- /* Permit other tasks to perform MIB statistics Get operation */
- ixOsalMutexUnlock(&ixEthAccMacState[portId].MIBStatsGetAccessLock);
-
- ixEthAccMibIIStatsEndianConvert (retStats);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-
-PRIVATE void
-ixEthAccMacNpeStatsResetMessageCallback (IxNpeMhNpeId npeId,
- IxNpeMhMessage msg)
-{
- IxEthAccPortId portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId);
-
-#ifndef NDEBUG
- /* Prudent to at least check the port is within range */
- if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS)
- {
- IX_ETH_ACC_FATAL_LOG(
- "IXETHACC:ixEthAccMacNpeStatsResetMessageCallback: Illegal port: %u\n",
- (UINT32)portId, 0, 0, 0, 0, 0);
- return;
- }
-#endif
-
- /*Unblock Stats Get & reset call*/
- ixOsalMutexUnlock(&ixEthAccMacState[portId].ackMIBStatsResetLock);
-
-}
-
-
-
-IxEthAccStatus
-ixEthAccMibIIStatsGetClear (IxEthAccPortId portId,
- IxEthEthObjStats *retStats)
-{
- IxNpeMhMessage message;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- printf("EthAcc: ixEthAccMibIIStatsGetClear (Mac) EthAcc service is not initialized\n");
- return (IX_ETH_ACC_FAIL);
- }
-
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (retStats == NULL)
- {
- printf("EthAcc: ixEthAccMibIIStatsGetClear (Mac) NULL argument\n");
- return (IX_ETH_ACC_FAIL);
- }
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- printf("EthAcc: ixEthAccMibIIStatsGetClear (Mac) NPE for port %d is not available\n", portId);
-
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot get and clear MIB II Stats.\n", (INT32)portId, 0, 0, 0, 0, 0);
-
- /* Return all zero stats */
- IX_ETH_ACC_MEMSET(retStats, 0, sizeof(IxEthEthObjStats));
-
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- printf("EthAcc: ixEthAccMibIIStatsGetClear (Mac) port %d is not initialized\n", portId);
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- IX_OSAL_CACHE_INVALIDATE(retStats, sizeof(IxEthEthObjStats));
-
- message.data[0] = IX_ETHNPE_RESETSTATS << IX_ETH_ACC_MAC_MSGID_SHL;
- message.data[1] = (UINT32) IX_OSAL_MMU_VIRT_TO_PHYS(retStats);
-
- /* Permit only one task to request MIB statistics Get-Reset operation at a time */
- ixOsalMutexLock(&ixEthAccMacState[portId].MIBStatsGetResetAccessLock, IX_OSAL_WAIT_FOREVER);
-
- if(ixNpeMhMessageWithResponseSend(IX_ETH_ACC_PORT_TO_NPE_ID(portId),
- message,
- IX_ETHNPE_RESETSTATS,
- ixEthAccMacNpeStatsResetMessageCallback,
- IX_NPEMH_SEND_RETRIES_DEFAULT)
- != IX_SUCCESS)
- {
- ixOsalMutexUnlock(&ixEthAccMacState[portId].MIBStatsGetResetAccessLock);
-
- printf("EthAcc: (Mac) ixEthAccMibIIStatsGetClear failed to send NPE message\n");
-
- return IX_ETH_ACC_FAIL;
- }
-
- /* Wait for callback invocation indicating response to this request */
- ixOsalMutexLock(&ixEthAccMacState[portId].ackMIBStatsResetLock, IX_ETH_ACC_MIB_STATS_DELAY_MSECS);
-
- /* permit other tasks to get and reset MIB stats*/
- ixOsalMutexUnlock(&ixEthAccMacState[portId].MIBStatsGetResetAccessLock);
-
- ixEthAccMibIIStatsEndianConvert(retStats);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccMibIIStatsClear (IxEthAccPortId portId)
-{
- static IxEthEthObjStats retStats;
- IxEthAccStatus status;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot clear MIB II Stats.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- /* there is no reset operation without a corresponding Get */
- status = ixEthAccMibIIStatsGetClear(portId, &retStats);
-
- return status;
-}
-
-/* Initialize the ethernet MAC settings */
-IxEthAccStatus
-ixEthAccMacInit(IxEthAccPortId portId)
-{
- IX_OSAL_MBUF_POOL* portDisablePool;
- UINT8 *data;
-
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot initialize Mac.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if(ixEthAccMacState[portId].macInitialised == false)
- {
- ixEthAccMacState[portId].fullDuplex = true;
- ixEthAccMacState[portId].rxFCSAppend = true;
- ixEthAccMacState[portId].txFCSAppend = true;
- ixEthAccMacState[portId].txPADAppend = true;
- ixEthAccMacState[portId].enabled = false;
- ixEthAccMacState[portId].promiscuous = true;
- ixEthAccMacState[portId].joinAll = false;
- ixEthAccMacState[portId].initDone = false;
- ixEthAccMacState[portId].macInitialised = true;
-
- /* initialize MIB stats mutexes */
- ixOsalMutexInit(&ixEthAccMacState[portId].ackMIBStatsLock);
- ixOsalMutexLock(&ixEthAccMacState[portId].ackMIBStatsLock, IX_OSAL_WAIT_FOREVER);
-
- ixOsalMutexInit(&ixEthAccMacState[portId].ackMIBStatsResetLock);
- ixOsalMutexLock(&ixEthAccMacState[portId].ackMIBStatsResetLock, IX_OSAL_WAIT_FOREVER);
-
- ixOsalMutexInit(&ixEthAccMacState[portId].MIBStatsGetAccessLock);
-
- ixOsalMutexInit(&ixEthAccMacState[portId].MIBStatsGetResetAccessLock);
-
- ixOsalMutexInit(&ixEthAccMacState[portId].npeLoopbackMessageLock);
-
- ixEthAccMacState[portId].portDisableRxMbufPtr = NULL;
- ixEthAccMacState[portId].portDisableTxMbufPtr = NULL;
-
- portDisablePool = IX_OSAL_MBUF_POOL_INIT(2,
- IX_ETHACC_RX_MBUF_MIN_SIZE,
- "portDisable Pool");
-
- IX_OSAL_ENSURE(portDisablePool != NULL, "Failed to initialize PortDisable pool");
-
- ixEthAccMacState[portId].portDisableRxMbufPtr = IX_OSAL_MBUF_POOL_GET(portDisablePool);
- ixEthAccMacState[portId].portDisableTxMbufPtr = IX_OSAL_MBUF_POOL_GET(portDisablePool);
-
- IX_OSAL_ENSURE(ixEthAccMacState[portId].portDisableRxMbufPtr != NULL,
- "Pool allocation failed");
- IX_OSAL_ENSURE(ixEthAccMacState[portId].portDisableTxMbufPtr != NULL,
- "Pool allocation failed");
- /* fill the payload of the Rx mbuf used in portDisable */
- IX_OSAL_MBUF_MLEN(ixEthAccMacState[portId].portDisableRxMbufPtr) = IX_ETHACC_RX_MBUF_MIN_SIZE;
-
- memset(IX_OSAL_MBUF_MDATA(ixEthAccMacState[portId].portDisableRxMbufPtr),
- 0xAA,
- IX_ETHACC_RX_MBUF_MIN_SIZE);
-
- /* fill the payload of the Tx mbuf used in portDisable (64 bytes) */
- IX_OSAL_MBUF_MLEN(ixEthAccMacState[portId].portDisableTxMbufPtr) = 64;
- IX_OSAL_MBUF_PKT_LEN(ixEthAccMacState[portId].portDisableTxMbufPtr) = 64;
-
- data = (UINT8 *) IX_OSAL_MBUF_MDATA(ixEthAccMacState[portId].portDisableTxMbufPtr);
- memset(data, 0xBB, 64);
- data[0] = 0x00; /* unicast destination MAC address */
- data[6] = 0x00; /* unicast source MAC address */
- data[12] = 0x08; /* typelength : IP frame */
- data[13] = 0x00; /* typelength : IP frame */
-
- IX_OSAL_CACHE_FLUSH(data, 64);
- }
-
- IX_OSAL_ASSERT (ixEthAccMacBase[portId] != 0);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_CORE_CNTRL,
- IX_ETH_ACC_CORE_RESET);
-
- ixOsalSleep(IX_ETH_ACC_MAC_RESET_DELAY);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_CORE_CNTRL,
- IX_ETH_ACC_CORE_MDC_EN);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_INT_CLK_THRESH,
- IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT);
-
- ixEthAccMacStateUpdate(portId);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-/* PRIVATE Functions*/
-
-PRIVATE void
-ixEthAccMacStateUpdate(IxEthAccPortId portId)
-{
- UINT32 regval;
-
- if ( ixEthAccMacState[portId].enabled == false )
- {
- /* Just disable both the transmitter and reciver in the MAC. */
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval);
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval & ~IX_ETH_ACC_RX_CNTRL1_RX_EN);
-
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval);
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval & ~IX_ETH_ACC_TX_CNTRL1_TX_EN);
- }
-
- if(ixEthAccMacState[portId].fullDuplex)
- {
- ixEthAccPortDuplexModeSetPriv (portId, IX_ETH_ACC_FULL_DUPLEX);
- }
- else
- {
- ixEthAccPortDuplexModeSetPriv (portId, IX_ETH_ACC_HALF_DUPLEX);
- }
-
- if(ixEthAccMacState[portId].rxFCSAppend)
- {
- ixEthAccPortRxFrameAppendFCSEnablePriv (portId);
- }
- else
- {
- ixEthAccPortRxFrameAppendFCSDisablePriv (portId);
- }
-
- if(ixEthAccMacState[portId].txFCSAppend)
- {
- ixEthAccPortTxFrameAppendFCSEnablePriv (portId);
- }
- else
- {
- ixEthAccPortTxFrameAppendFCSDisablePriv (portId);
- }
-
- if(ixEthAccMacState[portId].txPADAppend)
- {
- ixEthAccPortTxFrameAppendPaddingEnablePriv (portId);
- }
- else
- {
- ixEthAccPortTxFrameAppendPaddingDisablePriv (portId);
- }
-
- if(ixEthAccMacState[portId].promiscuous)
- {
- ixEthAccPortPromiscuousModeSetPriv(portId);
- }
- else
- {
- ixEthAccPortPromiscuousModeClearPriv(portId);
- }
-
- if ( ixEthAccMacState[portId].enabled == true )
- {
- /* Enable both the transmitter and reciver in the MAC. */
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval);
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval | IX_ETH_ACC_RX_CNTRL1_RX_EN);
-
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval);
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval | IX_ETH_ACC_TX_CNTRL1_TX_EN);
- }
-}
-
-
-PRIVATE BOOL
-ixEthAccMacEqual(IxEthAccMacAddr *macAddr1,
- IxEthAccMacAddr *macAddr2)
-{
- UINT32 i;
- for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE; i++)
- {
- if(macAddr1->macAddress[i] != macAddr2->macAddress[i])
- {
- return false;
- }
- }
- return true;
-}
-
-PRIVATE void
-ixEthAccMacPrint(IxEthAccMacAddr *m)
-{
- printf("%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x",
- m->macAddress[0], m->macAddress[1],
- m->macAddress[2], m->macAddress[3],
- m->macAddress[4], m->macAddress[5]);
-}
-
-/* Set the multicast address and address mask registers
- *
- * A bit in the address mask register must be set if
- * all multicast addresses always have that bit set, or if
- * all multicast addresses always have that bit cleared.
- *
- * A bit in the address register must be set if all multicast
- * addresses have that bit set, otherwise, it should be cleared
- */
-
-PRIVATE void
-ixEthAccMulticastAddressSet(IxEthAccPortId portId)
-{
- UINT32 i;
- UINT32 j;
- IxEthAccMacAddr addressMask;
- IxEthAccMacAddr address;
- IxEthAccMacAddr alwaysClearBits;
- IxEthAccMacAddr alwaysSetBits;
-
- /* calculate alwaysClearBits and alwaysSetBits:
- * alwaysClearBits is calculated by ORing all
- * multicast addresses, those bits that are always
- * clear are clear in the result
- *
- * alwaysSetBits is calculated by ANDing all
- * multicast addresses, those bits that are always set
- * are set in the result
- */
-
- if (ixEthAccMacState[portId].promiscuous == true)
- {
- /* Promiscuous Mode is set, and filtering
- * allow all packets, and enable the mcast and
- * bcast detection.
- */
- memset(&addressMask.macAddress,
- 0,
- IX_IEEE803_MAC_ADDRESS_SIZE);
- memset(&address.macAddress,
- 0,
- IX_IEEE803_MAC_ADDRESS_SIZE);
- }
- else
- {
- if(ixEthAccMacState[portId].joinAll == true)
- {
- /* Join all is set. The mask and address are
- * the multicast settings.
- */
- IxEthAccMacAddr macAddr = {{0x1,0x0,0x0,0x0,0x0,0x0}};
-
- memcpy(addressMask.macAddress,
- macAddr.macAddress,
- IX_IEEE803_MAC_ADDRESS_SIZE);
- memcpy(address.macAddress,
- macAddr.macAddress,
- IX_IEEE803_MAC_ADDRESS_SIZE);
- }
- else if(ixEthAccMacState[portId].mcastAddrIndex == 0)
- {
- /* No entry in the filtering database,
- * Promiscuous Mode is cleared, Broadcast filtering
- * is configured.
- */
- memset(addressMask.macAddress,
- IX_ETH_ACC_MAC_ALL_BITS_SET,
- IX_IEEE803_MAC_ADDRESS_SIZE);
- memset(address.macAddress,
- IX_ETH_ACC_MAC_ALL_BITS_SET,
- IX_IEEE803_MAC_ADDRESS_SIZE);
- }
- else
- {
- /* build a mask and an address which mix all entreis
- * from the list of multicast addresses
- */
- memset(alwaysClearBits.macAddress,
- 0,
- IX_IEEE803_MAC_ADDRESS_SIZE);
- memset(alwaysSetBits.macAddress,
- IX_ETH_ACC_MAC_ALL_BITS_SET,
- IX_IEEE803_MAC_ADDRESS_SIZE);
-
- for(i=0;i<ixEthAccMacState[portId].mcastAddrIndex;i++)
- {
- for(j=0;j<IX_IEEE803_MAC_ADDRESS_SIZE;j++)
- {
- alwaysClearBits.macAddress[j] |=
- ixEthAccMacState[portId].mcastAddrsTable[i].macAddress[j];
- alwaysSetBits.macAddress[j] &=
- ixEthAccMacState[portId].mcastAddrsTable[i].macAddress[j];
- }
- }
-
- for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE;i++)
- {
- addressMask.macAddress[i] = alwaysSetBits.macAddress[i]
- | ~alwaysClearBits.macAddress[i];
- address.macAddress[i] = alwaysSetBits.macAddress[i];
- }
- }
- }
-
- /*write the new addr filtering to h/w*/
- for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE;i++)
- {
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_ADDR_MASK_1+i*sizeof(UINT32),
- addressMask.macAddress[i]);
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_ADDR_1+i*sizeof(UINT32),
- address.macAddress[i]);
- }
-}
+++ /dev/null
-/**
- * @file IxEthAccMii.c
- *
- * @author Intel Corporation
- * @date
- *
- * @brief MII control functions
- *
- * Design Notes:
- *
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxOsal.h"
-#include "IxEthAcc.h"
-#include "IxEthAcc_p.h"
-#include "IxEthAccMac_p.h"
-#include "IxEthAccMii_p.h"
-
-
-PRIVATE UINT32 miiBaseAddressVirt;
-PRIVATE IxOsalMutex miiAccessLock;
-
-PUBLIC UINT32 ixEthAccMiiRetryCount = IX_ETH_ACC_MII_TIMEOUT_10TH_SECS;
-PUBLIC UINT32 ixEthAccMiiAccessTimeout = IX_ETH_ACC_MII_10TH_SEC_IN_MILLIS;
-
-/* -----------------------------------
- * private function prototypes
- */
-PRIVATE void
-ixEthAccMdioCmdWrite(UINT32 mdioCommand);
-
-PRIVATE void
-ixEthAccMdioCmdRead(UINT32 *data);
-
-PRIVATE void
-ixEthAccMdioStatusRead(UINT32 *data);
-
-
-PRIVATE void
-ixEthAccMdioCmdWrite(UINT32 mdioCommand)
-{
- REG_WRITE(miiBaseAddressVirt,
- IX_ETH_ACC_MAC_MDIO_CMD_1,
- mdioCommand & 0xff);
-
- REG_WRITE(miiBaseAddressVirt,
- IX_ETH_ACC_MAC_MDIO_CMD_2,
- (mdioCommand >> 8) & 0xff);
-
- REG_WRITE(miiBaseAddressVirt,
- IX_ETH_ACC_MAC_MDIO_CMD_3,
- (mdioCommand >> 16) & 0xff);
-
- REG_WRITE(miiBaseAddressVirt,
- IX_ETH_ACC_MAC_MDIO_CMD_4,
- (mdioCommand >> 24) & 0xff);
-}
-
-PRIVATE void
-ixEthAccMdioCmdRead(UINT32 *data)
-{
- UINT32 regval;
-
- REG_READ(miiBaseAddressVirt,
- IX_ETH_ACC_MAC_MDIO_CMD_1,
- regval);
-
- *data = regval & 0xff;
-
- REG_READ(miiBaseAddressVirt,
- IX_ETH_ACC_MAC_MDIO_CMD_2,
- regval);
-
- *data |= (regval & 0xff) << 8;
-
- REG_READ(miiBaseAddressVirt,
- IX_ETH_ACC_MAC_MDIO_CMD_3,
- regval);
-
- *data |= (regval & 0xff) << 16;
-
- REG_READ(miiBaseAddressVirt,
- IX_ETH_ACC_MAC_MDIO_CMD_4,
- regval);
-
- *data |= (regval & 0xff) << 24;
-
-}
-
-PRIVATE void
-ixEthAccMdioStatusRead(UINT32 *data)
-{
- UINT32 regval;
-
- REG_READ(miiBaseAddressVirt,
- IX_ETH_ACC_MAC_MDIO_STS_1,
- regval);
-
- *data = regval & 0xff;
-
- REG_READ(miiBaseAddressVirt,
- IX_ETH_ACC_MAC_MDIO_STS_2,
- regval);
-
- *data |= (regval & 0xff) << 8;
-
- REG_READ(miiBaseAddressVirt,
- IX_ETH_ACC_MAC_MDIO_STS_3,
- regval);
-
- *data |= (regval & 0xff) << 16;
-
- REG_READ(miiBaseAddressVirt,
- IX_ETH_ACC_MAC_MDIO_STS_4,
- regval);
-
- *data |= (regval & 0xff) << 24;
-
-}
-
-
-/********************************************************************
- * ixEthAccMiiInit
- */
-IxEthAccStatus
-ixEthAccMiiInit()
-{
- if(ixOsalMutexInit(&miiAccessLock)!= IX_SUCCESS)
- {
- return IX_ETH_ACC_FAIL;
- }
-
- miiBaseAddressVirt = (UINT32) IX_OSAL_MEM_MAP(IX_ETH_ACC_MAC_0_BASE, IX_OSAL_IXP400_ETHA_MAP_SIZE);
-
- if (miiBaseAddressVirt == 0)
- {
- ixOsalLog(IX_OSAL_LOG_LVL_FATAL,
- IX_OSAL_LOG_DEV_STDOUT,
- "EthAcc: Could not map MII I/O mapped memory\n",
- 0, 0, 0, 0, 0, 0);
-
- return IX_ETH_ACC_FAIL;
- }
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-void
-ixEthAccMiiUnload(void)
-{
- IX_OSAL_MEM_UNMAP(miiBaseAddressVirt);
-
- miiBaseAddressVirt = 0;
-}
-
-PUBLIC IxEthAccStatus
-ixEthAccMiiAccessTimeoutSet(UINT32 timeout, UINT32 retryCount)
-{
- if (retryCount < 1) return IX_ETH_ACC_FAIL;
-
- ixEthAccMiiRetryCount = retryCount;
- ixEthAccMiiAccessTimeout = timeout;
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-/*********************************************************************
- * ixEthAccMiiReadRtn - read a 16 bit value from a PHY
- */
-IxEthAccStatus
-ixEthAccMiiReadRtn (UINT8 phyAddr,
- UINT8 phyReg,
- UINT16 *value)
-{
- UINT32 mdioCommand;
- UINT32 regval;
- UINT32 miiTimeout;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- if ((phyAddr >= IXP425_ETH_ACC_MII_MAX_ADDR)
- || (phyReg >= IXP425_ETH_ACC_MII_MAX_REG))
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- if (value == NULL)
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER);
- mdioCommand = phyReg << IX_ETH_ACC_MII_REG_SHL
- | phyAddr << IX_ETH_ACC_MII_ADDR_SHL;
- mdioCommand |= IX_ETH_ACC_MII_GO;
-
- ixEthAccMdioCmdWrite(mdioCommand);
-
- miiTimeout = ixEthAccMiiRetryCount;
-
- while(miiTimeout)
- {
-
- ixEthAccMdioCmdRead(®val);
-
- if((regval & IX_ETH_ACC_MII_GO) == 0x0)
- {
- break;
- }
- /* Sleep for a while */
- ixOsalSleep(ixEthAccMiiAccessTimeout);
- miiTimeout--;
- }
-
-
-
- if(miiTimeout == 0)
- {
- ixOsalMutexUnlock(&miiAccessLock);
- *value = 0xffff;
- return IX_ETH_ACC_FAIL;
- }
-
-
- ixEthAccMdioStatusRead(®val);
- if(regval & IX_ETH_ACC_MII_READ_FAIL)
- {
- ixOsalMutexUnlock(&miiAccessLock);
- *value = 0xffff;
- return IX_ETH_ACC_FAIL;
- }
-
- *value = regval & 0xffff;
- ixOsalMutexUnlock(&miiAccessLock);
- return IX_ETH_ACC_SUCCESS;
-
-}
-
-
-/*********************************************************************
- * ixEthAccMiiWriteRtn - write a 16 bit value to a PHY
- */
-IxEthAccStatus
-ixEthAccMiiWriteRtn (UINT8 phyAddr,
- UINT8 phyReg,
- UINT16 value)
-{
- UINT32 mdioCommand;
- UINT32 regval;
- UINT16 readVal;
- UINT32 miiTimeout;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- if ((phyAddr >= IXP425_ETH_ACC_MII_MAX_ADDR)
- || (phyReg >= IXP425_ETH_ACC_MII_MAX_REG))
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- /* ensure that a PHY is present at this address */
- if(ixEthAccMiiReadRtn(phyAddr,
- IX_ETH_ACC_MII_CTRL_REG,
- &readVal) != IX_ETH_ACC_SUCCESS)
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER);
- mdioCommand = phyReg << IX_ETH_ACC_MII_REG_SHL
- | phyAddr << IX_ETH_ACC_MII_ADDR_SHL ;
- mdioCommand |= IX_ETH_ACC_MII_GO | IX_ETH_ACC_MII_WRITE | value;
-
- ixEthAccMdioCmdWrite(mdioCommand);
-
- miiTimeout = ixEthAccMiiRetryCount;
-
- while(miiTimeout)
- {
-
- ixEthAccMdioCmdRead(®val);
-
- /*The "GO" bit is reset to 0 when the write completes*/
- if((regval & IX_ETH_ACC_MII_GO) == 0x0)
- {
- break;
- }
- /* Sleep for a while */
- ixOsalSleep(ixEthAccMiiAccessTimeout);
- miiTimeout--;
- }
-
- ixOsalMutexUnlock(&miiAccessLock);
- if(miiTimeout == 0)
- {
- return IX_ETH_ACC_FAIL;
- }
- return IX_ETH_ACC_SUCCESS;
-}
-
-
-/*****************************************************************
- *
- * Phy query functions
- *
- */
-IxEthAccStatus
-ixEthAccMiiStatsShow (UINT32 phyAddr)
-{
- UINT16 regval;
- printf("Regisers on PHY at address 0x%x\n", phyAddr);
- ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_CTRL_REG, ®val);
- printf(" Control Register : 0x%4.4x\n", regval);
- ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_STAT_REG, ®val);
- printf(" Status Register : 0x%4.4x\n", regval);
- ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_PHY_ID1_REG, ®val);
- printf(" PHY ID1 Register : 0x%4.4x\n", regval);
- ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_PHY_ID2_REG, ®val);
- printf(" PHY ID2 Register : 0x%4.4x\n", regval);
- ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_AN_ADS_REG, ®val);
- printf(" Auto Neg ADS Register : 0x%4.4x\n", regval);
- ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_AN_PRTN_REG, ®val);
- printf(" Auto Neg Partner Ability Register : 0x%4.4x\n", regval);
- ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_AN_EXP_REG, ®val);
- printf(" Auto Neg Expansion Register : 0x%4.4x\n", regval);
- ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_AN_NEXT_REG, ®val);
- printf(" Auto Neg Next Register : 0x%4.4x\n", regval);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-
-/*****************************************************************
- *
- * Interface query functions
- *
- */
-IxEthAccStatus
-ixEthAccMdioShow (void)
-{
- UINT32 regval;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER);
- ixEthAccMdioCmdRead(®val);
- ixOsalMutexUnlock(&miiAccessLock);
-
- printf("MDIO command register\n");
- printf(" Go bit : 0x%x\n", (regval & BIT(31)) >> 31);
- printf(" MDIO Write : 0x%x\n", (regval & BIT(26)) >> 26);
- printf(" PHY address : 0x%x\n", (regval >> 21) & 0x1f);
- printf(" Reg address : 0x%x\n", (regval >> 16) & 0x1f);
-
- ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER);
- ixEthAccMdioStatusRead(®val);
- ixOsalMutexUnlock(&miiAccessLock);
-
- printf("MDIO status register\n");
- printf(" Read OK : 0x%x\n", (regval & BIT(31)) >> 31);
- printf(" Read Data : 0x%x\n", (regval >> 16) & 0xff);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
+++ /dev/null
-/**
- * @file IxEthDBAPI.c
- *
- * @brief Implementation of the public API
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB_p.h"
-#include "IxFeatureCtrl.h"
-
-extern HashTable dbHashtable;
-extern IxEthDBPortMap overflowUpdatePortList;
-extern BOOL ixEthDBPortUpdateRequired[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1];
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringStaticEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING);
-
- return ixEthDBTriggerAddPortUpdate(macAddr, portID, true);
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringDynamicEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING);
-
- return ixEthDBTriggerAddPortUpdate(macAddr, portID, false);
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringEntryDelete(IxEthDBMacAddr *macAddr)
-{
- HashNode *searchResult;
-
- IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
- searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS);
-
- if (searchResult == NULL)
- {
- return IX_ETH_DB_NO_SUCH_ADDR; /* not found */
- }
-
- ixEthDBReleaseHashNode(searchResult);
-
- /* build a remove event and place it on the event queue */
- return ixEthDBTriggerRemovePortUpdate(macAddr, ((MacDescriptor *) searchResult->data)->portID);
-}
-
-IX_ETH_DB_PUBLIC
-void ixEthDBDatabaseMaintenance()
-{
- HashIterator iterator;
- UINT32 portIndex;
- BOOL agingRequired = false;
-
- /* ports who will have deleted records and therefore will need updating */
- IxEthDBPortMap triggerPorts;
-
- if (IX_FEATURE_CTRL_SWCONFIG_ENABLED !=
- ixFeatureCtrlSwConfigurationCheck (IX_FEATURECTRL_ETH_LEARNING))
- {
- return;
- }
-
- SET_EMPTY_DEPENDENCY_MAP(triggerPorts);
-
- /* check if there's at least a port that needs aging */
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- if (ixEthDBPortInfo[portIndex].agingEnabled && ixEthDBPortInfo[portIndex].enabled)
- {
- agingRequired = true;
- }
- }
-
- if (agingRequired)
- {
- /* ask each NPE port to write back the database for aging inspection */
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE
- && ixEthDBPortInfo[portIndex].agingEnabled
- && ixEthDBPortInfo[portIndex].enabled)
- {
- IxNpeMhMessage message;
- IX_STATUS result;
-
- /* send EDB_GetMACAddressDatabase message */
- FILL_GETMACADDRESSDATABASE(message,
- 0 /* unused */,
- IX_OSAL_MMU_VIRT_TO_PHYS(ixEthDBPortInfo[portIndex].updateMethod.npeUpdateZone));
-
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portIndex), message, result);
-
- if (result == IX_SUCCESS)
- {
- /* analyze NPE copy */
- ixEthDBNPESyncScan(portIndex, ixEthDBPortInfo[portIndex].updateMethod.npeUpdateZone, FULL_ELT_BYTE_SIZE);
-
- IX_ETH_DB_SUPPORT_TRACE("DB: (API) Finished scanning NPE tree on port %d\n", portIndex);
- }
- else
- {
- ixEthDBPortInfo[portIndex].agingEnabled = false;
- ixEthDBPortInfo[portIndex].updateMethod.updateEnabled = false;
- ixEthDBPortInfo[portIndex].updateMethod.userControlled = true;
-
- ixOsalLog(IX_OSAL_LOG_LVL_FATAL,
- IX_OSAL_LOG_DEV_STDOUT,
- "EthDB: (Maintenance) warning, disabling aging and updates for port %d (assumed dead)\n",
- portIndex, 0, 0, 0, 0, 0);
-
- ixEthDBDatabaseClear(portIndex, IX_ETH_DB_ALL_RECORD_TYPES);
- }
- }
- }
-
- /* browse database and age entries */
- BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator));
-
- while (IS_ITERATOR_VALID(&iterator))
- {
- MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data;
- UINT32 *age = NULL;
- BOOL staticEntry = true;
-
- if (descriptor->type == IX_ETH_DB_FILTERING_RECORD)
- {
- age = &descriptor->recordData.filteringData.age;
- staticEntry = descriptor->recordData.filteringData.staticEntry;
- }
- else if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD)
- {
- age = &descriptor->recordData.filteringVlanData.age;
- staticEntry = descriptor->recordData.filteringVlanData.staticEntry;
- }
- else
- {
- staticEntry = true;
- }
-
- if (ixEthDBPortInfo[descriptor->portID].agingEnabled && (staticEntry == false))
- {
- /* manually increment the age if the port has no such capability */
- if ((ixEthDBPortDefinitions[descriptor->portID].capabilities & IX_ETH_ENTRY_AGING) == 0)
- {
- *age += (IX_ETH_DB_MAINTENANCE_TIME / 60);
- }
-
- /* age entry if it exceeded the maximum time to live */
- if (*age >= (IX_ETH_DB_LEARNING_ENTRY_AGE_TIME / 60))
- {
- /* add port to the set of update trigger ports */
- JOIN_PORT_TO_MAP(triggerPorts, descriptor->portID);
-
- /* delete entry */
- BUSY_RETRY(ixEthDBRemoveEntryAtHashIterator(&dbHashtable, &iterator));
- }
- else
- {
- /* move to the next record */
- BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator));
- }
- }
- else
- {
- /* move to the next record */
- BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator));
- }
- }
-
- /* update ports which lost records */
- ixEthDBUpdatePortLearningTrees(triggerPorts);
- }
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBDatabaseClear(IxEthDBPortId portID, IxEthDBRecordType recordType)
-{
- IxEthDBPortMap triggerPorts;
- HashIterator iterator;
-
- if (portID >= IX_ETH_DB_NUMBER_OF_PORTS && portID != IX_ETH_DB_ALL_PORTS)
- {
- return IX_ETH_DB_INVALID_PORT;
- }
-
- /* check if the user passes some extra bits */
- if ((recordType | IX_ETH_DB_ALL_RECORD_TYPES) != IX_ETH_DB_ALL_RECORD_TYPES)
- {
- return IX_ETH_DB_INVALID_ARG;
- }
-
- SET_EMPTY_DEPENDENCY_MAP(triggerPorts);
-
- /* browse database and age entries */
- BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator));
-
- while (IS_ITERATOR_VALID(&iterator))
- {
- MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data;
-
- if (((descriptor->portID == portID) || (portID == IX_ETH_DB_ALL_PORTS))
- && ((descriptor->type & recordType) != 0))
- {
- /* add to trigger if automatic updates are required */
- if (ixEthDBPortUpdateRequired[descriptor->type])
- {
- /* add port to the set of update trigger ports */
- JOIN_PORT_TO_MAP(triggerPorts, descriptor->portID);
- }
-
- /* delete entry */
- BUSY_RETRY(ixEthDBRemoveEntryAtHashIterator(&dbHashtable, &iterator));
- }
- else
- {
- /* move to the next record */
- BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator));
- }
- }
-
- /* update ports which lost records */
- ixEthDBUpdatePortLearningTrees(triggerPorts);
-
- return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringPortSearch(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
-{
- HashNode *searchResult;
- IxEthDBStatus result = IX_ETH_DB_NO_SUCH_ADDR;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING);
-
- searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS);
-
- if (searchResult == NULL)
- {
- return IX_ETH_DB_NO_SUCH_ADDR; /* not found */
- }
-
- if (((MacDescriptor *) (searchResult->data))->portID == portID)
- {
- result = IX_ETH_DB_SUCCESS; /* address and port match */
- }
-
- ixEthDBReleaseHashNode(searchResult);
-
- return result;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringDatabaseSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr)
-{
- HashNode *searchResult;
-
- IX_ETH_DB_CHECK_REFERENCE(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
- searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS);
-
- if (searchResult == NULL)
- {
- return IX_ETH_DB_NO_SUCH_ADDR; /* not found */
- }
-
- /* return the port ID */
- *portID = ((MacDescriptor *) searchResult->data)->portID;
-
- ixEthDBReleaseHashNode(searchResult);
-
- return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortAgingDisable(IxEthDBPortId portID)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING);
-
- ixEthDBPortInfo[portID].agingEnabled = false;
-
- return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortAgingEnable(IxEthDBPortId portID)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING);
-
- ixEthDBPortInfo[portID].agingEnabled = true;
-
- return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringPortUpdatingSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr)
-{
- HashNode *searchResult;
- MacDescriptor *descriptor;
-
- IX_ETH_DB_CHECK_REFERENCE(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
- searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS);
-
- if (searchResult == NULL)
- {
- return IX_ETH_DB_NO_SUCH_ADDR; /* not found */
- }
-
- descriptor = (MacDescriptor *) searchResult->data;
-
- /* return the port ID */
- *portID = descriptor->portID;
-
- /* reset entry age */
- if (descriptor->type == IX_ETH_DB_FILTERING_RECORD)
- {
- descriptor->recordData.filteringData.age = 0;
- }
- else
- {
- descriptor->recordData.filteringVlanData.age = 0;
- }
-
- ixEthDBReleaseHashNode(searchResult);
-
- return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortDependencyMapSet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(dependencyPortMap);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FILTERING);
-
- /* force bit at offset 255 to 0 (reserved) */
- dependencyPortMap[31] &= 0xFE;
-
- COPY_DEPENDENCY_MAP(ixEthDBPortInfo[portID].dependencyPortMap, dependencyPortMap);
-
- return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortDependencyMapGet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(dependencyPortMap);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FILTERING);
-
- COPY_DEPENDENCY_MAP(dependencyPortMap, ixEthDBPortInfo[portID].dependencyPortMap);
-
- return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortUpdateEnableSet(IxEthDBPortId portID, BOOL enableUpdate)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FILTERING);
-
- ixEthDBPortInfo[portID].updateMethod.updateEnabled = enableUpdate;
- ixEthDBPortInfo[portID].updateMethod.userControlled = true;
-
- return IX_ETH_DB_SUCCESS;
-}
+++ /dev/null
-/**
- * @file IxEthDBAPISupport.c
- *
- * @brief Public API support functions
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include <IxEthDB.h>
-#include <IxNpeMh.h>
-#include <IxFeatureCtrl.h>
-
-#include "IxEthDB_p.h"
-#include "IxEthDBMessages_p.h"
-#include "IxEthDB_p.h"
-#include "IxEthDBLog_p.h"
-
-#ifdef IX_UNIT_TEST
-
-int dbAccessCounter = 0;
-int overflowEvent = 0;
-
-#endif
-
-/*
- * External declaration
- */
-extern HashTable dbHashtable;
-
-/*
- * Internal declaration
- */
-IX_ETH_DB_PUBLIC
-PortInfo ixEthDBPortInfo[IX_ETH_DB_NUMBER_OF_PORTS];
-
-IX_ETH_DB_PRIVATE
-struct
-{
- BOOL saved;
- IxEthDBPriorityTable priorityTable;
- IxEthDBVlanSet vlanMembership;
- IxEthDBVlanSet transmitTaggingInfo;
- IxEthDBFrameFilter frameFilter;
- IxEthDBTaggingAction taggingAction;
- IxEthDBFirewallMode firewallMode;
- BOOL stpBlocked;
- BOOL srcAddressFilterEnabled;
- UINT32 maxRxFrameSize;
- UINT32 maxTxFrameSize;
-} ixEthDBPortState[IX_ETH_DB_NUMBER_OF_PORTS];
-
-#define IX_ETH_DB_DEFAULT_FRAME_SIZE (1518)
-
-/**
- * @brief initializes a port
- *
- * @param portID ID of the port to be initialized
- *
- * Note that redundant initializations are silently
- * dealt with and do not constitute an error
- *
- * This function is fully documented in the main
- * header file, IxEthDB.h
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBPortInit(IxEthDBPortId portID)
-{
- PortInfo *portInfo;
-
- if (portID >= IX_ETH_DB_NUMBER_OF_PORTS)
- {
- return;
- }
-
- portInfo = &ixEthDBPortInfo[portID];
-
- if (ixEthDBSingleEthNpeCheck(portID) != IX_ETH_DB_SUCCESS)
- {
- WARNING_LOG("EthDB: Unavailable Eth %d: Cannot initialize EthDB Port.\n", (UINT32) portID);
-
- return;
- }
-
- if (portInfo->initialized)
- {
- /* redundant */
- return;
- }
-
- /* initialize core fields */
- portInfo->portID = portID;
- SET_DEPENDENCY_MAP(portInfo->dependencyPortMap, portID);
-
- /* default values */
- portInfo->agingEnabled = false;
- portInfo->enabled = false;
- portInfo->macAddressUploaded = false;
- portInfo->maxRxFrameSize = IX_ETHDB_DEFAULT_FRAME_SIZE;
- portInfo->maxTxFrameSize = IX_ETHDB_DEFAULT_FRAME_SIZE;
-
- /* default update control values */
- portInfo->updateMethod.searchTree = NULL;
- portInfo->updateMethod.searchTreePendingWrite = false;
- portInfo->updateMethod.treeInitialized = false;
- portInfo->updateMethod.updateEnabled = false;
- portInfo->updateMethod.userControlled = false;
-
- /* default WiFi parameters */
- memset(portInfo->bbsid, 0, sizeof (portInfo->bbsid));
- portInfo->frameControlDurationID = 0;
-
- /* Ethernet NPE-specific initializations */
- if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
- {
- /* update handler */
- portInfo->updateMethod.updateHandler = ixEthDBNPEUpdateHandler;
- }
-
- /* initialize state save */
- ixEthDBPortState[portID].saved = false;
-
- portInfo->initialized = true;
-}
-
-/**
- * @brief enables a port
- *
- * @param portID ID of the port to enable
- *
- * This function is fully documented in the main
- * header file, IxEthDB.h
- *
- * @return IX_ETH_DB_SUCCESS if enabling was
- * accomplished, or a meaningful error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID)
-{
- IxEthDBPortMap triggerPorts;
- PortInfo *portInfo;
-
- IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- portInfo = &ixEthDBPortInfo[portID];
-
- if (portInfo->enabled)
- {
- /* redundant */
- return IX_ETH_DB_SUCCESS;
- }
-
- SET_DEPENDENCY_MAP(triggerPorts, portID);
-
- /* mark as enabled */
- portInfo->enabled = true;
-
- /* Operation stops here when Ethernet Learning is not enabled */
- if(IX_FEATURE_CTRL_SWCONFIG_DISABLED ==
- ixFeatureCtrlSwConfigurationCheck(IX_FEATURECTRL_ETH_LEARNING))
- {
- return IX_ETH_DB_SUCCESS;
- }
-
- if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE && !portInfo->macAddressUploaded)
- {
- IX_ETH_DB_SUPPORT_TRACE("DB: (Support) MAC address not set on port %d, enable failed\n", portID);
-
- /* must use UnicastAddressSet() before enabling an NPE port */
- return IX_ETH_DB_MAC_UNINITIALIZED;
- }
-
- if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
- {
- IX_ETH_DB_SUPPORT_TRACE("DB: (Support) Attempting to enable the NPE callback for port %d...\n", portID);
-
- if (!portInfo->updateMethod.userControlled
- && ((portInfo->featureCapability & IX_ETH_DB_FILTERING) != 0))
- {
- portInfo->updateMethod.updateEnabled = true;
- }
-
- /* if this is first time initialization then we already have
- write access to the tree and can AccessRelease directly */
- if (!portInfo->updateMethod.treeInitialized)
- {
- IX_ETH_DB_SUPPORT_TRACE("DB: (Support) Initializing tree for port %d\n", portID);
-
- /* create an initial tree and release access into it */
- ixEthDBUpdatePortLearningTrees(triggerPorts);
-
- /* mark tree as being initialized */
- portInfo->updateMethod.treeInitialized = true;
- }
- }
-
- if (ixEthDBPortState[portID].saved)
- {
- /* previous configuration data stored, restore state */
- if ((portInfo->featureCapability & IX_ETH_DB_FIREWALL) != 0)
- {
- ixEthDBFirewallModeSet(portID, ixEthDBPortState[portID].firewallMode);
- ixEthDBFirewallInvalidAddressFilterEnable(portID, ixEthDBPortState[portID].srcAddressFilterEnabled);
- }
-
-#if 0 /* test-only */
- if ((portInfo->featureCapability & IX_ETH_DB_VLAN_QOS) != 0)
- {
- ixEthDBAcceptableFrameTypeSet(portID, ixEthDBPortState[portID].frameFilter);
- ixEthDBIngressVlanTaggingEnabledSet(portID, ixEthDBPortState[portID].taggingAction);
-
- ixEthDBEgressVlanTaggingEnabledSet(portID, ixEthDBPortState[portID].transmitTaggingInfo);
- ixEthDBPortVlanMembershipSet(portID, ixEthDBPortState[portID].vlanMembership);
-
- ixEthDBPriorityMappingTableSet(portID, ixEthDBPortState[portID].priorityTable);
- }
-#endif
-
- if ((portInfo->featureCapability & IX_ETH_DB_SPANNING_TREE_PROTOCOL) != 0)
- {
- ixEthDBSpanningTreeBlockingStateSet(portID, ixEthDBPortState[portID].stpBlocked);
- }
-
- ixEthDBFilteringPortMaximumRxFrameSizeSet(portID, ixEthDBPortState[portID].maxRxFrameSize);
- ixEthDBFilteringPortMaximumTxFrameSizeSet(portID, ixEthDBPortState[portID].maxTxFrameSize);
-
- /* discard previous save */
- ixEthDBPortState[portID].saved = false;
- }
-
- IX_ETH_DB_SUPPORT_TRACE("DB: (Support) Enabling succeeded for port %d\n", portID);
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief disables a port
- *
- * @param portID ID of the port to disable
- *
- * This function is fully documented in the
- * main header file, IxEthDB.h
- *
- * @return IX_ETH_DB_SUCCESS if disabling was
- * successful or an appropriate error message
- * otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID)
-{
- HashIterator iterator;
- IxEthDBPortMap triggerPorts; /* ports who will have deleted records and therefore will need updating */
- BOOL result;
- PortInfo *portInfo;
- IxEthDBFeature learningEnabled;
-#if 0 /* test-only */
- IxEthDBPriorityTable classZeroTable;
-#endif
-
- IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- portInfo = &ixEthDBPortInfo[portID];
-
- if (!portInfo->enabled)
- {
- /* redundant */
- return IX_ETH_DB_SUCCESS;
- }
-
- if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
- {
- /* save filtering state */
- ixEthDBPortState[portID].firewallMode = portInfo->firewallMode;
- ixEthDBPortState[portID].frameFilter = portInfo->frameFilter;
- ixEthDBPortState[portID].taggingAction = portInfo->taggingAction;
- ixEthDBPortState[portID].stpBlocked = portInfo->stpBlocked;
- ixEthDBPortState[portID].srcAddressFilterEnabled = portInfo->srcAddressFilterEnabled;
- ixEthDBPortState[portID].maxRxFrameSize = portInfo->maxRxFrameSize;
- ixEthDBPortState[portID].maxTxFrameSize = portInfo->maxTxFrameSize;
-
- memcpy(ixEthDBPortState[portID].vlanMembership, portInfo->vlanMembership, sizeof (IxEthDBVlanSet));
- memcpy(ixEthDBPortState[portID].transmitTaggingInfo, portInfo->transmitTaggingInfo, sizeof (IxEthDBVlanSet));
- memcpy(ixEthDBPortState[portID].priorityTable, portInfo->priorityTable, sizeof (IxEthDBPriorityTable));
-
- ixEthDBPortState[portID].saved = true;
-
- /* now turn off all EthDB filtering features on the port */
-
-#if 0 /* test-only */
- /* VLAN & QoS */
- if ((portInfo->featureCapability & IX_ETH_DB_VLAN_QOS) != 0)
- {
- ixEthDBPortVlanMembershipRangeAdd((IxEthDBPortId) portID, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID);
- ixEthDBEgressVlanRangeTaggingEnabledSet((IxEthDBPortId) portID, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID, false);
- ixEthDBAcceptableFrameTypeSet((IxEthDBPortId) portID, IX_ETH_DB_ACCEPT_ALL_FRAMES);
- ixEthDBIngressVlanTaggingEnabledSet((IxEthDBPortId) portID, IX_ETH_DB_PASS_THROUGH);
-
- memset(classZeroTable, 0, sizeof (classZeroTable));
- ixEthDBPriorityMappingTableSet((IxEthDBPortId) portID, classZeroTable);
- }
-#endif
-
- /* STP */
- if ((portInfo->featureCapability & IX_ETH_DB_SPANNING_TREE_PROTOCOL) != 0)
- {
- ixEthDBSpanningTreeBlockingStateSet((IxEthDBPortId) portID, false);
- }
-
- /* Firewall */
- if ((portInfo->featureCapability & IX_ETH_DB_FIREWALL) != 0)
- {
- ixEthDBFirewallModeSet((IxEthDBPortId) portID, IX_ETH_DB_FIREWALL_BLACK_LIST);
- ixEthDBFirewallTableDownload((IxEthDBPortId) portID);
- ixEthDBFirewallInvalidAddressFilterEnable((IxEthDBPortId) portID, false);
- }
-
- /* Frame size filter */
- ixEthDBFilteringPortMaximumFrameSizeSet((IxEthDBPortId) portID, IX_ETH_DB_DEFAULT_FRAME_SIZE);
-
- /* WiFi */
- if ((portInfo->featureCapability & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0)
- {
- ixEthDBWiFiConversionTableDownload((IxEthDBPortId) portID);
- }
-
- /* save and disable the learning feature bit */
- learningEnabled = portInfo->featureStatus & IX_ETH_DB_LEARNING;
- portInfo->featureStatus &= ~IX_ETH_DB_LEARNING;
- }
- else
- {
- /* save the learning feature bit */
- learningEnabled = portInfo->featureStatus & IX_ETH_DB_LEARNING;
- }
-
- SET_EMPTY_DEPENDENCY_MAP(triggerPorts);
-
- ixEthDBUpdateLock();
-
- /* wipe out current entries for this port */
- BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator));
-
- while (IS_ITERATOR_VALID(&iterator))
- {
- MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data;
-
- /* check if the port match. If so, remove the entry */
- if (descriptor->portID == portID
- && (descriptor->type == IX_ETH_DB_FILTERING_RECORD || descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD)
- && !descriptor->recordData.filteringData.staticEntry)
- {
- /* delete entry */
- BUSY_RETRY(ixEthDBRemoveEntryAtHashIterator(&dbHashtable, &iterator));
-
- /* add port to the set of update trigger ports */
- JOIN_PORT_TO_MAP(triggerPorts, portID);
- }
- else
- {
- /* move to the next record */
- BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator));
- }
- }
-
- if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
- {
- if (portInfo->updateMethod.searchTree != NULL)
- {
- ixEthDBFreeMacTreeNode(portInfo->updateMethod.searchTree);
- portInfo->updateMethod.searchTree = NULL;
- }
-
- ixEthDBNPEUpdateHandler(portID, IX_ETH_DB_FILTERING_RECORD);
- }
-
- /* mark as disabled */
- portInfo->enabled = false;
-
- /* disable updates unless the user has specifically altered the default behavior */
- if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
- {
- if (!portInfo->updateMethod.userControlled)
- {
- portInfo->updateMethod.updateEnabled = false;
- }
-
- /* make sure we re-initialize the NPE learning tree when the port is re-enabled */
- portInfo->updateMethod.treeInitialized = false;
- }
-
- ixEthDBUpdateUnlock();
-
- /* restore learning feature bit */
- portInfo->featureStatus |= learningEnabled;
-
- /* if we've removed any records or lost any events make sure to force an update */
- IS_EMPTY_DEPENDENCY_MAP(result, triggerPorts);
-
- if (!result)
- {
- ixEthDBUpdatePortLearningTrees(triggerPorts);
- }
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief sends the updated maximum Tx/Rx frame lengths to the NPE
- *
- * @param portID ID of the port to update
- *
- * @return IX_ETH_DB_SUCCESS if the update completed
- * successfully or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBPortFrameLengthsUpdate(IxEthDBPortId portID)
-{
- IxNpeMhMessage message;
- PortInfo *portInfo = &ixEthDBPortInfo[portID];
- IX_STATUS result;
-
- FILL_SETMAXFRAMELENGTHS_MSG(message, portID, portInfo->maxRxFrameSize, portInfo->maxTxFrameSize);
-
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- return result;
-}
-
-/**
- * @brief sets the port maximum Rx frame size
- *
- * @param portID ID of the port to set the frame size on
- * @param maximumRxFrameSize maximum Rx frame size
- *
- * This function updates the internal data structures and
- * calls ixEthDBPortFrameLengthsUpdate() for NPE update.
- *
- * This function is fully documented in the main header
- * file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation was
- * successfull or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringPortMaximumRxFrameSizeSet(IxEthDBPortId portID, UINT32 maximumRxFrameSize)
-{
- IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- if (!ixEthDBPortInfo[portID].initialized)
- {
- return IX_ETH_DB_PORT_UNINITIALIZED;
- }
-
- if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
- {
- if ((maximumRxFrameSize < IX_ETHDB_MIN_NPE_FRAME_SIZE) ||
- (maximumRxFrameSize > IX_ETHDB_MAX_NPE_FRAME_SIZE))
- {
- return IX_ETH_DB_INVALID_ARG;
- }
- }
- else
- {
- return IX_ETH_DB_NO_PERMISSION;
- }
-
- /* update internal structure */
- ixEthDBPortInfo[portID].maxRxFrameSize = maximumRxFrameSize;
-
- /* update the maximum frame size in the NPE */
- return ixEthDBPortFrameLengthsUpdate(portID);
-}
-
-/**
- * @brief sets the port maximum Tx frame size
- *
- * @param portID ID of the port to set the frame size on
- * @param maximumTxFrameSize maximum Tx frame size
- *
- * This function updates the internal data structures and
- * calls ixEthDBPortFrameLengthsUpdate() for NPE update.
- *
- * This function is fully documented in the main header
- * file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation was
- * successfull or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringPortMaximumTxFrameSizeSet(IxEthDBPortId portID, UINT32 maximumTxFrameSize)
-{
- IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- if (!ixEthDBPortInfo[portID].initialized)
- {
- return IX_ETH_DB_PORT_UNINITIALIZED;
- }
-
- if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
- {
- if ((maximumTxFrameSize < IX_ETHDB_MIN_NPE_FRAME_SIZE) ||
- (maximumTxFrameSize > IX_ETHDB_MAX_NPE_FRAME_SIZE))
- {
- return IX_ETH_DB_INVALID_ARG;
- }
- }
- else
- {
- return IX_ETH_DB_NO_PERMISSION;
- }
-
- /* update internal structure */
- ixEthDBPortInfo[portID].maxTxFrameSize = maximumTxFrameSize;
-
- /* update the maximum frame size in the NPE */
- return ixEthDBPortFrameLengthsUpdate(portID);
-}
-
-/**
- * @brief sets the port maximum Tx and Rx frame sizes
- *
- * @param portID ID of the port to set the frame size on
- * @param maximumFrameSize maximum Tx and Rx frame sizes
- *
- * This function updates the internal data structures and
- * calls ixEthDBPortFrameLengthsUpdate() for NPE update.
- *
- * Note that both the maximum Tx and Rx frame size are set
- * to the same value. This function is kept for compatibility
- * reasons.
- *
- * This function is fully documented in the main header
- * file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation was
- * successfull or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringPortMaximumFrameSizeSet(IxEthDBPortId portID, UINT32 maximumFrameSize)
-{
- IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- if (!ixEthDBPortInfo[portID].initialized)
- {
- return IX_ETH_DB_PORT_UNINITIALIZED;
- }
-
- if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
- {
- if ((maximumFrameSize < IX_ETHDB_MIN_NPE_FRAME_SIZE) ||
- (maximumFrameSize > IX_ETHDB_MAX_NPE_FRAME_SIZE))
- {
- return IX_ETH_DB_INVALID_ARG;
- }
- }
- else
- {
- return IX_ETH_DB_NO_PERMISSION;
- }
-
- /* update internal structure */
- ixEthDBPortInfo[portID].maxRxFrameSize = maximumFrameSize;
- ixEthDBPortInfo[portID].maxTxFrameSize = maximumFrameSize;
-
- /* update the maximum frame size in the NPE */
- return ixEthDBPortFrameLengthsUpdate(portID);
-}
-
-/**
- * @brief sets the MAC address of an NPE port
- *
- * @param portID port ID to set the MAC address on
- * @param macAddr pointer to the 6-byte MAC address
- *
- * This function is called by the EthAcc
- * ixEthAccUnicastMacAddressSet() and should not be
- * manually invoked unless required by special circumstances.
- *
- * @return IX_ETH_DB_SUCCESS if the operation succeeded
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortAddressSet(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
-{
- IxNpeMhMessage message;
- IX_STATUS result;
-
- /* use this macro instead CHECK_PORT
- as the port doesn't need to be enabled */
- IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
- if (!ixEthDBPortInfo[portID].initialized)
- {
- return IX_ETH_DB_PORT_UNINITIALIZED;
- }
-
- /* Operation stops here when Ethernet Learning is not enabled */
- if(IX_FEATURE_CTRL_SWCONFIG_DISABLED ==
- ixFeatureCtrlSwConfigurationCheck(IX_FEATURECTRL_ETH_LEARNING))
- {
- return IX_ETH_DB_SUCCESS;
- }
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- /* exit if the port is not an Ethernet NPE */
- if (ixEthDBPortDefinitions[portID].type != IX_ETH_NPE)
- {
- return IX_ETH_DB_INVALID_PORT;
- }
-
- /* populate message */
- FILL_SETPORTADDRESS_MSG(message, portID, macAddr->macAddress);
-
- IX_ETH_DB_SUPPORT_TRACE("DB: (Support) Sending SetPortAddress on port %d...\n", portID);
-
- /* send a SetPortAddress message */
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- if (result == IX_SUCCESS)
- {
- ixEthDBPortInfo[portID].macAddressUploaded = true;
- }
-
- return result;
-}
+++ /dev/null
-/**
- * @file IxEthDBDBCore.c
- *
- * @brief Database support functions
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB_p.h"
-
-/* list of database hashtables */
-IX_ETH_DB_PUBLIC HashTable dbHashtable;
-IX_ETH_DB_PUBLIC MatchFunction matchFunctions[IX_ETH_DB_MAX_KEY_INDEX + 1];
-IX_ETH_DB_PUBLIC BOOL ixEthDBPortUpdateRequired[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1];
-IX_ETH_DB_PUBLIC UINT32 ixEthDBKeyType[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1];
-
-/* private initialization flag */
-IX_ETH_DB_PRIVATE BOOL ethDBInitializationComplete = false;
-
-/**
- * @brief initializes EthDB
- *
- * This function must be called to initialize the component.
- *
- * It does the following things:
- * - checks the port definition structure
- * - scans the capabilities of the NPE images and sets the
- * capabilities of the ports accordingly
- * - initializes the memory pools internally used in EthDB
- * for storing database records and handling data
- * - registers automatic update handlers for add and remove
- * operations
- * - registers hashing match functions, depending on key sets
- * - initializes the main database hashtable
- * - allocates contiguous memory zones to be used for NPE
- * updates
- * - registers the serialize methods used to convert data
- * into NPE-readable format
- * - starts the event processor
- *
- * Note that this function is documented in the public
- * component header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS or an appropriate error if the
- * component failed to initialize correctly
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBInit(void)
-{
- IxEthDBStatus result;
-
- if (ethDBInitializationComplete)
- {
- /* redundant */
- return IX_ETH_DB_SUCCESS;
- }
-
- /* trap an invalid port definition structure */
- IX_ETH_DB_PORTS_ASSERTION;
-
- /* memory management */
- ixEthDBInitMemoryPools();
-
- /* register hashing search methods */
- ixEthDBMatchMethodsRegister(matchFunctions);
-
- /* register type-based automatic port updates */
- ixEthDBUpdateTypeRegister(ixEthDBPortUpdateRequired);
-
- /* register record to key type mappings */
- ixEthDBKeyTypeRegister(ixEthDBKeyType);
-
- /* hash table */
- ixEthDBInitHash(&dbHashtable, NUM_BUCKETS, ixEthDBEntryXORHash, matchFunctions, (FreeFunction) ixEthDBFreeMacDescriptor);
-
- /* NPE update zones */
- ixEthDBNPEUpdateAreasInit();
-
- /* register record serialization methods */
- ixEthDBRecordSerializeMethodsRegister();
-
- /* start the event processor */
- result = ixEthDBEventProcessorInit();
-
- /* scan NPE features */
- if (result == IX_ETH_DB_SUCCESS)
- {
- ixEthDBFeatureCapabilityScan();
- }
-
- ethDBInitializationComplete = true;
-
- return result;
-}
-
-/**
- * @brief prepares EthDB for unloading
- *
- * This function must be called before removing the
- * EthDB component from memory (e.g. doing rmmod in
- * Linux) if the component is to be re-initialized again
- * without rebooting the platform.
- *
- * All the EthDB ports must be disabled before this
- * function is to be called. Failure to disable all
- * the ports will return the IX_ETH_DB_BUSY error.
- *
- * This function will destroy mutexes, deallocate
- * memory and stop the event processor.
- *
- * Note that this function is fully documented in the
- * main component header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if de-initialization
- * completed successfully or an appropriate error
- * message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBUnload(void)
-{
- IxEthDBPortId portIndex;
-
- if (!ethDBInitializationComplete)
- {
- /* redundant */
- return IX_ETH_DB_SUCCESS;
- }
-
- /* check if any ports are enabled */
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- if (ixEthDBPortInfo[portIndex].enabled)
- {
- return IX_ETH_DB_BUSY;
- }
- }
-
- /* free port resources */
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE)
- {
- ixOsalMutexDestroy(&ixEthDBPortInfo[portIndex].npeAckLock);
- }
-
- ixEthDBPortInfo[portIndex].initialized = false;
- }
-
- /* shutdown event processor */
- ixEthDBStopLearningFunction();
-
- /* deallocate NPE update zones */
- ixEthDBNPEUpdateAreasUnload();
-
- ethDBInitializationComplete = false;
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief adds a new entry to the Ethernet database
- *
- * @param newRecordTemplate address of the record template to use
- * @param updateTrigger port map containing the update triggers
- * resulting from this update operation
- *
- * Creates a new database entry, populates it with the data
- * copied from the given template and adds the record to the
- * database hash table.
- * It also checks whether the new record type is registered to trigger
- * automatic updates; if it is, the update trigger will contain the
- * port on which the record insertion was performed, as well as the
- * old port in case the addition was a record migration (from one port
- * to the other). The caller can use the updateTrigger to trigger
- * automatic updates on the ports changed as a result of this addition.
- *
- * @retval IX_ETH_DB_SUCCESS addition successful
- * @retval IX_ETH_DB_NOMEM insertion failed, no memory left in the mac descriptor memory pool
- * @retval IX_ETH_DB_BUSY database busy, cannot insert due to locking
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBAdd(MacDescriptor *newRecordTemplate, IxEthDBPortMap updateTrigger)
-{
- IxEthDBStatus result;
- MacDescriptor *newDescriptor;
- IxEthDBPortId originalPortID;
- HashNode *node = NULL;
-
- BUSY_RETRY(ixEthDBSearchHashEntry(&dbHashtable, ixEthDBKeyType[newRecordTemplate->type], newRecordTemplate, &node));
-
- TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER;
-
- if (node == NULL)
- {
- /* not found, create a new one */
- newDescriptor = ixEthDBAllocMacDescriptor();
-
- if (newDescriptor == NULL)
- {
- return IX_ETH_DB_NOMEM; /* no memory */
- }
-
- /* old port does not exist, avoid unnecessary updates */
- originalPortID = newRecordTemplate->portID;
- }
- else
- {
- /* a node with the same key exists, will update node */
- newDescriptor = (MacDescriptor *) node->data;
-
- /* save original port id */
- originalPortID = newDescriptor->portID;
- }
-
- /* copy/update fields into new record */
- memcpy(newDescriptor->macAddress, newRecordTemplate->macAddress, sizeof (IxEthDBMacAddr));
- memcpy(&newDescriptor->recordData, &newRecordTemplate->recordData, sizeof (IxEthDBRecordData));
-
- newDescriptor->type = newRecordTemplate->type;
- newDescriptor->portID = newRecordTemplate->portID;
- newDescriptor->user = newRecordTemplate->user;
-
- if (node == NULL)
- {
- /* new record, insert into hashtable */
- BUSY_RETRY_WITH_RESULT(ixEthDBAddHashEntry(&dbHashtable, newDescriptor), result);
-
- if (result != IX_ETH_DB_SUCCESS)
- {
- ixEthDBFreeMacDescriptor(newDescriptor);
-
- return result; /* insertion failed */
- }
- }
-
- if (node != NULL)
- {
- /* release access */
- ixEthDBReleaseHashNode(node);
- }
-
- /* trigger add/remove update if required by type */
- if (updateTrigger != NULL &&
- ixEthDBPortUpdateRequired[newRecordTemplate->type])
- {
- /* add new port to update list */
- JOIN_PORT_TO_MAP(updateTrigger, newRecordTemplate->portID);
-
- /* check if record has moved, we'll need to update the old port as well */
- if (originalPortID != newDescriptor->portID)
- {
- JOIN_PORT_TO_MAP(updateTrigger, originalPortID);
- }
- }
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief remove a record from the Ethernet database
- *
- * @param templateRecord template record used to determine
- * what record is to be removed
- * @param updateTrigger port map containing the update triggers
- * resulting from this update operation
- *
- * This function will examine the template record it receives
- * and attempts to delete a record of the same type and containing
- * the same keys as the template record. If deletion is successful
- * and the record type is registered for automatic port updates the
- * port will also be set in the updateTrigger port map, so that the
- * client can perform an update of the port.
- *
- * @retval IX_ETH_DB_SUCCESS removal was successful
- * @retval IX_ETH_DB_NO_SUCH_ADDR the record with the given MAC address was not found
- * @retval IX_ETH_DB_BUSY database busy, cannot remove due to locking
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBRemove(MacDescriptor *templateRecord, IxEthDBPortMap updateTrigger)
-{
- IxEthDBStatus result;
-
- TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER;
-
- BUSY_RETRY_WITH_RESULT(ixEthDBRemoveHashEntry(&dbHashtable, ixEthDBKeyType[templateRecord->type], templateRecord), result);
-
- if (result != IX_ETH_DB_SUCCESS)
- {
- return IX_ETH_DB_NO_SUCH_ADDR; /* not found */
- }
-
- /* trigger add/remove update if required by type */
- if (updateTrigger != NULL
- &&ixEthDBPortUpdateRequired[templateRecord->type])
- {
- /* add new port to update list */
- JOIN_PORT_TO_MAP(updateTrigger, templateRecord->portID);
- }
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief register record key types
- *
- * This function registers the appropriate key types,
- * depending on record types.
- *
- * All filtering records use the MAC address as the key.
- * WiFi and Firewall records use a compound key consisting
- * in both the MAC address and the port ID.
- *
- * @return the number of registered record types
- */
-IX_ETH_DB_PUBLIC
-UINT32 ixEthDBKeyTypeRegister(UINT32 *keyType)
-{
- /* safety */
- memset(keyType, 0, sizeof (keyType));
-
- /* register all known record types */
- keyType[IX_ETH_DB_FILTERING_RECORD] = IX_ETH_DB_MAC_KEY;
- keyType[IX_ETH_DB_FILTERING_VLAN_RECORD] = IX_ETH_DB_MAC_KEY;
- keyType[IX_ETH_DB_ALL_FILTERING_RECORDS] = IX_ETH_DB_MAC_KEY;
- keyType[IX_ETH_DB_WIFI_RECORD] = IX_ETH_DB_MAC_PORT_KEY;
- keyType[IX_ETH_DB_FIREWALL_RECORD] = IX_ETH_DB_MAC_PORT_KEY;
-
- return 5;
-}
-
-/**
- * @brief Sets a user-defined field into a database record
- *
- * Note that this function is fully documented in the main component
- * header file.
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBUserFieldSet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, IxEthDBVlanId vlanID, void *field)
-{
- HashNode *result = NULL;
-
- if (macAddr == NULL)
- {
- return IX_ETH_DB_INVALID_ARG;
- }
-
- if (recordType == IX_ETH_DB_FILTERING_RECORD)
- {
- result = ixEthDBSearch(macAddr, recordType);
- }
- else if (recordType == IX_ETH_DB_FILTERING_VLAN_RECORD)
- {
- result = ixEthDBVlanSearch(macAddr, vlanID, recordType);
- }
- else if (recordType == IX_ETH_DB_WIFI_RECORD || recordType == IX_ETH_DB_FIREWALL_RECORD)
- {
- IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
- result = ixEthDBPortSearch(macAddr, portID, recordType);
- }
- else
- {
- return IX_ETH_DB_INVALID_ARG;
- }
-
- if (result == NULL)
- {
- return IX_ETH_DB_NO_SUCH_ADDR;
- }
-
- ((MacDescriptor *) result->data)->user = field;
-
- ixEthDBReleaseHashNode(result);
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief Retrieves a user-defined field from a database record
- *
- * Note that this function is fully documented in the main component
- * header file.
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBUserFieldGet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, IxEthDBVlanId vlanID, void **field)
-{
- HashNode *result = NULL;
-
- if (macAddr == NULL || field == NULL)
- {
- return IX_ETH_DB_INVALID_ARG;
- }
-
- if (recordType == IX_ETH_DB_FILTERING_RECORD)
- {
- result = ixEthDBSearch(macAddr, recordType);
- }
- else if (recordType == IX_ETH_DB_FILTERING_VLAN_RECORD)
- {
- result = ixEthDBVlanSearch(macAddr, vlanID, recordType);
- }
- else if (recordType == IX_ETH_DB_WIFI_RECORD || recordType == IX_ETH_DB_FIREWALL_RECORD)
- {
- IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
- result = ixEthDBPortSearch(macAddr, portID, recordType);
- }
- else
- {
- return IX_ETH_DB_INVALID_ARG;
- }
-
- if (result == NULL)
- {
- return IX_ETH_DB_NO_SUCH_ADDR;
- }
-
- *field = ((MacDescriptor *) result->data)->user;
-
- ixEthDBReleaseHashNode(result);
-
- return IX_ETH_DB_SUCCESS;
-}
+++ /dev/null
-/**
- * @file IxEthDBEvents.c
- *
- * @brief Implementation of the event processor component
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include <IxNpeMh.h>
-#include <IxFeatureCtrl.h>
-
-#include "IxEthDB_p.h"
-
-/* forward prototype declarations */
-IX_ETH_DB_PUBLIC void ixEthDBEventProcessorLoop(void *);
-IX_ETH_DB_PUBLIC void ixEthDBNPEEventCallback(IxNpeMhNpeId npeID, IxNpeMhMessage msg);
-IX_ETH_DB_PRIVATE void ixEthDBProcessEvent(PortEvent *local_event, IxEthDBPortMap triggerPorts);
-IX_ETH_DB_PRIVATE IxEthDBStatus ixEthDBTriggerPortUpdate(UINT32 eventType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, BOOL staticEntry);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBStartLearningFunction(void);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBStopLearningFunction(void);
-
-/* data */
-IX_ETH_DB_PRIVATE IxOsalSemaphore eventQueueSemaphore;
-IX_ETH_DB_PRIVATE PortEventQueue eventQueue;
-IX_ETH_DB_PRIVATE IxOsalMutex eventQueueLock;
-IX_ETH_DB_PRIVATE IxOsalMutex portUpdateLock;
-
-IX_ETH_DB_PRIVATE BOOL ixEthDBLearningShutdown = false;
-IX_ETH_DB_PRIVATE BOOL ixEthDBEventProcessorRunning = false;
-
-/* imported data */
-extern HashTable dbHashtable;
-
-/**
- * @brief initializes the event processor
- *
- * Initializes the event processor queue and processing thread.
- * Called from ixEthDBInit() DB-subcomponent master init function.
- *
- * @warning do not call directly
- *
- * @retval IX_ETH_DB_SUCCESS initialization was successful
- * @retval IX_ETH_DB_FAIL initialization failed (OSAL or mutex init failure)
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBEventProcessorInit(void)
-{
- if (ixOsalMutexInit(&portUpdateLock) != IX_SUCCESS)
- {
- return IX_ETH_DB_FAIL;
- }
-
- if (ixOsalMutexInit(&eventQueueLock) != IX_SUCCESS)
- {
- return IX_ETH_DB_FAIL;
- }
-
- if (IX_FEATURE_CTRL_SWCONFIG_ENABLED ==
- ixFeatureCtrlSwConfigurationCheck (IX_FEATURECTRL_ETH_LEARNING))
- {
-
- /* start processor loop thread */
- if (ixEthDBStartLearningFunction() != IX_ETH_DB_SUCCESS)
- {
- return IX_ETH_DB_FAIL;
- }
- }
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief initializes the event queue and the event processor
- *
- * This function is called by the component initialization
- * function, ixEthDBInit().
- *
- * @warning do not call directly
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or IX_ETH_DB_FAIL otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBStartLearningFunction(void)
-{
- IxOsalThread eventProcessorThread;
- IxOsalThreadAttr threadAttr;
-
- threadAttr.name = "EthDB event thread";
- threadAttr.stackSize = 32 * 1024; /* 32kbytes */
- threadAttr.priority = 128;
-
- /* reset event queue */
- ixOsalMutexLock(&eventQueueLock, IX_OSAL_WAIT_FOREVER);
-
- RESET_QUEUE(&eventQueue);
-
- ixOsalMutexUnlock(&eventQueueLock);
-
- /* init event queue semaphore */
- if (ixOsalSemaphoreInit(&eventQueueSemaphore, 0) != IX_SUCCESS)
- {
- return IX_ETH_DB_FAIL;
- }
-
- ixEthDBLearningShutdown = false;
-
- /* create processor loop thread */
- if (ixOsalThreadCreate(&eventProcessorThread, &threadAttr, ixEthDBEventProcessorLoop, NULL) != IX_SUCCESS)
- {
- return IX_ETH_DB_FAIL;
- }
-
- /* start event processor */
- ixOsalThreadStart(&eventProcessorThread);
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief stops the event processor
- *
- * Stops the event processor and frees the event queue semaphore
- * Called by the component de-initialization function, ixEthDBUnload()
- *
- * @warning do not call directly
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or IX_ETH_DB_FAIL otherwise;
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBStopLearningFunction(void)
-{
- ixEthDBLearningShutdown = true;
-
- /* wake up event processing loop to actually process the shutdown event */
- ixOsalSemaphorePost(&eventQueueSemaphore);
-
- if (ixOsalSemaphoreDestroy(&eventQueueSemaphore) != IX_SUCCESS)
- {
- return IX_ETH_DB_FAIL;
- }
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief default NPE event processing callback
- *
- * @param npeID ID of the NPE that generated the event
- * @param msg NPE message (encapsulated event)
- *
- * Creates an event object on the Ethernet event processor queue
- * and signals the new event by incrementing the event queue semaphore.
- * Events are processed by @ref ixEthDBEventProcessorLoop() which runs
- * at user level.
- *
- * @see ixEthDBEventProcessorLoop()
- *
- * @warning do not call directly
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBNPEEventCallback(IxNpeMhNpeId npeID, IxNpeMhMessage msg)
-{
- PortEvent *local_event;
-
- IX_ETH_DB_IRQ_EVENTS_TRACE("DB: (Events) new event received by processor callback from port %d, id 0x%X\n", IX_ETH_DB_NPE_TO_PORT_ID(npeID), NPE_MSG_ID(msg), 0, 0, 0, 0);
-
- if (CAN_ENQUEUE(&eventQueue))
- {
- TEST_FIXTURE_LOCK_EVENT_QUEUE;
-
- local_event = QUEUE_HEAD(&eventQueue);
-
- /* create event structure on queue */
- local_event->eventType = NPE_MSG_ID(msg);
- local_event->portID = IX_ETH_DB_NPE_TO_PORT_ID(npeID);
-
- /* update queue */
- PUSH_UPDATE_QUEUE(&eventQueue);
-
- TEST_FIXTURE_UNLOCK_EVENT_QUEUE;
-
- IX_ETH_DB_IRQ_EVENTS_TRACE("DB: (Events) Waking up main processor loop...\n", 0, 0, 0, 0, 0, 0);
-
- /* increment event queue semaphore */
- ixOsalSemaphorePost(&eventQueueSemaphore);
- }
- else
- {
- IX_ETH_DB_IRQ_EVENTS_TRACE("DB: (Events) Warning: could not enqueue event (overflow)\n", 0, 0, 0, 0, 0, 0);
- }
-}
-
-/**
- * @brief Ethernet event processor loop
- *
- * Extracts at most EVENT_PROCESSING_LIMIT batches of events and
- * sends them for processing to @ref ixEthDBProcessEvent().
- * Triggers port updates which normally follow learning events.
- *
- * @warning do not call directly, executes in separate thread
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBEventProcessorLoop(void *unused1)
-{
- IxEthDBPortMap triggerPorts;
- IxEthDBPortId portIndex;
-
- ixEthDBEventProcessorRunning = true;
-
- IX_ETH_DB_EVENTS_TRACE("DB: (Events) Event processor loop was started\n");
-
- while (!ixEthDBLearningShutdown)
- {
- BOOL keepProcessing = true;
- UINT32 processedEvents = 0;
-
- IX_ETH_DB_EVENTS_VERBOSE_TRACE("DB: (Events) Waiting for new learning event...\n");
-
- ixOsalSemaphoreWait(&eventQueueSemaphore, IX_OSAL_WAIT_FOREVER);
-
- IX_ETH_DB_EVENTS_VERBOSE_TRACE("DB: (Events) Received new event\n");
-
- if (!ixEthDBLearningShutdown)
- {
- /* port update handling */
- SET_EMPTY_DEPENDENCY_MAP(triggerPorts);
-
- while (keepProcessing)
- {
- PortEvent local_event;
- UINT32 intLockKey;
-
- /* lock queue */
- ixOsalMutexLock(&eventQueueLock, IX_OSAL_WAIT_FOREVER);
-
- /* lock NPE interrupts */
- intLockKey = ixOsalIrqLock();
-
- /* extract event */
- local_event = *(QUEUE_TAIL(&eventQueue));
-
- SHIFT_UPDATE_QUEUE(&eventQueue);
-
- ixOsalIrqUnlock(intLockKey);
-
- ixOsalMutexUnlock(&eventQueueLock);
-
- IX_ETH_DB_EVENTS_TRACE("DB: (Events) Processing event with ID 0x%X\n", local_event.eventType);
-
- ixEthDBProcessEvent(&local_event, triggerPorts);
-
- processedEvents++;
-
- if (processedEvents > EVENT_PROCESSING_LIMIT /* maximum burst reached? */
- || ixOsalSemaphoreTryWait(&eventQueueSemaphore) != IX_SUCCESS) /* or empty queue? */
- {
- keepProcessing = false;
- }
- }
-
- ixEthDBUpdatePortLearningTrees(triggerPorts);
- }
- }
-
- /* turn off automatic updates */
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- ixEthDBPortInfo[portIndex].updateMethod.updateEnabled = false;
- }
-
- ixEthDBEventProcessorRunning = false;
-}
-
-/**
- * @brief event processor routine
- *
- * @param event event to be processed
- * @param triggerPorts port map accumulating ports to be updated
- *
- * Processes learning events by synchronizing the database with
- * newly learnt data. Called only by @ref ixEthDBEventProcessorLoop().
- *
- * @warning do not call directly
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBProcessEvent(PortEvent *local_event, IxEthDBPortMap triggerPorts)
-{
- MacDescriptor recordTemplate;
-
- switch (local_event->eventType)
- {
- case IX_ETH_DB_ADD_FILTERING_RECORD:
- /* add record */
- memset(&recordTemplate, 0, sizeof (recordTemplate));
- memcpy(recordTemplate.macAddress, local_event->macAddr.macAddress, sizeof (IxEthDBMacAddr));
-
- recordTemplate.type = IX_ETH_DB_FILTERING_RECORD;
- recordTemplate.portID = local_event->portID;
- recordTemplate.recordData.filteringData.staticEntry = local_event->staticEntry;
-
- ixEthDBAdd(&recordTemplate, triggerPorts);
-
- IX_ETH_DB_EVENTS_TRACE("DB: (Events) Added record on port %d\n", local_event->portID);
-
- break;
-
- case IX_ETH_DB_REMOVE_FILTERING_RECORD:
- /* remove record */
- memset(&recordTemplate, 0, sizeof (recordTemplate));
- memcpy(recordTemplate.macAddress, local_event->macAddr.macAddress, sizeof (IxEthDBMacAddr));
-
- recordTemplate.type = IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD;
-
- ixEthDBRemove(&recordTemplate, triggerPorts);
-
- IX_ETH_DB_EVENTS_TRACE("DB: (Events) Removed record on port %d\n", local_event->portID);
-
- break;
-
- default:
- /* can't handle/not interested in this event type */
- ERROR_LOG("DB: (Events) Event processor received an unknown event type (0x%X)\n", local_event->eventType);
-
- return;
- }
-}
-
-/**
- * @brief asynchronously adds a filtering record
- * by posting an ADD_FILTERING_RECORD event to the event queue
- *
- * @param macAddr MAC address of the new record
- * @param portID port ID of the new record
- * @param staticEntry true if record is static, false if dynamic
- *
- * @return IX_ETH_DB_SUCCESS if the event creation was
- * successfull or IX_ETH_DB_BUSY if the event queue is full
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBTriggerAddPortUpdate(IxEthDBMacAddr *macAddr, IxEthDBPortId portID, BOOL staticEntry)
-{
- MacDescriptor reference;
-
- TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER;
-
- /* fill search fields */
- memcpy(reference.macAddress, macAddr, sizeof (IxEthDBMacAddr));
- reference.portID = portID;
-
- /* set acceptable record types */
- reference.type = IX_ETH_DB_ALL_FILTERING_RECORDS;
-
- if (ixEthDBPeekHashEntry(&dbHashtable, IX_ETH_DB_MAC_PORT_KEY, &reference) == IX_ETH_DB_SUCCESS)
- {
- /* already have an identical record */
- return IX_ETH_DB_SUCCESS;
- }
- else
- {
- return ixEthDBTriggerPortUpdate(IX_ETH_DB_ADD_FILTERING_RECORD, macAddr, portID, staticEntry);
- }
-}
-
-/**
- * @brief asynchronously removes a filtering record
- * by posting a REMOVE_FILTERING_RECORD event to the event queue
- *
- * @param macAddr MAC address of the record to remove
- * @param portID port ID of the record to remove
- *
- * @return IX_ETH_DB_SUCCESS if the event creation was
- * successfull or IX_ETH_DB_BUSY if the event queue is full
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBTriggerRemovePortUpdate(IxEthDBMacAddr *macAddr, IxEthDBPortId portID)
-{
- if (ixEthDBPeek(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS) != IX_ETH_DB_NO_SUCH_ADDR)
- {
- return ixEthDBTriggerPortUpdate(IX_ETH_DB_REMOVE_FILTERING_RECORD, macAddr, portID, false);
- }
- else
- {
- return IX_ETH_DB_NO_SUCH_ADDR;
- }
-}
-
-/**
- * @brief adds an ADD or REMOVE event to the main event queue
- *
- * @param eventType event type - IX_ETH_DB_ADD_FILTERING_RECORD
- * to add and IX_ETH_DB_REMOVE_FILTERING_RECORD to remove a
- * record.
- *
- * @return IX_ETH_DB_SUCCESS if the event was successfully
- * sent or IX_ETH_DB_BUSY if the event queue is full
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBTriggerPortUpdate(UINT32 eventType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, BOOL staticEntry)
-{
- UINT32 intLockKey;
-
- /* lock interrupts to protect queue */
- intLockKey = ixOsalIrqLock();
-
- if (CAN_ENQUEUE(&eventQueue))
- {
- PortEvent *queueEvent = QUEUE_HEAD(&eventQueue);
-
- /* update fields on the queue */
- memcpy(queueEvent->macAddr.macAddress, macAddr->macAddress, sizeof (IxEthDBMacAddr));
-
- queueEvent->eventType = eventType;
- queueEvent->portID = portID;
- queueEvent->staticEntry = staticEntry;
-
- PUSH_UPDATE_QUEUE(&eventQueue);
-
- /* imcrement event queue semaphore */
- ixOsalSemaphorePost(&eventQueueSemaphore);
-
- /* unlock interrupts */
- ixOsalIrqUnlock(intLockKey);
-
- return IX_ETH_DB_SUCCESS;
- }
- else /* event queue full */
- {
- /* unlock interrupts */
- ixOsalIrqUnlock(intLockKey);
-
- return IX_ETH_DB_BUSY;
- }
-}
-
-/**
- * @brief Locks learning tree updates and port disable
- *
- *
- * This function locks portUpdateLock single mutex. It is primarily used
- * to avoid executing 'port disable' during ELT maintenance.
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBUpdateLock(void)
-{
- ixOsalMutexLock(&portUpdateLock, IX_OSAL_WAIT_FOREVER);
-}
-
-/**
- * @brief Unlocks learning tree updates and port disable
- *
- *
- * This function unlocks a portUpdateLock mutex. It is primarily used
- * to avoid executing 'port disable' during ELT maintenance.
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBUpdateUnlock(void)
-{
- ixOsalMutexUnlock(&portUpdateLock);
-}
-
+++ /dev/null
-/**
- * @file IxEthDBFeatures.c
- *
- * @brief Implementation of the EthDB feature control API
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxNpeDl.h"
-#include "IxEthDBQoS.h"
-#include "IxEthDB_p.h"
-
-/**
- * @brief scans the capabilities of the loaded NPE images
- *
- * This function MUST be called by the ixEthDBInit() function.
- * No EthDB features (including learning and filtering) are enabled
- * before this function is called.
- *
- * @return none
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBFeatureCapabilityScan(void)
-{
- IxNpeDlImageId imageId, npeAImageId;
- IxEthDBPortId portIndex;
- PortInfo *portInfo;
- IxEthDBPriorityTable defaultPriorityTable;
- IX_STATUS result;
- UINT32 queueIndex;
- UINT32 queueStructureIndex;
- UINT32 trafficClassDefinitionIndex;
-
- /* read version of NPE A - required to set the AQM queues for B and C */
- npeAImageId.functionalityId = 0;
- ixNpeDlLoadedImageGet(IX_NPEDL_NPEID_NPEA, &npeAImageId);
-
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- IxNpeMhMessage msg;
-
- portInfo = &ixEthDBPortInfo[portIndex];
-
- /* check and bypass if NPE B or C is fused out */
- if (ixEthDBSingleEthNpeCheck(portIndex) != IX_ETH_DB_SUCCESS) continue;
-
- /* all ports are capable of LEARNING by default */
- portInfo->featureCapability |= IX_ETH_DB_LEARNING;
- portInfo->featureStatus |= IX_ETH_DB_LEARNING;
-
- if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE)
- {
-
- if (ixNpeDlLoadedImageGet(IX_ETH_DB_PORT_ID_TO_NPE(portIndex), &imageId) != IX_SUCCESS)
- {
- WARNING_LOG("DB: (FeatureScan) NpeDl did not provide the image ID for NPE port %d\n", portIndex);
- }
- else
- {
- /* initialize and empty NPE response mutex */
- ixOsalMutexInit(&portInfo->npeAckLock);
- ixOsalMutexLock(&portInfo->npeAckLock, IX_OSAL_WAIT_FOREVER);
-
- /* check NPE response to GetStatus */
- msg.data[0] = IX_ETHNPE_NPE_GETSTATUS << 24;
- msg.data[1] = 0;
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portIndex), msg, result);
- if (result != IX_SUCCESS)
- {
- WARNING_LOG("DB: (FeatureScan) warning, could not send message to the NPE\n");
- continue;
- }
-
-
- if (imageId.functionalityId == 0x00
- || imageId.functionalityId == 0x03
- || imageId.functionalityId == 0x04
- || imageId.functionalityId == 0x80)
- {
- portInfo->featureCapability |= IX_ETH_DB_FILTERING;
- portInfo->featureCapability |= IX_ETH_DB_FIREWALL;
- portInfo->featureCapability |= IX_ETH_DB_SPANNING_TREE_PROTOCOL;
- }
- else if (imageId.functionalityId == 0x01
- || imageId.functionalityId == 0x81)
- {
- portInfo->featureCapability |= IX_ETH_DB_FILTERING;
- portInfo->featureCapability |= IX_ETH_DB_FIREWALL;
- portInfo->featureCapability |= IX_ETH_DB_SPANNING_TREE_PROTOCOL;
- portInfo->featureCapability |= IX_ETH_DB_VLAN_QOS;
- }
- else if (imageId.functionalityId == 0x02
- || imageId.functionalityId == 0x82)
- {
- portInfo->featureCapability |= IX_ETH_DB_WIFI_HEADER_CONVERSION;
- portInfo->featureCapability |= IX_ETH_DB_FIREWALL;
- portInfo->featureCapability |= IX_ETH_DB_SPANNING_TREE_PROTOCOL;
- portInfo->featureCapability |= IX_ETH_DB_VLAN_QOS;
- }
-
- /* reset AQM queues */
- memset(portInfo->ixEthDBTrafficClassAQMAssignments, 0, sizeof (portInfo->ixEthDBTrafficClassAQMAssignments));
-
- /* ensure there's at least one traffic class record in the definition table, otherwise we have no default case, hence no queues */
- IX_ENSURE(sizeof (ixEthDBTrafficClassDefinitions) != 0, "DB: no traffic class definitions found, check IxEthDBQoS.h");
-
- /* find the traffic class definition index compatible with the current NPE A functionality ID */
- for (trafficClassDefinitionIndex = 0 ;
- trafficClassDefinitionIndex < ARRAY_SIZE(ixEthDBTrafficClassDefinitions);
- trafficClassDefinitionIndex++)
- {
- if (ixEthDBTrafficClassDefinitions[trafficClassDefinitionIndex][IX_ETH_DB_NPE_A_FUNCTIONALITY_ID_INDEX] == npeAImageId.functionalityId)
- {
- /* found it */
- break;
- }
- }
-
- /* select the default case if we went over the array boundary */
- if (trafficClassDefinitionIndex == ARRAY_SIZE(ixEthDBTrafficClassDefinitions))
- {
- trafficClassDefinitionIndex = 0; /* the first record is the default case */
- }
-
- /* select queue assignment structure based on the traffic class configuration index */
- queueStructureIndex = ixEthDBTrafficClassDefinitions[trafficClassDefinitionIndex][IX_ETH_DB_QUEUE_ASSIGNMENT_INDEX];
-
- /* only traffic class 0 is active at initialization time */
- portInfo->ixEthDBTrafficClassCount = 1;
-
- /* enable port, VLAN and Firewall feature bits to initialize QoS/VLAN/Firewall configuration */
- portInfo->featureStatus |= IX_ETH_DB_VLAN_QOS;
- portInfo->featureStatus |= IX_ETH_DB_FIREWALL;
- portInfo->enabled = true;
-
-#define CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */
-#ifdef CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */
- /* set VLAN initial configuration (permissive) */
- if ((portInfo->featureCapability & IX_ETH_DB_VLAN_QOS) != 0) /* QoS-enabled image */
- {
- /* QoS capable */
- portInfo->ixEthDBTrafficClassAvailable = ixEthDBTrafficClassDefinitions[trafficClassDefinitionIndex][IX_ETH_DB_TRAFFIC_CLASS_COUNT_INDEX];
-
- /* set AQM queues */
- for (queueIndex = 0 ; queueIndex < IX_IEEE802_1Q_QOS_PRIORITY_COUNT ; queueIndex++)
- {
- portInfo->ixEthDBTrafficClassAQMAssignments[queueIndex] = ixEthDBQueueAssignments[queueStructureIndex][queueIndex];
- }
-
- /* set default PVID (0) and default traffic class 0 */
- ixEthDBPortVlanTagSet(portIndex, 0);
-
- /* enable reception of all frames */
- ixEthDBAcceptableFrameTypeSet(portIndex, IX_ETH_DB_ACCEPT_ALL_FRAMES);
-
- /* clear full VLAN membership */
- ixEthDBPortVlanMembershipRangeRemove(portIndex, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID);
-
- /* clear TTI table - no VLAN tagged frames will be transmitted */
- ixEthDBEgressVlanRangeTaggingEnabledSet(portIndex, 0, 4094, false);
-
- /* set membership on 0, otherwise no Tx or Rx is working */
- ixEthDBPortVlanMembershipAdd(portIndex, 0);
- }
- else /* QoS not available in this image */
-#endif /* test-only */
- {
- /* initialize traffic class availability (only class 0 is available) */
- portInfo->ixEthDBTrafficClassAvailable = 1;
-
- /* point all AQM queues to traffic class 0 */
- for (queueIndex = 0 ; queueIndex < IX_IEEE802_1Q_QOS_PRIORITY_COUNT ; queueIndex++)
- {
- portInfo->ixEthDBTrafficClassAQMAssignments[queueIndex] =
- ixEthDBQueueAssignments[queueStructureIndex][0];
- }
- }
-
-#ifdef CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */
- /* download priority mapping table and Rx queue configuration */
- memset (defaultPriorityTable, 0, sizeof (defaultPriorityTable));
- ixEthDBPriorityMappingTableSet(portIndex, defaultPriorityTable);
-#endif
-
- /* by default we turn off invalid source MAC address filtering */
- ixEthDBFirewallInvalidAddressFilterEnable(portIndex, false);
-
- /* disable port, VLAN, Firewall feature bits */
- portInfo->featureStatus &= ~IX_ETH_DB_VLAN_QOS;
- portInfo->featureStatus &= ~IX_ETH_DB_FIREWALL;
- portInfo->enabled = false;
-
- /* enable filtering by default if present */
- if ((portInfo->featureCapability & IX_ETH_DB_FILTERING) != 0)
- {
- portInfo->featureStatus |= IX_ETH_DB_FILTERING;
- }
- }
- }
- }
-}
-
-/**
- * @brief returns the capability of a port
- *
- * @param portID ID of the port
- * @param featureSet location to store the port capability in
- *
- * This function will save the capability set of the given port
- * into the given location. Capabilities are bit-ORed, each representing
- * a bit of the feature set.
- *
- * Note that this function is documented in the main component
- * public header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or IX_ETH_DB_INVALID_PORT if the given port is invalid
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFeatureCapabilityGet(IxEthDBPortId portID, IxEthDBFeature *featureSet)
-{
- IX_ETH_DB_CHECK_PORT_INITIALIZED(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(featureSet);
-
- *featureSet = ixEthDBPortInfo[portID].featureCapability;
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief enables or disables a port capability
- *
- * @param portID ID of the port
- * @param feature feature to enable or disable
- * @param enabled true to enable the selected feature or false to disable it
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature, BOOL enable)
-{
- PortInfo *portInfo;
- IxEthDBPriorityTable defaultPriorityTable;
- IxEthDBVlanSet vlanSet;
- IxEthDBStatus status = IX_ETH_DB_SUCCESS;
- BOOL portEnabled;
-
- IX_ETH_DB_CHECK_PORT_INITIALIZED(portID);
-
- portInfo = &ixEthDBPortInfo[portID];
- portEnabled = portInfo->enabled;
-
- /* check that only one feature is selected */
- if (!ixEthDBCheckSingleBitValue(feature))
- {
- return IX_ETH_DB_FEATURE_UNAVAILABLE;
- }
-
- /* port capable of this feature? */
- if ((portInfo->featureCapability & feature) == 0)
- {
- return IX_ETH_DB_FEATURE_UNAVAILABLE;
- }
-
- /* mutual exclusion between learning and WiFi header conversion */
- if (enable && ((feature | portInfo->featureStatus) & (IX_ETH_DB_FILTERING | IX_ETH_DB_WIFI_HEADER_CONVERSION))
- == (IX_ETH_DB_FILTERING | IX_ETH_DB_WIFI_HEADER_CONVERSION))
- {
- return IX_ETH_DB_NO_PERMISSION;
- }
-
- /* learning must be enabled before filtering */
- if (enable && (feature == IX_ETH_DB_FILTERING) && ((portInfo->featureStatus & IX_ETH_DB_LEARNING) == 0))
- {
- return IX_ETH_DB_NO_PERMISSION;
- }
-
- /* filtering must be disabled before learning */
- if (!enable && (feature == IX_ETH_DB_LEARNING) && ((portInfo->featureStatus & IX_ETH_DB_FILTERING) != 0))
- {
- return IX_ETH_DB_NO_PERMISSION;
- }
-
- /* redundant enabling or disabling */
- if ((!enable && ((portInfo->featureStatus & feature) == 0))
- || (enable && ((portInfo->featureStatus & feature) != 0)))
- {
- /* do nothing */
- return IX_ETH_DB_SUCCESS;
- }
-
- /* force port enabled */
- portInfo->enabled = true;
-
- if (enable)
- {
- /* turn on enable bit */
- portInfo->featureStatus |= feature;
-
-#ifdef CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */
- /* if this is VLAN/QoS set the default priority table */
- if (feature == IX_ETH_DB_VLAN_QOS)
- {
- /* turn on VLAN/QoS (most permissive mode):
- - set default 802.1Q priority mapping table, in accordance to the
- availability of traffic classes
- - set the acceptable frame filter to accept all
- - set the Ingress tagging mode to pass-through
- - set full VLAN membership list
- - set full TTI table
- - set the default 802.1Q tag to 0 (VLAN ID 0, Pri 0, CFI 0)
- - enable TPID port extraction
- */
-
- portInfo->ixEthDBTrafficClassCount = portInfo->ixEthDBTrafficClassAvailable;
-
- /* set default 802.1Q priority mapping table - note that C indexing starts from 0, so we substract 1 here */
- memcpy (defaultPriorityTable,
- (const void *) ixEthIEEE802_1QUserPriorityToTrafficClassMapping[portInfo->ixEthDBTrafficClassCount - 1],
- sizeof (defaultPriorityTable));
-
- /* update priority mapping and AQM queue assignments */
- status = ixEthDBPriorityMappingTableSet(portID, defaultPriorityTable);
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- status = ixEthDBAcceptableFrameTypeSet(portID, IX_ETH_DB_ACCEPT_ALL_FRAMES);
- }
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- status = ixEthDBIngressVlanTaggingEnabledSet(portID, IX_ETH_DB_PASS_THROUGH);
- }
-
- /* set membership and TTI tables */
- memset (vlanSet, 0xFF, sizeof (vlanSet));
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- /* use the internal function to bypass PVID check */
- status = ixEthDBPortVlanTableSet(portID, portInfo->vlanMembership, vlanSet);
- }
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- /* use the internal function to bypass PVID check */
- status = ixEthDBPortVlanTableSet(portID, portInfo->transmitTaggingInfo, vlanSet);
- }
-
- /* reset the PVID */
- if (status == IX_ETH_DB_SUCCESS)
- {
- status = ixEthDBPortVlanTagSet(portID, 0);
- }
-
- /* enable TPID port extraction */
- if (status == IX_ETH_DB_SUCCESS)
- {
- status = ixEthDBVlanPortExtractionEnable(portID, true);
- }
- }
- else if (feature == IX_ETH_DB_FIREWALL)
-#endif
- {
- /* firewall starts in black-list mode unless otherwise configured before *
- * note that invalid source MAC address filtering is disabled by default */
- if (portInfo->firewallMode != IX_ETH_DB_FIREWALL_BLACK_LIST
- && portInfo->firewallMode != IX_ETH_DB_FIREWALL_WHITE_LIST)
- {
- status = ixEthDBFirewallModeSet(portID, IX_ETH_DB_FIREWALL_BLACK_LIST);
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- status = ixEthDBFirewallInvalidAddressFilterEnable(portID, false);
- }
- }
- }
-
- if (status != IX_ETH_DB_SUCCESS)
- {
- /* checks failed, disable */
- portInfo->featureStatus &= ~feature;
- }
- }
- else
- {
- /* turn off features */
- if (feature == IX_ETH_DB_FIREWALL)
- {
- /* turning off the firewall is equivalent to:
- - set to black-list mode
- - clear all the entries and download the new table
- - turn off the invalid source address checking
- */
-
- status = ixEthDBDatabaseClear(portID, IX_ETH_DB_FIREWALL_RECORD);
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- status = ixEthDBFirewallModeSet(portID, IX_ETH_DB_FIREWALL_BLACK_LIST);
- }
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- status = ixEthDBFirewallInvalidAddressFilterEnable(portID, false);
- }
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- status = ixEthDBFirewallTableDownload(portID);
- }
- }
- else if (feature == IX_ETH_DB_WIFI_HEADER_CONVERSION)
- {
- /* turn off header conversion */
- status = ixEthDBDatabaseClear(portID, IX_ETH_DB_WIFI_RECORD);
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- status = ixEthDBWiFiConversionTableDownload(portID);
- }
- }
-#ifdef CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */
- else if (feature == IX_ETH_DB_VLAN_QOS)
- {
- /* turn off VLAN/QoS:
- - set a priority mapping table with one traffic class
- - set the acceptable frame filter to accept all
- - set the Ingress tagging mode to pass-through
- - clear the VLAN membership list
- - clear the TTI table
- - set the default 802.1Q tag to 0 (VLAN ID 0, Pri 0, CFI 0)
- - disable TPID port extraction
- */
-
- /* initialize all => traffic class 0 priority mapping table */
- memset (defaultPriorityTable, 0, sizeof (defaultPriorityTable));
- portInfo->ixEthDBTrafficClassCount = 1;
- status = ixEthDBPriorityMappingTableSet(portID, defaultPriorityTable);
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- status = ixEthDBAcceptableFrameTypeSet(portID, IX_ETH_DB_ACCEPT_ALL_FRAMES);
- }
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- status = ixEthDBIngressVlanTaggingEnabledSet(portID, IX_ETH_DB_PASS_THROUGH);
- }
-
- /* clear membership and TTI tables */
- memset (vlanSet, 0, sizeof (vlanSet));
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- /* use the internal function to bypass PVID check */
- status = ixEthDBPortVlanTableSet(portID, portInfo->vlanMembership, vlanSet);
- }
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- /* use the internal function to bypass PVID check */
- status = ixEthDBPortVlanTableSet(portID, portInfo->transmitTaggingInfo, vlanSet);
- }
-
- /* reset the PVID */
- if (status == IX_ETH_DB_SUCCESS)
- {
- status = ixEthDBPortVlanTagSet(portID, 0);
- }
-
- /* disable TPID port extraction */
- if (status == IX_ETH_DB_SUCCESS)
- {
- status = ixEthDBVlanPortExtractionEnable(portID, false);
- }
- }
-#endif
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- /* checks passed, disable */
- portInfo->featureStatus &= ~feature;
- }
- }
-
- /* restore port enabled state */
- portInfo->enabled = portEnabled;
-
- return status;
-}
-
-/**
- * @brief returns the status of a feature
- *
- * @param portID port ID
- * @param present location to store a boolean value indicating
- * if the feature is present (true) or not (false)
- * @param enabled location to store a booleam value indicating
- * if the feature is present (true) or not (false)
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFeatureStatusGet(IxEthDBPortId portID, IxEthDBFeature feature, BOOL *present, BOOL *enabled)
-{
- PortInfo *portInfo;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(present);
-
- IX_ETH_DB_CHECK_REFERENCE(enabled);
-
- portInfo = &ixEthDBPortInfo[portID];
-
- *present = (portInfo->featureCapability & feature) != 0;
- *enabled = (portInfo->featureStatus & feature) != 0;
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief returns the value of an EthDB property
- *
- * @param portID ID of the port
- * @param feature feature owning the property
- * @param property ID of the property
- * @param type location to store the property type into
- * @param value location to store the property value into
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFeaturePropertyGet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, IxEthDBPropertyType *type, void *value)
-{
- IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(type);
-
- IX_ETH_DB_CHECK_REFERENCE(value);
-
- if (feature == IX_ETH_DB_VLAN_QOS)
- {
- if (property == IX_ETH_DB_QOS_TRAFFIC_CLASS_COUNT_PROPERTY)
- {
- * (UINT32 *) value = ixEthDBPortInfo[portID].ixEthDBTrafficClassCount;
- *type = IX_ETH_DB_INTEGER_PROPERTY;
-
- return IX_ETH_DB_SUCCESS;
- }
- else if (property >= IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY
- && property <= IX_ETH_DB_QOS_TRAFFIC_CLASS_7_RX_QUEUE_PROPERTY)
- {
- UINT32 classDelta = property - IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY;
-
- if (classDelta >= ixEthDBPortInfo[portID].ixEthDBTrafficClassCount)
- {
- return IX_ETH_DB_FAIL;
- }
-
- * (UINT32 *) value = ixEthDBPortInfo[portID].ixEthDBTrafficClassAQMAssignments[classDelta];
- *type = IX_ETH_DB_INTEGER_PROPERTY;
-
- return IX_ETH_DB_SUCCESS;
- }
- }
-
- return IX_ETH_DB_INVALID_ARG;
-}
-
-/**
- * @brief sets the value of an EthDB property
- *
- * @param portID ID of the port
- * @param feature feature owning the property
- * @param property ID of the property
- * @param value location containing the property value
- *
- * This function implements a private property intended
- * only for EthAcc usage. Upon setting the IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE
- * property (the value is ignored), the availability of traffic classes is
- * frozen to whatever traffic class structure is currently in use.
- * This means that if VLAN_QOS has been enabled before EthAcc
- * initialization then all the defined traffic classes will be available;
- * otherwise only one traffic class (0) will be available.
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h as not accepting any parameters. The
- * current implementation is only intended for the private use of EthAcc.
- *
- * Also note that once this function is called the effect is irreversible,
- * unless EthDB is complete unloaded and re-initialized.
- *
- * @return IX_ETH_DB_INVALID_ARG (no read-write properties are
- * supported in this release)
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFeaturePropertySet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, void *value)
-{
- IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
- if ((feature == IX_ETH_DB_VLAN_QOS) && (property == IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE))
- {
- ixEthDBPortInfo[portID].ixEthDBTrafficClassAvailable = ixEthDBPortInfo[portID].ixEthDBTrafficClassCount;
-
- return IX_ETH_DB_SUCCESS;
- }
-
- return IX_ETH_DB_INVALID_ARG;
-}
+++ /dev/null
-/**
- * @file IxEthDBFirewall.c
- *
- * @brief Implementation of the firewall API
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#include "IxEthDB_p.h"
-
-/**
- * @brief updates the NPE firewall operating mode and
- * firewall address table
- *
- * @param portID ID of the port
- * @param epDelta initial entry point for binary searches (NPE optimization)
- * @param address address of the firewall MAC address table
- *
- * This function will send a message to the NPE configuring the
- * firewall mode (white list or black list), invalid source
- * address filtering and downloading a new MAC address database
- * to be used for firewall matching.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or IX_ETH_DB_FAIL otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFirewallUpdate(IxEthDBPortId portID, void *address, UINT32 epDelta)
-{
- IxNpeMhMessage message;
- IX_STATUS result;
-
- UINT32 mode = 0;
- PortInfo *portInfo = &ixEthDBPortInfo[portID];
-
- mode = (portInfo->srcAddressFilterEnabled != false) << 1 | (portInfo->firewallMode == IX_ETH_DB_FIREWALL_WHITE_LIST);
-
- FILL_SETFIREWALLMODE_MSG(message,
- IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID),
- epDelta,
- mode,
- IX_OSAL_MMU_VIRT_TO_PHYS(address));
-
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- return result;
-}
-
-/**
- * @brief configures the firewall white list/black list
- * access mode
- *
- * @param portID ID of the port
- * @param mode firewall filtering mode (IX_ETH_DB_FIREWALL_WHITE_LIST
- * or IX_ETH_DB_FIREWALL_BLACK_LIST)
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFirewallModeSet(IxEthDBPortId portID, IxEthDBFirewallMode mode)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL);
-
- if (mode != IX_ETH_DB_FIREWALL_WHITE_LIST
- && mode != IX_ETH_DB_FIREWALL_BLACK_LIST)
- {
- return IX_ETH_DB_INVALID_ARG;
- }
-
- ixEthDBPortInfo[portID].firewallMode = mode;
-
- return ixEthDBFirewallTableDownload(portID);
-}
-
-/**
- * @brief enables or disables the invalid source MAC address filter
- *
- * @param portID ID of the port
- * @param enable true to enable invalid source MAC address filtering
- * or false to disable it
- *
- * The invalid source MAC address filter will discard, when enabled,
- * frames whose source MAC address is a multicast or the broadcast MAC
- * address.
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFirewallInvalidAddressFilterEnable(IxEthDBPortId portID, BOOL enable)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL);
-
- ixEthDBPortInfo[portID].srcAddressFilterEnabled = enable;
-
- return ixEthDBFirewallTableDownload(portID);
-}
-
-/**
- * @brief adds a firewall record
- *
- * @param portID ID of the port
- * @param macAddr MAC address of the new record
- *
- * This function will add a new firewall record
- * on the specified port, using the specified
- * MAC address. If the record already exists this
- * function will silently return IX_ETH_DB_SUCCESS,
- * although no duplicate records are added.
- *
- * Note that this function is documented in the main
- * component header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFirewallEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
-{
- MacDescriptor recordTemplate;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL);
-
- memcpy(recordTemplate.macAddress, macAddr, sizeof (IxEthDBMacAddr));
-
- recordTemplate.type = IX_ETH_DB_FIREWALL_RECORD;
- recordTemplate.portID = portID;
-
- return ixEthDBAdd(&recordTemplate, NULL);
-}
-
-/**
- * @brief removes a firewall record
- *
- * @param portID ID of the port
- * @param macAddr MAC address of the record to remove
- *
- * This function will attempt to remove a firewall
- * record from the given port, using the specified
- * MAC address.
- *
- * Note that this function is documented in the main
- * component header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully of an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFirewallEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
-{
- MacDescriptor recordTemplate;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL);
-
- memcpy(recordTemplate.macAddress, macAddr, sizeof (IxEthDBMacAddr));
-
- recordTemplate.type = IX_ETH_DB_FIREWALL_RECORD;
- recordTemplate.portID = portID;
-
- return ixEthDBRemove(&recordTemplate, NULL);
-}
-
-/**
- * @brief downloads the firewall address table to an NPE
- *
- * @param portID ID of the port
- *
- * This function will download the firewall address table to
- * an NPE port.
- *
- * Note that this function is documented in the main
- * component header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or IX_ETH_DB_FAIL otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFirewallTableDownload(IxEthDBPortId portID)
-{
- IxEthDBPortMap query;
- IxEthDBStatus result;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL);
-
- SET_DEPENDENCY_MAP(query, portID);
-
- ixEthDBUpdateLock();
-
- ixEthDBPortInfo[portID].updateMethod.searchTree = ixEthDBQuery(NULL, query, IX_ETH_DB_FIREWALL_RECORD, MAX_FW_SIZE);
-
- result = ixEthDBNPEUpdateHandler(portID, IX_ETH_DB_FIREWALL_RECORD);
-
- ixEthDBUpdateUnlock();
-
- return result;
-}
+++ /dev/null
-/**
- * @file ethHash.c
- *
- * @brief Hashtable implementation
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#include "IxEthDB_p.h"
-#include "IxEthDBLocks_p.h"
-
-/**
- * @addtogroup EthDB
- *
- * @{
- */
-
-/**
- * @brief initializes a hash table object
- *
- * @param hashTable uninitialized hash table structure
- * @param numBuckets number of buckets to use
- * @param entryHashFunction hash function used
- * to hash entire hash node data block (for adding)
- * @param matchFunctions array of match functions, indexed on type,
- * used to differentiate records with the same hash value
- * @param freeFunction function used to free node data blocks
- *
- * Initializes the given hash table object.
- *
- * @internal
- */
-void ixEthDBInitHash(HashTable *hashTable,
- UINT32 numBuckets,
- HashFunction entryHashFunction,
- MatchFunction *matchFunctions,
- FreeFunction freeFunction)
-{
- UINT32 bucketIndex;
- UINT32 hashSize = numBuckets * sizeof(HashNode *);
-
- /* entry hashing, matching and freeing methods */
- hashTable->entryHashFunction = entryHashFunction;
- hashTable->matchFunctions = matchFunctions;
- hashTable->freeFunction = freeFunction;
-
- /* buckets */
- hashTable->numBuckets = numBuckets;
-
- /* set to 0 all buckets */
- memset(hashTable->hashBuckets, 0, hashSize);
-
- /* init bucket locks - note that initially all mutexes are unlocked after MutexInit()*/
- for (bucketIndex = 0 ; bucketIndex < numBuckets ; bucketIndex++)
- {
- ixOsalFastMutexInit(&hashTable->bucketLocks[bucketIndex]);
- }
-}
-
-/**
- * @brief adds an entry to the hash table
- *
- * @param hashTable hash table to add the entry to
- * @param entry entry to add
- *
- * The entry will be hashed using the entry hashing function and added to the
- * hash table, unless a locking blockage occurs, in which case the caller
- * should retry.
- *
- * @retval IX_ETH_DB_SUCCESS if adding <i>entry</i> has succeeded
- * @retval IX_ETH_DB_NOMEM if there's no memory left in the hash node pool
- * @retval IX_ETH_DB_BUSY if there's a locking failure on the insertion path
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBAddHashEntry(HashTable *hashTable, void *entry)
-{
- UINT32 hashValue = hashTable->entryHashFunction(entry);
- UINT32 bucketIndex = hashValue % hashTable->numBuckets;
- HashNode *bucket = hashTable->hashBuckets[bucketIndex];
- HashNode *newNode;
-
- LockStack locks;
-
- INIT_STACK(&locks);
-
- /* lock bucket */
- PUSH_LOCK(&locks, &hashTable->bucketLocks[bucketIndex]);
-
- /* lock insertion element (first in chain), if any */
- if (bucket != NULL)
- {
- PUSH_LOCK(&locks, &bucket->lock);
- }
-
- /* get new node */
- newNode = ixEthDBAllocHashNode();
-
- if (newNode == NULL)
- {
- /* unlock everything */
- UNROLL_STACK(&locks);
-
- return IX_ETH_DB_NOMEM;
- }
-
- /* init lock - note that mutexes are unlocked after MutexInit */
- ixOsalFastMutexInit(&newNode->lock);
-
- /* populate new link */
- newNode->data = entry;
-
- /* add to bucket */
- newNode->next = bucket;
- hashTable->hashBuckets[bucketIndex] = newNode;
-
- /* unlock bucket and insertion point */
- UNROLL_STACK(&locks);
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief removes an entry from the hashtable
- *
- * @param hashTable hash table to remove entry from
- * @param keyType type of record key used for matching
- * @param reference reference key used to identify the entry
- *
- * The reference key will be hashed using the key hashing function,
- * the entry is searched using the hashed value and then examined
- * against the reference entry using the match function. A positive
- * match will trigger the deletion of the entry.
- * Locking failures are reported and the caller should retry.
- *
- * @retval IX_ETH_DB_SUCCESS if the removal was successful
- * @retval IX_ETH_DB_NO_SUCH_ADDR if the entry was not found
- * @retval IX_ETH_DB_BUSY if a locking failure occured during the process
- *
- * @internal
- */
-IxEthDBStatus ixEthDBRemoveHashEntry(HashTable *hashTable, int keyType, void *reference)
-{
- UINT32 hashValue = hashTable->entryHashFunction(reference);
- UINT32 bucketIndex = hashValue % hashTable->numBuckets;
- HashNode *node = hashTable->hashBuckets[bucketIndex];
- HashNode *previousNode = NULL;
-
- LockStack locks;
-
- INIT_STACK(&locks);
-
- while (node != NULL)
- {
- /* try to lock node */
- PUSH_LOCK(&locks, &node->lock);
-
- if (hashTable->matchFunctions[keyType](reference, node->data))
- {
- /* found entry */
- if (node->next != NULL)
- {
- PUSH_LOCK(&locks, &node->next->lock);
- }
-
- if (previousNode == NULL)
- {
- /* node is head of chain */
- PUSH_LOCK(&locks, &hashTable->bucketLocks[bucketIndex]);
-
- hashTable->hashBuckets[bucketIndex] = node->next;
-
- POP_LOCK(&locks);
- }
- else
- {
- /* relink */
- previousNode->next = node->next;
- }
-
- UNROLL_STACK(&locks);
-
- /* free node */
- hashTable->freeFunction(node->data);
- ixEthDBFreeHashNode(node);
-
- return IX_ETH_DB_SUCCESS;
- }
- else
- {
- if (previousNode != NULL)
- {
- /* unlock previous node */
- SHIFT_STACK(&locks);
- }
-
- /* advance to next element in chain */
- previousNode = node;
- node = node->next;
- }
- }
-
- UNROLL_STACK(&locks);
-
- /* not found */
- return IX_ETH_DB_NO_SUCH_ADDR;
-}
-
-/**
- * @brief retrieves an entry from the hash table
- *
- * @param hashTable hash table to perform the search into
- * @param reference search key (a MAC address)
- * @param keyType type of record key used for matching
- * @param searchResult pointer where a reference to the located hash node
- * is placed
- *
- * Searches the entry with the same key as <i>reference</i> and places the
- * pointer to the resulting node in <i>searchResult</i>.
- * An implicit write access lock is granted after a search, which gives the
- * caller the opportunity to modify the entry.
- * Access should be released as soon as possible using @ref ixEthDBReleaseHashNode().
- *
- * @see ixEthDBReleaseHashNode()
- *
- * @retval IX_ETH_DB_SUCCESS if the search was completed successfully
- * @retval IX_ETH_DB_NO_SUCH_ADDRESS if no entry with the given key was found
- * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case
- * the caller should retry
- *
- * @warning unless the return value is <b>IX_ETH_DB_SUCCESS</b> the searchResult
- * location is NOT modified and therefore using a NULL comparison test when the
- * value was not properly initialized would be an error
- *
- * @internal
- */
-IxEthDBStatus ixEthDBSearchHashEntry(HashTable *hashTable, int keyType, void *reference, HashNode **searchResult)
-{
- UINT32 hashValue;
- HashNode *node;
-
- hashValue = hashTable->entryHashFunction(reference);
- node = hashTable->hashBuckets[hashValue % hashTable->numBuckets];
-
- while (node != NULL)
- {
- TRY_LOCK(&node->lock);
-
- if (hashTable->matchFunctions[keyType](reference, node->data))
- {
- *searchResult = node;
-
- return IX_ETH_DB_SUCCESS;
- }
- else
- {
- UNLOCK(&node->lock);
-
- node = node->next;
- }
- }
-
- /* not found */
- return IX_ETH_DB_NO_SUCH_ADDR;
-}
-
-/**
- * @brief reports the existence of an entry in the hash table
- *
- * @param hashTable hash table to perform the search into
- * @param reference search key (a MAC address)
- * @param keyType type of record key used for matching
- *
- * Searches the entry with the same key as <i>reference</i>.
- * No implicit write access lock is granted after a search, hence the
- * caller cannot access or modify the entry. The result is only temporary.
- *
- * @see ixEthDBReleaseHashNode()
- *
- * @retval IX_ETH_DB_SUCCESS if the search was completed successfully
- * @retval IX_ETH_DB_NO_SUCH_ADDRESS if no entry with the given key was found
- * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case
- * the caller should retry
- *
- * @internal
- */
-IxEthDBStatus ixEthDBPeekHashEntry(HashTable *hashTable, int keyType, void *reference)
-{
- UINT32 hashValue;
- HashNode *node;
-
- hashValue = hashTable->entryHashFunction(reference);
- node = hashTable->hashBuckets[hashValue % hashTable->numBuckets];
-
- while (node != NULL)
- {
- TRY_LOCK(&node->lock);
-
- if (hashTable->matchFunctions[keyType](reference, node->data))
- {
- UNLOCK(&node->lock);
-
- return IX_ETH_DB_SUCCESS;
- }
- else
- {
- UNLOCK(&node->lock);
-
- node = node->next;
- }
- }
-
- /* not found */
- return IX_ETH_DB_NO_SUCH_ADDR;
-}
-
-/**
- * @brief releases the write access lock
- *
- * @pre the node should have been obtained via @ref ixEthDBSearchHashEntry()
- *
- * @see ixEthDBSearchHashEntry()
- *
- * @internal
- */
-void ixEthDBReleaseHashNode(HashNode *node)
-{
- UNLOCK(&node->lock);
-}
-
-/**
- * @brief initializes a hash iterator
- *
- * @param hashTable hash table to be iterated
- * @param iterator iterator object
- *
- * If the initialization is successful the iterator will point to the
- * first hash table record (if any).
- * Testing if the iterator has not passed the end of the table should be
- * done using the IS_ITERATOR_VALID(iteratorPtr) macro.
- * An implicit write access lock is granted on the entry pointed by the iterator.
- * The access is automatically revoked when the iterator is incremented.
- * If the caller decides to terminate the iteration before the end of the table is
- * passed then the manual access release method, @ref ixEthDBReleaseHashIterator,
- * must be called.
- *
- * @see ixEthDBReleaseHashIterator()
- *
- * @retval IX_ETH_DB_SUCCESS if initialization was successful and the iterator points
- * to the first valid table node
- * @retval IX_ETH_DB_FAIL if the table is empty
- * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case the caller
- * should retry
- *
- * @warning do not use ixEthDBReleaseHashNode() on entries pointed by the iterator, as this
- * might place the database in a permanent invalid lock state
- *
- * @internal
- */
-IxEthDBStatus ixEthDBInitHashIterator(HashTable *hashTable, HashIterator *iterator)
-{
- iterator->bucketIndex = 0;
- iterator->node = NULL;
- iterator->previousNode = NULL;
-
- return ixEthDBIncrementHashIterator(hashTable, iterator);
-}
-
-/**
- * @brief releases the write access locks of the iterator nodes
- *
- * @warning use of this function is required only when the caller terminates an iteration
- * before reaching the end of the table
- *
- * @see ixEthDBInitHashIterator()
- * @see ixEthDBIncrementHashIterator()
- *
- * @param iterator iterator whose node(s) should be unlocked
- *
- * @internal
- */
-void ixEthDBReleaseHashIterator(HashIterator *iterator)
-{
- if (iterator->previousNode != NULL)
- {
- UNLOCK(&iterator->previousNode->lock);
- }
-
- if (iterator->node != NULL)
- {
- UNLOCK(&iterator->node->lock);
- }
-}
-
-/**
- * @brief incremenents an iterator so that it points to the next valid entry of the table
- * (if any)
- *
- * @param hashTable hash table to iterate
- * @param iterator iterator object
- *
- * @pre the iterator object must be initialized using @ref ixEthDBInitHashIterator()
- *
- * If the increment operation is successful the iterator will point to the
- * next hash table record (if any).
- * Testing if the iterator has not passed the end of the table should be
- * done using the IS_ITERATOR_VALID(iteratorPtr) macro.
- * An implicit write access lock is granted on the entry pointed by the iterator.
- * The access is automatically revoked when the iterator is re-incremented.
- * If the caller decides to terminate the iteration before the end of the table is
- * passed then the manual access release method, @ref ixEthDBReleaseHashIterator,
- * must be called.
- * Is is guaranteed that no other thread can remove or change the iterated entry until
- * the iterator is incremented successfully.
- *
- * @see ixEthDBReleaseHashIterator()
- *
- * @retval IX_ETH_DB_SUCCESS if the operation was successful and the iterator points
- * to the next valid table node
- * @retval IX_ETH_DB_FAIL if the iterator has passed the end of the table
- * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case the caller
- * should retry
- *
- * @warning do not use ixEthDBReleaseHashNode() on entries pointed by the iterator, as this
- * might place the database in a permanent invalid lock state
- *
- * @internal
- */
-IxEthDBStatus ixEthDBIncrementHashIterator(HashTable *hashTable, HashIterator *iterator)
-{
- /* unless iterator is just initialized... */
- if (iterator->node != NULL)
- {
- /* try next in chain */
- if (iterator->node->next != NULL)
- {
- TRY_LOCK(&iterator->node->next->lock);
-
- if (iterator->previousNode != NULL)
- {
- UNLOCK(&iterator->previousNode->lock);
- }
-
- iterator->previousNode = iterator->node;
- iterator->node = iterator->node->next;
-
- return IX_ETH_DB_SUCCESS;
- }
- else
- {
- /* last in chain, prepare for next bucket */
- iterator->bucketIndex++;
- }
- }
-
- /* try next used bucket */
- for (; iterator->bucketIndex < hashTable->numBuckets ; iterator->bucketIndex++)
- {
- HashNode **nodePtr = &(hashTable->hashBuckets[iterator->bucketIndex]);
- HashNode *node = *nodePtr;
-#if (CPU!=SIMSPARCSOLARIS) && !defined (__wince)
- if (((iterator->bucketIndex & IX_ETHDB_BUCKET_INDEX_MASK) == 0) &&
- (iterator->bucketIndex < (hashTable->numBuckets - IX_ETHDB_BUCKETPTR_AHEAD)))
- {
- /* preload next cache line (2 cache line ahead) */
- nodePtr += IX_ETHDB_BUCKETPTR_AHEAD;
- __asm__ ("pld [%0];\n": : "r" (nodePtr));
- }
-#endif
- if (node != NULL)
- {
- TRY_LOCK(&node->lock);
-
- /* unlock last one or two nodes in the previous chain */
- if (iterator->node != NULL)
- {
- UNLOCK(&iterator->node->lock);
-
- if (iterator->previousNode != NULL)
- {
- UNLOCK(&iterator->previousNode->lock);
- }
- }
-
- /* redirect iterator */
- iterator->previousNode = NULL;
- iterator->node = node;
-
- return IX_ETH_DB_SUCCESS;
- }
- }
-
- /* could not advance iterator */
- if (iterator->node != NULL)
- {
- UNLOCK(&iterator->node->lock);
-
- if (iterator->previousNode != NULL)
- {
- UNLOCK(&iterator->previousNode->lock);
- }
-
- iterator->node = NULL;
- }
-
- return IX_ETH_DB_END;
-}
-
-/**
- * @brief removes an entry pointed by an iterator
- *
- * @param hashTable iterated hash table
- * @param iterator iterator object
- *
- * Removes the entry currently pointed by the iterator and repositions the iterator
- * on the next valid entry (if any). Handles locking issues automatically and
- * implicitely grants write access lock to the new pointed entry.
- * Failures due to concurrent threads having write access locks in the same region
- * preserve the state of the database and the iterator object, leaving the caller
- * free to retry without loss of access. It is guaranteed that only the thread owning
- * the iterator can remove the object pointed by the iterator.
- *
- * @retval IX_ETH_DB_SUCCESS if removal has succeeded
- * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case the caller
- * should retry
- *
- * @internal
- */
-IxEthDBStatus ixEthDBRemoveEntryAtHashIterator(HashTable *hashTable, HashIterator *iterator)
-{
- HashIterator nextIteratorPos;
- LockStack locks;
-
- INIT_STACK(&locks);
-
- /* set initial bucket index for next position */
- nextIteratorPos.bucketIndex = iterator->bucketIndex;
-
- /* compute iterator position before removing anything and lock ahead */
- if (iterator->node->next != NULL)
- {
- PUSH_LOCK(&locks, &iterator->node->next->lock);
-
- /* reposition on the next node in the chain */
- nextIteratorPos.node = iterator->node->next;
- nextIteratorPos.previousNode = iterator->previousNode;
- }
- else
- {
- /* try next chain - don't know yet if we'll find anything */
- nextIteratorPos.node = NULL;
-
- /* if we find something it's a chain head */
- nextIteratorPos.previousNode = NULL;
-
- /* browse up in the buckets to find a non-null chain */
- while (++nextIteratorPos.bucketIndex < hashTable->numBuckets)
- {
- nextIteratorPos.node = hashTable->hashBuckets[nextIteratorPos.bucketIndex];
-
- if (nextIteratorPos.node != NULL)
- {
- /* found a non-empty chain, try to lock head */
- PUSH_LOCK(&locks, &nextIteratorPos.node->lock);
-
- break;
- }
- }
- }
-
- /* restore links over the to-be-deleted item */
- if (iterator->previousNode == NULL)
- {
- /* first in chain, lock bucket */
- PUSH_LOCK(&locks, &hashTable->bucketLocks[iterator->bucketIndex]);
-
- hashTable->hashBuckets[iterator->bucketIndex] = iterator->node->next;
-
- POP_LOCK(&locks);
- }
- else
- {
- /* relink */
- iterator->previousNode->next = iterator->node->next;
-
- /* unlock last remaining node in current chain when moving between chains */
- if (iterator->node->next == NULL)
- {
- UNLOCK(&iterator->previousNode->lock);
- }
- }
-
- /* delete entry */
- hashTable->freeFunction(iterator->node->data);
- ixEthDBFreeHashNode(iterator->node);
-
- /* reposition iterator */
- *iterator = nextIteratorPos;
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @}
- */
+++ /dev/null
-/**
- * @file IxEthDBLearning.c
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB_p.h"
-
-/**
- * @brief hashes the mac address in a mac descriptor with a XOR function
- *
- * @param entry pointer to a mac descriptor to be hashed
- *
- * This function only extracts the mac address and employs ixEthDBKeyXORHash()
- * to do the actual hashing.
- * Used only to add a whole entry to a hash table, as opposed to searching which
- * takes only a key and uses the key hashing directly.
- *
- * @see ixEthDBKeyXORHash()
- *
- * @return the hash value
- *
- * @internal
- */
-UINT32 ixEthDBEntryXORHash(void *entry)
-{
- MacDescriptor *descriptor = (MacDescriptor *) entry;
-
- return ixEthDBKeyXORHash(descriptor->macAddress);
-}
-
-/**
- * @brief hashes a mac address
- *
- * @param key pointer to a 6 byte structure (typically an IxEthDBMacAddr pointer)
- * to be hashed
- *
- * Given a 6 bytes MAC address, the hash used is:
- *
- * hash(MAC[0:5]) = MAC[0:1] ^ MAC[2:3] ^ MAC[4:5]
- *
- * Used by the hash table to search and remove entries based
- * solely on their keys (mac addresses).
- *
- * @return the hash value
- *
- * @internal
- */
-UINT32 ixEthDBKeyXORHash(void *key)
-{
- UINT32 hashValue;
- UINT8 *value = (UINT8 *) key;
-
- hashValue = (value[5] << 8) | value[4];
- hashValue ^= (value[3] << 8) | value[2];
- hashValue ^= (value[1] << 8) | value[0];
-
- return hashValue;
-}
-
-/**
- * @brief mac descriptor match function
- *
- * @param reference mac address (typically an IxEthDBMacAddr pointer) structure
- * @param entry pointer to a mac descriptor whose key (mac address) is to be
- * matched against the reference key
- *
- * Used by the hash table to retrieve entries. Hashing entries can produce
- * collisions, i.e. descriptors with different mac addresses and the same
- * hash value, where this function is used to differentiate entries.
- *
- * @retval true if the entry matches the reference key (equal addresses)
- * @retval false if the entry does not match the reference key
- *
- * @internal
- */
-BOOL ixEthDBAddressMatch(void *reference, void *entry)
-{
- return (ixEthDBAddressCompare(reference, ((MacDescriptor *) entry)->macAddress) == 0);
-}
-
-/**
- * @brief compares two mac addresses
- *
- * @param mac1 first mac address to compare
- * @param mac2 second mac address to compare
- *
- * This comparison works in a similar way to strcmp, producing similar results.
- * Used to insert values keyed on mac addresses into binary search trees.
- *
- * @retval -1 if mac1 < mac2
- * @retval 0 if ma1 == mac2
- * @retval 1 if mac1 > mac2
- */
-UINT32 ixEthDBAddressCompare(UINT8 *mac1, UINT8 *mac2)
-{
- UINT32 local_index;
-
- for (local_index = 0 ; local_index < IX_IEEE803_MAC_ADDRESS_SIZE ; local_index++)
- {
- if (mac1[local_index] > mac2[local_index])
- {
- return 1;
- }
- else if (mac1[local_index] < mac2[local_index])
- {
- return -1;
- }
- }
-
- return 0;
-}
-
+++ /dev/null
-/**
- * @file IxEthDBDBMem.c
- *
- * @brief Memory handling routines for the MAC address database
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#include "IxEthDB_p.h"
-
-IX_ETH_DB_PRIVATE HashNode *nodePool = NULL;
-IX_ETH_DB_PRIVATE MacDescriptor *macPool = NULL;
-IX_ETH_DB_PRIVATE MacTreeNode *treePool = NULL;
-
-IX_ETH_DB_PRIVATE HashNode nodePoolArea[NODE_POOL_SIZE];
-IX_ETH_DB_PRIVATE MacDescriptor macPoolArea[MAC_POOL_SIZE];
-IX_ETH_DB_PRIVATE MacTreeNode treePoolArea[TREE_POOL_SIZE];
-
-IX_ETH_DB_PRIVATE IxOsalMutex nodePoolLock;
-IX_ETH_DB_PRIVATE IxOsalMutex macPoolLock;
-IX_ETH_DB_PRIVATE IxOsalMutex treePoolLock;
-
-#define LOCK_NODE_POOL { ixOsalMutexLock(&nodePoolLock, IX_OSAL_WAIT_FOREVER); }
-#define UNLOCK_NODE_POOL { ixOsalMutexUnlock(&nodePoolLock); }
-
-#define LOCK_MAC_POOL { ixOsalMutexLock(&macPoolLock, IX_OSAL_WAIT_FOREVER); }
-#define UNLOCK_MAC_POOL { ixOsalMutexUnlock(&macPoolLock); }
-
-#define LOCK_TREE_POOL { ixOsalMutexLock(&treePoolLock, IX_OSAL_WAIT_FOREVER); }
-#define UNLOCK_TREE_POOL { ixOsalMutexUnlock(&treePoolLock); }
-
-/* private function prototypes */
-IX_ETH_DB_PRIVATE MacDescriptor* ixEthDBPoolAllocMacDescriptor(void);
-IX_ETH_DB_PRIVATE void ixEthDBPoolFreeMacDescriptor(MacDescriptor *macDescriptor);
-
-/**
- * @addtogroup EthMemoryManagement
- *
- * @{
- */
-
-/**
- * @brief initializes the memory pools used by the ethernet database component
- *
- * Initializes the hash table node, mac descriptor and mac tree node pools.
- * Called at initialization time by @ref ixEthDBInit().
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBInitMemoryPools(void)
-{
- int local_index;
-
- /* HashNode pool */
- ixOsalMutexInit(&nodePoolLock);
-
- for (local_index = 0 ; local_index < NODE_POOL_SIZE ; local_index++)
- {
- HashNode *freeNode = &nodePoolArea[local_index];
-
- freeNode->nextFree = nodePool;
- nodePool = freeNode;
- }
-
- /* MacDescriptor pool */
- ixOsalMutexInit(&macPoolLock);
-
- for (local_index = 0 ; local_index < MAC_POOL_SIZE ; local_index++)
- {
- MacDescriptor *freeDescriptor = &macPoolArea[local_index];
-
- freeDescriptor->nextFree = macPool;
- macPool = freeDescriptor;
- }
-
- /* MacTreeNode pool */
- ixOsalMutexInit(&treePoolLock);
-
- for (local_index = 0 ; local_index < TREE_POOL_SIZE ; local_index++)
- {
- MacTreeNode *freeNode = &treePoolArea[local_index];
-
- freeNode->nextFree = treePool;
- treePool = freeNode;
- }
-}
-
-/**
- * @brief allocates a hash node from the pool
- *
- * Allocates a hash node and resets its value.
- *
- * @return the allocated hash node or NULL if the pool is empty
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-HashNode* ixEthDBAllocHashNode(void)
-{
- HashNode *allocatedNode = NULL;
-
- if (nodePool != NULL)
- {
- LOCK_NODE_POOL;
-
- allocatedNode = nodePool;
- nodePool = nodePool->nextFree;
-
- UNLOCK_NODE_POOL;
-
- memset(allocatedNode, 0, sizeof(HashNode));
- }
-
- return allocatedNode;
-}
-
-/**
- * @brief frees a hash node into the pool
- *
- * @param hashNode node to be freed
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBFreeHashNode(HashNode *hashNode)
-{
- if (hashNode != NULL)
- {
- LOCK_NODE_POOL;
-
- hashNode->nextFree = nodePool;
- nodePool = hashNode;
-
- UNLOCK_NODE_POOL;
- }
-}
-
-/**
- * @brief allocates a mac descriptor from the pool
- *
- * Allocates a mac descriptor and resets its value.
- * This function is not used directly, instead @ref ixEthDBAllocMacDescriptor()
- * is used, which keeps track of the pointer reference count.
- *
- * @see ixEthDBAllocMacDescriptor()
- *
- * @warning this function is not used directly by any other function
- * apart from ixEthDBAllocMacDescriptor()
- *
- * @return the allocated mac descriptor or NULL if the pool is empty
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-MacDescriptor* ixEthDBPoolAllocMacDescriptor(void)
-{
- MacDescriptor *allocatedDescriptor = NULL;
-
- if (macPool != NULL)
- {
- LOCK_MAC_POOL;
-
- allocatedDescriptor = macPool;
- macPool = macPool->nextFree;
-
- UNLOCK_MAC_POOL;
-
- memset(allocatedDescriptor, 0, sizeof(MacDescriptor));
- }
-
- return allocatedDescriptor;
-}
-
-/**
- * @brief allocates and initializes a mac descriptor smart pointer
- *
- * Uses @ref ixEthDBPoolAllocMacDescriptor() to allocate a mac descriptor
- * from the pool and initializes its reference count.
- *
- * @see ixEthDBPoolAllocMacDescriptor()
- *
- * @return the allocated mac descriptor or NULL if the pool is empty
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-MacDescriptor* ixEthDBAllocMacDescriptor(void)
-{
- MacDescriptor *allocatedDescriptor = ixEthDBPoolAllocMacDescriptor();
-
- if (allocatedDescriptor != NULL)
- {
- LOCK_MAC_POOL;
-
- allocatedDescriptor->refCount++;
-
- UNLOCK_MAC_POOL;
- }
-
- return allocatedDescriptor;
-}
-
-/**
- * @brief frees a mac descriptor back into the pool
- *
- * @param macDescriptor mac descriptor to be freed
- *
- * @warning this function is not to be called by anyone but
- * ixEthDBFreeMacDescriptor()
- *
- * @see ixEthDBFreeMacDescriptor()
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBPoolFreeMacDescriptor(MacDescriptor *macDescriptor)
-{
- LOCK_MAC_POOL;
-
- macDescriptor->nextFree = macPool;
- macPool = macDescriptor;
-
- UNLOCK_MAC_POOL;
-}
-
-/**
- * @brief frees or reduces the usage count of a mac descriptor smart pointer
- *
- * If the reference count reaches 0 (structure is no longer used anywhere)
- * then the descriptor is freed back into the pool using ixEthDBPoolFreeMacDescriptor().
- *
- * @see ixEthDBPoolFreeMacDescriptor()
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBFreeMacDescriptor(MacDescriptor *macDescriptor)
-{
- if (macDescriptor != NULL)
- {
- LOCK_MAC_POOL;
-
- if (macDescriptor->refCount > 0)
- {
- macDescriptor->refCount--;
-
- if (macDescriptor->refCount == 0)
- {
- UNLOCK_MAC_POOL;
-
- ixEthDBPoolFreeMacDescriptor(macDescriptor);
- }
- else
- {
- UNLOCK_MAC_POOL;
- }
- }
- else
- {
- UNLOCK_MAC_POOL;
- }
- }
-}
-
-/**
- * @brief clones a mac descriptor smart pointer
- *
- * @param macDescriptor mac descriptor to clone
- *
- * Increments the usage count of the smart pointer
- *
- * @returns the cloned smart pointer
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-MacDescriptor* ixEthDBCloneMacDescriptor(MacDescriptor *macDescriptor)
-{
- LOCK_MAC_POOL;
-
- if (macDescriptor->refCount == 0)
- {
- UNLOCK_MAC_POOL;
-
- return NULL;
- }
-
- macDescriptor->refCount++;
-
- UNLOCK_MAC_POOL;
-
- return macDescriptor;
-}
-
-/**
- * @brief allocates a mac tree node from the pool
- *
- * Allocates and initializes a mac tree node from the pool.
- *
- * @return the allocated mac tree node or NULL if the pool is empty
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-MacTreeNode* ixEthDBAllocMacTreeNode(void)
-{
- MacTreeNode *allocatedNode = NULL;
-
- if (treePool != NULL)
- {
- LOCK_TREE_POOL;
-
- allocatedNode = treePool;
- treePool = treePool->nextFree;
-
- UNLOCK_TREE_POOL;
-
- memset(allocatedNode, 0, sizeof(MacTreeNode));
- }
-
- return allocatedNode;
-}
-
-/**
- * @brief frees a mac tree node back into the pool
- *
- * @param macNode mac tree node to be freed
- *
- * @warning not to be used except from ixEthDBFreeMacTreeNode().
- *
- * @see ixEthDBFreeMacTreeNode()
- *
- * @internal
- */
-void ixEthDBPoolFreeMacTreeNode(MacTreeNode *macNode)
-{
- if (macNode != NULL)
- {
- LOCK_TREE_POOL;
-
- macNode->nextFree = treePool;
- treePool = macNode;
-
- UNLOCK_TREE_POOL;
- }
-}
-
-/**
- * @brief frees or reduces the usage count of a mac tree node smart pointer
- *
- * @param macNode mac tree node to free
- *
- * Reduces the usage count of the given mac node. If the usage count
- * reaches 0 the node is freed back into the pool using ixEthDBPoolFreeMacTreeNode()
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBFreeMacTreeNode(MacTreeNode *macNode)
-{
- if (macNode->descriptor != NULL)
- {
- ixEthDBFreeMacDescriptor(macNode->descriptor);
- }
-
- if (macNode->left != NULL)
- {
- ixEthDBFreeMacTreeNode(macNode->left);
- }
-
- if (macNode->right != NULL)
- {
- ixEthDBFreeMacTreeNode(macNode->right);
- }
-
- ixEthDBPoolFreeMacTreeNode(macNode);
-}
-
-/**
- * @brief clones a mac tree node
- *
- * @param macNode mac tree node to be cloned
- *
- * Increments the usage count of the node, <i>its associated descriptor
- * and <b>recursively</b> of all its child nodes</i>.
- *
- * @warning this function is recursive and clones whole trees/subtrees, use only for
- * root nodes
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-MacTreeNode* ixEthDBCloneMacTreeNode(MacTreeNode *macNode)
-{
- if (macNode != NULL)
- {
- MacTreeNode *clonedMacNode = ixEthDBAllocMacTreeNode();
-
- if (clonedMacNode != NULL)
- {
- if (macNode->right != NULL)
- {
- clonedMacNode->right = ixEthDBCloneMacTreeNode(macNode->right);
- }
-
- if (macNode->left != NULL)
- {
- clonedMacNode->left = ixEthDBCloneMacTreeNode(macNode->left);
- }
-
- if (macNode->descriptor != NULL)
- {
- clonedMacNode->descriptor = ixEthDBCloneMacDescriptor(macNode->descriptor);
- }
- }
-
- return clonedMacNode;
- }
- else
- {
- return NULL;
- }
-}
-
-#ifndef NDEBUG
-/* Debug statistical functions for memory usage */
-
-extern HashTable dbHashtable;
-int ixEthDBNumHashElements(void);
-
-int ixEthDBNumHashElements(void)
-{
- UINT32 bucketIndex;
- int numElements = 0;
- HashTable *hashTable = &dbHashtable;
-
- for (bucketIndex = 0 ; bucketIndex < hashTable->numBuckets ; bucketIndex++)
- {
- if (hashTable->hashBuckets[bucketIndex] != NULL)
- {
- HashNode *node = hashTable->hashBuckets[bucketIndex];
-
- while (node != NULL)
- {
- numElements++;
-
- node = node->next;
- }
- }
- }
-
- return numElements;
-}
-
-UINT32 ixEthDBSearchTreeUsageGet(MacTreeNode *tree)
-{
- if (tree == NULL)
- {
- return 0;
- }
- else
- {
- return 1 /* this node */ + ixEthDBSearchTreeUsageGet(tree->left) + ixEthDBSearchTreeUsageGet(tree->right);
- }
-}
-
-int ixEthDBShowMemoryStatus(void)
-{
- MacDescriptor *mac;
- MacTreeNode *tree;
- HashNode *node;
-
- int macCounter = 0;
- int treeCounter = 0;
- int nodeCounter = 0;
-
- int totalTreeUsage = 0;
- int totalDescriptorUsage = 0;
- int totalCloneDescriptorUsage = 0;
- int totalNodeUsage = 0;
-
- UINT32 portIndex;
-
- LOCK_NODE_POOL;
- LOCK_MAC_POOL;
- LOCK_TREE_POOL;
-
- mac = macPool;
- tree = treePool;
- node = nodePool;
-
- while (mac != NULL)
- {
- macCounter++;
-
- mac = mac->nextFree;
-
- if (macCounter > MAC_POOL_SIZE)
- {
- break;
- }
- }
-
- while (tree != NULL)
- {
- treeCounter++;
-
- tree = tree->nextFree;
-
- if (treeCounter > TREE_POOL_SIZE)
- {
- break;
- }
- }
-
- while (node != NULL)
- {
- nodeCounter++;
-
- node = node->nextFree;
-
- if (nodeCounter > NODE_POOL_SIZE)
- {
- break;
- }
- }
-
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- int treeUsage = ixEthDBSearchTreeUsageGet(ixEthDBPortInfo[portIndex].updateMethod.searchTree);
-
- totalTreeUsage += treeUsage;
- totalCloneDescriptorUsage += treeUsage; /* each tree node contains a descriptor */
- }
-
- totalNodeUsage = ixEthDBNumHashElements();
- totalDescriptorUsage += totalNodeUsage; /* each hash table entry contains a descriptor */
-
- UNLOCK_NODE_POOL;
- UNLOCK_MAC_POOL;
- UNLOCK_TREE_POOL;
-
- printf("Ethernet database memory usage stats:\n\n");
-
- if (macCounter <= MAC_POOL_SIZE)
- {
- printf("\tMAC descriptor pool : %d free out of %d entries (%d%%)\n", macCounter, MAC_POOL_SIZE, macCounter * 100 / MAC_POOL_SIZE);
- }
- else
- {
- printf("\tMAC descriptor pool : invalid state (ring within the pool), normally %d entries\n", MAC_POOL_SIZE);
- }
-
- if (treeCounter <= TREE_POOL_SIZE)
- {
- printf("\tTree node pool : %d free out of %d entries (%d%%)\n", treeCounter, TREE_POOL_SIZE, treeCounter * 100 / TREE_POOL_SIZE);
- }
- else
- {
- printf("\tTREE descriptor pool : invalid state (ring within the pool), normally %d entries\n", TREE_POOL_SIZE);
- }
-
- if (nodeCounter <= NODE_POOL_SIZE)
- {
- printf("\tHash node pool : %d free out of %d entries (%d%%)\n", nodeCounter, NODE_POOL_SIZE, nodeCounter * 100 / NODE_POOL_SIZE);
- }
- else
- {
- printf("\tNODE descriptor pool : invalid state (ring within the pool), normally %d entries\n", NODE_POOL_SIZE);
- }
-
- printf("\n");
- printf("\tMAC descriptor usage : %d entries, %d cloned\n", totalDescriptorUsage, totalCloneDescriptorUsage);
- printf("\tTree node usage : %d entries\n", totalTreeUsage);
- printf("\tHash node usage : %d entries\n", totalNodeUsage);
- printf("\n");
-
- /* search for duplicate nodes in the mac pool */
- {
- MacDescriptor *reference = macPool;
-
- while (reference != NULL)
- {
- MacDescriptor *comparison = reference->nextFree;
-
- while (comparison != NULL)
- {
- if (reference == comparison)
- {
- printf("Warning: reached a duplicate (%p), invalid MAC pool state\n", reference);
-
- return 1;
- }
-
- comparison = comparison->nextFree;
- }
-
- reference = reference->nextFree;
- }
- }
-
- printf("No duplicates found in the MAC pool (sanity check ok)\n");
-
- return 0;
-}
-
-#endif /* NDEBUG */
-
-/**
- * @} EthMemoryManagement
- */
+++ /dev/null
-/**
- * @file IxEthDBDBNPEAdaptor.c
- *
- * @brief Routines that read and write learning/search trees in NPE-specific format
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB_p.h"
-#include "IxEthDBLog_p.h"
-
-/* forward prototype declarations */
-IX_ETH_DB_PUBLIC void ixEthDBELTShow(IxEthDBPortId portID);
-IX_ETH_DB_PUBLIC void ixEthDBShowNpeMsgHistory(void);
-
-/* data */
-UINT8* ixEthDBNPEUpdateArea[IX_ETH_DB_NUMBER_OF_PORTS];
-UINT32 dumpEltSize;
-
-/* private data */
-IX_ETH_DB_PRIVATE IxEthDBNoteWriteFn ixEthDBNPENodeWrite[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1];
-
-#define IX_ETH_DB_MAX_DELTA_ZONES (6) /* at most 6 EP Delta zones, according to NPE FS */
-IX_ETH_DB_PRIVATE UINT32 ixEthDBEPDeltaOffset[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1][IX_ETH_DB_MAX_DELTA_ZONES];
-IX_ETH_DB_PRIVATE UINT32 ixEthDBEPDelta[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1][IX_ETH_DB_MAX_DELTA_ZONES];
-
-/**
- * @brief allocates non-cached or contiguous NPE tree update areas for all the ports
- *
- * This function is called only once at initialization time from
- * @ref ixEthDBInit().
- *
- * @warning do not call manually
- *
- * @see ixEthDBInit()
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBNPEUpdateAreasInit(void)
-{
- UINT32 portIndex;
- PortUpdateMethod *update;
-
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- update = &ixEthDBPortInfo[portIndex].updateMethod;
-
- if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE)
- {
- update->npeUpdateZone = IX_OSAL_CACHE_DMA_MALLOC(FULL_ELT_BYTE_SIZE);
- update->npeGwUpdateZone = IX_OSAL_CACHE_DMA_MALLOC(FULL_GW_BYTE_SIZE);
- update->vlanUpdateZone = IX_OSAL_CACHE_DMA_MALLOC(FULL_VLAN_BYTE_SIZE);
-
- if (update->npeUpdateZone == NULL
- || update->npeGwUpdateZone == NULL
- || update->vlanUpdateZone == NULL)
- {
- ERROR_LOG("Fatal error: IX_ACC_DRV_DMA_MALLOC() returned NULL, no NPE update zones available\n");
- }
- else
- {
- memset(update->npeUpdateZone, 0, FULL_ELT_BYTE_SIZE);
- memset(update->npeGwUpdateZone, 0, FULL_GW_BYTE_SIZE);
- memset(update->vlanUpdateZone, 0, FULL_VLAN_BYTE_SIZE);
- }
- }
- else
- {
- /* unused */
- update->npeUpdateZone = NULL;
- update->npeGwUpdateZone = NULL;
- update->vlanUpdateZone = NULL;
- }
- }
-}
-
-/**
- * @brief deallocates the NPE update areas for all the ports
- *
- * This function is called at component de-initialization time
- * by @ref ixEthDBUnload().
- *
- * @warning do not call manually
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBNPEUpdateAreasUnload(void)
-{
- UINT32 portIndex;
-
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE)
- {
- IX_OSAL_CACHE_DMA_FREE(ixEthDBPortInfo[portIndex].updateMethod.npeUpdateZone);
- IX_OSAL_CACHE_DMA_FREE(ixEthDBPortInfo[portIndex].updateMethod.npeGwUpdateZone);
- IX_OSAL_CACHE_DMA_FREE(ixEthDBPortInfo[portIndex].updateMethod.vlanUpdateZone);
- }
- }
-}
-
-/**
- * @brief general-purpose NPE callback function
- *
- * @param npeID NPE ID
- * @param msg NPE message
- *
- * This function will unblock the caller by unlocking
- * the npeAckLock mutex defined for each NPE port
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBNpeMsgAck(IxNpeMhNpeId npeID, IxNpeMhMessage msg)
-{
- IxEthDBPortId portID = IX_ETH_DB_NPE_TO_PORT_ID(npeID);
- PortInfo *portInfo;
-
- if (portID >= IX_ETH_DB_NUMBER_OF_PORTS)
- {
- /* invalid port */
- return;
- }
-
- if (ixEthDBPortDefinitions[portID].type != IX_ETH_NPE)
- {
- /* not an NPE */
- return;
- }
-
- portInfo = &ixEthDBPortInfo[portID];
-
- ixOsalMutexUnlock(&portInfo->npeAckLock);
-}
-
-/**
- * @brief synchronizes the database with tree
- *
- * @param portID port ID of the NPE whose tree is to be scanned
- * @param eltBaseAddress memory base address of the NPE serialized tree
- * @param eltSize size in bytes of the NPE serialized tree
- *
- * Scans the NPE learning tree and resets the age of active database records.
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBNPESyncScan(IxEthDBPortId portID, void *eltBaseAddress, UINT32 eltSize)
-{
- UINT32 eltEntryOffset;
- UINT32 entryPortID;
-
- /* invalidate cache */
- IX_OSAL_CACHE_INVALIDATE(eltBaseAddress, eltSize);
-
- for (eltEntryOffset = ELT_ROOT_OFFSET ; eltEntryOffset < eltSize ; eltEntryOffset += ELT_ENTRY_SIZE)
- {
- /* (eltBaseAddress + eltEntryOffset) points to a valid NPE tree node
- *
- * the format of the node is MAC[6 bytes]:PortID[1 byte]:Reserved[6 bits]:Active[1 bit]:Valid[1 bit]
- * therefore we can just use the pointer for database searches as only the first 6 bytes are checked
- */
- void *eltNodeAddress = (void *) ((UINT32) eltBaseAddress + eltEntryOffset);
-
- /* debug */
- IX_ETH_DB_NPE_VERBOSE_TRACE("DB: (NPEAdaptor) checking node at offset %d...\n", eltEntryOffset / ELT_ENTRY_SIZE);
-
- if (IX_EDB_NPE_NODE_VALID(eltNodeAddress) != true)
- {
- IX_ETH_DB_NPE_VERBOSE_TRACE("\t... node is empty\n");
- }
- else if (eltEntryOffset == ELT_ROOT_OFFSET)
- {
- IX_ETH_DB_NPE_VERBOSE_TRACE("\t... node is root\n");
- }
-
- if (IX_EDB_NPE_NODE_VALID(eltNodeAddress))
- {
- entryPortID = IX_ETH_DB_NPE_LOGICAL_ID_TO_PORT_ID(IX_EDB_NPE_NODE_PORT_ID(eltNodeAddress));
-
- /* check only active entries belonging to this port */
- if (ixEthDBPortInfo[portID].agingEnabled && IX_EDB_NPE_NODE_ACTIVE(eltNodeAddress) && (portID == entryPortID)
- && ((ixEthDBPortDefinitions[portID].capabilities & IX_ETH_ENTRY_AGING) == 0))
- {
- /* search record */
- HashNode *node = ixEthDBSearch((IxEthDBMacAddr *) eltNodeAddress, IX_ETH_DB_ALL_FILTERING_RECORDS);
-
- /* safety check, maybe user deleted record right before sync? */
- if (node != NULL)
- {
- /* found record */
- MacDescriptor *descriptor = (MacDescriptor *) node->data;
-
- IX_ETH_DB_NPE_VERBOSE_TRACE("DB: (NPEAdaptor) synced entry [%s] already in the database, updating fields\n", mac2string(eltNodeAddress));
-
- /* reset age - set to -1 so that maintenance will restore it to 0 (or more) when incrementing */
- if (!descriptor->recordData.filteringData.staticEntry)
- {
- if (descriptor->type == IX_ETH_DB_FILTERING_RECORD)
- {
- descriptor->recordData.filteringData.age = AGE_RESET;
- }
- else if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD)
- {
- descriptor->recordData.filteringVlanData.age = AGE_RESET;
- }
- }
-
- /* end transaction */
- ixEthDBReleaseHashNode(node);
- }
- }
- else
- {
- IX_ETH_DB_NPE_VERBOSE_TRACE("\t... found portID %d, we check only port %d\n", entryPortID, portID);
- }
- }
- }
-}
-
-/**
- * @brief writes a search tree in NPE format
- *
- * @param type type of records to be written into the NPE update zone
- * @param totalSize maximum size of the linearized tree
- * @param baseAddress memory base address where to write the NPE tree into
- * @param tree search tree to write in NPE format
- * @param blocks number of written 64-byte blocks
- * @param startIndex optimal binary search start index
- *
- * Serializes the given tree in NPE linear format
- *
- * @return none
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBNPETreeWrite(IxEthDBRecordType type, UINT32 totalSize, void *baseAddress, MacTreeNode *tree, UINT32 *epDelta, UINT32 *blocks)
-{
- MacTreeNodeStack *stack;
- UINT32 maxOffset = 0;
- UINT32 emptyOffset;
-
- stack = ixOsalCacheDmaMalloc(sizeof (MacTreeNodeStack));
-
- if (stack == NULL)
- {
- ERROR_LOG("DB: (NPEAdaptor) failed to allocate the node stack for learning tree linearization, out of memory?\n");
- return;
- }
-
- /* zero out empty root */
- memset(baseAddress, 0, ELT_ENTRY_SIZE);
-
- NODE_STACK_INIT(stack);
-
- if (tree != NULL)
- {
- /* push tree root at offset 1 */
- NODE_STACK_PUSH(stack, tree, 1);
-
- maxOffset = 1;
- }
-
- while (NODE_STACK_NONEMPTY(stack))
- {
- MacTreeNode *node;
- UINT32 offset;
-
- NODE_STACK_POP(stack, node, offset);
-
- /* update maximum offset */
- if (offset > maxOffset)
- {
- maxOffset = offset;
- }
-
- IX_ETH_DB_NPE_VERBOSE_TRACE("DB: (NPEAdaptor) writing MAC [%s] at offset %d\n", mac2string(node->descriptor->macAddress), offset);
-
- /* add node to NPE ELT at position indicated by offset */
- if (offset < MAX_ELT_SIZE)
- {
- ixEthDBNPENodeWrite[type]((void *) (((UINT32) baseAddress) + offset * ELT_ENTRY_SIZE), node);
- }
-
- if (node->left != NULL)
- {
- NODE_STACK_PUSH(stack, node->left, LEFT_CHILD_OFFSET(offset));
- }
- else
- {
- /* ensure this entry is zeroed */
- memset((void *) ((UINT32) baseAddress + LEFT_CHILD_OFFSET(offset) * ELT_ENTRY_SIZE), 0, ELT_ENTRY_SIZE);
- }
-
- if (node->right != NULL)
- {
- NODE_STACK_PUSH(stack, node->right, RIGHT_CHILD_OFFSET(offset));
- }
- else
- {
- /* ensure this entry is zeroed */
- memset((void *) ((UINT32) baseAddress + RIGHT_CHILD_OFFSET(offset) * ELT_ENTRY_SIZE), 0, ELT_ENTRY_SIZE);
- }
- }
-
- emptyOffset = maxOffset + 1;
-
- /* zero out rest of the tree */
- IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Emptying tree from offset %d, address 0x%08X, %d bytes\n",
- emptyOffset, ((UINT32) baseAddress) + emptyOffset * ELT_ENTRY_SIZE, totalSize - (emptyOffset * ELT_ENTRY_SIZE));
-
- if (emptyOffset < MAX_ELT_SIZE - 1)
- {
- memset((void *) (((UINT32) baseAddress) + (emptyOffset * ELT_ENTRY_SIZE)), 0, totalSize - (emptyOffset * ELT_ENTRY_SIZE));
- }
-
- /* flush cache */
- IX_OSAL_CACHE_FLUSH(baseAddress, totalSize);
-
- /* debug */
- IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Ethernet learning/filtering tree XScale wrote at address 0x%08X (max %d bytes):\n\n",
- (UINT32) baseAddress, FULL_ELT_BYTE_SIZE);
-
- IX_ETH_DB_NPE_DUMP_ELT(baseAddress, FULL_ELT_BYTE_SIZE);
-
- /* compute number of 64-byte blocks */
- if (blocks != NULL)
- {
- *blocks = maxOffset != 0 ? 1 + maxOffset / 8 : 0;
-
- IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Wrote %d 64-byte blocks\n", *blocks);
- }
-
- /* compute epDelta - start index for binary search */
- if (epDelta != NULL)
- {
- UINT32 deltaIndex = 0;
-
- *epDelta = 0;
-
- for (; deltaIndex < IX_ETH_DB_MAX_DELTA_ZONES ; deltaIndex ++)
- {
- if (ixEthDBEPDeltaOffset[type][deltaIndex] >= maxOffset)
- {
- *epDelta = ixEthDBEPDelta[type][deltaIndex];
- break;
- }
- }
-
- IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Computed epDelta %d (based on maxOffset %d)\n", *epDelta, maxOffset);
- }
-
- ixOsalCacheDmaFree(stack);
-}
-
-/**
- * @brief implements a dummy node serialization function
- *
- * @param address address of where the node is to be serialized (unused)
- * @param node tree node to be serialized (unused)
- *
- * This function is registered for safety reasons and should
- * never be called. It will display an error message if this
- * function is called.
- *
- * @return none
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBNullSerialize(void *address, MacTreeNode *node)
-{
- IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Warning, the NullSerialize function was called, wrong record type?\n");
-}
-
-/**
- * @brief writes a filtering entry in NPE linear format
- *
- * @param address memory address to write node to
- * @param node node to be written
- *
- * Used by @ref ixEthDBNPETreeWrite to liniarize a search tree
- * in NPE-readable format.
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBNPELearningNodeWrite(void *address, MacTreeNode *node)
-{
- /* copy mac address */
- memcpy(address, node->descriptor->macAddress, IX_IEEE803_MAC_ADDRESS_SIZE);
-
- /* copy port ID */
- NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_ELT_PORT_ID_OFFSET) = IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(node->descriptor->portID);
-
- /* copy flags (valid and not active, as the NPE sets it to active) and clear reserved section (bits 2-7) */
- NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_ELT_FLAGS_OFFSET) = (UINT8) IX_EDB_FLAGS_INACTIVE_VALID;
-
- IX_ETH_DB_NPE_VERBOSE_TRACE("DB: (NPEAdaptor) writing ELT node 0x%08x:0x%08x\n", * (UINT32 *) address, * (((UINT32 *) (address)) + 1));
-}
-
-/**
- * @brief writes a WiFi header conversion record in
- * NPE linear format
- *
- * @param address memory address to write node to
- * @param node node to be written
- *
- * Used by @ref ixEthDBNPETreeWrite to liniarize a search tree
- * in NPE-readable format.
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBNPEWiFiNodeWrite(void *address, MacTreeNode *node)
-{
- /* copy mac address */
- memcpy(address, node->descriptor->macAddress, IX_IEEE803_MAC_ADDRESS_SIZE);
-
- /* copy index */
- NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_WIFI_INDEX_OFFSET) = node->descriptor->recordData.wifiData.gwAddressIndex;
-
- /* copy flags (type and valid) */
- NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_WIFI_FLAGS_OFFSET) = node->descriptor->recordData.wifiData.type << 1 | IX_EDB_FLAGS_VALID;
-}
-
-/**
- * @brief writes a WiFi gateway header conversion record in
- * NPE linear format
- *
- * @param address memory address to write node to
- * @param node node to be written
- *
- * Used by @ref ixEthDBNPETreeWrite to liniarize a search tree
- * in NPE-readable format.
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBNPEGatewayNodeWrite(void *address, MacTreeNode *node)
-{
- /* copy mac address */
- memcpy(address, node->descriptor->recordData.wifiData.gwMacAddress, IX_IEEE803_MAC_ADDRESS_SIZE);
-
- /* set reserved field, two bytes */
- NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_FW_RESERVED_OFFSET) = 0;
- NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_FW_RESERVED_OFFSET + 1) = 0;
-}
-
-/**
- * @brief writes a firewall record in
- * NPE linear format
- *
- * @param address memory address to write node to
- * @param node node to be written
- *
- * Used by @ref ixEthDBNPETreeWrite to liniarize a search tree
- * in NPE-readable format.
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBNPEFirewallNodeWrite(void *address, MacTreeNode *node)
-{
- /* set reserved field */
- NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_FW_RESERVED_OFFSET) = 0;
-
- /* set flags */
- NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_FW_FLAGS_OFFSET) = IX_EDB_FLAGS_VALID;
-
- /* copy mac address */
- memcpy((void *) ((UINT32) address + IX_EDB_NPE_NODE_FW_ADDR_OFFSET), node->descriptor->macAddress, IX_IEEE803_MAC_ADDRESS_SIZE);
-}
-
-/**
- * @brief registers the NPE serialization methods
- *
- * This functions registers NPE serialization methods
- * for writing the following types of records in NPE
- * readable linear format:
- * - filtering records
- * - WiFi header conversion records
- * - WiFi gateway header conversion records
- * - firewall records
- *
- * Note that this function should be called by the
- * component initialization function.
- *
- * @return number of registered record types
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-UINT32 ixEthDBRecordSerializeMethodsRegister()
-{
- int i;
-
- /* safety - register a blank method for everybody first */
- for ( i = 0 ; i < IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1 ; i++)
- {
- ixEthDBNPENodeWrite[i] = ixEthDBNullSerialize;
- }
-
- /* register real methods */
- ixEthDBNPENodeWrite[IX_ETH_DB_FILTERING_RECORD] = ixEthDBNPELearningNodeWrite;
- ixEthDBNPENodeWrite[IX_ETH_DB_FILTERING_VLAN_RECORD] = ixEthDBNPELearningNodeWrite;
- ixEthDBNPENodeWrite[IX_ETH_DB_WIFI_RECORD] = ixEthDBNPEWiFiNodeWrite;
- ixEthDBNPENodeWrite[IX_ETH_DB_FIREWALL_RECORD] = ixEthDBNPEFirewallNodeWrite;
- ixEthDBNPENodeWrite[IX_ETH_DB_GATEWAY_RECORD] = ixEthDBNPEGatewayNodeWrite;
-
- /* EP Delta arrays */
- memset(ixEthDBEPDeltaOffset, 0, sizeof (ixEthDBEPDeltaOffset));
- memset(ixEthDBEPDelta, 0, sizeof (ixEthDBEPDelta));
-
- /* filtering records */
- ixEthDBEPDeltaOffset[IX_ETH_DB_FILTERING_RECORD][0] = 1;
- ixEthDBEPDelta[IX_ETH_DB_FILTERING_RECORD][0] = 0;
-
- ixEthDBEPDeltaOffset[IX_ETH_DB_FILTERING_RECORD][1] = 3;
- ixEthDBEPDelta[IX_ETH_DB_FILTERING_RECORD][1] = 7;
-
- ixEthDBEPDeltaOffset[IX_ETH_DB_FILTERING_RECORD][2] = 511;
- ixEthDBEPDelta[IX_ETH_DB_FILTERING_RECORD][2] = 14;
-
- /* wifi records */
- ixEthDBEPDeltaOffset[IX_ETH_DB_WIFI_RECORD][0] = 1;
- ixEthDBEPDelta[IX_ETH_DB_WIFI_RECORD][0] = 0;
-
- ixEthDBEPDeltaOffset[IX_ETH_DB_WIFI_RECORD][1] = 3;
- ixEthDBEPDelta[IX_ETH_DB_WIFI_RECORD][1] = 7;
-
- ixEthDBEPDeltaOffset[IX_ETH_DB_WIFI_RECORD][2] = 511;
- ixEthDBEPDelta[IX_ETH_DB_WIFI_RECORD][2] = 14;
-
- /* firewall records */
- ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][0] = 0;
- ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][0] = 0;
-
- ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][1] = 1;
- ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][1] = 5;
-
- ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][2] = 3;
- ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][2] = 13;
-
- ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][3] = 7;
- ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][3] = 21;
-
- ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][4] = 15;
- ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][4] = 29;
-
- ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][5] = 31;
- ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][5] = 37;
-
- return 5; /* 5 methods registered */
-}
-
-#ifndef IX_NDEBUG
-
-IX_ETH_DB_PUBLIC UINT32 npeMsgHistory[IX_ETH_DB_NPE_MSG_HISTORY_DEPTH][2];
-IX_ETH_DB_PUBLIC UINT32 npeMsgHistoryLen = 0;
-
-/**
- * When compiled in DEBUG mode, this function can be used to display
- * the history of messages sent to the NPEs (up to 100).
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBShowNpeMsgHistory()
-{
- UINT32 i = 0;
- UINT32 base, len;
-
- if (npeMsgHistoryLen <= IX_ETH_DB_NPE_MSG_HISTORY_DEPTH)
- {
- base = 0;
- len = npeMsgHistoryLen;
- }
- else
- {
- base = npeMsgHistoryLen % IX_ETH_DB_NPE_MSG_HISTORY_DEPTH;
- len = IX_ETH_DB_NPE_MSG_HISTORY_DEPTH;
- }
-
- printf("NPE message history [last %d messages, from least to most recent]:\n", len);
-
- for (; i < len ; i++)
- {
- UINT32 pos = (base + i) % IX_ETH_DB_NPE_MSG_HISTORY_DEPTH;
- printf("msg[%d]: 0x%08x:0x%08x\n", i, npeMsgHistory[pos][0], npeMsgHistory[pos][1]);
- }
-}
-
-IX_ETH_DB_PUBLIC
-void ixEthDBELTShow(IxEthDBPortId portID)
-{
- IxNpeMhMessage message;
- IX_STATUS result;
-
- /* send EDB_GetMACAddressDatabase message */
- FILL_GETMACADDRESSDATABASE(message,
- 0 /* reserved */,
- IX_OSAL_MMU_VIRT_TO_PHYS(ixEthDBPortInfo[portID].updateMethod.npeUpdateZone));
-
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- if (result == IX_SUCCESS)
- {
- /* analyze NPE copy */
- UINT32 eltEntryOffset;
- UINT32 entryPortID;
-
- UINT32 eltBaseAddress = (UINT32) ixEthDBPortInfo[portID].updateMethod.npeUpdateZone;
- UINT32 eltSize = FULL_ELT_BYTE_SIZE;
-
- /* invalidate cache */
- IX_OSAL_CACHE_INVALIDATE((void *) eltBaseAddress, eltSize);
-
- printf("Listing records in main learning tree for port %d\n", portID);
-
- for (eltEntryOffset = ELT_ROOT_OFFSET ; eltEntryOffset < eltSize ; eltEntryOffset += ELT_ENTRY_SIZE)
- {
- /* (eltBaseAddress + eltEntryOffset) points to a valid NPE tree node
- *
- * the format of the node is MAC[6 bytes]:PortID[1 byte]:Reserved[6 bits]:Active[1 bit]:Valid[1 bit]
- * therefore we can just use the pointer for database searches as only the first 6 bytes are checked
- */
- void *eltNodeAddress = (void *) ((UINT32) eltBaseAddress + eltEntryOffset);
-
- if (IX_EDB_NPE_NODE_VALID(eltNodeAddress))
- {
- HashNode *node;
-
- entryPortID = IX_ETH_DB_NPE_LOGICAL_ID_TO_PORT_ID(IX_EDB_NPE_NODE_PORT_ID(eltNodeAddress));
-
- /* search record */
- node = ixEthDBSearch((IxEthDBMacAddr *) eltNodeAddress, IX_ETH_DB_ALL_RECORD_TYPES);
-
- printf("%s - port %d - %s ", mac2string((unsigned char *) eltNodeAddress), entryPortID,
- IX_EDB_NPE_NODE_ACTIVE(eltNodeAddress) ? "active" : "inactive");
-
- /* safety check, maybe user deleted record right before sync? */
- if (node != NULL)
- {
- /* found record */
- MacDescriptor *descriptor = (MacDescriptor *) node->data;
-
- printf("- %s ",
- descriptor->type == IX_ETH_DB_FILTERING_RECORD ? "filtering" :
- descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD ? "vlan" :
- descriptor->type == IX_ETH_DB_WIFI_RECORD ? "wifi" : "other (check main DB)");
-
- if (descriptor->type == IX_ETH_DB_FILTERING_RECORD) printf("- age %d - %s ",
- descriptor->recordData.filteringData.age,
- descriptor->recordData.filteringData.staticEntry ? "static" : "dynamic");
-
- if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD) printf("- age %d - %s - tci %d ",
- descriptor->recordData.filteringVlanData.age,
- descriptor->recordData.filteringVlanData.staticEntry ? "static" : "dynamic",
- descriptor->recordData.filteringVlanData.ieee802_1qTag);
-
- /* end transaction */
- ixEthDBReleaseHashNode(node);
- }
- else
- {
- printf("- not synced");
- }
-
- printf("\n");
- }
- }
- }
- else
- {
- ixOsalLog(IX_OSAL_LOG_LVL_FATAL, IX_OSAL_LOG_DEV_STDOUT,
- "EthDB: (ShowELT) Could not complete action (communication failure)\n",
- portID, 0, 0, 0, 0, 0);
- }
-}
-
-#endif
+++ /dev/null
-/**
- * @file IxEthDBDBPortUpdate.c
- *
- * @brief Implementation of dependency and port update handling
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB_p.h"
-
-/* forward prototype declarations */
-IX_ETH_DB_PRIVATE MacTreeNode* ixEthDBTreeInsert(MacTreeNode *searchTree, MacDescriptor *descriptor);
-IX_ETH_DB_PRIVATE void ixEthDBCreateTrees(IxEthDBPortMap updatePorts);
-IX_ETH_DB_PRIVATE MacTreeNode* ixEthDBTreeRebalance(MacTreeNode *searchTree);
-IX_ETH_DB_PRIVATE void ixEthDBRebalanceTreeToVine(MacTreeNode *root, UINT32 *size);
-IX_ETH_DB_PRIVATE void ixEthDBRebalanceVineToTree(MacTreeNode *root, UINT32 size);
-IX_ETH_DB_PRIVATE void ixEthDBRebalanceCompression(MacTreeNode *root, UINT32 count);
-IX_ETH_DB_PRIVATE UINT32 ixEthDBRebalanceLog2Floor(UINT32 x);
-
-extern HashTable dbHashtable;
-
-/**
- * @brief register types requiring automatic updates
- *
- * @param typeArray array indexed on record types, each
- * element indicating whether the record type requires an
- * automatic update (true) or not (false)
- *
- * Automatic updates are done for registered record types
- * upon adding, updating (that is, updating the record portID)
- * and removing records. Whenever an automatic update is triggered
- * the appropriate ports will be provided with new database
- * information.
- *
- * It is assumed that the typeArray parameter is allocated large
- * enough to hold all the user defined types. Also, the type
- * array should be initialized to false as this function only
- * caters for types which do require automatic updates.
- *
- * Note that this function should be called by the component
- * initialization function.
- *
- * @return number of record types registered for automatic
- * updates
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-UINT32 ixEthDBUpdateTypeRegister(BOOL *typeArray)
-{
- typeArray[IX_ETH_DB_FILTERING_RECORD] = true;
- typeArray[IX_ETH_DB_FILTERING_VLAN_RECORD] = true;
-
- return 2;
-}
-
-/**
- * @brief computes dependencies and triggers port learning tree updates
- *
- * @param triggerPorts port map consisting in the ports which triggered the update
- *
- * This function browses through all the ports and determines how to waterfall the update
- * event from the trigger ports to all other ports depending on them.
- *
- * Once the list of ports to be updated is determined this function
- * calls @ref ixEthDBCreateTrees.
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBUpdatePortLearningTrees(IxEthDBPortMap triggerPorts)
-{
- IxEthDBPortMap updatePorts;
- UINT32 portIndex;
-
- ixEthDBUpdateLock();
-
- SET_EMPTY_DEPENDENCY_MAP(updatePorts);
-
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- PortInfo *port = &ixEthDBPortInfo[portIndex];
- BOOL mapsCollide;
-
- MAPS_COLLIDE(mapsCollide, triggerPorts, port->dependencyPortMap);
-
- if (mapsCollide /* do triggers influence this port? */
- && !IS_PORT_INCLUDED(portIndex, updatePorts) /* and it's not already in the update list */
- && port->updateMethod.updateEnabled) /* and we're allowed to update it */
- {
- IX_ETH_DB_UPDATE_TRACE("DB: (Update) Adding port %d to update set\n", portIndex);
-
- JOIN_PORT_TO_MAP(updatePorts, portIndex);
- }
- else
- {
- IX_ETH_DB_UPDATE_TRACE("DB: (Update) Didn't add port %d to update set, reasons follow:\n", portIndex);
-
- if (!mapsCollide)
- {
- IX_ETH_DB_UPDATE_TRACE("\tMaps don't collide on port %d\n", portIndex);
- }
-
- if (IS_PORT_INCLUDED(portIndex, updatePorts))
- {
- IX_ETH_DB_UPDATE_TRACE("\tPort %d is already in the update set\n", portIndex);
- }
-
- if (!port->updateMethod.updateEnabled)
- {
- IX_ETH_DB_UPDATE_TRACE("\tPort %d doesn't have updateEnabled set\n", portIndex);
- }
- }
- }
-
- IX_ETH_DB_UPDATE_TRACE("DB: (Update) Updating port set\n");
-
- ixEthDBCreateTrees(updatePorts);
-
- ixEthDBUpdateUnlock();
-}
-
-/**
- * @brief creates learning trees and calls the port update handlers
- *
- * @param updatePorts set of ports in need of learning trees
- *
- * This function determines the optimal method of creating learning
- * trees using a minimal number of database queries, keeping in mind
- * that different ports can either use the same learning trees or they
- * can partially share them. The actual tree building routine is
- * @ref ixEthDBQuery.
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBCreateTrees(IxEthDBPortMap updatePorts)
-{
- UINT32 portIndex;
- BOOL result;
- BOOL portsLeft = true;
-
- while (portsLeft)
- {
- /* get port with minimal dependency map and NULL search tree */
- UINT32 minPortIndex = MAX_PORT_SIZE;
- UINT32 minimalSize = MAX_PORT_SIZE;
-
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- UINT32 size;
- PortInfo *port = &ixEthDBPortInfo[portIndex];
-
- /* generate trees only for ports that need them */
- if (!port->updateMethod.searchTreePendingWrite && IS_PORT_INCLUDED(portIndex, updatePorts))
- {
- GET_MAP_SIZE(port->dependencyPortMap, size);
-
- IX_ETH_DB_UPDATE_TRACE("DB: (Update) Dependency map for port %d: size %d\n",
- portIndex, size);
-
- if (size < minimalSize)
- {
- minPortIndex = portIndex;
- minimalSize = size;
- }
- }
- else
- {
- IX_ETH_DB_UPDATE_TRACE("DB: (Update) Skipped port %d from tree diff (%s)\n", portIndex,
- port->updateMethod.searchTreePendingWrite ? "pending write access" : "ignored by query");
- }
- }
-
- /* if a port was found than minimalSize is not MAX_PORT_SIZE */
- if (minimalSize != MAX_PORT_SIZE)
- {
- /* minPortIndex is the port we seek */
- PortInfo *port = &ixEthDBPortInfo[minPortIndex];
-
- IxEthDBPortMap query;
- MacTreeNode *baseTree;
-
- /* now try to find a port with minimal map difference */
- PortInfo *minimalDiffPort = NULL;
- UINT32 minimalDiff = MAX_PORT_SIZE;
-
- IX_ETH_DB_UPDATE_TRACE("DB: (Update) Minimal size port is %d\n", minPortIndex);
-
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- PortInfo *diffPort = &ixEthDBPortInfo[portIndex];
- BOOL mapIsSubset;
-
- IS_MAP_SUBSET(mapIsSubset, diffPort->dependencyPortMap, port->dependencyPortMap);
-
-
- if (portIndex != minPortIndex
- && diffPort->updateMethod.searchTree != NULL
- && mapIsSubset)
- {
- /* compute size and pick only minimal size difference */
- UINT32 diffPortSize;
- UINT32 sizeDifference;
-
- GET_MAP_SIZE(diffPort->dependencyPortMap, diffPortSize);
-
- IX_ETH_DB_UPDATE_TRACE("DB: (Update) Checking port %d for differences...\n", portIndex);
-
- sizeDifference = minimalSize - diffPortSize;
-
- if (sizeDifference < minimalDiff)
- {
- minimalDiffPort = diffPort;
- minimalDiff = sizeDifference;
-
- IX_ETH_DB_UPDATE_TRACE("DB: (Update) Minimal difference 0x%x was found on port %d\n",
- minimalDiff, portIndex);
- }
- }
- }
-
- /* check if filtering is enabled on this port */
- if ((port->featureStatus & IX_ETH_DB_FILTERING) != 0)
- {
- /* if minimalDiff is not MAX_PORT_SIZE minimalDiffPort points to the most similar port */
- if (minimalDiff != MAX_PORT_SIZE)
- {
- baseTree = ixEthDBCloneMacTreeNode(minimalDiffPort->updateMethod.searchTree);
- DIFF_MAPS(query, port->dependencyPortMap , minimalDiffPort->dependencyPortMap);
-
- IX_ETH_DB_UPDATE_TRACE("DB: (Update) Found minimal diff, extending tree %d on query\n",
- minimalDiffPort->portID);
- }
- else /* .. otherwise no similar port was found, build tree from scratch */
- {
- baseTree = NULL;
-
- COPY_DEPENDENCY_MAP(query, port->dependencyPortMap);
-
- IX_ETH_DB_UPDATE_TRACE("DB: (Update) No similar diff, creating tree from query\n");
- }
-
- IS_EMPTY_DEPENDENCY_MAP(result, query);
-
- if (!result) /* otherwise we don't need anything more on top of the cloned tree */
- {
- IX_ETH_DB_UPDATE_TRACE("DB: (Update) Adding query tree to port %d\n", minPortIndex);
-
- /* build learning tree */
- port->updateMethod.searchTree = ixEthDBQuery(baseTree, query, IX_ETH_DB_ALL_FILTERING_RECORDS, MAX_ELT_SIZE);
- }
- else
- {
- IX_ETH_DB_UPDATE_TRACE("DB: (Update) Query is empty, assuming identical nearest tree\n");
-
- port->updateMethod.searchTree = baseTree;
- }
- }
- else
- {
- /* filtering is not enabled, will download an empty tree */
- if (port->updateMethod.searchTree != NULL)
- {
- ixEthDBFreeMacTreeNode(port->updateMethod.searchTree);
- }
-
- port->updateMethod.searchTree = NULL;
- }
-
- /* mark tree as valid */
- port->updateMethod.searchTreePendingWrite = true;
- }
- else
- {
- portsLeft = false;
-
- IX_ETH_DB_UPDATE_TRACE("DB: (Update) No trees to create this round\n");
- }
- }
-
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- PortInfo *updatePort = &ixEthDBPortInfo[portIndex];
-
- if (updatePort->updateMethod.searchTreePendingWrite)
- {
- IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) Starting procedure to upload new search tree (%snull) into NPE %d\n",
- updatePort->updateMethod.searchTree != NULL ? "not " : "",
- portIndex);
-
- updatePort->updateMethod.updateHandler(portIndex, IX_ETH_DB_FILTERING_RECORD);
- }
- }
-}
-
-/**
- * @brief standard NPE update handler
- *
- * @param portID id of the port to be updated
- * @param type record type to be pushed during this update
- *
- * The NPE update handler manages updating the NPE databases
- * given a certain record type.
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBNPEUpdateHandler(IxEthDBPortId portID, IxEthDBRecordType type)
-{
- UINT32 epDelta, blockCount;
- IxNpeMhMessage message;
- UINT32 treeSize = 0;
- PortInfo *port = &ixEthDBPortInfo[portID];
-
- /* size selection and type check */
- if (type == IX_ETH_DB_FILTERING_RECORD || type == IX_ETH_DB_WIFI_RECORD)
- {
- treeSize = FULL_ELT_BYTE_SIZE;
- }
- else if (type == IX_ETH_DB_FIREWALL_RECORD)
- {
- treeSize = FULL_FW_BYTE_SIZE;
- }
- else
- {
- return IX_ETH_DB_INVALID_ARG;
- }
-
- /* serialize tree into memory */
- ixEthDBNPETreeWrite(type, treeSize, port->updateMethod.npeUpdateZone, port->updateMethod.searchTree, &epDelta, &blockCount);
-
- /* free internal copy */
- if (port->updateMethod.searchTree != NULL)
- {
- ixEthDBFreeMacTreeNode(port->updateMethod.searchTree);
- }
-
- /* forget last used search tree */
- port->updateMethod.searchTree = NULL;
- port->updateMethod.searchTreePendingWrite = false;
-
- /* dependending on the update type we do different things */
- if (type == IX_ETH_DB_FILTERING_RECORD || type == IX_ETH_DB_WIFI_RECORD)
- {
- IX_STATUS result;
-
- FILL_SETMACADDRESSDATABASE_MSG(message, IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID),
- epDelta, blockCount,
- IX_OSAL_MMU_VIRT_TO_PHYS(port->updateMethod.npeUpdateZone));
-
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- if (result == IX_SUCCESS)
- {
- IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) Finished downloading NPE tree on port %d\n", portID);
- }
- else
- {
- ixEthDBPortInfo[portID].agingEnabled = false;
- ixEthDBPortInfo[portID].updateMethod.updateEnabled = false;
- ixEthDBPortInfo[portID].updateMethod.userControlled = true;
-
- ERROR_LOG("EthDB: (PortUpdate) disabling aging and updates on port %d (assumed dead)\n", portID);
-
- ixEthDBDatabaseClear(portID, IX_ETH_DB_ALL_RECORD_TYPES);
-
- return IX_ETH_DB_FAIL;
- }
-
- return IX_ETH_DB_SUCCESS;
- }
- else if (type == IX_ETH_DB_FIREWALL_RECORD)
- {
- return ixEthDBFirewallUpdate(portID, port->updateMethod.npeUpdateZone, epDelta);
- }
-
- return IX_ETH_DB_INVALID_ARG;
-}
-
-/**
- * @brief queries the database for a set of records to be inserted into a given tree
- *
- * @param searchTree pointer to a tree where insertions will be performed; can be NULL
- * @param query set of ports that a database record must match to be inserted into the tree
- *
- * The query method browses through the database, extracts all the descriptors matching
- * the given query parameter and inserts them into the given learning tree.
- * Note that this is an append procedure, the given tree needs not to be empty.
- * A "descriptor matching the query" is a descriptor whose port id is in the query map.
- * If the given tree is empty (NULL) a new tree is created and returned.
- *
- * @return the tree root
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-MacTreeNode* ixEthDBQuery(MacTreeNode *searchTree, IxEthDBPortMap query, IxEthDBRecordType recordFilter, UINT32 maxEntries)
-{
- HashIterator iterator;
- UINT32 entryCount = 0;
-
- /* browse database */
- BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator));
-
- while (IS_ITERATOR_VALID(&iterator))
- {
- MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data;
-
- IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) querying [%s]:%d on port map ... ",
- mac2string(descriptor->macAddress),
- descriptor->portID);
-
- if ((descriptor->type & recordFilter) != 0
- && IS_PORT_INCLUDED(descriptor->portID, query))
- {
- MacDescriptor *descriptorClone = ixEthDBCloneMacDescriptor(descriptor);
-
- IX_ETH_DB_UPDATE_TRACE("match\n");
-
- if (descriptorClone != NULL)
- {
- /* add descriptor to tree */
- searchTree = ixEthDBTreeInsert(searchTree, descriptorClone);
-
- entryCount++;
- }
- }
- else
- {
- IX_ETH_DB_UPDATE_TRACE("no match\n");
- }
-
- if (entryCount < maxEntries)
- {
- /* advance to the next record */
- BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator));
- }
- else
- {
- /* the NPE won't accept more entries so we can stop now */
- ixEthDBReleaseHashIterator(&iterator);
-
- IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) number of elements reached maximum supported by port\n");
-
- break;
- }
- }
-
- IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) query inserted %d records in the search tree\n", entryCount);
-
- return ixEthDBTreeRebalance(searchTree);
-}
-
-/**
- * @brief inserts a mac descriptor into an tree
- *
- * @param searchTree tree where the insertion is to be performed (may be NULL)
- * @param descriptor descriptor to insert into tree
- *
- * @return the tree root
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-MacTreeNode* ixEthDBTreeInsert(MacTreeNode *searchTree, MacDescriptor *descriptor)
-{
- MacTreeNode *currentNode = searchTree;
- MacTreeNode *insertLocation = NULL;
- MacTreeNode *newNode;
- INT32 insertPosition = RIGHT;
-
- if (descriptor == NULL)
- {
- return searchTree;
- }
-
- /* create a new node */
- newNode = ixEthDBAllocMacTreeNode();
-
- if (newNode == NULL)
- {
- /* out of memory */
- ERROR_LOG("Warning: ixEthDBAllocMacTreeNode returned NULL in file %s:%d (out of memory?)\n", __FILE__, __LINE__);
-
- ixEthDBFreeMacDescriptor(descriptor);
-
- return NULL;
- }
-
- /* populate node */
- newNode->descriptor = descriptor;
-
- /* an empty initial tree is a special case */
- if (searchTree == NULL)
- {
- return newNode;
- }
-
- /* get insertion location */
- while (insertLocation == NULL)
- {
- MacTreeNode *nextNode;
-
- /* compare given key with current node key */
- insertPosition = ixEthDBAddressCompare(descriptor->macAddress, currentNode->descriptor->macAddress);
-
- /* navigate down */
- if (insertPosition == RIGHT)
- {
- nextNode = currentNode->right;
- }
- else if (insertPosition == LEFT)
- {
- nextNode = currentNode->left;
- }
- else
- {
- /* error, duplicate key */
- ERROR_LOG("Warning: trapped insertion of a duplicate MAC address in an NPE search tree\n");
-
- /* this will free the MAC descriptor as well */
- ixEthDBFreeMacTreeNode(newNode);
-
- return searchTree;
- }
-
- /* when we can no longer dive through the tree we found the insertion place */
- if (nextNode != NULL)
- {
- currentNode = nextNode;
- }
- else
- {
- insertLocation = currentNode;
- }
- }
-
- /* insert node */
- if (insertPosition == RIGHT)
- {
- insertLocation->right = newNode;
- }
- else
- {
- insertLocation->left = newNode;
- }
-
- return searchTree;
-}
-
-/**
- * @brief balance a tree
- *
- * @param searchTree tree to balance
- *
- * Converts a tree into a balanced tree and returns the root of
- * the balanced tree. The resulting tree is <i>route balanced</i>
- * not <i>perfectly balanced</i>. This makes no difference to the
- * average tree search time which is the same in both cases, O(log2(n)).
- *
- * @return root of the balanced tree or NULL if there's no memory left
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-MacTreeNode* ixEthDBTreeRebalance(MacTreeNode *searchTree)
-{
- MacTreeNode *pseudoRoot = ixEthDBAllocMacTreeNode();
- UINT32 size;
-
- if (pseudoRoot == NULL)
- {
- /* out of memory */
- return NULL;
- }
-
- pseudoRoot->right = searchTree;
-
- ixEthDBRebalanceTreeToVine(pseudoRoot, &size);
- ixEthDBRebalanceVineToTree(pseudoRoot, size);
-
- searchTree = pseudoRoot->right;
-
- /* remove pseudoRoot right branch, otherwise it will free the entire tree */
- pseudoRoot->right = NULL;
-
- ixEthDBFreeMacTreeNode(pseudoRoot);
-
- return searchTree;
-}
-
-/**
- * @brief converts a tree into a vine
- *
- * @param root root of tree to convert
- * @param size depth of vine (equal to the number of nodes in the tree)
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBRebalanceTreeToVine(MacTreeNode *root, UINT32 *size)
-{
- MacTreeNode *vineTail = root;
- MacTreeNode *remainder = vineTail->right;
- MacTreeNode *tempPtr;
-
- *size = 0;
-
- while (remainder != NULL)
- {
- if (remainder->left == NULL)
- {
- /* move tail down one */
- vineTail = remainder;
- remainder = remainder->right;
- (*size)++;
- }
- else
- {
- /* rotate around remainder */
- tempPtr = remainder->left;
- remainder->left = tempPtr->right;
- tempPtr->right = remainder;
- remainder = tempPtr;
- vineTail->right = tempPtr;
- }
- }
-}
-
-/**
- * @brief converts a vine into a balanced tree
- *
- * @param root vine to convert
- * @param size depth of vine
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBRebalanceVineToTree(MacTreeNode *root, UINT32 size)
-{
- UINT32 leafCount = size + 1 - (1 << ixEthDBRebalanceLog2Floor(size + 1));
-
- ixEthDBRebalanceCompression(root, leafCount);
-
- size = size - leafCount;
-
- while (size > 1)
- {
- ixEthDBRebalanceCompression(root, size / 2);
-
- size /= 2;
- }
-}
-
-/**
- * @brief compresses a vine/tree stage into a more balanced vine/tree
- *
- * @param root root of the tree to compress
- * @param count number of "spine" nodes
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBRebalanceCompression(MacTreeNode *root, UINT32 count)
-{
- MacTreeNode *scanner = root;
- MacTreeNode *child;
- UINT32 local_index;
-
- for (local_index = 0 ; local_index < count ; local_index++)
- {
- child = scanner->right;
- scanner->right = child->right;
- scanner = scanner->right;
- child->right = scanner->left;
- scanner->left = child;
- }
-}
-
-/**
- * @brief computes |_log2(x)_| (a.k.a. floor(log2(x)))
- *
- * @param x number to compute |_log2(x)_| for
- *
- * @return |_log2(x)_|
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-UINT32 ixEthDBRebalanceLog2Floor(UINT32 x)
-{
- UINT32 log = 0;
- UINT32 val = 1;
-
- while (val < x)
- {
- log++;
- val <<= 1;
- }
-
- return val == x ? log : log - 1;
-}
-
+++ /dev/null
-/**
- * @file IxEthDBAPI.c
- *
- * @brief Implementation of the public API
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB_p.h"
-
-extern HashTable dbHashtable;
-IX_ETH_DB_PRIVATE void ixEthDBPortInfoShow(IxEthDBPortId portID, IxEthDBRecordType recordFilter);
-IX_ETH_DB_PRIVATE IxEthDBStatus ixEthDBHeaderShow(IxEthDBRecordType recordFilter);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBDependencyPortMapShow(IxEthDBPortId portID, IxEthDBPortMap map);
-
-/**
- * @brief displays a port dependency map
- *
- * @param portID ID of the port
- * @param map port map to display
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBDependencyPortMapShow(IxEthDBPortId portID, IxEthDBPortMap map)
-{
- UINT32 portIndex;
- BOOL mapSelf = true, mapNone = true, firstPort = true;
-
- /* dependency port maps */
- printf("Dependency port map: ");
-
- /* browse the port map */
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- if (IS_PORT_INCLUDED(portIndex, map))
- {
- mapNone = false;
-
- if (portIndex != portID)
- {
- mapSelf = false;
- }
-
- printf("%s%d", firstPort ? "{" : ", ", portIndex);
-
- firstPort = false;
- }
- }
-
- if (mapNone)
- {
- mapSelf = false;
- }
-
- printf("%s (%s)\n", firstPort ? "" : "}", mapSelf ? "self" : mapNone ? "none" : "group");
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief displays all the filtering records belonging to a port
- *
- * @param portID ID of the port to display
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @warning deprecated, use @ref ixEthDBFilteringDatabaseShowRecords()
- * instead. Calling this function is equivalent to calling
- * ixEthDBFilteringDatabaseShowRecords(portID, IX_ETH_DB_FILTERING_RECORD)
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringDatabaseShow(IxEthDBPortId portID)
-{
- IxEthDBStatus local_result;
- HashIterator iterator;
- PortInfo *portInfo;
- UINT32 recordCount = 0;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- portInfo = &ixEthDBPortInfo[portID];
-
- /* display table header */
- printf("Ethernet database records for port ID [%d]\n", portID);
-
- ixEthDBDependencyPortMapShow(portID, portInfo->dependencyPortMap);
-
- if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
- {
- printf("NPE updates are %s\n\n", portInfo->updateMethod.updateEnabled ? "enabled" : "disabled");
- }
- else
- {
- printf("updates disabled (not an NPE)\n\n");
- }
-
- printf(" MAC address | Age | Type \n");
- printf("___________________________________\n");
-
- /* browse database */
- BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator));
-
- while (IS_ITERATOR_VALID(&iterator))
- {
- MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data;
-
- if (descriptor->portID == portID && descriptor->type == IX_ETH_DB_FILTERING_RECORD)
- {
- recordCount++;
-
- /* display entry */
- printf(" %02X:%02X:%02X:%02X:%02X:%02X | %5d | %s\n",
- descriptor->macAddress[0],
- descriptor->macAddress[1],
- descriptor->macAddress[2],
- descriptor->macAddress[3],
- descriptor->macAddress[4],
- descriptor->macAddress[5],
- descriptor->recordData.filteringData.age,
- descriptor->recordData.filteringData.staticEntry ? "static" : "dynamic");
- }
-
- /* move to the next record */
- BUSY_RETRY_WITH_RESULT(ixEthDBIncrementHashIterator(&dbHashtable, &iterator), local_result);
-
- /* debug */
- if (local_result == IX_ETH_DB_BUSY)
- {
- return IX_ETH_DB_FAIL;
- }
- }
-
- /* display number of records */
- printf("\nFound %d records\n", recordCount);
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief displays all the filtering records belonging to all the ports
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @warning deprecated, use @ref ixEthDBFilteringDatabaseShowRecords()
- * instead. Calling this function is equivalent to calling
- * ixEthDBFilteringDatabaseShowRecords(IX_ETH_DB_ALL_PORTS, IX_ETH_DB_FILTERING_RECORD)
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBFilteringDatabaseShowAll()
-{
- IxEthDBPortId portIndex;
-
- printf("\nEthernet learning/filtering database: listing %d ports\n\n", (UINT32) IX_ETH_DB_NUMBER_OF_PORTS);
-
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- ixEthDBFilteringDatabaseShow(portIndex);
-
- if (portIndex < IX_ETH_DB_NUMBER_OF_PORTS - 1)
- {
- printf("\n");
- }
- }
-}
-
-/**
- * @brief displays one record in a format depending on the record filter
- *
- * @param descriptor pointer to the record
- * @param recordFilter format filter
- *
- * This function will display the fields in a record depending on the
- * selected record filter.
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBRecordShow(MacDescriptor *descriptor, IxEthDBRecordType recordFilter)
-{
- if (recordFilter == IX_ETH_DB_FILTERING_VLAN_RECORD
- || recordFilter == (IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD))
- {
- /* display VLAN record header - leave this commented code in place, its purpose is to align the print format with the header
- printf(" MAC address | Age | Type | VLAN ID | CFI | QoS class \n");
- printf("___________________________________________________________________\n"); */
-
- if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD)
- {
- printf("%02X:%02X:%02X:%02X:%02X:%02X | %3d | %s | %d | %d | %d\n",
- descriptor->macAddress[0],
- descriptor->macAddress[1],
- descriptor->macAddress[2],
- descriptor->macAddress[3],
- descriptor->macAddress[4],
- descriptor->macAddress[5],
- descriptor->recordData.filteringVlanData.age,
- descriptor->recordData.filteringVlanData.staticEntry ? "static" : "dynamic",
- IX_ETH_DB_GET_VLAN_ID(descriptor->recordData.filteringVlanData.ieee802_1qTag),
- (descriptor->recordData.filteringVlanData.ieee802_1qTag & 0x1000) >> 12,
- IX_ETH_DB_GET_QOS_PRIORITY(descriptor->recordData.filteringVlanData.ieee802_1qTag));
- }
- else if (descriptor->type == IX_ETH_DB_FILTERING_RECORD)
- {
- printf("%02X:%02X:%02X:%02X:%02X:%02X | %3d | %s | - | - | -\n",
- descriptor->macAddress[0],
- descriptor->macAddress[1],
- descriptor->macAddress[2],
- descriptor->macAddress[3],
- descriptor->macAddress[4],
- descriptor->macAddress[5],
- descriptor->recordData.filteringData.age,
- descriptor->recordData.filteringData.staticEntry ? "static" : "dynamic");
- }
- }
- else if (recordFilter == IX_ETH_DB_FILTERING_RECORD)
- {
- /* display filtering record header - leave this commented code in place, its purpose is to align the print format with the header
- printf(" MAC address | Age | Type \n");
- printf("_______________________________________\n"); */
-
- if (descriptor->type == IX_ETH_DB_FILTERING_RECORD)
- {
- printf("%02X:%02X:%02X:%02X:%02X:%02X | %3d | %s \n",
- descriptor->macAddress[0],
- descriptor->macAddress[1],
- descriptor->macAddress[2],
- descriptor->macAddress[3],
- descriptor->macAddress[4],
- descriptor->macAddress[5],
- descriptor->recordData.filteringData.age,
- descriptor->recordData.filteringData.staticEntry ? "static" : "dynamic");
- }
- }
- else if (recordFilter == IX_ETH_DB_WIFI_RECORD)
- {
- /* display WiFi record header - leave this commented code in place, its purpose is to align the print format with the header
- printf(" MAC address | GW MAC address \n");
- printf("_______________________________________\n"); */
-
- if (descriptor->type == IX_ETH_DB_WIFI_RECORD)
- {
- if (descriptor->recordData.wifiData.type == IX_ETH_DB_WIFI_AP_TO_AP)
- {
- /* gateway address present */
- printf("%02X:%02X:%02X:%02X:%02X:%02X | %02X:%02X:%02X:%02X:%02X:%02X \n",
- descriptor->macAddress[0],
- descriptor->macAddress[1],
- descriptor->macAddress[2],
- descriptor->macAddress[3],
- descriptor->macAddress[4],
- descriptor->macAddress[5],
- descriptor->recordData.wifiData.gwMacAddress[0],
- descriptor->recordData.wifiData.gwMacAddress[1],
- descriptor->recordData.wifiData.gwMacAddress[2],
- descriptor->recordData.wifiData.gwMacAddress[3],
- descriptor->recordData.wifiData.gwMacAddress[4],
- descriptor->recordData.wifiData.gwMacAddress[5]);
- }
- else
- {
- /* no gateway */
- printf("%02X:%02X:%02X:%02X:%02X:%02X | ----no gateway----- \n",
- descriptor->macAddress[0],
- descriptor->macAddress[1],
- descriptor->macAddress[2],
- descriptor->macAddress[3],
- descriptor->macAddress[4],
- descriptor->macAddress[5]);
- }
- }
- }
- else if (recordFilter == IX_ETH_DB_FIREWALL_RECORD)
- {
- /* display Firewall record header - leave this commented code in place, its purpose is to align the print format with the header
- printf(" MAC address \n");
- printf("__________________\n"); */
-
- if (descriptor->type == IX_ETH_DB_FIREWALL_RECORD)
- {
- printf("%02X:%02X:%02X:%02X:%02X:%02X \n",
- descriptor->macAddress[0],
- descriptor->macAddress[1],
- descriptor->macAddress[2],
- descriptor->macAddress[3],
- descriptor->macAddress[4],
- descriptor->macAddress[5]);
- }
- }
- else if (recordFilter == IX_ETH_DB_ALL_RECORD_TYPES)
- {
- /* display composite record header - leave this commented code in place, its purpose is to align the print format with the header
- printf(" MAC address | Record | Age| Type | VLAN |CFI| QoS | GW MAC address \n");
- printf("_______________________________________________________________________________\n"); */
-
- if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD)
- {
- printf("%02X:%02X:%02X:%02X:%02X:%02X | VLAN | %2d | %s | %4d | %1d | %1d | -----------------\n",
- descriptor->macAddress[0],
- descriptor->macAddress[1],
- descriptor->macAddress[2],
- descriptor->macAddress[3],
- descriptor->macAddress[4],
- descriptor->macAddress[5],
- descriptor->recordData.filteringVlanData.age,
- descriptor->recordData.filteringVlanData.staticEntry ? "static " : "dynamic",
- IX_ETH_DB_GET_VLAN_ID(descriptor->recordData.filteringVlanData.ieee802_1qTag),
- (descriptor->recordData.filteringVlanData.ieee802_1qTag & 0x1000) >> 12,
- IX_ETH_DB_GET_QOS_PRIORITY(descriptor->recordData.filteringVlanData.ieee802_1qTag));
- }
- else if (descriptor->type == IX_ETH_DB_FILTERING_RECORD)
- {
- printf("%02X:%02X:%02X:%02X:%02X:%02X | Filter | %2d | %s | ---- | - | --- | -----------------\n",
- descriptor->macAddress[0],
- descriptor->macAddress[1],
- descriptor->macAddress[2],
- descriptor->macAddress[3],
- descriptor->macAddress[4],
- descriptor->macAddress[5],
- descriptor->recordData.filteringData.age,
- descriptor->recordData.filteringData.staticEntry ? "static " : "dynamic");
- }
- else if (descriptor->type == IX_ETH_DB_WIFI_RECORD)
- {
- if (descriptor->recordData.wifiData.type == IX_ETH_DB_WIFI_AP_TO_AP)
- {
- /* gateway address present */
- printf("%02X:%02X:%02X:%02X:%02X:%02X | WiFi | -- | AP=>AP | ---- | - | --- | %02X:%02X:%02X:%02X:%02X:%02X\n",
- descriptor->macAddress[0],
- descriptor->macAddress[1],
- descriptor->macAddress[2],
- descriptor->macAddress[3],
- descriptor->macAddress[4],
- descriptor->macAddress[5],
- descriptor->recordData.wifiData.gwMacAddress[0],
- descriptor->recordData.wifiData.gwMacAddress[1],
- descriptor->recordData.wifiData.gwMacAddress[2],
- descriptor->recordData.wifiData.gwMacAddress[3],
- descriptor->recordData.wifiData.gwMacAddress[4],
- descriptor->recordData.wifiData.gwMacAddress[5]);
- }
- else
- {
- /* no gateway */
- printf("%02X:%02X:%02X:%02X:%02X:%02X | WiFi | -- | AP=>ST | ---- | - | --- | -- no gateway -- \n",
- descriptor->macAddress[0],
- descriptor->macAddress[1],
- descriptor->macAddress[2],
- descriptor->macAddress[3],
- descriptor->macAddress[4],
- descriptor->macAddress[5]);
- }
- }
- else if (descriptor->type == IX_ETH_DB_FIREWALL_RECORD)
- {
- printf("%02X:%02X:%02X:%02X:%02X:%02X | FW | -- | ------- | ---- | - | --- | -----------------\n",
- descriptor->macAddress[0],
- descriptor->macAddress[1],
- descriptor->macAddress[2],
- descriptor->macAddress[3],
- descriptor->macAddress[4],
- descriptor->macAddress[5]);
- }
- }
- else
- {
- printf("invalid record filter\n");
- }
-}
-
-/**
- * @brief displays the status, records and configuration information of a port
- *
- * @param portID ID of the port
- * @param recordFilter record filter to display
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBPortInfoShow(IxEthDBPortId portID, IxEthDBRecordType recordFilter)
-{
- PortInfo *portInfo = &ixEthDBPortInfo[portID];
- UINT32 recordCount = 0;
- HashIterator iterator;
- IxEthDBStatus local_result;
-
- /* display port status */
- printf("== Port ID %d ==\n", portID);
-
- /* display capabilities */
- printf("- Capabilities: ");
-
- if ((portInfo->featureCapability & IX_ETH_DB_LEARNING) != 0)
- {
- printf("Learning (%s) ", ((portInfo->featureStatus & IX_ETH_DB_LEARNING) != 0) ? "on" : "off");
- }
-
- if ((portInfo->featureCapability & IX_ETH_DB_VLAN_QOS) != 0)
- {
- printf("VLAN/QoS (%s) ", ((portInfo->featureStatus & IX_ETH_DB_VLAN_QOS) != 0) ? "on" : "off");
- }
-
- if ((portInfo->featureCapability & IX_ETH_DB_FIREWALL) != 0)
- {
- printf("Firewall (%s) ", ((portInfo->featureStatus & IX_ETH_DB_FIREWALL) != 0) ? "on" : "off");
- }
-
- if ((portInfo->featureCapability & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0)
- {
- printf("WiFi (%s) ", ((portInfo->featureStatus & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0) ? "on" : "off");
- }
-
- if ((portInfo->featureCapability & IX_ETH_DB_SPANNING_TREE_PROTOCOL) != 0)
- {
- printf("STP (%s) ", ((portInfo->featureStatus & IX_ETH_DB_SPANNING_TREE_PROTOCOL) != 0) ? "on" : "off");
- }
-
- printf("\n");
-
- /* dependency map */
- ixEthDBDependencyPortMapShow(portID, portInfo->dependencyPortMap);
-
- /* NPE dynamic updates */
- if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
- {
- printf(" - NPE dynamic update is %s\n", portInfo->updateMethod.updateEnabled ? "enabled" : "disabled");
- }
- else
- {
- printf(" - dynamic update disabled (not an NPE)\n");
- }
-
- if ((portInfo->featureCapability & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0)
- {
- if ((portInfo->featureStatus & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0)
- {
- /* WiFi header conversion */
- if ((portInfo->frameControlDurationID
- + portInfo->bbsid[0]
- + portInfo->bbsid[1]
- + portInfo->bbsid[2]
- + portInfo->bbsid[3]
- + portInfo->bbsid[4]
- + portInfo->bbsid[5]) == 0)
- {
- printf(" - WiFi header conversion not configured\n");
- }
- else
- {
- printf(" - WiFi header conversion: BBSID [%02X:%02X:%02X:%02X:%02X:%02X], Frame Control 0x%X, Duration/ID 0x%X\n",
- portInfo->bbsid[0],
- portInfo->bbsid[1],
- portInfo->bbsid[2],
- portInfo->bbsid[3],
- portInfo->bbsid[4],
- portInfo->bbsid[5],
- portInfo->frameControlDurationID >> 16,
- portInfo->frameControlDurationID & 0xFFFF);
- }
- }
- else
- {
- printf(" - WiFi header conversion not enabled\n");
- }
- }
-
- /* Firewall */
- if ((portInfo->featureCapability & IX_ETH_DB_FIREWALL) != 0)
- {
- if ((portInfo->featureStatus & IX_ETH_DB_FIREWALL) != 0)
- {
- printf(" - Firewall is in %s-list mode\n", portInfo->firewallMode == IX_ETH_DB_FIREWALL_BLACK_LIST ? "black" : "white");
- printf(" - Invalid source MAC address filtering is %s\n", portInfo->srcAddressFilterEnabled ? "enabled" : "disabled");
- }
- else
- {
- printf(" - Firewall not enabled\n");
- }
- }
-
- /* browse database if asked to display records */
- if (recordFilter != IX_ETH_DB_NO_RECORD_TYPE)
- {
- printf("\n");
- ixEthDBHeaderShow(recordFilter);
-
- BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator));
-
- while (IS_ITERATOR_VALID(&iterator))
- {
- MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data;
-
- if (descriptor->portID == portID && (descriptor->type & recordFilter) != 0)
- {
- recordCount++;
-
- /* display entry */
- ixEthDBRecordShow(descriptor, recordFilter);
- }
-
- /* move to the next record */
- BUSY_RETRY_WITH_RESULT(ixEthDBIncrementHashIterator(&dbHashtable, &iterator), local_result);
-
- /* debug */
- if (local_result == IX_ETH_DB_BUSY)
- {
- printf("EthDB (API): Error, database browser failed (no access), giving up\n");
- }
- }
-
- printf("\nFound %d records\n\n", recordCount);
- }
-}
-
-/**
- * @brief displays a record header
- *
- * @param recordFilter record type filter
- *
- * This function displays a record header, depending on
- * the given record type filter. It is useful when used
- * in conjunction with ixEthDBRecordShow which will display
- * record fields formatted for the header, provided the same
- * record filter is used.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or IX_ETH_DB_INVALID_ARG if the recordFilter
- * parameter is invalid or not supported
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBHeaderShow(IxEthDBRecordType recordFilter)
-{
- if (recordFilter == IX_ETH_DB_FILTERING_VLAN_RECORD
- || recordFilter == (IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD))
- {
- /* display VLAN record header */
- printf(" MAC address | Age | Type | VLAN ID | CFI | QoS class \n");
- printf("___________________________________________________________________\n");
- }
- else if (recordFilter == IX_ETH_DB_FILTERING_RECORD)
- {
- /* display filtering record header */
- printf(" MAC address | Age | Type \n");
- printf("_______________________________________\n");
- }
- else if (recordFilter == IX_ETH_DB_WIFI_RECORD)
- {
- /* display WiFi record header */
- printf(" MAC address | GW MAC address \n");
- printf("_______________________________________\n");
- }
- else if (recordFilter == IX_ETH_DB_FIREWALL_RECORD)
- {
- /* display Firewall record header */
- printf(" MAC address \n");
- printf("__________________\n");
- }
- else if (recordFilter == IX_ETH_DB_ALL_RECORD_TYPES)
- {
- /* display composite record header */
- printf(" MAC address | Record | Age| Type | VLAN |CFI| QoS | GW MAC address \n");
- printf("_______________________________________________________________________________\n");
- }
- else
- {
- return IX_ETH_DB_INVALID_ARG;
- }
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief displays database information (records and port information)
- *
- * @param portID ID of the port to display (or IX_ETH_DB_ALL_PORTS for all the ports)
- * @param recordFilter record filter (use IX_ETH_DB_NO_RECORD_TYPE to display only
- * port information)
- *
- * Note that this function is documented in the main component header
- * file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully or
- * an appropriate error code otherwise
- *
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringDatabaseShowRecords(IxEthDBPortId portID, IxEthDBRecordType recordFilter)
-{
- IxEthDBPortId currentPort;
- BOOL showAllPorts = (portID == IX_ETH_DB_ALL_PORTS);
-
- IX_ETH_DB_CHECK_PORT_ALL(portID);
-
- printf("\nEthernet learning/filtering database: listing %d port(s)\n\n", showAllPorts ? (UINT32) IX_ETH_DB_NUMBER_OF_PORTS : 1);
-
- currentPort = showAllPorts ? 0 : portID;
-
- while (currentPort != IX_ETH_DB_NUMBER_OF_PORTS)
- {
- /* display port info */
- ixEthDBPortInfoShow(currentPort, recordFilter);
-
- /* next port */
- currentPort = showAllPorts ? currentPort + 1 : IX_ETH_DB_NUMBER_OF_PORTS;
- }
-
- return IX_ETH_DB_SUCCESS;
-}
-
+++ /dev/null
-/**
- * @file IxEthDBSearch.c
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB_p.h"
-
-extern HashTable dbHashtable;
-
-/**
- * @brief matches two database records based on their MAC addresses
- *
- * @param untypedReference record to match against
- * @param untypedEntry record to match
- *
- * @return true if the match is successful or false otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-BOOL ixEthDBAddressRecordMatch(void *untypedReference, void *untypedEntry)
-{
- MacDescriptor *entry = (MacDescriptor *) untypedEntry;
- MacDescriptor *reference = (MacDescriptor *) untypedReference;
-
- /* check accepted record types */
- if ((entry->type & reference->type) == 0) return false;
-
- return (ixEthDBAddressCompare((UINT8 *) entry->macAddress, (UINT8 *) reference->macAddress) == 0);
-}
-
-/**
- * @brief matches two database records based on their MAC addresses
- * and VLAN IDs
- *
- * @param untypedReference record to match against
- * @param untypedEntry record to match
- *
- * @return true if the match is successful or false otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-BOOL ixEthDBVlanRecordMatch(void *untypedReference, void *untypedEntry)
-{
- MacDescriptor *entry = (MacDescriptor *) untypedEntry;
- MacDescriptor *reference = (MacDescriptor *) untypedReference;
-
- /* check accepted record types */
- if ((entry->type & reference->type) == 0) return false;
-
- return (IX_ETH_DB_GET_VLAN_ID(entry->recordData.filteringVlanData.ieee802_1qTag) ==
- IX_ETH_DB_GET_VLAN_ID(reference->recordData.filteringVlanData.ieee802_1qTag)) &&
- (ixEthDBAddressCompare(entry->macAddress, reference->macAddress) == 0);
-}
-
-/**
- * @brief matches two database records based on their MAC addresses
- * and port IDs
- *
- * @param untypedReference record to match against
- * @param untypedEntry record to match
- *
- * @return true if the match is successful or false otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-BOOL ixEthDBPortRecordMatch(void *untypedReference, void *untypedEntry)
-{
- MacDescriptor *entry = (MacDescriptor *) untypedEntry;
- MacDescriptor *reference = (MacDescriptor *) untypedReference;
-
- /* check accepted record types */
- if ((entry->type & reference->type) == 0) return false;
-
- return (entry->portID == reference->portID) &&
- (ixEthDBAddressCompare(entry->macAddress, reference->macAddress) == 0);
-}
-
-/**
- * @brief dummy matching function, registered for safety
- *
- * @param reference record to match against (unused)
- * @param entry record to match (unused)
- *
- * This function is registered in the matching functions
- * array on invalid types. Calling it will display an
- * error message, indicating an error in the component logic.
- *
- * @return false
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-BOOL ixEthDBNullMatch(void *reference, void *entry)
-{
- /* display an error message */
-
- ixOsalLog(IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT, "DB: (Search) The NullMatch function was called, wrong key type?\n", 0, 0, 0, 0, 0, 0);
-
-
- return false;
-}
-
-/**
- * @brief registers hash matching methods
- *
- * @param matchFunctions table of match functions to be populated
- *
- * This function registers the available record matching functions
- * by indexing them on record types into the given function array.
- *
- * Note that it is compulsory to call this in ixEthDBInit(),
- * otherwise hashtable searching and removal will not work
- *
- * @return number of registered functions
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-UINT32 ixEthDBMatchMethodsRegister(MatchFunction *matchFunctions)
-{
- UINT32 i;
-
- /* safety first */
- for ( i = 0 ; i < IX_ETH_DB_MAX_KEY_INDEX + 1 ; i++)
- {
- matchFunctions[i] = ixEthDBNullMatch;
- }
-
- /* register MAC search method */
- matchFunctions[IX_ETH_DB_MAC_KEY] = ixEthDBAddressRecordMatch;
-
- /* register MAC/PortID search method */
- matchFunctions[IX_ETH_DB_MAC_PORT_KEY] = ixEthDBPortRecordMatch;
-
- /* register MAC/VLAN ID search method */
- matchFunctions[IX_ETH_DB_MAC_VLAN_KEY] = ixEthDBVlanRecordMatch;
-
- return 3; /* three methods */
-}
-
-/**
- * @brief search a record in the Ethernet datbase
- *
- * @param macAddress MAC address to perform the search on
- * @param typeFilter type of records to consider for matching
- *
- * @warning if searching is successful an implicit write lock
- * to the search result is granted, therefore unlock the
- * entry using @ref ixEthDBReleaseHashNode() as soon as possible.
- *
- * @see ixEthDBReleaseHashNode()
- *
- * @return the search result, or NULL if a record with the given
- * MAC address was not found
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-HashNode* ixEthDBSearch(IxEthDBMacAddr *macAddress, IxEthDBRecordType typeFilter)
-{
- HashNode *searchResult = NULL;
- MacDescriptor reference;
-
- TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER;
-
- if (macAddress == NULL)
- {
- return NULL;
- }
-
- /* fill search fields */
- memcpy(reference.macAddress, macAddress, sizeof (IxEthDBMacAddr));
-
- /* set acceptable record types */
- reference.type = typeFilter;
-
- BUSY_RETRY(ixEthDBSearchHashEntry(&dbHashtable, IX_ETH_DB_MAC_KEY, &reference, &searchResult));
-
- return searchResult;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPeek(IxEthDBMacAddr *macAddress, IxEthDBRecordType typeFilter)
-{
- MacDescriptor reference;
- IxEthDBStatus result;
-
- TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER;
-
- if (macAddress == NULL)
- {
- return IX_ETH_DB_INVALID_ARG;
- }
-
- /* fill search fields */
- memcpy(reference.macAddress, macAddress, sizeof (IxEthDBMacAddr));
-
- /* set acceptable record types */
- reference.type = typeFilter;
-
- result = ixEthDBPeekHashEntry(&dbHashtable, IX_ETH_DB_MAC_KEY, &reference);
-
- return result;
-}
-
-/**
- * @brief search a record in the Ethernet datbase
- *
- * @param macAddress MAC address to perform the search on
- * @param portID port ID to perform the search on
- * @param typeFilter type of records to consider for matching
- *
- * @warning if searching is successful an implicit write lock
- * to the search result is granted, therefore unlock the
- * entry using @ref ixEthDBReleaseHashNode() as soon as possible.
- *
- * @see ixEthDBReleaseHashNode()
- *
- * @return the search result, or NULL if a record with the given
- * MAC address/port ID combination was not found
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-HashNode* ixEthDBPortSearch(IxEthDBMacAddr *macAddress, IxEthDBPortId portID, IxEthDBRecordType typeFilter)
-{
- HashNode *searchResult = NULL;
- MacDescriptor reference;
-
- if (macAddress == NULL)
- {
- return NULL;
- }
-
- /* fill search fields */
- memcpy(reference.macAddress, macAddress, sizeof (IxEthDBMacAddr));
- reference.portID = portID;
-
- /* set acceptable record types */
- reference.type = typeFilter;
-
- BUSY_RETRY(ixEthDBSearchHashEntry(&dbHashtable, IX_ETH_DB_MAC_PORT_KEY, &reference, &searchResult));
-
- return searchResult;
-}
-
-/**
- * @brief search a record in the Ethernet datbase
- *
- * @param macAddress MAC address to perform the search on
- * @param vlanID VLAN ID to perform the search on
- * @param typeFilter type of records to consider for matching
- *
- * @warning if searching is successful an implicit write lock
- * to the search result is granted, therefore unlock the
- * entry using @ref ixEthDBReleaseHashNode() as soon as possible.
- *
- * @see ixEthDBReleaseHashNode()
- *
- * @return the search result, or NULL if a record with the given
- * MAC address/VLAN ID combination was not found
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-HashNode* ixEthDBVlanSearch(IxEthDBMacAddr *macAddress, IxEthDBVlanId vlanID, IxEthDBRecordType typeFilter)
-{
- HashNode *searchResult = NULL;
- MacDescriptor reference;
-
- if (macAddress == NULL)
- {
- return NULL;
- }
-
- /* fill search fields */
- memcpy(reference.macAddress, macAddress, sizeof (IxEthDBMacAddr));
- reference.recordData.filteringVlanData.ieee802_1qTag =
- IX_ETH_DB_SET_VLAN_ID(reference.recordData.filteringVlanData.ieee802_1qTag, vlanID);
-
- /* set acceptable record types */
- reference.type = typeFilter;
-
- BUSY_RETRY(ixEthDBSearchHashEntry(&dbHashtable, IX_ETH_DB_MAC_VLAN_KEY, &reference, &searchResult));
-
- return searchResult;
-}
+++ /dev/null
-/**
- * @file IxEthDBSpanningTree.c
- *
- * @brief Implementation of the STP API
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#include "IxEthDB_p.h"
-
-/**
- * @brief sets the STP blocking state of a port
- *
- * @param portID ID of the port
- * @param blocked true to block the port or false to unblock it
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBSpanningTreeBlockingStateSet(IxEthDBPortId portID, BOOL blocked)
-{
- IxNpeMhMessage message;
- IX_STATUS result;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_SPANNING_TREE_PROTOCOL);
-
- ixEthDBPortInfo[portID].stpBlocked = blocked;
-
- FILL_SETBLOCKINGSTATE_MSG(message, portID, blocked);
-
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- return result;
-}
-
-/**
- * @brief retrieves the STP blocking state of a port
- *
- * @param portID ID of the port
- * @param blocked address to write the blocked status into
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBSpanningTreeBlockingStateGet(IxEthDBPortId portID, BOOL *blocked)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_SPANNING_TREE_PROTOCOL);
-
- IX_ETH_DB_CHECK_REFERENCE(blocked);
-
- *blocked = ixEthDBPortInfo[portID].stpBlocked;
-
- return IX_ETH_DB_SUCCESS;
-}
+++ /dev/null
-/**
- * @file ethUtil.c
- *
- * @brief Utility functions
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#include "IxFeatureCtrl.h"
-#include "IxEthDB_p.h"
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBSingleEthNpeCheck(IxEthDBPortId portID)
-{
- /* If not IXP42X A0 stepping, proceed to check for existence of coprocessors */
- if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
- (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
- || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
- {
- if ((portID == 0) &&
- (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) ==
- IX_FEATURE_CTRL_COMPONENT_DISABLED))
- {
- return IX_ETH_DB_FAIL;
- }
-
- if ((portID == 1) &&
- (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) ==
- IX_FEATURE_CTRL_COMPONENT_DISABLED))
- {
- return IX_ETH_DB_FAIL;
- }
-
- if ((portID == 2) &&
- (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA_ETH) ==
- IX_FEATURE_CTRL_COMPONENT_DISABLED))
- {
- return IX_ETH_DB_FAIL;
- }
- }
-
- return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-BOOL ixEthDBCheckSingleBitValue(UINT32 value)
-{
-#if (CPU != SIMSPARCSOLARIS) && !defined (__wince)
- UINT32 shift;
-
- /* use the count-leading-zeros XScale instruction */
- __asm__ ("clz %0, %1\n" : "=r" (shift) : "r" (value));
-
- return ((value << shift) == 0x80000000UL);
-
-#else
-
- while (value != 0)
- {
- if (value == 1) return true;
- else if ((value & 1) == 1) return false;
-
- value >>= 1;
- }
-
- return false;
-
-#endif
-}
-
-const char *mac2string(const unsigned char *mac)
-{
- static char str[19];
-
- if (mac == NULL)
- {
- return NULL;
- }
-
- sprintf(str, "%02X:%02X:%02X:%02X:%02X:%02X", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
-
- return str;
-}
+++ /dev/null
-/**
- * @file IxEthDBVlan.c
- *
- * @brief Implementation of the VLAN API
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB.h"
-#include "IxEthDB_p.h"
-
-/* forward prototypes */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBUpdateTrafficClass(IxEthDBPortId portID, UINT32 classIndex);
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBVlanTableGet(IxEthDBPortId portID, IxEthDBVlanSet portVlanTable, IxEthDBVlanSet vlanSet);
-
-/* contants used by various functions as "action" parameter */
-#define ADD_VLAN (0x1)
-#define REMOVE_VLAN (0x2)
-
-/**
- * @brief adds or removes a VLAN from a VLAN set
- *
- * @param vlanID VLAN ID to add or remove
- * @param table VLAN set to add into or remove from
- * @param action ADD_VLAN or REMOVE_VLAN
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBLocalVlanMembershipChange(UINT32 vlanID, IxEthDBVlanSet table, UINT32 action)
-{
- UINT32 setOffset;
-
- /* add/remove VID to membership table */
- setOffset = VLAN_SET_OFFSET(vlanID); /* we need 9 bits to index the 512 byte membership array */
-
- if (action == ADD_VLAN)
- {
- table[setOffset] |= 1 << VLAN_SET_MASK(vlanID);
- }
- else if (action == REMOVE_VLAN)
- {
- table[setOffset] &= ~(1 << VLAN_SET_MASK(vlanID));
- }
-}
-
-/**
- * @brief updates a set of 8 VLANs in an NPE
- *
- * @param portID ID of the port
- * @param setOffset offset of the 8 VLANs
- *
- * This function updates the VLAN membership table
- * and Transmit Tagging Info table for 8 consecutive
- * VLAN IDs indexed by setOffset.
- *
- * For example, a setOffset of 0 indexes VLAN IDs 0
- * through 7, 1 indexes VLAN IDs 8 through 9 etc.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBVlanTableEntryUpdate(IxEthDBPortId portID, UINT32 setOffset)
-{
- PortInfo *portInfo = &ixEthDBPortInfo[portID];
- IxNpeMhMessage message;
- IX_STATUS result;
-
- FILL_SETPORTVLANTABLEENTRY_MSG(message, IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID),
- 2 * setOffset,
- portInfo->vlanMembership[setOffset],
- portInfo->transmitTaggingInfo[setOffset]);
-
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- return result;
-}
-
-/**
- * @brief updates a VLAN range in an NPE
- *
- * @param portID ID of the port
- *
- * This function is similar to @ref ixEthDBVlanTableEntryUpdate
- * except that it can update more than one VLAN set (up to
- * the entire VLAN membership and TTI tables if the offset is 0
- * and length is sizeof (IxEthDBVlanSet) (512 bytes).
- *
- * Updating the NPE via this method is slower as it requires
- * a memory copy from SDRAM, hence it is recommended that the
- * ixEthDBVlanTableEntryUpdate function is used where possible.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBVlanTableRangeUpdate(IxEthDBPortId portID)
-{
- PortInfo *portInfo = &ixEthDBPortInfo[portID];
- UINT8 *vlanUpdateZone = (UINT8 *) portInfo->updateMethod.vlanUpdateZone;
- IxNpeMhMessage message;
- UINT32 setIndex;
- IX_STATUS result;
-
- /* copy membership info and transmit tagging into into exchange area */
- for (setIndex = 0 ; setIndex < sizeof (portInfo->vlanMembership) ; setIndex++)
- {
- /* membership and TTI data are interleaved */
- vlanUpdateZone[setIndex * 2] = portInfo->vlanMembership[setIndex];
- vlanUpdateZone[setIndex * 2 + 1] = portInfo->transmitTaggingInfo[setIndex];
- }
-
- IX_OSAL_CACHE_FLUSH(vlanUpdateZone, FULL_VLAN_BYTE_SIZE);
-
- /* build NPE message */
- FILL_SETPORTVLANTABLERANGE_MSG(message, IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID), 0, 0,
- IX_OSAL_MMU_VIRT_TO_PHYS(vlanUpdateZone));
-
- /* send message */
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- return result;
-}
-
-/**
- * @brief adds or removes a VLAN from a port's VLAN membership table
- * or Transmit Tagging Information table
- *
- * @param portID ID of the port
- * @param vlanID VLAN ID to add or remove
- * @param table to add or remove from
- * @param action ADD_VLAN or REMOVE_VLAN
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBPortVlanMembershipChange(IxEthDBPortId portID, IxEthDBVlanId vlanID, IxEthDBVlanSet table, UINT32 action)
-{
- /* change VLAN in local membership table */
- ixEthDBLocalVlanMembershipChange(vlanID, table, action);
-
- /* send updated entry to NPE */
- return ixEthDBVlanTableEntryUpdate(portID, VLAN_SET_OFFSET(vlanID));
-}
-
-/**
- * @brief sets the default port VLAN tag (the lower 3 bytes are the PVID)
- *
- * @param portID ID of the port
- * @param vlanTag port VLAN tag (802.1Q tag)
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanTagSet(IxEthDBPortId portID, IxEthDBVlanTag vlanTag)
-{
- IxNpeMhMessage message;
- IX_STATUS result;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_VLAN_TAG(vlanTag);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- /* add VLAN ID to local membership table */
- ixEthDBPortVlanMembershipChange(portID,
- vlanTag & IX_ETH_DB_802_1Q_VLAN_MASK,
- ixEthDBPortInfo[portID].vlanMembership,
- ADD_VLAN);
-
- /* set tag in portInfo */
- ixEthDBPortInfo[portID].vlanTag = vlanTag;
-
- /* build VLAN_SetDefaultRxVID message */
- FILL_SETDEFAULTRXVID_MSG(message,
- IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID),
- IX_IEEE802_1Q_VLAN_TPID,
- vlanTag);
-
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- return result;
-}
-
-/**
- * @brief retrieves the default port VLAN tag (the lower 3 bytes are the PVID)
- *
- * @param portID ID of the port
- * @param vlanTag address to write the port VLAN tag (802.1Q tag) into
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanTagGet(IxEthDBPortId portID, IxEthDBVlanTag *vlanTag)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- IX_ETH_DB_CHECK_REFERENCE(vlanTag);
-
- *vlanTag = ixEthDBPortInfo[portID].vlanTag;
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief sets the VLAN tag (the lower 3 bytes are the PVID) of a
- * database filtering record
- *
- * @param portID ID of the port
- * @param vlanTag VLAN tag (802.1Q tag)
- *
- * Important: filtering records are automatically converted to
- * IX_ETH_DB_FILTERING_VLAN record when added a VLAN tag.
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBVlanTagSet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag vlanTag)
-{
- HashNode *searchResult;
- MacDescriptor *descriptor;
-
- IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
- IX_ETH_DB_CHECK_VLAN_TAG(vlanTag);
-
- searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS);
-
- if (searchResult == NULL)
- {
- return IX_ETH_DB_NO_SUCH_ADDR;
- }
-
- descriptor = (MacDescriptor *) searchResult->data;
-
- /* set record type to VLAN if not already set */
- descriptor->type = IX_ETH_DB_FILTERING_VLAN_RECORD;
-
- /* add vlan tag */
- descriptor->recordData.filteringVlanData.ieee802_1qTag = vlanTag;
-
- /* transaction completed */
- ixEthDBReleaseHashNode(searchResult);
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief retrieves the VLAN tag (the lower 3 bytes are the PVID) from a
- * database VLAN filtering record
- *
- * @param portID ID of the port
- * @param vlanTag address to write the VLAN tag (802.1Q tag) into
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBVlanTagGet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag *vlanTag)
-{
- HashNode *searchResult;
- MacDescriptor *descriptor;
-
- IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
- IX_ETH_DB_CHECK_REFERENCE(vlanTag);
-
- searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_FILTERING_VLAN_RECORD);
-
- if (searchResult == NULL)
- {
- return IX_ETH_DB_NO_SUCH_ADDR;
- }
-
- descriptor = (MacDescriptor *) searchResult->data;
-
- /* get vlan tag */
- *vlanTag = descriptor->recordData.filteringVlanData.ieee802_1qTag;
-
- /* transaction completed */
- ixEthDBReleaseHashNode(searchResult);
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief adds a VLAN to a port's VLAN membership table
- *
- * @param portID ID of the port
- * @param vlanID VLAN ID to add
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanMembershipAdd(IxEthDBPortId portID, IxEthDBVlanId vlanID)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_VLAN_ID(vlanID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- return ixEthDBPortVlanMembershipChange(portID, vlanID, ixEthDBPortInfo[portID].vlanMembership, ADD_VLAN);
-}
-
-/**
- * @brief removes a VLAN from a port's VLAN membership table
- *
- * @param portID ID of the port
- * @param vlanID VLAN ID to remove
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanMembershipRemove(IxEthDBPortId portID, IxEthDBVlanId vlanID)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- IX_ETH_DB_CHECK_VLAN_ID(vlanID);
-
- /* for safety isolate only the VLAN ID in the tag (the lower 12 bits) */
- vlanID = vlanID & IX_ETH_DB_802_1Q_VLAN_MASK;
-
- /* check we're not asked to remove the default port VID */
- if (vlanID == IX_ETH_DB_GET_VLAN_ID(ixEthDBPortInfo[portID].vlanTag))
- {
- return IX_ETH_DB_NO_PERMISSION;
- }
-
- return ixEthDBPortVlanMembershipChange(portID, vlanID, ixEthDBPortInfo[portID].vlanMembership, REMOVE_VLAN);
-}
-
-/**
- * @brief adds or removes a VLAN range from a port's
- * VLAN membership table or TTI table
- *
- * @param portID ID of the port
- * @param vlanIDMin start of the VLAN range
- * @param vlanIDMax end of the VLAN range
- * @param table VLAN set to add or remove from
- * @param action ADD_VLAN or REMOVE_VLAN
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBPortVlanMembershipRangeChange(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax, IxEthDBVlanSet table, UINT32 action)
-{
- UINT32 setOffsetMin, setOffsetMax;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- IX_ETH_DB_CHECK_VLAN_ID(vlanIDMin);
-
- IX_ETH_DB_CHECK_VLAN_ID(vlanIDMax);
-
- /* for safety isolate only the VLAN ID in the tags (the lower 12 bits) */
- vlanIDMin = vlanIDMin & IX_ETH_DB_802_1Q_VLAN_MASK;
- vlanIDMax = vlanIDMax & IX_ETH_DB_802_1Q_VLAN_MASK;
-
- /* is this a range? */
- if (vlanIDMax < vlanIDMin)
- {
- return IX_ETH_DB_INVALID_VLAN;
- }
-
- /* check that we're not specifically asked to remove the default port VID */
- if (action == REMOVE_VLAN && vlanIDMax == vlanIDMin && IX_ETH_DB_GET_VLAN_ID(ixEthDBPortInfo[portID].vlanTag) == vlanIDMin)
- {
- return IX_ETH_DB_NO_PERMISSION;
- }
-
- /* compute set offsets */
- setOffsetMin = VLAN_SET_OFFSET(vlanIDMin);
- setOffsetMax = VLAN_SET_OFFSET(vlanIDMax);
-
- /* change VLAN range */
- for (; vlanIDMin <= vlanIDMax ; vlanIDMin++)
- {
- /* change vlan in local membership table */
- ixEthDBLocalVlanMembershipChange(vlanIDMin, table, action);
- }
-
- /* if the range is within one set (max 8 VLANs in one table byte) we can just update that entry in the NPE */
- if (setOffsetMin == setOffsetMax)
- {
- /* send updated entry to NPE */
- return ixEthDBVlanTableEntryUpdate(portID, setOffsetMin);
- }
- else
- {
- /* update a zone of the membership/transmit tag info table */
- return ixEthDBVlanTableRangeUpdate(portID);
- }
-}
-
-/**
- * @brief adds a VLAN range to a port's VLAN membership table
- *
- * @param portID ID of the port
- * @param vlanIDMin start of the VLAN range
- * @param vlanIDMax end of the VLAN range
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanMembershipRangeAdd(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- return ixEthDBPortVlanMembershipRangeChange(portID, vlanIDMin, vlanIDMax, ixEthDBPortInfo[portID].vlanMembership, ADD_VLAN);
-}
-
-/**
- * @brief removes a VLAN range from a port's VLAN membership table
- *
- * @param portID ID of the port
- * @param vlanIDMin start of the VLAN range
- * @param vlanIDMax end of the VLAN range
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanMembershipRangeRemove(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- return ixEthDBPortVlanMembershipRangeChange(portID, vlanIDMin, vlanIDMax, ixEthDBPortInfo[portID].vlanMembership, REMOVE_VLAN);
-}
-
-/**
- * @brief sets a port's VLAN membership table or TTI table and
- * updates the NPE VLAN configuration
- *
- * @param portID ID of the port
- * @param portVlanTable port VLAN table to set
- * @param vlanSet new set contents
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanTableSet(IxEthDBPortId portID, IxEthDBVlanSet portVlanTable, IxEthDBVlanSet vlanSet)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- IX_ETH_DB_CHECK_REFERENCE(vlanSet);
-
- memcpy(portVlanTable, vlanSet, sizeof (IxEthDBVlanSet));
-
- return ixEthDBVlanTableRangeUpdate(portID);
-}
-
-/**
- * @brief retireves a port's VLAN membership table or TTI table
- *
- * @param portID ID of the port
- * @param portVlanTable port VLAN table to retrieve
- * @param vlanSet address to
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBVlanTableGet(IxEthDBPortId portID, IxEthDBVlanSet portVlanTable, IxEthDBVlanSet vlanSet)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- IX_ETH_DB_CHECK_REFERENCE(vlanSet);
-
- memcpy(vlanSet, portVlanTable, sizeof (IxEthDBVlanSet));
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief sets a port's VLAN membership table
- *
- * @param portID ID of the port
- * @param vlanSet new VLAN membership table
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanMembershipSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet)
-{
- IxEthDBVlanId vlanID;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(vlanSet);
-
- /* set the bit corresponding to the PVID just in case */
- vlanID = IX_ETH_DB_GET_VLAN_ID(ixEthDBPortInfo[portID].vlanTag);
- vlanSet[VLAN_SET_OFFSET(vlanID)] |= 1 << VLAN_SET_MASK(vlanID);
-
- return ixEthDBPortVlanTableSet(portID, ixEthDBPortInfo[portID].vlanMembership, vlanSet);
-}
-
-/**
- * @brief retrieves a port's VLAN membership table
- *
- * @param portID ID of the port
- * @param vlanSet location to store the port's VLAN membership table
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanMembershipGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- return ixEthDBVlanTableGet(portID, ixEthDBPortInfo[portID].vlanMembership, vlanSet);
-}
-
-/**
- * @brief enables or disables Egress tagging for one VLAN ID
- *
- * @param portID ID of the port
- * @param vlanID VLAN ID to enable or disable Egress tagging on
- * @param enabled true to enable and false to disable tagging
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL enabled)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_VLAN_ID(vlanID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- return ixEthDBPortVlanMembershipChange(portID, vlanID, ixEthDBPortInfo[portID].transmitTaggingInfo, enabled? ADD_VLAN : REMOVE_VLAN);
-}
-
-/**
- * @brief retrieves the Egress tagging status for one VLAN ID
- *
- * @param portID ID of the port
- * @param vlanID VLAN ID to retrieve the tagging status for
- * @param enabled location to store the tagging status
- * (true - tagging enabled, false - tagging disabled)
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL *enabled)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- IX_ETH_DB_CHECK_REFERENCE(enabled);
-
- IX_ETH_DB_CHECK_VLAN_ID(vlanID);
-
- *enabled = ((ixEthDBPortInfo[portID].transmitTaggingInfo[VLAN_SET_OFFSET(vlanID)] & (1 << VLAN_SET_MASK(vlanID))) != 0);
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief enables or disables Egress VLAN tagging for a VLAN range
- *
- * @param portID ID of the port
- * @param vlanIDMin start of VLAN range
- * @param vlanIDMax end of VLAN range
- * @param enabled true to enable or false to disable VLAN tagging
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBEgressVlanRangeTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax, BOOL enabled)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- return ixEthDBPortVlanMembershipRangeChange(portID, vlanIDMin, vlanIDMax, ixEthDBPortInfo[portID].transmitTaggingInfo, enabled? ADD_VLAN : REMOVE_VLAN);
-}
-
-/**
- * @brief sets the Egress VLAN tagging table (the Transmit Tagging
- * Information table)
- *
- * @param portID ID of the port
- * @param vlanSet new TTI table
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBEgressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet)
-{
- IxEthDBVlanId vlanID;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(vlanSet);
-
- /* set the PVID bit just in case */
- vlanID = IX_ETH_DB_GET_VLAN_ID(ixEthDBPortInfo[portID].vlanTag);
- vlanSet[VLAN_SET_OFFSET(vlanID)] |= 1 << VLAN_SET_MASK(vlanID);
-
- return ixEthDBPortVlanTableSet(portID, ixEthDBPortInfo[portID].transmitTaggingInfo, vlanSet);
-}
-
-/**
- * @brief retrieves the Egress VLAN tagging table (the Transmit
- * Tagging Information table)
- *
- * @param portID ID of the port
- * @param vlanSet location to store the port's TTI table
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBEgressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- return ixEthDBVlanTableGet(portID, ixEthDBPortInfo[portID].transmitTaggingInfo, vlanSet);
-}
-
-/**
- * @brief sends the NPE the updated frame filter and default
- * Ingress tagging
- *
- * @param portID ID of the port
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBIngressVlanModeUpdate(IxEthDBPortId portID)
-{
- PortInfo *portInfo = &ixEthDBPortInfo[portID];
- IxNpeMhMessage message;
- IX_STATUS result;
-
- FILL_SETRXTAGMODE_MSG(message, portID, portInfo->npeFrameFilter, portInfo->npeTaggingAction);
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- return result;
-}
-
-/**
- * @brief sets the default Ingress tagging behavior
- *
- * @param portID ID of the port
- * @param taggingAction default tagging behavior
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBIngressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBTaggingAction taggingAction)
-{
- PortInfo *portInfo;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- portInfo = &ixEthDBPortInfo[portID];
-
- if (taggingAction == IX_ETH_DB_PASS_THROUGH)
- {
- portInfo->npeTaggingAction = 0x00;
- }
- else if (taggingAction == IX_ETH_DB_ADD_TAG)
- {
- portInfo->npeTaggingAction = 0x02;
- }
- else if (taggingAction == IX_ETH_DB_REMOVE_TAG)
- {
- portInfo->npeTaggingAction = 0x01;
- }
- else
- {
- return IX_ETH_DB_INVALID_ARG;
- }
-
- portInfo->taggingAction = taggingAction;
-
- return ixEthDBIngressVlanModeUpdate(portID);
-}
-
-/**
- * @brief retrieves the default Ingress tagging behavior of a port
- *
- * @param portID ID of the port
- * @param taggingAction location to save the default tagging behavior
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBIngressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBTaggingAction *taggingAction)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- IX_ETH_DB_CHECK_REFERENCE(taggingAction);
-
- *taggingAction = ixEthDBPortInfo[portID].taggingAction;
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief sets the Ingress acceptable frame type filter
- *
- * @param portID ID of the port
- * @param frameFilter acceptable frame type filter
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBAcceptableFrameTypeSet(IxEthDBPortId portID, IxEthDBFrameFilter frameFilter)
-{
- PortInfo *portInfo;
- IxEthDBStatus result = IX_ETH_DB_SUCCESS;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- /* check parameter range
- the ORed value of the valid values is 0x7
- a value having extra bits is invalid */
- if ((frameFilter | 0x7) != 0x7 || frameFilter == 0)
- {
- return IX_ETH_DB_INVALID_ARG;
- }
-
- portInfo = &ixEthDBPortInfo[portID];
-
- portInfo->frameFilter = frameFilter;
- portInfo->npeFrameFilter = 0; /* allow all by default */
-
- /* if accepting priority tagged but not all VLAN tagged
- set the membership table to contain only VLAN ID 0
- hence remove vlans 1-4094 and add VLAN ID 0 */
- if (((frameFilter & IX_ETH_DB_PRIORITY_TAGGED_FRAMES) != 0)
- && ((frameFilter & IX_ETH_DB_VLAN_TAGGED_FRAMES) == 0))
- {
- result = ixEthDBPortVlanMembershipRangeChange(portID,
- 1, IX_ETH_DB_802_1Q_MAX_VLAN_ID, portInfo->vlanMembership, REMOVE_VLAN);
-
- if (result == IX_ETH_DB_SUCCESS)
- {
- ixEthDBLocalVlanMembershipChange(0, portInfo->vlanMembership, ADD_VLAN);
- result = ixEthDBVlanTableRangeUpdate(portID);
- }
- }
-
- /* untagged only? */
- if (frameFilter == IX_ETH_DB_UNTAGGED_FRAMES)
- {
- portInfo->npeFrameFilter = 0x01;
- }
-
- /* tagged only? */
- if ((frameFilter & IX_ETH_DB_UNTAGGED_FRAMES) == 0)
- {
- portInfo->npeFrameFilter = 0x02;
- }
-
- if (result == IX_ETH_DB_SUCCESS)
- {
- result = ixEthDBIngressVlanModeUpdate(portID);
- }
-
- return result;
-}
-
-/**
- * @brief retrieves the acceptable frame type filter for a port
- *
- * @param portID ID of the port
- * @param frameFilter location to store the frame filter
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBAcceptableFrameTypeGet(IxEthDBPortId portID, IxEthDBFrameFilter *frameFilter)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- IX_ETH_DB_CHECK_REFERENCE(frameFilter);
-
- *frameFilter = ixEthDBPortInfo[portID].frameFilter;
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief sends an NPE the updated configuration related
- * to one QoS priority (associated traffic class and AQM mapping)
- *
- * @param portID ID of the port
- * @param classIndex QoS priority (traffic class index)
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBUpdateTrafficClass(IxEthDBPortId portID, UINT32 classIndex)
-{
- IxNpeMhMessage message;
- IX_STATUS result;
-
- UINT32 trafficClass = ixEthDBPortInfo[portID].priorityTable[classIndex];
- UINT32 aqmQueue = ixEthDBPortInfo[portID].ixEthDBTrafficClassAQMAssignments[trafficClass];
-
- FILL_SETRXQOSENTRY(message, IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID), classIndex, trafficClass, aqmQueue);
-
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- return result;
-}
-
-/**
- * @brief sets the priority mapping table
- *
- * @param portID ID of the port
- * @param priorityTable new priority mapping table
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPriorityMappingTableSet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable)
-{
- UINT32 classIndex;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- IX_ETH_DB_CHECK_REFERENCE(priorityTable);
-
- for (classIndex = 0 ; classIndex < IX_IEEE802_1Q_QOS_PRIORITY_COUNT ; classIndex++)
- {
- /* check range */
- if (priorityTable[classIndex] >= ixEthDBPortInfo[portID].ixEthDBTrafficClassCount)
- {
- return IX_ETH_DB_INVALID_PRIORITY;
- }
- }
-
- /* set new traffic classes */
- for (classIndex = 0 ; classIndex < IX_IEEE802_1Q_QOS_PRIORITY_COUNT ; classIndex++)
- {
- ixEthDBPortInfo[portID].priorityTable[classIndex] = priorityTable[classIndex];
-
- if (ixEthDBUpdateTrafficClass(portID, classIndex) != IX_ETH_DB_SUCCESS)
- {
- return IX_ETH_DB_FAIL;
- }
- }
-
- return IX_ETH_DB_SUCCESS;
- }
-
-/**
- * @brief retrieves a port's priority mapping table
- *
- * @param portID ID of the port
- * @param priorityTable location to store the priority table
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPriorityMappingTableGet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- IX_ETH_DB_CHECK_REFERENCE(priorityTable);
-
- memcpy(priorityTable, ixEthDBPortInfo[portID].priorityTable, sizeof (IxEthDBPriorityTable));
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief sets one QoS priority => traffic class mapping
- *
- * @param portID ID of the port
- * @param userPriority QoS (user) priority
- * @param trafficClass associated traffic class
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPriorityMappingClassSet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority trafficClass)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- /* check ranges for userPriority and trafficClass */
- if (userPriority >= IX_IEEE802_1Q_QOS_PRIORITY_COUNT || trafficClass >= ixEthDBPortInfo[portID].ixEthDBTrafficClassCount)
- {
- return IX_ETH_DB_INVALID_PRIORITY;
- }
-
- ixEthDBPortInfo[portID].priorityTable[userPriority] = trafficClass;
-
- return ixEthDBUpdateTrafficClass(portID, userPriority);
-}
-
-/**
- * @brief retrieves one QoS priority => traffic class mapping
- *
- * @param portID ID of the port
- * @param userPriority QoS (user) priority
- * @param trafficClass location to store the associated traffic class
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPriorityMappingClassGet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority *trafficClass)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- IX_ETH_DB_CHECK_REFERENCE(trafficClass);
-
- /* check userPriority range */
- if (userPriority >= IX_IEEE802_1Q_QOS_PRIORITY_COUNT)
- {
- return IX_ETH_DB_INVALID_PRIORITY;
- }
-
- *trafficClass = ixEthDBPortInfo[portID].priorityTable[userPriority];
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief enables or disables the source port extraction
- * from the VLAN TPID field
- *
- * @param portID ID of the port
- * @param enable true to enable or false to disable
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBVlanPortExtractionEnable(IxEthDBPortId portID, BOOL enable)
-{
- IxNpeMhMessage message;
- IX_STATUS result;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- FILL_SETPORTIDEXTRACTIONMODE(message, portID, enable);
-
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- return result;
-}
+++ /dev/null
-/**
- * @file IxEthDBAPI.c
- *
- * @brief Implementation of the public API
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB_p.h"
-
-/* forward prototypes */
-IX_ETH_DB_PUBLIC
-MacTreeNode *ixEthDBGatewaySelect(MacTreeNode *stations);
-
-/**
- * @brief sets the BBSID value for the WiFi header conversion feature
- *
- * @param portID ID of the port
- * @param bbsid pointer to the 6-byte BBSID value
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiBBSIDSet(IxEthDBPortId portID, IxEthDBMacAddr *bbsid)
-{
- IxNpeMhMessage message;
- IX_STATUS result;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION);
-
- IX_ETH_DB_CHECK_REFERENCE(bbsid);
-
- memcpy(ixEthDBPortInfo[portID].bbsid, bbsid, sizeof (IxEthDBMacAddr));
-
- FILL_SETBBSID_MSG(message, portID, bbsid);
-
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- return result;
-}
-
-/**
- * @brief updates the Frame Control and Duration/ID WiFi header
- * conversion parameters in an NPE
- *
- * @param portID ID of the port
- *
- * This function will send a message to the NPE updating the
- * frame conversion parameters for 802.3 => 802.11 header conversion.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or IX_ETH_DB_FAIL otherwise
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBWiFiFrameControlDurationIDUpdate(IxEthDBPortId portID)
-{
- IxNpeMhMessage message;
- IX_STATUS result;
-
- FILL_SETFRAMECONTROLDURATIONID(message, portID, ixEthDBPortInfo[portID].frameControlDurationID);
-
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- return result;
-}
-
-/**
- * @brief sets the Duration/ID WiFi frame header conversion parameter
- *
- * @param portID ID of the port
- * @param durationID 16-bit value containing the new Duration/ID parameter
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiDurationIDSet(IxEthDBPortId portID, UINT16 durationID)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION);
-
- ixEthDBPortInfo[portID].frameControlDurationID = (ixEthDBPortInfo[portID].frameControlDurationID & 0xFFFF0000) | durationID;
-
- return ixEthDBWiFiFrameControlDurationIDUpdate(portID);
-}
-
-/**
- * @brief sets the Frame Control WiFi frame header conversion parameter
- *
- * @param portID ID of the port
- * @param durationID 16-bit value containing the new Frame Control parameter
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiFrameControlSet(IxEthDBPortId portID, UINT16 frameControl)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION);
-
- ixEthDBPortInfo[portID].frameControlDurationID = (ixEthDBPortInfo[portID].frameControlDurationID & 0xFFFF) | (frameControl << 16);
-
- return ixEthDBWiFiFrameControlDurationIDUpdate(portID);
-}
-
-/**
- * @brief removes a WiFi header conversion record
- *
- * @param portID ID of the port
- * @param macAddr MAC address of the record to remove
- *
- * Note that this function is documented in the main
- * component header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
-{
- MacDescriptor recordTemplate;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION);
-
- memcpy(recordTemplate.macAddress, macAddr, sizeof (IxEthDBMacAddr));
-
- recordTemplate.type = IX_ETH_DB_WIFI_RECORD;
- recordTemplate.portID = portID;
-
- return ixEthDBRemove(&recordTemplate, NULL);
-}
-
-/**
- * @brief adds a WiFi header conversion record
- *
- * @param portID ID of the port
- * @param macAddr MAC address of the record to add
- * @param gatewayMacAddr address of the gateway (or
- * NULL if this is a station record)
- *
- * This function adds a record of type AP_TO_AP (gateway is not NULL)
- * or AP_TO_STA (gateway is NULL) in the main database as a
- * WiFi header conversion record.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBWiFiEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr, IxEthDBMacAddr *gatewayMacAddr)
-{
- MacDescriptor recordTemplate;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION);
-
- memcpy(recordTemplate.macAddress, macAddr, sizeof (IxEthDBMacAddr));
-
- recordTemplate.type = IX_ETH_DB_WIFI_RECORD;
- recordTemplate.portID = portID;
-
- if (gatewayMacAddr != NULL)
- {
- memcpy(recordTemplate.recordData.wifiData.gwMacAddress, gatewayMacAddr, sizeof (IxEthDBMacAddr));
-
- recordTemplate.recordData.wifiData.type = IX_ETH_DB_WIFI_AP_TO_AP;
- }
- else
- {
- memset(recordTemplate.recordData.wifiData.gwMacAddress, 0, sizeof (IxEthDBMacAddr));
-
- recordTemplate.recordData.wifiData.type = IX_ETH_DB_WIFI_AP_TO_STA;
- }
-
- return ixEthDBAdd(&recordTemplate, NULL);
-}
-
-/**
- * @brief adds a WiFi header conversion record
- *
- * @param portID ID of the port
- * @param macAddr MAC address of the record to add
- * @param gatewayMacAddr address of the gateway
- *
- * This function adds a record of type AP_TO_AP
- * in the main database as a WiFi header conversion record.
- *
- * This is simply a wrapper over @ref ixEthDBWiFiEntryAdd().
- *
- * Note that this function is documented in the main
- * component header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiAccessPointEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr, IxEthDBMacAddr *gatewayMacAddr)
-{
- IX_ETH_DB_CHECK_REFERENCE(gatewayMacAddr);
-
- return ixEthDBWiFiEntryAdd(portID, macAddr, gatewayMacAddr);
-}
-
-/**
- * @brief adds a WiFi header conversion record
- *
- * @param portID ID of the port
- * @param macAddr MAC address of the record to add
- *
- * This function adds a record of type AP_TO_STA
- * in the main database as a WiFi header conversion record.
- *
- * This is simply a wrapper over @ref ixEthDBWiFiEntryAdd().
- *
- * Note that this function is documented in the main
- * component header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiStationEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
-{
- return ixEthDBWiFiEntryAdd(portID, macAddr, NULL);
-}
-
-/**
- * @brief selects a set of gateways from a tree of
- * WiFi header conversion records
- *
- * @param stations binary tree containing pointers to WiFi header
- * conversion records
- *
- * This function browses through the input binary tree, identifies
- * records of type AP_TO_AP, clones these records and appends them
- * to a vine (a single right-branch binary tree) which is returned
- * as result. A maximum of MAX_GW_SIZE entries containing gateways
- * will be cloned from the original tree.
- *
- * @return vine (linear binary tree) containing record
- * clones of AP_TO_AP type, which have a gateway field
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-MacTreeNode *ixEthDBGatewaySelect(MacTreeNode *stations)
-{
- MacTreeNodeStack *stack;
- MacTreeNode *gateways, *insertionPlace;
- UINT32 gwIndex = 1; /* skip the empty root */
-
- if (stations == NULL)
- {
- return NULL;
- }
-
- stack = ixOsalCacheDmaMalloc(sizeof (MacTreeNodeStack));
-
- if (stack == NULL)
- {
- ERROR_LOG("DB: (WiFi) failed to allocate the node stack for gateway tree linearization, out of memory?\n");
- return NULL;
- }
-
- /* initialize root node */
- gateways = insertionPlace = NULL;
-
- /* start browsing the station tree */
- NODE_STACK_INIT(stack);
-
- /* initialize stack by pushing the tree root at offset 0 */
- NODE_STACK_PUSH(stack, stations, 0);
-
- while (NODE_STACK_NONEMPTY(stack))
- {
- MacTreeNode *node;
- UINT32 offset;
-
- NODE_STACK_POP(stack, node, offset);
-
- /* we can store maximum 31 (32 total, 1 empty root) entries in the gateway tree */
- if (offset > (MAX_GW_SIZE - 1)) break;
-
- /* check if this record has a gateway address */
- if (node->descriptor != NULL && node->descriptor->recordData.wifiData.type == IX_ETH_DB_WIFI_AP_TO_AP)
- {
- /* found a record, create an insertion place */
- if (insertionPlace != NULL)
- {
- insertionPlace->right = ixEthDBAllocMacTreeNode();
- insertionPlace = insertionPlace->right;
- }
- else
- {
- gateways = ixEthDBAllocMacTreeNode();
- insertionPlace = gateways;
- }
-
- if (insertionPlace == NULL)
- {
- /* no nodes left, bail out with what we have */
- ixOsalCacheDmaFree(stack);
- return gateways;
- }
-
- /* clone the original record for the gateway tree */
- insertionPlace->descriptor = ixEthDBCloneMacDescriptor(node->descriptor);
-
- /* insert and update the offset in the original record */
- node->descriptor->recordData.wifiData.gwAddressIndex = gwIndex++;
- }
-
- /* browse the tree */
- if (node->left != NULL)
- {
- NODE_STACK_PUSH(stack, node->left, LEFT_CHILD_OFFSET(offset));
- }
-
- if (node->right != NULL)
- {
- NODE_STACK_PUSH(stack, node->right, RIGHT_CHILD_OFFSET(offset));
- }
- }
-
- ixOsalCacheDmaFree(stack);
- return gateways;
-}
-
-/**
- * @brief downloads the WiFi header conversion table to an NPE
- *
- * @param portID ID of the port
- *
- * This function prepares the WiFi header conversion tables and
- * downloads them to the specified NPE port.
- *
- * The header conversion tables consist in the main table of
- * addresses and the secondary table of gateways. AP_TO_AP records
- * from the first table contain index fields into the second table
- * for gateway selection.
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiConversionTableDownload(IxEthDBPortId portID)
-{
- IxEthDBPortMap query;
- MacTreeNode *stations = NULL, *gateways = NULL, *gateway = NULL;
- IxNpeMhMessage message;
- PortInfo *portInfo;
- IX_STATUS result;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION);
-
- portInfo = &ixEthDBPortInfo[portID];
-
- SET_DEPENDENCY_MAP(query, portID);
-
- ixEthDBUpdateLock();
-
- stations = ixEthDBQuery(NULL, query, IX_ETH_DB_WIFI_RECORD, MAX_ELT_SIZE);
- gateways = ixEthDBGatewaySelect(stations);
-
- /* clean up gw area */
- memset((void *) portInfo->updateMethod.npeGwUpdateZone, FULL_GW_BYTE_SIZE, 0);
-
- /* write all gateways */
- gateway = gateways;
-
- while (gateway != NULL)
- {
- ixEthDBNPEGatewayNodeWrite((void *) (((UINT32) portInfo->updateMethod.npeGwUpdateZone)
- + gateway->descriptor->recordData.wifiData.gwAddressIndex * ELT_ENTRY_SIZE),
- gateway);
-
- gateway = gateway->right;
- }
-
- /* free the gateway tree */
- if (gateways != NULL)
- {
- ixEthDBFreeMacTreeNode(gateways);
- }
-
- FILL_SETAPMACTABLE_MSG(message,
- IX_OSAL_MMU_VIRT_TO_PHYS(portInfo->updateMethod.npeGwUpdateZone));
-
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- if (result == IX_SUCCESS)
- {
- /* update the main tree (the stations tree) */
- portInfo->updateMethod.searchTree = stations;
-
- result = ixEthDBNPEUpdateHandler(portID, IX_ETH_DB_WIFI_RECORD);
- }
-
- ixEthDBUpdateUnlock();
-
- return result;
-}
+++ /dev/null
-/**
- * @file IxEthMii.c
- *
- * @author Intel Corporation
- * @date
- *
- * @brief MII control functions
- *
- * Design Notes:
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxOsal.h"
-
-#include "IxEthAcc.h"
-#include "IxEthMii_p.h"
-
-#ifdef __wince
-#include "IxOsPrintf.h"
-#endif
-
-/* Array to store the phy IDs of the discovered phys */
-PRIVATE UINT32 ixEthMiiPhyId[IXP425_ETH_ACC_MII_MAX_ADDR];
-
-/*********************************************************
- *
- * Scan for PHYs on the MII bus. This function returns
- * an array of booleans, one for each PHY address.
- * If a PHY is found at a particular address, the
- * corresponding entry in the array is set to true.
- *
- */
-
-PUBLIC IX_STATUS
-ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount)
-{
- UINT32 i;
- UINT16 regval, regvalId1, regvalId2;
-
- /*Search for PHYs on the MII*/
- /*Search for existant phys on the MDIO bus*/
-
- if ((phyPresent == NULL) ||
- (maxPhyCount > IXP425_ETH_ACC_MII_MAX_ADDR))
- {
- return IX_FAIL;
- }
-
- /* fill the array */
- for(i=0;
- i<IXP425_ETH_ACC_MII_MAX_ADDR;
- i++)
- {
- phyPresent[i] = false;
- }
-
- /* iterate through the PHY addresses */
- for(i=0;
- maxPhyCount > 0 && i<IXP425_ETH_ACC_MII_MAX_ADDR;
- i++)
- {
- ixEthMiiPhyId[i] = IX_ETH_MII_INVALID_PHY_ID;
- if(ixEthAccMiiReadRtn(i,
- IX_ETH_MII_CTRL_REG,
- ®val) == IX_ETH_ACC_SUCCESS)
- {
- if((regval & 0xffff) != 0xffff)
- {
- maxPhyCount--;
- /*Need to read the register twice here to flush PHY*/
- ixEthAccMiiReadRtn(i, IX_ETH_MII_PHY_ID1_REG, ®valId1);
- ixEthAccMiiReadRtn(i, IX_ETH_MII_PHY_ID1_REG, ®valId1);
- ixEthAccMiiReadRtn(i, IX_ETH_MII_PHY_ID2_REG, ®valId2);
- ixEthMiiPhyId[i] = (regvalId1 << IX_ETH_MII_REG_SHL) | regvalId2;
- if ((ixEthMiiPhyId[i] == IX_ETH_MII_KS8995_PHY_ID)
- || (ixEthMiiPhyId[i] == IX_ETH_MII_LXT971_PHY_ID)
- || (ixEthMiiPhyId[i] == IX_ETH_MII_LXT972_PHY_ID)
- || (ixEthMiiPhyId[i] == IX_ETH_MII_LXT973_PHY_ID)
- || (ixEthMiiPhyId[i] == IX_ETH_MII_LXT973A3_PHY_ID)
- || (ixEthMiiPhyId[i] == IX_ETH_MII_LXT9785_PHY_ID)
- )
- {
- /* supported phy */
- phyPresent[i] = true;
- } /* end of if(ixEthMiiPhyId) */
- else
- {
- if (ixEthMiiPhyId[i] != IX_ETH_MII_INVALID_PHY_ID)
- {
- /* unsupported phy */
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
- IX_OSAL_LOG_DEV_STDOUT,
- "ixEthMiiPhyScan : unexpected Mii PHY ID %8.8x\n",
- ixEthMiiPhyId[i], 2, 3, 4, 5, 6);
- ixEthMiiPhyId[i] = IX_ETH_MII_UNKNOWN_PHY_ID;
- phyPresent[i] = true;
- }
- }
- }
- }
- }
- return IX_SUCCESS;
-}
-
-/************************************************************
- *
- * Configure the PHY at the specified address
- *
- */
-PUBLIC IX_STATUS
-ixEthMiiPhyConfig(UINT32 phyAddr,
- BOOL speed100,
- BOOL fullDuplex,
- BOOL autonegotiate)
-{
- UINT16 regval=0;
-
- /* parameter check */
- if ((phyAddr < IXP425_ETH_ACC_MII_MAX_ADDR) &&
- (ixEthMiiPhyId[phyAddr] != IX_ETH_MII_INVALID_PHY_ID))
- {
- /*
- * set the control register
- */
- if(autonegotiate)
- {
- regval |= IX_ETH_MII_CR_AUTO_EN | IX_ETH_MII_CR_RESTART;
- }
- else
- {
- if(speed100)
- {
- regval |= IX_ETH_MII_CR_100;
- }
- if(fullDuplex)
- {
- regval |= IX_ETH_MII_CR_FDX;
- }
- } /* end of if-else() */
- if (ixEthAccMiiWriteRtn(phyAddr,
- IX_ETH_MII_CTRL_REG,
- regval) == IX_ETH_ACC_SUCCESS)
- {
- return IX_SUCCESS;
- }
- } /* end of if(phyAddr) */
- return IX_FAIL;
-}
-
-/******************************************************************
- *
- * Enable the PHY Loopback at the specified address
- */
-PUBLIC IX_STATUS
-ixEthMiiPhyLoopbackEnable (UINT32 phyAddr)
-{
- UINT16 regval ;
-
- if ((phyAddr < IXP425_ETH_ACC_MII_MAX_ADDR) &&
- (IX_ETH_MII_INVALID_PHY_ID != ixEthMiiPhyId[phyAddr]))
- {
- /* read/write the control register */
- if(ixEthAccMiiReadRtn (phyAddr,
- IX_ETH_MII_CTRL_REG,
- ®val)
- == IX_ETH_ACC_SUCCESS)
- {
- if(ixEthAccMiiWriteRtn (phyAddr,
- IX_ETH_MII_CTRL_REG,
- regval | IX_ETH_MII_CR_LOOPBACK)
- == IX_ETH_ACC_SUCCESS)
- {
- return IX_SUCCESS;
- }
- }
- }
- return IX_FAIL;
-}
-
-/******************************************************************
- *
- * Disable the PHY Loopback at the specified address
- */
-PUBLIC IX_STATUS
-ixEthMiiPhyLoopbackDisable (UINT32 phyAddr)
-{
- UINT16 regval ;
-
- if ((phyAddr < IXP425_ETH_ACC_MII_MAX_ADDR) &&
- (IX_ETH_MII_INVALID_PHY_ID != ixEthMiiPhyId[phyAddr]))
- {
- /* read/write the control register */
- if(ixEthAccMiiReadRtn (phyAddr,
- IX_ETH_MII_CTRL_REG,
- ®val)
- == IX_ETH_ACC_SUCCESS)
- {
- if(ixEthAccMiiWriteRtn (phyAddr,
- IX_ETH_MII_CTRL_REG,
- regval & (~IX_ETH_MII_CR_LOOPBACK))
- == IX_ETH_ACC_SUCCESS)
- {
- return IX_SUCCESS;
- }
- }
- }
- return IX_FAIL;
-}
-
-/******************************************************************
- *
- * Reset the PHY at the specified address
- */
-PUBLIC IX_STATUS
-ixEthMiiPhyReset(UINT32 phyAddr)
-{
- UINT32 timeout;
- UINT16 regval;
-
- if ((phyAddr < IXP425_ETH_ACC_MII_MAX_ADDR) &&
- (ixEthMiiPhyId[phyAddr] != IX_ETH_MII_INVALID_PHY_ID))
- {
- if ((ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT971_PHY_ID) ||
- (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT972_PHY_ID) ||
- (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT973_PHY_ID) ||
- (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT973A3_PHY_ID) ||
- (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT9785_PHY_ID)
- )
- {
- /* use the control register to reset the phy */
- ixEthAccMiiWriteRtn(phyAddr,
- IX_ETH_MII_CTRL_REG,
- IX_ETH_MII_CR_RESET);
-
- /* poll until the reset bit is cleared */
- timeout = 0;
- do
- {
- ixOsalSleep (IX_ETH_MII_RESET_POLL_MS);
-
- /* read the control register and check for timeout */
- ixEthAccMiiReadRtn(phyAddr,
- IX_ETH_MII_CTRL_REG,
- ®val);
- if ((regval & IX_ETH_MII_CR_RESET) == 0)
- {
- /* timeout bit is self-cleared */
- break;
- }
- timeout += IX_ETH_MII_RESET_POLL_MS;
- }
- while (timeout < IX_ETH_MII_RESET_DELAY_MS);
-
- /* check for timeout */
- if (timeout >= IX_ETH_MII_RESET_DELAY_MS)
- {
- ixEthAccMiiWriteRtn(phyAddr, IX_ETH_MII_CTRL_REG,
- IX_ETH_MII_CR_NORM_EN);
- return IX_FAIL;
- }
-
- return IX_SUCCESS;
- } /* end of if(ixEthMiiPhyId) */
- else if (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_KS8995_PHY_ID)
- {
- /* reset bit is reserved, just reset the control register */
- ixEthAccMiiWriteRtn(phyAddr, IX_ETH_MII_CTRL_REG,
- IX_ETH_MII_CR_NORM_EN);
- return IX_SUCCESS;
- }
- else
- {
- /* unknown PHY, set the control register reset bit,
- * wait 2 s. and clear the control register.
- */
- ixEthAccMiiWriteRtn(phyAddr, IX_ETH_MII_CTRL_REG,
- IX_ETH_MII_CR_RESET);
-
- ixOsalSleep (IX_ETH_MII_RESET_DELAY_MS);
-
- ixEthAccMiiWriteRtn(phyAddr, IX_ETH_MII_CTRL_REG,
- IX_ETH_MII_CR_NORM_EN);
- return IX_SUCCESS;
- } /* end of if-else(ixEthMiiPhyId) */
- } /* end of if(phyAddr) */
- return IX_FAIL;
-}
-
-/*****************************************************************
- *
- * Link state query functions
- */
-
-PUBLIC IX_STATUS
-ixEthMiiLinkStatus(UINT32 phyAddr,
- BOOL *linkUp,
- BOOL *speed100,
- BOOL *fullDuplex,
- BOOL *autoneg)
-{
- UINT16 ctrlRegval, statRegval, regval, regval4, regval5;
-
- /* check the parameters */
- if ((linkUp == NULL) ||
- (speed100 == NULL) ||
- (fullDuplex == NULL) ||
- (autoneg == NULL))
- {
- return IX_FAIL;
- }
-
- *linkUp = false;
- *speed100 = false;
- *fullDuplex = false;
- *autoneg = false;
-
- if ((phyAddr < IXP425_ETH_ACC_MII_MAX_ADDR) &&
- (ixEthMiiPhyId[phyAddr] != IX_ETH_MII_INVALID_PHY_ID))
- {
- if ((ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT971_PHY_ID) ||
- (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT972_PHY_ID) ||
- (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT9785_PHY_ID)
- )
- {
- /* --------------------------------------------------*/
- /* Retrieve information from PHY specific register */
- /* --------------------------------------------------*/
- if (ixEthAccMiiReadRtn(phyAddr,
- IX_ETH_MII_STAT2_REG,
- ®val) != IX_ETH_ACC_SUCCESS)
- {
- return IX_FAIL;
- }
- *linkUp = ((regval & IX_ETH_MII_SR2_LINK) != 0);
- *speed100 = ((regval & IX_ETH_MII_SR2_100) != 0);
- *fullDuplex = ((regval & IX_ETH_MII_SR2_FD) != 0);
- *autoneg = ((regval & IX_ETH_MII_SR2_AUTO) != 0);
- return IX_SUCCESS;
- } /* end of if(ixEthMiiPhyId) */
- else
- {
- /* ----------------------------------------------------*/
- /* Retrieve information from status and ctrl registers */
- /* ----------------------------------------------------*/
- if (ixEthAccMiiReadRtn(phyAddr,
- IX_ETH_MII_CTRL_REG,
- &ctrlRegval) != IX_ETH_ACC_SUCCESS)
- {
- return IX_FAIL;
- }
- ixEthAccMiiReadRtn(phyAddr, IX_ETH_MII_STAT_REG, &statRegval);
-
- *linkUp = ((statRegval & IX_ETH_MII_SR_LINK_STATUS) != 0);
- if (*linkUp)
- {
- *autoneg = ((ctrlRegval & IX_ETH_MII_CR_AUTO_EN) != 0) &&
- ((statRegval & IX_ETH_MII_SR_AUTO_SEL) != 0) &&
- ((statRegval & IX_ETH_MII_SR_AUTO_NEG) != 0);
-
- if (*autoneg)
- {
- /* mask the current stat values with the capabilities */
- ixEthAccMiiReadRtn(phyAddr, IX_ETH_MII_AN_ADS_REG, ®val4);
- ixEthAccMiiReadRtn(phyAddr, IX_ETH_MII_AN_PRTN_REG, ®val5);
- /* merge the flags from the 3 registers */
- regval = (statRegval & ((regval4 & regval5) << 6));
- /* initialise from status register values */
- if ((regval & IX_ETH_MII_SR_TX_FULL_DPX) != 0)
- {
- /* 100 Base X full dplx */
- *speed100 = true;
- *fullDuplex = true;
- return IX_SUCCESS;
- }
- if ((regval & IX_ETH_MII_SR_TX_HALF_DPX) != 0)
- {
- /* 100 Base X half dplx */
- *speed100 = true;
- return IX_SUCCESS;
- }
- if ((regval & IX_ETH_MII_SR_10T_FULL_DPX) != 0)
- {
- /* 10 mb full dplx */
- *fullDuplex = true;
- return IX_SUCCESS;
- }
- if ((regval & IX_ETH_MII_SR_10T_HALF_DPX) != 0)
- {
- /* 10 mb half dplx */
- return IX_SUCCESS;
- }
- } /* end of if(autoneg) */
- else
- {
- /* autonegotiate not complete, return setup parameters */
- *speed100 = ((ctrlRegval & IX_ETH_MII_CR_100) != 0);
- *fullDuplex = ((ctrlRegval & IX_ETH_MII_CR_FDX) != 0);
- }
- } /* end of if(linkUp) */
- } /* end of if-else(ixEthMiiPhyId) */
- } /* end of if(phyAddr) */
- else
- {
- return IX_FAIL;
- } /* end of if-else(phyAddr) */
- return IX_SUCCESS;
-}
-
-/*****************************************************************
- *
- * Link state display functions
- */
-
-PUBLIC IX_STATUS
-ixEthMiiPhyShow (UINT32 phyAddr)
-{
- BOOL linkUp, speed100, fullDuplex, autoneg;
- UINT16 cregval;
- UINT16 sregval;
-
-
- ixEthAccMiiReadRtn(phyAddr, IX_ETH_MII_STAT_REG, &sregval);
- ixEthAccMiiReadRtn(phyAddr, IX_ETH_MII_CTRL_REG, &cregval);
-
- /* get link information */
- if (ixEthMiiLinkStatus(phyAddr,
- &linkUp,
- &speed100,
- &fullDuplex,
- &autoneg) != IX_ETH_ACC_SUCCESS)
- {
- printf("PHY Status unknown\n");
- return IX_FAIL;
- }
-
- printf("PHY ID [phyAddr]: %8.8x\n",ixEthMiiPhyId[phyAddr]);
- printf( " Status reg: %4.4x\n",sregval);
- printf( " control reg: %4.4x\n",cregval);
- /* display link information */
- printf("PHY Status:\n");
- printf(" Link is %s\n",
- (linkUp ? "Up" : "Down"));
- if((sregval & IX_ETH_MII_SR_REMOTE_FAULT) != 0)
- {
- printf(" Remote fault detected\n");
- }
- printf(" Auto Negotiation %s\n",
- (autoneg ? "Completed" : "Not Completed"));
-
- printf("PHY Configuration:\n");
- printf(" Speed %sMb/s\n",
- (speed100 ? "100" : "10"));
- printf(" %s Duplex\n",
- (fullDuplex ? "Full" : "Half"));
- printf(" Auto Negotiation %s\n",
- (autoneg ? "Enabled" : "Disabled"));
- return IX_SUCCESS;
-}
-
+++ /dev/null
-/**
- * @file IxFeatureCtrl.c
- *
- * @author Intel Corporation
- * @date 29-Jan-2003
- *
- * @brief Feature Control Public API Implementation
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-#include "IxOsal.h"
-#include "IxVersionId.h"
-#include "IxFeatureCtrl.h"
-
-/* Macro to read from the Feature Control Register */
-#define IX_FEATURE_CTRL_READ(result) \
-do { \
-ixFeatureCtrlExpMap(); \
-(result) = IX_OSAL_READ_LONG(ixFeatureCtrlRegister); \
-} while (0)
-
-/* Macro to write to the Feature Control Register */
-#define IX_FEATURE_CTRL_WRITE(value) \
-do { \
-ixFeatureCtrlExpMap(); \
-IX_OSAL_WRITE_LONG(ixFeatureCtrlRegister, (value)); \
-} while (0)
-
-/*
- * This is the offset of the feature register relative to the base of the
- * Expansion Bus Controller MMR.
- */
-#define IX_FEATURE_CTRL_REG_OFFSET (0x00000028)
-
-
-/* Boolean to mark the fact that the EXP_CONFIG address space was mapped */
-PRIVATE BOOL ixFeatureCtrlExpCfgRegionMapped = false;
-
-/* Pointer holding the virtual address of the Feature Control Register */
-PRIVATE VUINT32 *ixFeatureCtrlRegister = NULL;
-
-/* Place holder to store the software configuration */
-PRIVATE BOOL swConfiguration[IX_FEATURECTRL_SWCONFIG_MAX];
-
-/* Flag to control swConfiguration[] is initialized once */
-PRIVATE BOOL swConfigurationFlag = false ;
-
-/* Array containing component mask values */
-#ifdef __ixp42X
-UINT32 componentMask[IX_FEATURECTRL_MAX_COMPONENTS] = {
- (0x1<<IX_FEATURECTRL_RCOMP),
- (0x1<<IX_FEATURECTRL_USB),
- (0x1<<IX_FEATURECTRL_HASH),
- (0x1<<IX_FEATURECTRL_AES),
- (0x1<<IX_FEATURECTRL_DES),
- (0x1<<IX_FEATURECTRL_HDLC),
- (0x1<<IX_FEATURECTRL_AAL),
- (0x1<<IX_FEATURECTRL_HSS),
- (0x1<<IX_FEATURECTRL_UTOPIA),
- (0x1<<IX_FEATURECTRL_ETH0),
- (0x1<<IX_FEATURECTRL_ETH1),
- (0x1<<IX_FEATURECTRL_NPEA),
- (0x1<<IX_FEATURECTRL_NPEB),
- (0x1<<IX_FEATURECTRL_NPEC),
- (0x1<<IX_FEATURECTRL_PCI),
- IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE,
- (0x3<<IX_FEATURECTRL_UTOPIA_PHY_LIMIT),
- (0x1<<IX_FEATURECTRL_UTOPIA_PHY_LIMIT_BIT2),
- IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE,
- IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE,
- IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE,
- IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE,
- IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE
-};
-#elif defined (__ixp46X)
-UINT32 componentMask[IX_FEATURECTRL_MAX_COMPONENTS] = {
- (0x1<<IX_FEATURECTRL_RCOMP),
- (0x1<<IX_FEATURECTRL_USB),
- (0x1<<IX_FEATURECTRL_HASH),
- (0x1<<IX_FEATURECTRL_AES),
- (0x1<<IX_FEATURECTRL_DES),
- (0x1<<IX_FEATURECTRL_HDLC),
- IX_FEATURECTRL_COMPONENT_ALWAYS_AVAILABLE, /* AAL component is always on */
- (0x1<<IX_FEATURECTRL_HSS),
- (0x1<<IX_FEATURECTRL_UTOPIA),
- (0x1<<IX_FEATURECTRL_ETH0),
- (0x1<<IX_FEATURECTRL_ETH1),
- (0x1<<IX_FEATURECTRL_NPEA),
- (0x1<<IX_FEATURECTRL_NPEB),
- (0x1<<IX_FEATURECTRL_NPEC),
- (0x1<<IX_FEATURECTRL_PCI),
- (0x1<<IX_FEATURECTRL_ECC_TIMESYNC),
- (0x3<<IX_FEATURECTRL_UTOPIA_PHY_LIMIT),
- (0x1<<IX_FEATURECTRL_UTOPIA_PHY_LIMIT_BIT2), /* NOT TO BE USED */
- (0x1<<IX_FEATURECTRL_USB_HOST_CONTROLLER),
- (0x1<<IX_FEATURECTRL_NPEA_ETH),
- (0x1<<IX_FEATURECTRL_NPEB_ETH),
- (0x1<<IX_FEATURECTRL_RSA),
- (0x3<<IX_FEATURECTRL_XSCALE_MAX_FREQ),
- (0x1<<IX_FEATURECTRL_XSCALE_MAX_FREQ_BIT2)
-};
-#endif /* __ixp42X */
-
-/**
- * Forward declaration
- */
-PRIVATE
-void ixFeatureCtrlExpMap(void);
-
-PRIVATE
-void ixFeatureCtrlSwConfigurationInit(void);
-
-/**
- * Function to map EXP_CONFIG space
- */
-PRIVATE
-void ixFeatureCtrlExpMap(void)
-{
- UINT32 expCfgBaseAddress = 0;
-
- /* If the EXP Configuration space has already been mapped then
- * return */
- if (ixFeatureCtrlExpCfgRegionMapped == true)
- {
- return;
- }
-
- /* Map (get virtual address) for the EXP_CONFIG space */
- expCfgBaseAddress = (UINT32)
- (IX_OSAL_MEM_MAP(IX_OSAL_IXP400_EXP_BUS_REGS_PHYS_BASE,
- IX_OSAL_IXP400_EXP_REG_MAP_SIZE));
-
- /* Assert that the mapping operation succeeded */
- IX_OSAL_ASSERT(expCfgBaseAddress);
-
- /* Set the address of the Feature register */
- ixFeatureCtrlRegister =
- (VUINT32 *) (expCfgBaseAddress + IX_FEATURE_CTRL_REG_OFFSET);
-
- /* Mark the fact that the EXP_CONFIG space has already been mapped */
- ixFeatureCtrlExpCfgRegionMapped = true;
-}
-
-/**
- * Function definition: ixFeatureCtrlSwConfigurationInit
- * This function will only initialize software configuration once.
- */
-PRIVATE void ixFeatureCtrlSwConfigurationInit(void)
-{
- UINT32 i;
- if (false == swConfigurationFlag)
- {
- for (i=0; i<IX_FEATURECTRL_SWCONFIG_MAX ; i++)
- {
- /* By default, all software configuration are enabled */
- swConfiguration[i]= true ;
- }
- /*Make sure this function only initializes swConfiguration[] once*/
- swConfigurationFlag = true ;
- }
-}
-
-/**
- * Function definition: ixFeatureCtrlRead
- */
-IxFeatureCtrlReg
-ixFeatureCtrlRead (void)
-{
- IxFeatureCtrlReg result;
-
-#if CPU!=SIMSPARCSOLARIS
- /* Read the feature control register */
- IX_FEATURE_CTRL_READ(result);
- return result;
-#else
- /* Return an invalid value for VxWorks simulation */
- result = 0xFFFFFFFF;
- return result;
-#endif
-}
-
-/**
- * Function definition: ixFeatureCtrlWrite
- */
-void
-ixFeatureCtrlWrite (IxFeatureCtrlReg expUnitReg)
-{
-#if CPU!=SIMSPARCSOLARIS
- /* Write value to feature control register */
- IX_FEATURE_CTRL_WRITE(expUnitReg);
-#endif
-}
-
-
-/**
- * Function definition: ixFeatureCtrlHwCapabilityRead
- */
-IxFeatureCtrlReg
-ixFeatureCtrlHwCapabilityRead (void)
-{
- IxFeatureCtrlReg currentReg, hwCapability;
-
- /* Capture a copy of feature control register */
- currentReg = ixFeatureCtrlRead();
-
- /* Try to enable all hardware components.
- * Only software disable hardware can be enabled again */
- ixFeatureCtrlWrite(0);
-
- /* Read feature control register to know the hardware capability. */
- hwCapability = ixFeatureCtrlRead();
-
- /* Restore initial feature control value */
- ixFeatureCtrlWrite(currentReg);
-
- /* return Hardware Capability */
- return hwCapability;
-}
-
-
-/**
- * Function definition: ixFeatureCtrlComponentCheck
- */
-IX_STATUS
-ixFeatureCtrlComponentCheck (IxFeatureCtrlComponentType componentType)
-{
- IxFeatureCtrlReg expUnitReg;
- UINT32 mask = 0;
-
- /* Lookup mask of component */
- mask=componentMask[componentType];
-
- /* Check if mask is available or not */
- if(IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE == mask)
- {
- return IX_FEATURE_CTRL_COMPONENT_DISABLED;
- }
-
- if(IX_FEATURECTRL_COMPONENT_ALWAYS_AVAILABLE == mask)
- {
- return IX_FEATURE_CTRL_COMPONENT_ENABLED;
- }
-
- /* Read feature control register to know current hardware capability. */
- expUnitReg = ixFeatureCtrlRead();
-
- /* For example: To check for Hashing Coprocessor (bit-2)
- * expUniteg = 0x0010
- * ~expUnitReg = 0x1101
- * componentType = 0x0100
- * ~expUnitReg & componentType = 0x0100 (Not zero)
- */
-
- /*
- * Inverse the bit value because available component is 0 in value
- */
- expUnitReg = ~expUnitReg ;
-
- if (expUnitReg & mask)
- {
- return (IX_FEATURE_CTRL_COMPONENT_ENABLED);
- }
- else
- {
- return (IX_FEATURE_CTRL_COMPONENT_DISABLED);
- }
-}
-
-
-/**
- * Function definition: ixFeatureCtrlProductIdRead
- */
-IxFeatureCtrlProductId
-ixFeatureCtrlProductIdRead ()
-{
-#if CPU!=SIMSPARCSOLARIS
- IxFeatureCtrlProductId pdId = 0 ;
-
- /* Use ARM instruction to move register0 from coprocessor to ARM register */
-
-#ifndef __wince
- __asm__("mrc p15, 0, %0, cr0, cr0, 0;" : "=r"(pdId) :);
-#else
-
-#ifndef IN_KERNEL
- BOOL mode;
-#endif
- extern IxFeatureCtrlProductId AsmixFeatureCtrlProductIdRead();
-
-#ifndef IN_KERNEL
- mode = SetKMode(true);
-#endif
- pdId = AsmixFeatureCtrlProductIdRead();
-#ifndef IN_KERNEL
- SetKMode(mode);
-#endif
-
-#endif
- return (pdId);
-#else
- /* Return an invalid value for VxWorks simulation */
- return 0xffffffff;
-#endif
-}
-
-/**
- * Function definition: ixFeatureCtrlDeviceRead
- */
-IxFeatureCtrlDeviceId
-ixFeatureCtrlDeviceRead ()
-{
- return ((ixFeatureCtrlProductIdRead() >> IX_FEATURE_CTRL_DEVICE_TYPE_OFFSET)
- & IX_FEATURE_CTRL_DEVICE_TYPE_MASK);
-} /* End function ixFeatureCtrlDeviceRead */
-
-
-/**
- * Function definition: ixFeatureCtrlSwConfigurationCheck
- */
-IX_STATUS
-ixFeatureCtrlSwConfigurationCheck (IxFeatureCtrlSwConfig swConfigType)
-{
- if (swConfigType >= IX_FEATURECTRL_SWCONFIG_MAX)
- {
- ixOsalLog(IX_OSAL_LOG_LVL_WARNING,
- IX_OSAL_LOG_DEV_STDOUT,
- "FeatureCtrl: Invalid software configuraiton input.\n",
- 0, 0, 0, 0, 0, 0);
-
- return IX_FEATURE_CTRL_SWCONFIG_DISABLED;
- }
-
- /* The function will only initialize once. */
- ixFeatureCtrlSwConfigurationInit();
-
- /* Check and return software configuration */
- return ((swConfiguration[(UINT32)swConfigType] == true) ? IX_FEATURE_CTRL_SWCONFIG_ENABLED: IX_FEATURE_CTRL_SWCONFIG_DISABLED);
-}
-
-/**
- * Function definition: ixFeatureCtrlSwConfigurationWrite
- */
-void
-ixFeatureCtrlSwConfigurationWrite (IxFeatureCtrlSwConfig swConfigType, BOOL enabled)
-{
- if (swConfigType >= IX_FEATURECTRL_SWCONFIG_MAX)
- {
- ixOsalLog(IX_OSAL_LOG_LVL_WARNING,
- IX_OSAL_LOG_DEV_STDOUT,
- "FeatureCtrl: Invalid software configuraiton input.\n",
- 0, 0, 0, 0, 0, 0);
-
- return;
- }
-
- /* The function will only initialize once. */
- ixFeatureCtrlSwConfigurationInit();
-
- /* Write software configuration */
- swConfiguration[(UINT32)swConfigType]=enabled ;
-}
-
-/**
- * Function definition: ixFeatureCtrlIxp400SwVersionShow
- */
-void
-ixFeatureCtrlIxp400SwVersionShow (void)
-{
- printf ("\nIXP400 Software Release %s %s\n\n", IX_VERSION_ID, IX_VERSION_INTERNAL_ID);
-
-}
-
-/**
- * Function definition: ixFeatureCtrlSoftwareBuildGet
- */
-IxFeatureCtrlBuildDevice
-ixFeatureCtrlSoftwareBuildGet (void)
-{
- #ifdef __ixp42X
- return IX_FEATURE_CTRL_SW_BUILD_IXP42X;
- #else
- return IX_FEATURE_CTRL_SW_BUILD_IXP46X;
- #endif
-}
+++ /dev/null
-/**
- * @file IxNpeDl.c
- *
- * @author Intel Corporation
- * @date 08 January 2002
- *
- * @brief This file contains the implementation of the public API for the
- * IXP425 NPE Downloader component
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * Put the system defined include files required
- */
-
-/*
- * Put the user defined include files required
- */
-#include "IxNpeDl.h"
-#include "IxNpeDlImageMgr_p.h"
-#include "IxNpeDlNpeMgr_p.h"
-#include "IxNpeDlMacros_p.h"
-#include "IxFeatureCtrl.h"
-#include "IxOsal.h"
-/*
- * #defines used in this file
- */
- #define IMAGEID_MAJOR_NUMBER_DEFAULT 0
- #define IMAGEID_MINOR_NUMBER_DEFAULT 0
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-typedef struct
-{
- BOOL validImage;
- IxNpeDlImageId imageId;
-} IxNpeDlNpeState;
-
-/* module statistics counters */
-typedef struct
-{
- UINT32 attemptedDownloads;
- UINT32 successfulDownloads;
- UINT32 criticalFailDownloads;
-} IxNpeDlStats;
-
-/*
- * Variable declarations global to this file only. Externs are followed
- * by static variables.
- */
-static IxNpeDlNpeState ixNpeDlNpeState[IX_NPEDL_NPEID_MAX] =
-{
- {false, {IX_NPEDL_NPEID_MAX, 0, 0, 0}},
- {false, {IX_NPEDL_NPEID_MAX, 0, 0, 0}},
- {false, {IX_NPEDL_NPEID_MAX, 0, 0, 0}}
-};
-
-static IxNpeDlStats ixNpeDlStats;
-
-/*
- * Software guard to prevent NPE from being started multiple times.
- */
-static BOOL ixNpeDlNpeStarted[IX_NPEDL_NPEID_MAX] ={false, false, false} ;
-
-
-/*
- * static function prototypes.
- */
-PRIVATE IX_STATUS
-ixNpeDlNpeInitAndStartInternal (UINT32 *imageLibrary, UINT32 imageId);
-
-/*
- * Function definition: ixNpeDlImageDownload
- */
-PUBLIC IX_STATUS
-ixNpeDlImageDownload (IxNpeDlImageId *imageIdPtr,
- BOOL verify)
-{
- UINT32 imageSize;
- UINT32 *imageCodePtr = NULL;
- IX_STATUS status;
- IxNpeDlNpeId npeId = imageIdPtr->npeId;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlImageDownload\n");
-
- ixNpeDlStats.attemptedDownloads++;
-
- /* Check input parameters */
- if ((npeId >= IX_NPEDL_NPEID_MAX) || (npeId < 0))
- {
- status = IX_NPEDL_PARAM_ERR;
- IX_NPEDL_ERROR_REPORT ("ixNpeDlImageDownload - invalid parameter\n");
- }
- else
- {
- /* Ensure initialisation has been completed */
- ixNpeDlNpeMgrInit();
-
- /* If not IXP42X A0 stepping, proceed to check for existence of npe's */
- if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
- (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
- || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
- {
- if (npeId == IX_NPEDL_NPEID_NPEA)
- {
- if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA) ==
- IX_FEATURE_CTRL_COMPONENT_DISABLED)
- {
- IX_NPEDL_WARNING_REPORT("Warning: the NPE A component you specified does"
- " not exist\n");
- return IX_SUCCESS;
- }
- } /* end of if(npeId) */
- else if (npeId == IX_NPEDL_NPEID_NPEB)
- {
- if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB)==
- IX_FEATURE_CTRL_COMPONENT_DISABLED)
- {
- IX_NPEDL_WARNING_REPORT("Warning: the NPE B component you specified"
- " does not exist\n");
- return IX_SUCCESS;
- }
- } /* end of elseif(npeId) */
- else if (npeId == IX_NPEDL_NPEID_NPEC)
- {
- if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC)==
- IX_FEATURE_CTRL_COMPONENT_DISABLED)
- {
- IX_NPEDL_WARNING_REPORT("Warning: the NPE C component you specified"
- " does not exist\n");
- return IX_SUCCESS;
- }
- } /* end of elseif(npeId) */
- } /* end of if(IX_FEATURE_CTRL_SILICON_TYPE_B0) */ /*End of Silicon Type Check*/
-
- /* stop and reset the NPE */
- if (IX_SUCCESS != ixNpeDlNpeStopAndReset (npeId))
- {
- IX_NPEDL_ERROR_REPORT ("Failed to stop and reset NPE\n");
- return IX_FAIL;
- }
-
- /* Locate image */
- status = ixNpeDlImageMgrImageLocate (imageIdPtr, &imageCodePtr,
- &imageSize);
- if (IX_SUCCESS == status)
- {
- /*
- * If download was successful, store image Id in list of
- * currently loaded images. If a critical error occured
- * during download, record that the NPE has an invalid image
- */
- status = ixNpeDlNpeMgrImageLoad (npeId, imageCodePtr,
- verify);
- if (IX_SUCCESS == status)
- {
- ixNpeDlNpeState[npeId].imageId = *imageIdPtr;
- ixNpeDlNpeState[npeId].validImage = true;
- ixNpeDlStats.successfulDownloads++;
-
- status = ixNpeDlNpeExecutionStart (npeId);
- }
- else if ((status == IX_NPEDL_CRITICAL_NPE_ERR) ||
- (status == IX_NPEDL_CRITICAL_MICROCODE_ERR))
- {
- ixNpeDlNpeState[npeId].imageId = *imageIdPtr;
- ixNpeDlNpeState[npeId].validImage = false;
- ixNpeDlStats.criticalFailDownloads++;
- }
- } /* end of if(IX_SUCCESS) */ /* condition: image located successfully in microcode image */
- } /* end of if-else(npeId) */ /* condition: parameter checks ok */
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlImageDownload : status = %d\n", status);
- return status;
-}
-
-/*
- * Function definition: ixNpeDlAvailableImagesCountGet
- */
-PUBLIC IX_STATUS
-ixNpeDlAvailableImagesCountGet (UINT32 *numImagesPtr)
-{
- IX_STATUS status;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlAvailableImagesCountGet\n");
-
- /* Check input parameters */
- if (numImagesPtr == NULL)
- {
- status = IX_NPEDL_PARAM_ERR;
- IX_NPEDL_ERROR_REPORT ("ixNpeDlAvailableImagesCountGet - "
- "invalid parameter\n");
- }
- else
- {
- /*
- * Use ImageMgr module to get no. of images listed in Image Library Header.
- * If NULL is passed as imageListPtr parameter to following function,
- * it will only fill number of images into numImagesPtr
- */
- status = ixNpeDlImageMgrImageListExtract (NULL, numImagesPtr);
- } /* end of if-else(numImagesPtr) */
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlAvailableImagesCountGet : "
- "status = %d\n", status);
- return status;
-}
-
-/*
- * Function definition: ixNpeDlAvailableImagesListGet
- */
-PUBLIC IX_STATUS
-ixNpeDlAvailableImagesListGet (IxNpeDlImageId *imageIdListPtr,
- UINT32 *listSizePtr)
-{
- IX_STATUS status;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlAvailableImagesListGet\n");
-
- /* Check input parameters */
- if ((imageIdListPtr == NULL) || (listSizePtr == NULL))
- {
- status = IX_NPEDL_PARAM_ERR;
- IX_NPEDL_ERROR_REPORT ("ixNpeDlAvailableImagesListGet - "
- "invalid parameter\n");
- }
- else
- {
- /* Call ImageMgr to get list of images listed in Image Library Header */
- status = ixNpeDlImageMgrImageListExtract (imageIdListPtr,
- listSizePtr);
- } /* end of if-else(imageIdListPtr) */
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlAvailableImagesListGet : status = %d\n",
- status);
- return status;
-}
-
-/*
- * Function definition: ixNpeDlLoadedImageGet
- */
-PUBLIC IX_STATUS
-ixNpeDlLoadedImageGet (IxNpeDlNpeId npeId,
- IxNpeDlImageId *imageIdPtr)
-{
- IX_STATUS status = IX_SUCCESS;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlLoadedImageGet\n");
-
- /* Check input parameters */
- if ((npeId >= IX_NPEDL_NPEID_MAX) || (npeId < 0) || (imageIdPtr == NULL))
- {
- status = IX_NPEDL_PARAM_ERR;
- IX_NPEDL_ERROR_REPORT ("ixNpeDlLoadedImageGet - invalid parameter\n");
- }
- else
- {
-
- /* If not IXP42X A0 stepping, proceed to check for existence of npe's */
- if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
- (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
- || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
- {
- if (npeId == IX_NPEDL_NPEID_NPEA &&
- (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA) ==
- IX_FEATURE_CTRL_COMPONENT_DISABLED))
- {
- IX_NPEDL_WARNING_REPORT("Warning: the NPE A component you specified does"
- " not exist\n");
- return IX_SUCCESS;
- } /* end of if(npeId) */
-
- if (npeId == IX_NPEDL_NPEID_NPEB &&
- (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB) ==
- IX_FEATURE_CTRL_COMPONENT_DISABLED))
- {
- IX_NPEDL_WARNING_REPORT("Warning: the NPE B component you specified does"
- " not exist\n");
- return IX_SUCCESS;
- } /* end of if(npeId) */
-
- if (npeId == IX_NPEDL_NPEID_NPEC &&
- (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC) ==
- IX_FEATURE_CTRL_COMPONENT_DISABLED))
- {
- IX_NPEDL_WARNING_REPORT("Warning: the NPE C component you specified does"
- " not exist\n");
- return IX_SUCCESS;
- } /* end of if(npeId) */
- } /* end of if not IXP42x-A0 silicon */
-
- if (ixNpeDlNpeState[npeId].validImage)
- {
- /* use npeId to get imageId from list of currently loaded
- images */
- *imageIdPtr = ixNpeDlNpeState[npeId].imageId;
- }
- else
- {
- status = IX_FAIL;
- } /* end of if-else(ixNpeDlNpeState) */
- } /* end of if-else(npeId) */
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlLoadedImageGet : status = %d\n",
- status);
- return status;
-}
-
-/*
- * Function definition: ixNpeDlLatestImageGet
- */
-PUBLIC IX_STATUS
-ixNpeDlLatestImageGet (
- IxNpeDlNpeId npeId,
- IxNpeDlFunctionalityId functionalityId,
- IxNpeDlImageId *imageIdPtr)
-{
- IX_STATUS status;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlLatestImageGet\n");
-
- /* Check input parameters */
- if ((npeId >= IX_NPEDL_NPEID_MAX) ||
- (npeId < 0) ||
- (imageIdPtr == NULL))
- {
- status = IX_NPEDL_PARAM_ERR;
- IX_NPEDL_ERROR_REPORT ("ixNpeDlLatestImageGet - "
- "invalid parameter\n");
- } /* end of if(npeId) */
- else
- {
-
- /* If not IXP42X A0 stepping, proceed to check for existence of npe's */
- if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
- (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
- || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
- {
- if (npeId == IX_NPEDL_NPEID_NPEA &&
- (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA) ==
- IX_FEATURE_CTRL_COMPONENT_DISABLED))
- {
- IX_NPEDL_WARNING_REPORT("Warning: the NPE A component you specified does"
- " not exist\n");
- return IX_SUCCESS;
- } /* end of if(npeId) */
-
- if (npeId == IX_NPEDL_NPEID_NPEB &&
- (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB) ==
- IX_FEATURE_CTRL_COMPONENT_DISABLED))
- {
- IX_NPEDL_WARNING_REPORT("Warning: the NPE B component you specified does"
- " not exist\n");
- return IX_SUCCESS;
- } /* end of if(npeId) */
-
- if (npeId == IX_NPEDL_NPEID_NPEC &&
- (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC) ==
- IX_FEATURE_CTRL_COMPONENT_DISABLED))
- {
- IX_NPEDL_WARNING_REPORT("Warning: the NPE C component you specified does"
- " not exist\n");
- return IX_SUCCESS;
- } /* end of if(npeId) */
- } /* end of if not IXP42x-A0 silicon */
-
- imageIdPtr->npeId = npeId;
- imageIdPtr->functionalityId = functionalityId;
- imageIdPtr->major = IMAGEID_MAJOR_NUMBER_DEFAULT;
- imageIdPtr->minor = IMAGEID_MINOR_NUMBER_DEFAULT;
- /* Call ImageMgr to get list of images listed in Image Library Header */
- status = ixNpeDlImageMgrLatestImageExtract(imageIdPtr);
- } /* end of if-else(npeId) */
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlLatestImageGet : status = %d\n",
- status);
-
- return status;
-}
-
-/*
- * Function definition: ixNpeDlNpeStopAndReset
- */
-PUBLIC IX_STATUS
-ixNpeDlNpeStopAndReset (IxNpeDlNpeId npeId)
-{
- IX_STATUS status = IX_SUCCESS;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlNpeStopAndReset\n");
-
- /* Ensure initialisation has been completed */
- ixNpeDlNpeMgrInit();
-
- /* If not IXP42X A0 stepping, proceed to check for existence of npe's */
- if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
- (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
- || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
- {
- /*
- * Check whether NPE is present
- */
- if (IX_NPEDL_NPEID_NPEA == npeId)
- {
- /* Check whether NPE A is present */
- if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA)==
- IX_FEATURE_CTRL_COMPONENT_DISABLED)
- {
- /* NPE A does not present */
- IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeStopAndReset - Warning:NPEA does not present.\n");
- return IX_SUCCESS;
- }
- } /* end of if(IX_NPEDL_NPEID_NPEA) */
- else if (IX_NPEDL_NPEID_NPEB == npeId)
- {
- /* Check whether NPE B is present */
- if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB)==
- IX_FEATURE_CTRL_COMPONENT_DISABLED)
- {
- /* NPE B does not present */
- IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeStopAndReset - Warning:NPEB does not present.\n");
- return IX_SUCCESS;
- }
- } /* end of elseif(IX_NPEDL_NPEID_NPEB) */
- else if (IX_NPEDL_NPEID_NPEC == npeId)
- {
- /* Check whether NPE C is present */
- if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC)==
- IX_FEATURE_CTRL_COMPONENT_DISABLED)
- {
- /* NPE C does not present */
- IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeStopAndReset - Warning:NPEC does not present.\n");
- return IX_SUCCESS;
- }
- } /* end of elseif(IX_NPEDL_NPEID_NPEC) */
- else
- {
- /* Invalid NPE ID */
- IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeStopAndReset - invalid Npe ID\n");
- status = IX_NPEDL_PARAM_ERR;
- } /* end of if-else(IX_NPEDL_NPEID_NPEC) */
- } /* end of if not IXP42x-A0 Silicon */
-
- if (status == IX_SUCCESS)
- {
- /* call NpeMgr function to stop the NPE */
- status = ixNpeDlNpeMgrNpeStop (npeId);
- if (status == IX_SUCCESS)
- {
- /* call NpeMgr function to reset the NPE */
- status = ixNpeDlNpeMgrNpeReset (npeId);
- }
- } /* end of if(status) */
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlNpeStopAndReset : status = %d\n", status);
-
- if (IX_SUCCESS == status)
- {
- /* Indicate NPE has been stopped */
- ixNpeDlNpeStarted[npeId] = false ;
- }
-
- return status;
-}
-
-/*
- * Function definition: ixNpeDlNpeExecutionStart
- */
-PUBLIC IX_STATUS
-ixNpeDlNpeExecutionStart (IxNpeDlNpeId npeId)
-{
- IX_STATUS status = IX_SUCCESS;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlNpeExecutionStart\n");
-
- /* If not IXP42X A0 stepping, proceed to check for existence of npe's */
- if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
- (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
- || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
- {
- /*
- * Check whether NPE is present
- */
- if (IX_NPEDL_NPEID_NPEA == npeId)
- {
- /* Check whether NPE A is present */
- if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA)==
- IX_FEATURE_CTRL_COMPONENT_DISABLED)
- {
- /* NPE A does not present */
- IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStart - Warning:NPEA does not present.\n");
- return IX_SUCCESS;
- }
- } /* end of if(IX_NPEDL_NPEID_NPEA) */
- else if (IX_NPEDL_NPEID_NPEB == npeId)
- {
- /* Check whether NPE B is present */
- if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB)==
- IX_FEATURE_CTRL_COMPONENT_DISABLED)
- {
- /* NPE B does not present */
- IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStart - Warning:NPEB does not present.\n");
- return IX_SUCCESS;
- }
- } /* end of elseif(IX_NPEDL_NPEID_NPEB) */
- else if (IX_NPEDL_NPEID_NPEC == npeId)
- {
- /* Check whether NPE C is present */
- if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC)==
- IX_FEATURE_CTRL_COMPONENT_DISABLED)
- {
- /* NPE C does not present */
- IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStart - Warning:NPEC does not present.\n");
- return IX_SUCCESS;
- }
- } /* end of elseif(IX_NPEDL_NPEID_NPEC) */
- else
- {
- /* Invalid NPE ID */
- IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeExecutionStart - invalid Npe ID\n");
- return IX_NPEDL_PARAM_ERR;
- } /* end of if-else(IX_NPEDL_NPEID_NPEC) */
- } /* end of if not IXP42x-A0 Silicon */
-
- if (true == ixNpeDlNpeStarted[npeId])
- {
- /* NPE has been started. */
- return IX_SUCCESS ;
- }
-
- /* Ensure initialisation has been completed */
- ixNpeDlNpeMgrInit();
-
- /* call NpeMgr function to start the NPE */
- status = ixNpeDlNpeMgrNpeStart (npeId);
-
- if (IX_SUCCESS == status)
- {
- /* Indicate NPE has started */
- ixNpeDlNpeStarted[npeId] = true ;
- }
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlNpeExecutionStart : status = %d\n",
- status);
-
- return status;
-}
-
-/*
- * Function definition: ixNpeDlNpeExecutionStop
- */
-PUBLIC IX_STATUS
-ixNpeDlNpeExecutionStop (IxNpeDlNpeId npeId)
-{
- IX_STATUS status = IX_SUCCESS;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlNpeExecutionStop\n");
-
- /* Ensure initialisation has been completed */
- ixNpeDlNpeMgrInit();
-
- /* If not IXP42X A0 stepping, proceed to check for existence of npe's */
- if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
- (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
- || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
- {
- /*
- * Check whether NPE is present
- */
- if (IX_NPEDL_NPEID_NPEA == npeId)
- {
- /* Check whether NPE A is present */
- if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA)==
- IX_FEATURE_CTRL_COMPONENT_DISABLED)
- {
- /* NPE A does not present */
- IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStop - Warning:NPEA does not present.\n");
- return IX_SUCCESS;
- }
- } /* end of if(IX_NPEDL_NPEID_NPEA) */
- else if (IX_NPEDL_NPEID_NPEB == npeId)
- {
- /* Check whether NPE B is present */
- if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB)==
- IX_FEATURE_CTRL_COMPONENT_DISABLED)
- {
- /* NPE B does not present */
- IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStop - Warning:NPEB does not present.\n");
- return IX_SUCCESS;
- }
- } /* end of elseif(IX_NPEDL_NPEID_NPEB) */
- else if (IX_NPEDL_NPEID_NPEC == npeId)
- {
- /* Check whether NPE C is present */
- if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC)==
- IX_FEATURE_CTRL_COMPONENT_DISABLED)
- {
- /* NPE C does not present */
- IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStop - Warning:NPEC does not present.\n");
- return IX_SUCCESS;
- }
- } /* end of elseif(IX_NPEDL_NPEID_NPEC) */
- else
- {
- /* Invalid NPE ID */
- IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeExecutionStop - invalid Npe ID\n");
- status = IX_NPEDL_PARAM_ERR;
- } /* end of if-else(IX_NPEDL_NPEID_NPEC) */
- } /* end of if not IXP42X-AO Silicon */
-
- if (status == IX_SUCCESS)
- {
- /* call NpeMgr function to stop the NPE */
- status = ixNpeDlNpeMgrNpeStop (npeId);
- }
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlNpeExecutionStop : status = %d\n",
- status);
-
- if (IX_SUCCESS == status)
- {
- /* Indicate NPE has been stopped */
- ixNpeDlNpeStarted[npeId] = false ;
- }
-
- return status;
-}
-
-/*
- * Function definition: ixNpeDlUnload
- */
-PUBLIC IX_STATUS
-ixNpeDlUnload (void)
-{
- IX_STATUS status;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlUnload\n");
-
- status = ixNpeDlNpeMgrUninit();
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlUnload : status = %d\n",
- status);
- return status;
-}
-
-/*
- * Function definition: ixNpeDlStatsShow
- */
-PUBLIC void
-ixNpeDlStatsShow (void)
-{
- ixOsalLog (IX_OSAL_LOG_LVL_USER,
- IX_OSAL_LOG_DEV_STDOUT,
- "\nixNpeDlStatsShow:\n"
- "\tDownloads Attempted by user: %u\n"
- "\tSuccessful Downloads: %u\n"
- "\tFailed Downloads (due to Critical Error): %u\n\n",
- ixNpeDlStats.attemptedDownloads,
- ixNpeDlStats.successfulDownloads,
- ixNpeDlStats.criticalFailDownloads,
- 0,0,0);
-
- ixNpeDlImageMgrStatsShow ();
- ixNpeDlNpeMgrStatsShow ();
-}
-
-/*
- * Function definition: ixNpeDlStatsReset
- */
-PUBLIC void
-ixNpeDlStatsReset (void)
-{
- ixNpeDlStats.attemptedDownloads = 0;
- ixNpeDlStats.successfulDownloads = 0;
- ixNpeDlStats.criticalFailDownloads = 0;
-
- ixNpeDlImageMgrStatsReset ();
- ixNpeDlNpeMgrStatsReset ();
-}
-
-/*
- * Function definition: ixNpeDlNpeInitAndStartInternal
- */
-PRIVATE IX_STATUS
-ixNpeDlNpeInitAndStartInternal (UINT32 *imageLibrary,
- UINT32 imageId)
-{
- UINT32 imageSize;
- UINT32 *imageCodePtr = NULL;
- IX_STATUS status;
- IxNpeDlNpeId npeId = IX_NPEDL_NPEID_FROM_IMAGEID_GET(imageId);
- IxFeatureCtrlDeviceId deviceId = IX_NPEDL_DEVICEID_FROM_IMAGEID_GET(imageId);
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlNpeInitAndStartInternal\n");
-
- ixNpeDlStats.attemptedDownloads++;
-
- /* Check input parameter device correctness */
- if ((deviceId >= IX_FEATURE_CTRL_DEVICE_TYPE_MAX) ||
- (deviceId < IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X))
- {
- status = IX_NPEDL_PARAM_ERR;
- IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeInitAndStartInternal - "
- "invalid parameter\n");
- } /* End valid device id checking */
-
- /* Check input parameters */
- else if ((npeId >= IX_NPEDL_NPEID_MAX) || (npeId < 0))
- {
- status = IX_NPEDL_PARAM_ERR;
- IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeInitAndStartInternal - "
- "invalid parameter\n");
- }
-
- else
- {
- /* Ensure initialisation has been completed */
- ixNpeDlNpeMgrInit();
-
- /* Checking if image being loaded is meant for device that is running.
- * Image is forward compatible. i.e Image built for IXP42X should run
- * on IXP46X but not vice versa.*/
- if (deviceId > (ixFeatureCtrlDeviceRead() & IX_FEATURE_CTRL_DEVICE_TYPE_MASK))
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeInitAndStartInternal - "
- "Device type mismatch. NPE Image not "
- "meant for device in use \n");
- return IX_NPEDL_DEVICE_ERR;
- }/* if statement - matching image device and current device */
-
- /* If not IXP42X A0 stepping, proceed to check for existence of npe's */
- if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
- (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
- || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
- {
- if (npeId == IX_NPEDL_NPEID_NPEA)
- {
- if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA) ==
- IX_FEATURE_CTRL_COMPONENT_DISABLED)
- {
- IX_NPEDL_WARNING_REPORT("Warning: the NPE A component you specified does"
- " not exist\n");
- return IX_SUCCESS;
- }
- } /* end of if(npeId) */
- else if (npeId == IX_NPEDL_NPEID_NPEB)
- {
- if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB)==
- IX_FEATURE_CTRL_COMPONENT_DISABLED)
- {
- IX_NPEDL_WARNING_REPORT("Warning: the NPE B component you specified"
- " does not exist\n");
- return IX_SUCCESS;
- }
- } /* end of elseif(npeId) */
- else if (npeId == IX_NPEDL_NPEID_NPEC)
- {
- if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC)==
- IX_FEATURE_CTRL_COMPONENT_DISABLED)
- {
- IX_NPEDL_WARNING_REPORT("Warning: the NPE C component you specified"
- " does not exist\n");
- return IX_SUCCESS;
- }
- } /* end of elseif(npeId) */
- } /* end of if not IXP42X-A0 Silicon */
-
- /* stop and reset the NPE */
- status = ixNpeDlNpeStopAndReset (npeId);
- if (IX_SUCCESS != status)
- {
- IX_NPEDL_ERROR_REPORT ("Failed to stop and reset NPE\n");
- return status;
- }
-
- /* Locate image */
- status = ixNpeDlImageMgrImageFind (imageLibrary, imageId,
- &imageCodePtr, &imageSize);
- if (IX_SUCCESS == status)
- {
- /*
- * If download was successful, store image Id in list of
- * currently loaded images. If a critical error occured
- * during download, record that the NPE has an invalid image
- */
- status = ixNpeDlNpeMgrImageLoad (npeId, imageCodePtr, true);
- if (IX_SUCCESS == status)
- {
- ixNpeDlNpeState[npeId].validImage = true;
- ixNpeDlStats.successfulDownloads++;
-
- status = ixNpeDlNpeExecutionStart (npeId);
- }
- else if ((status == IX_NPEDL_CRITICAL_NPE_ERR) ||
- (status == IX_NPEDL_CRITICAL_MICROCODE_ERR))
- {
- ixNpeDlNpeState[npeId].validImage = false;
- ixNpeDlStats.criticalFailDownloads++;
- }
-
- /* NOTE - The following section of code is here to support
- * a deprecated function ixNpeDlLoadedImageGet(). When that
- * function is removed from the API, this code should be revised.
- */
- ixNpeDlNpeState[npeId].imageId.npeId = npeId;
- ixNpeDlNpeState[npeId].imageId.functionalityId =
- IX_NPEDL_FUNCTIONID_FROM_IMAGEID_GET(imageId);
- ixNpeDlNpeState[npeId].imageId.major =
- IX_NPEDL_MAJOR_FROM_IMAGEID_GET(imageId);
- ixNpeDlNpeState[npeId].imageId.minor =
- IX_NPEDL_MINOR_FROM_IMAGEID_GET(imageId);
- } /* end of if(IX_SUCCESS) */ /* condition: image located successfully in microcode image */
- } /* end of if-else(npeId-deviceId) */ /* condition: parameter checks ok */
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlNpeInitAndStartInternal : "
- "status = %d\n", status);
- return status;
-}
-
-/*
- * Function definition: ixNpeDlCustomImageNpeInitAndStart
- */
-PUBLIC IX_STATUS
-ixNpeDlCustomImageNpeInitAndStart (UINT32 *imageLibrary,
- UINT32 imageId)
-{
- IX_STATUS status;
-
- if (imageLibrary == NULL)
- {
- status = IX_NPEDL_PARAM_ERR;
- IX_NPEDL_ERROR_REPORT ("ixNpeDlCustomImageNpeInitAndStart "
- "- invalid parameter\n");
- }
- else
- {
- status = ixNpeDlNpeInitAndStartInternal (imageLibrary, imageId);
- } /* end of if-else(imageLibrary) */
-
- return status;
-}
-
-/*
- * Function definition: ixNpeDlNpeInitAndStart
- */
-PUBLIC IX_STATUS
-ixNpeDlNpeInitAndStart (UINT32 imageId)
-{
- return ixNpeDlNpeInitAndStartInternal (NULL, imageId);
-}
-
-/*
- * Function definition: ixNpeDlLoadedImageFunctionalityGet
- */
-PUBLIC IX_STATUS
-ixNpeDlLoadedImageFunctionalityGet (IxNpeDlNpeId npeId,
- UINT8 *functionalityId)
-{
- /* Check input parameters */
- if ((npeId >= IX_NPEDL_NPEID_MAX) || (npeId < 0))
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlLoadedImageFunctionalityGet "
- "- invalid parameter\n");
- return IX_NPEDL_PARAM_ERR;
- }
- if (functionalityId == NULL)
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlLoadedImageFunctionalityGet "
- "- invalid parameter\n");
- return IX_NPEDL_PARAM_ERR;
- }
-
- if (ixNpeDlNpeState[npeId].validImage)
- {
- *functionalityId = ixNpeDlNpeState[npeId].imageId.functionalityId;
- return IX_SUCCESS;
- }
- else
- {
- return IX_FAIL;
- }
-}
+++ /dev/null
-/**
- * @file IxNpeDlImageMgr.c
- *
- * @author Intel Corporation
- * @date 09 January 2002
- *
- * @brief This file contains the implementation of the private API for the
- * IXP425 NPE Downloader ImageMgr module
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-
-/*
- * Put the system defined include files required.
- */
-#include "IxOsal.h"
-
-/*
- * Put the user defined include files required.
- */
-#include "IxNpeDlImageMgr_p.h"
-#include "IxNpeDlMacros_p.h"
-
-/*
- * define the flag which toggles the firmare inclusion
- */
-#define IX_NPE_MICROCODE_FIRMWARE_INCLUDED 1
-#include "IxNpeMicrocode.h"
-
-/*
- * Indicates the start of an NPE Image, in new NPE Image Library format.
- * 2 consecutive occurances indicates the end of the NPE Image Library
- */
-#define NPE_IMAGE_MARKER 0xfeedf00d
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/*
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * TO BE DEPRECATED IN A FUTURE RELEASE
- */
-typedef struct
-{
- UINT32 size;
- UINT32 offset;
- UINT32 id;
-} IxNpeDlImageMgrImageEntry;
-
-/*
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * TO BE DEPRECATED IN A FUTURE RELEASE
- */
-typedef union
-{
- IxNpeDlImageMgrImageEntry image;
- UINT32 eohMarker;
-} IxNpeDlImageMgrHeaderEntry;
-
-/*
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * TO BE DEPRECATED IN A FUTURE RELEASE
- */
-typedef struct
-{
- UINT32 signature;
- /* 1st entry in the header (there may be more than one) */
- IxNpeDlImageMgrHeaderEntry entry[1];
-} IxNpeDlImageMgrImageLibraryHeader;
-
-
-/*
- * NPE Image Header definition, used in new NPE Image Library format
- */
-typedef struct
-{
- UINT32 marker;
- UINT32 id;
- UINT32 size;
-} IxNpeDlImageMgrImageHeader;
-
-/* module statistics counters */
-typedef struct
-{
- UINT32 invalidSignature;
- UINT32 imageIdListOverflow;
- UINT32 imageIdNotFound;
-} IxNpeDlImageMgrStats;
-
-
-/*
- * Variable declarations global to this file only. Externs are followed by
- * static variables.
- */
-static IxNpeDlImageMgrStats ixNpeDlImageMgrStats;
-
-static UINT32* getIxNpeMicroCodeImageLibrary(void)
-{
- char *s;
-
- if ((s = getenv("npe_ucode")) != NULL)
- return (UINT32*) simple_strtoul(s, NULL, 16);
- else
- return NULL;
-}
-
-/*
- * static function prototypes.
- */
-PRIVATE BOOL
-ixNpeDlImageMgrSignatureCheck (UINT32 *microCodeImageLibrary);
-
-PRIVATE void
-ixNpeDlImageMgrImageIdFormat (UINT32 rawImageId, IxNpeDlImageId *imageId);
-
-PRIVATE BOOL
-ixNpeDlImageMgrImageIdCompare (IxNpeDlImageId *imageIdA,
- IxNpeDlImageId *imageIdB);
-
-PRIVATE BOOL
-ixNpeDlImageMgrNpeFunctionIdCompare (IxNpeDlImageId *imageIdA,
- IxNpeDlImageId *imageIdB);
-
-#if 0
-PRIVATE IX_STATUS
-ixNpeDlImageMgrImageFind_legacy (UINT32 *imageLibrary,
- UINT32 imageId,
- UINT32 **imagePtr,
- UINT32 *imageSize);
-
-/*
- * Function definition: ixNpeDlImageMgrMicrocodeImageLibraryOverride
- *
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE
- */
-IX_STATUS
-ixNpeDlImageMgrMicrocodeImageLibraryOverride (
- UINT32 *clientImageLibrary)
-{
- IX_STATUS status = IX_SUCCESS;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlImageMgrMicrocodeImageLibraryOverride\n");
-
- if (ixNpeDlImageMgrSignatureCheck (clientImageLibrary))
- {
- IxNpeMicroCodeImageLibrary = clientImageLibrary;
- }
- else
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrMicrocodeImageLibraryOverride: "
- "Client-supplied image has invalid signature\n");
- status = IX_FAIL;
- }
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlImageMgrMicrocodeImageLibraryOverride: status = %d\n",
- status);
- return status;
-}
-#endif
-
-/*
- * Function definition: ixNpeDlImageMgrImageListExtract
- *
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE
- */
-IX_STATUS
-ixNpeDlImageMgrImageListExtract (
- IxNpeDlImageId *imageListPtr,
- UINT32 *numImages)
-{
- UINT32 rawImageId;
- IxNpeDlImageId formattedImageId;
- IX_STATUS status = IX_SUCCESS;
- UINT32 imageCount = 0;
- IxNpeDlImageMgrImageLibraryHeader *header;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlImageMgrImageListExtract\n");
-
- header = (IxNpeDlImageMgrImageLibraryHeader *) getIxNpeMicroCodeImageLibrary();
-
- if (ixNpeDlImageMgrSignatureCheck (getIxNpeMicroCodeImageLibrary()))
- {
- /* for each image entry in the image header ... */
- while (header->entry[imageCount].eohMarker !=
- IX_NPEDL_IMAGEMGR_END_OF_HEADER)
- {
- /*
- * if the image list container from calling function has capacity,
- * add the image id to the list
- */
- if ((imageListPtr != NULL) && (imageCount < *numImages))
- {
- rawImageId = header->entry[imageCount].image.id;
- ixNpeDlImageMgrImageIdFormat (rawImageId, &formattedImageId);
- imageListPtr[imageCount] = formattedImageId;
- }
- /* imageCount reflects no. of image entries in image library header */
- imageCount++;
- }
-
- /*
- * if image list container from calling function was too small to
- * contain all image ids in the header, set return status to FAIL
- */
- if ((imageListPtr != NULL) && (imageCount > *numImages))
- {
- status = IX_FAIL;
- IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageListExtract: "
- "number of Ids found exceeds list capacity\n");
- ixNpeDlImageMgrStats.imageIdListOverflow++;
- }
- /* return number of image ids found in image library header */
- *numImages = imageCount;
- }
- else
- {
- status = IX_FAIL;
- IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageListExtract: "
- "invalid signature in image\n");
- }
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlImageMgrImageListExtract: status = %d\n",
- status);
- return status;
-}
-
-
-/*
- * Function definition: ixNpeDlImageMgrImageLocate
- *
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE
- */
-IX_STATUS
-ixNpeDlImageMgrImageLocate (
- IxNpeDlImageId *imageId,
- UINT32 **imagePtr,
- UINT32 *imageSize)
-{
- UINT32 imageOffset;
- UINT32 rawImageId;
- IxNpeDlImageId formattedImageId;
- /* used to index image entries in image library header */
- UINT32 imageCount = 0;
- IX_STATUS status = IX_FAIL;
- IxNpeDlImageMgrImageLibraryHeader *header;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlImageMgrImageLocate\n");
-
- header = (IxNpeDlImageMgrImageLibraryHeader *) getIxNpeMicroCodeImageLibrary();
-
- if (ixNpeDlImageMgrSignatureCheck (getIxNpeMicroCodeImageLibrary()))
- {
- /* for each image entry in the image library header ... */
- while (header->entry[imageCount].eohMarker !=
- IX_NPEDL_IMAGEMGR_END_OF_HEADER)
- {
- rawImageId = header->entry[imageCount].image.id;
- ixNpeDlImageMgrImageIdFormat (rawImageId, &formattedImageId);
- /* if a match for imageId is found in the image library header... */
- if (ixNpeDlImageMgrImageIdCompare (imageId, &formattedImageId))
- {
- /*
- * get pointer to the image in the image library using offset from
- * 1st word in image library
- */
- UINT32 *tmp=getIxNpeMicroCodeImageLibrary();
- imageOffset = header->entry[imageCount].image.offset;
- *imagePtr = &tmp[imageOffset];
- /* get the image size */
- *imageSize = header->entry[imageCount].image.size;
- status = IX_SUCCESS;
- break;
- }
- imageCount++;
- }
- if (status != IX_SUCCESS)
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageLocate: "
- "imageId not found in image library header\n");
- ixNpeDlImageMgrStats.imageIdNotFound++;
- }
- }
- else
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageLocate: "
- "invalid signature in image library\n");
- }
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlImageMgrImageLocate: status = %d\n", status);
- return status;
-}
-
-/*
- * Function definition: ixNpeDlImageMgrLatestImageExtract
- *
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE
- */
-IX_STATUS
-ixNpeDlImageMgrLatestImageExtract (IxNpeDlImageId *imageId)
-{
- UINT32 imageCount = 0;
- UINT32 rawImageId;
- IxNpeDlImageId formattedImageId;
- IX_STATUS status = IX_FAIL;
- IxNpeDlImageMgrImageLibraryHeader *header;
-
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlImageMgrLatestImageExtract\n");
-
- header = (IxNpeDlImageMgrImageLibraryHeader *) getIxNpeMicroCodeImageLibrary();
-
- if (ixNpeDlImageMgrSignatureCheck (getIxNpeMicroCodeImageLibrary()))
- {
- /* for each image entry in the image library header ... */
- while (header->entry[imageCount].eohMarker !=
- IX_NPEDL_IMAGEMGR_END_OF_HEADER)
- {
- rawImageId = header->entry[imageCount].image.id;
- ixNpeDlImageMgrImageIdFormat (rawImageId, &formattedImageId);
- /*
- * if a match for the npe Id and functionality Id of the imageId is
- * found in the image library header...
- */
- if(ixNpeDlImageMgrNpeFunctionIdCompare(imageId, &formattedImageId))
- {
- if(imageId->major <= formattedImageId.major)
- {
- if(imageId->minor < formattedImageId.minor)
- {
- imageId->minor = formattedImageId.minor;
- }
- imageId->major = formattedImageId.major;
- }
- status = IX_SUCCESS;
- }
- imageCount++;
- }
- if (status != IX_SUCCESS)
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrLatestImageExtract: "
- "imageId not found in image library header\n");
- ixNpeDlImageMgrStats.imageIdNotFound++;
- }
- }
- else
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrLatestImageGet: "
- "invalid signature in image library\n");
- }
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlImageMgrLatestImageGet: status = %d\n", status);
- return status;
-}
-
-/*
- * Function definition: ixNpeDlImageMgrSignatureCheck
- *
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE
- */
-PRIVATE BOOL
-ixNpeDlImageMgrSignatureCheck (UINT32 *microCodeImageLibrary)
-{
- IxNpeDlImageMgrImageLibraryHeader *header =
- (IxNpeDlImageMgrImageLibraryHeader *) microCodeImageLibrary;
- BOOL result = true;
-
- if (!header || header->signature != IX_NPEDL_IMAGEMGR_SIGNATURE)
- {
- result = false;
- ixNpeDlImageMgrStats.invalidSignature++;
- }
-
- return result;
-}
-
-
-/*
- * Function definition: ixNpeDlImageMgrImageIdFormat
- *
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE
- */
-PRIVATE void
-ixNpeDlImageMgrImageIdFormat (
- UINT32 rawImageId,
- IxNpeDlImageId *imageId)
-{
- imageId->npeId = (rawImageId >>
- IX_NPEDL_IMAGEID_NPEID_OFFSET) &
- IX_NPEDL_NPEIMAGE_FIELD_MASK;
- imageId->functionalityId = (rawImageId >>
- IX_NPEDL_IMAGEID_FUNCTIONID_OFFSET) &
- IX_NPEDL_NPEIMAGE_FIELD_MASK;
- imageId->major = (rawImageId >>
- IX_NPEDL_IMAGEID_MAJOR_OFFSET) &
- IX_NPEDL_NPEIMAGE_FIELD_MASK;
- imageId->minor = (rawImageId >>
- IX_NPEDL_IMAGEID_MINOR_OFFSET) &
- IX_NPEDL_NPEIMAGE_FIELD_MASK;
-
-}
-
-
-/*
- * Function definition: ixNpeDlImageMgrImageIdCompare
- *
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE
- */
-PRIVATE BOOL
-ixNpeDlImageMgrImageIdCompare (
- IxNpeDlImageId *imageIdA,
- IxNpeDlImageId *imageIdB)
-{
- if ((imageIdA->npeId == imageIdB->npeId) &&
- (imageIdA->functionalityId == imageIdB->functionalityId) &&
- (imageIdA->major == imageIdB->major) &&
- (imageIdA->minor == imageIdB->minor))
- {
- return true;
- }
- else
- {
- return false;
- }
-}
-
-/*
- * Function definition: ixNpeDlImageMgrNpeFunctionIdCompare
- *
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE
- */
-PRIVATE BOOL
-ixNpeDlImageMgrNpeFunctionIdCompare (
- IxNpeDlImageId *imageIdA,
- IxNpeDlImageId *imageIdB)
-{
- if ((imageIdA->npeId == imageIdB->npeId) &&
- (imageIdA->functionalityId == imageIdB->functionalityId))
- {
- return true;
- }
- else
- {
- return false;
- }
-}
-
-
-/*
- * Function definition: ixNpeDlImageMgrStatsShow
- */
-void
-ixNpeDlImageMgrStatsShow (void)
-{
- ixOsalLog (IX_OSAL_LOG_LVL_USER,
- IX_OSAL_LOG_DEV_STDOUT,
- "\nixNpeDlImageMgrStatsShow:\n"
- "\tInvalid Image Signatures: %u\n"
- "\tImage Id List capacity too small: %u\n"
- "\tImage Id not found: %u\n\n",
- ixNpeDlImageMgrStats.invalidSignature,
- ixNpeDlImageMgrStats.imageIdListOverflow,
- ixNpeDlImageMgrStats.imageIdNotFound,
- 0,0,0);
-}
-
-
-/*
- * Function definition: ixNpeDlImageMgrStatsReset
- */
-void
-ixNpeDlImageMgrStatsReset (void)
-{
- ixNpeDlImageMgrStats.invalidSignature = 0;
- ixNpeDlImageMgrStats.imageIdListOverflow = 0;
- ixNpeDlImageMgrStats.imageIdNotFound = 0;
-}
-
-
-#if 0
-/*
- * Function definition: ixNpeDlImageMgrImageFind_legacy
- *
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE
- */
-PRIVATE IX_STATUS
-ixNpeDlImageMgrImageFind_legacy (
- UINT32 *imageLibrary,
- UINT32 imageId,
- UINT32 **imagePtr,
- UINT32 *imageSize)
-{
- UINT32 imageOffset;
- /* used to index image entries in image library header */
- UINT32 imageCount = 0;
- IX_STATUS status = IX_FAIL;
- IxNpeDlImageMgrImageLibraryHeader *header;
- BOOL imageFound = false;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlImageMgrImageFind\n");
-
-
- /* If user didn't specify a library to use, use the default
- * one from IxNpeMicrocode.h
- */
- if (imageLibrary == NULL)
- {
- imageLibrary = IxNpeMicroCodeImageLibrary;
- }
-
- if (ixNpeDlImageMgrSignatureCheck (imageLibrary))
- {
- header = (IxNpeDlImageMgrImageLibraryHeader *) imageLibrary;
-
- /* for each image entry in the image library header ... */
- while ((header->entry[imageCount].eohMarker !=
- IX_NPEDL_IMAGEMGR_END_OF_HEADER) && !(imageFound))
- {
- /* if a match for imageId is found in the image library header... */
- if (imageId == header->entry[imageCount].image.id)
- {
- /*
- * get pointer to the image in the image library using offset from
- * 1st word in image library
- */
- imageOffset = header->entry[imageCount].image.offset;
- *imagePtr = &imageLibrary[imageOffset];
- /* get the image size */
- *imageSize = header->entry[imageCount].image.size;
- status = IX_SUCCESS;
- imageFound = true;
- }
- imageCount++;
- }
- if (status != IX_SUCCESS)
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageFind: "
- "imageId not found in image library header\n");
- ixNpeDlImageMgrStats.imageIdNotFound++;
- }
- }
- else
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageFind: "
- "invalid signature in image library\n");
- }
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlImageMgrImageFind: status = %d\n", status);
- return status;
-}
-#endif
-
-/*
- * Function definition: ixNpeDlImageMgrImageFind
- */
-IX_STATUS
-ixNpeDlImageMgrImageFind (
- UINT32 *imageLibrary,
- UINT32 imageId,
- UINT32 **imagePtr,
- UINT32 *imageSize)
-{
- IxNpeDlImageMgrImageHeader *image;
- UINT32 offset = 0;
-
- /* If user didn't specify a library to use, use the default
- * one from IxNpeMicrocode.h
- */
- if (imageLibrary == NULL)
- {
-#ifdef IX_NPEDL_READ_MICROCODE_FROM_FILE
- if (ixNpeMicrocode_binaryArray == NULL)
- {
- printk (KERN_ERR "ixp400.o: ERROR, no Microcode found in memory\n");
- return IX_FAIL;
- }
- else
- {
- imageLibrary = ixNpeMicrocode_binaryArray;
- }
-#else
- imageLibrary = getIxNpeMicroCodeImageLibrary();
- if (imageLibrary == NULL)
- {
- printf ("npe: ERROR, no Microcode found in memory\n");
- return IX_FAIL;
- }
-#endif /* IX_NPEDL_READ_MICROCODE_FROM_FILE */
- }
-
-#if 0
- /* For backward's compatibility with previous image format */
- if (ixNpeDlImageMgrSignatureCheck(imageLibrary))
- {
- return ixNpeDlImageMgrImageFind_legacy(imageLibrary,
- imageId,
- imagePtr,
- imageSize);
- }
-#endif
-
- while (*(imageLibrary+offset) == NPE_IMAGE_MARKER)
- {
- image = (IxNpeDlImageMgrImageHeader *)(imageLibrary+offset);
- offset += sizeof(IxNpeDlImageMgrImageHeader)/sizeof(UINT32);
-
- if (image->id == imageId)
- {
- *imagePtr = imageLibrary + offset;
- *imageSize = image->size;
- return IX_SUCCESS;
- }
- /* 2 consecutive NPE_IMAGE_MARKER's indicates end of library */
- else if (image->id == NPE_IMAGE_MARKER)
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageFind: "
- "imageId not found in image library header\n");
- ixNpeDlImageMgrStats.imageIdNotFound++;
- /* reached end of library, image not found */
- return IX_FAIL;
- }
- offset += image->size;
- }
-
- /* If we get here, our image library may be corrupted */
- IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageFind: "
- "image library format may be invalid or corrupted\n");
- return IX_FAIL;
-}
-
+++ /dev/null
-/**
- * @file IxNpeDlNpeMgr.c
- *
- * @author Intel Corporation
- * @date 09 January 2002
- *
- * @brief This file contains the implementation of the private API for the
- * IXP425 NPE Downloader NpeMgr module
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-
-/*
- * Put the user defined include files required.
- */
-#include "IxOsal.h"
-#include "IxNpeDl.h"
-#include "IxNpeDlNpeMgr_p.h"
-#include "IxNpeDlNpeMgrUtils_p.h"
-#include "IxNpeDlNpeMgrEcRegisters_p.h"
-#include "IxNpeDlMacros_p.h"
-#include "IxFeatureCtrl.h"
-
-/*
- * #defines and macros used in this file.
- */
-#define IX_NPEDL_BYTES_PER_WORD 4
-
-/* used to read download map from version in microcode image */
-#define IX_NPEDL_BLOCK_TYPE_INSTRUCTION 0x00000000
-#define IX_NPEDL_BLOCK_TYPE_DATA 0x00000001
-#define IX_NPEDL_BLOCK_TYPE_STATE 0x00000002
-#define IX_NPEDL_END_OF_DOWNLOAD_MAP 0x0000000F
-
-/*
- * masks used to extract address info from State information context
- * register addresses as read from microcode image
- */
-#define IX_NPEDL_MASK_STATE_ADDR_CTXT_REG 0x0000000F
-#define IX_NPEDL_MASK_STATE_ADDR_CTXT_NUM 0x000000F0
-
-/* LSB offset of Context Number field in State-Info Context Address */
-#define IX_NPEDL_OFFSET_STATE_ADDR_CTXT_NUM 4
-
-/* size (in words) of single State Information entry (ctxt reg address|data) */
-#define IX_NPEDL_STATE_INFO_ENTRY_SIZE 2
-
-
- #define IX_NPEDL_RESET_NPE_PARITY 0x0800
- #define IX_NPEDL_PARITY_BIT_MASK 0x3F00FFFF
- #define IX_NPEDL_CONFIG_CTRL_REG_MASK 0x3F3FFFFF
-
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-typedef struct
-{
- UINT32 type;
- UINT32 offset;
-} IxNpeDlNpeMgrDownloadMapBlockEntry;
-
-typedef union
-{
- IxNpeDlNpeMgrDownloadMapBlockEntry block;
- UINT32 eodmMarker;
-} IxNpeDlNpeMgrDownloadMapEntry;
-
-typedef struct
-{
- /* 1st entry in the download map (there may be more than one) */
- IxNpeDlNpeMgrDownloadMapEntry entry[1];
-} IxNpeDlNpeMgrDownloadMap;
-
-
-/* used to access an instruction or data block in a microcode image */
-typedef struct
-{
- UINT32 npeMemAddress;
- UINT32 size;
- UINT32 data[1];
-} IxNpeDlNpeMgrCodeBlock;
-
-/* used to access each Context Reg entry state-information block */
-typedef struct
-{
- UINT32 addressInfo;
- UINT32 value;
-} IxNpeDlNpeMgrStateInfoCtxtRegEntry;
-
-/* used to access a state-information block in a microcode image */
-typedef struct
-{
- UINT32 size;
- IxNpeDlNpeMgrStateInfoCtxtRegEntry ctxtRegEntry[1];
-} IxNpeDlNpeMgrStateInfoBlock;
-
-/* used to store some useful NPE information for easy access */
-typedef struct
-{
- UINT32 baseAddress;
- UINT32 insMemSize;
- UINT32 dataMemSize;
-} IxNpeDlNpeInfo;
-
-/* used to distinguish instruction and data memory operations */
-typedef enum
-{
- IX_NPEDL_MEM_TYPE_INSTRUCTION = 0,
- IX_NPEDL_MEM_TYPE_DATA
-} IxNpeDlNpeMemType;
-
-/* used to hold a reset value for a particular ECS register */
-typedef struct
-{
- UINT32 regAddr;
- UINT32 regResetVal;
-} IxNpeDlEcsRegResetValue;
-
-/* prototype of function to write either Instruction or Data memory */
-typedef IX_STATUS (*IxNpeDlNpeMgrMemWrite) (UINT32 npeBaseAddress,
- UINT32 npeMemAddress,
- UINT32 npeMemData,
- BOOL verify);
-
-/* module statistics counters */
-typedef struct
-{
- UINT32 instructionBlocksLoaded;
- UINT32 dataBlocksLoaded;
- UINT32 stateInfoBlocksLoaded;
- UINT32 criticalNpeErrors;
- UINT32 criticalMicrocodeErrors;
- UINT32 npeStarts;
- UINT32 npeStops;
- UINT32 npeResets;
-} IxNpeDlNpeMgrStats;
-
-
-/*
- * Variable declarations global to this file only. Externs are followed by
- * static variables.
- */
-static IxNpeDlNpeInfo ixNpeDlNpeInfo[] =
-{
- {
- 0,
- IX_NPEDL_INS_MEMSIZE_WORDS_NPEA,
- IX_NPEDL_DATA_MEMSIZE_WORDS_NPEA
- },
- {
- 0,
- IX_NPEDL_INS_MEMSIZE_WORDS_NPEB,
- IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB
- },
- {
- 0,
- IX_NPEDL_INS_MEMSIZE_WORDS_NPEC,
- IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC
- }
-};
-
-/* contains Reset values for Context Store Registers */
-static UINT32 ixNpeDlCtxtRegResetValues[] =
-{
- IX_NPEDL_CTXT_REG_RESET_STEVT,
- IX_NPEDL_CTXT_REG_RESET_STARTPC,
- IX_NPEDL_CTXT_REG_RESET_REGMAP,
- IX_NPEDL_CTXT_REG_RESET_CINDEX,
-};
-
-/* contains Reset values for Context Store Registers */
-static IxNpeDlEcsRegResetValue ixNpeDlEcsRegResetValues[] =
-{
- {IX_NPEDL_ECS_BG_CTXT_REG_0, IX_NPEDL_ECS_BG_CTXT_REG_0_RESET},
- {IX_NPEDL_ECS_BG_CTXT_REG_1, IX_NPEDL_ECS_BG_CTXT_REG_1_RESET},
- {IX_NPEDL_ECS_BG_CTXT_REG_2, IX_NPEDL_ECS_BG_CTXT_REG_2_RESET},
- {IX_NPEDL_ECS_PRI_1_CTXT_REG_0, IX_NPEDL_ECS_PRI_1_CTXT_REG_0_RESET},
- {IX_NPEDL_ECS_PRI_1_CTXT_REG_1, IX_NPEDL_ECS_PRI_1_CTXT_REG_1_RESET},
- {IX_NPEDL_ECS_PRI_1_CTXT_REG_2, IX_NPEDL_ECS_PRI_1_CTXT_REG_2_RESET},
- {IX_NPEDL_ECS_PRI_2_CTXT_REG_0, IX_NPEDL_ECS_PRI_2_CTXT_REG_0_RESET},
- {IX_NPEDL_ECS_PRI_2_CTXT_REG_1, IX_NPEDL_ECS_PRI_2_CTXT_REG_1_RESET},
- {IX_NPEDL_ECS_PRI_2_CTXT_REG_2, IX_NPEDL_ECS_PRI_2_CTXT_REG_2_RESET},
- {IX_NPEDL_ECS_DBG_CTXT_REG_0, IX_NPEDL_ECS_DBG_CTXT_REG_0_RESET},
- {IX_NPEDL_ECS_DBG_CTXT_REG_1, IX_NPEDL_ECS_DBG_CTXT_REG_1_RESET},
- {IX_NPEDL_ECS_DBG_CTXT_REG_2, IX_NPEDL_ECS_DBG_CTXT_REG_2_RESET},
- {IX_NPEDL_ECS_INSTRUCT_REG, IX_NPEDL_ECS_INSTRUCT_REG_RESET}
-};
-
-static IxNpeDlNpeMgrStats ixNpeDlNpeMgrStats;
-
-/* Set when NPE register memory has been mapped */
-static BOOL ixNpeDlMemInitialised = false;
-
-
-/*
- * static function prototypes.
- */
-PRIVATE IX_STATUS
-ixNpeDlNpeMgrMemLoad (IxNpeDlNpeId npeId, UINT32 npeBaseAddress,
- IxNpeDlNpeMgrCodeBlock *codeBlockPtr,
- BOOL verify, IxNpeDlNpeMemType npeMemType);
-PRIVATE IX_STATUS
-ixNpeDlNpeMgrStateInfoLoad (UINT32 npeBaseAddress,
- IxNpeDlNpeMgrStateInfoBlock *codeBlockPtr,
- BOOL verify);
-PRIVATE BOOL
-ixNpeDlNpeMgrBitsSetCheck (UINT32 npeBaseAddress, UINT32 regOffset,
- UINT32 expectedBitsSet);
-
-PRIVATE UINT32
-ixNpeDlNpeMgrBaseAddressGet (IxNpeDlNpeId npeId);
-
-/*
- * Function definition: ixNpeDlNpeMgrBaseAddressGet
- */
-PRIVATE UINT32
-ixNpeDlNpeMgrBaseAddressGet (IxNpeDlNpeId npeId)
-{
- IX_OSAL_ASSERT (ixNpeDlMemInitialised);
- return ixNpeDlNpeInfo[npeId].baseAddress;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrInit
- */
-void
-ixNpeDlNpeMgrInit (void)
-{
- /* Only map the memory once */
- if (!ixNpeDlMemInitialised)
- {
- UINT32 virtAddr;
-
- /* map the register memory for NPE-A */
- virtAddr = (UINT32) IX_OSAL_MEM_MAP (IX_NPEDL_NPEBASEADDRESS_NPEA,
- IX_OSAL_IXP400_NPEA_MAP_SIZE);
- IX_OSAL_ASSERT(virtAddr);
- ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEA].baseAddress = virtAddr;
-
- /* map the register memory for NPE-B */
- virtAddr = (UINT32) IX_OSAL_MEM_MAP (IX_NPEDL_NPEBASEADDRESS_NPEB,
- IX_OSAL_IXP400_NPEB_MAP_SIZE);
- IX_OSAL_ASSERT(virtAddr);
- ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEB].baseAddress = virtAddr;
-
- /* map the register memory for NPE-C */
- virtAddr = (UINT32) IX_OSAL_MEM_MAP (IX_NPEDL_NPEBASEADDRESS_NPEC,
- IX_OSAL_IXP400_NPEC_MAP_SIZE);
- IX_OSAL_ASSERT(virtAddr);
- ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEC].baseAddress = virtAddr;
-
- ixNpeDlMemInitialised = true;
- }
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrUninit
- */
-IX_STATUS
-ixNpeDlNpeMgrUninit (void)
-{
- if (!ixNpeDlMemInitialised)
- {
- return IX_FAIL;
- }
-
- IX_OSAL_MEM_UNMAP (ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEA].baseAddress);
- IX_OSAL_MEM_UNMAP (ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEB].baseAddress);
- IX_OSAL_MEM_UNMAP (ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEC].baseAddress);
-
- ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEA].baseAddress = 0;
- ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEB].baseAddress = 0;
- ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEC].baseAddress = 0;
-
- ixNpeDlMemInitialised = false;
-
- return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixNpeDlNpeMgrImageLoad
- */
-IX_STATUS
-ixNpeDlNpeMgrImageLoad (
- IxNpeDlNpeId npeId,
- UINT32 *imageCodePtr,
- BOOL verify)
-{
- UINT32 npeBaseAddress;
- IxNpeDlNpeMgrDownloadMap *downloadMap;
- UINT32 *blockPtr;
- UINT32 mapIndex = 0;
- IX_STATUS status = IX_SUCCESS;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlNpeMgrImageLoad\n");
-
- /* get base memory address of NPE from npeId */
- npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId);
-
- /* check execution status of NPE to verify NPE Stop was successful */
- if (!ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL,
- IX_NPEDL_EXCTL_STATUS_STOP))
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrImageDownload - "
- "NPE was not stopped before download\n");
- status = IX_FAIL;
- }
- else
- {
- /*
- * Read Download Map, checking each block type and calling
- * appropriate function to perform download
- */
- downloadMap = (IxNpeDlNpeMgrDownloadMap *) imageCodePtr;
- while ((downloadMap->entry[mapIndex].eodmMarker !=
- IX_NPEDL_END_OF_DOWNLOAD_MAP)
- && (status == IX_SUCCESS))
- {
- /* calculate pointer to block to be downloaded */
- blockPtr = imageCodePtr +
- downloadMap->entry[mapIndex].block.offset;
-
- switch (downloadMap->entry[mapIndex].block.type)
- {
- case IX_NPEDL_BLOCK_TYPE_INSTRUCTION:
- status = ixNpeDlNpeMgrMemLoad (npeId, npeBaseAddress,
- (IxNpeDlNpeMgrCodeBlock *)blockPtr,
- verify,
- IX_NPEDL_MEM_TYPE_INSTRUCTION);
- break;
- case IX_NPEDL_BLOCK_TYPE_DATA:
- status = ixNpeDlNpeMgrMemLoad (npeId, npeBaseAddress,
- (IxNpeDlNpeMgrCodeBlock *)blockPtr,
- verify, IX_NPEDL_MEM_TYPE_DATA);
- break;
- case IX_NPEDL_BLOCK_TYPE_STATE:
- status = ixNpeDlNpeMgrStateInfoLoad (npeBaseAddress,
- (IxNpeDlNpeMgrStateInfoBlock *) blockPtr,
- verify);
- break;
- default:
- IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrImageLoad: "
- "unknown block type in download map\n");
- status = IX_NPEDL_CRITICAL_MICROCODE_ERR;
- ixNpeDlNpeMgrStats.criticalMicrocodeErrors++;
- break;
- }
- mapIndex++;
- }/* loop: for each entry in download map, while status == SUCCESS */
- }/* condition: NPE stopped before attempting download */
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlNpeMgrImageLoad : status = %d\n",
- status);
- return status;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrMemLoad
- */
-PRIVATE IX_STATUS
-ixNpeDlNpeMgrMemLoad (
- IxNpeDlNpeId npeId,
- UINT32 npeBaseAddress,
- IxNpeDlNpeMgrCodeBlock *blockPtr,
- BOOL verify,
- IxNpeDlNpeMemType npeMemType)
-{
- UINT32 npeMemAddress;
- UINT32 blockSize;
- UINT32 memSize = 0;
- IxNpeDlNpeMgrMemWrite memWriteFunc = NULL;
- UINT32 localIndex = 0;
- IX_STATUS status = IX_SUCCESS;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlNpeMgrMemLoad\n");
-
- /*
- * select NPE EXCTL reg read/write commands depending on memory
- * type (instruction/data) to be accessed
- */
- if (npeMemType == IX_NPEDL_MEM_TYPE_INSTRUCTION)
- {
- memSize = ixNpeDlNpeInfo[npeId].insMemSize;
- memWriteFunc = (IxNpeDlNpeMgrMemWrite) ixNpeDlNpeMgrInsMemWrite;
- }
- else if (npeMemType == IX_NPEDL_MEM_TYPE_DATA)
- {
- memSize = ixNpeDlNpeInfo[npeId].dataMemSize;
- memWriteFunc = (IxNpeDlNpeMgrMemWrite) ixNpeDlNpeMgrDataMemWrite;
- }
-
- /*
- * NPE memory is loaded contiguously from each block, so only address
- * of 1st word in block is needed
- */
- npeMemAddress = blockPtr->npeMemAddress;
- /* number of words of instruction/data microcode in block to download */
- blockSize = blockPtr->size;
- if ((npeMemAddress + blockSize) > memSize)
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrMemLoad: "
- "Block size too big for NPE memory\n");
- status = IX_NPEDL_CRITICAL_MICROCODE_ERR;
- ixNpeDlNpeMgrStats.criticalMicrocodeErrors++;
- }
- else
- {
- for (localIndex = 0; localIndex < blockSize; localIndex++)
- {
- status = memWriteFunc (npeBaseAddress, npeMemAddress,
- blockPtr->data[localIndex], verify);
-
- if (status != IX_SUCCESS)
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrMemLoad: "
- "write to NPE memory failed\n");
- status = IX_NPEDL_CRITICAL_NPE_ERR;
- ixNpeDlNpeMgrStats.criticalNpeErrors++;
- break; /* abort download */
- }
- /* increment target (word)address in NPE memory */
- npeMemAddress++;
- }
- }/* condition: block size will fit in NPE memory */
-
- if (status == IX_SUCCESS)
- {
- if (npeMemType == IX_NPEDL_MEM_TYPE_INSTRUCTION)
- {
- ixNpeDlNpeMgrStats.instructionBlocksLoaded++;
- }
- else if (npeMemType == IX_NPEDL_MEM_TYPE_DATA)
- {
- ixNpeDlNpeMgrStats.dataBlocksLoaded++;
- }
- }
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlNpeMgrMemLoad : status = %d\n", status);
- return status;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrStateInfoLoad
- */
-PRIVATE IX_STATUS
-ixNpeDlNpeMgrStateInfoLoad (
- UINT32 npeBaseAddress,
- IxNpeDlNpeMgrStateInfoBlock *blockPtr,
- BOOL verify)
-{
- UINT32 blockSize;
- UINT32 ctxtRegAddrInfo;
- UINT32 ctxtRegVal;
- IxNpeDlCtxtRegNum ctxtReg; /* identifies Context Store reg (0-3) */
- UINT32 ctxtNum; /* identifies Context number (0-16) */
- UINT32 i;
- IX_STATUS status = IX_SUCCESS;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlNpeMgrStateInfoLoad\n");
-
- /* block size contains number of words of state-info in block */
- blockSize = blockPtr->size;
-
- ixNpeDlNpeMgrDebugInstructionPreExec (npeBaseAddress);
-
- /* for each state-info context register entry in block */
- for (i = 0; i < (blockSize/IX_NPEDL_STATE_INFO_ENTRY_SIZE); i++)
- {
- /* each state-info entry is 2 words (address, value) in length */
- ctxtRegAddrInfo = (blockPtr->ctxtRegEntry[i]).addressInfo;
- ctxtRegVal = (blockPtr->ctxtRegEntry[i]).value;
-
- ctxtReg = (ctxtRegAddrInfo & IX_NPEDL_MASK_STATE_ADDR_CTXT_REG);
- ctxtNum = (ctxtRegAddrInfo & IX_NPEDL_MASK_STATE_ADDR_CTXT_NUM) >>
- IX_NPEDL_OFFSET_STATE_ADDR_CTXT_NUM;
-
- /* error-check Context Register No. and Context Number values */
- /* NOTE that there is no STEVT register for Context 0 */
- if ((ctxtReg < 0) ||
- (ctxtReg >= IX_NPEDL_CTXT_REG_MAX) ||
- (ctxtNum > IX_NPEDL_CTXT_NUM_MAX) ||
- ((ctxtNum == 0) && (ctxtReg == IX_NPEDL_CTXT_REG_STEVT)))
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrStateInfoLoad: "
- "invalid Context Register Address\n");
- status = IX_NPEDL_CRITICAL_MICROCODE_ERR;
- ixNpeDlNpeMgrStats.criticalMicrocodeErrors++;
- break; /* abort download */
- }
-
- status = ixNpeDlNpeMgrCtxtRegWrite (npeBaseAddress, ctxtNum, ctxtReg,
- ctxtRegVal, verify);
- if (status != IX_SUCCESS)
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrStateInfoLoad: "
- "write of state-info to NPE failed\n");
- status = IX_NPEDL_CRITICAL_NPE_ERR;
- ixNpeDlNpeMgrStats.criticalNpeErrors++;
- break; /* abort download */
- }
- }/* loop: for each context reg entry in State Info block */
-
- ixNpeDlNpeMgrDebugInstructionPostExec (npeBaseAddress);
-
- if (status == IX_SUCCESS)
- {
- ixNpeDlNpeMgrStats.stateInfoBlocksLoaded++;
- }
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlNpeMgrStateInfoLoad : status = %d\n",
- status);
- return status;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrNpeReset
- */
-IX_STATUS
-ixNpeDlNpeMgrNpeReset (
- IxNpeDlNpeId npeId)
-{
- UINT32 npeBaseAddress;
- IxNpeDlCtxtRegNum ctxtReg; /* identifies Context Store reg (0-3) */
- UINT32 ctxtNum; /* identifies Context number (0-16) */
- UINT32 regAddr;
- UINT32 regVal;
- UINT32 localIndex;
- UINT32 indexMax;
- IX_STATUS status = IX_SUCCESS;
- IxFeatureCtrlReg unitFuseReg;
- UINT32 ixNpeConfigCtrlRegVal;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlNpeMgrNpeReset\n");
-
- /* get base memory address of NPE from npeId */
- npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId);
-
- /* pre-store the NPE Config Control Register Value */
- IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_CTL, &ixNpeConfigCtrlRegVal);
-
- ixNpeConfigCtrlRegVal |= 0x3F000000;
-
- /* disable the parity interrupt */
- IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_CTL, (ixNpeConfigCtrlRegVal & IX_NPEDL_PARITY_BIT_MASK));
-
- ixNpeDlNpeMgrDebugInstructionPreExec (npeBaseAddress);
-
- /*
- * clear the FIFOs
- */
- while (ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress,
- IX_NPEDL_REG_OFFSET_WFIFO,
- IX_NPEDL_MASK_WFIFO_VALID))
- {
- /* read from the Watch-point FIFO until empty */
- IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WFIFO,
- ®Val);
- }
-
- while (ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress,
- IX_NPEDL_REG_OFFSET_STAT,
- IX_NPEDL_MASK_STAT_OFNE))
- {
- /* read from the outFIFO until empty */
- IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_FIFO,
- ®Val);
- }
-
- while (ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress,
- IX_NPEDL_REG_OFFSET_STAT,
- IX_NPEDL_MASK_STAT_IFNE))
- {
- /*
- * step execution of the NPE intruction to read inFIFO using
- * the Debug Executing Context stack
- */
- status = ixNpeDlNpeMgrDebugInstructionExec (npeBaseAddress,
- IX_NPEDL_INSTR_RD_FIFO, 0, 0);
-
- if (IX_SUCCESS != status)
- {
- return status;
- }
-
- }
-
- /*
- * Reset the mailbox reg
- */
- /* ...from XScale side */
- IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_MBST,
- IX_NPEDL_REG_RESET_MBST);
- /* ...from NPE side */
- status = ixNpeDlNpeMgrDebugInstructionExec (npeBaseAddress,
- IX_NPEDL_INSTR_RESET_MBOX, 0, 0);
-
- if (IX_SUCCESS != status)
- {
- return status;
- }
-
- /*
- * Reset the physical registers in the NPE register file:
- * Note: no need to save/restore REGMAP for Context 0 here
- * since all Context Store regs are reset in subsequent code
- */
- for (regAddr = 0;
- (regAddr < IX_NPEDL_TOTAL_NUM_PHYS_REG) && (status != IX_FAIL);
- regAddr++)
- {
- /* for each physical register in the NPE reg file, write 0 : */
- status = ixNpeDlNpeMgrPhysicalRegWrite (npeBaseAddress, regAddr,
- 0, true);
- if (status != IX_SUCCESS)
- {
- return status; /* abort reset */
- }
- }
-
-
- /*
- * Reset the context store:
- */
- for (ctxtNum = IX_NPEDL_CTXT_NUM_MIN;
- ctxtNum <= IX_NPEDL_CTXT_NUM_MAX; ctxtNum++)
- {
- /* set each context's Context Store registers to reset values: */
- for (ctxtReg = 0; ctxtReg < IX_NPEDL_CTXT_REG_MAX; ctxtReg++)
- {
- /* NOTE that there is no STEVT register for Context 0 */
- if (!((ctxtNum == 0) && (ctxtReg == IX_NPEDL_CTXT_REG_STEVT)))
- {
- regVal = ixNpeDlCtxtRegResetValues[ctxtReg];
- status = ixNpeDlNpeMgrCtxtRegWrite (npeBaseAddress, ctxtNum,
- ctxtReg, regVal, true);
- if (status != IX_SUCCESS)
- {
- return status; /* abort reset */
- }
- }
- }
- }
-
- ixNpeDlNpeMgrDebugInstructionPostExec (npeBaseAddress);
-
- /* write Reset values to Execution Context Stack registers */
- indexMax = sizeof (ixNpeDlEcsRegResetValues) /
- sizeof (IxNpeDlEcsRegResetValue);
- for (localIndex = 0; localIndex < indexMax; localIndex++)
- {
- regAddr = ixNpeDlEcsRegResetValues[localIndex].regAddr;
- regVal = ixNpeDlEcsRegResetValues[localIndex].regResetVal;
- ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, regAddr, regVal);
- }
-
- /* clear the profile counter */
- ixNpeDlNpeMgrCommandIssue (npeBaseAddress,
- IX_NPEDL_EXCTL_CMD_CLR_PROFILE_CNT);
-
- /* clear registers EXCT, AP0, AP1, AP2 and AP3 */
- for (regAddr = IX_NPEDL_REG_OFFSET_EXCT;
- regAddr <= IX_NPEDL_REG_OFFSET_AP3;
- regAddr += IX_NPEDL_BYTES_PER_WORD)
- {
- IX_NPEDL_REG_WRITE (npeBaseAddress, regAddr, 0);
- }
-
- /* Reset the Watch-count register */
- IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC, 0);
-
- /*
- * WR IXA00055043 - Remove IMEM Parity Introduced by NPE Reset Operation
- */
-
- /*
- * Call the feature control API to fused out and reset the NPE and its
- * coprocessor - to reset internal states and remove parity error
- */
- unitFuseReg = ixFeatureCtrlRead ();
- unitFuseReg |= (IX_NPEDL_RESET_NPE_PARITY << npeId);
- ixFeatureCtrlWrite (unitFuseReg);
-
- /* call the feature control API to un-fused and un-reset the NPE & COP */
- unitFuseReg &= (~(IX_NPEDL_RESET_NPE_PARITY << npeId));
- ixFeatureCtrlWrite (unitFuseReg);
-
- /*
- * Call NpeMgr function to stop the NPE again after the Feature Control
- * has unfused and Un-Reset the NPE and its associated Coprocessors
- */
- status = ixNpeDlNpeMgrNpeStop (npeId);
-
- /* restore NPE configuration bus Control Register - Parity Settings */
- IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_CTL,
- (ixNpeConfigCtrlRegVal & IX_NPEDL_CONFIG_CTRL_REG_MASK));
-
- ixNpeDlNpeMgrStats.npeResets++;
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlNpeMgrNpeReset : status = %d\n", status);
- return status;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrNpeStart
- */
-IX_STATUS
-ixNpeDlNpeMgrNpeStart (
- IxNpeDlNpeId npeId)
-{
- UINT32 npeBaseAddress;
- UINT32 ecsRegVal;
- BOOL npeRunning;
- IX_STATUS status = IX_SUCCESS;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlNpeMgrNpeStart\n");
-
- /* get base memory address of NPE from npeId */
- npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId);
-
- /*
- * ensure only Background Context Stack Level is Active by turning off
- * the Active bit in each of the other Executing Context Stack levels
- */
- ecsRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress,
- IX_NPEDL_ECS_PRI_1_CTXT_REG_0);
- ecsRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE;
- ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_PRI_1_CTXT_REG_0,
- ecsRegVal);
-
- ecsRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress,
- IX_NPEDL_ECS_PRI_2_CTXT_REG_0);
- ecsRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE;
- ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_PRI_2_CTXT_REG_0,
- ecsRegVal);
-
- ecsRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress,
- IX_NPEDL_ECS_DBG_CTXT_REG_0);
- ecsRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE;
- ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_0,
- ecsRegVal);
-
- /* clear the pipeline */
- ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE);
-
- /* start NPE execution by issuing command through EXCTL register on NPE */
- ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_START);
-
- /*
- * check execution status of NPE to verify NPE Start operation was
- * successful
- */
- npeRunning = ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress,
- IX_NPEDL_REG_OFFSET_EXCTL,
- IX_NPEDL_EXCTL_STATUS_RUN);
- if (npeRunning)
- {
- ixNpeDlNpeMgrStats.npeStarts++;
- }
- else
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrNpeStart: "
- "failed to start NPE execution\n");
- status = IX_FAIL;
- }
-
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlNpeMgrNpeStart : status = %d\n", status);
- return status;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrNpeStop
- */
-IX_STATUS
-ixNpeDlNpeMgrNpeStop (
- IxNpeDlNpeId npeId)
-{
- UINT32 npeBaseAddress;
- IX_STATUS status = IX_SUCCESS;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlNpeMgrNpeStop\n");
-
- /* get base memory address of NPE from npeId */
- npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId);
-
- /* stop NPE execution by issuing command through EXCTL register on NPE */
- ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_STOP);
-
- /* verify that NPE Stop was successful */
- if (! ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL,
- IX_NPEDL_EXCTL_STATUS_STOP))
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrNpeStop: "
- "failed to stop NPE execution\n");
- status = IX_FAIL;
- }
-
- ixNpeDlNpeMgrStats.npeStops++;
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlNpeMgrNpeStop : status = %d\n", status);
- return status;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrBitsSetCheck
- */
-PRIVATE BOOL
-ixNpeDlNpeMgrBitsSetCheck (
- UINT32 npeBaseAddress,
- UINT32 regOffset,
- UINT32 expectedBitsSet)
-{
- UINT32 regVal;
- IX_NPEDL_REG_READ (npeBaseAddress, regOffset, ®Val);
-
- return expectedBitsSet == (expectedBitsSet & regVal);
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrStatsShow
- */
-void
-ixNpeDlNpeMgrStatsShow (void)
-{
- ixOsalLog (IX_OSAL_LOG_LVL_USER,
- IX_OSAL_LOG_DEV_STDOUT,
- "\nixNpeDlNpeMgrStatsShow:\n"
- "\tInstruction Blocks loaded: %u\n"
- "\tData Blocks loaded: %u\n"
- "\tState Information Blocks loaded: %u\n"
- "\tCritical NPE errors: %u\n"
- "\tCritical Microcode errors: %u\n",
- ixNpeDlNpeMgrStats.instructionBlocksLoaded,
- ixNpeDlNpeMgrStats.dataBlocksLoaded,
- ixNpeDlNpeMgrStats.stateInfoBlocksLoaded,
- ixNpeDlNpeMgrStats.criticalNpeErrors,
- ixNpeDlNpeMgrStats.criticalMicrocodeErrors,
- 0);
-
- ixOsalLog (IX_OSAL_LOG_LVL_USER,
- IX_OSAL_LOG_DEV_STDOUT,
- "\tSuccessful NPE Starts: %u\n"
- "\tSuccessful NPE Stops: %u\n"
- "\tSuccessful NPE Resets: %u\n\n",
- ixNpeDlNpeMgrStats.npeStarts,
- ixNpeDlNpeMgrStats.npeStops,
- ixNpeDlNpeMgrStats.npeResets,
- 0,0,0);
-
- ixNpeDlNpeMgrUtilsStatsShow ();
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrStatsReset
- */
-void
-ixNpeDlNpeMgrStatsReset (void)
-{
- ixNpeDlNpeMgrStats.instructionBlocksLoaded = 0;
- ixNpeDlNpeMgrStats.dataBlocksLoaded = 0;
- ixNpeDlNpeMgrStats.stateInfoBlocksLoaded = 0;
- ixNpeDlNpeMgrStats.criticalNpeErrors = 0;
- ixNpeDlNpeMgrStats.criticalMicrocodeErrors = 0;
- ixNpeDlNpeMgrStats.npeStarts = 0;
- ixNpeDlNpeMgrStats.npeStops = 0;
- ixNpeDlNpeMgrStats.npeResets = 0;
-
- ixNpeDlNpeMgrUtilsStatsReset ();
-}
+++ /dev/null
-/**
- * @file IxNpeDlNpeMgrUtils.c
- *
- * @author Intel Corporation
- * @date 18 February 2002
- *
- * @brief This file contains the implementation of the private API for the
- * IXP425 NPE Downloader NpeMgr Utils module
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-
-/*
- * Put the system defined include files required.
- */
-#define IX_NPE_DL_MAX_NUM_OF_RETRIES 1000000 /**< Maximum number of
- * retries before
- * timeout
- */
-
-/*
- * Put the user defined include files required.
- */
-#include "IxOsal.h"
-#include "IxNpeDl.h"
-#include "IxNpeDlNpeMgrUtils_p.h"
-#include "IxNpeDlNpeMgrEcRegisters_p.h"
-#include "IxNpeDlMacros_p.h"
-
-/*
- * #defines and macros used in this file.
- */
-
-/* used to bit-mask a number of bytes */
-#define IX_NPEDL_MASK_LOWER_BYTE_OF_WORD 0x000000FF
-#define IX_NPEDL_MASK_LOWER_SHORT_OF_WORD 0x0000FFFF
-#define IX_NPEDL_MASK_FULL_WORD 0xFFFFFFFF
-
-#define IX_NPEDL_BYTES_PER_WORD 4
-#define IX_NPEDL_BYTES_PER_SHORT 2
-
-#define IX_NPEDL_REG_SIZE_BYTE 8
-#define IX_NPEDL_REG_SIZE_SHORT 16
-#define IX_NPEDL_REG_SIZE_WORD 32
-
-/*
- * Introduce extra read cycles after issuing read command to NPE
- * so that we read the register after the NPE has updated it
- * This is to overcome race condition between XScale and NPE
- */
-#define IX_NPEDL_DELAY_READ_CYCLES 2
-/*
- * To mask top three MSBs of 32bit word to download into NPE IMEM
- */
-#define IX_NPEDL_MASK_UNUSED_IMEM_BITS 0x1FFFFFFF;
-
-
-/*
- * typedefs
- */
-typedef struct
-{
- UINT32 regAddress;
- UINT32 regSize;
-} IxNpeDlCtxtRegAccessInfo;
-
-/* module statistics counters */
-typedef struct
-{
- UINT32 insMemWrites;
- UINT32 insMemWriteFails;
- UINT32 dataMemWrites;
- UINT32 dataMemWriteFails;
- UINT32 ecsRegWrites;
- UINT32 ecsRegReads;
- UINT32 dbgInstructionExecs;
- UINT32 contextRegWrites;
- UINT32 physicalRegWrites;
- UINT32 nextPcWrites;
-} IxNpeDlNpeMgrUtilsStats;
-
-
-/*
- * Variable declarations global to this file only. Externs are followed by
- * static variables.
- */
-
-/*
- * contains useful address and function pointers to read/write Context Regs,
- * eliminating some switch or if-else statements in places
- */
-static IxNpeDlCtxtRegAccessInfo ixNpeDlCtxtRegAccInfo[IX_NPEDL_CTXT_REG_MAX] =
-{
- {
- IX_NPEDL_CTXT_REG_ADDR_STEVT,
- IX_NPEDL_REG_SIZE_BYTE
- },
- {
- IX_NPEDL_CTXT_REG_ADDR_STARTPC,
- IX_NPEDL_REG_SIZE_SHORT
- },
- {
- IX_NPEDL_CTXT_REG_ADDR_REGMAP,
- IX_NPEDL_REG_SIZE_SHORT
- },
- {
- IX_NPEDL_CTXT_REG_ADDR_CINDEX,
- IX_NPEDL_REG_SIZE_BYTE
- }
-};
-
-static UINT32 ixNpeDlSavedExecCount = 0;
-static UINT32 ixNpeDlSavedEcsDbgCtxtReg2 = 0;
-
-static IxNpeDlNpeMgrUtilsStats ixNpeDlNpeMgrUtilsStats;
-
-
-/*
- * static function prototypes.
- */
-PRIVATE __inline__ void
-ixNpeDlNpeMgrWriteCommandIssue (UINT32 npeBaseAddress, UINT32 cmd,
- UINT32 addr, UINT32 data);
-
-PRIVATE __inline__ UINT32
-ixNpeDlNpeMgrReadCommandIssue (UINT32 npeBaseAddress, UINT32 cmd, UINT32 addr);
-
-PRIVATE IX_STATUS
-ixNpeDlNpeMgrLogicalRegRead (UINT32 npeBaseAddress, UINT32 regAddr,
- UINT32 regSize, UINT32 ctxtNum, UINT32 *regVal);
-
-PRIVATE IX_STATUS
-ixNpeDlNpeMgrLogicalRegWrite (UINT32 npeBaseAddress, UINT32 regAddr,
- UINT32 regVal, UINT32 regSize,
- UINT32 ctxtNum, BOOL verify);
-
-/*
- * Function definition: ixNpeDlNpeMgrWriteCommandIssue
- */
-PRIVATE __inline__ void
-ixNpeDlNpeMgrWriteCommandIssue (
- UINT32 npeBaseAddress,
- UINT32 cmd,
- UINT32 addr,
- UINT32 data)
-{
- IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, data);
- IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXAD, addr);
- IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL, cmd);
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrReadCommandIssue
- */
-PRIVATE __inline__ UINT32
-ixNpeDlNpeMgrReadCommandIssue (
- UINT32 npeBaseAddress,
- UINT32 cmd,
- UINT32 addr)
-{
- UINT32 data = 0;
- int i;
-
- IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXAD, addr);
- IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL, cmd);
- for (i = 0; i <= IX_NPEDL_DELAY_READ_CYCLES; i++)
- {
- IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, &data);
- }
-
- return data;
-}
-
-/*
- * Function definition: ixNpeDlNpeMgrInsMemWrite
- */
-IX_STATUS
-ixNpeDlNpeMgrInsMemWrite (
- UINT32 npeBaseAddress,
- UINT32 insMemAddress,
- UINT32 insMemData,
- BOOL verify)
-{
- UINT32 insMemDataRtn;
-
- ixNpeDlNpeMgrWriteCommandIssue (npeBaseAddress,
- IX_NPEDL_EXCTL_CMD_WR_INS_MEM,
- insMemAddress, insMemData);
- if (verify)
- {
- /* write invalid data to this reg, so we can see if we're reading
- the EXDATA register too early */
- IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA,
- ~insMemData);
-
- /*Disabled since top 3 MSB are not used for Azusa hardware Refer WR:IXA00053900*/
- insMemData&=IX_NPEDL_MASK_UNUSED_IMEM_BITS;
-
- insMemDataRtn=ixNpeDlNpeMgrReadCommandIssue (npeBaseAddress,
- IX_NPEDL_EXCTL_CMD_RD_INS_MEM,
- insMemAddress);
-
- insMemDataRtn&=IX_NPEDL_MASK_UNUSED_IMEM_BITS;
-
- if (insMemData != insMemDataRtn)
- {
- ixNpeDlNpeMgrUtilsStats.insMemWriteFails++;
- return IX_FAIL;
- }
- }
-
- ixNpeDlNpeMgrUtilsStats.insMemWrites++;
- return IX_SUCCESS;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrDataMemWrite
- */
-IX_STATUS
-ixNpeDlNpeMgrDataMemWrite (
- UINT32 npeBaseAddress,
- UINT32 dataMemAddress,
- UINT32 dataMemData,
- BOOL verify)
-{
- ixNpeDlNpeMgrWriteCommandIssue (npeBaseAddress,
- IX_NPEDL_EXCTL_CMD_WR_DATA_MEM,
- dataMemAddress, dataMemData);
- if (verify)
- {
- /* write invalid data to this reg, so we can see if we're reading
- the EXDATA register too early */
- IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, ~dataMemData);
-
- if (dataMemData !=
- ixNpeDlNpeMgrReadCommandIssue (npeBaseAddress,
- IX_NPEDL_EXCTL_CMD_RD_DATA_MEM,
- dataMemAddress))
- {
- ixNpeDlNpeMgrUtilsStats.dataMemWriteFails++;
- return IX_FAIL;
- }
- }
-
- ixNpeDlNpeMgrUtilsStats.dataMemWrites++;
- return IX_SUCCESS;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrExecAccRegWrite
- */
-void
-ixNpeDlNpeMgrExecAccRegWrite (
- UINT32 npeBaseAddress,
- UINT32 regAddress,
- UINT32 regData)
-{
- ixNpeDlNpeMgrWriteCommandIssue (npeBaseAddress,
- IX_NPEDL_EXCTL_CMD_WR_ECS_REG,
- regAddress, regData);
- ixNpeDlNpeMgrUtilsStats.ecsRegWrites++;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrExecAccRegRead
- */
-UINT32
-ixNpeDlNpeMgrExecAccRegRead (
- UINT32 npeBaseAddress,
- UINT32 regAddress)
-{
- ixNpeDlNpeMgrUtilsStats.ecsRegReads++;
- return ixNpeDlNpeMgrReadCommandIssue (npeBaseAddress,
- IX_NPEDL_EXCTL_CMD_RD_ECS_REG,
- regAddress);
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrCommandIssue
- */
-void
-ixNpeDlNpeMgrCommandIssue (
- UINT32 npeBaseAddress,
- UINT32 command)
-{
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlNpeMgrCommandIssue\n");
-
- IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL, command);
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlNpeMgrCommandIssue\n");
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrDebugInstructionPreExec
- */
-void
-ixNpeDlNpeMgrDebugInstructionPreExec(
- UINT32 npeBaseAddress)
-{
- /* turn off the halt bit by clearing Execution Count register. */
- /* save reg contents 1st and restore later */
- IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCT,
- &ixNpeDlSavedExecCount);
- IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCT, 0);
-
- /* ensure that IF and IE are on (temporarily), so that we don't end up
- * stepping forever */
- ixNpeDlSavedEcsDbgCtxtReg2 = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress,
- IX_NPEDL_ECS_DBG_CTXT_REG_2);
-
- ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_2,
- (ixNpeDlSavedEcsDbgCtxtReg2 |
- IX_NPEDL_MASK_ECS_DBG_REG_2_IF |
- IX_NPEDL_MASK_ECS_DBG_REG_2_IE));
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrDebugInstructionExec
- */
-IX_STATUS
-ixNpeDlNpeMgrDebugInstructionExec(
- UINT32 npeBaseAddress,
- UINT32 npeInstruction,
- UINT32 ctxtNum,
- UINT32 ldur)
-{
- UINT32 ecsDbgRegVal;
- UINT32 oldWatchcount, newWatchcount;
- UINT32 retriesCount = 0;
- IX_STATUS status = IX_SUCCESS;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlNpeMgrDebugInstructionExec\n");
-
- /* set the Active bit, and the LDUR, in the debug level */
- ecsDbgRegVal = IX_NPEDL_MASK_ECS_REG_0_ACTIVE |
- (ldur << IX_NPEDL_OFFSET_ECS_REG_0_LDUR);
-
- ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_0,
- ecsDbgRegVal);
-
- /*
- * set CCTXT at ECS DEBUG L3 to specify in which context to execute the
- * instruction, and set SELCTXT at ECS DEBUG Level to specify which context
- * store to access.
- * Debug ECS Level Reg 1 has form 0x000n000n, where n = context number
- */
- ecsDbgRegVal = (ctxtNum << IX_NPEDL_OFFSET_ECS_REG_1_CCTXT) |
- (ctxtNum << IX_NPEDL_OFFSET_ECS_REG_1_SELCTXT);
-
- ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_1,
- ecsDbgRegVal);
-
- /* clear the pipeline */
- ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE);
-
- /* load NPE instruction into the instruction register */
- ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_INSTRUCT_REG,
- npeInstruction);
-
- /* we need this value later to wait for completion of NPE execution step */
- IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC, &oldWatchcount);
-
- /* issue a Step One command via the Execution Control register */
- ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_STEP);
-
- /* Watch Count register increments when NPE completes an instruction */
- IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC,
- &newWatchcount);
-
- /*
- * force the XScale to wait until the NPE has finished execution step
- * NOTE that this delay will be very small, just long enough to allow a
- * single NPE instruction to complete execution; if instruction execution
- * is not completed before timeout retries, exit the while loop
- */
- while ((IX_NPE_DL_MAX_NUM_OF_RETRIES > retriesCount)
- && (newWatchcount == oldWatchcount))
- {
- /* Watch Count register increments when NPE completes an instruction */
- IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC,
- &newWatchcount);
-
- retriesCount++;
- }
-
- if (IX_NPE_DL_MAX_NUM_OF_RETRIES > retriesCount)
- {
- ixNpeDlNpeMgrUtilsStats.dbgInstructionExecs++;
- }
- else
- {
- /* Return timeout status as the instruction has not been executed
- * after maximum retries */
- status = IX_NPEDL_CRITICAL_NPE_ERR;
- }
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlNpeMgrDebugInstructionExec\n");
-
- return status;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrDebugInstructionPostExec
- */
-void
-ixNpeDlNpeMgrDebugInstructionPostExec(
- UINT32 npeBaseAddress)
-{
- /* clear active bit in debug level */
- ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_0,
- 0);
-
- /* clear the pipeline */
- ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE);
-
- /* restore Execution Count register contents. */
- IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCT,
- ixNpeDlSavedExecCount);
-
- /* restore IF and IE bits to original values */
- ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_2,
- ixNpeDlSavedEcsDbgCtxtReg2);
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrLogicalRegRead
- */
-PRIVATE IX_STATUS
-ixNpeDlNpeMgrLogicalRegRead (
- UINT32 npeBaseAddress,
- UINT32 regAddr,
- UINT32 regSize,
- UINT32 ctxtNum,
- UINT32 *regVal)
-{
- IX_STATUS status = IX_SUCCESS;
- UINT32 npeInstruction = 0;
- UINT32 mask = 0;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlNpeMgrLogicalRegRead\n");
-
- switch (regSize)
- {
- case IX_NPEDL_REG_SIZE_BYTE:
- npeInstruction = IX_NPEDL_INSTR_RD_REG_BYTE;
- mask = IX_NPEDL_MASK_LOWER_BYTE_OF_WORD; break;
- case IX_NPEDL_REG_SIZE_SHORT:
- npeInstruction = IX_NPEDL_INSTR_RD_REG_SHORT;
- mask = IX_NPEDL_MASK_LOWER_SHORT_OF_WORD; break;
- case IX_NPEDL_REG_SIZE_WORD:
- npeInstruction = IX_NPEDL_INSTR_RD_REG_WORD;
- mask = IX_NPEDL_MASK_FULL_WORD; break;
- }
-
- /* make regAddr be the SRC and DEST operands (e.g. movX d0, d0) */
- npeInstruction |= (regAddr << IX_NPEDL_OFFSET_INSTR_SRC) |
- (regAddr << IX_NPEDL_OFFSET_INSTR_DEST);
-
- /* step execution of NPE intruction using Debug Executing Context stack */
- status = ixNpeDlNpeMgrDebugInstructionExec (npeBaseAddress, npeInstruction,
- ctxtNum, IX_NPEDL_RD_INSTR_LDUR);
-
- if (IX_SUCCESS != status)
- {
- return status;
- }
-
- /* read value of register from Execution Data register */
- IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, regVal);
-
- /* align value from left to right */
- *regVal = (*regVal >> (IX_NPEDL_REG_SIZE_WORD - regSize)) & mask;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlNpeMgrLogicalRegRead\n");
-
- return IX_SUCCESS;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrLogicalRegWrite
- */
-PRIVATE IX_STATUS
-ixNpeDlNpeMgrLogicalRegWrite (
- UINT32 npeBaseAddress,
- UINT32 regAddr,
- UINT32 regVal,
- UINT32 regSize,
- UINT32 ctxtNum,
- BOOL verify)
-{
- UINT32 npeInstruction = 0;
- UINT32 mask = 0;
- IX_STATUS status = IX_SUCCESS;
- UINT32 retRegVal;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlNpeMgrLogicalRegWrite\n");
-
- if (regSize == IX_NPEDL_REG_SIZE_WORD)
- {
- /* NPE register addressing is left-to-right: e.g. |d0|d1|d2|d3| */
- /* Write upper half-word (short) to |d0|d1| */
- status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress, regAddr,
- regVal >> IX_NPEDL_REG_SIZE_SHORT,
- IX_NPEDL_REG_SIZE_SHORT,
- ctxtNum, verify);
-
- if (IX_SUCCESS != status)
- {
- return status;
- }
-
- /* Write lower half-word (short) to |d2|d3| */
- status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress,
- regAddr + IX_NPEDL_BYTES_PER_SHORT,
- regVal & IX_NPEDL_MASK_LOWER_SHORT_OF_WORD,
- IX_NPEDL_REG_SIZE_SHORT,
- ctxtNum, verify);
-
- if (IX_SUCCESS != status)
- {
- return status;
- }
- }
- else
- {
- switch (regSize)
- {
- case IX_NPEDL_REG_SIZE_BYTE:
- npeInstruction = IX_NPEDL_INSTR_WR_REG_BYTE;
- mask = IX_NPEDL_MASK_LOWER_BYTE_OF_WORD; break;
- case IX_NPEDL_REG_SIZE_SHORT:
- npeInstruction = IX_NPEDL_INSTR_WR_REG_SHORT;
- mask = IX_NPEDL_MASK_LOWER_SHORT_OF_WORD; break;
- }
- /* mask out any redundant bits, so verify will work later */
- regVal &= mask;
-
- /* fill dest operand field of instruction with destination reg addr */
- npeInstruction |= (regAddr << IX_NPEDL_OFFSET_INSTR_DEST);
-
- /* fill src operand field of instruction with least-sig 5 bits of val*/
- npeInstruction |= ((regVal & IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA) <<
- IX_NPEDL_OFFSET_INSTR_SRC);
-
- /* fill coprocessor field of instruction with most-sig 11 bits of val*/
- npeInstruction |= ((regVal & IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA) <<
- IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA);
-
- /* step execution of NPE intruction using Debug ECS */
- status = ixNpeDlNpeMgrDebugInstructionExec(npeBaseAddress, npeInstruction,
- ctxtNum, IX_NPEDL_WR_INSTR_LDUR);
-
- if (IX_SUCCESS != status)
- {
- return status;
- }
- }/* condition: if reg to be written is 8-bit or 16-bit (not 32-bit) */
-
- if (verify)
- {
- status = ixNpeDlNpeMgrLogicalRegRead (npeBaseAddress, regAddr,
- regSize, ctxtNum, &retRegVal);
-
- if (IX_SUCCESS == status)
- {
- if (regVal != retRegVal)
- {
- status = IX_FAIL;
- }
- }
- }
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlNpeMgrLogicalRegWrite : status = %d\n",
- status);
-
- return status;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrPhysicalRegWrite
- */
-IX_STATUS
-ixNpeDlNpeMgrPhysicalRegWrite (
- UINT32 npeBaseAddress,
- UINT32 regAddr,
- UINT32 regValue,
- BOOL verify)
-{
- IX_STATUS status;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlNpeMgrPhysicalRegWrite\n");
-
-/*
- * There are 32 physical registers used in an NPE. These are
- * treated as 16 pairs of 32-bit registers. To write one of the pair,
- * write the pair number (0-16) to the REGMAP for Context 0. Then write
- * the value to register 0 or 4 in the regfile, depending on which
- * register of the pair is to be written
- */
-
- /*
- * set REGMAP for context 0 to (regAddr >> 1) to choose which pair (0-16)
- * of physical registers to write
- */
- status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress,
- IX_NPEDL_CTXT_REG_ADDR_REGMAP,
- (regAddr >>
- IX_NPEDL_OFFSET_PHYS_REG_ADDR_REGMAP),
- IX_NPEDL_REG_SIZE_SHORT, 0, verify);
- if (status == IX_SUCCESS)
- {
- /* regAddr = 0 or 4 */
- regAddr = (regAddr & IX_NPEDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR) *
- IX_NPEDL_BYTES_PER_WORD;
-
- status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress, regAddr, regValue,
- IX_NPEDL_REG_SIZE_WORD, 0, verify);
- }
-
- if (status != IX_SUCCESS)
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrPhysicalRegWrite: "
- "error writing to physical register\n");
- }
-
- ixNpeDlNpeMgrUtilsStats.physicalRegWrites++;
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlNpeMgrPhysicalRegWrite : status = %d\n",
- status);
- return status;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrCtxtRegWrite
- */
-IX_STATUS
-ixNpeDlNpeMgrCtxtRegWrite (
- UINT32 npeBaseAddress,
- UINT32 ctxtNum,
- IxNpeDlCtxtRegNum ctxtReg,
- UINT32 ctxtRegVal,
- BOOL verify)
-{
- UINT32 tempRegVal;
- UINT32 ctxtRegAddr;
- UINT32 ctxtRegSize;
- IX_STATUS status = IX_SUCCESS;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlNpeMgrCtxtRegWrite\n");
-
- /*
- * Context 0 has no STARTPC. Instead, this value is used to set
- * NextPC for Background ECS, to set where NPE starts executing code
- */
- if ((ctxtNum == 0) && (ctxtReg == IX_NPEDL_CTXT_REG_STARTPC))
- {
- /* read BG_CTXT_REG_0, update NEXTPC bits, and write back to reg */
- tempRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress,
- IX_NPEDL_ECS_BG_CTXT_REG_0);
- tempRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_NEXTPC;
- tempRegVal |= (ctxtRegVal << IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC) &
- IX_NPEDL_MASK_ECS_REG_0_NEXTPC;
-
- ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress,
- IX_NPEDL_ECS_BG_CTXT_REG_0, tempRegVal);
-
- ixNpeDlNpeMgrUtilsStats.nextPcWrites++;
- }
- else
- {
- ctxtRegAddr = ixNpeDlCtxtRegAccInfo[ctxtReg].regAddress;
- ctxtRegSize = ixNpeDlCtxtRegAccInfo[ctxtReg].regSize;
- status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress, ctxtRegAddr,
- ctxtRegVal, ctxtRegSize,
- ctxtNum, verify);
- if (status != IX_SUCCESS)
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrCtxtRegWrite: "
- "error writing to context store register\n");
- }
-
- ixNpeDlNpeMgrUtilsStats.contextRegWrites++;
- }
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlNpeMgrCtxtRegWrite : status = %d\n",
- status);
-
- return status;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrUtilsStatsShow
- */
-void
-ixNpeDlNpeMgrUtilsStatsShow (void)
-{
- ixOsalLog (IX_OSAL_LOG_LVL_USER,
- IX_OSAL_LOG_DEV_STDOUT,
- "\nixNpeDlNpeMgrUtilsStatsShow:\n"
- "\tInstruction Memory writes: %u\n"
- "\tInstruction Memory writes failed: %u\n"
- "\tData Memory writes: %u\n"
- "\tData Memory writes failed: %u\n",
- ixNpeDlNpeMgrUtilsStats.insMemWrites,
- ixNpeDlNpeMgrUtilsStats.insMemWriteFails,
- ixNpeDlNpeMgrUtilsStats.dataMemWrites,
- ixNpeDlNpeMgrUtilsStats.dataMemWriteFails,
- 0,0);
-
- ixOsalLog (IX_OSAL_LOG_LVL_USER,
- IX_OSAL_LOG_DEV_STDOUT,
- "\tExecuting Context Stack Register writes: %u\n"
- "\tExecuting Context Stack Register reads: %u\n"
- "\tPhysical Register writes: %u\n"
- "\tContext Store Register writes: %u\n"
- "\tExecution Backgound Context NextPC writes: %u\n"
- "\tDebug Instructions Executed: %u\n\n",
- ixNpeDlNpeMgrUtilsStats.ecsRegWrites,
- ixNpeDlNpeMgrUtilsStats.ecsRegReads,
- ixNpeDlNpeMgrUtilsStats.physicalRegWrites,
- ixNpeDlNpeMgrUtilsStats.contextRegWrites,
- ixNpeDlNpeMgrUtilsStats.nextPcWrites,
- ixNpeDlNpeMgrUtilsStats.dbgInstructionExecs);
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrUtilsStatsReset
- */
-void
-ixNpeDlNpeMgrUtilsStatsReset (void)
-{
- ixNpeDlNpeMgrUtilsStats.insMemWrites = 0;
- ixNpeDlNpeMgrUtilsStats.insMemWriteFails = 0;
- ixNpeDlNpeMgrUtilsStats.dataMemWrites = 0;
- ixNpeDlNpeMgrUtilsStats.dataMemWriteFails = 0;
- ixNpeDlNpeMgrUtilsStats.ecsRegWrites = 0;
- ixNpeDlNpeMgrUtilsStats.ecsRegReads = 0;
- ixNpeDlNpeMgrUtilsStats.physicalRegWrites = 0;
- ixNpeDlNpeMgrUtilsStats.contextRegWrites = 0;
- ixNpeDlNpeMgrUtilsStats.nextPcWrites = 0;
- ixNpeDlNpeMgrUtilsStats.dbgInstructionExecs = 0;
-}
+++ /dev/null
-/**
- * @file IxNpeMh.c
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the implementation of the public API for the
- * IXP425 NPE Message Handler component.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * Put the system defined include files required.
- */
-
-/*
- * Put the user defined include files required.
- */
-
-#include "IxOsal.h"
-#include "IxNpeMhMacros_p.h"
-
-#include "IxNpeMh.h"
-
-#include "IxNpeMhConfig_p.h"
-#include "IxNpeMhReceive_p.h"
-#include "IxNpeMhSend_p.h"
-#include "IxNpeMhSolicitedCbMgr_p.h"
-#include "IxNpeMhUnsolicitedCbMgr_p.h"
-
-/*
- * #defines and macros used in this file.
- */
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/*
- * Variable declarations global to this file only. Externs are followed by
- * static variables.
- */
-
-PRIVATE BOOL ixNpeMhInitialized = false;
-
-/*
- * Extern function prototypes.
- */
-
-/*
- * Static function prototypes.
- */
-
-/*
- * Function definition: ixNpeMhInitialize
- */
-
-PUBLIC IX_STATUS ixNpeMhInitialize (
- IxNpeMhNpeInterrupts npeInterrupts)
-{
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhInitialize\n");
-
- /* check the npeInterrupts parameter */
- if ((npeInterrupts != IX_NPEMH_NPEINTERRUPTS_NO) &&
- (npeInterrupts != IX_NPEMH_NPEINTERRUPTS_YES))
- {
- IX_NPEMH_ERROR_REPORT ("Illegal npeInterrupts parameter value\n");
- return IX_FAIL;
- }
-
- /* parameters are ok ... */
-
- /* initialize the Receive module */
- ixNpeMhReceiveInitialize ();
-
- /* initialize the Solicited Callback Manager module */
- ixNpeMhSolicitedCbMgrInitialize ();
-
- /* initialize the Unsolicited Callback Manager module */
- ixNpeMhUnsolicitedCbMgrInitialize ();
-
- /* initialize the Configuration module
- *
- * NOTE: This module was originally configured before the
- * others, but the sequence was changed so that interrupts
- * would only be enabled after the handler functions were
- * set up. The above modules need to be initialised to
- * handle the NPE interrupts. See SCR #2231.
- */
- ixNpeMhConfigInitialize (npeInterrupts);
-
- ixNpeMhInitialized = true;
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhInitialize\n");
-
- return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixNpeMhUnload
- */
-
-PUBLIC IX_STATUS ixNpeMhUnload (void)
-{
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhUnload\n");
-
- if (!ixNpeMhInitialized)
- {
- return IX_FAIL;
- }
-
- /* Uninitialize the Configuration module */
- ixNpeMhConfigUninit ();
-
- ixNpeMhInitialized = false;
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhUnload\n");
-
- return IX_SUCCESS;
-}
-
-
-/*
- * Function definition: ixNpeMhUnsolicitedCallbackRegister
- */
-
-PUBLIC IX_STATUS ixNpeMhUnsolicitedCallbackRegister (
- IxNpeMhNpeId npeId,
- IxNpeMhMessageId messageId,
- IxNpeMhCallback unsolicitedCallback)
-{
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhUnsolicitedCallbackRegister\n");
-
- /* check that we are initialized */
- if (!ixNpeMhInitialized)
- {
- IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n");
- return IX_FAIL;
- }
-
- /* check the npeId parameter */
- if (!ixNpeMhConfigNpeIdIsValid (npeId))
- {
- IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n");
- return IX_FAIL;
- }
-
- /* check the messageId parameter */
- if ((messageId < IX_NPEMH_MIN_MESSAGE_ID)
- || (messageId > IX_NPEMH_MAX_MESSAGE_ID))
- {
- IX_NPEMH_ERROR_REPORT ("Message ID is out of range\n");
- return IX_FAIL;
- }
-
- /* the unsolicitedCallback parameter is allowed to be NULL */
-
- /* parameters are ok ... */
-
- /* get the lock to prevent other clients from entering */
- ixNpeMhConfigLockGet (npeId);
-
- /* save the unsolicited callback for the message ID */
- ixNpeMhUnsolicitedCbMgrCallbackSave (
- npeId, messageId, unsolicitedCallback);
-
- /* release the lock to allow other clients back in */
- ixNpeMhConfigLockRelease (npeId);
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhUnsolicitedCallbackRegister\n");
-
- return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixNpeMhUnsolicitedCallbackForRangeRegister
- */
-
-PUBLIC IX_STATUS ixNpeMhUnsolicitedCallbackForRangeRegister (
- IxNpeMhNpeId npeId,
- IxNpeMhMessageId minMessageId,
- IxNpeMhMessageId maxMessageId,
- IxNpeMhCallback unsolicitedCallback)
-{
- IxNpeMhMessageId messageId;
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhUnsolicitedCallbackForRangeRegister\n");
-
- /* check that we are initialized */
- if (!ixNpeMhInitialized)
- {
- IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n");
- return IX_FAIL;
- }
-
- /* check the npeId parameter */
- if (!ixNpeMhConfigNpeIdIsValid (npeId))
- {
- IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n");
- return IX_FAIL;
- }
-
- /* check the minMessageId parameter */
- if ((minMessageId < IX_NPEMH_MIN_MESSAGE_ID)
- || (minMessageId > IX_NPEMH_MAX_MESSAGE_ID))
- {
- IX_NPEMH_ERROR_REPORT ("Min message ID is out of range\n");
- return IX_FAIL;
- }
-
- /* check the maxMessageId parameter */
- if ((maxMessageId < IX_NPEMH_MIN_MESSAGE_ID)
- || (maxMessageId > IX_NPEMH_MAX_MESSAGE_ID))
- {
- IX_NPEMH_ERROR_REPORT ("Max message ID is out of range\n");
- return IX_FAIL;
- }
-
- /* check the semantics of the message range parameters */
- if (minMessageId > maxMessageId)
- {
- IX_NPEMH_ERROR_REPORT ("Min message ID greater than max message "
- "ID\n");
- return IX_FAIL;
- }
-
- /* the unsolicitedCallback parameter is allowed to be NULL */
-
- /* parameters are ok ... */
-
- /* get the lock to prevent other clients from entering */
- ixNpeMhConfigLockGet (npeId);
-
- /* for each message ID in the range ... */
- for (messageId = minMessageId; messageId <= maxMessageId; messageId++)
- {
- /* save the unsolicited callback for the message ID */
- ixNpeMhUnsolicitedCbMgrCallbackSave (
- npeId, messageId, unsolicitedCallback);
- }
-
- /* release the lock to allow other clients back in */
- ixNpeMhConfigLockRelease (npeId);
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhUnsolicitedCallbackForRangeRegister\n");
-
- return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixNpeMhMessageSend
- */
-
-PUBLIC IX_STATUS ixNpeMhMessageSend (
- IxNpeMhNpeId npeId,
- IxNpeMhMessage message,
- UINT32 maxSendRetries)
-{
- IX_STATUS status = IX_SUCCESS;
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhMessageSend\n");
-
- /* check that we are initialized */
- if (!ixNpeMhInitialized)
- {
- IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n");
- return IX_FAIL;
- }
-
- /* check the npeId parameter */
- if (!ixNpeMhConfigNpeIdIsValid (npeId))
- {
- IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n");
- return IX_FAIL;
- }
-
- /* parameters are ok ... */
-
- /* get the lock to prevent other clients from entering */
- ixNpeMhConfigLockGet (npeId);
-
- /* send the message */
- status = ixNpeMhSendMessageSend (npeId, message, maxSendRetries);
- if (status != IX_SUCCESS)
- {
- IX_NPEMH_ERROR_REPORT ("Failed to send message\n");
- }
-
- /* release the lock to allow other clients back in */
- ixNpeMhConfigLockRelease (npeId);
-
- IX_NPEMH_TRACE1 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhMessageSend"
- " : status = %d\n", status);
-
- return status;
-}
-
-/*
- * Function definition: ixNpeMhMessageWithResponseSend
- */
-
-PUBLIC IX_STATUS ixNpeMhMessageWithResponseSend (
- IxNpeMhNpeId npeId,
- IxNpeMhMessage message,
- IxNpeMhMessageId solicitedMessageId,
- IxNpeMhCallback solicitedCallback,
- UINT32 maxSendRetries)
-{
- IX_STATUS status = IX_SUCCESS;
- IxNpeMhCallback unsolicitedCallback = NULL;
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhMessageWithResponseSend\n");
-
- /* check that we are initialized */
- if (!ixNpeMhInitialized)
- {
- IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n");
- return IX_FAIL;
- }
-
- /* the solicitecCallback parameter is allowed to be NULL. this */
- /* signifies the client is not interested in the response message */
-
- /* check the npeId parameter */
- if (!ixNpeMhConfigNpeIdIsValid (npeId))
- {
- IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n");
- return IX_FAIL;
- }
-
- /* check the solicitedMessageId parameter */
- if ((solicitedMessageId < IX_NPEMH_MIN_MESSAGE_ID)
- || (solicitedMessageId > IX_NPEMH_MAX_MESSAGE_ID))
- {
- IX_NPEMH_ERROR_REPORT ("Solicited message ID is out of range\n");
- return IX_FAIL;
- }
-
- /* check the solicitedMessageId parameter. if an unsolicited */
- /* callback has been registered for the specified message ID then */
- /* report an error and return failure */
- ixNpeMhUnsolicitedCbMgrCallbackRetrieve (
- npeId, solicitedMessageId, &unsolicitedCallback);
- if (unsolicitedCallback != NULL)
- {
- IX_NPEMH_ERROR_REPORT ("Solicited message ID conflicts with "
- "unsolicited message ID\n");
- return IX_FAIL;
- }
-
- /* parameters are ok ... */
-
- /* get the lock to prevent other clients from entering */
- ixNpeMhConfigLockGet (npeId);
-
- /* send the message */
- status = ixNpeMhSendMessageWithResponseSend (
- npeId, message, solicitedMessageId, solicitedCallback,
- maxSendRetries);
- if (status != IX_SUCCESS)
- {
- IX_NPEMH_ERROR_REPORT ("Failed to send message\n");
- }
-
- /* release the lock to allow other clients back in */
- ixNpeMhConfigLockRelease (npeId);
-
- IX_NPEMH_TRACE1 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhMessageWithResponseSend"
- " : status = %d\n", status);
-
- return status;
-}
-
-/*
- * Function definition: ixNpeMhMessagesReceive
- */
-
-PUBLIC IX_STATUS ixNpeMhMessagesReceive (
- IxNpeMhNpeId npeId)
-{
- IX_STATUS status = IX_SUCCESS;
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhMessagesReceive\n");
-
- /* check that we are initialized */
- if (!ixNpeMhInitialized)
- {
- IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n");
- return IX_FAIL;
- }
-
- /* check the npeId parameter */
- if (!ixNpeMhConfigNpeIdIsValid (npeId))
- {
- IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n");
- return IX_FAIL;
- }
-
- /* parameters are ok ... */
-
- /* get the lock to prevent other clients from entering */
- ixNpeMhConfigLockGet (npeId);
-
- /* receive messages from the NPE */
- status = ixNpeMhReceiveMessagesReceive (npeId);
-
- if (status != IX_SUCCESS)
- {
- IX_NPEMH_ERROR_REPORT ("Failed to receive message\n");
- }
-
- /* release the lock to allow other clients back in */
- ixNpeMhConfigLockRelease (npeId);
-
- IX_NPEMH_TRACE1 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhMessagesReceive"
- " : status = %d\n", status);
-
- return status;
-}
-
-/*
- * Function definition: ixNpeMhShow
- */
-
-PUBLIC IX_STATUS ixNpeMhShow (
- IxNpeMhNpeId npeId)
-{
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhShow\n");
-
- /* check that we are initialized */
- if (!ixNpeMhInitialized)
- {
- IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n");
- return IX_FAIL;
- }
-
- /* check the npeId parameter */
- if (!ixNpeMhConfigNpeIdIsValid (npeId))
- {
- IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n");
- return IX_FAIL;
- }
-
- /* parameters are ok ... */
-
- /* note we don't get the lock here as printing the statistics */
- /* to a console may take some time and we don't want to impact */
- /* system performance. this means that the statistics displayed */
- /* may be in a state of flux and make not represent a consistent */
- /* snapshot. */
-
- /* display a header */
- ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT,
- "Current state of NPE ID %d:\n\n", npeId, 0, 0, 0, 0, 0);
-
- /* show the current state of each module */
-
- /* show the current state of the Configuration module */
- ixNpeMhConfigShow (npeId);
-
- /* show the current state of the Receive module */
- ixNpeMhReceiveShow (npeId);
-
- /* show the current state of the Send module */
- ixNpeMhSendShow (npeId);
-
- /* show the current state of the Solicited Callback Manager module */
- ixNpeMhSolicitedCbMgrShow (npeId);
-
- /* show the current state of the Unsolicited Callback Manager module */
- ixNpeMhUnsolicitedCbMgrShow (npeId);
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhShow\n");
-
- return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixNpeMhShowReset
- */
-
-PUBLIC IX_STATUS ixNpeMhShowReset (
- IxNpeMhNpeId npeId)
-{
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhShowReset\n");
-
- /* check that we are initialized */
- if (!ixNpeMhInitialized)
- {
- IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n");
- return IX_FAIL;
- }
-
- /* check the npeId parameter */
- if (!ixNpeMhConfigNpeIdIsValid (npeId))
- {
- IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n");
- return IX_FAIL;
- }
-
- /* parameters are ok ... */
-
- /* note we don't get the lock here as resetting the statistics */
- /* shouldn't impact system performance. */
-
- /* reset the current state of each module */
-
- /* reset the current state of the Configuration module */
- ixNpeMhConfigShowReset (npeId);
-
- /* reset the current state of the Receive module */
- ixNpeMhReceiveShowReset (npeId);
-
- /* reset the current state of the Send module */
- ixNpeMhSendShowReset (npeId);
-
- /* reset the current state of the Solicited Callback Manager module */
- ixNpeMhSolicitedCbMgrShowReset (npeId);
-
- /* reset the current state of the Unsolicited Callback Manager module */
- ixNpeMhUnsolicitedCbMgrShowReset (npeId);
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhShowReset\n");
-
- return IX_SUCCESS;
-}
+++ /dev/null
-/**
- * @file IxNpeMhConfig.c
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the implementation of the private API for the
- * Configuration module.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * Put the system defined include files required.
- */
-
-
-/*
- * Put the user defined include files required.
- */
-
-#include "IxOsal.h"
-
-#include "IxNpeMhMacros_p.h"
-
-#include "IxNpeMhConfig_p.h"
-
-/*
- * #defines and macros used in this file.
- */
-#define IX_NPE_MH_MAX_NUM_OF_RETRIES 1000000 /**< Maximum number of
- * retries before
- * timeout
- */
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/**
- * @struct IxNpeMhConfigStats
- *
- * @brief This structure is used to maintain statistics for the
- * Configuration module.
- */
-
-typedef struct
-{
- UINT32 outFifoReads; /**< outFifo reads */
- UINT32 inFifoWrites; /**< inFifo writes */
- UINT32 maxInFifoFullRetries; /**< max retries if inFIFO full */
- UINT32 maxOutFifoEmptyRetries; /**< max retries if outFIFO empty */
-} IxNpeMhConfigStats;
-
-/*
- * Variable declarations global to this file only. Externs are followed by
- * static variables.
- */
-
-IxNpeMhConfigNpeInfo ixNpeMhConfigNpeInfo[IX_NPEMH_NUM_NPES] =
-{
- {
- 0,
- IX_NPEMH_NPEA_INT,
- 0,
- 0,
- 0,
- 0,
- 0,
- NULL,
- false
- },
- {
- 0,
- IX_NPEMH_NPEB_INT,
- 0,
- 0,
- 0,
- 0,
- 0,
- NULL,
- false
- },
- {
- 0,
- IX_NPEMH_NPEC_INT,
- 0,
- 0,
- 0,
- 0,
- 0,
- NULL,
- false
- }
-};
-
-PRIVATE IxNpeMhConfigStats ixNpeMhConfigStats[IX_NPEMH_NUM_NPES];
-
-/*
- * Extern function prototypes.
- */
-
-/*
- * Static function prototypes.
- */
-PRIVATE
-void ixNpeMhConfigIsr (void *parameter);
-
-/*
- * Function definition: ixNpeMhConfigIsr
- */
-
-PRIVATE
-void ixNpeMhConfigIsr (void *parameter)
-{
- IxNpeMhNpeId npeId = (IxNpeMhNpeId)parameter;
- UINT32 ofint;
- volatile UINT32 *statusReg =
- (UINT32 *)ixNpeMhConfigNpeInfo[npeId].statusRegister;
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhConfigIsr\n");
-
- /* get the OFINT (OutFifo interrupt) bit of the status register */
- IX_NPEMH_REGISTER_READ_BITS (statusReg, &ofint, IX_NPEMH_NPE_STAT_OFINT);
-
- /* if the OFINT status bit is set */
- if (ofint)
- {
- /* if there is an ISR registered for this NPE */
- if (ixNpeMhConfigNpeInfo[npeId].isr != NULL)
- {
- /* invoke the ISR routine */
- ixNpeMhConfigNpeInfo[npeId].isr (npeId);
- }
- else
- {
- /* if we don't service the interrupt the NPE will continue */
- /* to trigger the interrupt indefinitely */
- IX_NPEMH_ERROR_REPORT ("No ISR registered to service "
- "interrupt\n");
- }
- }
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhConfigIsr\n");
-}
-
-/*
- * Function definition: ixNpeMhConfigInitialize
- */
-
-void ixNpeMhConfigInitialize (
- IxNpeMhNpeInterrupts npeInterrupts)
-{
- IxNpeMhNpeId npeId;
- UINT32 virtualAddr[IX_NPEMH_NUM_NPES];
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhConfigInitialize\n");
-
- /* Request a mapping for the NPE-A config register address space */
- virtualAddr[IX_NPEMH_NPEID_NPEA] =
- (UINT32) IX_OSAL_MEM_MAP (IX_NPEMH_NPEA_BASE,
- IX_OSAL_IXP400_NPEA_MAP_SIZE);
- IX_OSAL_ASSERT (virtualAddr[IX_NPEMH_NPEID_NPEA]);
-
- /* Request a mapping for the NPE-B config register address space */
- virtualAddr[IX_NPEMH_NPEID_NPEB] =
- (UINT32) IX_OSAL_MEM_MAP (IX_NPEMH_NPEB_BASE,
- IX_OSAL_IXP400_NPEB_MAP_SIZE);
- IX_OSAL_ASSERT (virtualAddr[IX_NPEMH_NPEID_NPEB]);
-
- /* Request a mapping for the NPE-C config register address space */
- virtualAddr[IX_NPEMH_NPEID_NPEC] =
- (UINT32) IX_OSAL_MEM_MAP (IX_NPEMH_NPEC_BASE,
- IX_OSAL_IXP400_NPEC_MAP_SIZE);
- IX_OSAL_ASSERT (virtualAddr[IX_NPEMH_NPEID_NPEC]);
-
- /* for each NPE ... */
- for (npeId = 0; npeId < IX_NPEMH_NUM_NPES; npeId++)
- {
- /* declare a convenience pointer */
- IxNpeMhConfigNpeInfo *npeInfo = &ixNpeMhConfigNpeInfo[npeId];
-
- /* store the virtual addresses of the NPE registers for later use */
- npeInfo->virtualRegisterBase = virtualAddr[npeId];
- npeInfo->statusRegister = virtualAddr[npeId] + IX_NPEMH_NPESTAT_OFFSET;
- npeInfo->controlRegister = virtualAddr[npeId] + IX_NPEMH_NPECTL_OFFSET;
- npeInfo->inFifoRegister = virtualAddr[npeId] + IX_NPEMH_NPEFIFO_OFFSET;
- npeInfo->outFifoRegister = virtualAddr[npeId] + IX_NPEMH_NPEFIFO_OFFSET;
-
- /* for test purposes - to verify the register addresses */
- IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NPE %d status register = "
- "0x%08X\n", npeId, npeInfo->statusRegister);
- IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NPE %d control register = "
- "0x%08X\n", npeId, npeInfo->controlRegister);
- IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NPE %d inFifo register = "
- "0x%08X\n", npeId, npeInfo->inFifoRegister);
- IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NPE %d outFifo register = "
- "0x%08X\n", npeId, npeInfo->outFifoRegister);
-
- /* connect our ISR to the NPE interrupt */
- (void) ixOsalIrqBind (
- npeInfo->interruptId, ixNpeMhConfigIsr, (void *)npeId);
-
- /* initialise a mutex for this NPE */
- (void) ixOsalMutexInit (&npeInfo->mutex);
-
- /* if we should service the NPE's "outFIFO not empty" interrupt */
- if (npeInterrupts == IX_NPEMH_NPEINTERRUPTS_YES)
- {
- /* enable the NPE's "outFIFO not empty" interrupt */
- ixNpeMhConfigNpeInterruptEnable (npeId);
- }
- else
- {
- /* disable the NPE's "outFIFO not empty" interrupt */
- ixNpeMhConfigNpeInterruptDisable (npeId);
- }
- }
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhConfigInitialize\n");
-}
-
-/*
- * Function definition: ixNpeMhConfigUninit
- */
-
-void ixNpeMhConfigUninit (void)
-{
- IxNpeMhNpeId npeId;
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhConfigUninit\n");
-
- /* for each NPE ... */
- for (npeId = 0; npeId < IX_NPEMH_NUM_NPES; npeId++)
- {
- /* declare a convenience pointer */
- IxNpeMhConfigNpeInfo *npeInfo = &ixNpeMhConfigNpeInfo[npeId];
-
- /* disconnect ISR */
- ixOsalIrqUnbind(npeInfo->interruptId);
-
- /* destroy mutex associated with this NPE */
- ixOsalMutexDestroy(&npeInfo->mutex);
-
- IX_OSAL_MEM_UNMAP (npeInfo->virtualRegisterBase);
-
- npeInfo->virtualRegisterBase = 0;
- npeInfo->statusRegister = 0;
- npeInfo->controlRegister = 0;
- npeInfo->inFifoRegister = 0;
- npeInfo->outFifoRegister = 0;
- }
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhConfigUninit\n");
-}
-
-/*
- * Function definition: ixNpeMhConfigIsrRegister
- */
-
-void ixNpeMhConfigIsrRegister (
- IxNpeMhNpeId npeId,
- IxNpeMhConfigIsr isr)
-{
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhConfigIsrRegister\n");
-
- /* check if there is already an ISR registered for this NPE */
- if (ixNpeMhConfigNpeInfo[npeId].isr != NULL)
- {
- IX_NPEMH_TRACE0 (IX_NPEMH_DEBUG, "Over-writing registered NPE ISR\n");
- }
-
- /* save the ISR routine with the NPE info */
- ixNpeMhConfigNpeInfo[npeId].isr = isr;
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhConfigIsrRegister\n");
-}
-
-/*
- * Function definition: ixNpeMhConfigNpeInterruptEnable
- */
-
-BOOL ixNpeMhConfigNpeInterruptEnable (
- IxNpeMhNpeId npeId)
-{
- UINT32 ofe;
- volatile UINT32 *controlReg =
- (UINT32 *)ixNpeMhConfigNpeInfo[npeId].controlRegister;
-
- /* get the OFE (OutFifoEnable) bit of the control register */
- IX_NPEMH_REGISTER_READ_BITS (controlReg, &ofe, IX_NPEMH_NPE_CTL_OFE);
-
- /* if the interrupt is disabled then we must enable it */
- if (!ofe)
- {
- /* set the OFE (OutFifoEnable) bit of the control register */
- /* we must set the OFEWE (OutFifoEnableWriteEnable) at the same */
- /* time for the write to have effect */
- IX_NPEMH_REGISTER_WRITE_BITS (controlReg,
- (IX_NPEMH_NPE_CTL_OFE |
- IX_NPEMH_NPE_CTL_OFEWE),
- (IX_NPEMH_NPE_CTL_OFE |
- IX_NPEMH_NPE_CTL_OFEWE));
- }
-
- /* return the previous state of the interrupt */
- return (ofe != 0);
-}
-
-/*
- * Function definition: ixNpeMhConfigNpeInterruptDisable
- */
-
-BOOL ixNpeMhConfigNpeInterruptDisable (
- IxNpeMhNpeId npeId)
-{
- UINT32 ofe;
- volatile UINT32 *controlReg =
- (UINT32 *)ixNpeMhConfigNpeInfo[npeId].controlRegister;
-
- /* get the OFE (OutFifoEnable) bit of the control register */
- IX_NPEMH_REGISTER_READ_BITS (controlReg, &ofe, IX_NPEMH_NPE_CTL_OFE);
-
- /* if the interrupt is enabled then we must disable it */
- if (ofe)
- {
- /* unset the OFE (OutFifoEnable) bit of the control register */
- /* we must set the OFEWE (OutFifoEnableWriteEnable) at the same */
- /* time for the write to have effect */
- IX_NPEMH_REGISTER_WRITE_BITS (controlReg,
- (0 |
- IX_NPEMH_NPE_CTL_OFEWE),
- (IX_NPEMH_NPE_CTL_OFE |
- IX_NPEMH_NPE_CTL_OFEWE));
- }
-
- /* return the previous state of the interrupt */
- return (ofe != 0);
-}
-
-/*
- * Function definition: ixNpeMhConfigMessageIdGet
- */
-
-IxNpeMhMessageId ixNpeMhConfigMessageIdGet (
- IxNpeMhMessage message)
-{
- /* return the most-significant byte of the first word of the */
- /* message */
- return ((IxNpeMhMessageId) ((message.data[0] >> 24) & 0xFF));
-}
-
-/*
- * Function definition: ixNpeMhConfigNpeIdIsValid
- */
-
-BOOL ixNpeMhConfigNpeIdIsValid (
- IxNpeMhNpeId npeId)
-{
- /* check that the npeId parameter is within the range of valid IDs */
- return (npeId >= 0 && npeId < IX_NPEMH_NUM_NPES);
-}
-
-/*
- * Function definition: ixNpeMhConfigLockGet
- */
-
-void ixNpeMhConfigLockGet (
- IxNpeMhNpeId npeId)
-{
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhConfigLockGet\n");
-
- /* lock the mutex for this NPE */
- (void) ixOsalMutexLock (&ixNpeMhConfigNpeInfo[npeId].mutex,
- IX_OSAL_WAIT_FOREVER);
-
- /* disable the NPE's "outFIFO not empty" interrupt */
- ixNpeMhConfigNpeInfo[npeId].oldInterruptState =
- ixNpeMhConfigNpeInterruptDisable (npeId);
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhConfigLockGet\n");
-}
-
-/*
- * Function definition: ixNpeMhConfigLockRelease
- */
-
-void ixNpeMhConfigLockRelease (
- IxNpeMhNpeId npeId)
-{
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhConfigLockRelease\n");
-
- /* if the interrupt was previously enabled */
- if (ixNpeMhConfigNpeInfo[npeId].oldInterruptState)
- {
- /* enable the NPE's "outFIFO not empty" interrupt */
- ixNpeMhConfigNpeInfo[npeId].oldInterruptState =
- ixNpeMhConfigNpeInterruptEnable (npeId);
- }
-
- /* unlock the mutex for this NPE */
- (void) ixOsalMutexUnlock (&ixNpeMhConfigNpeInfo[npeId].mutex);
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhConfigLockRelease\n");
-}
-
-/*
- * Function definition: ixNpeMhConfigInFifoWrite
- */
-
-IX_STATUS ixNpeMhConfigInFifoWrite (
- IxNpeMhNpeId npeId,
- IxNpeMhMessage message)
-{
- volatile UINT32 *npeInFifo =
- (UINT32 *)ixNpeMhConfigNpeInfo[npeId].inFifoRegister;
- UINT32 retriesCount = 0;
-
- /* write the first word of the message to the NPE's inFIFO */
- IX_NPEMH_REGISTER_WRITE (npeInFifo, message.data[0]);
-
- /* need to wait for room to write second word - see SCR #493,
- poll for maximum number of retries, if exceed maximum
- retries, exit from while loop */
- while ((IX_NPE_MH_MAX_NUM_OF_RETRIES > retriesCount)
- && ixNpeMhConfigInFifoIsFull (npeId))
- {
- retriesCount++;
- }
-
- /* Return TIMEOUT status to caller, indicate that NPE Hang / Halt */
- if (IX_NPE_MH_MAX_NUM_OF_RETRIES == retriesCount)
- {
- return IX_NPEMH_CRITICAL_NPE_ERR;
- }
-
- /* write the second word of the message to the NPE's inFIFO */
- IX_NPEMH_REGISTER_WRITE (npeInFifo, message.data[1]);
-
- /* record in the stats the maximum number of retries needed */
- if (ixNpeMhConfigStats[npeId].maxInFifoFullRetries < retriesCount)
- {
- ixNpeMhConfigStats[npeId].maxInFifoFullRetries = retriesCount;
- }
-
- /* update statistical info */
- ixNpeMhConfigStats[npeId].inFifoWrites++;
-
- return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixNpeMhConfigOutFifoRead
- */
-
-IX_STATUS ixNpeMhConfigOutFifoRead (
- IxNpeMhNpeId npeId,
- IxNpeMhMessage *message)
-{
- volatile UINT32 *npeOutFifo =
- (UINT32 *)ixNpeMhConfigNpeInfo[npeId].outFifoRegister;
- UINT32 retriesCount = 0;
-
- /* read the first word of the message from the NPE's outFIFO */
- IX_NPEMH_REGISTER_READ (npeOutFifo, &message->data[0]);
-
- /* need to wait for NPE to write second word - see SCR #493
- poll for maximum number of retries, if exceed maximum
- retries, exit from while loop */
- while ((IX_NPE_MH_MAX_NUM_OF_RETRIES > retriesCount)
- && ixNpeMhConfigOutFifoIsEmpty (npeId))
- {
- retriesCount++;
- }
-
- /* Return TIMEOUT status to caller, indicate that NPE Hang / Halt */
- if (IX_NPE_MH_MAX_NUM_OF_RETRIES == retriesCount)
- {
- return IX_NPEMH_CRITICAL_NPE_ERR;
- }
-
- /* read the second word of the message from the NPE's outFIFO */
- IX_NPEMH_REGISTER_READ (npeOutFifo, &message->data[1]);
-
- /* record in the stats the maximum number of retries needed */
- if (ixNpeMhConfigStats[npeId].maxOutFifoEmptyRetries < retriesCount)
- {
- ixNpeMhConfigStats[npeId].maxOutFifoEmptyRetries = retriesCount;
- }
-
- /* update statistical info */
- ixNpeMhConfigStats[npeId].outFifoReads++;
-
- return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixNpeMhConfigShow
- */
-
-void ixNpeMhConfigShow (
- IxNpeMhNpeId npeId)
-{
- /* show the message fifo read counter */
- IX_NPEMH_SHOW ("Message FIFO reads",
- ixNpeMhConfigStats[npeId].outFifoReads);
-
- /* show the message fifo write counter */
- IX_NPEMH_SHOW ("Message FIFO writes",
- ixNpeMhConfigStats[npeId].inFifoWrites);
-
- /* show the max retries performed when inFIFO full */
- IX_NPEMH_SHOW ("Max inFIFO Full retries",
- ixNpeMhConfigStats[npeId].maxInFifoFullRetries);
-
- /* show the max retries performed when outFIFO empty */
- IX_NPEMH_SHOW ("Max outFIFO Empty retries",
- ixNpeMhConfigStats[npeId].maxOutFifoEmptyRetries);
-
- /* show the current status of the inFifo */
- ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT,
- "InFifo is %s and %s\n",
- (ixNpeMhConfigInFifoIsEmpty (npeId) ?
- (int) "EMPTY" : (int) "NOT EMPTY"),
- (ixNpeMhConfigInFifoIsFull (npeId) ?
- (int) "FULL" : (int) "NOT FULL"),
- 0, 0, 0, 0);
-
- /* show the current status of the outFifo */
- ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT,
- "OutFifo is %s and %s\n",
- (ixNpeMhConfigOutFifoIsEmpty (npeId) ?
- (int) "EMPTY" : (int) "NOT EMPTY"),
- (ixNpeMhConfigOutFifoIsFull (npeId) ?
- (int) "FULL" : (int) "NOT FULL"),
- 0, 0, 0, 0);
-}
-
-/*
- * Function definition: ixNpeMhConfigShowReset
- */
-
-void ixNpeMhConfigShowReset (
- IxNpeMhNpeId npeId)
-{
- /* reset the message fifo read counter */
- ixNpeMhConfigStats[npeId].outFifoReads = 0;
-
- /* reset the message fifo write counter */
- ixNpeMhConfigStats[npeId].inFifoWrites = 0;
-
- /* reset the max inFIFO Full retries counter */
- ixNpeMhConfigStats[npeId].maxInFifoFullRetries = 0;
-
- /* reset the max outFIFO empty retries counter */
- ixNpeMhConfigStats[npeId].maxOutFifoEmptyRetries = 0;
-}
-
-
+++ /dev/null
-/**
- * @file IxNpeMhReceive.c
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the implementation of the private API for the
- * Receive module.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * Put the system defined include files required.
- */
-
-
-/*
- * Put the user defined include files required.
- */
-#include "IxOsal.h"
-#include "IxNpeMhMacros_p.h"
-#include "IxNpeMhConfig_p.h"
-#include "IxNpeMhReceive_p.h"
-#include "IxNpeMhSolicitedCbMgr_p.h"
-#include "IxNpeMhUnsolicitedCbMgr_p.h"
-
-/*
- * #defines and macros used in this file.
- */
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/**
- * @struct IxNpeMhReceiveStats
- *
- * @brief This structure is used to maintain statistics for the Receive
- * module.
- */
-
-typedef struct
-{
- UINT32 isrs; /**< receive ISR invocations */
- UINT32 receives; /**< receive messages invocations */
- UINT32 messages; /**< messages received */
- UINT32 solicited; /**< solicited messages received */
- UINT32 unsolicited; /**< unsolicited messages received */
- UINT32 callbacks; /**< callbacks invoked */
-} IxNpeMhReceiveStats;
-
-/*
- * Variable declarations global to this file only. Externs are followed by
- * static variables.
- */
-
-PRIVATE IxNpeMhReceiveStats ixNpeMhReceiveStats[IX_NPEMH_NUM_NPES];
-
-/*
- * Extern function prototypes.
- */
-
-/*
- * Static function prototypes.
- */
-PRIVATE
-void ixNpeMhReceiveIsr (int npeId);
-
-PRIVATE
-void ixNpeMhReceiveIsr (int npeId)
-{
- int lockKey;
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhReceiveIsr\n");
-
- lockKey = ixOsalIrqLock ();
-
- /* invoke the message receive routine to get messages from the NPE */
- ixNpeMhReceiveMessagesReceive (npeId);
-
- /* update statistical info */
- ixNpeMhReceiveStats[npeId].isrs++;
-
- ixOsalIrqUnlock (lockKey);
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhReceiveIsr\n");
-}
-
-/*
- * Function definition: ixNpeMhReceiveInitialize
- */
-
-void ixNpeMhReceiveInitialize (void)
-{
- IxNpeMhNpeId npeId = 0;
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhReceiveInitialize\n");
-
- /* for each NPE ... */
- for (npeId = 0; npeId < IX_NPEMH_NUM_NPES; npeId++)
- {
- /* register our internal ISR for the NPE to handle "outFIFO not */
- /* empty" interrupts */
- ixNpeMhConfigIsrRegister (npeId, ixNpeMhReceiveIsr);
- }
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhReceiveInitialize\n");
-}
-
-/*
- * Function definition: ixNpeMhReceiveMessagesReceive
- */
-
-IX_STATUS ixNpeMhReceiveMessagesReceive (
- IxNpeMhNpeId npeId)
-{
- IxNpeMhMessage message = { { 0, 0 } };
- IxNpeMhMessageId messageId = 0;
- IxNpeMhCallback callback = NULL;
- IX_STATUS status;
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhReceiveMessagesReceive\n");
-
- /* update statistical info */
- ixNpeMhReceiveStats[npeId].receives++;
-
- /* while the NPE has messages in its outFIFO */
- while (!ixNpeMhConfigOutFifoIsEmpty (npeId))
- {
- /* read a message from the NPE's outFIFO */
- status = ixNpeMhConfigOutFifoRead (npeId, &message);
-
- if (IX_SUCCESS != status)
- {
- return status;
- }
-
- /* get the ID of the message */
- messageId = ixNpeMhConfigMessageIdGet (message);
-
- IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG,
- "Received message from NPE %d with ID 0x%02X\n",
- npeId, messageId);
-
- /* update statistical info */
- ixNpeMhReceiveStats[npeId].messages++;
-
- /* try to find a matching unsolicited callback for this message. */
-
- /* we assume the message is unsolicited. only if there is no */
- /* unsolicited callback for this message type do we assume the */
- /* message is solicited. it is much faster to check for an */
- /* unsolicited callback, so doing this check first should result */
- /* in better performance. */
-
- ixNpeMhUnsolicitedCbMgrCallbackRetrieve (
- npeId, messageId, &callback);
-
- if (callback != NULL)
- {
- IX_NPEMH_TRACE0 (IX_NPEMH_DEBUG,
- "Found matching unsolicited callback\n");
-
- /* update statistical info */
- ixNpeMhReceiveStats[npeId].unsolicited++;
- }
-
- /* if no unsolicited callback was found try to find a matching */
- /* solicited callback for this message */
- if (callback == NULL)
- {
- ixNpeMhSolicitedCbMgrCallbackRetrieve (
- npeId, messageId, &callback);
-
- if (callback != NULL)
- {
- IX_NPEMH_TRACE0 (IX_NPEMH_DEBUG,
- "Found matching solicited callback\n");
-
- /* update statistical info */
- ixNpeMhReceiveStats[npeId].solicited++;
- }
- }
-
- /* if a callback (either unsolicited or solicited) was found */
- if (callback != NULL)
- {
- /* invoke the callback to pass the message back to the client */
- callback (npeId, message);
-
- /* update statistical info */
- ixNpeMhReceiveStats[npeId].callbacks++;
- }
- else /* no callback (neither unsolicited nor solicited) was found */
- {
- IX_NPEMH_TRACE2 (IX_NPEMH_WARNING,
- "No matching callback for NPE %d"
- " and ID 0x%02X, discarding message\n",
- npeId, messageId);
-
- /* the message will be discarded. this is normal behaviour */
- /* if the client passes a NULL solicited callback when */
- /* sending a message. this indicates that the client is not */
- /* interested in receiving the response. alternatively a */
- /* NULL callback here may signify an unsolicited message */
- /* with no appropriate registered callback. */
- }
- }
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhReceiveMessagesReceive\n");
-
- return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixNpeMhReceiveShow
- */
-
-void ixNpeMhReceiveShow (
- IxNpeMhNpeId npeId)
-{
- /* show the ISR invocation counter */
- IX_NPEMH_SHOW ("Receive ISR invocations",
- ixNpeMhReceiveStats[npeId].isrs);
-
- /* show the receive message invocation counter */
- IX_NPEMH_SHOW ("Receive messages invocations",
- ixNpeMhReceiveStats[npeId].receives);
-
- /* show the message received counter */
- IX_NPEMH_SHOW ("Messages received",
- ixNpeMhReceiveStats[npeId].messages);
-
- /* show the solicited message counter */
- IX_NPEMH_SHOW ("Solicited messages received",
- ixNpeMhReceiveStats[npeId].solicited);
-
- /* show the unsolicited message counter */
- IX_NPEMH_SHOW ("Unsolicited messages received",
- ixNpeMhReceiveStats[npeId].unsolicited);
-
- /* show the callback invoked counter */
- IX_NPEMH_SHOW ("Callbacks invoked",
- ixNpeMhReceiveStats[npeId].callbacks);
-
- /* show the message discarded counter */
- IX_NPEMH_SHOW ("Received messages discarded",
- (ixNpeMhReceiveStats[npeId].messages -
- ixNpeMhReceiveStats[npeId].callbacks));
-}
-
-/*
- * Function definition: ixNpeMhReceiveShowReset
- */
-
-void ixNpeMhReceiveShowReset (
- IxNpeMhNpeId npeId)
-{
- /* reset the ISR invocation counter */
- ixNpeMhReceiveStats[npeId].isrs = 0;
-
- /* reset the receive message invocation counter */
- ixNpeMhReceiveStats[npeId].receives = 0;
-
- /* reset the message received counter */
- ixNpeMhReceiveStats[npeId].messages = 0;
-
- /* reset the solicited message counter */
- ixNpeMhReceiveStats[npeId].solicited = 0;
-
- /* reset the unsolicited message counter */
- ixNpeMhReceiveStats[npeId].unsolicited = 0;
-
- /* reset the callback invoked counter */
- ixNpeMhReceiveStats[npeId].callbacks = 0;
-}
+++ /dev/null
-/**
- * @file IxNpeMhSend.c
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the implementation of the private API for the
- * Send module.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * Put the system defined include files required.
- */
-
-
-/*
- * Put the user defined include files required.
- */
-
-#include "IxNpeMhMacros_p.h"
-
-#include "IxNpeMhConfig_p.h"
-#include "IxNpeMhSend_p.h"
-#include "IxNpeMhSolicitedCbMgr_p.h"
-
-/*
- * #defines and macros used in this file.
- */
-
-/**
- * @def IX_NPEMH_INFIFO_RETRY_DELAY_US
- *
- * @brief Amount of time (uSecs) to delay between retries
- * while inFIFO is Full when attempting to send a message
- */
-#define IX_NPEMH_INFIFO_RETRY_DELAY_US (1)
-
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/**
- * @struct IxNpeMhSendStats
- *
- * @brief This structure is used to maintain statistics for the Send
- * module.
- */
-
-typedef struct
-{
- UINT32 sends; /**< send invocations */
- UINT32 sendWithResponses; /**< send with response invocations */
- UINT32 queueFulls; /**< fifo queue full occurrences */
- UINT32 queueFullRetries; /**< fifo queue full retry occurrences */
- UINT32 maxQueueFullRetries; /**< max fifo queue full retries */
- UINT32 callbackFulls; /**< callback list full occurrences */
-} IxNpeMhSendStats;
-
-/*
- * Variable declarations global to this file only. Externs are followed by
- * static variables.
- */
-
-PRIVATE IxNpeMhSendStats ixNpeMhSendStats[IX_NPEMH_NUM_NPES];
-
-/*
- * Extern function prototypes.
- */
-
-/*
- * Static function prototypes.
- */
-PRIVATE
-BOOL ixNpeMhSendInFifoIsFull(
- IxNpeMhNpeId npeId,
- UINT32 maxSendRetries);
-
-/*
- * Function definition: ixNpeMhSendInFifoIsFull
- */
-
-PRIVATE
-BOOL ixNpeMhSendInFifoIsFull(
- IxNpeMhNpeId npeId,
- UINT32 maxSendRetries)
-{
- BOOL isFull = false;
- UINT32 numRetries = 0;
-
- /* check the NPE's inFIFO */
- isFull = ixNpeMhConfigInFifoIsFull (npeId);
-
- /* we retry a few times, just to give the NPE a chance to read from */
- /* the FIFO if the FIFO is currently full */
- while (isFull && (numRetries++ < maxSendRetries))
- {
- if (numRetries >= IX_NPEMH_SEND_RETRIES_DEFAULT)
- {
- /* Delay here for as short a time as possible (1 us). */
- /* Adding a delay here should ensure we are not hogging */
- /* the AHB bus while we are retrying */
- ixOsalBusySleep (IX_NPEMH_INFIFO_RETRY_DELAY_US);
- }
-
- /* re-check the NPE's inFIFO */
- isFull = ixNpeMhConfigInFifoIsFull (npeId);
-
- /* update statistical info */
- ixNpeMhSendStats[npeId].queueFullRetries++;
- }
-
- /* record the highest number of retries that occurred */
- if (ixNpeMhSendStats[npeId].maxQueueFullRetries < numRetries)
- {
- ixNpeMhSendStats[npeId].maxQueueFullRetries = numRetries;
- }
-
- if (isFull)
- {
- /* update statistical info */
- ixNpeMhSendStats[npeId].queueFulls++;
- }
-
- return isFull;
-}
-
-/*
- * Function definition: ixNpeMhSendMessageSend
- */
-
-IX_STATUS ixNpeMhSendMessageSend (
- IxNpeMhNpeId npeId,
- IxNpeMhMessage message,
- UINT32 maxSendRetries)
-{
- IX_STATUS status;
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhSendMessageSend\n");
-
- /* update statistical info */
- ixNpeMhSendStats[npeId].sends++;
-
- /* check if the NPE's inFIFO is full - if so return an error */
- if (ixNpeMhSendInFifoIsFull (npeId, maxSendRetries))
- {
- IX_NPEMH_TRACE0 (IX_NPEMH_WARNING, "NPE's inFIFO is full\n");
- return IX_FAIL;
- }
-
- /* write the message to the NPE's inFIFO */
- status = ixNpeMhConfigInFifoWrite (npeId, message);
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhSendMessageSend\n");
-
- return status;
-}
-
-/*
- * Function definition: ixNpeMhSendMessageWithResponseSend
- */
-
-IX_STATUS ixNpeMhSendMessageWithResponseSend (
- IxNpeMhNpeId npeId,
- IxNpeMhMessage message,
- IxNpeMhMessageId solicitedMessageId,
- IxNpeMhCallback solicitedCallback,
- UINT32 maxSendRetries)
-{
- IX_STATUS status = IX_SUCCESS;
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhSendMessageWithResponseSend\n");
-
- /* update statistical info */
- ixNpeMhSendStats[npeId].sendWithResponses++;
-
- /* sr: this sleep will call the receive routine (no interrupts used!!!) */
- ixOsalSleep (IX_NPEMH_INFIFO_RETRY_DELAY_US);
-
- /* check if the NPE's inFIFO is full - if so return an error */
- if (ixNpeMhSendInFifoIsFull (npeId, maxSendRetries))
- {
- IX_NPEMH_TRACE0 (IX_NPEMH_WARNING, "NPE's inFIFO is full\n");
- return IX_FAIL;
- }
-
- /* save the solicited callback */
- status = ixNpeMhSolicitedCbMgrCallbackSave (
- npeId, solicitedMessageId, solicitedCallback);
- if (status != IX_SUCCESS)
- {
- IX_NPEMH_ERROR_REPORT ("Failed to save solicited callback\n");
-
- /* update statistical info */
- ixNpeMhSendStats[npeId].callbackFulls++;
-
- return status;
- }
-
- /* write the message to the NPE's inFIFO */
- status = ixNpeMhConfigInFifoWrite (npeId, message);
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhSendMessageWithResponseSend\n");
-
- return status;
-}
-
-/*
- * Function definition: ixNpeMhSendShow
- */
-
-void ixNpeMhSendShow (
- IxNpeMhNpeId npeId)
-{
- /* show the message send invocation counter */
- IX_NPEMH_SHOW ("Send invocations",
- ixNpeMhSendStats[npeId].sends);
-
- /* show the message send with response invocation counter */
- IX_NPEMH_SHOW ("Send with response invocations",
- ixNpeMhSendStats[npeId].sendWithResponses);
-
- /* show the fifo queue full occurrence counter */
- IX_NPEMH_SHOW ("Fifo queue full occurrences",
- ixNpeMhSendStats[npeId].queueFulls);
-
- /* show the fifo queue full retry occurrence counter */
- IX_NPEMH_SHOW ("Fifo queue full retry occurrences",
- ixNpeMhSendStats[npeId].queueFullRetries);
-
- /* show the fifo queue full maximum retries counter */
- IX_NPEMH_SHOW ("Maximum fifo queue full retries",
- ixNpeMhSendStats[npeId].maxQueueFullRetries);
-
- /* show the callback list full occurrence counter */
- IX_NPEMH_SHOW ("Solicited callback list full occurrences",
- ixNpeMhSendStats[npeId].callbackFulls);
-}
-
-/*
- * Function definition: ixNpeMhSendShowReset
- */
-
-void ixNpeMhSendShowReset (
- IxNpeMhNpeId npeId)
-{
- /* reset the message send invocation counter */
- ixNpeMhSendStats[npeId].sends = 0;
-
- /* reset the message send with response invocation counter */
- ixNpeMhSendStats[npeId].sendWithResponses = 0;
-
- /* reset the fifo queue full occurrence counter */
- ixNpeMhSendStats[npeId].queueFulls = 0;
-
- /* reset the fifo queue full retry occurrence counter */
- ixNpeMhSendStats[npeId].queueFullRetries = 0;
-
- /* reset the max fifo queue full retries counter */
- ixNpeMhSendStats[npeId].maxQueueFullRetries = 0;
-
- /* reset the callback list full occurrence counter */
- ixNpeMhSendStats[npeId].callbackFulls = 0;
-}
+++ /dev/null
-/**
- * @file IxNpeMhSolicitedCbMgr.c
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the implementation of the private API for the
- * Solicited Callback Manager module.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-#ifndef IXNPEMHCONFIG_P_H
-# define IXNPEMHSOLICITEDCBMGR_C
-#else
-# error "Error, IxNpeMhConfig_p.h should not be included before this definition."
-#endif
-
-/*
- * Put the system defined include files required.
- */
-
-
-/*
- * Put the user defined include files required.
- */
-
-#include "IxOsal.h"
-
-#include "IxNpeMhMacros_p.h"
-#include "IxNpeMhSolicitedCbMgr_p.h"
-#include "IxNpeMhConfig_p.h"
-/*
- * #defines and macros used in this file.
- */
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/**
- * @struct IxNpeMhSolicitedCallbackListEntry
- *
- * @brief This structure is used to store the information associated with
- * an entry in the callback list. This consists of the ID of the send
- * message (which indicates the ID of the corresponding response message)
- * and the callback function pointer itself.
- *
- */
-
-typedef struct IxNpeMhSolicitedCallbackListEntry
-{
- /** message ID */
- IxNpeMhMessageId messageId;
-
- /** callback function pointer */
- IxNpeMhCallback callback;
-
- /** pointer to next entry in the list */
- struct IxNpeMhSolicitedCallbackListEntry *next;
-} IxNpeMhSolicitedCallbackListEntry;
-
-/**
- * @struct IxNpeMhSolicitedCallbackList
- *
- * @brief This structure is used to maintain the list of response
- * callbacks. The number of entries in this list will be variable, and
- * they will be stored in a linked list fashion for ease of addition and
- * removal. The entries themselves are statically allocated, and are
- * organised into a "free" list and a "callback" list. Adding an entry
- * means taking an entry from the "free" list and adding it to the
- * "callback" list. Removing an entry means removing it from the
- * "callback" list and returning it to the "free" list.
- */
-
-typedef struct
-{
- /** pointer to the head of the free list */
- IxNpeMhSolicitedCallbackListEntry *freeHead;
-
- /** pointer to the head of the callback list */
- IxNpeMhSolicitedCallbackListEntry *callbackHead;
-
- /** pointer to the tail of the callback list */
- IxNpeMhSolicitedCallbackListEntry *callbackTail;
-
- /** array of entries - the first entry is used as a dummy entry to */
- /* avoid the scenario of having an empty list, hence '+ 1' */
- IxNpeMhSolicitedCallbackListEntry entries[IX_NPEMH_MAX_CALLBACKS + 1];
-} IxNpeMhSolicitedCallbackList;
-
-/**
- * @struct IxNpeMhSolicitedCbMgrStats
- *
- * @brief This structure is used to maintain statistics for the Solicited
- * Callback Manager module.
- */
-
-typedef struct
-{
- UINT32 saves; /**< callback list saves */
- UINT32 retrieves; /**< callback list retrieves */
-} IxNpeMhSolicitedCbMgrStats;
-
-/*
- * Variable declarations global to this file only. Externs are followed by
- * static variables.
- */
-
-PRIVATE IxNpeMhSolicitedCallbackList
-ixNpeMhSolicitedCbMgrCallbackLists[IX_NPEMH_NUM_NPES];
-
-PRIVATE IxNpeMhSolicitedCbMgrStats
-ixNpeMhSolicitedCbMgrStats[IX_NPEMH_NUM_NPES];
-
-/*
- * Extern function prototypes.
- */
-
-/*
- * Static function prototypes.
- */
-
-/*
- * Function definition: ixNpeMhSolicitedCbMgrInitialize
- */
-
-void ixNpeMhSolicitedCbMgrInitialize (void)
-{
- IxNpeMhNpeId npeId;
- UINT32 localIndex;
- IxNpeMhSolicitedCallbackList *list = NULL;
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhSolicitedCbMgrInitialize\n");
-
- /* for each NPE ... */
- for (npeId = 0; npeId < IX_NPEMH_NUM_NPES; npeId++)
- {
- /* initialise a pointer to the list for convenience */
- list = &ixNpeMhSolicitedCbMgrCallbackLists[npeId];
-
- /* for each entry in the list, after the dummy entry ... */
- for (localIndex = 1; localIndex <= IX_NPEMH_MAX_CALLBACKS; localIndex++)
- {
- /* initialise the entry */
- list->entries[localIndex].messageId = 0x00;
- list->entries[localIndex].callback = NULL;
-
- /* if this entry is before the last entry */
- if (localIndex < IX_NPEMH_MAX_CALLBACKS)
- {
- /* chain this entry to the following entry */
- list->entries[localIndex].next = &(list->entries[localIndex + 1]);
- }
- else /* this entry is the last entry */
- {
- /* the last entry isn't chained to anything */
- list->entries[localIndex].next = NULL;
- }
- }
-
- /* set the free list pointer to point to the first real entry */
- /* (all real entries begin chained together on the free list) */
- list->freeHead = &(list->entries[1]);
-
- /* set the callback list pointers to point to the dummy entry */
- /* (the callback list is initially empty) */
- list->callbackHead = &(list->entries[0]);
- list->callbackTail = &(list->entries[0]);
- }
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhSolicitedCbMgrInitialize\n");
-}
-
-/*
- * Function definition: ixNpeMhSolicitedCbMgrCallbackSave
- */
-
-IX_STATUS ixNpeMhSolicitedCbMgrCallbackSave (
- IxNpeMhNpeId npeId,
- IxNpeMhMessageId solicitedMessageId,
- IxNpeMhCallback solicitedCallback)
-{
- IxNpeMhSolicitedCallbackList *list = NULL;
- IxNpeMhSolicitedCallbackListEntry *callbackEntry = NULL;
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhSolicitedCbMgrCallbackSave\n");
-
- /* initialise a pointer to the list for convenience */
- list = &ixNpeMhSolicitedCbMgrCallbackLists[npeId];
-
- /* check to see if there are any entries in the free list */
- if (list->freeHead == NULL)
- {
- IX_NPEMH_ERROR_REPORT ("Solicited callback list is full\n");
- return IX_FAIL;
- }
-
- /* there is an entry in the free list we can use */
-
- /* update statistical info */
- ixNpeMhSolicitedCbMgrStats[npeId].saves++;
-
- /* remove a callback entry from the start of the free list */
- callbackEntry = list->freeHead;
- list->freeHead = callbackEntry->next;
-
- /* fill in the callback entry with the new data */
- callbackEntry->messageId = solicitedMessageId;
- callbackEntry->callback = solicitedCallback;
-
- /* the new callback entry will be added to the tail of the callback */
- /* list, so it isn't chained to anything */
- callbackEntry->next = NULL;
-
- /* chain new callback entry to the last entry of the callback list */
- list->callbackTail->next = callbackEntry;
- list->callbackTail = callbackEntry;
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhSolicitedCbMgrCallbackSave\n");
-
- return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixNpeMhSolicitedCbMgrCallbackRetrieve
- */
-
-void ixNpeMhSolicitedCbMgrCallbackRetrieve (
- IxNpeMhNpeId npeId,
- IxNpeMhMessageId solicitedMessageId,
- IxNpeMhCallback *solicitedCallback)
-{
- IxNpeMhSolicitedCallbackList *list = NULL;
- IxNpeMhSolicitedCallbackListEntry *callbackEntry = NULL;
- IxNpeMhSolicitedCallbackListEntry *previousEntry = NULL;
-
- /* initialise a pointer to the list for convenience */
- list = &ixNpeMhSolicitedCbMgrCallbackLists[npeId];
-
- /* initialise the callback entry to the first entry of the callback */
- /* list - we must skip over the dummy entry, which is the previous */
- callbackEntry = list->callbackHead->next;
- previousEntry = list->callbackHead;
-
- /* traverse the callback list looking for an entry with a matching */
- /* message ID. note we also save the previous entry's pointer to */
- /* allow us to unchain the matching entry from the callback list */
- while ((callbackEntry != NULL) &&
- (callbackEntry->messageId != solicitedMessageId))
- {
- previousEntry = callbackEntry;
- callbackEntry = callbackEntry->next;
- }
-
- /* if we didn't find a matching callback entry */
- if (callbackEntry == NULL)
- {
- /* return a NULL callback in the outgoing parameter */
- *solicitedCallback = NULL;
- }
- else /* we found a matching callback entry */
- {
- /* update statistical info */
- ixNpeMhSolicitedCbMgrStats[npeId].retrieves++;
-
- /* return the callback in the outgoing parameter */
- *solicitedCallback = callbackEntry->callback;
-
- /* unchain callback entry by chaining previous entry to next */
- previousEntry->next = callbackEntry->next;
-
- /* if the callback entry is at the tail of the list */
- if (list->callbackTail == callbackEntry)
- {
- /* update the tail of the callback list */
- list->callbackTail = previousEntry;
- }
-
- /* re-initialise the callback entry */
- callbackEntry->messageId = 0x00;
- callbackEntry->callback = NULL;
-
- /* add the callback entry to the start of the free list */
- callbackEntry->next = list->freeHead;
- list->freeHead = callbackEntry;
- }
-}
-
-/*
- * Function definition: ixNpeMhSolicitedCbMgrShow
- */
-
-void ixNpeMhSolicitedCbMgrShow (
- IxNpeMhNpeId npeId)
-{
- /* show the solicited callback list save counter */
- IX_NPEMH_SHOW ("Solicited callback list saves",
- ixNpeMhSolicitedCbMgrStats[npeId].saves);
-
- /* show the solicited callback list retrieve counter */
- IX_NPEMH_SHOW ("Solicited callback list retrieves",
- ixNpeMhSolicitedCbMgrStats[npeId].retrieves);
-}
-
-/*
- * Function definition: ixNpeMhSolicitedCbMgrShowReset
- */
-
-void ixNpeMhSolicitedCbMgrShowReset (
- IxNpeMhNpeId npeId)
-{
- /* reset the solicited callback list save counter */
- ixNpeMhSolicitedCbMgrStats[npeId].saves = 0;
-
- /* reset the solicited callback list retrieve counter */
- ixNpeMhSolicitedCbMgrStats[npeId].retrieves = 0;
-}
+++ /dev/null
-/**
- * @file IxNpeMhUnsolicitedCbMgr.c
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the implementation of the private API for
- * the Unsolicited Callback Manager module.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * Put the system defined include files required.
- */
-
-
-/*
- * Put the user defined include files required.
- */
-#include "IxOsal.h"
-
-#include "IxNpeMhMacros_p.h"
-
-#include "IxNpeMhUnsolicitedCbMgr_p.h"
-
-
-/*
- * #defines and macros used in this file.
- */
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/**
- * @struct IxNpeMhUnsolicitedCallbackTable
- *
- * @brief This structure is used to maintain the list of registered
- * callbacks. One entry exists for each message ID, and a NULL entry will
- * signify that no callback has been registered for that ID.
- */
-
-typedef struct
-{
- /** array of entries */
- IxNpeMhCallback entries[IX_NPEMH_MAX_MESSAGE_ID + 1];
-} IxNpeMhUnsolicitedCallbackTable;
-
-/**
- * @struct IxNpeMhUnsolicitedCbMgrStats
- *
- * @brief This structure is used to maintain statistics for the Unsolicited
- * Callback Manager module.
- */
-
-typedef struct
-{
- UINT32 saves; /**< callback table saves */
- UINT32 overwrites; /**< callback table overwrites */
-} IxNpeMhUnsolicitedCbMgrStats;
-
-/*
- * Variable declarations global to this file only. Externs are followed by
- * static variables.
- */
-
-PRIVATE IxNpeMhUnsolicitedCallbackTable
-ixNpeMhUnsolicitedCallbackTables[IX_NPEMH_NUM_NPES];
-
-PRIVATE IxNpeMhUnsolicitedCbMgrStats
-ixNpeMhUnsolicitedCbMgrStats[IX_NPEMH_NUM_NPES];
-
-/*
- * Extern function prototypes.
- */
-
-/*
- * Static function prototypes.
- */
-
-/*
- * Function definition: ixNpeMhUnsolicitedCbMgrInitialize
- */
-
-void ixNpeMhUnsolicitedCbMgrInitialize (void)
-{
- IxNpeMhNpeId npeId = 0;
- IxNpeMhUnsolicitedCallbackTable *table = NULL;
- IxNpeMhMessageId messageId = 0;
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhUnsolicitedCbMgrInitialize\n");
-
- /* for each NPE ... */
- for (npeId = 0; npeId < IX_NPEMH_NUM_NPES; npeId++)
- {
- /* initialise a pointer to the table for convenience */
- table = &ixNpeMhUnsolicitedCallbackTables[npeId];
-
- /* for each message ID ... */
- for (messageId = IX_NPEMH_MIN_MESSAGE_ID;
- messageId <= IX_NPEMH_MAX_MESSAGE_ID; messageId++)
- {
- /* initialise the callback for this message ID to NULL */
- table->entries[messageId] = NULL;
- }
- }
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhUnsolicitedCbMgrInitialize\n");
-}
-
-/*
- * Function definition: ixNpeMhUnsolicitedCbMgrCallbackSave
- */
-
-void ixNpeMhUnsolicitedCbMgrCallbackSave (
- IxNpeMhNpeId npeId,
- IxNpeMhMessageId unsolicitedMessageId,
- IxNpeMhCallback unsolicitedCallback)
-{
- IxNpeMhUnsolicitedCallbackTable *table = NULL;
-
- /* initialise a pointer to the table for convenience */
- table = &ixNpeMhUnsolicitedCallbackTables[npeId];
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhUnsolicitedCbMgrCallbackSave\n");
-
- /* update statistical info */
- ixNpeMhUnsolicitedCbMgrStats[npeId].saves++;
-
- /* check if there is a callback already registered for this NPE and */
- /* message ID */
- if (table->entries[unsolicitedMessageId] != NULL)
- {
- /* if we are overwriting an existing callback */
- if (unsolicitedCallback != NULL)
- {
- IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "Unsolicited callback "
- "overwriting existing callback for NPE ID %d "
- "message ID 0x%02X\n", npeId, unsolicitedMessageId);
- }
- else /* if we are clearing an existing callback */
- {
- IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NULL unsolicited callback "
- "clearing existing callback for NPE ID %d "
- "message ID 0x%02X\n", npeId, unsolicitedMessageId);
- }
-
- /* update statistical info */
- ixNpeMhUnsolicitedCbMgrStats[npeId].overwrites++;
- }
-
- /* save the callback into the table */
- table->entries[unsolicitedMessageId] = unsolicitedCallback;
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhUnsolicitedCbMgrCallbackSave\n");
-}
-
-/*
- * Function definition: ixNpeMhUnsolicitedCbMgrCallbackRetrieve
- */
-
-void ixNpeMhUnsolicitedCbMgrCallbackRetrieve (
- IxNpeMhNpeId npeId,
- IxNpeMhMessageId unsolicitedMessageId,
- IxNpeMhCallback *unsolicitedCallback)
-{
- IxNpeMhUnsolicitedCallbackTable *table = NULL;
-
- /* initialise a pointer to the table for convenience */
- table = &ixNpeMhUnsolicitedCallbackTables[npeId];
-
- /* retrieve the callback from the table */
- *unsolicitedCallback = table->entries[unsolicitedMessageId];
-}
-
-/*
- * Function definition: ixNpeMhUnsolicitedCbMgrShow
- */
-
-void ixNpeMhUnsolicitedCbMgrShow (
- IxNpeMhNpeId npeId)
-{
- /* show the unsolicited callback table save counter */
- IX_NPEMH_SHOW ("Unsolicited callback table saves",
- ixNpeMhUnsolicitedCbMgrStats[npeId].saves);
-
- /* show the unsolicited callback table overwrite counter */
- IX_NPEMH_SHOW ("Unsolicited callback table overwrites",
- ixNpeMhUnsolicitedCbMgrStats[npeId].overwrites);
-}
-
-/*
- * Function definition: ixNpeMhUnsolicitedCbMgrShowReset
- */
-
-void ixNpeMhUnsolicitedCbMgrShowReset (
- IxNpeMhNpeId npeId)
-{
- /* reset the unsolicited callback table save counter */
- ixNpeMhUnsolicitedCbMgrStats[npeId].saves = 0;
-
- /* reset the unsolicited callback table overwrite counter */
- ixNpeMhUnsolicitedCbMgrStats[npeId].overwrites = 0;
-}
+++ /dev/null
-/**
- * @file IxOsalBufferMgt.c
- *
- * @brief Default buffer pool management and buffer management
- * Implementation.
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/*
- * OS may choose to use default bufferMgt by defining
- * IX_OSAL_USE_DEFAULT_BUFFER_MGT in IxOsalOsBufferMgt.h
- */
-
-#include "IxOsal.h"
-
-#define IX_OSAL_BUFFER_FREE_PROTECTION /* Define this to enable Illegal MBuf Freed Protection*/
-
-/*
- * The implementation is only used when the following
- * is defined.
- */
-#ifdef IX_OSAL_USE_DEFAULT_BUFFER_MGT
-
-
-#define IX_OSAL_MBUF_SYS_SIGNATURE (0x8BADF00D)
-#define IX_OSAL_MBUF_SYS_SIGNATURE_MASK (0xEFFFFFFF)
-#define IX_OSAL_MBUF_USED_FLAG (0x10000000)
-#define IX_OSAL_MBUF_SYS_SIGNATURE_INIT(bufPtr) IX_OSAL_MBUF_SIGNATURE (bufPtr) = (UINT32)IX_OSAL_MBUF_SYS_SIGNATURE
-
-/*
-* This implementation is protect, the buffer pool management's ixOsalMBufFree
-* against an invalid MBUF pointer argument that already has been freed earlier
-* or in other words resides in the free pool of MBUFs. This added feature,
-* checks the MBUF "USED" FLAG. The Flag tells if the MBUF is still not freed
-* back to the Buffer Pool.
-* Disable this feature for performance reasons by undef
-* IX_OSAL_BUFFER_FREE_PROTECTION macro.
-*/
-#ifdef IX_OSAL_BUFFER_FREE_PROTECTION /*IX_OSAL_BUFFER_FREE_PROTECTION With Buffer Free protection*/
-
-#define IX_OSAL_MBUF_GET_SYS_SIGNATURE(bufPtr) (IX_OSAL_MBUF_SIGNATURE (bufPtr)&(IX_OSAL_MBUF_SYS_SIGNATURE_MASK) )
-#define IX_OSAL_MBUF_SET_SYS_SIGNATURE(bufPtr) do { \
- IX_OSAL_MBUF_SIGNATURE (bufPtr)&(~IX_OSAL_MBUF_SYS_SIGNATURE_MASK);\
- IX_OSAL_MBUF_SIGNATURE (bufPtr)|=IX_OSAL_MBUF_SYS_SIGNATURE; \
- }while(0)
-
-#define IX_OSAL_MBUF_SET_USED_FLAG(bufPtr) IX_OSAL_MBUF_SIGNATURE (bufPtr)|=IX_OSAL_MBUF_USED_FLAG
-#define IX_OSAL_MBUF_CLEAR_USED_FLAG(bufPtr) IX_OSAL_MBUF_SIGNATURE (bufPtr)&=~IX_OSAL_MBUF_USED_FLAG
-#define IX_OSAL_MBUF_ISSET_USED_FLAG(bufPtr) (IX_OSAL_MBUF_SIGNATURE (bufPtr)&IX_OSAL_MBUF_USED_FLAG)
-
-#else
-
-#define IX_OSAL_MBUF_GET_SYS_SIGNATURE(bufPtr) IX_OSAL_MBUF_SIGNATURE (bufPtr)
-#define IX_OSAL_MBUF_SET_SYS_SIGNATURE(bufPtr) IX_OSAL_MBUF_SIGNATURE (bufPtr) = IX_OSAL_MBUF_SYS_SIGNATURE
-
-#endif /*IX_OSAL_BUFFER_FREE_PROTECTION With Buffer Free protection*/
-/*
- * Variable declarations global to this file only. Externs are followed by
- * static variables.
- */
-
-/*
- * A unit of 32, used to provide bit-shift for pool
- * management. Needs some work if users want more than 32 pools.
- */
-#define IX_OSAL_BUFF_FREE_BITS 32
-
-PRIVATE UINT32 ixOsalBuffFreePools[IX_OSAL_MBUF_MAX_POOLS /
- IX_OSAL_BUFF_FREE_BITS];
-
-PUBLIC IX_OSAL_MBUF_POOL ixOsalBuffPools[IX_OSAL_MBUF_MAX_POOLS];
-
-static int ixOsalBuffPoolsInUse = 0;
-
-#ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY
-PRIVATE IX_OSAL_MBUF *
-ixOsalBuffPoolMbufInit (UINT32 mbufSizeAligned,
- UINT32 dataSizeAligned,
- IX_OSAL_MBUF_POOL *poolPtr);
-#endif
-
-PRIVATE IX_OSAL_MBUF_POOL * ixOsalPoolAlloc (void);
-
-/*
- * Function definition: ixOsalPoolAlloc
- */
-
-/****************************/
-
-PRIVATE IX_OSAL_MBUF_POOL *
-ixOsalPoolAlloc (void)
-{
- register unsigned int i = 0;
-
- /*
- * Scan for the first free buffer. Free buffers are indicated by 0
- * on the corrsponding bit in ixOsalBuffFreePools.
- */
- if (ixOsalBuffPoolsInUse >= IX_OSAL_MBUF_MAX_POOLS)
- {
- /*
- * Fail to grab a ptr this time
- */
- return NULL;
- }
-
- while (ixOsalBuffFreePools[i / IX_OSAL_BUFF_FREE_BITS] &
- (1 << (i % IX_OSAL_BUFF_FREE_BITS)))
- i++;
- /*
- * Free buffer found. Mark it as busy and initialize.
- */
- ixOsalBuffFreePools[i / IX_OSAL_BUFF_FREE_BITS] |=
- (1 << (i % IX_OSAL_BUFF_FREE_BITS));
-
- memset (&ixOsalBuffPools[i], 0, sizeof (IX_OSAL_MBUF_POOL));
-
- ixOsalBuffPools[i].poolIdx = i;
- ixOsalBuffPoolsInUse++;
-
- return &ixOsalBuffPools[i];
-}
-
-
-#ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY
-PRIVATE IX_OSAL_MBUF *
-ixOsalBuffPoolMbufInit (UINT32 mbufSizeAligned,
- UINT32 dataSizeAligned,
- IX_OSAL_MBUF_POOL *poolPtr)
-{
- UINT8 *dataPtr;
- IX_OSAL_MBUF *realMbufPtr;
- /* Allocate cache-aligned memory for mbuf header */
- realMbufPtr = (IX_OSAL_MBUF *) IX_OSAL_CACHE_DMA_MALLOC (mbufSizeAligned);
- IX_OSAL_ASSERT (realMbufPtr != NULL);
- memset (realMbufPtr, 0, mbufSizeAligned);
-
- /* Allocate cache-aligned memory for mbuf data */
- dataPtr = (UINT8 *) IX_OSAL_CACHE_DMA_MALLOC (dataSizeAligned);
- IX_OSAL_ASSERT (dataPtr != NULL);
- memset (dataPtr, 0, dataSizeAligned);
-
- /* Fill in mbuf header fields */
- IX_OSAL_MBUF_MDATA (realMbufPtr) = dataPtr;
- IX_OSAL_MBUF_ALLOCATED_BUFF_DATA (realMbufPtr) = (UINT32)dataPtr;
-
- IX_OSAL_MBUF_MLEN (realMbufPtr) = dataSizeAligned;
- IX_OSAL_MBUF_ALLOCATED_BUFF_LEN (realMbufPtr) = dataSizeAligned;
-
- IX_OSAL_MBUF_NET_POOL (realMbufPtr) = (IX_OSAL_MBUF_POOL *) poolPtr;
-
- IX_OSAL_MBUF_SYS_SIGNATURE_INIT(realMbufPtr);
-
- /* update some statistical information */
- poolPtr->mbufMemSize += mbufSizeAligned;
- poolPtr->dataMemSize += dataSizeAligned;
-
- return realMbufPtr;
-}
-#endif /* #ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY */
-
-/*
- * Function definition: ixOsalBuffPoolInit
- */
-
-PUBLIC IX_OSAL_MBUF_POOL *
-ixOsalPoolInit (UINT32 count, UINT32 size, const char *name)
-{
-
- /* These variables are only used if UX_OSAL_BUFFER_ALLOC_SEPERATELY
- * is defined .
- */
-#ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY
- UINT32 i, mbufSizeAligned, dataSizeAligned;
- IX_OSAL_MBUF *currentMbufPtr = NULL;
-#else
- void *poolBufPtr;
- void *poolDataPtr;
- int mbufMemSize;
- int dataMemSize;
-#endif
-
- IX_OSAL_MBUF_POOL *poolPtr = NULL;
-
- if (count <= 0)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
- IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalPoolInit(): " "count = 0 \n", 0, 0, 0, 0, 0, 0);
- return NULL;
- }
-
- if (name == NULL)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
- IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalPoolInit(): " "NULL name \n", 0, 0, 0, 0, 0, 0);
- return NULL;
- }
-
- if (strlen (name) > IX_OSAL_MBUF_POOL_NAME_LEN)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
- IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalPoolInit(): "
- "ERROR - name length should be no greater than %d \n",
- IX_OSAL_MBUF_POOL_NAME_LEN, 0, 0, 0, 0, 0);
- return NULL;
- }
-
-/* OS can choose whether to allocate all buffers all together (if it
- * can handle a huge single alloc request), or to allocate buffers
- * separately by the defining IX_OSAL_BUFFER_ALLOC_SEPARATELY.
- */
-#ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY
- /* Get a pool Ptr */
- poolPtr = ixOsalPoolAlloc ();
-
- if (poolPtr == NULL)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
- IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalPoolInit(): " "Fail to Get PoolPtr \n", 0, 0, 0, 0, 0, 0);
- return NULL;
- }
-
- mbufSizeAligned = IX_OSAL_MBUF_POOL_SIZE_ALIGN (sizeof (IX_OSAL_MBUF));
- dataSizeAligned = IX_OSAL_MBUF_POOL_SIZE_ALIGN(size);
-
- poolPtr->nextFreeBuf = NULL;
- poolPtr->mbufMemPtr = NULL;
- poolPtr->dataMemPtr = NULL;
- poolPtr->bufDataSize = dataSizeAligned;
- poolPtr->totalBufsInPool = count;
- poolPtr->poolAllocType = IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC;
- strcpy (poolPtr->name, name);
-
-
- for (i = 0; i < count; i++)
- {
- /* create an mbuf */
- currentMbufPtr = ixOsalBuffPoolMbufInit (mbufSizeAligned,
- dataSizeAligned,
- poolPtr);
-
-#ifdef IX_OSAL_BUFFER_FREE_PROTECTION
-/* Set the Buffer USED Flag. If not, ixOsalMBufFree will fail.
- ixOsalMbufFree used here is in a special case whereby, it's
- used to add MBUF to the Pool. By specification, ixOsalMbufFree
- deallocates an allocated MBUF from Pool.
-*/
- IX_OSAL_MBUF_SET_USED_FLAG(currentMbufPtr);
-#endif
- /* Add it to the pool */
- ixOsalMbufFree (currentMbufPtr);
-
- /* flush the pool information to RAM */
- IX_OSAL_CACHE_FLUSH (currentMbufPtr, mbufSizeAligned);
- }
-
- /*
- * update the number of free buffers in the pool
- */
- poolPtr->freeBufsInPool = count;
-
-#else
-/* Otherwise allocate buffers in a continuous block fashion */
- poolBufPtr = IX_OSAL_MBUF_POOL_MBUF_AREA_ALLOC (count, mbufMemSize);
- IX_OSAL_ASSERT (poolBufPtr != NULL);
- poolDataPtr =
- IX_OSAL_MBUF_POOL_DATA_AREA_ALLOC (count, size, dataMemSize);
- IX_OSAL_ASSERT (poolDataPtr != NULL);
-
- poolPtr = ixOsalNoAllocPoolInit (poolBufPtr, poolDataPtr,
- count, size, name);
- if (poolPtr == NULL)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
- IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalPoolInit(): " "Fail to get pool ptr \n", 0, 0, 0, 0, 0, 0);
- return NULL;
- }
-
- poolPtr->poolAllocType = IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC;
-
-#endif /* IX_OSAL_BUFFER_ALLOC_SEPARATELY */
- return poolPtr;
-}
-
-PUBLIC IX_OSAL_MBUF_POOL *
-ixOsalNoAllocPoolInit (void *poolBufPtr,
- void *poolDataPtr, UINT32 count, UINT32 size, const char *name)
-{
- UINT32 i, mbufSizeAligned, sizeAligned;
- IX_OSAL_MBUF *currentMbufPtr = NULL;
- IX_OSAL_MBUF *nextMbufPtr = NULL;
- IX_OSAL_MBUF_POOL *poolPtr = NULL;
-
- /*
- * check parameters
- */
- if (poolBufPtr == NULL)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
- IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalNoAllocPoolInit(): "
- "ERROR - NULL poolBufPtr \n", 0, 0, 0, 0, 0, 0);
- return NULL;
- }
-
- if (count <= 0)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
- IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalNoAllocPoolInit(): "
- "ERROR - count must > 0 \n", 0, 0, 0, 0, 0, 0);
- return NULL;
- }
-
- if (name == NULL)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
- IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalNoAllocPoolInit(): "
- "ERROR - NULL name ptr \n", 0, 0, 0, 0, 0, 0);
- return NULL;
- }
-
- if (strlen (name) > IX_OSAL_MBUF_POOL_NAME_LEN)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
- IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalNoAllocPoolInit(): "
- "ERROR - name length should be no greater than %d \n",
- IX_OSAL_MBUF_POOL_NAME_LEN, 0, 0, 0, 0, 0);
- return NULL;
- }
-
- poolPtr = ixOsalPoolAlloc ();
-
- if (poolPtr == NULL)
- {
- return NULL;
- }
-
- /*
- * Adjust sizes to ensure alignment on cache line boundaries
- */
- mbufSizeAligned =
- IX_OSAL_MBUF_POOL_SIZE_ALIGN (sizeof (IX_OSAL_MBUF));
- /*
- * clear the mbuf memory area
- */
- memset (poolBufPtr, 0, mbufSizeAligned * count);
-
- if (poolDataPtr != NULL)
- {
- /*
- * Adjust sizes to ensure alignment on cache line boundaries
- */
- sizeAligned = IX_OSAL_MBUF_POOL_SIZE_ALIGN (size);
- /*
- * clear the data memory area
- */
- memset (poolDataPtr, 0, sizeAligned * count);
- }
- else
- {
- sizeAligned = 0;
- }
-
- /*
- * initialise pool fields
- */
- strcpy ((poolPtr)->name, name);
-
- poolPtr->dataMemPtr = poolDataPtr;
- poolPtr->mbufMemPtr = poolBufPtr;
- poolPtr->bufDataSize = sizeAligned;
- poolPtr->totalBufsInPool = count;
- poolPtr->mbufMemSize = mbufSizeAligned * count;
- poolPtr->dataMemSize = sizeAligned * count;
-
- currentMbufPtr = (IX_OSAL_MBUF *) poolBufPtr;
-
- poolPtr->nextFreeBuf = currentMbufPtr;
-
- for (i = 0; i < count; i++)
- {
- if (i < (count - 1))
- {
- nextMbufPtr =
- (IX_OSAL_MBUF *) ((unsigned) currentMbufPtr +
- mbufSizeAligned);
- }
- else
- { /* last mbuf in chain */
- nextMbufPtr = NULL;
- }
- IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR (currentMbufPtr) = nextMbufPtr;
- IX_OSAL_MBUF_NET_POOL (currentMbufPtr) = poolPtr;
-
- IX_OSAL_MBUF_SYS_SIGNATURE_INIT(currentMbufPtr);
-
- if (poolDataPtr != NULL)
- {
- IX_OSAL_MBUF_MDATA (currentMbufPtr) = poolDataPtr;
- IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(currentMbufPtr) = (UINT32) poolDataPtr;
-
- IX_OSAL_MBUF_MLEN (currentMbufPtr) = sizeAligned;
- IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(currentMbufPtr) = sizeAligned;
-
- poolDataPtr = (void *) ((unsigned) poolDataPtr + sizeAligned);
- }
-
- currentMbufPtr = nextMbufPtr;
- }
-
- /*
- * update the number of free buffers in the pool
- */
- poolPtr->freeBufsInPool = count;
-
- poolPtr->poolAllocType = IX_OSAL_MBUF_POOL_TYPE_USER_ALLOC;
-
- return poolPtr;
-}
-
-/*
- * Get a mbuf ptr from the pool
- */
-PUBLIC IX_OSAL_MBUF *
-ixOsalMbufAlloc (IX_OSAL_MBUF_POOL * poolPtr)
-{
- int lock;
- IX_OSAL_MBUF *newBufPtr = NULL;
-
- /*
- * check parameters
- */
- if (poolPtr == NULL)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
- IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalMbufAlloc(): "
- "ERROR - Invalid Parameter\n", 0, 0, 0, 0, 0, 0);
- return NULL;
- }
-
- lock = ixOsalIrqLock ();
-
- newBufPtr = poolPtr->nextFreeBuf;
- if (newBufPtr)
- {
- poolPtr->nextFreeBuf =
- IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR (newBufPtr);
- IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR (newBufPtr) = NULL;
-
- /*
- * update the number of free buffers in the pool
- */
- poolPtr->freeBufsInPool--;
- }
- else
- {
- /* Return NULL to indicate to caller that request is denied. */
- ixOsalIrqUnlock (lock);
-
- return NULL;
- }
-
-#ifdef IX_OSAL_BUFFER_FREE_PROTECTION
- /* Set Buffer Used Flag to indicate state.*/
- IX_OSAL_MBUF_SET_USED_FLAG(newBufPtr);
-#endif
-
- ixOsalIrqUnlock (lock);
-
- return newBufPtr;
-}
-
-PUBLIC IX_OSAL_MBUF *
-ixOsalMbufFree (IX_OSAL_MBUF * bufPtr)
-{
- int lock;
- IX_OSAL_MBUF_POOL *poolPtr;
-
- IX_OSAL_MBUF *nextBufPtr = NULL;
-
- /*
- * check parameters
- */
- if (bufPtr == NULL)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
- IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalMbufFree(): "
- "ERROR - Invalid Parameter\n", 0, 0, 0, 0, 0, 0);
- return NULL;
- }
-
-
-
- lock = ixOsalIrqLock ();
-
-#ifdef IX_OSAL_BUFFER_FREE_PROTECTION
-
- /* Prevention for Buffer freed more than once*/
- if(!IX_OSAL_MBUF_ISSET_USED_FLAG(bufPtr))
- {
- return NULL;
- }
- IX_OSAL_MBUF_CLEAR_USED_FLAG(bufPtr);
-#endif
-
- poolPtr = IX_OSAL_MBUF_NET_POOL (bufPtr);
-
- /*
- * check the mbuf wrapper signature (if mbuf wrapper was used)
- */
- if (poolPtr->poolAllocType == IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC)
- {
- IX_OSAL_ENSURE ( (IX_OSAL_MBUF_GET_SYS_SIGNATURE(bufPtr) == IX_OSAL_MBUF_SYS_SIGNATURE),
- "ixOsalBuffPoolBufFree: ERROR - Invalid mbuf signature.");
- }
-
- nextBufPtr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR (bufPtr);
-
- IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR (bufPtr) = poolPtr->nextFreeBuf;
- poolPtr->nextFreeBuf = bufPtr;
-
- /*
- * update the number of free buffers in the pool
- */
- poolPtr->freeBufsInPool++;
-
- ixOsalIrqUnlock (lock);
-
- return nextBufPtr;
-}
-
-PUBLIC void
-ixOsalMbufChainFree (IX_OSAL_MBUF * bufPtr)
-{
- while ((bufPtr = ixOsalMbufFree (bufPtr)));
-}
-
-/*
- * Function definition: ixOsalBuffPoolShow
- */
-PUBLIC void
-ixOsalMbufPoolShow (IX_OSAL_MBUF_POOL * poolPtr)
-{
- IX_OSAL_MBUF *nextBufPtr;
- int count = 0;
- int lock;
-
- /*
- * check parameters
- */
- if (poolPtr == NULL)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
- IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalBuffPoolShow(): "
- "ERROR - Invalid Parameter", 0, 0, 0, 0, 0, 0);
- /*
- * return IX_FAIL;
- */
- return;
- }
-
- lock = ixOsalIrqLock ();
- count = poolPtr->freeBufsInPool;
- nextBufPtr = poolPtr->nextFreeBuf;
- ixOsalIrqUnlock (lock);
-
- ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE,
- IX_OSAL_LOG_DEV_STDOUT, "=== POOL INFORMATION ===\n", 0, 0, 0,
- 0, 0, 0);
- ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT,
- "Pool Name: %s\n",
- (unsigned int) poolPtr->name, 0, 0, 0, 0, 0);
- ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT,
- "Pool Allocation Type: %d\n",
- (unsigned int) poolPtr->poolAllocType, 0, 0, 0, 0, 0);
- ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT,
- "Pool Mbuf Mem Usage (bytes): %d\n",
- (unsigned int) poolPtr->mbufMemSize, 0, 0, 0, 0, 0);
- ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT,
- "Pool Data Mem Usage (bytes): %d\n",
- (unsigned int) poolPtr->dataMemSize, 0, 0, 0, 0, 0);
- ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT,
- "Mbuf Data Capacity (bytes): %d\n",
- (unsigned int) poolPtr->bufDataSize, 0, 0, 0, 0, 0);
- ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT,
- "Total Mbufs in Pool: %d\n",
- (unsigned int) poolPtr->totalBufsInPool, 0, 0, 0, 0, 0);
- ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT,
- "Available Mbufs: %d\n", (unsigned int) count, 0,
- 0, 0, 0, 0);
- ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT,
- "Next Available Mbuf: %p\n", (unsigned int) nextBufPtr,
- 0, 0, 0, 0, 0);
-
- if (poolPtr->poolAllocType == IX_OSAL_MBUF_POOL_TYPE_USER_ALLOC)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE,
- IX_OSAL_LOG_DEV_STDOUT,
- "Mbuf Mem Area Start address: %p\n",
- (unsigned int) poolPtr->mbufMemPtr, 0, 0, 0, 0, 0);
- ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT,
- "Data Mem Area Start address: %p\n",
- (unsigned int) poolPtr->dataMemPtr, 0, 0, 0, 0, 0);
- }
-}
-
-PUBLIC void
-ixOsalMbufDataPtrReset (IX_OSAL_MBUF * bufPtr)
-{
- IX_OSAL_MBUF_POOL *poolPtr;
- UINT8 *poolDataPtr;
-
- if (bufPtr == NULL)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalBuffPoolBufDataPtrReset"
- ": ERROR - Invalid Parameter\n", 0, 0, 0, 0, 0, 0);
- return;
- }
-
- poolPtr = (IX_OSAL_MBUF_POOL *) IX_OSAL_MBUF_NET_POOL (bufPtr);
- poolDataPtr = poolPtr->dataMemPtr;
-
- if (poolPtr->poolAllocType == IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC)
- {
- if (IX_OSAL_MBUF_GET_SYS_SIGNATURE(bufPtr) != IX_OSAL_MBUF_SYS_SIGNATURE)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalBuffPoolBufDataPtrReset"
- ": invalid mbuf, cannot reset mData pointer\n", 0, 0,
- 0, 0, 0, 0);
- return;
- }
- IX_OSAL_MBUF_MDATA (bufPtr) = (UINT8*)IX_OSAL_MBUF_ALLOCATED_BUFF_DATA (bufPtr);
- }
- else
- {
- if (poolDataPtr)
- {
- unsigned int bufSize = poolPtr->bufDataSize;
- unsigned int bufDataAddr =
- (unsigned int) IX_OSAL_MBUF_MDATA (bufPtr);
- unsigned int poolDataAddr = (unsigned int) poolDataPtr;
-
- /*
- * the pointer is still pointing somewhere in the mbuf payload.
- * This operation moves the pointer to the beginning of the
- * mbuf payload
- */
- bufDataAddr = ((bufDataAddr - poolDataAddr) / bufSize) * bufSize;
- IX_OSAL_MBUF_MDATA (bufPtr) = &poolDataPtr[bufDataAddr];
- }
- else
- {
- ixOsalLog (IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalBuffPoolBufDataPtrReset"
- ": cannot be used if user supplied NULL pointer for pool data area "
- "when pool was created\n", 0, 0, 0, 0, 0, 0);
- return;
- }
- }
-
-}
-
-/*
- * Function definition: ixOsalBuffPoolUninit
- */
-PUBLIC IX_STATUS
-ixOsalBuffPoolUninit (IX_OSAL_MBUF_POOL * pool)
-{
- if (!pool)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalBuffPoolUninit: NULL ptr \n", 0, 0, 0, 0, 0, 0);
- return IX_FAIL;
- }
-
- if (pool->freeBufsInPool != pool->totalBufsInPool)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalBuffPoolUninit: need to return all ptrs to the pool first! \n",
- 0, 0, 0, 0, 0, 0);
- return IX_FAIL;
- }
-
- if (pool->poolAllocType == IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC)
- {
-#ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY
- UINT32 i;
- IX_OSAL_MBUF* pBuf;
-
- pBuf = pool->nextFreeBuf;
- /* Freed the Buffer one by one till all the Memory is freed*/
- for (i= pool->freeBufsInPool; i >0 && pBuf!=NULL ;i--){
- IX_OSAL_MBUF* pBufTemp;
- pBufTemp = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(pBuf);
- /* Freed MBUF Data Memory area*/
- IX_OSAL_CACHE_DMA_FREE( (void *) (IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(pBuf)) );
- /* Freed MBUF Struct Memory area*/
- IX_OSAL_CACHE_DMA_FREE(pBuf);
- pBuf = pBufTemp;
- }
-
-#else
- IX_OSAL_CACHE_DMA_FREE (pool->mbufMemPtr);
- IX_OSAL_CACHE_DMA_FREE (pool->dataMemPtr);
-#endif
- }
-
- ixOsalBuffFreePools[pool->poolIdx / IX_OSAL_BUFF_FREE_BITS] &=
- ~(1 << (pool->poolIdx % IX_OSAL_BUFF_FREE_BITS));
- ixOsalBuffPoolsInUse--;
- return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixOsalBuffPoolDataAreaSizeGet
- */
-PUBLIC UINT32
-ixOsalBuffPoolDataAreaSizeGet (int count, int size)
-{
- UINT32 memorySize;
- memorySize = count * IX_OSAL_MBUF_POOL_SIZE_ALIGN (size);
- return memorySize;
-}
-
-/*
- * Function definition: ixOsalBuffPoolMbufAreaSizeGet
- */
-PUBLIC UINT32
-ixOsalBuffPoolMbufAreaSizeGet (int count)
-{
- UINT32 memorySize;
- memorySize =
- count * IX_OSAL_MBUF_POOL_SIZE_ALIGN (sizeof (IX_OSAL_MBUF));
- return memorySize;
-}
-
-/*
- * Function definition: ixOsalBuffPoolFreeCountGet
- */
-PUBLIC UINT32 ixOsalBuffPoolFreeCountGet(IX_OSAL_MBUF_POOL * poolPtr)
-
-{
-
- return poolPtr->freeBufsInPool;
-
-}
-
-#endif /* IX_OSAL_USE_DEFAULT_BUFFER_MGT */
+++ /dev/null
-/**
- * @file IxOsalIoMem.c
- *
- * @brief OS-independent IO/Mem implementation
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/* Access to the global mem map is only allowed in this file */
-#define IxOsalIoMem_C
-
-#include "IxOsal.h"
-
-#define SEARCH_PHYSICAL_ADDRESS (1)
-#define SEARCH_VIRTUAL_ADDRESS (2)
-
-/*
- * Searches for map using one of the following criteria:
- *
- * - enough room to include a zone starting with the physical "requestedAddress" of size "size" (for mapping)
- * - includes the virtual "requestedAddress" in its virtual address space (already mapped, for unmapping)
- * - correct coherency
- *
- * Returns a pointer to the map or NULL if a suitable map is not found.
- */
-PRIVATE IxOsalMemoryMap *
-ixOsalMemMapFind (UINT32 requestedAddress,
- UINT32 size, UINT32 searchCriteria, UINT32 requestedEndianType)
-{
- UINT32 mapIndex;
-
- UINT32 numMapElements = ARRAY_SIZE(ixOsalGlobalMemoryMap);
-
- for (mapIndex = 0; mapIndex < numMapElements; mapIndex++)
- {
- IxOsalMemoryMap *map = &ixOsalGlobalMemoryMap[mapIndex];
-
- if (searchCriteria == SEARCH_PHYSICAL_ADDRESS
- && requestedAddress >= map->physicalAddress
- && (requestedAddress + size) <= (map->physicalAddress + map->size)
- && (map->mapEndianType & requestedEndianType) != 0)
- {
- return map;
- }
- else if (searchCriteria == SEARCH_VIRTUAL_ADDRESS
- && requestedAddress >= map->virtualAddress
- && requestedAddress <= (map->virtualAddress + map->size)
- && (map->mapEndianType & requestedEndianType) != 0)
- {
- return map;
- }
- else if (searchCriteria == SEARCH_PHYSICAL_ADDRESS)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3,
- IX_OSAL_LOG_DEV_STDOUT,
- "Osal: Checking [phys addr 0x%x:size 0x%x:endianType %d]\n",
- map->physicalAddress, map->size, map->mapEndianType, 0, 0, 0);
- }
- }
-
- /*
- * not found
- */
- return NULL;
-}
-
-/*
- * This function maps an I/O mapped physical memory zone of the given size
- * into a virtual memory zone accessible by the caller and returns a cookie -
- * the start address of the virtual memory zone.
- * IX_OSAL_MMAP_PHYS_TO_VIRT should NOT therefore be used on the returned
- * virtual address.
- * The memory zone is to be unmapped using ixOsalMemUnmap once the caller has
- * finished using this zone (e.g. on driver unload) using the cookie as
- * parameter.
- * The IX_OSAL_READ/WRITE_LONG/SHORT macros should be used to read and write
- * the mapped memory, adding the necessary offsets to the address cookie.
- *
- * Note: this function is not to be used directly. Use IX_OSAL_MEM_MAP
- * instead.
- */
-PUBLIC void *
-ixOsalIoMemMap (UINT32 requestedAddress,
- UINT32 size, IxOsalMapEndianessType requestedEndianType)
-{
- IxOsalMemoryMap *map;
-
- ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3,
- IX_OSAL_LOG_DEV_STDOUT,
- "OSAL: Mapping [addr 0x%x:size 0x%x:endianType %d]\n",
- requestedAddress, size, requestedEndianType, 0, 0, 0);
-
- if (requestedEndianType == IX_OSAL_LE)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
- IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalIoMemMap: Please specify component coherency mode to use MEM functions \n",
- 0, 0, 0, 0, 0, 0);
- return (NULL);
- }
- map = ixOsalMemMapFind (requestedAddress,
- size, SEARCH_PHYSICAL_ADDRESS, requestedEndianType);
- if (map != NULL)
- {
- UINT32 offset = requestedAddress - map->physicalAddress;
-
- ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3,
- IX_OSAL_LOG_DEV_STDOUT, "OSAL: Found map [", 0, 0, 0, 0, 0, 0);
- ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3,
- IX_OSAL_LOG_DEV_STDOUT, map->name, 0, 0, 0, 0, 0, 0);
- ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3,
- IX_OSAL_LOG_DEV_STDOUT,
- ":addr 0x%x: virt 0x%x:size 0x%x:ref %d:endianType %d]\n",
- map->physicalAddress, map->virtualAddress,
- map->size, map->refCount, map->mapEndianType, 0);
-
- if (map->type == IX_OSAL_DYNAMIC_MAP && map->virtualAddress == 0)
- {
- if (map->mapFunction != NULL)
- {
- map->mapFunction (map);
-
- if (map->virtualAddress == 0)
- {
- /*
- * failed
- */
- ixOsalLog (IX_OSAL_LOG_LVL_FATAL,
- IX_OSAL_LOG_DEV_STDERR,
- "OSAL: Remap failed - [addr 0x%x:size 0x%x:endianType %d]\n",
- requestedAddress, size, requestedEndianType, 0, 0, 0);
- return NULL;
- }
- }
- else
- {
- /*
- * error, no map function for a dynamic map
- */
- ixOsalLog (IX_OSAL_LOG_LVL_FATAL,
- IX_OSAL_LOG_DEV_STDERR,
- "OSAL: No map function for a dynamic map - "
- "[addr 0x%x:size 0x%x:endianType %d]\n",
- requestedAddress, size, requestedEndianType, 0, 0, 0);
-
- return NULL;
- }
- }
-
- /*
- * increment reference count
- */
- map->refCount++;
-
- return (void *) (map->virtualAddress + offset);
- }
-
- /*
- * requested address is not described in the global memory map
- */
- ixOsalLog (IX_OSAL_LOG_LVL_FATAL,
- IX_OSAL_LOG_DEV_STDERR,
- "OSAL: No mapping found - [addr 0x%x:size 0x%x:endianType %d]\n",
- requestedAddress, size, requestedEndianType, 0, 0, 0);
- return NULL;
-}
-
-/*
- * This function unmaps a previously mapped I/O memory zone using
- * the cookie obtained in the mapping operation. The memory zone in question
- * becomes unavailable to the caller once unmapped and the cookie should be
- * discarded.
- *
- * This function cannot fail if the given parameter is correct and does not
- * return a value.
- *
- * Note: this function is not to be used directly. Use IX_OSAL_MEM_UNMAP
- * instead.
- */
-PUBLIC void
-ixOsalIoMemUnmap (UINT32 requestedAddress, UINT32 endianType)
-{
- IxOsalMemoryMap *map;
-
- if (endianType == IX_OSAL_LE)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
- IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalIoMemUnmap: Please specify component coherency mode to use MEM functions \n",
- 0, 0, 0, 0, 0, 0);
- return;
- }
-
- if (requestedAddress == 0)
- {
- /*
- * invalid virtual address
- */
- return;
- }
-
- map =
- ixOsalMemMapFind (requestedAddress, 0, SEARCH_VIRTUAL_ADDRESS,
- endianType);
-
- if (map != NULL)
- {
- if (map->refCount > 0)
- {
- /*
- * decrement reference count
- */
- map->refCount--;
-
- if (map->refCount == 0)
- {
- /*
- * no longer used, deallocate
- */
- if (map->type == IX_OSAL_DYNAMIC_MAP
- && map->unmapFunction != NULL)
- {
- map->unmapFunction (map);
- }
- }
- }
- }
- else
- {
- ixOsalLog (IX_OSAL_LOG_LVL_WARNING,
- IX_OSAL_LOG_DEV_STDERR,
- "OSAL: ixOsServMemUnmap didn't find the requested map "
- "[virt addr 0x%x: endianType %d], ignoring call\n",
- requestedAddress, endianType, 0, 0, 0, 0);
- }
-}
-
-/*
- * This function Converts a virtual address into a physical
- * address, including the dynamically mapped memory.
- *
- * Parameters virtAddr - virtual address to convert
- * Return value: corresponding physical address, or NULL
- * if there is no physical address addressable
- * by the given virtual address
- * OS: VxWorks, Linux, WinCE, QNX, eCos
- * Reentrant: Yes
- * IRQ safe: Yes
- */
-PUBLIC UINT32
-ixOsalIoMemVirtToPhys (UINT32 virtualAddress, UINT32 requestedCoherency)
-{
- IxOsalMemoryMap *map =
- ixOsalMemMapFind (virtualAddress, 0, SEARCH_VIRTUAL_ADDRESS,
- requestedCoherency);
-
- if (map != NULL)
- {
- return map->physicalAddress + virtualAddress - map->virtualAddress;
- }
- else
- {
- return (UINT32) IX_OSAL_MMU_VIRT_TO_PHYS (virtualAddress);
- }
-}
-
-/*
- * This function Converts a virtual address into a physical
- * address, including the dynamically mapped memory.
- *
- * Parameters virtAddr - virtual address to convert
- * Return value: corresponding physical address, or NULL
- * if there is no physical address addressable
- * by the given virtual address
- * OS: VxWorks, Linux, WinCE, QNX, eCos
- * Reentrant: Yes
- * IRQ safe: Yes
- */
-PUBLIC UINT32
-ixOsalIoMemPhysToVirt (UINT32 physicalAddress, UINT32 requestedCoherency)
-{
- IxOsalMemoryMap *map =
- ixOsalMemMapFind (physicalAddress, 0, SEARCH_PHYSICAL_ADDRESS,
- requestedCoherency);
-
- if (map != NULL)
- {
- return map->virtualAddress + physicalAddress - map->physicalAddress;
- }
- else
- {
- return (UINT32) IX_OSAL_MMU_PHYS_TO_VIRT (physicalAddress);
- }
-}
+++ /dev/null
-/**
- * @file IxOsalOsCacheMMU.c (linux)
- *
- * @brief Cache MemAlloc and MemFree.
- *
- *
- * @par
- * IXP400 SW Release version 1.5
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxOsal.h"
-
-#include <malloc.h>
-
-/*
- * Allocate on a cache line boundary (null pointers are
- * not affected by this operation). This operation is NOT cache safe.
- */
-void *
-ixOsalCacheDmaMalloc (UINT32 n)
-{
- return malloc(n);
-}
-
-/*
- *
- */
-void
-ixOsalCacheDmaFree (void *ptr)
-{
- free(ptr);
-}
+++ /dev/null
-/**
- * @file IxOsalOsMsgQ.c (eCos)
- *
- * @brief OS-specific Message Queue implementation.
- *
- *
- * @par
- * IXP400 SW Release version 1.5
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxOsal.h"
-
-/*******************************
- * Public functions
- *******************************/
-PUBLIC IX_STATUS
-ixOsalMessageQueueCreate (IxOsalMessageQueue * queue,
- UINT32 msgCount, UINT32 msgLen)
-{
- diag_printf("%s called\n", __FUNCTION__);
- return IX_FAIL;
-}
-
-PUBLIC IX_STATUS
-ixOsalMessageQueueDelete (IxOsalMessageQueue * queue)
-{
- diag_printf("%s called\n", __FUNCTION__);
- return IX_FAIL;
-}
-
-PUBLIC IX_STATUS
-ixOsalMessageQueueSend (IxOsalMessageQueue * queue, UINT8 * message)
-{
- diag_printf("%s called\n", __FUNCTION__);
- return IX_FAIL;
-}
-
-PUBLIC IX_STATUS
-ixOsalMessageQueueReceive (IxOsalMessageQueue * queue, UINT8 * message)
-{
- diag_printf("%s called\n", __FUNCTION__);
- return IX_FAIL;
-}
-
+++ /dev/null
-/**
- * @file IxOsalOsSemaphore.c (eCos)
- *
- * @brief Implementation for semaphore and mutex.
- *
- *
- * @par
- * IXP400 SW Release version 1.5
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxOsal.h"
-#include "IxNpeMhReceive_p.h"
-
-/* Define a large number */
-#define IX_OSAL_MAX_LONG (0x7FFFFFFF)
-
-/* Max timeout in MS, used to guard against possible overflow */
-#define IX_OSAL_MAX_TIMEOUT_MS (IX_OSAL_MAX_LONG/HZ)
-
-
-PUBLIC IX_STATUS
-ixOsalSemaphoreInit (IxOsalSemaphore * sid, UINT32 start_value)
-{
- diag_printf("%s called\n", __FUNCTION__);
- return IX_SUCCESS;
-}
-
-/**
- * DESCRIPTION: If the semaphore is 'empty', the calling thread is blocked.
- * If the semaphore is 'full', it is taken and control is returned
- * to the caller. If the time indicated in 'timeout' is reached,
- * the thread will unblock and return an error indication. If the
- * timeout is set to 'IX_OSAL_WAIT_NONE', the thread will never block;
- * if it is set to 'IX_OSAL_WAIT_FOREVER', the thread will block until
- * the semaphore is available.
- *
- *
- */
-
-
-PUBLIC IX_STATUS
-ixOsalSemaphoreWait (IxOsalOsSemaphore * sid, INT32 timeout)
-{
- diag_printf("%s called\n", __FUNCTION__);
- return IX_SUCCESS;
-}
-
-/*
- * Attempt to get semaphore, return immediately,
- * no error info because users expect some failures
- * when using this API.
- */
-PUBLIC IX_STATUS
-ixOsalSemaphoreTryWait (IxOsalSemaphore * sid)
-{
- diag_printf("%s called\n", __FUNCTION__);
- return IX_FAIL;
-}
-
-/**
- *
- * DESCRIPTION: This function causes the next available thread in the pend queue
- * to be unblocked. If no thread is pending on this semaphore, the
- * semaphore becomes 'full'.
- */
-PUBLIC IX_STATUS
-ixOsalSemaphorePost (IxOsalSemaphore * sid)
-{
- diag_printf("%s called\n", __FUNCTION__);
- return IX_SUCCESS;
-}
-
-PUBLIC IX_STATUS
-ixOsalSemaphoreGetValue (IxOsalSemaphore * sid, UINT32 * value)
-{
- diag_printf("%s called\n", __FUNCTION__);
- return IX_FAIL;
-}
-
-PUBLIC IX_STATUS
-ixOsalSemaphoreDestroy (IxOsalSemaphore * sid)
-{
- diag_printf("%s called\n", __FUNCTION__);
- return IX_FAIL;
-}
-
-/****************************
- * Mutex
- ****************************/
-
-static void drv_mutex_init(IxOsalMutex *mutex)
-{
- *mutex = 0;
-}
-
-static void drv_mutex_destroy(IxOsalMutex *mutex)
-{
- *mutex = -1;
-}
-
-static int drv_mutex_trylock(IxOsalMutex *mutex)
-{
- int result = true;
-
- if (*mutex == 1)
- result = false;
-
- return result;
-}
-
-static void drv_mutex_unlock(IxOsalMutex *mutex)
-{
- if (*mutex == 1)
- printf("Trying to unlock unlocked mutex!");
-
- *mutex = 0;
-}
-
-PUBLIC IX_STATUS
-ixOsalMutexInit (IxOsalMutex * mutex)
-{
- drv_mutex_init(mutex);
- return IX_SUCCESS;
-}
-
-PUBLIC IX_STATUS
-ixOsalMutexLock (IxOsalMutex * mutex, INT32 timeout)
-{
- int tries;
-
- if (timeout == IX_OSAL_WAIT_NONE) {
- if (drv_mutex_trylock(mutex))
- return IX_SUCCESS;
- else
- return IX_FAIL;
- }
-
- tries = (timeout * 1000) / 50;
- while (1) {
- if (drv_mutex_trylock(mutex))
- return IX_SUCCESS;
- if (timeout != IX_OSAL_WAIT_FOREVER && tries-- <= 0)
- break;
- udelay(50);
- }
- return IX_FAIL;
-}
-
-PUBLIC IX_STATUS
-ixOsalMutexUnlock (IxOsalMutex * mutex)
-{
- drv_mutex_unlock(mutex);
- return IX_SUCCESS;
-}
-
-/*
- * Attempt to get mutex, return immediately,
- * no error info because users expect some failures
- * when using this API.
- */
-PUBLIC IX_STATUS
-ixOsalMutexTryLock (IxOsalMutex * mutex)
-{
- if (drv_mutex_trylock(mutex))
- return IX_SUCCESS;
- return IX_FAIL;
-}
-
-PUBLIC IX_STATUS
-ixOsalMutexDestroy (IxOsalMutex * mutex)
-{
- drv_mutex_destroy(mutex);
- return IX_SUCCESS;
-}
-
-PUBLIC IX_STATUS
-ixOsalFastMutexInit (IxOsalFastMutex * mutex)
-{
- return ixOsalMutexInit(mutex);
-}
-
-PUBLIC IX_STATUS ixOsalFastMutexTryLock(IxOsalFastMutex *mutex)
-{
- return ixOsalMutexTryLock(mutex);
-}
-
-
-PUBLIC IX_STATUS
-ixOsalFastMutexUnlock (IxOsalFastMutex * mutex)
-{
- return ixOsalMutexUnlock(mutex);
-}
-
-PUBLIC IX_STATUS
-ixOsalFastMutexDestroy (IxOsalFastMutex * mutex)
-{
- return ixOsalMutexDestroy(mutex);
-}
+++ /dev/null
-/**
- * @file IxOsalOsServices.c (linux)
- *
- * @brief Implementation for Irq, Mem, sleep.
- *
- *
- * @par
- * IXP400 SW Release version 1.5
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include <config.h>
-#include <common.h>
-#include "IxOsal.h"
-#include <IxEthAcc.h>
-#include <IxEthDB.h>
-#include <IxNpeDl.h>
-#include <IxQMgr.h>
-#include <IxNpeMh.h>
-
-static char *traceHeaders[] = {
- "",
- "[fatal] ",
- "[error] ",
- "[warning] ",
- "[message] ",
- "[debug1] ",
- "[debug2] ",
- "[debug3] ",
- "[all]"
-};
-
-/* by default trace all but debug message */
-PRIVATE int ixOsalCurrLogLevel = IX_OSAL_LOG_LVL_MESSAGE;
-
-/**************************************
- * Irq services
- *************************************/
-
-PUBLIC IX_STATUS
-ixOsalIrqBind (UINT32 vector, IxOsalVoidFnVoidPtr routine, void *parameter)
-{
- return IX_FAIL;
-}
-
-PUBLIC IX_STATUS
-ixOsalIrqUnbind (UINT32 vector)
-{
- return IX_FAIL;
-}
-
-PUBLIC UINT32
-ixOsalIrqLock ()
-{
- return 0;
-}
-
-/* Enable interrupts and task scheduling,
- * input parameter: irqEnable status returned
- * by ixOsalIrqLock().
- */
-PUBLIC void
-ixOsalIrqUnlock (UINT32 lockKey)
-{
-}
-
-PUBLIC UINT32
-ixOsalIrqLevelSet (UINT32 level)
-{
- return IX_FAIL;
-}
-
-PUBLIC void
-ixOsalIrqEnable (UINT32 irqLevel)
-{
-}
-
-PUBLIC void
-ixOsalIrqDisable (UINT32 irqLevel)
-{
-}
-
-/*********************
- * Log function
- *********************/
-
-INT32
-ixOsalLog (IxOsalLogLevel level,
- IxOsalLogDevice device,
- char *format, int arg1, int arg2, int arg3, int arg4, int arg5, int arg6)
-{
- /*
- * Return -1 for custom display devices
- */
- if ((device != IX_OSAL_LOG_DEV_STDOUT)
- && (device != IX_OSAL_LOG_DEV_STDERR))
- {
- debug("ixOsalLog: only IX_OSAL_LOG_DEV_STDOUT and IX_OSAL_LOG_DEV_STDERR are supported \n");
- return (IX_OSAL_LOG_ERROR);
- }
-
- if (level <= ixOsalCurrLogLevel && level != IX_OSAL_LOG_LVL_NONE)
- {
-#if 0 /* sr: U-Boots printf or debug doesn't return a length */
- int headerByteCount = (level == IX_OSAL_LOG_LVL_USER) ? 0 : diag_printf(traceHeaders[level - 1]);
-
- return headerByteCount + diag_printf (format, arg1, arg2, arg3, arg4, arg5, arg6);
-#else
- int headerByteCount = (level == IX_OSAL_LOG_LVL_USER) ? 0 : strlen(traceHeaders[level - 1]);
-
- return headerByteCount + strlen(format);
-#endif
- }
- else
- {
- /*
- * Return error
- */
- return (IX_OSAL_LOG_ERROR);
- }
-}
-
-PUBLIC UINT32
-ixOsalLogLevelSet (UINT32 level)
-{
- UINT32 oldLevel;
-
- /*
- * Check value first
- */
- if ((level < IX_OSAL_LOG_LVL_NONE) || (level > IX_OSAL_LOG_LVL_ALL))
- {
- ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE,
- IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalLogLevelSet: Log Level is between %d and%d \n",
- IX_OSAL_LOG_LVL_NONE, IX_OSAL_LOG_LVL_ALL, 0, 0, 0, 0);
- return IX_OSAL_LOG_LVL_NONE;
- }
- oldLevel = ixOsalCurrLogLevel;
-
- ixOsalCurrLogLevel = level;
-
- return oldLevel;
-}
-
-/**************************************
- * Task services
- *************************************/
-
-PUBLIC void
-ixOsalBusySleep (UINT32 microseconds)
-{
- udelay(microseconds);
-}
-
-PUBLIC void
-ixOsalSleep (UINT32 milliseconds)
-{
- if (milliseconds != 0) {
-#if 1
- /*
- * sr: We poll while we wait because interrupts are off in U-Boot
- * and CSR expects messages, etc to be dispatched while sleeping.
- */
- int i;
- IxQMgrDispatcherFuncPtr qDispatcherFunc;
-
- ixQMgrDispatcherLoopGet(&qDispatcherFunc);
-
- while (milliseconds--) {
- for (i = 1; i <= 2; i++)
- ixNpeMhMessagesReceive(i);
- (*qDispatcherFunc)(IX_QMGR_QUELOW_GROUP);
-
- udelay(1000);
- }
-#endif
- }
-}
-
-/**************************************
- * Memory functions
- *************************************/
-
-void *
-ixOsalMemAlloc (UINT32 size)
-{
- return (void *)0;
-}
-
-void
-ixOsalMemFree (void *ptr)
-{
-}
-
-/*
- * Copy count bytes from src to dest ,
- * returns pointer to the dest mem zone.
- */
-void *
-ixOsalMemCopy (void *dest, void *src, UINT32 count)
-{
- IX_OSAL_ASSERT (dest != NULL);
- IX_OSAL_ASSERT (src != NULL);
- return (memcpy (dest, src, count));
-}
-
-/*
- * Fills a memory zone with a given constant byte,
- * returns pointer to the memory zone.
- */
-void *
-ixOsalMemSet (void *ptr, UINT8 filler, UINT32 count)
-{
- IX_OSAL_ASSERT (ptr != NULL);
- return (memset (ptr, filler, count));
-}
+++ /dev/null
-/**
- * @file IxOsalOsThread.c (eCos)
- *
- * @brief OS-specific thread implementation.
- *
- *
- * @par
- * IXP400 SW Release version 1.5
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxOsal.h"
-
-/* Thread attribute is ignored */
-PUBLIC IX_STATUS
-ixOsalThreadCreate (IxOsalThread * ptrTid,
- IxOsalThreadAttr * threadAttr, IxOsalVoidFnVoidPtr entryPoint, void *arg)
-{
- return IX_SUCCESS;
-}
-
-/*
- * Start thread after given its thread handle
- */
-PUBLIC IX_STATUS
-ixOsalThreadStart (IxOsalThread * tId)
-{
- /* Thread already started upon creation */
- return IX_SUCCESS;
-}
-
-/*
- * In Linux threadKill does not actually destroy the thread,
- * it will stop the signal handling.
- */
-PUBLIC IX_STATUS
-ixOsalThreadKill (IxOsalThread * tid)
-{
- return IX_SUCCESS;
-}
-
-PUBLIC void
-ixOsalThreadExit (void)
-{
-}
-
-PUBLIC IX_STATUS
-ixOsalThreadPrioritySet (IxOsalOsThread * tid, UINT32 priority)
-{
- return IX_SUCCESS;
-}
-
-PUBLIC IX_STATUS
-ixOsalThreadSuspend (IxOsalThread * tId)
-{
- return IX_SUCCESS;
-
-}
-
-PUBLIC IX_STATUS
-ixOsalThreadResume (IxOsalThread * tId)
-{
- return IX_SUCCESS;
-}
+++ /dev/null
-/*
- * @file: IxQMgrAqmIf.c
- *
- * @author Intel Corporation
- * @date 30-Oct-2001
- *
- * @brief This component provides a set of functions for
- * perfoming I/O on the AQM hardware.
- *
- * Design Notes:
- * These functions are intended to be as fast as possible
- * and as a result perform NO PARAMETER CHECKING.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * Inlines are compiled as function when this is defined.
- * N.B. Must be placed before #include of "IxQMgrAqmIf_p.h
- */
-#ifndef IXQMGRAQMIF_P_H
-# define IXQMGRAQMIF_C
-#else
-# error
-#endif
-
-/*
- * User defined include files.
- */
-#include "IxOsal.h"
-#include "IxQMgr.h"
-#include "IxQMgrAqmIf_p.h"
-#include "IxQMgrLog_p.h"
-
-
-/*
- * #defines and macros used in this file.
- */
-
-/* These defines are the bit offsets of the various fields of
- * the queue configuration register
- */
-#define IX_QMGR_Q_CONFIG_WRPTR_OFFSET 0x00
-#define IX_QMGR_Q_CONFIG_RDPTR_OFFSET 0x07
-#define IX_QMGR_Q_CONFIG_BADDR_OFFSET 0x0E
-#define IX_QMGR_Q_CONFIG_ESIZE_OFFSET 0x16
-#define IX_QMGR_Q_CONFIG_BSIZE_OFFSET 0x18
-#define IX_QMGR_Q_CONFIG_NE_OFFSET 0x1A
-#define IX_QMGR_Q_CONFIG_NF_OFFSET 0x1D
-
-#define IX_QMGR_BASE_ADDR_16_WORD_ALIGN 0x40
-#define IX_QMGR_BASE_ADDR_16_WORD_SHIFT 0x6
-
-#define IX_QMGR_NE_NF_CLEAR_MASK 0x03FFFFFF
-#define IX_QMGR_NE_MASK 0x7
-#define IX_QMGR_NF_MASK 0x7
-#define IX_QMGR_SIZE_MASK 0x3
-#define IX_QMGR_ENTRY_SIZE_MASK 0x3
-#define IX_QMGR_BADDR_MASK 0x003FC000
-#define IX_QMGR_RDPTR_MASK 0x7F
-#define IX_QMGR_WRPTR_MASK 0x7F
-#define IX_QMGR_RDWRPTR_MASK 0x00003FFF
-
-#define IX_QMGR_AQM_ADDRESS_SPACE_SIZE_IN_WORDS 0x1000
-
-/* Base address of AQM SRAM */
-#define IX_QMGR_AQM_SRAM_BASE_ADDRESS_OFFSET \
-((IX_QMGR_QUECONFIG_BASE_OFFSET) + (IX_QMGR_QUECONFIG_SIZE))
-
-/* Min buffer size used for generating buffer size in QUECONFIG */
-#define IX_QMGR_MIN_BUFFER_SIZE 16
-
-/* Reset values of QMgr hardware registers */
-#define IX_QMGR_QUELOWSTAT_RESET_VALUE 0x33333333
-#define IX_QMGR_QUEUOSTAT_RESET_VALUE 0x00000000
-#define IX_QMGR_QUEUPPSTAT0_RESET_VALUE 0xFFFFFFFF
-#define IX_QMGR_QUEUPPSTAT1_RESET_VALUE 0x00000000
-#define IX_QMGR_INT0SRCSELREG_RESET_VALUE 0x00000000
-#define IX_QMGR_QUEIEREG_RESET_VALUE 0x00000000
-#define IX_QMGR_QINTREG_RESET_VALUE 0xFFFFFFFF
-#define IX_QMGR_QUECONFIG_RESET_VALUE 0x00000000
-
-#define IX_QMGR_PHYSICAL_AQM_BASE_ADDRESS IX_OSAL_IXP400_QMGR_PHYS_BASE
-
-#define IX_QMGR_QUELOWSTAT_BITS_PER_Q (BITS_PER_WORD/IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD)
-
-#define IX_QMGR_QUELOWSTAT_QID_MASK 0x7
-#define IX_QMGR_Q_CONFIG_ADDR_GET(qId)\
- (((qId) * IX_QMGR_NUM_BYTES_PER_WORD) +\
- IX_QMGR_QUECONFIG_BASE_OFFSET)
-
-#define IX_QMGR_ENTRY1_OFFSET 0
-#define IX_QMGR_ENTRY2_OFFSET 1
-#define IX_QMGR_ENTRY4_OFFSET 3
-
-/*
- * Variable declarations global to this file. Externs are followed by
- * statics.
- */
-UINT32 aqmBaseAddress = 0;
-/* Store addresses and bit-masks for certain queue access and status registers.
- * This is to facilitate inlining of QRead, QWrite and QStatusGet functions
- * in IxQMgr,h
- */
-extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[];
-UINT32 * ixQMgrAqmIfQueAccRegAddr[IX_QMGR_MAX_NUM_QUEUES];
-UINT32 ixQMgrAqmIfQueLowStatRegAddr[IX_QMGR_MIN_QUEUPP_QID];
-UINT32 ixQMgrAqmIfQueLowStatBitsOffset[IX_QMGR_MIN_QUEUPP_QID];
-UINT32 ixQMgrAqmIfQueLowStatBitsMask;
-UINT32 ixQMgrAqmIfQueUppStat0RegAddr;
-UINT32 ixQMgrAqmIfQueUppStat1RegAddr;
-UINT32 ixQMgrAqmIfQueUppStat0BitMask[IX_QMGR_MIN_QUEUPP_QID];
-UINT32 ixQMgrAqmIfQueUppStat1BitMask[IX_QMGR_MIN_QUEUPP_QID];
-
-/*
- * Fast mutexes, one for each queue, used to protect peek & poke functions
- */
-IxOsalFastMutex ixQMgrAqmIfPeekPokeFastMutex[IX_QMGR_MAX_NUM_QUEUES];
-
-/*
- * Function prototypes
- */
-PRIVATE unsigned
-watermarkToAqmWatermark (IxQMgrWMLevel watermark );
-
-PRIVATE unsigned
-entrySizeToAqmEntrySize (IxQMgrQEntrySizeInWords entrySize);
-
-PRIVATE unsigned
-bufferSizeToAqmBufferSize (unsigned bufferSizeInWords);
-
-PRIVATE void
-ixQMgrAqmIfRegistersReset (void);
-
-PRIVATE void
-ixQMgrAqmIfEntryAddressGet (unsigned int entryIndex,
- UINT32 configRegWord,
- unsigned int qEntrySizeInwords,
- unsigned int qSizeInWords,
- UINT32 **address);
-/*
- * Function definitions
- */
-void
-ixQMgrAqmIfInit (void)
-{
- UINT32 aqmVirtualAddr;
- int i;
-
- /* The value of aqmBaseAddress depends on the logical address
- * assigned by the MMU.
- */
- aqmVirtualAddr =
- (UINT32) IX_OSAL_MEM_MAP(IX_QMGR_PHYSICAL_AQM_BASE_ADDRESS,
- IX_OSAL_IXP400_QMGR_MAP_SIZE);
- IX_OSAL_ASSERT (aqmVirtualAddr);
-
- ixQMgrAqmIfBaseAddressSet (aqmVirtualAddr);
-
- ixQMgrAqmIfRegistersReset ();
-
- for (i = 0; i< IX_QMGR_MAX_NUM_QUEUES; i++)
- {
- ixOsalFastMutexInit(&ixQMgrAqmIfPeekPokeFastMutex[i]);
-
- /********************************************************************
- * Register addresses and bit masks are calculated and stored here to
- * facilitate inlining of QRead, QWrite and QStatusGet functions in
- * IxQMgr.h.
- * These calculations are normally performed dynamically in inlined
- * functions in IxQMgrAqmIf_p.h, and their semantics are reused here.
- */
-
- /* AQM Queue access reg addresses, per queue */
- ixQMgrAqmIfQueAccRegAddr[i] =
- (UINT32 *)(aqmBaseAddress + IX_QMGR_Q_ACCESS_ADDR_GET(i));
- ixQMgrQInlinedReadWriteInfo[i].qAccRegAddr =
- (volatile UINT32 *)(aqmBaseAddress + IX_QMGR_Q_ACCESS_ADDR_GET(i));
-
-
- ixQMgrQInlinedReadWriteInfo[i].qConfigRegAddr =
- (volatile UINT32 *)(aqmBaseAddress + IX_QMGR_Q_CONFIG_ADDR_GET(i));
-
- /* AQM Queue lower-group (0-31), only */
- if (i < IX_QMGR_MIN_QUEUPP_QID)
- {
- /* AQM Q underflow/overflow status register addresses, per queue */
- ixQMgrQInlinedReadWriteInfo[i].qUOStatRegAddr =
- (volatile UINT32 *)(aqmBaseAddress +
- IX_QMGR_QUEUOSTAT0_OFFSET +
- ((i / IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD) *
- IX_QMGR_NUM_BYTES_PER_WORD));
-
- /* AQM Q underflow status bit masks for status register per queue */
- ixQMgrQInlinedReadWriteInfo[i].qUflowStatBitMask =
- (IX_QMGR_UNDERFLOW_BIT_OFFSET + 1) <<
- ((i & (IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD - 1)) *
- (BITS_PER_WORD / IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD));
-
- /* AQM Q overflow status bit masks for status register, per queue */
- ixQMgrQInlinedReadWriteInfo[i].qOflowStatBitMask =
- (IX_QMGR_OVERFLOW_BIT_OFFSET + 1) <<
- ((i & (IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD - 1)) *
- (BITS_PER_WORD / IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD));
-
- /* AQM Q lower-group (0-31) status register addresses, per queue */
- ixQMgrAqmIfQueLowStatRegAddr[i] = aqmBaseAddress +
- IX_QMGR_QUELOWSTAT0_OFFSET +
- ((i / IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD) *
- IX_QMGR_NUM_BYTES_PER_WORD);
-
- /* AQM Q lower-group (0-31) status register bit offset */
- ixQMgrAqmIfQueLowStatBitsOffset[i] =
- (i & (IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD - 1)) *
- (BITS_PER_WORD / IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD);
- }
- else /* AQM Q upper-group (32-63), only */
- {
- /* AQM Q upper-group (32-63) Nearly Empty status reg bit masks */
- ixQMgrAqmIfQueUppStat0BitMask[i - IX_QMGR_MIN_QUEUPP_QID] =
- (1 << (i - IX_QMGR_MIN_QUEUPP_QID));
-
- /* AQM Q upper-group (32-63) Full status register bit masks */
- ixQMgrAqmIfQueUppStat1BitMask[i - IX_QMGR_MIN_QUEUPP_QID] =
- (1 << (i - IX_QMGR_MIN_QUEUPP_QID));
- }
- }
-
- /* AQM Q lower-group (0-31) status register bit mask */
- ixQMgrAqmIfQueLowStatBitsMask = (1 <<
- (BITS_PER_WORD /
- IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD)) - 1;
-
- /* AQM Q upper-group (32-63) Nearly Empty status register address */
- ixQMgrAqmIfQueUppStat0RegAddr = aqmBaseAddress + IX_QMGR_QUEUPPSTAT0_OFFSET;
-
- /* AQM Q upper-group (32-63) Full status register address */
- ixQMgrAqmIfQueUppStat1RegAddr = aqmBaseAddress + IX_QMGR_QUEUPPSTAT1_OFFSET;
-}
-
-/*
- * Uninitialise the AqmIf module by unmapping memory, etc
- */
-void
-ixQMgrAqmIfUninit (void)
-{
- UINT32 virtAddr;
-
- ixQMgrAqmIfBaseAddressGet (&virtAddr);
- IX_OSAL_MEM_UNMAP (virtAddr);
- ixQMgrAqmIfBaseAddressSet (0);
-}
-
-/*
- * Set the the logical base address of AQM
- */
-void
-ixQMgrAqmIfBaseAddressSet (UINT32 address)
-{
- aqmBaseAddress = address;
-}
-
-/*
- * Get the logical base address of AQM
- */
-void
-ixQMgrAqmIfBaseAddressGet (UINT32 *address)
-{
- *address = aqmBaseAddress;
-}
-
-/*
- * Get the logical base address of AQM SRAM
- */
-void
-ixQMgrAqmIfSramBaseAddressGet (UINT32 *address)
-{
- *address = aqmBaseAddress +
- IX_QMGR_AQM_SRAM_BASE_ADDRESS_OFFSET;
-}
-
-/*
- * This function will write the status bits of a queue
- * specified by qId.
- */
-void
-ixQMgrAqmIfQRegisterBitsWrite (IxQMgrQId qId,
- UINT32 registerBaseAddrOffset,
- unsigned queuesPerRegWord,
- UINT32 value)
-{
- volatile UINT32 *registerAddress;
- UINT32 registerWord;
- UINT32 statusBitsMask;
- UINT32 bitsPerQueue;
-
- bitsPerQueue = BITS_PER_WORD / queuesPerRegWord;
-
- /*
- * Calculate the registerAddress
- * multiple queues split accross registers
- */
- registerAddress = (UINT32*)(aqmBaseAddress +
- registerBaseAddrOffset +
- ((qId / queuesPerRegWord) *
- IX_QMGR_NUM_BYTES_PER_WORD));
-
- /* Read the current data */
- ixQMgrAqmIfWordRead (registerAddress, ®isterWord);
-
-
- if( (registerBaseAddrOffset == IX_QMGR_INT0SRCSELREG0_OFFSET) &&
- (qId == IX_QMGR_QUEUE_0) )
- {
- statusBitsMask = 0x7 ;
-
- /* Queue 0 at INT0SRCSELREG should not corrupt the value bit-3 */
- value &= 0x7 ;
- }
- else
- {
- /* Calculate the mask for the status bits for this queue. */
- statusBitsMask = ((1 << bitsPerQueue) - 1);
- statusBitsMask <<= ((qId & (queuesPerRegWord - 1)) * bitsPerQueue);
-
- /* Mask out bits in value that would overwrite other q data */
- value <<= ((qId & (queuesPerRegWord - 1)) * bitsPerQueue);
- value &= statusBitsMask;
- }
-
- /* Mask out bits to write to */
- registerWord &= ~statusBitsMask;
-
-
- /* Set the write bits */
- registerWord |= value;
-
- /*
- * Write the data
- */
- ixQMgrAqmIfWordWrite (registerAddress, registerWord);
-}
-
-/*
- * This function generates the parameters that can be used to
- * check if a Qs status matches the specified source select.
- * It calculates which status word to check (statusWordOffset),
- * the value to check the status against (checkValue) and the
- * mask (mask) to mask out all but the bits to check in the status word.
- */
-void
-ixQMgrAqmIfQStatusCheckValsCalc (IxQMgrQId qId,
- IxQMgrSourceId srcSel,
- unsigned int *statusWordOffset,
- UINT32 *checkValue,
- UINT32 *mask)
-{
- UINT32 shiftVal;
-
- if (qId < IX_QMGR_MIN_QUEUPP_QID)
- {
- switch (srcSel)
- {
- case IX_QMGR_Q_SOURCE_ID_E:
- *checkValue = IX_QMGR_Q_STATUS_E_BIT_MASK;
- *mask = IX_QMGR_Q_STATUS_E_BIT_MASK;
- break;
- case IX_QMGR_Q_SOURCE_ID_NE:
- *checkValue = IX_QMGR_Q_STATUS_NE_BIT_MASK;
- *mask = IX_QMGR_Q_STATUS_NE_BIT_MASK;
- break;
- case IX_QMGR_Q_SOURCE_ID_NF:
- *checkValue = IX_QMGR_Q_STATUS_NF_BIT_MASK;
- *mask = IX_QMGR_Q_STATUS_NF_BIT_MASK;
- break;
- case IX_QMGR_Q_SOURCE_ID_F:
- *checkValue = IX_QMGR_Q_STATUS_F_BIT_MASK;
- *mask = IX_QMGR_Q_STATUS_F_BIT_MASK;
- break;
- case IX_QMGR_Q_SOURCE_ID_NOT_E:
- *checkValue = 0;
- *mask = IX_QMGR_Q_STATUS_E_BIT_MASK;
- break;
- case IX_QMGR_Q_SOURCE_ID_NOT_NE:
- *checkValue = 0;
- *mask = IX_QMGR_Q_STATUS_NE_BIT_MASK;
- break;
- case IX_QMGR_Q_SOURCE_ID_NOT_NF:
- *checkValue = 0;
- *mask = IX_QMGR_Q_STATUS_NF_BIT_MASK;
- break;
- case IX_QMGR_Q_SOURCE_ID_NOT_F:
- *checkValue = 0;
- *mask = IX_QMGR_Q_STATUS_F_BIT_MASK;
- break;
- default:
- /* Should never hit */
- IX_OSAL_ASSERT(0);
- break;
- }
-
- /* One nibble of status per queue so need to shift the
- * check value and mask out to the correct position.
- */
- shiftVal = (qId % IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD) *
- IX_QMGR_QUELOWSTAT_BITS_PER_Q;
-
- /* Calculate the which status word to check from the qId,
- * 8 Qs status per word
- */
- *statusWordOffset = qId / IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD;
-
- *checkValue <<= shiftVal;
- *mask <<= shiftVal;
- }
- else
- {
- /* One status word */
- *statusWordOffset = 0;
- /* Single bits per queue and int source bit hardwired NE,
- * Qs start at 32.
- */
- *mask = 1 << (qId - IX_QMGR_MIN_QUEUPP_QID);
- *checkValue = *mask;
- }
-}
-
-void
-ixQMgrAqmIfQInterruptEnable (IxQMgrQId qId)
-{
- volatile UINT32 *registerAddress;
- UINT32 registerWord;
- UINT32 actualBitOffset;
-
- if (qId < IX_QMGR_MIN_QUEUPP_QID)
- {
- registerAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_QUEIEREG0_OFFSET);
- }
- else
- {
- registerAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_QUEIEREG1_OFFSET);
- }
-
- actualBitOffset = 1 << (qId % IX_QMGR_MIN_QUEUPP_QID);
-
- ixQMgrAqmIfWordRead (registerAddress, ®isterWord);
- ixQMgrAqmIfWordWrite (registerAddress, (registerWord | actualBitOffset));
-}
-
-void
-ixQMgrAqmIfQInterruptDisable (IxQMgrQId qId)
-{
- volatile UINT32 *registerAddress;
- UINT32 registerWord;
- UINT32 actualBitOffset;
-
- if (qId < IX_QMGR_MIN_QUEUPP_QID)
- {
- registerAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_QUEIEREG0_OFFSET);
- }
- else
- {
- registerAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_QUEIEREG1_OFFSET);
- }
-
- actualBitOffset = 1 << (qId % IX_QMGR_MIN_QUEUPP_QID);
-
- ixQMgrAqmIfWordRead (registerAddress, ®isterWord);
- ixQMgrAqmIfWordWrite (registerAddress, registerWord & (~actualBitOffset));
-}
-
-void
-ixQMgrAqmIfQueCfgWrite (IxQMgrQId qId,
- IxQMgrQSizeInWords qSizeInWords,
- IxQMgrQEntrySizeInWords entrySizeInWords,
- UINT32 freeSRAMAddress)
-{
- volatile UINT32 *cfgAddress = NULL;
- UINT32 qCfg = 0;
- UINT32 baseAddress = 0;
- unsigned aqmEntrySize = 0;
- unsigned aqmBufferSize = 0;
-
- /* Build config register */
- aqmEntrySize = entrySizeToAqmEntrySize (entrySizeInWords);
- qCfg |= (aqmEntrySize&IX_QMGR_ENTRY_SIZE_MASK) <<
- IX_QMGR_Q_CONFIG_ESIZE_OFFSET;
-
- aqmBufferSize = bufferSizeToAqmBufferSize (qSizeInWords);
- qCfg |= (aqmBufferSize&IX_QMGR_SIZE_MASK) << IX_QMGR_Q_CONFIG_BSIZE_OFFSET;
-
- /* baseAddress, calculated relative to aqmBaseAddress and start address */
- baseAddress = freeSRAMAddress -
- (aqmBaseAddress + IX_QMGR_QUECONFIG_BASE_OFFSET);
-
- /* Verify base address aligned to a 16 word boundary */
- if ((baseAddress % IX_QMGR_BASE_ADDR_16_WORD_ALIGN) != 0)
- {
- IX_QMGR_LOG_ERROR0("ixQMgrAqmIfQueCfgWrite () address is not on 16 word boundary\n");
- }
- /* Now convert it to a 16 word pointer as required by QUECONFIG register */
- baseAddress >>= IX_QMGR_BASE_ADDR_16_WORD_SHIFT;
-
-
- qCfg |= (baseAddress << IX_QMGR_Q_CONFIG_BADDR_OFFSET);
-
-
- cfgAddress = (UINT32*)(aqmBaseAddress +
- IX_QMGR_Q_CONFIG_ADDR_GET(qId));
-
-
- /* NOTE: High and Low watermarks are set to zero */
- ixQMgrAqmIfWordWrite (cfgAddress, qCfg);
-}
-
-void
-ixQMgrAqmIfQueCfgRead (IxQMgrQId qId,
- unsigned int numEntries,
- UINT32 *baseAddress,
- unsigned int *ne,
- unsigned int *nf,
- UINT32 *readPtr,
- UINT32 *writePtr)
-{
- UINT32 qcfg;
- UINT32 *cfgAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_Q_CONFIG_ADDR_GET(qId));
- unsigned int qEntrySizeInwords;
- unsigned int qSizeInWords;
- UINT32 *readPtr_ = NULL;
-
- /* Read the queue configuration register */
- ixQMgrAqmIfWordRead (cfgAddress, &qcfg);
-
- /* Extract the base address */
- *baseAddress = (UINT32)((qcfg & IX_QMGR_BADDR_MASK) >>
- (IX_QMGR_Q_CONFIG_BADDR_OFFSET));
-
- /* Base address is a 16 word pointer from the start of AQM SRAM.
- * Convert to absolute word address.
- */
- *baseAddress <<= IX_QMGR_BASE_ADDR_16_WORD_SHIFT;
- *baseAddress += (UINT32)IX_QMGR_QUECONFIG_BASE_OFFSET;
-
- /*
- * Extract the watermarks. 0->0 entries, 1->1 entries, 2->2 entries, 3->4 entries......
- * If ne > 0 ==> neInEntries = 2^(ne - 1)
- * If ne == 0 ==> neInEntries = 0
- * The same applies.
- */
- *ne = ((qcfg) >> (IX_QMGR_Q_CONFIG_NE_OFFSET)) & IX_QMGR_NE_MASK;
- *nf = ((qcfg) >> (IX_QMGR_Q_CONFIG_NF_OFFSET)) & IX_QMGR_NF_MASK;
-
- if (0 != *ne)
- {
- *ne = 1 << (*ne - 1);
- }
- if (0 != *nf)
- {
- *nf = 1 << (*nf - 1);
- }
-
- /* Get the queue entry size in words */
- qEntrySizeInwords = ixQMgrQEntrySizeInWordsGet (qId);
-
- /* Get the queue size in words */
- qSizeInWords = ixQMgrQSizeInWordsGet (qId);
-
- ixQMgrAqmIfEntryAddressGet (0/* Entry 0. i.e the readPtr*/,
- qcfg,
- qEntrySizeInwords,
- qSizeInWords,
- &readPtr_);
- *readPtr = (UINT32)readPtr_;
- *readPtr -= (UINT32)aqmBaseAddress;/* Offset, not absolute address */
-
- *writePtr = (qcfg >> IX_QMGR_Q_CONFIG_WRPTR_OFFSET) & IX_QMGR_WRPTR_MASK;
- *writePtr = *baseAddress + (*writePtr * (IX_QMGR_NUM_BYTES_PER_WORD));
- return;
-}
-
-unsigned
-ixQMgrAqmIfLog2 (unsigned number)
-{
- unsigned count = 0;
-
- /*
- * N.B. this function will return 0
- * for ixQMgrAqmIfLog2 (0)
- */
- while (number/2)
- {
- number /=2;
- count++;
- }
-
- return count;
-}
-
-void ixQMgrAqmIfIntSrcSelReg0Bit3Set (void)
-{
-
- volatile UINT32 *registerAddress;
- UINT32 registerWord;
-
- /*
- * Calculate the registerAddress
- * multiple queues split accross registers
- */
- registerAddress = (UINT32*)(aqmBaseAddress +
- IX_QMGR_INT0SRCSELREG0_OFFSET);
-
- /* Read the current data */
- ixQMgrAqmIfWordRead (registerAddress, ®isterWord);
-
- /* Set the write bits */
- registerWord |= (1<<IX_QMGR_INT0SRCSELREG0_BIT3) ;
-
- /*
- * Write the data
- */
- ixQMgrAqmIfWordWrite (registerAddress, registerWord);
-}
-
-
-void
-ixQMgrAqmIfIntSrcSelWrite (IxQMgrQId qId,
- IxQMgrSourceId sourceId)
-{
- ixQMgrAqmIfQRegisterBitsWrite (qId,
- IX_QMGR_INT0SRCSELREG0_OFFSET,
- IX_QMGR_INTSRC_NUM_QUE_PER_WORD,
- sourceId);
-}
-
-
-
-void
-ixQMgrAqmIfWatermarkSet (IxQMgrQId qId,
- unsigned ne,
- unsigned nf)
-{
- volatile UINT32 *address = 0;
- UINT32 value = 0;
- unsigned aqmNeWatermark = 0;
- unsigned aqmNfWatermark = 0;
-
- address = (UINT32*)(aqmBaseAddress +
- IX_QMGR_Q_CONFIG_ADDR_GET(qId));
-
- aqmNeWatermark = watermarkToAqmWatermark (ne);
- aqmNfWatermark = watermarkToAqmWatermark (nf);
-
- /* Read the current watermarks */
- ixQMgrAqmIfWordRead (address, &value);
-
- /* Clear out the old watermarks */
- value &= IX_QMGR_NE_NF_CLEAR_MASK;
-
- /* Generate the value to write */
- value |= (aqmNeWatermark << IX_QMGR_Q_CONFIG_NE_OFFSET) |
- (aqmNfWatermark << IX_QMGR_Q_CONFIG_NF_OFFSET);
-
- ixQMgrAqmIfWordWrite (address, value);
-
-}
-
-PRIVATE void
-ixQMgrAqmIfEntryAddressGet (unsigned int entryIndex,
- UINT32 configRegWord,
- unsigned int qEntrySizeInwords,
- unsigned int qSizeInWords,
- UINT32 **address)
-{
- UINT32 readPtr;
- UINT32 baseAddress;
- UINT32 *topOfAqmSram;
-
- topOfAqmSram = ((UINT32 *)aqmBaseAddress + IX_QMGR_AQM_ADDRESS_SPACE_SIZE_IN_WORDS);
-
- /* Extract the base address */
- baseAddress = (UINT32)((configRegWord & IX_QMGR_BADDR_MASK) >>
- (IX_QMGR_Q_CONFIG_BADDR_OFFSET));
-
- /* Base address is a 16 word pointer from the start of AQM SRAM.
- * Convert to absolute word address.
- */
- baseAddress <<= IX_QMGR_BASE_ADDR_16_WORD_SHIFT;
- baseAddress += ((UINT32)aqmBaseAddress + (UINT32)IX_QMGR_QUECONFIG_BASE_OFFSET);
-
- /* Extract the read pointer. Read pointer is a word pointer */
- readPtr = (UINT32)((configRegWord >>
- IX_QMGR_Q_CONFIG_RDPTR_OFFSET)&IX_QMGR_RDPTR_MASK);
-
- /* Read/Write pointers(word pointers) are offsets from the queue buffer space base address.
- * Calculate the absolute read pointer address. NOTE: Queues are circular buffers.
- */
- readPtr = (readPtr + (entryIndex * qEntrySizeInwords)) & (qSizeInWords - 1); /* Mask by queue size */
- *address = (UINT32 *)(baseAddress + (readPtr * (IX_QMGR_NUM_BYTES_PER_WORD)));
-
- switch (qEntrySizeInwords)
- {
- case IX_QMGR_Q_ENTRY_SIZE1:
- IX_OSAL_ASSERT((*address + IX_QMGR_ENTRY1_OFFSET) < topOfAqmSram);
- break;
- case IX_QMGR_Q_ENTRY_SIZE2:
- IX_OSAL_ASSERT((*address + IX_QMGR_ENTRY2_OFFSET) < topOfAqmSram);
- break;
- case IX_QMGR_Q_ENTRY_SIZE4:
- IX_OSAL_ASSERT((*address + IX_QMGR_ENTRY4_OFFSET) < topOfAqmSram);
- break;
- default:
- IX_QMGR_LOG_ERROR0("Invalid Q Entry size passed to ixQMgrAqmIfEntryAddressGet");
- break;
- }
-
-}
-
-IX_STATUS
-ixQMgrAqmIfQPeek (IxQMgrQId qId,
- unsigned int entryIndex,
- unsigned int *entry)
-{
- UINT32 *cfgRegAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_Q_CONFIG_ADDR_GET(qId));
- UINT32 *entryAddress = NULL;
- UINT32 configRegWordOnEntry;
- UINT32 configRegWordOnExit;
- unsigned int qEntrySizeInwords;
- unsigned int qSizeInWords;
-
- /* Get the queue entry size in words */
- qEntrySizeInwords = ixQMgrQEntrySizeInWordsGet (qId);
-
- /* Get the queue size in words */
- qSizeInWords = ixQMgrQSizeInWordsGet (qId);
-
- /* Read the config register */
- ixQMgrAqmIfWordRead (cfgRegAddress, &configRegWordOnEntry);
-
- /* Get the entry address */
- ixQMgrAqmIfEntryAddressGet (entryIndex,
- configRegWordOnEntry,
- qEntrySizeInwords,
- qSizeInWords,
- &entryAddress);
-
- /* Get the lock or return busy */
- if (IX_SUCCESS != ixOsalFastMutexTryLock(&ixQMgrAqmIfPeekPokeFastMutex[qId]))
- {
- return IX_FAIL;
- }
-
- while(qEntrySizeInwords--)
- {
- ixQMgrAqmIfWordRead (entryAddress++, entry++);
- }
-
- /* Release the lock */
- ixOsalFastMutexUnlock(&ixQMgrAqmIfPeekPokeFastMutex[qId]);
-
- /* Read the config register */
- ixQMgrAqmIfWordRead (cfgRegAddress, &configRegWordOnExit);
-
- /* Check that the read and write pointers have not changed */
- if (configRegWordOnEntry != configRegWordOnExit)
- {
- return IX_FAIL;
- }
-
- return IX_SUCCESS;
-}
-
-IX_STATUS
-ixQMgrAqmIfQPoke (IxQMgrQId qId,
- unsigned entryIndex,
- unsigned int *entry)
-{
- UINT32 *cfgRegAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_Q_CONFIG_ADDR_GET(qId));
- UINT32 *entryAddress = NULL;
- UINT32 configRegWordOnEntry;
- UINT32 configRegWordOnExit;
- unsigned int qEntrySizeInwords;
- unsigned int qSizeInWords;
-
- /* Get the queue entry size in words */
- qEntrySizeInwords = ixQMgrQEntrySizeInWordsGet (qId);
-
- /* Get the queue size in words */
- qSizeInWords = ixQMgrQSizeInWordsGet (qId);
-
- /* Read the config register */
- ixQMgrAqmIfWordRead (cfgRegAddress, &configRegWordOnEntry);
-
- /* Get the entry address */
- ixQMgrAqmIfEntryAddressGet (entryIndex,
- configRegWordOnEntry,
- qEntrySizeInwords,
- qSizeInWords,
- &entryAddress);
-
- /* Get the lock or return busy */
- if (IX_SUCCESS != ixOsalFastMutexTryLock(&ixQMgrAqmIfPeekPokeFastMutex[qId]))
- {
- return IX_FAIL;
- }
-
- /* Else read the entry directly from SRAM. This will not move the read pointer */
- while(qEntrySizeInwords--)
- {
- ixQMgrAqmIfWordWrite (entryAddress++, *entry++);
- }
-
- /* Release the lock */
- ixOsalFastMutexUnlock(&ixQMgrAqmIfPeekPokeFastMutex[qId]);
-
- /* Read the config register */
- ixQMgrAqmIfWordRead (cfgRegAddress, &configRegWordOnExit);
-
- /* Check that the read and write pointers have not changed */
- if (configRegWordOnEntry != configRegWordOnExit)
- {
- return IX_FAIL;
- }
-
- return IX_SUCCESS;
-}
-
-PRIVATE unsigned
-watermarkToAqmWatermark (IxQMgrWMLevel watermark )
-{
- unsigned aqmWatermark = 0;
-
- /*
- * Watermarks 0("000"),1("001"),2("010"),4("011"),
- * 8("100"),16("101"),32("110"),64("111")
- */
- aqmWatermark = ixQMgrAqmIfLog2 (watermark * 2);
-
- return aqmWatermark;
-}
-
-PRIVATE unsigned
-entrySizeToAqmEntrySize (IxQMgrQEntrySizeInWords entrySize)
-{
- /* entrySize 1("00"),2("01"),4("10") */
- return (ixQMgrAqmIfLog2 (entrySize));
-}
-
-PRIVATE unsigned
-bufferSizeToAqmBufferSize (unsigned bufferSizeInWords)
-{
- /* bufferSize 16("00"),32("01),64("10"),128("11") */
- return (ixQMgrAqmIfLog2 (bufferSizeInWords / IX_QMGR_MIN_BUFFER_SIZE));
-}
-
-/*
- * Reset AQM registers to default values.
- */
-PRIVATE void
-ixQMgrAqmIfRegistersReset (void)
-{
- volatile UINT32 *qConfigWordAddress = NULL;
- unsigned int i;
-
- /*
- * Need to initialize AQM hardware registers to an initial
- * value as init may have been called as a result of a soft
- * reset. i.e. soft reset does not reset hardware registers.
- */
-
- /* Reset queues 0..31 status registers 0..3 */
- ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUELOWSTAT0_OFFSET),
- IX_QMGR_QUELOWSTAT_RESET_VALUE);
- ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUELOWSTAT1_OFFSET),
- IX_QMGR_QUELOWSTAT_RESET_VALUE);
- ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUELOWSTAT2_OFFSET),
- IX_QMGR_QUELOWSTAT_RESET_VALUE);
- ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUELOWSTAT3_OFFSET),
- IX_QMGR_QUELOWSTAT_RESET_VALUE);
-
- /* Reset underflow/overflow status registers 0..1 */
- ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEUOSTAT0_OFFSET),
- IX_QMGR_QUEUOSTAT_RESET_VALUE);
- ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEUOSTAT1_OFFSET),
- IX_QMGR_QUEUOSTAT_RESET_VALUE);
-
- /* Reset queues 32..63 nearly empty status registers */
- ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEUPPSTAT0_OFFSET),
- IX_QMGR_QUEUPPSTAT0_RESET_VALUE);
-
- /* Reset queues 32..63 full status registers */
- ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEUPPSTAT1_OFFSET),
- IX_QMGR_QUEUPPSTAT1_RESET_VALUE);
-
- /* Reset int0 status flag source select registers 0..3 */
- ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_INT0SRCSELREG0_OFFSET),
- IX_QMGR_INT0SRCSELREG_RESET_VALUE);
- ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_INT0SRCSELREG1_OFFSET),
- IX_QMGR_INT0SRCSELREG_RESET_VALUE);
- ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_INT0SRCSELREG2_OFFSET),
- IX_QMGR_INT0SRCSELREG_RESET_VALUE);
- ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_INT0SRCSELREG3_OFFSET),
- IX_QMGR_INT0SRCSELREG_RESET_VALUE);
-
- /* Reset queue interrupt enable register 0..1 */
- ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEIEREG0_OFFSET),
- IX_QMGR_QUEIEREG_RESET_VALUE);
- ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEIEREG1_OFFSET),
- IX_QMGR_QUEIEREG_RESET_VALUE);
-
- /* Reset queue interrupt register 0..1 */
- ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QINTREG0_OFFSET),
- IX_QMGR_QINTREG_RESET_VALUE);
- ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QINTREG1_OFFSET),
- IX_QMGR_QINTREG_RESET_VALUE);
-
- /* Reset queue configuration words 0..63 */
- qConfigWordAddress = (UINT32 *)(aqmBaseAddress + IX_QMGR_QUECONFIG_BASE_OFFSET);
- for (i = 0; i < (IX_QMGR_QUECONFIG_SIZE / sizeof(UINT32)); i++)
- {
- ixQMgrAqmIfWordWrite(qConfigWordAddress,
- IX_QMGR_QUECONFIG_RESET_VALUE);
- /* Next word */
- qConfigWordAddress++;
- }
-}
-
+++ /dev/null
-/**
- * @file IxQMgrDispatcher.c
- *
- * @author Intel Corporation
- * @date 20-Dec-2001
- *
- * @brief This file contains the implementation of the Dispatcher sub component
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * User defined include files.
- */
-#include "IxQMgr.h"
-#include "IxQMgrAqmIf_p.h"
-#include "IxQMgrQCfg_p.h"
-#include "IxQMgrDispatcher_p.h"
-#include "IxQMgrLog_p.h"
-#include "IxQMgrDefines_p.h"
-#include "IxFeatureCtrl.h"
-#include "IxOsal.h"
-
-
-
-/*
- * #defines and macros used in this file.
- */
-
-
-/*
- * This constant is used to indicate the number of priority levels supported
- */
-#define IX_QMGR_NUM_PRIORITY_LEVELS 3
-
-/*
- * This constant is used to set the size of the array of status words
- */
-#define MAX_Q_STATUS_WORDS 4
-
-/*
- * This macro is used to check if a given priority is valid
- */
-#define IX_QMGR_DISPATCHER_PRIORITY_CHECK(priority) \
-(((priority) >= IX_QMGR_Q_PRIORITY_0) && ((priority) <= IX_QMGR_Q_PRIORITY_2))
-
-/*
- * This macto is used to check that a given interrupt source is valid
- */
-#define IX_QMGR_DISPATCHER_SOURCE_ID_CHECK(srcSel) \
-(((srcSel) >= IX_QMGR_Q_SOURCE_ID_E) && ((srcSel) <= IX_QMGR_Q_SOURCE_ID_NOT_F))
-
-/*
- * Number of times a dummy callback is called before logging a trace
- * message
- */
-#define LOG_THROTTLE_COUNT 1000000
-
-/* Priority tables limits */
-#define IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX (0)
-#define IX_QMGR_MID_LOW_QUE_PRIORITY_TABLE_INDEX (16)
-#define IX_QMGR_MAX_LOW_QUE_PRIORITY_TABLE_INDEX (31)
-#define IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX (32)
-#define IX_QMGR_MID_UPP_QUE_PRIORITY_TABLE_INDEX (48)
-#define IX_QMGR_MAX_UPP_QUE_PRIORITY_TABLE_INDEX (63)
-
-/*
- * This macro is used to check if a given callback type is valid
- */
-#define IX_QMGR_DISPATCHER_CALLBACK_TYPE_CHECK(type) \
- (((type) >= IX_QMGR_TYPE_REALTIME_OTHER) && \
- ((type) <= IX_QMGR_TYPE_REALTIME_SPORADIC))
-
-/*
- * define max index in lower queue to use in loops
- */
-#define IX_QMGR_MAX_LOW_QUE_TABLE_INDEX (31)
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/*
- * Information on a queue needed by the Dispatcher
- */
-typedef struct
-{
- IxQMgrCallback callback; /* Notification callback */
- IxQMgrCallbackId callbackId; /* Notification callback identifier */
- unsigned dummyCallbackCount; /* Number of times runs of dummy callback */
- IxQMgrPriority priority; /* Dispatch priority */
- unsigned int statusWordOffset; /* Offset to the status word to check */
- UINT32 statusMask; /* Status mask */
- UINT32 statusCheckValue; /* Status check value */
- UINT32 intRegCheckMask; /* Interrupt register check mask */
-} IxQMgrQInfo;
-
-/*
- * Variable declarations global to this file. Externs are followed by
- * statics.
- */
-
-/*
- * Flag to keep record of what dispatcher set in featureCtrl when ixQMgrInit()
- * is called. This is needed because it is possible that a client might
- * change whether the live lock prevention dispatcher is used between
- * calls to ixQMgrInit() and ixQMgrDispatcherLoopGet().
- */
-PRIVATE IX_STATUS ixQMgrOrigB0Dispatcher = IX_FEATURE_CTRL_COMPONENT_ENABLED;
-
-/*
- * keep record of Q types - not in IxQMgrQInfo for performance as
- * it is only used with ixQMgrDispatcherLoopRunB0LLP()
- */
-PRIVATE IxQMgrType ixQMgrQTypes[IX_QMGR_MAX_NUM_QUEUES];
-
-/*
- * This array contains a list of queue identifiers ordered by priority. The table
- * is split logically between queue identifiers 0-31 and 32-63.
- */
-static IxQMgrQId priorityTable[IX_QMGR_MAX_NUM_QUEUES];
-
-/*
- * This flag indicates to the dispatcher that the priority table needs to be rebuilt.
- */
-static BOOL rebuildTable = false;
-
-/* Dispatcher statistics */
-static IxQMgrDispatcherStats dispatcherStats;
-
-/* Table of queue information */
-static IxQMgrQInfo dispatchQInfo[IX_QMGR_MAX_NUM_QUEUES];
-
-/* Masks use to identify the first queues in the priority tables
-* when comparing with the interrupt register
-*/
-static unsigned int lowPriorityTableFirstHalfMask;
-static unsigned int uppPriorityTableFirstHalfMask;
-
-/*
- * Static function prototypes
- */
-
-/*
- * This function is the default callback for all queues
- */
-PRIVATE void
-dummyCallback (IxQMgrQId qId,
- IxQMgrCallbackId cbId);
-
-PRIVATE void
-ixQMgrDispatcherReBuildPriorityTable (void);
-
-/*
- * Function definitions.
- */
-void
-ixQMgrDispatcherInit (void)
-{
- int i;
- IxFeatureCtrlProductId productId = 0;
- IxFeatureCtrlDeviceId deviceId = 0;
- BOOL stickyIntSilicon = true;
-
- /* Set default priorities */
- for (i=0; i< IX_QMGR_MAX_NUM_QUEUES; i++)
- {
- dispatchQInfo[i].callback = dummyCallback;
- dispatchQInfo[i].callbackId = 0;
- dispatchQInfo[i].dummyCallbackCount = 0;
- dispatchQInfo[i].priority = IX_QMGR_Q_PRIORITY_2;
- dispatchQInfo[i].statusWordOffset = 0;
- dispatchQInfo[i].statusCheckValue = 0;
- dispatchQInfo[i].statusMask = 0;
- /*
- * There are two interrupt registers, 32 bits each. One for the lower
- * queues(0-31) and one for the upper queues(32-63). Therefore need to
- * mod by 32 i.e the min upper queue identifier.
- */
- dispatchQInfo[i].intRegCheckMask = (1<<(i%(IX_QMGR_MIN_QUEUPP_QID)));
-
- /*
- * Set the Q types - will only be used with livelock
- */
- ixQMgrQTypes[i] = IX_QMGR_TYPE_REALTIME_OTHER;
-
- /* Reset queue statistics */
- dispatcherStats.queueStats[i].callbackCnt = 0;
- dispatcherStats.queueStats[i].priorityChangeCnt = 0;
- dispatcherStats.queueStats[i].intNoCallbackCnt = 0;
- dispatcherStats.queueStats[i].intLostCallbackCnt = 0;
- dispatcherStats.queueStats[i].notificationEnabled = false;
- dispatcherStats.queueStats[i].srcSel = 0;
-
- }
-
- /* Priority table. Order the table from queue 0 to 63 */
- ixQMgrDispatcherReBuildPriorityTable();
-
- /* Reset statistics */
- dispatcherStats.loopRunCnt = 0;
-
- /* Get the device ID for the underlying silicon */
- deviceId = ixFeatureCtrlDeviceRead();
-
- /* Get the product ID for the underlying silicon */
- productId = ixFeatureCtrlProductIdRead();
-
- /*
- * Check featureCtrl to see if Livelock prevention is required
- */
- ixQMgrOrigB0Dispatcher = ixFeatureCtrlSwConfigurationCheck(
- IX_FEATURECTRL_ORIGB0_DISPATCHER);
-
- /*
- * Check if the silicon supports the sticky interrupt feature.
- * IF (IXP42X AND A0) -> No sticky interrupt feature supported
- */
- if ((IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X ==
- (IX_FEATURE_CTRL_DEVICE_TYPE_MASK & deviceId)) &&
- (IX_FEATURE_CTRL_SILICON_TYPE_A0 ==
- (IX_FEATURE_CTRL_SILICON_STEPPING_MASK & productId)))
- {
- stickyIntSilicon = false;
- }
-
- /*
- * IF user wants livelock prev option AND silicon supports sticky interrupt
- * feature -> enable the sticky interrupt bit
- */
- if ((IX_FEATURE_CTRL_SWCONFIG_DISABLED == ixQMgrOrigB0Dispatcher) &&
- stickyIntSilicon)
- {
- ixQMgrStickyInterruptRegEnable();
- }
-}
-
-IX_STATUS
-ixQMgrDispatcherPrioritySet (IxQMgrQId qId,
- IxQMgrPriority priority)
-{
- int ixQMgrLockKey;
-
- if (!ixQMgrQIsConfigured(qId))
- {
- return IX_QMGR_Q_NOT_CONFIGURED;
- }
-
- if (!IX_QMGR_DISPATCHER_PRIORITY_CHECK(priority))
- {
- return IX_QMGR_Q_INVALID_PRIORITY;
- }
-
- ixQMgrLockKey = ixOsalIrqLock();
-
- /* Change priority */
- dispatchQInfo[qId].priority = priority;
- /* Set flag */
- rebuildTable = true;
-
- ixOsalIrqUnlock(ixQMgrLockKey);
-
-#ifndef NDEBUG
- /* Update statistics */
- dispatcherStats.queueStats[qId].priorityChangeCnt++;
-#endif
-
- return IX_SUCCESS;
-}
-
-IX_STATUS
-ixQMgrNotificationCallbackSet (IxQMgrQId qId,
- IxQMgrCallback callback,
- IxQMgrCallbackId callbackId)
-{
- if (!ixQMgrQIsConfigured(qId))
- {
- return IX_QMGR_Q_NOT_CONFIGURED;
- }
-
- if (NULL == callback)
- {
- /* Reset to dummy callback */
- dispatchQInfo[qId].callback = dummyCallback;
- dispatchQInfo[qId].dummyCallbackCount = 0;
- dispatchQInfo[qId].callbackId = 0;
- }
- else
- {
- dispatchQInfo[qId].callback = callback;
- dispatchQInfo[qId].callbackId = callbackId;
- }
-
- return IX_SUCCESS;
-}
-
-IX_STATUS
-ixQMgrNotificationEnable (IxQMgrQId qId,
- IxQMgrSourceId srcSel)
-{
- IxQMgrQStatus qStatusOnEntry;/* The queue status on entry/exit */
- IxQMgrQStatus qStatusOnExit; /* to this function */
- int ixQMgrLockKey;
-
-#ifndef NDEBUG
- if (!ixQMgrQIsConfigured (qId))
- {
- return IX_QMGR_Q_NOT_CONFIGURED;
- }
-
- if ((qId < IX_QMGR_MIN_QUEUPP_QID) &&
- !IX_QMGR_DISPATCHER_SOURCE_ID_CHECK(srcSel))
- {
- /* QId 0-31 source id invalid */
- return IX_QMGR_INVALID_INT_SOURCE_ID;
- }
-
- if ((IX_QMGR_Q_SOURCE_ID_NE != srcSel) &&
- (qId >= IX_QMGR_MIN_QUEUPP_QID))
- {
- /*
- * For queues 32-63 the interrupt source is fixed to the Nearly
- * Empty status flag and therefore should have a srcSel of NE.
- */
- return IX_QMGR_INVALID_INT_SOURCE_ID;
- }
-#endif
-
-#ifndef NDEBUG
- dispatcherStats.queueStats[qId].notificationEnabled = true;
- dispatcherStats.queueStats[qId].srcSel = srcSel;
-#endif
-
- /* Get the current queue status */
- ixQMgrAqmIfQueStatRead (qId, &qStatusOnEntry);
-
- /*
- * Enabling interrupts results in Read-Modify-Write
- * so need critical section
- */
-
- ixQMgrLockKey = ixOsalIrqLock();
-
- /* Calculate the checkMask and checkValue for this q */
- ixQMgrAqmIfQStatusCheckValsCalc (qId,
- srcSel,
- &dispatchQInfo[qId].statusWordOffset,
- &dispatchQInfo[qId].statusCheckValue,
- &dispatchQInfo[qId].statusMask);
-
-
- /* Set the interrupt source is this queue is in the range 0-31 */
- if (qId < IX_QMGR_MIN_QUEUPP_QID)
- {
- ixQMgrAqmIfIntSrcSelWrite (qId, srcSel);
- }
-
- /* Enable the interrupt */
- ixQMgrAqmIfQInterruptEnable (qId);
-
- ixOsalIrqUnlock(ixQMgrLockKey);
-
- /* Get the current queue status */
- ixQMgrAqmIfQueStatRead (qId, &qStatusOnExit);
-
- /* If the status has changed return a warning */
- if (qStatusOnEntry != qStatusOnExit)
- {
- return IX_QMGR_WARNING;
- }
-
- return IX_SUCCESS;
-}
-
-
-IX_STATUS
-ixQMgrNotificationDisable (IxQMgrQId qId)
-{
- int ixQMgrLockKey;
-
-#ifndef NDEBUG
- /* Validate parameters */
- if (!ixQMgrQIsConfigured (qId))
- {
- return IX_QMGR_Q_NOT_CONFIGURED;
- }
-#endif
-
- /*
- * Enabling interrupts results in Read-Modify-Write
- * so need critical section
- */
-#ifndef NDEBUG
- dispatcherStats.queueStats[qId].notificationEnabled = false;
-#endif
-
- ixQMgrLockKey = ixOsalIrqLock();
-
- ixQMgrAqmIfQInterruptDisable (qId);
-
- ixOsalIrqUnlock(ixQMgrLockKey);
-
- return IX_SUCCESS;
-}
-
-void
-ixQMgrStickyInterruptRegEnable(void)
-{
- /* Use Aqm If function to set Interrupt Register0 Bit-3 */
- ixQMgrAqmIfIntSrcSelReg0Bit3Set ();
-}
-
-#if !defined __XSCALE__ || defined __linux
-
-/* Count the number of leading zero bits in a word,
- * and return the same value than the CLZ instruction.
- *
- * word (in) return value (out)
- * 0x80000000 0
- * 0x40000000 1
- * ,,, ,,,
- * 0x00000002 30
- * 0x00000001 31
- * 0x00000000 32
- *
- * The C version of this function is used as a replacement
- * for system not providing the equivalent of the CLZ
- * assembly language instruction.
- *
- * Note that this version is big-endian
- */
-unsigned int
-ixQMgrCountLeadingZeros(UINT32 word)
-{
- unsigned int leadingZerosCount = 0;
-
- if (word == 0)
- {
- return 32;
- }
- /* search the first bit set by testing the MSB and shifting the input word */
- while ((word & 0x80000000) == 0)
- {
- word <<= 1;
- leadingZerosCount++;
- }
- return leadingZerosCount;
-}
-#endif /* not __XSCALE__ or __linux */
-
-void
-ixQMgrDispatcherLoopGet (IxQMgrDispatcherFuncPtr *qDispatcherFuncPtr)
-{
- IxFeatureCtrlProductId productId = 0;
- IxFeatureCtrlDeviceId deviceId = 0;
-
- /* Get the device ID for the underlying silicon */
- deviceId = ixFeatureCtrlDeviceRead();
-
- /* Get the product ID for the underlying silicon */
- productId = ixFeatureCtrlProductIdRead ();
-
- /* IF (IXP42X AND A0 silicon) -> use ixQMgrDispatcherLoopRunA0 */
- if ((IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X ==
- (IX_FEATURE_CTRL_DEVICE_TYPE_MASK & deviceId)) &&
- (IX_FEATURE_CTRL_SILICON_TYPE_A0 ==
- (IX_FEATURE_CTRL_SILICON_STEPPING_MASK & productId)))
- {
- /*For IXP42X A0 silicon */
- *qDispatcherFuncPtr = &ixQMgrDispatcherLoopRunA0 ;
- }
- else /*For IXP42X B0 or IXP46X silicon*/
- {
- if (IX_FEATURE_CTRL_SWCONFIG_ENABLED == ixQMgrOrigB0Dispatcher)
- {
- /* Default for IXP42X B0 and IXP46X silicon */
- *qDispatcherFuncPtr = &ixQMgrDispatcherLoopRunB0;
- }
- else
- {
- /* FeatureCtrl indicated that livelock dispatcher be used */
- *qDispatcherFuncPtr = &ixQMgrDispatcherLoopRunB0LLP;
- }
- }
-}
-
-void
-ixQMgrDispatcherLoopRunA0 (IxQMgrDispatchGroup group)
-{
- UINT32 intRegVal; /* Interrupt reg val */
- UINT32 intRegValAfterWrite; /* Interrupt reg val after writing back */
- UINT32 intRegCheckMask; /* Mask for checking interrupt bits */
- UINT32 qStatusWordsB4Write[MAX_Q_STATUS_WORDS]; /* Status b4 interrupt write */
- UINT32 qStatusWordsAfterWrite[MAX_Q_STATUS_WORDS]; /* Status after interrupt write */
- IxQMgrQInfo *currDispatchQInfo;
- BOOL statusChangeFlag;
-
- int priorityTableIndex;/* Priority table index */
- int qIndex; /* Current queue being processed */
- int endIndex; /* Index of last queue to process */
-
-#ifndef NDEBUG
- IX_OSAL_ASSERT((group == IX_QMGR_QUEUPP_GROUP) ||
- (group == IX_QMGR_QUELOW_GROUP));
-#endif
-
- /* Read Q status registers before interrupt status read/write */
- ixQMgrAqmIfQStatusRegsRead (group, qStatusWordsB4Write);
-
- /* Read the interrupt register */
- ixQMgrAqmIfQInterruptRegRead (group, &intRegVal);
-
- /* No bit set : nothing to process (the reaminder of the algorithm is
- * based on the fact that the interrupt register value contains at
- * least one bit set
- */
- if (intRegVal == 0)
- {
-#ifndef NDEBUG
- /* Update statistics */
- dispatcherStats.loopRunCnt++;
-#endif
-
- /* Rebuild the priority table if needed */
- if (rebuildTable)
- {
- ixQMgrDispatcherReBuildPriorityTable ();
- }
-
- return;
- }
-
- /* Write it back to clear the interrupt */
- ixQMgrAqmIfQInterruptRegWrite (group, intRegVal);
-
- /* Read Q status registers after interrupt status read/write */
- ixQMgrAqmIfQStatusRegsRead (group, qStatusWordsAfterWrite);
-
- /* get the first queue Id from the interrupt register value */
- qIndex = (BITS_PER_WORD - 1) - ixQMgrCountLeadingZeros(intRegVal);
-
- /* check if any change occured during hw register modifications */
- if (IX_QMGR_QUELOW_GROUP == group)
- {
- statusChangeFlag =
- (qStatusWordsB4Write[0] != qStatusWordsAfterWrite[0]) ||
- (qStatusWordsB4Write[1] != qStatusWordsAfterWrite[1]) ||
- (qStatusWordsB4Write[2] != qStatusWordsAfterWrite[2]) ||
- (qStatusWordsB4Write[3] != qStatusWordsAfterWrite[3]);
- }
- else
- {
- statusChangeFlag =
- (qStatusWordsB4Write[0] != qStatusWordsAfterWrite[0]);
- /* Set the queue range based on the queue group to proccess */
- qIndex += IX_QMGR_MIN_QUEUPP_QID;
- }
-
- if (statusChangeFlag == false)
- {
- /* check if the interrupt register contains
- * only 1 bit set (happy day scenario)
- */
- currDispatchQInfo = &dispatchQInfo[qIndex];
- if (intRegVal == currDispatchQInfo->intRegCheckMask)
- {
- /* only 1 queue event triggered a notification *
- * Call the callback function for this queue
- */
- currDispatchQInfo->callback (qIndex,
- currDispatchQInfo->callbackId);
-#ifndef NDEBUG
- /* Update statistics */
- dispatcherStats.queueStats[qIndex].callbackCnt++;
-#endif
- }
- else
- {
- /* the event is triggered by more than 1 queue,
- * the queue search will be starting from the beginning
- * or the middle of the priority table
- *
- * the serach will end when all the bits of the interrupt
- * register are cleared. There is no need to maintain
- * a seperate value and test it at each iteration.
- */
- if (IX_QMGR_QUELOW_GROUP == group)
- {
- /* check if any bit related to queues in the first
- * half of the priority table is set
- */
- if (intRegVal & lowPriorityTableFirstHalfMask)
- {
- priorityTableIndex = IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX;
- }
- else
- {
- priorityTableIndex = IX_QMGR_MID_LOW_QUE_PRIORITY_TABLE_INDEX;
- }
- }
- else
- {
- /* check if any bit related to queues in the first
- * half of the priority table is set
- */
- if (intRegVal & uppPriorityTableFirstHalfMask)
- {
- priorityTableIndex = IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX;
- }
- else
- {
- priorityTableIndex = IX_QMGR_MID_UPP_QUE_PRIORITY_TABLE_INDEX;
- }
- }
-
- /* iterate following the priority table until all the bits
- * of the interrupt register are cleared.
- */
- do
- {
- qIndex = priorityTable[priorityTableIndex++];
- currDispatchQInfo = &dispatchQInfo[qIndex];
- intRegCheckMask = currDispatchQInfo->intRegCheckMask;
-
- /* If this queue caused this interrupt to be raised */
- if (intRegVal & intRegCheckMask)
- {
- /* Call the callback function for this queue */
- currDispatchQInfo->callback (qIndex,
- currDispatchQInfo->callbackId);
-#ifndef NDEBUG
- /* Update statistics */
- dispatcherStats.queueStats[qIndex].callbackCnt++;
-#endif
-
- /* Clear the interrupt register bit */
- intRegVal &= ~intRegCheckMask;
- }
- }
- while(intRegVal);
- }
- }
- else
- {
- /* A change in queue status occured during the hw interrupt
- * register update. To maintain the interrupt consistency, it
- * is necessary to iterate through all queues of the queue group.
- */
-
- /* Read interrupt status again */
- ixQMgrAqmIfQInterruptRegRead (group, &intRegValAfterWrite);
-
- if (IX_QMGR_QUELOW_GROUP == group)
- {
- priorityTableIndex = IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX;
- endIndex = IX_QMGR_MAX_LOW_QUE_PRIORITY_TABLE_INDEX;
- }
- else
- {
- priorityTableIndex = IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX;
- endIndex = IX_QMGR_MAX_UPP_QUE_PRIORITY_TABLE_INDEX;
- }
-
- for ( ; priorityTableIndex<=endIndex; priorityTableIndex++)
- {
- qIndex = priorityTable[priorityTableIndex];
- currDispatchQInfo = &dispatchQInfo[qIndex];
- intRegCheckMask = currDispatchQInfo->intRegCheckMask;
-
- /* If this queue caused this interrupt to be raised */
- if (intRegVal & intRegCheckMask)
- {
- /* Call the callback function for this queue */
- currDispatchQInfo->callback (qIndex,
- currDispatchQInfo->callbackId);
-#ifndef NDEBUG
- /* Update statistics */
- dispatcherStats.queueStats[qIndex].callbackCnt++;
-#endif
-
- } /* if (intRegVal .. */
-
- /*
- * If interrupt bit is set in intRegValAfterWrite don't
- * proceed as this will be caught in next interrupt
- */
- else if ((intRegValAfterWrite & intRegCheckMask) == 0)
- {
- /* Check if an interrupt was lost for this Q */
- if (ixQMgrAqmIfQStatusCheck(qStatusWordsB4Write,
- qStatusWordsAfterWrite,
- currDispatchQInfo->statusWordOffset,
- currDispatchQInfo->statusCheckValue,
- currDispatchQInfo->statusMask))
- {
- /* Call the callback function for this queue */
- currDispatchQInfo->callback (qIndex,
- dispatchQInfo[qIndex].callbackId);
-#ifndef NDEBUG
- /* Update statistics */
- dispatcherStats.queueStats[qIndex].callbackCnt++;
- dispatcherStats.queueStats[qIndex].intLostCallbackCnt++;
-#endif
- } /* if ixQMgrAqmIfQStatusCheck(.. */
- } /* else if ((intRegValAfterWrite ... */
- } /* for (priorityTableIndex=0 ... */
- }
-
- /* Rebuild the priority table if needed */
- if (rebuildTable)
- {
- ixQMgrDispatcherReBuildPriorityTable ();
- }
-
-#ifndef NDEBUG
- /* Update statistics */
- dispatcherStats.loopRunCnt++;
-#endif
-}
-
-
-
-void
-ixQMgrDispatcherLoopRunB0 (IxQMgrDispatchGroup group)
-{
- UINT32 intRegVal; /* Interrupt reg val */
- UINT32 intRegCheckMask; /* Mask for checking interrupt bits */
- IxQMgrQInfo *currDispatchQInfo;
-
-
- int priorityTableIndex; /* Priority table index */
- int qIndex; /* Current queue being processed */
-
-#ifndef NDEBUG
- IX_OSAL_ASSERT((group == IX_QMGR_QUEUPP_GROUP) ||
- (group == IX_QMGR_QUELOW_GROUP));
- IX_OSAL_ASSERT((group == IX_QMGR_QUEUPP_GROUP) ||
- (group == IX_QMGR_QUELOW_GROUP));
-#endif
-
- /* Read the interrupt register */
- ixQMgrAqmIfQInterruptRegRead (group, &intRegVal);
-
-
- /* No queue has interrupt register set */
- if (intRegVal != 0)
- {
-
- /* Write it back to clear the interrupt */
- ixQMgrAqmIfQInterruptRegWrite (group, intRegVal);
-
- /* get the first queue Id from the interrupt register value */
- qIndex = (BITS_PER_WORD - 1) - ixQMgrCountLeadingZeros(intRegVal);
-
- if (IX_QMGR_QUEUPP_GROUP == group)
- {
- /* Set the queue range based on the queue group to proccess */
- qIndex += IX_QMGR_MIN_QUEUPP_QID;
- }
-
- /* check if the interrupt register contains
- * only 1 bit set
- * For example:
- * intRegVal = 0x0010
- * currDispatchQInfo->intRegCheckMask = 0x0010
- * intRegVal == currDispatchQInfo->intRegCheckMask is true.
- */
- currDispatchQInfo = &dispatchQInfo[qIndex];
- if (intRegVal == currDispatchQInfo->intRegCheckMask)
- {
- /* only 1 queue event triggered a notification *
- * Call the callback function for this queue
- */
- currDispatchQInfo->callback (qIndex,
- currDispatchQInfo->callbackId);
-#ifndef NDEBUG
- /* Update statistics */
- dispatcherStats.queueStats[qIndex].callbackCnt++;
-#endif
- }
- else
- {
- /* the event is triggered by more than 1 queue,
- * the queue search will be starting from the beginning
- * or the middle of the priority table
- *
- * the serach will end when all the bits of the interrupt
- * register are cleared. There is no need to maintain
- * a seperate value and test it at each iteration.
- */
- if (IX_QMGR_QUELOW_GROUP == group)
- {
- /* check if any bit related to queues in the first
- * half of the priority table is set
- */
- if (intRegVal & lowPriorityTableFirstHalfMask)
- {
- priorityTableIndex = IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX;
- }
- else
- {
- priorityTableIndex = IX_QMGR_MID_LOW_QUE_PRIORITY_TABLE_INDEX;
- }
- }
- else
- {
- /* check if any bit related to queues in the first
- * half of the priority table is set
- */
- if (intRegVal & uppPriorityTableFirstHalfMask)
- {
- priorityTableIndex = IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX;
- }
- else
- {
- priorityTableIndex = IX_QMGR_MID_UPP_QUE_PRIORITY_TABLE_INDEX;
- }
- }
-
- /* iterate following the priority table until all the bits
- * of the interrupt register are cleared.
- */
- do
- {
- qIndex = priorityTable[priorityTableIndex++];
- currDispatchQInfo = &dispatchQInfo[qIndex];
- intRegCheckMask = currDispatchQInfo->intRegCheckMask;
-
- /* If this queue caused this interrupt to be raised */
- if (intRegVal & intRegCheckMask)
- {
- /* Call the callback function for this queue */
- currDispatchQInfo->callback (qIndex,
- currDispatchQInfo->callbackId);
-#ifndef NDEBUG
- /* Update statistics */
- dispatcherStats.queueStats[qIndex].callbackCnt++;
-#endif
-
- /* Clear the interrupt register bit */
- intRegVal &= ~intRegCheckMask;
- }
- }
- while(intRegVal);
- } /*End of intRegVal == currDispatchQInfo->intRegCheckMask */
- } /* End of intRegVal != 0 */
-
-#ifndef NDEBUG
- /* Update statistics */
- dispatcherStats.loopRunCnt++;
-#endif
-
- /* Rebuild the priority table if needed */
- if (rebuildTable)
- {
- ixQMgrDispatcherReBuildPriorityTable ();
- }
-}
-
-void
-ixQMgrDispatcherLoopRunB0LLP (IxQMgrDispatchGroup group)
-{
- UINT32 intRegVal =0; /* Interrupt reg val */
- UINT32 intRegCheckMask; /* Mask for checking interrupt bits */
- IxQMgrQInfo *currDispatchQInfo;
-
- int priorityTableIndex; /* Priority table index */
- int qIndex; /* Current queue being processed */
-
- UINT32 intRegValCopy = 0;
- UINT32 intEnableRegVal = 0;
- UINT8 i = 0;
-
-#ifndef NDEBUG
- IX_OSAL_ASSERT((group == IX_QMGR_QUEUPP_GROUP) ||
- (group == IX_QMGR_QUELOW_GROUP));
-#endif
-
- /* Read the interrupt register */
- ixQMgrAqmIfQInterruptRegRead (group, &intRegVal);
-
- /*
- * mask any interrupts that are not enabled
- */
- ixQMgrAqmIfQInterruptEnableRegRead (group, &intEnableRegVal);
- intRegVal &= intEnableRegVal;
-
- /* No queue has interrupt register set */
- if (intRegVal != 0)
- {
- if (IX_QMGR_QUELOW_GROUP == group)
- {
- /*
- * As the sticky bit is set, the interrupt register will
- * not clear if write back at this point because the condition
- * has not been cleared. Take a copy and write back later after
- * the condition has been cleared
- */
- intRegValCopy = intRegVal;
- }
- else
- {
- /* no sticky for upper Q's, so write back now */
- ixQMgrAqmIfQInterruptRegWrite (group, intRegVal);
- }
-
- /* get the first queue Id from the interrupt register value */
- qIndex = (BITS_PER_WORD - 1) - ixQMgrCountLeadingZeros(intRegVal);
-
- if (IX_QMGR_QUEUPP_GROUP == group)
- {
- /* Set the queue range based on the queue group to proccess */
- qIndex += IX_QMGR_MIN_QUEUPP_QID;
- }
-
- /* check if the interrupt register contains
- * only 1 bit set
- * For example:
- * intRegVal = 0x0010
- * currDispatchQInfo->intRegCheckMask = 0x0010
- * intRegVal == currDispatchQInfo->intRegCheckMask is true.
- */
- currDispatchQInfo = &dispatchQInfo[qIndex];
- if (intRegVal == currDispatchQInfo->intRegCheckMask)
- {
-
- /*
- * check if Q type periodic - only lower queues can
- * have there type set to periodic
- */
- if (IX_QMGR_TYPE_REALTIME_PERIODIC == ixQMgrQTypes[qIndex])
- {
- /*
- * Disable the notifications on any sporadics
- */
- for (i=0; i <= IX_QMGR_MAX_LOW_QUE_TABLE_INDEX; i++)
- {
- if (IX_QMGR_TYPE_REALTIME_SPORADIC == ixQMgrQTypes[i])
- {
- ixQMgrNotificationDisable(i);
-#ifndef NDEBUG
- /* Update statistics */
- dispatcherStats.queueStats[i].disableCount++;
-#endif
- }
- }
- }
-
- currDispatchQInfo->callback (qIndex,
- currDispatchQInfo->callbackId);
-#ifndef NDEBUG
- /* Update statistics */
- dispatcherStats.queueStats[qIndex].callbackCnt++;
-#endif
- }
- else
- {
- /* the event is triggered by more than 1 queue,
- * the queue search will be starting from the beginning
- * or the middle of the priority table
- *
- * the serach will end when all the bits of the interrupt
- * register are cleared. There is no need to maintain
- * a seperate value and test it at each iteration.
- */
- if (IX_QMGR_QUELOW_GROUP == group)
- {
- /* check if any bit related to queues in the first
- * half of the priority table is set
- */
- if (intRegVal & lowPriorityTableFirstHalfMask)
- {
- priorityTableIndex =
- IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX;
- }
- else
- {
- priorityTableIndex =
- IX_QMGR_MID_LOW_QUE_PRIORITY_TABLE_INDEX;
- }
- }
- else
- {
- /* check if any bit related to queues in the first
- * half of the priority table is set
- */
- if (intRegVal & uppPriorityTableFirstHalfMask)
- {
- priorityTableIndex =
- IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX;
- }
- else
- {
- priorityTableIndex =
- IX_QMGR_MID_UPP_QUE_PRIORITY_TABLE_INDEX;
- }
- }
-
- /* iterate following the priority table until all the bits
- * of the interrupt register are cleared.
- */
- do
- {
- qIndex = priorityTable[priorityTableIndex++];
- currDispatchQInfo = &dispatchQInfo[qIndex];
- intRegCheckMask = currDispatchQInfo->intRegCheckMask;
-
- /* If this queue caused this interrupt to be raised */
- if (intRegVal & intRegCheckMask)
- {
- /*
- * check if Q type periodic - only lower queues can
- * have there type set to periodic. There can only be one
- * periodic queue, so the sporadics are only disabled once.
- */
- if (IX_QMGR_TYPE_REALTIME_PERIODIC == ixQMgrQTypes[qIndex])
- {
- /*
- * Disable the notifications on any sporadics
- */
- for (i=0; i <= IX_QMGR_MAX_LOW_QUE_TABLE_INDEX; i++)
- {
- if (IX_QMGR_TYPE_REALTIME_SPORADIC ==
- ixQMgrQTypes[i])
- {
- ixQMgrNotificationDisable(i);
- /*
- * remove from intRegVal as we don't want
- * to service any sporadics now
- */
- intRegVal &= ~dispatchQInfo[i].intRegCheckMask;
-#ifndef NDEBUG
- /* Update statistics */
- dispatcherStats.queueStats[i].disableCount++;
-#endif
- }
- }
- }
-
- currDispatchQInfo->callback (qIndex,
- currDispatchQInfo->callbackId);
-#ifndef NDEBUG
- /* Update statistics */
- dispatcherStats.queueStats[qIndex].callbackCnt++;
-#endif
- /* Clear the interrupt register bit */
- intRegVal &= ~intRegCheckMask;
- }
- }
- while(intRegVal);
- } /*End of intRegVal == currDispatchQInfo->intRegCheckMask */
- } /* End of intRegVal != 0 */
-
-#ifndef NDEBUG
- /* Update statistics */
- dispatcherStats.loopRunCnt++;
-#endif
-
- if ((intRegValCopy != 0) && (IX_QMGR_QUELOW_GROUP == group))
- {
- /*
- * lower groups (therefore sticky) AND at least one enabled interrupt
- * Write back to clear the interrupt
- */
- ixQMgrAqmIfQInterruptRegWrite (IX_QMGR_QUELOW_GROUP, intRegValCopy);
- }
-
- /* Rebuild the priority table if needed */
- if (rebuildTable)
- {
- ixQMgrDispatcherReBuildPriorityTable ();
- }
-}
-
-PRIVATE void
-ixQMgrDispatcherReBuildPriorityTable (void)
-{
- UINT32 qIndex;
- UINT32 priority;
- int lowQuePriorityTableIndex = IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX;
- int uppQuePriorityTableIndex = IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX;
-
- /* Reset the rebuild flag */
- rebuildTable = false;
-
- /* initialize the mak used to identify the queues in the first half
- * of the priority table
- */
- lowPriorityTableFirstHalfMask = 0;
- uppPriorityTableFirstHalfMask = 0;
-
- /* For each priority level */
- for(priority=0; priority<IX_QMGR_NUM_PRIORITY_LEVELS; priority++)
- {
- /* Foreach low queue in this priority */
- for(qIndex=0; qIndex<IX_QMGR_MIN_QUEUPP_QID; qIndex++)
- {
- if (dispatchQInfo[qIndex].priority == priority)
- {
- /* build the priority table bitmask which match the
- * queues of the first half of the priority table
- */
- if (lowQuePriorityTableIndex < IX_QMGR_MID_LOW_QUE_PRIORITY_TABLE_INDEX)
- {
- lowPriorityTableFirstHalfMask |= dispatchQInfo[qIndex].intRegCheckMask;
- }
- /* build the priority table */
- priorityTable[lowQuePriorityTableIndex++] = qIndex;
- }
- }
- /* Foreach upp queue */
- for(qIndex=IX_QMGR_MIN_QUEUPP_QID; qIndex<=IX_QMGR_MAX_QID; qIndex++)
- {
- if (dispatchQInfo[qIndex].priority == priority)
- {
- /* build the priority table bitmask which match the
- * queues of the first half of the priority table
- */
- if (uppQuePriorityTableIndex < IX_QMGR_MID_UPP_QUE_PRIORITY_TABLE_INDEX)
- {
- uppPriorityTableFirstHalfMask |= dispatchQInfo[qIndex].intRegCheckMask;
- }
- /* build the priority table */
- priorityTable[uppQuePriorityTableIndex++] = qIndex;
- }
- }
- }
-}
-
-IxQMgrDispatcherStats*
-ixQMgrDispatcherStatsGet (void)
-{
- return &dispatcherStats;
-}
-
-PRIVATE void
-dummyCallback (IxQMgrQId qId,
- IxQMgrCallbackId cbId)
-{
- /* Throttle the trace message */
- if ((dispatchQInfo[qId].dummyCallbackCount % LOG_THROTTLE_COUNT) == 0)
- {
- IX_QMGR_LOG_WARNING2("--> dummyCallback: qId (%d), callbackId (%d)\n",qId,cbId);
- }
- dispatchQInfo[qId].dummyCallbackCount++;
-
-#ifndef NDEBUG
- /* Update statistcs */
- dispatcherStats.queueStats[qId].intNoCallbackCnt++;
-#endif
-}
-void
-ixQMgrLLPShow (int resetStats)
-{
-#ifndef NDEBUG
- UINT8 i = 0;
- UINT32 intEnableRegVal = 0;
-
- printf ("Livelock statistics are printed on the fly.\n");
- printf ("qId Type EnableCnt DisableCnt IntEnableState Callbacks\n");
- printf ("=== ======== ========= ========== ============== =========\n");
-
- for (i=0; i<= IX_QMGR_MAX_LOW_QUE_TABLE_INDEX; i++)
- {
- if (ixQMgrQTypes[i] != IX_QMGR_TYPE_REALTIME_OTHER)
- {
- printf (" %2d ", i);
-
- if (ixQMgrQTypes[i] == IX_QMGR_TYPE_REALTIME_SPORADIC)
- {
- printf ("Sporadic");
- }
- else
- {
- printf ("Periodic");
- }
-
-
- ixQMgrAqmIfQInterruptEnableRegRead (IX_QMGR_QUELOW_GROUP,
- &intEnableRegVal);
-
-
- intEnableRegVal &= dispatchQInfo[i].intRegCheckMask;
- intEnableRegVal = intEnableRegVal >> i;
-
- printf (" %10d %10d %10d %10d\n",
- dispatcherStats.queueStats[i].enableCount,
- dispatcherStats.queueStats[i].disableCount,
- intEnableRegVal,
- dispatcherStats.queueStats[i].callbackCnt);
-
- if (resetStats)
- {
- dispatcherStats.queueStats[i].enableCount =
- dispatcherStats.queueStats[i].disableCount =
- dispatcherStats.queueStats[i].callbackCnt = 0;
- }
- }
- }
-#else
- IX_QMGR_LOG0("Livelock Prevention statistics are only collected in debug mode\n");
-#endif
-}
-
-void
-ixQMgrPeriodicDone (void)
-{
- UINT32 i = 0;
- UINT32 ixQMgrLockKey = 0;
-
- /*
- * for the lower queues
- */
- for (i=0; i <= IX_QMGR_MAX_LOW_QUE_TABLE_INDEX; i++)
- {
- /*
- * check for sporadics
- */
- if (IX_QMGR_TYPE_REALTIME_SPORADIC == ixQMgrQTypes[i])
- {
- /*
- * enable any sporadics
- */
- ixQMgrLockKey = ixOsalIrqLock();
- ixQMgrAqmIfQInterruptEnable(i);
- ixOsalIrqUnlock(ixQMgrLockKey);
-#ifndef NDEBUG
- /*
- * Update statistics
- */
- dispatcherStats.queueStats[i].enableCount++;
- dispatcherStats.queueStats[i].notificationEnabled = true;
-#endif
- }
- }
-}
-IX_STATUS
-ixQMgrCallbackTypeSet (IxQMgrQId qId,
- IxQMgrType type)
-{
- UINT32 ixQMgrLockKey = 0;
- IxQMgrType ixQMgrOldType =0;
-
-#ifndef NDEBUG
- if (!ixQMgrQIsConfigured(qId))
- {
- return IX_QMGR_Q_NOT_CONFIGURED;
- }
- if (qId >= IX_QMGR_MIN_QUEUPP_QID)
- {
- return IX_QMGR_PARAMETER_ERROR;
- }
- if(!IX_QMGR_DISPATCHER_CALLBACK_TYPE_CHECK(type))
- {
- return IX_QMGR_PARAMETER_ERROR;
- }
-#endif
-
- ixQMgrOldType = ixQMgrQTypes[qId];
- ixQMgrQTypes[qId] = type;
-
- /*
- * check if Q has been changed from type SPORADIC
- */
- if (IX_QMGR_TYPE_REALTIME_SPORADIC == ixQMgrOldType)
- {
- /*
- * previously Q was a SPORADIC, this means that LLP
- * might have had it disabled. enable it now.
- */
- ixQMgrLockKey = ixOsalIrqLock();
- ixQMgrAqmIfQInterruptEnable(qId);
- ixOsalIrqUnlock(ixQMgrLockKey);
-
-#ifndef NDEBUG
- /*
- * Update statistics
- */
- dispatcherStats.queueStats[qId].enableCount++;
-#endif
- }
-
- return IX_SUCCESS;
-}
-
-IX_STATUS
-ixQMgrCallbackTypeGet (IxQMgrQId qId,
- IxQMgrType *type)
-{
-#ifndef NDEBUG
- if (!ixQMgrQIsConfigured(qId))
- {
- return IX_QMGR_Q_NOT_CONFIGURED;
- }
- if (qId >= IX_QMGR_MIN_QUEUPP_QID)
- {
- return IX_QMGR_PARAMETER_ERROR;
- }
- if(type == NULL)
- {
- return IX_QMGR_PARAMETER_ERROR;
- }
-#endif
-
- *type = ixQMgrQTypes[qId];
- return IX_SUCCESS;
-}
+++ /dev/null
-/**
- * @file IxQMgrInit.c
- *
- * @author Intel Corporation
- * @date 30-Oct-2001
- *
- * @brief: Provided initialization of the QMgr component and its subcomponents.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * System defined include files.
- */
-
-/*
- * User defined include files.
- */
-#include "IxOsal.h"
-#include "IxQMgr.h"
-#include "IxQMgrQCfg_p.h"
-#include "IxQMgrDispatcher_p.h"
-#include "IxQMgrLog_p.h"
-#include "IxQMgrQAccess_p.h"
-#include "IxQMgrDefines_p.h"
-#include "IxQMgrAqmIf_p.h"
-
-/*
- * Set to true if initialized
- * N.B. global so integration/unit tests can reinitialize
- */
-BOOL qMgrIsInitialized = false;
-
-/*
- * Function definitions.
- */
-IX_STATUS
-ixQMgrInit (void)
-{
- if (qMgrIsInitialized)
- {
- IX_QMGR_LOG0("ixQMgrInit: IxQMgr already initialised\n");
- return IX_FAIL;
- }
-
- /* Initialise the QCfg component */
- ixQMgrQCfgInit ();
-
- /* Initialise the Dispatcher component */
- ixQMgrDispatcherInit ();
-
- /* Initialise the Access component */
- ixQMgrQAccessInit ();
-
- /* Initialization complete */
- qMgrIsInitialized = true;
-
- return IX_SUCCESS;
-}
-
-IX_STATUS
-ixQMgrUnload (void)
-{
- if (!qMgrIsInitialized)
- {
- return IX_FAIL;
- }
-
- /* Uninitialise the QCfg component */
- ixQMgrQCfgUninit ();
-
- /* Uninitialization complete */
- qMgrIsInitialized = false;
-
- return IX_SUCCESS;
-}
-
-void
-ixQMgrShow (void)
-{
- IxQMgrQCfgStats *qCfgStats = NULL;
- IxQMgrDispatcherStats *dispatcherStats = NULL;
- int i;
- UINT32 lowIntRegRead, upIntRegRead;
-
- qCfgStats = ixQMgrQCfgStatsGet ();
- dispatcherStats = ixQMgrDispatcherStatsGet ();
- ixQMgrAqmIfQInterruptRegRead (IX_QMGR_QUELOW_GROUP, &lowIntRegRead);
- ixQMgrAqmIfQInterruptRegRead (IX_QMGR_QUEUPP_GROUP, &upIntRegRead);
- printf("Generic Stats........\n");
- printf("=====================\n");
- printf("Loop Run Count..........%u\n",dispatcherStats->loopRunCnt);
- printf("Watermark set count.....%d\n", qCfgStats->wmSetCnt);
- printf("===========================================\n");
- printf("On the fly Interrupt Register Stats........\n");
- printf("===========================================\n");
- printf("Lower Interrupt Register............0x%08x\n",lowIntRegRead);
- printf("Upper Interrupt Register............0x%08x\n",upIntRegRead);
- printf("==============================================\n");
- printf("Queue Specific Stats........\n");
- printf("============================\n");
-
- for (i=0; i<IX_QMGR_MAX_NUM_QUEUES; i++)
- {
- if (ixQMgrQIsConfigured(i))
- {
- ixQMgrQShow(i);
- }
- }
-
- printf("============================\n");
-}
-
-IX_STATUS
-ixQMgrQShow (IxQMgrQId qId)
-{
- IxQMgrQCfgStats *qCfgStats = NULL;
- IxQMgrDispatcherStats *dispatcherStats = NULL;
-
- if (!ixQMgrQIsConfigured(qId))
- {
- return IX_QMGR_Q_NOT_CONFIGURED;
- }
-
- dispatcherStats = ixQMgrDispatcherStatsGet ();
- qCfgStats = ixQMgrQCfgQStatsGet (qId);
-
- printf("QId %d\n", qId);
- printf("======\n");
- printf(" IxQMgrQCfg Stats\n");
- printf(" Name..................... \"%s\"\n", qCfgStats->qStats[qId].qName);
- printf(" Size in words............ %u\n", qCfgStats->qStats[qId].qSizeInWords);
- printf(" Entry size in words...... %u\n", qCfgStats->qStats[qId].qEntrySizeInWords);
- printf(" Nearly empty watermark... %u\n", qCfgStats->qStats[qId].ne);
- printf(" Nearly full watermark.... %u\n", qCfgStats->qStats[qId].nf);
- printf(" Number of full entries... %u\n", qCfgStats->qStats[qId].numEntries);
- printf(" Sram base address........ 0x%X\n", qCfgStats->qStats[qId].baseAddress);
- printf(" Read pointer............. 0x%X\n", qCfgStats->qStats[qId].readPtr);
- printf(" Write pointer............ 0x%X\n", qCfgStats->qStats[qId].writePtr);
-
-#ifndef NDEBUG
- if (dispatcherStats->queueStats[qId].notificationEnabled)
- {
- char *localEvent = "none ????";
- switch (dispatcherStats->queueStats[qId].srcSel)
- {
- case IX_QMGR_Q_SOURCE_ID_E:
- localEvent = "Empty";
- break;
- case IX_QMGR_Q_SOURCE_ID_NE:
- localEvent = "Nearly Empty";
- break;
- case IX_QMGR_Q_SOURCE_ID_NF:
- localEvent = "Nearly Full";
- break;
- case IX_QMGR_Q_SOURCE_ID_F:
- localEvent = "Full";
- break;
- case IX_QMGR_Q_SOURCE_ID_NOT_E:
- localEvent = "Not Empty";
- break;
- case IX_QMGR_Q_SOURCE_ID_NOT_NE:
- localEvent = "Not Nearly Empty";
- break;
- case IX_QMGR_Q_SOURCE_ID_NOT_NF:
- localEvent = "Not Nearly Full";
- break;
- case IX_QMGR_Q_SOURCE_ID_NOT_F:
- localEvent = "Not Full";
- break;
- default :
- break;
- }
- printf(" Notifications localEvent...... %s\n", localEvent);
- }
- else
- {
- printf(" Notifications............ not enabled\n");
- }
- printf(" IxQMgrDispatcher Stats\n");
- printf(" Callback count................%d\n",
- dispatcherStats->queueStats[qId].callbackCnt);
- printf(" Priority change count.........%d\n",
- dispatcherStats->queueStats[qId].priorityChangeCnt);
- printf(" Interrupt no callback count...%d\n",
- dispatcherStats->queueStats[qId].intNoCallbackCnt);
- printf(" Interrupt lost callback count...%d\n",
- dispatcherStats->queueStats[qId].intLostCallbackCnt);
-#endif
-
- return IX_SUCCESS;
-}
-
-
-
-
+++ /dev/null
-/**
- * @file IxQMgrQAccess.c
- *
- * @author Intel Corporation
- * @date 30-Oct-2001
- *
- * @brief This file contains functions for putting entries on a queue and
- * removing entries from a queue.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * Inlines are compiled as function when this is defined.
- * N.B. Must be placed before #include of "IxQMgr.h"
- */
-#ifndef IXQMGR_H
-# define IXQMGRQACCESS_C
-#else
-# error
-#endif
-
-/*
- * System defined include files.
- */
-
-/*
- * User defined include files.
- */
-#include "IxQMgr.h"
-#include "IxQMgrAqmIf_p.h"
-#include "IxQMgrQAccess_p.h"
-#include "IxQMgrQCfg_p.h"
-#include "IxQMgrDefines_p.h"
-
-/*
- * Global variables and extern definitions
- */
-extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[];
-
-/*
- * Function definitions.
- */
-void
-ixQMgrQAccessInit (void)
-{
-}
-
-IX_STATUS
-ixQMgrQReadWithChecks (IxQMgrQId qId,
- UINT32 *entry)
-{
- IxQMgrQEntrySizeInWords entrySizeInWords;
- IxQMgrQInlinedReadWriteInfo *infoPtr;
-
- if (NULL == entry)
- {
- return IX_QMGR_PARAMETER_ERROR;
- }
-
- /* Check QId */
- if (!ixQMgrQIsConfigured(qId))
- {
- return IX_QMGR_Q_NOT_CONFIGURED;
- }
-
- /* Get the q entry size in words */
- entrySizeInWords = ixQMgrQEntrySizeInWordsGet (qId);
-
- ixQMgrAqmIfQPop (qId, entrySizeInWords, entry);
-
- /* reset the current read count if the counter wrapped around
- * (unsigned arithmetic)
- */
- infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
- if (infoPtr->qReadCount-- > infoPtr->qSizeInEntries)
- {
- infoPtr->qReadCount = 0;
- }
-
- /* Check if underflow occurred on the read */
- if (ixQMgrAqmIfUnderflowCheck (qId))
- {
- return IX_QMGR_Q_UNDERFLOW;
- }
-
- return IX_SUCCESS;
-}
-
-/* this function reads the remaining of the q entry
- * for queues configured with many words.
- * (the first word of the entry is already read
- * in the inlined function and the entry pointer already
- * incremented
- */
-IX_STATUS
-ixQMgrQReadMWordsMinus1 (IxQMgrQId qId,
- UINT32 *entry)
-{
- IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
- UINT32 entrySize = infoPtr->qEntrySizeInWords;
- volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr;
-
- while (--entrySize)
- {
- /* read the entry and accumulate the result */
- *(++entry) = IX_OSAL_READ_LONG(++qAccRegAddr);
- }
- /* underflow is available for lower queues only */
- if (qId < IX_QMGR_MIN_QUEUPP_QID)
- {
- /* get the queue status */
- UINT32 status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr);
-
- /* check the underflow status */
- if (status & infoPtr->qUflowStatBitMask)
- {
- /* the queue is empty
- * clear the underflow status bit if it was set
- */
- IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr,
- status & ~infoPtr->qUflowStatBitMask);
- return IX_QMGR_Q_UNDERFLOW;
- }
- }
- return IX_SUCCESS;
-}
-
-IX_STATUS
-ixQMgrQWriteWithChecks (IxQMgrQId qId,
- UINT32 *entry)
-{
- IxQMgrQEntrySizeInWords entrySizeInWords;
- IxQMgrQInlinedReadWriteInfo *infoPtr;
-
- if (NULL == entry)
- {
- return IX_QMGR_PARAMETER_ERROR;
- }
-
- /* Check QId */
- if (!ixQMgrQIsConfigured(qId))
- {
- return IX_QMGR_Q_NOT_CONFIGURED;
- }
-
- /* Get the q entry size in words */
- entrySizeInWords = ixQMgrQEntrySizeInWordsGet (qId);
-
- ixQMgrAqmIfQPush (qId, entrySizeInWords, entry);
-
- /* reset the current read count if the counter wrapped around
- * (unsigned arithmetic)
- */
- infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
- if (infoPtr->qWriteCount++ >= infoPtr->qSizeInEntries)
- {
- infoPtr->qWriteCount = infoPtr->qSizeInEntries;
- }
-
- /* Check if overflow occurred on the write*/
- if (ixQMgrAqmIfOverflowCheck (qId))
- {
- return IX_QMGR_Q_OVERFLOW;
- }
-
- return IX_SUCCESS;
-}
-
-IX_STATUS
-ixQMgrQPeek (IxQMgrQId qId,
- unsigned int entryIndex,
- UINT32 *entry)
-{
- unsigned int numEntries;
-
-#ifndef NDEBUG
- if ((NULL == entry) || (entryIndex >= IX_QMGR_Q_SIZE_INVALID))
- {
- return IX_QMGR_PARAMETER_ERROR;
- }
-
- if (!ixQMgrQIsConfigured(qId))
- {
- return IX_QMGR_Q_NOT_CONFIGURED;
- }
-#endif
-
- if (IX_SUCCESS != ixQMgrQNumEntriesGet (qId, &numEntries))
- {
- return IX_FAIL;
- }
-
- if (entryIndex >= numEntries) /* entryIndex starts at 0 */
- {
- return IX_QMGR_ENTRY_INDEX_OUT_OF_BOUNDS;
- }
-
- return ixQMgrAqmIfQPeek (qId, entryIndex, entry);
-}
-
-IX_STATUS
-ixQMgrQPoke (IxQMgrQId qId,
- unsigned entryIndex,
- UINT32 *entry)
-{
- unsigned int numEntries;
-
-#ifndef NDEBUG
- if ((NULL == entry) || (entryIndex > 128))
- {
- return IX_QMGR_PARAMETER_ERROR;
- }
-
- if (!ixQMgrQIsConfigured(qId))
- {
- return IX_QMGR_Q_NOT_CONFIGURED;
- }
-#endif
-
- if (IX_SUCCESS != ixQMgrQNumEntriesGet (qId, &numEntries))
- {
- return IX_FAIL;
- }
-
- if (numEntries < (entryIndex + 1)) /* entryIndex starts at 0 */
- {
- return IX_QMGR_ENTRY_INDEX_OUT_OF_BOUNDS;
- }
-
- return ixQMgrAqmIfQPoke (qId, entryIndex, entry);
-}
-
-IX_STATUS
-ixQMgrQStatusGetWithChecks (IxQMgrQId qId,
- IxQMgrQStatus *qStatus)
-{
- if (NULL == qStatus)
- {
- return IX_QMGR_PARAMETER_ERROR;
- }
-
- if (!ixQMgrQIsConfigured (qId))
- {
- return IX_QMGR_Q_NOT_CONFIGURED;
- }
-
- ixQMgrAqmIfQueStatRead (qId, qStatus);
-
- return IX_SUCCESS;
-}
-
-IX_STATUS
-ixQMgrQNumEntriesGet (IxQMgrQId qId,
- unsigned *numEntriesPtr)
-{
- UINT32 qPtrs;
- UINT32 qStatus;
- unsigned numEntries;
- IxQMgrQInlinedReadWriteInfo *infoPtr;
-
-
-#ifndef NDEBUG
- if (NULL == numEntriesPtr)
- {
- return IX_QMGR_PARAMETER_ERROR;
- }
-
- /* Check QId */
- if (!ixQMgrQIsConfigured(qId))
- {
- return IX_QMGR_Q_NOT_CONFIGURED;
- }
-#endif
-
- /* get fast access data */
- infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
-
- /* get snapshot */
- qPtrs = IX_OSAL_READ_LONG(infoPtr->qConfigRegAddr);
-
- /* Mod subtraction of pointers to get number of words in Q. */
- numEntries = (qPtrs - (qPtrs >> 7)) & 0x7f;
-
- if (numEntries == 0)
- {
- /*
- * Could mean either full or empty queue
- * so look at status
- */
- ixQMgrAqmIfQueStatRead (qId, &qStatus);
-
- if (qId < IX_QMGR_MIN_QUEUPP_QID)
- {
- if (qStatus & IX_QMGR_Q_STATUS_E_BIT_MASK)
- {
- /* Empty */
- *numEntriesPtr = 0;
- }
- else if (qStatus & IX_QMGR_Q_STATUS_F_BIT_MASK)
- {
- /* Full */
- *numEntriesPtr = infoPtr->qSizeInEntries;
- }
- else
- {
- /*
- * Queue status and read/write pointers are volatile.
- * The queue state has changed since we took the
- * snapshot of the read and write pointers.
- * Client can retry if they wish
- */
- *numEntriesPtr = 0;
- return IX_QMGR_WARNING;
- }
- }
- else /* It is an upper queue which does not have an empty status bit maintained */
- {
- if (qStatus & IX_QMGR_Q_STATUS_F_BIT_MASK)
- {
- /* The queue is Full at the time of snapshot. */
- *numEntriesPtr = infoPtr->qSizeInEntries;
- }
- else
- {
- /* The queue is either empty, either moving,
- * Client can retry if they wish
- */
- *numEntriesPtr = 0;
- return IX_QMGR_WARNING;
- }
- }
- }
- else
- {
- *numEntriesPtr = (numEntries / infoPtr->qEntrySizeInWords) & (infoPtr->qSizeInEntries - 1);
- }
-
- return IX_SUCCESS;
-}
-
-#if defined(__wince) && defined(NO_INLINE_APIS)
-
-PUBLIC IX_STATUS
-ixQMgrQRead (IxQMgrQId qId,
- UINT32 *entryPtr)
-{
- extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[];
- IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
- UINT32 entry, entrySize;
-
- /* get a new entry */
- entrySize = infoPtr->qEntrySizeInWords;
- entry = IX_OSAL_READ_LONG(infoPtr->qAccRegAddr);
-
- if (entrySize != IX_QMGR_Q_ENTRY_SIZE1)
- {
- *entryPtr = entry;
- /* process the remaining part of the entry */
- return ixQMgrQReadMWordsMinus1(qId, entryPtr);
- }
-
- /* underflow is available for lower queues only */
- if (qId < IX_QMGR_MIN_QUEUPP_QID)
- {
- /* the counter of queue entries is decremented. In happy
- * day scenario there are many entries in the queue
- * and the counter does not reach zero.
- */
- if (infoPtr->qReadCount-- == 0)
- {
- /* There is maybe no entry in the queue
- * qReadCount is now negative, but will be corrected before
- * the function returns.
- */
- UINT32 qPtrs; /* queue internal pointers */
-
- /* when a queue is empty, the hw guarantees to return
- * a null value. If the value is not null, the queue is
- * not empty.
- */
- if (entry == 0)
- {
- /* get the queue status */
- UINT32 status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr);
-
- /* check the underflow status */
- if (status & infoPtr->qUflowStatBitMask)
- {
- /* the queue is empty
- * clear the underflow status bit if it was set
- */
- IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr,
- status & ~infoPtr->qUflowStatBitMask);
- *entryPtr = 0;
- infoPtr->qReadCount = 0;
- return IX_QMGR_Q_UNDERFLOW;
- }
- }
- /* store the result */
- *entryPtr = entry;
-
- /* No underflow occured : someone is filling the queue
- * or the queue contains null entries.
- * The current counter needs to be
- * updated from the current number of entries in the queue
- */
-
- /* get snapshot of queue pointers */
- qPtrs = IX_OSAL_READ_LONG(infoPtr->qConfigRegAddr);
-
- /* Mod subtraction of pointers to get number of words in Q. */
- qPtrs = (qPtrs - (qPtrs >> 7)) & 0x7f;
-
- if (qPtrs == 0)
- {
- /* no entry in the queue */
- infoPtr->qReadCount = 0;
- }
- else
- {
- /* convert the number of words inside the queue
- * to a number of entries
- */
- infoPtr->qReadCount = qPtrs & (infoPtr->qSizeInEntries - 1);
- }
- return IX_SUCCESS;
- }
- }
- *entryPtr = entry;
- return IX_SUCCESS;
-}
-
-PUBLIC IX_STATUS
-ixQMgrQBurstRead (IxQMgrQId qId,
- UINT32 numEntries,
- UINT32 *entries)
-{
- extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[];
- IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
- UINT32 nullCheckEntry;
-
- if (infoPtr->qEntrySizeInWords == IX_QMGR_Q_ENTRY_SIZE1)
- {
- volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr;
-
- /* the code is optimized to take care of data dependencies:
- * Durig a read, there are a few cycles needed to get the
- * read complete. During these cycles, it is poossible to
- * do some CPU, e.g. increment pointers and decrement
- * counters.
- */
-
- /* fetch a queue entry */
- nullCheckEntry = IX_OSAL_READ_LONG(infoPtr->qAccRegAddr);
-
- /* iterate the specified number of queue entries */
- while (--numEntries)
- {
- /* check the result of the previous read */
- if (nullCheckEntry == 0)
- {
- /* if we read a NULL entry, stop. We have underflowed */
- break;
- }
- else
- {
- /* write the entry */
- *entries = nullCheckEntry;
- /* fetch next entry */
- nullCheckEntry = IX_OSAL_READ_LONG(qAccRegAddr);
- /* increment the write address */
- entries++;
- }
- }
- /* write the pre-fetched entry */
- *entries = nullCheckEntry;
- }
- else
- {
- IxQMgrQEntrySizeInWords entrySizeInWords = infoPtr->qEntrySizeInWords;
- /* read the specified number of queue entries */
- nullCheckEntry = 0;
- while (numEntries--)
- {
- int i;
-
- for (i = 0; i < entrySizeInWords; i++)
- {
- *entries = IX_OSAL_READ_LONG(infoPtr->qAccRegAddr + i);
- nullCheckEntry |= *entries++;
- }
-
- /* if we read a NULL entry, stop. We have underflowed */
- if (nullCheckEntry == 0)
- {
- break;
- }
- nullCheckEntry = 0;
- }
- }
-
- /* reset the current read count : next access to the read function
- * will force a underflow status check
- */
- infoPtr->qWriteCount = 0;
-
- /* Check if underflow occurred on the read */
- if (nullCheckEntry == 0 && qId < IX_QMGR_MIN_QUEUPP_QID)
- {
- /* get the queue status */
- UINT32 status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr);
-
- if (status & infoPtr->qUflowStatBitMask)
- {
- /* clear the underflow status bit if it was set */
- IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr,
- status & ~infoPtr->qUflowStatBitMask);
- return IX_QMGR_Q_UNDERFLOW;
- }
- }
-
- return IX_SUCCESS;
-}
-
-PUBLIC IX_STATUS
-ixQMgrQWrite (IxQMgrQId qId,
- UINT32 *entry)
-{
- extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[];
- IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
- UINT32 entrySize;
-
- /* write the entry */
- IX_OSAL_WRITE_LONG(infoPtr->qAccRegAddr, *entry);
- entrySize = infoPtr->qEntrySizeInWords;
-
- if (entrySize != IX_QMGR_Q_ENTRY_SIZE1)
- {
- /* process the remaining part of the entry */
- volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr;
- while (--entrySize)
- {
- ++entry;
- IX_OSAL_WRITE_LONG(++qAccRegAddr, *entry);
- }
- entrySize = infoPtr->qEntrySizeInWords;
- }
-
- /* overflow is available for lower queues only */
- if (qId < IX_QMGR_MIN_QUEUPP_QID)
- {
- UINT32 qSize = infoPtr->qSizeInEntries;
- /* increment the current number of entries in the queue
- * and check for overflow
- */
- if (infoPtr->qWriteCount++ == qSize)
- {
- /* the queue may have overflow */
- UINT32 qPtrs; /* queue internal pointers */
-
- /* get the queue status */
- UINT32 status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr);
-
- /* read the status twice because the status may
- * not be immediately ready after the write operation
- */
- if ((status & infoPtr->qOflowStatBitMask) ||
- ((status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr))
- & infoPtr->qOflowStatBitMask))
- {
- /* the queue is full, clear the overflow status
- * bit if it was set
- */
- IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr,
- status & ~infoPtr->qOflowStatBitMask);
- infoPtr->qWriteCount = infoPtr->qSizeInEntries;
- return IX_QMGR_Q_OVERFLOW;
- }
- /* No overflow occured : someone is draining the queue
- * and the current counter needs to be
- * updated from the current number of entries in the queue
- */
-
- /* get q pointer snapshot */
- qPtrs = IX_OSAL_READ_LONG(infoPtr->qConfigRegAddr);
-
- /* Mod subtraction of pointers to get number of words in Q. */
- qPtrs = (qPtrs - (qPtrs >> 7)) & 0x7f;
-
- if (qPtrs == 0)
- {
- /* the queue may be full at the time of the
- * snapshot. Next access will check
- * the overflow status again.
- */
- infoPtr->qWriteCount = qSize;
- }
- else
- {
- /* convert the number of words to a number of entries */
- if (entrySize == IX_QMGR_Q_ENTRY_SIZE1)
- {
- infoPtr->qWriteCount = qPtrs & (qSize - 1);
- }
- else
- {
- infoPtr->qWriteCount = (qPtrs / entrySize) & (qSize - 1);
- }
- }
- }
- }
- return IX_SUCCESS;
-}
-
-PUBLIC IX_STATUS
-ixQMgrQBurstWrite (IxQMgrQId qId,
- unsigned numEntries,
- UINT32 *entries)
-{
- extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[];
- IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
- UINT32 status;
-
- /* update the current write count */
- infoPtr->qWriteCount += numEntries;
-
- if (infoPtr->qEntrySizeInWords == IX_QMGR_Q_ENTRY_SIZE1)
- {
- volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr;
- while (numEntries--)
- {
- IX_OSAL_WRITE_LONG(qAccRegAddr, *entries);
- entries++;
- }
- }
- else
- {
- IxQMgrQEntrySizeInWords entrySizeInWords = infoPtr->qEntrySizeInWords;
- int i;
-
- /* write each queue entry */
- while (numEntries--)
- {
- /* write the queueEntrySize number of words for each entry */
- for (i = 0; i < entrySizeInWords; i++)
- {
- IX_OSAL_WRITE_LONG((infoPtr->qAccRegAddr + i), *entries);
- entries++;
- }
- }
- }
-
- /* check if the write count overflows */
- if (infoPtr->qWriteCount > infoPtr->qSizeInEntries)
- {
- /* reset the current write count */
- infoPtr->qWriteCount = infoPtr->qSizeInEntries;
- }
-
- /* Check if overflow occurred on the write operation */
- if (qId < IX_QMGR_MIN_QUEUPP_QID)
- {
- /* get the queue status */
- status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr);
-
- /* read the status twice because the status may
- * not be ready at the time of the write
- */
- if ((status & infoPtr->qOflowStatBitMask) ||
- ((status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr))
- & infoPtr->qOflowStatBitMask))
- {
- /* clear the underflow status bit if it was set */
- IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr,
- status & ~infoPtr->qOflowStatBitMask);
- return IX_QMGR_Q_OVERFLOW;
- }
- }
-
- return IX_SUCCESS;
-}
-
-PUBLIC IX_STATUS
-ixQMgrQStatusGet (IxQMgrQId qId,
- IxQMgrQStatus *qStatus)
-{
- /* read the status of a queue in the range 0-31 */
- if (qId < IX_QMGR_MIN_QUEUPP_QID)
- {
- extern UINT32 ixQMgrAqmIfQueLowStatRegAddr[];
- extern UINT32 ixQMgrAqmIfQueLowStatBitsOffset[];
- extern UINT32 ixQMgrAqmIfQueLowStatBitsMask;
- extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[];
- IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
- volatile UINT32 *lowStatRegAddr = (UINT32*)ixQMgrAqmIfQueLowStatRegAddr[qId];
- volatile UINT32 *qUOStatRegAddr = infoPtr->qUOStatRegAddr;
-
- UINT32 lowStatBitsOffset = ixQMgrAqmIfQueLowStatBitsOffset[qId];
- UINT32 lowStatBitsMask = ixQMgrAqmIfQueLowStatBitsMask;
- UINT32 underflowBitMask = infoPtr->qUflowStatBitMask;
- UINT32 overflowBitMask = infoPtr->qOflowStatBitMask;
-
- /* read the status register for this queue */
- *qStatus = IX_OSAL_READ_LONG(lowStatRegAddr);
- /* mask out the status bits relevant only to this queue */
- *qStatus = (*qStatus >> lowStatBitsOffset) & lowStatBitsMask;
-
- /* Check if the queue has overflowed */
- if (IX_OSAL_READ_LONG(qUOStatRegAddr) & overflowBitMask)
- {
- /* clear the overflow status bit if it was set */
- IX_OSAL_WRITE_LONG(qUOStatRegAddr,
- (IX_OSAL_READ_LONG(qUOStatRegAddr) &
- ~overflowBitMask));
- *qStatus |= IX_QMGR_Q_STATUS_OF_BIT_MASK;
- }
-
- /* Check if the queue has underflowed */
- if (IX_OSAL_READ_LONG(qUOStatRegAddr) & underflowBitMask)
- {
- /* clear the underflow status bit if it was set */
- IX_OSAL_WRITE_LONG(qUOStatRegAddr,
- (IX_OSAL_READ_LONG(qUOStatRegAddr) &
- ~underflowBitMask));
- *qStatus |= IX_QMGR_Q_STATUS_UF_BIT_MASK;
- }
- }
- else /* read status of a queue in the range 32-63 */
- {
- extern UINT32 ixQMgrAqmIfQueUppStat0RegAddr;
- extern UINT32 ixQMgrAqmIfQueUppStat1RegAddr;
- extern UINT32 ixQMgrAqmIfQueUppStat0BitMask[];
- extern UINT32 ixQMgrAqmIfQueUppStat1BitMask[];
-
- volatile UINT32 *qNearEmptyStatRegAddr = (UINT32*)ixQMgrAqmIfQueUppStat0RegAddr;
- volatile UINT32 *qFullStatRegAddr = (UINT32*)ixQMgrAqmIfQueUppStat1RegAddr;
- int maskIndex = qId - IX_QMGR_MIN_QUEUPP_QID;
- UINT32 qNearEmptyStatBitMask = ixQMgrAqmIfQueUppStat0BitMask[maskIndex];
- UINT32 qFullStatBitMask = ixQMgrAqmIfQueUppStat1BitMask[maskIndex];
-
- /* Reset the status bits */
- *qStatus = 0;
-
- /* Check if the queue is nearly empty */
- if (IX_OSAL_READ_LONG(qNearEmptyStatRegAddr) & qNearEmptyStatBitMask)
- {
- *qStatus |= IX_QMGR_Q_STATUS_NE_BIT_MASK;
- }
-
- /* Check if the queue is full */
- if (IX_OSAL_READ_LONG(qFullStatRegAddr) & qFullStatBitMask)
- {
- *qStatus |= IX_QMGR_Q_STATUS_F_BIT_MASK;
- }
- }
- return IX_SUCCESS;
-}
-#endif /* def NO_INLINE_APIS */
+++ /dev/null
-/**
- * @file QMgrQCfg.c
- *
- * @author Intel Corporation
- * @date 30-Oct-2001
- *
- * @brief This modules provides an interface for setting up the static
- * configuration of AQM queues.This file contains the following
- * functions:
- *
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * System defined include files.
- */
-
-/*
- * User defined include files.
- */
-#include "IxOsal.h"
-#include "IxQMgr.h"
-#include "IxQMgrAqmIf_p.h"
-#include "IxQMgrQCfg_p.h"
-#include "IxQMgrDefines_p.h"
-
-/*
- * #defines and macros used in this file.
- */
-
-#define IX_QMGR_MIN_ENTRY_SIZE_IN_WORDS 16
-
-/* Total size of SRAM */
-#define IX_QMGR_AQM_SRAM_SIZE_IN_BYTES 0x4000
-
-/*
- * Check that qId is a valid queue identifier. This is provided to
- * make the code easier to read.
- */
-#define IX_QMGR_QID_IS_VALID(qId) \
-(((qId) >= (IX_QMGR_MIN_QID)) && ((qId) <= (IX_QMGR_MAX_QID)))
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/*
- * This struct describes an AQM queue.
- * N.b. bufferSizeInWords and qEntrySizeInWords are stored in the queue
- * as these are requested by Access in the data path. sizeInEntries is
- * not required by the data path so it can be calculated dynamically.
- *
- */
-typedef struct
-{
- char qName[IX_QMGR_MAX_QNAME_LEN+1]; /* Textual description of a queue*/
- IxQMgrQSizeInWords qSizeInWords; /* The number of words in the queue */
- IxQMgrQEntrySizeInWords qEntrySizeInWords; /* Number of words per queue entry*/
- BOOL isConfigured; /* This flag is true if the queue has
- * been configured
- */
-} IxQMgrCfgQ;
-
-/*
- * Variable declarations global to this file. Externs are followed by
- * statics.
- */
-
-extern UINT32 * ixQMgrAqmIfQueAccRegAddr[];
-
-/* Store data required to inline read and write access
- */
-IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[IX_QMGR_MAX_NUM_QUEUES];
-
-static IxQMgrCfgQ cfgQueueInfo[IX_QMGR_MAX_NUM_QUEUES];
-
-/* This pointer holds the starting address of AQM SRAM not used by
- * the AQM queues.
- */
-static UINT32 freeSramAddress=0;
-
-/* 4 words of zeroed memory for inline access */
-static UINT32 zeroedPlaceHolder[4] = { 0, 0, 0, 0 };
-
-static BOOL cfgInitialized = false;
-
-static IxOsalMutex ixQMgrQCfgMutex;
-
-/*
- * Statistics
- */
-static IxQMgrQCfgStats stats;
-
-/*
- * Function declarations
- */
-PRIVATE BOOL
-watermarkLevelIsOk (IxQMgrQId qId, IxQMgrWMLevel level);
-
-PRIVATE BOOL
-qSizeInWordsIsOk (IxQMgrQSizeInWords qSize);
-
-PRIVATE BOOL
-qEntrySizeInWordsIsOk (IxQMgrQEntrySizeInWords entrySize);
-
-/*
- * Function definitions.
- */
-void
-ixQMgrQCfgInit (void)
-{
- int loopIndex;
-
- for (loopIndex=0; loopIndex < IX_QMGR_MAX_NUM_QUEUES;loopIndex++)
- {
- /* info for code inlining */
- ixQMgrAqmIfQueAccRegAddr[loopIndex] = zeroedPlaceHolder;
-
- /* info for code inlining */
- ixQMgrQInlinedReadWriteInfo[loopIndex].qReadCount = 0;
- ixQMgrQInlinedReadWriteInfo[loopIndex].qWriteCount = 0;
- ixQMgrQInlinedReadWriteInfo[loopIndex].qAccRegAddr = zeroedPlaceHolder;
- ixQMgrQInlinedReadWriteInfo[loopIndex].qUOStatRegAddr = zeroedPlaceHolder;
- ixQMgrQInlinedReadWriteInfo[loopIndex].qUflowStatBitMask = 0;
- ixQMgrQInlinedReadWriteInfo[loopIndex].qOflowStatBitMask = 0;
- ixQMgrQInlinedReadWriteInfo[loopIndex].qEntrySizeInWords = 0;
- ixQMgrQInlinedReadWriteInfo[loopIndex].qSizeInEntries = 0;
- ixQMgrQInlinedReadWriteInfo[loopIndex].qConfigRegAddr = zeroedPlaceHolder;
- }
-
- /* Initialise the AqmIf component */
- ixQMgrAqmIfInit ();
-
- /* Reset all queues to have queue name = NULL, entry size = 0 and
- * isConfigured = false
- */
- for (loopIndex=0; loopIndex < IX_QMGR_MAX_NUM_QUEUES;loopIndex++)
- {
- strcpy (cfgQueueInfo[loopIndex].qName, "");
- cfgQueueInfo[loopIndex].qSizeInWords = 0;
- cfgQueueInfo[loopIndex].qEntrySizeInWords = 0;
- cfgQueueInfo[loopIndex].isConfigured = false;
-
- /* Statistics */
- stats.qStats[loopIndex].isConfigured = false;
- stats.qStats[loopIndex].qName = cfgQueueInfo[loopIndex].qName;
- }
-
- /* Statistics */
- stats.wmSetCnt = 0;
-
- ixQMgrAqmIfSramBaseAddressGet (&freeSramAddress);
-
- ixOsalMutexInit(&ixQMgrQCfgMutex);
-
- cfgInitialized = true;
-}
-
-void
-ixQMgrQCfgUninit (void)
-{
- cfgInitialized = false;
-
- /* Uninitialise the AqmIf component */
- ixQMgrAqmIfUninit ();
-}
-
-IX_STATUS
-ixQMgrQConfig (char *qName,
- IxQMgrQId qId,
- IxQMgrQSizeInWords qSizeInWords,
- IxQMgrQEntrySizeInWords qEntrySizeInWords)
-{
- UINT32 aqmLocalBaseAddress;
-
- if (!cfgInitialized)
- {
- return IX_FAIL;
- }
-
- if (!IX_QMGR_QID_IS_VALID(qId))
- {
- return IX_QMGR_INVALID_Q_ID;
- }
-
- else if (NULL == qName)
- {
- return IX_QMGR_PARAMETER_ERROR;
- }
-
- else if (strlen (qName) > IX_QMGR_MAX_QNAME_LEN)
- {
- return IX_QMGR_PARAMETER_ERROR;
- }
-
- else if (!qSizeInWordsIsOk (qSizeInWords))
- {
- return IX_QMGR_INVALID_QSIZE;
- }
-
- else if (!qEntrySizeInWordsIsOk (qEntrySizeInWords))
- {
- return IX_QMGR_INVALID_Q_ENTRY_SIZE;
- }
-
- else if (cfgQueueInfo[qId].isConfigured)
- {
- return IX_QMGR_Q_ALREADY_CONFIGURED;
- }
-
- ixOsalMutexLock(&ixQMgrQCfgMutex, IX_OSAL_WAIT_FOREVER);
-
- /* Write the config register */
- ixQMgrAqmIfQueCfgWrite (qId,
- qSizeInWords,
- qEntrySizeInWords,
- freeSramAddress);
-
-
- strcpy (cfgQueueInfo[qId].qName, qName);
- cfgQueueInfo[qId].qSizeInWords = qSizeInWords;
- cfgQueueInfo[qId].qEntrySizeInWords = qEntrySizeInWords;
-
- /* store pre-computed information in the same cache line
- * to facilitate inlining of QRead and QWrite functions
- * in IxQMgr.h
- */
- ixQMgrQInlinedReadWriteInfo[qId].qReadCount = 0;
- ixQMgrQInlinedReadWriteInfo[qId].qWriteCount = 0;
- ixQMgrQInlinedReadWriteInfo[qId].qEntrySizeInWords = qEntrySizeInWords;
- ixQMgrQInlinedReadWriteInfo[qId].qSizeInEntries =
- (UINT32)qSizeInWords / (UINT32)qEntrySizeInWords;
-
- /* Calculate the new freeSramAddress from the size of the queue
- * currently being configured.
- */
- freeSramAddress += (qSizeInWords * IX_QMGR_NUM_BYTES_PER_WORD);
-
- /* Get the virtual SRAM address */
- ixQMgrAqmIfBaseAddressGet (&aqmLocalBaseAddress);
-
- IX_OSAL_ASSERT((freeSramAddress - (aqmLocalBaseAddress + (IX_QMGR_QUEBUFFER_SPACE_OFFSET))) <=
- IX_QMGR_QUE_BUFFER_SPACE_SIZE);
-
- /* The queue is now configured */
- cfgQueueInfo[qId].isConfigured = true;
-
- ixOsalMutexUnlock(&ixQMgrQCfgMutex);
-
-#ifndef NDEBUG
- /* Update statistics */
- stats.qStats[qId].isConfigured = true;
- stats.qStats[qId].qName = cfgQueueInfo[qId].qName;
-#endif
- return IX_SUCCESS;
-}
-
-IxQMgrQSizeInWords
-ixQMgrQSizeInWordsGet (IxQMgrQId qId)
-{
- /* No parameter checking as this is used on the data path */
- return (cfgQueueInfo[qId].qSizeInWords);
-}
-
-IX_STATUS
-ixQMgrQSizeInEntriesGet (IxQMgrQId qId,
- unsigned *qSizeInEntries)
-{
- if (!ixQMgrQIsConfigured(qId))
- {
- return IX_QMGR_Q_NOT_CONFIGURED;
- }
-
- if(NULL == qSizeInEntries)
- {
- return IX_QMGR_PARAMETER_ERROR;
- }
-
- *qSizeInEntries = (UINT32)(cfgQueueInfo[qId].qSizeInWords) /
- (UINT32)cfgQueueInfo[qId].qEntrySizeInWords;
-
- return IX_SUCCESS;
-}
-
-IxQMgrQEntrySizeInWords
-ixQMgrQEntrySizeInWordsGet (IxQMgrQId qId)
-{
- /* No parameter checking as this is used on the data path */
- return (cfgQueueInfo[qId].qEntrySizeInWords);
-}
-
-IX_STATUS
-ixQMgrWatermarkSet (IxQMgrQId qId,
- IxQMgrWMLevel ne,
- IxQMgrWMLevel nf)
-{
- IxQMgrQStatus qStatusOnEntry;/* The queue status on entry/exit */
- IxQMgrQStatus qStatusOnExit; /* to this function */
-
- if (!ixQMgrQIsConfigured(qId))
- {
- return IX_QMGR_Q_NOT_CONFIGURED;
- }
-
- if (!watermarkLevelIsOk (qId, ne))
- {
- return IX_QMGR_INVALID_Q_WM;
- }
-
- if (!watermarkLevelIsOk (qId, nf))
- {
- return IX_QMGR_INVALID_Q_WM;
- }
-
- /* Get the current queue status */
- ixQMgrAqmIfQueStatRead (qId, &qStatusOnEntry);
-
-#ifndef NDEBUG
- /* Update statistics */
- stats.wmSetCnt++;
-#endif
-
- ixQMgrAqmIfWatermarkSet (qId,
- ne,
- nf);
-
- /* Get the current queue status */
- ixQMgrAqmIfQueStatRead (qId, &qStatusOnExit);
-
- /* If the status has changed return a warning */
- if (qStatusOnEntry != qStatusOnExit)
- {
- return IX_QMGR_WARNING;
- }
-
- return IX_SUCCESS;
-}
-
-IX_STATUS
-ixQMgrAvailableSramAddressGet (UINT32 *address,
- unsigned *sizeOfFreeRam)
-{
- UINT32 aqmLocalBaseAddress;
-
- if ((NULL == address)||(NULL == sizeOfFreeRam))
- {
- return IX_QMGR_PARAMETER_ERROR;
- }
- if (!cfgInitialized)
- {
- return IX_FAIL;
- }
-
- *address = freeSramAddress;
-
- /* Get the virtual SRAM address */
- ixQMgrAqmIfBaseAddressGet (&aqmLocalBaseAddress);
-
- /*
- * Calculate the size in bytes of free sram
- * i.e. current free SRAM virtual pointer from
- * (base + total size)
- */
- *sizeOfFreeRam =
- (aqmLocalBaseAddress +
- IX_QMGR_AQM_SRAM_SIZE_IN_BYTES) -
- freeSramAddress;
-
- if (0 == *sizeOfFreeRam)
- {
- return IX_QMGR_NO_AVAILABLE_SRAM;
- }
-
- return IX_SUCCESS;
-}
-
-BOOL
-ixQMgrQIsConfigured (IxQMgrQId qId)
-{
- if (!IX_QMGR_QID_IS_VALID(qId))
- {
- return false;
- }
-
- return cfgQueueInfo[qId].isConfigured;
-}
-
-IxQMgrQCfgStats*
-ixQMgrQCfgStatsGet (void)
-{
- return &stats;
-}
-
-IxQMgrQCfgStats*
-ixQMgrQCfgQStatsGet (IxQMgrQId qId)
-{
- unsigned int ne;
- unsigned int nf;
- UINT32 baseAddress;
- UINT32 readPtr;
- UINT32 writePtr;
-
- stats.qStats[qId].qSizeInWords = cfgQueueInfo[qId].qSizeInWords;
- stats.qStats[qId].qEntrySizeInWords = cfgQueueInfo[qId].qEntrySizeInWords;
-
- if (IX_SUCCESS != ixQMgrQNumEntriesGet (qId, &stats.qStats[qId].numEntries))
- {
- if (IX_QMGR_WARNING != ixQMgrQNumEntriesGet (qId, &stats.qStats[qId].numEntries))
- {
- IX_QMGR_LOG_WARNING1("Failed to get the number of entries in queue.... %d\n", qId);
- }
- }
-
- ixQMgrAqmIfQueCfgRead (qId,
- stats.qStats[qId].numEntries,
- &baseAddress,
- &ne,
- &nf,
- &readPtr,
- &writePtr);
-
- stats.qStats[qId].baseAddress = baseAddress;
- stats.qStats[qId].ne = ne;
- stats.qStats[qId].nf = nf;
- stats.qStats[qId].readPtr = readPtr;
- stats.qStats[qId].writePtr = writePtr;
-
- return &stats;
-}
-
-/*
- * Static function definitions
- */
-
-PRIVATE BOOL
-watermarkLevelIsOk (IxQMgrQId qId, IxQMgrWMLevel level)
-{
- unsigned qSizeInEntries;
-
- switch (level)
- {
- case IX_QMGR_Q_WM_LEVEL0:
- case IX_QMGR_Q_WM_LEVEL1:
- case IX_QMGR_Q_WM_LEVEL2:
- case IX_QMGR_Q_WM_LEVEL4:
- case IX_QMGR_Q_WM_LEVEL8:
- case IX_QMGR_Q_WM_LEVEL16:
- case IX_QMGR_Q_WM_LEVEL32:
- case IX_QMGR_Q_WM_LEVEL64:
- break;
- default:
- return false;
- }
-
- /* Check watermark is not bigger than the qSizeInEntries */
- ixQMgrQSizeInEntriesGet(qId, &qSizeInEntries);
-
- if ((unsigned)level > qSizeInEntries)
- {
- return false;
- }
-
- return true;
-}
-
-PRIVATE BOOL
-qSizeInWordsIsOk (IxQMgrQSizeInWords qSize)
-{
- BOOL status;
-
- switch (qSize)
- {
- case IX_QMGR_Q_SIZE16:
- case IX_QMGR_Q_SIZE32:
- case IX_QMGR_Q_SIZE64:
- case IX_QMGR_Q_SIZE128:
- status = true;
- break;
- default:
- status = false;
- break;
- }
-
- return status;
-}
-
-PRIVATE BOOL
-qEntrySizeInWordsIsOk (IxQMgrQEntrySizeInWords entrySize)
-{
- BOOL status;
-
- switch (entrySize)
- {
- case IX_QMGR_Q_ENTRY_SIZE1:
- case IX_QMGR_Q_ENTRY_SIZE2:
- case IX_QMGR_Q_ENTRY_SIZE4:
- status = true;
- break;
- default:
- status = false;
- break;
- }
-
- return status;
-}
+++ /dev/null
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-LOCAL_CFLAGS += -I$(TOPDIR)/drivers/net/npe/include -DCONFIG_IXP425_COMPONENT_ETHDB -D__linux
-CFLAGS += $(LOCAL_CFLAGS)
-CPPFLAGS += $(LOCAL_CFLAGS) # needed for depend
-
-obj-y := npe.o \
- miiphy.o \
- IxOsalBufferMgt.o \
- IxOsalIoMem.o \
- IxOsalOsCacheMMU.o \
- IxOsalOsMsgQ.o \
- IxOsalOsSemaphore.o \
- IxOsalOsServices.o \
- IxOsalOsThread.o \
- IxEthAcc.o \
- IxEthAccCommon.o \
- IxEthAccControlInterface.o \
- IxEthAccDataPlane.o \
- IxEthAccMac.o \
- IxEthAccMii.o \
- IxEthDBAPI.o \
- IxEthDBAPISupport.o \
- IxEthDBCore.o \
- IxEthDBEvents.o \
- IxEthDBFeatures.o \
- IxEthDBFirewall.o \
- IxEthDBHashtable.o \
- IxEthDBLearning.o \
- IxEthDBMem.o \
- IxEthDBNPEAdaptor.o \
- IxEthDBPortUpdate.o \
- IxEthDBReports.o \
- IxEthDBSearch.o \
- IxEthDBSpanningTree.o \
- IxEthDBUtil.o \
- IxEthDBVlan.o \
- IxEthDBWiFi.o \
- IxEthMii.o \
- IxQMgrAqmIf.o \
- IxQMgrDispatcher.o \
- IxQMgrInit.o \
- IxQMgrQAccess.o \
- IxQMgrQCfg.o \
- IxFeatureCtrl.o \
- IxNpeDl.o \
- IxNpeDlImageMgr.o \
- IxNpeDlNpeMgr.o \
- IxNpeDlNpeMgrUtils.o \
- IxNpeMh.o \
- IxNpeMhConfig.o \
- IxNpeMhReceive.o \
- IxNpeMhSend.o \
- IxNpeMhSolicitedCbMgr.o \
- IxNpeMhUnsolicitedCbMgr.o
+++ /dev/null
-/**
- * @file IxAssert.h
- *
- * @date 21-MAR-2002 (replaced by OSAL)
- *
- * @brief This file contains assert and ensure macros used by the IXP400 software
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxAssert IXP400 Assertion Macros (IxAssert) API
- *
- * @brief Assertion support
- *
- * @{
- */
-
-#ifndef IXASSERT_H
-
-#ifndef __doxygen_HIDE
-#define IXASSERT_H
-#endif /* __doxygen_HIDE */
-
-#include "IxOsalBackward.h"
-
-#endif /* IXASSERT_H */
-
-/**
- * @} addtogroup IxAssert
- */
-
-
-
+++ /dev/null
-/**
- * @file IxAtmSch.h
- *
- * @date 23-NOV-2001
- *
- * @brief Header file for the IXP400 ATM Traffic Shaper
- *
- * This component demonstrates an ATM Traffic Shaper implementation. It
- * will perform shaping on upto 12 ports and total of 44 VCs accross all ports,
- * 32 are intended for AAL0/5 and 12 for OAM (1 per port).
- * The supported traffic types are;1 rt-VBR VC where PCR = SCR.
- * (Effectively CBR) and Up-to 44 VBR VCs.
- *
- * This component models the ATM ports and VCs and is capable of producing
- * a schedule of ATM cells per port which can be supplied to IxAtmdAcc
- * for execution on the data path.
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- *
- * @sa IxAtmm.h
- *
- */
-
-/**
- * @defgroup IxAtmSch IXP400 ATM Transmit Scheduler (IxAtmSch) API
- *
- * @brief IXP400 ATM scheduler component Public API
- *
- * @{
- */
-
-#ifndef IXATMSCH_H
-#define IXATMSCH_H
-
-#include "IxOsalTypes.h"
-#include "IxAtmTypes.h"
-
-/*
- * #defines and macros used in this file.
- */
-
-/* Return codes */
-
-/**
- * @ingroup IxAtmSch
- *
- * @def IX_ATMSCH_RET_NOT_ADMITTED
- * @brief Indicates that CAC function has rejected VC registration due
- * to insufficient line capacity.
-*/
-#define IX_ATMSCH_RET_NOT_ADMITTED 2
-
-/**
- * @ingroup IxAtmSch
- *
- * @def IX_ATMSCH_RET_QUEUE_FULL
- * @brief Indicates that the VC queue is full, no more demand can be
- * queued at this time.
- */
-#define IX_ATMSCH_RET_QUEUE_FULL 3
-
-/**
- * @ingroup IxAtmSch
- *
- * @def IX_ATMSCH_RET_QUEUE_EMPTY
- * @brief Indicates that all VC queues on this port are empty and
- * therefore there are no cells to be scheduled at this time.
- */
-#define IX_ATMSCH_RET_QUEUE_EMPTY 4
-
-/*
- * Function declarations
- */
-
-/**
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchInit(void)
- *
- * @brief This function is used to initialize the ixAtmSch component. It
- * should be called before any other IxAtmSch API function.
- *
- * @param None
- *
- * @return
- * - <b>IX_SUCCESS :</b> indicates that
- * -# The ATM scheduler component has been successfully initialized.
- * -# The scheduler is ready to accept Port modelling requests.
- * - <b>IX_FAIL :</b> Some internal error has prevented the scheduler component
- * from initialising.
- */
-PUBLIC IX_STATUS
-ixAtmSchInit(void);
-
-/**
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchPortModelInitialize( IxAtmLogicalPort port,
- unsigned int portRate,
- unsigned int minCellsToSchedule)
- *
- * @brief This function shall be called first to initialize an ATM port before
- * any other ixAtmSch API calls may be made for that port.
- *
- * @param port @ref IxAtmLogicalPort [in] - The specific port to initialize. Valid
- * values range from 0 to IX_UTOPIA_MAX_PORTS - 1, representing a
- * maximum of IX_UTOPIA_MAX_PORTS possible ports.
- *
- * @param portRate unsigned int [in] - Value indicating the upstream capacity
- * of the indicated port. The value should be supplied in
- * units of ATM (53 bytes) cells per second.
- * A port rate of 800Kbits/s is the equivalent
- * of 1886 cells per second
- *
- * @param minCellsToSchedule unsigned int [in] - This parameter specifies the minimum
- * number of cells which the scheduler will put in a schedule
- * table for this port. This value sets the worst case CDVT for VCs
- * on this port i.e. CDVT = 1*minCellsToSchedule/portRate.
- * @return
- * - <b>IX_SUCCESS :</b> indicates that
- * -# The ATM scheduler has been successfully initialized.
- * -# The requested port model has been established.
- * -# The scheduler is ready to accept VC modelling requests
- * on the ATM port.
- * - <b>IX_FAIL :</b> indicates the requested port could not be
- * initialized. */
-PUBLIC IX_STATUS
-ixAtmSchPortModelInitialize( IxAtmLogicalPort port,
- unsigned int portRate,
- unsigned int minCellsToSchedule);
-
-/**
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchPortRateModify( IxAtmLogicalPort port,
- unsigned int portRate)
- *
- * @brief This function is called to modify the portRate on a
- * previously initialized port, typically in the event that
- * the line condition of the port changes.
- *
- * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port which is to be
- * modified.
- *
- * @param portRate unsigned int [in] - Value indicating the new upstream
- * capacity for this port in cells/second.
- * A port rate of 800Kbits/s is the equivalent
- * of 1886 cells per second
- *
- * @return
- * - <b>IX_SUCCESS :</b> The port rate has been successfully modified.<br>
- * - <b>IX_FAIL :</b> The port rate could not be modified, either
- * because the input data was invalid, or the new port rate is
- * insufficient to support established ATM VC contracts on this
- * port.
- *
- * @warning The IxAtmSch component will validate the supplied port
- * rate is sufficient to support all established VC
- * contracts on the port. If the new port rate is
- * insufficient to support all established contracts then
- * the request to modify the port rate will be rejected.
- * In this event, the user is expected to remove
- * established contracts using the ixAtmSchVcModelRemove
- * interface and then retry this interface.
- *
- * @sa ixAtmSchVcModelRemove() */
-PUBLIC IX_STATUS
-ixAtmSchPortRateModify( IxAtmLogicalPort port,
- unsigned int portRate);
-
-
-/**
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchVcModelSetup( IxAtmLogicalPort port,
- IxAtmTrafficDescriptor *trafficDesc,
- IxAtmSchedulerVcId *vcId)
- *
- * @brief A client calls this interface to set up an upstream
- * (transmitting) virtual connection model (VC) on the
- * specified ATM port. This function also provides the
- * virtual * connection admission control (CAC) service to the
- * client.
- *
- * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the upstream
- * VC is to be established.
- *
- * @param *trafficDesc @ref IxAtmTrafficDescriptor [in] - Pointer to a structure
- * describing the requested traffic contract of the VC to be
- * established. This structure contains the typical ATM
- * traffic descriptor values (e.g. PCR, SCR, MBS, CDVT, etc.)
- * defined by the ATM standard.
- *
- * @param *vcId @ref IxAtmSchedulerVcId [out] - This value will be filled with the
- * port-unique identifier for this virtual connection. A
- * valid identification is a non-negative number.
- *
- * @return
- * - <b>IX_SUCCESS :</b> The VC has been successfully established on
- * this port. The client may begin to submit demand on this VC.
- * - <b>IX_ATMSCH_RET_NOT_ADMITTED :</b> The VC cannot be established
- * on this port because there is insufficient upstream capacity
- * available to support the requested traffic contract descriptor
- * - <b>IX_FAIL :</b>Input data are invalid. VC has not been
- * established.
- */
-PUBLIC IX_STATUS
-ixAtmSchVcModelSetup( IxAtmLogicalPort port,
- IxAtmTrafficDescriptor *trafficDesc,
- IxAtmSchedulerVcId *vcId);
-
-/**
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchVcConnIdSet( IxAtmLogicalPort port,
- IxAtmSchedulerVcId vcId,
- IxAtmConnId vcUserConnId)
- *
- * @brief A client calls this interface to set the vcUserConnId for a VC on
- * the specified ATM port. This vcUserConnId will default to
- * IX_ATM_IDLE_CELLS_CONNID if this function is not called for a VC.
- * Hence if the client does not call this function for a VC then only idle
- * cells will be scheduled for this VC.
- *
- * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the upstream
- * VC is has been established.
- *
- * @param vcId @ref IxAtmSchedulerVcId [in] - This is the unique identifier for this virtual
- * connection. A valid identification is a non-negative number and is
- * all ports.
- *
- * @param vcUserConnId @ref IxAtmConnId [in] - The connId is used to refer to a VC in schedule
- * table entries. It is treated as the Id by which the scheduler client
- * knows the VC. It is used in any communicatations from the Scheduler
- * to the scheduler user e.g. schedule table entries.
- *
- * @return
- * - <b>IX_SUCCESS :</b> The id has successfully been set.
- * - <b>IX_FAIL :</b>Input data are invalid. connId id is not established.
- */
-PUBLIC IX_STATUS
-ixAtmSchVcConnIdSet( IxAtmLogicalPort port,
- IxAtmSchedulerVcId vcId,
- IxAtmConnId vcUserConnId);
-
-/**
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchVcModelRemove( IxAtmLogicalPort port,
- IxAtmSchedulerVcId vcId)
- *
- * @brief Interface called by the client to remove a previously
- * established VC on a particular port.
- *
- * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the VC to be
- * removed is established.
- *
- * @param vcId @ref IxAtmSchedulerVcId [in] - Identifies the VC to be removed. This is the
- * value returned by the @ref ixAtmSchVcModelSetup call which
- * established the relevant VC.
- *
- * @return
- * - <b>IX_SUCCESS :</b> The VC has been successfully removed from
- * this port. It is no longer modelled on this port.
- * - <b>IX_FAIL :</b>Input data are invalid. The VC is still being modeled
- * by the traffic shaper.
- *
- * @sa ixAtmSchVcModelSetup()
- */
-PUBLIC IX_STATUS
-ixAtmSchVcModelRemove( IxAtmLogicalPort port,
- IxAtmSchedulerVcId vcId);
-
-/**
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchVcQueueUpdate( IxAtmLogicalPort port,
- IxAtmSchedulerVcId vcId,
- unsigned int numberOfCells)
- *
- * @brief The client calls this function to notify IxAtmSch that the
- * user of a VC has submitted cells for transmission.
- *
- * This information is stored, aggregated from a number of calls to
- * ixAtmSchVcQueueUpdate and eventually used in the call to
- * ixAtmSchTableUpdate.
- *
- * Normally IxAtmSch will update the VC queue by adding the number of
- * cells to the current queue length. However, if IxAtmSch
- * determines that the user has over-submitted for the VC and
- * exceeded its transmission quota the queue request can be rejected.
- * The user should resubmit the request later when the queue has been
- * depleted.
- *
- * This implementation of ixAtmSchVcQueueUpdate uses no operating
- * system or external facilities, either directly or indirectly.
- * This allows clients to call this function form within an interrupt handler.
- *
- * This interface is structurally compatible with the
- * IxAtmdAccSchQueueUpdate callback type definition required for
- * IXP400 ATM scheduler interoperability.
- *
- * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the VC to be
- * updated is established.
- *
- * @param vcId @ref IxAtmSchedulerVcId [in] - Identifies the VC to be updated. This is the
- * value returned by the @ref ixAtmSchVcModelSetup call which
- * established the relevant VC.
- *
- * @param numberOfCells unsigned int [in] - Indicates how many ATM cells should
- * be added to the queue for this VC.
- *
- * @return
- * - <b>IX_SUCCESS :</b> The VC queue has been successfully updated.
- * - <b>IX_ATMSCH_RET_QUEUE_FULL :</b> The VC queue has reached a
- * preset limit. This indicates the client has over-submitted
- * and exceeded its transmission quota. The request is
- * rejected. The VC queue is not updated. The VC user is
- * advised to resubmit the request later.
- * - <b>IX_FAIL :</b> The input are invalid. No VC queue is updated.
- *
- * @warning IxAtmSch assumes that the calling software ensures that
- * calls to ixAtmSchVcQueueUpdate, ixAtmSchVcQueueClear and
- * ixAtmSchTableUpdate are both self and mutually exclusive
- * for the same port.
- *
- * @sa ixAtmSchVcQueueUpdate(), ixAtmSchVcQueueClear(), ixAtmSchTableUpdate(). */
-PUBLIC IX_STATUS
-ixAtmSchVcQueueUpdate( IxAtmLogicalPort port,
- IxAtmSchedulerVcId vcId,
- unsigned int numberOfCells);
-
-/**
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchVcQueueClear( IxAtmLogicalPort port,
- IxAtmSchedulerVcId vcId)
- *
- * @brief The client calls this function to remove all currently
- * queued cells from a registered VC. The pending cell count
- * for the specified VC is reset to zero.
- *
- * This interface is structurally compatible with the
- * IxAtmdAccSchQueueClear callback type definition required for
- * IXP400 ATM scheduler interoperability.
- *
- * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the VC to be
- * cleared is established.
- *
- * @param vcId @ref IxAtmSchedulerVcId [in] - Identifies the VC to be cleared. This is the
- * value returned by the @ref ixAtmSchVcModelSetup call which
- * established the relevant VC.
- *
- * @return
- * - <b>IX_SUCCESS :</b> The VC queue has been successfully cleared.
- * - <b>IX_FAIL :</b> The input are invalid. No VC queue is modified.
- *
- * @warning IxAtmSch assumes that the calling software ensures that
- * calls to ixAtmSchVcQueueUpdate, ixAtmSchVcQueueClear and
- * ixAtmSchTableUpdate are both self and mutually exclusive
- * for the same port.
- *
- * @sa ixAtmSchVcQueueUpdate(), ixAtmSchVcQueueClear(), ixAtmSchTableUpdate(). */
-PUBLIC IX_STATUS
-ixAtmSchVcQueueClear( IxAtmLogicalPort port,
- IxAtmSchedulerVcId vcId);
-
-/**
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchTableUpdate( IxAtmLogicalPort port,
- unsigned int maxCells,
- IxAtmScheduleTable **rettable)
- *
- * @brief The client calls this function to request an update of the
- * schedule table for a particular ATM port.
- *
- * This is called when the client decides it needs a new sequence of
- * cells to send (probably because the transmit queue is near to
- * empty for this ATM port). The scheduler will use its stored
- * information on the cells submitted for transmit (i.e. data
- * supplied via @ref ixAtmSchVcQueueUpdate function) with the traffic
- * descriptor information of all established VCs on the ATM port to
- * decide the sequence of cells to be sent and fill the schedule
- * table for a period of time into the future.
- *
- * IxAtmSch will guarantee a minimum of minCellsToSchedule if there
- * is at least one cell ready to send. If there are no cells then
- * IX_ATMSCH_RET_QUEUE_EMPTY is returned.
- *
- * This implementation of ixAtmSchTableUpdate uses no operating
- * system or external facilities, either directly or indirectly.
- * This allows clients to call this function form within an FIQ
- * interrupt handler.
- *
- * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port for which requested
- * schedule table is to be generated.
- *
- * @param maxCells unsigned [in] - Specifies the maximum number of cells
- * that must be scheduled in the supplied table during any
- * call to the interface.
- *
- * @param **table @ref IxAtmScheduleTable [out] - A pointer to an area of
- * storage is returned which contains the generated
- * schedule table. The client should not modify the
- * contents of this table.
- *
- * @return
- * - <b>IX_SUCCESS :</b> The schedule table has been published.
- * Currently there is at least one VC queue that is nonempty.
- * - <b>IX_ATMSCH_RET_QUEUE_EMPTY :</b> Currently all VC queues on
- * this port are empty. The schedule table returned is set to
- * NULL. The client is not expected to invoke this function
- * again until more cells have been submitted on this port
- * through the @ref ixAtmSchVcQueueUpdate function.
- * - <b>IX_FAIL :</b> The input are invalid. No action is taken.
- *
- * @warning IxAtmSch assumes that the calling software ensures that
- * calls to ixAtmSchVcQueueUpdate, ixAtmSchVcQueueClear and
- * ixAtmSchTableUpdate are both self and mutually exclusive
- * for the same port.
- *
- * @warning Subsequent calls to this function for the same port will
- * overwrite the contents of previously supplied schedule
- * tables. The client must be completely finished with the
- * previously supplied schedule table before calling this
- * function again for the same port.
- *
- * @sa ixAtmSchVcQueueUpdate(), ixAtmSchVcQueueClear(), ixAtmSchTableUpdate(). */
-PUBLIC IX_STATUS
-ixAtmSchTableUpdate( IxAtmLogicalPort port,
- unsigned int maxCells,
- IxAtmScheduleTable **rettable);
-
-/**
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchShow(void)
- *
- * @brief Utility function which will print statistics on the current
- * and accumulated state of VCs and traffic in the ATM
- * scheduler component. Output is sent to the default output
- * device.
- *
- * @param none
- * @return none
- */
-PUBLIC void
-ixAtmSchShow(void);
-
-/**
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchStatsClear(void)
- *
- * @brief Utility function which will reset all counter statistics in
- * the ATM scheduler to zero.
- *
- * @param none
- * @return none
- */
-PUBLIC void
-ixAtmSchStatsClear(void);
-
-#endif
-/* IXATMSCH_H */
-
-/** @} */
+++ /dev/null
-/**
- * @file IxAtmTypes.h
- *
- * @date 24-MAR-2002
- *
- * @brief This file contains Atm types common to a number of Atm components.
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/* ------------------------------------------------------
- Doxygen group definitions
- ------------------------------------------------------ */
-/**
- * @defgroup IxAtmTypes IXP400 ATM Types (IxAtmTypes)
- *
- * @brief The common set of types used in many Atm components
- *
- * @{ */
-
-#ifndef IXATMTYPES_H
-#define IXATMTYPES_H
-
-#include "IxNpeA.h"
-
-/**
- * @enum IxAtmLogicalPort
- *
- * @brief Logical Port Definitions :
- *
- * Only 1 port is available in SPHY configuration
- * 12 ports are enabled in MPHY configuration
- *
- */
-typedef enum
-{
- IX_UTOPIA_PORT_0 = 0, /**< Port 0 */
-#ifdef IX_NPE_MPHYMULTIPORT
- IX_UTOPIA_PORT_1, /**< Port 1 */
- IX_UTOPIA_PORT_2, /**< Port 2 */
- IX_UTOPIA_PORT_3, /**< Port 3 */
- IX_UTOPIA_PORT_4, /**< Port 4 */
- IX_UTOPIA_PORT_5, /**< Port 5 */
- IX_UTOPIA_PORT_6, /**< Port 6 */
- IX_UTOPIA_PORT_7, /**< Port 7 */
- IX_UTOPIA_PORT_8, /**< Port 8 */
- IX_UTOPIA_PORT_9, /**< Port 9 */
- IX_UTOPIA_PORT_10, /**< Port 10 */
- IX_UTOPIA_PORT_11, /**< Port 11 */
-#endif /* IX_NPE_MPHY */
- IX_UTOPIA_MAX_PORTS /**< Not a port - just a definition for the
- * maximum possible ports
- */
-} IxAtmLogicalPort;
-
-/**
- * @def IX_ATM_CELL_PAYLOAD_SIZE
- * @brief Size of a ATM cell payload
- */
-#define IX_ATM_CELL_PAYLOAD_SIZE (48)
-
-/**
- * @def IX_ATM_CELL_SIZE
- * @brief Size of a ATM cell, including header
- */
-#define IX_ATM_CELL_SIZE (53)
-
-/**
- * @def IX_ATM_CELL_SIZE_NO_HEC
- * @brief Size of a ATM cell, excluding HEC byte
- */
-#define IX_ATM_CELL_SIZE_NO_HEC (IX_ATM_CELL_SIZE - 1)
-
-/**
- * @def IX_ATM_OAM_CELL_SIZE_NO_HEC
- * @brief Size of a OAM cell, excluding HEC byte
- */
-#define IX_ATM_OAM_CELL_SIZE_NO_HEC IX_ATM_CELL_SIZE_NO_HEC
-
-/**
- * @def IX_ATM_AAL0_48_CELL_PAYLOAD_SIZE
- * @brief Size of a AAL0 48 Cell payload
- */
-#define IX_ATM_AAL0_48_CELL_PAYLOAD_SIZE IX_ATM_CELL_PAYLOAD_SIZE
-
-/**
- * @def IX_ATM_AAL5_CELL_PAYLOAD_SIZE
- * @brief Size of a AAL5 Cell payload
- */
-#define IX_ATM_AAL5_CELL_PAYLOAD_SIZE IX_ATM_CELL_PAYLOAD_SIZE
-
-/**
- * @def IX_ATM_AAL0_52_CELL_SIZE_NO_HEC
- * @brief Size of a AAL0 52 Cell, excluding HEC byte
- */
-#define IX_ATM_AAL0_52_CELL_SIZE_NO_HEC IX_ATM_CELL_SIZE_NO_HEC
-
-
-/**
- * @def IX_ATM_MAX_VPI
- * @brief Maximum value of an ATM VPI
- */
-#define IX_ATM_MAX_VPI 255
-
-/**
- * @def IX_ATM_MAX_VCI
- * @brief Maximum value of an ATM VCI
- */
-#define IX_ATM_MAX_VCI 65535
-
- /**
- * @def IX_ATM_MAX_NUM_AAL_VCS
- * @brief Maximum number of active AAL5/AAL0 VCs in the system
- */
-#define IX_ATM_MAX_NUM_AAL_VCS 32
-
-/**
- * @def IX_ATM_MAX_NUM_VC
- * @brief Maximum number of active AAL5/AAL0 VCs in the system
- * The use of this macro is depreciated, it is retained for
- * backward compatiblity. For current software release
- * and beyond the define IX_ATM_MAX_NUM_AAL_VC should be used.
- */
-#define IX_ATM_MAX_NUM_VC IX_ATM_MAX_NUM_AAL_VCS
-
-
-
-/**
- * @def IX_ATM_MAX_NUM_OAM_TX_VCS
- * @brief Maximum number of active OAM Tx VCs in the system,
- * 1 OAM VC per port
- */
-#define IX_ATM_MAX_NUM_OAM_TX_VCS IX_UTOPIA_MAX_PORTS
-
-/**
- * @def IX_ATM_MAX_NUM_OAM_RX_VCS
- * @brief Maximum number of active OAM Rx VCs in the system,
- * 1 OAM VC shared accross all ports
- */
-#define IX_ATM_MAX_NUM_OAM_RX_VCS 1
-
-/**
- * @def IX_ATM_MAX_NUM_AAL_OAM_TX_VCS
- * @brief Maximum number of active AAL5/AAL0/OAM Tx VCs in the system
- */
-#define IX_ATM_MAX_NUM_AAL_OAM_TX_VCS (IX_ATM_MAX_NUM_AAL_VCS + IX_ATM_MAX_NUM_OAM_TX_VCS)
-
-/**
- * @def IX_ATM_MAX_NUM_AAL_OAM_RX_VCS
- * @brief Maximum number of active AAL5/AAL0/OAM Rx VCs in the system
- */
-#define IX_ATM_MAX_NUM_AAL_OAM_RX_VCS (IX_ATM_MAX_NUM_AAL_VCS + IX_ATM_MAX_NUM_OAM_RX_VCS)
-
-/**
- * @def IX_ATM_IDLE_CELLS_CONNID
- * @brief VC Id used to indicate idle cells in the returned schedule table.
- */
-#define IX_ATM_IDLE_CELLS_CONNID 0
-
-
-/**
- * @def IX_ATM_CELL_HEADER_VCI_GET
- * @brief get the VCI field from a cell header
- */
-#define IX_ATM_CELL_HEADER_VCI_GET(cellHeader) \
- (((cellHeader) >> 4) & IX_OAM_VCI_BITS_MASK);
-
-/**
- * @def IX_ATM_CELL_HEADER_VPI_GET
- * @brief get the VPI field from a cell header
- */
-#define IX_ATM_CELL_HEADER_VPI_GET(cellHeader) \
- (((cellHeader) >> 20) & IX_OAM_VPI_BITS_MASK);
-
-/**
- * @def IX_ATM_CELL_HEADER_PTI_GET
- * @brief get the PTI field from a cell header
- */
-#define IX_ATM_CELL_HEADER_PTI_GET(cellHeader) \
- ((cellHeader) >> 1) & IX_OAM_PTI_BITS_MASK;
-
-/**
- * @typedef IxAtmCellHeader
- *
- * @brief ATM Cell Header, does not contain 4 byte HEC, added by NPE-A
- */
-typedef unsigned int IxAtmCellHeader;
-
-
-/**
- * @enum IxAtmServiceCategory
- *
- * @brief Enumerated type representing available ATM service categories.
- * For more informatoin on these categories, see "Traffic Management
- * Specification" v4.1, published by the ATM Forum -
- * http://www.atmforum.com
- */
-typedef enum
-{
- IX_ATM_CBR, /**< Constant Bit Rate */
- IX_ATM_RTVBR, /**< Real Time Variable Bit Rate */
- IX_ATM_VBR, /**< Variable Bit Rate */
- IX_ATM_UBR, /**< Unspecified Bit Rate */
- IX_ATM_ABR /**< Available Bit Rate (not supported) */
-
-} IxAtmServiceCategory;
-
-/**
- *
- * @enum IxAtmRxQueueId
- *
- * @brief Rx Queue Type for RX traffic
- *
- * IxAtmRxQueueId defines the queues involved for receiving data.
- *
- * There are two queues to facilitate prioritisation handling
- * and processing the 2 queues with different algorithms and
- * constraints
- *
- * e.g. : one queue can carry voice (or time-critical traffic), the
- * other queue can carry non-voice traffic
- *
- */
-typedef enum
-{
- IX_ATM_RX_A = 0, /**< RX queue A */
- IX_ATM_RX_B, /**< RX queue B */
- IX_ATM_MAX_RX_STREAMS /**< Maximum number of RX streams */
-} IxAtmRxQueueId;
-
-/**
- * @brief Structure describing an ATM traffic contract for a Virtual
- * Connection (VC).
- *
- * Structure is used to specify the requested traffic contract for a
- * VC to the IxAtmSch component using the @ref ixAtmSchVcModelSetup
- * interface.
- *
- * These parameters are defined by the ATM forum working group
- * (http://www.atmforum.com).
- *
- * @note Typical values for a voice channel 64 Kbit/s
- * - atmService @a IX_ATM_RTVBR
- * - pcr 400 (include IP overhead, and AAL5 trailer)
- * - cdvt 5000000 (5 ms)
- * - scr = pcr
- *
- * @note Typical values for a data channel 800 Kbit/s
- * - atmService @a IX_ATM_UBR
- * - pcr 1962 (include IP overhead, and AAL5 trailer)
- * - cdvt 5000000 (5 ms)
- *
- */
-typedef struct
-{
- IxAtmServiceCategory atmService; /**< ATM service category */
- unsigned pcr; /**< Peak Cell Rate - cells per second */
- unsigned cdvt; /**< Cell Delay Variation Tolerance - in nanoseconds */
- unsigned scr; /**< Sustained Cell Rate - cells per second */
- unsigned mbs; /**< Max Burst Size - cells */
- unsigned mcr; /**< Minimum Cell Rate - cells per second */
- unsigned mfs; /**< Max Frame Size - cells */
-} IxAtmTrafficDescriptor;
-
-/**
- * @typedef IxAtmConnId
- *
- * @brief ATM VC data connection identifier.
- *
- * This is is generated by IxAtmdAcc when a successful connection is
- * made on a VC. The is the ID by which IxAtmdAcc knows an active
- * VC and should be used in IxAtmdAcc API calls to reference a
- * specific VC.
- */
-typedef unsigned int IxAtmConnId;
-
-/**
- * @typedef IxAtmSchedulerVcId
- *
- * @brief ATM VC scheduling connection identifier.
- *
- * This id is generated and used by ATM Tx controller, generally
- * the traffic shaper (e.g. IxAtmSch). The IxAtmdAcc component
- * will request one of these Ids whenever a data connection on
- * a Tx VC is requested. This ID will be used in callbacks to
- * the ATM Transmission Ctrl s/w (e.g. IxAtmm) to reference a
- * particular VC.
- */
-typedef int IxAtmSchedulerVcId;
-
-/**
- * @typedef IxAtmNpeRxVcId
- *
- * @brief ATM Rx VC identifier used by the ATM Npe.
- *
- * This Id is generated by IxAtmdAcc when a successful data connection
- * is made on a rx VC.
- */
-typedef unsigned int IxAtmNpeRxVcId;
-
-/**
- * @brief ATM Schedule Table entry
- *
- * This IxAtmScheduleTableEntry is used by an ATM scheduler to inform
- * IxAtmdAcc about the data to transmit (in term of cells per VC)
- *
- * This structure defines
- * @li the number of cells to be transmitted (numberOfCells)
- * @li the VC connection to be used for transmission (connId).
- *
- * @note - When the connection Id value is IX_ATM_IDLE_CELLS_CONNID, the
- * corresponding number of idle cells will be transmitted to the hardware.
- *
- */
-typedef struct
-{
- IxAtmConnId connId; /**< connection Id
- *
- * Identifier of VC from which cells are to be transmitted.
- * When this valus is IX_ATM_IDLE_CELLS_CONNID, this indicates
- * that the system should transmit the specified number
- * of idle cells. Unknown connIds result in the transmission
- * idle cells.
- */
- unsigned int numberOfCells; /**< number of cells to transmit
- *
- * The number of contiguous cells to schedule from this VC
- * at this point. The valid range is from 1 to
- * @a IX_ATM_SCHEDULETABLE_MAXCELLS_PER_ENTRY. This
- * number can swap over mbufs and pdus. OverSchduling results
- * in the transmission of idle cells.
- */
-} IxAtmScheduleTableEntry;
-
-/**
- * @brief This structure defines a schedule table which gives details
- * on which data (from which VCs) should be transmitted for a
- * forthcoming period of time for a particular port and the
- * order in which that data should be transmitted.
- *
- * The schedule table consists of a series of entries each of which
- * will schedule one or more cells from a particular registered VC.
- * The total number of cells scheduled and the total number of
- * entries in the table are also indicated.
- *
- */
-typedef struct
-{
- unsigned tableSize; /**< Number of entries
- *
- * Indicates the total number of
- * entries in the table.
- */
- unsigned totalCellSlots; /**< Number of cells
- *
- * Indicates the total number of ATM
- * cells which are scheduled by all the
- * entries in the table.
- */
- IxAtmScheduleTableEntry *table; /**< Pointer to schedule entries
- *
- * Pointer to an array
- * containing tableSize entries
- */
-} IxAtmScheduleTable;
-
-#endif /* IXATMTYPES_H */
-
-/**
- * @} defgroup IxAtmTypes
- */
-
-
+++ /dev/null
-/**
- * @file IxAtmdAcc.h
- *
- * @date 07-Nov-2001
- *
- * @brief IxAtmdAcc Public API
- *
- * This file contains the public API of IxAtmdAcc, related to the
- * data functions of the component
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/* ------------------------------------------------------
- Doxygen group definitions
- ------------------------------------------------------ */
-
-/**
- *
- * @defgroup IxAtmdAccAPI IXP400 ATM Driver Access (IxAtmdAcc) API
- *
- * @brief The public API for the IXP400 Atm Driver Data component
- *
- * IxAtmdAcc is the low level interface by which AAL0/AAL5 and
- * OAM data gets transmitted to,and received from the Utopia bus.
- *
- * For AAL0/AAL5 services transmit and receive connections may
- * be established independantly for unique combinations of
- * port,VPI,and VCI.
- *
- * Two AAL0 services supporting 48 or 52 byte cell data are provided.
- * Submitted AAL0 PDUs must be a multiple of the cell data size (48/52).
- * AAL0_52 is a raw cell service the client must format
- * the PDU with an ATM cell header (excluding HEC) at the start of
- * each cell, note that AtmdAcc does not validate the cell headers in
- * a submitted PDU.
- *
- * OAM cells cannot be received over the AAL0 service but instead
- * are received over a dedicated OAM service.
- *
- * For the OAM service an "OAM Tx channel" may be enabled for a port
- * by establishing a single dedicated OAM Tx connection on that port.
- * A single "OAM Rx channel" for all ports may be enabled by
- * establishing a dedicated OAM Rx connection.
- *
- * The OAM service allows buffers containing 52 byte OAM F4/F5 cells
- * to be transmitted and received over the dedicated OAM channels.
- * HEC is appended/removed, and CRC-10 performed by the NPE. The OAM
- * service offered by AtmdAcc is a raw cell transport service.
- * It is assumed that ITU I.610 procedures that make use of this
- * service are implemented above AtmdAcc.
- *
- * Note that the dedicated OAM connections are established on
- * reserved VPI,VCI, and (in the case of Rx) port values defined below.
- * These values are used purely to descriminate the dedicated OAM channels
- * and do not identify a particular OAM F4/F5 flow. F4/F5 flows may be
- * realised for particluar VPI/VCIs by manipulating the VPI,VCI
- * fields of the ATM cell headers of cells in the buffers passed
- * to AtmdAcc. Note that AtmdAcc does not validate the cell headers
- * in a submitted OAM PDU.
- *
- *
- *
- * This part is related to the User datapath processing
- *
- * @{
- */
-
-#ifndef IXATMDACC_H
-#define IXATMDACC_H
-
-#include "IxAtmTypes.h"
-
-/* ------------------------------------------------------
- AtmdAcc Data Types definition
- ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @def IX_ATMDACC_WARNING
- *
- * @brief Warning return code
- *
- * This constant is used to tell IxAtmDAcc user about a special case.
- *
- */
-#define IX_ATMDACC_WARNING 2
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @def IX_ATMDACC_BUSY
- *
- * @brief Busy return code
- *
- * This constant is used to tell IxAtmDAcc user that the request
- * is correct, but cannot be processed because the IxAtmAcc resources
- * are already used. The user has to retry its request later
- *
- */
-#define IX_ATMDACC_BUSY 3
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @def IX_ATMDACC_RESOURCES_STILL_ALLOCATED
- *
- * @brief Disconnect return code
- *
- * This constant is used to tell IxAtmDAcc user that the disconnect
- * functions are not complete because the resources used by the driver
- * are not yet released. The user has to retry the disconnect call
- * later.
- *
- */
-#define IX_ATMDACC_RESOURCES_STILL_ALLOCATED 4
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @def IX_ATMDACC_DEFAULT_REPLENISH_COUNT
- *
- * @brief Default resources usage for RxVcFree replenish mechanism
- *
- * This constant is used to tell IxAtmDAcc to allocate and use
- * the minimum of resources for rx free replenish.
- *
- * @sa ixAtmdAccRxVcConnect
- */
-#define IX_ATMDACC_DEFAULT_REPLENISH_COUNT 0
-
-
-/**
- * @ingroup IxAtmdAccAPI
- *
- * @def IX_ATMDACC_OAM_TX_VPI
- *
- * @brief The reserved value used for the dedicated OAM
- * Tx connection. This "well known" value is used by atmdAcc and
- * its clients to dsicriminate the OAM channel, and should be chosen so
- * that it does not coencide with the VPI value used in an AAL0/AAL5 connection.
- * Any attempt to connect a service type other than OAM on this VPI will fail.
- *
- *
- */
-#define IX_ATMDACC_OAM_TX_VPI 0
-
-/**
- * @ingroup IxAtmdAccAPI
- *
- * @def IX_ATMDACC_OAM_TX_VCI
- *
- * @brief The reserved value used for the dedicated OAM
- * Tx connection. This "well known" value is used by atmdAcc and
- * its clients to dsicriminate the OAM channel, and should be chosen so
- * that it does not coencide with the VCI value used in an AAL0/AAL5 connection.
- * Any attempt to connect a service type other than OAM on this VCI will fail.
- */
-#define IX_ATMDACC_OAM_TX_VCI 0
-
-
- /**
- * @ingroup IxAtmdAccAPI
- *
- * @def IX_ATMDACC_OAM_RX_PORT
- *
- * @brief The reserved dummy PORT used for all dedicated OAM
- * Rx connections. Note that this is not a real port but must
- * have a value that lies within the valid range of port values.
- */
-#define IX_ATMDACC_OAM_RX_PORT IX_UTOPIA_PORT_0
-
- /**
- * @ingroup IxAtmdAccAPI
- *
- * @def IX_ATMDACC_OAM_RX_VPI
- *
- * @brief The reserved value value used for the dedicated OAM
- * Rx connection. This value should be chosen so that it does not
- * coencide with the VPI value used in an AAL0/AAL5 connection.
- * Any attempt to connect a service type other than OAM on this VPI will fail.
- */
-#define IX_ATMDACC_OAM_RX_VPI 0
-
-/**
- * @ingroup IxAtmdAccAPI
- *
- * @def IX_ATMDACC_OAM_RX_VCI
- *
- * @brief The reserved value value used for the dedicated OAM
- * Rx connection. This value should be chosen so that it does not
- * coencide with the VCI value used in an AAL0/AAL5 connection.
- * Any attempt to connect a service type other than OAM on this VCI will fail.
- */
-#define IX_ATMDACC_OAM_RX_VCI 0
-
-
-/**
- * @enum IxAtmdAccPduStatus
- *
- * @ingroup IxAtmdAccAPI
- *
- * @brief IxAtmdAcc Pdu status :
- *
- * IxAtmdAccPduStatus is used during a RX operation to indicate
- * the status of the received PDU
- *
- */
-
-typedef enum
-{
- IX_ATMDACC_AAL0_VALID = 0, /**< aal0 pdu */
- IX_ATMDACC_OAM_VALID, /**< OAM pdu */
- IX_ATMDACC_AAL2_VALID, /**< aal2 pdu @b reserved for future use */
- IX_ATMDACC_AAL5_VALID, /**< aal5 pdu complete and trailer is valid */
- IX_ATMDACC_AAL5_PARTIAL, /**< aal5 pdu not complete, trailer is missing */
- IX_ATMDACC_AAL5_CRC_ERROR, /**< aal5 pdu not complete, crc error/length error */
- IX_ATMDACC_MBUF_RETURN /**< empty buffer returned to the user */
-} IxAtmdAccPduStatus;
-
-
-/**
- *
- * @enum IxAtmdAccAalType
- *
- * @ingroup IxAtmdAccAPI
- *
- * @brief IxAtmdAcc AAL Service Type :
- *
- * IxAtmdAccAalType defines the type of traffic to run on this VC
- *
- */
-typedef enum
-{
- IX_ATMDACC_AAL5, /**< ITU-T AAL5 */
- IX_ATMDACC_AAL2, /**< ITU-T AAL2 @b reserved for future use */
- IX_ATMDACC_AAL0_48, /**< AAL0 48 byte payloads (cell header is added by NPE)*/
- IX_ATMDACC_AAL0_52, /**< AAL0 52 byte cell data (HEC is added by NPE) */
- IX_ATMDACC_OAM, /**< OAM cell transport service (HEC is added by NPE)*/
- IX_ATMDACC_MAX_SERVICE_TYPE /**< not a service, used for parameter validation */
-} IxAtmdAccAalType;
-
-/**
- *
- * @enum IxAtmdAccClpStatus
- *
- * @ingroup IxAtmdAccAPI
- *
- * @brief IxAtmdAcc CLP indication
- *
- * IxAtmdAccClpStatus defines the CLP status of the current PDU
- *
- */
-typedef enum
-{
- IX_ATMDACC_CLP_NOT_SET = 0, /**< CLP indication is not set */
- IX_ATMDACC_CLP_SET = 1 /**< CLP indication is set */
-} IxAtmdAccClpStatus;
-
-/**
- * @typedef IxAtmdAccUserId
- *
- * @ingroup IxAtmdAccAPI
- *
- * @brief User-supplied Id
- *
- * IxAtmdAccUserId is passed through callbacks and allows the
- * IxAtmdAcc user to identify the source of a call back. The range of
- * this user-owned Id is [0...2^32-1)].
- *
- * The user provides this own Ids on a per-channel basis as a parameter
- * in a call to @a ixAtmdAccRxVcConnect() or @a ixAtmdAccRxVcConnect()
- *
- * @sa ixAtmdAccRxVcConnect
- * @sa ixAtmdAccTxVcConnect
- *
- */
-typedef unsigned int IxAtmdAccUserId;
-
-/* ------------------------------------------------------
- Part of the IxAtmdAcc interface related to RX traffic
- ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @brief Rx callback prototype
- *
- * IxAtmdAccRxVcRxCallback is the prototype of the Rx callback user
- * function called once per PDU to pass a receive Pdu to a user on a
- * partilcular connection. The callback is likely to push the mbufs
- * to a protocol layer, and recycle the mbufs for a further use.
- *
- * @note -This function is called ONLY in the context of
- * the @a ixAtmdAccRxDispatch() function
- *
- * @sa ixAtmdAccRxDispatch
- * @sa ixAtmdAccRxVcConnect
- *
- * @param port @ref IxAtmLogicalPort [in] - the port on which this PDU was received
- * a logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
- * @param userId @ref IxAtmdAccUserId [in] - user Id provided in the call
- * to @a ixAtmdAccRxVcConnect()
- * @param status @ref IxAtmdAccPduStatus [in] - an indication about the PDU validity.
- * In the case of AAL0 the only possibile value is
- * AAL0_VALID, in this case the client may optionally determine
- * that an rx timeout occured by checking if the mbuf is
- * compleletly or only partially filled, the later case
- * indicating a timeout.
- * In the case of OAM the only possible value is OAM valid.
- * The status is set to @a IX_ATMDACC_MBUF_RETURN when
- * the mbuf is released during a disconnect process.
- * @param clp @ref IxAtmdAccClpStatus [in] - clp indication for this PDU.
- * For AAL5/AAL0_48 this information
- * is set if the clp bit of any rx cell is set
- * For AAL0-52/OAM the client may inspect the CLP in individual
- * cell headers in the PDU, and this parameter is set to 0.
- * @param *mbufPtr @ref IX_OSAL_MBUF [in] - depending on the servive type a pointer to
- * an mbuf (AAL5/AAL0/OAM) or mbuf chain (AAL5 only),
- * that comprises the complete PDU data.
- *
- * This parameter is guaranteed not to be a null pointer.
- *
- */
-typedef void (*IxAtmdAccRxVcRxCallback) (IxAtmLogicalPort port,
- IxAtmdAccUserId userId,
- IxAtmdAccPduStatus status,
- IxAtmdAccClpStatus clp,
- IX_OSAL_MBUF * mbufPtr);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @brief Callback prototype for free buffer level is low.
- *
- * IxAtmdAccRxVcFreeLowCallback is the prototype of the user function
- * which get called on a per-VC basis, when more mbufs are needed to
- * continue the ATM data reception. This function is likely to supply
- * more available mbufs by one or many calls to the replenish function
- * @a ixAtmdAccRxVcFreeReplenish()
- *
- * This function is called when the number of available buffers for
- * reception is going under the threshold level as defined
- * in @a ixAtmdAccRxVcFreeLowCallbackRegister()
- *
- * This function is called inside an Qmgr dispatch context. No system
- * resource or interrupt-unsafe feature should be used inside this
- * callback.
- *
- * @sa ixAtmdAccRxVcFreeLowCallbackRegister
- * @sa IxAtmdAccRxVcFreeLowCallback
- * @sa ixAtmdAccRxVcFreeReplenish
- * @sa ixAtmdAccRxVcFreeEntriesQuery
- * @sa ixAtmdAccRxVcConnect
- *
- * @param userId @ref IxAtmdAccUserId [in] - user Id provided in the call
- * to @a ixAtmdAccRxVcConnect()
- *
- * @return None
- *
- */
-typedef void (*IxAtmdAccRxVcFreeLowCallback) (IxAtmdAccUserId userId);
-
-/* ------------------------------------------------------
- Part of the IxAtmdAcc interface related to TX traffic
- ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @brief Buffer callback prototype.
- *
- * This function is called to relinguish ownership of a transmitted
- * buffer chain to the user.
- *
- * @note -In the case of a chained mbuf the AmtdAcc component can
- * chain many user buffers together and pass ownership to the user in
- * one function call.
- *
- * @param userId @ref IxAtmdAccUserId [in] - user If provided at registration of this
- * callback.
- * @param mbufPtr @ref IX_OSAL_MBUF [in] - a pointer to mbufs or chain of mbufs and is
- * guaranteed not to be a null pointer.
- *
- */
-typedef void (*IxAtmdAccTxVcBufferReturnCallback) (IxAtmdAccUserId userId,
- IX_OSAL_MBUF * mbufPtr);
-
-/* ------------------------------------------------------
- Part of the IxAtmdAcc interface related to Initialisation
- ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccInit (void)
- *
- * @brief Initialise the IxAtmdAcc Component
- *
- * This function initialise the IxAtmdAcc component. This function shall
- * be called before any other function of the API. Its role is to
- * initialise all internal resources of the IxAtmdAcc component.
- *
- * The ixQmgr component needs to be initialized prior the use of
- * @a ixAtmdAccInit()
- *
- * @param none
- *
- * Failing to initilialize the IxAtmdAcc API before any use of it will
- * result in a failed status.
- * If the specified component is not present, a success status will still be
- * returned, however, a warning indicating the NPE to download to is not
- * present will be issued.
- *
- * @return @li IX_SUCCESS initialisation is complete (in case of component not
- * being present, a warning is clearly indicated)
- * @return @li IX_FAIL unable to process this request either
- * because this IxAtmdAcc is already initialised
- * or some unspecified error has occrred.
- */
-PUBLIC IX_STATUS ixAtmdAccInit (void);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccShow (void)
- *
- * @brief Show IxAtmdAcc configuration on a per port basis
- *
- * @param none
- *
- * @return none
- *
- * @note - Display use printf() and are redirected to stdout
- */
-PUBLIC void
-ixAtmdAccShow (void);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccStatsShow (void)
- *
- * @brief Show all IxAtmdAcc stats
- *
- * @param none
- *
- * @return none
- *
- * @note - Stats display use printf() and are redirected to stdout
- */
-PUBLIC void
-ixAtmdAccStatsShow (void);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccStatsReset (void)
- *
- * @brief Reset all IxAtmdAcc stats
- *
- * @param none
- *
- * @return none
- *
- */
-PUBLIC void
-ixAtmdAccStatsReset (void);
-
-/* ------------------------------------------------------
- Part of the IxAtmdAcc interface related to RX traffic
- ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccRxVcConnect (IxAtmLogicalPort port,
- unsigned int vpi,
- unsigned int vci,
- IxAtmdAccAalType aalServiceType,
- IxAtmRxQueueId rxQueueId,
- IxAtmdAccUserId userCallbackId,
- IxAtmdAccRxVcRxCallback rxCallback,
- unsigned int minimumReplenishCount,
- IxAtmConnId * connIdPtr,
- IxAtmNpeRxVcId * npeVcIdPtr )
- *
- * @brief Connect to a Aal Pdu receive service for a particular
- * port/vpi/vci, and service type.
- *
- * This function allows a user to connect to an Aal5/Aal0/OAM Pdu receive service
- * for a particular port/vpi/vci. It registers the callback and allocates
- * internal resources and a Connection Id to be used in further API calls
- * related to this VCC.
- *
- * The function will setup VC receive service on the specified rx queue.
- *
- * This function is blocking and makes use internal locks, and hence
- * should not be called from an interrupt context.
- *
- * On return from @a ixAtmdAccRxVcConnect() with a failure status, the
- * connection Id parameter is unspecified. Its value cannot be used.
- * A connId is the reference by which IxAtmdAcc refers to a
- * connected VC. This identifier is the result of a succesful call
- * to a connect function. This identifier is invalid after a
- * sucessful call to a disconnect function.
- *
- * Calling this function for the same combination of Vpi, Vci and more
- * than once without calling @a ixAtmdAccRxVcTryDisconnect() will result in a
- * failure status.
- *
- * If this function returns success the user should supply receive
- * buffers by calling @a ixAtmdAccRxVcFreeReplenish() and then call
- * @a ixAtmdAccRxVcEnable() to begin receiving pdus.
- *
- * There is a choice of two receive Qs on which the VC pdus could be
- * receive. The user must associate the VC with one of these. Essentially
- * having two qs allows more flexible system configuration such as have
- * high prioriy traffic on one q (e.g. voice) and low priority traffic on
- * the other (e.g. data). The high priority Q could be serviced in
- * preference to the low priority Q. One queue may be configured to be
- * serviced as soon as there is traffic, the other queue may be configured
- * to be serviced by a polling mechanism running at idle time.
- *
- * Two AAL0 services supporting 48 or 52 byte cell data are provided.
- * Received AAL0 PDUs will be be a multiple of the cell data size (48/52).
- * AAL0_52 is a raw cell service and includes an ATM cell header
- * (excluding HEC) at the start of each cell.
- *
- * A single "OAM Rx channel" for all ports may be enabled by
- * establishing a dedicated OAM Rx connection.
- *
- * The OAM service allows buffers containing 52 byte OAM F4/F5 cells
- * to be transmitted and received over the dedicated OAM channels.
- * HEC is appended/removed, and CRC-10 performed by the NPE. The OAM
- * service offered by AtmdAcc is a raw cell transport service.
- * It is assumed that ITU I.610 procedures that make use of this
- * service are implemented above AtmdAcc.
- *
- * Note that the dedicated OAM connections are established on
- * reserved VPI,VCI, and (in the case of Rx) port values.
- * These values are used purely to descriminate the dedicated OAM channels
- * and do not identify a particular OAM F4/F5 flow. F4/F5 flows may be
- * realised for particluar VPI/VCIs by manipulating the VPI,VCI
- * fields of the ATM cell headers of cells in the buffers passed
- * to AtmdAcc.
- *
- * Calling this function prior to enable the port will fail.
- *
- * @sa ixAtmdAccRxDispatch
- * @sa ixAtmdAccRxVcEnable
- * @sa ixAtmdAccRxVcDisable
- * @sa ixAtmdAccRxVcTryDisconnect
- * @sa ixAtmdAccPortEnable
- *
- * @param port @ref IxAtmLogicalPort [in] - VC identification : logical PHY port
- * [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
- * @param vpi unsigned int [in] - VC identification : ATM Vpi [0..255] or IX_ATMDACC_OAM_VPI
- * @param vci unsigned int [in] - VC identification : ATM Vci [0..65535] or IX_ATMDACC_OAM_VCI
- * @param aalServiceType @ref IxAtmdAccAalType [in] - type of service: AAL5, AAL0_48, AAL0_52, or OAM
- * @param rxQueueId @ref IxAtmRxQueueId [in] - this identifieds which of two Qs the VC
- * should use.when icoming traffic is processed
- * @param userCallbackId @ref IxAtmdAccUserId [in] - user Id used later as a parameter to
- * the supplied rxCallback.
- * @param rxCallback [in] @ref IxAtmdAccRxVxRxCallback - function called when mbufs are received.
- * This parameter cannot be a null pointer.
- * @param bufferFreeCallback [in] - function to be called to return
- * ownership of buffers to IxAtmdAcc user.
- * @param minimumReplenishCount unsigned int [in] - For AAL5/AAL0 the number of free mbufs
- * to be used with this channel. Use a high number when the expected traffic
- * rate on this channel is high, or when the user's mbufs are small, or when
- * the RxVcFreeLow Notification has to be invoked less often. When this
- * value is IX_ATMDACC_DEFAULT_REPLENISH_COUNT, the minimum of
- * resources will be used. Depending on traffic rate, pdu
- * size and mbuf size, rxfree queue size, polling/interrupt rate, this value may
- * require to be replaced by a different value in the range 1-128
- * For OAM the rxFree queue size is fixed by atmdAcc and this parameter is ignored.
- * @param connIdPtr @ref IxAtmConnId [out] - pointer to a connection Id
- * This parameter cannot be a null pointer.
- * @param npeVcIdPtr @ref IxAtmNpeRxVcId [out] - pointer to an npe Vc Id
- * This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS successful call to IxAtmdAccRxVcConnect
- * @return @li IX_ATMDACC_BUSY cannot process this request :
- * no VC is available
- * @return @li IX_FAIL
- * parameter error,
- * VC already in use,
- * attempt to connect AAL service on reserved OAM VPI/VCI,
- * attempt to connect OAM service on VPI/VCI other than the reserved OAM VPI/VCI,
- * port is not initialised,
- * or some other error occurs during processing.
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxVcConnect (IxAtmLogicalPort port,
- unsigned int vpi,
- unsigned int vci,
- IxAtmdAccAalType aalServiceType,
- IxAtmRxQueueId rxQueueId,
- IxAtmdAccUserId userCallbackId,
- IxAtmdAccRxVcRxCallback rxCallback,
- unsigned int minimumReplenishCount,
- IxAtmConnId * connIdPtr,
- IxAtmNpeRxVcId * npeVcIdPtr );
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccRxVcFreeReplenish (IxAtmConnId connId,
- IX_OSAL_MBUF * mbufPtr)
- *
- * @brief Provide free mbufs for data reception on a connection.
- *
- * This function provides mbufs for data reception by the hardware. This
- * function needs to be called by the user on a regular basis to ensure
- * no packet loss. Providing free buffers is a connection-based feature;
- * each connection can have different requirements in terms of buffer size
- * number of buffers, recycling rate. This function could be invoked from
- * within the context of a @a IxAtmdAccRxVcFreeLowCallback() callback
- * for a particular VC
- *
- * Mbufs provided through this function call can be chained. They will be
- * unchained internally. A call to this function with chained mbufs or
- * multiple calls with unchained mbufs are equivalent, but calls with
- * unchained mbufs are more efficients.
- *
- * Mbufs provided to this interface need to be able to hold at least one
- * full cell payload (48/52 bytes, depending on service type).
- * Chained buffers with a size less than the size supported by the hardware
- * will be returned through the rx callback provided during the connect step.
- *
- * Failing to invoke this function prior to enabling the RX traffic
- * can result in packet loss.
- *
- * This function is not reentrant for the same connId.
- *
- * This function does not use system resources and can be
- * invoked from an interrupt context.
- *
- * @note - Over replenish is detected, and extra mbufs are returned through
- * the rx callback provided during the connect step.
- *
- * @note - Mbuf provided to the replenish function should have a length greater or
- * equal to 48/52 bytes according to service type.
- *
- * @note - The memory cache of mMbuf payload should be invalidated prior to Mbuf
- * submission. Flushing the Mbuf headers is handled by IxAtmdAcc.
- *
- * @note - When a chained mbuf is provided, this function process the mbufs
- * up to the hardware limit and invokes the user-supplied callback
- * to release extra buffers.
- *
- * @sa ixAtmdAccRxVcFreeLowCallbackRegister
- * @sa IxAtmdAccRxVcFreeLowCallback
- * @sa ixAtmdAccRxVcConnect
- *
- * @param connId @ref IxAtmConnId [in] - connection Id as returned from a succesfull call to
- * @a IxAtmdAccRxVcConnect()
- * @param mbufPtr @ref IX_OSAL_MBUF [in] - pointer to a mbuf structure to be used for data
- * reception. The mbuf pointed to by this parameter can be chained
- * to an other mbuf.
- *
- * @return @li IX_SUCCESS successful call to @a ixAtmdAccRxVcFreeReplenish()
- * and the mbuf is now ready to use for incoming traffic.
- * @return @li IX_ATMDACC_BUSY cannot process this request because
- * the max number of outstanding free buffers has been reached
- * or the internal resources have exhausted for this VC.
- * The user is responsible for retrying this request later.
- * @return @li IX_FAIL cannot process this request because of parameter
- * errors or some unspecified internal error has occurred.
- *
- * @note - It is not always guaranteed the replenish step to be as fast as the
- * hardware is consuming Rx Free mbufs. There is nothing in IxAtmdAcc to
- * guarantee that replenish reaches the rxFree threshold level. If the
- * threshold level is not reached, the next rxFree low notification for
- * this channel will not be triggered.
- * The preferred ways to replenish can be as follows (depending on
- * applications and implementations) :
- * @li Replenish in a rxFree low notification until the function
- * ixAtmdAccRxVcFreeReplenish() returns IX_ATMDACC_BUSY
- * @li Query the queue level using @sa ixAtmdAccRxVcFreeEntriesQuery, then
- * , replenish using @a ixAtmdAccRxVcFreeReplenish(), then query the queue
- * level again, and replenish if the threshold is still not reached.
- * @li Trigger replenish from an other event source and use rxFree starvation
- * to throttle the Rx traffic.
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxVcFreeReplenish (IxAtmConnId connId,
- IX_OSAL_MBUF * mbufPtr);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccRxVcFreeLowCallbackRegister (IxAtmConnId connId,
- unsigned int numberOfMbufs,
- IxAtmdAccRxVcFreeLowCallback callback)
- *
- * @brief Configure the RX Free threshold value and register a callback
- * to handle threshold notifications.
- *
- * The function ixAtmdAccRxVcFreeLowCallbackRegister sets the threshold value for
- * a particular RX VC. When the number of buffers reaches this threshold
- * the callback is invoked.
- *
- * This function should be called once per VC before RX traffic is
- * enabled.This function will fail if the curent level of the free buffers
- * is equal or less than the threshold value.
- *
- * @sa ixAtmdAccRxVcFreeLowCallbackRegister
- * @sa IxAtmdAccRxVcFreeLowCallback
- * @sa ixAtmdAccRxVcFreeReplenish
- * @sa ixAtmdAccRxVcFreeEntriesQuery
- * @sa ixAtmdAccRxVcConnect
- *
- * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call
- * to @a IxAtmdAccRxVcConnect()
- * @param numberOfMbufs unsigned int [in] - threshold number of buffers. This number
- * has to be a power of 2, one of the values 0,1,2,4,8,16,32....
- * The maximum value cannot be more than half of the rxFree queue
- * size (which can be retrieved using @a ixAtmdAccRxVcFreeEntriesQuery()
- * before any use of the @a ixAtmdAccRxVcFreeReplenish() function)
- * @param callback @ref IxAtmdAccRxVcFreeLowCallback [in] - function telling the user that the number of
- * free buffers has reduced to the threshold value.
- *
- * @return @li IX_SUCCESS Threshold set successfully.
- * @return @li IX_FAIL parameter error or the current number of free buffers
- * is less than or equal to the threshold supplied or some
- * unspecified error has occrred.
- *
- * @note - the callback will be called when the threshold level will drop from
- * exactly (numberOfMbufs + 1) to (numberOfMbufs).
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxVcFreeLowCallbackRegister (IxAtmConnId connId,
- unsigned int numberOfMbufs,
- IxAtmdAccRxVcFreeLowCallback callback);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccRxVcFreeEntriesQuery (IxAtmConnId connId,
- unsigned int *numberOfMbufsPtr)
- *
- * @brief Get the number of rx mbufs the system can accept to replenish the
- * the rx reception mechanism on a particular channel
- *
- * The ixAtmdAccRxVcFreeEntriesQuery function is used to retrieve the current
- * number of available mbuf entries for reception, on a per-VC basis. This
- * function can be used to know the number of mbufs which can be provided
- * using @a ixAtmdAccRxVcFreeReplenish().
- *
- * This function can be used from a timer context, or can be associated
- * with a threshold event, or can be used inside an active polling
- * mechanism which is under user control.
- *
- * This function is reentrant and does not use system resources and can
- * be invoked from an interrupt context.
- *
- * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call
- * to @a IxAtmdAccRxVcConnect()
- * @param numberOfMbufsPtr unsigned int [out] - Pointer to the number of available entries.
- * . This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS the current number of mbufs not yet used for incoming traffic
- * @return @li IX_FAIL invalid parameter
- *
- * @sa ixAtmdAccRxVcFreeReplenish
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxVcFreeEntriesQuery (IxAtmConnId connId,
- unsigned int *numberOfMbufsPtr);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccRxVcEnable (IxAtmConnId connId)
- *
- * @brief Start the RX service on a VC.
- *
- * This functions kicks-off the traffic reception for a particular VC.
- * Once invoked, incoming PDUs will be made available by the hardware
- * and are eventually directed to the @a IxAtmdAccRxVcRxCallback() callback
- * registered for the connection.
- *
- * If the traffic is already running, this function returns IX_SUCCESS.
- * This function can be invoked many times.
- *
- * IxAtmdAccRxVcFreeLowCallback event will occur only after
- * @a ixAtmdAccRxVcEnable() function is invoked.
- *
- * Before using this function, the @a ixAtmdAccRxVcFreeReplenish() function
- * has to be used to replenish the RX Free queue. If not, incoming traffic
- * may be discarded.and in the case of interrupt driven reception the
- * @a IxAtmdAccRxVcFreeLowCallback() callback may be invoked as a side effect
- * during a replenish action.
- *
- * This function is not reentrant and should not be used inside an
- * interrupt context.
- *
- * For an VC connection this function can be called after a call to
- * @a ixAtmdAccRxVcDisable() and should not be called after
- * @a ixAtmdAccRxVcTryDisconnect()
- *
- * @sa ixAtmdAccRxVcDisable
- * @sa ixAtmdAccRxVcConnect
- * @sa ixAtmdAccRxVcFreeReplenish
- *
- * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call
- * to @a IxAtmdAccRxVcConnect()
- *
- * @return @li IX_SUCCESS successful call to ixAtmdAccRxVcEnable
- * @return @li IX_ATMDACC_WARNING the channel is already enabled
- * @return @li IX_FAIL invalid parameters or some unspecified internal
- * error occured.
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxVcEnable (IxAtmConnId connId);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccRxVcDisable (IxAtmConnId connId)
- *
- * @brief Stop the RX service on a VC.
- *
- * This functions stops the traffic reception for a particular VC connection.
- *
- * Once invoked, incoming Pdus are discarded by the hardware. Any Pdus
- * pending will be freed to the user
- *
- * Hence once this function returns no more receive callbacks will be
- * called for that VC. However, buffer free callbacks will be invoked
- * until such time as all buffers supplied by the user have been freed
- * back to the user
- *
- * Calling this function doe not invalidate the connId.
- * @a ixAtmdAccRxVcEnable() can be invoked to enable Pdu reception again.
- *
- * If the traffic is already stopped, this function returns IX_SUCCESS.
- *
- * This function is not reentrant and should not be used inside an
- * interrupt context.
- *
- * @sa ixAtmdAccRxVcConnect
- * @sa ixAtmdAccRxVcEnable
- * @sa ixAtmdAccRxVcDisable
- *
- * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call to @a
- * IxAtmdAccRxVcConnect()
- *
- * @return @li IX_SUCCESS successful call to @a ixAtmdAccRxVcDisable().
- * @return @li IX_ATMDACC_WARNING the channel is already disabled
- * @return @li IX_FAIL invalid parameters or some unspecified internal error occured
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxVcDisable (IxAtmConnId connId);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccRxVcTryDisconnect (IxAtmConnId connId)
- *
- * @brief Disconnect a VC from the RX service.
- *
- * This function deregisters the VC and guarantees that all resources
- * associated with this VC are free. After its execution, the connection
- * Id is not available.
- *
- * This function will fail until such time as all resources allocated to
- * the VC connection have been freed. The user is responsible to delay and
- * call again this function many times until a success status is returned.
- *
- * This function needs internal locks and should not be called from an
- * interrupt context
- *
- * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call to
- * @a IxAtmdAccRxVcConnect()
- *
- * @return @li IX_SUCCESS successful call to ixAtmdAccRxVcDisable
- * @return @li IX_ATMDACC_RESOURCES_STILL_ALLOCATED not all resources
- * associated with the connection have been freed.
- * @return @li IX_FAIL cannot process this request because of a parameter
- * error
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxVcTryDisconnect (IxAtmConnId connId);
-
-/* ------------------------------------------------------
- Part of the IxAtmdAcc interface related to TX traffic
- ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccTxVcConnect (IxAtmLogicalPort port,
- unsigned int vpi,
- unsigned int vci,
- IxAtmdAccAalType aalServiceType,
- IxAtmdAccUserId userId,
- IxAtmdAccTxVcBufferReturnCallback bufferFreeCallback,
- IxAtmConnId * connIdPtr)
- *
- * @brief Connect to a Aal Pdu transmit service for a particular
- * port/vpi/vci and service type.
- *
- * This function allows a user to connect to an Aal5/Aal0/OAM Pdu transmit service
- * for a particular port/vpi/vci. It registers the callback and allocates
- * internal resources and a Connection Id to be used in further API calls
- * related to this VC.
- *
- * The function will setup VC transmit service on the specified on the
- * specified port. A connId is the reference by which IxAtmdAcc refers to a
- * connected VC. This identifier is the result of a succesful call
- * to a connect function. This identifier is invalid after a
- * sucessful call to a disconnect function.
- *
- * This function needs internal locks, and hence should not be called
- * from an interrupt context.
- *
- * On return from @a ixAtmdAccTxVcConnect() with a failure status, the
- * connection Id parameter is unspecified. Its value cannot be used.
- *
- * Calling this function for the same combination of port, Vpi, Vci and
- * more than once without calling @a ixAtmdAccTxVcTryDisconnect() will result
- * in a failure status.
- *
- * Two AAL0 services supporting 48 or 52 byte cell data are provided.
- * Submitted AAL0 PDUs must be a multiple of the cell data size (48/52).
- * AAL0_52 is a raw cell service the client must format
- * the PDU with an ATM cell header (excluding HEC) at the start of
- * each cell, note that AtmdAcc does not validate the cell headers in
- * a submitted PDU.
- *
- * For the OAM service an "OAM Tx channel" may be enabled for a port
- * by establishing a single dedicated OAM Tx connection on that port.
- *
- * The OAM service allows buffers containing 52 byte OAM F4/F5 cells
- * to be transmitted and received over the dedicated OAM channels.
- * HEC is appended/removed, and CRC-10 performed by the NPE. The OAM
- * service offered by AtmdAcc is a raw cell transport service.
- * It is assumed that ITU I.610 procedures that make use of this
- * service are implemented above AtmdAcc.
- *
- * Note that the dedicated OAM connections are established on
- * reserved VPI,VCI, and (in the case of Rx) port values.
- * These values are used purely to descriminate the dedicated OAM channels
- * and do not identify a particular OAM F4/F5 flow. F4/F5 flows may be
- * realised for particluar VPI/VCIs by manipulating the VPI,VCI
- * fields of the ATM cell headers of cells in the buffers passed
- * to AtmdAcc.
- *
- * Calling this function before enabling the port will fail.
- *
- * @sa ixAtmdAccTxVcTryDisconnect
- * @sa ixAtmdAccPortTxScheduledModeEnable
- * @sa ixAtmdAccPortEnable
- *
- * @param port @ref IxAtmLogicalPort [in] - VC identification : logical PHY port
- * [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
- * @param vpi unsigned int [in] - VC identification : ATM Vpi [0..255] or IX_ATMDACC_OAM_VPI
- * @param vci unsigned int [in] - VC identification : ATM Vci [0..65535] or IX_ATMDACC_OAM_VCI
- * @param aalServiceType @ref IxAtmdAccAalType [in] - type of service AAL5, AAL0_48, AAL0_52, or OAM
- * @param userId @ref IxAtmdAccUserId [in] - user id to be used later during callbacks related
- * to this channel
- * @param bufferFreeCallback @ref IxAtmdAccTxVcBufferReturnCallback [in] - function called when mbufs
- * transmission is complete. This parameter cannot be a null
- * pointer.
- * @param connIdPtr @ref IxAtmConnId [out] - Pointer to a connection Id.
- * This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS successful call to @a IxAtmdAccRxVcConnect().
- * @return @li IX_ATMDACC_BUSY cannot process this request
- * because no VC is available
- * @return @li IX_FAIL
- * parameter error,
- * VC already in use,
- * attempt to connect AAL service on reserved OAM VPI/VCI,
- * attempt to connect OAM service on VPI/VCI other than the reserved OAM VPI/VCI,
- * port is not initialised,
- * or some other error occurs during processing.
- *
- * @note - Unscheduled mode is not supported in ixp425 1.0. Therefore, the
- * function @a ixAtmdAccPortTxScheduledModeEnable() need to be called
- * for this port before any establishing a Tx Connection
- */
-PUBLIC IX_STATUS ixAtmdAccTxVcConnect (IxAtmLogicalPort port,
- unsigned int vpi,
- unsigned int vci,
- IxAtmdAccAalType aalServiceType,
- IxAtmdAccUserId userId,
- IxAtmdAccTxVcBufferReturnCallback bufferFreeCallback,
- IxAtmConnId * connIdPtr);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccTxVcPduSubmit (IxAtmConnId connId,
- IX_OSAL_MBUF * mbufPtr,
- IxAtmdAccClpStatus clp,
- unsigned int numberOfCells)
- *
- * @brief Submit a Pdu for transmission on connection.
- *
- * A data user calls this function to submit an mbufs containing a Pdu
- * to be transmitted. The buffer supplied can be chained and the Pdu it
- * contains must be complete.
- *
- * The transmission behavior of this call depends on the operational mode
- * of the port on which the connection is made.
- *
- * In unscheduled mode the mbuf will be submitted to the hardware
- * immediately if sufficent resource is available. Otherwise the function
- * will return failure.
- *
- * In scheduled mode the buffer is queued internally in IxAtmdAcc. The cell
- * demand is made known to the traffic shaping entity. Cells from the
- * buffers are MUXed onto the port some time later as dictated by the
- * traffic shaping entity. The traffic shaping entity does this by sending
- * transmit schedules to IxAtmdAcc via @a ixAtmdAccPortTxProcess() function call.
- *
- * Note that the dedicated OAM channel is scheduled just like any
- * other channel. This means that any OAM traffic relating to an
- * active AAL0/AAL5 connection will be scheduled independantly of the
- * AAL0/AAL5 traffic for that connection.
- *
- * When transmission is complete, the TX Done mechanism will give the
- * owmnership of these buffers back to the customer. The tx done mechanism
- * must be in operation before transmission is attempted.
- *
- * For AAL0/OAM submitted AAL0 PDUs must be a multiple of the cell data
- * size (48/52). AAL0_52 and OAM are raw cell services, and the client
- * must format the PDU with an ATM cell header (excluding HEC) at the
- * start of each cell, note that AtmdAcc does not validate the cell headers in
- * a submitted PDU.
- *
- *
- * @sa IxAtmdAccTxVcBufferReturnCallback
- * @sa ixAtmdAccTxDoneDispatch
- *
- * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call to
- * @a ixAtmdAccTxVcConnect()
- * @param mbufPtr @ref IX_OSAL_MBUF [in] - pointer to a chained structure of mbufs to transmit.
- * This parameter cannot be a null pointer.
- * @param clp @ref IxAtmdAccClpStatus [in] - clp indication for this PDU. All cells of this pdu
- * will be sent with the clp bit set
- * @param numberOfCells unsigned int [in] - number of cells in the PDU.
- *
- * @return @li IX_SUCCESS successful call to @a ixAtmdAccTxVcPduSubmit()
- * The pdu pointed by the mbufPtr parameter will be
- * transmitted
- * @return @li IX_ATMDACC_BUSY unable to process this request because
- * internal resources are all used. The caller is responsible
- * for retrying this request later.
- * @return @li IX_FAIL unable to process this request because of error
- * in the parameters (wrong connId supplied,
- * or wrong mbuf pointer supplied), the total length of all buffers
- * in the chain should be a multiple of the cell size
- * ( 48/52 depending on the service type ),
- * or unspecified error during processing
- *
- * @note - This function in not re-entrant for the same VC (e.g. : two
- * thread cannot send PDUs for the same VC). But two threads can
- * safely call this function with a different connection Id
- *
- * @note - In unscheduled mode, this function is not re-entrant on a per
- * port basis. The size of pdus is limited to 8Kb.
- *
- * @note - 0-length mbufs should be removed from the chain before submission.
- * The total length of the pdu (sdu + padding +trailer) has to be
- * updated in the header of the first mbuf of a chain of mbufs.
- *
- * @note - Aal5 trailer information (UUI, CPI, SDU length) has to be supplied
- * before submission.
- *
- * @note - The payload memory cache should be flushed, if needed, prior to
- * transmission. Mbuf headers are flushed by IxAtmdAcc
- *
- * @note - This function does not use system resources and can be used
- * inside an interrupt context
- */
-PUBLIC IX_STATUS ixAtmdAccTxVcPduSubmit (IxAtmConnId connId,
- IX_OSAL_MBUF * mbufPtr,
- IxAtmdAccClpStatus clp,
- unsigned int numberOfCells);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccTxVcTryDisconnect (IxAtmConnId connId)
- *
- * @brief Disconnect from a Aal Pdu transmit service for a particular
- * port/vpi/vci.
- *
- * This function deregisters the VC and guarantees that all resources
- * associated with this VC are free. After its execution, the connection
- * Id is not available.
- *
- * This function will fail until such time as all resources allocated to
- * the VC connection have been freed. The user is responsible to delay
- * and call again this function many times until a success status is
- * returned.
- *
- * After its execution, the connection Id is not available.
- *
- * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call to
- * @a ixAtmdAccTxVcConnect()
- *
- * @return @li IX_SUCCESS successful call to @a ixAtmdAccTxVcTryDisconnect()
- * @return @li IX_ATMDACC_RESOURCES_STILL_ALLOCATED not all resources
- * associated with the connection have been freed. This condition will
- * disappear after Tx and TxDone is complete for this channel.
- * @return @li IX_FAIL unable to process this request because of errors
- * in the parameters (wrong connId supplied)
- *
- * @note - This function needs internal locks and should not be called
- * from an interrupt context
- *
- * @note - If the @a IX_ATMDACC_RESOURCES_STILL_ALLOCATED error does not
- * clear after a while, this may be linked to a previous problem
- * of cell overscheduling. Diabling the port and retry a disconnect
- * will free the resources associated with this channel.
- *
- * @sa ixAtmdAccPortTxProcess
- *
- */
-PUBLIC IX_STATUS ixAtmdAccTxVcTryDisconnect (IxAtmConnId connId);
-
-#endif /* IXATMDACC_H */
-
-/**
- * @} defgroup IxAtmdAccAPI
- */
-
-
+++ /dev/null
-/**
- * @file IxAtmdAccCtrl.h
- *
- * @date 20-Mar-2002
- *
- * @brief IxAtmdAcc Public API
- *
- * This file contains the public API of IxAtmdAcc, related to the
- * control functions of the component.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/* ------------------------------------------------------
- Doxygen group definitions
- ------------------------------------------------------ */
-
-/**
- *
- * @defgroup IxAtmdAccCtrlAPI IXP400 ATM Driver Access (IxAtmdAcc) Control API
- *
- * @brief The public API for the IXP400 Atm Driver Control component
- *
- * IxAtmdAcc is the low level interface by which AAL PDU get transmitted
- * to,and received from the Utopia bus
- *
- * This part is related to the Control configuration
- *
- * @{
- */
-
-#ifndef IXATMDACCCTRL_H
-#define IXATMDACCCTRL_H
-
-#include "IxAtmdAcc.h"
-
-/* ------------------------------------------------------
- AtmdAccCtrl Data Types definition
- ------------------------------------------------------ */
-
-/**
-*
-* @ingroup IxAtmdAccCtrlAPI
-*
-* @def IX_ATMDACC_PORT_DISABLE_IN_PROGRESS
-*
-* @brief Port enable return code
-*
-* This constant is used to tell IxAtmDAcc user that the port disable
-* functions are not complete. The user can call ixAtmdAccPortDisableComplete()
-* to find out when the disable has finished. The port enable can then proceed.
-*
-*/
-#define IX_ATMDACC_PORT_DISABLE_IN_PROGRESS 5
-
-/**
-*
-* @ingroup IxAtmdAccCtrlAPI
-*
-* @def IX_ATMDACC_ALLPDUS
-*
-* @brief All PDUs
-*
-* This constant is used to tell IxAtmDAcc to process all PDUs from
-* the RX queue or the TX Done
-*
-* @sa IxAtmdAccRxDispatcher
-* @sa IxAtmdAccTxDoneDispatcher
-*
-*/
-#define IX_ATMDACC_ALLPDUS 0xffffffff
-
-/* ------------------------------------------------------
- Part of the IxAtmdAcc interface related to RX traffic
- ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @brief Callback prototype for notification of available PDUs for
- * an Rx Q.
- *
- * This a protoype for a function which is called when there is at
- * least one Pdu available for processing on a particular Rx Q.
- *
- * This function should call @a ixAtmdAccRxDispatch() with
- * the aprropriate number of parameters to read and process the Rx Q.
- *
- * @sa ixAtmdAccRxDispatch
- * @sa ixAtmdAccRxVcConnect
- * @sa ixAtmdAccRxDispatcherRegister
- *
- * @param rxQueueId @ref IxAtmRxQueueId [in] indicates which RX queue to has Pdus to process.
- * @param numberOfPdusToProcess unsigned int [in] indicates the minimum number of
- * PDUs available to process all PDUs from the queue.
- * @param reservedPtr unsigned int* [out] pointer to a int location which can
- * be written to, but does not retain written values. This is
- * provided to make this prototype compatible
- * with @a ixAtmdAccRxDispatch()
- *
- * @return @li int - ignored.
- *
- */
-typedef IX_STATUS (*IxAtmdAccRxDispatcher) (IxAtmRxQueueId rxQueueId,
- unsigned int numberOfPdusToProcess,
- unsigned int *reservedPtr);
-
-/* ------------------------------------------------------
- Part of the IxAtmdAcc interface related to TX traffic
- ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @brief Callback prototype for transmitted mbuf when threshold level is
- * crossed.
- *
- * IxAtmdAccTxDoneDispatcher is the prototype of the user function
- * which get called when pdus are completely transmitted. This function
- * is likely to call the @a ixAtmdAccTxDoneDispatch() function.
- *
- * This function is called when the number of available pdus for
- * reception is crossing the threshold level as defined
- * in @a ixAtmdAccTxDoneDispatcherRegister()
- *
- * This function is called inside an Qmgr dispatch context. No system
- * resource or interrupt-unsafe feature should be used inside this
- * callback.
- *
- * Transmitted buffers recycling implementation is a sytem-wide mechanism
- * and needs to be set before any traffic is started. If this threshold
- * mechanism is not used, the user is responsible for polling the
- * transmitted buffers with @a ixAtmdAccTxDoneDispatch()
- * and @a ixAtmdAccTxDoneLevelQuery() functions.
- *
- * @sa ixAtmdAccTxDoneDispatcherRegister
- * @sa ixAtmdAccTxDoneDispatch
- * @sa ixAtmdAccTxDoneLevelQuery
- *
- * @param numberOfPdusToProcess unsigned int [in] - The current number of pdus currently
- * available for recycling
- * @param *reservedPtr unsigned int [out] - pointer to a int location which can be
- * written to but does not retain written values. This is provided
- * to make this prototype compatible
- * with @a ixAtmdAccTxDoneDispatch()
- *
- * @return @li IX_SUCCESS This is provided to make
- * this prototype compatible with @a ixAtmdAccTxDoneDispatch()
- * @return @li IX_FAIL invalid parameters or some unspecified internal
- * error occured. This is provided to make
- * this prototype compatible with @a ixAtmdAccTxDoneDispatch()
- *
- */
-typedef IX_STATUS (*IxAtmdAccTxDoneDispatcher) (unsigned int numberOfPdusToProcess,
- unsigned int *reservedPtr);
-
-/**
-*
-* @ingroup IxAtmdAccCtrlAPI
-*
-* @brief Notification that the threshold number of scheduled cells
-* remains in a port's transmit Q.
-*
-* The is the prototype for of the user notification function which
-* gets called on a per-port basis, when the number of remaining
-* scheduled cells to be transmitted decreases to the threshold level.
-* The number of cells passed as a parameter can be used for scheduling
-* purposes as the maximum number of cells that can be passed in a
-* schedule table to the @a ixAtmdAccPortTxProcess() function.
-*
-* @sa ixAtmdAccPortTxCallbackRegister
-* @sa ixAtmdAccPortTxProcess
-* @sa ixAtmdAccPortTxFreeEntriesQuery
-*
-* @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
-* @param numberOfAvailableCells unsigned int [in] - number of available
-* cell entries.for the port
-*
-* @note - This functions shall not use system resources when used
-* inside an interrupt context.
-*
-*/
-typedef void (*IxAtmdAccPortTxLowCallback) (IxAtmLogicalPort port,
- unsigned int numberOfAvailableCells);
-
-/**
-*
-* @ingroup IxAtmdAccCtrlAPI
-*
-* @brief Prototype to submit cells for transmission
-*
-* IxAtmdAccTxVcDemandUpdateCallback is the prototype of the callback
-* function used by AtmD to notify an ATM Scheduler that the user of
-* a VC has submitted cells for transmission.
-*
-* @sa IxAtmdAccTxVcDemandUpdateCallback
-* @sa IxAtmdAccTxVcDemandClearCallback
-* @sa IxAtmdAccTxSchVcIdGetCallback
-* @sa ixAtmdAccPortTxScheduledModeEnable
-*
-* @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the VC to be updated
-* is established
-* @param vcId int [in] - Identifies the VC to be updated. This is the value
-* returned by the @a IxAtmdAccTxSchVcIdGetCallback() call .
-* @param numberOfCells unsigned int [in] - Indicates how many ATM cells should be added
-* to the queue for this VC.
-*
-* @return @li IX_SUCCESS the function is registering the cell demand for
-* this VC.
-* @return @li IX_FAIL the function cannot register cell for this VC : the
-* scheduler maybe overloaded or misconfigured
-*
-*/
-typedef IX_STATUS (*IxAtmdAccTxVcDemandUpdateCallback) (IxAtmLogicalPort port,
- int vcId,
- unsigned int numberOfCells);
-
-/**
-*
-* @ingroup IxAtmdAccCtrlAPI
-*
-* @brief prototype to remove all currently queued cells from a
-* registered VC
-*
-* IxAtmdAccTxVcDemandClearCallback is the prototype of the function
-* to remove all currently queued cells from a registered VC. The
-* pending cell count for the specified VC is reset to zero. After the
-* use of this callback, the scheduler shall not schedule more cells
-* for this VC.
-*
-* This callback function is called during a VC disconnection
-* @a ixAtmdAccTxVcTryDisconnect()
-*
-* @sa IxAtmdAccTxVcDemandUpdateCallback
-* @sa IxAtmdAccTxVcDemandClearCallback
-* @sa IxAtmdAccTxSchVcIdGetCallback
-* @sa ixAtmdAccPortTxScheduledModeEnable
-* @sa ixAtmdAccTxVcTryDisconnect
-*
-* @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the VC to be cleared
-* is established
-* @param vcId int [in] - Identifies the VC to be cleared. This is the value
-* returned by the @a IxAtmdAccTxSchVcIdGetCallback() call .
-*
-* @return none
-*
-*/
-typedef void (*IxAtmdAccTxVcDemandClearCallback) (IxAtmLogicalPort port,
- int vcId);
-
-/**
-*
-* @ingroup IxAtmdAccCtrlAPI
-*
-* @brief prototype to get a scheduler vc id
-*
-* IxAtmdAccTxSchVcIdGetCallback is the prototype of the function to get
-* a scheduler vcId
-*
-* @sa IxAtmdAccTxVcDemandUpdateCallback
-* @sa IxAtmdAccTxVcDemandClearCallback
-* @sa IxAtmdAccTxSchVcIdGetCallback
-* @sa ixAtmdAccPortTxScheduledModeEnable
-*
-* @param port @ref IxAtmLogicalPort [in] - Specifies the ATM logical port on which the VC is
-* established
-* @param vpi unsigned int [in] - For AAL0/AAL5 specifies the ATM vpi on which the
-* VC is established.
-* For OAM specifies the dedicated "OAM Tx channel" VPI.
-* @param vci unsigned int [in] - For AAL0/AAL5 specifies the ATM vci on which the
-* VC is established.
-* For OAM specifies the dedicated "OAM Tx channel" VCI.
-* @param connId @ref IxAtmConnId [in] - specifies the IxAtmdAcc connection Id already
-* associated with this VC
-* @param vcId int* [out] - pointer to a vcId
-*
-* @return @li IX_SUCCESS the function is returning a Scheduler vcId for this
-* VC
-* @return @li IX_FAIL the function cannot process scheduling for this VC.
-* the contents of vcId is unspecified
-*
-*/
-typedef IX_STATUS (*IxAtmdAccTxSchVcIdGetCallback) (IxAtmLogicalPort port,
- unsigned int vpi,
- unsigned int vci,
- IxAtmConnId connId,
- int *vcId);
-
-/* ------------------------------------------------------
- Part of the IxAtmdAcc interface related to RX traffic
- ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccRxDispatcherRegister (
- IxAtmRxQueueId queueId,
- IxAtmdAccRxDispatcher callback)
- *
- * @brief Register a notification callback to be invoked when there is
- * at least one entry on a particular Rx queue.
- *
- * This function registers a callback to be invoked when there is at
- * least one entry in a particular queue. The registered callback is
- * called every time when the hardware adds one or more pdus to the
- * specified Rx queue.
- *
- * This function cannot be used when a Rx Vc using this queue is
- * already existing.
- *
- * @note -The callback function can be the API function
- * @a ixAtmdAccRxDispatch() : every time the threhold level
- * of the queue is reached, the ixAtmdAccRxDispatch() is
- * invoked to remove all entries from the queue.
- *
- * @sa ixAtmdAccRxDispatch
- * @sa IxAtmdAccRxDispatcher
- *
- * @param queueId @ref IxAtmRxQueueId [in] RX queue identification
- * @param callback @ref IxAtmdAccRxDispatcher [in] function triggering the delivery of incoming
- * traffic. This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS Successful call to @a ixAtmdAccRxDispatcherRegister()
- * @return @li IX_FAIL error in the parameters, or there is an
- * already active RX VC for this queue or some unspecified
- * internal error occurred.
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxDispatcherRegister (
- IxAtmRxQueueId queueId,
- IxAtmdAccRxDispatcher callback);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccRxDispatch (IxAtmRxQueueId rxQueueId,
- unsigned int numberOfPdusToProcess,
- unsigned int *numberOfPdusProcessedPtr)
- *
- *
- * @brief Control function which executes Rx processing for a particular
- * Rx stream.
- *
- * The @a IxAtmdAccRxDispatch() function is used to process received Pdus
- * available from one of the two incoming RX streams. When this function
- * is invoked, the incoming traffic (up to the number of PDUs passed as
- * a parameter) will be transferred to the IxAtmdAcc users through the
- * callback @a IxAtmdAccRxVcRxCallback(), as registered during the
- * @a ixAtmdAccRxVcConnect() call.
- *
- * The user receive callbacks will be executed in the context of this
- * function.
- *
- * Failing to use this function on a regular basis when there is traffic
- * will block incoming traffic and can result in Pdus being dropped by
- * the hardware.
- *
- * This should be used to control when received pdus are handed off from
- * the hardware to Aal users from a particluar stream. The function can
- * be used from a timer context, or can be registered as a callback in
- * response to an rx stream threshold event, or can be used inside an
- * active polling mechanism which is under user control.
- *
- * @note - The signature of this function is directly compatible with the
- * callback prototype which can be register with @a ixAtmdAccRxDispatcherRegister().
- *
- * @sa ixAtmdAccRxDispatcherRegister
- * @sa IxAtmdAccRxVcRxCallback
- * @sa ixAtmdAccRxVcFreeEntriesQuery
- *
- * @param rxQueueId @ref IxAtmRxQueueId [in] - indicates which RX queue to process.
- * @param numberOfPdusToProcess unsigned int [in] - indicates the maxiumum number of PDU to
- * remove from the RX queue. A value of IX_ATMDACC_ALLPDUS indicates
- * to process all PDUs from the queue. This includes at least the PDUs
- * in the queue when the fuction is invoked. Because of real-time
- * constraints, there is no guarantee thatthe queue will be empty
- * when the function exits. If this parameter is greater than the
- * number of entries of the queues, the function will succeed
- * and the parameter numberOfPdusProcessedPtr will reflect the exact
- * number of PDUs processed.
- * @param *numberOfPdusProcessedPtr unsigned int [out] - indicates the actual number of PDU
- * processed during this call. This parameter cannot be a null
- * pointer.
- *
- * @return @li IX_SUCCESS the number of PDUs as indicated in
- * numberOfPdusProcessedPtr are removed from the RX queue and the VC callback
- * are called.
- * @return @li IX_FAIL invalid parameters or some unspecified internal
- * error occured.
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxDispatch (IxAtmRxQueueId rxQueueId,
- unsigned int numberOfPdusToProcess,
- unsigned int *numberOfPdusProcessedPtr);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccRxLevelQuery (IxAtmRxQueueId rxQueueId,
- unsigned int *numberOfPdusPtr)
- *
- * @brief Query the number of entries in a particular RX queue.
- *
- * This function is used to retrieve the number of pdus received by
- * the hardware and ready for distribution to users.
- *
- * @param rxQueueId @ref IxAtmRxQueueId [in] - indicates which of two RX queues to query.
- * @param numberOfPdusPtr unsigned int* [out] - Pointer to store the number of available
- * PDUs in the RX queue. This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS the value in numberOfPdusPtr specifies the
- * number of incoming pdus waiting in this queue
- * @return @li IX_FAIL an error occurs during processing.
- * The value in numberOfPdusPtr is unspecified.
- *
- * @note - This function is reentrant, doesn't use system resources
- * and can be used from an interrupt context.
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxLevelQuery (IxAtmRxQueueId rxQueueId,
- unsigned int *numberOfPdusPtr);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccRxQueueSizeQuery (IxAtmRxQueueId rxQueueId,
- unsigned int *numberOfPdusPtr)
- *
- * @brief Query the size of a particular RX queue.
- *
- * This function is used to retrieve the number of pdus the system is
- * able to queue when reception is complete.
- *
- * @param rxQueueId @ref IxAtmRxQueueId [in] - indicates which of two RX queues to query.
- * @param numberOfPdusPtr unsigned int* [out] - Pointer to store the number of pdus
- * the system is able to queue in the RX queue. This parameter
- * cannot be a null pointer.
- *
- * @return @li IX_SUCCESS the value in numberOfPdusPtr specifies the
- * number of pdus the system is able to queue.
- * @return @li IX_FAIL an error occurs during processing.
- * The value in numberOfPdusPtr is unspecified.
- *
- * @note - This function is reentrant, doesn't use system resources
- * and can be used from an interrupt context.
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxQueueSizeQuery (IxAtmRxQueueId rxQueueId,
- unsigned int *numberOfPdusPtr);
-
-/* ------------------------------------------------------
- Part of the IxAtmdAcc interface related to TX traffic
- ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccPortTxFreeEntriesQuery (IxAtmLogicalPort port,
- unsigned int *numberOfCellsPtr)
- *
- * @brief Get the number of available cells the system can accept for
- * transmission.
- *
- * The function is used to retrieve the number of cells that can be
- * queued for transmission to the hardware.
- *
- * This number is based on the worst schedule table where one cell
- * is stored in one schedule table entry, depending on the pdus size
- * and mbuf size and fragmentation.
- *
- * This function doesn't use system resources and can be used from a
- * timer context, or can be associated with a threshold event, or can
- * be used inside an active polling mechanism
- *
- * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
- * @param numberOfCellsPtr unsigned int* [out] - number of available cells.
- * This parameter cannot be a null pointer.
- *
- * @sa ixAtmdAccPortTxProcess
- *
- * @return @li IX_SUCCESS numberOfCellsPtr contains the number of cells that can be scheduled
- * for this port.
- * @return @li IX_FAIL error in the parameters, or some processing error
- * occured.
- *
- */
-PUBLIC IX_STATUS ixAtmdAccPortTxFreeEntriesQuery (IxAtmLogicalPort port,
- unsigned int *numberOfCellsPtr);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccPortTxCallbackRegister (IxAtmLogicalPort port,
- unsigned int numberOfCells,
- IxAtmdAccPortTxLowCallback callback)
- *
- * @brief Configure the Tx port threshold value and register a callback to handle
- * threshold notifications.
- *
- * This function sets the threshold in cells
- *
- * @sa ixAtmdAccPortTxCallbackRegister
- * @sa ixAtmdAccPortTxProcess
- * @sa ixAtmdAccPortTxFreeEntriesQuery
- *
- * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
- * @param numberOfCells unsigned int [in] - threshold value which triggers the callback
- * invocation, This number has to be one of the
- * values 0,1,2,4,8,16,32 ....
- * The maximum value cannot be more than half of the txVc queue
- * size (which can be retrieved using @a ixAtmdAccPortTxFreeEntriesQuery()
- * before any Tx traffic is sent for this port)
- * @param callback @ref IxAtmdAccPortTxLowCallback [in] - callback function to invoke when the threshold
- * level is reached.
- * This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS Successful call to @a ixAtmdAccPortTxCallbackRegister()
- * @return @li IX_FAIL error in the parameters, Tx channel already set for this port
- * threshold level is not correct or within the range regarding the
- * queue size:or unspecified error during processing:
- *
- * @note - This callback function get called when the threshold level drops from
- * (numberOfCells+1) cells to (numberOfCells) cells
- *
- * @note - This function should be called during system initialisation,
- * outside an interrupt context
- *
- */
-PUBLIC IX_STATUS ixAtmdAccPortTxCallbackRegister (IxAtmLogicalPort port,
- unsigned int numberOfCells,
- IxAtmdAccPortTxLowCallback callback);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccPortTxScheduledModeEnable (IxAtmLogicalPort port,
- IxAtmdAccTxVcDemandUpdateCallback vcDemandUpdateCallback,
- IxAtmdAccTxVcDemandClearCallback vcDemandClearCallback,
- IxAtmdAccTxSchVcIdGetCallback vcIdGetCallback)
- *
- * @brief Put the port into Scheduled Mode
- *
- * This function puts the specified port into scheduled mode of
- * transmission which means an external s/w entity controls the
- * transmission of cells on this port. This faciltates traffic shaping on
- * the port.
- *
- * Any buffers submitted on a VC for this port will be queued in IxAtmdAcc.
- * The transmission of these buffers to and by the hardware will be driven
- * by a transmit schedule submitted regulary in calls to
- * @a ixAtmdAccPortTxProcess() by traffic shaping entity.
- *
- * The transmit schedule is expected to be dynamic in nature based on
- * the demand in cells for each VC on the port. Hence the callback
- * parameters provided to this function allow IxAtmdAcc to inform the
- * shaping entity of demand changes for each VC on the port.
- *
- * By default a port is in Unscheduled Mode so if this function is not
- * called, transmission of data is done without sheduling rules, on a
- * first-come, first-out basis.
- *
- * Once a port is put in scheduled mode it cannot be reverted to
- * un-scheduled mode. Note that unscheduled mode is not supported
- * in ixp425 1.0
- *
- * @note - This function should be called before any VCs have be
- * connected on a port. Otherwise this function call will return failure.
- *
- * @note - This function uses internal locks and should not be called from
- * an interrupt context
- *
- * @sa IxAtmdAccTxVcDemandUpdateCallback
- * @sa IxAtmdAccTxVcDemandClearCallback
- * @sa IxAtmdAccTxSchVcIdGetCallback
- * @sa ixAtmdAccPortTxProcess
- *
- * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
- * @param vcDemandUpdateCallback @ref IxAtmdAccTxVcDemandUpdateCallback [in] - callback function used to update
- * the number of outstanding cells for transmission. This parameter
- * cannot be a null pointer.
- * @param vcDemandClearCallback @ref IxAtmdAccTxVcDemandClearCallback [in] - callback function used to remove all
- * clear the number of outstanding cells for a VC. This parameter
- * cannot be a null pointer.
- * @param vcIdGetCallback @ref IxAtmdAccTxSchVcIdGetCallback [in] - callback function used to exchange vc
- * Identifiers between IxAtmdAcc and the entity supplying the
- * transmit schedule. This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS scheduler registration is complete and the port
- * is now in scheduled mode.
- * @return @li IX_FAIL failed (wrong parameters, or traffic is already
- * enabled on this port, possibly without ATM shaping)
- *
- */
-PUBLIC IX_STATUS ixAtmdAccPortTxScheduledModeEnable (IxAtmLogicalPort port,
- IxAtmdAccTxVcDemandUpdateCallback vcDemandUpdateCallback,
- IxAtmdAccTxVcDemandClearCallback vcDemandClearCallback,
- IxAtmdAccTxSchVcIdGetCallback vcIdGetCallback);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccPortTxProcess (IxAtmLogicalPort port,
- IxAtmScheduleTable* scheduleTablePtr)
- *
- * @brief Transmit queue cells to the H/W based on the supplied schedule
- * table.
- *
- * This function @a ixAtmdAccPortTxProcess() process the schedule
- * table provided as a parameter to the function. As a result cells are
- * sent to the underlaying hardware for transmission.
- *
- * The schedule table is executed in its entirety or not at all. So the
- * onus is on the caller not to submit a table containing more cells than
- * can be transmitted at that point. The maximum numbers that can be
- * transmitted is guaranteed to be the number of cells as returned by the
- * function @a ixAtmdAccPortTxFreeEntriesQuery().
- *
- * When the scheduler is invoked on a threshold level, IxAtmdAcc gives the
- * minimum number of cells (to ensure the callback will fire again later)
- * and the maximum number of cells that @a ixAtmdAccPortTxProcess()
- * will be able to process (assuming the ATM scheduler is able
- * to produce the worst-case schedule table, i.e. one entry per cell).
- *
- * When invoked ouside a threshold level, the overall number of cells of
- * the schedule table should be less than the number of cells returned
- * by the @a ixAtmdAccPortTxFreeEntriesQuery() function.
- *
- * After invoking the @a ixAtmdAccPortTxProcess() function, it is the
- * user choice to query again the queue level with the function
- * @a ixAtmdAccPortTxFreeEntriesQuery() and, depending on a new cell
- * number, submit an other schedule table.
- *
- * IxAtmdAcc will check that the number of cells in the schedule table
- * is compatible with the current transmit level. If the
- *
- * Obsolete or invalid connection Id will be silently discarded.
- *
- * This function is not reentrant for the same port.
- *
- * This functions doesn't use system resources and can be used inside an
- * interrupt context.
- *
- * This function is used as a response to the hardware requesting more
- * cells to transmit.
- *
- * @sa ixAtmdAccPortTxScheduledModeEnable
- * @sa ixAtmdAccPortTxFreeEntriesQuery
- * @sa ixAtmdAccPortTxCallbackRegister
- * @sa ixAtmdAccPortEnable
- *
- * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
- * @param scheduleTablePtr @ref IxAtmScheduleTable* [in] - pointer to a scheduler update table. The
- * content of this table is not modified by this function. This
- * parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS the schedule table process is complete
- * and cells are transmitted to the hardware
- * @return @li IX_ATMDACC_WARNING : Traffic will be dropped: the schedule table exceed
- * the hardware capacity If this error is ignored, further traffic
- * and schedule will work correctly.
- * Overscheduling does not occur when the schedule table does
- * not contain more entries that the number of free entries returned
- * by @a ixAtmdAccPortTxFreeEntriesQuery().
- * However, Disconnect attempts just after this error will fail permanently
- * with the error code @a IX_ATMDACC_RESOURCES_STILL_ALLOCATED, and it is
- * necessary to disable the port to make @a ixAtmdAccTxVcTryDisconnect()
- * successful.
- * @return @li IX_FAIL a wrong parameter is supplied, or the format of
- * the schedule table is invalid, or the port is not Enabled, or
- * an internal severe error occured. No cells is transmitted to the hardware
- *
- * @note - If the failure is linked to an overschedule of data cells
- * the result is an inconsistency in the output traffic (one or many
- * cells may be missing and the traffic contract is not respected).
- *
- */
-PUBLIC IX_STATUS ixAtmdAccPortTxProcess (IxAtmLogicalPort port,
- IxAtmScheduleTable* scheduleTablePtr);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccTxDoneDispatch (unsigned int numberOfPdusToProcess,
- unsigned int *numberOfPdusProcessedPtr)
- *
- * @brief Process a number of pending transmit done pdus from the hardware.
- *
- * As a by-product of Atm transmit operation buffers which transmission
- * is complete need to be recycled to users. This function is invoked
- * to service the oustanding list of transmitted buffers and pass them
- * to VC users.
- *
- * Users are handed back pdus by invoking the free callback registered
- * during the @a ixAtmdAccTxVcConnect() call.
- *
- * There is a single Tx done stream servicing all active Atm Tx ports
- * which can contain a maximum of 64 entries. If this stream fills port
- * transmission will stop so this function must be call sufficently
- * frequently to ensure no disruption to the transmit operation.
- *
- * This function can be used from a timer context, or can be associated
- * with a TxDone level threshold event (see @a ixAtmdAccTxDoneDispatcherRegister() ),
- * or can be used inside an active polling mechanism under user control.
- *
- * For ease of use the signature of this function is compatible with the
- * TxDone threshold event callback prototype.
- *
- * This functions can be used inside an interrupt context.
- *
- * @sa ixAtmdAccTxDoneDispatcherRegister
- * @sa IxAtmdAccTxVcBufferReturnCallback
- * @sa ixAtmdAccTxDoneLevelQuery
- *
- * @param numberOfPdusToProcess unsigned int [in] - maxiumum number of pdus to remove
- * from the TX Done queue
- * @param *numberOfPdusProcessedPtr unsigned int [out] - number of pdus removed from
- * the TX Done queue. This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS the number of pdus as indicated in
- * numberOfPdusToProcess are removed from the TX Done hardware
- * and passed to the user through the Tx Done callback registered
- * during a call to @a ixAtmdAccTxVcConnect()
- * @return @li IX_FAIL invalid parameters or numberOfPdusProcessedPtr is
- * a null pointer or some unspecified internal error occured.
- *
- */
-PUBLIC IX_STATUS
-ixAtmdAccTxDoneDispatch (unsigned int numberOfPdusToProcess,
- unsigned int *numberOfPdusProcessedPtr);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccTxDoneLevelQuery (unsigned int *numberOfPdusPtr)
- *
- * @brief Query the current number of transmit pdus ready for
- * recycling.
- *
- * This function is used to get the number of transmitted pdus which
- * the hardware is ready to hand back to user.
- *
- * This function can be used from a timer context, or can be associated
- * with a threshold event, on can be used inside an active polling
- * mechanism
- *
- * @sa ixAtmdAccTxDoneDispatch
- *
- * @param *numberOfPdusPtr unsigned int [out] - Pointer to the number of pdus transmitted
- * at the time of this function call, and ready for recycling
- * This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS numberOfPdusPtr contains the number of pdus
- * ready for recycling at the time of this function call
- *
- * @return @li IX_FAIL wrong parameter (null pointer as parameter).or
- * unspecified rocessing error occurs..The value in numberOfPdusPtr
- * is unspecified.
- *
- */
-PUBLIC IX_STATUS
-ixAtmdAccTxDoneLevelQuery (unsigned int *numberOfPdusPtr);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccTxDoneQueueSizeQuery (unsigned int *numberOfPdusPtr)
- *
- * @brief Query the TxDone queue size.
- *
- * This function is used to get the number of pdus which
- * the hardware is able to store after transmission is complete
- *
- * The returned value can be used to set a threshold and enable
- * a callback to be notified when the number of pdus is going over
- * the threshold.
- *
- * @sa ixAtmdAccTxDoneDispatcherRegister
- *
- * @param *numberOfPdusPtr unsigned int [out] - Pointer to the number of pdus the system
- * is able to queue after transmission
- *
- * @return @li IX_SUCCESS numberOfPdusPtr contains the the number of
- * pdus the system is able to queue after transmission
- * @return @li IX_FAIL wrong parameter (null pointer as parameter).or
- * unspecified rocessing error occurs..The value in numberOfPdusPtr
- * is unspecified.
- *
- * @note - This function is reentrant, doesn't use system resources
- * and can be used from an interrupt context.
- */
-PUBLIC IX_STATUS
-ixAtmdAccTxDoneQueueSizeQuery (unsigned int *numberOfPdusPtr);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccTxDoneDispatcherRegister (unsigned int numberOfPdus,
- IxAtmdAccTxDoneDispatcher notificationCallback)
- *
- * @brief Configure the Tx Done stream threshold value and register a
- * callback to handle threshold notifications.
- *
- * This function sets the threshold level in term of number of pdus at
- * which the supplied notification function should be called.
- *
- * The higher the threshold value is, the less events will be necessary
- * to process transmitted buffers.
- *
- * Transmitted buffers recycling implementation is a sytem-wide mechanism
- * and needs to be set prior any traffic is started. If this threshold
- * mechanism is not used, the user is responsible for polling the
- * transmitted buffers thanks to @a ixAtmdAccTxDoneDispatch() and
- * @a ixAtmdAccTxDoneLevelQuery() functions.
- *
- * This function should be called during system initialisation outside
- * an interrupt context
- *
- * @sa ixAtmdAccTxDoneDispatcherRegister
- * @sa ixAtmdAccTxDoneDispatch
- * @sa ixAtmdAccTxDoneLevelQuery
- *
- * @param numberOfPdus unsigned int [in] - The number of TxDone pdus which triggers the
- * callback invocation This number has to be a power of 2, one of the
- * values 0,1,2,4,8,16,32 ...
- * The maximum value cannot be more than half of the txDone queue
- * size (which can be retrieved using @a ixAtmdAccTxDoneQueueSizeQuery())
- * @param notificationCallback @ref IxAtmdAccTxDoneDispatcher [in] - The function to invoke. (This
- * parameter can be @a ixAtmdAccTxDoneDispatch()).This
- * parameter ust not be a null pointer.
- *
- * @return @li IX_SUCCESS Successful call to ixAtmdAccTxDoneDispatcherRegister
- * @return @li IX_FAIL error in the parameters:
- *
- * @note - The notificationCallback will be called exactly when the threshold level
- * will increase from (numberOfPdus) to (numberOfPdus+1)
- *
- * @note - If there is no Tx traffic, there is no guarantee that TxDone Pdus will
- * be released to the user (when txDone level is permanently under the threshold
- * level. One of the preffered way to return resources to the user is to use
- * a mix of txDone notifications, used together with a slow
- * rate timer and an exclusion mechanism protecting from re-entrancy
- *
- * @note - The TxDone threshold will only hand back buffers when the threshold level is
- * crossed. Setting this threshold to a great number reduce the interrupt rate
- * and the cpu load, but also increase the number of outstanding mbufs and has
- * a system wide impact when these mbufs are needed by other components.
- *
- */
-PUBLIC IX_STATUS ixAtmdAccTxDoneDispatcherRegister (unsigned int numberOfPdus,
- IxAtmdAccTxDoneDispatcher notificationCallback);
-
-/* ------------------------------------------------------
- Part of the IxAtmdAcc interface related to Utopia config
- ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @defgroup IxAtmdAccUtopiaCtrlAPI IXP400 ATM Driver Access (IxAtmdAcc) Utopia Control API
- *
- * @brief The public API for the IXP400 Atm Driver Control component
- *
- * IxAtmdAcc is the low level interface by which AAL PDU get
- * transmitted to,and received from the Utopia bus
- *
- * This part is related to the UTOPIA configuration.
- *
- * @{
- */
-
-/**
- *
- * @brief Utopia configuration
- *
- * This structure is used to set the Utopia parameters
- * @li contains the values of Utopia registers, to be set during initialisation
- * @li contains debug commands for NPE, to be used during development steps
- *
- * @note - the exact description of all parameters is done in the Utopia reference
- * documents.
- *
- */
-typedef struct
-{
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtTxConfig_
- * @brief Utopia Tx Config Register
- */
- struct UtTxConfig_
- {
-
- unsigned int reserved_1:1; /**< [31] These bits are always 0.*/
- unsigned int txInterface:1; /**< [30] Utopia Transmit Interface. The following encoding
- * is used to set the Utopia Transmit interface as ATM master
- * or PHY slave:
- * @li 1 - PHY
- * @li 0 - ATM
- */
- unsigned int txMode:1; /**< [29] Utopia Transmit Mode. The following encoding is used
- * to set the Utopia Transmit mode to SPHY or MPHY:
- * @li 1 - SPHY
- * @li 0 - MPHY
- */
- unsigned int txOctet:1; /**< [28] Utopia Transmit cell transfer protocol. Used to set
- * the Utopia cell transfer protocol to Octet-level handshaking.
- * Note this is only applicable in SPHY mode.
- * @li 1 - Octet-handshaking enabled
- * @li 0 - Cell-handshaking enabled
- */
- unsigned int txParity:1; /**< [27] Utopia Transmit parity enabled when set. TxEvenParity
- * defines the parity format odd/even.
- * @li 1 - Enable Parity generation.
- * @li 0 - ut_op_prty held low.
- */
- unsigned int txEvenParity:1; /**< [26] Utopia Transmit Parity Mode
- * @li 1 - Even Parity Generated.
- * @li 0 - Odd Parity Generated.
- */
- unsigned int txHEC:1; /**< [25] Header Error Check Insertion Mode. Specifies if the transmit
- * cell header check byte is calculated and inserted when set.
- * @li 1 - Generate HEC.
- * @li 0 - Disable HEC generation.
- */
- unsigned int txCOSET:1; /**< [24] If enabled the HEC is Exclusive-OR'ed with the value 0x55 before
- * being presented on the Utopia bus.
- * @li 1 - Enable HEC ExOR with value 0x55
- * @li 0 - Use generated HEC value.
- */
-
- unsigned int reserved_2:1; /**< [23] These bits are always 0
- */
- unsigned int txCellSize:7; /**< [22:16] Transmit expected cell size. Configures the cell size
- * for the transmit module: Values between 52-64 are valid.
- */
- unsigned int reserved_3:3; /**< [15:13] These bits are always 0 */
- unsigned int txAddrRange:5; /**< [12:8] When configured as an ATM master in MPHY mode this
- * register specifies the upper limit of the PHY polling logical
- * range. The number of active PHYs are TxAddrRange + 1.
- */
- unsigned int reserved_4:3; /**< [7:5] These bits are always 0 */
- unsigned int txPHYAddr:5; /**< [4:0] When configured as a slave in an MPHY system this register
- * specifies the physical address of the PHY.
- */
- }
-
- utTxConfig; /**< Tx config Utopia register */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtTxStatsConfig_
- * @brief Utopia Tx stats Register
- */
- struct UtTxStatsConfig_
- {
-
- unsigned int vpi:12; /**< [31:20] ATM VPI [11:0] OR GFC [3:0] and VPI [7:0]
- @li Note: if VCStatsTxGFC is set to 0 the GFC field is ignored in test. */
-
- unsigned int vci:16; /**< [19:4] ATM VCI [15:0] or PHY Address[4] */
-
- unsigned int pti:3; /**< [3:1] ATM PTI [2:0] or PHY Address[3:1]
- @li Note: if VCStatsTxPTI is set to 0 the PTI field is ignored in test.
- @li Note: if VCStatsTxEnb is set to 0 only the transmit PHY port
- address as defined by this register is used for ATM statistics [4:0]. */
-
- unsigned int clp:1; /**< [0] ATM CLP or PHY Address [0]
- @li Note: if VCStatsTxCLP is set to 0 the CLP field is ignored in test.
- @li Note: if VCStatsTxEnb is set to 0 only the transmit PHY port
- address as defined by this register is used for ATM statistics [4:0]. */
- }
-
- utTxStatsConfig; /**< Tx stats config Utopia register */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtTxDefineIdle_
- * @brief Utopia Tx idle cells Register
- */
- struct UtTxDefineIdle_
- {
-
- unsigned int vpi:12; /**< [31:20] ATM VPI [11:0] OR GFC [3:0] and VPI [7:0]
- @li Note: if VCIdleTxGFC is set to 0 the GFC field is ignored in test. */
-
- unsigned int vci:16; /**< [19:4] ATM VCI [15:0] */
-
- unsigned int pti:3; /**< [3:1] ATM PTI PTI [2:0]
- @li Note: if VCIdleTxPTI is set to 0 the PTI field is ignored in test.*/
-
- unsigned int clp:1; /**< [0] ATM CLP [0]
- @li Note: if VCIdleTxCLP is set to 0 the CLP field is ignored in test.*/
- }
-
- utTxDefineIdle; /**< Tx idle cell config Utopia register */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtTxEnableFields_
- * @brief Utopia Tx ienable fields Register
- */
- struct UtTxEnableFields_
- {
-
- unsigned int defineTxIdleGFC:1; /**< [31] This register is used to include or exclude the GFC
- field of the ATM header when testing for Idle cells.
- @li 1 - GFC field is valid.
- @li 0 - GFC field ignored.*/
-
- unsigned int defineTxIdlePTI:1; /**< [30] This register is used to include or exclude the PTI
- field of the ATM header when testing for Idle cells.
- @li 1 - PTI field is valid
- @li 0 - PTI field ignored.*/
-
- unsigned int defineTxIdleCLP:1; /**< [29] This register is used to include or
- exclude the CLP field of the ATM header when testing for Idle cells.
- @li 1 - CLP field is valid.
- @li 0 - CLP field ignored. */
-
- unsigned int phyStatsTxEnb:1; /**< [28] This register is used to enable or disable ATM
- statistics gathering based on the specified PHY address as defined
- in TxStatsConfig register.
- @li 1 - Enable statistics for specified transmit PHY address.
- @li 0 - Disable statistics for specified transmit PHY address. */
-
- unsigned int vcStatsTxEnb:1; /**< [27] This register is used to change the ATM
- statistics-gathering mode from the specified logical PHY address
- to a specific VPI/VCI address.
- @li 1 - Enable statistics for specified VPI/VCI address.
- @li 0 - Disable statistics for specified VPI/VCI address */
-
- unsigned int vcStatsTxGFC:1; /**< [26] This register is used to include or exclude the GFC
- field of the ATM header when ATM VPI/VCI statistics are enabled.
- GFC is only available at the UNI and uses the first 4-bits of
- the VPI field.
- @li 1 - GFC field is valid
- @li 0 - GFC field ignored.*/
-
- unsigned int vcStatsTxPTI:1; /**< [25] This register is used to include or exclude the PTI
- field of the ATM header when ATM VPI/VCI statistics are enabled.
- @li 1 - PTI field is valid
- @li 0 - PTI field ignored.*/
-
- unsigned int vcStatsTxCLP:1; /**< [24] This register is used to include or exclude the CLP
- field of the ATM header when ATM VPI/VCI statistics are enabled.
- @li 1 - CLP field is valid
- @li 0 - CLP field ignored. */
-
- unsigned int reserved_1:3; /**< [23-21] These bits are always 0 */
-
- unsigned int txPollStsInt:1; /**< [20] Enable the assertion of the ucp_tx_poll_sts condition
- where there is a change in polling status.
- @li 1 - ucp_tx_poll_sts asserted whenever there is a change in status
- @li 0 - ucp_tx_poll_sts asserted if ANY transmit PHY is available
- */
- unsigned int txCellOvrInt:1; /**< [19] Enable TxCellCount overflow CBI Transmit Status condition
- assertion.
- @li 1 - If TxCellCountOvr is set assert the Transmit Status Condition.
- @li 0 - No CBI Transmit Status condition assertion */
-
- unsigned int txIdleCellOvrInt:1; /**< [18] Enable TxIdleCellCount overflow Transmit Status Condition
- @li 1 - If TxIdleCellCountOvr is set assert the Transmit Status Condition
- @li 0 - No CBI Transmit Status condition assertion..*/
-
- unsigned int enbIdleCellCnt:1; /**< [17] Enable Transmit Idle Cell Count.
- @li 1 - Enable count of Idle cells transmitted.
- @li 0 - No count is maintained. */
-
- unsigned int enbTxCellCnt:1; /**< [16] Enable Transmit Valid Cell Count of non-idle/non-error cells
- @li 1 - Enable count of valid cells transmitted- non-idle/non-error
- @li 0 - No count is maintained.*/
-
- unsigned int reserved_2:16; /**< [15:0] These bits are always 0 */
- } utTxEnableFields; /**< Tx enable Utopia register */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtTxTransTable0_
- * @brief Utopia Tx translation table Register
- */
- struct UtTxTransTable0_
- {
-
- unsigned int phy0:5; /**< [31-27] Tx Mapping value of logical phy 0 */
-
- unsigned int phy1:5; /**< [26-22] Tx Mapping value of logical phy 1 */
-
- unsigned int phy2:5; /**< [21-17] Tx Mapping value of logical phy 2 */
-
- unsigned int reserved_1:1; /**< [16] These bits are always 0.*/
-
- unsigned int phy3:5; /**< [15-11] Tx Mapping value of logical phy 3 */
-
- unsigned int phy4:5; /**< [10-6] Tx Mapping value of logical phy 4 */
-
- unsigned int phy5:5; /**< [5-1] Tx Mapping value of logical phy 5 */
-
- unsigned int reserved_2:1; /**< [0] These bits are always 0 */
- } utTxTransTable0; /**< Tx translation table */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtTxTransTable1_
- * @brief Utopia Tx translation table Register
- */
- struct UtTxTransTable1_
- {
-
- unsigned int phy6:5; /**< [31-27] Tx Mapping value of logical phy 6 */
-
- unsigned int phy7:5; /**< [26-22] Tx Mapping value of logical phy 7 */
-
- unsigned int phy8:5; /**< [21-17] Tx Mapping value of logical phy 8 */
-
- unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */
-
- unsigned int phy9:5; /**< [15-11] Tx Mapping value of logical phy 3 */
-
- unsigned int phy10:5; /**< [10-6] Tx Mapping value of logical phy 4 */
-
- unsigned int phy11:5; /**< [5-1] Tx Mapping value of logical phy 5 */
-
- unsigned int reserved_2:1; /**< [0] These bits are always 0 */
- } utTxTransTable1; /**< Tx translation table */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtTxTransTable2_
- * @brief Utopia Tx translation table Register
- */
- struct UtTxTransTable2_
- {
-
- unsigned int phy12:5; /**< [31-27] Tx Mapping value of logical phy 6 */
-
- unsigned int phy13:5; /**< [26-22] Tx Mapping value of logical phy 7 */
-
- unsigned int phy14:5; /**< [21-17] Tx Mapping value of logical phy 8 */
-
- unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */
-
- unsigned int phy15:5; /**< [15-11] Tx Mapping value of logical phy 3 */
-
- unsigned int phy16:5; /**< [10-6] Tx Mapping value of logical phy 4 */
-
- unsigned int phy17:5; /**< [5-1] Tx Mapping value of logical phy 5 */
-
- unsigned int reserved_2:1; /**< [0] These bits are always 0 */
- } utTxTransTable2; /**< Tx translation table */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtTxTransTable3_
- * @brief Utopia Tx translation table Register
- */
- struct UtTxTransTable3_
- {
-
- unsigned int phy18:5; /**< [31-27] Tx Mapping value of logical phy 6 */
-
- unsigned int phy19:5; /**< [26-22] Tx Mapping value of logical phy 7 */
-
- unsigned int phy20:5; /**< [21-17] Tx Mapping value of logical phy 8 */
-
- unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */
-
- unsigned int phy21:5; /**< [15-11] Tx Mapping value of logical phy 3 */
-
- unsigned int phy22:5; /**< [10-6] Tx Mapping value of logical phy 4 */
-
- unsigned int phy23:5; /**< [5-1] Tx Mapping value of logical phy 5 */
-
- unsigned int reserved_2:1; /**< [0] These bits are always 0 */
- } utTxTransTable3; /**< Tx translation table */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtTxTransTable4_
- * @brief Utopia Tx translation table Register
- */
- struct UtTxTransTable4_
- {
-
- unsigned int phy24:5; /**< [31-27] Tx Mapping value of logical phy 6 */
-
- unsigned int phy25:5; /**< [26-22] Tx Mapping value of logical phy 7 */
-
- unsigned int phy26:5; /**< [21-17] Tx Mapping value of logical phy 8 */
-
- unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */
-
- unsigned int phy27:5; /**< [15-11] Tx Mapping value of logical phy 3 */
-
- unsigned int phy28:5; /**< [10-6] Tx Mapping value of logical phy 4 */
-
- unsigned int phy29:5; /**< [5-1] Tx Mapping value of logical phy 5 */
-
- unsigned int reserved_2:1; /**< [0] These bits are always 0 */
- } utTxTransTable4; /**< Tx translation table */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtTxTransTable5_
- * @brief Utopia Tx translation table Register
- */
- struct UtTxTransTable5_
- {
-
- unsigned int phy30:5; /**< [31-27] Tx Mapping value of logical phy 6 */
-
- unsigned int reserved_1:27; /**< [26-0] These bits are always 0 */
-
- } utTxTransTable5; /**< Tx translation table */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtRxConfig_
- * @brief Utopia Rx config Register
- */
- struct UtRxConfig_
- {
-
- unsigned int rxInterface:1; /**< [31] Utopia Receive Interface. The following encoding is used
- to set the Utopia Receive interface as ATM master or PHY slave:
- @li 1 - PHY
- @li 0 - ATM */
-
- unsigned int rxMode:1; /**< [30] Utopia Receive Mode. The following encoding is used to set
- the Utopia Receive mode to SPHY or MPHY:
- @li 1 - SPHY
- @li 0 - MPHY */
-
- unsigned int rxOctet:1; /**< [29] Utopia Receive cell transfer protocol. Used to set the Utopia
- cell transfer protocol to Octet-level handshaking. Note this is only
- applicable in SPHY mode.
- @li 1 - Octet-handshaking enabled
- @li 0 - Cell-handshaking enabled */
-
- unsigned int rxParity:1; /**< [28] Utopia Receive Parity Checking enable.
- @li 1 - Parity checking enabled
- @li 0 - Parity checking disabled */
-
- unsigned int rxEvenParity:1;/**< [27] Utopia Receive Parity Mode
- @li 1 - Check for Even Parity
- @li 0 - Check for Odd Parity.*/
-
- unsigned int rxHEC:1; /**< [26] RxHEC Header Error Check Mode. Enables/disables cell header
- error checking on the received cell header.
- @li 1 - HEC checking enabled
- @li 0 - HEC checking disabled */
-
- unsigned int rxCOSET:1; /**< [25] If enabled the HEC is Exclusive-OR'ed with the value 0x55
- before being tested with the received HEC.
- @li 1 - Enable HEC ExOR with value 0x55.
- @li 0 - Use generated HEC value.*/
-
- unsigned int rxHECpass:1; /**< [24] Specifies if the incoming cell HEC byte should be transferred
- after optional processing to the NPE2 Coprocessor Bus Interface or
- if it should be discarded.
- @li 1 - HEC maintained 53-byte/UDC cell sent to NPE2.
- @li 0 - HEC discarded 52-byte/UDC cell sent to NPE2 coprocessor.*/
-
- unsigned int reserved_1:1; /**< [23] These bits are always 0 */
-
- unsigned int rxCellSize:7; /**< [22:16] Receive cell size. Configures the receive cell size.
- Values between 52-64 are valid */
-
- unsigned int rxHashEnbGFC:1; /**< [15] Specifies if the VPI field [11:8]/GFC field should be
- included in the Hash data input or if the bits should be padded
- with 1'b0.
- @li 1 - VPI [11:8]/GFC field valid and used in Hash residue calculation.
- @li 0 - VPI [11:8]/GFC field padded with 1'b0 */
-
- unsigned int rxPreHash:1; /**< [14] Enable Pre-hash value generation. Specifies if the
- incoming cell data should be pre-hashed to allow VPI/VCI header look-up
- in a hash table.
- @li 1 - Pre-hashing enabled
- @li 0 - Pre-hashing disabled */
-
- unsigned int reserved_2:1; /**< [13] These bits are always 0 */
-
- unsigned int rxAddrRange:5; /**< [12:8] In ATM master, MPHY mode,
- * this register specifies the upper
- * limit of the PHY polling logical range. The number of active PHYs are
- * RxAddrRange + 1.
- */
- unsigned int reserved_3:3; /**< [7-5] These bits are always 0 .*/
- unsigned int rxPHYAddr:5; /**< [4:0] When configured as a slave in an MPHY system this register
- * specifies the physical address of the PHY.
- */
- } utRxConfig; /**< Rx config Utopia register */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtRxStatsConfig_
- * @brief Utopia Rx stats config Register
- */
- struct UtRxStatsConfig_
- {
-
- unsigned int vpi:12; /**< [31:20] ATM VPI VPI [11:0] OR GFC [3:0] and VPI [7:0]
- @li Note: if VCStatsRxGFC is set to 0 the GFC field is ignored in test. */
-
- unsigned int vci:16; /**< [19:4] VCI [15:0] or PHY Address [4] */
-
- unsigned int pti:3; /**< [3:1] PTI [2:0] or or PHY Address [3:1]
- @li Note: if VCStatsRxPTI is set to 0 the PTI field is ignored in test.
- @li Note: if VCStatsRxEnb is set to 0 only the PHY port address is used
- for statistics gathering.. */
-
- unsigned int clp:1; /**< [0] CLP [0] or PHY Address [0]
- @li Note: if VCStatsRxCLP is set to 0 the CLP field is ignored in test.
- @li Note: if VCStatsRxEnb is set to 0 only the PHY port address is used
- for statistics gathering.. */
- } utRxStatsConfig; /**< Rx stats config Utopia register */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtRxDefineIdle_
- * @brief Utopia Rx idle cells config Register
- */
- struct UtRxDefineIdle_
- {
-
- unsigned int vpi:12; /**< [31:20] ATM VPI [11:0] OR GFC [3:0] and VPI [7:0]
- @li Note: if VCIdleRxGFC is set to 0 the GFC field is ignored in test. */
-
- unsigned int vci:16; /**< [19:4] ATM VCI [15:0] */
-
- unsigned int pti:3; /**< [3:1] ATM PTI PTI [2:0]
- @li Note: if VCIdleRxPTI is set to 0 the PTI field is ignored in test.*/
-
- unsigned int clp:1; /**< [0] ATM CLP [0]
- @li Note: if VCIdleRxCLP is set to 0 the CLP field is ignored in test.*/
- } utRxDefineIdle; /**< Rx idle cell config Utopia register */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtRxEnableFields_
- * @brief Utopia Rx enable Register
- */
- struct UtRxEnableFields_
- {
-
- unsigned int defineRxIdleGFC:1;/**< [31] This register is used to include or exclude the GFC
- field of the ATM header when testing for Idle cells.
- @li 1 - GFC field is valid.
- @li 0 - GFC field ignored.*/
-
- unsigned int defineRxIdlePTI:1;/**< [30] This register is used to include or exclude the PTI
- field of the ATM header when testing for Idle cells.
- @li 1 - PTI field is valid.
- @li 0 - PTI field ignored.*/
-
- unsigned int defineRxIdleCLP:1;/**< [29] This register is used to include or exclude the CLP
- field of the ATM header when testing for Idle cells.
- @li 1 - CLP field is valid.
- @li 0 - CLP field ignored.*/
-
- unsigned int phyStatsRxEnb:1;/**< [28] This register is used to enable or disable ATM statistics
- gathering based on the specified PHY address as defined in RxStatsConfig
- register.
- @li 1 - Enable statistics for specified receive PHY address.
- @li 0 - Disable statistics for specified receive PHY address.*/
-
- unsigned int vcStatsRxEnb:1;/**< [27] This register is used to enable or disable ATM statistics
- gathering based on a specific VPI/VCI address.
- @li 1 - Enable statistics for specified VPI/VCI address.
- @li 0 - Disable statistics for specified VPI/VCI address.*/
-
- unsigned int vcStatsRxGFC:1;/**< [26] This register is used to include or exclude the GFC field
- of the ATM header when ATM VPI/VCI statistics are enabled. GFC is only
- available at the UNI and uses the first 4-bits of the VPI field.
- @li 1 - GFC field is valid.
- @li 0 - GFC field ignored. */
-
- unsigned int vcStatsRxPTI:1;/**< [25] This register is used to include or exclude the PTI field
- of the ATM header when ATM VPI/VCI statistics are enabled.
- @li 1 - PTI field is valid.
- @li 0 - PTI field ignored.*/
-
- unsigned int vcStatsRxCLP:1;/**< [24] This register is used to include or exclude the CLP field
- of the ATM header when ATM VPI/VCI statistics are enabled.
- @li 1 - CLP field is valid.
- @li 0 - CLP field ignored. */
-
- unsigned int discardHecErr:1;/**< [23] Discard cells with an invalid HEC.
- @li 1 - Discard cells with HEC errors
- @li 0 - Cells with HEC errors are passed */
-
- unsigned int discardParErr:1;/**< [22] Discard cells containing parity errors.
- @li 1 - Discard cells with parity errors
- @li 0 - Cells with parity errors are passed */
-
- unsigned int discardIdle:1; /**< [21] Discard Idle Cells based on DefineIdle register values
- @li 1 - Discard IDLE cells
- @li 0 - IDLE cells passed */
-
- unsigned int enbHecErrCnt:1;/**< [20] Enable Receive HEC Error Count.
- @li 1 - Enable count of received cells containing HEC errors
- @li 0 - No count is maintained. */
-
- unsigned int enbParErrCnt:1;/**< [19] Enable Parity Error Count
- @li 1 - Enable count of received cells containing Parity errors
- @li 0 - No count is maintained. */
-
- unsigned int enbIdleCellCnt:1;/**< [18] Enable Receive Idle Cell Count.
- @li 1 - Enable count of Idle cells received.
- @li 0 - No count is maintained.*/
-
- unsigned int enbSizeErrCnt:1;/**< [17] Enable Receive Size Error Count.
- @li 1 - Enable count of received cells of incorrect size
- @li 0 - No count is maintained. */
-
- unsigned int enbRxCellCnt:1;/**< [16] Enable Receive Valid Cell Count of non-idle/non-error cells.
- @li 1 - Enable count of valid cells received - non-idle/non-error
- @li 0 - No count is maintained. */
-
- unsigned int reserved_1:3; /**< [15:13] These bits are always 0 */
-
- unsigned int rxCellOvrInt:1; /**< [12] Enable CBI Utopia Receive Status Condition if the RxCellCount
- register overflows.
- @li 1 - CBI Receive Status asserted.
- @li 0 - No CBI Receive Status asserted.*/
-
- unsigned int invalidHecOvrInt:1; /**< [11] Enable CBI Receive Status Condition if the InvalidHecCount
- register overflows.
- @li 1 - CBI Receive Condition asserted.
- @li 0 - No CBI Receive Condition asserted */
-
- unsigned int invalidParOvrInt:1; /**< [10] Enable CBI Receive Status Condition if the InvalidParCount
- register overflows
- @li 1 - CBI Receive Condition asserted.
- @li 0 - No CBI Receive Condition asserted */
-
- unsigned int invalidSizeOvrInt:1; /**< [9] Enable CBI Receive Status Condition if the InvalidSizeCount
- register overflows.
- @li 1 - CBI Receive Status Condition asserted.
- @li 0 - No CBI Receive Status asserted */
-
- unsigned int rxIdleOvrInt:1; /**< [8] Enable CBI Receive Status Condition if the RxIdleCount overflows.
- @li 1 - CBI Receive Condition asserted.
- @li 0 - No CBI Receive Condition asserted */
-
- unsigned int reserved_2:3; /**< [7:5] These bits are always 0 */
-
- unsigned int rxAddrMask:5; /**< [4:0] This register is used as a mask to allow the user to increase
- the PHY receive address range. The register should be programmed with
- the address-range limit, i.e. if set to 0x3 the address range increases
- to a maximum of 4 addresses. */
- } utRxEnableFields; /**< Rx enable Utopia register */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtRxTransTable0_
- * @brief Utopia Rx translation table Register
- */
- struct UtRxTransTable0_
- {
-
- unsigned int phy0:5; /**< [31-27] Rx Mapping value of logical phy 0 */
-
- unsigned int phy1:5; /**< [26-22] Rx Mapping value of logical phy 1 */
-
- unsigned int phy2:5; /**< [21-17] Rx Mapping value of logical phy 2 */
-
- unsigned int reserved_1:1; /**< [16] These bits are always 0 */
-
- unsigned int phy3:5; /**< [15-11] Rx Mapping value of logical phy 3 */
-
- unsigned int phy4:5; /**< [10-6] Rx Mapping value of logical phy 4 */
-
- unsigned int phy5:5; /**< [5-1] Rx Mapping value of logical phy 5 */
-
- unsigned int reserved_2:1; /**< [0] These bits are always 0 */
- }
-
- utRxTransTable0; /**< Rx translation table */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtRxTransTable1_
- * @brief Utopia Rx translation table Register
- */
- struct UtRxTransTable1_
- {
-
- unsigned int phy6:5; /**< [31-27] Rx Mapping value of logical phy 6 */
-
- unsigned int phy7:5; /**< [26-22] Rx Mapping value of logical phy 7 */
-
- unsigned int phy8:5; /**< [21-17] Rx Mapping value of logical phy 8 */
-
- unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */
-
- unsigned int phy9:5; /**< [15-11] Rx Mapping value of logical phy 3 */
-
- unsigned int phy10:5; /**< [10-6] Rx Mapping value of logical phy 4 */
-
- unsigned int phy11:5; /**< [5-1] Rx Mapping value of logical phy 5 */
-
- unsigned int reserved_2:1; /**< [0] These bits are always 0 */
- }
-
- utRxTransTable1; /**< Rx translation table */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtRxTransTable2_
- * @brief Utopia Rx translation table Register
- */
- struct UtRxTransTable2_
- {
-
- unsigned int phy12:5; /**< [31-27] Rx Mapping value of logical phy 6 */
-
- unsigned int phy13:5; /**< [26-22] Rx Mapping value of logical phy 7 */
-
- unsigned int phy14:5; /**< [21-17] Rx Mapping value of logical phy 8 */
-
- unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */
-
- unsigned int phy15:5; /**< [15-11] Rx Mapping value of logical phy 3 */
-
- unsigned int phy16:5; /**< [10-6] Rx Mapping value of logical phy 4 */
-
- unsigned int phy17:5; /**< [5-1] Rx Mapping value of logical phy 5 */
-
- unsigned int reserved_2:1; /**< [0] These bits are always 0 */
- } utRxTransTable2; /**< Rx translation table */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtRxTransTable3_
- * @brief Utopia Rx translation table Register
- */
- struct UtRxTransTable3_
- {
-
- unsigned int phy18:5; /**< [31-27] Rx Mapping value of logical phy 6 */
-
- unsigned int phy19:5; /**< [26-22] Rx Mapping value of logical phy 7 */
-
- unsigned int phy20:5; /**< [21-17] Rx Mapping value of logical phy 8 */
-
- unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */
-
- unsigned int phy21:5; /**< [15-11] Rx Mapping value of logical phy 3 */
-
- unsigned int phy22:5; /**< [10-6] Rx Mapping value of logical phy 4 */
-
- unsigned int phy23:5; /**< [5-1] Rx Mapping value of logical phy 5 */
-
- unsigned int reserved_2:1; /**< [0] These bits are always 0 */
- } utRxTransTable3; /**< Rx translation table */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtRxTransTable4_
- * @brief Utopia Rx translation table Register
- */
- struct UtRxTransTable4_
- {
-
- unsigned int phy24:5; /**< [31-27] Rx Mapping value of logical phy 6 */
-
- unsigned int phy25:5; /**< [26-22] Rx Mapping value of logical phy 7 */
-
- unsigned int phy26:5; /**< [21-17] Rx Mapping value of logical phy 8 */
-
- unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */
-
- unsigned int phy27:5; /**< [15-11] Rx Mapping value of logical phy 3 */
-
- unsigned int phy28:5; /**< [10-6] Rx Mapping value of logical phy 4 */
-
- unsigned int phy29:5; /**< [5-1] Rx Mapping value of logical phy 5 */
-
- unsigned int reserved_2:1; /**< [0] These bits are always 0 */
- } utRxTransTable4; /**< Rx translation table */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtRxTransTable5_
- * @brief Utopia Rx translation table Register
- */
- struct UtRxTransTable5_
- {
-
- unsigned int phy30:5; /**< [31-27] Rx Mapping value of logical phy 6 */
-
- unsigned int reserved_1:27; /**< [26-0] These bits are always 0 */
-
- } utRxTransTable5; /**< Rx translation table */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtSysConfig_
- * @brief NPE setup Register
- */
- struct UtSysConfig_
- {
-
- unsigned int reserved_1:2; /**< [31-30] These bits are always 0 */
- unsigned int txEnbFSM:1; /**< [29] Enables the operation ofthe Utopia Transmit FSM
- * @li 1 - FSM enabled
- * @li 0 - FSM inactive
- */
- unsigned int rxEnbFSM:1; /**< [28] Enables the operation ofthe Utopia Revieve FSM
- * @li 1 - FSM enabled
- * @li 0 - FSM inactive
- */
- unsigned int disablePins:1; /**< [27] Disable Utopia interface I/O pins forcing the signals to an
- * inactive state. Note that this bit is set on reset and must be
- * de-asserted
- * @li 0 - Normal data transfer
- * @li 1 - Utopia interface pins are forced inactive
- */
- unsigned int tstLoop:1; /**< [26] Test Loop Back Enable.
- * @li Note: For loop back to function RxMode and Tx Mode must both be set
- * to single PHY mode.
- * @li 0 - Loop back
- * @li 1 - Normal operating mode
- */
-
- unsigned int txReset:1; /**< [25] Resets the Utopia Coprocessor transmit module to a known state.
- * @li Note: All transmit configuration and status registers will be reset
- * to their reset values.
- * @li 0 - Normal operating mode
- * @li 1 - Reset transmit modules
- */
-
- unsigned int rxReset:1; /**< [24] Resets the Utopia Coprocessor receive module to a known state.
- * @li Note: All receive configuration and status registers will be reset
- * to their reset values.
- * @li 0 - Normal operating mode
- * @li 1 - Reset receive modules
- */
-
- unsigned int reserved_2:24; /**< [23-0] These bits are always 0 */
- } utSysConfig; /**< NPE debug config */
-
-}
-IxAtmdAccUtopiaConfig;
-
-/**
-*
-* @brief Utopia status
-*
-* This structure is used to set/get the Utopia status parameters
-* @li contains debug cell counters, to be accessed during a read operation
-*
-* @note - the exact description of all parameters is done in the Utopia reference
-* documents.
-*
-*/
-typedef struct
-{
-
- unsigned int utTxCellCount; /**< count of cells transmitted */
-
- unsigned int utTxIdleCellCount; /**< count of idle cells transmitted */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtTxCellConditionStatus_
- * @brief Utopia Tx Status Register
- */
- struct UtTxCellConditionStatus_
- {
-
- unsigned int reserved_1:2; /**< [31:30] These bits are always 0 */
- unsigned int txFIFO2Underflow:1; /**< [29] This bit is set if 64-byte
- * Transmit FIFO2 indicates a FIFO underflow
- * error condition.
- */
- unsigned int txFIFO1Underflow:1; /**< [28] This bit is set if
- * 64-byte Transmit FIFO1 indicates a FIFO
- * underflow error condition.
- */
- unsigned int txFIFO2Overflow:1; /**< [27] This bit is set if 64-byte
- * Transmit FIFO2 indicates a FIFO overflow
- * error condition.
- */
- unsigned int txFIFO1Overflow:1; /**< [26] This bit is set if 64-byte
- * Transmit FIFO1 indicates a FIFO overflow
- * error condition.
- */
- unsigned int txIdleCellCountOvr:1; /**< [25] This bit is set if the
- * TxIdleCellCount register overflows.
- */
- unsigned int txCellCountOvr:1; /**< [24] This bit is set if the
- * TxCellCount register overflows
- */
- unsigned int reserved_2:24; /**< [23:0] These bits are always 0 */
- } utTxCellConditionStatus; /**< Tx cells condition status */
-
- unsigned int utRxCellCount; /**< count of cell received */
- unsigned int utRxIdleCellCount; /**< count of idle cell received */
- unsigned int utRxInvalidHECount; /**< count of invalid cell
- * received because of HEC errors
- */
- unsigned int utRxInvalidParCount; /**< count of invalid cell received
- * because of parity errors
- */
- unsigned int utRxInvalidSizeCount; /**< count of invalid cell
- * received because of cell
- * size errors
- */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtRxCellConditionStatus_
- * @brief Utopia Rx Status Register
- */
- struct UtRxCellConditionStatus_
- {
-
- unsigned int reserved_1:3; /**< [31:29] These bits are always 0.*/
- unsigned int rxCellCountOvr:1; /**< [28] This bit is set if the RxCellCount register overflows. */
- unsigned int invalidHecCountOvr:1; /**< [27] This bit is set if the InvalidHecCount register overflows.*/
- unsigned int invalidParCountOvr:1; /**< [26] This bit is set if the InvalidParCount register overflows.*/
- unsigned int invalidSizeCountOvr:1; /**< [25] This bit is set if the InvalidSizeCount register overflows.*/
- unsigned int rxIdleCountOvr:1; /**< [24] This bit is set if the RxIdleCount register overflows.*/
- unsigned int reserved_2:4; /**< [23:20] These bits are always 0 */
- unsigned int rxFIFO2Underflow:1; /**< [19] This bit is set if 64-byte Receive FIFO2
- * indicates a FIFO underflow error condition.
- */
- unsigned int rxFIFO1Underflow:1; /**< [18] This bit is set if 64-byte Receive
- * FIFO1 indicates a FIFO underflow error condition
- . */
- unsigned int rxFIFO2Overflow:1; /**< [17] This bit is set if 64-byte Receive FIFO2
- * indicates a FIFO overflow error condition.
- */
- unsigned int rxFIFO1Overflow:1; /**< [16] This bit is set if 64-byte Receive FIFO1
- * indicates a FIFO overflow error condition.
- */
- unsigned int reserved_3:16; /**< [15:0] These bits are always 0. */
- } utRxCellConditionStatus; /**< Rx cells condition status */
-
-} IxAtmdAccUtopiaStatus;
-
-/**
- * @} defgroup IxAtmdAccUtopiaCtrlAPI
- */
-
- /**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccUtopiaConfigSet (const IxAtmdAccUtopiaConfig *
- ixAtmdAccUtopiaConfigPtr)
- *
- * @brief Send the configuration structure to the Utopia interface
- *
- * This function downloads the @a IxAtmdAccUtopiaConfig structure to
- * the Utopia and has the following effects
- * @li setup the Utopia interface
- * @li initialise the NPE
- * @li reset the Utopia cell counters and status registers to known values
- *
- * This action has to be done once at initialisation. A lock is preventing
- * the concurrent use of @a ixAtmdAccUtopiaStatusGet() and
- * @A ixAtmdAccUtopiaConfigSet()
- *
- * @param *ixAtmdAccNPEConfigPtr @ref IxAtmdAccUtopiaConfig [in] - pointer to a structure to download to
- * Utopia. This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS successful download
- * @return @li IX_FAIL error in the parameters, or configuration is not
- * complete or failed
- *
- * @sa ixAtmdAccUtopiaStatusGet
- *
- */
-PUBLIC IX_STATUS ixAtmdAccUtopiaConfigSet (const IxAtmdAccUtopiaConfig *
- ixAtmdAccUtopiaConfigPtr);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccUtopiaStatusGet (IxAtmdAccUtopiaStatus *
- ixAtmdAccUtopiaStatus)
- *
- * @brief Get the Utopia interface configuration.
- *
- * This function reads the Utopia registers and the Cell counts
- * and fills the @a IxAtmdAccUtopiaStatus structure
- *
- * A lock is preventing the concurrent
- * use of @a ixAtmdAccUtopiaStatusGet() and @A ixAtmdAccUtopiaConfigSet()
- *
- * @param ixAtmdAccUtopiaStatus @ref IxAtmdAccUtopiaStatus [out] - pointer to structure to be updated from internal
- * hardware counters. This parameter cannot be a NULL pointer.
- *
- * @return @li IX_SUCCESS successful read
- * @return @li IX_FAIL error in the parameters null pointer, or
- * configuration read is not complete or failed
- *
- * @sa ixAtmdAccUtopiaConfigSet
- *
- */
-PUBLIC IX_STATUS ixAtmdAccUtopiaStatusGet (IxAtmdAccUtopiaStatus *
- ixAtmdAccUtopiaStatus);
-
-/**
- *
- * @ingroup IxAtmdAcc
- *
- * @fn ixAtmdAccPortEnable (IxAtmLogicalPort port)
- *
- * @brief enable a PHY logical port
- *
- * This function enables the transmission over one port. It should be
- * called before accessing any resource from this port and before the
- * establishment of a VC.
- *
- * When a port is enabled, the cell transmission to the Utopia interface
- * is started. If there is no traffic already running, idle cells are
- * sent over the interface.
- *
- * This function can be called multiple times.
- *
- * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
- *
- * @return @li IX_SUCCESS enable is complete
- * @return @li IX_ATMDACC_WARNING port already enabled
- * @return @li IX_FAIL enable failed, wrong parameter, or cannot
- * initialise this port (the port is maybe already in use,
- * or there is a hardware issue)
- *
- * @note - This function needs internal locks and should not be
- * called from an interrupt context
- *
- * @sa ixAtmdAccPortDisable
- *
- */
-PUBLIC IX_STATUS ixAtmdAccPortEnable (IxAtmLogicalPort port);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccPortDisable (IxAtmLogicalPort port)
- *
- * @brief disable a PHY logical port
- *
- * This function disable the transmission over one port.
- *
- * When a port is disabled, the cell transmission to the Utopia interface
- * is stopped.
- *
- * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
- *
- * @return @li IX_SUCCESS disable is complete
- * @return @li IX_ATMDACC_WARNING port already disabled
- * @return @li IX_FAIL disable failed, wrong parameter .
- *
- * @note - This function needs internal locks and should not be called
- * from an interrupt context
- *
- * @note - The response from hardware is done through the txDone mechanism
- * to ensure the synchrnisation with tx resources. Therefore, the
- * txDone mechanism needs to be serviced to make a PortDisable complete.
- *
- * @sa ixAtmdAccPortEnable
- * @sa ixAtmdAccPortDisableComplete
- * @sa ixAtmdAccTxDoneDispatch
- *
- */
-PUBLIC IX_STATUS ixAtmdAccPortDisable (IxAtmLogicalPort port);
-
-/**
-*
-* @ingroup IxAtmdAccCtrlAPI
-*
-* @fn ixAtmdAccPortDisableComplete (IxAtmLogicalPort port)
-*
-* @brief disable a PHY logical port
-*
-* This function indicates if the port disable for a port has completed. This
-* function will return true if the port has never been enabled.
-*
-* @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
-*
-* @return @li true disable is complete
-* @return @li false disable failed, wrong parameter .
-*
-* @note - This function needs internal locks and should not be called
-* from an interrupt context
-*
-* @sa ixAtmdAccPortEnable
-* @sa ixAtmdAccPortDisable
-*
-*/
-PUBLIC BOOL ixAtmdAccPortDisableComplete (IxAtmLogicalPort port);
-
-#endif /* IXATMDACCCTRL_H */
-
-/**
- * @} defgroup IxAtmdAccCtrlAPI
- */
-
-
+++ /dev/null
-/**
- * @file IxAtmm.h
- *
- * @date 3-DEC-2001
- *
- * @brief Header file for the IXP400 ATM Manager component (IxAtmm)
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-
-/**
- * @defgroup IxAtmm IXP400 ATM Manager (IxAtmm) API
- *
- * @brief IXP400 ATM Manager component Public API
- *
- * @{
- */
-
-#ifndef IXATMM_H
-#define IXATMM_H
-
-/*
- * Put the user defined include files required
- */
-#include "IxAtmSch.h"
-#include "IxOsalTypes.h"
-
-/*
- * #defines and macros used in this file.
- */
-
-/**
- * @def IX_ATMM_RET_ALREADY_INITIALIZED
- *
- * @brief Component has already been initialized
- */
-#define IX_ATMM_RET_ALREADY_INITIALIZED 2
-
-/**
- * @def IX_ATMM_RET_INVALID_PORT
- *
- * @brief Specified port does not exist or is out of range */
-#define IX_ATMM_RET_INVALID_PORT 3
-
-/**
- * @def IX_ATMM_RET_INVALID_VC_DESCRIPTOR
- *
- * @brief The VC description does not adhere to ATM standards */
-#define IX_ATMM_RET_INVALID_VC_DESCRIPTOR 4
-
-/**
- * @def IX_ATMM_RET_VC_CONFLICT
- *
- * @brief The VPI/VCI values supplied are either reserved, or they
- * conflict with a previously registered VC on this port */
-#define IX_ATMM_RET_VC_CONFLICT 5
-
-/**
- * @def IX_ATMM_RET_PORT_CAPACITY_IS_FULL
- *
- * @brief The virtual connection cannot be established on the port
- * because the remaining port capacity is not sufficient to
- * support it */
-#define IX_ATMM_RET_PORT_CAPACITY_IS_FULL 6
-
-/**
- * @def IX_ATMM_RET_NO_SUCH_VC
- *
- * @brief No registered VC, as described by the supplied VCI/VPI or
- * VC identifier values, exists on this port */
-#define IX_ATMM_RET_NO_SUCH_VC 7
-
-/**
- * @def IX_ATMM_RET_INVALID_VC_ID
- *
- * @brief The specified VC identifier is out of range. */
-#define IX_ATMM_RET_INVALID_VC_ID 8
-
-/**
- * @def IX_ATMM_RET_INVALID_PARAM_PTR
- *
- * @brief A pointer parameter was NULL. */
-#define IX_ATMM_RET_INVALID_PARAM_PTR 9
-
-/**
- * @def IX_ATMM_UTOPIA_SPHY_ADDR
- *
- * @brief The phy address when in SPHY mode */
-#define IX_ATMM_UTOPIA_SPHY_ADDR 31
-
-/**
- * @def IX_ATMM_THREAD_PRI_HIGH
- *
- * @brief The value of high priority thread */
-#define IX_ATMM_THREAD_PRI_HIGH 90
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/** @brief Definition for use in the @ref IxAtmmVc structure.
- * Indicates the direction of a VC */
-typedef enum
-{
- IX_ATMM_VC_DIRECTION_TX=0, /**< Atmm Vc direction transmit*/
- IX_ATMM_VC_DIRECTION_RX, /**< Atmm Vc direction receive*/
- IX_ATMM_VC_DIRECTION_INVALID /**< Atmm Vc direction invalid*/
-} IxAtmmVcDirection;
-
-/** @brief Definition for use with @ref IxAtmmVcChangeCallback
- * callback. Indicates that the event type represented by the
- * callback for this VC. */
-typedef enum
-{
- IX_ATMM_VC_CHANGE_EVENT_REGISTER=0, /**< Atmm Vc event register*/
- IX_ATMM_VC_CHANGE_EVENT_DEREGISTER, /**< Atmm Vc event de-register*/
- IX_ATMM_VC_CHANGE_EVENT_INVALID /**< Atmm Vc event invalid*/
-} IxAtmmVcChangeEvent;
-
-/** @brief Definitions for use with @ref ixAtmmUTOPIAInit interface to
- * indicate that UTOPIA loopback should be enabled or disabled
- * on initialisation. */
-typedef enum
-{
- IX_ATMM_UTOPIA_LOOPBACK_DISABLED=0, /**< Atmm Utopia loopback mode disabled*/
- IX_ATMM_UTOPIA_LOOPBACK_ENABLED, /**< Atmm Utopia loopback mode enabled*/
- IX_ATMM_UTOPIA_LOOPBACK_INVALID /**< Atmm Utopia loopback mode invalid*/
-} IxAtmmUtopiaLoopbackMode;
-
-/** @brief This structure describes the required attributes of a
- * virtual connection.
-*/
-typedef struct {
- unsigned vpi; /**< VPI value of this virtual connection */
- unsigned vci; /**< VCI value of this virtual connection. */
- IxAtmmVcDirection direction; /**< VC direction */
-
- /** Traffic descriptor of this virtual connection. This structure
- * is defined by the @ref IxAtmSch component. */
- IxAtmTrafficDescriptor trafficDesc;
-} IxAtmmVc;
-
-
-/** @brief Definitions for use with @ref ixAtmmUtopiaInit interface to
- * indicate that UTOPIA multi-phy/single-phy mode is used.
- */
-typedef enum
-{
- IX_ATMM_MPHY_MODE = 0, /**< Atmm phy mode mphy*/
- IX_ATMM_SPHY_MODE, /**< Atmm phy mode sphy*/
- IX_ATMM_PHY_MODE_INVALID /**< Atmm phy mode invalid*/
-} IxAtmmPhyMode;
-
-
-/** @brief Structure contains port-specific information required to
- * initialize IxAtmm, and specifically, the IXP400 UTOPIA
- * Level-2 device. */
-typedef struct {
- unsigned reserved_1:11; /**< [31:21] Should be zero */
- unsigned UtopiaTxPhyAddr:5; /**< [20:16] Address of the
- * transmit (Tx) PHY for this
- * port on the 5-bit UTOPIA
- * Level-2 address bus */
- unsigned reserved_2:11; /**< [15:5] Should be zero */
- unsigned UtopiaRxPhyAddr:5; /**< [4:0] Address of the receive
- * (Rx) PHY for this port on the
- * 5-bit UTOPIA Level-2
- * address bus */
-} IxAtmmPortCfg;
-
-/** @brief Callback type used with @ref ixAtmmVcChangeCallbackRegister interface
- * Defines a callback type which will be used to notify registered
- * users of registration/deregistration events on a particular port
- *
- * @param eventType @ref IxAtmmVcChangeEvent [in] - Event indicating
- * whether the VC supplied has been added or
- * removed
- *
- * @param port @ref IxAtmLogicalPort [in] - Specifies the port on which the event has
- * occurred
- *
- * @param vcChanged @ref IxAtmmVc* [in] - Pointer to a structure which gives
- * details of the VC which has been added
- * or removed on the port
- */
-typedef void (*IxAtmmVcChangeCallback) (IxAtmmVcChangeEvent eventType,
- IxAtmLogicalPort port,
- const IxAtmmVc* vcChanged);
-
-/*
- * Variable declarations global to this file only. Externs are followed by
- * static variables.
- */
-
-/*
- * Extern function prototypes
- */
-
-/*
- * Function declarations
- */
-
-
-/**
- * @ingroup IxAtmm
- *
- * @fn ixAtmmInit (void)
- *
- * @brief Interface to initialize the IxAtmm software component. Can
- * be called once only.
- *
- * Must be called before any other IxAtmm API is called.
- *
- * @param "none"
- *
- * @return @li IX_SUCCESS : IxAtmm has been successfully initialized.
- * Calls to other IxAtmm interfaces may now be performed.
- * @return @li IX_FAIL : IxAtmm has already been initialized.
- */
-PUBLIC IX_STATUS
-ixAtmmInit (void);
-
-/**
- * @ingroup IxAtmm
- *
- * @fn ixAtmmUtopiaInit (unsigned numPorts,
- IxAtmmPhyMode phyMode,
- IxAtmmPortCfg portCfgs[],
- IxAtmmUtopiaLoopbackMode loopbackMode)
- *
- * @brief Interface to initialize the UTOPIA Level-2 ATM coprocessor
- * for the specified number of physical ports. The function
- * must be called before the ixAtmmPortInitialize interface
- * can operate successfully.
- *
- * @param numPorts unsigned [in] - Indicates the total number of logical
- * ports that are active on the device. Up to 12 ports are
- * supported.
- *
- * @param phyMode @ref IxAtmmPhyMode [in] - Put the Utopia coprocessor in SPHY
- * or MPHY mode.
- *
- * @param portCfgs[] @ref IxAtmmPortCfg [in] - Pointer to an array of elements
- * detailing the UTOPIA specific port characteristics. The
- * length of the array must be equal to the number of ports
- * activated. ATM ports are referred to by the relevant
- * offset in this array in all subsequent IxAtmm interface
- * calls.
- *
- * @param loopbackMode @ref IxAtmmUtopiaLoopbackMode [in] - Value must be one of
- * @ref IX_ATMM_UTOPIA_LOOPBACK_ENABLED or @ref
- * IX_ATMM_UTOPIA_LOOPBACK_DISABLED indicating whether
- * loopback should be enabled on the device. Loopback can
- * only be supported on a single PHY, therefore the numPorts
- * parameter must be 1 if loopback is enabled.
- *
- * @return @li IX_SUCCESS : Indicates that the UTOPIA device has been
- * successfully initialized for the supplied ports.
- * @return @li IX_ATMM_RET_ALREADY_INITIALIZED : The UTOPIA device has
- * already been initialized.
- * @return @li IX_FAIL : The supplied parameters are invalid or have been
- * rejected by the UTOPIA-NPE device.
- *
- * @warning
- * This interface may only be called once.
- * Port identifiers are assumed to range from 0 to (numPorts - 1) in all
- * instances.
- * In all subsequent calls to interfaces supplied by IxAtmm, the specified
- * port value is expected to represent the offset in the portCfgs array
- * specified in this interface. i.e. The first port in this array will
- * subsequently be represented as port 0, the second port as port 1,
- * and so on.*/
-PUBLIC IX_STATUS
-ixAtmmUtopiaInit (unsigned numPorts,
- IxAtmmPhyMode phyMode,
- IxAtmmPortCfg portCfgs[],
- IxAtmmUtopiaLoopbackMode loopbackMode);
-
-
-/**
- * @ingroup IxAtmm
- *
- * @fn ixAtmmPortInitialize (IxAtmLogicalPort port,
- unsigned txPortRate,
- unsigned rxPortRate)
- *
- * @brief The interface is called following @ref ixAtmmUtopiaInit ()
- * and before calls to any other IxAtmm interface. It serves
- * to activate the registered ATM port with IxAtmm.
- *
- * The transmit and receive port rates are specified in bits per
- * second. This translates to ATM cells per second according to the
- * following formula: CellsPerSecond = portRate / (53*8) The
- * IXP400 device supports only 53 byte cells. The client shall make
- * sure that the off-chip physical layer device has already been
- * initialized.
- *
- * IxAtmm will configure IxAtmdAcc and IxAtmSch to enable scheduling
- * on the port.
- *
- * This interface must be called once for each active port in the
- * system. The first time the interface is invoked, it will configure
- * the mechanism by which the handling of transmit, transmit-done and
- * receive are driven with the IxAtmdAcc component.
- *
- * This function is reentrant.
- *
- * @note The minimum tx rate that will be accepted is 424 bit/s which equates
- * to 1 cell (53 bytes) per second.
- *
- * @param port @ref IxAtmLogicalPort [in] - Identifies the port which is to be
- * initialized.
- *
- * @param txPortRate unsigned [in] - Value specifies the
- * transmit port rate for this port in
- * bits/second. This value is used by the ATM Scheduler
- * component is evaluating VC access requests for the port.
- *
- * @param rxPortRate unsigned [in] - Value specifies the
- * receive port rate for this port in bits/second.
- *
- * @return @li IX_SUCCESS : The specificed ATM port has been successfully
- * initialized. IxAtmm is ready to accept VC registrations on
- * this port.
- *
- * @return @li IX_ATMM_RET_ALREADY_INITIALIZED : ixAtmmPortInitialize has
- * already been called successfully on this port. The current
- * call is rejected.
- *
- * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the
- * input is not valid. The request is rejected.
- *
- * @return @li IX_FAIL : IxAtmm could not initialize the port because the
- * inputs are not understood.
- *
- * @sa ixAtmmPortEnable, ixAtmmPortDisable
- *
- */
-PUBLIC IX_STATUS
-ixAtmmPortInitialize (IxAtmLogicalPort port,
- unsigned txPortRate,
- unsigned rxPortRate);
-
-/**
- * @ingroup IxAtmm
- *
- * @fn ixAtmmPortModify (IxAtmLogicalPort port,
- unsigned txPortRate,
- unsigned rxPortRate)
- *
- * @brief A client may call this interface to change the existing
- * port rate (expressed in bits/second) on an established ATM
- * port.
- *
- * @param port @ref IxAtmLogicalPort [in] - Identifies the port which is to be
- * initialized.
- *
- * @param txPortRate unsigned [in] - Value specifies the``
- * transmit port rate for this port in
- * bits/second. This value is used by the ATM Scheduler
- * component is evaluating VC access requests for the port.
- *
- * @param rxPortRate unsigned [in] - Value specifies the
- * receive port rate for this port in
- * bits/second.
- *
- * @return @li IX_SUCCESS : The indicated ATM port rates have been
- * successfully modified.
- *
- * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the
- * input is not valid. The request is rejected.
- *
- * @return @li IX_FAIL : IxAtmm could not update the port because the
- * inputs are not understood, or the interface was called before
- * the port was initialized. */
-PUBLIC IX_STATUS
-ixAtmmPortModify (IxAtmLogicalPort port,
- unsigned txPortRate,
- unsigned rxPortRate);
-
-/**
- * @ingroup IxAtmm
- *
- * @fn ixAtmmPortQuery (IxAtmLogicalPort port,
- unsigned *txPortRate,
- unsigned *rxPortRate);
-
- *
- * @brief The client may call this interface to request details on
- * currently registered transmit and receive rates for an ATM
- * port.
- *
- * @param port @ref IxAtmLogicalPort [in] - Value identifies the port from which the
- * rate details are requested.
- *
- * @param *txPortRate unsigned [out] - Pointer to a value
- * which will be filled with the value of the transmit port
- * rate specified in bits/second.
- *
- * @param *rxPortRate unsigned [out] - Pointer to a value
- * which will be filled with the value of the receive port
- * rate specified in bits/second.
- *
- * @return @li IX_SUCCESS : The information requested on the specified
- * port has been successfully supplied in the output.
- *
- * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the
- * input is not valid. The request is rejected.
- *
- * @return @li IX_ATMM_RET_INVALID_PARAM_PTR : A pointer parameter was
- * NULL.
- *
- * @return @li IX_FAIL : IxAtmm could not update the port because the
- * inputs are not understood, or the interface was called before
- * the port was initialized. */
-PUBLIC IX_STATUS
-ixAtmmPortQuery (IxAtmLogicalPort port,
- unsigned *txPortRate,
- unsigned *rxPortRate);
-
-/**
- * @ingroup IxAtmm
- *
- * @fn ixAtmmPortEnable(IxAtmLogicalPort port)
- *
- * @brief The client call this interface to enable transmit for an ATM
- * port. At initialisation, all the ports are disabled.
- *
- * @param port @ref IxAtmLogicalPort [in] - Value identifies the port
- *
- * @return @li IX_SUCCESS : Transmission over this port is started.
- *
- * @return @li IX_FAIL : The port parameter is not valid, or the
- * port is already enabled
- *
- * @note - When a port is disabled, Rx and Tx VC Connect requests will fail
- *
- * @note - This function uses system resources and should not be used
- * inside an interrupt context.
- *
- * @sa ixAtmmPortDisable */
-PUBLIC IX_STATUS
-ixAtmmPortEnable(IxAtmLogicalPort port);
-
-/**
- * @ingroup IxAtmm
- *
- * @fn ixAtmmPortDisable(IxAtmLogicalPort port)
- *
- * @brief The client call this interface to disable transmit for an ATM
- * port. At initialisation, all the ports are disabled.
- *
- * @param port @ref IxAtmLogicalPort [in] - Value identifies the port
- *
- * @return @li IX_SUCCESS : Transmission over this port is stopped.
- *
- * @return @li IX_FAIL : The port parameter is not valid, or the
- * port is already disabled
- *
- * @note - When a port is disabled, Rx and Tx VC Connect requests will fail
- *
- * @note - This function call does not stop RX traffic. It is supposed
- * that this function is invoked when a serious problem
- * is detected (e.g. physical layer broken). Then, the RX traffic
- * is not passing.
- *
- * @note - This function is blocking until the hw acknowledge that the
- * transmission is stopped.
- *
- * @note - This function uses system resources and should not be used
- * inside an interrupt context.
- *
- * @sa ixAtmmPortEnable */
-PUBLIC IX_STATUS
-ixAtmmPortDisable(IxAtmLogicalPort port);
-
-/**
- * @ingroup IxAtmm
- *
- * @fn ixAtmmVcRegister (IxAtmLogicalPort port,
- IxAtmmVc *vcToAdd,
- IxAtmSchedulerVcId *vcId)
- *
- * @brief This interface is used to register an ATM Virtual
- * Connection on the specified ATM port.
- *
- * Each call to this interface registers a unidirectional virtual
- * connection with the parameters specified. If a bi-directional VC
- * is needed, the function should be called twice (once for each
- * direction, Tx & Rx) where the VPI and VCI and port parameters in
- * each call are identical.
- *
- * With the addition of each new VC to a port, a series of
- * callback functions are invoked by the IxAtmm component to notify
- * possible external components of the change. The callback functions
- * are registered using the @ref ixAtmmVcChangeCallbackRegister interface.
- *
- * The IxAtmSch component is notified of the registration of transmit
- * VCs.
- *
- * @param port @ref IxAtmLogicalPort [in] - Identifies port on which the specified VC is
- * to be registered.
- *
- * @param *vcToAdd @ref IxAtmmVc [in] - Pointer to an @ref IxAtmmVc structure
- * containing a description of the VC to be registered. The
- * client shall fill the vpi, vci and direction and relevant
- * trafficDesc members of this structure before calling this
- * function.
- *
- * @param *vcId @ref IxAtmSchedulerVcId [out] - Pointer to an integer value which is filled
- * with the per-port unique identifier value for this VC.
- * This identifier will be required when a request is
- * made to deregister or change this VC. VC identifiers
- * for transmit VCs will have a value between 0-43,
- * i.e. 32 data Tx VCs + 12 OAM Tx Port VCs.
- * Receive VCs will have a value between 44-66,
- * i.e. 32 data Rx VCs + 1 OAM Rx VC.
- *
- * @return @li IX_SUCCESS : The VC has been successfully registered on
- * this port. The VC is ready for a client to configure IxAtmdAcc
- * for receive and transmit operations on the VC.
- * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the
- * input is not valid or has not been initialized. The request
- * is rejected.
- * @return @li IX_ATMM_RET_INVALID_VC_DESCRIPTOR : The descriptor
- * pointed to by vcToAdd is invalid. The registration request
- * is rejected.
- * @return @li IX_ATMM_RET_VC_CONFLICT : The VC requested conflicts with
- * reserved VPI and/or VCI values or with another VC already activated
- * on this port.
- * @return @li IX_ATMM_RET_PORT_CAPACITY_IS_FULL : The VC cannot be
- * registered in the port becuase the port capacity is
- * insufficient to support the requested ATM traffic contract.
- * The registration request is rejected.
- * @return @li IX_ATMM_RET_INVALID_PARAM_PTR : A pointer parameter was
- * NULL.
- *
- * @warning IxAtmm has no capability of signaling or negotiating a virtual
- * connection. Negotiation of the admission of the VC to the network
- * is beyond the scope of this function. This is assumed to be
- * performed by the calling client, if appropriate,
- * before or after this function is called.
- */
-PUBLIC IX_STATUS
-ixAtmmVcRegister (IxAtmLogicalPort port,
- IxAtmmVc *vcToAdd,
- IxAtmSchedulerVcId *vcId);
-
-/**
- * @ingroup IxAtmm
- *
- * @fn ixAtmmVcDeregister (IxAtmLogicalPort port, IxAtmSchedulerVcId vcId)
- *
- * @brief Function called by a client to deregister a VC from the
- * system.
- *
- * With the removal of each new VC from a port, a series of
- * registered callback functions are invoked by the IxAtmm component
- * to notify possible external components of the change. The callback
- * functions are registered using the @ref ixAtmmVcChangeCallbackRegister.
- *
- * The IxAtmSch component is notified of the removal of transmit VCs.
- *
- * @param port @ref IxAtmLogicalPort [in] - Identifies port on which the VC to be
- * removed is currently registered.
- *
- * @param vcId @ref IxAtmSchedulerVcId [in] - VC identifier value of the VC to
- * be deregistered. This value was supplied to the client when
- the VC was originally registered. This value can also be
- queried from the IxAtmm component through the @ref ixAtmmVcQuery
- * interface.
- *
- * @return @li IX_SUCCESS : The specified VC has been successfully
- * removed from this port.
- * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the
- * input is not valid or has not been initialized. The request
- * is rejected.
- * @return @li IX_FAIL : There is no registered VC associated with the
- * supplied identifier registered on this port. */
-PUBLIC IX_STATUS
-ixAtmmVcDeregister (IxAtmLogicalPort port, IxAtmSchedulerVcId vcId);
-
-/**
- * @ingroup IxAtmm
- *
- * @fn ixAtmmVcQuery (IxAtmLogicalPort port,
- unsigned vpi,
- unsigned vci,
- IxAtmmVcDirection direction,
- IxAtmSchedulerVcId *vcId,
- IxAtmmVc *vcDesc)
- *
- * @brief This interface supplies information about an active VC on a
- * particular port when supplied with the VPI, VCI and
- * direction of that VC.
- *
- * @param port @ref IxAtmLogicalPort [in] - Identifies port on which the VC to be
- * queried is currently registered.
- *
- * @param vpi unsigned [in] - ATM VPI value of the requested VC.
- *
- * @param vci unsigned [in] - ATM VCI value of the requested VC.
- *
- * @param direction @ref IxAtmmVcDirection [in] - One of @ref
- * IX_ATMM_VC_DIRECTION_TX or @ref IX_ATMM_VC_DIRECTION_RX
- * indicating the direction (Tx or Rx) of the requested VC.
- *
- * @param *vcId @ref IxAtmSchedulerVcId [out] - Pointer to an integer value which will be
- * filled with the VC identifier value for the requested
- * VC (as returned by @ref ixAtmmVcRegister), if it
- * exists on this port.
- *
- * @param *vcDesc @ref IxAtmmVc [out] - Pointer to an @ref IxAtmmVc structure
- * which will be filled with the specific details of the
- * requested VC, if it exists on this port.
- *
- * @return @li IX_SUCCESS : The specified VC has been found on this port
- * and the requested details have been returned.
- * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the
- * input is not valid or has not been initialized. The request
- * is rejected.
- * @return @li IX_ATMM_RET_NO_SUCH_VC : No VC exists on the specified
- * port which matches the search criteria (VPI, VCI, direction)
- * given. No data is returned.
- * @return @li IX_ATMM_RET_INVALID_PARAM_PTR : A pointer parameter was
- * NULL.
- *
- */
-PUBLIC IX_STATUS
-ixAtmmVcQuery (IxAtmLogicalPort port,
- unsigned vpi,
- unsigned vci,
- IxAtmmVcDirection direction,
- IxAtmSchedulerVcId *vcId,
- IxAtmmVc *vcDesc);
-
-
-/**
- * @ingroup IxAtmm
- *
- * @fn ixAtmmVcIdQuery (IxAtmLogicalPort port, IxAtmSchedulerVcId vcId, IxAtmmVc *vcDesc)
- *
- * @brief This interface supplies information about an active VC on a
- * particular port when supplied with a vcId for that VC.
- *
- * @param port @ref IxAtmLogicalPort [in] - Identifies port on which the VC to be
- * queried is currently registered.
- *
- * @param vcId @ref IxAtmSchedulerVcId [in] - Value returned by @ref ixAtmmVcRegister which
- * uniquely identifies the requested VC on this port.
- *
- * @param *vcDesc @ref IxAtmmVc [out] - Pointer to an @ref IxAtmmVc structure
- * which will be filled with the specific details of the
- * requested VC, if it exists on this port.
- *
- * @return @li IX_SUCCESS : The specified VC has been found on this port
- * and the requested details have been returned.
- * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the
- * input is not valid or has not been initialized. The request
- * is rejected.
- * @return @li IX_ATMM_RET_NO_SUCH_VC : No VC exists on the specified
- * port which matches the supplied identifier. No data is
- * returned.
- * @return @li IX_ATMM_RET_INVALID_PARAM_PTR : A pointer parameter was
- * NULL.
- */
-PUBLIC IX_STATUS
-ixAtmmVcIdQuery (IxAtmLogicalPort port, IxAtmSchedulerVcId vcId, IxAtmmVc *vcDesc);
-
-/**
- * @ingroup IxAtmm
- *
- * @fn ixAtmmVcChangeCallbackRegister (IxAtmmVcChangeCallback callback)
- *
- * @brief This interface is invoked to supply a function to IxAtmm
- * which will be called to notify the client if a new VC is
- * registered with IxAtmm or an existing VC is removed.
- *
- * The callback, when invoked, will run within the context of the call
- * to @ref ixAtmmVcRegister or @ref ixAtmmVcDeregister which caused
- * the change of state.
- *
- * A maximum of 32 calbacks may be registered in with IxAtmm.
- *
- * @param callback @ref IxAtmmVcChangeCallback [in] - Callback which complies
- * with the @ref IxAtmmVcChangeCallback definition. This
- * function will be invoked by IxAtmm with the appropiate
- * parameters for the relevant VC when any VC has been
- * registered or deregistered with IxAtmm.
- *
- * @return @li IX_SUCCESS : The specified callback has been registered
- * successfully with IxAtmm and will be invoked when appropriate.
- * @return @li IX_FAIL : Either the supplied callback is invalid, or
- * IxAtmm has already registered 32 and connot accommodate
- * any further registrations of this type. The request is
- * rejected.
- *
- * @warning The client must not call either the @ref
- * ixAtmmVcRegister or @ref ixAtmmVcDeregister interfaces
- * from within the supplied callback function. */
-PUBLIC IX_STATUS ixAtmmVcChangeCallbackRegister (IxAtmmVcChangeCallback callback);
-
-
-/**
- * @ingroup IxAtmm
- *
- * @fn ixAtmmVcChangeCallbackDeregister (IxAtmmVcChangeCallback callback)
- *
- * @brief This interface is invoked to deregister a previously supplied
- * callback function.
- *
- * @param callback @ref IxAtmmVcChangeCallback [in] - Callback which complies
- * with the @ref IxAtmmVcChangeCallback definition. This
- * function will removed from the table of callbacks.
- *
- * @return @li IX_SUCCESS : The specified callback has been deregistered
- * successfully from IxAtmm.
- * @return @li IX_FAIL : Either the supplied callback is invalid, or
- * is not currently registered with IxAtmm.
- */
-PUBLIC IX_STATUS
-ixAtmmVcChangeCallbackDeregister (IxAtmmVcChangeCallback callback);
-
-/**
- * @ingroup IxAtmm
- *
- * @fn ixAtmmUtopiaStatusShow (void)
- *
- * @brief Display utopia status counters
- *
- * @param "none"
- *
- * @return @li IX_SUCCESS : Show function was successful
- * @return @li IX_FAIL : Internal failure
- */
-PUBLIC IX_STATUS
-ixAtmmUtopiaStatusShow (void);
-
-/**
- * @ingroup IxAtmm
- *
- * @fn ixAtmmUtopiaCfgShow (void)
- *
- * @brief Display utopia information(config registers and status registers)
- *
- * @param "none"
- *
- * @return @li IX_SUCCESS : Show function was successful
- * @return @li IX_FAIL : Internal failure
- */
-PUBLIC IX_STATUS
-ixAtmmUtopiaCfgShow (void);
-
-#endif
-/* IXATMM_H */
-
-/** @} */
+++ /dev/null
-/**
- * @file IxDmaAcc.h
- *
- * @date 15 October 2002
- *
- * @brief API of the IXP400 DMA Access Driver Component (IxDma)
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/*---------------------------------------------------------------------
- Doxygen group definitions
- ---------------------------------------------------------------------*/
-
-#ifndef IXDMAACC_H
-#define IXDMAACC_H
-
-#include "IxOsal.h"
-#include "IxNpeDl.h"
-/**
- * @defgroup IxDmaTypes IXP400 DMA Types (IxDmaTypes)
- * @brief The common set of types used in the DMA component
- * @{
- */
-
-/**
- * @ingroup IxDmaTypes
- * @enum IxDmaReturnStatus
- * @brief Dma return status definitions
- */
-typedef enum
-{
- IX_DMA_SUCCESS = IX_SUCCESS, /**< DMA Transfer Success */
- IX_DMA_FAIL = IX_FAIL, /**< DMA Transfer Fail */
- IX_DMA_INVALID_TRANSFER_WIDTH, /**< Invalid transfer width */
- IX_DMA_INVALID_TRANSFER_LENGTH, /**< Invalid transfer length */
- IX_DMA_INVALID_TRANSFER_MODE, /**< Invalid transfer mode */
- IX_DMA_INVALID_ADDRESS_MODE, /**< Invalid address mode */
- IX_DMA_REQUEST_FIFO_FULL /**< DMA request queue is full */
-} IxDmaReturnStatus;
-
-/**
- * @ingroup IxDmaTypes
- * @enum IxDmaTransferMode
- * @brief Dma transfer mode definitions
- * @note Copy and byte swap, and copy and reverse modes only support multiples of word data length.
- */
-typedef enum
-{
- IX_DMA_COPY_CLEAR = 0, /**< copy and clear source*/
- IX_DMA_COPY, /**< copy */
- IX_DMA_COPY_BYTE_SWAP, /**< copy and byte swap (endian) */
- IX_DMA_COPY_REVERSE, /**< copy and reverse */
- IX_DMA_TRANSFER_MODE_INVALID /**< Invalid transfer mode */
-} IxDmaTransferMode;
-
-/**
- * @ingroup IxDmaTypes
- * @enum IxDmaAddressingMode
- * @brief Dma addressing mode definitions
- * @note Fixed source address to fixed destination address addressing mode is not supported.
- */
-typedef enum
-{
- IX_DMA_INC_SRC_INC_DST = 0, /**< Incremental source address to incremental destination address */
- IX_DMA_INC_SRC_FIX_DST, /**< Incremental source address to incremental destination address */
- IX_DMA_FIX_SRC_INC_DST, /**< Incremental source address to incremental destination address */
- IX_DMA_FIX_SRC_FIX_DST, /**< Incremental source address to incremental destination address */
- IX_DMA_ADDRESSING_MODE_INVALID /**< Invalid Addressing Mode */
-} IxDmaAddressingMode;
-
-/**
- * @ingroup IxDmaTypes
- * @enum IxDmaTransferWidth
- * @brief Dma transfer width definitions
- * @Note Fixed addresses (either source or destination) do not support burst transfer width.
- */
-typedef enum
-{
- IX_DMA_32_SRC_32_DST = 0, /**< 32-bit src to 32-bit dst */
- IX_DMA_32_SRC_16_DST, /**< 32-bit src to 16-bit dst */
- IX_DMA_32_SRC_8_DST, /**< 32-bit src to 8-bit dst */
- IX_DMA_16_SRC_32_DST, /**< 16-bit src to 32-bit dst */
- IX_DMA_16_SRC_16_DST, /**< 16-bit src to 16-bit dst */
- IX_DMA_16_SRC_8_DST, /**< 16-bit src to 8-bit dst */
- IX_DMA_8_SRC_32_DST, /**< 8-bit src to 32-bit dst */
- IX_DMA_8_SRC_16_DST, /**< 8-bit src to 16-bit dst */
- IX_DMA_8_SRC_8_DST, /**< 8-bit src to 8-bit dst */
- IX_DMA_8_SRC_BURST_DST, /**< 8-bit src to burst dst - Not supported for fixed destination address */
- IX_DMA_16_SRC_BURST_DST, /**< 16-bit src to burst dst - Not supported for fixed destination address */
- IX_DMA_32_SRC_BURST_DST, /**< 32-bit src to burst dst - Not supported for fixed destination address */
- IX_DMA_BURST_SRC_8_DST, /**< burst src to 8-bit dst - Not supported for fixed source address */
- IX_DMA_BURST_SRC_16_DST, /**< burst src to 16-bit dst - Not supported for fixed source address */
- IX_DMA_BURST_SRC_32_DST, /**< burst src to 32-bit dst - Not supported for fixed source address*/
- IX_DMA_BURST_SRC_BURST_DST, /**< burst src to burst dst - Not supported for fixed source and destination address
-*/
- IX_DMA_TRANSFER_WIDTH_INVALID /**< Invalid transfer width */
-} IxDmaTransferWidth;
-
-/**
- * @ingroup IxDmaTypes
- * @enum IxDmaNpeId
- * @brief NpeId numbers to identify NPE A, B or C
- */
-typedef enum
-{
- IX_DMA_NPEID_NPEA = 0, /**< Identifies NPE A */
- IX_DMA_NPEID_NPEB, /**< Identifies NPE B */
- IX_DMA_NPEID_NPEC, /**< Identifies NPE C */
- IX_DMA_NPEID_MAX /**< Total Number of NPEs */
-} IxDmaNpeId;
-/* @} */
-/**
- * @defgroup IxDmaAcc IXP400 DMA Access Driver (IxDmaAcc) API
- *
- * @brief The public API for the IXP400 IxDmaAcc component
- *
- * @{
- */
-
-/**
- * @ingroup IxDmaAcc
- * @brief DMA Request Id type
- */
-typedef UINT32 IxDmaAccRequestId;
-
-/**
- * @ingroup IxDmaAcc
- * @def IX_DMA_REQUEST_FULL
- * @brief DMA request queue is full
- * This constant is a return value used to tell the user that the IxDmaAcc
- * queue is full.
- *
- */
-#define IX_DMA_REQUEST_FULL 16
-
-/**
- * @ingroup IxDmaAcc
- * @brief DMA completion notification
- * This function is called to notify a client that the DMA has been completed
- * @param status @ref IxDmaReturnStatus [out] - reporting to client
- *
- */
-typedef void (*IxDmaAccDmaCompleteCallback) (IxDmaReturnStatus status);
-
-/**
- * @ingroup IxDmaAcc
- *
- * @fn ixDmaAccInit(IxNpeDlNpeId npeId)
- *
- * @brief Initialise the DMA Access component
- * This function will initialise the DMA Access component internals
- * @param npeId @ref IxNpeDlNpeId [in] - NPE to use for Dma Transfer
- * @return @li IX_SUCCESS succesfully initialised the component
- * @return @li IX_FAIL Initialisation failed for some unspecified
- * internal reason.
- */
-PUBLIC IX_STATUS
-ixDmaAccInit(IxNpeDlNpeId npeId);
-
-/**
- * @ingroup IxDmaAcc
- *
- * @fn ixDmaAccDmaTransfer(
- IxDmaAccDmaCompleteCallback callback,
- UINT32 SourceAddr,
- UINT32 DestinationAddr,
- UINT16 TransferLength,
- IxDmaTransferMode TransferMode,
- IxDmaAddressingMode AddressingMode,
- IxDmaTransferWidth TransferWidth)
- *
- * @brief Perform DMA transfer
- * This function will perform DMA transfer between devices within the
- * IXP400 memory map.
- * @note The following are restrictions for IxDmaAccDmaTransfer:
- * @li The function is non re-entrant.
- * @li The function assumes host devices are operating in big-endian mode.
- * @li Fixed address does not suport burst transfer width
- * @li Fixed source address to fixed destinatiom address mode is not suported
- * @li The incrementing source address for expansion bus will not support a burst transfer width and copy and clear mode
- *
- * @param callback @ref IxDmaAccDmaCompleteCallback [in] - function pointer to be stored and called when the DMA transfer is completed. This cannot be NULL.
- * @param SourceAddr UINT32 [in] - Starting address of DMA source. Must be a valid IXP400 memory map address.
- * @param DestinationAddr UINT32 [in] - Starting address of DMA destination. Must be a valid IXP400 memory map address.
- * @param TransferLength UINT16 [in] - The size of DMA data transfer. The range must be from 1-64Kbyte
- * @param TransferMode @ref IxDmaTransferMode [in] - The DMA transfer mode
- * @param AddressingMode @ref IxDmaAddressingMode [in] - The DMA addressing mode
- * @param TransferWidth @ref IxDmaTransferWidth [in] - The DMA transfer width
- *
- * @return @li IX_DMA_SUCCESS Notification that the DMA request is succesful
- * @return @li IX_DMA_FAIL IxDmaAcc not yet initialised or some internal error has occured
- * @return @li IX_DMA_INVALID_TRANSFER_WIDTH Transfer width is nit valid
- * @return @li IX_DMA_INVALID_TRANSFER_LENGTH Transfer length outside of valid range
- * @return @li IX_DMA_INVALID_TRANSFER_MODE Transfer Mode not valid
- * @return @li IX_DMA_REQUEST_FIFO_FULL IxDmaAcc request queue is full
- */
-PUBLIC IxDmaReturnStatus
-ixDmaAccDmaTransfer(
- IxDmaAccDmaCompleteCallback callback,
- UINT32 SourceAddr,
- UINT32 DestinationAddr,
- UINT16 TransferLength,
- IxDmaTransferMode TransferMode,
- IxDmaAddressingMode AddressingMode,
- IxDmaTransferWidth TransferWidth);
-/**
- * @ingroup IxDmaAcc
- *
- * @fn ixDmaAccShow(void)
- *
- * @brief Display some component information for debug purposes
- * Show some internal operation information relating to the DMA service.
- * At a minimum the following will show.
- * - the number of the DMA pend (in queue)
- * @param None
- * @return @li None
- */
-PUBLIC IX_STATUS
-ixDmaAccShow(void);
-
-#endif /* IXDMAACC_H */
-
+++ /dev/null
-/** @file IxEthAcc.h
- *
- * @brief this file contains the public API of @ref IxEthAcc component
- *
- * Design notes:
- * The IX_OSAL_MBUF address is to be specified on bits [31-5] and must
- * be cache aligned (bits[4-0] cleared)
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- *
- */
-
-#ifndef IxEthAcc_H
-#define IxEthAcc_H
-
-#include <IxOsBuffMgt.h>
-#include <IxTypes.h>
-
-/**
- * @defgroup IxEthAcc IXP400 Ethernet Access (IxEthAcc) API
- *
- * @brief ethAcc is a library that does provides access to the internal IXP400 10/100Bt Ethernet MACs.
- *
- *@{
- */
-
-/**
- * @ingroup IxEthAcc
- * @brief Definition of the Ethernet Access status
- */
-typedef enum /* IxEthAccStatus */
-{
- IX_ETH_ACC_SUCCESS = IX_SUCCESS, /**< return success*/
- IX_ETH_ACC_FAIL = IX_FAIL, /**< return fail*/
- IX_ETH_ACC_INVALID_PORT, /**< return invalid port*/
- IX_ETH_ACC_PORT_UNINITIALIZED, /**< return uninitialized*/
- IX_ETH_ACC_MAC_UNINITIALIZED, /**< return MAC uninitialized*/
- IX_ETH_ACC_INVALID_ARG, /**< return invalid arg*/
- IX_ETH_TX_Q_FULL, /**< return tx queue is full*/
- IX_ETH_ACC_NO_SUCH_ADDR /**< return no such address*/
-} IxEthAccStatus;
-
-/**
- * @ingroup IxEthAcc
- * @enum IxEthAccPortId
- * @brief Definition of the IXP400 Mac Ethernet device.
- */
-typedef enum
-{
- IX_ETH_PORT_1 = 0, /**< Ethernet Port 1 */
- IX_ETH_PORT_2 = 1 /**< Ethernet port 2 */
- ,IX_ETH_PORT_3 = 2 /**< Ethernet port 3 */
-} IxEthAccPortId;
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETH_ACC_NUMBER_OF_PORTS
- *
- * @brief Definition of the number of ports
- *
- */
-#ifdef __ixp46X
-#define IX_ETH_ACC_NUMBER_OF_PORTS (3)
-#else
-#define IX_ETH_ACC_NUMBER_OF_PORTS (2)
-#endif
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_IEEE803_MAC_ADDRESS_SIZE
- *
- * @brief Definition of the size of the MAC address
- *
- */
-#define IX_IEEE803_MAC_ADDRESS_SIZE (6)
-
-
-/**
- *
- * @brief Definition of the IEEE 802.3 Ethernet MAC address structure.
- *
- * The data should be packed with bytes xx:xx:xx:xx:xx:xx
- * @note
- * The data must be packed in network byte order.
- */
-typedef struct
-{
- UINT8 macAddress[IX_IEEE803_MAC_ADDRESS_SIZE]; /**< MAC address */
-} IxEthAccMacAddr;
-
-/**
- * @ingroup IxEthAcc
- * @def IX_ETH_ACC_NUM_TX_PRIORITIES
- * @brief Definition of the number of transmit priorities
- *
- */
-#define IX_ETH_ACC_NUM_TX_PRIORITIES (8)
-
-/**
- * @ingroup IxEthAcc
- * @enum IxEthAccTxPriority
- * @brief Definition of the relative priority used to transmit a frame
- *
- */
-typedef enum
-{
- IX_ETH_ACC_TX_PRIORITY_0 = 0, /**<Lowest Priority submission */
- IX_ETH_ACC_TX_PRIORITY_1 = 1, /**<submission prority of 1 (0 is lowest)*/
- IX_ETH_ACC_TX_PRIORITY_2 = 2, /**<submission prority of 2 (0 is lowest)*/
- IX_ETH_ACC_TX_PRIORITY_3 = 3, /**<submission prority of 3 (0 is lowest)*/
- IX_ETH_ACC_TX_PRIORITY_4 = 4, /**<submission prority of 4 (0 is lowest)*/
- IX_ETH_ACC_TX_PRIORITY_5 = 5, /**<submission prority of 5 (0 is lowest)*/
- IX_ETH_ACC_TX_PRIORITY_6 = 6, /**<submission prority of 6 (0 is lowest)*/
- IX_ETH_ACC_TX_PRIORITY_7 = 7, /**<Highest priority submission */
-
- IX_ETH_ACC_TX_DEFAULT_PRIORITY = IX_ETH_ACC_TX_PRIORITY_0 /**< By default send all
- packets with lowest priority */
-} IxEthAccTxPriority;
-
-/**
- * @ingroup IxEthAcc
- * @enum IxEthAccRxFrameType
- * @brief Identify the type of a frame.
- *
- * @sa IX_ETHACC_NE_FLAGS
- * @sa IX_ETHACC_NE_LINKMASK
- */
-typedef enum
-{
- IX_ETHACC_RX_LLCTYPE = 0x00, /**< 802.3 - 8802, with LLC/SNAP */
- IX_ETHACC_RX_ETHTYPE = 0x10, /**< 802.3 (Ethernet) without LLC/SNAP */
- IX_ETHACC_RX_STATYPE = 0x20, /**< 802.11, AP <=> STA */
- IX_ETHACC_RX_APTYPE = 0x30 /**< 802.11, AP <=> AP */
-} IxEthAccRxFrameType;
-
-/**
- * @ingroup IxEthAcc
- * @enum IxEthAccDuplexMode
- * @brief Definition to provision the duplex mode of the MAC.
- *
- */
-typedef enum
-{
- IX_ETH_ACC_FULL_DUPLEX, /**< Full duplex operation of the MAC */
- IX_ETH_ACC_HALF_DUPLEX /**< Half duplex operation of the MAC */
-} IxEthAccDuplexMode;
-
-
-/**
- * @ingroup IxEthAcc
- * @struct IxEthAccNe
- * @brief Definition of service-specific informations.
- *
- * This structure defines the Ethernet service-specific informations
- * and enable QoS and VLAN features.
- */
-typedef struct
-{
- UINT32 ixReserved_next; /**< reserved for chaining */
- UINT32 ixReserved_lengths; /**< reserved for buffer lengths */
- UINT32 ixReserved_data; /**< reserved for buffer pointer */
- UINT8 ixDestinationPortId; /**< Destination portId for this packet, if known by NPE */
- UINT8 ixSourcePortId; /**< Source portId for this packet */
- UINT16 ixFlags; /**< BitField of option for this frame */
- UINT8 ixQoS; /**< QoS class of the frame */
- UINT8 ixReserved; /**< reserved */
- UINT16 ixVlanTCI; /**< Vlan TCI */
- UINT8 ixDestMac[IX_IEEE803_MAC_ADDRESS_SIZE]; /**< Destination MAC address */
- UINT8 ixSourceMac[IX_IEEE803_MAC_ADDRESS_SIZE]; /**< Source MAC address */
-} IxEthAccNe;
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_PORT_UNKNOWN
- *
- * @brief Contents of the field @a IX_ETHACC_NE_DESTPORTID when no
- * destination port can be found by the NPE for this frame.
- *
- */
-#define IX_ETHACC_NE_PORT_UNKNOWN (0xff)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_DESTMAC
- *
- * @brief The location of the destination MAC address in the Mbuf header.
- *
- */
-#define IX_ETHACC_NE_DESTMAC(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixDestMac
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_SOURCEMAC
- *
- * @brief The location of the source MAC address in the Mbuf header.
- *
- */
-#define IX_ETHACC_NE_SOURCEMAC(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixSourceMac
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_VLANTCI
- *
- * @brief The VLAN Tag Control Information associated with this frame
- *
- * The VLAN Tag Control Information associated with this frame. On Rx
- * path, this field is extracted from the packet header.
- * On Tx path, the value of this field is inserted in the frame when
- * the port is configured to insert or replace vlan tags in the
- * egress frames.
- *
- * @sa IX_ETHACC_NE_FLAGS
- */
-#define IX_ETHACC_NE_VLANTCI(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixVlanTCI
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_SOURCEPORTID
- *
- * @brief The port where this frame came from.
- *
- * The port where this frame came from. This field is set on receive
- * with the port information. This field is ignored on Transmit path.
- */
-#define IX_ETHACC_NE_SOURCEPORTID(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixSourcePortId
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_DESTPORTID
- *
- * @brief The destination port where this frame should be sent.
- *
- * The destination port where this frame should be sent.
- *
- * @li In the transmit direction, this field contains the destination port
- * and is ignored unless @a IX_ETHACC_NE_FLAG_DST is set.
- *
- * @li In the receive direction, this field contains the port where the
- * destination MAC addresses has been learned. If the destination
- * MAC address is unknown, then this value is set to the reserved value
- * @a IX_ETHACC_NE_PORT_UNKNOWN
- *
- */
-#define IX_ETHACC_NE_DESTPORTID(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixDestinationPortId
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_QOS
- *
- * @brief QualityOfService class (QoS) for this received frame.
- *
- */
-#define IX_ETHACC_NE_QOS(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixQoS
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_FLAGS
- *
- * @brief Bit Mask of the different flags associated with a frame
- *
- * The flags are the bit-oring combination
- * of the following different fields :
- *
- * @li IP flag (Rx @a IX_ETHACC_NE_IPMASK)
- * @li Spanning Tree flag (Rx @a IX_ETHACC_NE_STMASK)
- * @li Link layer type (Rx and Tx @a IX_ETHACC_NE_LINKMASK)
- * @li VLAN Tagged Frame (Rx @a IX_ETHACC_NE_VLANMASK)
- * @li New source MAC address (Rx @a IX_ETHACC_NE_NEWSRCMASK)
- * @li Multicast flag (Rx @a IX_ETHACC_NE_MCASTMASK)
- * @li Broadcast flag (Rx @a IX_ETHACC_NE_BCASTMASK)
- * @li Destination port flag (Tx @a IX_ETHACC_NE_PORTMASK)
- * @li Tag/Untag Tx frame (Tx @a IX_ETHACC_NE_TAGMODEMASK)
- * @li Overwrite destination port (Tx @a IX_ETHACC_NE_PORTOVERMASK)
- * @li Filtered frame (Rx @a IX_ETHACC_NE_STMASK)
- * @li VLAN Enabled (Rx and Tx @a IX_ETHACC_NE_VLANENABLEMASK)
- */
-#define IX_ETHACC_NE_FLAGS(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixFlags
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_BCASTMASK
- *
- * @brief This mask defines if a received frame is a broadcast frame.
- *
- * This mask defines if a received frame is a broadcast frame.
- * The BCAST flag is set when the destination MAC address of
- * a frame is broadcast.
- *
- * @sa IX_ETHACC_NE_FLAGS
- *
- */
-#define IX_ETHACC_NE_BCASTMASK (0x1)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_MCASTMASK
- *
- * @brief This mask defines if a received frame is a multicast frame.
- *
- * This mask defines if a received frame is a multicast frame.
- * The MCAST flag is set when the destination MAC address of
- * a frame is multicast.
- *
- * @sa IX_ETHACC_NE_FLAGS
- *
- */
-#define IX_ETHACC_NE_MCASTMASK (0x1 << 1)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_IPMASK
- *
- * @brief This mask defines if a received frame is a IP frame.
- *
- * This mask applies to @a IX_ETHACC_NE_FLAGS and defines if a received
- * frame is a IP frame. The IP flag is set on Rx direction, depending on
- * the frame contents. The flag is set when the length/type field of a
- * received frame is 0x8000.
- *
- * @sa IX_ETHACC_NE_FLAGS
- *
- */
-#define IX_ETHACC_NE_IPMASK (0x1 << 2)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_VLANMASK
- *
- * @brief This mask defines if a received frame is VLAN tagged.
- *
- * This mask defines if a received frame is VLAN tagged.
- * When set, the Rx frame is VLAN-tagged and the tag value
- * is available thru @a IX_ETHACC_NE_VLANID.
- * Note that when sending frames which are already tagged
- * this flag should be set, to avoid inserting another VLAN tag.
- *
- * @sa IX_ETHACC_NE_FLAGS
- * @sa IX_ETHACC_NE_VLANID
- *
- */
-#define IX_ETHACC_NE_VLANMASK (0x1 << 3)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_LINKMASK
- *
- * @brief This mask is the link layer protocol indicator
- *
- * This mask applies to @a IX_ETHACC_NE_FLAGS.
- * It reflects the state of a frame as it exits an NPE on the Rx path
- * or enters an NPE on the Tx path. Its values are as follows:
- * @li 0x00 - IEEE802.3 - 8802 (Rx) / IEEE802.3 - 8802 (Tx)
- * @li 0x01 - IEEE802.3 - Ethernet (Rx) / IEEE802.3 - Ethernet (Tx)
- * @li 0x02 - IEEE802.11 AP -> STA (Rx) / IEEE802.11 STA -> AP (Tx)
- * @li 0x03 - IEEE802.11 AP -> AP (Rx) / IEEE802.11 AP->AP (Tx)
- *
- * @sa IX_ETHACC_NE_FLAGS
- *
- */
-#define IX_ETHACC_NE_LINKMASK (0x3 << 4)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_STMASK
- *
- * @brief This mask defines if a received frame is a Spanning Tree frame.
- *
- * This mask applies to @a IX_ETHACC_NE_FLAGS.
- * On rx direction, it defines if a received if frame is a Spanning Tree frame.
- * Setting this fkag on transmit direction overrides the port settings
- * regarding the VLAN options and
- *
- * @sa IX_ETHACC_NE_FLAGS
- *
- */
-#define IX_ETHACC_NE_STMASK (0x1 << 6)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_FILTERMASK
- *
- * @brief This bit indicates whether a frame has been filtered by the Rx service.
- *
- * This mask applies to @a IX_ETHACC_NE_FLAGS.
- * Certain frames, which should normally be fully filtered by the NPE to due
- * the destination MAC address being on the same segment as the Rx port are
- * still forwarded to the XScale (although the payload is invalid) in order
- * to learn the MAC address of the transmitting station, if this is unknown.
- * Normally EthAcc will filter and recycle these framess internally and no
- * frames with the FILTER bit set will be received by the client.
- *
- * @sa IX_ETHACC_NE_FLAGS
- *
- */
-#define IX_ETHACC_NE_FILTERMASK (0x1 << 7)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_PORTMASK
- *
- * @brief This mask defines the rule to transmit a frame
- *
- * This mask defines the rule to transmit a frame. When set, a frame
- * is transmitted to the destination port as set by the macro
- * @a IX_ETHACC_NE_DESTPORTID. If not set, the destination port
- * is searched using the destination MAC address.
- *
- * @note This flag is meaningful only for multiport Network Engines.
- *
- * @sa IX_ETHACC_NE_FLAGS
- * @sa IX_ETHACC_NE_DESTPORTID
- *
- */
-#define IX_ETHACC_NE_PORTOVERMASK (0x1 << 8)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_TAGMODEMASK
- *
- * @brief This mask defines the tagging rules to apply to a transmit frame.
- *
- * This mask defines the tagging rules to apply to a transmit frame
- * regardless of the default setting for a port. When used together
- * with @a IX_ETHACC_NE_TAGOVERMASK and when set, the
- * frame will be tagged prior to transmission. When not set,
- * the frame will be untagged prior to transmission. This is accomplished
- * irrespective of the Egress tagging rules, constituting a per-frame override.
- *
- * @sa IX_ETHACC_NE_FLAGS
- * @sa IX_ETHACC_NE_TAGOVERMASK
- *
- */
-#define IX_ETHACC_NE_TAGMODEMASK (0x1 << 9)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_TAGOVERMASK
- *
- * @brief This mask defines the rule to transmit a frame
- *
- * This mask defines the rule to transmit a frame. When set, the
- * default transmit rules of a port are overriden.
- * When not set, the default rules as set by @ref IxEthDB should apply.
- *
- * @sa IX_ETHACC_NE_FLAGS
- * @sa IX_ETHACC_NE_TAGMODEMASK
- *
- */
-#define IX_ETHACC_NE_TAGOVERMASK (0x1 << 10)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_VLANENABLEMASK
- *
- * @brief This mask defines if a frame is a VLAN frame or not
- *
- * When set, frames undergo normal VLAN processing on the Tx path
- * (membership filtering, tagging, tag removal etc). If this flag is
- * not set, the frame is considered to be a regular non-VLAN frame
- * and no VLAN processing will be performed.
- *
- * Note that VLAN-enabled NPE images will always set this flag in all
- * Rx frames, and images which are not VLAN enabled will clear this
- * flag for all received frames.
- *
- * @sa IX_ETHACC_NE_FLAGS
- *
- */
-#define IX_ETHACC_NE_VLANENABLEMASK (0x1 << 14)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_NEWSRCMASK
- *
- * @brief This mask defines if a received frame has been learned.
- *
- * This mask defines if the source MAC address of a frame is
- * already known. If the bit is set, the source MAC address was
- * unknown to the NPE at the time the frame was received.
- *
- * @sa IX_ETHACC_NE_FLAGS
- *
- */
-#define IX_ETHACC_NE_NEWSRCMASK (0x1 << 15)
-
-/**
- * @ingroup IxEthAcc
- *
- * @brief This defines the recommanded minimum size of MBUF's submitted
- * to the frame receive service.
- *
- */
-#define IX_ETHACC_RX_MBUF_MIN_SIZE (2048)
-
-/**
- * @ingroup IxEthAcc
- *
- * @brief This defines the highest MII address of any attached PHYs
- *
- * The maximum number for PHY address is 31, add on for range checking.
- *
- */
-#define IXP425_ETH_ACC_MII_MAX_ADDR 32
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccInit(void)
- *
- * @brief Initializes the IXP400 Ethernet Access Service.
- *
- * @li Reentrant - no
- * @li ISR Callable - no
- *
- * This should be called once per module initialization.
- * @pre
- * The NPE must first be downloaded with the required microcode which supports all
- * required features.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : Service has failed to initialize.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccInit(void);
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccUnload(void)
- *
- * @brief Unload the Ethernet Access Service.
- *
- * @li Reentrant - no
- * @li ISR Callable - no
- *
- * @return void
- *
- * <hr>
- */
-PUBLIC void ixEthAccUnload(void);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortInit( IxEthAccPortId portId)
- *
- * @brief Initializes an NPE/Ethernet MAC Port.
- *
- * The NPE/Ethernet port initialisation includes the following steps
- * @li Initialize the NPE/Ethernet MAC hardware.
- * @li Verify NPE downloaded and operational.
- * @li The NPE shall be available for usage once this API returns.
- * @li Verify that the Ethernet port is present before initializing
- *
- * @li Reentrant - no
- * @li ISR Callable - no
- *
- * This should be called once per mac device.
- * The NPE/MAC shall be in disabled state after init.
- *
- * @pre
- * The component must be initialized via @a ixEthAccInit
- * The NPE must first be downloaded with the required microcode which supports all
- * required features.
- *
- * Dependant on Services: (Must be initialized before using this service may be initialized)
- * ixNPEmh - NPE Message handling service.
- * ixQmgr - Queue Manager component.
- *
- * @param portId @ref IxEthAccPortId [in]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS: if the ethernet port is not present, a warning is issued.
- * @li @a IX_ETH_ACC_FAIL : The NPE processor has failed to initialize.
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccPortInit(IxEthAccPortId portId);
-
-
-/*************************************************************************
-
- ##### ## ##### ## ##### ## ##### # #
- # # # # # # # # # # # # # #
- # # # # # # # # # # # # ######
- # # ###### # ###### ##### ###### # # #
- # # # # # # # # # # # # #
- ##### # # # # # # # # # # #
-
-*************************************************************************/
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortTxFrameSubmit(
- IxEthAccPortId portId,
- IX_OSAL_MBUF *buffer,
- IxEthAccTxPriority priority)
- *
- * @brief This function shall be used to submit MBUFs buffers for transmission on a particular MAC device.
- *
- * When the frame is transmitted, the buffer shall be returned thru the
- * callback @a IxEthAccPortTxDoneCallback.
- *
- * In case of over-submitting, the order of the frames on the
- * network may be modified.
- *
- * Buffers shall be not queued for transmission if the port is disabled.
- * The port can be enabled using @a ixEthAccPortEnable
- *
- *
- * @li Reentrant - yes
- * @li ISR Callable - yes
- *
- *
- * @pre
- * @a ixEthAccPortTxDoneCallbackRegister must be called to register a function to allow this service to
- * return the buffer to the calling service.
- *
- * @note
- * If the buffer submit fails for any reason the user has retained ownership of the buffer.
- *
- * @param portId @ref IxEthAccPortId [in] - MAC port ID to transmit Ethernet frame on.
- * @param buffer @ref IX_OSAL_MBUF [in] - pointer to an MBUF formatted buffer. Chained buffers are supported for transmission.
- * Chained packets are not supported and the field IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR is ignored.
- * @param priority @ref IxEthAccTxPriority [in]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : Failed to queue frame for transmission.
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-
-PUBLIC IxEthAccStatus ixEthAccPortTxFrameSubmit(
- IxEthAccPortId portId,
- IX_OSAL_MBUF *buffer,
- IxEthAccTxPriority priority);
-
-/**
- * @ingroup IxEthAcc
- *
- * @brief Function prototype for Ethernet Tx Buffer Done callback. Registered
- * via @a ixEthAccTxBufferDoneCallbackRegister
- *
- * This function is called once the previously submitted buffer is no longer required by this service.
- * It may be returned upon successful transmission of the frame or during the shutdown of
- * the port prior to the transmission of a queued frame.
- * The calling of this registered function is not a guarantee of successful transmission of the buffer.
- *
- *
- * @li Reentrant - yes , The user provided function should be reentrant.
- * @li ISR Callable - yes , The user provided function must be callable from an ISR.
- *
- *
- * <b>Calling Context </b>:
- * @par
- * This callback is called in the context of the queue manager dispatch loop @a ixQmgrgrDispatcherLoopRun
- * within the @ref IxQMgrAPI component. The calling context may be from interrupt or high priority thread.
- * The decision is system specific.
- *
- * @param callbackTag UINT32 [in] - This tag is that provided when the callback was registered for a particular MAC
- * via @a ixEthAccPortTxDoneCallbackRegister. It allows the same callback to be used for multiple MACs.
- * @param mbuf @ref IX_OSAL_MBUF [in] - Pointer to the Tx mbuf descriptor.
- *
- * @return void
- *
- * @note
- * The field IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR is modified by the access layer and reset to NULL.
- *
- * <hr>
- */
-typedef void (*IxEthAccPortTxDoneCallback) ( UINT32 callbackTag, IX_OSAL_MBUF *buffer );
-
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortTxDoneCallbackRegister( IxEthAccPortId portId,
- IxEthAccPortTxDoneCallback txCallbackFn,
- UINT32 callbackTag)
- *
- * @brief Register a callback function to allow
- * the transmitted buffers to return to the user.
- *
- * This function registers the transmit buffer done function callback for a particular port.
- *
- * The registered callback function is called once the previously submitted buffer is no longer required by this service.
- * It may be returned upon successful transmission of the frame or shutdown of port prior to submission.
- * The calling of this registered function is not a guarantee of successful transmission of the buffer.
- *
- * If called several times the latest callback shall be registered for a particular port.
- *
- * @li Reentrant - yes
- * @li ISR Callable - yes
- *
- * @pre
- * The port must be initialized via @a ixEthAccPortInit
- *
- *
- * @param portId @ref IxEthAccPortId [in] - Register callback for a particular MAC device.
- * @param txCallbackFn @ref IxEthAccPortTxDoneCallback [in] - Function to be called to return transmit buffers to the user.
- * @param callbackTag UINT32 [in] - This tag shall be provided to the callback function.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- * @li @a IX_ETH_ACC_INVALID_ARG : An argument other than portId is invalid.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortTxDoneCallbackRegister(IxEthAccPortId portId,
- IxEthAccPortTxDoneCallback txCallbackFn,
- UINT32 callbackTag);
-
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @brief Function prototype for Ethernet Frame Rx callback. Registered via @a ixEthAccPortRxCallbackRegister
- *
- * It is the responsibility of the user function to free any MBUF's which it receives.
- *
- * @li Reentrant - yes , The user provided function should be reentrant.
- * @li ISR Callable - yes , The user provided function must be callable from an ISR.
- * @par
- *
- * This function dispatches frames to the user level
- * via the provided function. The invocation shall be made for each
- * frame dequeued from the Ethernet QM queue. The user is required to free any MBUF's
- * supplied via this callback. In addition the registered callback must free up MBUF's
- * from the receive free queue when the port is disabled
- *
- * If called several times the latest callback shall be registered for a particular port.
- *
- * <b>Calling Context </b>:
- * @par
- * This callback is called in the context of the queue manager dispatch loop @a ixQmgrgrDispatcherLoopRun
- * within the @ref IxQMgrAPI component. The calling context may be from interrupt or high priority thread.
- * The decision is system specific.
- *
- *
- * @param callbackTag UINT32 [in] - This tag is that provided when the callback was registered for a particular MAC
- * via @a ixEthAccPortRxCallbackRegister. It allows the same callback to be used for multiple MACs.
- * @param mbuf @ref IX_OSAL_MBUF [in] - Pointer to the Rx mbuf header. Mbufs may be chained if
- * the frame length is greater than the supplied mbuf length.
- * @param reserved [in] - deprecated parameter The information is passed
- * thru the IxEthAccNe header destination port ID field
- * (@sa IX_ETHACC_NE_DESTPORTID). For backward
- * compatibility,the value is equal to IX_ETH_DB_UNKNOWN_PORT (0xff).
- *
- * @return void
- *
- * @note
- * Buffers may not be filled up to the length supplied in
- * @a ixEthAccPortRxFreeReplenish(). The firmware fills
- * them to the previous 64 bytes boundary. The user has to be aware
- * that the length of the received mbufs may be smaller than the length
- * of the supplied mbufs.
- * The mbuf header contains the following modified field
- * @li @a IX_OSAL_MBUF_PKT_LEN is set in the header of the first mbuf and indicates
- * the total frame size
- * @li @a IX_OSAL_MBUF_MLEN is set each mbuf header and indicates the payload length
- * @li @a IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR contains a pointer to the next
- * mbuf, or NULL at the end of a chain.
- * @li @a IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR is modified. Its value is reset to NULL
- * @li @a IX_OSAL_MBUF_FLAGS contains the bit 4 set for a broadcast packet and the bit 5
- * set for a multicast packet. Other bits are unmodified.
- *
- * <hr>
- */
-typedef void (*IxEthAccPortRxCallback) (UINT32 callbackTag, IX_OSAL_MBUF *buffer, UINT32 reserved);
-
-/**
- * @ingroup IxEthAcc
- *
- * @brief Function prototype for Ethernet Frame Rx callback. Registered via @a ixEthAccPortMultiBufferRxCallbackRegister
- *
- * It is the responsibility of the user function to free any MBUF's which it receives.
- *
- * @li Reentrant - yes , The user provided function should be reentrant.
- * @li ISR Callable - yes , The user provided function must be callable from an ISR.
- * @par
- *
- * This function dispatches many frames to the user level
- * via the provided function. The invocation shall be made for multiple frames
- * dequeued from the Ethernet QM queue. The user is required to free any MBUF's
- * supplied via this callback. In addition the registered callback must free up MBUF's
- * from the receive free queue when the port is disabled
- *
- * If called several times the latest callback shall be registered for a particular port.
- *
- * <b>Calling Context </b>:
- * @par
- * This callback is called in the context of the queue manager dispatch loop @a ixQmgrDispatcherLoopRun
- * within the @ref IxQMgrAPI component. The calling context may be from interrupt or high priority thread.
- * The decision is system specific.
- *
- *
- * @param callbackTag - This tag is that provided when the callback was registered for a particular MAC
- * via @a ixEthAccPortMultiBufferRxCallbackRegister. It allows the same callback to be used for multiple MACs.
- * @param mbuf - Pointer to an array of Rx mbuf headers. Mbufs
- * may be chained if
- * the frame length is greater than the supplied mbuf length.
- * The end of the array contains a zeroed entry (NULL pointer).
- *
- * @return void
- *
- * @note The mbufs passed to this callback have the same structure than the
- * buffers passed to @a IxEthAccPortRxCallback interfac.
- *
- * @note The usage of this callback is exclusive with the usage of
- * @a ixEthAccPortRxCallbackRegister and @a IxEthAccPortRxCallback
- *
- * @sa ixEthAccPortMultiBufferRxCallbackRegister
- * @sa IxEthAccPortMultiBufferRxCallback
- * @sa ixEthAccPortRxCallbackRegister
- * @sa IxEthAccPortRxCallback
- * <hr>
- */
-
-typedef void (*IxEthAccPortMultiBufferRxCallback) (UINT32 callbackTag, IX_OSAL_MBUF **buffer);
-
-
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortRxCallbackRegister( IxEthAccPortId portId, IxEthAccPortRxCallback rxCallbackFn, UINT32 callbackTag)
- *
- * @brief Register a callback function to allow
- * the reception of frames.
- *
- * The registered callback function is called once a frame is received by this service.
- *
- * If called several times the latest callback shall be registered for a particular port.
- *
- *
- * @li Reentrant - yes
- * @li ISR Callable - yes
- *
- *
- * @param portId @ref IxEthAccPortId [in] - Register callback for a particular MAC device.
- * @param rxCallbackFn @ref IxEthAccPortRxCallback [in] - Function to be called when Ethernet frames are availble.
- * @param callbackTag UINT32 [in] - This tag shall be provided to the callback function.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- * @li @a IX_ETH_ACC_INVALID_ARG : An argument other than portId is invalid.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortRxCallbackRegister(IxEthAccPortId portId,
- IxEthAccPortRxCallback rxCallbackFn,
- UINT32 callbackTag);
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortMultiBufferRxCallbackRegister( IxEthAccPortId portId, IxEthAccPortMultiBufferRxCallback rxCallbackFn, UINT32 callbackTag)
- *
- * @brief Register a callback function to allow
- * the reception of frames.
- *
- * The registered callback function is called once a frame is
- * received by this service. If many frames are already received,
- * the function is called once.
- *
- * If called several times the latest callback shall be registered for a particular port.
- *
- * @li Reentrant - yes
- * @li ISR Callable - yes
- *
- *
- * @param portId - Register callback for a particular MAC device.
- * @param rxCallbackFn - @a IxEthAccMultiBufferRxCallbackFn - Function to be called when Ethernet frames are availble.
- * @param callbackTag - This tag shall be provided to the callback function.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- * @li @a IX_ETH_ACC_INVALID_ARG : An argument other than portId is invalid.
- *
- * @sa ixEthAccPortMultiBufferRxCallbackRegister
- * @sa IxEthAccPortMultiBufferRxCallback
- * @sa ixEthAccPortRxCallbackRegister
- * @sa IxEthAccPortRxCallback
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortMultiBufferRxCallbackRegister(IxEthAccPortId portId,
- IxEthAccPortMultiBufferRxCallback rxCallbackFn,
- UINT32 callbackTag);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortRxFreeReplenish( IxEthAccPortId portId, IX_OSAL_MBUF *buffer)
- *
- * @brief This function provides buffers for the Ethernet receive path.
- *
- * This component does not have a buffer management mechanisms built in. All Rx buffers must be supplied to it
- * via this interface.
- *
- * @li Reentrant - yes
- * @li ISR Callable - yes
- *
- * @param portId @ref IxEthAccPortId [in] - Provide buffers only to specific Rx MAC.
- * @param buffer @ref IX_OSAL_MBUF [in] - Provide an MBUF to the Ethernet receive mechanism.
- * Buffers size smaller than IX_ETHACC_RX_MBUF_MIN_SIZE may result in poor
- * performances and excessive buffer chaining. Buffers
- * larger than this size may be suitable for jumbo frames.
- * Chained packets are not supported and the field IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR must be NULL.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : Buffer has was not able to queue the
- * buffer in the receive service.
- * @li @a IX_ETH_ACC_FAIL : Buffer size is less than IX_ETHACC_RX_MBUF_MIN_SIZE
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * @note
- * If the buffer replenish operation fails it is the responsibility
- * of the user to free the buffer.
- *
- * @note
- * Sufficient buffers must be supplied to the component to maintain
- * receive throughput and avoid rx buffer underflow conditions.
- * To meet this goal, It is expected that the user preload the
- * component with a sufficent number of buffers prior to enabling the
- * NPE Ethernet receive path. The recommended minimum number of
- * buffers is 8.
- *
- * @note
- * For maximum performances, the mbuf size should be greater
- * than the maximum frame size (Ethernet header, payload and FCS) + 64.
- * Supplying smaller mbufs to the service results in mbuf
- * chaining and degraded performances. The recommended size
- * is @a IX_ETHACC_RX_MBUF_MIN_SIZE, which is
- * enough to take care of 802.3 frames and "baby jumbo" frames without
- * chaining, and "jumbo" frame within chaining.
- *
- * @note
- * Buffers may not be filled up to their length. The firware fills
- * them up to the previous 64 bytes boundary. The user has to be aware
- * that the length of the received mbufs may be smaller than the length
- * of the supplied mbufs.
- *
- * @warning This function checks the parameters if the NDEBUG
- * flag is not defined. Turning on the argument checking (disabled by
- * default) results in a lower EthAcc performance as this function
- * is part of the data path.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortRxFreeReplenish( IxEthAccPortId portId, IX_OSAL_MBUF *buffer);
-
-
-
-/***************************************************************
-
- #### #### # # ##### ##### #### #
- # # # # ## # # # # # # #
- # # # # # # # # # # # #
- # # # # # # # ##### # # #
- # # # # # ## # # # # # #
- #### #### # # # # # #### ######
-
-
- ##### # ## # # ######
- # # # # # ## # #
- # # # # # # # # #####
- ##### # ###### # # # #
- # # # # # ## #
- # ###### # # # # ######
-
-***************************************************************/
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortEnable(IxEthAccPortId portId)
- *
- * @brief This enables an Ethernet port for both Tx and Rx.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @pre The port must first be initialized via @a ixEthAccPortInit and the MAC address
- * must be set using @a ixEthAccUnicastMacAddressSet before enabling it
- * The rx and Tx Done callbacks registration via @a
- * ixEthAccPortTxDoneCallbackRegister amd @a ixEthAccPortRxCallbackRegister
- * has to be done before enabling the traffic.
- *
- * @param portId @ref IxEthAccPortId [in] - Port id to act upon.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is not initialized
- * @li @a IX_ETH_ACC_MAC_UNINITIALIZED : port MAC address is not initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccPortEnable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortDisable(IxEthAccPortId portId)
- *
- * @brief This disables an Ethernet port for both Tx and Rx.
- *
- * Free MBufs are returned to the user via the registered callback when the port is disabled
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @pre The port must be enabled with @a ixEthAccPortEnable, otherwise this
- * function has no effect
- *
- * @param portId @ref IxEthAccPortId [in] - Port id to act upon.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is not initialized
- * @li @a IX_ETH_ACC_MAC_UNINITIALIZED : port MAC address is not initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccPortDisable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortEnabledQuery(IxEthAccPortId portId, BOOL *enabled)
- *
- * @brief Get the enabled state of a port.
- *
- * @li Reentrant - yes
- * @li ISR Callable - yes
- *
- * @pre The port must first be initialized via @a ixEthAccPortInit
- *
- * @param portId @ref IxEthAccPortId [in] - Port id to act upon.
- * @param enabled BOOL [out] - location to store the state of the port
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortEnabledQuery(IxEthAccPortId portId, BOOL *enabled);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortPromiscuousModeClear(IxEthAccPortId portId)
- *
- * @brief Put the Ethernet MAC device in non-promiscuous mode.
- *
- * In non-promiscuous mode the MAC filters all frames other than
- * destination MAC address which matches the following criteria:
- * @li Unicast address provisioned via @a ixEthAccUnicastMacAddressSet
- * @li All broadcast frames.
- * @li Multicast addresses provisioned via @a ixEthAccMulticastAddressJoin
- *
- * Other functions modify the MAC filtering
- *
- * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast
- * frames are forwarded to the application
- * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the
- * effects of @a ixEthAccPortMulticastAddressJoinAll()
- * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new
- * filtering address
- * @li @a ixEthAccPortMulticastAddressJoin() - provision a new
- * filtering address
- * @li @a ixEthAccPortPromiscuousModeSet() - all frames are
- * forwarded to the application regardless of the multicast
- * address provisioned
- * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded
- * to the application following the multicast address provisioned
- *
- * In all cases, unicast and broadcast addresses are forwarded to
- * the application.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @sa ixEthAccPortPromiscuousModeSet
- *
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccPortPromiscuousModeClear(IxEthAccPortId portId);
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortPromiscuousModeSet(IxEthAccPortId portId)
- *
- * @brief Put the MAC device in promiscuous mode.
- *
- * If the device is in promiscuous mode then all all received frames shall be forwared
- * to the NPE for processing.
- *
- * Other functions modify the MAC filtering
- *
- * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast
- * frames are forwarded to the application
- * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the
- * effects of @a ixEthAccPortMulticastAddressJoinAll()
- * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new
- * filtering address
- * @li @a ixEthAccPortMulticastAddressJoin() - provision a new
- * filtering address
- * @li @a ixEthAccPortPromiscuousModeSet() - all frames are
- * forwarded to the application regardless of the multicast
- * address provisioned
- * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded
- * to the application following the multicast address provisioned
- *
- * In all cases, unicast and broadcast addresses are forwarded to
- * the application.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @sa ixEthAccPortPromiscuousModeClear
- *
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccPortPromiscuousModeSet(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortUnicastMacAddressSet( IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr)
- *
- * @brief Configure unicast MAC address for a particular port
- *
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- * @param *macAddr @ref IxEthAccMacAddr [in] - Ethernet Mac address.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccPortUnicastMacAddressSet(IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortUnicastMacAddressGet( IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr)
- *
- * @brief Get unicast MAC address for a particular MAC port
- *
- * @pre
- * The MAC address must first be set via @a ixEthAccMacPromiscuousModeSet
- * If the MAC address has not been set, the function returns a
- * IX_ETH_ACC_MAC_UNINITIALIZED status
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- * @param *macAddr @ref IxEthAccMacAddr [out] - Ethernet MAC address.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_MAC_UNINITIALIZED : port MAC address is not initialized.
- * @li @a IX_ETH_ACC_FAIL : macAddr is invalid.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortUnicastMacAddressGet(IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr);
-
-
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortMulticastAddressJoin( IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr)
- *
- * @brief Add a multicast address to the MAC address table.
- *
- * @note
- * Due to the operation of the Ethernet MAC multicast filtering mechanism, frames which do not
- * have a multicast destination address which were provisioned via this API may be forwarded
- * to the NPE's. This is a result of the hardware comparison algorithm used in the destination mac address logic
- * within the Ethernet MAC.
- *
- * See Also: IXP425 hardware development manual.
- *
- * Other functions modify the MAC filtering
- *
- * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast
- * frames are forwarded to the application
- * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the
- * effects of @a ixEthAccPortMulticastAddressJoinAll()
- * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new
- * filtering address
- * @li @a ixEthAccPortMulticastAddressJoin() - provision a new
- * filtering address
- * @li @a ixEthAccPortPromiscuousModeSet() - all frames are
- * forwarded to the application regardless of the multicast
- * address provisioned
- * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded
- * to the application following the multicast address provisioned
- *
- * In all cases, unicast and broadcast addresses are forwarded to
- * the application.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- * @param *macAddr @ref IxEthAccMacAddr [in] - Ethernet Mac address.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : Error writing to the MAC registers
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortMulticastAddressJoin(IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortMulticastAddressJoinAll( IxEthAccPortId portId)
- *
- * @brief Filter all frames with multicast dest.
- *
- * This function clears the MAC address table, and then sets
- * the MAC to forward ALL multicast frames to the NPE.
- * Specifically, it forwards all frames whose destination address
- * has the LSB of the highest byte set (01:00:00:00:00:00). This
- * bit is commonly referred to as the "multicast bit".
- * Broadcast frames will still be forwarded.
- *
- * Other functions modify the MAC filtering
- *
- * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast
- * frames are forwarded to the application
- * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the
- * effects of @a ixEthAccPortMulticastAddressJoinAll()
- * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new
- * filtering address
- * @li @a ixEthAccPortMulticastAddressJoin() - provision a new
- * filtering address
- * @li @a ixEthAccPortPromiscuousModeSet() - all frames are
- * forwarded to the application regardless of the multicast
- * address provisioned
- * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded
- * to the application following the multicast address provisioned
- *
- * In all cases, unicast and broadcast addresses are forwarded to
- * the application.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortMulticastAddressJoinAll(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortMulticastAddressLeave( IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr)
- *
- * @brief Remove a multicast address from the MAC address table.
- *
- * Other functions modify the MAC filtering
- *
- * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast
- * frames are forwarded to the application
- * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the
- * effects of @a ixEthAccPortMulticastAddressJoinAll()
- * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new
- * filtering address
- * @li @a ixEthAccPortMulticastAddressJoin() - provision a new
- * filtering address
- * @li @a ixEthAccPortPromiscuousModeSet() - all frames are
- * forwarded to the application regardless of the multicast
- * address provisioned
- * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded
- * to the application following the multicast address provisioned
- *
- * In all cases, unicast and broadcast addresses are forwarded to
- * the application.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- * @param *macAddr @ref IxEthAccMacAddr [in] - Ethernet Mac address.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_NO_SUCH_ADDR : Failed if MAC address was not in the table.
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortMulticastAddressLeave(IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortMulticastAddressLeaveAll( IxEthAccPortId portId)
- *
- * @brief This function unconfigures the multicast filtering settings
- *
- * This function first clears the MAC address table, and then sets
- * the MAC as configured by the promiscuous mode current settings.
- *
- * Other functions modify the MAC filtering
- *
- * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast
- * frames are forwarded to the application
- * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the
- * effects of @a ixEthAccPortMulticastAddressJoinAll()
- * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new
- * filtering address
- * @li @a ixEthAccPortMulticastAddressJoin() - provision a new
- * filtering address
- * @li @a ixEthAccPortPromiscuousModeSet() - all frames are
- * forwarded to the application regardless of the multicast
- * address provisioned
- * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded
- * to the application following the multicast address provisioned
- *
- * In all cases, unicast and broadcast addresses are forwarded to
- * the application.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortMulticastAddressLeaveAll(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortUnicastAddressShow(IxEthAccPortId portId)
- *
- * @brief Displays unicast MAC address
- *
- * Displays unicast address which is configured using
- * @a ixEthAccUnicastMacAddressSet. This function also displays the MAC filter used
- * to filter multicast frames.
- *
- * Other functions modify the MAC filtering
- *
- * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast
- * frames are forwarded to the application
- * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the
- * effects of @a ixEthAccPortMulticastAddressJoinAll()
- * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new
- * filtering address
- * @li @a ixEthAccPortMulticastAddressJoin() - provision a new
- * filtering address
- * @li @a ixEthAccPortPromiscuousModeSet() - all frames are
- * forwarded to the application regardless of the multicast
- * address provisioned
- * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded
- * to the application following the multicast address provisioned
- *
- * In all cases, unicast and broadcast addresses are forwarded to
- * the application.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- *
- * @return void
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccPortUnicastAddressShow(IxEthAccPortId portId);
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortMulticastAddressShow( IxEthAccPortId portId)
- *
- * @brief Displays multicast MAC address
- *
- * Displays multicast address which have been configured using @a ixEthAccMulticastAddressJoin
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- *
- * @return void
- *
- * <hr>
- */
-PUBLIC void ixEthAccPortMulticastAddressShow( IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortDuplexModeSet( IxEthAccPortId portId, IxEthAccDuplexMode mode )
- *
- * @brief Set the duplex mode for the MAC.
- *
- * Configure the IXP400 MAC to either full or half duplex.
- *
- * @note
- * The configuration should match that provisioned on the PHY.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in]
- * @param mode @ref IxEthAccDuplexMode [in]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortDuplexModeSet(IxEthAccPortId portId,IxEthAccDuplexMode mode);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortDuplexModeGet( IxEthAccPortId portId, IxEthAccDuplexMode *mode )
- *
- * @brief Get the duplex mode for the MAC.
- *
- * return the duplex configuration of the IXP400 MAC.
- *
- * @note
- * The configuration should match that provisioned on the PHY.
- * See @a ixEthAccDuplexModeSet
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in]
- * @param *mode @ref IxEthAccDuplexMode [out]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- *
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortDuplexModeGet(IxEthAccPortId portId,IxEthAccDuplexMode *mode );
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortTxFrameAppendPaddingEnable( IxEthAccPortId portId)
- *
- * @brief Enable padding bytes to be appended to runt frames submitted to
- * this port
- *
- * Enable up to 60 null-bytes padding bytes to be appended to runt frames
- * submitted to this port. This is the default behavior of the access
- * component.
- *
- * @warning Do not change this behaviour while the port is enabled.
- *
- * @note When Tx padding is enabled, Tx FCS generation is turned on
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @sa ixEthAccPortTxFrameAppendFCSDusable
- *
- * @param portId @ref IxEthAccPortId [in]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortTxFrameAppendPaddingEnable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortTxFrameAppendPaddingDisable( IxEthAccPortId portId)
- *
- * @brief Disable padding bytes to be appended to runt frames submitted to
- * this port
- *
- * Disable padding bytes to be appended to runt frames
- * submitted to this port. This is not the default behavior of the access
- * component.
- *
- * @warning Do not change this behaviour while the port is enabled.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortTxFrameAppendPaddingDisable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortTxFrameAppendFCSEnable( IxEthAccPortId portId)
- *
- * @brief Enable the appending of Ethernet FCS to all frames submitted to this port
- *
- * When enabled, the FCS is added to the submitted frames. This is the default
- * behavior of the access component.
- * Do not change this behaviour while the port is enabled.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortTxFrameAppendFCSEnable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortTxFrameAppendFCSDisable( IxEthAccPortId portId)
- *
- * @brief Disable the appending of Ethernet FCS to all frames submitted to this port.
- *
- * When disabled, the Ethernet FCS is not added to the submitted frames.
- * This is not the default
- * behavior of the access component.
- *
- * @note Since the FCS is not appended to the frame it is expected that the frame submitted to the
- * component includes a valid FCS at the end of the data, although this will not be validated.
- *
- * The component shall forward the frame to the Ethernet MAC WITHOUT modification.
- *
- * Do not change this behaviour while the port is enabled.
- *
- * @note Tx FCS append is not disabled while Tx padding is enabled.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @sa ixEthAccPortTxFrameAppendPaddingEnable
- *
- * @param portId @ref IxEthAccPortId [in]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortTxFrameAppendFCSDisable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortRxFrameAppendFCSEnable( IxEthAccPortId portId)
- *
- * @brief Forward frames with FCS included in the receive buffer.
- *
- * The FCS is not striped from the receive buffer.
- * The received frame length includes the FCS size (4 bytes). ie.
- * A minimum sized ethernet frame shall have a length of 64bytes.
- *
- * Frame FCS validity checks are still carried out on all received frames.
- *
- * This is not the default
- * behavior of the access component.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortRxFrameAppendFCSEnable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortRxFrameAppendFCSDisable( IxEthAccPortId portId)
- *
- * @brief Do not forward the FCS portion of the received Ethernet frame to the user.
- * The FCS is striped from the receive buffer.
- * The received frame length does not include the FCS size (4 bytes).
- * Frame FCS validity checks are still carried out on all received frames.
- *
- * This is the default behavior of the component.
- * Do not change this behaviour while the port is enabled.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortRxFrameAppendFCSDisable(IxEthAccPortId portId);
-
-
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @enum IxEthAccSchedulerDiscipline
- *
- * @brief Definition for the port scheduling discipline
- *
- * Select the port scheduling discipline on receive and transmit path
- * @li FIFO : No Priority : In this configuration all frames are processed
- * in the access component in the strict order in which
- * the component received them.
- * @li FIFO : Priority : This shall be a very simple priority mechanism.
- * Higher prior-ity frames shall be forwarded
- * before lower priority frames. There shall be no
- * fairness mechanisms applied across different
- * priorities. Higher priority frames could starve
- * lower priority frames indefinitely.
- */
-typedef enum
-{
- FIFO_NO_PRIORITY, /**<frames submitted with no priority*/
- FIFO_PRIORITY /**<higher prority frames submitted before lower priority*/
-}IxEthAccSchedulerDiscipline;
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IxEthAccTxSchedulerDiscipline
- *
- * @brief Deprecated definition for the port transmit scheduling discipline
- */
-#define IxEthAccTxSchedulerDiscipline IxEthAccSchedulerDiscipline
-
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccTxSchedulingDisciplineSet( IxEthAccPortId portId, IxEthAccSchedulerDiscipline sched)
- *
- * @brief Set the port scheduling to one of @a IxEthAccSchedulerDiscipline
- *
- * The default behavior of the component is @a FIFO_NO_PRIORITY.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @pre
- *
- *
- * @param portId @ref IxEthAccPortId [in]
- * @param sched @ref IxEthAccSchedulerDiscipline [in]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS : Set appropriate discipline.
- * @li @a IX_ETH_ACC_FAIL : Invalid/unsupported discipline.
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccTxSchedulingDisciplineSet(IxEthAccPortId portId,
- IxEthAccSchedulerDiscipline sched);
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccRxSchedulingDisciplineSet(IxEthAccSchedulerDiscipline sched)
- *
- * @brief Set the Rx scheduling to one of @a IxEthAccSchedulerDiscipline
- *
- * The default behavior of the component is @a FIFO_NO_PRIORITY.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @pre
- *
- * @param sched : @a IxEthAccSchedulerDiscipline
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS : Set appropriate discipline.
- * @li @a IX_ETH_ACC_FAIL : Invalid/unsupported discipline.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccRxSchedulingDisciplineSet(IxEthAccSchedulerDiscipline sched);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn IxEthAccStatus ixEthAccNpeLoopbackEnable(IxEthAccPortId portId)
- *
- * @brief Enable NPE loopback
- *
- * When this loopback mode is enabled all the transmitted frames are
- * received on the same port, without payload.
- *
- * This function is recommended for power-up diagnostic checks and
- * should never be used under normal Ethernet traffic operations.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @pre
- *
- * @param portId : ID of the port
- *
- * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is
- * guaranteed to restore correct Ethernet Tx/Rx operation.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS : NPE loopback mode enabled
- * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortNpeLoopbackEnable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn IxEthAccStatus ixEthAccPortNpeLoopbackDisable(IxEthAccPortId portId)
- *
- * @brief Disable NPE loopback
- *
- * This function is used to disable the NPE loopback if previously
- * enabled using ixEthAccNpeLoopbackEnable.
- *
- * This function is recommended for power-up diagnostic checks and
- * should never be used under normal Ethernet traffic operations.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @pre
- *
- * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is
- * guaranteed to restore correct Ethernet Tx/Rx operation.
- *
- * @param portId : ID of the port
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS : NPE loopback successfully disabled
- * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortNpeLoopbackDisable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn IxEthAccStatus ixEthAccPortTxEnable(IxEthAccPortId portId)
- *
- * @brief Enable Tx on the port
- *
- * This function is the complement of ixEthAccPortTxDisable and should
- * be used only after Tx was disabled. A MAC core reset is required before
- * this function is called (see @a ixEthAccPortMacReset).
- *
- * This function is the recommended usage scenario for emergency security
- * shutdown and hardware failure recovery and should never be used for throttling
- * traffic.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @pre
- *
- * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is
- * guaranteed to restore correct Ethernet Tx/Rx operation.
- *
- * @param portId : ID of the port
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS : Tx successfully enabled
- * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortTxEnable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn IxEthAccStatus ixEthAccPortTxDisable(IxEthAccPortId portId)
- *
- * @brief Disable Tx on the port
- *
- * This function can be used to disable Tx in the MAC core.
- * Tx can be re-enabled, although this is not guaranteed, by performing
- * a MAC core reset (@a ixEthAccPortMacReset) and calling ixEthAccPortTxEnable.
- * Note that using this function is not recommended, except for shutting
- * down Tx for emergency reasons. For proper port shutdown and re-enabling
- * see ixEthAccPortEnable and ixEthAccPortDisable.
- *
- * This function is the recommended usage scenario for emergency security
- * shutdown and hardware failure recovery and should never be used for throttling
- * traffic.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is
- * guaranteed to restore correct Ethernet Tx/Rx operation.
- *
- * @pre
- *
- * @param portId : ID of the port
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS : Tx successfully disabled
- * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortTxDisable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn IxEthAccStatus ixEthAccPortRxEnable(IxEthAccPortId portId)
- *
- * @brief Enable Rx on the port
- *
- * This function is the complement of ixEthAccPortRxDisable and should
- * be used only after Rx was disabled.
- *
- * This function is the recommended usage scenario for emergency security
- * shutdown and hardware failure recovery and should never be used for throttling
- * traffic.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is
- * guaranteed to restore correct Ethernet Tx/Rx operation.
- *
- * @pre
- *
- * @param portId : ID of the port
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS : Rx successfully enabled
- * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortRxEnable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn IxEthAccStatus ixEthAccPortRxDisable(IxEthAccPortId portId)
- *
- * @brief Disable Rx on the port
- *
- * This function can be used to disable Rx in the MAC core.
- * Rx can be re-enabled, although this is not guaranteed, by performing
- * a MAC core reset (@a ixEthAccPortMacReset) and calling ixEthAccPortRxEnable.
- * Note that using this function is not recommended, except for shutting
- * down Rx for emergency reasons. For proper port shutdown and re-enabling
- * see ixEthAccPortEnable and ixEthAccPortDisable.
- *
- * This function is the recommended usage scenario for emergency security
- * shutdown and hardware failure recovery and should never be used for throttling
- * traffic.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @pre
- *
- * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is
- * guaranteed to restore correct Ethernet Tx/Rx operation.
- *
- * @param portId : ID of the port
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS : Rx successfully disabled
- * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortRxDisable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn IxEthAccStatus ixEthAccPortMacReset(IxEthAccPortId portId)
- *
- * @brief Reset MAC core on the port
- *
- * This function will perform a MAC core reset (NPE Ethernet coprocessor).
- * This function is inherently unsafe and the NPE recovery is not guaranteed
- * after this function is called. The proper manner of performing port disable
- * and enable (which will reset the MAC as well) is ixEthAccPortEnable/ixEthAccPortDisable.
- *
- * This function is the recommended usage scenario for hardware failure recovery
- * and should never be used for throttling traffic.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @pre
- *
- * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is
- * guaranteed to restore correct Ethernet Tx/Rx operation.
- *
- * @param portId : ID of the port
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS : MAC core reset
- * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortMacReset(IxEthAccPortId portId);
-
-/*********************************************************************************
- #### ##### ## ##### # #### ##### # #### ####
- # # # # # # # # # # # #
- #### # # # # # #### # # # ####
- # # ###### # # # # # # #
- # # # # # # # # # # # # # # #
- #### # # # # # #### # # #### ####
-**********************************************************************************/
-
-
-/**
- *
- * @brief This struct defines the statistics returned by this component.
- *
- * The component returns MIB2 EthObj variables which are obtained from the
- * hardware or maintained by this component.
- *
- *
- */
-typedef struct
-{
- UINT32 dot3StatsAlignmentErrors; /**< link error count (rx) */
- UINT32 dot3StatsFCSErrors; /**< link error count (rx) */
- UINT32 dot3StatsInternalMacReceiveErrors; /**< link error count (rx) */
- UINT32 RxOverrunDiscards; /**< NPE: discarded frames count (rx) */
- UINT32 RxLearnedEntryDiscards; /**< NPE: discarded frames count(rx) */
- UINT32 RxLargeFramesDiscards; /**< NPE: discarded frames count(rx) */
- UINT32 RxSTPBlockedDiscards; /**< NPE: discarded frames count(rx) */
- UINT32 RxVLANTypeFilterDiscards; /**< NPE: discarded frames count (rx) */
- UINT32 RxVLANIdFilterDiscards; /**< NPE: discarded frames count (rx) */
- UINT32 RxInvalidSourceDiscards; /**< NPE: discarded frames count (rx) */
- UINT32 RxBlackListDiscards; /**< NPE: discarded frames count (rx) */
- UINT32 RxWhiteListDiscards; /**< NPE: discarded frames count (rx) */
- UINT32 RxUnderflowEntryDiscards; /**< NPE: discarded frames count (rx) */
- UINT32 dot3StatsSingleCollisionFrames; /**< link error count (tx) */
- UINT32 dot3StatsMultipleCollisionFrames; /**< link error count (tx) */
- UINT32 dot3StatsDeferredTransmissions; /**< link error count (tx) */
- UINT32 dot3StatsLateCollisions; /**< link error count (tx) */
- UINT32 dot3StatsExcessiveCollsions; /**< link error count (tx) */
- UINT32 dot3StatsInternalMacTransmitErrors; /**< link error count (tx) */
- UINT32 dot3StatsCarrierSenseErrors; /**< link error count (tx) */
- UINT32 TxLargeFrameDiscards; /**< NPE: discarded frames count (tx) */
- UINT32 TxVLANIdFilterDiscards; /**< NPE: discarded frames count (tx) */
-
-}IxEthEthObjStats;
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccMibIIStatsGet(IxEthAccPortId portId ,IxEthEthObjStats *retStats )
- *
- * @brief Returns the statistics maintained for a port.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @pre
- *
- *
- * @param portId @ref IxEthAccPortId [in]
- * @param retStats @ref IxEthEthObjStats [out]
- * @note Please note the user is responsible for cache coheriency of the retStat
- * buffer. The data is actually populated via the NPE's. As such cache safe
- * memory should be used in the retStats argument.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : Invalid arguments.
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccMibIIStatsGet(IxEthAccPortId portId, IxEthEthObjStats *retStats );
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccMibIIStatsGetClear(IxEthAccPortId portId, IxEthEthObjStats *retStats)
- *
- * @brief Returns and clears the statistics maintained for a port.
- *
- * @li Reentrant - yes
- * @li ISR Callable - yes
- *
- * @pre
- *
- * @param portId @ref IxEthAccPortId [in]
- * @param retStats @ref IxEthEthObjStats [out]
- * @note Please note the user is responsible for cache coheriency of the retStats
- * buffer. The data is actually populated via the NPE's. As such cache safe
- * memory should be used in the retStats argument.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : invalid arguments.
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccMibIIStatsGetClear(IxEthAccPortId portId, IxEthEthObjStats *retStats);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccMibIIStatsClear(IxEthAccPortId portId)
- *
- * @brief Clears the statistics maintained for a port.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @pre
- *
- * @param portId @ref IxEthAccPortId [in]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : Invalid arguments.
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccMibIIStatsClear(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccMacInit(IxEthAccPortId portId)
- *
- * @brief Initializes the ethernet MAC settings
- *
- * @li Reentrant - no
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccMacInit(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccStatsShow(IxEthAccPortId portId)
- *
- *
- * @brief Displays a ports statistics on the standard io console using printf.
- *
- * @li Reentrant - no
- * @li ISR Callable - no
- *
- * @pre
- *
- * @param portId @ref IxEthAccPortId [in]
- *
- * @return void
- *
- * <hr>
- */
-PUBLIC void ixEthAccStatsShow(IxEthAccPortId portId);
-
-/*************************************************************************
-
- # # # # # # ##### # ####
- ## ## # # ## ## # # # # #
- # ## # # # # ## # # # # # #
- # # # # # # # # # # #
- # # # # # # # # # # #
- # # # # # # ##### # ####
-
-*************************************************************************/
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccMiiReadRtn (UINT8 phyAddr,
- UINT8 phyReg,
- UINT16 *value)
- *
- *
- * @brief Reads a 16 bit value from a PHY
- *
- * Reads a 16-bit word from a register of a MII-compliant PHY. Reading
- * is performed through the MII management interface. This function returns
- * when the read operation has successfully completed, or when a timeout has elapsed.
- *
- * @li Reentrant - no
- * @li ISR Callable - no
- *
- * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock.
- *
- * @param phyAddr UINT8 [in] - the address of the Ethernet PHY (0-31)
- * @param phyReg UINT8 [in] - the number of the MII register to read (0-31)
- * @param value UINT16 [in] - the value read from the register
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : failed to read the register.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccMiiReadRtn (UINT8 phyAddr, UINT8 phyReg, UINT16 *value);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccMiiWriteRtn (UINT8 phyAddr,
- UINT8 phyReg,
- UINT16 value)
- *
- *
- * @brief Writes a 16 bit value to a PHY
- *
- * Writes a 16-bit word from a register of a MII-compliant PHY. Writing
- * is performed through the MII management interface. This function returns
- * when the write operation has successfully completed, or when a timeout has elapsed.
- *
- * @li Reentrant - no
- * @li ISR Callable - no
- *
- * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock.
- *
- * @param phyAddr UINT8 [in] - the address of the Ethernet PHY (0-31)
- * @param phyReg UINT8 [in] - the number of the MII register to write (0-31)
- * @param value UINT16 [out] - the value to write to the register
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : failed to write register.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccMiiWriteRtn (UINT8 phyAddr, UINT8 phyReg, UINT16 value);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccMiiAccessTimeoutSet(UINT32 timeout)
- *
- * @brief Overrides the default timeout value and retry count when reading or
- * writing MII registers using ixEthAccMiiWriteRtn or ixEthAccMiiReadRtn
- *
- * The default behavior of the component is to use a IX_ETH_ACC_MII_10TH_SEC_IN_MILLIS ms
- * timeout (declared as 100 in IxEthAccMii_p.h) and a retry count of IX_ETH_ACC_MII_TIMEOUT_10TH_SECS
- * (declared as 5 in IxEthAccMii_p.h).
- *
- * The MII read and write functions will attempt to read the status of the register up
- * to the retry count times, delaying between each attempt with the timeout value.
- *
- * @li Reentrant - no
- * @li ISR Callable - no
- *
- * @pre
- *
- * @param timeout UINT32 [in] - new timeout value, in milliseconds
- * @param timeout UINT32 [in] - new retry count (a minimum value of 1 must be used)
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : invalid parameter(s)
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccMiiAccessTimeoutSet(UINT32 timeout, UINT32 retryCount);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccMiiStatsShow (UINT32 phyAddr)
- *
- *
- * @brief Displays detailed information on a specified PHY
- *
- * Displays the current values of the first eigth MII registers for a PHY,
- *
- * @li Reentrant - no
- * @li ISR Callable - no
- *
- * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and
- * generating the MDIO clock.
- *
- * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31)
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : invalid arguments.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccMiiStatsShow (UINT32 phyAddr);
-
-
-
-/******* BOARD SPECIFIC DEPRECATED API *********/
-
-/* The following functions are high level functions which rely
- * on the properties and interface of some Ethernet PHYs. The
- * implementation is hardware specific and has been moved to
- * the hardware-specific component IxEthMii.
- */
-
- #include "IxEthMii.h"
-
-/**
- * @ingroup IxEthAcc
- *
- * @def ixEthAccMiiPhyScan
- *
- * @brief : deprecated API entry point. This definition
- * ensures backward compatibility
- *
- * See @ref ixEthMiiPhyScan
- *
- * @note this feature is board specific
- *
- */
-#define ixEthAccMiiPhyScan(phyPresent) ixEthMiiPhyScan(phyPresent,IXP425_ETH_ACC_MII_MAX_ADDR)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def ixEthAccMiiPhyConfig
- *
- * @brief : deprecated API entry point. This definition
- * ensures backward compatibility
- *
- * See @ref ixEthMiiPhyConfig
- *
- * @note this feature is board specific
- */
-#define ixEthAccMiiPhyConfig(phyAddr,speed100,fullDuplex,autonegotiate) \
- ixEthMiiPhyConfig(phyAddr,speed100,fullDuplex,autonegotiate)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def ixEthAccMiiPhyReset
- *
- * @brief : deprecated API entry point. This definition
- * ensures backward compatibility
- *
- * See @ref ixEthMiiPhyReset
- *
- * @note this feature is board specific
- */
-#define ixEthAccMiiPhyReset(phyAddr) \
- ixEthMiiPhyReset(phyAddr)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def ixEthAccMiiLinkStatus
- *
- * @brief : deprecated API entry point. This definition
- * ensures backward compatibility
- *
- * See @ref ixEthMiiLinkStatus
- *
- * @note this feature is board specific
- */
-#define ixEthAccMiiLinkStatus(phyAddr,linkUp,speed100,fullDuplex,autoneg) \
- ixEthMiiLinkStatus(phyAddr,linkUp,speed100,fullDuplex,autoneg)
-
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @def ixEthAccMiiShow
- *
- * @brief : deprecated API entry point. This definition
- * ensures backward compatibility
- *
- * See @ref ixEthMiiPhyShow
- *
- * @note this feature is board specific
- */
-#define ixEthAccMiiShow(phyAddr) \
- ixEthMiiPhyShow(phyAddr)
-
-#endif /* ndef IxEthAcc_H */
-/**
- *@}
- */
+++ /dev/null
-/**
- * @file IxEthAccDataPlane_p.h
- *
- * @author Intel Corporation
- * @date 12-Feb-2002
- *
- * @brief Internal Header file for IXP425 Ethernet Access component.
- *
- * Design Notes:
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-
-
-#ifndef IxEthAccDataPlane_p_H
-#define IxEthAccDataPlane_p_H
-
-#include <IxOsal.h>
-#include <IxQMgr.h>
-
-/**
- * @addtogroup IxEthAccPri
- *@{
- */
-
-/* typedefs global to this file*/
-
-typedef struct
-{
- IX_OSAL_MBUF *pHead;
- IX_OSAL_MBUF *pTail;
-}IxEthAccDataPlaneQList;
-
-
-/**
- * @struct IxEthAccDataPlaneStats
- * @brief Statistics data structure associated with the data plane
- *
- */
-typedef struct
-{
- UINT32 addToSwQ;
- UINT32 removeFromSwQ;
- UINT32 unchainedTxMBufs;
- UINT32 chainedTxMBufs;
- UINT32 unchainedTxDoneMBufs;
- UINT32 chainedTxDoneMBufs;
- UINT32 unchainedRxMBufs;
- UINT32 chainedRxMBufs;
- UINT32 unchainedRxFreeMBufs;
- UINT32 chainedRxFreeMBufs;
- UINT32 rxCallbackCounter;
- UINT32 rxCallbackBurstRead;
- UINT32 txDoneCallbackCounter;
- UINT32 unexpectedError;
-} IxEthAccDataPlaneStats;
-
-/**
- * @fn ixEthAccMbufFromSwQ
- * @brief used during disable steps to convert mbufs from
- * swq format, ready to be pushed into hw queues for NPE,
- * back into XScale format
- */
-IX_OSAL_MBUF *ixEthAccMbufFromSwQ(IX_OSAL_MBUF *mbuf);
-
-/**
- * @fn ixEthAccDataPlaneShow
- * @brief Show function (for data plane statistics
- */
-void ixEthAccDataPlaneShow(void);
-
-/*
- * lock dataplane when atomic operation is required
- */
-#define IX_ETH_ACC_DATA_PLANE_LOCK(arg) arg = ixOsalIrqLock();
-#define IX_ETH_ACC_DATA_PLANE_UNLOCK(arg) ixOsalIrqUnlock(arg);
-
-/*
- * Use MBUF fields
- */
-#define IX_ETHACC_NE_SHARED(mBufPtr) \
- ((IxEthAccNe *)&((mBufPtr)->ix_ne))
-
-#if 1
-
-#define IX_ETHACC_NE_NEXT(mBufPtr) (mBufPtr)->ix_ne.reserved[0]
-
-/* tm - wrong!! len and pkt_len are in the second word - #define IX_ETHACC_NE_LEN(mBufPtr) (mBufPtr)->ix_ne.reserved[3] */
-#define IX_ETHACC_NE_LEN(mBufPtr) (mBufPtr)->ix_ne.reserved[1]
-
-#define IX_ETHACC_NE_DATA(mBufPtr)(mBufPtr)->ix_ne.reserved[2]
-
-#else
-
-#define IX_ETHACC_NE_NEXT(mBufPtr) \
- IX_ETHACC_NE_SHARED(mBufPtr)->ixReserved_next
-
-#define IX_ETHACC_NE_LEN(mBufPtr) \
- IX_ETHACC_NE_SHARED(mBufPtr)->ixReserved_lengths
-
-#define IX_ETHACC_NE_DATA(mBufPtr) \
- IX_ETHACC_NE_SHARED(mBufPtr)->ixReserved_data
-#endif
-
-/*
- * Use MBUF next pointer field to chain data.
- */
-#define IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER(mbuf) (mbuf)->ix_ctrl.ix_chain
-
-
-
-#define IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(mbuf_list) ((mbuf_list.pHead) == NULL)
-
-
-#define IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD(mbuf_list,mbuf_to_add) \
- do { \
- int lockVal; \
- IX_ETH_ACC_DATA_PLANE_LOCK(lockVal); \
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.addToSwQ); \
- if ( (mbuf_list.pHead) != NULL ) \
- { \
- (IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_add))) = (mbuf_list.pHead);\
- (mbuf_list.pHead) = (mbuf_to_add); \
- } \
- else { \
- (mbuf_list.pTail) = (mbuf_list.pHead) = (mbuf_to_add); \
- IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_add)) = NULL; \
- } \
- IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal); \
- } while(0)
-
-
-#define IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_TAIL(mbuf_list,mbuf_to_add) \
- do { \
- int lockVal; \
- IX_ETH_ACC_DATA_PLANE_LOCK(lockVal); \
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.addToSwQ); \
- if ( (mbuf_list.pHead) == NULL ) \
- { \
- (mbuf_list.pHead) = mbuf_to_add; \
- IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_add)) = NULL; \
- } \
- else { \
- IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_list.pTail)) = (mbuf_to_add); \
- IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_add)) = NULL; \
- } \
- (mbuf_list.pTail) = mbuf_to_add; \
- IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal); \
- } while (0)
-
-
-#define IX_ETH_ACC_DATAPLANE_REMOVE_MBUF_FROM_Q_HEAD(mbuf_list,mbuf_to_rem) \
- do { \
- int lockVal; \
- IX_ETH_ACC_DATA_PLANE_LOCK(lockVal); \
- if ( (mbuf_list.pHead) != NULL ) \
- { \
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.removeFromSwQ); \
- (mbuf_to_rem) = (mbuf_list.pHead) ; \
- (mbuf_list.pHead) = (IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_rem)));\
- } \
- else { \
- (mbuf_to_rem) = NULL; \
- } \
- IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal); \
- } while (0)
-
-
-/**
- * @brief message handler QManager entries for NPE id => port ID conversion (NPE_B => 0, NPE_C => 1)
- */
-#define IX_ETH_ACC_PORT_TO_NPE_ID(port) \
- ixEthAccPortData[(port)].npeId
-
-#define IX_ETH_ACC_NPE_TO_PORT_ID(npe) ((npe == 0 ? 2 : (npe == 1 ? 0 : ( npe == 2 ? 1 : -1 ))))
-
-#define IX_ETH_ACC_PORT_TO_TX_Q_ID(port) \
- ixEthAccPortData[(port)].ixEthAccTxData.txQueue
-
-#define IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(port) \
- ixEthAccPortData[(port)].ixEthAccRxData.rxFreeQueue
-
-#define IX_ETH_ACC_PORT_TO_TX_Q_SOURCE(port) (port == IX_ETH_PORT_1 ? IX_ETH_ACC_TX_FRAME_ENET0_Q_SOURCE : (port == IX_ETH_PORT_2 ? IX_ETH_ACC_TX_FRAME_ENET1_Q_SOURCE : IX_ETH_ACC_TX_FRAME_ENET2_Q_SOURCE))
-
-#define IX_ETH_ACC_PORT_TO_RX_FREE_Q_SOURCE(port) (port == IX_ETH_PORT_1 ? IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q_SOURCE : (port == IX_ETH_PORT_2 ? IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q_SOURCE : IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q_SOURCE ))
-
-/* Flush the mbufs chain and all data pointed to by the mbuf */
-
-#ifndef NDEBUG
-#define IX_ETH_ACC_STATS_INC(x) (x++)
-#else
-#define IX_ETH_ACC_STATS_INC(x)
-#endif
-
-#define IX_ETH_ACC_MAX_TX_FRAMES_TO_SUBMIT 128
-
-void ixEthRxFrameQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId);
-void ixEthRxMultiBufferQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId);
-void ixEthTxFrameDoneQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId);
-
-#endif /* IxEthAccDataPlane_p_H */
-
-
-/**
- *@}
- */
-
+++ /dev/null
-/*
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-
-#ifndef IxEthAccMac_p_H
-#define IxEthAccMac_p_H
-
-#include "IxOsal.h"
-
-#define IX_ETH_ACC_MAX_MULTICAST_ADDRESSES 256
-#define IX_ETH_ACC_NUM_PORTS 3
-#define IX_ETH_ACC_MAX_FRAME_SIZE_DEFAULT 1536
-#define IX_ETH_ACC_MAX_FRAME_SIZE_UPPER_RANGE (65536-64)
-#define IX_ETH_ACC_MAX_FRAME_SIZE_LOWER_RANGE 64
-
-/*
- *
- * MAC register definitions
- *
- */
-#define IX_ETH_ACC_MAC_0_BASE IX_OSAL_IXP400_ETHA_PHYS_BASE
-#define IX_ETH_ACC_MAC_1_BASE IX_OSAL_IXP400_ETHB_PHYS_BASE
-#define IX_ETH_ACC_MAC_2_BASE IX_OSAL_IXP400_ETH_NPEA_PHYS_BASE
-
-#define IX_ETH_ACC_MAC_TX_CNTRL1 0x000
-#define IX_ETH_ACC_MAC_TX_CNTRL2 0x004
-#define IX_ETH_ACC_MAC_RX_CNTRL1 0x010
-#define IX_ETH_ACC_MAC_RX_CNTRL2 0x014
-#define IX_ETH_ACC_MAC_RANDOM_SEED 0x020
-#define IX_ETH_ACC_MAC_THRESH_P_EMPTY 0x030
-#define IX_ETH_ACC_MAC_THRESH_P_FULL 0x038
-#define IX_ETH_ACC_MAC_BUF_SIZE_TX 0x040
-#define IX_ETH_ACC_MAC_TX_DEFER 0x050
-#define IX_ETH_ACC_MAC_RX_DEFER 0x054
-#define IX_ETH_ACC_MAC_TX_TWO_DEFER_1 0x060
-#define IX_ETH_ACC_MAC_TX_TWO_DEFER_2 0x064
-#define IX_ETH_ACC_MAC_SLOT_TIME 0x070
-#define IX_ETH_ACC_MAC_MDIO_CMD_1 0x080
-#define IX_ETH_ACC_MAC_MDIO_CMD_2 0x084
-#define IX_ETH_ACC_MAC_MDIO_CMD_3 0x088
-#define IX_ETH_ACC_MAC_MDIO_CMD_4 0x08c
-#define IX_ETH_ACC_MAC_MDIO_STS_1 0x090
-#define IX_ETH_ACC_MAC_MDIO_STS_2 0x094
-#define IX_ETH_ACC_MAC_MDIO_STS_3 0x098
-#define IX_ETH_ACC_MAC_MDIO_STS_4 0x09c
-#define IX_ETH_ACC_MAC_ADDR_MASK_1 0x0A0
-#define IX_ETH_ACC_MAC_ADDR_MASK_2 0x0A4
-#define IX_ETH_ACC_MAC_ADDR_MASK_3 0x0A8
-#define IX_ETH_ACC_MAC_ADDR_MASK_4 0x0AC
-#define IX_ETH_ACC_MAC_ADDR_MASK_5 0x0B0
-#define IX_ETH_ACC_MAC_ADDR_MASK_6 0x0B4
-#define IX_ETH_ACC_MAC_ADDR_1 0x0C0
-#define IX_ETH_ACC_MAC_ADDR_2 0x0C4
-#define IX_ETH_ACC_MAC_ADDR_3 0x0C8
-#define IX_ETH_ACC_MAC_ADDR_4 0x0CC
-#define IX_ETH_ACC_MAC_ADDR_5 0x0D0
-#define IX_ETH_ACC_MAC_ADDR_6 0x0D4
-#define IX_ETH_ACC_MAC_INT_CLK_THRESH 0x0E0
-#define IX_ETH_ACC_MAC_UNI_ADDR_1 0x0F0
-#define IX_ETH_ACC_MAC_UNI_ADDR_2 0x0F4
-#define IX_ETH_ACC_MAC_UNI_ADDR_3 0x0F8
-#define IX_ETH_ACC_MAC_UNI_ADDR_4 0x0FC
-#define IX_ETH_ACC_MAC_UNI_ADDR_5 0x100
-#define IX_ETH_ACC_MAC_UNI_ADDR_6 0x104
-#define IX_ETH_ACC_MAC_CORE_CNTRL 0x1FC
-
-
-/*
- *
- *Bit definitions
- *
- */
-
-/* TX Control Register 1*/
-
-#define IX_ETH_ACC_TX_CNTRL1_TX_EN BIT(0)
-#define IX_ETH_ACC_TX_CNTRL1_DUPLEX BIT(1)
-#define IX_ETH_ACC_TX_CNTRL1_RETRY BIT(2)
-#define IX_ETH_ACC_TX_CNTRL1_PAD_EN BIT(3)
-#define IX_ETH_ACC_TX_CNTRL1_FCS_EN BIT(4)
-#define IX_ETH_ACC_TX_CNTRL1_2DEFER BIT(5)
-#define IX_ETH_ACC_TX_CNTRL1_RMII BIT(6)
-
-/* TX Control Register 2 */
-#define IX_ETH_ACC_TX_CNTRL2_RETRIES_MASK 0xf
-
-/* RX Control Register 1 */
-#define IX_ETH_ACC_RX_CNTRL1_RX_EN BIT(0)
-#define IX_ETH_ACC_RX_CNTRL1_PADSTRIP_EN BIT(1)
-#define IX_ETH_ACC_RX_CNTRL1_CRC_EN BIT(2)
-#define IX_ETH_ACC_RX_CNTRL1_PAUSE_EN BIT(3)
-#define IX_ETH_ACC_RX_CNTRL1_LOOP_EN BIT(4)
-#define IX_ETH_ACC_RX_CNTRL1_ADDR_FLTR_EN BIT(5)
-#define IX_ETH_ACC_RX_CNTRL1_RX_RUNT_EN BIT(6)
-#define IX_ETH_ACC_RX_CNTRL1_BCAST_DIS BIT(7)
-
-/* RX Control Register 2 */
-#define IX_ETH_ACC_RX_CNTRL2_DEFER_EN BIT(0)
-
-
-
-/* Core Control Register */
-#define IX_ETH_ACC_CORE_RESET BIT(0)
-#define IX_ETH_ACC_CORE_RX_FIFO_FLUSH BIT(1)
-#define IX_ETH_ACC_CORE_TX_FIFO_FLUSH BIT(2)
-#define IX_ETH_ACC_CORE_SEND_JAM BIT(3)
-#define IX_ETH_ACC_CORE_MDC_EN BIT(4)
-
-/* 1st bit of 1st MAC octet */
-#define IX_ETH_ACC_ETH_MAC_BCAST_MCAST_BIT ( 1)
-
-
-/*
- *
- * Default values
- *
- */
-
-
-#define IX_ETH_ACC_TX_CNTRL1_DEFAULT (IX_ETH_ACC_TX_CNTRL1_TX_EN | \
- IX_ETH_ACC_TX_CNTRL1_RETRY | \
- IX_ETH_ACC_TX_CNTRL1_FCS_EN | \
- IX_ETH_ACC_TX_CNTRL1_2DEFER | \
- IX_ETH_ACC_TX_CNTRL1_PAD_EN)
-
-#define IX_ETH_ACC_TX_MAX_RETRIES_DEFAULT 0x0f
-
-#define IX_ETH_ACC_RX_CNTRL1_DEFAULT (IX_ETH_ACC_RX_CNTRL1_CRC_EN \
- | IX_ETH_ACC_RX_CNTRL1_RX_EN)
-
-#define IX_ETH_ACC_RX_CNTRL2_DEFAULT 0x0
-
-/* Thresholds determined by NPE firmware FS */
-#define IX_ETH_ACC_MAC_THRESH_P_EMPTY_DEFAULT 0x12
-#define IX_ETH_ACC_MAC_THRESH_P_FULL_DEFAULT 0x30
-
-/* Number of bytes that must be in the tx fifo before
- transmission commences*/
-#define IX_ETH_ACC_MAC_BUF_SIZE_TX_DEFAULT 0x8
-
-/* One-part deferral values */
-#define IX_ETH_ACC_MAC_TX_DEFER_DEFAULT 0x15
-#define IX_ETH_ACC_MAC_RX_DEFER_DEFAULT 0x16
-
-/* Two-part deferral values... */
-#define IX_ETH_ACC_MAC_TX_TWO_DEFER_1_DEFAULT 0x08
-#define IX_ETH_ACC_MAC_TX_TWO_DEFER_2_DEFAULT 0x07
-
-/* This value applies to MII */
-#define IX_ETH_ACC_MAC_SLOT_TIME_DEFAULT 0x80
-
-/* This value applies to RMII */
-#define IX_ETH_ACC_MAC_SLOT_TIME_RMII_DEFAULT 0xFF
-
-#define IX_ETH_ACC_MAC_ADDR_MASK_DEFAULT 0xFF
-
-#define IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT 0x1
-/*The following is a value chosen at random*/
-#define IX_ETH_ACC_RANDOM_SEED_DEFAULT 0x8
-
-/*By default we must configure the MAC to generate the
- MDC clock*/
-#define IX_ETH_ACC_CORE_DEFAULT (IX_ETH_ACC_CORE_MDC_EN)
-
-#define IXP425_ETH_ACC_MAX_PHY 2
-#define IXP425_ETH_ACC_MAX_AN_ENTRIES 20
-#define IX_ETH_ACC_MAC_RESET_DELAY 1
-
-#define IX_ETH_ACC_MAC_ALL_BITS_SET 0xFF
-
-#define IX_ETH_ACC_MAC_MSGID_SHL 24
-
-#define IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS 20
-#define IX_ETH_ACC_PORT_DISABLE_DELAY_COUNT 200 /* 4 seconds timeout */
-#define IX_ETH_ACC_PORT_DISABLE_RETRY_COUNT 3
-#define IX_ETH_ACC_MIB_STATS_DELAY_MSECS 2000 /* 2 seconds delay for ethernet stats */
-
-/*Register access macros*/
-#if (CPU == SIMSPARCSOLARIS)
-extern void registerWriteStub (UINT32 base, UINT32 offset, UINT32 val);
-extern UINT32 registerReadStub (UINT32 base, UINT32 offset);
-
-#define REG_WRITE(b,o,v) registerWriteStub(b, o, v)
-#define REG_READ(b,o,v) do { v = registerReadStub(b, o); } while (0)
-#else
-#define REG_WRITE(b,o,v) IX_OSAL_WRITE_LONG((volatile UINT32 *)(b + o), v)
-#define REG_READ(b,o,v) (v = IX_OSAL_READ_LONG((volatile UINT32 *)(b + o)))
-
-#endif
-
-void ixEthAccMacUnload(void);
-IxEthAccStatus ixEthAccMacMemInit(void);
-
-/* MAC core loopback */
-IxEthAccStatus ixEthAccPortLoopbackEnable(IxEthAccPortId portId);
-IxEthAccStatus ixEthAccPortLoopbackDisable(IxEthAccPortId portId);
-
-/* MAC core traffic control */
-IxEthAccStatus ixEthAccPortTxEnablePriv(IxEthAccPortId portId);
-IxEthAccStatus ixEthAccPortTxDisablePriv(IxEthAccPortId portId);
-IxEthAccStatus ixEthAccPortRxEnablePriv(IxEthAccPortId portId);
-IxEthAccStatus ixEthAccPortRxDisablePriv(IxEthAccPortId portId);
-IxEthAccStatus ixEthAccPortMacResetPriv(IxEthAccPortId portId);
-
-/* NPE software loopback */
-IxEthAccStatus ixEthAccNpeLoopbackDisablePriv(IxEthAccPortId portId);
-IxEthAccStatus ixEthAccNpeLoopbackEnablePriv(IxEthAccPortId portId);
-
-#endif /*IxEthAccMac_p_H*/
-
+++ /dev/null
-/**
- * @file IxEthAccMii_p.h
- *
- * @author Intel Corporation
- * @date
- *
- * @brief MII Header file
- *
- * Design Notes:
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxEthAccMii_p_H
-#define IxEthAccMii_p_H
-
-/* MII definitions - these have been verified against the LXT971 and LXT972 PHYs*/
-
-#define IXP425_ETH_ACC_MII_MAX_REG 32 /* max register per phy */
-
-#define IX_ETH_ACC_MII_REG_SHL 16
-#define IX_ETH_ACC_MII_ADDR_SHL 21
-
-/* Definitions for MII access routines*/
-
-#define IX_ETH_ACC_MII_GO BIT(31)
-#define IX_ETH_ACC_MII_WRITE BIT(26)
-#define IX_ETH_ACC_MII_TIMEOUT_10TH_SECS 5
-#define IX_ETH_ACC_MII_10TH_SEC_IN_MILLIS 100
-#define IX_ETH_ACC_MII_READ_FAIL BIT(31)
-
-#define IX_ETH_ACC_MII_PHY_DEF_DELAY 300 /* max delay before link up, etc. */
-#define IX_ETH_ACC_MII_PHY_NO_DELAY 0x0 /* do not delay */
-#define IX_ETH_ACC_MII_PHY_NULL 0xff /* PHY is not present */
-#define IX_ETH_ACC_MII_PHY_DEF_ADDR 0x0 /* default PHY's logical address */
-
-#ifndef IX_ETH_ACC_MII_MONITOR_DELAY
-# define IX_ETH_ACC_MII_MONITOR_DELAY 0x5 /* in seconds */
-#endif
-
-/* Register definition */
-
-#define IX_ETH_ACC_MII_CTRL_REG 0x0 /* Control Register */
-#define IX_ETH_ACC_MII_STAT_REG 0x1 /* Status Register */
-#define IX_ETH_ACC_MII_PHY_ID1_REG 0x2 /* PHY identifier 1 Register */
-#define IX_ETH_ACC_MII_PHY_ID2_REG 0x3 /* PHY identifier 2 Register */
-#define IX_ETH_ACC_MII_AN_ADS_REG 0x4 /* Auto-Negotiation */
- /* Advertisement Register */
-#define IX_ETH_ACC_MII_AN_PRTN_REG 0x5 /* Auto-Negotiation */
- /* partner ability Register */
-#define IX_ETH_ACC_MII_AN_EXP_REG 0x6 /* Auto-Negotiation */
- /* Expansion Register */
-#define IX_ETH_ACC_MII_AN_NEXT_REG 0x7 /* Auto-Negotiation */
- /* next-page transmit Register */
-
-IxEthAccStatus ixEthAccMdioShow (void);
-IxEthAccStatus ixEthAccMiiInit(void);
-void ixEthAccMiiUnload(void);
-
-#endif /*IxEthAccMii_p_H*/
+++ /dev/null
-/**
- * @file IxEthAccQueueAssign_p.h
- *
- * @author Intel Corporation
- * @date 06-Mar-2002
- *
- * @brief Mapping from QMgr Q's to internal assignment
- *
- * Design Notes:
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @addtogroup IxEthAccPri
- *@{
- */
-
-/*
- * Os/System dependancies.
- */
-#include "IxOsal.h"
-
-/*
- * Intermodule dependancies
- */
-#include "IxQMgr.h"
-#include "IxQueueAssignments.h"
-
-/* Check range of Q's assigned to this component. */
-#if IX_ETH_ACC_RX_FRAME_ETH_Q >= (IX_QMGR_MIN_QUEUPP_QID ) | \
- IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q >= (IX_QMGR_MIN_QUEUPP_QID) | \
- IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q >= (IX_QMGR_MIN_QUEUPP_QID) | \
- IX_ETH_ACC_TX_FRAME_ENET0_Q >= (IX_QMGR_MIN_QUEUPP_QID) | \
- IX_ETH_ACC_TX_FRAME_ENET1_Q >= (IX_QMGR_MIN_QUEUPP_QID) | \
- IX_ETH_ACC_TX_FRAME_DONE_ETH_Q >= (IX_QMGR_MIN_QUEUPP_QID)
-#error "Not all Ethernet Access Queues are betweem 1-31, requires full functionalty Q's unless otherwise validated "
-#endif
-
-/**
-*
-* @typedef IxEthAccQregInfo
-*
-* @brief
-*
-*/
-typedef struct
-{
- IxQMgrQId qId;
- char *qName;
- IxQMgrCallback qCallback;
- IxQMgrCallbackId callbackTag;
- IxQMgrQSizeInWords qSize;
- IxQMgrQEntrySizeInWords qWords;
- BOOL qNotificationEnableAtStartup;
- IxQMgrSourceId qConditionSource;
- IxQMgrWMLevel AlmostEmptyThreshold;
- IxQMgrWMLevel AlmostFullThreshold;
-
-} IxEthAccQregInfo;
-
-/*
- * Prototypes for all QM callbacks.
- */
-
-/*
- * Rx Callbacks
- */
-IX_ETH_ACC_PUBLIC
-void ixEthRxFrameQMCallback(IxQMgrQId, IxQMgrCallbackId);
-
-IX_ETH_ACC_PUBLIC
-void ixEthRxMultiBufferQMCallback(IxQMgrQId, IxQMgrCallbackId);
-
-IX_ETH_ACC_PUBLIC
-void ixEthRxFreeQMCallback(IxQMgrQId, IxQMgrCallbackId);
-
-/*
- * Tx Callback.
- */
-IX_ETH_ACC_PUBLIC
-void ixEthTxFrameQMCallback(IxQMgrQId, IxQMgrCallbackId);
-
-IX_ETH_ACC_PUBLIC
-void ixEthTxFrameDoneQMCallback(IxQMgrQId, IxQMgrCallbackId );
-
-
-#define IX_ETH_ACC_QM_QUEUE_DISPATCH_PRIORITY (IX_QMGR_Q_PRIORITY_0) /* Highest priority */
-
-/*
- * Queue watermarks
- */
-#define IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_NOT_E )
-#define IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_E )
-#define IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_E )
-#define IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_E )
-#define IX_ETH_ACC_TX_FRAME_ENET0_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_E )
-#define IX_ETH_ACC_TX_FRAME_ENET1_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_E )
-#define IX_ETH_ACC_TX_FRAME_ENET2_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_E )
-#define IX_ETH_ACC_TX_FRAME_DONE_ETH_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_NOT_E )
+++ /dev/null
-/**
- * @file IxEthAcc_p.h
- *
- * @author Intel Corporation
- * @date 12-Feb-2002
- *
- * @brief Internal Header file for IXP425 Ethernet Access component.
- *
- * Design Notes:
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @addtogroup IxEthAccPri
- *@{
- */
-
-#ifndef IxEthAcc_p_H
-#define IxEthAcc_p_H
-
-/*
- * Os/System dependancies.
- */
-#include "IxOsal.h"
-
-/*
- * Intermodule dependancies
- */
-#include "IxNpeDl.h"
-#include "IxQMgr.h"
-
-#include "IxEthNpe.h"
-
-/*
- * Intra module dependancies
- */
-
-#include "IxEthAccDataPlane_p.h"
-#include "IxEthAccMac_p.h"
-
-
-#define INLINE __inline__
-
-#ifdef NDEBUG
-
-#define IX_ETH_ACC_PRIVATE static
-
-#else
-
-#define IX_ETH_ACC_PRIVATE
-
-#endif /* ndef NDEBUG */
-
-#define IX_ETH_ACC_PUBLIC
-
-
-#define IX_ETH_ACC_IS_PORT_VALID(port) ((port) < IX_ETH_ACC_NUMBER_OF_PORTS ? true : false )
-
-
-
-#ifndef NDEBUG
-#define IX_ETH_ACC_FATAL_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_FATAL,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
-#define IX_ETH_ACC_WARNING_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_WARNING,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
-#define IX_ETH_ACC_DEBUG_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_FATAL,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
-#else
-#define IX_ETH_ACC_FATAL_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_FATAL,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
-#define IX_ETH_ACC_WARNING_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_WARNING,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
-#define IX_ETH_ACC_DEBUG_LOG(a,b,c,d,e,f,g) {}
-#endif
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccInitDataPlane(void);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccQMgrQueuesConfig(void);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccQMgrRxCallbacksRegister(IxQMgrCallback ixQMgrCallback);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccSingleEthNpeCheck(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC void ixEthAccQMgrRxQEntryGet(UINT32 *numRxQueueEntries);
-
-/* prototypes for the private control plane functions (used by the control interface wrapper) */
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortEnablePriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortDisablePriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortEnabledQueryPriv(IxEthAccPortId portId, BOOL *enabled);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortPromiscuousModeClearPriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortPromiscuousModeSetPriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortUnicastMacAddressSetPriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortUnicastMacAddressGetPriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressJoinPriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressJoinAllPriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressLeavePriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressLeaveAllPriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortUnicastAddressShowPriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC void ixEthAccPortMulticastAddressShowPriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortDuplexModeSetPriv(IxEthAccPortId portId, IxEthAccDuplexMode mode);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortDuplexModeGetPriv(IxEthAccPortId portId, IxEthAccDuplexMode *mode);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendPaddingEnablePriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendPaddingDisablePriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendFCSEnablePriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendFCSDisablePriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortRxFrameAppendFCSEnablePriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortRxFrameAppendFCSDisablePriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccTxSchedulingDisciplineSetPriv(IxEthAccPortId portId, IxEthAccSchedulerDiscipline sched);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccRxSchedulingDisciplineSetPriv(IxEthAccSchedulerDiscipline sched);
-
-/**
- * @struct ixEthAccRxDataStats
- * @brief Stats data structures for data path. - Not obtained from h/w
- *
- */
-typedef struct
-{
- UINT32 rxFrameClientCallback;
- UINT32 rxFreeRepOK;
- UINT32 rxFreeRepDelayed;
- UINT32 rxFreeRepFromSwQOK;
- UINT32 rxFreeRepFromSwQDelayed;
- UINT32 rxFreeLateNotificationEnabled;
- UINT32 rxFreeLowCallback;
- UINT32 rxFreeOverflow;
- UINT32 rxFreeLock;
- UINT32 rxDuringDisable;
- UINT32 rxSwQDuringDisable;
- UINT32 rxUnlearnedMacAddress;
- UINT32 rxPriority[IX_ETH_ACC_TX_PRIORITY_7 + 1];
- UINT32 rxUnexpectedError;
- UINT32 rxFiltered;
-} IxEthAccRxDataStats;
-
-/**
- * @struct IxEthAccTxDataStats
- * @brief Stats data structures for data path. - Not obtained from h/w
- *
- */
-typedef struct
-{
- UINT32 txQOK;
- UINT32 txQDelayed;
- UINT32 txFromSwQOK;
- UINT32 txFromSwQDelayed;
- UINT32 txLowThreshCallback;
- UINT32 txDoneClientCallback;
- UINT32 txDoneClientCallbackDisable;
- UINT32 txOverflow;
- UINT32 txLock;
- UINT32 txPriority[IX_ETH_ACC_TX_PRIORITY_7 + 1];
- UINT32 txLateNotificationEnabled;
- UINT32 txDoneDuringDisable;
- UINT32 txDoneSwQDuringDisable;
- UINT32 txUnexpectedError;
-} IxEthAccTxDataStats;
-
-/* port Disable state machine : list of states */
-typedef enum
-{
- /* general port states */
- DISABLED = 0,
- ACTIVE,
-
- /* particular Tx/Rx states */
- REPLENISH,
- RECEIVE,
- TRANSMIT,
- TRANSMIT_DONE
-} IxEthAccPortDisableState;
-
-typedef struct
-{
- BOOL fullDuplex;
- BOOL rxFCSAppend;
- BOOL txFCSAppend;
- BOOL txPADAppend;
- BOOL enabled;
- BOOL promiscuous;
- BOOL joinAll;
- IxOsalMutex ackMIBStatsLock;
- IxOsalMutex ackMIBStatsResetLock;
- IxOsalMutex MIBStatsGetAccessLock;
- IxOsalMutex MIBStatsGetResetAccessLock;
- IxOsalMutex npeLoopbackMessageLock;
- IxEthAccMacAddr mcastAddrsTable[IX_ETH_ACC_MAX_MULTICAST_ADDRESSES];
- UINT32 mcastAddrIndex;
- IX_OSAL_MBUF *portDisableTxMbufPtr;
- IX_OSAL_MBUF *portDisableRxMbufPtr;
-
- volatile IxEthAccPortDisableState portDisableState;
- volatile IxEthAccPortDisableState rxState;
- volatile IxEthAccPortDisableState txState;
-
- BOOL initDone;
- BOOL macInitialised;
-} IxEthAccMacState;
-
-/**
- * @struct IxEthAccRxInfo
- * @brief System-wide data structures associated with the data plane.
- *
- */
-typedef struct
-{
- IxQMgrQId higherPriorityQueue[IX_QMGR_MAX_NUM_QUEUES]; /**< higher priority queue list */
- IxEthAccSchedulerDiscipline schDiscipline; /**< Receive Xscale QoS type */
-} IxEthAccInfo;
-
-/**
- * @struct IxEthAccRxDataInfo
- * @brief Per Port data structures associated with the receive data plane.
- *
- */
-typedef struct
-{
- IxQMgrQId rxFreeQueue; /**< rxFree Queue for this port */
- IxEthAccPortRxCallback rxCallbackFn;
- UINT32 rxCallbackTag;
- IxEthAccDataPlaneQList freeBufferList;
- IxEthAccPortMultiBufferRxCallback rxMultiBufferCallbackFn;
- UINT32 rxMultiBufferCallbackTag;
- BOOL rxMultiBufferCallbackInUse;
- IxEthAccRxDataStats stats; /**< Receive s/w stats */
-} IxEthAccRxDataInfo;
-
-/**
- * @struct IxEthAccTxDataInfo
- * @brief Per Port data structures associated with the transmit data plane.
- *
- */
-typedef struct
-{
- IxEthAccPortTxDoneCallback txBufferDoneCallbackFn;
- UINT32 txCallbackTag;
- IxEthAccDataPlaneQList txQ[IX_ETH_ACC_NUM_TX_PRIORITIES]; /**< Transmit Q */
- IxEthAccSchedulerDiscipline schDiscipline; /**< Transmit Xscale QoS */
- IxQMgrQId txQueue; /**< txQueue for this port */
- IxEthAccTxDataStats stats; /**< Transmit s/w stats */
-} IxEthAccTxDataInfo;
-
-
-/**
- * @struct IxEthAccPortDataInfo
- * @brief Per Port data structures associated with the port data plane.
- *
- */
-typedef struct
-{
- BOOL portInitialized;
- UINT32 npeId; /**< NpeId for this port */
- IxEthAccTxDataInfo ixEthAccTxData; /**< Transmit data control structures */
- IxEthAccRxDataInfo ixEthAccRxData; /**< Receive data control structures */
-} IxEthAccPortDataInfo;
-
-extern IxEthAccPortDataInfo ixEthAccPortData[];
-#define IX_ETH_IS_PORT_INITIALIZED(port) (ixEthAccPortData[port].portInitialized)
-
-extern BOOL ixEthAccServiceInit;
-#define IX_ETH_ACC_IS_SERVICE_INITIALIZED() (ixEthAccServiceInit == true )
-
-/*
- * Maximum number of frames to consume from the Rx Frame Q.
- */
-
-#define IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK (128)
-
-/*
- * Max number of times to load the Rx Free Q from callback.
- */
-#define IX_ETH_ACC_MAX_RX_FREE_BUFFERS_LOAD (256) /* Set greater than depth of h/w Q + drain time at line rate */
-
-/*
- * Max number of times to read from the Tx Done Q in one sitting.
- */
-
-#define IX_ETH_ACC_MAX_TX_FRAME_DONE_CONSUME_PER_CALLBACK (256)
-
-/*
- * Max number of times to take buffers from S/w queues and write them to the H/w Tx
- * queues on receipt of a Tx low threshold callback
- */
-
-#define IX_ETH_ACC_MAX_TX_FRAME_TX_CONSUME_PER_CALLBACK (16)
-
-
-#define IX_ETH_ACC_FLUSH_CACHE(addr,size) IX_OSAL_CACHE_FLUSH((addr),(size))
-#define IX_ETH_ACC_INVALIDATE_CACHE(addr,size) IX_OSAL_CACHE_INVALIDATE((addr),(size))
-
-
-#define IX_ETH_ACC_MEMSET(start,value,size) memset(start,value,size)
-
-#endif /* ndef IxEthAcc_p_H */
-
-
-
+++ /dev/null
-/** @file IxEthDB.h
- *
- * @brief this file contains the public API of @ref IxEthDB component
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- *
- */
-
-#ifndef IxEthDB_H
-#define IxEthDB_H
-
-#include <IxOsBuffMgt.h>
-#include <IxTypes.h>
-
-/**
- * @defgroup IxEthDB IXP400 Ethernet Database (IxEthDB) API
- *
- * @brief ethDB is a library that does provides a MAC address database learning/filtering capability
- *
- *@{
- */
-
-#define INLINE __inline__
-
-#define IX_ETH_DB_PRIVATE PRIVATE /* imported from IxTypes.h */
-
-#define IX_ETH_DB_PUBLIC PUBLIC
-
-/**
- * @brief port ID => message handler NPE id conversion (0 => NPE_B, 1 => NPE_C)
- */
-#define IX_ETH_DB_PORT_ID_TO_NPE(id) (id == 0 ? 1 : (id == 1 ? 2 : (id == 2 ? 0 : -1)))
-
-/**
- * @def IX_ETH_DB_NPE_TO_PORT_ID(npe)
- * @brief message handler NPE id => port ID conversion (NPE_B => 0, NPE_C => 1)
- */
-#define IX_ETH_DB_NPE_TO_PORT_ID(npe) (npe == 0 ? 2 : (npe == 1 ? 0 : (npe == 2 ? 1 : -1)))
-
-/* temporary define - won't work for Azusa */
-#define IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(id) (IX_ETH_DB_PORT_ID_TO_NPE(id) << 4)
-#define IX_ETH_DB_NPE_LOGICAL_ID_TO_PORT_ID(id) (IX_ETH_DB_NPE_TO_PORT_ID(id >> 4))
-
-/**
- * @def IX_IEEE803_MAC_ADDRESS_SIZE
- * @brief The size of the MAC address
- */
-#define IX_IEEE803_MAC_ADDRESS_SIZE (6)
-
-/**
- * @def IX_IEEE802_1Q_QOS_PRIORITY_COUNT
- * @brief Number of QoS priorities defined by IEEE802.1Q
- */
-#define IX_IEEE802_1Q_QOS_PRIORITY_COUNT (8)
-
-/**
- * @enum IxEthDBStatus
- * @brief Ethernet Database API return values
- */
-typedef enum /* IxEthDBStatus */
-{
- IX_ETH_DB_SUCCESS = IX_SUCCESS, /**< Success */
- IX_ETH_DB_FAIL = IX_FAIL, /**< Failure */
- IX_ETH_DB_INVALID_PORT, /**< Invalid port */
- IX_ETH_DB_PORT_UNINITIALIZED, /**< Port not initialized */
- IX_ETH_DB_MAC_UNINITIALIZED, /**< MAC not initialized */
- IX_ETH_DB_INVALID_ARG, /**< Invalid argument */
- IX_ETH_DB_NO_SUCH_ADDR, /**< Address not found for search or delete operations */
- IX_ETH_DB_NOMEM, /**< Learning database memory full */
- IX_ETH_DB_BUSY, /**< Learning database cannot complete operation, access temporarily blocked */
- IX_ETH_DB_END, /**< Database browser passed the end of the record set */
- IX_ETH_DB_INVALID_VLAN, /**< Invalid VLAN ID (valid range is 0..4094, 0 signifies no VLAN membership, used for priority tagged frames) */
- IX_ETH_DB_INVALID_PRIORITY, /**< Invalid QoS priority/traffic class (valid range for QoS priority is 0..7, valid range for traffic class depends on run-time configuration) */
- IX_ETH_DB_NO_PERMISSION, /**< No permission for attempted operation */
- IX_ETH_DB_FEATURE_UNAVAILABLE, /**< Feature not available (or not enabled) */
- IX_ETH_DB_INVALID_KEY, /**< Invalid search key */
- IX_ETH_DB_INVALID_RECORD_TYPE /**< Invalid record type */
-} IxEthDBStatus;
-
-/** @brief VLAN ID type, valid range is 0..4094, 0 signifying no VLAN membership */
-typedef UINT32 IxEthDBVlanId;
-
-/** @brief 802.1Q VLAN tag, contains 3 bits user priority, 1 bit CFI, 12 bits VLAN ID */
-typedef UINT32 IxEthDBVlanTag;
-
-/** @brief QoS priority/traffic class type, valid range is 0..7, 0 being the lowest */
-typedef UINT32 IxEthDBPriority;
-
-/** @brief Priority mapping table; 0..7 QoS priorities used to index, table contains traffic classes */
-typedef UINT8 IxEthDBPriorityTable[8];
-
-/** @brief A 4096 bit array used to map the complete VLAN ID range */
-typedef UINT8 IxEthDBVlanSet[512];
-
-#define IX_ETH_DB_802_1Q_VLAN_MASK (0xFFF)
-#define IX_ETH_DB_802_1Q_QOS_MASK (0x7)
-
-#define IX_ETH_DB_802_1Q_MAX_VLAN_ID (0xFFE)
-
-/**
- * @def IX_ETH_DB_SET_VLAN_ID
- * @brief returns the given 802.1Q tag with the VLAN ID field substituted with the given VLAN ID
- *
- * This macro is used to change the VLAN ID in a 802.1Q tag.
- *
- * Example:
- *
- * tag = IX_ETH_DB_SET_VLAN_ID(tag, 32)
- *
- * inserts the VLAN ID "32" in the given tag.
- */
-#define IX_ETH_DB_SET_VLAN_ID(vlanTag, vlanID) (((vlanTag) & 0xF000) | ((vlanID) & IX_ETH_DB_802_1Q_VLAN_MASK))
-
-/**
-* @def IX_ETH_DB_GET_VLAN_ID
-* @brief returns the VLAN ID from the given 802.1Q tag
-*/
-#define IX_ETH_DB_GET_VLAN_ID(vlanTag) ((vlanTag) & IX_ETH_DB_802_1Q_VLAN_MASK)
-
-#define IX_ETH_DB_GET_QOS_PRIORITY(vlanTag) (((vlanTag) >> 13) & IX_ETH_DB_802_1Q_QOS_MASK)
-
-#define IX_ETH_DB_SET_QOS_PRIORITY(vlanTag, priority) (((vlanTag) & 0x1FFF) | (((priority) & IX_ETH_DB_802_1Q_QOS_MASK) << 13))
-
-#define IX_ETH_DB_CHECK_VLAN_TAG(vlanTag) { if(((vlanTag & 0xFFFF0000) != 0) || (IX_ETH_DB_GET_VLAN_ID(vlanTag) > 4094)) return IX_ETH_DB_INVALID_VLAN; }
-
-#define IX_ETH_DB_CHECK_VLAN_ID(vlanId) { if (vlanId > IX_ETH_DB_802_1Q_MAX_VLAN_ID) return IX_ETH_DB_INVALID_VLAN; }
-
-#define IX_IEEE802_1Q_VLAN_TPID (0x8100)
-
-typedef enum
-{
- IX_ETH_DB_UNTAGGED_FRAMES = 0x1, /**< Accepts untagged frames */
- IX_ETH_DB_VLAN_TAGGED_FRAMES = 0x2, /**< Accepts tagged frames */
- IX_ETH_DB_PRIORITY_TAGGED_FRAMES = 0x4, /**< Accepts tagged frames with VLAN ID set to 0 (no VLAN membership) */
- IX_ETH_DB_ACCEPT_ALL_FRAMES =
- IX_ETH_DB_UNTAGGED_FRAMES | IX_ETH_DB_VLAN_TAGGED_FRAMES /**< Accepts all the frames */
-} IxEthDBFrameFilter;
-
-typedef enum
-{
- IX_ETH_DB_PASS_THROUGH = 0x1, /**< Leave frame as-is */
- IX_ETH_DB_ADD_TAG = 0x2, /**< Add default port VLAN tag */
- IX_ETH_DB_REMOVE_TAG = 0x3 /**< Remove VLAN tag from frame */
-} IxEthDBTaggingAction;
-
-typedef enum
-{
- IX_ETH_DB_FIREWALL_WHITE_LIST = 0x1, /**< Firewall operates in white-list mode (MAC address based admission) */
- IX_ETH_DB_FIREWALL_BLACK_LIST = 0x2 /**< Firewall operates in black-list mode (MAC address based blocking) */
-} IxEthDBFirewallMode;
-
-typedef enum
-{
- IX_ETH_DB_FILTERING_RECORD = 0x01, /**< <table><caption> Filtering record </caption>
- * <tr><td> MAC address <td> static/dynamic type <td> age
- * </table>
- */
- IX_ETH_DB_FILTERING_VLAN_RECORD = 0x02, /**< <table><caption> VLAN-enabled filtering record </caption>
- * <tr><td> MAC address <td> static/dynamic type <td> age <td> 802.1Q tag
- * </table>
- */
- IX_ETH_DB_WIFI_RECORD = 0x04, /**< <table><caption> WiFi header conversion record </caption>
- * <tr><td> MAC address <td> optional gateway MAC address <td>
- * </table>
- */
- IX_ETH_DB_FIREWALL_RECORD = 0x08, /**< <table><caption> Firewall record </caption>
- * <tr><td> MAC address
- * </table>
- */
- IX_ETH_DB_GATEWAY_RECORD = 0x10, /**< <i>For internal use only</i> */
- IX_ETH_DB_MAX_RECORD_TYPE_INDEX = 0x10, /**< <i>For internal use only</i> */
- IX_ETH_DB_NO_RECORD_TYPE = 0, /**< None of the registered record types */
- IX_ETH_DB_ALL_FILTERING_RECORDS = IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD, /**< All the filtering records */
- IX_ETH_DB_ALL_RECORD_TYPES = IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD |
- IX_ETH_DB_WIFI_RECORD | IX_ETH_DB_FIREWALL_RECORD /**< All the record types registered within EthDB */
-} IxEthDBRecordType;
-
-typedef enum
-{
- IX_ETH_DB_LEARNING = 0x01, /**< Learning feature; enables EthDB to learn MAC address (filtering) records, including 802.1Q enabled records */
- IX_ETH_DB_FILTERING = 0x02, /**< Filtering feature; enables EthDB to communicate with the NPEs for downloading filtering information in the NPEs; depends on the learning feature */
- IX_ETH_DB_VLAN_QOS = 0x04, /**< VLAN/QoS feature; enables EthDB to configure NPEs to operate in VLAN/QoS aware modes */
- IX_ETH_DB_FIREWALL = 0x08, /**< Firewall feature; enables EthDB to configure NPEs to operate in firewall mode, using white/black address lists */
- IX_ETH_DB_SPANNING_TREE_PROTOCOL = 0x10, /**< Spanning tree protocol feature; enables EthDB to configure the NPEs as STP nodes */
- IX_ETH_DB_WIFI_HEADER_CONVERSION = 0x20 /**< WiFi 802.3 to 802.11 header conversion feature; enables EthDB to handle WiFi conversion data */
-} IxEthDBFeature;
-
-typedef UINT32 IxEthDBProperty; /**< Property ID type */
-
-typedef enum
-{
- IX_ETH_DB_INTEGER_PROPERTY = 0x1, /**< 4 byte unsigned integer type */
- IX_ETH_DB_STRING_PROPERTY = 0x2, /**< NULL-terminated string type of maximum 255 characters (including the terminator) */
- IX_ETH_DB_MAC_ADDR_PROPERTY = 0x3, /**< 6 byte MAC address type */
- IX_ETH_DB_BOOL_PROPERTY = 0x4 /**< 4 byte boolean type; can contain only true and false values */
-} IxEthDBPropertyType;
-
-/* list of supported properties for the IX_ETH_DB_VLAN_QOS feature */
-#define IX_ETH_DB_QOS_TRAFFIC_CLASS_COUNT_PROPERTY (0x01) /**< Property identifying number the supported number of traffic classes */
-#define IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY (0x10) /**< Rx queue assigned to traffic class 0 */
-#define IX_ETH_DB_QOS_TRAFFIC_CLASS_1_RX_QUEUE_PROPERTY (0x11) /**< Rx queue assigned to traffic class 1 */
-#define IX_ETH_DB_QOS_TRAFFIC_CLASS_2_RX_QUEUE_PROPERTY (0x12) /**< Rx queue assigned to traffic class 2 */
-#define IX_ETH_DB_QOS_TRAFFIC_CLASS_3_RX_QUEUE_PROPERTY (0x13) /**< Rx queue assigned to traffic class 3 */
-#define IX_ETH_DB_QOS_TRAFFIC_CLASS_4_RX_QUEUE_PROPERTY (0x14) /**< Rx queue assigned to traffic class 4 */
-#define IX_ETH_DB_QOS_TRAFFIC_CLASS_5_RX_QUEUE_PROPERTY (0x15) /**< Rx queue assigned to traffic class 5 */
-#define IX_ETH_DB_QOS_TRAFFIC_CLASS_6_RX_QUEUE_PROPERTY (0x16) /**< Rx queue assigned to traffic class 6 */
-#define IX_ETH_DB_QOS_TRAFFIC_CLASS_7_RX_QUEUE_PROPERTY (0x17) /**< Rx queue assigned to traffic class 7 */
-
-/* private property used by EthAcc to indicate queue configuration complete */
-#define IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE (0x18)
-
-/**
- *
- * @brief The IEEE 802.3 Ethernet MAC address structure.
- *
- * The data should be packed with bytes xx:xx:xx:xx:xx:xx
- *
- * @note The data must be packed in network byte order.
- */
-typedef struct
-{
- UINT8 macAddress[IX_IEEE803_MAC_ADDRESS_SIZE];
-} IxEthDBMacAddr;
-
-/**
- * @ingroup IxEthDB
- *
- * @brief Definition of an IXP400 port.
- */
-typedef UINT32 IxEthDBPortId;
-
-/**
- * @ingroup IxEthDB
- *
- * @brief Port dependency map definition
- */
-typedef UINT8 IxEthDBPortMap[32];
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBInit(void)
- *
- * @brief Initializes the Ethernet learning/filtering database
- *
- * @note calling this function multiple times does not constitute an error;
- * redundant calls will be ignored, returning IX_ETH_DB_SUCCESS
- *
- * @retval IX_ETH_DB_SUCCESS initialization was successful
- * @retval IX_ETH_DB_FAIL initialization failed (OS error)
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBInit(void);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBUnload(void)
- *
- * @brief Stops and prepares the EthDB component for unloading.
- *
- * @retval IX_ETH_DB_SUCCESS de-initialization was successful
- * @retval IX_ETH_DB_BUSY de-initialization failed, ports must be disabled first
- * @retval IX_ETH_DB_FAIL de-initialization failed (OS error)
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBUnload(void);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn void ixEthDBPortInit(IxEthDBPortId portID)
- *
- * @brief Initializes a port
- *
- * This function is called automatically by the Ethernet Access
- * ixEthAccPortInit() routine for Ethernet NPE ports and should be manually
- * called for any user-defined port (any port that is not one of
- * the two Ethernet NPEs).
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to be initialized
- *
- * @see IxEthDBPortDefs.h for port definitions
- *
- * @note calling this function multiple times does not constitute an error;
- * redundant calls will be ignored
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBPortInit(IxEthDBPortId portID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID)
- *
- * @brief Enables a port
- *
- * This function is called automatically from the Ethernet Access component
- * ixEthAccPortEnable() routine for Ethernet NPE ports and should be manually
- * called for any user-defined port (any port that is not one of
- * the Ethernet NPEs).
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to enable processing on
- *
- * @retval IX_ETH_DB_SUCCESS if enabling is successful
- * @retval IX_ETH_DB_FAIL if the enabling was not successful due to
- * a message handler error
- * @retval IX_ETH_DB_MAC_UNINITIALIZED the MAC address of this port was
- * not initialized (only for Ethernet NPEs)
- * @retval IX_ETH_DB_INVALID_PORT if portID is invalid
- *
- * @pre ixEthDBPortAddressSet needs to be called prior to enabling the port events
- * for Ethernet NPEs
- *
- * @see ixEthDBPortAddressSet
- *
- * @see IxEthDBPortDefs.h for port definitions
- *
- * @note calling this function multiple times does not constitute an error;
- * redundant calls will be ignored
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID)
- *
- * @brief Disables processing on a port
- *
- * This function is called automatically from the Ethernet Access component
- * ixEthAccPortDisable() routine for Ethernet NPE ports and should be manually
- * called for any user-defined port (any port that is not one of
- * the Ethernet NPEs).
- *
- * @note Calling ixEthAccPortDisable() will disable the respective Ethernet NPE.
- * After Ethernet NPEs are disabled they are stopped therefore
- * when re-enabled they need to be reset, downloaded with microcode and started.
- * For learning to restart working the user needs to call again
- * ixEthAccPortUnicastMacAddressSet or ixEthDBUnicastAddressSet
- * with the respective port MAC address.
- * Residual MAC addresses learnt before the port was disabled are deleted as soon
- * as the port is disabled. This only applies to dynamic (learnt) entries, static
- * entries do not dissapear when the port is disabled.
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to disable processing on
- *
- * @retval IX_ETH_DB_SUCCESS if disabling is successful
- * @retval IX_ETH_DB_FAIL if the disabling was not successful due to
- * a message handler error
- * @retval IX_ETH_DB_INVALID_PORT if portID is invalid
- *
- * @note calling this function multiple times after the first time completed successfully
- * does not constitute an error; redundant calls will be ignored and return IX_ETH_DB_SUCCESS
-*/
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortAddressSet(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Sets the port MAC address
- *
- * This function is to be called from the Ethernet Access component top-level
- * ixEthDBUnicastAddressSet(). Event processing cannot be enabled for a port
- * until its MAC address has been set.
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port whose MAC address is set
- * @param macAddr @ref IxEthDBMacAddr [in] - port MAC address
- *
- * @retval IX_ETH_DB_SUCCESS MAC address was set successfully
- * @retval IX_ETH_DB_FAIL MAC address was not set due to a message handler failure
- * @retval IX_ETH_DB_INVALID_PORT if the port is not an Ethernet NPE
- *
- * @see IxEthDBPortDefs.h for port definitions
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortAddressSet(IxEthDBPortId portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFilteringPortMaximumFrameSizeSet(IxEthDBPortId portID, UINT32 maximumFrameSize)
- *
- * @brief Set the maximum frame size supported on the given port ID
- *
- * This functions set the maximum frame size supported on a specific port ID
- *
- * - Reentrant - yes
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to configure
- * @param maximumFrameSize UINT32 [in] - maximum frame size to configure
- *
- * @retval IX_ETH_DB_SUCCESS the port is configured
- * @retval IX_ETH_DB_PORT_UNINITIALIZED the port has not been initialized
- * @retval IX_ETH_DB_INVALID_PORT portID is invalid
- * @retval IX_ETH_DB_INVALID_ARG size parameter is out of range
- * @retval IX_ETH_DB_NO_PERMISSION selected port is not an Ethernet NPE
- * @retval IX_FAIL unknown OS or NPE communication error
- *
- * @note
- * This maximum frame size is used to filter the frames based on their
- * destination addresses and the capabilities of the destination port.
- * The mximum value that can be set for a NPE port is 16320.
- * (IX_ETHNPE_ACC_FRAME_LENGTH_MAX)
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringPortMaximumFrameSizeSet(IxEthDBPortId portID, UINT32 maximumFrameSize);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFilteringStaticEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Populate the Ethernet learning/filtering database with a static MAC address
- *
- * Populates the Ethernet learning/filtering database with a static MAC address. The entry will not be subject to aging.
- * If there is an entry (static or dynamic) with the corresponding MAC address on any port this entry will take precedence.
- * Any other entry with the same MAC address will be removed.
- *
- * - Reentrant - yes
- * - ISR Callable - yes
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to add the static address to
- * @param macAddr @ref IxEthDBMacAddr [in] - static MAC address to add
- *
- * @retval IX_ETH_DB_SUCCESS the add was successful
- * @retval IX_ETH_DB_FAIL failed to populate the database entry
- * @retval IX_ETH_DB_BUSY failed due to a temporary busy condition (i.e. lack of CPU cycles), try again later
- * @retval IX_ETH_DB_INVALID_PORT portID is invalid
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> pointer argument
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE learning feature is disabled
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringStaticEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFilteringDynamicEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Populate the Ethernet learning/filtering database with a dynamic MAC address
- *
- * Populates the Ethernet learning/filtering database with a dynamic MAC address. This entry will be subject to normal
- * aging function, if aging is enabled on its port.
- * If there is an entry (static or dynamic) with the same MAC address on any port this entry will take precedence.
- * Any other entry with the same MAC address will be removed.
- *
- * - Reentrant - yes
- * - ISR Callable - yes
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to add the dynamic address to
- * @param macAddr @ref IxEthDBMacAddr [in] - static MAC address to add
- *
- * @retval IX_ETH_DB_SUCCESS the add was successful
- * @retval IX_ETH_DB_FAIL failed to populate the database entry
- * @retval IX_ETH_DB_BUSY failed due to a temporary busy condition (i.e. lack of CPU cycles), try again later
- * @retval IX_ETH_DB_INVALID_PORT portID is invalid
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> pointer argument
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE learning feature is disabled
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringDynamicEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFilteringEntryDelete(IxEthDBMacAddr *macAddr)
- *
- * @brief Removes a MAC address entry from the Ethernet learning/filtering database
- *
- * @param macAddr IxEthDBMacAddr [in] - MAC address to remove
- *
- * - Reentrant - yes
- * - ISR Callable - no
- *
- * @retval IX_ETH_DB_SUCCESS the removal was successful
- * @retval IX_ETH_DB_NO_SUCH_ADDR failed to remove the address (not in the database)
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> pointer argument
- * @retval IX_ETH_DB_BUSY failed due to a temporary busy condition (i.e. lack of CPU cycles), try again later
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringEntryDelete(IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFilteringPortSearch(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Search the Ethernet learning/filtering database for the given MAC address and port ID
- *
- * This functions searches the database for a specific port ID and MAC address. Both the port ID
- * and the MAC address have to match in order for the record to be reported as found.
- *
- * - Reentrant - yes
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to search for
- * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to search for
- *
- * @retval IX_ETH_DB_SUCCESS the record exists in the database
- * @retval IX_ETH_DB_INVALID_ARG invalid macAddr pointer argument
- * @retval IX_ETH_DB_NO_SUCH_ADDR the record was not found in the database
- * @retval IX_ETH_DB_INVALID_PORT portID is invalid
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port ID is not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE learning feature is disabled
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringPortSearch(IxEthDBPortId portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFilteringDatabaseSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Search the Ethernet learning/filtering database for a MAC address and return the port ID
- *
- * Searches the database for a MAC address. The function returns the portID for the
- * MAC address record, if found. If no match is found the function returns IX_ETH_DB_NO_SUCH_ADDR.
- * The portID is only valid if the function finds a match.
- *
- * - Reentrant - yes
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID the address belongs to (populated only on a successful search)
- * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to search for
- *
- * @retval IX_ETH_DB_SUCCESS the record exists in the database
- * @retval IX_ETH_DB_NO_SUCH_ADDR the record was not found in the database
- * @retval IX_ETH_DB_INVALID_ARG invalid macAddr or portID pointer argument(s)
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringDatabaseSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFilteringPortUpdatingSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Search the filtering database for a MAC address, return the port ID and reset the record age
- *
- * Searches the database for a MAC address. The function returns the portID for the
- * MAC address record and resets the entry age to 0, if found.
- * If no match is found the function returns IX_ETH_DB_NO_SUCH_ADDR.
- * The portID is only valid if the function finds a match.
- *
- * - Reentrant - yes
- * - ISR Callable - no
- *
- * @retval IX_ETH_DB_SUCCESS the MAC address was found
- * @retval IX_ETH_DB_NO_SUCH_ADDR the MAC address was not found
- * @retval IX_ETH_DB_INVALID_ARG invalid macAddr or portID pointer argument(s)
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringPortUpdatingSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @def IX_ETH_DB_MAINTENANCE_TIME
- *
- * @brief The @ref ixEthDBDatabaseMaintenance must be called by the user at a frequency of
- * IX_ETH_DB_MAINTENANCE_TIME
- *
- */
-#define IX_ETH_DB_MAINTENANCE_TIME (1 * 60) /* 1 Minute */
-
-/**
- * @ingroup IxEthDB
- *
- * @def IX_ETH_DB_LEARNING_ENTRY_AGE_TIME
- *
- * @brief The define specifies the filtering database age entry time. Static entries older than
- * IX_ETH_DB_LEARNING_ENTRY_AGE_TIME +/- IX_ETH_DB_MAINTENANCE_TIME shall be removed.
- *
- */
-#define IX_ETH_DB_LEARNING_ENTRY_AGE_TIME (15 * 60 ) /* 15 Mins */
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortAgingDisable(IxEthDBPortId portID)
- *
- * @brief Disable the aging function for a specific port
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to disable aging on
- *
- * - Reentrant - yes
- * - ISR Callable - no
- *
- * @retval IX_ETH_DB_SUCCESS aging disabled successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is invalid
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port ID is not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE learning feature is disabled
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortAgingDisable(IxEthDBPortId portID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortAgingEnable(IxEthDBPortId portID)
- *
- * @brief Enable the aging function for a specific port
- *
- * Enables the aging of dynamic MAC address entries stored in the learning/filtering database
- *
- * @note The aging function relies on the @ref ixEthDBDatabaseMaintenance being called with a period of
- * @ref IX_ETH_DB_MAINTENANCE_TIME seconds.
- *
- * - Reentrant - yes
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to enable aging on
- *
- * @retval IX_ETH_DB_SUCCESS aging enabled successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is invalid
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port ID is not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE learning feature is disabled
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortAgingEnable(IxEthDBPortId portID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn void ixEthDBDatabaseMaintenance(void)
- *
- * @brief Performs a maintenance operation on the Ethernet learning/filtering database
- *
- * In order to perform a database maintenance this function must be called every
- * @ref IX_ETH_DB_MAINTENANCE_TIME seconds. It should be called regardless of whether learning is
- * enabled or not.
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @note this function call will be ignored if the learning feature is disabled
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBDatabaseMaintenance(void);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFilteringDatabaseShow(IxEthDBPortId portID)
- *
- * @brief This function displays the Mac Ethernet MAC address filtering tables.
- *
- * It displays the MAC address, port ID, entry type (dynamic/static),and age for
- * the given port ID.
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to display the MAC address entries
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is invalid
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port ID is not initialized
- * @retval IX_ETH_DB_FAIL record browser failed due to an internal busy or lock condition
- *
- * @note this function is deprecated and kept for compatibility reasons; use @ref ixEthDBFilteringDatabaseShowRecords instead
- *
- * @see ixEthDBFilteringDatabaseShowRecords
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringDatabaseShow(IxEthDBPortId portID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn void ixEthDBFilteringDatabaseShowAll(void)
- *
- * @brief Displays the MAC address recorded in the filtering database for all registered
- * ports (see IxEthDBPortDefs.h), grouped by port ID.
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @retval void
- *
- * @note this function is deprecated and kept for compatibility reasons; use @ref ixEthDBFilteringDatabaseShowRecords instead
- *
- * @see ixEthDBFilteringDatabaseShowRecords
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBFilteringDatabaseShowAll(void);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFilteringDatabaseShowRecords(IxEthDBPortId portID, IxEthDBRecordType recordFilter)
- *
- * @brief This function displays per port database records, given a record type filter
- *
- * The supported record type filters are:
- *
- * - IX_ETH_DB_FILTERING_RECORD - displays the non-VLAN filtering records (MAC address, age, static/dynamic)
- * - IX_ETH_DB_FILTERING_VLAN_RECORD - displays the VLAN filtering records (MAC address, age, static/dynamic, VLAN ID, CFI, QoS class)
- * - IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD - displays the previous two types of records
- * - IX_ETH_DB_WIFI_RECORD - displays the WiFi header conversion records (MAC address, optional gateway MAC address) and WiFi header conversion parameters (BBSID, Duration/ID)
- * - IX_ETH_DB_FIREWALL_RECORD - displays the firewall MAC address table and firewall operating mode (white list/black list)
- * - IX_ETH_DB_ALL_RECORD_TYPES - displays all the record types
- * - IX_ETH_DB_NO_RECORD_TYPE - displays only the port status (no records are displayed)
- *
- * Additionally, the status of each port will be displayed, containg the following information: type, capabilities, enabled status,
- * aging enabled status, group membership and maximum frame size.
- *
- * The port ID can either be an actual port or IX_ETH_DB_ALL_PORTS, in which case the requested information
- * will be displayed for all the ports (grouped by port)
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @param portID ID of the port to display information on (use IX_ETH_DB_ALL_PORTS for all the ports)
- * @param recordFilter record type filter
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is invalid
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port ID is not initialized
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringDatabaseShowRecords(IxEthDBPortId portID, IxEthDBRecordType recordFilter);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortDependencyMapSet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap)
- *
- * @brief Sets the dependency port map for a port
- *
- * @param portID ID of the port to set the dependency map to
- * @param dependencyPortMap new dependency map (as bitmap, each bit set indicates a port being included)
- *
- * This function is used to share filtering information between ports.
- * By adding a port into another port's dependency map the target port
- * filtering data will import the filtering data from the port it depends on.
- * Any changes to filtering data for a port - such as adding, updating or removing records -
- * will trigger updates in the filtering information for all the ports depending on
- * on the updated port.
- *
- * For example, if ports 2 and 3 are set in the port 0 dependency map the filtering
- * information for port 0 will also include the filtering information from ports 2 and 3.
- * Adding a record to port 2 will also trigger an update not only on port 2 but also on
- * port 0.
- *
- * The dependency map is a 256 bit array where each bit corresponds to a port corresponding to the
- * bit offset (bit 0 - port 0, bit 1 - port 1 etc). Setting a bit to 1 indicates that the corresponding
- * port is the port map. For example, a dependency port map of 0x14 consists in the ports with IDs 2 and 4.
- * Note that the last bit (offset 255) is reserved and should never be set (it will be automatically
- * cleared by the function).
- *
- * By default, each port has a dependency port map consisting only of itself, i.e.
- *
- * @verbatim
- IxEthDBPortMap portMap;
-
- // clear all ports from port map
- memset(portMap, 0, sizeof (portMap));
-
- // include portID in port map
- portMap[portID / 8] = 1 << (portID % 8);
- @endverbatim
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @note Setting dependency maps is useful for NPE ports, which benefit from automatic updates
- * of filtering information. Setting dependency maps for user-defined ports is not an error
- * but will have no actual effect.
- *
- * @note Including a port in its own dependency map is not compulsory, however note that
- * in this case updating the port will not trigger an update on the port itself, which
- * might not be the intended behavior
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>dependencyPortMap</i> pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Filtering is not available or not enabled for the port
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortDependencyMapSet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortDependencyMapGet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap)
- *
- * @brief Retrieves the dependency port map for a port
- *
- * @param portID ID of the port to set the dependency map to
- * @param dependencyPortMap location where the port dependency map is to be copied
- *
- * This function will copy the port dependency map to a user specified location.
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>dependencyPortMap</i> pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Filtering is not available or not enabled for the port
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortDependencyMapGet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortVlanTagSet(IxEthDBPortId portID, IxEthDBVlanTag vlanTag)
- *
- * @brief Sets the default 802.1Q VLAN tag for a given port
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to set the default VLAN tag to
- * @param vlanTag @ref IxEthDBVlanTag [in] - default 802.1Q VLAN tag
- *
- * The tag format has 16 bits and it is defined in the IEEE802.1Q specification.
- * This tag will be used for tagging untagged frames (if enabled) and classifying
- * unexpedited traffic into an internal traffic class (using the user priority field).
- *
- * <table border="1"> <caption> 802.1Q tag format </caption>
- * <tr> <td> <b> 3 bits <td> <b> 1 bit <td> <b> 12 bits </b>
- * <tr> <td> user priority <td> CFI <td> VID
- * </table>
- *
- * User Priority : Defines user priority, giving eight (2^3) priority levels. IEEE 802.1P defines
- * the operation for these 3 user priority bits
- *
- * CFI : Canonical Format Indicator is always set to zero for Ethernet switches. CFI is used for
- * compatibility reason between Ethernet type network and Token Ring type network. If a frame received
- * at an Ethernet port has a CFI set to 1, then that frame should not be forwarded as it is to an untagged port.
- *
- * VID : VLAN ID is the identification of the VLAN, which is basically used by the standard 802.1Q.
- * It has 12 bits and allow the id entification of 4096 (2^12) VLANs. Of the 4096 possible VIDs, a VID of 0
- * is used to identify priority frames and value 4095 (FFF) is reserved, so the maximum possible VLAN
- * configurations are 4,094.
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_ETH_DB_INVALID_VLAN <i>vlanTag</i> argument does not parse to a valid 802.1Q VLAN tag
- *
- * @note a VLAN ID value of 0 indicates that the port is not part of any VLAN
- * @note the value of the cannonical frame indicator (CFI) field is ignored, the
- * field being used only in frame tagging operations
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanTagSet(IxEthDBPortId portID, IxEthDBVlanTag vlanTag);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortVlanTagGet(IxEthDBPortId portID, IxEthDBVlanTag *vlanTag)
- *
- * @brief Retrieves the default 802.1Q port VLAN tag for a given port (see also @ref ixEthDBPortVlanTagSet)
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to retrieve the default VLAN tag from
- * @param vlanTag @ref IxEthDBVlanTag [out] - location to write the default port 802.1Q VLAN tag to
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid vlanTag pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanTagGet(IxEthDBPortId portID, IxEthDBVlanTag *vlanTag);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBVlanTagSet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag vlanTag)
- *
- * @brief Sets the 802.1Q VLAN tag for a database record
- *
- * @param macAddr MAC address
- * @param vlanTag 802.1Q VLAN tag
- *
- * This function is used together with @ref ixEthDBVlanTagGet to provide MAC-based VLAN classification support.
- * Please note that the bridging application must contain specific code to make use of this feature (see below).
- *
- * VLAN tags can be set only in IX_ETH_DB_FILTERING_RECORD or IX_ETH_DB_FILTERING_VLAN_RECORD type records.
- * If to an IX_ETH_DB_FILTERING_RECORD type record is added a VLAN tag the record type is automatically
- * changed to IX_ETH_DB_FILTERING_VLAN_RECORD. Once this has occurred the record type will never
- * revert to a non-VLAN type (unless deleted and re-added).
- *
- * Record types used for different purposes (such as IX_ETH_DB_WIFI_RECORD) will be ignored by
- * this function.
- *
- * After using this function to associate a VLAN ID with a MAC address the VLAN ID can be extracted knowing the
- * MAC address using @ref ixEthDBVlanTagGet. This mechanism can be used to implement MAC-based VLAN classification
- * if a bridging application searches for the VLAN tag when receiving a frame based on the source MAC address
- * (contained in the <i>ixp_ne_src_mac</i> field of the buffer header).
- * If found in the database, the application can instruct the NPE to tag the frame by writing the VLAN tag
- * in the <i>ixp_ne_vlan_tci</i> field of the buffer header. This way the NPE will inspect the Egress tagging
- * rule associated with the given VLAN ID on the Tx port and tag the frame if Egress tagging on the VLAN is
- * allowed. Additionally, Egress tagging can be forced by setting the <i>ixp_ne_tx_flags.tag_over</i> and
- * <i>ixp_ne_tx_flags.tag_mode</i> flags in the buffer header.
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @note this function will <b>not</b> add a filtering record, it can only be used to update an existing one
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> pointer
- * @retval IX_ETH_DB_NO_SUCH_ADDR a filtering record with the specified MAC address was not found
- * @retval IX_ETH_DB_INVALID_VLAN <i>vlanTag</i> argument does not parse to a valid 802.1Q VLAN tag
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBVlanTagSet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag vlanTag);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn ixEthDBVlanTagGet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag *vlanTag)
- *
- * @brief Retrieves the 802.1Q VLAN tag from a database record given the record MAC address
- *
- * @param macAddr MAC address
- * @param vlanTag location to write the record 802.1Q VLAN tag to
- *
- * @note VLAN tags can be retrieved only from IX_ETH_DB_FILTERING_VLAN_RECORD type records
- *
- * This function is used together with ixEthDBVlanTagSet to provide MAC-based VLAN classification support.
- * Please note that the bridging application must contain specific code to make use of this feature (see @ref ixEthDBVlanTagSet).
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> or <i>vlanTag</i> pointer
- * @retval IX_ETH_DB_NO_SUCH_ADDR a filtering record with the specified MAC address was not found
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBVlanTagGet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag *vlanTag);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortVlanMembershipAdd(IxEthDBPortId portID, IxEthDBVlanId vlanID)
- *
- * @brief Adds a VLAN ID to a port's VLAN membership table
- *
- * Adding a VLAN ID to a port's VLAN membership table will cause frames tagged with the specified
- * VLAN ID to be accepted by the frame filter, if Ingress VLAN membership filtering is enabled.
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to add the VLAN ID membership to
- * @param vlanID @ref IxEthDBVlanId [in] - VLAN ID to be added to the port membership table
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_VLAN vlanID is not a valid VLAN ID
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- *
- * @note A port's default VLAN ID is always in its own membership table, hence there
- * is no need to explicitly add it using this function (although it is not an error
- * to do so)
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanMembershipAdd(IxEthDBPortId portID, IxEthDBVlanId vlanID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortVlanMembershipRangeAdd(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax)
- *
- * @brief Adds a VLAN ID range to a port's VLAN membership table
- *
- * All the VLAN IDs in the specified range will be added to the port VLAN
- * membership table, including the range start and end VLAN IDs. Tagged frames with
- * VLAN IDs in the specified range will be accepted by the frame filter, if Ingress VLAN
- * membership filtering is enabled.
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to add the VLAN membership range into
- * @param vlanIDMin @ref IxEthDBVlanId [in] - start of the VLAN ID range
- * @param vlanIDMax @ref IxEthDBVlanId [in] - end of the VLAN ID range
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_VLAN the specified VLAN IDs are invalid or do not constitute a range
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- *
- * @note Is is valid to use the same VLAN ID for both vlanIDMin and vlanIDMax, in which case this
- * function will behave as @ref ixEthDBPortVlanMembershipAdd
- *
- * @note A port's default VLAN ID is always in its own membership table, hence there is no need
- * to explicitly add it using this function (although it is not an error to do so)
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanMembershipRangeAdd(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortVlanMembershipRemove(IxEthDBPortId portID, IxEthDBVlanId vlanID)
- *
- * @brief Removes a VLAN ID from a port's VLAN membership table
- *
- * Frames tagged with a VLAN ID which is not in a port's VLAN membership table
- * will be discarded by the frame filter, if Ingress membership filtering is enabled.
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to remove the VLAN ID membership from
- * @param vlanID @ref IxEthDBVlanId [in] - VLAN ID to be removed from the port membership table
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_INVALID_VLAN vlanID is not a valid VLAN ID
- * @retval IX_ETH_DB_NO_PERMISSION attempted to remove the default VLAN ID
- * from the port membership table (vlanID was set to the default port VLAN ID)
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- *
- * @note A port's default VLAN ID cannot be removed from the port's membership
- * table; attempting it will return IX_ETH_DB_NO_PERMISSION
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanMembershipRemove(IxEthDBPortId portID, IxEthDBVlanId vlanID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortVlanMembershipRangeRemove(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax)
- *
- * @brief Removes a VLAN ID range from a port's VLAN membership table
- *
- * All the VLAN IDs in the specified range will be removed from the port VLAN
- * membership table, including the range start and end VLAN IDs. Tagged frames
- * with VLAN IDs in the range will be discarded by the frame filter, if Ingress
- * membership filtering is enabled.
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to remove the VLAN membership range from
- * @param vlanIDMin @ref IxEthDBVlanId [in] - start of the VLAN ID range
- * @param vlanIDMax @ref IxEthDBVlanId [in] - end of the VLAN ID range
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_VLAN the specified VLAN IDs are invalid or do not constitute a range
- * @retval IX_ETH_DB_NO_PERMISSION attempted to remove the default VLAN ID
- * from the port membership table (both vlanIDMin and vlanIDMax were set to the default port VLAN ID)
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- *
- * @note Is is valid to use the same VLAN ID for both vlanIDMin and vlanIDMax, in which case
- * function will behave as @ref ixEthDBPortVlanMembershipRemove
- *
- * @note If the given range overlaps the default port VLAN ID this function
- * will remove all the VLAN IDs in the range except for the port VLAN ID from its
- * own membership table. This situation will be silently dealt with (no error message
- * will be returned) as long as the range contains more than one value (i.e. at least
- * one other value, apart from the default port VLAN ID). If the function is called
- * with the vlanIDMin and vlanIDMax parameters both set to the port default VLAN ID, the
- * function will infer that an attempt was specifically made to remove the default port
- * VLAN ID from the port membership table, in which case the return value will be
- * IX_ETH_DB_NO_PERMISSION.
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanMembershipRangeRemove(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortVlanMembershipSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet)
- *
- * @brief Sets a port's VLAN membership table
- *
- * Sets a port's VLAN membership table from a complete VLAN table containing all the possible
- * 4096 VLAN IDs. The table format is an array containing 4096 bits (512 bytes), where each bit
- * indicates whether the VLAN at that bit index is in the port's membership list (if set) or
- * not (unset).
- *
- * The bit at index 0, indicating VLAN ID 0, indicates no VLAN membership and therefore no
- * other bit must be set if bit 0 is set.
- *
- * The bit at index 4095 is reserved and should never be set (it will be ignored if set).
- *
- * The bit referencing the same VLAN ID as the default port VLAN ID should always be set, as
- * the membership list must contain at least the default port VLAN ID.
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to set the VLAN membership table to
- * @param vlanSet @ref IxEthDBVlanSet [in] - pointer to the VLAN membership table
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>vlanSet</i> pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanMembershipSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortVlanMembershipGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet)
- *
- * @brief Retrieves a port's VLAN membership table
- *
- * Retrieves the complete VLAN membership table from a port, containing all the possible
- * 4096 VLAN IDs. The table format is an array containing 4096 bits (512 bytes), where each bit
- * indicates whether the VLAN at that bit index is in the port's membership list (if set) or
- * not (unset).
- *
- * The bit at index 0, indicating VLAN ID 0, indicates no VLAN membership and therefore no
- * other bit will be set if bit 0 is set.
- *
- * The bit at index 4095 is reserved and will not be set (it will be ignored if set).
- *
- * The bit referencing the same VLAN ID as the default port VLAN ID will always be set, as
- * the membership list must contain at least the default port VLAN ID.
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to retrieve the VLAN membership table from
- * @param vlanSet @ref IxEthDBVlanSet [out] - pointer a location where the VLAN membership table will be
- * written to
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>vlanSet</i> pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanMembershipGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBAcceptableFrameTypeSet(IxEthDBPortId portID, IxEthDBFrameFilter frameFilter)
- *
- * @brief Sets a port's acceptable frame type filter
- *
- * The acceptable frame type is one (or a combination) of the following values:
- * - IX_ETH_DB_ACCEPT_ALL_FRAMES - accepts all the frames
- * - IX_ETH_DB_UNTAGGED_FRAMES - accepts untagged frames
- * - IX_ETH_DB_VLAN_TAGGED_FRAMES - accepts tagged frames
- * - IX_ETH_DB_PRIORITY_TAGGED_FRAMES - accepts tagged frames with VLAN ID set to 0 (no VLAN membership)
- *
- * Except for using the exact values given above only the following combinations are valid:
- * - IX_ETH_DB_UNTAGGED_FRAMES | IX_ETH_DB_VLAN_TAGGED_FRAMES
- * - IX_ETH_DB_UNTAGGED_FRAMES | IX_ETH_DB_PRIORITY_TAGGED_FRAMES
- *
- * Please note that IX_ETH_DB_UNTAGGED_FRAMES | IX_ETH_DB_VLAN_TAGGED_FRAMES is equivalent
- * to IX_ETH_DB_ACCEPT_ALL_FRAMES.
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @note by default the acceptable frame type filter is set to IX_ETH_DB_ACCEPT_ALL_FRAMES
- *
- * @note setting the acceptable frame type to PRIORITY_TAGGED_FRAMES is internally
- * accomplished by changing the frame filter to VLAN_TAGGED_FRAMES and setting the
- * VLAN membership list to include only VLAN ID 0; the membership list will need
- * to be restored manually to an appropriate value if the acceptable frame type
- * filter is changed back to ACCEPT_ALL_FRAMES or VLAN_TAGGED_FRAMES; failure to do so
- * will filter all VLAN traffic bar frames tagged with VLAN ID 0
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to set the acceptable frame type filter to
- * @param frameFilter @ref IxEthDBFrameFilter [in] - acceptable frame type filter
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid frame type filter
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBAcceptableFrameTypeSet(IxEthDBPortId portID, IxEthDBFrameFilter frameFilter);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBAcceptableFrameTypeGet(IxEthDBPortId portID, IxEthDBFrameFilter *frameFilter)
- *
- * @brief Retrieves a port's acceptable frame type filter
- *
- * For a description of the acceptable frame types see @ref ixEthDBAcceptableFrameTypeSet
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to retrieve the acceptable frame type filter from
- * @param frameFilter @ref IxEthDBFrameFilter [out] - location to store the acceptable frame type filter
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>frameFilter</i> pointer argument
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBAcceptableFrameTypeGet(IxEthDBPortId portID, IxEthDBFrameFilter *frameFilter);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPriorityMappingTableSet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable)
- *
- * @brief Sets a port's priority mapping table
- *
- * The priority mapping table is an 8x2 table mapping a QoS (user) priority into an internal
- * traffic class. There are 8 valid QoS priorities (0..7, 0 being the lowest) which can be
- * mapped into one of the 4 available traffic classes (0..3, 0 being the lowest).
- * If a custom priority mapping table is not specified using this function the following
- * default priority table will be used (as per IEEE 802.1Q and IEEE 802.1D):
- *
- * <table border="1"> <caption> QoS traffic classes </caption>
- * <tr> <td> <b> QoS priority <td> <b> Default traffic class <td> <b> Traffic type </b>
- * <tr> <td> 0 <td> 1 <td> Best effort, default class for unexpedited traffic
- * <tr> <td> 1 <td> 0 <td> Background traffic
- * <tr> <td> 2 <td> 0 <td> Spare bandwidth
- * <tr> <td> 3 <td> 1 <td> Excellent effort
- * <tr> <td> 4 <td> 2 <td> Controlled load
- * <tr> <td> 5 <td> 2 <td> Video traffic
- * <tr> <td> 6 <td> 3 <td> Voice traffic
- * <tr> <td> 7 <td> 3 <td> Network control
- * </table>
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID of the port to set the priority mapping table to
- * @param priorityTable @ref IxEthDBPriorityTable [in] - location of the user priority table
- *
- * @note The provided table will be copied into internal data structures in EthDB and
- * can be deallocated by the called after this function has completed its execution, if
- * so desired
- *
- * @warning The number of available traffic classes differs depending on the NPE images
- * and queue configuration. Check IxEthDBQoS.h for up-to-date information on the availability of
- * traffic classes. Note that specifiying a traffic class in the priority map which exceeds
- * the system availability will produce an IX_ETH_DB_INVALID_PRIORITY return error code and no
- * priority will be remapped.
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>priorityTable</i> pointer
- * @retval IX_ETH_DB_INVALID_PRIORITY at least one priority value exceeds
- * the current number of available traffic classes
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPriorityMappingTableSet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPriorityMappingTableGet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable)
- *
- * @brief Retrieves a port's priority mapping table
- *
- * The priority mapping table for the given port will be copied in the location
- * specified by the caller using "priorityTable"
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @param portID ID @ref IxEthDBPortId [in] - of the port to retrieve the priority mapping table from
- * @param priorityTable @ref IxEthDBPriorityTable [out] - pointer to a user specified location where the table will be copied to
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid priorityTable pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPriorityMappingTableGet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPriorityMappingClassSet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority trafficClass)
- *
- * @brief Sets one QoS/user priority => traffic class mapping in a port's priority mapping table
- *
- * This function establishes a mapping between a user (QoS) priority and an internal traffic class.
- * The mapping will be saved in the port's priority mapping table. Use this function when not all
- * the QoS priorities need remapping (see also @ref ixEthDBPriorityMappingTableSet)
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to set the mapping to
- * @param userPriority @ref IxEthDBPriority [in] - user (QoS) priority, between 0 and 7 (0 being the lowest)
- * @param trafficClass @ref IxEthDBPriority [in] - internal traffic class, between 0 and 3 (0 being the lowest)
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_PRIORITY <i>userPriority</i> out of range or
- * <i>trafficClass</i> is beyond the number of currently available traffic classes
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPriorityMappingClassSet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority trafficClass);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPriorityMappingClassGet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority *trafficClass)
- *
- * @brief Retrieves one QoS/user priority => traffic class mapping in a port's priority mapping table
- *
- * This function retrieves the internal traffic class associated with a QoS (user) priority from a given
- * port's priority mapping table. Use this function when not all the QoS priority mappings are
- * required (see also @ref ixEthDBPriorityMappingTableGet)
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to set the mapping to
- * @param userPriority @ref IxEthDBPriority [in] - user (QoS) priority, between 0 and 7 (0 being the lowest)
- * @param trafficClass @ref IxEthDBPriority [out] - location to write the corresponding internal traffic class to
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_PRIORITY invalid userPriority value (out of range)
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>trafficClass</i> pointer argument
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPriorityMappingClassGet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority *trafficClass);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL enabled)
- *
- * @brief Enables or disables Egress VLAN tagging for a port and a given VLAN
- *
- * This function enables or disables Egress VLAN tagging for the given port and VLAN ID.
- * If the VLAN tagging for a certain VLAN ID is enabled then all the frames to be
- * transmitted on the given port tagged with the same VLAN ID will be transmitted in a tagged format.
- * If tagging is not enabled for the given VLAN ID, the VLAN tag from the frames matching
- * this VLAN ID will be removed (the frames will be untagged).
- *
- * VLAN ID 4095 is reserved and should never be used with this function.
- * VLAN ID 0 has the special meaning of "No VLAN membership" and it is used in this
- * context to allow the port to send priority-tagged frames or not.
- *
- * By default, no Egress VLAN tagging is enabled on any port.
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to enable or disable the VLAN ID Egress tagging on
- * @param vlanID @ref IxEthDBVlanId [in] - VLAN ID to be matched against outgoing frames
- * @param enabled BOOL [in] - true to enable Egress VLAN tagging on the port and given VLAN, and
- * false to disable Egress VLAN tagging
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_VLAN invalid VLAN ID (out of range)
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL enabled);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL *enabled)
- *
- * @brief Retrieves the Egress VLAN tagging enabling status for a port and VLAN ID
- *
- * @param portID [in] - ID of the port to extract the Egress VLAN ID tagging status from
- * @param vlanID VLAN [in] - ID whose tagging status is to be extracted
- * @param enabled [in] - user-specifed location where the status is copied to; following
- * the successfull execution of this function the value will be true if Egress VLAN
- * tagging is enabled for the given port and VLAN ID, and false otherwise
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @see ixEthDBEgressVlanEntryTaggingEnabledGet
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_VLAN invalid VLAN ID (out of range)
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>enabled</i> argument pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL *enabled);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBEgressVlanRangeTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax, BOOL enabled)
- *
- * @brief Enables or disables Egress VLAN tagging for a port and given VLAN range
- *
- * This function is very similar to @ref ixEthDBEgressVlanEntryTaggingEnabledSet with the
- * difference that it can manipulate the Egress tagging status on multiple VLAN IDs,
- * defined by a contiguous range. Note that both limits in the range are explicitly
- * included in the execution of this function.
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to enable or disable the VLAN ID Egress tagging on
- * @param vlanIDMin @ref IxEthDBVlanId [in] - start of the VLAN range to be matched against outgoing frames
- * @param vlanIDMax @ref IxEthDBVlanId [in] - end of the VLAN range to be matched against outgoing frames
- * @param enabled BOOL [in] - true to enable Egress VLAN tagging on the port and given VLAN range,
- * and false to disable Egress VLAN tagging
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_VLAN invalid VLAN ID (out of range), or do not constitute a range
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_ETH_DB_NO_PERMISSION attempted to explicitly remove the default port VLAN ID from the tagging table
- * @retval IX_FAIL unknown OS or NPE communication error
- *
- * @note Specifically removing the default port VLAN ID from the Egress tagging table by setting both vlanIDMin and vlanIDMax
- * to the VLAN ID portion of the PVID is not allowed by this function and will return IX_ETH_DB_NO_PERMISSION.
- * However, this can be circumvented, should the user specifically desire this, by either using a
- * larger range (vlanIDMin < vlanIDMax) or by using ixEthDBEgressVlanEntryTaggingEnabledSet.
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBEgressVlanRangeTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax, BOOL enabled);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBEgressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet)
- *
- * @brief Sets the complete Egress VLAN tagging table for a port
- *
- * This function is used to set the VLAN tagging/untagging per VLAN ID for a given port
- * covering the entire VLAN ID range (0..4094). The <i>vlanSet</i> parameter is a 4096
- * bit array, each bit indicating the Egress behavior for the corresponding VLAN ID.
- * If a bit is set then outgoing frames with the corresponding VLAN ID will be transmitted
- * with the VLAN tag, otherwise the frame will be transmitted without the VLAN tag.
- *
- * Bit 0 has a special significance, indicating tagging or tag removal for priority-tagged
- * frames.
- *
- * Bit 4095 is reserved and should never be set (it will be ignored if set).
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port whose Egress VLAN tagging behavior is set
- * @param vlanSet @ref IxEthDBVlanSet [in] - 4096 bit array controlling per-VLAN tagging and untagging
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>vlanSet</i> pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- *
- * @warning This function will automatically add the default port VLAN ID to the Egress tagging table
- * every time it is called. The user should manually call ixEthDBEgressVlanEntryTaggingEnabledSet to
- * prevent tagging on the default port VLAN ID if the default behavior is not intended.
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBEgressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBEgressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet)
- *
- * @brief Retrieves the complete Egress VLAN tagging table from a port
- *
- * This function copies the 4096 bit table controlling the Egress VLAN tagging into a user specified
- * area. Each bit in the array indicates whether tagging for the corresponding VLAN (the bit position
- * in the array) is enabled (the bit is set) or not (the bit is unset).
- *
- * Bit 4095 is reserved and should not be set (it will be ignored if set).
- *
- * @see ixEthDBEgressVlanTaggingEnabledSet
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port whose Egress VLAN tagging behavior is retrieved
- * @param vlanSet @ref IxEthDBVlanSet [out] - user location to copy the Egress tagging table into; should have
- * room to store 4096 bits (512 bytes)
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>vlanSet</i> pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBEgressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBIngressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBTaggingAction taggingAction)
- *
- * @brief Sets the Ingress VLAN tagging behavior for a port
- *
- * A port's Ingress tagging behavior is controlled by the taggingAction parameter,
- * which can take one of the following values:
- *
- * - IX_ETH_DB_PASS_THROUGH - leaves the frame unchanged (does not add or remove the VLAN tag)
- * - IX_ETH_DB_ADD_TAG - adds the VLAN tag if not present, using the default port VID
- * - IX_ETH_DB_REMOVE_TAG - removes the VLAN tag if present
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port whose Ingress VLAN tagging behavior is set
- * @param taggingAction @ref IxEthDBTaggingAction [in] - tagging behavior for the port
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>taggingAction</i> argument
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBIngressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBTaggingAction taggingAction);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBIngressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBTaggingAction *taggingAction)
- *
- * @brief Retrieves the Ingress VLAN tagging behavior from a port (see @ref ixEthDBIngressVlanTaggingEnabledSet)
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port whose Ingress VLAN tagging behavior is set
- * @param taggingAction @ref IxEthDBTaggingAction [out] - location where the tagging behavior for the port is written to
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>taggingAction</i> pointer argument
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBIngressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBTaggingAction *taggingAction);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBVlanPortExtractionEnable(IxEthDBPortId portID, BOOL enable)
- *
- * @brief Enables or disables port ID extraction
- *
- * This feature can be used in the situation when a multi-port device (e.g. a switch)
- * is connected to an IXP4xx port and the device can provide incoming frame port
- * identification by tagging the TPID field in the Ethernet frame. Enabling
- * port extraction will instruct the NPE to copy the TPID field from the frame and
- * place it in the <i>ixp_ne_src_port</i> of the <i>ixp_buf</i> header. In addition,
- * the NPE restores the TPID field to 0.
- *
- * If the frame is not tagged the NPE will fill the <i>ixp_ne_src_port</i> with the
- * port ID of the MII interface the frame was received from.
- *
- * The TPID field is the least significant byte of the type/length field, which is
- * normally set to 0x8100 for 802.1Q-tagged frames.
- *
- * This feature is disabled by default.
- *
- * @param portID ID of the port to configure port ID extraction on
- * @param enable true to enable port ID extraction and false to disable it
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBVlanPortExtractionEnable(IxEthDBPortId portID, BOOL enable);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFeatureCapabilityGet(IxEthDBPortId portID, IxEthDBFeature *featureSet)
- *
- * @brief Retrieves the feature capability set for a port
- *
- * This function retrieves the feature capability set for a port or the common capabilities shared between all
- * the ports, writing the feature capability set in a user specified location.
- *
- * The feature capability set will consist of a set formed by OR-ing one or more of the following values:
- * - IX_ETH_DB_LEARNING - Learning feature; enables EthDB to learn MAC address (filtering) records, including 802.1Q enabled records
- * - IX_ETH_DB_FILTERING - Filtering feature; enables EthDB to communicate with the NPEs for downloading filtering information in the NPEs; depends on the learning feature
- * - IX_ETH_DB_VLAN_QOS - VLAN/QoS feature; enables EthDB to configure NPEs to operate in VLAN/QoS aware modes
- * - IX_ETH_DB_FIREWALL - Firewall feature; enables EthDB to configure NPEs to operate in firewall mode, using white/black address lists
- * - IX_ETH_DB_SPANNING_TREE_PROTOCOL - Spanning tree protocol feature; enables EthDB to configure the NPEs as STP nodes
- * - IX_ETH_DB_WIFI_HEADER_CONVERSION - WiFi 802.3 to 802.11 header conversion feature; enables EthDB to handle WiFi conversion data
- *
- * Note that EthDB provides only the LEARNING feature for non-NPE ports.
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to retrieve the capability set for
- * (use IX_ETH_DB_ALL_PORTS to retrieve the common capabilities shared between all the ports)
- * @param featureSet @ref IxEthDBFeature [out] - location where the capability set will be written to
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>featureSet</i> pointer
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFeatureCapabilityGet(IxEthDBPortId portID, IxEthDBFeature *featureSet);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature, BOOL enabled)
- *
- * @brief Enables or disables one or more EthDB features
- *
- * Selects one or more features (see @ref ixEthDBFeatureCapabilityGet for a description of the supported
- * features) to be enabled or disabled on the selected port (or all the ports).
- *
- * Note that some features are mutually incompatible:
- * - IX_ETH_DB_FILTERING is incompatible with IX_ETH_DB_WIFI_HEADER_CONVERSION
- *
- * Also note that some features require other features to be enabled:
- * - IX_ETH_DB_FILTERING requires IX_ETH_DB_LEARNING
- *
- * This function will either enable the entire selected feature set for the selected port (or all the ports),
- * in which case it will return IX_ETH_DB_SUCCESS, or in case of error it will not enable any feature at all
- * and return an appropriate error message.
- *
- * The following features are enabled by default (for ports with the respective capability),
- * for compatibility reasons with previous versions of CSR:
- * - IX_ETH_DB_LEARNING
- * - IX_ETH_DB_FILTERING
- *
- * All other features are disabled by default and require manual enabling using ixEthDBFeatureEnable.
- *
- * <b>Default settings for VLAN, QoS, Firewall and WiFi header conversion features:</b>
- *
- * <i>VLAN</i>
- *
- * When the VLAN/QoS feature is enabled for a port for the first time the default VLAN behavior
- * of the port is set to be as <b>permissive</b> (it will accept all the frames) and
- * <b>non-interferential</b> (it will not change any frames) as possible:
- * - the port VLAN ID (VID) is set to 0
- * - the Ingress acceptable frame filter is set to accept all frames
- * - the VLAN port membership is set to the complete VLAN range (0 - 4094)
- * - the Ingress tagging mode is set to pass-through (will not change frames)
- * - the Egress tagging mode is to send tagged frames in the entire VLAN range (0 - 4094)
- *
- * Note that further disabling and re-enabling the VLAN feature for a given port will not reset the port VLAN behavior
- * to the settings listed above. Any VLAN settings made by the user are kept.
- *
- * <i>QoS</i>
- *
- * The following default priority mapping table will be used (as per IEEE 802.1Q and IEEE 802.1D):
- *
- * <table border="1"> <caption> QoS traffic classes </caption>
- * <tr> <td> <b> QoS priority <td> <b> Default traffic class <td> <b> Traffic type </b>
- * <tr> <td> 0 <td> 1 <td> Best effort, default class for unexpedited traffic
- * <tr> <td> 1 <td> 0 <td> Background traffic
- * <tr> <td> 2 <td> 0 <td> Spare bandwidth
- * <tr> <td> 3 <td> 1 <td> Excellent effort
- * <tr> <td> 4 <td> 2 <td> Controlled load
- * <tr> <td> 5 <td> 2 <td> Video traffic
- * <tr> <td> 6 <td> 3 <td> Voice traffic
- * <tr> <td> 7 <td> 3 <td> Network control
- * </table>
- *
- * <i> Firewall </i>
- *
- * The port firewall is configured by default in <b>black-list mode</b>, and the firewall address table is empty.
- * This means the firewall will not filter any frames until the feature is configured and the firewall table is
- * downloaded to the NPE.
- *
- * <i> Spanning Tree </i>
- *
- * The port is set to <b>STP unblocked mode</b>, therefore it will accept all frames until re-configured.
- *
- * <i> WiFi header conversion </i>
- *
- * The WiFi header conversion database is empty, therefore no actual header conversion will take place until this
- * feature is configured and the conversion table downloaded to the NPE.
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to enable or disable the features on (use IX_ETH_DB_ALL_PORTS for all the ports)
- * @param feature @ref IxEthDBFeature [in] - feature or feature set to enable or disable
- * @param enabled BOOL [in] - true to enable the feature and false to disable it
- *
- * @note Certain features, from a functional point of view, cannot be disabled as such at NPE level;
- * when such features are set to <i>disabled</i> using the EthDB API they will be configured in such
- * a way to determine a behavior equivalent to the feature being disabled. As well as this, disabled
- * features cannot be configured or accessed via the EthDB API (except for getting their status).
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_NO_PERMISSION attempted to enable mutually exclusive features,
- * or a feature that depends on another feature which is not present or enabled
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE at least one of the features selected is unavailable
- * @retval IX_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature, BOOL enabled);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFeatureStatusGet(IxEthDBPortId portID, IxEthDBFeature feature, BOOL *present, BOOL *enabled)
- *
- * @brief Retrieves the availability and status of a feature set
- *
- * This function returns the availability and status for a feature set.
- * Note that if more than one feature is selected (e.g. IX_ETH_DB_LEARNING | IX_ETH_DB_FILTERING)
- * the "present" and "enabled" return values will be set to true only if all the features in the
- * feature set are present and enabled (not only some).
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port
- * @param feature @ref IxEthDBFeature [in] - identifier of the feature to retrieve the status for
- * @param present BOOL [out] - location where a boolean flag indicating whether this feature is present will be written to
- * @param enabled BOOL [out] - location where a boolean flag indicating whether this feature is enabled will be written to
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG either <i>present</i> or <i>enabled</i> pointer argument is invalid
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFeatureStatusGet(IxEthDBPortId portID, IxEthDBFeature feature, BOOL *present, BOOL *enabled);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFeaturePropertyGet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, IxEthDBPropertyType *type, void *value)
- *
- * @brief Retrieves the value of a feature property
- *
- * The EthDB features usually contain feature-specific properties describing or
- * controlling how the feature operates. While essential properties (e.g. the
- * firewall operating mode) have their own API, secondary properties can be
- * retrieved using this function.
- *
- * Properties can be read-only or read-write. ixEthDBFeaturePropertyGet operates with
- * both types of features.
- *
- * Properties have types associated with them. A descriptor indicating the property
- * type is returned in the <i>type</i> argument for convenience.
- *
- * The currently supported properties and their corresponding features are as follows:
- *
- * <table border="1"> <caption> Properties for IX_ETH_DB_VLAN_QOS </caption>
- * <tr> <td> <b> Property identifier <td> <b> Property type <td> <b> Property value <td> <b> Read-Only </b>
- * <tr> <td> IX_ETH_DB_QOS_TRAFFIC_CLASS_COUNT_PROPERTY <td> IX_ETH_DB_INTEGER_PROPERTY <td> number of internal traffic classes <td> Yes
- * <tr> <td> IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY <td> IX_ETH_DB_INTEGER_PROPERTY <td> queue assignment for traffic class 0 <td> Yes
- * <tr> <td> IX_ETH_DB_QOS_TRAFFIC_CLASS_1_RX_QUEUE_PROPERTY <td> IX_ETH_DB_INTEGER_PROPERTY <td> queue assignment for traffic class 1 <td> Yes
- * <tr> <td> IX_ETH_DB_QOS_TRAFFIC_CLASS_2_RX_QUEUE_PROPERTY <td> IX_ETH_DB_INTEGER_PROPERTY <td> queue assignment for traffic class 2 <td> Yes
- * <tr> <td> IX_ETH_DB_QOS_TRAFFIC_CLASS_3_RX_QUEUE_PROPERTY <td> IX_ETH_DB_INTEGER_PROPERTY <td> queue assignment for traffic class 3 <td> Yes
- * <tr> <td> IX_ETH_DB_QOS_TRAFFIC_CLASS_4_RX_QUEUE_PROPERTY <td> IX_ETH_DB_INTEGER_PROPERTY <td> queue assignment for traffic class 4 <td> Yes
- * <tr> <td> IX_ETH_DB_QOS_TRAFFIC_CLASS_5_RX_QUEUE_PROPERTY <td> IX_ETH_DB_INTEGER_PROPERTY <td> queue assignment for traffic class 5 <td> Yes
- * <tr> <td> IX_ETH_DB_QOS_TRAFFIC_CLASS_6_RX_QUEUE_PROPERTY <td> IX_ETH_DB_INTEGER_PROPERTY <td> queue assignment for traffic class 6 <td> Yes
- * <tr> <td> IX_ETH_DB_QOS_TRAFFIC_CLASS_7_RX_QUEUE_PROPERTY <td> IX_ETH_DB_INTEGER_PROPERTY <td> queue assignment for traffic class 7 <td> Yes
- * </table>
- *
- * @see ixEthDBFeaturePropertySet
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port
- * @param feature @ref IxEthDBFeature [in] - EthDB feature for which the property is retrieved
- * @param property @ref IxEthDBProperty [in] - property identifier
- * @param type @ref IxEthDBPropertyType [out] - location where the property type will be stored
- * @param value void [out] - location where the property value will be stored
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_INVALID_ARG invalid property identifier, <i>type</i> or <i>value</i> pointer arguments
- * @retval IX_ETH_DB_FAIL incorrect property value or unknown error
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFeaturePropertyGet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, IxEthDBPropertyType *type, void *value);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFeaturePropertySet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, void *value)
- *
- * @brief Sets the value of a feature property
- *
- * Unlike @ref ixEthDBFeaturePropertyGet, this function operates only with read-write properties
- *
- * The currently supported properties and their corresponding features are as follows:
- *
- * - IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE (for IX_ETH_DB_VLAN_QOS): freezes the availability of traffic classes
- * to the number of traffic classes currently in use
- *
- * Note that this function creates deep copies of the property values; once the function is invoked the client
- * can free or reuse the memory area containing the original property value.
- *
- * Copy behavior for different property types is defined as follows:
- *
- * - IX_ETH_DB_INTEGER_PROPERTY - 4 bytes are copied from the source location
- * - IX_ETH_DB_STRING_PROPERTY - the source string will be copied up to the NULL '\0' string terminator, maximum of 255 characters
- * - IX_ETH_DB_MAC_ADDR_PROPERTY - 6 bytes are copied from the source location
- * - IX_ETH_DB_BOOL_PROPERTY - 4 bytes are copied from the source location; the only allowed values are true (1L) and false (0L)
- *
- * @see ixEthDBFeaturePropertySet
- *
- * @warning IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE is provided for EthAcc internal use;
- * do not attempt to set this property directly
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port
- * @param feature @ref IxEthDBFeature [in] - EthDB feature for which the property is set
- * @param property @ref IxEthDBProperty [in] - property identifier
- * @param value void [in] - location where the property value is to be copied from
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_INVALID_ARG invalid property identifier, <i>value</i> pointer, or invalid property value
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFeaturePropertySet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, void *value);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBDatabaseClear(IxEthDBPortId portID, IxEthDBRecordType recordType)
- *
- * @brief Deletes a set of record types from the Ethernet Database
- *
- * This function deletes all the records of certain types (specified in the recordType filter)
- * associated with a port. Additionally, the IX_ETH_DB_ALL_PORTS value can be used as port ID
- * to indicate that the specified record types should be deleted for all the ports.
- *
- * The record type filter can be an ORed combination of the following types:
- *
- * <caption> Record types </caption>
- * - IX_ETH_DB_FILTERING_RECORD <table><caption> Filtering record </caption>
- * <tr><td> MAC address <td> static/dynamic type <td> age </tr>
- * </table>
- *
- * - IX_ETH_DB_FILTERING_VLAN_RECORD <table><caption> VLAN-enabled filtering record </caption>
- * <tr><td> MAC address <td> static/dynamic type <td> age <td> 802.1Q tag </tr>
- * </table>
- *
- * - IX_ETH_DB_WIFI_RECORD <table><caption> WiFi header conversion record </caption>
- * <tr><td> MAC address <td> optional gateway MAC address <td> </tr>
- * </table>
- *
- * - IX_ETH_DB_FIREWALL_RECORD <table><caption> Firewall record </caption>
- * <tr><td> MAC address </tr>
- * </table>
- * - IX_ETH_DB_ALL_RECORD_TYPES
- *
- * Any combination of the above types is valid e.g.
- *
- * (IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD | IX_ETH_DB_FIREWALL_RECORD),
- *
- * although some might be redundant (it is not an error to do so) e.g.
- *
- * (IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_ALL_RECORD_TYPES)
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port
- * @param recordType @ref IxEthDBRecordType [in] - record type filter
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>recordType</i> filter
- *
- * @note If the record type filter contains any unrecognized value (hence the
- * IX_ETH_DB_INVALID_ARG error value is returned) no actual records will be deleted.
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBDatabaseClear(IxEthDBPortId portID, IxEthDBRecordType recordType);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBWiFiStationEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Adds an "Access Point to Station" record to the database, for 802.3 => 802.11 frame
- * header conversion
- *
- * Frame header conversion is controlled by the set of MAC addresses
- * added using @ref ixEthDBWiFiStationEntryAdd and @ref ixEthDBWiFiAccessPointEntryAdd.
- * Conversion arguments are added using @ref ixEthDBWiFiFrameControlSet,
- * @ref ixEthDBWiFiDurationIDSet and @ref ixEthDBWiFiBBSIDSet.
- *
- * Note that adding the same MAC address twice will not return an error
- * (but will not accomplish anything either), while re-adding a record previously added
- * as an "Access Point to Access Point" will migrate the record to the "Access Point
- * to Station" type.
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port
- * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to add
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_INVALID_ARG macAddr is an invalid pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> pointer argument
- * @retval IX_ETH_DB_NOMEM maximum number of records reached
- * @retval IX_ETH_DB_BUSY lock condition or transaction in progress, try again later
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiStationEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBWiFiAccessPointEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr, IxEthDBMacAddr *gatewayMacAddr)
- *
- * @brief Adds an "Access Point to Access Point" record to the database
- *
- * @see ixEthDBWiFiStationEntryAdd
- *
- * Note that adding the same MAC address twice will simply overwrite the previously
- * defined gateway MAC address value in the same record, if the record was previously of the
- * "Access Point to Access Point" type.
- *
- * Re-adding a MAC address as "Access Point to Access Point", which was previously added as
- * "Access Point to Station" will migrate the record type to "Access Point to Access Point" and
- * record the gateway MAC address.
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port
- * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to add
- * @param gatewayMacAddr @ref IxEthDBMacAddr [in] - MAC address of the gateway Access Point
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG macAddr is an invalid pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> or <i>gatewayMacAddr</i> pointer argument
- * @retval IX_ETH_DB_NOMEM maximum number of records reached
- * @retval IX_ETH_DB_BUSY lock condition or transaction in progress, try again later
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiAccessPointEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr, IxEthDBMacAddr *gatewayMacAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBWiFiEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Removes a WiFi station record
- *
- * This function removes both types of WiFi records ("Access Point to Station" and
- * "Access Point to Access Point").
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port
- * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to remove
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> pointer argument
- * @retval IX_ETH_DB_NO_SUCH_ADDR specified address was not found in the database
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled
- * @retval IX_ETH_DB_BUSY lock condition or transaction in progress, try again later
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBWiFiConversionTableDownload(IxEthDBPortId portID)
- *
- * @brief Downloads the MAC address table for 802.3 => 802.11 frame header
- * conversion to the NPE
- *
- * Note that the frame conversion MAC address table must be individually downloaded
- * to each NPE for which the frame header conversion feature is enabled (i.e. it
- * is not possible to specify IX_ETH_DB_ALL_PORTS).
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled
- * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiConversionTableDownload(IxEthDBPortId portID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBWiFiFrameControlSet(IxEthDBPortId portID, UINT16 frameControl)
- *
- * @brief Sets the GlobalFrameControl field
- *
- * The GlobalFrameControl field is a 2-byte value inserted in the <i>Frame Control</i>
- * field for all 802.3 to 802.11 frame header conversions
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port
- * @param frameControl UINT16 [in] - GlobalFrameControl value
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled
- * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiFrameControlSet(IxEthDBPortId portID, UINT16 frameControl);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBWiFiDurationIDSet(IxEthDBPortId portID, UINT16 durationID)
- *
- * @brief Sets the GlobalDurationID field
- *
- * The GlobalDurationID field is a 2-byte value inserted in the <i>Duration/ID</i>
- * field for all 802.3 to 802.11 frame header conversions
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port
- * @param durationID UINT16 [in] - GlobalDurationID field
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled
- * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiDurationIDSet(IxEthDBPortId portID, UINT16 durationID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBWiFiBBSIDSet(IxEthDBPortId portID, IxEthDBMacAddr *bbsid)
- *
- * @brief Sets the BBSID field
- *
- * The BBSID field is a 6-byte value which
- * identifies the infrastructure of the service set managed
- * by the Access Point having the IXP400 as its processor. The value
- * is written in the <i>BBSID</i> field of the 802.11 frame header.
- * The BBSID value is the MAC address of the Access Point.
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port
- * @param bbsid @ref IxEthDBMacAddr [in] - pointer to 6 bytes containing the BSSID
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>bbsid</i> pointer argument
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled
- * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiBBSIDSet(IxEthDBPortId portID, IxEthDBMacAddr *bbsid);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBSpanningTreeBlockingStateSet(IxEthDBPortId portID, BOOL blocked)
- *
- * @brief Sets the STP blocked/unblocked state for a port
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port
- * @param blocked BOOL [in] - true to set the port as STP blocked, false to set it as unblocked
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Spanning Tree Protocol feature not enabled
- * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBSpanningTreeBlockingStateSet(IxEthDBPortId portID, BOOL blocked);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBSpanningTreeBlockingStateGet(IxEthDBPortId portID, BOOL *blocked)
- *
- * @brief Retrieves the STP blocked/unblocked state for a port
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port
- * @param blocked BOOL * [in] - set to true if the port is STP blocked, false otherwise
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>blocked</i> pointer argument
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Spanning Tree Protocol feature not enabled
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBSpanningTreeBlockingStateGet(IxEthDBPortId portID, BOOL *blocked);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFirewallModeSet(IxEthDBPortId portID, IxEthDBFirewallMode mode)
- *
- * @brief Sets the firewall mode to use white or black listing
- *
- * When enabled, the NPE MAC address based firewall support operates in two modes:
- *
- * - white-list mode (MAC address based admission)
- * - <i>mode</i> set to IX_ETH_DB_FIREWALL_WHITE_LIST
- * - only packets originating from MAC addresses contained in the firewall address list
- * are allowed on the Rx path
- * - black-list mode (MAC address based blocking)
- * - <i>mode</i> set to IX_ETH_DB_FIREWALL_BLACK_LIST
- * - packets originating from MAC addresses contained in the firewall address list
- * are discarded
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port
- * @param mode @ref IxEthDBFirewallMode [in] - firewall mode (IX_ETH_DB_FIREWALL_WHITE_LIST or IX_ETH_DB_FIREWALL_BLACK_LIST)
- *
- * @note by default the firewall operates in black-list mode with an empty address
- * list, hence it doesn't filter any packets
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Firewall feature not enabled
- * @retval IX_ETH_DB_INVALID_ARGUMENT <i>mode</i> argument is not a valid firewall configuration mode
- * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error
-*/
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFirewallModeSet(IxEthDBPortId portID, IxEthDBFirewallMode mode);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn ixEthDBFirewallInvalidAddressFilterEnable(IxEthDBPortId portID, BOOL enable)
- *
- * @brief Enables or disables invalid MAC address filtering
- *
- * According to IEEE802 it is illegal for a source address to be a multicast
- * or broadcast address. If this feature is enabled the NPE inspects the source
- * MAC addresses of incoming frames and discards them if invalid addresses are
- * detected.
- *
- * By default this service is enabled, if the firewall feature is supported by the
- * NPE image.
- *
- * @param portID ID of the port
- * @param enable true to enable invalid MAC address filtering and false to disable it
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Firewall feature not enabled
- * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFirewallInvalidAddressFilterEnable(IxEthDBPortId portID, BOOL enable);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFirewallEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Adds a MAC address to the firewall address list
- *
- * Note that adding the same MAC address twice will not return an error
- * but will not actually accomplish anything.
- *
- * The firewall MAC address list has a limited number of entries; once
- * the maximum number of entries has been reached this function will failed
- * to add more addresses, returning IX_ETH_DB_NOMEM.
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port
- * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to be added
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> pointer argument
- * @retval IX_ETH_DB_NOMEM maximum number of records reached
- * @retval IX_ETH_DB_BUSY lock condition or transaction in progress, try again later
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Firewall feature not enabled
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFirewallEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFirewallEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Removes a MAC address from the firewall address list
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port
- * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to be removed
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> pointer argument
- * @retval IX_ETH_DB_NO_SUCH_ADDR address not found
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Firewall feature not enabled
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFirewallEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFirewallTableDownload(IxEthDBPortId portID)
- *
- * @brief Downloads the MAC firewall table to a port
- *
- * @param portID ID of the port
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Firewall feature not enabled
- * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFirewallTableDownload(IxEthDBPortId portID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBUserFieldSet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, IxEthDBVlanId vlanID, void *field)
- *
- * @brief Adds a user-defined field to a database record
- *
- * This function associates a user-defined field to a database record.
- * The user-defined field is passed as a <i>(void *)</i> parameter, hence it can be used
- * for any purpose (such as identifying a structure). Retrieving the user-defined field from
- * a record is done using @ref ixEthDBUserFieldGet. Note that EthDB never uses the user-defined
- * field for any internal operation and it is not aware of the significance of its contents. The
- * field is only stored as a pointer.
- *
- * The database record is identified using a combination of the given parameters, depending on the record type.
- * All the record types require the record MAC address.
- *
- * - IX_ETH_DB_FILTERING_RECORD requires only the MAC address
- * - IX_ETH_DB_VLAN_FILTERING_RECORD requires the MAC address and the VLAN ID
- * - IX_ETH_DB_WIFI_RECORD requires the MAC address and the portID
- * - IX_ETH_DB_FIREWALL_RECORD requires the MAC address and the portID
- *
- * Please note that if a parameter is not required it is completely ignored (it does not undergo parameter checking).
- * The user-defined field can be cleared using a <b>NULL</b> <i>field</i> parameter.
- *
- * @param recordType @ref IxEthDBRecordType [in] - type of record (can be IX_ETH_DB_FILTERING_RECORD,
- * IX_ETH_DB_FILTERING_VLAN_RECORD, IX_ETH_DB_WIFI_RECORD or IX_ETH_DB_FIREWALL_RECORD)
- * @param portID @ref IxEthDBPortId [in] - ID of the port (required only for WIFI and FIREWALL records)
- * @param macAddr @ref IxEthDBMacAddr * [in] - MAC address of the record
- * @param vlanID @ref IxEthDBVlanId [in] - VLAN ID of the record (required only for FILTERING_VLAN records)
- * @param field void * [in] - user defined field
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID was required but it is not a valid port identifier
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> pointer argument
- * @retval IX_ETH_DB_NO_SUCH_ADDR record not found
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBUserFieldSet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, IxEthDBVlanId vlanID, void *field);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBUserFieldGet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, IxEthDBVlanId vlanID, void **field)
- *
- * @brief Retrieves a user-defined field from a database record
- *
- * The database record is identified using a combination of the given parameters, depending on the record type.
- * All the record types require the record MAC address.
- *
- * - IX_ETH_DB_FILTERING_RECORD requires only the MAC address
- * - IX_ETH_DB_VLAN_FILTERING_RECORD requires the MAC address and the VLAN ID
- * - IX_ETH_DB_WIFI_RECORD requires the MAC address and the portID
- * - IX_ETH_DB_FIREWALL_RECORD requires the MAC address and the portID
- *
- * Please note that if a parameter is not required it is completely ignored (it does not undergo parameter checking).
- *
- * If no user-defined field was registered with the specified record then <b>NULL</b> will be written
- * at the location specified by <i>field</i>.
- *
- * @param recordType type of record (can be IX_ETH_DB_FILTERING_RECORD, IX_ETH_DB_FILTERING_VLAN_RECORD, IX_ETH_DB_WIFI_RECORD
- * or IX_ETH_DB_FIREWALL_RECORD)
- * @param portID ID of the port (required only for WIFI and FIREWALL records)
- * @param macAddr MAC address of the record
- * @param vlanID VLAN ID of the record (required only for FILTERING_VLAN records)
- * @param field location to write the user defined field into
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID was required but it is not a valid port identifier
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> or <i>field</i> pointer arguments
- * @retval IX_ETH_DB_NO_SUCH_ADDR record not found
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBUserFieldGet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portId, IxEthDBVlanId vlanID, void **field);
-
-/**
- * @}
- */
-
-#endif /* IxEthDB_H */
+++ /dev/null
-/**
- * @file IxEthAccDBLocks_p.h
- *
- * @brief Definition of transaction lock stacks and lock utility macros
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxEthAccDBLocks_p_H
-#define IxEthAccDBLocks_p_H
-
-#include "IxOsPrintf.h"
-
-/* Lock and lock stacks */
-typedef struct
-{
- IxOsalFastMutex* locks[MAX_LOCKS];
- UINT32 stackPointer, basePointer;
-} LockStack;
-
-#define TRY_LOCK(mutex) \
- { \
- if (ixOsalFastMutexTryLock(mutex) != IX_SUCCESS) \
- { \
- return IX_ETH_DB_BUSY; \
- } \
- }
-
-
-#define UNLOCK(mutex) { ixOsalFastMutexUnlock(mutex); }
-
-#define INIT_STACK(stack) \
- { \
- (stack)->basePointer = 0; \
- (stack)->stackPointer = 0; \
- }
-
-#define PUSH_LOCK(stack, lock) \
- { \
- if ((stack)->stackPointer == MAX_LOCKS) \
- { \
- ERROR_LOG("Ethernet DB: maximum number of elements in a lock stack has been exceeded on push, heavy chaining?\n"); \
- UNROLL_STACK(stack); \
- \
- return IX_ETH_DB_NOMEM; \
- } \
- \
- if (ixOsalFastMutexTryLock(lock) == IX_SUCCESS) \
- { \
- (stack)->locks[(stack)->stackPointer++] = (lock); \
- } \
- else \
- { \
- UNROLL_STACK(stack); \
- \
- return IX_ETH_DB_BUSY; \
- } \
- }
-
-#define POP_LOCK(stack) \
- { \
- ixOsalFastMutexUnlock((stack)->locks[--(stack)->stackPointer]); \
- }
-
-#define UNROLL_STACK(stack) \
- { \
- while ((stack)->stackPointer > (stack)->basePointer) \
- { \
- POP_LOCK(stack); \
- } \
- }
-
-#define SHIFT_STACK(stack) \
- { \
- if ((stack)->basePointer == MAX_LOCKS - 1) \
- { \
- ERROR_LOG("Ethernet DB: maximum number of elements in a lock stack has been exceeded on shift, heavy chaining?\n"); \
- UNROLL_STACK(stack); \
- \
- return IX_ETH_DB_BUSY; \
- } \
- \
- ixOsalFastMutexUnlock((stack)->locks[(stack)->basePointer++]); \
- }
-
-#endif /* IxEthAccDBLocks_p_H */
+++ /dev/null
-/**
- * @file IxEthDBLog_p.h
- *
- * @brief definitions of log macros and log configuration
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include <IxOsal.h>
-
-#ifdef IX_UNIT_TEST
-#define NULL_PRINT_ROUTINE(format, arg...) /* nothing */
-#else
-#define NULL_PRINT_ROUTINE if(0) printf
-#endif
-
-/***************************************************
- * Globals *
- ***************************************************/
-/* safe to permanently leave these on */
-#define HAS_ERROR_LOG
-#define HAS_ERROR_IRQ_LOG
-#define HAS_WARNING_LOG
-
-/***************************************************
- * Log Configuration *
- ***************************************************/
-
-/* debug output can be turned on unless specifically
- declared as a non-debug build */
-#ifndef NDEBUG
-
-#undef HAS_EVENTS_TRACE
-#undef HAS_EVENTS_VERBOSE_TRACE
-
-#undef HAS_SUPPORT_TRACE
-#undef HAS_SUPPORT_VERBOSE_TRACE
-
-#undef HAS_NPE_TRACE
-#undef HAS_NPE_VERBOSE_TRACE
-#undef HAS_DUMP_NPE_TREE
-
-#undef HAS_UPDATE_TRACE
-#undef HAS_UPDATE_VERBOSE_TRACE
-
-#endif /* NDEBUG */
-
-
-/***************************************************
- * Log Macros *
- ***************************************************/
-
-/************** Globals ******************/
-
-#ifdef HAS_ERROR_LOG
-
- #define ERROR_LOG printf
-
-#else
-
- #define ERROR_LOG NULL_PRINT_ROUTINE
-
-#endif
-
-#ifdef HAS_ERROR_IRQ_LOG
-
- #define ERROR_IRQ_LOG(format, arg1, arg2, arg3, arg4, arg5, arg6) ixOsalLog(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, format, arg1, arg2, arg3, arg4, arg5, arg6)
-
-#else
-
- #define ERROR_IRQ_LOG(format, arg1, arg2, arg3, arg4, arg5, arg6) /* nothing */
-
-#endif
-
-#ifdef HAS_WARNING_LOG
-
- #define WARNING_LOG printf
-
-#else
-
- #define WARNING_LOG NULL_PRINT_ROUTINE
-
-#endif
-
-/************** Events *******************/
-
-#ifdef HAS_EVENTS_TRACE
-
- #define IX_ETH_DB_EVENTS_TRACE printf
- #define IX_ETH_DB_IRQ_EVENTS_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, format, arg1, arg2, arg3, arg4, arg5, arg6)
-
- #ifdef HAS_EVENTS_VERBOSE_TRACE
-
- #define IX_ETH_DB_EVENTS_VERBOSE_TRACE printf
-
- #else
-
- #define IX_ETH_DB_EVENTS_VERBOSE_TRACE NULL_PRINT_ROUTINE
-
- #endif /* HAS_EVENTS_VERBOSE_TRACE */
-
-#else
-
- #define IX_ETH_DB_EVENTS_TRACE NULL_PRINT_ROUTINE
- #define IX_ETH_DB_EVENTS_VERBOSE_TRACE NULL_PRINT_ROUTINE
- #define IX_ETH_DB_IRQ_EVENTS_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) /* nothing */
-
-#endif /* HAS_EVENTS_TRACE */
-
-/************** Support *******************/
-
-#ifdef HAS_SUPPORT_TRACE
-
- #define IX_ETH_DB_SUPPORT_TRACE printf
- #define IX_ETH_DB_SUPPORT_IRQ_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, format, arg1, arg2, arg3, arg4, arg5, arg6)
-
- #ifdef HAS_SUPPORT_VERBOSE_TRACE
-
- #define IX_ETH_DB_SUPPORT_VERBOSE_TRACE printf
-
- #else
-
- #define IX_ETH_DB_SUPPORT_VERBOSE_TRACE NULL_PRINT_ROUTINE
-
- #endif /* HAS_SUPPORT_VERBOSE_TRACE */
-
-#else
-
- #define IX_ETH_DB_SUPPORT_TRACE NULL_PRINT_ROUTINE
- #define IX_ETH_DB_SUPPORT_VERBOSE_TRACE NULL_PRINT_ROUTINE
- #define IX_ETH_DB_SUPPORT_IRQ_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) /* nothing */
-
-#endif /* HAS_SUPPORT_TRACE */
-
-/************** NPE Adaptor *******************/
-
-#ifdef HAS_NPE_TRACE
-
- #define IX_ETH_DB_NPE_TRACE printf
- #define IX_ETH_DB_NPE_IRQ_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, format, arg1, arg2, arg3, arg4, arg5, arg6)
-
- #ifdef HAS_NPE_VERBOSE_TRACE
-
- #define IX_ETH_DB_NPE_VERBOSE_TRACE printf
-
- #else
-
- #define IX_ETH_DB_NPE_VERBOSE_TRACE NULL_PRINT_ROUTINE
-
- #endif /* HAS_NPE_VERBOSE_TRACE */
-
-#else
-
- #define IX_ETH_DB_NPE_TRACE NULL_PRINT_ROUTINE
- #define IX_ETH_DB_NPE_VERBOSE_TRACE NULL_PRINT_ROUTINE
- #define IX_ETH_DB_NPE_IRQ_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) /* nothing */
-
-#endif /* HAS_NPE_TRACE */
-
-#ifdef HAS_DUMP_NPE_TREE
-
-#define IX_ETH_DB_NPE_DUMP_ELT(eltBaseAddress, eltSize) ixEthELTDumpTree(eltBaseAddress, eltSize)
-
-#else
-
-#define IX_ETH_DB_NPE_DUMP_ELT(eltBaseAddress, eltSize) /* nothing */
-
-#endif /* HAS_DUMP_NPE_TREE */
-
-/************** Port Update *******************/
-
-#ifdef HAS_UPDATE_TRACE
-
- #define IX_ETH_DB_UPDATE_TRACE printf
-
- #ifdef HAS_UPDATE_VERBOSE_TRACE
-
- #define IX_ETH_DB_UPDATE_VERBOSE_TRACE printf
-
- #else
-
- #define IX_ETH_DB_UPDATE_VERBOSE_TRACE NULL_PRINT_ROUTINE
-
- #endif
-
-#else /* HAS_UPDATE_VERBOSE_TRACE */
-
- #define IX_ETH_DB_UPDATE_TRACE NULL_PRINT_ROUTINE
- #define IX_ETH_DB_UPDATE_VERBOSE_TRACE NULL_PRINT_ROUTINE
-
-#endif /* HAS_UPDATE_TRACE */
+++ /dev/null
-/**
- * @file IxEthDBMessages_p.h
- *
- * @brief Definitions of NPE messages
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxEthDBMessages_p_H
-#define IxEthDBMessages_p_H
-
-#include <IxEthNpe.h>
-#include <IxOsCacheMMU.h>
-#include "IxEthDB_p.h"
-
-/* events watched by the Eth event processor */
-#define IX_ETH_DB_MIN_EVENT_ID (IX_ETHNPE_EDB_GETMACADDRESSDATABASE)
-#define IX_ETH_DB_MAX_EVENT_ID (IX_ETHNPE_PC_SETAPMACTABLE)
-
-/* macros to fill and extract data from NPE messages - place any endian conversions here */
-#define RESET_ELT_MESSAGE(message) { memset((void *) &(message), 0, sizeof((message))); }
-#define NPE_MSG_ID(msg) ((msg).data[0] >> 24)
-
-#define FILL_SETPORTVLANTABLEENTRY_MSG(message, portID, setOffset, vlanMembershipSet, ttiSet) \
- do { \
- message.data[0] = (IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY << 24) | (portID << 16) | (setOffset * 2); \
- message.data[1] = (vlanMembershipSet << 8) | ttiSet; \
- } while (0);
-
-#define FILL_SETPORTVLANTABLERANGE_MSG(message, portID, offset, length, zone) \
- do { \
- message.data[0] = IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE << 24 | portID << 16 | offset << 9 | length << 1; \
- message.data[1] = (UINT32) zone; \
- } while (0);
-
-#define FILL_SETDEFAULTRXVID_MSG(message, portID, tpid, vlanTag) \
- do { \
- message.data[0] = (IX_ETHNPE_VLAN_SETDEFAULTRXVID << 24) \
- | (portID << 16); \
- \
- message.data[1] = (tpid << 16) | vlanTag; \
- } while (0);
-
-#define FILL_SETRXTAGMODE_MSG(message, portID, filterMode, tagMode) \
- do { \
- message.data[0] = IX_ETHNPE_VLAN_SETRXTAGMODE << 24 \
- | portID << 16 \
- | filterMode << 2 \
- | tagMode; \
- \
- message.data[1] = 0; \
- } while (0);
-
-#define FILL_SETRXQOSENTRY(message, portID, classIndex, trafficClass, aqmQueue) \
- do { \
- message.data[0] = IX_ETHNPE_VLAN_SETRXQOSENTRY << 24 \
- | portID << 16 \
- | classIndex; \
- \
- message.data[1] = trafficClass << 24 \
- | 0x1 << 23 \
- | aqmQueue << 16 \
- | aqmQueue << 4; \
- } while (0);
-
-#define FILL_SETPORTIDEXTRACTIONMODE(message, portID, enable) \
- do { \
- message.data[0] = IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE << 24 \
- | portID << 16 \
- | (enable ? 0x1 : 0x0); \
- \
- message.data[1] = 0; \
- } while (0);
-
-
-#define FILL_SETBLOCKINGSTATE_MSG(message, portID, blocked) \
- do { \
- message.data[0] = IX_ETHNPE_STP_SETBLOCKINGSTATE << 24 \
- | portID << 16 \
- | (blocked ? 0x1 : 0x0); \
- \
- message.data[1] = 0; \
- } while (0);
-
-#define FILL_SETBBSID_MSG(message, portID, bbsid) \
- do { \
- message.data[0] = IX_ETHNPE_PC_SETBBSID << 24 \
- | portID << 16 \
- | bbsid->macAddress[0] << 8 \
- | bbsid->macAddress[1]; \
- \
- message.data[1] = bbsid->macAddress[2] << 24 \
- | bbsid->macAddress[3] << 16 \
- | bbsid->macAddress[4] << 8 \
- | bbsid->macAddress[5]; \
- } while (0);
-
-#define FILL_SETFRAMECONTROLDURATIONID(message, portID, frameControlDurationID) \
- do { \
- message.data[0] = (IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID << 24) | (portID << 16); \
- message.data[1] = frameControlDurationID; \
- } while (0);
-
-#define FILL_SETAPMACTABLE_MSG(message, zone) \
- do { \
- message.data[0] = IX_ETHNPE_PC_SETAPMACTABLE << 24 \
- | 0 << 8 /* always use index 0 */ \
- | 64; /* 32 entries, 8 bytes each, 4 bytes in a word */ \
- message.data[1] = (UINT32) zone; \
- } while (0);
-
-#define FILL_SETFIREWALLMODE_MSG(message, portID, epDelta, mode, address) \
- do { \
- message.data[0] = IX_ETHNPE_FW_SETFIREWALLMODE << 24 \
- | portID << 16 \
- | (epDelta & 0xFF) << 8 \
- | mode; \
- \
- message.data[1] = (UINT32) address; \
- } while (0);
-
-#define FILL_SETMACADDRESSDATABASE_MSG(message, portID, epDelta, blockCount, address) \
- do { \
- message.data[0] = IX_ETHNPE_EDB_SETMACADDRESSSDATABASE << 24 \
- | (epDelta & 0xFF) << 8 \
- | (blockCount & 0xFF); \
- \
- message.data[1] = (UINT32) address; \
- } while (0);
-
-#define FILL_GETMACADDRESSDATABASE(message, npeId, zone) \
- do { \
- message.data[0] = IX_ETHNPE_EDB_GETMACADDRESSDATABASE << 24; \
- message.data[1] = (UINT32) zone; \
- } while (0);
-
-#define FILL_SETMAXFRAMELENGTHS_MSG(message, portID, maxRxFrameSize, maxTxFrameSize) \
- do { \
- message.data[0] = IX_ETHNPE_SETMAXFRAMELENGTHS << 24 \
- | portID << 16 \
- | ((maxRxFrameSize + 63) / 64) << 8 /* max Rx 64-byte blocks */ \
- | (maxTxFrameSize + 63) / 64; /* max Tx 64-byte blocks */ \
- \
- message.data[1] = maxRxFrameSize << 16 | maxTxFrameSize; \
- } while (0);
-
-#define FILL_SETPORTADDRESS_MSG(message, portID, macAddress) \
- do { \
- message.data[0] = IX_ETHNPE_EDB_SETPORTADDRESS << 24 \
- | portID << 16 \
- | macAddress[0] << 8 \
- | macAddress[1]; \
- \
- message.data[1] = macAddress[2] << 24 \
- | macAddress[3] << 16 \
- | macAddress[4] << 8 \
- | macAddress[5]; \
- } while (0);
-
-/* access to a MAC node in the NPE tree */
-#define NPE_NODE_BYTE(eltNodeAddr, offset) (((UINT8 *) (eltNodeAddr))[offset])
-
-/* browsing of the implicit linear binary tree structure of the NPE tree */
-#define LEFT_CHILD_OFFSET(offset) ((offset) << 1)
-#define RIGHT_CHILD_OFFSET(offset) (((offset) << 1) + 1)
-
-#define IX_EDB_FLAGS_ACTIVE (0x2)
-#define IX_EDB_FLAGS_VALID (0x1)
-#define IX_EDB_FLAGS_RESERVED (0xfc)
-#define IX_EDB_FLAGS_INACTIVE_VALID (0x1)
-
-#define IX_EDB_NPE_NODE_ELT_PORT_ID_OFFSET (6)
-#define IX_EDB_NPE_NODE_ELT_FLAGS_OFFSET (7)
-#define IX_EDB_NPE_NODE_WIFI_INDEX_OFFSET (6)
-#define IX_EDB_NPE_NODE_WIFI_FLAGS_OFFSET (7)
-#define IX_EDB_NPE_NODE_FW_FLAGS_OFFSET (1)
-#define IX_EDB_NPE_NODE_FW_RESERVED_OFFSET (6)
-#define IX_EDB_NPE_NODE_FW_ADDR_OFFSET (2)
-
-#define IX_EDB_NPE_NODE_VALID(address) ((NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_ELT_FLAGS_OFFSET) & IX_EDB_FLAGS_VALID) != 0)
-#define IX_EDB_NPE_NODE_ACTIVE(address) ((NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_ELT_FLAGS_OFFSET) & IX_EDB_FLAGS_ACTIVE) != 0)
-#define IX_EDB_NPE_NODE_PORT_ID(address) (NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_ELT_PORT_ID_OFFSET))
-
-/* macros to send messages to the NPEs */
-#define IX_ETHDB_ASYNC_SEND_NPE_MSG(npeId, msg, result) \
- do { \
- result = ixNpeMhMessageSend(npeId, msg, IX_NPEMH_SEND_RETRIES_DEFAULT); \
- \
- if (result != IX_SUCCESS) \
- { \
- ERROR_LOG("DB: Failed to send NPE message\n"); \
- } \
- } while (0);
-
-#define IX_ETHDB_SYNC_SEND_NPE_MSG(npeId, msg, result) \
- do { \
- result = ixNpeMhMessageWithResponseSend(npeId, msg, msg.data[0] >> 24, ixEthDBNpeMsgAck, IX_NPEMH_SEND_RETRIES_DEFAULT); \
- \
- if (result == IX_SUCCESS) \
- { \
- result = ixOsalMutexLock(&ixEthDBPortInfo[IX_ETH_DB_NPE_TO_PORT_ID(npeId)].npeAckLock, IX_ETH_DB_NPE_TIMEOUT); \
- \
- if (result != IX_SUCCESS) \
- { \
- ERROR_LOG("DB: NPE failed to respond within %dms\n", IX_ETH_DB_NPE_TIMEOUT); \
- } \
- } \
- else \
- { \
- ERROR_LOG("DB: Failed to send NPE message\n"); \
- } \
- } while (0);
-
-#ifndef IX_NDEBUG
-#define IX_ETH_DB_NPE_MSG_HISTORY_DEPTH (100)
-extern IX_ETH_DB_PUBLIC UINT32 npeMsgHistory[IX_ETH_DB_NPE_MSG_HISTORY_DEPTH][2];
-extern IX_ETH_DB_PUBLIC UINT32 npeMsgHistoryLen;
-#endif
-
-#define IX_ETHDB_SEND_NPE_MSG(npeId, msg, result) { LOG_NPE_MSG(msg); IX_ETHDB_SYNC_SEND_NPE_MSG(npeId, msg, result); }
-
-#endif /* IxEthDBMessages_p_H */
+++ /dev/null
-/**
- * @file IxEthDBPortDefs.h
- *
- * @brief Public definition of the ports and port capabilities
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxEthDBPortDefs IXP400 Ethernet Database Port Definitions (IxEthDBPortDefs)
- *
- * @brief IXP400 Public definition of the ports and port capabilities
- *
- * @{
- */
-
-#ifndef IxEthDBPortDefs_H
-#define IxEthDBPortDefs_H
-
-/**
- * @brief Port types - currently only Ethernet NPEs are recognized as specific types
- * All other (user-defined) ports must be specified as IX_ETH_GENERIC
- */
-typedef enum
-{
- IX_ETH_GENERIC = 0, /**< generic ethernet port */
- IX_ETH_NPE /**< specific Ethernet NPE */
-} IxEthDBPortType;
-
-/**
- * @brief Port capabilities - used by ixEthAccDatabaseMaintenance to decide whether it
- * should manually age entries or not depending on the port capabilities.
- *
- * Ethernet NPEs have aging capabilities, meaning that they will age the entries
- * automatically (by themselves).*/
-typedef enum
-{
- IX_ETH_NO_CAPABILITIES = 0, /**< no aging capabilities */
- IX_ETH_ENTRY_AGING = 0x1 /**< aging capabilities present */
-} IxEthDBPortCapability;
-
-/**
- * @brief Port Definition - a structure contains the Port type and capabilities
- */
-typedef struct
-{
- IxEthDBPortType type;
- IxEthDBPortCapability capabilities;
-} IxEthDBPortDefinition;
-
-/**
- * @brief Port definitions structure, indexed on the port ID
- * @warning Ports 0 and 1 are used by the Ethernet access component therefore
- * it is essential to be left untouched. Port 2 here (WAN) is given as
- * an example port. The NPE firmware also assumes the NPE B to be
- * the port 0 and NPE C to be the port 1.
- *
- * @note that only 32 ports (0..31) are supported by EthDB
- */
-static const IxEthDBPortDefinition ixEthDBPortDefinitions[] =
-{
- /* id type capabilities */
- { /* 0 */ IX_ETH_NPE, IX_ETH_NO_CAPABILITIES }, /* Ethernet NPE B */
- { /* 1 */ IX_ETH_NPE, IX_ETH_NO_CAPABILITIES }, /* Ethernet NPE C */
- { /* 2 */ IX_ETH_NPE, IX_ETH_NO_CAPABILITIES }, /* Ethernet NPE A */
- { /* 3 */ IX_ETH_GENERIC, IX_ETH_NO_CAPABILITIES }, /* WAN port */
-};
-
-/**
- * @def IX_ETH_DB_NUMBER_OF_PORTS
- * @brief number of supported ports
- */
-#define IX_ETH_DB_NUMBER_OF_PORTS ARRAY_SIZE(ixEthDBPortDefinitions)
-
-/**
- * @def IX_ETH_DB_UNKNOWN_PORT
- * @brief definition of an unknown port
- */
-#define IX_ETH_DB_UNKNOWN_PORT (0xff)
-
-/**
- * @def IX_ETH_DB_ALL_PORTS
- * @brief Special port ID indicating all the ports
- * @note This port ID can be used only by a subset of the EthDB API; each
- * function specifically mentions whether this is a valid parameter as the port ID
- */
-#define IX_ETH_DB_ALL_PORTS (IX_ETH_DB_NUMBER_OF_PORTS + 1)
-
-/**
- * @def IX_ETH_DB_PORTS_ASSERTION
- * @brief catch invalid port definitions (<2) with a
- * compile-time assertion resulting in a duplicate case error.
- */
-#define IX_ETH_DB_PORTS_ASSERTION { switch(0) { case 0 : ; case 1 : ; case IX_ETH_DB_NUMBER_OF_PORTS : ; }}
-
-/**
- * @def IX_ETH_DB_CHECK_PORT(portID)
- * @brief safety checks to verify whether the port is invalid or uninitialized
- */
-#define IX_ETH_DB_CHECK_PORT(portID) \
-{ \
- if ((portID) >= IX_ETH_DB_NUMBER_OF_PORTS) \
- { \
- return IX_ETH_DB_INVALID_PORT; \
- } \
- \
- if (!ixEthDBPortInfo[(portID)].enabled) \
- { \
- return IX_ETH_DB_PORT_UNINITIALIZED; \
- } \
-}
-
-/**
- * @def IX_ETH_DB_CHECK_PORT_ALL(portID)
- * @brief safety checks to verify whether the port is invalid or uninitialized;
- * tolerates the use of IX_ETH_DB_ALL_PORTS
- */
-#define IX_ETH_DB_CHECK_PORT_ALL(portID) \
-{ \
- if ((portID) != IX_ETH_DB_ALL_PORTS) \
- IX_ETH_DB_CHECK_PORT(portID) \
-}
-
-#endif /* IxEthDBPortDefs_H */
-/**
- *@}
- */
+++ /dev/null
-/**
- * @file IxEthDBQoS.h
- *
- * @brief Public definitions for QoS traffic classes
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxEthDBPortDefs IXP400 Ethernet QoS definitions
- *
- * @brief IXP00 Public definitions for QoS traffic classes
- *
- * @{
- */
-
-#ifndef IxEthDBQoS_H
-#define IxEthDBQoS_H
-
-/**
- * @def IX_ETH_DB_QUEUE_UNAVAILABLE
- * @brief alias to indicate a queue (traffic class) is not available
- */
-#define IX_ETH_DB_QUEUE_UNAVAILABLE (0)
-
-#ifndef IX_IEEE802_1Q_QOS_PRIORITY_COUNT
-/**
- * @def IX_IEEE802_1Q_QOS_PRIORITY_COUNT
- * @brief number of QoS priorities, according to IEEE 802.1Q
- */
-#define IX_IEEE802_1Q_QOS_PRIORITY_COUNT (8)
-#endif
-
-/**
- * @brief array containing all the supported traffic class configurations
- */
-static const
-UINT8 ixEthDBQueueAssignments[][IX_IEEE802_1Q_QOS_PRIORITY_COUNT] =
-{
- { 4, 5, 6, 7, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE },
- { 15, 16, 17, 18, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE },
- { 11, 23, 26, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE },
- { 4, 5, 6, 7, 8, 9, 10, 11 }
- /* add here all other cases of queue configuration structures and update ixEthDBTrafficClassDefinitions to use them */
-};
-
-/**
- * @brief value used to index the NPE A functionality ID in the traffic class definition table
- */
-#define IX_ETH_DB_NPE_A_FUNCTIONALITY_ID_INDEX (0)
-
-/**
- * @brief value used to index the traffic class count in the traffic class definition table
- */
-#define IX_ETH_DB_TRAFFIC_CLASS_COUNT_INDEX (1)
-
-/**
- * @brief value used to index the queue assignment index in the traffic class definition table
- */
-#define IX_ETH_DB_QUEUE_ASSIGNMENT_INDEX (2)
-
-/**
- * @brief traffic class definitions
- *
- * This array contains the default traffic class definition configuration,
- * as well as any special cases dictated by the functionality ID of NPE A.
- *
- * The default case should not be removed (otherwise the Ethernet
- * components will assert a fatal failure on initialization).
- */
-static const
-UINT8 ixEthDBTrafficClassDefinitions[][3] =
-{
- /* NPE A functionality ID | traffic class count | queue assignment index (points to the queue enumeration in ixEthDBQueueAssignments) */
- { 0x00, 4, 0 }, /* default case - DO NOT REMOVE */
- { 0x04, 4, 1 }, /* NPE A image ID 0.4.0.0 */
- { 0x09, 3, 2 }, /* NPE A image ID 0.9.0.0 */
- { 0x80, 8, 3 }, /* NPE A image ID 10.80.02.0 */
- { 0x81, 8, 3 }, /* NPE A image ID 10.81.02.0 */
- { 0x82, 8, 3 } /* NPE A image ID 10.82.02.0 */
-};
-
-/**
- * @brief IEEE 802.1Q recommended QoS Priority => traffic class maps
- *
- * @verbatim
- Number of available traffic classes
- 1 2 3 4 5 6 7 8
- QoS Priority
- 0 0 0 0 1 1 1 1 2
- 1 0 0 0 0 0 0 0 0
- 2 0 0 0 0 0 0 0 1
- 3 0 0 0 1 1 2 2 3
- 4 0 1 1 2 2 3 3 4
- 5 0 1 1 2 3 4 4 5
- 6 0 1 2 3 4 5 5 6
- 7 0 1 2 3 4 5 6 7
-
- @endverbatim
- */
-static const
-UINT8 ixEthIEEE802_1QUserPriorityToTrafficClassMapping[IX_IEEE802_1Q_QOS_PRIORITY_COUNT][IX_IEEE802_1Q_QOS_PRIORITY_COUNT] =
- {
- { 0, 0, 0, 0, 0, 0, 0, 0 }, /* 1 traffic class available */
- { 0, 0, 0, 0, 1, 1, 1, 1 }, /* 2 traffic classes available */
- { 0, 0, 0, 0, 1, 1, 2, 2 }, /* 3 traffic classes available */
- { 1, 0, 0, 1, 2, 2, 3, 3 }, /* 4 traffic classes available */
- { 1, 0, 0, 1, 2, 3, 4, 4 }, /* 5 traffic classes available */
- { 1, 0, 0, 2, 3, 4, 5, 5 }, /* 6 traffic classes available */
- { 1, 0, 0, 2, 3, 4, 5, 6 }, /* 7 traffic classes available */
- { 2, 0, 1, 3, 4, 5, 6, 7 } /* 8 traffic classes available */
- };
-
-#endif /* IxEthDBQoS_H */
-
-/**
- *@}
- */
+++ /dev/null
-/**
- * @file IxEthDB_p.h
- *
- * @brief Private MAC learning API
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxEthDB_p_H
-#define IxEthDB_p_H
-
-#include <IxTypes.h>
-#include <IxOsal.h>
-#include <IxEthDB.h>
-#include <IxNpeMh.h>
-#include <IxEthDBPortDefs.h>
-
-#include "IxEthDBMessages_p.h"
-#include "IxEthDBLog_p.h"
-
-#if (CPU==SIMSPARCSOLARIS)
-
-/* when running unit tests intLock() won't protect the event queue so we lock it manually */
-#define TEST_FIXTURE_LOCK_EVENT_QUEUE { ixOsalMutexLock(&eventQueueLock, IX_OSAL_WAIT_FOREVER); }
-#define TEST_FIXTURE_UNLOCK_EVENT_QUEUE { ixOsalMutexUnlock(&eventQueueLock); }
-
-#else
-
-#define TEST_FIXTURE_LOCK_EVENT_QUEUE /* nothing */
-#define TEST_FIXTURE_UNLOCK_EVENT_QUEUE /* nothing */
-
-#endif /* #if(CPU==SIMSPARCSOLARIS) */
-
-#ifndef IX_UNIT_TEST
-
-#define TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER /* nothing */
-#define TEST_FIXTURE_MARK_OVERFLOW_EVENT /* nothing */
-
-#else
-
-extern int dbAccessCounter;
-extern int overflowEvent;
-
-#define TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER { dbAccessCounter++; }
-#define TEST_FIXTURE_MARK_OVERFLOW_EVENT { overflowEvent = 1; }
-
-#endif
-
-/* code readability markers */
-#define __mempool__ /* memory pool marker */
-#define __lock__ /* hash write locking marker */
-#define __smartpointer__ /* smart pointer marker - warning: use only clone() when duplicating! */
-#define __alignment__ /* marker for data used only as alignment zones */
-
-/* constants */
-#define IX_ETH_DB_NPE_TIMEOUT (100) /* NPE response timeout, in ms */
-
-/**
- * number of hash table buckets
- * it should be at least 8x the predicted number of entries for performance
- * each bucket needs 8 bytes
- */
-#define NUM_BUCKETS (8192)
-
-/**
- * number of hash table buckets to preload when incrementing bucket iterator
- * = two cache lines
- */
-#define IX_ETHDB_CACHE_LINE_AHEAD (2)
-
-#define IX_ETHDB_BUCKETPTR_AHEAD ((IX_ETHDB_CACHE_LINE_AHEAD * IX_OSAL_CACHE_LINE_SIZE)/sizeof(void *))
-
-#define IX_ETHDB_BUCKET_INDEX_MASK (((IX_OSAL_CACHE_LINE_SIZE)/sizeof(void *)) - 1)
-
-/* locks */
-#define MAX_LOCKS (20) /**< maximum number of locks used simultaneously, do not tamper with */
-
-/* learning tree constants */
-#define INITIAL_ELT_SIZE (8) /**< initial byte size of tree (empty unused root size) */
-#define MAX_ELT_SIZE (512) /**< maximum number of entries (includes unused root) */
-#define MAX_GW_SIZE (32) /**< maximum number of gateway entries (including unused root) */
-#define MAX_FW_SIZE (32) /**< maximum number of firewall entries (including unused root) */
-#define ELT_ENTRY_SIZE (8) /**< entry size, in bytes */
-#define ELT_ROOT_OFFSET (ELT_ENTRY_SIZE) /**< tree root offset, in bytes - node preceeding root is unused */
-#define FULL_ELT_BYTE_SIZE (MAX_ELT_SIZE * ELT_ENTRY_SIZE) /**< full size of tree, in bytes, including unused root */
-#define FULL_GW_BYTE_SIZE (MAX_GW_SIZE * ELT_ENTRY_SIZE) /**< full size of gateway list, in bytes, including unused root */
-#define FULL_FW_BYTE_SIZE (MAX_FW_SIZE * ELT_ENTRY_SIZE) /**< full size of firewall table, in bytes, including unused root */
-
-/* maximum size of the VLAN table:
- * 4096 bits (one per VLAN)
- * 8 bits in one byte
- * interleaved VLAN membership and VLAN TTI (*2) */
-#define FULL_VLAN_BYTE_SIZE (4096 / 8 * 2)
-
-/* upper 9 bits used as set index, lower 3 bits as byte index */
-#define VLAN_SET_OFFSET(vlanID) ((vlanID) >> 3)
-#define VLAN_SET_MASK(vlanID) (0x7 - ((vlanID) & 0x7))
-
-/* Update zone definitions */
-#define NPE_TREE_MEM_SIZE (4096) /* ((511 entries + 1 unused root) * 8 bytes/entry) */
-
-/* check the above value, we rely on 4k */
-#if NPE_TREE_MEM_SIZE != 4096
- #error NPE_TREE_MEM_SIZE is not defined to 4096 bytes!
-#endif
-
-/* Size Filtering limits (Jumbo frame filtering) */
-#define IX_ETHDB_MAX_FRAME_SIZE 65535 /* other ports than NPE ports */
-#define IX_ETHDB_MIN_FRAME_SIZE 1 /* other ports than NPE ports */
-#define IX_ETHDB_MAX_NPE_FRAME_SIZE 16320 /* NPE ports firmware limit */
-#define IX_ETHDB_MIN_NPE_FRAME_SIZE 1 /* NPE ports firmware limit */
-#define IX_ETHDB_DEFAULT_FRAME_SIZE 1522
-
-/* memory management pool sizes */
-
-/*
- * Note:
- *
- * NODE_POOL_SIZE controls the maximum number of elements in the database at any one time.
- * It should be large enough to cover all the search trees of all the ports simultaneously.
- *
- * MAC_POOL_SIZE should be higher than NODE_POOL_SIZE by at least the total number of MAC addresses
- * possible to be held at any time in all the ports.
- *
- * TREE_POOL_SIZE should follow the same guideline as for MAC_POOL_SIZE.
- *
- * The database structure described here (2000/4000/4000) is enough for two NPEs holding at most 511
- * entries each plus one PCI NIC holding at most 900 entries.
- */
-
-#define NODE_POOL_SIZE (2000) /**< number of HashNode objects - also master number of elements in the database; each entry has 16 bytes */
-#define MAC_POOL_SIZE (4000) /**< number of MacDescriptor objects; each entry has 28 bytes */
-#define TREE_POOL_SIZE (4000) /**< number of MacTreeNode objects; each entry has 16 bytes */
-
-/* retry policies */
-#define BUSY_RETRY_ENABLED (true) /**< if set to true the API will retry automatically calls returning BUSY */
-#define FOREVER_RETRY (true) /**< if set to true the API will retry forever BUSY calls */
-#define MAX_RETRIES (400) /**< upper retry limit - used only when FOREVER_RETRY is false */
-#define BUSY_RETRY_YIELD (5) /**< ticks to yield for every failed retry */
-
-/* event management */
-#define EVENT_QUEUE_SIZE (500) /**< size of the sink collecting events from the Message Handler FIFO */
-#define EVENT_PROCESSING_LIMIT (100) /**< batch processing control size (how many events are extracted from the queue at once) */
-
-/* MAC descriptors */
-#define STATIC_ENTRY (true)
-#define DYNAMIC_ENTRY (false)
-
-/* age reset on next maintenance - incrementing by 1 will reset to 0 */
-#define AGE_RESET (0xFFFFFFFF)
-
-/* dependency maps */
-#define EMPTY_DEPENDENCY_MAP (0)
-
-/* trees */
-#define RIGHT (1)
-#define LEFT (-1)
-
-/* macros */
-#define IX_ETH_DB_CHECK_PORT_EXISTS(portID) \
-{ \
- if ((portID) >= IX_ETH_DB_NUMBER_OF_PORTS) \
- { \
- return IX_ETH_DB_INVALID_PORT; \
- } \
-}
-
-#define IX_ETH_DB_CHECK_PORT_INITIALIZED(portID) \
-{ \
- if ((portID) >= IX_ETH_DB_NUMBER_OF_PORTS) \
- { \
- return IX_ETH_DB_INVALID_PORT; \
- } \
- else \
- { \
- if (!ixEthDBPortInfo[portID].initialized) \
- { \
- return IX_ETH_DB_PORT_UNINITIALIZED; \
- } \
- } \
-}
-
-/* single NPE check */
-#define IX_ETH_DB_CHECK_SINGLE_NPE(portID) \
- if (ixEthDBSingleEthNpeCheck(portID) != IX_ETH_DB_SUCCESS) \
- { \
- WARNING_LOG("EthDB: port ID %d is unavailable\n",(UINT32) portID); \
- \
- return IX_ETH_DB_INVALID_PORT; \
- }
-
-/* feature check */
-#define IX_ETH_DB_CHECK_FEATURE(portID, feature) \
- if ((ixEthDBPortInfo[portID].featureStatus & feature) == 0) \
- { \
- return IX_ETH_DB_FEATURE_UNAVAILABLE; \
- }
-
-/* busy retrying */
-#define BUSY_RETRY(functionCall) \
- { \
- UINT32 retries = 0; \
- IxEthDBStatus br_result; \
- \
- while ((br_result = functionCall) == IX_ETH_DB_BUSY \
- && BUSY_RETRY_ENABLED && (FOREVER_RETRY || ++retries < MAX_RETRIES)) { ixOsalSleep(BUSY_RETRY_YIELD); }; \
- \
- if ((!FOREVER_RETRY && retries == MAX_RETRIES) || (br_result == IX_ETH_DB_FAIL)) \
- {\
- ERROR_LOG("Ethernet Learning Database Error: BUSY_RETRY failed at %s:%d\n", __FILE__, __LINE__); \
- }\
- }
-
-#define BUSY_RETRY_WITH_RESULT(functionCall, brwr_result) \
- { \
- UINT32 retries = 0; \
- \
- while ((brwr_result = functionCall) == IX_ETH_DB_BUSY \
- && BUSY_RETRY_ENABLED && (FOREVER_RETRY || ++retries < MAX_RETRIES)) { ixOsalSleep(BUSY_RETRY_YIELD); }; \
- \
- if ((!FOREVER_RETRY && retries == MAX_RETRIES) || (brwr_result == IX_ETH_DB_FAIL)) \
- {\
- ERROR_LOG("Ethernet Learning Database Error: BUSY_RETRY_WITH_RESULT failed at %s:%d\n", __FILE__, __LINE__); \
- }\
- }
-
-/* iterators */
-#define IS_ITERATOR_VALID(iteratorPtr) ((iteratorPtr)->node != NULL)
-
-/* dependency port maps */
-
-/* Warning: if port indexing starts from 1 replace (portID) with (portID - 1) in DEPENDENCY_MAP (and make sure IX_ETH_DB_NUMBER_OF_PORTS is big enough) */
-
-/* gives an empty dependency map */
-#define SET_EMPTY_DEPENDENCY_MAP(map) { int i = 0; for (; i < 32 ; i++) map[i] = 0; }
-
-#define IS_EMPTY_DEPENDENCY_MAP(result, map) { int i = 0 ; result = true; for (; i < 32 ; i++) if (map[i] != 0) { result = false; break; }}
-
-/**
- * gives a map consisting only of 'portID'
- */
-#define SET_DEPENDENCY_MAP(map, portID) {SET_EMPTY_DEPENDENCY_MAP(map); map[portID >> 3] = 1 << (portID & 0x7);}
-
-/**
- * gives a map resulting from joining map1 and map2
- */
-#define JOIN_MAPS(map, map1, map2) { int i = 0; for (; i < 32 ; i++) map[i] = map1[i] | map2[i]; }
-
-/**
- * gives the map resulting from joining portID and map
- */
-#define JOIN_PORT_TO_MAP(map, portID) { map[portID >> 3] |= 1 << (portID & 0x7); }
-
-/**
- * gives the map resulting from excluding portID from map
- */
-#define EXCLUDE_PORT_FROM_MAP(map, portID) { map[portID >> 3] &= ~(1 << (portID & 0x7); }
-
-/**
- * returns true if map1 is a subset of map2 and false otherwise
- */
-#define IS_MAP_SUBSET(result, map1, map2) { int i = 0; result = true; for (; i < 32 ; i++) if ((map1[i] | map2[i]) != map2[i]) result = false; }
-
-/**
- * returns true is portID is part of map and false otherwise
- */
-#define IS_PORT_INCLUDED(portID, map) ((map[portID >> 3] & (1 << (portID & 0x7))) != 0)
-
-/**
- * returns the difference between map1 and map2 (ports included in map1 and not included in map2)
- */
-#define DIFF_MAPS(map, map1, map2) { int i = 0; for (; i < 32 ; i++) map[i] = map1[i] ^ (map1[i] & map2[i]); }
-
-/**
- * returns true if the maps collide (have at least one port in common) and false otherwise
- */
-#define MAPS_COLLIDE(result, map1, map2) { int i = 0; result = false; for (; i < 32 ; i++) if ((map1[i] & map2[i]) != 0) result = true; }
-
-/* size (number of ports) of a dependency map */
-#define GET_MAP_SIZE(map, size) { int i = 0, b = 0; size = 0; for (; i < 32 ; i++) { char y = map[i]; for (; b < 8 && (y >>= 1); b++) size += (y & 1); }}
-
-/* copy map2 into map1 */
-#define COPY_DEPENDENCY_MAP(map1, map2) { memcpy (map1, map2, sizeof (map1)); }
-
-/* definition of a port map size/port number which cannot be reached (we support at most 32 ports) */
-#define MAX_PORT_SIZE (0xFF)
-#define MAX_PORT_NUMBER (0xFF)
-
-#define IX_ETH_DB_CHECK_REFERENCE(ptr) { if ((ptr) == NULL) { return IX_ETH_DB_INVALID_ARG; } }
-#define IX_ETH_DB_CHECK_MAP(portID, map) { if (!IS_PORT_INCLUDED(portID, map)) { return IX_ETH_DB_INVALID_ARG; } }
-
-/* event queue macros */
-#define EVENT_QUEUE_WRAP(offset) ((offset) >= EVENT_QUEUE_SIZE ? (offset) - EVENT_QUEUE_SIZE : (offset))
-
-#define CAN_ENQUEUE(eventQueuePtr) ((eventQueuePtr)->length < EVENT_QUEUE_SIZE)
-
-#define QUEUE_HEAD(eventQueuePtr) (&(eventQueuePtr)->queue[EVENT_QUEUE_WRAP((eventQueuePtr)->base + (eventQueuePtr)->length)])
-
-#define QUEUE_TAIL(eventQueuePtr) (&(eventQueuePtr)->queue[(eventQueuePtr)->base])
-
-#define PUSH_UPDATE_QUEUE(eventQueuePtr) { (eventQueuePtr)->length++; }
-
-#define SHIFT_UPDATE_QUEUE(eventQueuePtr) \
- { \
- (eventQueuePtr)->base = EVENT_QUEUE_WRAP((eventQueuePtr)->base + 1); \
- (eventQueuePtr)->length--; \
- }
-
-#define RESET_QUEUE(eventQueuePtr) \
- { \
- (eventQueuePtr)->base = 0; \
- (eventQueuePtr)->length = 0; \
- }
-
-/* node stack macros - used to browse a tree without using a recursive function */
-#define NODE_STACK_INIT(stack) { (stack)->nodeCount = 0; }
-#define NODE_STACK_PUSH(stack, node, offset) { (stack)->nodes[(stack)->nodeCount] = (node); (stack)->offsets[(stack)->nodeCount++] = (offset); }
-#define NODE_STACK_POP(stack, node, offset) { (node) = (stack)->nodes[--(stack)->nodeCount]; offset = (stack)->offsets[(stack)->nodeCount]; }
-#define NODE_STACK_NONEMPTY(stack) ((stack)->nodeCount != 0)
-
-#ifndef IX_NDEBUG
-#define IX_ETH_DB_NPE_MSG_HISTORY_DEPTH (100)
-#define LOG_NPE_MSG(msg) \
- do { \
- UINT32 npeMsgHistoryIndex = (npeMsgHistoryLen++) % IX_ETH_DB_NPE_MSG_HISTORY_DEPTH; \
- npeMsgHistory[npeMsgHistoryIndex][0] = msg.data[0]; \
- npeMsgHistory[npeMsgHistoryIndex][1] = msg.data[1]; \
- } while (0);
-#else
-#define LOG_NPE_MSG() /* nothing */
-#endif
-
-/* ----------- Data -------------- */
-
-/* typedefs */
-
-typedef UINT32 (*HashFunction)(void *entity);
-typedef BOOL (*MatchFunction)(void *reference, void *entry);
-typedef void (*FreeFunction)(void *entry);
-
-/**
- * basic component of a hash table
- */
-typedef struct HashNode_t
-{
- void *data; /**< specific data */
- struct HashNode_t *next; /**< used for bucket chaining */
-
- __mempool__ struct HashNode_t *nextFree; /**< memory pool management */
-
- __lock__ IxOsalFastMutex lock; /**< node lock */
-} HashNode;
-
-/**
- * @brief hash table iterator definition
- *
- * an iterator is an object which can be used
- * to browse a hash table
- */
-typedef struct
-{
- UINT32 bucketIndex; /**< index of the currently iterated bucket */
- HashNode *previousNode; /**< reference to the previously iterated node within the current bucket */
- HashNode *node; /**< reference to the currently iterated node */
-} HashIterator;
-
-/**
- * definition of a MAC descriptor (a database record)
- */
-
-typedef enum
-{
- IX_ETH_DB_WIFI_AP_TO_STA = 0x0,
- IX_ETH_DB_WIFI_AP_TO_AP = 0x1
-} IxEthDBWiFiRecordType;
-
-typedef union
-{
- struct
- {
- UINT32 age;
- BOOL staticEntry; /**< true if this address is static (doesn't age) */
- } filteringData;
-
- struct
- {
- UINT32 age;
- BOOL staticEntry;
- UINT32 ieee802_1qTag;
- } filteringVlanData;
-
- struct
- {
- IxEthDBWiFiRecordType type; /**< AP_TO_AP (0x1) or AP_TO_STA (0x0) */
- UINT32 gwAddressIndex; /**< used only when linearizing the entries for NPE usage */
- UINT8 gwMacAddress[IX_IEEE803_MAC_ADDRESS_SIZE];
-
- __alignment__ UINT8 reserved2[2];
- } wifiData;
-} IxEthDBRecordData;
-
-typedef struct MacDescriptor_t
-{
- UINT8 macAddress[IX_IEEE803_MAC_ADDRESS_SIZE];
-
- __alignment__ UINT8 reserved1[2];
-
- UINT32 portID;
- IxEthDBRecordType type;
- IxEthDBRecordData recordData;
-
- /* used for internal operations, such as NPE linearization */
- void *internal;
-
- /* custom user data */
- void *user;
-
- __mempool__ struct MacDescriptor_t *nextFree; /**< memory pool management */
- __smartpointer__ UINT32 refCount; /**< smart pointer reference counter */
-} MacDescriptor;
-
-/**
- * hash table definition
- */
-typedef struct
-{
- HashNode *hashBuckets[NUM_BUCKETS];
- UINT32 numBuckets;
-
- __lock__ IxOsalFastMutex bucketLocks[NUM_BUCKETS];
-
- HashFunction entryHashFunction;
- MatchFunction *matchFunctions;
- FreeFunction freeFunction;
-} HashTable;
-
-typedef enum
-{
- IX_ETH_DB_MAC_KEY = 1,
- IX_ETH_DB_MAC_PORT_KEY = 2,
- IX_ETH_DB_MAC_VLAN_KEY = 3,
- IX_ETH_DB_MAX_KEY_INDEX = 3
-} IxEthDBSearchKeyType;
-
-typedef struct MacTreeNode_t
-{
- __smartpointer__ MacDescriptor *descriptor;
- struct MacTreeNode_t *left, *right;
-
- __mempool__ struct MacTreeNode_t *nextFree;
-} MacTreeNode;
-
-typedef IxEthDBStatus (*IxEthDBPortUpdateHandler)(IxEthDBPortId portID, IxEthDBRecordType type);
-
-typedef void (*IxEthDBNoteWriteFn)(void *address, MacTreeNode *node);
-
-typedef struct
-{
- BOOL updateEnabled; /**< true if updates are enabled for port */
- BOOL userControlled; /**< true if the user has manually used ixEthDBPortUpdateEnableSet */
- BOOL treeInitialized; /**< true if the NPE has received an initial tree */
- IxEthDBPortUpdateHandler updateHandler; /**< port update handler routine */
- void *npeUpdateZone; /**< port update memory zone */
- void *npeGwUpdateZone; /**< port update memory zone for gateways */
- void *vlanUpdateZone; /**< port update memory zone for VLAN tables */
- MacTreeNode *searchTree; /**< internal search tree, in MacTreeNode representation */
- BOOL searchTreePendingWrite; /**< true if searchTree holds a tree pending write to the port */
-} PortUpdateMethod;
-
-typedef struct
-{
- IxEthDBPortId portID; /**< port ID */
- BOOL enabled; /**< true if the port is enabled */
- BOOL agingEnabled; /**< true if aging on this port is enabled */
- BOOL initialized;
- IxEthDBPortMap dependencyPortMap; /**< dependency port map for this port */
- PortUpdateMethod updateMethod; /**< update method structure */
- BOOL macAddressUploaded; /**< true if the MAC address was uploaded into the port */
- UINT32 maxRxFrameSize; /**< maximum Rx frame size for this port */
- UINT32 maxTxFrameSize; /**< maximum Rx frame size for this port */
-
- UINT8 bbsid[6];
- __alignment__ UINT8 reserved[2];
- UINT32 frameControlDurationID; /**< Frame Control - Duration/ID WiFi control */
-
- IxEthDBVlanTag vlanTag; /**< default VLAN tag for port */
- IxEthDBPriorityTable priorityTable; /**< QoS <=> internal priority mapping */
- IxEthDBVlanSet vlanMembership;
- IxEthDBVlanSet transmitTaggingInfo;
- IxEthDBFrameFilter frameFilter;
- IxEthDBTaggingAction taggingAction;
-
- UINT32 npeFrameFilter;
- UINT32 npeTaggingAction;
-
- IxEthDBFirewallMode firewallMode;
- BOOL srcAddressFilterEnabled;
-
- BOOL stpBlocked;
-
- IxEthDBFeature featureCapability;
- IxEthDBFeature featureStatus;
-
- UINT32 ixEthDBTrafficClassAQMAssignments[IX_IEEE802_1Q_QOS_PRIORITY_COUNT];
-
- UINT32 ixEthDBTrafficClassCount;
-
- UINT32 ixEthDBTrafficClassAvailable;
-
-
-
- __lock__ IxOsalMutex npeAckLock;
-} PortInfo;
-
-/* list of port information structures indexed on port Ids */
-extern IX_ETH_DB_PUBLIC PortInfo ixEthDBPortInfo[IX_ETH_DB_NUMBER_OF_PORTS];
-
-typedef enum
-{
- IX_ETH_DB_ADD_FILTERING_RECORD = 0xFF0001,
- IX_ETH_DB_REMOVE_FILTERING_RECORD = 0xFF0002
-} PortEventType;
-
-typedef struct
-{
- UINT32 eventType;
- IxEthDBPortId portID;
- IxEthDBMacAddr macAddr;
- BOOL staticEntry;
-} PortEvent;
-
-typedef struct
-{
- PortEvent queue[EVENT_QUEUE_SIZE];
- UINT32 base;
- UINT32 length;
-} PortEventQueue;
-
-typedef struct
-{
- IxEthDBPortId portID; /**< originating port */
- MacDescriptor *macDescriptors[MAX_ELT_SIZE]; /**< addresses to be synced into db */
- UINT32 addressCount; /**< number of addresses */
-} TreeSyncInfo;
-
-typedef struct
-{
- MacTreeNode *nodes[MAX_ELT_SIZE];
- UINT32 offsets[MAX_ELT_SIZE];
- UINT32 nodeCount;
-} MacTreeNodeStack;
-
-/* Prototypes */
-
-/* ----------- Memory management -------------- */
-
-IX_ETH_DB_PUBLIC void ixEthDBInitMemoryPools(void);
-
-IX_ETH_DB_PUBLIC HashNode* ixEthDBAllocHashNode(void);
-IX_ETH_DB_PUBLIC void ixEthDBFreeHashNode(HashNode *);
-
-IX_ETH_DB_PUBLIC __smartpointer__ MacDescriptor* ixEthDBAllocMacDescriptor(void);
-IX_ETH_DB_PUBLIC __smartpointer__ MacDescriptor* ixEthDBCloneMacDescriptor(MacDescriptor *macDescriptor);
-IX_ETH_DB_PUBLIC __smartpointer__ void ixEthDBFreeMacDescriptor(MacDescriptor *);
-
-IX_ETH_DB_PUBLIC __smartpointer__ MacTreeNode* ixEthDBAllocMacTreeNode(void);
-IX_ETH_DB_PUBLIC __smartpointer__ MacTreeNode* ixEthDBCloneMacTreeNode(MacTreeNode *);
-IX_ETH_DB_PUBLIC __smartpointer__ void ixEthDBFreeMacTreeNode(MacTreeNode *);
-
-IX_ETH_DB_PUBLIC void ixEthDBPoolFreeMacTreeNode(MacTreeNode *);
-IX_ETH_DB_PUBLIC UINT32 ixEthDBSearchTreeUsageGet(MacTreeNode *tree);
-IX_ETH_DB_PUBLIC int ixEthDBShowMemoryStatus(void);
-
-/* Hash Table */
-IX_ETH_DB_PUBLIC void ixEthDBInitHash(HashTable *hashTable, UINT32 numBuckets, HashFunction entryHashFunction, MatchFunction *matchFunctions, FreeFunction freeFunction);
-
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBAddHashEntry(HashTable *hashTable, void *entry);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBRemoveHashEntry(HashTable *hashTable, int keyType, void *reference);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBSearchHashEntry(HashTable *hashTable, int keyType, void *reference, HashNode **searchResult);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPeekHashEntry(HashTable *hashTable, int keyType, void *reference);
-IX_ETH_DB_PUBLIC void ixEthDBReleaseHashNode(HashNode *node);
-
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBInitHashIterator(HashTable *hashTable, HashIterator *iterator);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBIncrementHashIterator(HashTable *hashTable, HashIterator *iterator);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBRemoveEntryAtHashIterator(HashTable *hashTable, HashIterator *iterator);
-IX_ETH_DB_PUBLIC void ixEthDBReleaseHashIterator(HashIterator *iterator);
-
-/* API Support */
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPortAddressSet(IxEthDBPortId portID, IxEthDBMacAddr *macAddr);
-IX_ETH_DB_PUBLIC void ixEthDBMaximumFrameSizeAckCallback(IxNpeMhNpeId npeID, IxNpeMhMessage msg);
-
-/* DB Core functions */
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBInit(void);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBAdd(MacDescriptor *newRecordTemplate, IxEthDBPortMap updateTrigger);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBRemove(MacDescriptor *templateRecord, IxEthDBPortMap updateTrigger);
-IX_ETH_DB_PUBLIC HashNode* ixEthDBSearch(IxEthDBMacAddr *macAddress, IxEthDBRecordType typeFilter);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPeek(IxEthDBMacAddr *macAddress, IxEthDBRecordType typeFilter);
-
-/* Learning support */
-IX_ETH_DB_PUBLIC UINT32 ixEthDBAddressCompare(UINT8 *mac1, UINT8 *mac2);
-IX_ETH_DB_PUBLIC BOOL ixEthDBAddressMatch(void *reference, void *entry);
-IX_ETH_DB_PUBLIC UINT32 ixEthDBEntryXORHash(void *macDescriptor);
-IX_ETH_DB_PUBLIC UINT32 ixEthDBKeyXORHash(void *macAddress);
-
-/* Port updates */
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBNPEUpdateHandler(IxEthDBPortId portID, IxEthDBRecordType type);
-IX_ETH_DB_PUBLIC void ixEthDBUpdatePortLearningTrees(IxEthDBPortMap triggerPorts);
-IX_ETH_DB_PUBLIC void ixEthDBNPEAccessRequest(IxEthDBPortId portID);
-IX_ETH_DB_PUBLIC void ixEthDBUpdateLock(void);
-IX_ETH_DB_PUBLIC void ixEthDBUpdateUnlock(void);
-IX_ETH_DB_PUBLIC MacTreeNode* ixEthDBQuery(MacTreeNode *searchTree, IxEthDBPortMap query, IxEthDBRecordType recordFilter, UINT32 maximumEntries);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBFirewallUpdate(IxEthDBPortId portID, void *address, UINT32 epDelta);
-
-/* Init/unload */
-IX_ETH_DB_PUBLIC void ixEthDBPortSetAckCallback(IxNpeMhNpeId npeID, IxNpeMhMessage msg);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBEventProcessorInit(void);
-IX_ETH_DB_PUBLIC void ixEthDBPortInit(IxEthDBPortId portID);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID);
-IX_ETH_DB_PUBLIC void ixEthDBNPEUpdateAreasInit(void);
-IX_ETH_DB_PUBLIC UINT32 ixEthDBMatchMethodsRegister(MatchFunction *matchFunctions);
-IX_ETH_DB_PUBLIC UINT32 ixEthDBRecordSerializeMethodsRegister(void);
-IX_ETH_DB_PUBLIC UINT32 ixEthDBUpdateTypeRegister(BOOL *typeArray);
-IX_ETH_DB_PUBLIC void ixEthDBNPEUpdateAreasUnload(void);
-IX_ETH_DB_PUBLIC void ixEthDBFeatureCapabilityScan(void);
-IX_ETH_DB_PUBLIC UINT32 ixEthDBKeyTypeRegister(UINT32 *keyType);
-
-/* Event processing */
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBDefaultEventCallbackEnable(IxEthDBPortId portID, BOOL enable);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBTriggerAddPortUpdate(IxEthDBMacAddr *macAddr, IxEthDBPortId portID, BOOL staticEntry);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBTriggerRemovePortUpdate(IxEthDBMacAddr *macAddr, IxEthDBPortId portID);
-IX_ETH_DB_PUBLIC void ixEthDBNPEEventCallback(IxNpeMhNpeId npeID, IxNpeMhMessage msg);
-
-/* NPE adaptor */
-IX_ETH_DB_PUBLIC void ixEthDBGetMacDatabaseCbk(IxNpeMhNpeId npeID, IxNpeMhMessage msg);
-IX_ETH_DB_PUBLIC void ixEthDBNpeMsgAck(IxNpeMhNpeId npeID, IxNpeMhMessage msg);
-IX_ETH_DB_PUBLIC void ixEthDBNPESyncScan(IxEthDBPortId portID, void *eltBaseAddress, UINT32 eltSize);
-IX_ETH_DB_PUBLIC void ixEthDBNPETreeWrite(IxEthDBRecordType type, UINT32 totalSize, void *baseAddress, MacTreeNode *tree, UINT32 *blocks, UINT32 *startIndex);
-IX_ETH_DB_PUBLIC void ixEthDBNPEGatewayNodeWrite(void *address, MacTreeNode *node);
-
-/* Other public API functions */
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBStartLearningFunction(void);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBStopLearningFunction(void);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPortUpdateEnableSet(IxEthDBPortId portID, BOOL enableUpdate);
-
-/* Maximum Tx/Rx public functions */
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBFilteringPortMaximumRxFrameSizeSet(IxEthDBPortId portID, UINT32 maximumRxFrameSize);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBFilteringPortMaximumTxFrameSizeSet(IxEthDBPortId portID, UINT32 maximumTxFrameSize);
-
-/* VLAN-related */
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPortVlanTableSet(IxEthDBPortId portID, IxEthDBVlanSet portVlanTable, IxEthDBVlanSet vlanSet);
-
-/* Record search */
-IX_ETH_DB_PUBLIC BOOL ixEthDBAddressRecordMatch(void *untypedReference, void *untypedEntry);
-IX_ETH_DB_PUBLIC BOOL ixEthDBVlanRecordMatch(void *untypedReference, void *untypedEntry);
-IX_ETH_DB_PUBLIC BOOL ixEthDBPortRecordMatch(void *untypedReference, void *untypedEntry);
-IX_ETH_DB_PUBLIC BOOL ixEthDBNullMatch(void *reference, void *entry);
-IX_ETH_DB_PUBLIC HashNode* ixEthDBPortSearch(IxEthDBMacAddr *macAddress, IxEthDBPortId portID, IxEthDBRecordType typeFilter);
-IX_ETH_DB_PUBLIC HashNode* ixEthDBVlanSearch(IxEthDBMacAddr *macAddress, IxEthDBVlanId vlanID, IxEthDBRecordType typeFilter);
-
-/* Utilities */
-IX_ETH_DB_PUBLIC const char* mac2string(const unsigned char *mac);
-IX_ETH_DB_PUBLIC void showHashInfo(void);
-IX_ETH_DB_PUBLIC int ixEthDBAnalyzeHash(void);
-IX_ETH_DB_PUBLIC const char* errorString(IxEthDBStatus error);
-IX_ETH_DB_PUBLIC int numHashElements(void);
-IX_ETH_DB_PUBLIC void zapHashtable(void);
-IX_ETH_DB_PUBLIC BOOL ixEthDBCheckSingleBitValue(UINT32 value);
-
-/* Single Eth NPE Check */
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBSingleEthNpeCheck(IxEthDBPortId portId);
-
-#endif /* IxEthDB_p_H */
-
+++ /dev/null
-/**
- * @file IxEthMii.h
- *
- * @brief this file contains the public API of @ref IxEthMii component
- *
- * Design notes :
- * The main intent of this API is to inplement MII high level fonctionalitoes
- * to support the codelets provided with the IXP400 software releases. It
- * superceedes previous interfaces provided with @ref IxEThAcc component.
- *
- * This API has been tested with the PHYs provided with the
- * IXP400 development platforms. It may not work for specific Ethernet PHYs
- * used on specific boards.
- *
- * This source code detects and interface the LXT972, LXT973 and KS6995
- * Ethernet PHYs.
- *
- * This source code should be considered as an example which may need
- * to be adapted for different hardware implementations.
- *
- * It is strongly recommended to use public domain and GPL utilities
- * like libmii, mii-diag for MII interface support.
- *
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxEthMii_H
-#define IxEthMii_H
-
-#include <IxTypes.h>
-
-/**
- * @defgroup IxEthMii IXP400 Ethernet Phy Access (IxEthMii) API
- *
- * @brief ethMii is a library that does provides access to the
- * Ethernet PHYs
- *
- *@{
- */
-
-/**
- * @ingroup IxEthMii
- *
- * @fn ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount)
- *
- * @brief Scan the MDIO bus for PHYs
- * This function scans PHY addresses 0 through 31, and sets phyPresent[n] to
- * true if a phy is discovered at address n.
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock.
- *
- * @param phyPresent BOOL [in] - boolean array of IXP425_ETH_ACC_MII_MAX_ADDR entries
- * @param maxPhyCount UINT32 [in] - number of PHYs to search for (the scan will stop when
- * the indicated number of PHYs is found).
- *
- * @return IX_STATUS
- * - IX_ETH_ACC_SUCCESS
- * - IX_ETH_ACC_FAIL : invalid arguments.
- *
- * <hr>
- */
-PUBLIC IX_STATUS ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount);
-
-/**
- * @ingroup IxEthMii
- *
- * @fn ixEthMiiPhyConfig(UINT32 phyAddr,
- BOOL speed100,
- BOOL fullDuplex,
- BOOL autonegotiate)
- *
- *
- * @brief Configure a PHY
- * Configure a PHY's speed, duplex and autonegotiation status
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock.
- *
- * @param phyAddr UINT32 [in]
- * @param speed100 BOOL [in] - set to true for 100Mbit/s operation, false for 10Mbit/s
- * @param fullDuplex BOOL [in] - set to true for Full Duplex, false for Half Duplex
- * @param autonegotiate BOOL [in] - set to true to enable autonegotiation
- *
- * @return IX_STATUS
- * - IX_SUCCESS
- * - IX_FAIL : invalid arguments.
- *
- * <hr>
- */
-PUBLIC IX_STATUS ixEthMiiPhyConfig(UINT32 phyAddr,
- BOOL speed100,
- BOOL fullDuplex,
- BOOL autonegotiate);
-
-/**
- * @ingroup IxEthMii
- *
- * @fn ixEthMiiPhyLoopbackEnable(UINT32 phyAddr)
- *
- *
- * @brief Enable PHY Loopback in a specific Eth MII port
- *
- * @note When PHY Loopback is enabled, frames sent out to the PHY from the
- * IXP400 will be looped back to the IXP400. They will not be transmitted out
- * on the wire.
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31)
- *
- * @return IX_STATUS
- * - IX_SUCCESS
- * - IX_FAIL : invalid arguments.
- * <hr>
- */
-PUBLIC IX_STATUS
-ixEthMiiPhyLoopbackEnable (UINT32 phyAddr);
-
-/**
- * @ingroup IxEthMii
- *
- * @fn ixEthMiiPhyLoopbackDisable(UINT32 phyAddr)
- *
- *
- * @brief Disable PHY Loopback in a specific Eth MII port
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31)
- *
- * @return IX_STATUS
- * - IX_SUCCESS
- * - IX_FAIL : invalid arguments.
- * <hr>
- */
-PUBLIC IX_STATUS
-ixEthMiiPhyLoopbackDisable (UINT32 phyAddr);
-
-/**
- * @ingroup IxEthMii
- *
- * @fn ixEthMiiPhyReset(UINT32 phyAddr)
- *
- * @brief Reset a PHY
- * Reset a PHY
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock.
- *
- * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31)
- *
- * @return IX_STATUS
- * - IX_SUCCESS
- * - IX_FAIL : invalid arguments.
- *
- * <hr>
- */
-PUBLIC IX_STATUS ixEthMiiPhyReset(UINT32 phyAddr);
-
-
-/**
- * @ingroup IxEthMii
- *
- * @fn ixEthMiiLinkStatus(UINT32 phyAddr,
- BOOL *linkUp,
- BOOL *speed100,
- BOOL *fullDuplex,
- BOOL *autoneg)
- *
- * @brief Retrieve the current status of a PHY
- * Retrieve the link, speed, duplex and autonegotiation status of a PHY
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock.
- *
- * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31)
- * @param linkUp BOOL [out] - set to true if the link is up
- * @param speed100 BOOL [out] - set to true indicates 100Mbit/s, false indicates 10Mbit/s
- * @param fullDuplex BOOL [out] - set to true indicates Full Duplex, false indicates Half Duplex
- * @param autoneg BOOL [out] - set to true indicates autonegotiation is enabled, false indicates autonegotiation is disabled
- *
- * @return IX_STATUS
- * - IX_SUCCESS
- * - IX_FAIL : invalid arguments.
- *
- * <hr>
- */
-PUBLIC IX_STATUS ixEthMiiLinkStatus(UINT32 phyAddr,
- BOOL *linkUp,
- BOOL *speed100,
- BOOL *fullDuplex,
- BOOL *autoneg);
-
-/**
- * @ingroup IxEthMii
- *
- * @fn ixEthMiiPhyShow (UINT32 phyAddr)
- *
- *
- * @brief Display information on a specified PHY
- * Display link status, speed, duplex and Auto Negotiation status
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock.
- *
- * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31)
- *
- * @return IX_STATUS
- * - IX_SUCCESS
- * - IX_FAIL : invalid arguments.
- *
- * <hr>
- */
-PUBLIC IX_STATUS ixEthMiiPhyShow (UINT32 phyAddr);
-
-#endif /* ndef IxEthMii_H */
-/**
- *@}
- */
+++ /dev/null
-/**
- * @file IxEthMii_p.h
- *
- * @author Intel Corporation
- * @date
- *
- * @brief MII Header file
- *
- * Design Notes:
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxEthMii_p_H
-#define IxEthMii_p_H
-
-
-/* MII definitions - these have been verified against the LXT971 and
- LXT972 PHYs*/
-
-#define IX_ETH_MII_MAX_REG_NUM 0x20 /* max number of registers */
-
-#define IX_ETH_MII_CTRL_REG 0x0 /* Control Register */
-#define IX_ETH_MII_STAT_REG 0x1 /* Status Register */
-#define IX_ETH_MII_PHY_ID1_REG 0x2 /* PHY identifier 1 Register */
-#define IX_ETH_MII_PHY_ID2_REG 0x3 /* PHY identifier 2 Register */
-#define IX_ETH_MII_AN_ADS_REG 0x4 /* Auto-Negotiation */
- /* Advertisement Register */
-#define IX_ETH_MII_AN_PRTN_REG 0x5 /* Auto-Negotiation */
- /* partner ability Register */
-#define IX_ETH_MII_AN_EXP_REG 0x6 /* Auto-Negotiation */
- /* Expansion Register */
-#define IX_ETH_MII_AN_NEXT_REG 0x7 /* Auto-Negotiation */
- /* next-page transmit Register */
-
-#define IX_ETH_MII_STAT2_REG 0x11 /* Status Register 2*/
-
-
-/* MII control register bit */
-
-#define IX_ETH_MII_CR_COLL_TEST 0x0080 /* collision test */
-#define IX_ETH_MII_CR_FDX 0x0100 /* FDX =1, half duplex =0 */
-#define IX_ETH_MII_CR_RESTART 0x0200 /* restart auto negotiation */
-#define IX_ETH_MII_CR_ISOLATE 0x0400 /* isolate PHY from MII */
-#define IX_ETH_MII_CR_POWER_DOWN 0x0800 /* power down */
-#define IX_ETH_MII_CR_AUTO_EN 0x1000 /* auto-negotiation enable */
-#define IX_ETH_MII_CR_100 0x2000 /* 0 = 10mb, 1 = 100mb */
-#define IX_ETH_MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
-#define IX_ETH_MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
-#define IX_ETH_MII_CR_NORM_EN 0x0000 /* just enable the PHY */
-#define IX_ETH_MII_CR_DEF_0_MASK 0xca7f /* they must return zero */
-#define IX_ETH_MII_CR_RES_MASK 0x007f /* reserved bits, return zero */
-
-/* MII Status register bit definitions */
-
-#define IX_ETH_MII_SR_LINK_STATUS 0x0004 /* link Status -- 1 = link */
-#define IX_ETH_MII_SR_AUTO_SEL 0x0008 /* auto speed select capable */
-#define IX_ETH_MII_SR_REMOTE_FAULT 0x0010 /* Remote fault detect */
-#define IX_ETH_MII_SR_AUTO_NEG 0x0020 /* auto negotiation complete */
-#define IX_ETH_MII_SR_10T_HALF_DPX 0x0800 /* 10BaseT HD capable */
-#define IX_ETH_MII_SR_10T_FULL_DPX 0x1000 /* 10BaseT FD capable */
-#define IX_ETH_MII_SR_TX_HALF_DPX 0x2000 /* TX HD capable */
-#define IX_ETH_MII_SR_TX_FULL_DPX 0x4000 /* TX FD capable */
-#define IX_ETH_MII_SR_T4 0x8000 /* T4 capable */
-#define IX_ETH_MII_SR_ABIL_MASK 0xff80 /* abilities mask */
-#define IX_ETH_MII_SR_EXT_CAP 0x0001 /* extended capabilities */
-
-
-/* LXT971/2 Status 2 register bit definitions */
-#define IX_ETH_MII_SR2_100 0x4000
-#define IX_ETH_MII_SR2_TX 0x2000
-#define IX_ETH_MII_SR2_RX 0x1000
-#define IX_ETH_MII_SR2_COL 0x0800
-#define IX_ETH_MII_SR2_LINK 0x0400
-#define IX_ETH_MII_SR2_FD 0x0200
-#define IX_ETH_MII_SR2_AUTO 0x0100
-#define IX_ETH_MII_SR2_AUTO_CMPLT 0x0080
-#define IX_ETH_MII_SR2_POLARITY 0x0020
-#define IX_ETH_MII_SR2_PAUSE 0x0010
-#define IX_ETH_MII_SR2_ERROR 0x0008
-
-/* MII Link Code word bit definitions */
-
-#define IX_ETH_MII_BP_FAULT 0x2000 /* remote fault */
-#define IX_ETH_MII_BP_ACK 0x4000 /* acknowledge */
-#define IX_ETH_MII_BP_NP 0x8000 /* nexp page is supported */
-
-/* MII Next Page bit definitions */
-
-#define IX_ETH_MII_NP_TOGGLE 0x0800 /* toggle bit */
-#define IX_ETH_MII_NP_ACK2 0x1000 /* acknowledge two */
-#define IX_ETH_MII_NP_MSG 0x2000 /* message page */
-#define IX_ETH_MII_NP_ACK1 0x4000 /* acknowledge one */
-#define IX_ETH_MII_NP_NP 0x8000 /* nexp page will follow */
-
-/* MII Expansion Register bit definitions */
-
-#define IX_ETH_MII_EXP_FAULT 0x0010 /* parallel detection fault */
-#define IX_ETH_MII_EXP_PRTN_NP 0x0008 /* link partner next-page able */
-#define IX_ETH_MII_EXP_LOC_NP 0x0004 /* local PHY next-page able */
-#define IX_ETH_MII_EXP_PR 0x0002 /* full page received */
-#define IX_ETH_MII_EXP_PRT_AN 0x0001 /* link partner auto neg able */
-
-/* technology ability field bit definitions */
-
-#define IX_ETH_MII_TECH_10BASE_T 0x0020 /* 10Base-T */
-#define IX_ETH_MII_TECH_10BASE_FD 0x0040 /* 10Base-T Full Duplex */
-#define IX_ETH_MII_TECH_100BASE_TX 0x0080 /* 100Base-TX */
-#define IX_ETH_MII_TECH_100BASE_TX_FD 0x0100 /* 100Base-TX Full Duplex */
-
-#define IX_ETH_MII_TECH_100BASE_T4 0x0200 /* 100Base-T4 */
-#define IX_ETH_MII_ADS_TECH_MASK 0x1fe0 /* technology abilities mask */
-#define IX_ETH_MII_TECH_MASK IX_ETH_MII_ADS_TECH_MASK
-#define IX_ETH_MII_ADS_SEL_MASK 0x001f /* selector field mask */
-
-#define IX_ETH_MII_AN_FAIL 0x10 /* auto-negotiation fail */
-#define IX_ETH_MII_STAT_FAIL 0x20 /* errors in the status register */
-#define IX_ETH_MII_PHY_NO_ABLE 0x40 /* the PHY lacks some abilities */
-
-/* Definitions for MII access routines*/
-
-#define IX_ETH_MII_GO BIT(31)
-#define IX_ETH_MII_WRITE BIT(26)
-#define IX_ETH_MII_TIMEOUT_10TH_SECS (5)
-#define IX_ETH_MII_10TH_SEC_IN_MILLIS (100)
-#define IX_ETH_MII_READ_FAIL BIT(31)
-
-/* When we reset the PHY we delay for 2 seconds to allow the reset to
- complete*/
-#define IX_ETH_MII_RESET_DELAY_MS (2000)
-#define IX_ETH_MII_RESET_POLL_MS (50)
-
-#define IX_ETH_MII_REG_SHL 16
-#define IX_ETH_MII_ADDR_SHL 21
-
-/* supported PHYs */
-#define IX_ETH_MII_LXT971_PHY_ID 0x001378E0
-#define IX_ETH_MII_LXT972_PHY_ID 0x001378E2
-#define IX_ETH_MII_LXT973_PHY_ID 0x00137A10
-#define IX_ETH_MII_LXT973A3_PHY_ID 0x00137A11
-#define IX_ETH_MII_KS8995_PHY_ID 0x00221450
-#define IX_ETH_MII_LXT9785_PHY_ID 0x001378FF
-
-
-#define IX_ETH_MII_INVALID_PHY_ID 0x00000000
-#define IX_ETH_MII_UNKNOWN_PHY_ID 0xffffffff
-
-#endif /*IxEthAccMii_p_H*/
+++ /dev/null
-#ifndef __doxygen_HIDE /* This file is not part of the API */
-
-/**
- * @file IxEthNpe.h
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxEthNpe IXP400 Ethernet NPE (IxEthNpe) API
- *
- * @brief Contains the API for Ethernet NPE.
- *
- * All messages given to NPE, get back an acknowledgment. The acknowledgment
- * is identical to the message sent to the NPE (except for NPE_GETSTATUS message).
- *
- * @{
- */
-
-
-/*--------------------------------------------------------------------------
- * APB Message IDs - XScale->NPE
- *------------------------------------------------------------------------*/
-
-/**
- * @def IX_ETHNPE_NPE_GETSTATUS
- *
- * @brief Request from the XScale client for the NPE to return the firmware
- * version of the currently executing image.
- *
- * Acknowledgment message id is same as the request message id.
- * NPE returns the firmware version ID to XScale.
- */
-#define IX_ETHNPE_NPE_GETSTATUS 0x00
-
-/**
- * @def IX_ETHNPE_EDB_SETPORTADDRESS
- *
- * @brief Request from the XScale client for the NPE to set the Ethernet
- * port's port ID and MAC address.
- */
-#define IX_ETHNPE_EDB_SETPORTADDRESS 0x01
-
-/**
- * @def IX_ETHNPE_EDB_GETMACADDRESSDATABASE
- *
- * @brief Request from XScale client to the NPE requesting upload of
- * Ethernet Filtering Database or Header Conversion Database from NPE's
- * data memory to XScale accessible SDRAM.
- */
-#define IX_ETHNPE_EDB_GETMACADDRESSDATABASE 0x02
-
-/**
- * @def IX_ETHNPE_EDB_SETMACADDRESSSDATABASE
- *
- * @brief Request from XScale client to the NPE requesting download of
- * Ethernet Filtering Database or Header Conversion Database from SDRAM
- * to the NPE's datamemory.
- */
-#define IX_ETHNPE_EDB_SETMACADDRESSSDATABASE 0x03
-
-/**
- * @def IX_ETHNPE_GETSTATS
- *
- * @brief Request from the XScale client for the current MAC port statistics
- * data to be written to the (empty) statistics structure and the specified
- * location in externa memory.
- */
-#define IX_ETHNPE_GETSTATS 0x04
-
-/**
- * @def IX_ETHNPE_RESETSTATS
- *
- * @brief Request from the XScale client to the NPE to reset all of its internal
- * MAC port statistics state variables.
- *
- * As a side effect, this message entails an implicit request that the NPE
- * write the current MAC port statistics into the MAC statistics structure
- * at the specified location in external memory.
- */
-#define IX_ETHNPE_RESETSTATS 0x05
-
-/**
- * @def IX_ETHNPE_SETMAXFRAMELENGTHS
- *
- * @brief Request from the XScale client to the NPE to configure maximum framelengths
- * and block sizes in receive and transmit direction.
- */
-#define IX_ETHNPE_SETMAXFRAMELENGTHS 0x06
-
-/**
- * @def IX_ETHNPE_VLAN_SETRXTAGMODE
- *
- * @brief Request from the XScale client to the NPE to configure VLAN frame type
- * filtering and VLAN the tagging mode for the receiver.
- */
-#define IX_ETHNPE_VLAN_SETRXTAGMODE 0x07
-
-/**
- * @def IX_ETHNPE_VLAN_SETDEFAULTRXVID
- *
- * @brief Request from the XScale client to the NPE to set receiver's default
- * VLAN tag (PVID)and internal traffic class.
- */
-#define IX_ETHNPE_VLAN_SETDEFAULTRXVID 0x08
-
-/**
- * @def IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY
- *
- * @brief Request from the XScale client to the NPE to configure VLAN Port
- * membership and Tx tagging for 8 consecutive VLANID's.
- */
-#define IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY 0x09
-
-/**
- * @def IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE
- *
- * @brief Request from the XScale client to the NPE to configure VLAN Port
- * membership and Tx tagging for a range of VLANID's.
- */
-#define IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE 0x0A
-
-/**
- * @def IX_ETHNPE_VLAN_SETRXQOSENTRY
- *
- * @brief Request from the XScale client to the NPE to map a user priority
- * to QoS class and an AQM queue number.
- */
-#define IX_ETHNPE_VLAN_SETRXQOSENTRY 0x0B
-
-/**
- * @def IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE
- *
- * @brief Request from the XScale client to the NPE to enable or disable
- * portID extraction from VLAN-tagged frames for the specified port.
- */
-#define IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C
-
-/**
- * @def IX_ETHNPE_STP_SETBLOCKINGSTATE
- *
- * @brief Request from the XScale client to the NPE to block or unblock
- * forwarding for spanning tree BPDUs.
- */
-#define IX_ETHNPE_STP_SETBLOCKINGSTATE 0x0D
-
-/**
- * @def IX_ETHNPE_FW_SETFIREWALLMODE
- *
- * @brief Request from the XScale client to the NPE to configure firewall
- * services modes of operation and/or download Ethernet Firewall Database from
- * SDRAM to NPE.
- */
-#define IX_ETHNPE_FW_SETFIREWALLMODE 0x0E
-
-/**
- * @def IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID
- *
- * @brief Request from the XScale client to the NPE to set global frame control
- * and duration/ID field for the 802.3 to 802.11 protocol header conversion
- * service.
- */
-#define IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID 0x0F
-
-/**
- * @def IX_ETHNPE_PC_SETBBSID
- *
- * @brief Request from the XScale client to the NPE to set global BBSID field
- * value for the 802.3 to 802.11 protocol header conversion service.
- */
-#define IX_ETHNPE_PC_SETBBSID 0x10
-
-/**
- * @def IX_ETHNPE_PC_SETAPMACTABLE
- *
- * @brief Request from the XScale client to the NPE to update a block/section/
- * range of the AP MAC Address Table.
- */
-#define IX_ETHNPE_PC_SETAPMACTABLE 0x11
-
-/**
- * @def IX_ETHNPE_SETLOOPBACK_MODE
- *
- * @brief Turn on or off the NPE frame loopback.
- */
-#define IX_ETHNPE_SETLOOPBACK_MODE (0x12)
-
-/*--------------------------------------------------------------------------
- * APB Message IDs - NPE->XScale
- *------------------------------------------------------------------------*/
-
-/**
- * @def IX_ETHNPE_NPE_GETSTATUS_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_NPE_GETSTATUS message. NPE firmware version
- * id is returned in the message.
- */
-#define IX_ETHNPE_NPE_GETSTATUS_ACK 0x00
-
-/**
- * @def IX_ETHNPE_EDB_SETPORTADDRESS_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_EDB_SETPORTADDRESS message.
- */
-#define IX_ETHNPE_EDB_SETPORTADDRESS_ACK 0x01
-
-/**
- * @def IX_ETHNPE_EDB_GETMACADDRESSDATABASE_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_EDB_GETMACADDRESSDATABASE message
- */
-#define IX_ETHNPE_EDB_GETMACADDRESSDATABASE_ACK 0x02
-
-/**
- * @def IX_ETHNPE_EDB_SETMACADDRESSSDATABASE_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_EDB_SETMACADDRESSSDATABASE message.
- */
-#define IX_ETHNPE_EDB_SETMACADDRESSSDATABASE_ACK 0x03
-
-/**
- * @def IX_ETHNPE_GETSTATS_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_GETSTATS message.
- */
-#define IX_ETHNPE_GETSTATS_ACK 0x04
-
-/**
- * @def IX_ETHNPE_RESETSTATS_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_RESETSTATS message.
- */
-#define IX_ETHNPE_RESETSTATS_ACK 0x05
-
-/**
- * @def IX_ETHNPE_SETMAXFRAMELENGTHS_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_SETMAXFRAMELENGTHS message.
- */
-#define IX_ETHNPE_SETMAXFRAMELENGTHS_ACK 0x06
-
-/**
- * @def IX_ETHNPE_VLAN_SETRXTAGMODE_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_VLAN_SETRXTAGMODE message.
- */
-#define IX_ETHNPE_VLAN_SETRXTAGMODE_ACK 0x07
-
-/**
- * @def IX_ETHNPE_VLAN_SETDEFAULTRXVID_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_VLAN_SETDEFAULTRXVID message.
- */
-#define IX_ETHNPE_VLAN_SETDEFAULTRXVID_ACK 0x08
-
-/**
- * @def IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY message.
- */
-#define IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY_ACK 0x09
-
-/**
- * @def IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE message.
- */
-#define IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE_ACK 0x0A
-
-/**
- * @def IX_ETHNPE_VLAN_SETRXQOSENTRY_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_VLAN_SETRXQOSENTRY message.
- */
-#define IX_ETHNPE_VLAN_SETRXQOSENTRY_ACK 0x0B
-
-/**
- * @def IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE message.
- */
-#define IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE_ACK 0x0C
-
-/**
- * @def IX_ETHNPE_STP_SETBLOCKINGSTATE_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_STP_SETBLOCKINGSTATE message.
- */
-#define IX_ETHNPE_STP_SETBLOCKINGSTATE_ACK 0x0D
-
-/**
- * @def IX_ETHNPE_FW_SETFIREWALLMODE_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_FW_SETFIREWALLMODE message.
- */
-#define IX_ETHNPE_FW_SETFIREWALLMODE_ACK 0x0E
-
-/**
- * @def IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID message.
- */
-#define IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID_ACK 0x0F
-
-/**
- * @def IX_ETHNPE_PC_SETBBSID_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_PC_SETBBSID message.
- */
-#define IX_ETHNPE_PC_SETBBSID_ACK 0x10
-
-/**
- * @def IX_ETHNPE_PC_SETAPMACTABLE_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_PC_SETAPMACTABLE message.
- */
-#define IX_ETHNPE_PC_SETAPMACTABLE_ACK 0x11
-
-/**
- * @def IX_ETHNPE_SETLOOPBACK_MODE_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_SETLOOPBACK_MODE message.
- */
-#define IX_ETHNPE_SETLOOPBACK_MODE_ACK (0x12)
-
-/*--------------------------------------------------------------------------
- * Queue Manager Queue entry bit field boundary definitions
- *------------------------------------------------------------------------*/
-
-/**
- * @def MASK(hi,lo)
- *
- * @brief Macro for mask
- */
-#define MASK(hi,lo) (((1 << (1 + ((hi) - (lo)))) - 1) << (lo))
-
-/**
- * @def BITS(x,hi,lo)
- *
- * @brief Macro for bits
- */
-#define BITS(x,hi,lo) (((x) & MASK(hi,lo)) >> (lo))
-
-/**
- * @def IX_ETHNPE_QM_Q_RXENET_LENGTH_MASK
- *
- * @brief QMgr Queue LENGTH field mask
- */
-#define IX_ETHNPE_QM_Q_RXENET_LENGTH_MASK 0x3fff
-
-/**
- * @def IX_ETHNPE_QM_Q_FIELD_FLAG_R
- *
- * @brief QMgr Queue FLAG field right boundary
- */
-#define IX_ETHNPE_QM_Q_FIELD_FLAG_R 20
-
-/**
- * @def IX_ETHNPE_QM_Q_FIELD_FLAG_MASK
- *
- * @brief QMgr Queue FLAG field mask
- *
- * Multicast bit : BIT(4)
- * Broadcast bit : BIT(5)
- * IP bit : BIT(6) (linux only)
- *
- */
-#ifdef __vxworks
-#define IX_ETHNPE_QM_Q_FIELD_FLAG_MASK 0x30
-#else
-#define IX_ETHNPE_QM_Q_FIELD_FLAG_MASK 0x70
-#endif
-
-
-/**
- * @def IX_ETHNPE_QM_Q_FIELD_NPEID_L
- *
- * @brief QMgr Queue NPE ID field left boundary
- */
-#define IX_ETHNPE_QM_Q_FIELD_NPEID_L 1
-
-/**
- * @def IX_ETHNPE_QM_Q_FIELD_NPEID_R
- *
- * @brief QMgr Queue NPE ID field right boundary
- */
-#define IX_ETHNPE_QM_Q_FIELD_NPEID_R 0
-
-/**
- * @def IX_ETHNPE_QM_Q_FIELD_PRIOR_L
- *
- * @brief QMgr Queue Priority field left boundary
- */
-#define IX_ETHNPE_QM_Q_FIELD_PRIOR_L 2
-
-/**
- * @def IX_ETHNPE_QM_Q_FIELD_PRIOR_R
- *
- * @brief QMgr Queue Priority field right boundary
- */
-#define IX_ETHNPE_QM_Q_FIELD_PRIOR_R 0
-
-/**
- * @def IX_ETHNPE_QM_Q_FIELD_ADDR_L
- *
- * @brief QMgr Queue Address field left boundary
- */
-#define IX_ETHNPE_QM_Q_FIELD_ADDR_L 31
-
-/**
- * @def IX_ETHNPE_QM_Q_FIELD_ADDR_R
- *
- * @brief QMgr Queue Address field right boundary
- */
-#define IX_ETHNPE_QM_Q_FIELD_ADDR_R 5
-
-/*--------------------------------------------------------------------------
- * Queue Manager Queue entry bit field masks
- *------------------------------------------------------------------------*/
-
-/**
- * @def IX_ETHNPE_QM_Q_FREEENET_ADDR_MASK
- *
- * @brief Macro to mask the Address field of the FreeEnet Queue Manager Entry
- */
-#define IX_ETHNPE_QM_Q_FREEENET_ADDR_MASK \
- MASK (IX_ETHNPE_QM_Q_FIELD_ADDR_L, \
- IX_ETHNPE_QM_Q_FIELD_ADDR_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_RXENET_NPEID_MASK
- *
- * @brief Macro to mask the NPE ID field of the RxEnet Queue Manager Entry
- */
-#define IX_ETHNPE_QM_Q_RXENET_NPEID_MASK \
- MASK (IX_ETHNPE_QM_Q_FIELD_NPEID_L, \
- IX_ETHNPE_QM_Q_FIELD_NPEID_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_RXENET_ADDR_MASK
- *
- * @brief Macro to mask the Mbuf Address field of the RxEnet Queue Manager Entry
- */
-#define IX_ETHNPE_QM_Q_RXENET_ADDR_MASK \
- MASK (IX_ETHNPE_QM_Q_FIELD_ADDR_L, \
- IX_ETHNPE_QM_Q_FIELD_ADDR_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_TXENET_PRIOR_MASK
- *
- * @brief Macro to mask the Priority field of the TxEnet Queue Manager Entry
- */
-#define IX_ETHNPE_QM_Q_TXENET_PRIOR_MASK \
- MASK (IX_ETHNPE_QM_Q_FIELD_PRIOR_L, \
- IX_ETHNPE_QM_Q_FIELD_PRIOR_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_TXENET_ADDR_MASK
- *
- * @brief Macro to mask the Mbuf Address field of the TxEnet Queue Manager Entry
- */
-#define IX_ETHNPE_QM_Q_TXENET_ADDR_MASK \
- MASK (IX_ETHNPE_QM_Q_FIELD_ADDR_L, \
- IX_ETHNPE_QM_Q_FIELD_ADDR_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_TXENETDONE_NPEID_MASK
- *
- * @brief Macro to mask the NPE ID field of the TxEnetDone Queue Manager Entry
- */
-#define IX_ETHNPE_QM_Q_TXENETDONE_NPEID_MASK \
- MASK (IX_ETHNPE_QM_Q_FIELD_NPEID_L, \
- IX_ETHNPE_QM_Q_FIELD_NPEID_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_TXENETDONE_ADDR_MASK
- *
- * @brief Macro to mask the Mbuf Address field of the TxEnetDone Queue Manager
- * Entry
- */
-#define IX_ETHNPE_QM_Q_TXENETDONE_ADDR_MASK \
- MASK (IX_ETHNPE_QM_Q_FIELD_ADDR_L, \
- IX_ETHNPE_QM_Q_FIELD_ADDR_R)
-
-/*--------------------------------------------------------------------------
- * Queue Manager Queue entry bit field value extraction macros
- *------------------------------------------------------------------------*/
-
-/**
- * @def IX_ETHNPE_QM_Q_FREEENET_ADDR_VAL(x)
- *
- * @brief Extraction macro for Address field of FreeNet Queue Manager Entry
- *
- * Pointer to an mbuf buffer descriptor
- */
-#define IX_ETHNPE_QM_Q_FREEENET_ADDR_VAL(x) \
- ((x) & IX_ETHNPE_QM_Q_FREEENET_ADDR_MASK)
-
-/**
- * @def IX_ETHNPE_QM_Q_RXENET_NPEID_VAL(x)
- *
- * @brief Extraction macro for NPE ID field of RxEnet Queue Manager Entry
- *
- * Set to 0 for entries originating from the Eth0 NPE;
- * Set to 1 for entries originating from the Eth1 NPE.
- */
-#define IX_ETHNPE_QM_Q_RXENET_NPEID_VAL(x) \
- BITS (x, IX_ETHNPE_QM_Q_FIELD_NPEID_L, \
- IX_ETHNPE_QM_Q_FIELD_NPEID_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_RXENET_PORTID_VAL(x)
- *
- * @brief Extraction macro for Port ID field of RxEnet Queue Manager Entry
- *
- * 0-5: Assignable (by the XScale client) to any of the physical ports.
- * 6: It is reserved
- * 7: Indication that the NPE did not find the associated frame's destination MAC address within
- * its internal filtering database.
- */
-#define IX_ETHNPE_QM_Q_RXENET_PORTID_VAL(x) \
- BITS (x, IX_ETHNPE_QM_Q_FIELD_PORTID_L, \
- IX_ETHNPE_QM_Q_Field_PortID_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_RXENET_ADDR_VAL(x)
- *
- * @brief Extraction macro for Address field of RxEnet Queue Manager Entry
- *
- * Pointer to an mbuf buffer descriptor
- */
-#define IX_ETHNPE_QM_Q_RXENET_ADDR_VAL(x) \
- ((x) & IX_ETHNPE_QM_Q_RXENET_ADDR_MASK)
-
-/**
- * @def IX_ETHNPE_QM_Q_TXENET_PRIOR_VAL(x)
- *
- * @brief Extraction macro for Priority field of TxEnet Queue Manager Entry
- *
- * Priority of the packet (as described in IEEE 802.1D). This field is
- * cleared upon return from the Ethernet NPE to the TxEnetDone queue.
- */
-#define IX_ETHNPE_QM_Q_TXENET_PRIOR_VAL(x) \
- BITS (x, IX_ETHNPE_QM_Q_FIELD_PRIOR_L, \
- IX_ETHNPE_QM_Q_FIELD_PRIOR_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_TXENET_ADDR_VAL(x)
- *
- * @brief Extraction macro for Address field of Queue Manager TxEnet Queue
- * Manager Entry
- *
- * Pointer to an mbuf buffer descriptor
- */
-#define IX_ETHNPE_QM_Q_TXENET_ADDR_VAL(x) \
- ((x) & IX_ETHNPE_QM_Q_TXENET_ADDR_MASK)
-
-/**
- * @def IX_ETHNPE_QM_Q_TXENETDONE_NPEID_VAL(x)
- *
- * @brief Extraction macro for NPE ID field of TxEnetDone Queue Manager Entry
- *
- * Set to 0 for entries originating from the Eth0 NPE; set to 1 for en-tries
- * originating from the Eth1 NPE.
- */
-#define IX_ETHNPE_QM_Q_TXENETDONE_NPEID_VAL(x) \
- BITS (x, IX_ETHNPE_QM_Q_FIELD_NPEID_L, \
- IX_ETHNPE_QM_Q_FIELD_NPEID_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_TXENETDONE_ADDR_VAL(x)
- *
- * @brief Extraction macro for Address field of TxEnetDone Queue Manager Entry
- *
- * Pointer to an mbuf buffer descriptor
- */
-#define IX_ETHNPE_QM_Q_TXENETDONE_ADDR_VAL(x) \
- ((x) & IX_ETHNPE_QM_Q_TXENETDONE_ADDR_MASK)
-
-
-/*--------------------------------------------------------------------------
- * NPE limits
- *------------------------------------------------------------------------*/
-
-/**
- * @def IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN
- *
- * @brief Macro to check the minimum length of a rx free buffer
- */
-#define IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN (64)
-
-/**
- * @def IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MASK
- *
- * @brief Mask to apply to the mbuf length before submitting it to the NPE
- * (the NPE handles only rx free mbufs which are multiple of 64)
- *
- * @sa IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MASK
- */
-#define IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MASK (~63)
-
-/**
- * @def IX_ETHNPE_ACC_RXFREE_BUFFER_ROUND_UP(size)
- *
- * @brief Round up to get the size necessary to receive without chaining
- * the frames which are (size) bytes (the NPE operates by multiple of 64)
- * e.g. To receive 1514 bytes frames, the size of the buffers in replenish
- * has to be at least (1514+63)&(~63) = 1536 bytes.
- *
- */
-#define IX_ETHNPE_ACC_RXFREE_BUFFER_ROUND_UP(size) (((size) + 63) & ~63)
-
-/**
- * @def IX_ETHNPE_ACC_RXFREE_BUFFER_ROUND_DOWN(size)
- *
- * @brief Round down to apply to the mbuf length before submitting
- * it to the NPE. (the NPE operates by multiple of 64)
- *
- */
-#define IX_ETHNPE_ACC_RXFREE_BUFFER_ROUND_DOWN(size) ((size) & ~63)
-
-/**
- * @def IX_ETHNPE_ACC_FRAME_LENGTH_MAX
- *
- * @brief maximum mbuf length supported by the NPE
- *
- * @sa IX_ETHNPE_ACC_FRAME_LENGTH_MAX
- */
-#define IX_ETHNPE_ACC_FRAME_LENGTH_MAX (16320)
-
-/**
- * @def IX_ETHNPE_ACC_FRAME_LENGTH_DEFAULT
- *
- * @brief default mbuf length supported by the NPE
- *
- * @sa IX_ETHNPE_ACC_FRAME_LENGTH_DEFAULT
- */
-#define IX_ETHNPE_ACC_FRAME_LENGTH_DEFAULT (1522)
-
-/**
- * @def IX_ETHNPE_ACC_LENGTH_OFFSET
- *
- * @brief Offset of the cluster length field in the word shared with the NPEs
- */
-#define IX_ETHNPE_ACC_LENGTH_OFFSET 16
-
-/**
- * @def IX_ETHNPE_ACC_PKTLENGTH_MASK
- *
- * @brief Mask of the cluster length field in the word shared with the NPEs
- */
-#define IX_ETHNPE_ACC_PKTLENGTH_MASK 0x3fff
-
-
-/**
- *@}
- */
-
-#endif /* __doxygen_HIDE */
+++ /dev/null
-/**
- * @file IxFeatureCtrl.h
- *
- * @date 30-Jan-2003
-
- * @brief This file contains the public API of the IXP400 Feature Control
- * component.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-/* ------------------------------------------------------
- Doxygen group definitions
- ------------------------------------------------------ */
-/**
- * @defgroup IxFeatureCtrlAPI IXP400 Feature Control (IxFeatureCtrl) API
- *
- * @brief The Public API for the IXP400 Feature Control.
- *
- * @{
- */
-
-#ifndef IXFEATURECTRL_H
-#define IXFEATURECTRL_H
-
-/*
- * User defined include files
- */
-#include "IxOsal.h"
-
-/*
- * #defines and macros
- */
-
-/*************************************************************
- * The following are IxFeatureCtrlComponentCheck return values.
- ************************************************************/
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURE_CTRL_COMPONENT_DISABLED
- *
- * @brief Hardware Component is disabled/unavailable.
- * Return status by ixFeatureCtrlComponentCheck()
- */
-#define IX_FEATURE_CTRL_COMPONENT_DISABLED 0
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURE_CTRL_COMPONENT_ENABLED
- *
- * @brief Hardware Component is available.
- * Return status by ixFeatureCtrlComponentCheck()
- */
-#define IX_FEATURE_CTRL_COMPONENT_ENABLED 1
-
-/***********************************************************************************
- * Product ID in XScale CP15 - Register 0
- * - It contains information on the maximum XScale Core Frequency and
- * Silicon Stepping.
- * - XScale Core Frequency Id indicates only the maximum XScale frequency
- * achievable and not the running XScale frequency (maybe stepped down).
- * - The register is read by using ixFeatureCtrlProductIdRead.
- * - Usage example:
- * productId = ixFeatureCtrlProductIdRead();
- * if( (productId & IX_FEATURE_CTRL_SILICON_STEPPING_MASK) ==
- * IX_FEATURE_CTRL_SILICON_TYPE_A0 )
- * if( (productId & IX_FEATURE_CTRL_XSCALE_FREQ_MASK) ==
- * IX_FEATURE_CTRL_XSCALE_FREQ_533 )
- *
- * 31 28 27 24 23 20 19 16 15 12 11 9 8 4 3 0
- * --------------------------------------------------------------------------------
- * | 0x6 | 0x9 | 0x0 | 0x5 | 0x4 | Device ID | XScale Core Freq Id | Si Stepping Id |
- * --------------------------------------------------------------------------------
- *
- * Maximum Achievable XScale Core Frequency Id : 533MHz - 0x1C
- * 400MHz - 0x1D
- * 266MHz - 0x1F
- *
- * <b>THE CORE FREQUENCY ID IS NOT APPLICABLE TO IXP46X <\b>
- *
- * The above is applicable to IXP42X only. CP15 in IXP46X does not contain any
- * Frequency ID.
- *
- * Si Stepping Id : A - 0x0
- * B - 0x1
- *
- * XScale Core freq Id - Device ID [11:9] : IXP42X - 0x0
- * IXP46X - 0x1
- *************************************************************************************/
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURE_CTRL_SILICON_TYPE_A0
- *
- * @brief This is the value of A0 Silicon in product ID.
- */
-#define IX_FEATURE_CTRL_SILICON_TYPE_A0 0
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURE_CTRL_SILICON_TYPE_B0
- *
- * @brief This is the value of B0 Silicon in product ID.
- */
-#define IX_FEATURE_CTRL_SILICON_TYPE_B0 1
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURE_CTRL_SILICON_STEPPING_MASK
- *
- * @brief This is the mask of silicon stepping in product ID.
- */
-#define IX_FEATURE_CTRL_SILICON_STEPPING_MASK 0xF
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURE_CTRL_DEVICE_TYPE_MASK
- *
- * @brief This is the mask of silicon stepping in product ID.
- */
-#define IX_FEATURE_CTRL_DEVICE_TYPE_MASK (0x7)
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURE_CTRL_DEVICE_TYPE_OFFSET
- *
- * @brief This is the mask of silicon stepping in product ID.
- */
-#define IX_FEATURE_CTRL_DEVICE_TYPE_OFFSET 9
-
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURE_CTRL_XSCALE_FREQ_533
- *
- * @brief This is the value of 533MHz XScale Core in product ID.
- */
-#define IX_FEATURE_CTRL_XSCALE_FREQ_533 ((0x1C)<<4)
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURE_CTRL_XSCALE_FREQ_400
- *
- * @brief This is the value of 400MHz XScale Core in product ID.
- */
-#define IX_FEATURE_CTRL_XSCALE_FREQ_400 ((0x1D)<<4)
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURE_CTRL_XSCALE_FREQ_266
- *
- * @brief This is the value of 266MHz XScale Core in product ID.
- */
-#define IX_FEATURE_CTRL_XSCALE_FREQ_266 ((0x1F)<<4)
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURE_CTRL_XSCALE_FREQ_MASK
- *
- * @brief This is the mask of XScale Core in product ID.
- */
-#define IX_FEATURE_CTRL_XSCALE_FREQ_MASK ((0xFF)<<4)
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURECTRL_REG_UTOPIA_32PHY
- *
- * @brief Maximum UTOPIA PHY available is 32.
- *
- */
-#define IX_FEATURECTRL_REG_UTOPIA_32PHY 0x0
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURECTRL_REG_UTOPIA_16PHY
- *
- * @brief Maximum UTOPIA PHY available is 16.
- *
- */
-#define IX_FEATURECTRL_REG_UTOPIA_16PHY 0x1
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURECTRL_REG_UTOPIA_8PHY
- *
- * @brief Maximum UTOPIA PHY available to is 8.
- *
- */
-#define IX_FEATURECTRL_REG_UTOPIA_8PHY 0x2
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURECTRL_REG_UTOPIA_4PHY
- *
- * @brief Maximum UTOPIA PHY available to is 4.
- *
- */
-#define IX_FEATURECTRL_REG_UTOPIA_4PHY 0x3
-
-#ifdef __ixp46X
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURECTRL_REG_XSCALE_533FREQ
- *
- * @brief Maximum frequency available to IXP46x is 533 MHz.
- *
- */
-#define IX_FEATURECTRL_REG_XSCALE_533FREQ 0x0
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURECTRL_REG_XSCALE_667FREQ
- *
- * @brief Maximum frequency available to IXP46x is 667 MHz.
- *
- */
-#define IX_FEATURECTRL_REG_XSCALE_667FREQ 0x1
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURECTRL_REG_XSCALE_400FREQ
- *
- * @brief Maximum frequency available to IXP46x is 400 MHz.
- *
- */
-#define IX_FEATURECTRL_REG_XSCALE_400FREQ 0x2
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURECTRL_REG_XSCALE_266FREQ
- *
- * @brief Maximum frequency available to IXP46x is 266 MHz.
- *
- */
-#define IX_FEATURECTRL_REG_XSCALE_266FREQ 0x3
-
-#endif /* __ixp46X */
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE
- *
- * @brief Component selected is not available for device
- *
- */
-#define IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE 0x0000
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURECTRL_COMPONENT_ALWAYS_AVAILABLE
- *
- * @brief Component selected is not available for device
- *
- */
-#define IX_FEATURECTRL_COMPONENT_ALWAYS_AVAILABLE 0xffff
-
-/**
- * @defgroup IxFeatureCtrlSwConfig Software Configuration for Access Component
- *
- * @ingroup IxFeatureCtrlAPI
- *
- * @brief This section describes software configuration in access component. The
- * configuration can be changed at run-time. ixFeatureCtrlSwConfigurationCheck( )
- * will be used across applicable access component to check the configuration.
- * ixFeatureCtrlSwConfigurationWrite( ) is used to write the software configuration.
- *
- * @note <b>All software configurations are default to be enabled.</b>
- *
- * @{
- */
-/**
- * @ingroup IxFeatureCtrlSwConfig
- *
- * @def IX_FEATURE_CTRL_SWCONFIG_DISABLED
- *
- * @brief Software configuration is disabled.
- *
- */
-#define IX_FEATURE_CTRL_SWCONFIG_DISABLED 0
-
-/**
- * @ingroup IxFeatureCtrlSwConfig
- *
- * @def IX_FEATURE_CTRL_SWCONFIG_ENABLED
- *
- * @brief Software configuration is enabled.
- *
- */
-#define IX_FEATURE_CTRL_SWCONFIG_ENABLED 1
-
-/**
- * Section for enums
- **/
-
-/**
- * @ingroup IxFeatureCtrlBuildDevice
- *
- * @enum IxFeatureCtrlBuildDevice
- *
- * @brief Indicates software build type.
- *
- * Default build type is IXP42X
- *
- */
-typedef enum
-{
- IX_FEATURE_CTRL_SW_BUILD_IXP42X = 0, /**<Build type is IXP42X */
- IX_FEATURE_CTRL_SW_BUILD_IXP46X /**<Build type is IXP46X */
-} IxFeatureCtrlBuildDevice;
-
-/**
- * @ingroup IxFeatureCtrlSwConfig
- *
- * @enum IxFeatureCtrlSwConfig
- *
- * @brief Enumeration for software configuration in access components.
- *
- * Entry for new run-time software configuration should be added here.
- */
-typedef enum
-{
- IX_FEATURECTRL_ETH_LEARNING = 0, /**< EthDB Learning Feature */
- IX_FEATURECTRL_ORIGB0_DISPATCHER, /**< IXP42X B0 and IXP46X dispatcher without
- livelock prevention functionality Feature */
- IX_FEATURECTRL_SWCONFIG_MAX /**< Maximum boudary for IxFeatureCtrlSwConfig */
-} IxFeatureCtrlSwConfig;
-
-
-/************************************************************************
- * IXP400 Feature Control Register
- * - It contains the information (available/unavailable) of IXP425&IXP46X
- * hardware components in their corresponding bit location.
- * - Bit value of 0 means the hardware component is available
- * or not software disabled. Hardware component that is available
- * can be software disabled.
- * - Bit value of 1 means the hardware is unavailable or software
- * disabled.Hardware component that is unavailable cannot be software
- * enabled.
- * - Use ixFeatureCtrlHwCapabilityRead() to read the hardware component's
- * availability.
- * - Use ixFeatureCtrlRead() to get the current IXP425/IXP46X feature control
- * register value.
- *
- * Bit Field Description (Hardware Component Availability)
- * --- ---------------------------------------------------
- * 0 RComp Circuitry
- * 1 USB Controller
- * 2 Hashing Coprocessor
- * 3 AES Coprocessor
- * 4 DES Coprocessor
- * 5 HDLC Coprocessor
- * 6 AAL Coprocessor - Always available in IXP46X
- * 7 HSS Coprocesspr
- * 8 Utopia Coprocessor
- * 9 Ethernet 0 Coprocessor
- * 10 Ethernet 1 Coprocessor
- * 11 NPE A
- * 12 NPE B
- * 13 NPE C
- * 14 PCI Controller
- * 15 ECC/TimeSync Coprocessor - Only applicable to IXP46X
- * 16-17 Utopia PHY Limit Status : 0x0 - 32 PHY
- * 0x1 - 16 PHY
- * 0x2 - 8 PHY
- * 0x3 - 4 PHY
- *
- * Portions below are only applicable to IXP46X
- * 18 USB Host Coprocessor
- * 19 NPE A Ethernet - 0 for Enable if Utopia = 1
- * 20 NPE B Ethernet coprocessor 1-3.
- * 21 RSA Crypto Block coprocessor.
- * 22-23 Processor frequency : 0x0 - 533 MHz
- * 0x1 - 667 MHz
- * 0x2 - 400 MHz
- * 0x3 - 266 MHz
- * 24-31 Reserved
- *
- ************************************************************************/
-/*Section generic to both IXP42X and IXP46X*/
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @enum IxFeatureCtrlComponentType
- *
- * @brief Enumeration for components availavble
- *
- */
-typedef enum
-{
- IX_FEATURECTRL_RCOMP = 0, /**<bit location for RComp Circuitry*/
- IX_FEATURECTRL_USB, /**<bit location for USB Controller*/
- IX_FEATURECTRL_HASH, /**<bit location for Hashing Coprocessor*/
- IX_FEATURECTRL_AES, /**<bit location for AES Coprocessor*/
- IX_FEATURECTRL_DES, /**<bit location for DES Coprocessor*/
- IX_FEATURECTRL_HDLC, /**<bit location for HDLC Coprocessor*/
- IX_FEATURECTRL_AAL, /**<bit location for AAL Coprocessor*/
- IX_FEATURECTRL_HSS, /**<bit location for HSS Coprocessor*/
- IX_FEATURECTRL_UTOPIA, /**<bit location for UTOPIA Coprocessor*/
- IX_FEATURECTRL_ETH0, /**<bit location for Ethernet 0 Coprocessor*/
- IX_FEATURECTRL_ETH1, /**<bit location for Ethernet 1 Coprocessor*/
- IX_FEATURECTRL_NPEA, /**<bit location for NPE A*/
- IX_FEATURECTRL_NPEB, /**<bit location for NPE B*/
- IX_FEATURECTRL_NPEC, /**<bit location for NPE C*/
- IX_FEATURECTRL_PCI, /**<bit location for PCI Controller*/
- IX_FEATURECTRL_ECC_TIMESYNC, /**<bit location for TimeSync Coprocessor*/
- IX_FEATURECTRL_UTOPIA_PHY_LIMIT, /**<bit location for Utopia PHY Limit Status*/
- IX_FEATURECTRL_UTOPIA_PHY_LIMIT_BIT2, /**<2nd bit of PHY limit status*/
- IX_FEATURECTRL_USB_HOST_CONTROLLER, /**<bit location for USB host controller*/
- IX_FEATURECTRL_NPEA_ETH, /**<bit location for NPE-A Ethernet Disable*/
- IX_FEATURECTRL_NPEB_ETH, /**<bit location for NPE-B Ethernet 1-3 Coprocessors Disable*/
- IX_FEATURECTRL_RSA, /**<bit location for RSA Crypto block Coprocessors Disable*/
- IX_FEATURECTRL_XSCALE_MAX_FREQ, /**<bit location for XScale max frequency*/
- IX_FEATURECTRL_XSCALE_MAX_FREQ_BIT2, /**<2nd xscale max freq bit NOT TO BE USED */
- IX_FEATURECTRL_MAX_COMPONENTS
-} IxFeatureCtrlComponentType;
-
-/**
- * @ingroup IxFeatureCtrlDeviceId
- *
- * @enum IxFeatureCtrlDeviceId
- *
- * @brief Enumeration for device type.
- *
- * @warning This enum is closely related to the npe image. Its format should comply
- * with formats used in the npe image ImageID. This is indicated by the
- * first nibble of the image ID. This should also be in sync with the
- * with what is defined in CP15. Current available formats are
- * - IXP42X - 0000
- * - IXP46X - 0001
- *
- */
-typedef enum
-{
- IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X = 0, /**<Device type is IXP42X */
- IX_FEATURE_CTRL_DEVICE_TYPE_IXP46X, /**<Device type is IXP46X */
- IX_FEATURE_CTRL_DEVICE_TYPE_MAX /**<Max devices */
-} IxFeatureCtrlDeviceId;
-
-
-/**
- * @} addtogroup IxFeatureCtrlSwConfig
- */
-
-/*
- * Typedefs
- */
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @typedef IxFeatureCtrlReg
- *
- * @brief Feature Control Register that contains hardware components'
- * availability information.
- */
-typedef UINT32 IxFeatureCtrlReg;
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @typedef IxFeatureCtrlProductId
- *
- * @brief Product ID of Silicon that contains Silicon Stepping and
- * Maximum XScale Core Frequency information.
- */
-typedef UINT32 IxFeatureCtrlProductId;
-
-/*
- * Prototypes for interface functions
- */
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @fn IxFeatureCtrlReg ixFeatureCtrlRead (void)
- *
- * @brief This function reads out the CURRENT value of Feature Control Register.
- * The current value may not be the same as that of the hardware component
- * availability.
- *
- * The bit location of each hardware component is defined above.
- * A value of '1' in bit means the hardware component is not available. A value of '0'
- * means the hardware component is available.
- *
- * @return
- * - IxFeatureCtrlReg - the current value of IXP400 Feature Control Register
- */
-PUBLIC IxFeatureCtrlReg
-ixFeatureCtrlRead (void);
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @fn IxFeatureDeviceId ixFeatureCtrlDeviceRead (void)
- *
- * @brief This function gets the type of device that the software is currently running
- * on
- *
- * This function reads the feature Ctrl register specifically to obtain the device id.
- * The definitions of the avilable IDs are as above.
- *
- * @return
- * - IxFeatureCtrlDeviceId - the type of device currently running
- */
-IxFeatureCtrlDeviceId
-ixFeatureCtrlDeviceRead (void);
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @fn IxFeatureCtrlBuildDevice ixFeatureCtrlSoftwareBuildGet (void)
- *
- * @brief This function refers to the value set by the compiler flag to determine
- * the type of device the software is built for.
- *
- * The function reads the compiler flag to determine the device the software is
- * built for. When the user executes build in the command line,
- * a compile time flag (__ixp42X/__ixp46X is set. This API reads this
- * flag and returns the software build type to the calling client.
- *
- * @return
- * - IxFeatureCtrlBuildDevice - the type of device software is built for.
- */
-IxFeatureCtrlBuildDevice
-ixFeatureCtrlSoftwareBuildGet (void);
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @fn IxFeatureCtrlReg ixFeatureCtrlHwCapabilityRead (void)
- *
- * @brief This function reads out the hardware capability of a silicon type as defined in
- * feature control register.This value is different from that returned by
- * ixFeatureCtrlRead() because this function returns the actual hardware component
- * availability.
- *
- * The bit location of each hardware component is defined above.
- * A value of '1' in bit means the hardware component is not available. A value of '0'
- * means the hardware component is available.
- *
- * @return
- * - IxFeatureCtrlReg - the hardware capability of IXP400.
- *
- * @warning
- * - This function must not be called when IXP400 is running as the result
- * is undefined.
- */
-PUBLIC IxFeatureCtrlReg
-ixFeatureCtrlHwCapabilityRead (void);
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @fn void ixFeatureCtrlWrite (IxFeatureCtrlReg expUnitReg)
- *
- * @brief This function write the value stored in IxFeatureCtrlReg expUnitReg
- * to the Feature Control Register.
- *
- * The bit location of each hardware component is defined above.
- * The write is only effective on available hardware components. Writing '1' in a
- * bit will software disable the respective hardware component. A '0' will mean that
- * the hardware component will remain to be operable.
- *
- * @param expUnitReg @ref IxFeatureCtrlReg [in] - The value to be written to feature control
- * register.
- *
- * @return none
- *
- */
-PUBLIC void
-ixFeatureCtrlWrite (IxFeatureCtrlReg expUnitReg);
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @fn IX_STATUS ixFeatureCtrlComponentCheck (IxFeatureCtrlComponentType componentType)
- *
- * @brief This function will check the availability of hardware component specified
- * as componentType value.
- *
- * Usage Example:<br>
- * - if(IX_FEATURE_CTRL_COMPONENT_DISABLED !=
- * ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0)) <br>
- * - if(IX_FEATURE_CTRL_COMPONENT_ENABLED ==
- * ixFeatureCtrlComponentCheck(IX_FEATURECTRL_PCI)) <br>
- *
- * This function is typically called during component initialization time.
- *
- * @param componentType @ref IxFeatureCtrlComponentType [in] - the type of a component as
- * defined above as IX_FEATURECTRL_XXX (Exp: IX_FEATURECTRL_PCI, IX_FEATURECTRL_ETH0)
-
- *
- * @return
- * - IX_FEATURE_CTRL_COMPONENT_ENABLED if component is available
- * - IX_FEATURE_CTRL_COMPONENT_DISABLED if component is unavailable
- */
-PUBLIC IX_STATUS
-ixFeatureCtrlComponentCheck (IxFeatureCtrlComponentType componentType);
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @fn IxFeatureCtrlProductId ixFeatureCtrlProductIdRead (void)
- *
- * @brief This function will return IXP400 product ID i.e. CP15,
- * Register 0.
- *
- * @return
- * - IxFeatureCtrlProductId - the value of product ID.
- *
- */
-PUBLIC IxFeatureCtrlProductId
-ixFeatureCtrlProductIdRead (void) ;
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @fn IX_STATUS ixFeatureCtrlSwConfigurationCheck (IxFeatureCtrlSwConfig swConfigType)
- *
- * @brief This function checks whether the specified software configuration is
- * enabled or disabled.
- *
- * Usage Example:<br>
- * - if(IX_FEATURE_CTRL_SWCONFIG_DISABLED !=
- * ixFeatureCtrlSwConfigurationCheck(IX_FEATURECTRL_ETH_LEARNING)) <br>
- * - if(IX_FEATURE_CTRL_SWCONFIG_ENABLED ==
- * ixFeatureCtrlSwConfigurationCheck(IX_FEATURECTRL_ETH_LEARNING)) <br>
- *
- * This function is typically called during access component initialization time.
- *
- * @param swConfigType @ref IxFeatureCtrlSwConfig [in] - the type of a software configuration
- * defined in IxFeatureCtrlSwConfig enumeration.
- *
- * @return
- * - IX_FEATURE_CTRL_SWCONFIG_ENABLED if software configuration is enabled.
- * - IX_FEATURE_CTRL_SWCONFIG_DISABLED if software configuration is disabled.
- */
-PUBLIC IX_STATUS
-ixFeatureCtrlSwConfigurationCheck (IxFeatureCtrlSwConfig swConfigType);
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @fn void ixFeatureCtrlSwConfigurationWrite (IxFeatureCtrlSwConfig swConfigType, BOOL enabled)
- *
- * @brief This function enable/disable the specified software configuration.
- *
- * Usage Example:<br>
- * - ixFeatureCtrlSwConfigurationWrite(IX_FEATURECTRL_ETH_LEARNING, true) is used
- * to enable Ethernet Learning Feature <br>
- * - ixFeatureCtrlSwConfigurationWrite(IX_FEATURECTRL_ETH_LEARNING, false) is used
- * to disable Ethernet Learning Feature <br>
- *
- * @param swConfigType IxFeatureCtrlSwConfig [in] - the type of a software configuration
- * defined in IxFeatureCtrlSwConfig enumeration.
- * @param enabled BOOL [in] - To enable(true) / disable (false) the specified software
- * configuration.
- *
- * @return none
- *
- */
-PUBLIC void
-ixFeatureCtrlSwConfigurationWrite (IxFeatureCtrlSwConfig swConfigType, BOOL enabled);
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @fn void ixFeatureCtrlIxp400SwVersionShow (void)
- *
- * @brief This function shows the current software release information for IXP400
- *
- * @return none
- *
- */
-PUBLIC void
-ixFeatureCtrlIxp400SwVersionShow (void);
-
-#endif /* IXFEATURECTRL_H */
-
-/**
- * @} defgroup IxFeatureCtrlAPI
- */
+++ /dev/null
-/**
- * @file IxHssAcc.h
- *
- * @date 07-DEC-2001
- *
- * @brief This file contains the public API of the IXP400 HSS Access
- * component
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/* ------------------------------------------------------
- Doxygen group definitions
- ------------------------------------------------------ */
-/**
- * @defgroup IxHssAccAPI IXP400 HSS Access (IxHssAcc) API
- *
- * @brief The public API for the IXP400 HssAccess component
- *
- * IxHssAcc is the access layer to the HSS packetised and channelised
- * services
- *
- * <b> Design Notes </b><br>
- * <UL>
- * <LI>When a packet-pipe is configured for 56Kbps RAW mode, byte alignment of
- * the transmitted data is not preserved. All raw data that is transmitted
- * will be received in proper order by the receiver, but the first bit of
- * the packet may be seen at any offset within a byte; all subsequent bytes
- * will have the same offset for the duration of the packet. The same offset
- * also applies to all subsequent packets received on the packet-pipe too.
- * (Similar results will occur for data received from remote end.) While
- * this behavior will also occur for 56Kbps HDLC mode, the HDLC
- * encoding/decoding will preserve the original byte alignment at the
- * receiver end.
- * </UL>
- *
- * <b> 56Kbps Packetised Service Bandwidth Limitation </b><br>
- * <UL>
- * <LI>IxHssAcc supports 56Kbps packetised service at a maximum aggregate rate
- * for all HSS ports/HDLC channels of 12.288Mbps[1] in each direction, i.e.
- * it supports 56Kbps packetised service on up to 8 T1 trunks. It does
- * not support 56Kbps packetised service on 8 E1 trunks (i.e. 4 trunks per
- * HSS port) unless those trunks are running 'fractional E1' with maximum
- * aggregate rate of 12.288 Mbps in each direction.<br>
- * [1] 12.288Mbps = 1.536Mbp * 8 T1
- * </UL>
- * @{ */
-
-#ifndef IXHSSACC_H
-#define IXHSSACC_H
-
-#include "IxOsal.h"
-
-/*
- * #defines for function return types, etc.
- */
-
-/**
- * @def IX_HSSACC_TSLOTS_PER_HSS_PORT
- *
- * @brief The max number of TDM timeslots supported per HSS port - 4E1's =
- * 32x4 = 128
- */
-#define IX_HSSACC_TSLOTS_PER_HSS_PORT 128
-
-/* -----------------------------------------------------------
- The following are HssAccess return values returned through
- service interfaces. The globally defined IX_SUCCESS (0) and
- IX_FAIL (1) in IxOsalTypes.h are also used.
- ----------------------------------------------------------- */
-/**
- * @def IX_HSSACC_PARAM_ERR
- *
- * @brief HssAccess function return value for a parameter error
- */
-#define IX_HSSACC_PARAM_ERR 2
-
-/**
- * @def IX_HSSACC_RESOURCE_ERR
- *
- * @brief HssAccess function return value for a resource error
- */
-#define IX_HSSACC_RESOURCE_ERR 3
-
-/**
- * @def IX_HSSACC_PKT_DISCONNECTING
- *
- * @brief Indicates that a disconnect call is progressing and will
- * disconnect soon
- */
-#define IX_HSSACC_PKT_DISCONNECTING 4
-
-/**
- * @def IX_HSSACC_Q_WRITE_OVERFLOW
- *
- * @brief Indicates that an attempt to Tx or to replenish an
- * RxFree Q failed due to Q overflow.
- */
-#define IX_HSSACC_Q_WRITE_OVERFLOW 5
-
-/* -------------------------------------------------------------------
- The following errors are HSS/NPE errors returned on error retrieval
- ------------------------------------------------------------------- */
-/**
- * @def IX_HSSACC_NO_ERROR
- *
- * @brief HSS port no error present
- */
-#define IX_HSSACC_NO_ERROR 0
-
-/**
- * @def IX_HSSACC_TX_FRM_SYNC_ERR
- *
- * @brief HSS port TX Frame Sync error
- */
-#define IX_HSSACC_TX_FRM_SYNC_ERR 1
-
-/**
- * @def IX_HSSACC_TX_OVER_RUN_ERR
- *
- * @brief HSS port TX over-run error
- */
-#define IX_HSSACC_TX_OVER_RUN_ERR 2
-
-/**
- * @def IX_HSSACC_CHANNELISED_SW_TX_ERR
- *
- * @brief NPE software error in channelised TX
- */
-#define IX_HSSACC_CHANNELISED_SW_TX_ERR 3
-
-/**
- * @def IX_HSSACC_PACKETISED_SW_TX_ERR
- *
- * @brief NPE software error in packetised TX
- */
-#define IX_HSSACC_PACKETISED_SW_TX_ERR 4
-
-/**
- * @def IX_HSSACC_RX_FRM_SYNC_ERR
- *
- * @brief HSS port RX Frame Sync error
- */
-#define IX_HSSACC_RX_FRM_SYNC_ERR 5
-
-/**
- * @def IX_HSSACC_RX_OVER_RUN_ERR
- *
- * @brief HSS port RX over-run error
- */
-#define IX_HSSACC_RX_OVER_RUN_ERR 6
-
-/**
- * @def IX_HSSACC_CHANNELISED_SW_RX_ERR
- *
- * @brief NPE software error in channelised RX
- */
-#define IX_HSSACC_CHANNELISED_SW_RX_ERR 7
-
-/**
- * @def IX_HSSACC_PACKETISED_SW_RX_ERR
- *
- * @brief NPE software error in packetised TX
- */
-#define IX_HSSACC_PACKETISED_SW_RX_ERR 8
-
-/* -----------------------------------
- Packetised service specific defines
- ----------------------------------- */
-
-/**
- * @def IX_HSSACC_PKT_MIN_RX_MBUF_SIZE
- *
- * @brief Minimum size of the Rx mbuf in bytes which the client must supply
- * to the component.
- */
-#define IX_HSSACC_PKT_MIN_RX_MBUF_SIZE 64
-
-/* --------------------------------------------------------------------
- Enumerated Types - these enumerated values may be used in setting up
- the contents of hardware registers
- -------------------------------------------------------------------- */
-/**
- * @enum IxHssAccHssPort
- * @brief The HSS port ID - There are two identical ports (0-1).
- *
- */
-typedef enum
-{
- IX_HSSACC_HSS_PORT_0, /**< HSS Port 0 */
- IX_HSSACC_HSS_PORT_1, /**< HSS Port 1 */
- IX_HSSACC_HSS_PORT_MAX /**< Delimiter for error checks */
-} IxHssAccHssPort;
-
-/**
- * @enum IxHssAccHdlcPort
- * @brief The HDLC port ID - There are four identical HDLC ports (0-3) per
- * HSS port and they correspond to the 4 E1/T1 trunks.
- *
- */
-typedef enum
-{
- IX_HSSACC_HDLC_PORT_0, /**< HDLC Port 0 */
- IX_HSSACC_HDLC_PORT_1, /**< HDLC Port 1 */
- IX_HSSACC_HDLC_PORT_2, /**< HDLC Port 2 */
- IX_HSSACC_HDLC_PORT_3, /**< HDLC Port 3 */
- IX_HSSACC_HDLC_PORT_MAX /**< Delimiter for error checks */
-} IxHssAccHdlcPort;
-
-/**
- * @enum IxHssAccTdmSlotUsage
- * @brief The HSS TDM stream timeslot assignment types
- *
- */
-typedef enum
-{
- IX_HSSACC_TDMMAP_UNASSIGNED, /**< Unassigned */
- IX_HSSACC_TDMMAP_HDLC, /**< HDLC - packetised */
- IX_HSSACC_TDMMAP_VOICE56K, /**< Voice56K - channelised */
- IX_HSSACC_TDMMAP_VOICE64K, /**< Voice64K - channelised */
- IX_HSSACC_TDMMAP_MAX /**< Delimiter for error checks */
-} IxHssAccTdmSlotUsage;
-
-/**
- * @enum IxHssAccFrmSyncType
- * @brief The HSS frame sync pulse type
- *
- */
-typedef enum
-{
- IX_HSSACC_FRM_SYNC_ACTIVE_LOW, /**< Frame sync is sampled low */
- IX_HSSACC_FRM_SYNC_ACTIVE_HIGH, /**< sampled high */
- IX_HSSACC_FRM_SYNC_FALLINGEDGE, /**< sampled on a falling edge */
- IX_HSSACC_FRM_SYNC_RISINGEDGE, /**< sampled on a rising edge */
- IX_HSSACC_FRM_SYNC_TYPE_MAX /**< Delimiter for error checks */
-} IxHssAccFrmSyncType;
-
-/**
- * @enum IxHssAccFrmSyncEnable
- * @brief The IxHssAccFrmSyncEnable determines how the frame sync pulse is
- * used
- * */
-typedef enum
-{
- IX_HSSACC_FRM_SYNC_INPUT, /**< Frame sync is sampled as an input */
- IX_HSSACC_FRM_SYNC_INVALID_VALUE, /**< 1 is not used */
- IX_HSSACC_FRM_SYNC_OUTPUT_FALLING, /**< Frame sync is an output generated
- off a falling clock edge */
- IX_HSSACC_FRM_SYNC_OUTPUT_RISING, /**< Frame sync is an output generated
- off a rising clock edge */
- IX_HSSACC_FRM_SYNC_ENABLE_MAX /**< Delimiter for error checks */
-} IxHssAccFrmSyncEnable;
-
-/**
- * @enum IxHssAccClkEdge
- * @brief IxHssAccClkEdge is used to determine the clk edge to use for
- * framing and data
- *
- */
-typedef enum
-{
- IX_HSSACC_CLK_EDGE_FALLING, /**< Clock sampled off a falling edge */
- IX_HSSACC_CLK_EDGE_RISING, /**< Clock sampled off a rising edge */
- IX_HSSACC_CLK_EDGE_MAX /**< Delimiter for error checks */
-} IxHssAccClkEdge;
-
-/**
- * @enum IxHssAccClkDir
- * @brief The HSS clock direction
- *
- */
-typedef enum
-{
- IX_HSSACC_SYNC_CLK_DIR_INPUT, /**< Clock is an input */
- IX_HSSACC_SYNC_CLK_DIR_OUTPUT, /**< Clock is an output */
- IX_HSSACC_SYNC_CLK_DIR_MAX /**< Delimiter for error checks */
-} IxHssAccClkDir;
-
-/**
- * @enum IxHssAccFrmPulseUsage
- * @brief The HSS frame pulse usage
- *
- */
-typedef enum
-{
- IX_HSSACC_FRM_PULSE_ENABLED, /**< Generate/Receive frame pulses */
- IX_HSSACC_FRM_PULSE_DISABLED, /**< Disregard frame pulses */
- IX_HSSACC_FRM_PULSE_MAX /**< Delimiter for error checks */
-} IxHssAccFrmPulseUsage;
-
-/**
- * @enum IxHssAccDataRate
- * @brief The HSS Data rate in relation to the clock
- *
- */
-typedef enum
-{
- IX_HSSACC_CLK_RATE, /**< Data rate is at the configured clk speed */
- IX_HSSACC_HALF_CLK_RATE, /**< Data rate is half the configured clk speed */
- IX_HSSACC_DATA_RATE_MAX /**< Delimiter for error checks */
-} IxHssAccDataRate;
-
-/**
- * @enum IxHssAccDataPolarity
- * @brief The HSS data polarity type
- *
- */
-typedef enum
-{
- IX_HSSACC_DATA_POLARITY_SAME, /**< Don't invert data between NPE and
- HSS FIFOs */
- IX_HSSACC_DATA_POLARITY_INVERT, /**< Invert data between NPE and HSS
- FIFOs */
- IX_HSSACC_DATA_POLARITY_MAX /**< Delimiter for error checks */
-} IxHssAccDataPolarity;
-
-/**
- * @enum IxHssAccBitEndian
- * @brief HSS Data endianness
- *
- */
-typedef enum
-{
- IX_HSSACC_LSB_ENDIAN, /**< TX/RX Least Significant Bit first */
- IX_HSSACC_MSB_ENDIAN, /**< TX/RX Most Significant Bit first */
- IX_HSSACC_ENDIAN_MAX /**< Delimiter for the purposes of error checks */
-} IxHssAccBitEndian;
-
-
-/**
- * @enum IxHssAccDrainMode
- * @brief Tx pin open drain mode
- *
- */
-typedef enum
-{
- IX_HSSACC_TX_PINS_NORMAL, /**< Normal mode */
- IX_HSSACC_TX_PINS_OPEN_DRAIN, /**< Open Drain mode */
- IX_HSSACC_TX_PINS_MAX /**< Delimiter for error checks */
-} IxHssAccDrainMode;
-
-/**
- * @enum IxHssAccSOFType
- * @brief HSS start of frame types
- *
- */
-typedef enum
-{
- IX_HSSACC_SOF_FBIT, /**< Framing bit transmitted and expected on rx */
- IX_HSSACC_SOF_DATA, /**< Framing bit not transmitted nor expected on rx */
- IX_HSSACC_SOF_MAX /**< Delimiter for error checks */
-} IxHssAccSOFType;
-
-/**
- * @enum IxHssAccDataEnable
- * @brief IxHssAccDataEnable is used to determine whether or not to drive
- * the data pins
- *
- */
-typedef enum
-{
- IX_HSSACC_DE_TRI_STATE, /**< TRI-State the data pins */
- IX_HSSACC_DE_DATA, /**< Push data out the data pins */
- IX_HSSACC_DE_MAX /**< Delimiter for error checks */
-} IxHssAccDataEnable;
-
-/**
- * @enum IxHssAccTxSigType
- * @brief IxHssAccTxSigType is used to determine how to drive the data pins
- *
- */
-typedef enum
-{
- IX_HSSACC_TXSIG_LOW, /**< Drive the data pins low */
- IX_HSSACC_TXSIG_HIGH, /**< Drive the data pins high */
- IX_HSSACC_TXSIG_HIGH_IMP, /**< Drive the data pins with high impedance */
- IX_HSSACC_TXSIG_MAX /**< Delimiter for error checks */
-} IxHssAccTxSigType;
-
-/**
- * @enum IxHssAccFbType
- * @brief IxHssAccFbType determines how to drive the Fbit
- *
- * @warning This will only be used for T1 @ 1.544MHz
- *
- */
-typedef enum
-{
- IX_HSSACC_FB_FIFO, /**< Fbit is dictated in FIFO */
- IX_HSSACC_FB_HIGH_IMP, /**< Fbit is high impedance */
- IX_HSSACC_FB_MAX /**< Delimiter for error checks */
-} IxHssAccFbType;
-
-/**
- * @enum IxHssAcc56kEndianness
- * @brief 56k data endianness when using the 56k type
- *
- */
-typedef enum
-{
- IX_HSSACC_56KE_BIT_7_UNUSED, /**< High bit is unused */
- IX_HSSACC_56KE_BIT_0_UNUSED, /**< Low bit is unused */
- IX_HSSACC_56KE_MAX /**< Delimiter for error checks */
-} IxHssAcc56kEndianness;
-
-/**
- * @enum IxHssAcc56kSel
- * @brief 56k data transmission type when using the 56k type
- *
- */
-typedef enum
-{
- IX_HSSACC_56KS_32_8_DATA, /**< 32/8 bit data */
- IX_HSSACC_56KS_56K_DATA, /**< 56K data */
- IX_HSSACC_56KS_MAX /**< Delimiter for error checks */
-} IxHssAcc56kSel;
-
-
-/**
- * @enum IxHssAccClkSpeed
- * @brief IxHssAccClkSpeed represents the HSS clock speeds available
- *
- */
-typedef enum
-{
- IX_HSSACC_CLK_SPEED_512KHZ, /**< 512KHz */
- IX_HSSACC_CLK_SPEED_1536KHZ, /**< 1.536MHz */
- IX_HSSACC_CLK_SPEED_1544KHZ, /**< 1.544MHz */
- IX_HSSACC_CLK_SPEED_2048KHZ, /**< 2.048MHz */
- IX_HSSACC_CLK_SPEED_4096KHZ, /**< 4.096MHz */
- IX_HSSACC_CLK_SPEED_8192KHZ, /**< 8.192MHz */
- IX_HSSACC_CLK_SPEED_MAX /**< Delimiter for error checking */
-} IxHssAccClkSpeed;
-
-/**
- * @enum IxHssAccPktStatus
- * @brief Indicates the status of packets passed to the client
- *
- */
-typedef enum
-{
- IX_HSSACC_PKT_OK, /**< Error free.*/
- IX_HSSACC_STOP_SHUTDOWN_ERROR, /**< Errored due to stop or shutdown
- occurrance.*/
- IX_HSSACC_HDLC_ALN_ERROR, /**< HDLC alignment error */
- IX_HSSACC_HDLC_FCS_ERROR, /**< HDLC Frame Check Sum error.*/
- IX_HSSACC_RXFREE_Q_EMPTY_ERROR, /**< RxFree Q became empty
- while receiving this packet.*/
- IX_HSSACC_HDLC_MAX_FRAME_SIZE_EXCEEDED, /**< HDLC frame size
- received is greater than
- max specified at connect.*/
- IX_HSSACC_HDLC_ABORT_ERROR, /**< HDLC frame received is invalid due to an
- abort sequence received.*/
- IX_HSSACC_DISCONNECT_IN_PROGRESS /**< Packet returned
- because a disconnect is in progress */
-} IxHssAccPktStatus;
-
-
-/**
- * @enum IxHssAccPktCrcType
- * @brief HDLC CRC type
- *
- */
-typedef enum
-{
- IX_HSSACC_PKT_16_BIT_CRC = 16, /**< 16 bit CRC is being used */
- IX_HSSACC_PKT_32_BIT_CRC = 32 /**< 32 bit CRC is being used */
-} IxHssAccPktCrcType;
-
-/**
- * @enum IxHssAccPktHdlcIdleType
- * @brief HDLC idle transmission type
- *
- */
-typedef enum
-{
- IX_HSSACC_HDLC_IDLE_ONES, /**< idle tx/rx will be a succession of ones */
- IX_HSSACC_HDLC_IDLE_FLAGS /**< idle tx/rx will be repeated flags */
-} IxHssAccPktHdlcIdleType;
-
-/**
- * @brief Structure containing HSS port configuration parameters
- *
- * Note: All of these are used for TX. Only some are specific to RX.
- *
- */
-typedef struct
-{
- IxHssAccFrmSyncType frmSyncType; /**< frame sync pulse type (tx/rx) */
- IxHssAccFrmSyncEnable frmSyncIO; /**< how the frame sync pulse is
- used (tx/rx) */
- IxHssAccClkEdge frmSyncClkEdge; /**< frame sync clock edge type
- (tx/rx) */
- IxHssAccClkEdge dataClkEdge; /**< data clock edge type (tx/rx) */
- IxHssAccClkDir clkDirection; /**< clock direction (tx/rx) */
- IxHssAccFrmPulseUsage frmPulseUsage; /**< whether to use the frame sync
- pulse or not (tx/rx) */
- IxHssAccDataRate dataRate; /**< data rate in relation to the
- clock (tx/rx) */
- IxHssAccDataPolarity dataPolarity; /**< data polarity type (tx/rx) */
- IxHssAccBitEndian dataEndianness; /**< data endianness (tx/rx) */
- IxHssAccDrainMode drainMode; /**< tx pin open drain mode (tx) */
- IxHssAccSOFType fBitUsage; /**< start of frame types (tx/rx) */
- IxHssAccDataEnable dataEnable; /**< whether or not to drive the data
- pins (tx) */
- IxHssAccTxSigType voice56kType; /**< how to drive the data pins for
- voice56k type (tx) */
- IxHssAccTxSigType unassignedType; /**< how to drive the data pins for
- unassigned type (tx) */
- IxHssAccFbType fBitType; /**< how to drive the Fbit (tx) */
- IxHssAcc56kEndianness voice56kEndian;/**< 56k data endianness when using
- the 56k type (tx) */
- IxHssAcc56kSel voice56kSel; /**< 56k data transmission type when
- using the 56k type (tx) */
- unsigned frmOffset; /**< frame pulse offset in bits wrt
- the first timeslot (0-1023) (tx/rx) */
- unsigned maxFrmSize; /**< frame size in bits (1-1024)
- (tx/rx) */
-} IxHssAccPortConfig;
-
-/**
- * @brief Structure containing HSS configuration parameters
- *
- */
-typedef struct
-{
- IxHssAccPortConfig txPortConfig; /**< HSS tx port configuration */
- IxHssAccPortConfig rxPortConfig; /**< HSS rx port configuration */
- unsigned numChannelised; /**< The number of channelised
- timeslots (0-32) */
- unsigned hssPktChannelCount; /**< The number of packetised
- clients (0 - 4) */
- UINT8 channelisedIdlePattern; /**< The byte to be transmitted on
- channelised service when there
- is no client data to tx */
- BOOL loopback; /**< The HSS loopback state */
- unsigned packetizedIdlePattern; /**< The data to be transmitted on
- packetised service when there is
- no client data to tx */
- IxHssAccClkSpeed clkSpeed; /**< The HSS clock speed */
-} IxHssAccConfigParams;
-
-/**
- * @brief This structure contains 56Kbps, HDLC-mode configuration parameters
- *
- */
-typedef struct
-{
- BOOL hdlc56kMode; /**< 56kbps(true)/64kbps(false) HDLC */
- IxHssAcc56kEndianness hdlc56kEndian; /**< 56kbps data endianness
- - ignored if hdlc56kMode is false*/
- BOOL hdlc56kUnusedBitPolarity0; /**< The polarity '0'(true)/'1'(false) of the unused
- bit while in 56kbps mode
- - ignored if hdlc56kMode is false*/
-} IxHssAccHdlcMode;
-
-/**
- * @brief This structure contains information required by the NPE to
- * configure the HDLC co-processor
- *
- */
-typedef struct
-{
- IxHssAccPktHdlcIdleType hdlcIdleType; /**< What to transmit when a HDLC port is idle */
- IxHssAccBitEndian dataEndian; /**< The HDLC data endianness */
- IxHssAccPktCrcType crcType; /**< The CRC type to be used for this HDLC port */
-} IxHssAccPktHdlcFraming;
-
-/**
- * @typedef UINT32 IxHssAccPktUserId
- *
- * @brief The client supplied value which will be supplied as a parameter
- * with a given callback.
- *
- * This value will be passed into the ixHssAccPktPortConnect function once each
- * with given callbacks. This value will then be passed back to the client
- * as one of the parameters to each of these callbacks,
- * when these callbacks are called.
- */
-typedef UINT32 IxHssAccPktUserId;
-
-
-/**
- * @typedef IxHssAccLastErrorCallback
- * @brief Prototype of the clients function to accept notification of the
- * last error
- *
- * This function is registered through the config. The client will initiate
- * the last error retrieval. The HssAccess component will send a message to
- * the NPE through the NPE Message Handler. When a response to the read is
- * received, the NPE Message Handler will callback the HssAccess component
- * which will execute this function in the same IxNpeMh context. The client
- * will be passed the last error and the related service port (packetised
- * 0-3, channelised 0)
- *
- * @param lastHssError unsigned [in] - The last Hss error registered that
- * has been registered.
- * @param servicePort unsigned [in] - This is the service port number.
- * (packetised 0-3, channelised 0)
- *
- * @return void
- */
-typedef void (*IxHssAccLastErrorCallback) (unsigned lastHssError,
- unsigned servicePort);
-
-/**
- * @typedef IxHssAccPktRxCallback
- * @brief Prototype of the clients function to accept notification of
- * packetised rx
- *
- * This function is registered through the ixHssAccPktPortConnect. hssPktAcc will pass
- * received data in the form of mbufs to the client. The mbuf passed back
- * to the client could contain a chain of buffers, depending on the packet
- * size received.
- *
- * @param *buffer @ref IX_OSAL_MBUF [in] - This is the mbuf which contains the
- * payload received.
- * @param numHssErrs unsigned [in] - This is the number of hssErrors
- * the Npe has received
- * @param pktStatus @ref IxHssAccPktStatus [in] - This is the status of the
- * mbuf that has been received.
- * @param rxUserId @ref IxHssAccPktUserId [in] - This is the client supplied value
- * passed in at ixHssAccPktPortConnect time which is now returned to the client.
- *
- * @return void
- */
-typedef void (*IxHssAccPktRxCallback) (IX_OSAL_MBUF *buffer,
- unsigned numHssErrs,
- IxHssAccPktStatus pktStatus,
- IxHssAccPktUserId rxUserId);
-
-/**
- * @typedef IxHssAccPktRxFreeLowCallback
- * @brief Prototype of the clients function to accept notification of
- * requirement of more Rx Free buffers
- *
- * The client can choose to register a callback of this type when
- * calling a connecting. This function is registered through the ixHssAccPktPortConnect.
- * If defined, the access layer will provide the trigger for
- * this callback. The callback will be responsible for supplying mbufs to
- * the access layer for use on the receive path from the HSS using
- * ixHssPktAccFreeBufReplenish.
- *
- * @return void
- */
-typedef void (*IxHssAccPktRxFreeLowCallback) (IxHssAccPktUserId rxFreeLowUserId);
-
-/**
- * @typedef IxHssAccPktTxDoneCallback
- * @brief Prototype of the clients function to accept notification of
- * completion with Tx buffers
- *
- * This function is registered through the ixHssAccPktPortConnect. It enables
- * the hssPktAcc to pass buffers back to the client
- * when transmission is complete.
- *
- * @param *buffer @ref IX_OSAL_MBUF [in] - This is the mbuf which contained
- * the payload that was for Tx.
- * @param numHssErrs unsigned [in] - This is the number of hssErrors
- * the Npe has received
- * @param pktStatus @ref IxHssAccPktStatus [in] - This is the status of the
- * mbuf that has been transmitted.
- * @param txDoneUserId @ref IxHssAccPktUserId [in] - This is the client supplied value
- * passed in at ixHssAccPktPortConnect time which is now returned to the client.
- *
- * @return void
- */
-typedef void (*IxHssAccPktTxDoneCallback) (IX_OSAL_MBUF *buffer,
- unsigned numHssErrs,
- IxHssAccPktStatus pktStatus,
- IxHssAccPktUserId txDoneUserId);
-
-/**
- * @typedef IxHssAccChanRxCallback
- * @brief Prototype of the clients function to accept notification of
- * channelised rx
- *
- * This callback, if defined by the client in the connect, will get called
- * in the context of an IRQ. The IRQ will be triggered when the hssSyncQMQ
- * is not empty. The queued entry will be dequeued and this function will
- * be executed.
- *
- * @param hssPortId @ref IxHssAccHssPort - The HSS port Id. There are two
- * identical ports (0-1).
- * @param txOffset unsigned [in] - an offset indicating from where within
- * the txPtrList the NPE is currently transmitting from.
- * @param rxOffset unsigned [in] - an offset indicating where within the
- * receive buffers the NPE has just written the received data to.
- * @param numHssErrs unsigned [in] - This is the number of hssErrors
- * the Npe has received
- *
- * @return void
- */
-typedef void (*IxHssAccChanRxCallback) (IxHssAccHssPort hssPortId,
- unsigned rxOffset,
- unsigned txOffset,
- unsigned numHssErrs);
-
-/*
- * Prototypes for interface functions.
- */
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccPortInit (IxHssAccHssPort hssPortId,
- IxHssAccConfigParams *configParams,
- IxHssAccTdmSlotUsage *tdmMap,
- IxHssAccLastErrorCallback lastHssErrorCallback)
- *
- * @brief Initialise a HSS port. No channelised or packetised connections
- * should exist in the HssAccess layer while this interface is being called.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1).
- * @param *configParams @ref IxHssAccConfigParams [in] - A pointer to the HSS
- * configuration structure
- * @param *tdmMap @ref IxHssAccTdmSlotUsage [in] - A pointer to an array of size
- * IX_HSSACC_TSLOTS_PER_HSS_PORT, defining the slot usage over the HSS port
- * @param lastHssErrorCallback @ref IxHssAccLastErrorCallback [in] - Client
- * callback to report last error
- *
- * @return
- * - IX_SUCCESS The function executed successfully
- * - IX_FAIL The function did not execute successfully
- * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- * parameter error
- */
-PUBLIC IX_STATUS
-ixHssAccPortInit (IxHssAccHssPort hssPortId,
- IxHssAccConfigParams *configParams,
- IxHssAccTdmSlotUsage *tdmMap,
- IxHssAccLastErrorCallback lastHssErrorCallback);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccLastErrorRetrievalInitiate (
- IxHssAccHssPort hssPortId)
- *
- * @brief Initiate the retrieval of the last HSS error. The HSS port
- * should be configured before attempting to call this interface.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - the HSS port ID
- *
- * @return
- * - IX_SUCCESS The function executed successfully
- * - IX_FAIL The function did not execute successfully
- * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- * parameter error
- */
-PUBLIC IX_STATUS
-ixHssAccLastErrorRetrievalInitiate (IxHssAccHssPort hssPortId);
-
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccInit ()
- *
- * @brief This function is responsible for initialising resources for use
- * by the packetised and channelised clients. It should be called after
- * HSS NPE image has been downloaded into NPE-A and before any other
- * HssAccess interface is called.
- * No other HssAccPacketised interface should be called while this interface
- * is being processed.
- *
- * @return
- * - IX_SUCCESS The function executed successfully
- * - IX_FAIL The function did not execute successfully
- * - IX_HSSACC_RESOURCE_ERR The function did not execute successfully due
- * to a resource error
- */
-PUBLIC IX_STATUS
-ixHssAccInit (void);
-
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn ixHssAccPktPortConnect (IxHssAccHssPort hssPortId,
- IxHssAccHdlcPort hdlcPortId,
- BOOL hdlcFraming,
- IxHssAccHdlcMode hdlcMode,
- BOOL hdlcBitInvert,
- unsigned blockSizeInWords,
- UINT32 rawIdleBlockPattern,
- IxHssAccPktHdlcFraming hdlcTxFraming,
- IxHssAccPktHdlcFraming hdlcRxFraming,
- unsigned frmFlagStart,
- IxHssAccPktRxCallback rxCallback,
- IxHssAccPktUserId rxUserId,
- IxHssAccPktRxFreeLowCallback rxFreeLowCallback,
- IxHssAccPktUserId rxFreeLowUserId,
- IxHssAccPktTxDoneCallback txDoneCallback,
- IxHssAccPktUserId txDoneUserId)
- *
- * @brief This function is responsible for connecting a client to one of
- * the 4 available HDLC ports. The HSS port should be configured before
- * attempting a connect. No other HssAccPacketised interface should be
- * called while this connect is being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1).
- * @param hdlcPortId @ref IxHssAccHdlcPort [in] - This is the number of the HDLC port and
- * it corresponds to the physical E1/T1 trunk i.e. 0, 1, 2, 3
- * @param hdlcFraming BOOL [in] - This value determines whether the service
- * will use HDLC data or the debug, raw data type i.e. no HDLC processing
- * @param hdlcMode @ref IxHssAccHdlcMode [in] - This structure contains 56Kbps, HDLC-mode
- * configuration parameters
- * @param hdlcBitInvert BOOL [in] - This value determines whether bit inversion
- * will occur between HDLC and HSS co-processors i.e. post-HDLC processing for
- * transmit and pre-HDLC processing for receive, for the specified HDLC Termination
- * Point
- * @param blockSizeInWords unsigned [in] - The max tx/rx block size
- * @param rawIdleBlockPattern UINT32 [in] - Tx idle pattern in raw mode
- * @param hdlcTxFraming @ref IxHssAccPktHdlcFraming [in] - This structure contains
- * the following information required by the NPE to configure the HDLC
- * co-processor for TX
- * @param hdlcRxFraming @ref IxHssAccPktHdlcFraming [in] - This structure contains
- * the following information required by the NPE to configure the HDLC
- * co-processor for RX
- * @param frmFlagStart unsigned - Number of flags to precede to
- * transmitted flags (0-2).
- * @param rxCallback @ref IxHssAccPktRxCallback [in] - Pointer to
- * the clients packet receive function.
- * @param rxUserId @ref IxHssAccPktUserId [in] - The client supplied rx value
- * to be passed back as an argument to the supplied rxCallback
- * @param rxFreeLowCallback @ref IxHssAccPktRxFreeLowCallback [in] - Pointer to
- * the clients Rx free buffer request function. If NULL, assume client will
- * trigger independently.
- * @param rxFreeLowUserId @ref IxHssAccPktUserId [in] - The client supplied RxFreeLow value
- * to be passed back as an argument to the supplied rxFreeLowCallback
- * @param txDoneCallback @ref IxHssAccPktTxDoneCallback [in] - Pointer to the
- * clients Tx done callback function
- * @param txDoneUserId @ref IxHssAccPktUserId [in] - The client supplied txDone value
- * to be passed back as an argument to the supplied txDoneCallback
- *
- * @return
- * - IX_SUCCESS The function executed successfully
- * - IX_FAIL The function did not execute successfully
- * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- * parameter error
- * - IX_HSSACC_RESOURCE_ERR The function did not execute successfully due
- * to a resource error
- */
-PUBLIC IX_STATUS
-ixHssAccPktPortConnect (IxHssAccHssPort hssPortId,
- IxHssAccHdlcPort hdlcPortId,
- BOOL hdlcFraming,
- IxHssAccHdlcMode hdlcMode,
- BOOL hdlcBitInvert,
- unsigned blockSizeInWords,
- UINT32 rawIdleBlockPattern,
- IxHssAccPktHdlcFraming hdlcTxFraming,
- IxHssAccPktHdlcFraming hdlcRxFraming,
- unsigned frmFlagStart,
- IxHssAccPktRxCallback rxCallback,
- IxHssAccPktUserId rxUserId,
- IxHssAccPktRxFreeLowCallback rxFreeLowCallback,
- IxHssAccPktUserId rxFreeLowUserId,
- IxHssAccPktTxDoneCallback txDoneCallback,
- IxHssAccPktUserId txDoneUserId);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccPktPortEnable (IxHssAccHssPort hssPortId,
- IxHssAccHdlcPort hdlcPortId)
- *
- * @brief This function is responsible for enabling a packetised service
- * for the specified HSS/HDLC port combination. It enables the RX flow. The
- * client must have already connected to a packetised service and is responsible
- * for ensuring an adequate amount of RX mbufs have been supplied to the access
- * component before enabling the packetised service. This function must be called
- * on a given port before any call to ixHssAccPktPortTx on the same port.
- * No other HssAccPacketised interface should be called while this interface is
- * being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1).
- * @param hdlcPortId @ref IxHssAccHdlcPort [in] - The port id (0,1,2,3) to enable the service
- * on.
- *
- * @return
- * - IX_SUCCESS The function executed successfully
- * - IX_FAIL The function did not execute successfully
- * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- * parameter error
- */
-PUBLIC IX_STATUS
-ixHssAccPktPortEnable (IxHssAccHssPort hssPortId,
- IxHssAccHdlcPort hdlcPortId);
-
-/**
- * @fn IX_STATUS ixHssAccPktPortDisable (IxHssAccHssPort hssPortId,
- IxHssAccHdlcPort hdlcPortId)
- *
- * @brief This function is responsible for disabling a packetised service
- * for the specified HSS/HDLC port combination. It disables the RX flow.
- * The client must have already connected to and enabled a packetised service
- * for the specified HDLC port. This disable interface can be called before a
- * disconnect, but is not required to.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1).
- * @param hdlcPortId @ref IxHssAccHdlcPort [in] - The port id (0,1,2,3) to disable
- * the service on.
- *
- * @return
- * - IX_SUCCESS The function executed successfully
- * - IX_FAIL The function did not execute successfully
- * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- * parameter error
- */
-PUBLIC IX_STATUS
-ixHssAccPktPortDisable (IxHssAccHssPort hssPortId,
- IxHssAccHdlcPort hdlcPortId);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccPktPortDisconnect (IxHssAccHssPort hssPortId,
- IxHssAccHdlcPort hdlcPortId)
- *
- * @brief This function is responsible for disconnecting a client from one
- * of the 4 available HDLC ports. It is not required that the Rx Flow
- * has been disabled before calling this function. If the RX Flow has not been
- * disabled, the disconnect will disable it before proceeding with the
- * disconnect. No other HssAccPacketised
- * interface should be called while this interface is being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1).
- * @param hdlcPortId @ref IxHssAccHdlcPort [in] - This is the number of the HDLC port
- * to disconnect and it corresponds to the physical E1/T1 trunk i.e. 0, 1, 2, 3
- *
- * @return
- * - IX_SUCCESS The function executed successfully
- * - IX_FAIL The function did not execute successfully
- * - IX_HSSACC_PKT_DISCONNECTING The function has initiated the disconnecting
- * procedure but it has not completed yet.
- */
-PUBLIC IX_STATUS
-ixHssAccPktPortDisconnect (IxHssAccHssPort hssPortId,
- IxHssAccHdlcPort hdlcPortId);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn BOOL ixHssAccPktPortIsDisconnectComplete (IxHssAccHssPort hssPortId,
- IxHssAccHdlcPort hdlcPortId)
- *
- * @brief This function is called to check if a given HSS/HDLC port
- * combination is in a connected state or not. This function may be called
- * at any time to determine a ports state. No other HssAccPacketised
- * interface should be called while this interface is being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1).
- * @param hdlcPortId @ref IxHssAccHdlcPort [in] - This is the number of the HDLC port
- * to disconnect and it corresponds to the physical E1/T1 trunk i.e. 0, 1, 2, 3
- *
- * @return
- * - true The state of this HSS/HDLC port combination is disconnected,
- * so if a disconnect was called, it is now completed.
- * - false The state of this HSS/HDLC port combination is connected,
- * so if a disconnect was called, it is not yet completed.
- */
-PUBLIC BOOL
-ixHssAccPktPortIsDisconnectComplete (IxHssAccHssPort hssPortId,
- IxHssAccHdlcPort hdlcPortId);
-
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccPktPortRxFreeReplenish (IxHssAccHssPort hssPortId,
- IxHssAccHdlcPort hdlcPortId,
- IX_OSAL_MBUF *buffer)
- *
- * @brief Function which the client calls at regular intervals to provide
- * mbufs to the access component for RX. A connection should exist for
- * the specified hssPortId/hdlcPortId combination before attempting to call this
- * interface. Also, the connection should not be in a disconnecting state.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1).
- * @param hdlcPortId @ref IxHssAccHdlcPort [in] - This is the number of the HDLC port
- * and it corresponds to the physical E1/T1 trunk i.e. 0, 1, 2, 3
- * @param *buffer @ref IX_OSAL_MBUF [in] - A pointer to a free mbuf to filled with payload.
- *
- * @return
- * - IX_SUCCESS The function executed successfully
- * - IX_FAIL The function did not execute successfully
- * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- * parameter error
- * - IX_HSSACC_RESOURCE_ERR The function did not execute successfully due
- * to a resource error
- * - IX_HSSACC_Q_WRITE_OVERFLOW The function did not succeed due to a Q
- * overflow
- */
-PUBLIC IX_STATUS
-ixHssAccPktPortRxFreeReplenish (IxHssAccHssPort hssPortId,
- IxHssAccHdlcPort hdlcPortId,
- IX_OSAL_MBUF *buffer);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccPktPortTx (IxHssAccHssPort hssPortId,
- IxHssAccHdlcPort hdlcPortId,
- IX_OSAL_MBUF *buffer)
- *
- * @brief Function which the client calls when it wants to transmit
- * packetised data. An enabled connection should exist on the specified
- * hssPortId/hdlcPortId combination before attempting to call this interface.
- * No other HssAccPacketised
- * interface should be called while this interface is being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1).
- * @param hdlcPortId @ref IxHssAccHdlcPort [in] - This is the number of the HDLC port
- * and it corresponds to the physical E1/T1 trunk i.e. 0, 1, 2, 3
- * @param *buffer @ref IX_OSAL_MBUF [in] - A pointer to a chain of mbufs which the
- * client has filled with the payload
- *
- * @return
- * - IX_SUCCESS The function executed successfully
- * - IX_FAIL The function did not execute successfully
- * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- * parameter error
- * - IX_HSSACC_RESOURCE_ERR The function did not execute successfully due
- * to a resource error. See note.
- * - IX_HSSACC_Q_WRITE_OVERFLOW The function did not succeed due to a Q
- * overflow
- *
- * @note IX_HSSACC_RESOURCE_ERR is returned when a free descriptor cannot be
- * obtained to send the chain of mbufs to the NPE. This is a normal scenario.
- * HssAcc has a pool of descriptors and this error means that they are currently
- * all in use.
- * The recommended approach to this is to retry until a descriptor becomes free
- * and the packet is successfully transmitted.
- * Alternatively, the user could wait until the next IxHssAccPktTxDoneCallback
- * callback is triggered, and then retry, as it is this event that causes a
- * transmit descriptor to be freed.
- */
-PUBLIC IX_STATUS
-ixHssAccPktPortTx (IxHssAccHssPort hssPortId,
- IxHssAccHdlcPort hdlcPortId,
- IX_OSAL_MBUF *buffer);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccChanConnect (IxHssAccHssPort hssPortId,
- unsigned bytesPerTSTrigger,
- UINT8 *rxCircular,
- unsigned numRxBytesPerTS,
- UINT32 *txPtrList,
- unsigned numTxPtrLists,
- unsigned numTxBytesPerBlk,
- IxHssAccChanRxCallback rxCallback)
- *
- * @brief This function allows the client to connect to the Tx/Rx NPE
- * Channelised Service. There can only be one client per HSS port. The
- * client is responsible for ensuring that the HSS port is configured
- * appropriately before its connect request. No other HssAccChannelised
- * interface should be called while this interface is being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1).
- * @param bytesPerTSTrigger unsigned [in] - The NPE will trigger the access
- * component after bytesPerTSTrigger have been received for all trunk
- * timeslots. This figure is a multiple of 8 e.g. 8 for 1ms trigger, 16 for
- * 2ms trigger.
- * @param *rxCircular UINT8 [in] - A pointer to memory allocated by the
- * client to be filled by data received. The buffer at this address is part
- * of a pool of buffers to be accessed in a circular fashion. This address
- * will be written to by the NPE. Therefore, it needs to be a physical address.
- * @param numRxBytesPerTS unsigned [in] - The number of bytes allocated per
- * timeslot within the receive memory. This figure will depend on the
- * latency of the system. It needs to be deep enough for data to be read by
- * the client before the NPE re-writes over that memory e.g. if the client
- * samples at a rate of 40bytes per timeslot, numRxBytesPerTS may need to
- * be 40bytes * 3. This would give the client 3 * 5ms of time before
- * received data is over-written.
- * @param *txPtrList UINT32 [in] - The address of an area of contiguous
- * memory allocated by the client to be populated with pointers to data for
- * transmission. Each pointer list contains a pointer per active channel.
- * The txPtrs will point to data to be transmitted by the NPE. Therefore,
- * they must point to physical addresses.
- * @param numTxPtrLists unsigned [in] - The number of pointer lists in
- * txPtrList. This figure is dependent on jitter.
- * @param numTxBytesPerBlk unsigned [in] - The size of the Tx data, in
- * bytes, that each pointer within the PtrList points to.
- * @param rxCallback @ref IxHssAccChanRxCallback [in] - A client function
- * pointer to be called back to handle the actual tx/rx of channelised
- * data. If this is not NULL, an ISR will call this function. If this
- * pointer is NULL, it implies that the client will use a polling mechanism
- * to detect when the tx and rx of channelised data is to occur. The client
- * will use hssChanAccStatus for this.
- *
- * @return
- * - IX_SUCCESS The function executed successfully
- * - IX_FAIL The function did not execute successfully
- * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- * parameter error
- */
-
-PUBLIC IX_STATUS
-ixHssAccChanConnect (IxHssAccHssPort hssPortId,
- unsigned bytesPerTSTrigger,
- UINT8 *rxCircular,
- unsigned numRxBytesPerTS,
- UINT32 *txPtrList,
- unsigned numTxPtrLists,
- unsigned numTxBytesPerBlk,
- IxHssAccChanRxCallback rxCallback);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccChanPortEnable (IxHssAccHssPort hssPortId)
- *
- * @brief This function is responsible for enabling a channelised service
- * for the specified HSS port. It enables the NPE RX flow. The client must
- * have already connected to a channelised service before enabling the
- * channelised service. No other HssAccChannelised
- * interface should be called while this interface is being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1).
- *
- * @return
- * - IX_SUCCESS The function executed successfully
- * - IX_FAIL The function did not execute successfully
- * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- * parameter error
- */
-PUBLIC IX_STATUS
-ixHssAccChanPortEnable (IxHssAccHssPort hssPortId);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccChanPortDisable (IxHssAccHssPort hssPortId)
- *
- * @brief This function is responsible for disabling a channelised service
- * for the specified HSS port. It disables the NPE RX flow. The client must
- * have already connected to and enabled a channelised service for the
- * specified HSS port. This disable interface can be called before a
- * disconnect, but is not required to. No other HssAccChannelised
- * interface should be called while this interface is being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1).
- *
- * @return
- * - IX_SUCCESS The function executed successfully
- * - IX_FAIL The function did not execute successfully
- * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- * parameter error
- */
-PUBLIC IX_STATUS
-ixHssAccChanPortDisable (IxHssAccHssPort hssPortId);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccChanDisconnect (IxHssAccHssPort hssPortId)
- *
- * @brief This function allows the client to Disconnect from a channelised
- * service. If the NPE RX Flow has not been disabled, the disconnect will
- * disable it before proceeding with other disconnect functionality.
- * No other HssAccChannelised interface should be called while this
- * interface is being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1).
- *
- * @return
- * - IX_SUCCESS The function executed successfully
- * - IX_FAIL The function did not execute successfully
- * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- * parameter error
- */
-PUBLIC IX_STATUS
-ixHssAccChanDisconnect (IxHssAccHssPort hssPortId);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccChanStatusQuery (IxHssAccHssPort hssPortId,
- BOOL *dataRecvd,
- unsigned *rxOffset,
- unsigned *txOffset,
- unsigned *numHssErrs)
- *
- * @brief This function is called by the client to query whether or not
- * channelised data has been received. If there is, hssChanAcc will return
- * the details in the output parameters. An enabled connection should
- * exist on the specified hssPortId before attempting to call this interface.
- * No other HssAccChannelised interface should be called while this
- * interface is being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1).
- * @param *dataRecvd BOOL [out] - This BOOL indicates to the client whether
- * or not the access component has read any data for the client. If
- * false, the other output parameters will not have been written to.
- * @param *rxOffset unsigned [out] - An offset to indicate to the client
- * where within the receive buffers the NPE has just written the received
- * data to.
- * @param *txOffset unsigned [out] - An offset to indicate to the client
- * from where within the txPtrList the NPE is currently transmitting from
- * @param *numHssErrs unsigned [out] - The total number of HSS port errors
- * since initial port configuration
- *
- *
- * @return
- * - IX_SUCCESS The function executed successfully
- * - IX_FAIL The function did not execute successfully
- * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- * parameter error
- */
-PUBLIC IX_STATUS
-ixHssAccChanStatusQuery (IxHssAccHssPort hssPortId,
- BOOL *dataRecvd,
- unsigned *rxOffset,
- unsigned *txOffset,
- unsigned *numHssErrs);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn void ixHssAccShow (void)
- *
- * @brief This function will display the current state of the IxHssAcc
- * component. The output is sent to stdout.
- *
- * @return void
- */
-PUBLIC void
-ixHssAccShow (void);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn void ixHssAccStatsInit (void)
- *
- * @brief This function will reset the IxHssAcc statistics.
- *
- * @return void
- */
-PUBLIC void
-ixHssAccStatsInit (void);
-
-#endif /* IXHSSACC_H */
-
-/**
- * @} defgroup IxHssAcc
- */
+++ /dev/null
-/**
- * @file IxI2cDrv.h
- *
- * @brief Header file for the IXP400 I2C Driver (IxI2cDrv)
- *
- * @version $Revision: 0.1 $
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxI2cDrv IXP400 I2C Driver(IxI2cDrv) API
- *
- * @brief IXP400 I2C Driver Public API
- *
- * @{
- */
-#ifndef IXI2CDRV_H
-#define IXI2CDRV_H
-
-#ifdef __ixp46X
-#include "IxOsal.h"
-
-/*
- * Section for #define
- */
-
-/**
- * @ingroup IxI2cDrv
- * @brief The interval of micro/mili seconds the IXP will wait before it polls for
- * status from the ixI2cIntrXferStatus; Every 20us is 1 byte @
- * 400Kbps and 4 bytes @ 100Kbps. This is dependent on delay type selected
- * through the API ixI2cDrvDelayTypeSelect.
- */
-#define IX_I2C_US_POLL_FOR_XFER_STATUS 20
-
-/**
- * @ingroup IxI2cDrv
- * @brief The number of tries that will be attempted to call a callback
- * function if the callback does not or is unable to resolve the
- * issue it is called to resolve
- */
-#define IX_I2C_NUM_OF_TRIES_TO_CALL_CALLBACK_FUNC 10
-
-
-/**
- * @ingroup IxI2cDrv
- * @brief Number of tries slave will poll the IDBR Rx full bit before it
- * gives up
- */
-#define IX_I2C_NUM_TO_POLL_IDBR_RX_FULL 0x100
-
-/**
- * @ingroup IxI2cDrv
- * @brief Number of tries slave will poll the IDBR Tx empty bit before it
- * gives up
- */
-#define IX_I2C_NUM_TO_POLL_IDBR_TX_EMPTY 0x100
-
-/*
- * Section for enum
- */
-
-/**
- * @ingroup IxI2cDrv
- *
- * @enum IxI2cMasterStatus
- *
- * @brief The master status - transfer complete, bus error or arbitration loss
- */
-typedef enum
-{
- IX_I2C_MASTER_XFER_COMPLETE = IX_SUCCESS,
- IX_I2C_MASTER_XFER_BUS_ERROR,
- IX_I2C_MASTER_XFER_ARB_LOSS
-} IxI2cMasterStatus;
-
-
-/**
- * @ingroup IxI2cDrv
- *
- * @enum IX_I2C_STATUS
- *
- * @brief The status that can be returned in a I2C driver initialization
- */
-typedef enum
-{
- IX_I2C_SUCCESS = IX_SUCCESS, /**< Success status */
- IX_I2C_FAIL, /**< Fail status */
- IX_I2C_NOT_SUPPORTED, /**< hardware does not have dedicated I2C hardware */
- IX_I2C_NULL_POINTER, /**< parameter passed in is NULL */
- IX_I2C_INVALID_SPEED_MODE_ENUM_VALUE, /**< speed mode selected is invalid */
- IX_I2C_INVALID_FLOW_MODE_ENUM_VALUE, /**< flow mode selected is invalid */
- IX_I2C_SLAVE_ADDR_CB_MISSING, /**< slave callback is NULL */
- IX_I2C_GEN_CALL_CB_MISSING, /**< general callback is NULL */
- IX_I2C_INVALID_SLAVE_ADDR, /**< invalid slave address specified */
- IX_I2C_INT_BIND_FAIL, /**< interrupt bind fail */
- IX_I2C_INT_UNBIND_FAIL, /**< interrupt unbind fail */
- IX_I2C_NOT_INIT, /**< I2C is not initialized yet */
- IX_I2C_MASTER_BUS_BUSY, /**< master detected a I2C bus busy */
- IX_I2C_MASTER_ARB_LOSS, /**< master experienced arbitration loss */
- IX_I2C_MASTER_XFER_ERROR, /**< master experienced a transfer error */
- IX_I2C_MASTER_BUS_ERROR, /**< master detected a I2C bus error */
- IX_I2C_MASTER_NO_BUFFER, /**< no buffer provided for master transfer */
- IX_I2C_MASTER_INVALID_XFER_MODE, /**< xfer mode selected is invalid */
- IX_I2C_SLAVE_ADDR_NOT_DETECTED, /**< polled slave addr not detected */
- IX_I2C_GEN_CALL_ADDR_DETECTED, /**< polling detected general call */
- IX_I2C_SLAVE_READ_DETECTED, /**< polling detected slave read request */
- IX_I2C_SLAVE_WRITE_DETECTED, /**< polling detected slave write request */
- IX_I2C_SLAVE_NO_BUFFER, /**< no buffer provided for slave transfers */
- IX_I2C_DATA_SIZE_ZERO, /**< data size transfer is zero - invalid */
- IX_I2C_SLAVE_WRITE_BUFFER_EMPTY, /**< slave buffer is used till empty */
- IX_I2C_SLAVE_WRITE_ERROR, /**< slave write experienced an error */
- IX_I2C_SLAVE_OR_GEN_READ_BUFFER_FULL, /**< slave buffer is filled up */
- IX_I2C_SLAVE_OR_GEN_READ_ERROR /**< slave read experienced an error */
-} IX_I2C_STATUS;
-
-/**
- * @ingroup IxI2cDrv
- *
- * @enum IxI2cSpeedMode
- *
- * @brief Type of speed modes supported by the I2C hardware.
- */
-typedef enum
-{
- IX_I2C_NORMAL_MODE = 0x0,
- IX_I2C_FAST_MODE
-} IxI2cSpeedMode;
-
-/**
- * @ingroup IxI2cDrv
- *
- * @enum IxI2cXferMode
- *
- * @brief Used for indicating it is a repeated start or normal transfer
- */
-typedef enum
-{
- IX_I2C_NORMAL = 0x0,
- IX_I2C_REPEATED_START
-} IxI2cXferMode;
-
-/**
- * @ingroup IxI2cDrv
- *
- * @enum IxI2cFlowMode
- *
- * @brief Used for indicating it is a poll or interrupt mode
- */
-typedef enum
-{
- IX_I2C_POLL_MODE = 0x0,
- IX_I2C_INTERRUPT_MODE
-} IxI2cFlowMode;
-
-/**
- * @ingroup IxI2cDrv
- *
- * @enum IxI2cDelayMode
- *
- * @brief Used for selecting looping delay or OS scheduler delay
- */
-typedef enum
-{
- IX_I2C_LOOP_DELAY = 1, /**< delay in microseconds */
- IX_I2C_SCHED_DELAY /**< delay in miliseconds */
-} IxI2cDelayMode;
-
-/**
- * @ingroup IxI2cDrv
- *
- * @brief The pointer to the function that will be called when the master
- * has completed its receive. The parameter that is passed will
- * provide the status of the read (success, arb loss, or bus
- * error), the transfer mode (normal or repeated start, the
- * buffer pointer and number of bytes transferred.
- */
-typedef void (*IxI2cMasterReadCallbackP)(IxI2cMasterStatus, IxI2cXferMode, char*, UINT32);
-
-/**
- * @ingroup IxI2cDrv
- *
- * @brief The pointer to the function that will be called when the master
- * has completed its transmit. The parameter that is passed will
- * provide the status of the write (success, arb loss, or buss
- * error), the transfer mode (normal or repeated start), the
- * buffer pointer and number of bytes transferred.
- */
-typedef void (*IxI2cMasterWriteCallbackP)(IxI2cMasterStatus, IxI2cXferMode, char*, UINT32);
-
-/**
- * @ingroup IxI2cDrv
- *
- * @brief The pointer to the function that will be called when a slave
- * address detected in interrupt mode for a read. The parameters
- * that is passed will provide the read status, buffer pointer,
- * buffer size, and the bytes received. When a start of a read
- * is initiated there will be no buffer allocated and this callback
- * will be called to request for a buffer. While receiving, if the
- * buffer gets filled, this callback will be called to request for
- * a new buffer while sending the filled buffer's pointer and size,
- * and data size received. When the receive is complete, this
- * callback will be called to process the data and free the memory
- * by passing the buffer's pointer and size, and data size received.
- */
-typedef void (*IxI2cSlaveReadCallbackP)(IX_I2C_STATUS, char*, UINT32, UINT32);
-
-/**
- * @ingroup IxI2cDrv
- *
- * @brief The pointer to the function that will be called when a slave
- * address detected in interrupt mode for a write. The parameters
- * that is passed will provide the write status, buffer pointer,
- * buffer size, and the bytes received. When a start of a write is
- * initiated there will be no buffer allocated and this callback
- * will be called to request for a buffer and to fill it with data.
- * While transmitting, if the data in the buffer empties, this
- * callback will be called to request for more data to be filled in
- * the same or new buffer. When the transmit is complete, this
- * callback will be called to free the memory or other actions to
- * be taken.
- */
-typedef void (*IxI2cSlaveWriteCallbackP)(IX_I2C_STATUS, char*, UINT32, UINT32);
-
-/**
- * @ingroup IxI2cDrv
- *
- * @brief The pointer to the function that will be called when a general
- * call detected in interrupt mode for a read. The parameters that
- * is passed will provide the read status, buffer pointer, buffer
- * size, and the bytes received. When a start of a read is
- * initiated there will be no buffer allocated and this callback
- * will be called to request for a buffer. While receiving, if the
- * buffer gets filled, this callback will be called to request for
- * a new buffer while sending the filled buffer's pointer and size,
- * and data size received. When the receive is complete, this
- * callback will be called to process the data and free the memory
- * by passing the buffer's pointer and size, and data size received.
- */
-typedef void (*IxI2cGenCallCallbackP)(IX_I2C_STATUS, char*, UINT32, UINT32);
-
-/*
- * Section for struct
- */
-
-/**
- * @brief contains all the variables required to initialize the I2C unit
- *
- * Structure to be filled and used for calling initialization
- */
-typedef struct
-{
- IxI2cSpeedMode I2cSpeedSelect; /**<Select either normal (100kbps)
- or fast mode (400kbps)*/
- IxI2cFlowMode I2cFlowSelect; /**<Select interrupt or poll mode*/
- IxI2cMasterReadCallbackP MasterReadCBP;
- /**<The master read callback pointer */
- IxI2cMasterWriteCallbackP MasterWriteCBP;
- /**<The master write callback pointer */
- IxI2cSlaveReadCallbackP SlaveReadCBP;
- /**<The slave read callback pointer */
- IxI2cSlaveWriteCallbackP SlaveWriteCBP;
- /**<The slave write callback pointer */
- IxI2cGenCallCallbackP GenCallCBP;
- /**<The general call callback pointer */
- BOOL I2cGenCallResponseEnable; /**<Enable/disable the unit to
- respond to generall calls.*/
- BOOL I2cSlaveAddrResponseEnable;/**<Enable/disable the unit to
- respond to the slave address set in
- ISAR*/
- BOOL SCLEnable; /**<Enable/disable the unit from
- driving the SCL line during master
- mode operation*/
- UINT8 I2cHWAddr; /**<The address the unit will
- response to as a slave device*/
-} IxI2cInitVars;
-
-/**
- * @brief contains results of counters and their overflow
- *
- * Structure contains all values of counters and associated overflows.
- */
-typedef struct
-{
- UINT32 ixI2cMasterXmitCounter; /**<Total bytes transmitted as
- master.*/
- UINT32 ixI2cMasterFailedXmitCounter; /**<Total bytes failed for
- transmission as master.*/
- UINT32 ixI2cMasterRcvCounter; /**<Total bytes received as
- master.*/
- UINT32 ixI2cMasterFailedRcvCounter; /**<Total bytes failed for
- receival as master.*/
- UINT32 ixI2cSlaveXmitCounter; /**<Total bytes transmitted as
- slave.*/
- UINT32 ixI2cSlaveFailedXmitCounter; /**<Total bytes failed for
- transmission as slave.*/
- UINT32 ixI2cSlaveRcvCounter; /**<Total bytes received as
- slave.*/
- UINT32 ixI2cSlaveFailedRcvCounter; /**<Total bytes failed for
- receival as slave.*/
- UINT32 ixI2cGenAddrCallSucceedCounter; /**<Total bytes successfully
- transmitted for general address.*/
- UINT32 ixI2cGenAddrCallFailedCounter; /**<Total bytes failed transmission
- for general address.*/
- UINT32 ixI2cArbLossCounter; /**<Total instances of arbitration
- loss has occured.*/
-} IxI2cStatsCounters;
-
-
-/*
- * Section for prototypes interface functions
- */
-
-/**
- * @ingroup IxI2cDrv
- *
- * @fn ixI2cDrvInit(
- IxI2cInitVars *InitVarsSelected)
- *
- * @brief Initializes the I2C Driver.
- *
- * @param "IxI2cInitVars [in] *InitVarsSelected" - struct containing required
- * variables for initialization
- *
- * Global Data :
- * - None.
- *
- * This API will check if the hardware supports this I2C driver and the validity
- * of the parameters passed in. It will continue to process the parameters
- * passed in by setting the speed of the I2C unit (100kbps or 400kbps), setting
- * the flow to either interrupt or poll mode, setting the address of the I2C unit,
- * enabling/disabling the respond to General Calls, enabling/disabling the respond
- * to Slave Address and SCL line driving. If it is interrupt mode, then it will
- * register the callback routines for master, slavetransfer and general call receive.
- *
- * @return
- * - IX_I2C_SUCCESS - Successfully initialize and enable the I2C
- * hardware.
- * - IX_I2C_NOT_SUPPORTED - The hardware does not support or have a
- * dedicated I2C unit to support this driver
- * - IX_I2C_NULL_POINTER - The parameter passed in is a NULL pointed
- * - IX_I2C_INVALID_SPEED_MODE_ENUM_VALUE - The speed mode selected in the
- * InitVarsSelected is invalid
- * - IX_I2C_INVALID_FLOW_MODE_ENUM_VALUE - The flow mode selected in the
- * InitVarsSelected is invalid
- * - IX_I2C_INVALID_SLAVE_ADDR - The address 0x0 is reserved for
- * general call.
- * - IX_I2C_SLAVE_ADDR_CB_MISSING - interrupt mode is selected but
- * slave address callback pointer is NULL
- * - IX_I2C_GEN_CALL_CB_MISSING - interrupt mode is selected but
- * general call callback pointer is NULL
- * - IX_I2C_INT_BIND_FAIL - The ISR for the I2C failed to bind
- * - IX_I2C_INT_UNBIND_FAIL - The ISR for the I2C failed to unbind
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvInit(IxI2cInitVars *InitVarsSelected);
-
-/**
- * @ingroup IxI2cDrv
- *
- * @fn ixI2cDrvUninit(
- void)
- *
- * @brief Disables the I2C hardware
- *
- * @param - None
- *
- * Global Data :
- * - None.
- *
- * This API will disable the I2C hardware, unbind interrupt, and unmap memory.
- *
- * @return
- * - IX_I2C_SUCCESS - successfully un-initialized I2C
- * - IX_I2C_INT_UNBIND_FAIL - failed to unbind the I2C interrupt
- * - IX_I2C_NOT_INIT - I2C not init yet.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvUninit(void);
-
-/**
- * @ingroup IxI2cDrv
- *
- * @fn ixI2cDrvSlaveAddrSet(
- UINT8 SlaveAddrSet)
- *
- * @brief Sets the I2C Slave Address
- *
- * @param "UINT8 [in] SlaveAddrSet" - Slave Address to be inserted into ISAR
- *
- * Global Data :
- * - None.
- *
- * This API will insert the SlaveAddrSet into the ISAR.
- *
- * @return
- * - IX_I2C_SUCCESS - successfuly set the slave addr
- * - IX_I2C_INVALID_SLAVE_ADDR - invalid slave address (zero) specified
- * - IX_I2C_NOT_INIT - I2C not init yet.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvSlaveAddrSet(UINT8 SlaveAddrSet);
-
-/**
- * @ingroup IxI2cDrv
- *
- * @fn ixI2cDrvBusScan(
- void)
- *
- * @brief scans the I2C bus for slave devices
- *
- * @param - None
- *
- * Global Data :
- * - None.
- *
- * This API will prompt all slave addresses for a reply except its own
- *
- * @return
- * - IX_I2C_SUCCESS - found at least one slave device
- * - IX_I2C_FAIL - Fail to find even one slave device
- * - IX_I2C_BUS_BUSY - The I2C bus is busy (held by another I2C master)
- * - IX_I2C_ARB_LOSS - The I2C bus was loss to another I2C master
- * - IX_I2C_NOT_INIT - I2C not init yet.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvBusScan(void);
-
-/**
- * @ingroup IxI2cDrv
- *
- * @fn ixI2cDrvWriteTransfer(
- UINT8 SlaveAddr,
- char *bufP,
- UINT32 dataSize,
- IxI2cXferMode XferModeSelect)
- *
- * @param "UINT8 [in] SlaveAddr" - The slave address to request data from.
- * @param "char [in] *bufP" - The pointer to the data to be transmitted.
- * @param "UINT32 [in] dataSize" - The number of bytes requested.
- * @param "IxI2cXferMode [in] XferModeSelect" - the transfer mode selected,
- * either repeated start (ends w/o stop) or normal (start and stop)
- *
- * Global Data :
- * - None.
- *
- * This API will try to obtain master control of the I2C bus and transmit the
- * number of bytes, specified by dataSize, to the user specified slave
- * address from the buffer pointer. It will use either interrupt or poll mode
- * depending on the method selected.
- *
- * If in interrupt mode and IxI2cMasterWriteCallbackP is not NULL, the driver
- * will initiate the transfer and return immediately. The function pointed to
- * by IxI2cMasterWriteCallbackP will be called in the interrupt service
- * handlers when the operation is complete.
- *
- * If in interrupt mode and IxI2cMasterWriteCallbackP is NULL, then the driver
- * will wait for the operation to complete, and then return.
- *
- * And if the repeated start transfer mode is selected, then it will not send a
- * stop signal at the end of all the transfers.
- * *NOTE*: If repeated start transfer mode is selected, it has to end with a
- * normal mode transfer mode else the bus will continue to be held
- * by the IXP.
- *
- * @return
- * - IX_I2C_SUCCESS - Successfuuly wrote data to slave.
- * - IX_I2C_MASTER_BUS_BUSY - The I2C bus is busy (held by another I2C master)
- * - IX_I2C_MASTER_ARB_LOSS - The I2C bus was loss to another I2C master
- * - IX_I2C_MASTER_XFER_ERROR - There was a transfer error
- * - IX_I2C_MASTER_BUS_ERROR - There was a bus error during transfer
- * - IX_I2C_MASTER_NO_BUFFER - buffer pointer is NULL
- * - IX_I2C_MASTER_INVALID_XFER_MODE - Xfer mode selected is invalid
- * - IX_I2C_DATA_SIZE_ZERO - dataSize passed in is zero, which is invalid
- * - IX_I2C_NOT_INIT - I2C not init yet.
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvWriteTransfer(
- UINT8 SlaveAddr,
- char *bufP,
- UINT32 dataSize,
- IxI2cXferMode XferModeSelect);
-
-/**
- * @ingroup IxI2cDrv
- *
- * @fn ixI2cDrvReadTransfer(
- UINT8 SlaveAddr,
- char *bufP,
- UINT32 dataSize,
- IxI2cXferMode XferModeSelect)
- *
- * @brief Initiates a transfer to receive bytes of data from a slave
- * device through the I2C bus.
- *
- * @param "UINT8 [in] SlaveAddr" - The slave address to request data from.
- * @param "char [out] *bufP" - The pointer to the buffer to store the
- * requested data.
- * @param "UINT32 [in] dataSize" - The number of bytes requested.
- * @param "IxI2cXferMode [in] XferModeSelect" - the transfer mode selected,
- * either repeated start (ends w/o stop) or normal (start and stop)
- *
- * Global Data :
- * - None.
- *
- * This API will try to obtain master control of the I2C bus and receive the
- * number of bytes, specified by dataSize, from the user specified address
- * into the receive buffer. It will use either interrupt or poll mode depending
- * on the mode selected.
- *
- * If in interrupt mode and IxI2cMasterReadCallbackP is not NULL, the driver
- * will initiate the transfer and return immediately. The function pointed to
- * by IxI2cMasterReadCallbackP will be called in the interrupt service
- * handlers when the operation is complete.
- *
- * If in interrupt mode and IxI2cMasterReadCallbackP is NULL, then the driver will
- * wait for the operation to complete, and then return.
- *
- * And if the repeated start transfer mode is selected, then it will not send a
- * stop signal at the end of all the transfers.
- * *NOTE*: If repeated start transfer mode is selected, it has to end with a
- * normal mode transfer mode else the bus will continue to be held
- * by the IXP.
- *
- * @return
- * - IX_I2C_SUCCESS - Successfuuly read slave data
- * - IX_I2C_MASTER_BUS_BUSY - The I2C bus is busy (held by another I2C master)
- * - IX_I2C_MASTER_ARB_LOSS - The I2C bus was loss to another I2C master
- * - IX_I2C_MASTER_XFER_ERROR - There was a bus error during transfer
- * - IX_I2C_MASTER_BUS_ERROR - There was a bus error during transfer
- * - IX_I2C_MASTER_NO_BUFFER - buffer pointer is NULL
- * - IX_I2C_MASTER_INVALID_XFER_MODE - Xfer mode selected is invalid
- * - IX_I2C_INVALID_SLAVE_ADDR - invalid slave address (zero) specified
- * - IX_I2C_DATA_SIZE_ZERO - dataSize passed in is zero, which is invalid
- * - IX_I2C_NOT_INIT - I2C not init yet.
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvReadTransfer(
- UINT8 SlaveAddr,
- char *bufP,
- UINT32 dataSize,
- IxI2cXferMode XferModeSelect);
-
-/**
- * @ingroup IxI2cDrv
- *
- * @fn ixI2cDrvSlaveAddrAndGenCallDetectedCheck(
- void)
- *
- * @brief Checks the I2C Status Register to determine if a slave address is
- * detected
- *
- * @param - None
- *
- * Global Data :
- * - None.
- *
- * This API is used in polled mode to determine if the I2C unit is requested
- * for a slave or general call transfer. If it is requested for a slave
- * transfer then it will determine if it is a general call (read only), read,
- * or write transfer requested.
- *
- * @return
- * - IX_I2C_SLAVE_ADDR_NOT_DETECTED - The I2C unit is not requested for slave
- * transfer
- * - IX_I2C_GEN_CALL_ADDR_DETECTED - The I2C unit is not requested for slave
- * transfer but for general call
- * - IX_I2C_SLAVE_READ_DETECTED - The I2C unit is requested for a read
- * - IX_I2C_SLAVE_WRITE_DETECTED - The I2C unit is requested for a write
- * - IX_I2C_NOT_INIT - I2C not init yet.
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvSlaveAddrAndGenCallDetectedCheck(void);
-
-/**
- * @ingroup IxI2cDrv
- *
- * @fn ixI2cDrvSlaveOrGenDataReceive(
- char *bufP,
- UINT32 bufSize,
- UINT32 *dataSizeRcvd)
- *
- * @brief Performs the slave receive or general call receive data transfer
- *
- * @param "char [in] *bufP" - the pointer to the buffer to store data
- * "UINT32 [in] bufSize" - the buffer size allocated
- * "UINT32 [in] *dataSizeRcvd" - the length of data received in bytes
- *
- * Global Data :
- * - None.
- *
- * This API is only used in polled mode to perform the slave read or general call
- * receive data. It will continuously store the data received into bufP until
- * complete or until bufP is full in which it will return
- * IX_I2C_SLAVE_OR_GEN_READ_BUFFER_FULL. If in interrupt mode, the callback will be
- * used.
- *
- * @return
- * - IX_I2C_SUCCESS - The I2C driver transferred the data successfully.
- * - IX_I2C_SLAVE_OR_GEN_READ_BUFFER_FULL - The I2C driver has ran out of
- * space to store the received data.
- * - IX_I2C_SLAVE_OR_GEN_READ_ERROR - The I2C driver didn't manage to
- * detect the IDBR Rx Full bit
- * - IX_I2C_DATA_SIZE_ZERO - bufSize passed in is zero, which is invalid
- * - IX_I2C_SLAVE_NO_BUFFER - buffer pointer is NULL
- * - IX_I2C_NULL_POINTER - dataSizeRcvd is NULL
- * - IX_I2C_NOT_INIT - I2C not init yet.
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvSlaveOrGenDataReceive(
- char *bufP,
- UINT32 bufSize,
- UINT32 *dataSizeRcvd);
-
-/**
- * @ingroup IxI2cDrv
- *
- * @fn ixI2cDrvSlaveDataTransmit(
- char *bufP,
- UINT32 dataSize,
- UINT32 *dataSizeXmtd)
- *
- * @brief Performs the slave write data transfer
- *
- * @param "char [in] *bufP" - the pointer to the buffer for data to be
- * transmitted
- * "UINT32 [in] bufSize" - the buffer size allocated
- * "UINT32 [in] *dataSizeRcvd" - the length of data trasnmitted in
- * bytes
- *
- * Global Data :
- * - None.
- *
- * This API is only used in polled mode to perform the slave transmit data. It
- * will continuously transmit the data from bufP until complete or until bufP
- * is empty in which it will return IX_I2C_SLAVE_WRITE_BUFFER_EMPTY. If in
- * interrupt mode, the callback will be used.
- *
- * @return
- * - IX_I2C_SUCCESS - The I2C driver transferred the data successfully.
- * - IX_I2C_SLAVE_WRITE_BUFFER_EMPTY - The I2C driver needs more data to
- * transmit.
- * - IX_I2C_SLAVE_WRITE_ERROR -The I2C driver didn't manage to detect the
- * IDBR Tx empty bit or the slave stop bit.
- * - IX_I2C_DATA_SIZE_ZERO - dataSize passed in is zero, which is invalid
- * - IX_I2C_SLAVE_NO_BUFFER - buffer pointer is NULL
- * - IX_I2C_NULL_POINTER - dataSizeXmtd is NULL
- * - IX_I2C_NOT_INIT - I2C not init yet.
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvSlaveDataTransmit(
- char *bufP,
- UINT32 dataSize,
- UINT32 *dataSizeXmtd);
-
-/**
- * @ingroup IxI2cDrv
- *
- * @fn ixI2cDrvSlaveOrGenCallBufReplenish(
- char *bufP,
- UINT32 bufSize)
- *
- * @brief Replenishes the buffer which stores buffer info for both slave and
- * general call
- *
- * @param "char [in] *bufP" - pointer to the buffer allocated
- * "UINT32 [in] bufSize" - size of the buffer
- *
- * Global Data :
- * - None.
- *
- * This API is only used in interrupt mode for replenishing the same buffer
- * that is used by both slave and generall call by updating the buffer info
- * with new info and clearing previous offsets set by previous transfers.
- *
- * @return
- * - None
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-PUBLIC void
-ixI2cDrvSlaveOrGenCallBufReplenish(
- char *bufP,
- UINT32 bufSize);
-
-/**
- * @ingroup IxI2cDrv
- *
- * @fn ixI2cDrvStatsGet(IxI2cStatsCounters *I2cStats)
- *
- * @brief Returns the I2C Statistics through the pointer passed in
- *
- * @param - "IxI2cStatsCounters [out] *I2cStats" - I2C statistics counter will
- * be read and written to the location pointed by this pointer.
- *
- * Global Data :
- * - None.
- *
- * This API will return the statistics counters of the I2C driver.
- *
- * @return
- * - IX_I2C_NULL_POINTER - pointer passed in is NULL
- * - IX_I2C_SUCCESS - successfully obtained I2C statistics
- *
- * @li Reentrant : yes
- * @li ISR Callable : no
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvStatsGet(IxI2cStatsCounters *I2cStats);
-
-/**
- * @ingroup IxI2cDrv
- *
- * @fn ixI2cDrvStatsReset(void)
- *
- * @brief Reset I2C statistics counters.
- *
- * @param - None
- *
- * Global Data :
- * - None.
- *
- * This API will reset the statistics counters of the I2C driver.
- *
- * @return
- * - None
- *
- * @li Reentrant : yes
- * @li ISR Callable : no
- *
- */
-PUBLIC void
-ixI2cDrvStatsReset(void);
-
-/**
- * @ingroup IxI2cDrv
- *
- * @fn ixI2cDrvShow(void)
- *
- * @brief Displays the I2C status register and the statistics counter.
- *
- * @param - None
- *
- * Global Data :
- * - None.
- *
- * This API will display the I2C Status register and is useful if any error
- * occurs. It displays the detection of bus error, slave address, general call,
- * address, IDBR receive full, IDBR transmit empty, arbitration loss, slave
- * STOP signal, I2C bus busy, unit busy, ack/nack, and read/write mode. It will
- * also call the ixI2cDrvGetStats and then display the statistics counter.
- *
- * @return
- * - IX_I2C_SUCCESS - successfully displayed statistics and status register
- * - IX_I2C_NOT_INIT - I2C not init yet.
- *
- * @li Reentrant : yes
- * @li ISR Callable : no
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvShow(void);
-
-/**
- * @ingroup IxI2cDrv
- *
- * @fn ixI2cDrvDelayTypeSelect (IxI2cDelayMode delayMechanismSelect)
- *
- * @brief Sets the delay type of either looping delay or OS scheduler delay
- * according to the argument provided.
- *
- * @param - "IxI2cDelayMode [in] delayTypeSelect" - the I2C delay type selected
- *
- * Global Data :
- * - None.
- *
- * This API will set the delay type used by the I2C Driver to either looping
- * delay or OS scheduler delay.
- *
- * @return
- * - None
- *
- * @li Reentrant : yes
- * @li ISR Callable : no
- *
- */
-PUBLIC void
-ixI2cDrvDelayTypeSelect (IxI2cDelayMode delayTypeSelect);
-
-#endif /* __ixp46X */
-#endif /* IXI2CDRV_H */
+++ /dev/null
-#ifndef __doxygen_HIDE /* This file is not part of the API */
-
-/**
- * @file IxNpeA.h
- *
- * @date 22-Mar-2002
- *
- * @brief Header file for the IXP400 ATM NPE API
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxNpeA IXP400 NPE-A (IxNpeA) API
- *
- * @brief The Public API for the IXP400 NPE-A
- *
- * @{
- */
-
-#ifndef IX_NPE_A_H
-#define IX_NPE_A_H
-
-#include "IxQMgr.h"
-#include "IxOsal.h"
-#include "IxQueueAssignments.h"
-
-/* General Message Ids */
-
-/* ATM Message Ids */
-
-/**
- * @def IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_WRITE
- *
- * @brief ATM Message ID command to write the data to the offset in the
- * Utopia Configuration Table
- */
-#define IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_WRITE 0x20
-
-/**
- * @def IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_LOAD
- *
- * @brief ATM Message ID command triggers the NPE to copy the Utopia
- * Configuration Table to the Utopia coprocessor
- */
-#define IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_LOAD 0x21
-
-/**
- * @def IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_UPLOAD
- *
- * @brief ATM Message ID command triggers the NPE to read-back the Utopia
- * status registers and update the Utopia Status Table.
- */
-#define IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_UPLOAD 0x22
-
-/**
- * @def IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_READ
- *
- * @brief ATM Message ID command to read the Utopia Status Table at the
- * specified offset.
- */
-#define IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_READ 0x23
-
-/**
- * @def IX_NPE_A_MSSG_ATM_TX_ENABLE
- *
- * @brief ATM Message ID command triggers the NPE to re-enable processing
- * of any entries on the TxVcQ for this port.
- *
- * This command will be ignored for a port already enabled
- */
-#define IX_NPE_A_MSSG_ATM_TX_ENABLE 0x25
-
- /**
- * @def IX_NPE_A_MSSG_ATM_TX_DISABLE
- *
- * @brief ATM Message ID command triggers the NPE to disable processing on
- * this port
- *
- * This command will be ignored for a port already disabled
- */
-#define IX_NPE_A_MSSG_ATM_TX_DISABLE 0x26
-
-/**
- * @def IX_NPE_A_MSSG_ATM_RX_ENABLE
- *
- * @brief ATM Message ID command triggers the NPE to process any received
- * cells for this VC according to the VC Lookup Table.
- *
- * Re-issuing this command with different contents for a VC that is not
- * disabled will cause unpredictable behavior.
- */
-#define IX_NPE_A_MSSG_ATM_RX_ENABLE 0x27
-
-/**
- * @def IX_NPE_A_MSSG_ATM_RX_DISABLE
- *
- * @brief ATM Message ID command triggers the NPE to disable processing for
- * this VC.
- *
- * This command will be ignored for a VC already disabled
- */
-#define IX_NPE_A_MSSG_ATM_RX_DISABLE 0x28
-
-/**
- * @def IX_NPE_A_MSSG_ATM_STATUS_READ
- *
- * @brief ATM Message ID command to read the ATM status. The data is returned via
- * a response message
- */
-#define IX_NPE_A_MSSG_ATM_STATUS_READ 0x29
-
-/*--------------------------------------------------------------------------
- * HSS Message IDs
- *--------------------------------------------------------------------------*/
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PORT_CONFIG_WRITE
- *
- * @brief HSS Message ID command writes the ConfigWord value to the location
- * in the HSS_CONFIG_TABLE specified by offset for HSS port hPort.
- */
-#define IX_NPE_A_MSSG_HSS_PORT_CONFIG_WRITE 0x40
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PORT_CONFIG_LOAD
- *
- * @brief HSS Message ID command triggers the NPE to copy the contents of the
- * HSS Configuration Table to the appropriate configuration registers in the
- * HSS coprocessor for the port specified by hPort.
- */
-#define IX_NPE_A_MSSG_HSS_PORT_CONFIG_LOAD 0x41
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PORT_ERROR_READ
- *
- * @brief HSS Message ID command triggers the NPE to return an HssErrorReadResponse
- * message for HSS port hPort.
- */
-#define IX_NPE_A_MSSG_HSS_PORT_ERROR_READ 0x42
-
-/**
- * @def IX_NPE_A_MSSG_HSS_CHAN_FLOW_ENABLE
- *
- * @brief HSS Message ID command triggers the NPE to reset internal status and
- * enable the HssChannelized operation on the HSS port specified by hPort.
- */
-#define IX_NPE_A_MSSG_HSS_CHAN_FLOW_ENABLE 0x43
-
-/**
- * @def IX_NPE_A_MSSG_HSS_CHAN_FLOW_DISABLE
- *
- * @brief HSS Message ID command triggers the NPE to disable the HssChannelized
- * operation on the HSS port specified by hPort.
- */
-#define IX_NPE_A_MSSG_HSS_CHAN_FLOW_DISABLE 0x44
-
-/**
- * @def IX_NPE_A_MSSG_HSS_CHAN_IDLE_PATTERN_WRITE
- *
- * @brief HSS Message ID command writes the HSSnC_IDLE_PATTERN value for HSS
- * port hPort. (n=hPort)
- */
-#define IX_NPE_A_MSSG_HSS_CHAN_IDLE_PATTERN_WRITE 0x45
-
-/**
- * @def IX_NPE_A_MSSG_HSS_CHAN_NUM_CHANS_WRITE
- *
- * @brief HSS Message ID command writes the HSSnC_NUM_CHANNELS value for HSS
- * port hPort. (n=hPort)
- */
-#define IX_NPE_A_MSSG_HSS_CHAN_NUM_CHANS_WRITE 0x46
-
-/**
- * @def IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_ADDR_WRITE
- *
- * @brief HSS Message ID command writes the HSSnC_RX_BUF_ADDR value for HSS
- * port hPort. (n=hPort)
- */
-#define IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_ADDR_WRITE 0x47
-
-/**
- * @def IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_CFG_WRITE
- *
- * @brief HSS Message ID command writes the HSSnC_RX_BUF_SIZEB and
- * HSSnC_RX_TRIG_PERIOD values for HSS port hPort. (n=hPort)
- */
-#define IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_CFG_WRITE 0x48
-
-/**
- * @def IX_NPE_A_MSSG_HSS_CHAN_TX_BLK_CFG_WRITE
- *
- * @brief HSS Message ID command writes the HSSnC_TX_BLK1_SIZEB,
- * HSSnC_TX_BLK1_SIZEW, HSSnC_TX_BLK2_SIZEB, and HSSnC_TX_BLK2_SIZEW values
- * for HSS port hPort. (n=hPort)
- */
-#define IX_NPE_A_MSSG_HSS_CHAN_TX_BLK_CFG_WRITE 0x49
-
-/**
- * @def IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_ADDR_WRITE
- * @brief HSS Message ID command writes the HSSnC_TX_BUF_ADDR value for HSS
- * port hPort. (n=hPort)
- */
-#define IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_ADDR_WRITE 0x4A
-
-/**
- * @def IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_SIZE_WRITE
- *
- * @brief HSS Message ID command writes the HSSnC_TX_BUF_SIZEN value for HSS
- * port hPort. (n=hPort)
- */
-#define IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_SIZE_WRITE 0x4B
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_ENABLE
- *
- * @brief HSS Message ID command triggers the NPE to reset internal status and
- * enable the HssPacketized operation for the flow specified by pPipe on
- * the HSS port specified by hPort.
- */
-#define IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_ENABLE 0x50
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_DISABLE
- * @brief HSS Message ID command triggers the NPE to disable the HssPacketized
- * operation for the flow specified by pPipe on the HSS port specified by hPort.
- */
-#define IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_DISABLE 0x51
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PKT_NUM_PIPES_WRITE
- * @brief HSS Message ID command writes the HSSnP_NUM_PIPES value for HSS
- * port hPort.(n=hPort)
- */
-#define IX_NPE_A_MSSG_HSS_PKT_NUM_PIPES_WRITE 0x52
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_FIFO_SIZEW_WRITE
- *
- * @brief HSS Message ID command writes the HSSnP_PIPEp_FIFOSIZEW value for
- * packet-pipe pPipe on HSS port hPort. (n=hPort, p=pPipe)
- */
-#define IX_NPE_A_MSSG_HSS_PKT_PIPE_FIFO_SIZEW_WRITE 0x53
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_HDLC_CFG_WRITE
- *
- * @brief HSS Message ID command writes the HSSnP_PIPEp_HDLC_RXCFG and
- * HSSnP_PIPEp_HDLC_TXCFG values for packet-pipe pPipe on HSS port hPort.
- * (n=hPort, p=pPipe)
- */
-#define IX_NPE_A_MSSG_HSS_PKT_PIPE_HDLC_CFG_WRITE 0x54
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_IDLE_PATTERN_WRITE
- *
- * @brief HSS Message ID command writes the HSSnP_PIPEp_IDLE_PATTERN value
- * for packet-pipe pPipe on HSS port hPort. (n=hPort, p=pPipe)
- */
-#define IX_NPE_A_MSSG_HSS_PKT_PIPE_IDLE_PATTERN_WRITE 0x55
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_RX_SIZE_WRITE
- *
- * @brief HSS Message ID command writes the HSSnP_PIPEp_RXSIZEB value for
- * packet-pipe pPipe on HSS port hPort. (n=hPort, p=pPipe)
- */
-#define IX_NPE_A_MSSG_HSS_PKT_PIPE_RX_SIZE_WRITE 0x56
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_MODE_WRITE
- *
- * @brief HSS Message ID command writes the HSSnP_PIPEp_MODE value for
- * packet-pipe pPipe on HSS port hPort. (n=hPort, p=pPipe)
- */
-#define IX_NPE_A_MSSG_HSS_PKT_PIPE_MODE_WRITE 0x57
-
-
-
-/* Queue Entry Masks */
-
-/*--------------------------------------------------------------------------
- * ATM Descriptor Structure offsets
- *--------------------------------------------------------------------------*/
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_STATUS_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor Status field
- *
- * It is used for descriptor error reporting.
- */
-#define IX_NPE_A_RXDESCRIPTOR_STATUS_OFFSET 0
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_VCID_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor VC ID field
- *
- * It is used to hold an identifier number for this VC
- */
-#define IX_NPE_A_RXDESCRIPTOR_VCID_OFFSET 1
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_CURRMBUFSIZE_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor Current Mbuf
- * Size field
- *
- * Number of bytes the current mbuf data buffer can hold
- */
-#define IX_NPE_A_RXDESCRIPTOR_CURRMBUFSIZE_OFFSET 2
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_ATMHEADER_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor ATM Header
- */
-#define IX_NPE_A_RXDESCRIPTOR_ATMHEADER_OFFSET 4
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_CURRMBUFLEN_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor Current MBuf length
- *
- *
- * RX - Initialized to zero. The NPE updates this field as each cell is received and
- * zeroes it with every new mbuf for chaining. Will not be bigger than currBbufSize.
- */
-#define IX_NPE_A_RXDESCRIPTOR_CURRMBUFLEN_OFFSET 12
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_TIMELIMIT__OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor Time Limit field
- *
- * Contains the Payload Reassembly Time Limit (used for aal0_xx only)
- */
-#define IX_NPE_A_RXDESCRIPTOR_TIMELIMIT_OFFSET 14
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_PCURRMBUFF_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor Current MBuf Pointer
- *
- * The current mbuf pointer of a chain of mbufs.
- */
-#define IX_NPE_A_RXDESCRIPTOR_PCURRMBUFF_OFFSET 20
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_PCURRMBUFDATA_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor Current MBuf Pointer
- *
- * Pointer to the next byte to be read or next free location to be written.
- */
-#define IX_NPE_A_RXDESCRIPTOR_PCURRMBUFDATA_OFFSET 24
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_PNEXTMBUF_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor Next MBuf Pointer
- *
- * Pointer to the next MBuf in a chain of MBufs.
- */
-#define IX_NPE_A_RXDESCRIPTOR_PNEXTMBUF_OFFSET 28
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_TOTALLENGTH_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor Total Length
- *
- * Total number of bytes written to the chain of MBufs by the NPE
- */
-#define IX_NPE_A_RXDESCRIPTOR_TOTALLENGTH_OFFSET 32
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor AAL5 CRC Residue
- *
- * Current CRC value for a PDU
- */
-#define IX_NPE_A_RXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET 36
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_SIZE
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor Size
- *
- * The size of the Receive descriptor
- */
-#define IX_NPE_A_RXDESCRIPTOR_SIZE 40
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_PORT_OFFSET
- *
- * @brief ATM Descriptor structure offset for Transmit Descriptor Port
- *
- * Port identifier.
- */
-#define IX_NPE_A_TXDESCRIPTOR_PORT_OFFSET 0
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_RSVD_OFFSET
- *
- * @brief ATM Descriptor structure offset for Transmit Descriptor RSVD
- */
-#define IX_NPE_A_TXDESCRIPTOR_RSVD_OFFSET 1
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_CURRMBUFLEN_OFFSET
- *
- * @brief ATM Descriptor structure offset for Transmit Descriptor Current MBuf Length
- *
- * TX - Initialized by the XScale to the number of bytes in the current MBuf data buffer.
- * The NPE decrements this field for every transmitted cell. Thus, when the NPE writes a
- * descriptor the TxDone queue, this field will equal zero.
- */
-#define IX_NPE_A_TXDESCRIPTOR_CURRMBUFLEN_OFFSET 2
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_ATMHEADER_OFFSET
- * @brief ATM Descriptor structure offset for Transmit Descriptor ATM Header
- */
-#define IX_NPE_A_TXDESCRIPTOR_ATMHEADER_OFFSET 4
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_PCURRMBUFF_OFFSET
- *
- * @brief ATM Descriptor structure offset for Transmit Descriptor Pointer to the current MBuf chain
- */
-#define IX_NPE_A_TXDESCRIPTOR_PCURRMBUFF_OFFSET 8
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_PCURRMBUFDATA_OFFSET
- *
- * @brief ATM Descriptor structure offset for Transmit Descriptor Pointer to the current MBuf Data
- *
- * Pointer to the next byte to be read or next free location to be written.
- */
-#define IX_NPE_A_TXDESCRIPTOR_PCURRMBUFDATA_OFFSET 12
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_PNEXTMBUF_OFFSET
- *
- * @brief ATM Descriptor structure offset for Transmit Descriptor Pointer to the Next MBuf chain
- */
-#define IX_NPE_A_TXDESCRIPTOR_PNEXTMBUF_OFFSET 16
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_TOTALLENGTH_OFFSET
- *
- * @brief ATM Descriptor structure offset for Transmit Descriptor Total Length
- *
- * Total number of bytes written to the chain of MBufs by the NPE
- */
-#define IX_NPE_A_TXDESCRIPTOR_TOTALLENGTH_OFFSET 20
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET
- *
- * @brief ATM Descriptor structure offset for Transmit Descriptor AAL5 CRC Residue
- *
- * Current CRC value for a PDU
- */
-#define IX_NPE_A_TXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET 24
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_SIZE
- *
- * @brief ATM Descriptor structure offset for Transmit Descriptor Size
- */
-#define IX_NPE_A_TXDESCRIPTOR_SIZE 28
-
-/**
- * @def IX_NPE_A_CHAIN_DESC_COUNT_MAX
- *
- * @brief Maximum number of chained MBufs that can be chained together
- */
-#define IX_NPE_A_CHAIN_DESC_COUNT_MAX 256
-
-/*
- * Definition of the ATM cell header
- *
- * This would most conviently be defined as the bit field shown below.
- * Endian portability prevents this, therefore a set of macros
- * are defined to access the fields within the cell header assumed to
- * be passed as a UINT32.
- *
- * Changes to field sizes or orders must be reflected in the offset
- * definitions above.
- *
- * typedef struct
- * {
- * unsigned int gfc:4;
- * unsigned int vpi:8;
- * unsigned int vci:16;
- * unsigned int pti:3;
- * unsigned int clp:1;
- * } IxNpeA_AtmCellHeader;
- *
- */
-
-/** Mask to acess GFC */
-#define GFC_MASK 0xf0000000
-
-/** return GFC from ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_GFC_GET( header ) \
-(((header) & GFC_MASK) >> 28)
-
-/** set GFC into ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_GFC_SET( header,gfc ) \
-do { \
- (header) &= ~GFC_MASK; \
- (header) |= (((gfc) << 28) & GFC_MASK); \
-} while(0)
-
-/** Mask to acess VPI */
-#define VPI_MASK 0x0ff00000
-
-/** return VPI from ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_VPI_GET( header ) \
-(((header) & VPI_MASK) >> 20)
-
-/** set VPI into ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_VPI_SET( header, vpi ) \
-do { \
- (header) &= ~VPI_MASK; \
- (header) |= (((vpi) << 20) & VPI_MASK); \
-} while(0)
-
-/** Mask to acess VCI */
-#define VCI_MASK 0x000ffff0
-
-/** return VCI from ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_VCI_GET( header ) \
-(((header) & VCI_MASK) >> 4)
-
-/** set VCI into ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_VCI_SET( header, vci ) \
-do { \
- (header) &= ~VCI_MASK; \
- (header) |= (((vci) << 4) & VCI_MASK); \
-} while(0)
-
-/** Mask to acess PTI */
-#define PTI_MASK 0x0000000e
-
-/** return PTI from ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_PTI_GET( header ) \
-(((header) & PTI_MASK) >> 1)
-
-/** set PTI into ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_PTI_SET( header, pti ) \
-do { \
- (header) &= ~PTI_MASK; \
- (header) |= (((pti) << 1) & PTI_MASK); \
-} while(0)
-
-/** Mask to acess CLP */
-#define CLP_MASK 0x00000001
-
-/** return CLP from ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_CLP_GET( header ) \
-((header) & CLP_MASK)
-
-/** set CLP into ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_CLP_SET( header, clp ) \
-do { \
- (header) &= ~CLP_MASK; \
- (header) |= ((clp) & CLP_MASK); \
-} while(0)
-
-
-/*
-* Definition of the Rx bitfield
-*
-* This would most conviently be defined as the bit field shown below.
-* Endian portability prevents this, therefore a set of macros
-* are defined to access the fields within the rxBitfield assumed to
-* be passed as a UINT32.
-*
-* Changes to field sizes or orders must be reflected in the offset
-* definitions above.
-*
-* Rx bitfield
-* struct
-* { IX_NPEA_RXBITFIELD(
-* unsigned int status:1,
-* unsigned int port:7,
-* unsigned int vcId:8,
-* unsigned int currMbufSize:16);
-* } rxBitField;
-*
-*/
-
-/** Mask to acess the rxBitField status */
-#define STATUS_MASK 0x80000000
-
-/** return the rxBitField status */
-#define IX_NPE_A_RXBITFIELD_STATUS_GET( rxbitfield ) \
-(((rxbitfield) & STATUS_MASK) >> 31)
-
-/** set the rxBitField status */
-#define IX_NPE_A_RXBITFIELD_STATUS_SET( rxbitfield, status ) \
-do { \
- (rxbitfield) &= ~STATUS_MASK; \
- (rxbitfield) |= (((status) << 31) & STATUS_MASK); \
-} while(0)
-
-/** Mask to acess the rxBitField port */
-#define PORT_MASK 0x7f000000
-
-/** return the rxBitField port */
-#define IX_NPE_A_RXBITFIELD_PORT_GET( rxbitfield ) \
-(((rxbitfield) & PORT_MASK) >> 24)
-
-/** set the rxBitField port */
-#define IX_NPE_A_RXBITFIELD_PORT_SET( rxbitfield, port ) \
-do { \
- (rxbitfield) &= ~PORT_MASK; \
- (rxbitfield) |= (((port) << 24) & PORT_MASK); \
-} while(0)
-
-/** Mask to acess the rxBitField vcId */
-#define VCID_MASK 0x00ff0000
-
-/** return the rxBitField vcId */
-#define IX_NPE_A_RXBITFIELD_VCID_GET( rxbitfield ) \
-(((rxbitfield) & VCID_MASK) >> 16)
-
-/** set the rxBitField vcId */
-#define IX_NPE_A_RXBITFIELD_VCID_SET( rxbitfield, vcid ) \
-do { \
- (rxbitfield) &= ~VCID_MASK; \
- (rxbitfield) |= (((vcid) << 16) & VCID_MASK); \
-} while(0)
-
-/** Mask to acess the rxBitField mbuf size */
-#define CURRMBUFSIZE_MASK 0x0000ffff
-
-/** return the rxBitField mbuf size */
-#define IX_NPE_A_RXBITFIELD_CURRMBUFSIZE_GET( rxbitfield ) \
-((rxbitfield) & CURRMBUFSIZE_MASK)
-
-/** set the rxBitField mbuf size */
-#define IX_NPE_A_RXBITFIELD_CURRMBUFSIZE_SET( rxbitfield, currmbufsize ) \
-do { \
- (rxbitfield) &= ~CURRMBUFSIZE_MASK; \
- (rxbitfield) |= ((currmbufsize) & CURRMBUFSIZE_MASK); \
-} while(0)
-
-
-
-/**
- * @brief Tx Descriptor definition
- */
-typedef struct
-{
- UINT8 port; /**< Tx Port number */
- UINT8 aalType; /**< AAL Type */
- UINT16 currMbufLen; /**< mbuf length */
- UINT32 atmCellHeader; /**< ATM cell header */
- IX_OSAL_MBUF *pCurrMbuf; /**< pointer to mbuf */
- unsigned char *pCurrMbufData; /**< Pointer to mbuf->dat */
- IX_OSAL_MBUF *pNextMbuf; /**< Pointer to next mbuf */
- UINT32 totalLen; /**< Total Length */
- UINT32 aal5CrcResidue; /**< AAL5 CRC Residue */
-} IxNpeA_TxAtmVc;
-
-/* Changes to field sizes or orders must be reflected in the offset
- * definitions above. */
-
-
-
-
-/**
- * @brief Rx Descriptor definition
- */
-typedef struct
-{
- UINT32 rxBitField; /**< Received bit field */
- UINT32 atmCellHeader; /**< ATM Cell Header */
- UINT32 rsvdWord0; /**< Reserved field */
- UINT16 currMbufLen; /**< Mbuf Length */
- UINT8 timeLimit; /**< Payload Reassembly timeLimit (used for aal0_xx only) */
- UINT8 rsvdByte0; /**< Reserved field */
- UINT32 rsvdWord1; /**< Reserved field */
- IX_OSAL_MBUF *pCurrMbuf; /**< Pointer to current mbuf */
- unsigned char *pCurrMbufData; /**< Pointer to current mbuf->data */
- IX_OSAL_MBUF *pNextMbuf; /**< Pointer to next mbuf */
- UINT32 totalLen; /**< Total Length */
- UINT32 aal5CrcResidue; /**< AAL5 CRC Residue */
-} IxNpeA_RxAtmVc;
-
-
-/**
- * @brief NPE-A AAL Type
- */
-typedef enum
-{
- IX_NPE_A_AAL_TYPE_INVALID = 0, /**< Invalid AAL type */
- IX_NPE_A_AAL_TYPE_0_48 = 0x1, /**< AAL0 - 48 byte */
- IX_NPE_A_AAL_TYPE_0_52 = 0x2, /**< AAL0 - 52 byte */
- IX_NPE_A_AAL_TYPE_5 = 0x5, /**< AAL5 */
- IX_NPE_A_AAL_TYPE_OAM = 0xF /**< OAM */
-} IxNpeA_AalType;
-
-/**
- * @brief NPE-A Payload format 52-bytes & 48-bytes
- */
-typedef enum
-{
- IX_NPE_A_52_BYTE_PAYLOAD = 0, /**< 52 byte payload */
- IX_NPE_A_48_BYTE_PAYLOAD /**< 48 byte payload */
-} IxNpeA_PayloadFormat;
-
-/**
- * @brief HSS Packetized NpePacket Descriptor Structure
- */
-typedef struct
-{
- UINT8 status; /**< Status of the packet passed to the client */
- UINT8 errorCount; /**< Number of errors */
- UINT8 chainCount; /**< Mbuf chain count e.g. 0 - No mbuf chain */
- UINT8 rsvdByte0; /**< Reserved byte to make the descriptor word align */
-
- UINT16 packetLength; /**< Packet Length */
- UINT16 rsvdShort0; /**< Reserved short to make the descriptor a word align */
-
- IX_OSAL_MBUF *pRootMbuf; /**< Pointer to Root mbuf */
- IX_OSAL_MBUF *pNextMbuf; /**< Pointer to next mbuf */
- UINT8 *pMbufData; /**< Pointer to the current mbuf->data */
- UINT32 mbufLength; /**< Current mbuf length */
-
-} IxNpeA_NpePacketDescriptor;
-
-
-#endif
-/**
- *@}
- */
-
-#endif /* __doxygen_HIDE */
+++ /dev/null
-/**
- * @file IxNpeDl.h
- *
- * @date 14 December 2001
-
- * @brief This file contains the public API of the IXP400 NPE Downloader
- * component.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeDl IXP400 NPE-Downloader (IxNpeDl) API
- *
- * @brief The Public API for the IXP400 NPE Downloader
- *
- * @{
- */
-
-#ifndef IXNPEDL_H
-#define IXNPEDL_H
-
-/*
- * Put the user defined include files required
- */
-#include "IxOsalTypes.h"
-#include "IxNpeMicrocode.h"
-
-/*
- * #defines for function return types, etc.
- */
-
-/**
- * @def IX_NPEDL_PARAM_ERR
- *
- * @brief NpeDl function return value for a parameter error
- */
-#define IX_NPEDL_PARAM_ERR 2
-
-/**
- * @def IX_NPEDL_RESOURCE_ERR
- *
- * @brief NpeDl function return value for a resource error
- */
-#define IX_NPEDL_RESOURCE_ERR 3
-
-/**
- * @def IX_NPEDL_CRITICAL_NPE_ERR
- *
- * @brief NpeDl function return value for a Critical NPE error occuring during
- download. Assume NPE is left in unstable condition if this value is
- returned or NPE is hang / halt.
- */
-#define IX_NPEDL_CRITICAL_NPE_ERR 4
-
-/**
- * @def IX_NPEDL_CRITICAL_MICROCODE_ERR
- *
- * @brief NpeDl function return value for a Critical Microcode error
- * discovered during download. Assume NPE is left in unstable condition
- * if this value is returned.
- */
-#define IX_NPEDL_CRITICAL_MICROCODE_ERR 5
-
-/**
- * @def IX_NPEDL_DEVICE_ERR
- *
- * @brief NpeDl function return value when image being downloaded
- * is not meant for the device in use
- */
-#define IX_NPEDL_DEVICE_ERR 6
-
-/**
- * @defgroup NPEImageID IXP400 NPE Image ID Definition
- *
- * @ingroup IxNpeDl
- *
- * @brief Definition of NPE Image ID to be passed to ixNpeDlNpeInitAndStart()
- * as input of type UINT32 which has the following fields format:
- *
- * Field [Bit Location] <BR>
- * -------------------- <BR>
- * Device ID [31 - 28] <BR>
- * NPE ID [27 - 24] <BR>
- * NPE Functionality ID [23 - 16] <BR>
- * Major Release Number [15 - 8] <BR>
- * Minor Release Number [7 - 0] <BR>
- *
- *
- * @{
- */
-
-/**
- * @def IX_NPEDL_NPEIMAGE_FIELD_MASK
- *
- * @brief Mask for NPE Image ID's Field
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define IX_NPEDL_NPEIMAGE_FIELD_MASK 0xff
-
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEID_MASK
- *
- * @brief Mask for NPE Image NPE ID's Field
- *
- */
-#define IX_NPEDL_NPEIMAGE_NPEID_MASK 0xf
-
-/**
- * @def IX_NPEDL_NPEIMAGE_DEVICEID_MASK
- *
- * @brief Mask for NPE Image Device ID's Field
- *
- */
-#define IX_NPEDL_NPEIMAGE_DEVICEID_MASK 0xf
-
-/**
- * @def IX_NPEDL_NPEIMAGE_BIT_LOC_NPEID
- *
- * @brief Location of NPE ID field in term of bit.
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define IX_NPEDL_NPEIMAGE_BIT_LOC_NPEID 24
-
-/**
- * @def IX_NPEDL_NPEIMAGE_BIT_LOC_FUNCTIONALITYID
- *
- * @brief Location of Functionality ID field in term of bit.
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define IX_NPEDL_NPEIMAGE_BIT_LOC_FUNCTIONALITYID 16
-
-/**
- * @def IX_NPEDL_NPEIMAGE_BIT_LOC_MAJOR
- *
- * @brief Location of Major Release Number field in term of bit.
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define IX_NPEDL_NPEIMAGE_BIT_LOC_MAJOR 8
-
-/**
- * @def IX_NPEDL_NPEIMAGE_BIT_LOC_MINOR
- *
- * @brief Location of Minor Release Number field in term of bit.
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define IX_NPEDL_NPEIMAGE_BIT_LOC_MINOR 0
-
-/**
- * @} addtogroup NPEImageID
- */
-
-/**
- * @def ixNpeDlMicrocodeImageOverride(x)
- *
- * @brief Map old terminology that uses term "image" to new term
- * "image library"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define ixNpeDlMicrocodeImageOverride(x) ixNpeDlMicrocodeImageLibraryOverride(x)
-
-/**
- * @def IxNpeDlVersionId
- *
- * @brief Map old terminology that uses term "version" to new term
- * "image"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define IxNpeDlVersionId IxNpeDlImageId
-
-/**
- * @def ixNpeDlVersionDownload
- *
- * @brief Map old terminology that uses term "version" to new term
- * "image"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define ixNpeDlVersionDownload(x,y) ixNpeDlImageDownload(x,y)
-
-/**
- * @def ixNpeDlAvailableVersionsCountGet
- *
- * @brief Map old terminology that uses term "version" to new term
- * "image"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define ixNpeDlAvailableVersionsCountGet(x) ixNpeDlAvailableImagesCountGet(x)
-
-/**
- * @def ixNpeDlAvailableVersionsListGet
- *
- * @brief Map old terminology that uses term "version" to new term
- * "image"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define ixNpeDlAvailableVersionsListGet(x,y) ixNpeDlAvailableImagesListGet(x,y)
-
- /**
- * @def ixNpeDlLoadedVersionGet
- *
- * @brief Map old terminology that uses term "version" to new term
- * "image"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define ixNpeDlLoadedVersionGet(x,y) ixNpeDlLoadedImageGet(x,y)
-
- /**
- * @def clientImage
- *
- * @brief Map old terminology that uses term "image" to new term
- * "image library"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define clientImage clientImageLibrary
-
- /**
- * @def versionIdPtr
- *
- * @brief Map old terminology that uses term "version" to new term
- * "image"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define versionIdPtr imageIdPtr
-
- /**
- * @def numVersionsPtr
- *
- * @brief Map old terminology that uses term "version" to new term
- * "image"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define numVersionsPtr numImagesPtr
-
-/**
- * @def versionIdListPtr
- *
- * @brief Map old terminology that uses term "version" to new term
- * "image"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define versionIdListPtr imageIdListPtr
-
-/**
- * @def IxNpeDlBuildId
- *
- * @brief Map old terminology that uses term "buildId" to new term
- * "functionalityId"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define IxNpeDlBuildId IxNpeDlFunctionalityId
-
-/**
- * @def buildId
- *
- * @brief Map old terminology that uses term "buildId" to new term
- * "functionalityId"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define buildId functionalityId
-
-/**
- * @def IX_NPEDL_MicrocodeImage
- *
- * @brief Map old terminology that uses term "image" to new term
- * "image library"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define IX_NPEDL_MicrocodeImage IX_NPEDL_MicrocodeImageLibrary
-
-/*
- * Typedefs
- */
-
-/**
- * @typedef IxNpeDlFunctionalityId
- * @brief Used to make up Functionality ID field of Image Id
- *
- * @warning <b>THIS typedef HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-typedef UINT8 IxNpeDlFunctionalityId;
-
-/**
- * @typedef IxNpeDlMajor
- * @brief Used to make up Major Release field of Image Id
- *
- * @warning <b>THIS typedef HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-typedef UINT8 IxNpeDlMajor;
-
-/**
- * @typedef IxNpeDlMinor
- * @brief Used to make up Minor Revision field of Image Id
- *
- * @warning <b>THIS typedef HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-typedef UINT8 IxNpeDlMinor;
-
-/*
- * Enums
- */
-
-/**
- * @brief NpeId numbers to identify NPE A, B or C
- * @note In this context, for IXP425 Silicon (B0):<br>
- * - NPE-A has HDLC, HSS, AAL and UTOPIA Coprocessors.<br>
- * - NPE-B has Ethernet Coprocessor.<br>
- * - NPE-C has Ethernet, AES, DES and HASH Coprocessors.<br>
- * - IXP400 Product Line have different combinations of coprocessors.
- */
-typedef enum
-{
- IX_NPEDL_NPEID_NPEA = 0, /**< Identifies NPE A */
- IX_NPEDL_NPEID_NPEB, /**< Identifies NPE B */
- IX_NPEDL_NPEID_NPEC, /**< Identifies NPE C */
- IX_NPEDL_NPEID_MAX /**< Total Number of NPEs */
-} IxNpeDlNpeId;
-
-/*
- * Structs
- */
-
-/**
- * @brief Image Id to identify each image contained in an image library
- *
- * @warning <b>THIS struct HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-typedef struct
-{
- IxNpeDlNpeId npeId; /**< NPE ID */
- IxNpeDlFunctionalityId functionalityId; /**< Build ID indicates functionality of image */
- IxNpeDlMajor major; /**< Major Release Number */
- IxNpeDlMinor minor; /**< Minor Revision Number */
-} IxNpeDlImageId;
-
-/*
- * Prototypes for interface functions
- */
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlNpeInitAndStart (UINT32 imageId)
- *
- * @brief Stop, reset, download microcode (firmware) and finally start NPE.
- *
- * @param imageId UINT32 [in] - Id of the microcode image to download.
- *
- * This function locates the image specified by the <i>imageId</i> parameter
- * from the default microcode image library which is included internally by
- * this component.
- * It then stops and resets the NPE, loads the firmware image onto the NPE,
- * and then restarts the NPE.
- *
- * @note A list of valid image IDs is included in this header file.
- * See #defines with prefix IX_NPEDL_NPEIMAGE_...
- *
- * @note This function, along with @ref ixNpeDlCustomImageNpeInitAndStart
- * and @ref ixNpeDlLoadedImageFunctionalityGet, supercedes the following
- * functions which are deprecated and will be removed completely in a
- * future release:
- * - @ref ixNpeDlImageDownload
- * - @ref ixNpeDlAvailableImagesCountGet
- * - @ref ixNpeDlAvailableImagesListGet
- * - @ref ixNpeDlLatestImageGet
- * - @ref ixNpeDlLoadedImageGet
- * - @ref ixNpeDlMicrocodeImageLibraryOverride
- * - @ref ixNpeDlNpeExecutionStop
- * - @ref ixNpeDlNpeStopAndReset
- * - @ref ixNpeDlNpeExecutionStart
- *
- * @pre
- * - The Client is responsible for ensuring mutual access to the NPE.
- * @post
- * - The NPE Instruction Pipeline will be cleared if State Information
- * has been downloaded.
- * - If the download fails with a critical error, the NPE may
- * be left in an ususable state.
- * @return
- * - IX_SUCCESS if the download was successful;
- * - IX_NPEDL_PARAM_ERR if a parameter error occured
- * - IX_NPEDL_CRITICAL_NPE_ERR if a critical NPE error occured during
- * download
- * - IX_NPEDL_CRITICAL_MICROCODE_ERR if a critical microcode error
- * occured during download
- * - IX_NPEDL_DEVICE_ERR if the image being loaded is not meant for
- * the device currently running.
- * - IX_FAIL if NPE is not available or image is failed to be located.
- * A warning is issued if the NPE is not present.
- */
-PUBLIC IX_STATUS
-ixNpeDlNpeInitAndStart (UINT32 npeImageId);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlCustomImageNpeInitAndStart (UINT32 *imageLibrary,
- UINT32 imageId)
- *
- * @brief Stop, reset, download microcode (firmware) and finally start NPE
- *
- * @param imageId UINT32 [in] - Id of the microcode image to download.
- *
- * This function locates the image specified by the <i>imageId</i> parameter
- * from the specified microcode image library which is pointed to by the
- * <i>imageLibrary</i> parameter.
- * It then stops and resets the NPE, loads the firmware image onto the NPE,
- * and then restarts the NPE.
- *
- * This is a facility for users who wish to use an image from an external
- * library of NPE firmware images. To use a standard image from the
- * built-in library, see @ref ixNpeDlNpeInitAndStart instead.
- *
- * @note A list of valid image IDs is included in this header file.
- * See #defines with prefix IX_NPEDL_NPEIMAGE_...
- *
- * @note This function, along with @ref ixNpeDlNpeInitAndStart
- * and @ref ixNpeDlLoadedImageFunctionalityGet, supercedes the following
- * functions which are deprecated and will be removed completely in a
- * future release:
- * - @ref ixNpeDlImageDownload
- * - @ref ixNpeDlAvailableImagesCountGet
- * - @ref ixNpeDlAvailableImagesListGet
- * - @ref ixNpeDlLatestImageGet
- * - @ref ixNpeDlLoadedImageGet
- * - @ref ixNpeDlMicrocodeImageLibraryOverride
- * - @ref ixNpeDlNpeExecutionStop
- * - @ref ixNpeDlNpeStopAndReset
- * - @ref ixNpeDlNpeExecutionStart
- *
- * @pre
- * - The Client is responsible for ensuring mutual access to the NPE.
- * - The image library supplied must be in the correct format for use
- * by the NPE Downloader (IxNpeDl) component. Details of the library
- * format are contained in the Functional Specification document for
- * IxNpeDl.
- * @post
- * - The NPE Instruction Pipeline will be cleared if State Information
- * has been downloaded.
- * - If the download fails with a critical error, the NPE may
- * be left in an ususable state.
- * @return
- * - IX_SUCCESS if the download was successful;
- * - IX_NPEDL_PARAM_ERR if a parameter error occured
- * - IX_NPEDL_CRITICAL_NPE_ERR if a critical NPE error occured during
- * download
- * - IX_NPEDL_CRITICAL_MICROCODE_ERR if a critical microcode error
- * occured during download
- * - IX_NPEDL_DEVICE_ERR if the image being loaded is not meant for
- * the device currently running.
- * - IX_FAIL if NPE is not available or image is failed to be located.
- * A warning is issued if the NPE is not present.
- */
-PUBLIC IX_STATUS
-ixNpeDlCustomImageNpeInitAndStart (UINT32 *imageLibrary,
- UINT32 npeImageId);
-
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlLoadedImageFunctionalityGet (IxNpeDlNpeId npeId,
- UINT8 *functionalityId)
- *
- * @brief Gets the functionality of the image last loaded on a particular NPE
- *
- * @param npeId @ref IxNpeDlNpeId [in] - Id of the target NPE.
- * @param functionalityId UINT8* [out] - the functionality ID of the image
- * last loaded on the NPE.
- *
- * This function retrieves the functionality ID of the image most recently
- * downloaded successfully to the specified NPE. If the NPE does not contain
- * a valid image, this function returns a FAIL status.
- *
- * @warning This function is not intended for general use, as a knowledge of
- * how to interpret the functionality ID is required. As such, this function
- * should only be used by other Access Layer components of the IXP400 Software
- * Release.
- *
- * @pre
- *
- * @post
- *
- * @return
- * - IX_SUCCESS if the operation was successful
- * - IX_NPEDL_PARAM_ERR if a parameter error occured
- * - IX_FAIL if the NPE does not have a valid image loaded
- */
-PUBLIC IX_STATUS
-ixNpeDlLoadedImageFunctionalityGet (IxNpeDlNpeId npeId,
- UINT8 *functionalityId);
-
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn IX_STATUS ixNpeDlMicrocodeImageLibraryOverride (UINT32 *clientImageLibrary)
- *
- * @brief This instructs NPE Downloader to use client-supplied microcode image library.
- *
- * @param clientImageLibrary UINT32* [in] - Pointer to the client-supplied
- * NPE microcode image library
- *
- * This function sets NPE Downloader to use a client-supplied microcode image library
- * instead of the standard image library which is included by the NPE Downloader.
- * <b>This function is provided mainly for increased testability and should not
- * be used in normal circumstances.</b> When not used, NPE Downloader will use
- * a "built-in" image library, local to this component, which should always contain the
- * latest microcode for the NPEs.
- *
- * @warning <b>THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlCustomImageNpeInitAndStart.
- *
- * @pre
- * - <i>clientImageLibrary</i> should point to a microcode image library valid for use
- * by the NPE Downloader component.
- *
- * @post
- * - the client-supplied image library will be used for all subsequent operations
- * performed by the NPE Downloader
- *
- * @return
- * - IX_SUCCESS if the operation was successful
- * - IX_NPEDL_PARAM_ERR if a parameter error occured
- * - IX_FAIL if the client-supplied image library did not contain a valid signature
- */
-PUBLIC IX_STATUS
-ixNpeDlMicrocodeImageLibraryOverride (UINT32 *clientImageLibrary);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlImageDownload (IxNpeDlImageId *imageIdPtr,
- BOOL verify)
- *
- * @brief Stop, reset, download microcode and finally start NPE.
- *
- * @param imageIdPtr @ref IxNpeDlImageId* [in] - Pointer to Id of the microcode
- * image to download.
- * @param verify BOOL [in] - ON/OFF option to verify the download. If ON
- * (verify == true), the Downloader will read back
- * each word written to the NPE registers to
- * ensure the download operation was successful.
- *
- * Using the <i>imageIdPtr</i>, this function locates a particular image of
- * microcode in the microcode image library in memory, and downloads the microcode
- * to a particular NPE.
- *
- * @warning <b>THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart and @ref ixNpeDlCustomImageNpeInitAndStart.
- *
- * @pre
- * - The Client is responsible for ensuring mutual access to the NPE.
- * - The Client should use ixNpeDlLatestImageGet() to obtain the latest
- * version of the image before attempting download.
- * @post
- * - The NPE Instruction Pipeline will be cleared if State Information
- * has been downloaded.
- * - If the download fails with a critical error, the NPE may
- * be left in an ususable state.
- * @return
- * - IX_SUCCESS if the download was successful;
- * - IX_NPEDL_PARAM_ERR if a parameter error occured
- * - IX_NPEDL_CRITICAL_NPE_ERR if a critical NPE error occured during
- * download
- * - IX_PARAM_CRITICAL_MICROCODE_ERR if a critical microcode error
- * occured during download
- * - IX_FAIL if NPE is not available or image is failed to be located.
- * A warning is issued if the NPE is not present.
- */
-PUBLIC IX_STATUS
-ixNpeDlImageDownload (IxNpeDlImageId *imageIdPtr,
- BOOL verify);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlAvailableImagesCountGet (UINT32 *numImagesPtr)
- *
- * @brief Get the number of Images available in a microcode image library
- *
- * @param numImagesPtr UINT32* [out] - A pointer to the number of images in
- * the image library.
- *
- * Gets the number of images available in the microcode image library.
- * Then returns this in a variable pointed to by <i>numImagesPtr</i>.
- *
- * @warning <b>THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart and @ref ixNpeDlCustomImageNpeInitAndStart.
- *
- * @pre
- * - The Client should declare the variable to which numImagesPtr points
- *
- * @post
- *
- * @return
- * - IX_SUCCESS if the operation was successful
- * - IX_NPEDL_PARAM_ERR if a parameter error occured
- * - IX_FAIL otherwise
- */
-PUBLIC IX_STATUS
-ixNpeDlAvailableImagesCountGet (UINT32 *numImagesPtr);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlAvailableImagesListGet (IxNpeDlImageId *imageIdListPtr,
- UINT32 *listSizePtr)
- *
- * @brief Get a list of the images available in a microcode image library
- *
- * @param imageIdListPtr @ref IxNpeDlImageId* [out] - Array to contain list of
- * image Ids (memory
- * allocated by Client).
- * @param listSizePtr UINT32* [inout] - As an input, this param should point
- * to the max number of Ids the
- * <i>imageIdListPtr</i> array can
- * hold. NpeDl will replace the input
- * value of this parameter with the
- * number of image Ids actually filled
- * into the array before returning.
- *
- * Finds list of images available in the microcode image library.
- * Fills these into the array pointed to by <i>imageIdListPtr</i>
- *
- * @warning <b>THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart and @ref ixNpeDlCustomImageNpeInitAndStart.
- *
- * @pre
- * - The Client should declare the variable to which numImagesPtr points
- * - The Client should create an array (<i>imageIdListPtr</i>) large
- * enough to contain all the image Ids in the image library
- *
- * @post
- *
- * @return
- * - IX_SUCCESS if the operation was successful
- * - IX_NPEDL_PARAM_ERR if a parameter error occured
- * - IX_FAIL otherwise
- */
-PUBLIC IX_STATUS
-ixNpeDlAvailableImagesListGet (IxNpeDlImageId *imageIdListPtr,
- UINT32 *listSizePtr);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlLoadedImageGet (IxNpeDlNpeId npeId,
- IxNpeDlImageId *imageIdPtr)
- *
- * @brief Gets the Id of the image currently loaded on a particular NPE
- *
- * @param npeId @ref IxNpeDlNpeId [in] - Id of the target NPE.
- * @param imageIdPtr @ref IxNpeDlImageId* [out] - Pointer to the where the
- * image id should be stored.
- *
- * If an image of microcode was previously downloaded successfully to the NPE
- * by NPE Downloader, this function returns in <i>imageIdPtr</i> the image
- * Id of that image loaded on the NPE.
- *
- * @pre
- * - The Client has allocated memory to the <i>imageIdPtr</i> pointer.
- *
- * @post
- *
- * @return
- * - IX_SUCCESS if the operation was successful
- * - IX_NPEDL_PARAM_ERR if a parameter error occured
- * - IX_FAIL if the NPE doesn't currently have a image loaded
- */
-PUBLIC IX_STATUS
-ixNpeDlLoadedImageGet (IxNpeDlNpeId npeId,
- IxNpeDlImageId *imageIdPtr);
-
-/**
- * @fn PUBLIC IX_STATUS ixNpeDlLatestImageGet (IxNpeDlNpeId npeId, IxNpeDlFunctionalityId
- functionalityId, IxNpeDlImageId *imageIdPtr)
- *
- * @brief This instructs NPE Downloader to get Id of the latest version for an
- * image that is specified by the client.
- *
- * @param npeId @ref IxNpeDlNpeId [in] - Id of the target NPE.
- * @param functionalityId @ref IxNpeDlFunctionalityId [in] - functionality of the image
- * @param imageIdPtr @ref IxNpeDlImageId* [out] - Pointer to the where the
- * image id should be stored.
- *
- * This function sets NPE Downloader to return the id of the latest version for
- * image. The user will select the image by providing a particular NPE
- * (specifying <i>npeId</i>) with particular functionality (specifying
- * <i>FunctionalityId</i>). The most recent version available as determined by the
- * highest Major and Minor revision numbers is returned in <i>imageIdPtr</i>.
- *
- * @warning <b>THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart and @ref ixNpeDlCustomImageNpeInitAndStart.
- *
- * @return
- * - IX_SUCCESS if the operation was successful
- * - IX_NPEDL_PARAM_ERR if a parameter error occured
- * - IX_FAIL otherwise
- */
-PUBLIC IX_STATUS
-ixNpeDlLatestImageGet (IxNpeDlNpeId npeId,
- IxNpeDlFunctionalityId functionalityId,
- IxNpeDlImageId *imageIdPtr);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlNpeStopAndReset (IxNpeDlNpeId npeId)
- *
- * @brief Stops and Resets an NPE
- *
- * @param npeId @ref IxNpeDlNpeId [in] - Id of the target NPE.
- *
- * This function performs a soft NPE reset by writing reset values to
- * particular NPE registers. Note that this does not reset NPE co-processors.
- * This implicitly stops NPE code execution before resetting the NPE.
- *
- * @note It is no longer necessary to call this function before downloading
- * a new image to the NPE. It is left on the API only to allow greater control
- * of NPE execution if required. Where appropriate, use @ref ixNpeDlNpeInitAndStart
- * or @ref ixNpeDlCustomImageNpeInitAndStart instead.
- *
- * @warning <b>THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart and @ref ixNpeDlCustomImageNpeInitAndStart.
- *
- * @pre
- * - The Client is responsible for ensuring mutual access to the NPE.
- *
- * @post
- *
- * @return
- * - IX_SUCCESS if the operation was successful
- * - IX_NPEDL_PARAM_ERR if a parameter error occured
- * - IX_FAIL otherwise
- * - IX_NPEDL_CRITICAL_NPE_ERR failed to reset NPE due to timeout error.
- * Timeout error could happen if NPE hang
- */
-PUBLIC IX_STATUS
-ixNpeDlNpeStopAndReset (IxNpeDlNpeId npeId);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlNpeExecutionStart (IxNpeDlNpeId npeId)
- *
- * @brief Starts code execution on a NPE
- *
- * @param npeId @ref IxNpeDlNpeId [in] - Id of the target NPE
- *
- * Starts execution of code on a particular NPE. A client would typically use
- * this after a download to NPE is performed, to start/restart code execution
- * on the NPE.
- *
- * @note It is no longer necessary to call this function after downloading
- * a new image to the NPE. It is left on the API only to allow greater control
- * of NPE execution if required. Where appropriate, use @ref ixNpeDlNpeInitAndStart
- * or @ref ixNpeDlCustomImageNpeInitAndStart instead.
- *
- * @warning <b>THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart and @ref ixNpeDlCustomImageNpeInitAndStart.
- *
- * @pre
- * - The Client is responsible for ensuring mutual access to the NPE.
- * - Note that this function does not set the NPE Next Program Counter
- * (NextPC), so it should be set beforehand if required by downloading
- * appropriate State Information (using ixNpeDlVersionDownload()).
- *
- * @post
- *
- * @return
- * - IX_SUCCESS if the operation was successful
- * - IX_NPEDL_PARAM_ERR if a parameter error occured
- * - IX_FAIL otherwise
- */
-PUBLIC IX_STATUS
-ixNpeDlNpeExecutionStart (IxNpeDlNpeId npeId);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlNpeExecutionStop (IxNpeDlNpeId npeId)
- *
- * @brief Stops code execution on a NPE
- *
- * @param npeId @ref IxNpeDlNpeId [in] - Id of the target NPE
- *
- * Stops execution of code on a particular NPE. This would typically be used
- * by a client before a download to NPE is performed, to stop code execution on
- * an NPE, unless ixNpeDlNpeStopAndReset() is used instead. Unlike
- * ixNpeDlNpeStopAndReset(), this function only halts the NPE and leaves
- * all registers and settings intact. This is useful, for example, between
- * stages of a multi-stage download, to stop the NPE prior to downloading the
- * next image while leaving the current state of the NPE intact..
- *
- * @warning <b>THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart and @ref ixNpeDlCustomImageNpeInitAndStart.
- *
- * @pre
- * - The Client is responsible for ensuring mutual access to the NPE.
- *
- * @post
- *
- * @return
- * - IX_SUCCESS if the operation was successful
- * - IX_NPEDL_PARAM_ERR if a parameter error occured
- * - IX_FAIL otherwise
- */
-PUBLIC IX_STATUS
-ixNpeDlNpeExecutionStop (IxNpeDlNpeId npeId);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlUnload (void)
- *
- * @brief This function will uninitialise the IxNpeDl component.
- *
- * This function will uninitialise the IxNpeDl component. It should only be
- * called once, and only if the IxNpeDl component has already been initialised by
- * calling any of the following functions:
- * - @ref ixNpeDlNpeInitAndStart
- * - @ref ixNpeDlCustomImageNpeInitAndStart
- * - @ref ixNpeDlImageDownload (deprecated)
- * - @ref ixNpeDlNpeStopAndReset (deprecated)
- * - @ref ixNpeDlNpeExecutionStop (deprecated)
- * - @ref ixNpeDlNpeExecutionStart (deprecated)
- *
- * If possible, this function should be called before a soft reboot or unloading
- * a kernel module to perform any clean up operations required for IxNpeDl.
- *
- * The following actions will be performed by this function:
- * - Unmapping of any kernel memory mapped by IxNpeDl
- *
- * @return
- * - IX_SUCCESS if the operation was successful
- * - IX_FAIL otherwise
- */
-
-PUBLIC IX_STATUS
-ixNpeDlUnload (void);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC void ixNpeDlStatsShow (void)
- *
- * @brief This function will display run-time statistics from the IxNpeDl
- * component
- *
- * @return none
- */
-PUBLIC void
-ixNpeDlStatsShow (void);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC void ixNpeDlStatsReset (void)
- *
- * @brief This function will reset the statistics of the IxNpeDl component
- *
- * @return none
- */
-PUBLIC void
-ixNpeDlStatsReset (void);
-
-#endif /* IXNPEDL_H */
-
-/**
- * @} defgroup IxNpeDl
- */
-
-
+++ /dev/null
-/**
- * @file IxNpeDlImageMgr_p.h
- *
- * @author Intel Corporation
- * @date 14 December 2001
-
- * @brief This file contains the private API for the ImageMgr module
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeDlImageMgr_p IxNpeDlImageMgr_p
- *
- * @brief The private API for the IxNpeDl ImageMgr module
- *
- * @{
- */
-
-#ifndef IXNPEDLIMAGEMGR_P_H
-#define IXNPEDLIMAGEMGR_P_H
-
-
-/*
- * Put the user defined include files required.
- */
-#include "IxNpeDl.h"
-#include "IxOsalTypes.h"
-
-
-/*
- * #defines and macros
- */
-
-/**
- * @def IX_NPEDL_IMAGEMGR_SIGNATURE
- *
- * @brief Signature found as 1st word in a microcode image library
- */
-#define IX_NPEDL_IMAGEMGR_SIGNATURE 0xDEADBEEF
-
-/**
- * @def IX_NPEDL_IMAGEMGR_END_OF_HEADER
- *
- * @brief Marks end of header in a microcode image library
- */
-#define IX_NPEDL_IMAGEMGR_END_OF_HEADER 0xFFFFFFFF
-
-/**
- * @def IX_NPEDL_IMAGEID_NPEID_OFFSET
- *
- * @brief Offset from LSB of NPE ID field in Image ID
- */
-#define IX_NPEDL_IMAGEID_NPEID_OFFSET 24
-
-/**
- * @def IX_NPEDL_IMAGEID_DEVICEID_OFFSET
- *
- * @brief Offset from LSB of Device ID field in Image ID
- */
-#define IX_NPEDL_IMAGEID_DEVICEID_OFFSET 28
-
-/**
- * @def IX_NPEDL_IMAGEID_FUNCTIONID_OFFSET
- *
- * @brief Offset from LSB of Functionality ID field in Image ID
- */
-#define IX_NPEDL_IMAGEID_FUNCTIONID_OFFSET 16
-
-/**
- * @def IX_NPEDL_IMAGEID_MAJOR_OFFSET
- *
- * @brief Offset from LSB of Major revision field in Image ID
- */
-#define IX_NPEDL_IMAGEID_MAJOR_OFFSET 8
-
-/**
- * @def IX_NPEDL_IMAGEID_MINOR_OFFSET
- *
- * @brief Offset from LSB of Minor revision field in Image ID
- */
-#define IX_NPEDL_IMAGEID_MINOR_OFFSET 0
-
-
-/**
- * @def IX_NPEDL_NPEID_FROM_IMAGEID_GET
- *
- * @brief Macro to extract NPE ID field from Image ID
- */
-#define IX_NPEDL_NPEID_FROM_IMAGEID_GET(imageId) \
- (((imageId) >> IX_NPEDL_IMAGEID_NPEID_OFFSET) & \
- IX_NPEDL_NPEIMAGE_NPEID_MASK)
-
-/**
- * @def IX_NPEDL_DEVICEID_FROM_IMAGEID_GET
- *
- * @brief Macro to extract NPE ID field from Image ID
- */
-#define IX_NPEDL_DEVICEID_FROM_IMAGEID_GET(imageId) \
- (((imageId) >> IX_NPEDL_IMAGEID_DEVICEID_OFFSET) & \
- IX_NPEDL_NPEIMAGE_DEVICEID_MASK)
-
-/**
- * @def IX_NPEDL_FUNCTIONID_FROM_IMAGEID_GET
- *
- * @brief Macro to extract Functionality ID field from Image ID
- */
-#define IX_NPEDL_FUNCTIONID_FROM_IMAGEID_GET(imageId) \
- (((imageId) >> IX_NPEDL_IMAGEID_FUNCTIONID_OFFSET) & \
- IX_NPEDL_NPEIMAGE_FIELD_MASK)
-
-/**
- * @def IX_NPEDL_MAJOR_FROM_IMAGEID_GET
- *
- * @brief Macro to extract Major revision field from Image ID
- */
-#define IX_NPEDL_MAJOR_FROM_IMAGEID_GET(imageId) \
- (((imageId) >> IX_NPEDL_IMAGEID_MAJOR_OFFSET) & \
- IX_NPEDL_NPEIMAGE_FIELD_MASK)
-
-/**
- * @def IX_NPEDL_MINOR_FROM_IMAGEID_GET
- *
- * @brief Macro to extract Minor revision field from Image ID
- */
-#define IX_NPEDL_MINOR_FROM_IMAGEID_GET(imageId) \
- (((imageId) >> IX_NPEDL_IMAGEID_MINOR_OFFSET) & \
- IX_NPEDL_NPEIMAGE_FIELD_MASK)
-
-
-/*
- * Prototypes for interface functions
- */
-
-/**
- * @fn IX_STATUS ixNpeDlImageMgrMicrocodeImageLibraryOverride (UINT32 *clientImageLibrary)
- *
- * @brief This instructs NPE Downloader to use client-supplied microcode image library.
- *
- * This function sets NPE Downloader to use a client-supplied microcode image library
- * instead of the standard image library which is included by the NPE Downloader.
- *
- * @note THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.
- * It will be removed in a future release.
- * See API header file IxNpeDl.h for more information.
- *
- * @pre
- * - <i>clientImageLibrary</i> should point to a microcode image library valid for use
- * by the NPE Downloader component.
- *
- * @post
- * - the client-supplied image uibrary will be used for all subsequent operations
- * performed by the NPE Downloader
- *
- * @return
- * - IX_SUCCESS if the operation was successful
- * - IX_FAIL if the client-supplied image library did not contain a valid signature
- */
-IX_STATUS
-ixNpeDlImageMgrMicrocodeImageLibraryOverride (UINT32 *clientImageLibrary);
-
-
-/**
- * @fn IX_STATUS ixNpeDlImageMgrImageListExtract (IxNpeDlImageId *imageListPtr,
- UINT32 *numImages)
- *
- * @brief Extracts a list of images available in the NPE microcode image library.
- *
- * @param IxNpeDlImageId* [out] imageListPtr - pointer to array to contain
- * a list of images. If NULL,
- * only the number of images
- * is returned (in
- * <i>numImages</i>)
- * @param UINT32* [inout] numImages - As input, it points to a variable
- * containing the number of images which
- * can be stored in the
- * <i>imageListPtr</i> array. Its value
- * is ignored as input if
- * <i>imageListPtr</i> is NULL. As an
- * output, it will contain number of
- * images in the image library.
- *
- * This function reads the header of the microcode image library and extracts a list of the
- * images available in the image library. It can also be used to find the number of
- * images in the image library.
- *
- * @note THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.
- * It will be removed in a future release.
- * See API header file IxNpeDl.h for more information.
- *
- * @pre
- * - if <i>imageListPtr</i> != NULL, <i>numImages</i> should reflect the
- * number of image Id elements the <i>imageListPtr</i> can contain.
- *
- * @post
- * - <i>numImages</i> will reflect the number of image Id's found in the
- * microcode image library.
- *
- * @return
- * - IX_SUCCESS if the operation was successful
- * - IX_FAIL otherwise
- */
-IX_STATUS
-ixNpeDlImageMgrImageListExtract (IxNpeDlImageId *imageListPtr,
- UINT32 *numImages);
-
-
-/**
- * @fn IX_STATUS ixNpeDlImageMgrImageLocate (IxNpeDlImageId *imageId,
- UINT32 **imagePtr,
- UINT32 *imageSize)
- *
- * @brief Finds a image block in the NPE microcode image library.
- *
- * @param IxNpeDlImageId* [in] imageId - the id of the image to locate
- * @param UINT32** [out] imagePtr - pointer to the image in memory
- * @param UINT32* [out] imageSize - size (in 32-bit words) of image
- *
- * This function examines the header of the microcode image library for the location
- * and size of the specified image.
- *
- * @note THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.
- * It will be removed in a future release.
- * See API header file IxNpeDl.h for more information.
- *
- * @pre
- *
- * @post
- *
- * @return
- * - IX_SUCCESS if the operation was successful
- * - IX_FAIL otherwise
- */
-IX_STATUS
-ixNpeDlImageMgrImageLocate (IxNpeDlImageId *imageId,
- UINT32 **imagePtr,
- UINT32 *imageSize);
-
-/**
- * @fn IX_STATUS ixNpeDlImageMgrLatestImageExtract (IxNpeDlImageId *imageId)
- *
- * @brief Finds the most recent version of an image in the NPE image library.
- *
- * @param IxNpeDlImageId* [inout] imageId - the id of the image
- *
- * This function determines the most recent version of a specified image by its
- * higest major release and minor revision numbers
- *
- * @note THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.
- * It will be removed in a future release.
- * See API header file IxNpeDl.h for more information.
- *
- * @pre
- *
- * @post
- *
- * @return
- * - IX_SUCCESS if the operation was successful
- * - IX_FAIL otherwise
- */
-IX_STATUS
-ixNpeDlImageMgrLatestImageExtract (IxNpeDlImageId *imageId);
-
-/**
- * @fn void ixNpeDlImageMgrStatsShow (void)
- *
- * @brief This function will display the statistics of the IxNpeDl ImageMgr
- * module
- *
- * @return none
- */
-void
-ixNpeDlImageMgrStatsShow (void);
-
-
-/**
- * @fn void ixNpeDlImageMgrStatsReset (void)
- *
- * @brief This function will reset the statistics of the IxNpeDl ImageMgr
- * module
- *
- * @return none
- */
-void
-ixNpeDlImageMgrStatsReset (void);
-
-
-/**
- * @fn IX_STATUS ixNpeDlImageMgrImageGet (UINT32 *imageLibrary,
- UINT32 imageId,
- UINT32 **imagePtr,
- UINT32 *imageSize)
- *
- * @brief Finds a image block in the NPE microcode image library.
- *
- * @param UINT32* [in] imageLibrary - the image library to use
- * @param UINT32 [in] imageId - the id of the image to locate
- * @param UINT32** [out] imagePtr - pointer to the image in memory
- * @param UINT32* [out] imageSize - size (in 32-bit words) of image
- *
- * This function examines the header of the specified microcode image library
- * for the location and size of the specified image. It returns a pointer to
- * the image in the <i>imagePtr</i> parameter.
- * If no image library is specified (imageLibrary == NULL), then the default
- * built-in image library will be used.
- *
- * @pre
- *
- * @post
- *
- * @return
- * - IX_SUCCESS if the operation was successful
- * - IX_FAIL otherwise
- */
-IX_STATUS
-ixNpeDlImageMgrImageFind (UINT32 *imageLibrary,
- UINT32 imageId,
- UINT32 **imagePtr,
- UINT32 *imageSize);
-
-
-#endif /* IXNPEDLIMAGEMGR_P_H */
-
-/**
- * @} defgroup IxNpeDlImageMgr_p
- */
+++ /dev/null
-/**
- * @file IxNpeDlMacros_p.h
- *
- * @author Intel Corporation
- * @date 21 January 2002
- *
- * @brief This file contains the macros for the IxNpeDl component.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeDlMacros_p IxNpeDlMacros_p
- *
- * @brief Macros for the IxNpeDl component.
- *
- * @{
- */
-
-#ifndef IXNPEDLMACROS_P_H
-#define IXNPEDLMACROS_P_H
-
-
-/*
- * Put the user defined include files required.
- */
-#if (CPU != XSCALE)
-/* To support IxNpeDl unit tests... */
-#include <stdio.h>
-#include "test/IxNpeDlTestReg.h"
-
-#else
-#include "IxOsal.h"
-
-#endif
-
-
-/*
- * Typedefs
- */
-
-/**
- * @typedef IxNpeDlTraceTypes
- * @brief Enumeration defining IxNpeDl trace levels
- */
-typedef enum
-{
- IX_NPEDL_TRACE_OFF, /**< no trace */
- IX_NPEDL_DEBUG, /**< debug */
- IX_NPEDL_FN_ENTRY_EXIT /**< function entry/exit */
-} IxNpeDlTraceTypes;
-
-
-/*
- * #defines and macros.
- */
-
-/* Implementation of the following macros for use with IxNpeDl unit test code */
-#if (CPU != XSCALE)
-
-
-/**
- * @def IX_NPEDL_TRACE_LEVEL
- *
- * @brief IxNpeDl debug trace level
- */
-#define IX_NPEDL_TRACE_LEVEL IX_NPEDL_FN_ENTRY_EXIT
-
-/**
- * @def IX_NPEDL_ERROR_REPORT
- *
- * @brief Mechanism for reporting IxNpeDl software errors
- *
- * @param char* [in] STR - Error string to report
- *
- * This macro simply prints the error string passed.
- * Intended for use with IxNpeDl unit test code.
- *
- * @return none
- */
-#define IX_NPEDL_ERROR_REPORT(STR) printf ("IxNpeDl ERROR: %s\n", (STR));
-
-/**
- * @def IX_NPEDL_WARNING_REPORT
- *
- * @brief Mechanism for reporting IxNpeDl software errors
- *
- * @param char* [in] STR - Error string to report
- *
- * This macro simply prints the error string passed.
- * Intended for use with IxNpeDl unit test code.
- *
- * @return none
- */
-#define IX_NPEDL_WARNING_REPORT(STR) printf ("IxNpeDl WARNING: %s\n", (STR));
-
-/**
- * @def IX_NPEDL_TRACE0
- *
- * @brief Mechanism for tracing debug for the IxNpeDl component, for no arguments
- *
- * @param unsigned [in] LEVEL - one of IxNpeDlTraceTypes enumerated values
- * @param char* [in] STR - Trace string
- *
- * This macro simply prints the trace string passed, if the level is supported.
- * Intended for use with IxNpeDl unit test code.
- *
- * @return none
- */
-#define IX_NPEDL_TRACE0(LEVEL, STR) \
-{ \
- if (LEVEL <= IX_NPEDL_TRACE_LEVEL) \
- { \
- printf ("IxNpeDl TRACE: "); \
- printf ((STR)); \
- printf ("\n"); \
- } \
-}
-
- /**
- * @def IX_NPEDL_TRACE1
- *
- * @brief Mechanism for tracing debug for the IxNpeDl component, with 1 argument
- *
- * @param unsigned [in] LEVEL - one of IxNpeDlTraceTypes enumerated values
- * @param char* [in] STR - Trace string
- * @param argType [in] ARG1 - Argument to trace
- *
- * This macro simply prints the trace string passed, if the level is supported.
- * Intended for use with IxNpeDl unit test code.
- *
- * @return none
- */
-#define IX_NPEDL_TRACE1(LEVEL, STR, ARG1) \
-{ \
- if (LEVEL <= IX_NPEDL_TRACE_LEVEL) \
- { \
- printf ("IxNpeDl TRACE: "); \
- printf (STR, ARG1); \
- printf ("\n"); \
- } \
-}
-
-/**
- * @def IX_NPEDL_TRACE2
- *
- * @brief Mechanism for tracing debug for the IxNpeDl component, with 2 arguments
- *
- * @param unsigned [in] LEVEL - one of IxNpeDlTraceTypes enumerated values
- * @param char* [in] STR - Trace string
- * @param argType [in] ARG1 - Argument to trace
- * @param argType [in] ARG2 - Argument to trace
- *
- * This macro simply prints the trace string passed, if the level is supported.
- * Intended for use with IxNpeDl unit test code.
- *
- * @return none
- */
-#define IX_NPEDL_TRACE2(LEVEL, STR, ARG1, ARG2) \
-{ \
- if (LEVEL <= IX_NPEDL_TRACE_LEVEL) \
- { \
- printf ("IxNpeDl TRACE: "); \
- printf (STR, ARG1, ARG2); \
- printf ("\n"); \
- } \
-}
-
-
-/**
- * @def IX_NPEDL_REG_WRITE
- *
- * @brief Mechanism for writing to a memory-mapped register
- *
- * @param UINT32 [in] base - Base memory address for this NPE's registers
- * @param UINT32 [in] offset - Offset from base memory address
- * @param UINT32 [in] value - Value to write to register
- *
- * This macro calls a function from Unit Test code to write a register. This
- * allows extra flexibility for unit testing of the IxNpeDl component.
- *
- * @return none
- */
-#define IX_NPEDL_REG_WRITE(base, offset, value) \
-{ \
- ixNpeDlTestRegWrite (base, offset, value); \
-}
-
-
-/**
- * @def IX_NPEDL_REG_READ
- *
- * @brief Mechanism for reading from a memory-mapped register
- *
- * @param UINT32 [in] base - Base memory address for this NPE's registers
- * @param UINT32 [in] offset - Offset from base memory address
- * @param UINT32 *[out] value - Value read from register
- *
- * This macro calls a function from Unit Test code to read a register. This
- * allows extra flexibility for unit testing of the IxNpeDl component.
- *
- * @return none
- */
-#define IX_NPEDL_REG_READ(base, offset, value) \
-{ \
- ixNpeDlTestRegRead (base, offset, value); \
-}
-
-
-/* Implementation of the following macros when integrated with IxOsal */
-#else /* #if (CPU != XSCALE) */
-
-
-/**
- * @def IX_NPEDL_TRACE_LEVEL
- *
- * @brief IxNpeDl debug trace level
- */
-#define IX_NPEDL_TRACE_LEVEL IX_NPEDL_DEBUG
-
-
-/**
- * @def IX_NPEDL_ERROR_REPORT
- *
- * @brief Mechanism for reporting IxNpeDl software errors
- *
- * @param char* [in] STR - Error string to report
- *
- * This macro is used to report IxNpeDl software errors.
- *
- * @return none
- */
-#define IX_NPEDL_ERROR_REPORT(STR) \
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, STR, 0, 0, 0, 0, 0, 0);
-
-/**
- * @def IX_NPEDL_WARNING_REPORT
- *
- * @brief Mechanism for reporting IxNpeDl software warnings
- *
- * @param char* [in] STR - Warning string to report
- *
- * This macro is used to report IxNpeDl software warnings.
- *
- * @return none
- */
-#define IX_NPEDL_WARNING_REPORT(STR) \
- ixOsalLog (IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT, STR, 0, 0, 0, 0, 0, 0);
-
-
-/**
- * @def IX_NPEDL_TRACE0
- *
- * @brief Mechanism for tracing debug for the IxNpeDl component, for no arguments
- *
- * @param unsigned [in] LEVEL - one of IxNpeDlTraceTypes enumerated values
- * @param char* [in] STR - Trace string
- *
- * This macro simply prints the trace string passed, if the level is supported.
- *
- * @return none
- */
-#define IX_NPEDL_TRACE0(LEVEL, STR) \
-{ \
- if (LEVEL <= IX_NPEDL_TRACE_LEVEL) \
- { \
- if (LEVEL == IX_NPEDL_FN_ENTRY_EXIT) \
- { \
- ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3, IX_OSAL_LOG_DEV_STDOUT, STR, 0, 0, 0, 0, 0, 0); \
- } \
- else if (LEVEL == IX_NPEDL_DEBUG) \
- { \
- ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, STR, 0, 0, 0, 0, 0, 0); \
- } \
- } \
-}
-
-/**
- * @def IX_NPEDL_TRACE1
- *
- * @brief Mechanism for tracing debug for the IxNpeDl component, with 1 argument
- *
- * @param unsigned [in] LEVEL - one of IxNpeDlTraceTypes enumerated values
- * @param char* [in] STR - Trace string
- * @param argType [in] ARG1 - Argument to trace
- *
- * This macro simply prints the trace string passed, if the level is supported.
- *
- * @return none
- */
-#define IX_NPEDL_TRACE1(LEVEL, STR, ARG1) \
-{ \
- if (LEVEL <= IX_NPEDL_TRACE_LEVEL) \
- { \
- if (LEVEL == IX_NPEDL_FN_ENTRY_EXIT) \
- { \
- ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3, IX_OSAL_LOG_DEV_STDOUT, STR, ARG1, 0, 0, 0, 0, 0); \
- } \
- else if (LEVEL == IX_NPEDL_DEBUG) \
- { \
- ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, STR, ARG1, 0, 0, 0, 0, 0); \
- } \
- } \
-}
-
-/**
- * @def IX_NPEDL_TRACE2
- *
- * @brief Mechanism for tracing debug for the IxNpeDl component, with 2 arguments
- *
- * @param unsigned [in] LEVEL - one of IxNpeDlTraceTypes enumerated values
- * @param char* [in] STR - Trace string
- * @param argType [in] ARG1 - Argument to trace
- * @param argType [in] ARG2 - Argument to trace
- *
- * This macro simply prints the trace string passed, if the level is supported.
- *
- * @return none
- */
-#define IX_NPEDL_TRACE2(LEVEL, STR, ARG1, ARG2) \
-{ \
- if (LEVEL <= IX_NPEDL_TRACE_LEVEL) \
- { \
- if (LEVEL == IX_NPEDL_FN_ENTRY_EXIT) \
- { \
- ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3, IX_OSAL_LOG_DEV_STDOUT, STR, ARG1, ARG2, 0, 0, 0, 0); \
- } \
- else if (LEVEL == IX_NPEDL_DEBUG) \
- { \
- ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, STR, ARG1, ARG2, 0, 0, 0, 0); \
- } \
- } \
-}
-
-/**
- * @def IX_NPEDL_REG_WRITE
- *
- * @brief Mechanism for writing to a memory-mapped register
- *
- * @param UINT32 [in] base - Base memory address for this NPE's registers
- * @param UINT32 [in] offset - Offset from base memory address
- * @param UINT32 [in] value - Value to write to register
- *
- * This macro forms the address of the register from base address + offset, and
- * dereferences that address to write the contents of the register.
- *
- * @return none
- */
-#define IX_NPEDL_REG_WRITE(base, offset, value) \
- IX_OSAL_WRITE_LONG(((base) + (offset)), (value))
-
-
-
-/**
- * @def IX_NPEDL_REG_READ
- *
- * @brief Mechanism for reading from a memory-mapped register
- *
- * @param UINT32 [in] base - Base memory address for this NPE's registers
- * @param UINT32 [in] offset - Offset from base memory address
- * @param UINT32 *[out] value - Value read from register
- *
- * This macro forms the address of the register from base address + offset, and
- * dereferences that address to read the register contents.
- *
- * @return none
- */
-#define IX_NPEDL_REG_READ(base, offset, value) \
- *(value) = IX_OSAL_READ_LONG(((base) + (offset)))
-
-#endif /* #if (CPU != XSCALE) */
-
-#endif /* IXNPEDLMACROS_P_H */
-
-/**
- * @} defgroup IxNpeDlMacros_p
- */
+++ /dev/null
-/**
- * @file IxNpeDlNpeMgrEcRegisters_p.h
- *
- * @author Intel Corporation
- * @date 14 December 2001
-
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-
-#ifndef IXNPEDLNPEMGRECREGISTERS_P_H
-#define IXNPEDLNPEMGRECREGISTERS_P_H
-
-#include "IxOsal.h"
-
-/*
- * Base Memory Addresses for accessing NPE registers
- */
-
-#define IX_NPEDL_NPE_BASE (IX_OSAL_IXP400_PERIPHERAL_PHYS_BASE)
-
-#define IX_NPEDL_NPEA_OFFSET (0x6000) /**< NPE-A register base offset */
-#define IX_NPEDL_NPEB_OFFSET (0x7000) /**< NPE-B register base offset */
-#define IX_NPEDL_NPEC_OFFSET (0x8000) /**< NPE-C register base offset */
-
-/**
- * @def IX_NPEDL_NPEBASEADDRESS_NPEA
- * @brief Base Memory Address of NPE-A Configuration Bus registers
- */
-#define IX_NPEDL_NPEBASEADDRESS_NPEA (IX_NPEDL_NPE_BASE + IX_NPEDL_NPEA_OFFSET)
-
-/**
- * @def IX_NPEDL_NPEBASEADDRESS_NPEB
- * @brief Base Memory Address of NPE-B Configuration Bus registers
- */
-#define IX_NPEDL_NPEBASEADDRESS_NPEB (IX_NPEDL_NPE_BASE + IX_NPEDL_NPEB_OFFSET)
-
-/**
- * @def IX_NPEDL_NPEBASEADDRESS_NPEC
- * @brief Base Memory Address of NPE-C Configuration Bus registers
- */
-#define IX_NPEDL_NPEBASEADDRESS_NPEC (IX_NPEDL_NPE_BASE + IX_NPEDL_NPEC_OFFSET)
-
-
-/*
- * Instruction Memory Size (in words) for each NPE
- */
-
-/**
- * @def IX_NPEDL_INS_MEMSIZE_WORDS_NPEA
- * @brief Size (in words) of NPE-A Instruction Memory
- */
-#define IX_NPEDL_INS_MEMSIZE_WORDS_NPEA 4096
-
-/**
- * @def IX_NPEDL_INS_MEMSIZE_WORDS_NPEB
- * @brief Size (in words) of NPE-B Instruction Memory
- */
-#define IX_NPEDL_INS_MEMSIZE_WORDS_NPEB 2048
-
-/**
- * @def IX_NPEDL_INS_MEMSIZE_WORDS_NPEC
- * @brief Size (in words) of NPE-B Instruction Memory
- */
-#define IX_NPEDL_INS_MEMSIZE_WORDS_NPEC 2048
-
-
-/*
- * Data Memory Size (in words) for each NPE
- */
-
-/**
- * @def IX_NPEDL_DATA_MEMSIZE_WORDS_NPEA
- * @brief Size (in words) of NPE-A Data Memory
- */
-#define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEA 2048
-
-/**
- * @def IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB
- * @brief Size (in words) of NPE-B Data Memory
- */
-#define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB 2048
-
-/**
- * @def IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC
- * @brief Size (in words) of NPE-C Data Memory
- */
-#define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC 2048
-
-
-/*
- * Configuration Bus Register offsets (in bytes) from NPE Base Address
- */
-
-/**
- * @def IX_NPEDL_REG_OFFSET_EXAD
- * @brief Offset (in bytes) of EXAD (Execution Address) register from NPE Base
- * Address
- */
-#define IX_NPEDL_REG_OFFSET_EXAD 0x00000000
-
-/**
- * @def IX_NPEDL_REG_OFFSET_EXDATA
- * @brief Offset (in bytes) of EXDATA (Execution Data) register from NPE Base
- * Address
- */
-#define IX_NPEDL_REG_OFFSET_EXDATA 0x00000004
-
-/**
- * @def IX_NPEDL_REG_OFFSET_EXCTL
- * @brief Offset (in bytes) of EXCTL (Execution Control) register from NPE Base
- * Address
- */
-#define IX_NPEDL_REG_OFFSET_EXCTL 0x00000008
-
-/**
- * @def IX_NPEDL_REG_OFFSET_EXCT
- * @brief Offset (in bytes) of EXCT (Execution Count) register from NPE Base
- * Address
- */
-#define IX_NPEDL_REG_OFFSET_EXCT 0x0000000C
-
-/**
- * @def IX_NPEDL_REG_OFFSET_AP0
- * @brief Offset (in bytes) of AP0 (Action Point 0) register from NPE Base
- * Address
- */
-#define IX_NPEDL_REG_OFFSET_AP0 0x00000010
-
-/**
- * @def IX_NPEDL_REG_OFFSET_AP1
- * @brief Offset (in bytes) of AP1 (Action Point 1) register from NPE Base
- * Address
- */
-#define IX_NPEDL_REG_OFFSET_AP1 0x00000014
-
-/**
- * @def IX_NPEDL_REG_OFFSET_AP2
- * @brief Offset (in bytes) of AP2 (Action Point 2) register from NPE Base
- * Address
- */
-#define IX_NPEDL_REG_OFFSET_AP2 0x00000018
-
-/**
- * @def IX_NPEDL_REG_OFFSET_AP3
- * @brief Offset (in bytes) of AP3 (Action Point 3) register from NPE Base
- * Address
- */
-#define IX_NPEDL_REG_OFFSET_AP3 0x0000001C
-
-/**
- * @def IX_NPEDL_REG_OFFSET_WFIFO
- * @brief Offset (in bytes) of WFIFO (Watchpoint FIFO) register from NPE Base
- * Address
- */
-#define IX_NPEDL_REG_OFFSET_WFIFO 0x00000020
-
-/**
- * @def IX_NPEDL_REG_OFFSET_WC
- * @brief Offset (in bytes) of WC (Watch Count) register from NPE Base
- * Address
- */
-#define IX_NPEDL_REG_OFFSET_WC 0x00000024
-
-/**
- * @def IX_NPEDL_REG_OFFSET_PROFCT
- * @brief Offset (in bytes) of PROFCT (Profile Count) register from NPE Base
- * Address
- */
-#define IX_NPEDL_REG_OFFSET_PROFCT 0x00000028
-
-/**
- * @def IX_NPEDL_REG_OFFSET_STAT
- * @brief Offset (in bytes) of STAT (Messaging Status) register from NPE Base
- * Address
- */
-#define IX_NPEDL_REG_OFFSET_STAT 0x0000002C
-
-/**
- * @def IX_NPEDL_REG_OFFSET_CTL
- * @brief Offset (in bytes) of CTL (Messaging Control) register from NPE Base
- * Address
- */
-#define IX_NPEDL_REG_OFFSET_CTL 0x00000030
-
-/**
- * @def IX_NPEDL_REG_OFFSET_MBST
- * @brief Offset (in bytes) of MBST (Mailbox Status) register from NPE Base
- * Address
- */
-#define IX_NPEDL_REG_OFFSET_MBST 0x00000034
-
-/**
- * @def IX_NPEDL_REG_OFFSET_FIFO
- * @brief Offset (in bytes) of FIFO (messaging in/out FIFO) register from NPE
- * Base Address
- */
-#define IX_NPEDL_REG_OFFSET_FIFO 0x00000038
-
-
-/*
- * Non-zero reset values for the Configuration Bus registers
- */
-
-/**
- * @def IX_NPEDL_REG_RESET_FIFO
- * @brief Reset value for Mailbox (MBST) register
- * NOTE that if used, it should be complemented with an NPE intruction
- * to clear the Mailbox at the NPE side as well
- */
-#define IX_NPEDL_REG_RESET_MBST 0x0000F0F0
-
-
-/*
- * Bit-masks used to read/write particular bits in Configuration Bus registers
- */
-
-/**
- * @def IX_NPEDL_MASK_WFIFO_VALID
- * @brief Masks the VALID bit in the WFIFO register
- */
-#define IX_NPEDL_MASK_WFIFO_VALID 0x80000000
-
-/**
- * @def IX_NPEDL_MASK_STAT_OFNE
- * @brief Masks the OFNE bit in the STAT register
- */
-#define IX_NPEDL_MASK_STAT_OFNE 0x00010000
-
-/**
- * @def IX_NPEDL_MASK_STAT_IFNE
- * @brief Masks the IFNE bit in the STAT register
- */
-#define IX_NPEDL_MASK_STAT_IFNE 0x00080000
-
-
-/*
- * EXCTL (Execution Control) Register commands
-*/
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_NPE_STEP
- * @brief EXCTL Command to Step execution of an NPE Instruction
- */
-
-#define IX_NPEDL_EXCTL_CMD_NPE_STEP 0x01
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_NPE_START
- * @brief EXCTL Command to Start NPE execution
- */
-#define IX_NPEDL_EXCTL_CMD_NPE_START 0x02
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_NPE_STOP
- * @brief EXCTL Command to Stop NPE execution
- */
-#define IX_NPEDL_EXCTL_CMD_NPE_STOP 0x03
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE
- * @brief EXCTL Command to Clear NPE instruction pipeline
- */
-#define IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE 0x04
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_RD_INS_MEM
- * @brief EXCTL Command to read NPE instruction memory at address in EXAD
- * register and return value in EXDATA register
- */
-#define IX_NPEDL_EXCTL_CMD_RD_INS_MEM 0x10
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_WR_INS_MEM
- * @brief EXCTL Command to write NPE instruction memory at address in EXAD
- * register with data in EXDATA register
- */
-#define IX_NPEDL_EXCTL_CMD_WR_INS_MEM 0x11
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_RD_DATA_MEM
- * @brief EXCTL Command to read NPE data memory at address in EXAD
- * register and return value in EXDATA register
- */
-#define IX_NPEDL_EXCTL_CMD_RD_DATA_MEM 0x12
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_WR_DATA_MEM
- * @brief EXCTL Command to write NPE data memory at address in EXAD
- * register with data in EXDATA register
- */
-#define IX_NPEDL_EXCTL_CMD_WR_DATA_MEM 0x13
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_RD_ECS_REG
- * @brief EXCTL Command to read Execution Access register at address in EXAD
- * register and return value in EXDATA register
- */
-#define IX_NPEDL_EXCTL_CMD_RD_ECS_REG 0x14
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_WR_ECS_REG
- * @brief EXCTL Command to write Execution Access register at address in EXAD
- * register with data in EXDATA register
- */
-#define IX_NPEDL_EXCTL_CMD_WR_ECS_REG 0x15
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_CLR_PROFILE_CNT
- * @brief EXCTL Command to clear Profile Count register
- */
-#define IX_NPEDL_EXCTL_CMD_CLR_PROFILE_CNT 0x0C
-
-
-/*
- * EXCTL (Execution Control) Register status bit masks
- */
-
-/**
- * @def IX_NPEDL_EXCTL_STATUS_RUN
- * @brief Masks the RUN status bit in the EXCTL register
- */
-#define IX_NPEDL_EXCTL_STATUS_RUN 0x80000000
-
-/**
- * @def IX_NPEDL_EXCTL_STATUS_STOP
- * @brief Masks the STOP status bit in the EXCTL register
- */
-#define IX_NPEDL_EXCTL_STATUS_STOP 0x40000000
-
-/**
- * @def IX_NPEDL_EXCTL_STATUS_CLEAR
- * @brief Masks the CLEAR status bit in the EXCTL register
- */
-#define IX_NPEDL_EXCTL_STATUS_CLEAR 0x20000000
-
-/**
- * @def IX_NPEDL_EXCTL_STATUS_ECS_K
- * @brief Masks the K (pipeline Klean) status bit in the EXCTL register
- */
-#define IX_NPEDL_EXCTL_STATUS_ECS_K 0x00800000
-
-
-/*
- * Executing Context Stack (ECS) level registers
- */
-
-/**
- * @def IX_NPEDL_ECS_BG_CTXT_REG_0
- * @brief Execution Access register address for register 0 at Backgound
- * Executing Context Stack level
- */
-#define IX_NPEDL_ECS_BG_CTXT_REG_0 0x00
-
-/**
- * @def IX_NPEDL_ECS_BG_CTXT_REG_1
- * @brief Execution Access register address for register 1 at Backgound
- * Executing Context Stack level
- */
-#define IX_NPEDL_ECS_BG_CTXT_REG_1 0x01
-
-/**
- * @def IX_NPEDL_ECS_BG_CTXT_REG_2
- * @brief Execution Access register address for register 2 at Backgound
- * Executing Context Stack level
- */
-#define IX_NPEDL_ECS_BG_CTXT_REG_2 0x02
-
-/**
- * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_0
- * @brief Execution Access register address for register 0 at Priority 1
- * Executing Context Stack level
- */
-#define IX_NPEDL_ECS_PRI_1_CTXT_REG_0 0x04
-
-/**
- * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_1
- * @brief Execution Access register address for register 1 at Priority 1
- * Executing Context Stack level
- */
-#define IX_NPEDL_ECS_PRI_1_CTXT_REG_1 0x05
-
-/**
- * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_2
- * @brief Execution Access register address for register 2 at Priority 1
- * Executing Context Stack level
- */
-#define IX_NPEDL_ECS_PRI_1_CTXT_REG_2 0x06
-
-/**
- * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_0
- * @brief Execution Access register address for register 0 at Priority 2
- * Executing Context Stack level
- */
-#define IX_NPEDL_ECS_PRI_2_CTXT_REG_0 0x08
-
-/**
- * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_1
- * @brief Execution Access register address for register 1 at Priority 2
- * Executing Context Stack level
- */
-#define IX_NPEDL_ECS_PRI_2_CTXT_REG_1 0x09
-
-/**
- * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_2
- * @brief Execution Access register address for register 2 at Priority 2
- * Executing Context Stack level
- */
-#define IX_NPEDL_ECS_PRI_2_CTXT_REG_2 0x0A
-
-/**
- * @def IX_NPEDL_ECS_DBG_CTXT_REG_0
- * @brief Execution Access register address for register 0 at Debug
- * Executing Context Stack level
- */
-#define IX_NPEDL_ECS_DBG_CTXT_REG_0 0x0C
-
-/**
- * @def IX_NPEDL_ECS_DBG_CTXT_REG_1
- * @brief Execution Access register address for register 1 at Debug
- * Executing Context Stack level
- */
-#define IX_NPEDL_ECS_DBG_CTXT_REG_1 0x0D
-
-/**
- * @def IX_NPEDL_ECS_DBG_CTXT_REG_2
- * @brief Execution Access register address for register 2 at Debug
- * Executing Context Stack level
- */
-#define IX_NPEDL_ECS_DBG_CTXT_REG_2 0x0E
-
-/**
- * @def IX_NPEDL_ECS_INSTRUCT_REG
- * @brief Execution Access register address for NPE Instruction Register
- */
-#define IX_NPEDL_ECS_INSTRUCT_REG 0x11
-
-
-/*
- * Execution Access register reset values
- */
-
-/**
- * @def IX_NPEDL_ECS_BG_CTXT_REG_0_RESET
- * @brief Reset value for Execution Access Background ECS level register 0
- */
-#define IX_NPEDL_ECS_BG_CTXT_REG_0_RESET 0xA0000000
-
-/**
- * @def IX_NPEDL_ECS_BG_CTXT_REG_1_RESET
- * @brief Reset value for Execution Access Background ECS level register 1
- */
-#define IX_NPEDL_ECS_BG_CTXT_REG_1_RESET 0x01000000
-
-/**
- * @def IX_NPEDL_ECS_BG_CTXT_REG_2_RESET
- * @brief Reset value for Execution Access Background ECS level register 2
- */
-#define IX_NPEDL_ECS_BG_CTXT_REG_2_RESET 0x00008000
-
-/**
- * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_0_RESET
- * @brief Reset value for Execution Access Priority 1 ECS level register 0
- */
-#define IX_NPEDL_ECS_PRI_1_CTXT_REG_0_RESET 0x20000080
-
-/**
- * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_1_RESET
- * @brief Reset value for Execution Access Priority 1 ECS level register 1
- */
-#define IX_NPEDL_ECS_PRI_1_CTXT_REG_1_RESET 0x01000000
-
-/**
- * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_2_RESET
- * @brief Reset value for Execution Access Priority 1 ECS level register 2
- */
-#define IX_NPEDL_ECS_PRI_1_CTXT_REG_2_RESET 0x00008000
-
-/**
- * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_0_RESET
- * @brief Reset value for Execution Access Priority 2 ECS level register 0
- */
-#define IX_NPEDL_ECS_PRI_2_CTXT_REG_0_RESET 0x20000080
-
-/**
- * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_1_RESET
- * @brief Reset value for Execution Access Priority 2 ECS level register 1
- */
-#define IX_NPEDL_ECS_PRI_2_CTXT_REG_1_RESET 0x01000000
-
-/**
- * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_2_RESET
- * @brief Reset value for Execution Access Priority 2 ECS level register 2
- */
-#define IX_NPEDL_ECS_PRI_2_CTXT_REG_2_RESET 0x00008000
-
-/**
- * @def IX_NPEDL_ECS_DBG_CTXT_REG_0_RESET
- * @brief Reset value for Execution Access Debug ECS level register 0
- */
-#define IX_NPEDL_ECS_DBG_CTXT_REG_0_RESET 0x20000000
-
-/**
- * @def IX_NPEDL_ECS_DBG_CTXT_REG_1_RESET
- * @brief Reset value for Execution Access Debug ECS level register 1
- */
-#define IX_NPEDL_ECS_DBG_CTXT_REG_1_RESET 0x00000000
-
-/**
- * @def IX_NPEDL_ECS_DBG_CTXT_REG_2_RESET
- * @brief Reset value for Execution Access Debug ECS level register 2
- */
-#define IX_NPEDL_ECS_DBG_CTXT_REG_2_RESET 0x001E0000
-
-/**
- * @def IX_NPEDL_ECS_INSTRUCT_REG_RESET
- * @brief Reset value for Execution Access NPE Instruction Register
- */
-#define IX_NPEDL_ECS_INSTRUCT_REG_RESET 0x1003C00F
-
-
-/*
- * masks used to read/write particular bits in Execution Access registers
- */
-
-/**
- * @def IX_NPEDL_MASK_ECS_REG_0_ACTIVE
- * @brief Mask the A (Active) bit in Execution Access Register 0 of all ECS
- * levels
- */
-#define IX_NPEDL_MASK_ECS_REG_0_ACTIVE 0x80000000
-
-/**
- * @def IX_NPEDL_MASK_ECS_REG_0_NEXTPC
- * @brief Mask the NextPC bits in Execution Access Register 0 of all ECS
- * levels (except Debug ECS level)
- */
-#define IX_NPEDL_MASK_ECS_REG_0_NEXTPC 0x1FFF0000
-
-/**
- * @def IX_NPEDL_MASK_ECS_REG_0_LDUR
- * @brief Mask the LDUR bits in Execution Access Register 0 of all ECS levels
- */
-#define IX_NPEDL_MASK_ECS_REG_0_LDUR 0x00000700
-
-/**
- * @def IX_NPEDL_MASK_ECS_REG_1_CCTXT
- * @brief Mask the NextPC bits in Execution Access Register 1 of all ECS levels
- */
-#define IX_NPEDL_MASK_ECS_REG_1_CCTXT 0x000F0000
-
-/**
- * @def IX_NPEDL_MASK_ECS_REG_1_SELCTXT
- * @brief Mask the NextPC bits in Execution Access Register 1 of all ECS levels
- */
-#define IX_NPEDL_MASK_ECS_REG_1_SELCTXT 0x0000000F
-
-/**
- * @def IX_NPEDL_MASK_ECS_DBG_REG_2_IF
- * @brief Mask the IF bit in Execution Access Register 2 of Debug ECS level
- */
-#define IX_NPEDL_MASK_ECS_DBG_REG_2_IF 0x00100000
-
-/**
- * @def IX_NPEDL_MASK_ECS_DBG_REG_2_IE
- * @brief Mask the IE bit in Execution Access Register 2 of Debug ECS level
- */
-#define IX_NPEDL_MASK_ECS_DBG_REG_2_IE 0x00080000
-
-
-/*
- * Bit-Offsets from LSB of particular bit-fields in Execution Access registers
- */
-
-/**
- * @def IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC
- * @brief LSB-offset of NextPC field in Execution Access Register 0 of all ECS
- * levels (except Debug ECS level)
- */
-#define IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC 16
-
-/**
- * @def IX_NPEDL_OFFSET_ECS_REG_0_LDUR
- * @brief LSB-offset of LDUR field in Execution Access Register 0 of all ECS
- * levels
- */
-#define IX_NPEDL_OFFSET_ECS_REG_0_LDUR 8
-
-/**
- * @def IX_NPEDL_OFFSET_ECS_REG_1_CCTXT
- * @brief LSB-offset of CCTXT field in Execution Access Register 1 of all ECS
- * levels
- */
-#define IX_NPEDL_OFFSET_ECS_REG_1_CCTXT 16
-
-/**
- * @def IX_NPEDL_OFFSET_ECS_REG_1_SELCTXT
- * @brief LSB-offset of SELCTXT field in Execution Access Register 1 of all ECS
- * levels
- */
-#define IX_NPEDL_OFFSET_ECS_REG_1_SELCTXT 0
-
-
-/*
- * NPE core & co-processor instruction templates to load into NPE Instruction
- * Register, for read/write of NPE register file registers
- */
-
-/**
- * @def IX_NPEDL_INSTR_RD_REG_BYTE
- * @brief NPE Instruction, used to read an 8-bit NPE internal logical register
- * and return the value in the EXDATA register (aligned to MSB).
- * NPE Assembler instruction: "mov8 d0, d0 &&& DBG_WrExec"
- */
-#define IX_NPEDL_INSTR_RD_REG_BYTE 0x0FC00000
-
-/**
- * @def IX_NPEDL_INSTR_RD_REG_SHORT
- * @brief NPE Instruction, used to read a 16-bit NPE internal logical register
- * and return the value in the EXDATA register (aligned to MSB).
- * NPE Assembler instruction: "mov16 d0, d0 &&& DBG_WrExec"
- */
-#define IX_NPEDL_INSTR_RD_REG_SHORT 0x0FC08010
-
-/**
- * @def IX_NPEDL_INSTR_RD_REG_WORD
- * @brief NPE Instruction, used to read a 16-bit NPE internal logical register
- * and return the value in the EXDATA register.
- * NPE Assembler instruction: "mov32 d0, d0 &&& DBG_WrExec"
- */
-#define IX_NPEDL_INSTR_RD_REG_WORD 0x0FC08210
-
-/**
- * @def IX_NPEDL_INSTR_WR_REG_BYTE
- * @brief NPE Immediate-Mode Instruction, used to write an 8-bit NPE internal
- * logical register.
- * NPE Assembler instruction: "mov8 d0, #0"
- */
-#define IX_NPEDL_INSTR_WR_REG_BYTE 0x00004000
-
-/**
- * @def IX_NPEDL_INSTR_WR_REG_SHORT
- * @brief NPE Immediate-Mode Instruction, used to write a 16-bit NPE internal
- * logical register.
- * NPE Assembler instruction: "mov16 d0, #0"
- */
-#define IX_NPEDL_INSTR_WR_REG_SHORT 0x0000C000
-
-/**
- * @def IX_NPEDL_INSTR_RD_FIFO
- * @brief NPE Immediate-Mode Instruction, used to write a 16-bit NPE internal
- * logical register.
- * NPE Assembler instruction: "cprd32 d0 &&& DBG_RdInFIFO"
- */
-#define IX_NPEDL_INSTR_RD_FIFO 0x0F888220
-
-/**
- * @def IX_NPEDL_INSTR_RESET_MBOX
- * @brief NPE Instruction, used to reset Mailbox (MBST) register
- * NPE Assembler instruction: "mov32 d0, d0 &&& DBG_ClearM"
- */
-#define IX_NPEDL_INSTR_RESET_MBOX 0x0FAC8210
-
-
-/*
- * Bit-offsets from LSB, of particular bit-fields in an NPE instruction
- */
-
-/**
- * @def IX_NPEDL_OFFSET_INSTR_SRC
- * @brief LSB-offset to SRC (source operand) field of an NPE Instruction
- */
-#define IX_NPEDL_OFFSET_INSTR_SRC 4
-
-/**
- * @def IX_NPEDL_OFFSET_INSTR_DEST
- * @brief LSB-offset to DEST (destination operand) field of an NPE Instruction
- */
-#define IX_NPEDL_OFFSET_INSTR_DEST 9
-
-/**
- * @def IX_NPEDL_OFFSET_INSTR_COPROC
- * @brief LSB-offset to COPROC (coprocessor instruction) field of an NPE
- * Instruction
- */
-#define IX_NPEDL_OFFSET_INSTR_COPROC 18
-
-
-/*
- * masks used to read/write particular bits of an NPE Instruction
- */
-
-/**
- * @def IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA
- * @brief Mask the bits of 16-bit data value (least-sig 5 bits) to be used in
- * SRC field of immediate-mode NPE instruction
- */
-#define IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA 0x1F
-
-/**
- * @def IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA
- * @brief Mask the bits of 16-bit data value (most-sig 11 bits) to be used in
- * COPROC field of immediate-mode NPE instruction
- */
-#define IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA 0xFFE0
-
-/**
- * @def IX_NPEDL_OFFSET_IMMED_INSTR_COPROC_DATA
- * @brief LSB offset of the bit-field of 16-bit data value (most-sig 11 bits)
- * to be used in COPROC field of immediate-mode NPE instruction
- */
-#define IX_NPEDL_OFFSET_IMMED_INSTR_COPROC_DATA 5
-
-/**
- * @def IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA
- * @brief Number of left-shifts required to align most-sig 11 bits of 16-bit
- * data value into COPROC field of immediate-mode NPE instruction
- */
-#define IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA \
- (IX_NPEDL_OFFSET_INSTR_COPROC - IX_NPEDL_OFFSET_IMMED_INSTR_COPROC_DATA)
-
-/**
- * @def IX_NPEDL_WR_INSTR_LDUR
- * @brief LDUR value used with immediate-mode NPE Instructions by the NpeDl
- * for writing to NPE internal logical registers
- */
-#define IX_NPEDL_WR_INSTR_LDUR 1
-
-/**
- * @def IX_NPEDL_RD_INSTR_LDUR
- * @brief LDUR value used with NON-immediate-mode NPE Instructions by the NpeDl
- * for reading from NPE internal logical registers
- */
-#define IX_NPEDL_RD_INSTR_LDUR 0
-
-
-/**
- * @enum IxNpeDlCtxtRegNum
- * @brief Numeric values to identify the NPE internal Context Store registers
- */
-typedef enum
-{
- IX_NPEDL_CTXT_REG_STEVT = 0, /**< identifies STEVT */
- IX_NPEDL_CTXT_REG_STARTPC, /**< identifies STARTPC */
- IX_NPEDL_CTXT_REG_REGMAP, /**< identifies REGMAP */
- IX_NPEDL_CTXT_REG_CINDEX, /**< identifies CINDEX */
- IX_NPEDL_CTXT_REG_MAX /**< Total number of Context Store registers */
-} IxNpeDlCtxtRegNum;
-
-
-/*
- * NPE Context Store register logical addresses
- */
-
-/**
- * @def IX_NPEDL_CTXT_REG_ADDR_STEVT
- * @brief Logical address of STEVT NPE internal Context Store register
- */
-#define IX_NPEDL_CTXT_REG_ADDR_STEVT 0x0000001B
-
-/**
- * @def IX_NPEDL_CTXT_REG_ADDR_STARTPC
- * @brief Logical address of STARTPC NPE internal Context Store register
- */
-#define IX_NPEDL_CTXT_REG_ADDR_STARTPC 0x0000001C
-
-/**
- * @def IX_NPEDL_CTXT_REG_ADDR_REGMAP
- * @brief Logical address of REGMAP NPE internal Context Store register
- */
-#define IX_NPEDL_CTXT_REG_ADDR_REGMAP 0x0000001E
-
-/**
- * @def IX_NPEDL_CTXT_REG_ADDR_CINDEX
- * @brief Logical address of CINDEX NPE internal Context Store register
- */
-#define IX_NPEDL_CTXT_REG_ADDR_CINDEX 0x0000001F
-
-
-/*
- * NPE Context Store register reset values
- */
-
-/**
- * @def IX_NPEDL_CTXT_REG_RESET_STEVT
- * @brief Reset value of STEVT NPE internal Context Store register
- * (STEVT = off, 0x80)
- */
-#define IX_NPEDL_CTXT_REG_RESET_STEVT 0x80
-
-/**
- * @def IX_NPEDL_CTXT_REG_RESET_STARTPC
- * @brief Reset value of STARTPC NPE internal Context Store register
- * (STARTPC = 0x0000)
- */
-#define IX_NPEDL_CTXT_REG_RESET_STARTPC 0x0000
-
-/**
- * @def IX_NPEDL_CTXT_REG_RESET_REGMAP
- * @brief Reset value of REGMAP NPE internal Context Store register
- * (REGMAP = d0->p0, d8->p2, d16->p4)
- */
-#define IX_NPEDL_CTXT_REG_RESET_REGMAP 0x0820
-
-/**
- * @def IX_NPEDL_CTXT_REG_RESET_CINDEX
- * @brief Reset value of CINDEX NPE internal Context Store register
- * (CINDEX = 0)
- */
-#define IX_NPEDL_CTXT_REG_RESET_CINDEX 0x00
-
-
-/*
- * numeric range of context levels available on an NPE
- */
-
-/**
- * @def IX_NPEDL_CTXT_NUM_MIN
- * @brief Lowest NPE Context number in range
- */
-#define IX_NPEDL_CTXT_NUM_MIN 0
-
-/**
- * @def IX_NPEDL_CTXT_NUM_MAX
- * @brief Highest NPE Context number in range
- */
-#define IX_NPEDL_CTXT_NUM_MAX 15
-
-
-/*
- * Physical NPE internal registers
- */
-
-/**
- * @def IX_NPEDL_TOTAL_NUM_PHYS_REG
- * @brief Number of Physical registers currently supported
- * Initial NPE implementations will have a 32-word register file.
- * Later implementations may have a 64-word register file.
- */
-#define IX_NPEDL_TOTAL_NUM_PHYS_REG 32
-
-/**
- * @def IX_NPEDL_OFFSET_PHYS_REG_ADDR_REGMAP
- * @brief LSB-offset of Regmap number in Physical NPE register address, used
- * for Physical To Logical register address mapping in the NPE
- */
-#define IX_NPEDL_OFFSET_PHYS_REG_ADDR_REGMAP 1
-
-/**
- * @def IX_NPEDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR
- * @brief Mask to extract a logical NPE register address from a physical
- * register address, used for Physical To Logical address mapping
- */
-#define IX_NPEDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR 0x1
-
-#endif /* IXNPEDLNPEMGRECREGISTERS_P_H */
+++ /dev/null
-/**
- * @file IxNpeDlNpeMgrUtils_p.h
- *
- * @author Intel Corporation
- * @date 18 February 2002
- * @brief This file contains the private API for the NpeMgr module.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-
-/**
- * @defgroup IxNpeDlNpeMgrUtils_p IxNpeDlNpeMgrUtils_p
- *
- * @brief The private API for the IxNpeDl NpeMgr Utils module
- *
- * @{
- */
-
-#ifndef IXNPEDLNPEMGRUTILS_P_H
-#define IXNPEDLNPEMGRUTILS_P_H
-
-
-/*
- * Put the user defined include files required.
- */
-#include "IxNpeDl.h"
-#include "IxOsalTypes.h"
-#include "IxNpeDlNpeMgrEcRegisters_p.h"
-
-
-/*
- * Function Prototypes
- */
-
-/**
- * @fn IX_STATUS ixNpeDlNpeMgrInsMemWrite (UINT32 npeBaseAddress,
- UINT32 insMemAddress,
- UINT32 insMemData,
- BOOL verify)
- *
- * @brief Writes a word to NPE Instruction memory
- *
- * @param UINT32 [in] npeBaseAddress - Base Address of NPE
- * @param UINT32 [in] insMemAddress - NPE instruction memory address to write
- * @param UINT32 [in] insMemData - data to write to instruction memory
- * @param BOOL [in] verify - if true, verify the memory location is
- * written successfully.
- *
- * This function is used to write a single word of data to a location in NPE
- * instruction memory. If the <i>verify</i> option is ON, NpeDl will read back
- * from the memory location to verify that it was written successfully
- *
- * @pre
- *
- * @post
- *
- * @return
- * - IX_FAIL if verify is true and the memory location was not written
- * successfully
- * - IX_SUCCESS otherwise
- */
-IX_STATUS
-ixNpeDlNpeMgrInsMemWrite (UINT32 npeBaseAddress, UINT32 insMemAddress,
- UINT32 insMemData, BOOL verify);
-
-
-/**
- * @fn IX_STATUS ixNpeDlNpeMgrDataMemWrite (UINT32 npeBaseAddress,
- UINT32 dataMemAddress,
- UINT32 dataMemData,
- BOOL verify)
- *
- * @brief Writes a word to NPE Data memory
- *
- * @param UINT32 [in] npeBaseAddress - Base Address of NPE
- * @param UINT32 [in] dataMemAddress - NPE data memory address to write
- * @param UINT32 [in] dataMemData - data to write to NPE data memory
- * @param BOOL [in] verify - if true, verify the memory location is
- * written successfully.
- *
- * This function is used to write a single word of data to a location in NPE
- * data memory. If the <i>verify</i> option is ON, NpeDl will read back from
- * the memory location to verify that it was written successfully
- *
- * @pre
- *
- * @post
- *
- * @return
- * - IX_FAIL if verify is true and the memory location was not written
- * successfully
- * - IX_SUCCESS otherwise
- */
-IX_STATUS
-ixNpeDlNpeMgrDataMemWrite (UINT32 npeBaseAddress, UINT32 dataMemAddress,
- UINT32 dataMemData, BOOL verify);
-
-
-/**
- * @fn void ixNpeDlNpeMgrExecAccRegWrite (UINT32 npeBaseAddress,
- UINT32 regAddress,
- UINT32 regData)
- *
- * @brief Writes a word to an NPE Execution Access register
- *
- * @param UINT32 [in] npeBaseAddress - Base Address of NPE
- * @param UINT32 [in] regAddress - NPE Execution Access register address
- * @param UINT32 [in] regData - data to write to register
- *
- * This function is used to write a single word of data to an NPE Execution
- * Access register.
- *
- * @pre
- *
- * @post
- *
- * @return none
- */
-void
-ixNpeDlNpeMgrExecAccRegWrite (UINT32 npeBaseAddress, UINT32 regAddress,
- UINT32 regData);
-
-
-/**
- * @fn UINT32 ixNpeDlNpeMgrExecAccRegRead (UINT32 npeBaseAddress,
- UINT32 regAddress)
- *
- * @brief Reads the contents of an NPE Execution Access register
- *
- * @param UINT32 [in] npeBaseAddress - Base Address of NPE
- * @param UINT32 [in] regAddress - NPE Execution Access register address
- *
- * This function is used to read the contents of an NPE Execution
- * Access register.
- *
- * @pre
- *
- * @post
- *
- * @return The value read from the Execution Access register
- */
-UINT32
-ixNpeDlNpeMgrExecAccRegRead (UINT32 npeBaseAddress, UINT32 regAddress);
-
-
-/**
- * @fn void ixNpeDlNpeMgrCommandIssue (UINT32 npeBaseAddress,
- UINT32 command)
- *
- * @brief Issues an NPE Execution Control command
- *
- * @param UINT32 [in] npeBaseAddress - Base Address of NPE
- * @param UINT32 [in] command - Command to issue
- *
- * This function is used to issue a stand-alone NPE Execution Control command
- * (e.g. command to Stop NPE execution)
- *
- * @pre
- *
- * @post
- *
- * @return none
- */
-void
-ixNpeDlNpeMgrCommandIssue (UINT32 npeBaseAddress, UINT32 command);
-
-
-/**
- * @fn void ixNpeDlNpeMgrDebugInstructionPreExec (UINT32 npeBaseAddress)
- *
- * @brief Prepare to executes one or more NPE instructions in the Debug
- * Execution Stack level.
- *
- * @param UINT32 [in] npeBaseAddress - Base Address of NPE
- *
- * This function should be called once before a sequence of calls to
- * ixNpeDlNpeMgrDebugInstructionExec().
- *
- * @pre
- *
- * @post
- * - ixNpeDlNpeMgrDebugInstructionPostExec() should be called to restore
- * registers values altered by this function
- *
- * @return none
- */
-void
-ixNpeDlNpeMgrDebugInstructionPreExec (UINT32 npeBaseAddress);
-
-
-/**
- * @fn IX_STATUS ixNpeDlNpeMgrDebugInstructionExec (UINT32 npeBaseAddress,
- UINT32 npeInstruction,
- UINT32 ctxtNum,
- UINT32 ldur)
- *
- * @brief Executes a single instruction on the NPE at the Debug Execution Stack
- * level
- *
- * @param UINT32 [in] npeBaseAddress - Base Address of NPE
- * @param UINT32 [in] npeInstruction - Value to write to INSTR (Instruction)
- * register
- * @param UINT32 [in] ctxtNum - context the instruction will be executed
- * in and which context store it may access
- * @param UINT32 [in] ldur - Long Immediate Duration, set to non-zero
- * to use long-immediate mode instruction
- *
- * This function is used to execute a single instruction in the NPE pipeline at
- * the debug Execution Context Stack level. It won't disturb the state of other
- * executing contexts. Its useful for performing NPE operations, such as
- * writing to NPE Context Store registers and physical registers, that cannot
- * be carried out directly using the Configuration Bus registers. This function
- * will return TIMEOUT status if NPE not responding due to NPS is hang / halt.
- *
- * @pre
- * - The NPE should be stopped and in a clean state
- * - ixNpeDlNpeMgrDebugInstructionPreExec() should be called once before
- * a sequential of 1 or more calls to this function
- *
- * @post
- * - ixNpeDlNpeMgrDebugInstructionPostExec() should be called after
- * a sequence of calls to this function
- *
- * @return
- * - IX_NPEDL_CRITICAL_NPE_ERR if execution of instruction failed / timeout
- * - IX_SUCCESS otherwise
- */
-IX_STATUS
-ixNpeDlNpeMgrDebugInstructionExec (UINT32 npeBaseAddress,
- UINT32 npeInstruction,
- UINT32 ctxtNum, UINT32 ldur);
-
-
-/**
- * @fn void ixNpeDlNpeMgrDebugInstructionPostExec (UINT32 npeBaseAddress)
- *
- * @brief Clean up after executing one or more NPE instructions in the
- * Debug Stack Level
- *
- * @param UINT32 [in] npeBaseAddress - Base Address of NPE
- *
- * This function should be called once following a sequence of calls to
- * ixNpeDlNpeMgrDebugInstructionExec().
- *
- * @pre
- * - ixNpeDlNpeMgrDebugInstructionPreExec() was called earlier
- *
- * @post
- * - The Instruction Pipeline will cleared
- *
- * @return none
- */
-void
-ixNpeDlNpeMgrDebugInstructionPostExec (UINT32 npeBaseAddress);
-
-
-/**
- * @fn IX_STATUS ixNpeDlNpeMgrPhysicalRegWrite (UINT32 npeBaseAddress,
- UINT32 regAddr,
- UINT32 regValue,
- BOOL verify)
- *
- * @brief Write one of the 32* 32-bit physical registers in the NPE data
- * register file
- *
- * @param UINT32 [in] npeBaseAddress - Base Address of NPE
- * @param UINT32 [in] regAddr - number of the physical register (0-31)*
- * @param UINT32 [in] regValue - value to write to the physical register
- * @param BOOL [in] verify - if true, verify the register is written
- * successfully.
- *
- * This function writes a physical register in the NPE data register file.
- * If the <i>verify</i> option is ON, NpeDl will read back the register to
- * verify that it was written successfully
- * *Note that release 1.0 of this software supports 32 physical
- * registers, but 64 may be supported in future versions.
- *
- * @pre
- * - The NPE should be stopped and in a clean state
- * - ixNpeDlNpeMgrDebugInstructionPreExec() should be called once before
- * a sequential of 1 or more calls to this function
- *
- * @post
- * - Contents of REGMAP Context Store register for Context 0 will be altered
- * - ixNpeDlNpeMgrDebugInstructionPostExec() should be called after
- * a sequence of calls to this function
- *
- * @return
- * - IX_FAIL if verify is true and the Context Register was not written
- * successfully
- * - IX_SUCCESS if Context Register was written successfully
- * - IX_NPEDL_CRITICAL_NPE_ERR if Context Register was not written
- * successfully due to timeout error where NPE is not responding
- */
-IX_STATUS
-ixNpeDlNpeMgrPhysicalRegWrite (UINT32 npeBaseAddress, UINT32 regAddr,
- UINT32 regValue, BOOL verify);
-
-
-/**
- * @fn IX_STATUS ixNpeDlNpeMgrCtxtRegWrite (UINT32 npeBaseAddress,
- UINT32 ctxtNum,
- IxNpeDlCtxtRegNum ctxtReg,
- UINT32 ctxtRegVal,
- BOOL verify)
- *
- * @brief Writes a value to a Context Store register on an NPE
- *
- * @param UINT32 [in] npeBaseAddress - Base Address of NPE
- * @param UINT32 [in] ctxtNum - context store to access
- * @param IxNpeDlCtxtRegNum [in] ctxtReg - which Context Store reg to write
- * @param UINT32 [in] ctxtRegVal - value to write to the Context Store
- * register
- * @param BOOL [in] verify - if true, verify the register is
- * written successfully.
- *
- * This function writes the contents of a Context Store register in the NPE
- * register file. If the <i>verify</i> option is ON, NpeDl will read back the
- * register to verify that it was written successfully
- *
- * @pre
- * - The NPE should be stopped and in a clean state
- * - ixNpeDlNpeMgrDebugInstructionPreExec() should be called once before
- * a sequential of 1 or more calls to this function
- *
- * @post
- * - ixNpeDlNpeMgrDebugInstructionPostExec() should be called after
- * a sequence of calls to this function
- *
- * @return
- * - IX_FAIL if verify is true and the Context Register was not written
- * successfully
- * - IX_SUCCESS if Context Register was written successfully
- * - IX_NPEDL_CRITICAL_NPE_ERR if Context Register was not written
- * successfully due to timeout error where NPE is not responding
- */
-IX_STATUS
-ixNpeDlNpeMgrCtxtRegWrite (UINT32 npeBaseAddress, UINT32 ctxtNum,
- IxNpeDlCtxtRegNum ctxtReg, UINT32 ctxtRegVal,
- BOOL verify);
-
-
-/**
- * @fn void ixNpeDlNpeMgrUtilsStatsShow (void)
- *
- * @brief This function will display the statistics of the IxNpeDl NpeMgrUtils
- * module
- *
- * @return none
- */
-void
-ixNpeDlNpeMgrUtilsStatsShow (void);
-
-
-/**
- * @fn void ixNpeDlNpeMgrUtilsStatsReset (void)
- *
- * @brief This function will reset the statistics of the IxNpeDl NpeMgrUtils
- * module
- *
- * @return none
- */
-void
-ixNpeDlNpeMgrUtilsStatsReset (void);
-
-
-#endif /* IXNPEDLNPEMGRUTILS_P_H */
+++ /dev/null
-/**
- * @file IxNpeDlNpeMgr_p.h
- *
- * @author Intel Corporation
- * @date 14 December 2001
- * @brief This file contains the private API for the NpeMgr module.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-
-/**
- * @defgroup IxNpeDlNpeMgr_p IxNpeDlNpeMgr_p
- *
- * @brief The private API for the IxNpeDl NpeMgr module
- *
- * @{
- */
-
-#ifndef IXNPEDLNPEMGR_P_H
-#define IXNPEDLNPEMGR_P_H
-
-
-/*
- * Put the user defined include files required.
- */
-#include "IxNpeDl.h"
-#include "IxOsalTypes.h"
-
-
-/*
- * Function Prototypes
- */
-
-
-/**
- * @fn void ixNpeDlNpeMgrInit (void)
- *
- * @brief Initialises the NpeMgr module
- *
- * @param none
- *
- * This function initialises the NpeMgr module.
- * It should be called before any other function in this module is called.
- * It only needs to be called once, but can be called multiple times safely.
- * The code will ASSERT on failure.
- *
- * @pre
- * - It must be called before any other function in this module
- *
- * @post
- * - NPE Configuration Register memory space will be mapped using
- * IxOsal. This memory will not be unmapped by this module.
- *
- * @return none
- */
-void
-ixNpeDlNpeMgrInit (void);
-
-
-/**
- * @fn IX_STATUS ixNpeMhNpeMgrUninit (void)
- *
- * @brief This function will uninitialise the IxNpeDlNpeMgr sub-component.
- *
- * This function will uninitialise the IxNpeDlNpeMgr sub-component.
- * It should only be called once, and only if the IxNpeDlNpeMgr sub-component
- * has already been initialised by calling @ref ixNpeDlNpeMgrInit().
- * No other IxNpeDlNpeMgr sub-component API functions should be called
- * until @ref ixNpeDlNpeMgrInit() is called again.
- * If possible, this function should be called before a soft reboot or unloading
- * a kernel module to perform any clean up operations required for IxNpeMh.
- *
- * @return
- * - IX_SUCCESS if the operation was successful
- * - IX_FAIL otherwise
- */
-
-IX_STATUS ixNpeDlNpeMgrUninit (void);
-
-
-/**
- * @fn IX_STATUS ixNpeDlNpeMgrImageLoad (IxNpeDlNpeId npeId,
- UINT32 *imageCodePtr,
- BOOL verify)
- *
- * @brief Loads a image of microcode onto an NPE
- *
- * @param IxNpeDlNpeId [in] npeId - Id of target NPE
- * @param UINT32* [in] imageCodePtr - pointer to image code in image to be
- * downloaded
- * @param BOOL [in] verify - if true, verify each word written to
- * NPE memory.
- *
- * This function loads a image containing blocks of microcode onto a
- * particular NPE. If the <i>verify</i> option is ON, NpeDl will read back each
- * word written and verify that it was written successfully
- *
- * @pre
- * - The NPE should be stopped beforehand
- *
- * @post
- * - The NPE Instruction Pipeline may be flushed clean
- *
- * @return
- * - IX_SUCCESS if the download was successful
- * - IX_FAIL if the download failed
- * - IX_NPEDL_CRITICAL_NPE_ERR if the download failed due to timeout error
- * where NPE is not responding
- */
-IX_STATUS
-ixNpeDlNpeMgrImageLoad (IxNpeDlNpeId npeId, UINT32 *imageCodePtr,
- BOOL verify);
-
-
-/**
- * @fn IX_STATUS ixNpeDlNpeMgrNpeReset (IxNpeDlNpeId npeId)
- *
- * @brief sets a NPE to RESET state
- *
- * @param IxNpeDlNpeId [in] npeId - id of target NPE
- *
- * This function performs a soft NPE reset by writing reset values to the
- * Configuration Bus Execution Control registers, the Execution Context Stack
- * registers, the Physical Register file, and the Context Store registers for
- * each context number. It also clears inFIFO, outFIFO and Watchpoint FIFO.
- * It does not reset NPE Co-processors.
- *
- * @pre
- * - The NPE should be stopped beforehand
- *
- * @post
- * - NPE NextProgram Counter (NextPC) will be set to a fixed initial value,
- * such as 0. This should be explicitly set by downloading State
- * Information before starting NPE Execution.
- * - The NPE Instruction Pipeline will be in a clean state.
- *
- * @return
- * - IX_SUCCESS if the operation was successful
- * - IX_FAIL if the operation failed
- * - IX_NPEDL_CRITICAL_NPE_ERR if the operation failed due to NPE hang
- */
-IX_STATUS
-ixNpeDlNpeMgrNpeReset (IxNpeDlNpeId npeId);
-
-
-/**
- * @fn IX_STATUS ixNpeDlNpeMgrNpeStart (IxNpeDlNpeId npeId)
- *
- * @brief Starts NPE Execution
- *
- * @param IxNpeDlNpeId [in] npeId - Id of target NPE
- *
- * Ensures only background Execution Stack Level is Active, clears instruction
- * pipeline, and starts Execution on a NPE by sending a Start NPE command to
- * the NPE. Checks the execution status of the NPE to verify that it is
- * running.
- *
- * @pre
- * - The NPE should be stopped beforehand.
- * - Note that this function does not set the NPE Next Program Counter
- * (NextPC), so it should be set beforehand if required by downloading
- * appropriate State Information.
- *
- * @post
- *
- * @return
- * - IX_SUCCESS if the operation was successful
- * - IX_FAIL otherwise
- */
-IX_STATUS
-ixNpeDlNpeMgrNpeStart (IxNpeDlNpeId npeId);
-
-
-/**
- * @fn IX_STATUS ixNpeDlNpeMgrNpeStop (IxNpeDlNpeId npeId)
- *
- * @brief Halts NPE Execution
- *
- * @param IxNpeDlNpeId [in] npeId - id of target NPE
- *
- * Stops execution on an NPE by sending a Stop NPE command to the NPE.
- * Checks the execution status of the NPE to verify that it has stopped.
- *
- * @pre
- *
- * @post
- *
- * @return
- * - IX_SUCCESS if the operation was successful
- * - IX_FAIL otherwise
- */
-IX_STATUS
-ixNpeDlNpeMgrNpeStop (IxNpeDlNpeId npeId);
-
-
-/**
- * @fn void ixNpeDlNpeMgrStatsShow (void)
- *
- * @brief This function will display statistics of the IxNpeDl NpeMgr module
- *
- * @return none
- */
-void
-ixNpeDlNpeMgrStatsShow (void);
-
-
-/**
- * @fn void ixNpeDlNpeMgrStatsReset (void)
- *
- * @brief This function will reset the statistics of the IxNpeDl NpeMgr module
- *
- * @return none
- */
-void
-ixNpeDlNpeMgrStatsReset (void);
-
-
-#endif /* IXNPEDLIMAGEMGR_P_H */
-
-/**
- * @} defgroup IxNpeDlNpeMgr_p
- */
+++ /dev/null
-/**
- * @file IxNpeMh.h
- *
- * @date 14 Dec 2001
- *
- * @brief This file contains the public API for the IXP400 NPE Message
- * Handler component.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeMh IXP400 NPE Message Handler (IxNpeMh) API
- *
- * @brief The public API for the IXP400 NPE Message Handler component.
- *
- * @{
- */
-
-#ifndef IXNPEMH_H
-#define IXNPEMH_H
-
-#include "IxOsalTypes.h"
-
-/*
- * #defines for function return types, etc.
- */
-
-#define IX_NPEMH_MIN_MESSAGE_ID (0x00) /**< minimum valid message ID */
-#define IX_NPEMH_MAX_MESSAGE_ID (0xFF) /**< maximum valid message ID */
-
-#define IX_NPEMH_SEND_RETRIES_DEFAULT (3) /**< default msg send retries */
-
-
-/**
- * @def IX_NPEMH_CRITICAL_NPE_ERR
- *
- * @brief NpeMH function return value for a Critical NPE error occuring during
- sending/receiving message. Assume NPE hang / halt if this value is
- returned.
- */
-#define IX_NPEMH_CRITICAL_NPE_ERR 2
-
-/**
- * @enum IxNpeMhNpeId
- *
- * @brief The ID of a particular NPE.
- * @note In this context, for IXP425 Silicon (B0):<br>
- * - NPE-A has HDLC, HSS, AAL and UTOPIA Coprocessors.<br>
- * - NPE-B has Ethernet Coprocessor.<br>
- * - NPE-C has Ethernet, AES, DES and HASH Coprocessors.<br>
- * - IXP400 Product Line have different combinations of coprocessors.
- */
-
-typedef enum
-{
- IX_NPEMH_NPEID_NPEA = 0, /**< ID for NPE-A */
- IX_NPEMH_NPEID_NPEB, /**< ID for NPE-B */
- IX_NPEMH_NPEID_NPEC, /**< ID for NPE-C */
- IX_NPEMH_NUM_NPES /**< Number of NPEs */
-} IxNpeMhNpeId;
-
-/**
- * @enum IxNpeMhNpeInterrupts
- *
- * @brief Indicator specifying whether or not NPE interrupts should drive
- * receiving of messages from the NPEs.
- */
-
-typedef enum
-{
- IX_NPEMH_NPEINTERRUPTS_NO = 0, /**< Don't use NPE interrupts */
- IX_NPEMH_NPEINTERRUPTS_YES /**< Do use NPE interrupts */
-} IxNpeMhNpeInterrupts;
-
-/**
- * @brief The 2-word message structure to send to and receive from the
- * NPEs.
- */
-
-typedef struct
-{
- UINT32 data[2]; /**< the actual data of the message */
-} IxNpeMhMessage;
-
-/** message ID */
-typedef UINT32 IxNpeMhMessageId;
-
-/**
- * @typedef IxNpeMhCallback
- *
- * @brief This prototype shows the format of a message callback function.
- *
- * This prototype shows the format of a message callback function. The
- * message callback will be passed the message to be handled and will also
- * be told from which NPE the message was received. The message callback
- * will either be registered by ixNpeMhUnsolicitedCallbackRegister() or
- * passed as a parameter to ixNpeMhMessageWithResponseSend(). It will be
- * called from within an ISR triggered by the NPE's "outFIFO not empty"
- * interrupt (see ixNpeMhInitialize()). The parameters passed are the ID
- * of the NPE that the message was received from, and the message to be
- * handled.<P><B>Re-entrancy:</B> This function is only a prototype, and
- * will be implemented by the client. It does not need to be re-entrant.
- */
-
-typedef void (*IxNpeMhCallback) (IxNpeMhNpeId, IxNpeMhMessage);
-
-/*
- * Prototypes for interface functions.
- */
-
-/**
- * @ingroup IxNpeMh
- *
- * @fn IX_STATUS ixNpeMhInitialize (
- IxNpeMhNpeInterrupts npeInterrupts)
- *
- * @brief This function will initialise the IxNpeMh component.
- *
- * @param npeInterrupts @ref IxNpeMhNpeInterrupts [in] - This parameter
- * dictates whether or not the IxNpeMh component will service NPE "outFIFO
- * not empty" interrupts to trigger receiving and processing of messages
- * from the NPEs. If not then the client must use ixNpeMhMessagesReceive()
- * to control message receiving and processing.
- *
- * This function will initialise the IxNpeMh component. It should only be
- * called once, prior to using the IxNpeMh component. The following
- * actions will be performed by this function:<OL><LI>Initialization of
- * internal data structures (e.g. solicited and unsolicited callback
- * tables).</LI><LI>Configuration of the interface with the NPEs (e.g.
- * enabling of NPE "outFIFO not empty" interrupts).</LI><LI>Registration of
- * ISRs that will receive and handle messages when the NPEs' "outFIFO not
- * empty" interrupts fire (if npeInterrupts equals
- * IX_NPEMH_NPEINTERRUPTS_YES).</LI></OL>
- *
- * @return The function returns a status indicating success or failure.
- */
-
-PUBLIC IX_STATUS ixNpeMhInitialize (
- IxNpeMhNpeInterrupts npeInterrupts);
-
-/**
- * @ingroup IxNpeMh
- *
- * @fn IX_STATUS ixNpeMhUnload (void)
- *
- * @brief This function will uninitialise the IxNpeMh component.
- *
- * This function will uninitialise the IxNpeMh component. It should only be
- * called once, and only if the IxNpeMh component has already been initialised.
- * No other IxNpeMh API functions should be called until @ref ixNpeMhInitialize
- * is called again.
- * If possible, this function should be called before a soft reboot or unloading
- * a kernel module to perform any clean up operations required for IxNpeMh.
- *
- * The following actions will be performed by this function:
- * <OL><LI>Unmapping of kernel memory mapped by the function
- * @ref ixNpeMhInitialize.</LI></OL>
- *
- * @return The function returns a status indicating success or failure.
- */
-
-PUBLIC IX_STATUS ixNpeMhUnload (void);
-
-/**
- * @ingroup IxNpeMh
- *
- * @fn IX_STATUS ixNpeMhUnsolicitedCallbackRegister (
- IxNpeMhNpeId npeId,
- IxNpeMhMessageId messageId,
- IxNpeMhCallback unsolicitedCallback)
- *
- * @brief This function will register an unsolicited callback for a
- * particular NPE and message ID.
- *
- * @param npeId @ref IxNpeMhNpeId [in] - The ID of the NPE whose messages
- * the unsolicited callback will handle.
- * @param messageId @ref IxNpeMhMessageId [in] - The ID of the messages the
- * unsolicited callback will handle.
- * @param unsolicitedCallback @ref IxNpeMhCallback [in] - The unsolicited
- * callback function. A value of NULL will deregister any previously
- * registered callback for this NPE and message ID.
- *
- * This function will register an unsolicited message callback for a
- * particular NPE and message ID.<P>If an unsolicited callback is already
- * registered for the specified NPE and message ID then the callback will
- * be overwritten. Only one client will be responsible for handling a
- * particular message ID associated with a NPE. Registering a NULL
- * unsolicited callback will deregister any previously registered
- * callback.<P>The callback function will be called from an ISR that will
- * be triggered by the NPE's "outFIFO not empty" interrupt (see
- * ixNpeMhInitialize()) to handle any unsolicited messages of the specific
- * message ID received from the NPE. Unsolicited messages will be handled
- * in the order they are received.<P>If no unsolicited callback can be
- * found for a received message then it is assumed that the message is
- * solicited.<P>If more than one client may be interested in a particular
- * unsolicited message then the suggested strategy is to register a
- * callback for the message that can itself distribute the message to
- * multiple clients as necessary.<P>See also
- * ixNpeMhUnsolicitedCallbackForRangeRegister().<P><B>Re-entrancy:</B> This
- * function will be callable from any thread at any time. IxOsal
- * will be used for any necessary resource protection.
- *
- * @return The function returns a status indicating success or failure.
- */
-
-PUBLIC IX_STATUS ixNpeMhUnsolicitedCallbackRegister (
- IxNpeMhNpeId npeId,
- IxNpeMhMessageId messageId,
- IxNpeMhCallback unsolicitedCallback);
-
-/**
- * @ingroup IxNpeMh
- *
- * @fn IX_STATUS ixNpeMhUnsolicitedCallbackForRangeRegister (
- IxNpeMhNpeId npeId,
- IxNpeMhMessageId minMessageId,
- IxNpeMhMessageId maxMessageId,
- IxNpeMhCallback unsolicitedCallback)
- *
- * @brief This function will register an unsolicited callback for a
- * particular NPE and range of message IDs.
- *
- * @param npeId @ref IxNpeMhNpeId [in] - The ID of the NPE whose messages the
- * unsolicited callback will handle.
- * @param minMessageId @ref IxNpeMhMessageId [in] - The minimum message ID in
- * the range of message IDs the unsolicited callback will handle.
- * @param maxMessageId @ref IxNpeMhMessageId [in] - The maximum message ID in
- * the range of message IDs the unsolicited callback will handle.
- * @param unsolicitedCallback @ref IxNpeMhCallback [in] - The unsolicited
- * callback function. A value of NULL will deregister any previously
- * registered callback(s) for this NPE and range of message IDs.
- *
- * This function will register an unsolicited callback for a particular NPE
- * and range of message IDs. It is a convenience function that is
- * effectively the same as calling ixNpeMhUnsolicitedCallbackRegister() for
- * each ID in the specified range. See
- * ixNpeMhUnsolicitedCallbackRegister() for more
- * information.<P><B>Re-entrancy:</B> This function will be callable from
- * any thread at any time. IxOsal will be used for any necessary
- * resource protection.
- *
- * @return The function returns a status indicating success or failure.
- */
-
-PUBLIC IX_STATUS ixNpeMhUnsolicitedCallbackForRangeRegister (
- IxNpeMhNpeId npeId,
- IxNpeMhMessageId minMessageId,
- IxNpeMhMessageId maxMessageId,
- IxNpeMhCallback unsolicitedCallback);
-
-/**
- * @ingroup IxNpeMh
- *
- * @fn IX_STATUS ixNpeMhMessageSend (
- IxNpeMhNpeId npeId,
- IxNpeMhMessage message,
- UINT32 maxSendRetries)
- *
- * @brief This function will send a message to a particular NPE.
- *
- * @param npeId @ref IxNpeMhNpeId [in] - The ID of the NPE to send the message
- * to.
- * @param message @ref IxNpeMhMessage [in] - The message to send.
- * @param maxSendRetries UINT32 [in] - Max num. of retries to perform
- * if the NPE's inFIFO is full.
- *
- * This function will send a message to a particular NPE. It will be the
- * client's responsibility to ensure that the message is properly formed.
- * The return status will signify to the client if the message was
- * successfully sent or not.<P>If the message is sent to the NPE then this
- * function will return a status of success. Note that this will only mean
- * the message has been placed in the NPE's inFIFO. There will be no way
- * of knowing that the NPE has actually read the message, but once in the
- * incoming message queue it will be safe to assume that the NPE will
- * process it.
- * <P>The inFIFO may fill up sometimes if the Xscale is sending messages
- * faster than the NPE can handle them. This forces us to retry attempts
- * to send the message until the NPE services the inFIFO. The client should
- * specify a ceiling value for the number of retries suitable to their
- * needs. IX_NPEMH_SEND_RETRIES_DEFAULT can be used as a default value for
- * the <i>maxSendRetries</i> parameter for this function. Each retry
- * exceeding this default number will incur a blocking delay of 1 microsecond,
- * to avoid consuming too much AHB bus bandwidth while performing retries.
- * <P>Note this function <B>must</B> only be used for messages.
- * that do not solicit responses. If the message being sent will solicit a
- * response then the ixNpeMhMessageWithResponseSend() function <B>must</B>
- * be used to ensure that the response is correctly
- * handled. <P> This function will return timeout status if NPE hang / halt
- * while sending message. The timeout error is not related to the
- * <i>maxSendRetries</i> as mentioned above. The timeout error will only occur
- * if the first word of the message has been sent to NPE (not exceeding
- * <i>maxSendRetries</i> when sending 1st message word), but the second word of
- * the message can't be written to NPE's inFIFO due to NPE hang / halt after
- * maximum waiting time (IX_NPE_MH_MAX_NUM_OF_RETRIES).
- * <P><B>Re-entrancy:</B> This function will be callable from any
- * thread at any time. IxOsal will be used for any necessary
- * resource protection.
- *
- * @return The function returns a status indicating success, failure or timeout.
- */
-
-PUBLIC IX_STATUS ixNpeMhMessageSend (
- IxNpeMhNpeId npeId,
- IxNpeMhMessage message,
- UINT32 maxSendRetries);
-
-/**
- * @ingroup IxNpeMh
- *
- * @fn IX_STATUS ixNpeMhMessageWithResponseSend (
- IxNpeMhNpeId npeId,
- IxNpeMhMessage message,
- IxNpeMhMessageId solicitedMessageId,
- IxNpeMhCallback solicitedCallback,
- UINT32 maxSendRetries)
- *
- * @brief This function is equivalent to the ixNpeMhMessageSend() function,
- * but must be used when the message being sent will solicited a response.
- *
- * @param npeId @ref IxNpeMhNpeId [in] - The ID of the NPE to send the message
- * to.
- * @param message @ref IxNpeMhMessage [in] - The message to send.
- * @param solicitedMessageId @ref IxNpeMhMessageId [in] - The ID of the
- * solicited response message.
- * @param solicitedCallback @ref IxNpeMhCallback [in] - The function to use to
- * pass the response message back to the client. A value of NULL will
- * cause the response message to be discarded.
- * @param maxSendRetries UINT32 [in] - Max num. of retries to perform
- * if the NPE's inFIFO is full.
- *
- * This function is equivalent to the ixNpeMhMessageSend() function, but
- * must be used when the message being sent will solicited a
- * response.<P>The client must specify the ID of the solicited response
- * message to allow the response to be recognised when it is received. The
- * client must also specify a callback function to handle the received
- * response. The IxNpeMh component will not offer the facility to send a
- * message to a NPE and receive a response within the same context.<P>Note
- * if the client is not interested in the response, specifying a NULL
- * callback will cause the response message to be discarded.<P>The
- * solicited callback will be stored and called some time later from an ISR
- * that will be triggered by the NPE's "outFIFO not empty" interrupt (see
- * ixNpeMhInitialize()) to handle the response message corresponding to the
- * message sent. Response messages will be handled in the order they are
- * received.<P>
- * <P>The inFIFO may fill up sometimes if the Xscale is sending messages
- * faster than the NPE can handle them. This forces us to retry attempts
- * to send the message until the NPE services the inFIFO. The client should
- * specify a ceiling value for the number of retries suitable to their
- * needs. IX_NPEMH_SEND_RETRIES_DEFAULT can be used as a default value for
- * the <i>maxSendRetries</i> parameter for this function. Each retry
- * exceeding this default number will incur a blocking delay of 1 microsecond,
- * to avoid consuming too much AHB bus bandwidth while performing retries.
- * <P> This function will return timeout status if NPE hang / halt
- * while sending message. The timeout error is not related to the
- * <i>maxSendRetries</i> as mentioned above. The timeout error will only occur
- * if the first word of the message has been sent to NPE (not exceeding
- * <i>maxSendRetries</i> when sending 1st message word), but the second word of
- * the message can't be written to NPE's inFIFO due to NPE hang / halt after
- * maximum waiting time (IX_NPE_MH_MAX_NUM_OF_RETRIES).
- * <P><B>Re-entrancy:</B> This function will be callable from any
- * thread at any time. IxOsal will be used for any necessary
- * resource protection.
- *
- * @return The function returns a status indicating success or failure.
- */
-
-PUBLIC IX_STATUS ixNpeMhMessageWithResponseSend (
- IxNpeMhNpeId npeId,
- IxNpeMhMessage message,
- IxNpeMhMessageId solicitedMessageId,
- IxNpeMhCallback solicitedCallback,
- UINT32 maxSendRetries);
-
-/**
- * @ingroup IxNpeMh
- *
- * @fn IX_STATUS ixNpeMhMessagesReceive (
- IxNpeMhNpeId npeId)
- *
- * @brief This function will receive messages from a particular NPE and
- * pass each message to the client via a solicited callback (for solicited
- * messages) or an unsolicited callback (for unsolicited messages).
- *
- * @param npeId @ref IxNpeMhNpeId [in] - The ID of the NPE to receive and
- * process messages from.
- *
- * This function will receive messages from a particular NPE and pass each
- * message to the client via a solicited callback (for solicited messages)
- * or an unsolicited callback (for unsolicited messages).<P>If the IxNpeMh
- * component is initialised to service NPE "outFIFO not empty" interrupts
- * (see ixNpeMhInitialize()) then there is no need to call this function.
- * This function is only provided as an alternative mechanism to control
- * the receiving and processing of messages from the NPEs.<P> This function
- * will return timeout status if NPE hang / halt while receiving message. The
- * timeout error will only occur if this function has read the first word of
- * the message and can't read second word of the message from NPE's outFIFO
- * after maximum retries (IX_NPE_MH_MAX_NUM_OF_RETRIES).
- * <P>Note this function cannot be called from within
- * an ISR as it will use resource protection mechanisms.<P><B>Re-entrancy:</B>
- * This function will be callable from any thread at any time. IxOsal will be
- * used for any necessary resource protection.
- *
- * @return The function returns a status indicating success, failure or timeout.
- */
-
-PUBLIC IX_STATUS ixNpeMhMessagesReceive (
- IxNpeMhNpeId npeId);
-
-/**
- * @ingroup IxNpeMh
- *
- * @fn IX_STATUS ixNpeMhShow (
- IxNpeMhNpeId npeId)
- *
- * @brief This function will display the current state of the IxNpeMh
- * component.
- *
- * <B>Re-entrancy:</B> This function will be callable from
- * any thread at any time. However, no resource protection will be used
- * so as not to impact system performance. As this function is only
- * reading statistical information then this is acceptable.
- *
- * @param npeId @ref IxNpeMhNpeId [in] - The ID of the NPE to display state
- * information for.
- *
- * @return The function returns a status indicating success or failure.
- */
-
-PUBLIC IX_STATUS ixNpeMhShow (
- IxNpeMhNpeId npeId);
-
-/**
- * @ingroup IxNpeMh
- *
- * @fn IX_STATUS ixNpeMhShowReset (
- IxNpeMhNpeId npeId)
- *
- * @brief This function will reset the current state of the IxNpeMh
- * component.
- *
- * <B>Re-entrancy:</B> This function will be callable from
- * any thread at any time. However, no resource protection will be used
- * so as not to impact system performance. As this function is only
- * writing statistical information then this is acceptable.
- *
- * @param npeId @ref IxNpeMhNpeId [in] - The ID of the NPE to reset state
- * information for.
- *
- * @return The function returns a status indicating success or failure.
- */
-
-PUBLIC IX_STATUS ixNpeMhShowReset (
- IxNpeMhNpeId npeId);
-
-#endif /* IXNPEMH_H */
-
-/**
- * @} defgroup IxNpeMh
- */
+++ /dev/null
-/**
- * @file IxNpeMhConfig_p.h
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the private API for the Configuration module.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeMhConfig_p IxNpeMhConfig_p
- *
- * @brief The private API for the Configuration module.
- *
- * @{
- */
-
-#ifndef IXNPEMHCONFIG_P_H
-#define IXNPEMHCONFIG_P_H
-
-#include "IxOsal.h"
-
-#include "IxNpeMh.h"
-#include "IxNpeMhMacros_p.h"
-
-/*
- * inline definition
- */
-/* enable function inlining for performances */
-#ifdef IXNPEMHSOLICITEDCBMGR_C
-/* Non-inline functions will be defined in this translation unit.
- Reason is that in GNU Compiler, if the Optimization is turn off, all extern inline
- functions will not be compiled.
-*/
-# ifndef __wince
-# ifndef IXNPEMHCONFIG_INLINE
-# define IXNPEMHCONFIG_INLINE
-# endif
-# else
-# ifndef IXNPEMHCONFIG_INLINE
-# define IXNPEMHCONFIG_INLINE IX_OSAL_INLINE_EXTERN
-# endif
-# endif /* __wince*/
-
-#else
-
-# ifndef IXNPEMHCONFIG_INLINE
-# define IXNPEMHCONFIG_INLINE IX_OSAL_INLINE_EXTERN
-# endif /* IXNPEMHCONFIG_INLINE */
-#endif /* IXNPEMHSOLICITEDCBMGR_C */
-/*
- * Typedefs and #defines, etc.
- */
-
-typedef void (*IxNpeMhConfigIsr) (int); /**< ISR function pointer */
-
-/**
- * @struct IxNpeMhConfigNpeInfo
- *
- * @brief This structure is used to maintain the configuration information
- * associated with an NPE.
- */
-
-typedef struct
-{
- IxOsalMutex mutex; /**< mutex */
- UINT32 interruptId; /**< interrupt ID */
- UINT32 virtualRegisterBase; /**< register virtual base address */
- UINT32 statusRegister; /**< status register virtual address */
- UINT32 controlRegister; /**< control register virtual address */
- UINT32 inFifoRegister; /**< inFIFO register virutal address */
- UINT32 outFifoRegister; /**< outFIFO register virtual address */
- IxNpeMhConfigIsr isr; /**< isr routine for handling interrupt */
- BOOL oldInterruptState; /**< old interrupt state (true => enabled) */
-} IxNpeMhConfigNpeInfo;
-
-
-/*
- * #defines for function return types, etc.
- */
-
-/**< NPE register base address */
-#define IX_NPEMH_NPE_BASE (IX_OSAL_IXP400_PERIPHERAL_PHYS_BASE)
-
-#define IX_NPEMH_NPEA_OFFSET (0x6000) /**< NPE-A register base offset */
-#define IX_NPEMH_NPEB_OFFSET (0x7000) /**< NPE-B register base offset */
-#define IX_NPEMH_NPEC_OFFSET (0x8000) /**< NPE-C register base offset */
-
-#define IX_NPEMH_NPESTAT_OFFSET (0x002C) /**< NPE status register offset */
-#define IX_NPEMH_NPECTL_OFFSET (0x0030) /**< NPE control register offset */
-#define IX_NPEMH_NPEFIFO_OFFSET (0x0038) /**< NPE FIFO register offset */
-
-/** NPE-A register base address */
-#define IX_NPEMH_NPEA_BASE (IX_NPEMH_NPE_BASE + IX_NPEMH_NPEA_OFFSET)
-/** NPE-B register base address */
-#define IX_NPEMH_NPEB_BASE (IX_NPEMH_NPE_BASE + IX_NPEMH_NPEB_OFFSET)
-/** NPE-C register base address */
-#define IX_NPEMH_NPEC_BASE (IX_NPEMH_NPE_BASE + IX_NPEMH_NPEC_OFFSET)
-
-/* NPE-A configuration */
-
-/** NPE-A interrupt */
-#define IX_NPEMH_NPEA_INT (IX_OSAL_IXP400_NPEA_IRQ_LVL)
-/** NPE-A FIFO register */
-#define IX_NPEMH_NPEA_FIFO (IX_NPEMH_NPEA_BASE + IX_NPEMH_NPEFIFO_OFFSET)
-/** NPE-A control register */
-#define IX_NPEMH_NPEA_CTL (IX_NPEMH_NPEA_BASE + IX_NPEMH_NPECTL_OFFSET)
-/** NPE-A status register */
-#define IX_NPEMH_NPEA_STAT (IX_NPEMH_NPEA_BASE + IX_NPEMH_NPESTAT_OFFSET)
-
-/* NPE-B configuration */
-
-/** NPE-B interrupt */
-#define IX_NPEMH_NPEB_INT (IX_OSAL_IXP400_NPEB_IRQ_LVL)
-/** NPE-B FIFO register */
-#define IX_NPEMH_NPEB_FIFO (IX_NPEMH_NPEB_BASE + IX_NPEMH_NPEFIFO_OFFSET)
-/** NPE-B control register */
-#define IX_NPEMH_NPEB_CTL (IX_NPEMH_NPEB_BASE + IX_NPEMH_NPECTL_OFFSET)
-/** NPE-B status register */
-#define IX_NPEMH_NPEB_STAT (IX_NPEMH_NPEB_BASE + IX_NPEMH_NPESTAT_OFFSET)
-
-/* NPE-C configuration */
-
-/** NPE-C interrupt */
-#define IX_NPEMH_NPEC_INT (IX_OSAL_IXP400_NPEC_IRQ_LVL)
-/** NPE-C FIFO register */
-#define IX_NPEMH_NPEC_FIFO (IX_NPEMH_NPEC_BASE + IX_NPEMH_NPEFIFO_OFFSET)
-/** NPE-C control register */
-#define IX_NPEMH_NPEC_CTL (IX_NPEMH_NPEC_BASE + IX_NPEMH_NPECTL_OFFSET)
-/** NPE-C status register */
-#define IX_NPEMH_NPEC_STAT (IX_NPEMH_NPEC_BASE + IX_NPEMH_NPESTAT_OFFSET)
-
-/* NPE control register bit definitions */
-#define IX_NPEMH_NPE_CTL_OFE (1 << 16) /**< OutFifoEnable */
-#define IX_NPEMH_NPE_CTL_IFE (1 << 17) /**< InFifoEnable */
-#define IX_NPEMH_NPE_CTL_OFEWE (1 << 24) /**< OutFifoEnableWriteEnable */
-#define IX_NPEMH_NPE_CTL_IFEWE (1 << 25) /**< InFifoEnableWriteEnable */
-
-/* NPE status register bit definitions */
-#define IX_NPEMH_NPE_STAT_OFNE (1 << 16) /**< OutFifoNotEmpty */
-#define IX_NPEMH_NPE_STAT_IFNF (1 << 17) /**< InFifoNotFull */
-#define IX_NPEMH_NPE_STAT_OFNF (1 << 18) /**< OutFifoNotFull */
-#define IX_NPEMH_NPE_STAT_IFNE (1 << 19) /**< InFifoNotEmpty */
-#define IX_NPEMH_NPE_STAT_MBINT (1 << 20) /**< Mailbox interrupt */
-#define IX_NPEMH_NPE_STAT_IFINT (1 << 21) /**< InFifo interrupt */
-#define IX_NPEMH_NPE_STAT_OFINT (1 << 22) /**< OutFifo interrupt */
-#define IX_NPEMH_NPE_STAT_WFINT (1 << 23) /**< WatchFifo interrupt */
-
-
-/**
- * Variable declarations. Externs are followed by static variables.
- */
-extern IxNpeMhConfigNpeInfo ixNpeMhConfigNpeInfo[IX_NPEMH_NUM_NPES];
-
-
-/*
- * Prototypes for interface functions.
- */
-
-/**
- * @fn void ixNpeMhConfigInitialize (
- IxNpeMhNpeInterrupts npeInterrupts)
- *
- * @brief This function initialises the Configuration module.
- *
- * @param IxNpeMhNpeInterrupts npeInterrupts (in) - whether or not to
- * service the NPE "outFIFO not empty" interrupts.
- *
- * @return No return value.
- */
-
-void ixNpeMhConfigInitialize (
- IxNpeMhNpeInterrupts npeInterrupts);
-
-/**
- * @fn void ixNpeMhConfigUninit (void)
- *
- * @brief This function uninitialises the Configuration module.
- *
- * @return No return value.
- */
-
-void ixNpeMhConfigUninit (void);
-
-/**
- * @fn void ixNpeMhConfigIsrRegister (
- IxNpeMhNpeId npeId,
- IxNpeMhConfigIsr isr)
- *
- * @brief This function registers an ISR to handle NPE "outFIFO not
- * empty" interrupts.
- *
- * @param IxNpeMhNpeId npeId (in) - the ID of the NPE whose interrupt will
- * be handled.
- * @param IxNpeMhConfigIsr isr (in) - the ISR function pointer that the
- * interrupt will trigger.
- *
- * @return No return value.
- */
-
-void ixNpeMhConfigIsrRegister (
- IxNpeMhNpeId npeId,
- IxNpeMhConfigIsr isr);
-
-/**
- * @fn BOOL ixNpeMhConfigNpeInterruptEnable (
- IxNpeMhNpeId npeId)
- *
- * @brief This function enables a NPE's "outFIFO not empty" interrupt.
- *
- * @param IxNpeMhNpeId npeId (in) - the ID of the NPE whose interrupt will
- * be enabled.
- *
- * @return Returns the previous state of the interrupt (true => enabled).
- */
-
-BOOL ixNpeMhConfigNpeInterruptEnable (
- IxNpeMhNpeId npeId);
-
-/**
- * @fn BOOL ixNpeMhConfigNpeInterruptDisable (
- IxNpeMhNpeId npeId)
- *
- * @brief This function disables a NPE's "outFIFO not empty" interrupt
- *
- * @param IxNpeMhNpeId npeId (in) - the ID of the NPE whose interrupt will
- * be disabled.
- *
- * @return Returns the previous state of the interrupt (true => enabled).
- */
-
-BOOL ixNpeMhConfigNpeInterruptDisable (
- IxNpeMhNpeId npeId);
-
-/**
- * @fn IxNpeMhMessageId ixNpeMhConfigMessageIdGet (
- IxNpeMhMessage message)
- *
- * @brief This function gets the ID of a message.
- *
- * @param IxNpeMhMessage message (in) - the message to get the ID of.
- *
- * @return the ID of the message
- */
-
-IxNpeMhMessageId ixNpeMhConfigMessageIdGet (
- IxNpeMhMessage message);
-
-/**
- * @fn BOOL ixNpeMhConfigNpeIdIsValid (
- IxNpeMhNpeId npeId)
- *
- * @brief This function checks to see if a NPE ID is valid.
- *
- * @param IxNpeMhNpeId npeId (in) - the NPE ID to validate.
- *
- * @return true if the NPE ID is valid, otherwise false.
- */
-
-BOOL ixNpeMhConfigNpeIdIsValid (
- IxNpeMhNpeId npeId);
-
-/**
- * @fn void ixNpeMhConfigLockGet (
- IxNpeMhNpeId npeId)
- *
- * @brief This function gets a lock for exclusive NPE interaction, and
- * disables the NPE's "outFIFO not empty" interrupt.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which to get the
- * lock and disable its interrupt.
- *
- * @return No return value.
- */
-
-void ixNpeMhConfigLockGet (
- IxNpeMhNpeId npeId);
-
-/**
- * @fn void ixNpeMhConfigLockRelease (
- IxNpeMhNpeId npeId)
- *
- * @brief This function releases a lock for exclusive NPE interaction, and
- * enables the NPE's "outFIFO not empty" interrupt.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which to release
- * the lock and enable its interrupt.
- *
- * @return No return value.
- */
-
-void ixNpeMhConfigLockRelease (
- IxNpeMhNpeId npeId);
-
-/**
- * @fn BOOL ixNpeMhConfigInFifoIsEmpty (
- IxNpeMhNpeId npeId)
- *
- * @brief This inline function checks if a NPE's inFIFO is empty.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the inFIFO
- * will be checked.
- *
- * @return true if the inFIFO is empty, otherwise false.
- */
-
-IXNPEMHCONFIG_INLINE BOOL ixNpeMhConfigInFifoIsEmpty (
- IxNpeMhNpeId npeId);
-
-/**
- * @fn BOOL ixNpeMhConfigInFifoIsFull (
- IxNpeMhNpeId npeId)
- *
- * @brief This inline function checks if a NPE's inFIFO is full.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the inFIFO
- * will be checked.
- *
- * @return true if the inFIFO is full, otherwise false.
- */
-
-IXNPEMHCONFIG_INLINE BOOL ixNpeMhConfigInFifoIsFull (
- IxNpeMhNpeId npeId);
-
-/**
- * @fn BOOL ixNpeMhConfigOutFifoIsEmpty (
- IxNpeMhNpeId npeId)
- *
- * @brief This inline function checks if a NPE's outFIFO is empty.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the outFIFO
- * will be checked.
- *
- * @return true if the outFIFO is empty, otherwise false.
- */
-
-IXNPEMHCONFIG_INLINE BOOL ixNpeMhConfigOutFifoIsEmpty (
- IxNpeMhNpeId npeId);
-
-/**
- * @fn BOOL ixNpeMhConfigOutFifoIsFull (
- IxNpeMhNpeId npeId)
- *
- * @brief This inline function checks if a NPE's outFIFO is full.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the outFIFO
- * will be checked.
- *
- * @return true if the outFIFO is full, otherwise false.
- */
-
-IXNPEMHCONFIG_INLINE BOOL ixNpeMhConfigOutFifoIsFull (
- IxNpeMhNpeId npeId);
-
-/**
- * @fn IX_STATUS ixNpeMhConfigInFifoWrite (
- IxNpeMhNpeId npeId,
- IxNpeMhMessage message)
- *
- * @brief This function writes a message to a NPE's inFIFO. The caller
- * must first check that the NPE's inFifo is not full. After writing the first
- * word of the message, this function will keep polling NPE's inFIFO is not
- * full to write the second word. If inFIFO is not available after maximum
- * retries (IX_NPE_MH_MAX_NUM_OF_RETRIES), this function will return TIMEOUT
- * status to indicate NPE hang / halt.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the inFIFO
- * will be written to.
- * @param IxNpeMhMessage message (in) - The message to write.
- *
- * @return The function returns a status indicating success, failure or timeout.
- */
-
-IX_STATUS ixNpeMhConfigInFifoWrite (
- IxNpeMhNpeId npeId,
- IxNpeMhMessage message);
-
-/**
- * @fn IX_STATUS ixNpeMhConfigOutFifoRead (
- IxNpeMhNpeId npeId,
- IxNpeMhMessage *message)
- *
- * @brief This function reads a message from a NPE's outFIFO. The caller
- * must first check that the NPE's outFifo is not empty. After reading the first
- * word of the message, this function will keep polling NPE's outFIFO is not
- * empty to read the second word. If outFIFO is empty after maximum
- * retries (IX_NPE_MH_MAX_NUM_OF_RETRIES), this function will return TIMEOUT
- * status to indicate NPE hang / halt.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the outFIFO
- * will be read from.
- * @param IxNpeMhMessage message (out) - The message read.
- *
- * @return The function returns a status indicating success, failure or timeout.
- */
-
-IX_STATUS ixNpeMhConfigOutFifoRead (
- IxNpeMhNpeId npeId,
- IxNpeMhMessage *message);
-
-/**
- * @fn void ixNpeMhConfigShow (
- IxNpeMhNpeId npeId)
- *
- * @brief This function will display the current state of the Configuration
- * module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to display state
- * information for.
- *
- * @return No return value.
- */
-
-void ixNpeMhConfigShow (
- IxNpeMhNpeId npeId);
-
-/**
- * @fn void ixNpeMhConfigShowReset (
- IxNpeMhNpeId npeId)
- *
- * @brief This function will reset the current state of the Configuration
- * module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to reset state
- * information for.
- *
- * @return No return value.
- */
-
-void ixNpeMhConfigShowReset (
- IxNpeMhNpeId npeId);
-
-/*
- * Inline functions
- */
-
-/*
- * This inline function checks if a NPE's inFIFO is empty.
- */
-
-IXNPEMHCONFIG_INLINE
-BOOL ixNpeMhConfigInFifoIsEmpty (
- IxNpeMhNpeId npeId)
-{
- UINT32 ifne;
- volatile UINT32 *statusReg =
- (UINT32 *)ixNpeMhConfigNpeInfo[npeId].statusRegister;
-
- /* get the IFNE (InFifoNotEmpty) bit of the status register */
- IX_NPEMH_REGISTER_READ_BITS (statusReg, &ifne, IX_NPEMH_NPE_STAT_IFNE);
-
- /* if the IFNE status bit is unset then the inFIFO is empty */
- return (ifne == 0);
-}
-
-
-/*
- * This inline function checks if a NPE's inFIFO is full.
- */
-IXNPEMHCONFIG_INLINE
-BOOL ixNpeMhConfigInFifoIsFull (
- IxNpeMhNpeId npeId)
-{
- UINT32 ifnf;
- volatile UINT32 *statusReg =
- (UINT32 *)ixNpeMhConfigNpeInfo[npeId].statusRegister;
-
- /* get the IFNF (InFifoNotFull) bit of the status register */
- IX_NPEMH_REGISTER_READ_BITS (statusReg, &ifnf, IX_NPEMH_NPE_STAT_IFNF);
-
- /* if the IFNF status bit is unset then the inFIFO is full */
- return (ifnf == 0);
-}
-
-
-/*
- * This inline function checks if a NPE's outFIFO is empty.
- */
-IXNPEMHCONFIG_INLINE
-BOOL ixNpeMhConfigOutFifoIsEmpty (
- IxNpeMhNpeId npeId)
-{
- UINT32 ofne;
- volatile UINT32 *statusReg =
- (UINT32 *)ixNpeMhConfigNpeInfo[npeId].statusRegister;
-
- /* get the OFNE (OutFifoNotEmpty) bit of the status register */
- IX_NPEMH_REGISTER_READ_BITS (statusReg, &ofne, IX_NPEMH_NPE_STAT_OFNE);
-
- /* if the OFNE status bit is unset then the outFIFO is empty */
- return (ofne == 0);
-}
-
-/*
- * This inline function checks if a NPE's outFIFO is full.
- */
-IXNPEMHCONFIG_INLINE
-BOOL ixNpeMhConfigOutFifoIsFull (
- IxNpeMhNpeId npeId)
-{
- UINT32 ofnf;
- volatile UINT32 *statusReg =
- (UINT32 *)ixNpeMhConfigNpeInfo[npeId].statusRegister;
-
- /* get the OFNF (OutFifoNotFull) bit of the status register */
- IX_NPEMH_REGISTER_READ_BITS (statusReg, &ofnf, IX_NPEMH_NPE_STAT_OFNF);
-
- /* if the OFNF status bit is unset then the outFIFO is full */
- return (ofnf == 0);
-}
-
-#endif /* IXNPEMHCONFIG_P_H */
-
-/**
- * @} defgroup IxNpeMhConfig_p
- */
+++ /dev/null
-/**
- * @file IxNpeMhMacros_p.h
- *
- * @author Intel Corporation
- * @date 21 Jan 2002
- *
- * @brief This file contains the macros for the IxNpeMh component.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeMhMacros_p IxNpeMhMacros_p
- *
- * @brief Macros for the IxNpeMh component.
- *
- * @{
- */
-
-#ifndef IXNPEMHMACROS_P_H
-#define IXNPEMHMACROS_P_H
-
-/* if we are running as a unit test */
-#ifdef IX_UNIT_TEST
-#undef NDEBUG
-#endif /* #ifdef IX_UNIT_TEST */
-
-#include "IxOsal.h"
-
-/*
- * #defines for function return types, etc.
- */
-
-#define IX_NPEMH_SHOW_TEXT_WIDTH (40) /**< text width for stats display */
-#define IX_NPEMH_SHOW_STAT_WIDTH (10) /**< stat width for stats display */
-
-/**
- * @def IX_NPEMH_SHOW
- *
- * @brief Macro for displaying a stat preceded by a textual description.
- */
-
-#define IX_NPEMH_SHOW(TEXT, STAT) \
- ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, \
- "%-40s: %10d\n", (int) TEXT, (int) STAT, 0, 0, 0, 0)
-
-/*
- * Prototypes for interface functions.
- */
-
-/**
- * @typedef IxNpeMhTraceTypes
- *
- * @brief Enumeration defining IxNpeMh trace levels
- */
-
-typedef enum
-{
- IX_NPEMH_TRACE_OFF = IX_OSAL_LOG_LVL_NONE, /**< no trace */
- IX_NPEMH_WARNING = IX_OSAL_LOG_LVL_WARNING, /**< warning */
- IX_NPEMH_DEBUG = IX_OSAL_LOG_LVL_MESSAGE, /**< debug */
- IX_NPEMH_FN_ENTRY_EXIT = IX_OSAL_LOG_LVL_DEBUG3 /**< function entry/exit */
-} IxNpeMhTraceTypes;
-
-#ifdef IX_UNIT_TEST
-#define IX_NPEMH_TRACE_LEVEL (IX_NPEMH_FN_ENTRY_EXIT) /**< trace level */
-#else
-#define IX_NPEMH_TRACE_LEVEL (IX_NPEMH_TRACE_OFF) /**< trace level */
-#endif
-
-/**
- * @def IX_NPEMH_TRACE0
- *
- * @brief Trace macro taking 0 arguments.
- */
-
-#define IX_NPEMH_TRACE0(LEVEL, STR) \
- IX_NPEMH_TRACE6(LEVEL, STR, 0, 0, 0, 0, 0, 0)
-
-/**
- * @def IX_NPEMH_TRACE1
- *
- * @brief Trace macro taking 1 argument.
- */
-
-#define IX_NPEMH_TRACE1(LEVEL, STR, ARG1) \
- IX_NPEMH_TRACE6(LEVEL, STR, ARG1, 0, 0, 0, 0, 0)
-
-/**
- * @def IX_NPEMH_TRACE2
- *
- * @brief Trace macro taking 2 arguments.
- */
-
-#define IX_NPEMH_TRACE2(LEVEL, STR, ARG1, ARG2) \
- IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, 0, 0, 0, 0)
-
-/**
- * @def IX_NPEMH_TRACE3
- *
- * @brief Trace macro taking 3 arguments.
- */
-
-#define IX_NPEMH_TRACE3(LEVEL, STR, ARG1, ARG2, ARG3) \
- IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, 0, 0, 0)
-
-/**
- * @def IX_NPEMH_TRACE4
- *
- * @brief Trace macro taking 4 arguments.
- */
-
-#define IX_NPEMH_TRACE4(LEVEL, STR, ARG1, ARG2, ARG3, ARG4) \
- IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, 0, 0)
-
-/**
- * @def IX_NPEMH_TRACE5
- *
- * @brief Trace macro taking 5 arguments.
- */
-
-#define IX_NPEMH_TRACE5(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, ARG5) \
- IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, ARG5, 0)
-
-/**
- * @def IX_NPEMH_TRACE6
- *
- * @brief Trace macro taking 6 arguments.
- */
-
-#define IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, ARG5, ARG6) \
-{ \
- if (LEVEL <= IX_NPEMH_TRACE_LEVEL) \
- { \
- (void) ixOsalLog (LEVEL, IX_OSAL_LOG_DEV_STDOUT, (STR), \
- (int)(ARG1), (int)(ARG2), (int)(ARG3), \
- (int)(ARG4), (int)(ARG5), (int)(ARG6)); \
- } \
-}
-
-/**
- * @def IX_NPEMH_ERROR_REPORT
- *
- * @brief Error reporting facility.
- */
-
-#define IX_NPEMH_ERROR_REPORT(STR) \
-{ \
- (void) ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, \
- (STR), 0, 0, 0, 0, 0, 0); \
-}
-
-/* if we are running on XScale, i.e. real environment */
-#if CPU==XSCALE
-
-/**
- * @def IX_NPEMH_REGISTER_READ
- *
- * @brief This macro reads a memory-mapped register.
- */
-
-#define IX_NPEMH_REGISTER_READ(registerAddress, value) \
-{ \
- *value = IX_OSAL_READ_LONG(registerAddress); \
-}
-
-/**
- * @def IX_NPEMH_REGISTER_READ_BITS
- *
- * @brief This macro partially reads a memory-mapped register.
- */
-
-#define IX_NPEMH_REGISTER_READ_BITS(registerAddress, value, mask) \
-{ \
- *value = (IX_OSAL_READ_LONG(registerAddress) & mask); \
-}
-
-/**
- * @def IX_NPEMH_REGISTER_WRITE
- *
- * @brief This macro writes a memory-mapped register.
- */
-
-#define IX_NPEMH_REGISTER_WRITE(registerAddress, value) \
-{ \
- IX_OSAL_WRITE_LONG(registerAddress, value); \
-}
-
-/**
- * @def IX_NPEMH_REGISTER_WRITE_BITS
- *
- * @brief This macro partially writes a memory-mapped register.
- */
-
-#define IX_NPEMH_REGISTER_WRITE_BITS(registerAddress, value, mask) \
-{ \
- UINT32 orig = IX_OSAL_READ_LONG(registerAddress); \
- orig &= (~mask); \
- orig |= (value & mask); \
- IX_OSAL_WRITE_LONG(registerAddress, orig); \
-}
-
-
-/* if we are running as a unit test */
-#else /* #if CPU==XSCALE */
-
-#include "IxNpeMhTestRegister.h"
-
-/**
- * @def IX_NPEMH_REGISTER_READ
- *
- * @brief This macro reads a memory-mapped register.
- */
-
-#define IX_NPEMH_REGISTER_READ(registerAddress, value) \
-{ \
- ixNpeMhTestRegisterRead (registerAddress, value); \
-}
-
-/**
- * @def IX_NPEMH_REGISTER_READ_BITS
- *
- * @brief This macro partially reads a memory-mapped register.
- */
-
-#define IX_NPEMH_REGISTER_READ_BITS(registerAddress, value, mask) \
-{ \
- ixNpeMhTestRegisterReadBits (registerAddress, value, mask); \
-}
-
-/**
- * @def IX_NPEMH_REGISTER_WRITE
- *
- * @brief This macro writes a memory-mapped register.
- */
-
-#define IX_NPEMH_REGISTER_WRITE(registerAddress, value) \
-{ \
- ixNpeMhTestRegisterWrite (registerAddress, value); \
-}
-
-/**
- * @def IX_NPEMH_REGISTER_WRITE_BITS
- *
- * @brief This macro partially writes a memory-mapped register.
- */
-
-#define IX_NPEMH_REGISTER_WRITE_BITS(registerAddress, value, mask) \
-{ \
- ixNpeMhTestRegisterWriteBits (registerAddress, value, mask); \
-}
-
-#endif /* #if CPU==XSCALE */
-
-#endif /* IXNPEMHMACROS_P_H */
-
-/**
- * @} defgroup IxNpeMhMacros_p
- */
+++ /dev/null
-/**
- * @file IxNpeMhReceive_p.h
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the private API for the Receive module.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeMhReceive_p IxNpeMhReceive_p
- *
- * @brief The private API for the Receive module.
- *
- * @{
- */
-
-#ifndef IXNPEMHRECEIVE_P_H
-#define IXNPEMHRECEIVE_P_H
-
-#include "IxNpeMh.h"
-#include "IxOsalTypes.h"
-
-/*
- * #defines for function return types, etc.
- */
-
-/*
- * Prototypes for interface functions.
- */
-
-/**
- * @fn void ixNpeMhReceiveInitialize (void)
- *
- * @brief This function registers an internal ISR to handle the NPEs'
- * "outFIFO not empty" interrupts and receive messages from the NPEs when
- * they become available.
- *
- * @return No return value.
- */
-
-void ixNpeMhReceiveInitialize (void);
-
-/**
- * @fn IX_STATUS ixNpeMhReceiveMessagesReceive (
- IxNpeMhNpeId npeId)
- *
- * @brief This function reads messages from a particular NPE's outFIFO
- * until the outFIFO is empty, and for each message looks first for an
- * unsolicited callback, then a solicited callback, to pass the message
- * back to the client. If no callback can be found the message is
- * discarded and an error reported. This function will return TIMEOUT
- * status if NPE hang / halt.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to receive
- * messages from.
- *
- * @return The function returns a status indicating success, failure or timeout.
- */
-
-IX_STATUS ixNpeMhReceiveMessagesReceive (
- IxNpeMhNpeId npeId);
-
-/**
- * @fn void ixNpeMhReceiveShow (
- IxNpeMhNpeId npeId)
- *
- * @brief This function will display the current state of the Receive
- * module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to display state
- * information for.
- *
- * @return No return status.
- */
-
-void ixNpeMhReceiveShow (
- IxNpeMhNpeId npeId);
-
-/**
- * @fn void ixNpeMhReceiveShowReset (
- IxNpeMhNpeId npeId)
- *
- * @brief This function will reset the current state of the Receive
- * module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to reset state
- * information for.
- *
- * @return No return status.
- */
-
-void ixNpeMhReceiveShowReset (
- IxNpeMhNpeId npeId);
-
-#endif /* IXNPEMHRECEIVE_P_H */
-
-/**
- * @} defgroup IxNpeMhReceive_p
- */
+++ /dev/null
-/**
- * @file IxNpeMhSend_p.h
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the private API for the Send module.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeMhSend_p IxNpeMhSend_p
- *
- * @brief The private API for the Send module.
- *
- * @{
- */
-
-#ifndef IXNPEMHSEND_P_H
-#define IXNPEMHSEND_P_H
-
-#include "IxNpeMh.h"
-#include "IxOsalTypes.h"
-
-/*
- * #defines for function return types, etc.
- */
-
-/*
- * Prototypes for interface functions.
- */
-
-/**
- * @fn IX_STATUS ixNpeMhSendMessageSend (
- IxNpeMhNpeId npeId,
- IxNpeMhMessage message,
- UINT32 maxSendRetries)
- *
- * @brief This function writes a message to the specified NPE's inFIFO,
- * and must be used when the message being sent does not solicit a response
- * from the NPE. This function will return TIMEOUT status if NPE hang / halt.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to send the message
- * to.
- * @param IxNpeMhMessage message (in) - The message to send.
- * @param UINT32 maxSendRetries (in) - Max num. of retries to perform
- * if the NPE's inFIFO is full.
- *
- * @return The function returns a status indicating success, failure or timeout.
- */
-
-IX_STATUS ixNpeMhSendMessageSend (
- IxNpeMhNpeId npeId,
- IxNpeMhMessage message,
- UINT32 maxSendRetries);
-
-/**
- * @fn IX_STATUS ixNpeMhSendMessageWithResponseSend (
- IxNpeMhNpeId npeId,
- IxNpeMhMessage message,
- IxNpeMhMessageId solicitedMessageId,
- IxNpeMhCallback solicitedCallback,
- UINT32 maxSendRetries)
- *
- * @brief This function writes a message to the specified NPE's inFIFO,
- * and must be used when the message being sent solicits a response from
- * the NPE. The ID of the solicited response must be specified so that it
- * can be recognised, and a callback provided to pass the response back to
- * the client. This function will return TIMEOUT status if NPE hang / halt.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to send the message
- * to.
- * @param IxNpeMhMessage message (in) - The message to send.
- * @param IxNpeMhMessageId solicitedMessageId (in) - The ID of the
- * solicited response.
- * @param IxNpeMhCallback solicitedCallback (in) - The callback to pass the
- * solicited response back to the client.
- * @param UINT32 maxSendRetries (in) - Max num. of retries to perform
- * if the NPE's inFIFO is full.
- *
- * @return The function returns a status indicating success, failure or timeout.
- */
-
-IX_STATUS ixNpeMhSendMessageWithResponseSend (
- IxNpeMhNpeId npeId,
- IxNpeMhMessage message,
- IxNpeMhMessageId solicitedMessageId,
- IxNpeMhCallback solicitedCallback,
- UINT32 maxSendRetries);
-
-/**
- * @fn void ixNpeMhSendShow (
- IxNpeMhNpeId npeId)
- *
- * @brief This function will display the current state of the Send module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to display state
- * information for.
- *
- * @return No return value.
- */
-
-void ixNpeMhSendShow (
- IxNpeMhNpeId npeId);
-
-/**
- * @fn void ixNpeMhSendShowReset (
- IxNpeMhNpeId npeId)
- *
- * @brief This function will reset the current state of the Send module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to reset state
- * information for.
- *
- * @return No return value.
- */
-
-void ixNpeMhSendShowReset (
- IxNpeMhNpeId npeId);
-
-#endif /* IXNPEMHSEND_P_H */
-
-/**
- * @} defgroup IxNpeMhSend_p
- */
+++ /dev/null
-/**
- * @file IxNpeMhSolicitedCbMgr_p.h
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the private API for the Solicited Callback
- * Manager module.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeMhSolicitedCbMgr_p IxNpeMhSolicitedCbMgr_p
- *
- * @brief The private API for the Solicited Callback Manager module.
- *
- * @{
- */
-
-#ifndef IXNPEMHSOLICITEDCBMGR_P_H
-#define IXNPEMHSOLICITEDCBMGR_P_H
-
-#include "IxNpeMh.h"
-#include "IxOsalTypes.h"
-
-/*
- * #defines for function return types, etc.
- */
-
-/** Maximum number of solicited callbacks that can be stored in the list */
-#define IX_NPEMH_MAX_CALLBACKS (16)
-
-/*
- * Prototypes for interface functions.
- */
-
-/**
- * @fn void ixNpeMhSolicitedCbMgrInitialize (void)
- *
- * @brief This function initializes the Solicited Callback Manager module,
- * setting up a callback data structure for each NPE.
- *
- * @return No return value.
- */
-
-void ixNpeMhSolicitedCbMgrInitialize (void);
-
-/**
- * @fn IX_STATUS ixNpeMhSolicitedCbMgrCallbackSave (
- IxNpeMhNpeId npeId,
- IxNpeMhMessageId solicitedMessageId,
- IxNpeMhCallback solicitedCallback)
- *
- * @brief This function saves a callback in the specified NPE's callback
- * list. If the callback list is full the function will fail.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE in whose callback
- * list the callback will be saved.
- * @param IxNpeMhMessageId solicitedMessageId (in) - The ID of the message
- * that this callback is for.
- * @param IxNpeMhCallback solicitedCallback (in) - The callback function
- * pointer to save.
- *
- * @return The function returns a status indicating success or failure.
- */
-
-IX_STATUS ixNpeMhSolicitedCbMgrCallbackSave (
- IxNpeMhNpeId npeId,
- IxNpeMhMessageId solicitedMessageId,
- IxNpeMhCallback solicitedCallback);
-
-/**
- * @fn void ixNpeMhSolicitedCbMgrCallbackRetrieve (
- IxNpeMhNpeId npeId,
- IxNpeMhMessageId solicitedMessageId,
- IxNpeMhCallback *solicitedCallback)
- *
- * @brief This function retrieves the first ID-matching callback from the
- * specified NPE's callback list. If no matching callback can be found the
- * function will fail.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE from whose callback
- * list the callback will be retrieved.
- * @param IxNpeMhMessageId solicitedMessageId (in) - The ID of the message
- * that the callback is for.
- * @param IxNpeMhCallback solicitedCallback (out) - The callback function
- * pointer retrieved.
- *
- * @return No return value.
- */
-
-void ixNpeMhSolicitedCbMgrCallbackRetrieve (
- IxNpeMhNpeId npeId,
- IxNpeMhMessageId solicitedMessageId,
- IxNpeMhCallback *solicitedCallback);
-
-/**
- * @fn void ixNpeMhSolicitedCbMgrShow (
- IxNpeMhNpeId npeId)
- *
- * @brief This function will display the current state of the Solicited
- * Callback Manager module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to display state
- * information for.
- *
- * @return No return value.
- */
-
-void ixNpeMhSolicitedCbMgrShow (
- IxNpeMhNpeId npeId);
-
-/**
- * @fn void ixNpeMhSolicitedCbMgrShowReset (
- IxNpeMhNpeId npeId)
- *
- * @brief This function will reset the current state of the Solicited
- * Callback Manager module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to reset state
- * information for.
- *
- * @return No return value.
- */
-
-void ixNpeMhSolicitedCbMgrShowReset (
- IxNpeMhNpeId npeId);
-
-#endif /* IXNPEMHSOLICITEDCBMGR_P_H */
-
-/**
- * @} defgroup IxNpeMhSolicitedCbMgr_p
- */
+++ /dev/null
-/**
- * @file IxNpeMhUnsolicitedCbMgr_p.h
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the private API for the Unsolicited Callback
- * Manager module.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxNpeMhUnsolicitedCbMgr_p IxNpeMhUnsolicitedCbMgr_p
- *
- * @brief The private API for the Unsolicited Callback Manager module.
- *
- * @{
- */
-
-#ifndef IXNPEMHUNSOLICITEDCBMGR_P_H
-#define IXNPEMHUNSOLICITEDCBMGR_P_H
-
-#include "IxNpeMh.h"
-#include "IxOsalTypes.h"
-
-/*
- * #defines for function return types, etc.
- */
-
-/*
- * Prototypes for interface functions.
- */
-
-/**
- * @fn void ixNpeMhUnsolicitedCbMgrInitialize (void)
- *
- * @brief This function initializes the Unsolicited Callback Manager
- * module, setting up a callback data structure for each NPE.
- *
- * @return No return value.
- */
-
-void ixNpeMhUnsolicitedCbMgrInitialize (void);
-
-/**
- * @fn void ixNpeMhUnsolicitedCbMgrCallbackSave (
- IxNpeMhNpeId npeId,
- IxNpeMhMessageId unsolicitedMessageId,
- IxNpeMhCallback unsolicitedCallback)
- *
- * @brief This function saves a callback in the specified NPE's callback
- * table. If a callback already exists for the specified ID then it will
- * be overwritten.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE in whose callback
- * table the callback will be saved.
- * @param IxNpeMhMessageId unsolicitedMessageId (in) - The ID of the
- * messages that this callback is for.
- * @param IxNpeMhCallback unsolicitedCallback (in) - The callback function
- * pointer to save.
- *
- * @return No return value.
- */
-
-void ixNpeMhUnsolicitedCbMgrCallbackSave (
- IxNpeMhNpeId npeId,
- IxNpeMhMessageId unsolicitedMessageId,
- IxNpeMhCallback unsolicitedCallback);
-
-/**
- * @fn void ixNpeMhUnsolicitedCbMgrCallbackRetrieve (
- IxNpeMhNpeId npeId,
- IxNpeMhMessageId unsolicitedMessageId,
- IxNpeMhCallback *unsolicitedCallback)
- *
- * @brief This function retrieves the callback for the specified ID from
- * the specified NPE's callback table. If no callback is registered for
- * the specified ID and NPE then a callback value of NULL will be returned.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE from whose callback
- * table the callback will be retrieved.
- * @param IxNpeMhMessageId unsolicitedMessageId (in) - The ID of the
- * messages that the callback is for.
- * @param IxNpeMhCallback unsolicitedCallback (out) - The callback function
- * pointer retrieved.
- *
- * @return No return value.
- */
-
-void ixNpeMhUnsolicitedCbMgrCallbackRetrieve (
- IxNpeMhNpeId npeId,
- IxNpeMhMessageId unsolicitedMessageId,
- IxNpeMhCallback *unsolicitedCallback);
-
-/**
- * @fn void ixNpeMhUnsolicitedCbMgrShow (
- IxNpeMhNpeId npeId)
- *
- * @brief This function will display the current state of the Unsolicited
- * Callback Manager module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to display state
- * information for.
- *
- * @return No return value.
- */
-
-void ixNpeMhUnsolicitedCbMgrShow (
- IxNpeMhNpeId npeId);
-
-/**
- * @fn void ixNpeMhUnsolicitedCbMgrShowReset (
- IxNpeMhNpeId npeId)
- *
- * @brief This function will reset the current state of the Unsolicited
- * Callback Manager module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to reset state
- * information for.
- *
- * @return No return value.
- */
-
-void ixNpeMhUnsolicitedCbMgrShowReset (
- IxNpeMhNpeId npeId);
-
-#endif /* IXNPEMHUNSOLICITEDCBMGR_P_H */
-
-/**
- * @} defgroup IxNpeMhUnsolicitedCbMgr_p
- */
+++ /dev/null
-/**
- * @date April 18, 2005
- *
- * @brief IXP400 NPE Microcode Image file
- *
- * This file was generated by the IxNpeDlImageGen tool.
- * It contains a NPE microcode image suitable for use
- * with the NPE Downloader (IxNpeDl) component in the
- * IXP400 Access Driver software library.
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeMicrocode IXP400 NPE Microcode Image Library
- *
- * @brief Library containing a set of NPE firmware images, for use
- * with NPE Downloader s/w component
- *
- * @{
- */
-
-/**
- * @def IX_NPE_IMAGE_INCLUDE
- *
- * @brief Wrap the following Image identifiers with "#if IX_NPE_IMAGE_INCLUDE ... #endif" to include the image in the library
- */
-#define IX_NPE_IMAGE_INCLUDE 1
-
-/**
- * @def IX_NPE_IMAGE_OMIT
- *
- * @brief Wrap the following Image identifiers with "#if IX_NPE_IMAGE_OMIT ... #endif" to OMIT the image from the library
- */
-#define IX_NPE_IMAGE_OMIT 0
-
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_HSS0
- *
- * @brief NPE Image Id for NPE-A with HSS-0 Only feature. It supports 32 channelized and 4 packetized.
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_HSS0 0x00010000
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_HSS0_ATM_SPHY_1_PORT
- *
- * @brief NPE Image Id for NPE-A with HSS-0 and ATM feature. For HSS, it supports 16/32 channelized and 4/0 packetized. For ATM, it supports AAL5, AAL0 and OAM for UTOPIA SPHY, 1 logical port, 32 VCs. It also has Fast Path support.
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_HSS0_ATM_SPHY_1_PORT 0x00020000
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_HSS0_ATM_MPHY_1_PORT
- *
- * @brief NPE Image Id for NPE-A with HSS-0 and ATM feature. For HSS, it supports 16/32 channelized and 4/0 packetized. For ATM, it supports AAL5, AAL0 and OAM for UTOPIA MPHY, 1 logical port, 32 VCs. It also has Fast Path support.
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_HSS0_ATM_MPHY_1_PORT 0x00030000
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_ATM_MPHY_12_PORT
- *
- * @brief NPE Image Id for NPE-A with ATM-Only feature. It supports AAL5, AAL0 and OAM for UTOPIA MPHY, 12 logical ports, 32 VCs. It also has Fast Path support.
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_ATM_MPHY_12_PORT 0x00040000
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_DMA
- *
- * @brief NPE Image Id for NPE-A with DMA-Only feature.
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_DMA 0x00150100
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_HSS_2_PORT
- *
- * @brief NPE Image Id for NPE-A with HSS-0 and HSS-1 feature. Each HSS port supports 32 channelized and 4 packetized.
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_HSS_2_PORT 0x00090000
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_ETH
- *
- * @brief NPE Image Id for NPE-A with Basic Ethernet Rx/Tx which includes: MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_ETH 0x10800200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_FIREWALL
- *
- * @brief NPE Image Id for NPE-A with Basic Ethernet Rx/Tx which includes: MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_FIREWALL 0x10800200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS
- *
- * @brief NPE Image Id for NPE-A with Ethernet Rx/Tx which includes: MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL, VLAN_QOS
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS 0x10810200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
- *
- * @brief NPE Image Id for NPE-A with Ethernet Rx/Tx which includes: SPANNING_TREE, FIREWALL, VLAN_QOS, HEADER_CONVERSION
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV 0x10820200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEB_ETH
- *
- * @brief NPE Image Id for NPE-B with Basic Ethernet Rx/Tx which includes: MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL
- */
-#define IX_NPEDL_NPEIMAGE_NPEB_ETH 0x01000200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL
- *
- * @brief NPE Image Id for NPE-B with Basic Ethernet Rx/Tx which includes: MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL
- */
-#define IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL 0x01000200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS
- *
- * @brief NPE Image Id for NPE-B with Ethernet Rx/Tx which includes: MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL, VLAN_QOS
- */
-#define IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS 0x01010200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEB_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
- *
- * @brief NPE Image Id for NPE-B with Ethernet Rx/Tx which includes: SPANNING_TREE, FIREWALL, VLAN_QOS, HEADER_CONVERSION
- */
-#define IX_NPEDL_NPEIMAGE_NPEB_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV 0x01020200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEB_DMA
- *
- * @brief NPE Image Id for NPE-B with DMA-Only feature.
- */
-#define IX_NPEDL_NPEIMAGE_NPEB_DMA 0x01020100
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEC_ETH
- *
- * @brief NPE Image Id for NPE-C with Basic Ethernet Rx/Tx which includes: MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL
- */
-#define IX_NPEDL_NPEIMAGE_NPEC_ETH 0x02000200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL
- *
- * @brief NPE Image Id for NPE-C with Basic Ethernet Rx/Tx which includes: MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL
- */
-#define IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL 0x02000200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS
- *
- * @brief NPE Image Id for NPE-C with Ethernet Rx/Tx which includes: MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL, VLAN_QOS
- */
-#define IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS 0x02010200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEC_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
- *
- * @brief NPE Image Id for NPE-C with Ethernet Rx/Tx which includes: SPANNING_TREE, FIREWALL, VLAN_QOS, HEADER_CONVERSION
- */
-#define IX_NPEDL_NPEIMAGE_NPEC_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV 0x02020200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEC_DMA
- *
- * @brief NPE Image Id for NPE-C with DMA-Only feature.
- */
-#define IX_NPEDL_NPEIMAGE_NPEC_DMA 0x02080100
-#endif
-
-/* Number of NPE firmware images in this library */
-#define IX_NPE_MICROCODE_AVAILABLE_VERSIONS_COUNT 17
-
-/* Location of Microcode Images */
-#ifdef IX_NPE_MICROCODE_FIRMWARE_INCLUDED
-#ifdef IX_NPEDL_READ_MICROCODE_FROM_FILE
-
-extern UINT32* ixNpeMicrocode_binaryArray;
-
-#else
-
-extern unsigned IxNpeMicrocode_array[];
-
-#endif
-#endif
-
-/*
- * sr: undef all but the bare minimum to reduce flash usage for U-Boot
- */
-#undef IX_NPEDL_NPEIMAGE_NPEA_HSS0
-#undef IX_NPEDL_NPEIMAGE_NPEA_HSS0_ATM_SPHY_1_PORT
-#undef IX_NPEDL_NPEIMAGE_NPEA_HSS0_ATM_MPHY_1_PORT
-#undef IX_NPEDL_NPEIMAGE_NPEA_ATM_MPHY_12_PORT
-#undef IX_NPEDL_NPEIMAGE_NPEA_DMA
-#undef IX_NPEDL_NPEIMAGE_NPEA_HSS_2_PORT
-#undef IX_NPEDL_NPEIMAGE_NPEA_ETH
-#undef IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_FIREWALL
-#undef IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS
-#undef IX_NPEDL_NPEIMAGE_NPEA_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
-#undef IX_NPEDL_NPEIMAGE_NPEB_ETH
-#undef IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL
-/* #undef IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS */
-#undef IX_NPEDL_NPEIMAGE_NPEB_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
-#undef IX_NPEDL_NPEIMAGE_NPEB_DMA
-#undef IX_NPEDL_NPEIMAGE_NPEC_ETH
-#undef IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL
-/* #undef IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS */
-#undef IX_NPEDL_NPEIMAGE_NPEC_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
-#undef IX_NPEDL_NPEIMAGE_NPEC_DMA
-
-/**
- * @} defgroup IxNpeMicrocode
- */
+++ /dev/null
-/**
- * @file IxOsBufLib.h (Replaced by OSAL)
- *
- * @date 9 Oct 2002
- *
- * @brief This file contains the mbuf pool initialisation entry point
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- *
- */
-
-#ifndef IXOSBUFLIB_H
-#define IXOSBUFLIB_H
-
-#include "IxOsalBackward.h"
-
-#endif /* IXOSBUFLIB_H */
-
+++ /dev/null
-/**
- * @file (Replaced by OSAL)
- *
- * @brief This file includes the OS dependant MBUF header files.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#ifndef IxOsBuffMgt_inc
-#define IxOsBuffMgt_inc
-
-#include "IxOsalBackward.h"
-
-#endif /* ndef IxOsBuffMgt_inc */
+++ /dev/null
-/**
- * @file IxOsBuffPoolMgt.h (Replaced by OSAL)
- *
- * @date 9 Oct 2002
- *
- * @brief This file contains the mbuf pool implementation API
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- * This module contains the implementation of the OS Services buffer pool
- * management service. This module provides routines for creating pools
- * of buffers for exchange of network data, getting and returning buffers
- * from and to the pool, and some other utility functions.
- * <P>
- * Currently, the pool has 2 underlying implementations - one for the vxWorks
- * OS, and another which attempts to be OS-agnostic so that it can be used on
- * other OS's such as Linux. The API is largely the same for all OS's,
- * but there are some differences to be aware of. These are documented
- * in the API descriptions below.
- * <P>
- * The most significant difference is this: when this module is used with
- * the WindRiver VxWorks OS, it will create a pool of vxWorks "MBufs".
- * These can be used directly with the vxWorks "netBufLib" OS Library.
- * For other OS's, it will create a pool of generic buffers. These may need
- * to be converted into other buffer types (sk_buff's in Linux, for example)
- * before being used with any built-in OS routines available for
- * manipulating network data buffers.
- *
- * @sa IxOsBuffMgt.h
- */
-
-#ifndef IXOSBUFFPOOLMGT_H
-#define IXOSBUFFPOOLMGT_H
-
-#include "IxOsalBackward.h"
-
-#endif /* IXOSBUFFPOOLMGT_H */
-
+++ /dev/null
-/**
- * @file IxOsCacheMMU.h
- *
- * @brief this file contains the API of the @ref IxCacheMMU component
- *
- * <hr>
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsCacheMMU_H
-
-#ifndef __doxygen_hide
-#define IxOsCacheMMU_H
-#endif /* __doxygen_hide */
-
-#ifdef __doxygen_HIDE
-#define IX_OS_CACHE_DOXYGEN
-#endif /* __doxygen_HIDE */
-
-#include "IxOsalBackward.h"
-
-#endif /* IxOsCacheMMU_H */
-
+++ /dev/null
-/**
- * @file IxOsPrintf.h
- *
- * @brief this file contains the API of the @ref IxOsServices component
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxTypes.h"
-
-#ifndef IxOsPrintf_H
-
-#ifndef __doxygen_hide
-#define IxOsPrintf_H
-#endif /* __doxygen_hide */
-
-#ifdef __wince
-
-#ifndef IX_USE_SERCONSOLE
-
-static int
-ixLogMsg(
- char *pFormat,
- ...
- )
-{
-#ifndef IN_KERNEL
- static WCHAR pOutputString[256];
- static char pNarrowStr[256];
- int returnCnt = 0;
- va_list ap;
-
- pOutputString[0] = 0;
- pNarrowStr[0] = 0;
-
- va_start(ap, pFormat);
-
- returnCnt = _vsnprintf(pNarrowStr, 256, pFormat, ap);
-
- MultiByteToWideChar(
- CP_ACP,
- MB_PRECOMPOSED,
- pNarrowStr,
- -1,
- pOutputString,
- 256
- );
-
- OutputDebugString(pOutputString);
-
- return returnCnt;
-#else
- return 0;
-#endif
-}
-#define printf ixLogMsg
-
-#endif /* IX_USE_SERCONSOLE */
-
-#endif /* __wince */
-
-/**
- * @} IxOsPrintf
- */
-
-#endif /* IxOsPrintf_H */
+++ /dev/null
-/**
- * @file (Replaced by OSAL)
- *
- * @brief this file contains the API of the @ref IxOsServices component
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-#ifndef IxOsServices_H
-
-#ifndef __doxygen_hide
-#define IxOsServices_H
-#endif /* __doxygen_hide */
-
-#include "IxOsalBackward.h"
-
-#endif /* IxOsServices_H */
-
-
+++ /dev/null
-/**
- * @file IxOsServicesComponents.h (Replaced by OSAL)
- *
- * @brief Header file for memory access
- *
- * @par
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsServicesComponents_H
-#define IxOsServicesComponents_H
-
-#include "IxOsalBackward.h"
- * codelets_parityENAcc
- * timeSyncAcc
- * parityENAcc
- * sspAcc
- * i2c
- * integration_sspAcc
- * integration_i2c
-#define ix_timeSyncAcc 36
-#define ix_parityENAcc 37
-#define ix_codelets_parityENAcc 38
-#define ix_sspAcc 39
-#define ix_i2c 40
-#define ix_integration_sspAcc 41
-#define ix_integration_i2c 42
-#define ix_osal 43
-#define ix_integration_parityENAcc 44
-#define ix_integration_timeSyncAcc 45
-
-/***************************
- * timeSyncAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_timeSyncAcc)
-
-#if defined (IX_OSSERV_VXWORKS_LE)
-
-#define CSR_LE_DATA_COHERENT_MAPPING
-
-#endif /* IX_OSSERV_VXWORKS_LE */
-
-#endif /* timeSyncAcc */
-
-/***************************
- * parityENAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_parityENAcc)
-
-#if defined (IX_OSSERV_VXWORKS_LE)
-
-#define CSR_LE_DATA_COHERENT_MAPPING
-
-#endif /* IX_OSSERV_VXWORKS_LE */
-
-#endif /* parityENAcc */
-
-/***************************
- * codelets_parityENAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_parityENAcc)
-
-#if defined (IX_OSSERV_VXWORKS_LE)
-
-#define CSR_LE_DATA_COHERENT_MAPPING
-
-#endif /* IX_OSSERV_VXWORKS_LE */
-
-#endif /* codelets_parityENAcc */
-
-#endif /* IxOsServicesComponents_H */
-
-/***************************
- * integration_timeSyncAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_integration_timeSyncAcc)
-
-#if defined (IX_OSSERV_VXWORKS_LE)
-
-#define CSR_LE_DATA_COHERENT_MAPPING
-
-#endif /* IX_OSSERV_VXWORKS_LE */
-
-#endif /* integration_timeSyncAcc */
-
-/***************************
- * integration_parityENAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_integration_parityENAcc)
-
-#if defined (IX_OSSERV_VXWORKS_LE)
-
-#define CSR_LE_DATA_COHERENT_MAPPING
-
-#endif /* IX_OSSERV_VXWORKS_LE */
-
-#endif /* integration_parityENAcc */
+++ /dev/null
-/**
- * @file IxOsServicesEndianess.h (Replaced by OSAL)
- *
- * @brief Header file for determining system endianess and OS
- *
- * @par
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsServicesEndianess_H
-#define IxOsServicesEndianess_H
-
-#include "IxOsalBackward.h"
-
-#endif /* IxOsServicesEndianess_H */
+++ /dev/null
-/**
- * @file IxOsServicesMemAccess.h (Replaced by OSAL)
- *
- * @brief Header file for memory access
- *
- * @par
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsServicesMemAccess_H
-#define IxOsServicesMemAccess_H
-
-#include "IxOsalBackward.h"
-
-#endif /* IxOsServicesMemAccess_H */
+++ /dev/null
-/**
- * @file IxOsServicesMemMap.h (Replaced by OSAL)
- *
- * @brief Header file for memory access maps
- *
- * @par
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsServicesMemMap_H
-#define IxOsServicesMemMap_H
-
-#include "IxOsalBackward.h"
-#define IX_OSSERV_ETH_NPEA_MAP_SIZE (0x1000) /**< Eth for NPEA map size */
-#define IX_OSSERV_ETH_NPEA_PHYS_BASE IXP425_Eth_NPEA_BASE_PHYS
-
-#endif /* IxOsServicesMemMap_H */
+++ /dev/null
-/**
- * @file IxOsal.h
- *
- * @brief Top include file for OSAL
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsal_H
-#define IxOsal_H
-
-/* Basic types */
-#include "IxOsalTypes.h"
-
-/* Include assert */
-#include "IxOsalAssert.h"
-
-/*
- * Config header gives users option to choose IO MEM
- * and buffer management modules
- */
-
-#include "IxOsalConfig.h"
-
-/*
- * Symbol file needed by some OS.
- */
-#include "IxOsalUtilitySymbols.h"
-
-/* OS-specific header */
-#include "IxOsalOs.h"
-
-
-/**
- * @defgroup IxOsal Operating System Abstraction Layer (IxOsal) API
- *
- * @brief This service provides a thin layer of OS dependency services.
- *
- * This file contains the API to the functions which are some what OS dependant and would
- * require porting to a particular OS.
- * A primary focus of the component development is to make them as OS independent as possible.
- * All other components should abstract their OS dependency to this module.
- * Services overview
- * -# Data types, constants, defines
- * -# Interrupts
- * - bind interrupts to handlers
- * - unbind interrupts from handlers
- * - disables all interrupts
- * - enables all interrupts
- * - selectively disables interrupts
- * - enables an interrupt level
- * - disables an interrupt level
- * -# Memory
- * - allocates memory
- * - frees memory
- * - copies memory zones
- * - fills a memory zone
- * - allocates cache-safe memory
- * - frees cache-safe memory
- * - physical to virtual address translation
- * - virtual to physical address translation
- * - cache to memory flush
- * - cache line invalidate
- * -# Threads
- * - creates a new thread
- * - starts a newly created thread
- * - kills an existing thread
- * - exits a running thread
- * - sets the priority of an existing thread
- * - suspends thread execution
- * - resumes thread execution
- * -# IPC
- * - creates a message queue
- * - deletes a message queue
- * - sends a message to a message queue
- * - receives a message from a message queue
- * -# Thread Synchronisation
- * - initializes a mutex
- * - locks a mutex
- * - unlocks a mutex
- * - non-blocking attempt to lock a mutex
- * - destroys a mutex object
- * - initializes a fast mutex
- * - non-blocking attempt to lock a fast mutex
- * - unlocks a fast mutex
- * - destroys a fast mutex object
- * - initializes a semaphore
- * - posts to (increments) a semaphore
- * - waits on (decrements) a semaphore
- * - non-blocking wait on semaphore
- * - gets semaphore value
- * - destroys a semaphore object
- * - yields execution of current thread
- * -# Time functions
- * - yielding sleep for a number of milliseconds
- * - busy sleep for a number of microseconds
- * - value of the timestamp counter
- * - resolution of the timestamp counter
- * - system clock rate, in ticks
- * - current system time
- * - converts ixOsalTimeVal into ticks
- * - converts ticks into ixOsalTimeVal
- * - converts ixOsalTimeVal to milliseconds
- * - converts milliseconds to IxOsalTimeval
- * - "equal" comparison for IxOsalTimeval
- * - "less than" comparison for IxOsalTimeval
- * - "greater than" comparison for IxOsalTimeval
- * - "add" operator for IxOsalTimeval
- * - "subtract" operator for IxOsalTimeval
- * -# Logging
- * - sets the current logging verbosity level
- * - interrupt-safe logging function
- * -# Timer services
- * - schedules a repeating timer
- * - schedules a single-shot timer
- * - cancels a running timer
- * - displays all the running timers
- * -# Optional Modules
- * - Buffer management module
- * - I/O memory and endianess support module
- *
- * @{
- */
-
-
-/*
- * Prototypes
- */
-
-/* ========================== Interrupts ================================
- *
- */
-
-/**
- * @ingroup IxOsal
- *
- * @brief Binds an interrupt handler to an interrupt level
- *
- * @param irqLevel (in) - interrupt level
- * @param irqHandler (in) - interrupt handler
- * @param parameter (in) - custom parameter to be passed to the
- * interrupt handler
- *
- * Binds an interrupt handler to an interrupt level. The operation will
- * fail if the wrong level is selected, if the handler is NULL, or if the
- * interrupt is already bound. This functions binds the specified C
- * routine to an interrupt level. When called, the "parameter" value will
- * be passed to the routine.
- *
- * Reentrant: no
- * IRQ safe: no
- *
- * @return IX_SUCCESS if the operation succeeded or IX_FAIL otherwise
- */
-PUBLIC IX_STATUS ixOsalIrqBind (UINT32 irqLevel,
- IxOsalVoidFnVoidPtr irqHandler,
- void *parameter);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Unbinds an interrupt handler from an interrupt level
- *
- * @param irqLevel (in) - interrupt level
- *
- * Unbinds the selected interrupt level from any previously registered
- * handler
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return IX_SUCCESS if the operation succeeded or IX_FAIL otherwise
- */
-PUBLIC IX_STATUS ixOsalIrqUnbind (UINT32 irqLevel);
-
-
-/**
- * @ingroup IxOsal
- *
- * @brief Disables all interrupts
- *
- * @param - none
- *
- * Disables all the interrupts and prevents tasks scheduling
- *
- * @li Reentrant: no
- * @li IRQ safe: yes
- *
- * @return interrupt enable status prior to locking
- */
-PUBLIC UINT32 ixOsalIrqLock (void);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Enables all interrupts
- *
- * @param irqEnable (in) - interrupt enable status, prior to interrupt
- * locking
- *
- * Enables the interrupts and task scheduling, cancelling the effect
- * of ixOsalIrqLock()
- *
- * @li Reentrant: no
- * @li IRQ safe: yes
- *
- * @return IX_SUCCESS if the operation succeeded or IX_FAIL otherwise
- */
-PUBLIC void ixOsalIrqUnlock (UINT32 irqEnable);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Selectively disables interrupts
- *
- * @param irqLevel - new interrupt level
- *
- * Disables the interrupts below the specified interrupt level
- *
- * @li Reentrant: no
- * @li IRQ safe: yes
- *
- * @note Depending on the implementation this function can disable all
- * the interrupts
- *
- * @return previous interrupt level
- */
-PUBLIC UINT32 ixOsalIrqLevelSet (UINT32 irqLevel);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Enables an interrupt level
- *
- * @param irqLevel - interrupt level to enable
- *
- * Enables the specified interrupt level
- *
- * @li Reentrant: no
- * @li IRQ safe: yes
- *
- * @return - none
- */
-PUBLIC void ixOsalIrqEnable (UINT32 irqLevel);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Disables an interrupt level
- *
- * @param irqLevel - interrupt level to disable
- *
- * Disables the specified interrupt level
- *
- * @li Reentrant: no
- * @li IRQ safe: yes
- *
- * @return - none
- */
-PUBLIC void ixOsalIrqDisable (UINT32 irqLevel);
-
-
-/* ============================= Memory =================================
- *
- */
-
-/**
- * @ingroup IxOsal
- *
- * @brief Allocates memory
- *
- * @param size - memory size to allocate, in bytes
- *
- * Allocates a memory zone of a given size
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return Pointer to the allocated zone or NULL if the allocation failed
- */
-PUBLIC void *ixOsalMemAlloc (UINT32 size);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Frees memory
- *
- * @param ptr - pointer to the memory zone
- *
- * Frees a previously allocated memory zone
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - none
- */
-PUBLIC void ixOsalMemFree (void *ptr);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Copies memory zones
- *
- * @param dest - destination memory zone
- * @param src - source memory zone
- * @param count - number of bytes to copy
- *
- * Copies count bytes from the source memory zone pointed by src into the
- * memory zone pointed by dest.
- *
- * @li Reentrant: no
- * @li IRQ safe: yes
- *
- * @return Pointer to the destination memory zone
- */
-PUBLIC void *ixOsalMemCopy (void *dest, void *src, UINT32 count);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Fills a memory zone
- *
- * @param ptr - pointer to the memory zone
- * @param filler - byte to fill the memory zone with
- * @param count - number of bytes to fill
- *
- * Fills a memory zone with a given constant byte
- *
- * @li Reentrant: no
- * @li IRQ safe: yes
- *
- * @return Pointer to the memory zone
- */
-PUBLIC void *ixOsalMemSet (void *ptr, UINT8 filler, UINT32 count);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Allocates cache-safe memory
- *
- * @param size - size, in bytes, of the allocated zone
- *
- * Allocates a cache-safe memory zone of at least "size" bytes and returns
- * the pointer to the memory zone. This memory zone, depending on the
- * platform, is either uncached or aligned on a cache line boundary to make
- * the CACHE_FLUSH and CACHE_INVALIDATE macros safe to use. The memory
- * allocated with this function MUST be freed with ixOsalCacheDmaFree(),
- * otherwise memory corruption can occur.
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return Pointer to the memory zone or NULL if allocation failed
- *
- * @note It is important to note that cache coherence is maintained in
- * software by using the IX_OSAL_CACHE_FLUSH and IX_OSAL_CACHE_INVALIDATE
- * macros to maintain consistency between cache and external memory.
- */
-PUBLIC void *ixOsalCacheDmaMalloc (UINT32 size);
-
-/* Macros for ixOsalCacheDmaMalloc*/
-#define IX_OSAL_CACHE_DMA_MALLOC(size) ixOsalCacheDmaMalloc(size)
-
-/**
- * @ingroup IxOsal
- *
- * @brief Frees cache-safe memory
- *
- * @param ptr - pointer to the memory zone
- *
- * Frees a memory zone previously allocated with ixOsalCacheDmaMalloc()
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - none
- */
-PUBLIC void ixOsalCacheDmaFree (void *ptr);
-
-#define IX_OSAL_CACHE_DMA_FREE(ptr) ixOsalCacheDmaFree(ptr)
-
-/**
- * @ingroup IxOsal
- *
- * @brief physical to virtual address translation
- *
- * @param physAddr - physical address
- *
- * Converts a physical address into its equivalent MMU-mapped virtual address
- *
- * @li Reentrant: no
- * @li IRQ safe: yes
- *
- * @return Corresponding virtual address, as UINT32
- */
-#define IX_OSAL_MMU_PHYS_TO_VIRT(physAddr) \
- IX_OSAL_OS_MMU_PHYS_TO_VIRT(physAddr)
-
-
-/**
- * @ingroup IxOsal
- *
- * @brief virtual to physical address translation
- *
- * @param virtAddr - virtual address
- *
- * Converts a virtual address into its equivalent MMU-mapped physical address
- *
- * @li Reentrant: no
- * @li IRQ safe: yes
- *
- * @return Corresponding physical address, as UINT32
- */
-#define IX_OSAL_MMU_VIRT_TO_PHYS(virtAddr) \
- IX_OSAL_OS_MMU_VIRT_TO_PHYS(virtAddr)
-
-
-
-/**
- * @ingroup IxOsal
- *
- * @brief cache to memory flush
- *
- * @param addr - memory address to flush from cache
- * @param size - number of bytes to flush (rounded up to a cache line)
- *
- * Flushes the cached value of the memory zone pointed by "addr" into memory,
- * rounding up to a cache line. Use before the zone is to be read by a
- * processing unit which is not cache coherent with the main CPU.
- *
- * @li Reentrant: no
- * @li IRQ safe: yes
- *
- * @return - none
- */
-#define IX_OSAL_CACHE_FLUSH(addr, size) IX_OSAL_OS_CACHE_FLUSH(addr, size)
-
-
-
-/**
- * @ingroup IxOsal
- *
- * @brief cache line invalidate
- *
- * @param addr - memory address to invalidate in cache
- * @param size - number of bytes to invalidate (rounded up to a cache line)
- *
- * Invalidates the cached value of the memory zone pointed by "addr",
- * rounding up to a cache line. Use before reading the zone from the main
- * CPU, if the zone has been updated by a processing unit which is not cache
- * coherent with the main CPU.
- *
- * @li Reentrant: no
- * @li IRQ safe: yes
- *
- * @return - none
- */
-#define IX_OSAL_CACHE_INVALIDATE(addr, size) IX_OSAL_OS_CACHE_INVALIDATE(addr, size)
-
-
-/* ============================= Threads =================================
- *
- */
-
-/**
- * @ingroup IxOsal
- *
- * @brief Creates a new thread
- *
- * @param thread - handle of the thread to be created
- * @param threadAttr - pointer to a thread attribute object
- * @param startRoutine - thread entry point
- * @param arg - argument given to the thread
- *
- * Creates a thread given a thread handle and a thread attribute object. The
- * same thread attribute object can be used to create separate threads. "NULL"
- * can be specified as the attribute, in which case the default values will
- * be used. The thread needs to be explicitly started using ixOsalThreadStart().
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalThreadCreate (IxOsalThread * thread,
- IxOsalThreadAttr * threadAttr,
- IxOsalVoidFnVoidPtr startRoutine,
- void *arg);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Starts a newly created thread
- *
- * @param thread - handle of the thread to be started
- *
- * Starts a thread given its thread handle. This function is to be called
- * only once, following the thread initialization.
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalThreadStart (IxOsalThread * thread);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Kills an existing thread
- *
- * @param thread - handle of the thread to be killed
- *
- * Kills a thread given its thread handle.
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @note It is not possible to kill threads in Linux kernel mode. This
- * function will only send a SIGTERM signal, and it is the responsibility
- * of the thread to check for the presence of this signal with
- * signal_pending().
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalThreadKill (IxOsalThread * thread);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Exits a running thread
- *
- * Terminates the calling thread
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - This function never returns
- */
-PUBLIC void ixOsalThreadExit (void);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Sets the priority of an existing thread
- *
- * @param thread - handle of the thread
- * @param priority - new priority, between 0 and 255 (0 being the highest)
- *
- * Sets the thread priority
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalThreadPrioritySet (IxOsalThread * thread,
- UINT32 priority);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Suspends thread execution
- *
- * @param thread - handle of the thread
- *
- * Suspends the thread execution
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalThreadSuspend (IxOsalThread * thread);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Resumes thread execution
- *
- * @param thread - handle of the thread
- *
- * Resumes the thread execution
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalThreadResume (IxOsalThread * thread);
-
-
-/* ======================= Message Queues (IPC) ==========================
- *
- */
-
-/**
- * @ingroup IxOsal
- *
- * @brief Creates a message queue
- *
- * @param queue - queue handle
- * @param msgCount - maximum number of messages to hold in the queue
- * @param msgLen - maximum length of each message, in bytes
- *
- * Creates a message queue of msgCount messages, each containing msgLen bytes
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalMessageQueueCreate (IxOsalMessageQueue * queue,
- UINT32 msgCount, UINT32 msgLen);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Deletes a message queue
- *
- * @param queue - queue handle
- *
- * Deletes a message queue
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalMessageQueueDelete (IxOsalMessageQueue * queue);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Sends a message to a message queue
- *
- * @param queue - queue handle
- * @param message - message to send
- *
- * Sends a message to the message queue. The message will be copied (at the
- * configured size of the message) into the queue.
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalMessageQueueSend (IxOsalMessageQueue * queue,
- UINT8 * message);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Receives a message from a message queue
- *
- * @param queue - queue handle
- * @param message - pointer to where the message should be copied to
- *
- * Retrieves the first message from the message queue
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalMessageQueueReceive (IxOsalMessageQueue * queue,
- UINT8 * message);
-
-
-/* ======================= Thread Synchronisation ========================
- *
- */
-
-/**
- * @ingroup IxOsal
- *
- * @brief initializes a mutex
- *
- * @param mutex - mutex handle
- *
- * Initializes a mutex object
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalMutexInit (IxOsalMutex * mutex);
-
-/**
- * @ingroup IxOsal
- *
- * @brief locks a mutex
- *
- * @param mutex - mutex handle
- * @param timeout - timeout in ms; IX_OSAL_WAIT_FOREVER (-1) to wait forever
- * or IX_OSAL_WAIT_NONE to return immediately
- *
- * Locks a mutex object
- *
- * @li Reentrant: yes
- * @li IRQ safe: no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalMutexLock (IxOsalMutex * mutex, INT32 timeout);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Unlocks a mutex
- *
- * @param mutex - mutex handle
- *
- * Unlocks a mutex object
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalMutexUnlock (IxOsalMutex * mutex);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Non-blocking attempt to lock a mutex
- *
- * @param mutex - mutex handle
- *
- * Attempts to lock a mutex object, returning immediately with IX_SUCCESS if
- * the lock was successful or IX_FAIL if the lock failed
- *
- * @li Reentrant: yes
- * @li IRQ safe: no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalMutexTryLock (IxOsalMutex * mutex);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Destroys a mutex object
- *
- * @param mutex - mutex handle
- * @param
- *
- * Destroys a mutex object; the caller should ensure that no thread is
- * blocked on this mutex
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalMutexDestroy (IxOsalMutex * mutex);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Initializes a fast mutex
- *
- * @param mutex - fast mutex handle
- *
- * Initializes a fast mutex object
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalFastMutexInit (IxOsalFastMutex * mutex);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Non-blocking attempt to lock a fast mutex
- *
- * @param mutex - fast mutex handle
- *
- * Attempts to lock a fast mutex object, returning immediately with
- * IX_SUCCESS if the lock was successful or IX_FAIL if the lock failed
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalFastMutexTryLock (IxOsalFastMutex * mutex);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Unlocks a fast mutex
- *
- * @param mutex - fast mutex handle
- *
- * Unlocks a fast mutex object
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalFastMutexUnlock (IxOsalFastMutex * mutex);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Destroys a fast mutex object
- *
- * @param mutex - fast mutex handle
- *
- * Destroys a fast mutex object
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalFastMutexDestroy (IxOsalFastMutex * mutex);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Initializes a semaphore
- *
- * @param semaphore - semaphore handle
- * @param value - initial semaphore value
- *
- * Initializes a semaphore object
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalSemaphoreInit (IxOsalSemaphore * semaphore,
- UINT32 value);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Posts to (increments) a semaphore
- *
- * @param semaphore - semaphore handle
- *
- * Increments a semaphore object
- *
- * @li Reentrant: no
- * @li IRQ safe: yes
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalSemaphorePost (IxOsalSemaphore * semaphore);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Waits on (decrements) a semaphore
- *
- * @param semaphore - semaphore handle
- * @param timeout - timeout, in ms; IX_OSAL_WAIT_FOREVER (-1) if the thread
- * is to block indefinitely or IX_OSAL_WAIT_NONE (0) if the thread is to
- * return immediately even if the call fails
- *
- * Decrements a semaphore, blocking if the semaphore is
- * unavailable (value is 0).
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalSemaphoreWait (IxOsalSemaphore * semaphore,
- INT32 timeout);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Non-blocking wait on semaphore
- *
- * @param semaphore - semaphore handle
- *
- * Decrements a semaphore, not blocking the calling thread if the semaphore
- * is unavailable
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalSemaphoreTryWait (IxOsalSemaphore * semaphore);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Gets semaphore value
- *
- * @param semaphore - semaphore handle
- * @param value - location to store the semaphore value
- *
- * Retrieves the current value of a semaphore object
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalSemaphoreGetValue (IxOsalSemaphore * semaphore,
- UINT32 * value);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Destroys a semaphore object
- *
- * @param semaphore - semaphore handle
- *
- * Destroys a semaphore object; the caller should ensure that no thread is
- * blocked on this semaphore
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalSemaphoreDestroy (IxOsalSemaphore * semaphore);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Yields execution of current thread
- *
- * Yields the execution of the current thread
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - none
- */
-PUBLIC void ixOsalYield (void);
-
-
-/* ========================== Time functions ===========================
- *
- */
-
-/**
- * @ingroup IxOsal
- *
- * @brief Yielding sleep for a number of milliseconds
- *
- * @param milliseconds - number of milliseconds to sleep
- *
- * The calling thread will sleep for the specified number of milliseconds.
- * This sleep is yielding, hence other tasks will be scheduled by the
- * operating system during the sleep period. Calling this function with an
- * argument of 0 will place the thread at the end of the current scheduling
- * loop.
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - none
- */
-PUBLIC void ixOsalSleep (UINT32 milliseconds);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Busy sleep for a number of microseconds
- *
- * @param microseconds - number of microseconds to sleep
- *
- * Sleeps for the specified number of microseconds, without explicitly
- * yielding thread execution to the OS scheduler
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - none
- */
-PUBLIC void ixOsalBusySleep (UINT32 microseconds);
-
-/**
- * @ingroup IxOsal
- *
- * @brief XXX
- *
- * Retrieves the current timestamp
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - The current timestamp
- *
- * @note The implementation of this function is platform-specific. Not
- * all the platforms provide a high-resolution timestamp counter.
- */
-PUBLIC UINT32 ixOsalTimestampGet (void);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Resolution of the timestamp counter
- *
- * Retrieves the resolution (frequency) of the timestamp counter.
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - The resolution of the timestamp counter
- *
- * @note The implementation of this function is platform-specific. Not all
- * the platforms provide a high-resolution timestamp counter.
- */
-PUBLIC UINT32 ixOsalTimestampResolutionGet (void);
-
-/**
- * @ingroup IxOsal
- *
- * @brief System clock rate, in ticks
- *
- * Retrieves the resolution (number of ticks per second) of the system clock
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - The system clock rate
- *
- * @note The implementation of this function is platform and OS-specific.
- * The system clock rate is not always available - e.g. Linux does not
- * provide this information in user mode
- */
-PUBLIC UINT32 ixOsalSysClockRateGet (void);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Current system time
- *
- * @param tv - pointer to an IxOsalTimeval structure to store the current
- * time in
- *
- * Retrieves the current system time (real-time)
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - none
- *
- * @note The implementation of this function is platform-specific. Not all
- * platforms have a real-time clock.
- */
-PUBLIC void ixOsalTimeGet (IxOsalTimeval * tv);
-
-
-
-/* Internal function to convert timer val to ticks.
- * NOTE - This should not be called by the user.
- * Use the macro IX_OSAL_TIMEVAL_TO_TICKS
- * OS-independent, implemented in framework.
- */
-PUBLIC UINT32 ixOsalTimevalToTicks (IxOsalTimeval tv);
-
-
-/**
- * @ingroup IxOsal
- *
- * @brief Converts ixOsalTimeVal into ticks
- *
- * @param tv - an IxOsalTimeval structure
- *
- * Converts an IxOsalTimeval structure into OS ticks
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - Corresponding number of ticks
- *
- * Note: This function is OS-independent. Implemented by core.
- */
-#define IX_OSAL_TIMEVAL_TO_TICKS(tv) ixOsalTimevalToTicks(tv)
-
-
-
-/* Internal function to convert ticks to timer val
- * NOTE - This should not be called by the user.
- * Use the macro IX_OSAL_TICKS_TO_TIMEVAL
- */
-
-PUBLIC void ixOsalTicksToTimeval (UINT32 ticks, IxOsalTimeval * pTv);
-
-
-/**
- * @ingroup IxOsal
- *
- * @brief Converts ticks into ixOsalTimeVal
- *
- * @param ticks - number of ticks
- * @param pTv - pointer to the destination structure
- *
- * Converts the specified number of ticks into an IxOsalTimeval structure
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - Corresponding IxOsalTimeval structure
- * Note: This function is OS-independent. Implemented by core.
- */
-#define IX_OSAL_TICKS_TO_TIMEVAL(ticks, pTv) \
- ixOsalTicksToTimeval(ticks, pTv)
-
-
-
-
-/**
- * @ingroup IxOsal
- *
- * @brief Converts ixOsalTimeVal to milliseconds
- *
- * @param tv - IxOsalTimeval structure to convert
- *
- * Converts an IxOsalTimeval structure into milliseconds
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - Corresponding number of milliseconds
- * Note: This function is OS-independent. Implemented by core.
- */
-#define IX_OSAL_TIMEVAL_TO_MS(tv) ((tv.secs * 1000) + (tv.nsecs / 1000000))
-
-
-/**
- * @ingroup IxOsal
- *
- * @brief Converts milliseconds to IxOsalTimeval
- *
- * @param milliseconds - number of milliseconds to convert
- * @param pTv - pointer to the destination structure
- *
- * Converts a millisecond value into an IxOsalTimeval structure
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - Corresponding IxOsalTimeval structure
- * Note: This function is OS-independent. Implemented by core.
- */
-#define IX_OSAL_MS_TO_TIMEVAL(milliseconds, pTv) \
- ((IxOsalTimeval *) pTv)->secs = milliseconds / 1000; \
- ((IxOsalTimeval *) pTv)->nsecs = (milliseconds % 1000) * 1000000
-
-
-/**
- * @ingroup IxOsal
- *
- * @brief "equal" comparison for IxOsalTimeval
- *
- * @param tvA, tvB - IxOsalTimeval structures to compare
- *
- * Compares two IxOsalTimeval structures for equality
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - true if the structures are equal
- * - false otherwise
- * Note: This function is OS-independant
- */
-#define IX_OSAL_TIME_EQ(tvA, tvB) \
- ((tvA).secs == (tvB).secs && (tvA).nsecs == (tvB).nsecs)
-
-
-/**
- * @ingroup IxOsal
- *
- * @brief "less than" comparison for IxOsalTimeval
- *
- * @param tvA, tvB - IxOsalTimeval structures to compare
- *
- * Compares two IxOsalTimeval structures to determine if the first one is
- * less than the second one
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - true if tvA < tvB
- * - false otherwise
- * Note: This function is OS-independent. Implemented by core.
- */
-#define IX_OSAL_TIME_LT(tvA,tvB) \
- ((tvA).secs < (tvB).secs || \
- ((tvA).secs == (tvB).secs && (tvA).nsecs < (tvB).nsecs))
-
-
-/**
- * @ingroup IxOsal
- *
- * @brief "greater than" comparison for IxOsalTimeval
- *
- * @param tvA, tvB - IxOsalTimeval structures to compare
- *
- * Compares two IxOsalTimeval structures to determine if the first one is
- * greater than the second one
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - true if tvA > tvB
- * - false otherwise
- * Note: This function is OS-independent.
- */
-#define IX_OSAL_TIME_GT(tvA, tvB) \
- ((tvA).secs > (tvB).secs || \
- ((tvA).secs == (tvB).secs && (tvA).nsecs > (tvB).nsecs))
-
-
-/**
- * @ingroup IxOsal
- *
- * @brief "add" operator for IxOsalTimeval
- *
- * @param tvA, tvB - IxOsalTimeval structures to add
- *
- * Adds the second IxOsalTimevalStruct to the first one (equivalent to
- * tvA += tvB)
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - none
- * Note: This function is OS-independent.
- */
-#define IX_OSAL_TIME_ADD(tvA, tvB) \
- (tvA).secs += (tvB).secs; \
- (tvA).nsecs += (tvB).nsecs; \
- if ((tvA).nsecs >= IX_OSAL_BILLION) \
- { \
- (tvA).secs++; \
- (tvA).nsecs -= IX_OSAL_BILLION; }
-
-
-/**
- * @ingroup IxOsal
- *
- * @brief "subtract" operator for IxOsalTimeval
- *
- * @param tvA, tvB - IxOsalTimeval structures to subtract
- *
- * Subtracts the second IxOsalTimevalStruct from the first one (equivalent
- * to tvA -= tvB)
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - none
- * Note: This function is OS-independent. Implemented by core.
- */
-#define IX_OSAL_TIME_SUB(tvA, tvB) \
- if ((tvA).nsecs >= (tvB).nsecs) \
- { \
- (tvA).secs -= (tvB).secs; \
- (tvA).nsecs -= (tvB).nsecs; \
- } \
- else \
- { \
- (tvA).secs -= ((tvB).secs + 1); \
- (tvA).nsecs += IX_OSAL_BILLION - (tvB).nsecs; \
- }
-
-
-/* ============================= Logging ==============================
- *
- */
-
-/**
- * @ingroup IxOsal
- *
- * @brief Interrupt-safe logging function
- *
- * @param level - identifier prefix for the message
- * @param device - output device
- * @param format - message format, in a printf format
- * @param ... - up to 6 arguments to be printed
- *
- * IRQ-safe logging function, similar to printf. Accepts up to 6 arguments
- * to print (excluding the level, device and the format). This function will
- * actually display the message only if the level is lower than the current
- * verbosity level or if the IX_OSAL_LOG_USER level is used. An output device
- * must be specified (see IxOsalTypes.h).
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - Beside the exceptions documented in the note below, the returned
- * value is the number of printed characters, or -1 if the parameters are
- * incorrect (NULL format, unknown output device)
- *
- * @note The exceptions to the return value are:
- * VxWorks: The return value is 32 if the specified level is 1 and 64
- * if the specified level is greater than 1 and less or equal than 9.
- * WinCE: If compiled for EBOOT then the return value is always 0.
- *
- * @note The given print format should take into account the specified
- * output device. IX_OSAL_STDOUT supports all the usual print formats,
- * however a custom hex display specified by IX_OSAL_HEX would support
- * only a fixed number of hexadecimal digits.
- */
-PUBLIC INT32 ixOsalLog (IxOsalLogLevel level,
- IxOsalLogDevice device,
- char *format,
- int arg1,
- int arg2, int arg3, int arg4, int arg5, int arg6);
-
-/**
- * @ingroup IxOsal
- *
- * @brief sets the current logging verbosity level
- *
- * @param level - new log verbosity level
- *
- * Sets the log verbosity level. The default value is IX_OSAL_LOG_ERROR.
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - Old log verbosity level
- */
-PUBLIC UINT32 ixOsalLogLevelSet (UINT32 level);
-
-
-/* ============================= Logging ==============================
- *
- */
-
-/**
- * @ingroup IxOsal
- *
- * @brief Schedules a repeating timer
- *
- * @param timer - handle of the timer object
- * @param period - timer trigger period, in milliseconds
- * @param priority - timer priority (0 being the highest)
- * @param callback - user callback to invoke when the timer triggers
- * @param param - custom parameter passed to the callback
- *
- * Schedules a timer to be called every period milliseconds. The timer
- * will invoke the specified callback function possibly in interrupt
- * context, passing the given parameter. If several timers trigger at the
- * same time contention issues are dealt according to the specified timer
- * priorities.
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalRepeatingTimerSchedule (IxOsalTimer * timer,
- UINT32 period,
- UINT32 priority,
- IxOsalVoidFnVoidPtr callback,
- void *param);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Schedules a single-shot timer
- *
- * @param timer - handle of the timer object
- * @param period - timer trigger period, in milliseconds
- * @param priority - timer priority (0 being the highest)
- * @param callback - user callback to invoke when the timer triggers
- * @param param - custom parameter passed to the callback
- *
- * Schedules a timer to be called after period milliseconds. The timer
- * will cease to function past its first trigger. The timer will invoke
- * the specified callback function, possibly in interrupt context, passing
- * the given parameter. If several timers trigger at the same time contention
- * issues are dealt according to the specified timer priorities.
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS
-ixOsalSingleShotTimerSchedule (IxOsalTimer * timer,
- UINT32 period,
- UINT32 priority,
- IxOsalVoidFnVoidPtr callback, void *param);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Cancels a running timer
- *
- * @param timer - handle of the timer object
- *
- * Cancels a single-shot or repeating timer.
- *
- * @li Reentrant: no
- * @li IRQ safe: yes
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalTimerCancel (IxOsalTimer * timer);
-
-/**
- * @ingroup IxOsal
- *
- * @brief displays all the running timers
- *
- * Displays a list with all the running timers and their parameters (handle,
- * period, type, priority, callback and user parameter)
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - none
- */
-PUBLIC void ixOsalTimersShow (void);
-
-
-/* ============================= Version ==============================
- *
- */
-
-/**
- * @ingroup IxOsal
- *
- * @brief provides the name of the Operating System running
- *
- * @param osName - Pointer to a NULL-terminated string of characters
- * that holds the name of the OS running.
- * This is both an input and an ouput parameter
- * @param maxSize - Input parameter that defines the maximum number of
- * bytes that can be stored in osName
- *
- * Returns a string of characters that describe the Operating System name
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * return - IX_SUCCESS for successful retrieval
- * - IX_FAIL if (osType == NULL | maxSize =< 0)
- */
-PUBLIC IX_STATUS ixOsalOsNameGet (INT8* osName, INT32 maxSize);
-
-/**
- * @ingroup IxOsal
- *
- * @brief provides the version of the Operating System running
- *
- * @param osVersion - Pointer to a NULL terminated string of characters
- * that holds the version of the OS running.
- * This is both an input and an ouput parameter
- * @param maxSize - Input parameter that defines the maximum number of
- * bytes that can be stored in osVersion
- *
- * Returns a string of characters that describe the Operating System's version
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * return - IX_SUCCESS for successful retrieval
- * - IX_FAIL if (osVersion == NULL | maxSize =< 0)
- */
-PUBLIC IX_STATUS ixOsalOsVersionGet(INT8* osVersion, INT32 maxSize);
-
-
-
-/**
- * @} IxOsal
- */
-
-#endif /* IxOsal_H */
+++ /dev/null
-/*
- * @file IxOsalAssert.h
- * @author Intel Corporation
- * @date 25-08-2004
- *
- * @brief description goes here
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IX_OSAL_ASSERT_H
-#define IX_OSAL_ASSERT_H
-
-/*
- * Put the system defined include files required
- * @par
- * <TAGGED>
- */
-
-#include "IxOsalOsAssert.h"
-
-/**
- * @brief Assert macro, assert the condition is true. This
- * will not be compiled out.
- * N.B. will result in a system crash if it is false.
- */
-#define IX_OSAL_ASSERT(c) IX_OSAL_OS_ASSERT(c)
-
-
-/**
- * @brief Ensure macro, ensure the condition is true.
- * This will be conditionally compiled out and
- * may be used for test purposes.
- */
-#ifdef IX_OSAL_ENSURE_ON
-#define IX_OSAL_ENSURE(c, str) do { \
-if (!(c)) ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, str, \
-0, 0, 0, 0, 0, 0); } while (0)
-
-#else
-#define IX_OSAL_ENSURE(c, str)
-#endif
-
-
-#endif /* IX_OSAL_ASSERT_H */
+++ /dev/null
-/**
- * This file is intended to provide backward
- * compatibility for main osService/OSSL
- * APIs.
- *
- * It shall be phased out gradually and users
- * are strongly recommended to use IX_OSAL API.
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IX_OSAL_BACKWARD_H
-#define IX_OSAL_BACKWARD_H
-
-#include "IxOsal.h"
-
-#include "IxOsalBackwardCacheMMU.h"
-
-#include "IxOsalBackwardOsServices.h"
-
-#include "IxOsalBackwardMemMap.h"
-
-#include "IxOsalBackwardBufferMgt.h"
-
-#include "IxOsalBackwardOssl.h"
-
-#include "IxOsalBackwardAssert.h"
-
-#endif /* IX_OSAL_BACKWARD_H */
+++ /dev/null
-/**
- * This file is intended to provide backward
- * compatibility for main osService/OSSL
- * APIs.
- *
- * It shall be phased out gradually and users
- * are strongly recommended to use IX_OSAL API.
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IX_OSAL_BACKWARD_ASSERT_H
-#define IX_OSAL_BACKWARD_ASSERT_H
-
-#define IX_ENSURE(c, str) IX_OSAL_ENSURE(c, str)
-#define IX_ASSERT(c) IX_OSAL_ASSERT(c)
-
-#endif /* IX_OSAL_BACKWARD_ASSERT_H */
+++ /dev/null
-/**
- * This file is intended to provide backward
- * compatibility for main osService/OSSL
- * APIs.
- *
- * It shall be phased out gradually and users
- * are strongly recommended to use IX_OSAL API.
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IX_OSAL_BACKWARD_BUFFER_MGT_H
-#define IX_OSAL_BACKWARD_BUFFER_MGT_H
-
-typedef IX_OSAL_MBUF IX_MBUF;
-
-typedef IX_OSAL_MBUF_POOL IX_MBUF_POOL;
-
-
-#define IX_MBUF_NEXT_BUFFER_IN_PKT_PTR(m_blk_ptr) \
- IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(m_blk_ptr)
-
-
-#define IX_MBUF_NEXT_PKT_IN_CHAIN_PTR(m_blk_ptr) \
- IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m_blk_ptr)
-
-
-#define IX_MBUF_MDATA(m_blk_ptr) \
- IX_OSAL_MBUF_MDATA(m_blk_ptr)
-
-
-#define IX_MBUF_MLEN(m_blk_ptr) \
- IX_OSAL_MBUF_MLEN(m_blk_ptr)
-
-
-#define IX_MBUF_TYPE(m_blk_ptr) \
- IX_OSAL_MBUF_MTYPE(m_blk_ptr)
-
-/* Same as IX_MBUF_TYPE */
-#define IX_MBUF_MTYPE(m_blk_ptr) \
- IX_OSAL_MBUF_MTYPE(m_blk_ptr)
-
-#define IX_MBUF_FLAGS(m_blk_ptr) \
- IX_OSAL_MBUF_FLAGS(m_blk_ptr)
-
-
-#define IX_MBUF_NET_POOL(m_blk_ptr) \
- IX_OSAL_MBUF_NET_POOL(m_blk_ptr)
-
-
-#define IX_MBUF_PKT_LEN(m_blk_ptr) \
- IX_OSAL_MBUF_PKT_LEN(m_blk_ptr)
-
-
-#define IX_MBUF_PRIV(m_blk_ptr) \
- IX_OSAL_MBUF_PRIV(m_blk_ptr)
-
-
-#define IX_MBUF_ALLOCATED_BUFF_LEN(m_blk_ptr) \
- IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(m_blk_ptr)
-
-
-#define IX_MBUF_ALLOCATED_BUFF_DATA(m_blk_ptr) \
- IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(m_blk_ptr)
-
-
-#define IX_MBUF_POOL_SIZE_ALIGN(size) \
- IX_OSAL_MBUF_POOL_SIZE_ALIGN(size)
-
-
-#define IX_MBUF_POOL_MBUF_AREA_SIZE_ALIGNED(count) \
- IX_OSAL_MBUF_POOL_MBUF_AREA_SIZE_ALIGNED(count)
-
-
-#define IX_MBUF_POOL_DATA_AREA_SIZE_ALIGNED(count, size) \
- IX_OSAL_MBUF_POOL_DATA_AREA_SIZE_ALIGNED(count, size)
-
-
-#define IX_MBUF_POOL_MBUF_AREA_ALLOC(count, memAreaSize) \
- IX_OSAL_MBUF_POOL_MBUF_AREA_ALLOC(count, memAreaSize)
-
-
-#define IX_MBUF_POOL_DATA_AREA_ALLOC(count, size, memAreaSize) \
- IX_OSAL_MBUF_POOL_DATA_AREA_ALLOC(count, size, memAreaSize)
-
-IX_STATUS
-ixOsalOsIxp400BackwardPoolInit (IX_OSAL_MBUF_POOL ** poolPtrPtr,
- UINT32 count, UINT32 size, const char *name);
-
-
-/* This one needs extra steps*/
-#define IX_MBUF_POOL_INIT(poolPtr, count, size, name) \
- ixOsalOsIxp400BackwardPoolInit( poolPtr, count, size, name)
-
-
-#define IX_MBUF_POOL_INIT_NO_ALLOC(poolPtrPtr, bufPtr, dataPtr, count, size, name) \
- (*poolPtrPtr = IX_OSAL_MBUF_NO_ALLOC_POOL_INIT(bufPtr, dataPtr, count, size, name))
-
-
-IX_STATUS
-ixOsalOsIxp400BackwardMbufPoolGet (IX_OSAL_MBUF_POOL * poolPtr,
- IX_OSAL_MBUF ** newBufPtrPtr);
-
-#define IX_MBUF_POOL_GET(poolPtr, bufPtrPtr) \
- ixOsalOsIxp400BackwardMbufPoolGet(poolPtr, bufPtrPtr)
-
-
-#define IX_MBUF_POOL_PUT(bufPtr) \
- IX_OSAL_MBUF_POOL_PUT(bufPtr)
-
-
-#define IX_MBUF_POOL_PUT_CHAIN(bufPtr) \
- IX_OSAL_MBUF_POOL_PUT_CHAIN(bufPtr)
-
-
-#define IX_MBUF_POOL_SHOW(poolPtr) \
- IX_OSAL_MBUF_POOL_SHOW(poolPtr)
-
-
-#define IX_MBUF_POOL_MDATA_RESET(bufPtr) \
- IX_OSAL_MBUF_POOL_MDATA_RESET(bufPtr)
-
-#endif /* IX_OSAL_BACKWARD_BUFFER_MGT_H */
+++ /dev/null
-/**
- * This file is intended to provide backward
- * compatibility for main osService/OSSL
- * APIs.
- *
- * It shall be phased out gradually and users
- * are strongly recommended to use IX_OSAL API.
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IX_OSAL_BACKWARD_CACHE_MMU_H
-#define IX_OSAL_BACKWARD_CACHE_MMU_H
-
-#ifdef IX_OSAL_CACHED
-#define IX_ACC_CACHE_ENABLED
-#endif
-
-#define IX_XSCALE_CACHE_LINE_SIZE IX_OSAL_CACHE_LINE_SIZE
-
-#define IX_ACC_DRV_DMA_MALLOC(size) IX_OSAL_CACHE_DMA_MALLOC(size)
-
-#define IX_ACC_DRV_DMA_FREE(ptr,size) IX_OSAL_CACHE_DMA_FREE(ptr)
-
-#define IX_MMU_VIRTUAL_TO_PHYSICAL_TRANSLATION(addr) IX_OSAL_MMU_VIRT_TO_PHYS(addr)
-
-#define IX_MMU_PHYSICAL_TO_VIRTUAL_TRANSLATION(addr) IX_OSAL_MMU_PHYS_TO_VIRT(addr)
-
-#define IX_ACC_DATA_CACHE_INVALIDATE(addr,size) IX_OSAL_CACHE_INVALIDATE(addr, size)
-
-#define IX_ACC_DATA_CACHE_FLUSH(addr,size) IX_OSAL_CACHE_FLUSH(addr,size)
-
-#endif /* IX_OSAL_BACKWARD_CACHE_MMU_H */
+++ /dev/null
-/**
- * This file is intended to provide backward
- * compatibility for main osService/OSSL
- * APIs.
- *
- * It shall be phased out gradually and users
- * are strongly recommended to use IX_OSAL API.
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#ifndef IX_OSAL_BACKWARD_MEM_MAP_H
-#define IX_OSAL_BACKWARD_MEM_MAP_H
-
-#include "IxOsal.h"
-
-#define IX_OSSERV_SWAP_LONG(wData) IX_OSAL_SWAP_LONG(wData)
-#define IX_OSSERV_SWAP_SHORT(sData) IX_OSAL_SWAP_SHORT(sData)
-
-#define IX_OSSERV_SWAP_SHORT_ADDRESS(sAddr) IX_OSAL_SWAP_SHORT_ADDRESS(sAddr)
-#define IX_OSSERV_SWAP_BYTE_ADDRESS(bAddr) IX_OSAL_SWAP_BYTE_ADDRESS(bAddr)
-
-#define IX_OSSERV_BE_XSTOBUSL(wData) IX_OSAL_BE_XSTOBUSL(wData)
-#define IX_OSSERV_BE_XSTOBUSS(sData) IX_OSAL_BE_XSTOBUSS(sData)
-#define IX_OSSERV_BE_XSTOBUSB(bData) IX_OSAL_BE_XSTOBUSB(bData)
-#define IX_OSSERV_BE_BUSTOXSL(wData) IX_OSAL_BE_BUSTOXSL(wData)
-#define IX_OSSERV_BE_BUSTOXSS(sData) IX_OSAL_BE_BUSTOXSS(sData)
-#define IX_OSSERV_BE_BUSTOXSB(bData) IX_OSAL_BE_BUSTOXSB(bData)
-
-#define IX_OSSERV_LE_AC_XSTOBUSL(wAddr) IX_OSAL_LE_AC_XSTOBUSL(wAddr)
-#define IX_OSSERV_LE_AC_XSTOBUSS(sAddr) IX_OSAL_LE_AC_XSTOBUSS(sAddr)
-#define IX_OSSERV_LE_AC_XSTOBUSB(bAddr) IX_OSAL_LE_AC_XSTOBUSB(bAddr)
-#define IX_OSSERV_LE_AC_BUSTOXSL(wAddr) IX_OSAL_LE_AC_BUSTOXSL(wAddr)
-#define IX_OSSERV_LE_AC_BUSTOXSS(sAddr) IX_OSAL_LE_AC_BUSTOXSS(sAddr)
-#define IX_OSSERV_LE_AC_BUSTOXSB(bAddr) IX_OSAL_LE_AC_BUSTOXSB(bAddr)
-
-#define IX_OSSERV_LE_DC_XSTOBUSL(wData) IX_OSAL_LE_DC_XSTOBUSL(wData)
-#define IX_OSSERV_LE_DC_XSTOBUSS(sData) IX_OSAL_LE_DC_XSTOBUSS(sData)
-#define IX_OSSERV_LE_DC_XSTOBUSB(bData) IX_OSAL_LE_DC_XSTOBUSB(bData)
-#define IX_OSSERV_LE_DC_BUSTOXSL(wData) IX_OSAL_LE_DC_BUSTOXSL(wData)
-#define IX_OSSERV_LE_DC_BUSTOXSS(sData) IX_OSAL_LE_DC_BUSTOXSS(sData)
-#define IX_OSSERV_LE_DC_BUSTOXSB(bData) IX_OSAL_LE_DC_BUSTOXSB(bData)
-
-#define IX_OSSERV_READ_LONG(wAddr) IX_OSAL_READ_LONG(wAddr)
-#define IX_OSSERV_READ_SHORT(sAddr) IX_OSAL_READ_SHORT(sAddr)
-#define IX_OSSERV_READ_BYTE(bAddr) IX_OSAL_READ_BYTE(bAddr)
-#define IX_OSSERV_WRITE_LONG(wAddr, wData) IX_OSAL_WRITE_LONG(wAddr, wData)
-#define IX_OSSERV_WRITE_SHORT(sAddr, sData) IX_OSAL_WRITE_SHORT(sAddr, sData)
-#define IX_OSSERV_WRITE_BYTE(bAddr, bData) IX_OSAL_WRITE_BYTE(bAddr, bData)
-
-
-#define IX_OSSERV_READ_NPE_SHARED_LONG(wAddr) IX_OSAL_READ_BE_SHARED_LONG(wAddr)
-#define IX_OSSERV_READ_NPE_SHARED_SHORT(sAddr) IX_OSAL_READ_BE_SHARED_SHORT(sAddr)
-#define IX_OSSERV_WRITE_NPE_SHARED_LONG(wAddr, wData) IX_OSAL_WRITE_BE_SHARED_LONG(wAddr, wData)
-#define IX_OSSERV_WRITE_NPE_SHARED_SHORT(sAddr, sData) IX_OSAL_WRITE_BE_SHARED_SHORT(sAddr, sData)
-
-#define IX_OSSERV_SWAP_NPE_SHARED_LONG(wData) IX_OSAL_SWAP_BE_SHARED_LONG(wData)
-#define IX_OSSERV_SWAP_NPE_SHARED_SHORT(sData) IX_OSAL_SWAP_BE_SHARED_SHORT(sData)
-
-
-/* Map osServ address/size */
-#define IX_OSSERV_QMGR_MAP_SIZE IX_OSAL_IXP400_QMGR_MAP_SIZE
-#define IX_OSSERV_EXP_REG_MAP_SIZE IX_OSAL_IXP400_EXP_REG_MAP_SIZE
-#define IX_OSSERV_UART1_MAP_SIZE IX_OSAL_IXP400_UART1_MAP_SIZE
-#define IX_OSSERV_UART2_MAP_SIZE IX_OSAL_IXP400_UART2_MAP_SIZE
-#define IX_OSSERV_PMU_MAP_SIZE IX_OSAL_IXP400_PMU_MAP_SIZE
-#define IX_OSSERV_OSTS_MAP_SIZE IX_OSAL_IXP400_OSTS_MAP_SIZE
-#define IX_OSSERV_NPEA_MAP_SIZE IX_OSAL_IXP400_NPEA_MAP_SIZE
-#define IX_OSSERV_NPEB_MAP_SIZE IX_OSAL_IXP400_NPEB_MAP_SIZE
-#define IX_OSSERV_NPEC_MAP_SIZE IX_OSAL_IXP400_NPEC_MAP_SIZE
-#define IX_OSSERV_ETHA_MAP_SIZE IX_OSAL_IXP400_ETHA_MAP_SIZE
-#define IX_OSSERV_ETHB_MAP_SIZE IX_OSAL_IXP400_ETHB_MAP_SIZE
-#define IX_OSSERV_USB_MAP_SIZE IX_OSAL_IXP400_USB_MAP_SIZE
-#define IX_OSSERV_GPIO_MAP_SIZE IX_OSAL_IXP400_GPIO_MAP_SIZE
-#define IX_OSSERV_EXP_BUS_MAP_SIZE IX_OSAL_IXP400_EXP_BUS_MAP_SIZE
-#define IX_OSSERV_EXP_BUS_CS0_MAP_SIZE IX_OSAL_IXP400_EXP_BUS_CS0_MAP_SIZE
-#define IX_OSSERV_EXP_BUS_CS1_MAP_SIZE IX_OSAL_IXP400_EXP_BUS_CS1_MAP_SIZE
-#define IX_OSSERV_EXP_BUS_CS4_MAP_SIZE IX_OSAL_IXP400_EXP_BUS_CS4_MAP_SIZE
-
-
-#define IX_OSSERV_GPIO_PHYS_BASE IX_OSAL_IXP400_GPIO_PHYS_BASE
-#define IX_OSSERV_UART1_PHYS_BASE IX_OSAL_IXP400_UART1_PHYS_BASE
-#define IX_OSSERV_UART2_PHYS_BASE IX_OSAL_IXP400_UART2_PHYS_BASE
-#define IX_OSSERV_ETHA_PHYS_BASE IX_OSAL_IXP400_ETHA_PHYS_BASE
-#define IX_OSSERV_ETHB_PHYS_BASE IX_OSAL_IXP400_ETHB_PHYS_BASE
-#define IX_OSSERV_NPEA_PHYS_BASE IX_OSAL_IXP400_NPEA_PHYS_BASE
-#define IX_OSSERV_NPEB_PHYS_BASE IX_OSAL_IXP400_NPEB_PHYS_BASE
-#define IX_OSSERV_NPEC_PHYS_BASE IX_OSAL_IXP400_NPEC_PHYS_BASE
-#define IX_OSSERV_PERIPHERAL_PHYS_BASE IX_OSAL_IXP400_PERIPHERAL_PHYS_BASE
-#define IX_OSSERV_QMGR_PHYS_BASE IX_OSAL_IXP400_QMGR_PHYS_BASE
-#define IX_OSSERV_OSTS_PHYS_BASE IX_OSAL_IXP400_OSTS_PHYS_BASE
-#define IX_OSSERV_USB_PHYS_BASE IX_OSAL_IXP400_USB_PHYS_BASE
-#define IX_OSSERV_EXP_BUS_PHYS_BASE IX_OSAL_IXP400_EXP_BUS_PHYS_BASE
-#define IX_OSSERV_EXP_BUS_BOOT_PHYS_BASE IX_OSAL_IXP400_EXP_BUS_BOOT_PHYS_BASE
-#define IX_OSSERV_EXP_BUS_CS0_PHYS_BASE IX_OSAL_IXP400_EXP_BUS_CS0_PHYS_BASE
-#define IX_OSSERV_EXP_BUS_CS1_PHYS_BASE IX_OSAL_IXP400_EXP_BUS_CS1_PHYS_BASE
-#define IX_OSSERV_EXP_BUS_CS4_PHYS_BASE IX_OSAL_IXP400_EXP_BUS_CS4_PHYS_BASE
-#define IX_OSSERV_EXP_BUS_REGS_PHYS_BASE IX_OSAL_IXP400_EXP_BUS_REGS_PHYS_BASE
-
-#define IX_OSSERV_MEM_MAP(physAddr, size) IX_OSAL_MEM_MAP(physAddr, size)
-
-#define IX_OSSERV_MEM_UNMAP(virtAddr) IX_OSAL_MEM_UNMAP(virtAddr)
-
-#endif /* IX_OSAL_BACKWARD_MEM_MAP_H */
+++ /dev/null
-/**
- * This file is intended to provide backward
- * compatibility for main osService/OSSL
- * APIs.
- *
- * It shall be phased out gradually and users
- * are strongly recommended to use IX_OSAL API.
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IX_OSAL_BACKWARD_OSSERVICES_H
-#define IX_OSAL_BACKWARD_OSSERVICES_H
-
-#ifndef __vxworks
-typedef UINT32 IX_IRQ_STATUS;
-#else
-typedef int IX_IRQ_STATUS;
-#endif
-
-typedef IxOsalMutex IxMutex;
-
-typedef IxOsalFastMutex IxFastMutex;
-
-typedef IxOsalVoidFnVoidPtr IxVoidFnVoidPtr;
-
-typedef IxOsalVoidFnPtr IxVoidFnPtr;
-
-
-#define LOG_NONE IX_OSAL_LOG_LVL_NONE
-#define LOG_USER IX_OSAL_LOG_LVL_USER
-#define LOG_FATAL IX_OSAL_LOG_LVL_FATAL
-#define LOG_ERROR IX_OSAL_LOG_LVL_ERROR
-#define LOG_WARNING IX_OSAL_LOG_LVL_WARNING
-#define LOG_MESSAGE IX_OSAL_LOG_LVL_MESSAGE
-#define LOG_DEBUG1 IX_OSAL_LOG_LVL_DEBUG1
-#define LOG_DEBUG2 IX_OSAL_LOG_LVL_DEBUG2
-#define LOG_DEBUG3 IX_OSAL_LOG_LVL_DEBUG3
-#ifndef __vxworks
-#define LOG_ALL IX_OSAL_LOG_LVL_ALL
-#endif
-
-PUBLIC IX_STATUS
-ixOsServIntBind (int level, void (*routine) (void *), void *parameter);
-
-PUBLIC IX_STATUS ixOsServIntUnbind (int level);
-
-
-PUBLIC int ixOsServIntLock (void);
-
-PUBLIC void ixOsServIntUnlock (int lockKey);
-
-
-PUBLIC int ixOsServIntLevelSet (int level);
-
-PUBLIC IX_STATUS ixOsServMutexInit (IxMutex * mutex);
-
-PUBLIC IX_STATUS ixOsServMutexLock (IxMutex * mutex);
-
-PUBLIC IX_STATUS ixOsServMutexUnlock (IxMutex * mutex);
-
-PUBLIC IX_STATUS ixOsServMutexDestroy (IxMutex * mutex);
-
-PUBLIC IX_STATUS ixOsServFastMutexInit (IxFastMutex * mutex);
-
-PUBLIC IX_STATUS ixOsServFastMutexTryLock (IxFastMutex * mutex);
-
-PUBLIC IX_STATUS ixOsServFastMutexUnlock (IxFastMutex * mutex);
-
-PUBLIC int
-ixOsServLog (int level, char *format, int arg1, int arg2, int arg3, int arg4,
- int arg5, int arg6);
-
-
-PUBLIC int ixOsServLogLevelSet (int level);
-
-PUBLIC void ixOsServSleep (int microseconds);
-
-PUBLIC void ixOsServTaskSleep (int milliseconds);
-
-PUBLIC unsigned int ixOsServTimestampGet (void);
-
-
-PUBLIC void ixOsServUnload (void);
-
-PUBLIC void ixOsServYield (void);
-
-#endif
-/* IX_OSAL_BACKWARD_OSSERVICES_H */
+++ /dev/null
-/**
- * This file is intended to provide backward
- * compatibility for main osService/OSSL
- * APIs.
- *
- * It shall be phased out gradually and users
- * are strongly recommended to use IX_OSAL API.
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IX_OSAL_BACKWARD_OSSL_H
-#define IX_OSAL_BACKWARD_OSSL_H
-
-
-typedef IxOsalThread ix_ossl_thread_t;
-
-typedef IxOsalSemaphore ix_ossl_sem_t;
-
-typedef IxOsalMutex ix_ossl_mutex_t;
-
-typedef IxOsalTimeval ix_ossl_time_t;
-
-
-/* Map sub-fields for ix_ossl_time_t */
-#define tv_sec secs
-#define tv_nec nsecs
-
-
-typedef IX_STATUS ix_error;
-
-typedef UINT32 ix_ossl_thread_priority;
-
-typedef UINT32 ix_uint32;
-
-
-#define IX_OSSL_ERROR_SUCCESS IX_SUCCESS
-
-#define IX_ERROR_SUCCESS IX_SUCCESS
-
-
-typedef enum
-{
- IX_OSSL_SEM_UNAVAILABLE = 0,
- IX_OSSL_SEM_AVAILABLE
-} ix_ossl_sem_state;
-
-
-typedef enum
-{
- IX_OSSL_MUTEX_UNLOCK = 0,
- IX_OSSL_MUTEX_LOCK
-} ix_ossl_mutex_state;
-
-
-typedef IxOsalVoidFnVoidPtr ix_ossl_thread_entry_point_t;
-
-
-#define IX_OSSL_THREAD_PRI_HIGH 90
-#define IX_OSSL_THREAD_PRI_MEDIUM 160
-#define IX_OSSL_THREAD_PRI_LOW 240
-
-
-#define IX_OSSL_WAIT_FOREVER IX_OSAL_WAIT_FOREVER
-
-#define IX_OSSL_WAIT_NONE IX_OSAL_WAIT_NONE
-
-#define BILLION IX_OSAL_BILLION
-
-#define IX_OSSL_TIME_EQ(a,b) IX_OSAL_TIME_EQ(a,b)
-
-#define IX_OSSL_TIME_GT(a,b) IX_OSAL_TIME_GT(a,b)
-
-#define IX_OSSL_TIME_LT(a,b) IX_OSAL_TIME_LT(a,b)
-
-#define IX_OSSL_TIME_ADD(a,b) IX_OSAL_TIME_ADD(a,b)
-
-#define IX_OSSL_TIME_SUB(a,b) IX_OSAL_TIME_SUB(a,b)
-
-
-/* a is tick, b is timeval */
-#define IX_OSSL_TIME_CONVERT_TO_TICK(a,b) \
- (a) = IX_OSAL_TIMEVAL_TO_TICKS(b)
-
-
-
-
-PUBLIC IX_STATUS
-ixOsalOsIxp400BackwardOsslThreadCreate (IxOsalVoidFnVoidPtr entryPoint,
- void *arg, IxOsalThread * ptrThread);
-
-#define ix_ossl_thread_create(entryPoint, arg, ptrTid) \
- ixOsalOsIxp400BackwardOsslThreadCreate(entryPoint, arg, ptrTid)
-
-
-/* void ix_ossl_thread_exit(ix_error retError, void* retObj) */
-#define ix_ossl_thread_exit(retError, retObj) \
- ixOsalThreadExit()
-
-
-PUBLIC IX_STATUS ixOsalOsIxp400BackwardOsslThreadKill (IxOsalThread tid);
-
-/* ix_error ix_ossl_thread_kill(tid) */
-#define ix_ossl_thread_kill(tid) \
- ixOsalOsIxp400BackwardOsslThreadKill(tid)
-
-
-PUBLIC IX_STATUS
-ixOsalOsIxp400BackwardOsslThreadSetPriority (IxOsalThread tid,
- UINT32 priority);
-
-
-/*
- * ix_error ix_ossl_thread_set_priority(ix_ossl_thread_t tid,
- * ix_ossl_thread_priority priority
- * );
- */
-
-#define ix_ossl_thread_set_priority(tid, priority) \
- ixOsalOsIxp400BackwardOsslThreadSetPriority(tid, priority)
-
-
-PUBLIC IX_STATUS ixOsalOsIxp400BackwardOsslTickGet (int *pticks);
-
-#define ix_ossl_tick_get(pticks) \
- ixOsalOsIxp400BackwardOsslTickGet(pticks)
-
-PUBLIC IX_STATUS ixOsalOsIxp400BackwardOsslThreadDelay (int ticks);
-
-#define ix_ossl_thread_delay(ticks) ixOsalOsIxp400BackwardOsslThreadDelay(ticks)
-
-
-
-/* ix_error ix_ossl_sem_init(int start_value, ix_ossl_sem_t* sid); */
-/* Note sid is a pointer to semaphore */
-#define ix_ossl_sem_init(value, sid) \
- ixOsalSemaphoreInit(sid, value)
-
-
-PUBLIC IX_STATUS
-ixOsalOsIxp400BackwardOsslSemaphoreWait (IxOsalSemaphore semaphore,
- INT32 timeout);
-
-
-/*
-ix_error ix_ossl_sem_take(
- ix_ossl_sem_t sid,
- ix_uint32 timeout
- );
-*/
-
-#define ix_ossl_sem_take( sid, timeout) \
- ixOsalOsIxp400BackwardOsslSemaphoreWait(sid, timeout)
-
-
-
-PUBLIC IX_STATUS
-ixOsalOsIxp400BackwardOsslSemaphorePost (IxOsalSemaphore sid);
-
-/*ix_error ix_ossl_sem_give(ix_ossl_sem_t sid); */
-#define ix_ossl_sem_give(sid) \
- ixOsalOsIxp400BackwardOsslSemaphorePost(sid);
-
-
-PUBLIC IX_STATUS ixOsalOsIxp400BackwardSemaphoreDestroy (IxOsalSemaphore sid);
-
-#define ix_ossl_sem_fini(sid) \
- ixOsalOsIxp400BackwardSemaphoreDestroy(sid)
-
-
-PUBLIC IX_STATUS
-ixOsalOsIxp400BackwardOsslMutexInit (ix_ossl_mutex_state start_state,
- IxOsalMutex * pMutex);
-
-
-/* ix_error ix_ossl_mutex_init(ix_ossl_mutex_state start_state, ix_ossl_mutex_t* mid); */
-#define ix_ossl_mutex_init(start_state, pMutex) \
- ixOsalOsIxp400BackwardOsslMutexInit(start_state, pMutex)
-
-
-PUBLIC IX_STATUS
-ixOsalOsIxp400BackwardOsslMutexLock (IxOsalMutex mid, INT32 timeout);
-
-/*
-ix_error ix_ossl_mutex_lock(
- ix_ossl_mutex_t mid,
- ix_uint32 timeout
- );
-*/
-#define ix_ossl_mutex_lock(mid, timeout) \
- ixOsalOsIxp400BackwardOsslMutexLock(mid, timout)
-
-
-PUBLIC IX_STATUS ixOsalOsIxp400BackwardOsslMutexUnlock (IxOsalMutex mid);
-
-/* ix_error ix_ossl_mutex_unlock(ix_ossl_mutex_t mid); */
-#define ix_ossl_mutex_unlock(mid) \
- ixOsalOsIxp400BackwardOsslMutexUnlock(mid)
-
-PUBLIC IX_STATUS ixOsalOsIxp400BackwardOsslMutexDestroy (IxOsalMutex mid);
-
-#define ix_ossl_mutex_fini(mid) \
- ixOsalOsIxp400BackwardOsslMutexDestroy(mid);
-
-#define ix_ossl_sleep(sleeptime_ms) \
- ixOsalSleep(sleeptime_ms)
-
-PUBLIC IX_STATUS ixOsalOsIxp400BackwardOsslSleepTick (UINT32 ticks);
-
-#define ix_ossl_sleep_tick(sleeptime_ticks) \
- ixOsalOsIxp400BackwardOsslSleepTick(sleeptime_ticks)
-
-
-PUBLIC IX_STATUS ixOsalOsIxp400BackwardOsslTimeGet (IxOsalTimeval * pTv);
-
-#define ix_ossl_time_get(pTv) \
- ixOsalOsIxp400BackwardOsslTimeGet(pTv)
-
-
-typedef UINT32 ix_ossl_size_t;
-
-#define ix_ossl_malloc(arg_size) \
- ixOsalMemAlloc(arg_size)
-
-#define ix_ossl_free(arg_pMemory) \
- ixOsalMemFree(arg_pMemory)
-
-
-#define ix_ossl_memcpy(arg_pDest, arg_pSrc,arg_Count) \
- ixOsalMemCopy(arg_pDest, arg_pSrc,arg_Count)
-
-#define ix_ossl_memset(arg_pDest, arg_pChar, arg_Count) \
- ixOsalMemSet(arg_pDest, arg_pChar, arg_Count)
-
-
-#endif /* IX_OSAL_BACKWARD_OSSL_H */
+++ /dev/null
-/**
- * @file IxOsalBufferMgt.h
- *
- * @brief OSAL Buffer pool management and buffer management definitions.
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-/* @par
- * -- Copyright Notice --
- *
- * @par
- * Copyright 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994
- * The Regents of the University of California. All rights reserved.
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsalBufferMgt_H
-#define IxOsalBufferMgt_H
-
-#include "IxOsal.h"
-/**
- * @defgroup IxOsalBufferMgt OSAL Buffer Management Module.
- *
- * @brief Buffer management module for IxOsal
- *
- * @{
- */
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_MAX_POOLS
- *
- * @brief The maximum number of pools that can be allocated, must be
- * a multiple of 32 as required by implementation logic.
- * @note This can safely be increased if more pools are required.
- */
-#define IX_OSAL_MBUF_MAX_POOLS 32
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_NAME_LEN
- *
- * @brief The maximum string length of the pool name
- */
-#define IX_OSAL_MBUF_POOL_NAME_LEN 64
-
-
-
-/**
- * Define IX_OSAL_MBUF
- */
-
-
-/* forward declaration of internal structure */
-struct __IXP_BUF;
-
-/*
- * OS can define it in IxOsalOs.h to skip the following
- * definition.
- */
-#ifndef IX_OSAL_ATTRIBUTE_ALIGN32
-#define IX_OSAL_ATTRIBUTE_ALIGN32 __attribute__ ((aligned(32)))
-#endif
-
-/* release v1.4 backward compatible definitions */
-struct __IX_MBUF
-{
- struct __IXP_BUF *ix_next IX_OSAL_ATTRIBUTE_ALIGN32;
- struct __IXP_BUF *ix_nextPacket;
- UINT8 *ix_data;
- UINT32 ix_len;
- unsigned char ix_type;
- unsigned char ix_flags;
- unsigned short ix_reserved;
- UINT32 ix_rsvd;
- UINT32 ix_PktLen;
- void *ix_priv;
-};
-
-struct __IX_CTRL
-{
- UINT32 ix_reserved[2]; /**< Reserved field */
- UINT32 ix_signature; /**< Field to indicate if buffers are allocated by the system */
- UINT32 ix_allocated_len; /**< Allocated buffer length */
- UINT32 ix_allocated_data; /**< Allocated buffer data pointer */
- void *ix_pool; /**< pointer to the buffer pool */
- struct __IXP_BUF *ix_chain; /**< chaining */
- void *ix_osbuf_ptr; /**< Storage for OS-specific buffer pointer */
-};
-
-struct __IX_NE_SHARED
-{
- UINT32 reserved[8] IX_OSAL_ATTRIBUTE_ALIGN32; /**< Reserved area for NPE Service-specific usage */
-};
-
-
-/*
- * IXP buffer structure
- */
-typedef struct __IXP_BUF
-{
- struct __IX_MBUF ix_mbuf IX_OSAL_ATTRIBUTE_ALIGN32; /**< buffer header */
- struct __IX_CTRL ix_ctrl; /**< buffer management */
- struct __IX_NE_SHARED ix_ne; /**< Reserved area for NPE Service-specific usage*/
-} IXP_BUF;
-
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def typedef IX_OSAL_MBUF
- *
- * @brief Generic IXP mbuf format.
- */
-typedef IXP_BUF IX_OSAL_MBUF;
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_IXP_NEXT_BUFFER_IN_PKT_PTR(m_blk_ptr)
- *
- * @brief Return pointer to the next mbuf in a single packet
- */
-#define IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(m_blk_ptr) \
- (m_blk_ptr)->ix_mbuf.ix_next
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m_blk_ptr)
- *
- * @brief Return pointer to the next packet in the chain
- */
-#define IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m_blk_ptr) \
- (m_blk_ptr)->ix_mbuf.ix_nextPacket
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_MDATA(m_blk_ptr)
- *
- * @brief Return pointer to the data in the mbuf
- */
-#define IX_OSAL_MBUF_MDATA(m_blk_ptr) (m_blk_ptr)->ix_mbuf.ix_data
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_MLEN(m_blk_ptr)
- *
- * @brief Return the data length
- */
-#define IX_OSAL_MBUF_MLEN(m_blk_ptr) \
- (m_blk_ptr)->ix_mbuf.ix_len
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_MTYPE(m_blk_ptr)
- *
- * @brief Return the data type in the mbuf
- */
-#define IX_OSAL_MBUF_MTYPE(m_blk_ptr) \
- (m_blk_ptr)->ix_mbuf.ix_type
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_FLAGS(m_blk_ptr)
- *
- * @brief Return the buffer flags
- */
-#define IX_OSAL_MBUF_FLAGS(m_blk_ptr) \
- (m_blk_ptr)->ix_mbuf.ix_flags
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_NET_POOL(m_blk_ptr)
- *
- * @brief Return pointer to a network pool
- */
-#define IX_OSAL_MBUF_NET_POOL(m_blk_ptr) \
- (m_blk_ptr)->ix_ctrl.ix_pool
-
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_PKT_LEN(m_blk_ptr)
- *
- * @brief Return the total length of all the data in
- * the mbuf chain for this packet
- */
-#define IX_OSAL_MBUF_PKT_LEN(m_blk_ptr) \
- (m_blk_ptr)->ix_mbuf.ix_PktLen
-
-
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_PRIV(m_blk_ptr)
- *
- * @brief Return the private field
- */
-#define IX_OSAL_MBUF_PRIV(m_blk_ptr) \
- (m_blk_ptr)->ix_mbuf.ix_priv
-
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_SIGNATURE(m_blk_ptr)
- *
- * @brief Return the signature field of IX_OSAL_MBUF
- */
-#define IX_OSAL_MBUF_SIGNATURE(m_blk_ptr) \
- (m_blk_ptr)->ix_ctrl.ix_signature
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_OSBUF_PTR(m_blk_ptr)
- *
- * @brief Return ix_osbuf_ptr field of IX_OSAL_MBUF, which is used to store OS-specific buffer pointer during a buffer conversion.
- */
-#define IX_OSAL_MBUF_OSBUF_PTR(m_blk_ptr) \
- (m_blk_ptr)->ix_ctrl.ix_osbuf_ptr
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(m_blk_ptr)
- *
- * @brief Return the allocated buffer size
- */
-#define IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(m_blk_ptr) \
- (m_blk_ptr)->ix_ctrl.ix_allocated_len
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(m_blk_ptr)
- *
- * @brief Return the allocated buffer pointer
- */
-#define IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(m_blk_ptr) \
- (m_blk_ptr)->ix_ctrl.ix_allocated_data
-
-
-
-/* Name length */
-#define IX_OSAL_MBUF_POOL_NAME_LEN 64
-
-
-/****************************************************
- * Macros for buffer pool management
- ****************************************************/
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_FREE_COUNT(m_pool_ptr
- *
- * @brief Return the total number of freed buffers left in the pool.
- */
-#define IX_OSAL_MBUF_POOL_FREE_COUNT(m_pool_ptr) \
- ixOsalBuffPoolFreeCountGet(m_pool_ptr)
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_SIZE_ALIGN
- *
- * @brief This macro takes an integer as an argument and
- * rounds it up to be a multiple of the memory cache-line
- * size.
- *
- * @param int [in] size - the size integer to be rounded up
- *
- * @return int - the size, rounded up to a multiple of
- * the cache-line size
- */
-#define IX_OSAL_MBUF_POOL_SIZE_ALIGN(size) \
- ((((size) + (IX_OSAL_CACHE_LINE_SIZE - 1)) / \
- IX_OSAL_CACHE_LINE_SIZE) * \
- IX_OSAL_CACHE_LINE_SIZE)
-
-/* Don't use this directly, use macro */
-PUBLIC UINT32 ixOsalBuffPoolMbufAreaSizeGet (int count);
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_MBUF_AREA_SIZE_ALIGNED
- *
- * @brief This macro calculates, from the number of mbufs required, the
- * size of the memory area required to contain the mbuf headers for the
- * buffers in the pool. The size to be used for each mbuf header is
- * rounded up to a multiple of the cache-line size, to ensure
- * each mbuf header aligns on a cache-line boundary.
- * This macro is used by IX_OSAL_MBUF_POOL_MBUF_AREA_ALLOC()
- *
- * @param int [in] count - the number of buffers the pool will contain
- *
- * @return int - the total size required for the pool mbuf area (aligned)
- */
-#define IX_OSAL_MBUF_POOL_MBUF_AREA_SIZE_ALIGNED(count) \
- ixOsalBuffPoolMbufAreaSizeGet(count)
-
-
-/* Don't use this directly, use macro */
-PUBLIC UINT32 ixOsalBuffPoolDataAreaSizeGet (int count, int size);
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_DATA_AREA_SIZE_ALIGNED
- *
- * @brief This macro calculates, from the number of mbufs required and the
- * size of the data portion for each mbuf, the size of the data memory area
- * required. The size is adjusted to ensure alignment on cache line boundaries.
- * This macro is used by IX_OSAL_MBUF_POOL_DATA_AREA_ALLOC()
- *
- *
- * @param int [in] count - The number of mbufs in the pool.
- * @param int [in] size - The desired size for each mbuf data portion.
- * This size will be rounded up to a multiple of the
- * cache-line size to ensure alignment on cache-line
- * boundaries for each data block.
- *
- * @return int - the total size required for the pool data area (aligned)
- */
-#define IX_OSAL_MBUF_POOL_DATA_AREA_SIZE_ALIGNED(count, size) \
- ixOsalBuffPoolDataAreaSizeGet((count), (size))
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_MBUF_AREA_ALLOC
- *
- * @brief Allocates the memory area needed for the number of mbuf headers
- * specified by <i>count</i>.
- * This macro ensures the mbuf headers align on cache line boundaries.
- * This macro evaluates to a pointer to the memory allocated.
- *
- * @param int [in] count - the number of mbufs the pool will contain
- * @param int [out] memAreaSize - the total amount of memory allocated
- *
- * @return void * - a pointer to the allocated memory area
- */
-#define IX_OSAL_MBUF_POOL_MBUF_AREA_ALLOC(count, memAreaSize) \
- IX_OSAL_CACHE_DMA_MALLOC((memAreaSize = \
- IX_OSAL_MBUF_POOL_MBUF_AREA_SIZE_ALIGNED(count)))
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_DATA_AREA_ALLOC
- *
- * @brief Allocates the memory pool for the data portion of the pool mbufs.
- * The number of mbufs is specified by <i>count</i>. The size of the data
- * portion of each mbuf is specified by <i>size</i>.
- * This macro ensures the mbufs are aligned on cache line boundaries
- * This macro evaluates to a pointer to the memory allocated.
- *
- * @param int [in] count - the number of mbufs the pool will contain
- * @param int [in] size - the desired size (in bytes) required for the data
- * portion of each mbuf. Note that this size may be
- * rounded up to ensure alignment on cache-line
- * boundaries.
- * @param int [out] memAreaSize - the total amount of memory allocated
- *
- * @return void * - a pointer to the allocated memory area
- */
-#define IX_OSAL_MBUF_POOL_DATA_AREA_ALLOC(count, size, memAreaSize) \
- IX_OSAL_CACHE_DMA_MALLOC((memAreaSize = \
- IX_OSAL_MBUF_POOL_DATA_AREA_SIZE_ALIGNED(count,size)))
-
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_INIT
- *
- * @brief Wrapper macro for ixOsalPoolInit()
- * See function description below for details.
- */
-#define IX_OSAL_MBUF_POOL_INIT(count, size, name) \
- ixOsalPoolInit((count), (size), (name))
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_NO_ALLOC_POOL_INIT
- *
- * @return Pointer to the new pool or NULL if the initialization failed.
- *
- * @brief Wrapper macro for ixOsalNoAllocPoolInit()
- * See function description below for details.
- *
- */
-#define IX_OSAL_MBUF_NO_ALLOC_POOL_INIT(bufPtr, dataPtr, count, size, name) \
- ixOsalNoAllocPoolInit( (bufPtr), (dataPtr), (count), (size), (name))
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_GET
- *
- * @brief Wrapper macro for ixOsalMbufAlloc()
- * See function description below for details.
- */
-#define IX_OSAL_MBUF_POOL_GET(poolPtr) \
- ixOsalMbufAlloc(poolPtr)
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_PUT
- *
- * @brief Wrapper macro for ixOsalMbufFree()
- * See function description below for details.
- */
-#define IX_OSAL_MBUF_POOL_PUT(bufPtr) \
- ixOsalMbufFree(bufPtr)
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_PUT_CHAIN
- *
- * @brief Wrapper macro for ixOsalMbufChainFree()
- * See function description below for details.
- */
-#define IX_OSAL_MBUF_POOL_PUT_CHAIN(bufPtr) \
- ixOsalMbufChainFree(bufPtr)
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_SHOW
- *
- * @brief Wrapper macro for ixOsalMbufPoolShow()
- * See function description below for details.
- */
-#define IX_OSAL_MBUF_POOL_SHOW(poolPtr) \
- ixOsalMbufPoolShow(poolPtr)
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_MDATA_RESET
- *
- * @brief Wrapper macro for ixOsalMbufDataPtrReset()
- * See function description below for details.
- */
-#define IX_OSAL_MBUF_POOL_MDATA_RESET(bufPtr) \
- ixOsalMbufDataPtrReset(bufPtr)
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_UNINIT
- *
- * @brief Wrapper macro for ixOsalBuffPoolUninit()
- * See function description below for details.
- */
-#define IX_OSAL_MBUF_POOL_UNINIT(m_pool_ptr) \
- ixOsalBuffPoolUninit(m_pool_ptr)
-
-/*
- * Include OS-specific bufferMgt definitions
- */
-#include "IxOsalOsBufferMgt.h"
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_CONVERT_OSBUF_TO_IXPBUF( osBufPtr, ixpBufPtr)
- *
- * @brief Convert pre-allocated os-specific buffer format to OSAL IXP_BUF (IX_OSAL_MBUF) format.
- * It is users' responsibility to provide pre-allocated and valid buffer pointers.
- * @param osBufPtr (in) - a pre-allocated os-specific buffer pointer.
- * @param ixpBufPtr (in)- a pre-allocated OSAL IXP_BUF pointer
- * @return None
- */
-#define IX_OSAL_CONVERT_OSBUF_TO_IXPBUF( osBufPtr, ixpBufPtr) \
- IX_OSAL_OS_CONVERT_OSBUF_TO_IXPBUF( osBufPtr, ixpBufPtr)
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_CONVERT_IXPBUF_TO_OSBUF( ixpBufPtr, osBufPtr)
- *
- * @brief Convert pre-allocated OSAL IXP_BUF (IX_OSAL_MBUF) format to os-specific buffer pointers.
- * @param ixpBufPtr (in) - OSAL IXP_BUF pointer
- * @param osBufPtr (out) - os-specific buffer pointer.
- * @return None
- */
-
-#define IX_OSAL_CONVERT_IXPBUF_TO_OSBUF( ixpBufPtr, osBufPtr) \
- IX_OSAL_OS_CONVERT_IXPBUF_TO_OSBUF( ixpBufPtr, osBufPtr)
-
-
-PUBLIC IX_OSAL_MBUF_POOL *ixOsalPoolInit (UINT32 count,
- UINT32 size, const char *name);
-
-PUBLIC IX_OSAL_MBUF_POOL *ixOsalNoAllocPoolInit (void *poolBufPtr,
- void *poolDataPtr,
- UINT32 count,
- UINT32 size,
- const char *name);
-
-PUBLIC IX_OSAL_MBUF *ixOsalMbufAlloc (IX_OSAL_MBUF_POOL * pool);
-
-PUBLIC IX_OSAL_MBUF *ixOsalMbufFree (IX_OSAL_MBUF * mbuf);
-
-PUBLIC void ixOsalMbufChainFree (IX_OSAL_MBUF * mbuf);
-
-PUBLIC void ixOsalMbufDataPtrReset (IX_OSAL_MBUF * mbuf);
-
-PUBLIC void ixOsalMbufPoolShow (IX_OSAL_MBUF_POOL * pool);
-
-PUBLIC IX_STATUS ixOsalBuffPoolUninit (IX_OSAL_MBUF_POOL * pool);
-
-PUBLIC UINT32 ixOsalBuffPoolFreeCountGet(IX_OSAL_MBUF_POOL * pool);
-
-
-/**
- * @} IxOsalBufferMgt
- */
-
-
-#endif /* IxOsalBufferMgt_H */
+++ /dev/null
-/**
- * @file IxOsalBufferMgtDefault.h
- *
- * @brief Default buffer pool management and buffer management
- * definitions.
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IX_OSAL_BUFFER_MGT_DEFAULT_H
-#define IX_OSAL_BUFFER_MGT_DEFAULT_H
-
-/**
- * @enum IxMbufPoolAllocationType
- * @brief Used to indicate how the pool memory was allocated
- */
-
-typedef enum
-{
- IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC = 0, /**< mbuf pool allocated by the system */
- IX_OSAL_MBUF_POOL_TYPE_USER_ALLOC /**< mbuf pool allocated by the user */
-} IxOsalMbufPoolAllocationType;
-
-
-/**
- * @brief Implementation of buffer pool structure for use with non-VxWorks OS
- */
-
-typedef struct
-{
- IX_OSAL_MBUF *nextFreeBuf; /**< Pointer to the next free mbuf */
- void *mbufMemPtr; /**< Pointer to the mbuf memory area */
- void *dataMemPtr; /**< Pointer to the data memory area */
- int bufDataSize; /**< The size of the data portion of each mbuf */
- int totalBufsInPool; /**< Total number of mbufs in the pool */
- int freeBufsInPool; /**< Number of free mbufs currently in the pool */
- int mbufMemSize; /**< The size of the pool mbuf memory area */
- int dataMemSize; /**< The size of the pool data memory area */
- char name[IX_OSAL_MBUF_POOL_NAME_LEN + 1]; /**< Descriptive name for pool */
- IxOsalMbufPoolAllocationType poolAllocType;
- unsigned int poolIdx; /**< Pool Index */
-} IxOsalMbufPool;
-
-typedef IxOsalMbufPool IX_OSAL_MBUF_POOL;
-
-
-PUBLIC IX_STATUS ixOsalBuffPoolUninit (IX_OSAL_MBUF_POOL * pool);
-
-
-#endif /* IX_OSAL_BUFFER_MGT_DEFAULT_H */
+++ /dev/null
-/**
- * @file IxOsalConfig.h
- *
- * @brief OSAL Configuration header file
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/*
- * This file contains user-editable fields for modules inclusion.
- */
-#ifndef IxOsalConfig_H
-#define IxOsalConfig_H
-
-
-/*
- * Note: in the future these config options may
- * become build time decision.
- */
-
-/* Choose cache */
-#define IX_OSAL_CACHED
-/* #define IX_OSAL_UNCACHED */
-
-
-/*
- * Select the module headers to include
- */
-#include "IxOsalIoMem.h" /* I/O Memory Management module API */
-#include "IxOsalBufferMgt.h" /* Buffer Management module API */
-
-/*
- * Select main platform header file to use
- */
-#include "IxOsalOem.h"
-
-
-
-#endif /* IxOsalConfig_H */
+++ /dev/null
-/**
- * @file IxOsalEndianess.h (Obsolete file)
- *
- * @brief Header file for determining system endianess and OS
- *
- * @par
- * @version $Revision: 1.1
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#ifndef IxOsalEndianess_H
-#define IxOsalEndianess_H
-
-#if defined (__vxworks) || defined (__linux)
-
-/* get ntohl/ntohs/htohl/htons macros and CPU definitions for VxWorks */
-/* #include <netinet/in.h> */
-
-#elif defined (__wince)
-
-/* get ntohl/ntohs/htohl/htons macros definitions for WinCE */
-#include <Winsock2.h>
-
-#else
-
-#error Unknown OS, please add a section with the include file for htonl/htons/ntohl/ntohs
-
-#endif /* vxworks or linux or wince */
-
-/* Compiler specific endianness selector - WARNING this works only with arm gcc, use appropriate defines with diab */
-
-#ifndef __wince
-
-#if defined (__ARMEL__)
-
-#ifndef __LITTLE_ENDIAN
-
-#define __LITTLE_ENDIAN
-
-#endif /* _LITTLE_ENDIAN */
-
-#elif defined (__ARMEB__) || CPU == SIMSPARCSOLARIS
-
-#ifndef __BIG_ENDIAN
-
-#define __BIG_ENDIAN
-
-#endif /* __BIG_ENDIAN */
-
-#else
-
-#error Error, could not identify target endianness
-
-#endif /* endianness selector no WinCE OSes */
-
-#else /* ndef __wince */
-
-#define __LITTLE_ENDIAN
-
-#endif /* def __wince */
-
-
-/* OS mode selector */
-#if defined (__vxworks) && defined (__LITTLE_ENDIAN)
-
-#define IX_OSAL_VXWORKS_LE
-
-#elif defined (__vxworks) && defined (__BIG_ENDIAN)
-
-#define IX_OSAL_VXWORKS_BE
-
-#elif defined (__linux) && defined (__BIG_ENDIAN)
-
-#define IX_OSAL_LINUX_BE
-
-#elif defined (__linux) && defined (__LITTLE_ENDIAN)
-
-#define IX_OSAL_LINUX_LE
-
-#elif defined (BOOTLOADER_BLD) && defined (__LITTLE_ENDIAN)
-
-#define IX_OSAL_EBOOT_LE
-
-#elif defined (__wince) && defined (__LITTLE_ENDIAN)
-
-#define IX_OSAL_WINCE_LE
-
-#else
-
-#error Unknown OS/Endianess combination - only vxWorks BE LE, Linux BE LE, WinCE BE LE are supported
-
-#endif /* mode selector */
-
-
-
-#endif /* IxOsalEndianess_H */
+++ /dev/null
-/*
- * @file IxOsalIoMem.h
- * @author Intel Corporation
- * @date 25-08-2004
- *
- * @brief description goes here
- */
-
-/**
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsalIoMem_H
-#define IxOsalIoMem_H
-
-
-/*
- * Decide OS and Endianess, such as IX_OSAL_VXWORKS_LE.
- */
-#include "IxOsalEndianess.h"
-
-/**
- * @defgroup IxOsalIoMem Osal IoMem module
- *
- * @brief I/O memory and endianess support.
- *
- * @{
- */
-
-/* Low-level conversion macros - DO NOT USE UNLESS ABSOLUTELY NEEDED */
-#ifndef __wince
-
-
-/*
- * Private function to swap word
- */
-#ifdef __XSCALE__
-static __inline__ UINT32
-ixOsalCoreWordSwap (UINT32 wordIn)
-{
- /*
- * Storage for the swapped word
- */
- UINT32 wordOut;
-
- /*
- * wordIn = A, B, C, D
- */
- __asm__ (" eor r1, %1, %1, ror #16;" /* R1 = A^C, B^D, C^A, D^B */
- " bic r1, r1, #0x00ff0000;" /* R1 = A^C, 0 , C^A, D^B */
- " mov %0, %1, ror #8;" /* wordOut = D, A, B, C */
- " eor %0, %0, r1, lsr #8;" /* wordOut = D, C, B, A */
- : "=r" (wordOut): "r" (wordIn):"r1");
-
- return wordOut;
-}
-
-#define IX_OSAL_SWAP_LONG(wData) (ixOsalCoreWordSwap(wData))
-#else
-#define IX_OSAL_SWAP_LONG(wData) ((wData >> 24) | (((wData >> 16) & 0xFF) << 8) | (((wData >> 8) & 0xFF) << 16) | ((wData & 0xFF) << 24))
-#endif
-
-#else /* ndef __wince */
-#define IX_OSAL_SWAP_LONG(wData) ((((UINT32)wData << 24) | ((UINT32)wData >> 24)) | (((wData << 8) & 0xff0000) | ((wData >> 8) & 0xff00)))
-#endif /* ndef __wince */
-
-#define IX_OSAL_SWAP_SHORT(sData) ((sData >> 8) | ((sData & 0xFF) << 8))
-#define IX_OSAL_SWAP_SHORT_ADDRESS(sAddr) ((sAddr) ^ 0x2)
-#define IX_OSAL_SWAP_BYTE_ADDRESS(bAddr) ((bAddr) ^ 0x3)
-
-#define IX_OSAL_BE_XSTOBUSL(wData) (wData)
-#define IX_OSAL_BE_XSTOBUSS(sData) (sData)
-#define IX_OSAL_BE_XSTOBUSB(bData) (bData)
-#define IX_OSAL_BE_BUSTOXSL(wData) (wData)
-#define IX_OSAL_BE_BUSTOXSS(sData) (sData)
-#define IX_OSAL_BE_BUSTOXSB(bData) (bData)
-
-#define IX_OSAL_LE_AC_XSTOBUSL(wAddr) (wAddr)
-#define IX_OSAL_LE_AC_XSTOBUSS(sAddr) IX_OSAL_SWAP_SHORT_ADDRESS(sAddr)
-#define IX_OSAL_LE_AC_XSTOBUSB(bAddr) IX_OSAL_SWAP_BYTE_ADDRESS(bAddr)
-#define IX_OSAL_LE_AC_BUSTOXSL(wAddr) (wAddr)
-#define IX_OSAL_LE_AC_BUSTOXSS(sAddr) IX_OSAL_SWAP_SHORT_ADDRESS(sAddr)
-#define IX_OSAL_LE_AC_BUSTOXSB(bAddr) IX_OSAL_SWAP_BYTE_ADDRESS(bAddr)
-
-#define IX_OSAL_LE_DC_XSTOBUSL(wData) IX_OSAL_SWAP_LONG(wData)
-#define IX_OSAL_LE_DC_XSTOBUSS(sData) IX_OSAL_SWAP_SHORT(sData)
-#define IX_OSAL_LE_DC_XSTOBUSB(bData) (bData)
-#define IX_OSAL_LE_DC_BUSTOXSL(wData) IX_OSAL_SWAP_LONG(wData)
-#define IX_OSAL_LE_DC_BUSTOXSS(sData) IX_OSAL_SWAP_SHORT(sData)
-#define IX_OSAL_LE_DC_BUSTOXSB(bData) (bData)
-
-
-/*
- * Decide SDRAM mapping, then implement read/write
- */
-#include "IxOsalMemAccess.h"
-
-
-/**
- * @ingroup IxOsalIoMem
- * @enum IxOsalMapEntryType
- * @brief This is an emum for OSAL I/O mem map type.
- */
-typedef enum
-{
- IX_OSAL_STATIC_MAP = 0, /**<Set map entry type to static map */
- IX_OSAL_DYNAMIC_MAP /**<Set map entry type to dynamic map */
-} IxOsalMapEntryType;
-
-
-/**
- * @ingroup IxOsalIoMem
- * @enum IxOsalMapEndianessType
- * @brief This is an emum for OSAL I/O mem Endianess and Coherency mode.
- */
-typedef enum
-{
- IX_OSAL_BE = 0x1, /**<Set map endian mode to Big Endian */
- IX_OSAL_LE_AC = 0x2, /**<Set map endian mode to Little Endian, Address Coherent */
- IX_OSAL_LE_DC = 0x4, /**<Set map endian mode to Little Endian, Data Coherent */
- IX_OSAL_LE = 0x8 /**<Set map endian mode to Little Endian without specifying coherency mode */
-} IxOsalMapEndianessType;
-
-
-/**
- * @struct IxOsalMemoryMap
- * @brief IxOsalMemoryMap structure
- */
-typedef struct _IxOsalMemoryMap
-{
- IxOsalMapEntryType type; /**< map type - IX_OSAL_STATIC_MAP or IX_OSAL_DYNAMIC_MAP */
-
- UINT32 physicalAddress; /**< physical address of the memory mapped I/O zone */
-
- UINT32 size; /**< size of the map */
-
- UINT32 virtualAddress; /**< virtual address of the zone; must be predefined
- in the global memory map for static maps and has
- to be NULL for dynamic maps (populated on allocation)
- */
- /*
- * pointer to a map function called to map a dynamic map;
- * will populate the virtualAddress field
- */
- void (*mapFunction) (struct _IxOsalMemoryMap * map); /**< pointer to a map function called to map a dynamic map */
-
- /*
- * pointer to a map function called to unmap a dynamic map;
- * will reset the virtualAddress field to NULL
- */
- void (*unmapFunction) (struct _IxOsalMemoryMap * map); /**< pointer to a map function called to unmap a dynamic map */
-
- /*
- * reference count describing how many components share this map;
- * actual allocation/deallocation for dynamic maps is done only
- * between 0 <=> 1 transitions of the counter
- */
- UINT32 refCount; /**< reference count describing how many components share this map */
-
- /*
- * memory endian type for the map; can be a combination of IX_OSAL_BE (Big
- * Endian) and IX_OSAL_LE or IX_OSAL_LE_AC or IX_OSAL_LE_DC
- * (Little Endian, Address Coherent or Data Coherent). Any combination is
- * allowed provided it contains at most one LE flag - e.g.
- * (IX_OSAL_BE), (IX_OSAL_LE_AC), (IX_OSAL_BE | IX_OSAL_LE_DC) are valid
- * combinations while (IX_OSAL_BE | IX_OSAL_LE_DC | IX_OSAL_LE_AC) is not.
- */
- IxOsalMapEndianessType mapEndianType; /**< memory endian type for the map */
-
- char *name; /**< user-friendly name */
-} IxOsalMemoryMap;
-
-
-
-
-/* Internal function to map a memory zone
- * NOTE - This should not be called by the user.
- * Use the macro IX_OSAL_MEM_MAP instead
- */
-PUBLIC void *ixOsalIoMemMap (UINT32 requestedAddress,
- UINT32 size,
- IxOsalMapEndianessType requestedCoherency);
-
-
-/* Internal function to unmap a memory zone mapped with ixOsalIoMemMap
- * NOTE - This should not be called by the user.
- * Use the macro IX_OSAL_MEM_UNMAP instead
- */
-PUBLIC void ixOsalIoMemUnmap (UINT32 requestedAddress, UINT32 coherency);
-
-
-/* Internal function to convert virtual address to physical address
- * NOTE - This should not be called by the user.
- * Use the macro IX_OSAL_MMAP_VIRT_TO_PHYS */
-PUBLIC UINT32 ixOsalIoMemVirtToPhys (UINT32 virtualAddress, UINT32 coherency);
-
-
-/* Internal function to convert physical address to virtual address
- * NOTE - This should not be called by the user.
- * Use the macro IX_OSAL_MMAP_PHYS_TO_VIRT */
-PUBLIC UINT32
-ixOsalIoMemPhysToVirt (UINT32 physicalAddress, UINT32 coherency);
-
-/**
- * @ingroup IxOsalIoMem
- *
- * @def IX_OSAL_MEM_MAP(physAddr, size)
- *
- * @brief Map an I/O mapped physical memory zone to virtual zone and return virtual
- * pointer.
- * @param physAddr - the physical address
- * @param size - the size
- * @return start address of the virtual memory zone.
- *
- * @note This function maps an I/O mapped physical memory zone of the given size
- * into a virtual memory zone accessible by the caller and returns a cookie -
- * the start address of the virtual memory zone.
- * IX_OSAL_MMAP_PHYS_TO_VIRT should NOT therefore be used on the returned
- * virtual address.
- * The memory zone is to be unmapped using IX_OSAL_MEM_UNMAP once the caller has
- * finished using this zone (e.g. on driver unload) using the cookie as
- * parameter.
- * The IX_OSAL_READ/WRITE_LONG/SHORT macros should be used to read and write
- * the mapped memory, adding the necessary offsets to the address cookie.
- */
-#define IX_OSAL_MEM_MAP(physAddr, size) \
- ixOsalIoMemMap((physAddr), (size), IX_OSAL_COMPONENT_MAPPING)
-
-
-/**
- * @ingroup IxOsalIoMem
- *
- * @def IX_OSAL_MEM_UNMAP(virtAddr)
- *
- * @brief Unmap a previously mapped I/O memory zone using virtual pointer obtained
- * during the mapping operation.
- * pointer.
- * @param virtAddr - the virtual pointer to the zone to be unmapped.
- * @return none
- *
- * @note This function unmaps a previously mapped I/O memory zone using
- * the cookie obtained in the mapping operation. The memory zone in question
- * becomes unavailable to the caller once unmapped and the cookie should be
- * discarded.
- *
- * This function cannot fail if the given parameter is correct and does not
- * return a value.
- */
-#define IX_OSAL_MEM_UNMAP(virtAddr) \
- ixOsalIoMemUnmap ((virtAddr), IX_OSAL_COMPONENT_MAPPING)
-
-/**
- * @ingroup IxOsalIoMem
- *
- * @def IX_OSAL_MMAP_VIRT_TO_PHYS(virtAddr)
- *
- * @brief This function Converts a virtual address into a physical
- * address, including the dynamically mapped memory.
- *
- * @param virtAddr - virtual address to convert
- * Return value: corresponding physical address, or NULL
- */
-#define IX_OSAL_MMAP_VIRT_TO_PHYS(virtAddr) \
- ixOsalIoMemVirtToPhys(virtAddr, IX_OSAL_COMPONENT_MAPPING)
-
-
-/**
- * @ingroup IxOsalIoMem
- *
- * @def IX_OSAL_MMAP_PHYS_TO_VIRT(physAddr)
- *
- * @brief This function Converts a virtual address into a physical
- * address, including the dynamically mapped memory.
- *
- * @param physAddr - physical address to convert
- * Return value: corresponding virtual address, or NULL
- *
- */
-#define IX_OSAL_MMAP_PHYS_TO_VIRT(physAddr) \
- ixOsalIoMemPhysToVirt(physAddr, IX_OSAL_COMPONENT_MAPPING)
-
-/**
- * @} IxOsalIoMem
- */
-
-#endif /* IxOsalIoMem_H */
+++ /dev/null
-/**
- * @file IxOsalMemAccess.h
- *
- * @brief Header file for memory access
- *
- * @par
- * @version $Revision: 1.0 $
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsalMemAccess_H
-#define IxOsalMemAccess_H
-
-
-/* Global BE switch
- *
- * Should be set only in BE mode and only if the component uses I/O memory.
- */
-
-#if defined (__BIG_ENDIAN)
-
-#define IX_OSAL_BE_MAPPING
-
-#endif /* Global switch */
-
-
-/* By default only static memory maps in use;
- define IX_OSAL_DYNAMIC_MEMORY_MAP per component if dynamic maps are
- used instead in that component */
-#define IX_OSAL_STATIC_MEMORY_MAP
-
-
-/*
- * SDRAM coherency mode
- * Must be defined to BE, LE_DATA_COHERENT or LE_ADDRESS_COHERENT.
- * The mode changes depending on OS
- */
-#if defined (IX_OSAL_LINUX_BE) || defined (IX_OSAL_VXWORKS_BE)
-
-#define IX_SDRAM_BE
-
-#elif defined (IX_OSAL_VXWORKS_LE)
-
-#define IX_SDRAM_LE_DATA_COHERENT
-
-#elif defined (IX_OSAL_LINUX_LE)
-
-#define IX_SDRAM_LE_DATA_COHERENT
-
-#elif defined (IX_OSAL_WINCE_LE)
-
-#define IX_SDRAM_LE_DATA_COHERENT
-
-#elif defined (IX_OSAL_EBOOT_LE)
-
-#define IX_SDRAM_LE_ADDRESS_COHERENT
-
-#endif
-
-
-
-
-/**************************************
- * Retrieve current component mapping *
- **************************************/
-
-/*
- * Only use customized mapping for LE.
- *
- */
-#if defined (IX_OSAL_VXWORKS_LE) || defined (IX_OSAL_LINUX_LE) || defined (IX_OSAL_WINCE_LE) || defined (IX_OSAL_EBOOT_LE)
-
-#include "IxOsalOsIxp400CustomizedMapping.h"
-
-#endif
-
-
-/*******************************************************************
- * Turn off IX_STATIC_MEMORY map for components using dynamic maps *
- *******************************************************************/
-#ifdef IX_OSAL_DYNAMIC_MEMORY_MAP
-
-#undef IX_OSAL_STATIC_MEMORY_MAP
-
-#endif
-
-
-/************************************************************
- * Turn off BE access for components using LE or no mapping *
- ************************************************************/
-
-#if ( defined (IX_OSAL_LE_AC_MAPPING) || defined (IX_OSAL_LE_DC_MAPPING) || defined (IX_OSAL_NO_MAPPING) )
-
-#undef IX_OSAL_BE_MAPPING
-
-#endif
-
-
-/*****************
- * Safety checks *
- *****************/
-
-/* Default to no_mapping */
-#if !defined (IX_OSAL_BE_MAPPING) && !defined (IX_OSAL_LE_AC_MAPPING) && !defined (IX_OSAL_LE_DC_MAPPING) && !defined (IX_OSAL_NO_MAPPING)
-
-#define IX_OSAL_NO_MAPPING
-
-#endif /* check at least one mapping */
-
-/* No more than one mapping can be defined for a component */
-#if (defined (IX_OSAL_BE_MAPPING) && defined (IX_OSAL_LE_AC_MAPPING)) \
- ||(defined (IX_OSAL_BE_MAPPING) && defined (IX_OSAL_LE_DC_MAPPING)) \
- ||(defined (IX_OSAL_BE_MAPPING) && defined (IX_OSAL_NO_MAPPING)) \
- ||(defined (IX_OSAL_LE_DC_MAPPING) && defined (IX_OSAL_NO_MAPPING)) \
- ||(defined (IX_OSAL_LE_DC_MAPPING) && defined (IX_OSAL_LE_AC_MAPPING)) \
- ||(defined (IX_OSAL_LE_AC_MAPPING) && defined (IX_OSAL_NO_MAPPING))
-
-
-#ifdef IX_OSAL_BE_MAPPING
-#warning IX_OSAL_BE_MAPPING is defined
-#endif
-
-#ifdef IX_OSAL_LE_AC_MAPPING
-#warning IX_OSAL_LE_AC_MAPPING is defined
-#endif
-
-#ifdef IX_OSAL_LE_DC_MAPPING
-#warning IX_OSAL_LE_DC_MAPPING is defined
-#endif
-
-#ifdef IX_OSAL_NO_MAPPING
-#warning IX_OSAL_NO_MAPPING is defined
-#endif
-
-#error More than one I/O mapping is defined, please check your component mapping
-
-#endif /* check at most one mapping */
-
-
-/* Now set IX_OSAL_COMPONENT_MAPPING */
-
-#ifdef IX_OSAL_BE_MAPPING
-#define IX_OSAL_COMPONENT_MAPPING IX_OSAL_BE
-#endif
-
-#ifdef IX_OSAL_LE_AC_MAPPING
-#define IX_OSAL_COMPONENT_MAPPING IX_OSAL_LE_AC
-#endif
-
-#ifdef IX_OSAL_LE_DC_MAPPING
-#define IX_OSAL_COMPONENT_MAPPING IX_OSAL_LE_DC
-#endif
-
-#ifdef IX_OSAL_NO_MAPPING
-#define IX_OSAL_COMPONENT_MAPPING IX_OSAL_LE
-#endif
-
-
-/* SDRAM coherency should be defined */
-#if !defined (IX_SDRAM_BE) && !defined (IX_SDRAM_LE_DATA_COHERENT) && !defined (IX_SDRAM_LE_ADDRESS_COHERENT)
-
-#error SDRAM coherency must be defined
-
-#endif /* SDRAM coherency must be defined */
-
-/* SDRAM coherency cannot be defined in several ways */
-#if (defined (IX_SDRAM_BE) && (defined (IX_SDRAM_LE_DATA_COHERENT) || defined (IX_SDRAM_LE_ADDRESS_COHERENT))) \
- || (defined (IX_SDRAM_LE_DATA_COHERENT) && (defined (IX_SDRAM_BE) || defined (IX_SDRAM_LE_ADDRESS_COHERENT))) \
- || (defined (IX_SDRAM_LE_ADDRESS_COHERENT) && (defined (IX_SDRAM_BE) || defined (IX_SDRAM_LE_DATA_COHERENT)))
-
-#error SDRAM coherency cannot be defined in more than one way
-
-#endif /* SDRAM coherency must be defined exactly once */
-
-
-/*********************
- * Read/write macros *
- *********************/
-
-/* WARNING - except for addition of special cookie read/write macros (see below)
- these macros are NOT user serviceable. Please do not modify */
-
-#define IX_OSAL_READ_LONG_RAW(wAddr) (*(wAddr))
-#define IX_OSAL_READ_SHORT_RAW(sAddr) (*(sAddr))
-#define IX_OSAL_READ_BYTE_RAW(bAddr) (*(bAddr))
-#define IX_OSAL_WRITE_LONG_RAW(wAddr, wData) (*(wAddr) = (wData))
-#define IX_OSAL_WRITE_SHORT_RAW(sAddr,sData) (*(sAddr) = (sData))
-#define IX_OSAL_WRITE_BYTE_RAW(bAddr, bData) (*(bAddr) = (bData))
-
-#ifdef __linux
-
-/* Linux - specific cookie reads/writes.
- Redefine per OS if dynamic memory maps are used
- and I/O memory is accessed via functions instead of raw pointer access. */
-
-#define IX_OSAL_READ_LONG_COOKIE(wCookie) (readl((UINT32) (wCookie) ))
-#define IX_OSAL_READ_SHORT_COOKIE(sCookie) (readw((UINT32) (sCookie) ))
-#define IX_OSAL_READ_BYTE_COOKIE(bCookie) (readb((UINT32) (bCookie) ))
-#define IX_OSAL_WRITE_LONG_COOKIE(wCookie, wData) (writel(wData, (UINT32) (wCookie) ))
-#define IX_OSAL_WRITE_SHORT_COOKIE(sCookie, sData) (writew(sData, (UINT32) (sCookie) ))
-#define IX_OSAL_WRITE_BYTE_COOKIE(bCookie, bData) (writeb(bData, (UINT32) (bCookie) ))
-
-#endif /* linux */
-
-#ifdef __wince
-
-/* WinCE - specific cookie reads/writes. */
-
-static __inline__ UINT32
-ixOsalWinCEReadLCookie (volatile UINT32 * lCookie)
-{
- return *lCookie;
-}
-
-static __inline__ UINT16
-ixOsalWinCEReadWCookie (volatile UINT16 * wCookie)
-{
-#if 0
- UINT32 auxVal = *((volatile UINT32 *) wCookie);
- if ((unsigned) wCookie & 3)
- return (UINT16) (auxVal >> 16);
- else
- return (UINT16) (auxVal & 0xffff);
-#else
- return *wCookie;
-#endif
-}
-
-static __inline__ UINT8
-ixOsalWinCEReadBCookie (volatile UINT8 * bCookie)
-{
-#if 0
- UINT32 auxVal = *((volatile UINT32 *) bCookie);
- return (UINT8) ((auxVal >> (3 - (((unsigned) bCookie & 3) << 3)) & 0xff));
-#else
- return *bCookie;
-#endif
-}
-
-static __inline__ void
-ixOsalWinCEWriteLCookie (volatile UINT32 * lCookie, UINT32 lVal)
-{
- *lCookie = lVal;
-}
-
-static __inline__ void
-ixOsalWinCEWriteWCookie (volatile UINT16 * wCookie, UINT16 wVal)
-{
-#if 0
- volatile UINT32 *auxCookie =
- (volatile UINT32 *) ((unsigned) wCookie & ~3);
- if ((unsigned) wCookie & 3)
- {
- *auxCookie &= 0xffff;
- *auxCookie |= (UINT32) wVal << 16;
- }
- else
- {
- *auxCookie &= ~0xffff;
- *auxCookie |= (UINT32) wVal & 0xffff;
- }
-#else
- *wCookie = wVal;
-#endif
-}
-
-static __inline__ void
-ixOsalWinCEWriteBCookie (volatile UINT8 * bCookie, UINT8 bVal)
-{
-#if 0
- volatile UINT32 *auxCookie =
- (volatile UINT32 *) ((unsigned) bCookie & ~3);
- *auxCookie &= 0xff << (3 - (((unsigned) bCookie & 3) << 3));
- *auxCookie |= (UINT32) bVal << (3 - (((unsigned) bCookie & 3) << 3));
-#else
- *bCookie = bVal;
-#endif
-}
-
-
-#define IX_OSAL_READ_LONG_COOKIE(wCookie) (ixOsalWinCEReadLCookie(wCookie))
-#define IX_OSAL_READ_SHORT_COOKIE(sCookie) (ixOsalWinCEReadWCookie(sCookie))
-#define IX_OSAL_READ_BYTE_COOKIE(bCookie) (ixOsalWinCEReadBCookie(bCookie))
-#define IX_OSAL_WRITE_LONG_COOKIE(wCookie, wData) (ixOsalWinCEWriteLCookie(wCookie, wData))
-#define IX_OSAL_WRITE_SHORT_COOKIE(sCookie, sData) (ixOsalWinCEWriteWCookie(sCookie, sData))
-#define IX_OSAL_WRITE_BYTE_COOKIE(bCookie, bData) (ixOsalWinCEWriteBCookie(bCookie, bData))
-
-#endif /* wince */
-
-#if defined (__vxworks) || (defined (__linux) && defined (IX_OSAL_STATIC_MEMORY_MAP)) || \
- (defined (__wince) && defined (IX_OSAL_STATIC_MEMORY_MAP))
-
-#define IX_OSAL_READ_LONG_IO(wAddr) IX_OSAL_READ_LONG_RAW(wAddr)
-#define IX_OSAL_READ_SHORT_IO(sAddr) IX_OSAL_READ_SHORT_RAW(sAddr)
-#define IX_OSAL_READ_BYTE_IO(bAddr) IX_OSAL_READ_BYTE_RAW(bAddr)
-#define IX_OSAL_WRITE_LONG_IO(wAddr, wData) IX_OSAL_WRITE_LONG_RAW(wAddr, wData)
-#define IX_OSAL_WRITE_SHORT_IO(sAddr, sData) IX_OSAL_WRITE_SHORT_RAW(sAddr, sData)
-#define IX_OSAL_WRITE_BYTE_IO(bAddr, bData) IX_OSAL_WRITE_BYTE_RAW(bAddr, bData)
-
-#elif (defined (__linux) && !defined (IX_OSAL_STATIC_MEMORY_MAP)) || \
- (defined (__wince) && !defined (IX_OSAL_STATIC_MEMORY_MAP))
-
-#ifndef __wince
-#include <asm/io.h>
-#endif /* ndef __wince */
-
-#define IX_OSAL_READ_LONG_IO(wAddr) IX_OSAL_READ_LONG_COOKIE(wAddr)
-#define IX_OSAL_READ_SHORT_IO(sAddr) IX_OSAL_READ_SHORT_COOKIE(sAddr)
-#define IX_OSAL_READ_BYTE_IO(bAddr) IX_OSAL_READ_BYTE_COOKIE(bAddr)
-#define IX_OSAL_WRITE_LONG_IO(wAddr, wData) IX_OSAL_WRITE_LONG_COOKIE(wAddr, wData)
-#define IX_OSAL_WRITE_SHORT_IO(sAddr, sData) IX_OSAL_WRITE_SHORT_COOKIE(sAddr, sData)
-#define IX_OSAL_WRITE_BYTE_IO(bAddr, bData) IX_OSAL_WRITE_BYTE_COOKIE(bAddr, bData)
-
-#endif
-
-/* Define BE macros */
-#define IX_OSAL_READ_LONG_BE(wAddr) IX_OSAL_BE_BUSTOXSL(IX_OSAL_READ_LONG_IO((volatile UINT32 *) (wAddr) ))
-#define IX_OSAL_READ_SHORT_BE(sAddr) IX_OSAL_BE_BUSTOXSS(IX_OSAL_READ_SHORT_IO((volatile UINT16 *) (sAddr) ))
-#define IX_OSAL_READ_BYTE_BE(bAddr) IX_OSAL_BE_BUSTOXSB(IX_OSAL_READ_BYTE_IO((volatile UINT8 *) (bAddr) ))
-#define IX_OSAL_WRITE_LONG_BE(wAddr, wData) IX_OSAL_WRITE_LONG_IO((volatile UINT32 *) (wAddr), IX_OSAL_BE_XSTOBUSL((UINT32) (wData) ))
-#define IX_OSAL_WRITE_SHORT_BE(sAddr, sData) IX_OSAL_WRITE_SHORT_IO((volatile UINT16 *) (sAddr), IX_OSAL_BE_XSTOBUSS((UINT16) (sData) ))
-#define IX_OSAL_WRITE_BYTE_BE(bAddr, bData) IX_OSAL_WRITE_BYTE_IO((volatile UINT8 *) (bAddr), IX_OSAL_BE_XSTOBUSB((UINT8) (bData) ))
-
-/* Define LE AC macros */
-#define IX_OSAL_READ_LONG_LE_AC(wAddr) IX_OSAL_READ_LONG_IO((volatile UINT32 *) IX_OSAL_LE_AC_BUSTOXSL((UINT32) (wAddr) ))
-#define IX_OSAL_READ_SHORT_LE_AC(sAddr) IX_OSAL_READ_SHORT_IO((volatile UINT16 *) IX_OSAL_LE_AC_BUSTOXSS((UINT32) (sAddr) ))
-#define IX_OSAL_READ_BYTE_LE_AC(bAddr) IX_OSAL_READ_BYTE_IO((volatile UINT8 *) IX_OSAL_LE_AC_BUSTOXSB((UINT32) (bAddr) ))
-#define IX_OSAL_WRITE_LONG_LE_AC(wAddr, wData) IX_OSAL_WRITE_LONG_IO((volatile UINT32 *) IX_OSAL_LE_AC_XSTOBUSL((UINT32) (wAddr) ), (UINT32) (wData))
-#define IX_OSAL_WRITE_SHORT_LE_AC(sAddr, sData) IX_OSAL_WRITE_SHORT_IO((volatile UINT16 *) IX_OSAL_LE_AC_XSTOBUSS((UINT32) (sAddr) ), (UINT16) (sData))
-#define IX_OSAL_WRITE_BYTE_LE_AC(bAddr, bData) IX_OSAL_WRITE_BYTE_IO((volatile UINT8 *) IX_OSAL_LE_AC_XSTOBUSB((UINT32) (bAddr) ), (UINT8) (bData))
-
-
-/* Inline functions are required here to avoid reading the same I/O location 2 or 4 times for the byte swap */
-static __inline__ UINT32
-ixOsalDataCoherentLongReadSwap (volatile UINT32 * wAddr)
-{
- UINT32 wData = IX_OSAL_READ_LONG_IO (wAddr);
- return IX_OSAL_LE_DC_BUSTOXSL (wData);
-}
-
-static __inline__ UINT16
-ixOsalDataCoherentShortReadSwap (volatile UINT16 * sAddr)
-{
- UINT16 sData = IX_OSAL_READ_SHORT_IO (sAddr);
- return IX_OSAL_LE_DC_BUSTOXSS (sData);
-}
-
-static __inline__ void
-ixOsalDataCoherentLongWriteSwap (volatile UINT32 * wAddr, UINT32 wData)
-{
- wData = IX_OSAL_LE_DC_XSTOBUSL (wData);
- IX_OSAL_WRITE_LONG_IO (wAddr, wData);
-}
-
-static __inline__ void
-ixOsalDataCoherentShortWriteSwap (volatile UINT16 * sAddr, UINT16 sData)
-{
- sData = IX_OSAL_LE_DC_XSTOBUSS (sData);
- IX_OSAL_WRITE_SHORT_IO (sAddr, sData);
-}
-
-/* Define LE DC macros */
-
-#define IX_OSAL_READ_LONG_LE_DC(wAddr) ixOsalDataCoherentLongReadSwap((volatile UINT32 *) (wAddr) )
-#define IX_OSAL_READ_SHORT_LE_DC(sAddr) ixOsalDataCoherentShortReadSwap((volatile UINT16 *) (sAddr) )
-#define IX_OSAL_READ_BYTE_LE_DC(bAddr) IX_OSAL_LE_DC_BUSTOXSB(IX_OSAL_READ_BYTE_IO((volatile UINT8 *) (bAddr) ))
-#define IX_OSAL_WRITE_LONG_LE_DC(wAddr, wData) ixOsalDataCoherentLongWriteSwap((volatile UINT32 *) (wAddr), (UINT32) (wData))
-#define IX_OSAL_WRITE_SHORT_LE_DC(sAddr, sData) ixOsalDataCoherentShortWriteSwap((volatile UINT16 *) (sAddr), (UINT16) (sData))
-#define IX_OSAL_WRITE_BYTE_LE_DC(bAddr, bData) IX_OSAL_WRITE_BYTE_IO((volatile UINT8 *) (bAddr), IX_OSAL_LE_DC_XSTOBUSB((UINT8) (bData)))
-
-#if defined (IX_OSAL_BE_MAPPING)
-
-#define IX_OSAL_READ_LONG(wAddr) IX_OSAL_READ_LONG_BE(wAddr)
-#define IX_OSAL_READ_SHORT(sAddr) IX_OSAL_READ_SHORT_BE(sAddr)
-#define IX_OSAL_READ_BYTE(bAddr) IX_OSAL_READ_BYTE_BE(bAddr)
-#define IX_OSAL_WRITE_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_BE(wAddr, wData)
-#define IX_OSAL_WRITE_SHORT(sAddr, sData) IX_OSAL_WRITE_SHORT_BE(sAddr, sData)
-#define IX_OSAL_WRITE_BYTE(bAddr, bData) IX_OSAL_WRITE_BYTE_BE(bAddr, bData)
-
-#elif defined (IX_OSAL_LE_AC_MAPPING)
-
-#define IX_OSAL_READ_LONG(wAddr) IX_OSAL_READ_LONG_LE_AC(wAddr)
-#define IX_OSAL_READ_SHORT(sAddr) IX_OSAL_READ_SHORT_LE_AC(sAddr)
-#define IX_OSAL_READ_BYTE(bAddr) IX_OSAL_READ_BYTE_LE_AC(bAddr)
-#define IX_OSAL_WRITE_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_LE_AC(wAddr, wData)
-#define IX_OSAL_WRITE_SHORT(sAddr, sData) IX_OSAL_WRITE_SHORT_LE_AC(sAddr, sData)
-#define IX_OSAL_WRITE_BYTE(bAddr, bData) IX_OSAL_WRITE_BYTE_LE_AC(bAddr, bData)
-
-#elif defined (IX_OSAL_LE_DC_MAPPING)
-
-#define IX_OSAL_READ_LONG(wAddr) IX_OSAL_READ_LONG_LE_DC(wAddr)
-#define IX_OSAL_READ_SHORT(sAddr) IX_OSAL_READ_SHORT_LE_DC(sAddr)
-#define IX_OSAL_READ_BYTE(bAddr) IX_OSAL_READ_BYTE_LE_DC(bAddr)
-#define IX_OSAL_WRITE_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_LE_DC(wAddr, wData)
-#define IX_OSAL_WRITE_SHORT(sAddr, sData) IX_OSAL_WRITE_SHORT_LE_DC(sAddr, sData)
-#define IX_OSAL_WRITE_BYTE(bAddr, bData) IX_OSAL_WRITE_BYTE_LE_DC(bAddr, bData)
-
-#endif /* End of BE and LE coherency mode switch */
-
-
-/* Reads/writes to and from memory shared with NPEs - depends on the SDRAM coherency */
-
-#if defined (IX_SDRAM_BE)
-
-#define IX_OSAL_READ_BE_SHARED_LONG(wAddr) IX_OSAL_READ_LONG_RAW(wAddr)
-#define IX_OSAL_READ_BE_SHARED_SHORT(sAddr) IX_OSAL_READ_SHORT_RAW(sAddr)
-#define IX_OSAL_READ_BE_SHARED_BYTE(bAddr) IX_OSAL_READ_BYTE_RAW(bAddr)
-
-#define IX_OSAL_WRITE_BE_SHARED_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_RAW(wAddr, wData)
-#define IX_OSAL_WRITE_BE_SHARED_SHORT(sAddr, sData) IX_OSAL_WRITE_SHORT_RAW(sAddr, sData)
-#define IX_OSAL_WRITE_BE_SHARED_BYTE(bAddr, bData) IX_OSAL_WRITE_BYTE_RAW(bAddr, bData)
-
-#define IX_OSAL_SWAP_BE_SHARED_LONG(wData) (wData)
-#define IX_OSAL_SWAP_BE_SHARED_SHORT(sData) (sData)
-#define IX_OSAL_SWAP_BE_SHARED_BYTE(bData) (bData)
-
-#elif defined (IX_SDRAM_LE_ADDRESS_COHERENT)
-
-#define IX_OSAL_READ_BE_SHARED_LONG(wAddr) IX_OSAL_READ_LONG_RAW(wAddr)
-#define IX_OSAL_READ_BE_SHARED_SHORT(sAddr) IX_OSAL_READ_SHORT_RAW(IX_OSAL_SWAP_SHORT_ADDRESS(sAddr))
-#define IX_OSAL_READ_BE_SHARED_BYTE(bAddr) IX_OSAL_READ_BYTE_RAW(IX_OSAL_SWAP_BYTE_ADDRESS(bAddr))
-
-#define IX_OSAL_WRITE_BE_SHARED_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_RAW(wAddr, wData)
-#define IX_OSAL_WRITE_BE_SHARED_SHORT(sAddr, sData) IX_OSAL_WRITE_SHORT_RAW(IX_OSAL_SWAP_SHORT_ADDRESS(sAddr), sData)
-#define IX_OSAL_WRITE_BE_SHARED_BYTE(bAddr, bData) IX_OSAL_WRITE_BYTE_RAW(IX_OSAL_SWAP_BYTE_ADDRESS(bAddr), bData)
-
-#define IX_OSAL_SWAP_BE_SHARED_LONG(wData) (wData)
-#define IX_OSAL_SWAP_BE_SHARED_SHORT(sData) (sData)
-#define IX_OSAL_SWAP_BE_SHARED_BYTE(bData) (bData)
-
-#elif defined (IX_SDRAM_LE_DATA_COHERENT)
-
-#define IX_OSAL_READ_BE_SHARED_LONG(wAddr) IX_OSAL_SWAP_LONG(IX_OSAL_READ_LONG_RAW(wAddr))
-#define IX_OSAL_READ_BE_SHARED_SHORT(sAddr) IX_OSAL_SWAP_SHORT(IX_OSAL_READ_SHORT_RAW(sAddr))
-#define IX_OSAL_READ_BE_SHARED_BYTE(bAddr) IX_OSAL_READ_BYTE_RAW(bAddr)
-
-#define IX_OSAL_WRITE_BE_SHARED_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_RAW(wAddr, IX_OSAL_SWAP_LONG(wData))
-#define IX_OSAL_WRITE_BE_SHARED_SHORT(sAddr, sData) IX_OSAL_WRITE_SHORT_RAW(sAddr, IX_OSAL_SWAP_SHORT(sData))
-#define IX_OSAL_WRITE_BE_SHARED_BYTE(bAddr, bData) IX_OSAL_WRITE_BYTE_RAW(bAddr, bData)
-
-#define IX_OSAL_SWAP_BE_SHARED_LONG(wData) IX_OSAL_SWAP_LONG(wData)
-#define IX_OSAL_SWAP_BE_SHARED_SHORT(sData) IX_OSAL_SWAP_SHORT(sData)
-
-#endif
-
-
-#define IX_OSAL_COPY_BE_SHARED_LONG_ARRAY(wDestAddr, wSrcAddr, wCount) \
- { \
- UINT32 i; \
- \
- for ( i = 0 ; i < wCount ; i++ ) \
- { \
- * (((UINT32 *) wDestAddr) + i) = IX_OSAL_READ_BE_SHARED_LONG(((UINT32 *) wSrcAddr) + i); \
- }; \
- };
-
-#endif /* IxOsalMemAccess_H */
+++ /dev/null
-/**
- * @file IxOsalIxpOem.h
- *
- * @brief this file contains platform-specific defines.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsalOem_H
-#define IxOsalOem_H
-
-#include "IxOsalTypes.h"
-
-/* OS-specific header for Platform package */
-#include "IxOsalOsIxp400.h"
-
-/*
- * Platform Name
- */
-#define IX_OSAL_PLATFORM_NAME ixp400
-
-/*
- * Cache line size
- */
-#define IX_OSAL_CACHE_LINE_SIZE (32)
-
-
-/* Platform-specific fastmutex implementation */
-PUBLIC IX_STATUS ixOsalOemFastMutexTryLock (IxOsalFastMutex * mutex);
-
-/* Platform-specific init (MemMap) */
-PUBLIC IX_STATUS
-ixOsalOemInit (void);
-
-/* Platform-specific unload (MemMap) */
-PUBLIC void
-ixOsalOemUnload (void);
-
-/* Default implementations */
-
-PUBLIC UINT32
-ixOsalIxp400SharedTimestampGet (void);
-
-
-UINT32
-ixOsalIxp400SharedTimestampRateGet (void);
-
-UINT32
-ixOsalIxp400SharedSysClockRateGet (void);
-
-void
-ixOsalIxp400SharedTimeGet (IxOsalTimeval * tv);
-
-
-INT32
-ixOsalIxp400SharedLog (UINT32 level, UINT32 device, char *format,
- int arg1, int arg2, int arg3, int arg4,
- int arg5, int arg6);
-
-#endif /* IxOsal_Oem_H */
+++ /dev/null
-#ifndef IxOsalOs_H
-#define IxOsalOs_H
-
-#ifndef IX_OSAL_CACHED
-#error "Uncached memory not supported in linux environment"
-#endif
-
-static inline unsigned long __v2p(unsigned long v)
-{
- if (v < 0x40000000)
- return (v & 0xfffffff);
- else
- return v;
-}
-
-#define IX_OSAL_OS_MMU_VIRT_TO_PHYS(addr) __v2p((u32)addr)
-#define IX_OSAL_OS_MMU_PHYS_TO_VIRT(addr) (addr)
-
-/*
- * Data cache not enabled (hopefully)
- */
-#define IX_OSAL_OS_CACHE_INVALIDATE(addr, size)
-#define IX_OSAL_OS_CACHE_FLUSH(addr, size)
-#define HAL_DCACHE_INVALIDATE(addr, size)
-#define HAL_DCACHE_FLUSH(addr, size)
-
-#define __ixp42X /* sr: U-Boot needs this define */
-
-#endif /* IxOsalOs_H */
-
+++ /dev/null
-#ifndef IxOsalOsAssert_H
-#define IxOsalOsAssert_H
-
-#define IX_OSAL_OS_ASSERT(c) if(!(c)) \
- { \
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, "Assertion failure \n", 0, 0, 0, 0, 0, 0);\
- while(1); \
- }
-
-#endif /* IxOsalOsAssert_H */
+++ /dev/null
-/**
- * @file IxOsalOsBufferMgt.h
- *
- * @brief vxworks-specific buffer management module definitions.
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#ifndef IX_OSAL_OS_BUFFER_MGT_H
-#define IX_OSAL_OS_BUFFER_MGT_H
-
-/*
- * use the defaul bufferMgt provided by OSAL framework.
- */
-#define IX_OSAL_USE_DEFAULT_BUFFER_MGT
-
-#include "IxOsalBufferMgtDefault.h"
-
-#if 0 /* FIXME */
-/* Define os-specific buffer macros for subfields */
-#define IX_OSAL_OSBUF_MDATA(osBufPtr) IX_OSAL_MBUF_MDATA(osBufPtr)
- ( ((M_BLK *) osBufPtr)->m_data )
-
-#define IX_OSAL_OSBUF_MLEN(osBufPtr) \
- ( ((M_BLK *) osBufPtr)->m_len )
-
-#define IX_OSAL_OSBUF_PKT_LEN(osBufPtr) \
- ( ((M_BLK *) osBufPtr)->m_pkthdr.len )
-
-#define IX_OSAL_OS_CONVERT_OSBUF_TO_IXPBUF( osBufPtr, ixpBufPtr) \
- { \
- IX_OSAL_MBUF_OSBUF_PTR( (IX_OSAL_MBUF *) ixpBufPtr) = (void *) osBufPtr; \
- IX_OSAL_MBUF_MDATA((IX_OSAL_MBUF *) ixpBufPtr) = IX_OSAL_OSBUF_MDATA(osBufPtr); \
- IX_OSAL_MBUF_PKT_LEN((IX_OSAL_MBUF *) ixpBufPtr) = IX_OSAL_OSBUF_PKT_LEN(osBufPtr); \
- IX_OSAL_MBUF_MLEN((IX_OSAL_MBUF *) ixpBufPtr) = IX_OSAL_OSBUF_MLEN(osBufPtr); \
- }
-
-#define IX_OSAL_OS_CONVERT_IXPBUF_TO_OSBUF( ixpBufPtr, osBufPtr) \
- { \
- if (ixpBufPtr == NULL) \
- { /* Do nothing */ } \
- else \
- { \
- (M_BLK *) osBufPtr = (M_BLK *) IX_OSAL_MBUF_OSBUF_PTR((IX_OSAL_MBUF *) ixpBufPtr); \
- if (osBufPtr == NULL) \
- { /* Do nothing */ } \
- else \
- { \
- IX_OSAL_OSBUF_MLEN(osBufPtr) =IX_OSAL_MBUF_MLEN((IX_OSAL_MBUF *) ixpBufPtr); \
- IX_OSAL_OSBUF_PKT_LEN(osBufPtr) =IX_OSAL_MBUF_PKT_LEN((IX_OSAL_MBUF *) ixpBufPtr); \
- } \
- } \
- }
-
-#endif /* FIXME */
-
-#endif /* #define IX_OSAL_OS_BUFFER_MGT_H */
+++ /dev/null
-/**
- * @file IxOsalOsIxp400.h
- *
- * @brief OS and platform specific definitions
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsalOsIxp400_H
-#define IxOsalOsIxp400_H
-
-#define BIT(x) (1<<(x))
-
-#define IXP425_EthA_BASE 0xc8009000
-#define IXP425_EthB_BASE 0xc800a000
-
-#define IXP425_PSMA_BASE 0xc8006000
-#define IXP425_PSMB_BASE 0xc8007000
-#define IXP425_PSMC_BASE 0xc8008000
-
-#define IXP425_PERIPHERAL_BASE 0xc8000000
-
-#define IXP425_QMGR_BASE 0x60000000
-#define IXP425_OSTS 0xC8005000
-
-#define IXP425_INT_LVL_NPEA 0
-#define IXP425_INT_LVL_NPEB 1
-#define IXP425_INT_LVL_NPEC 2
-
-#define IXP425_INT_LVL_QM1 3
-#define IXP425_INT_LVL_QM2 4
-
-#define IXP425_EXPANSION_BUS_BASE1 0x50000000
-#define IXP425_EXPANSION_BUS_BASE2 0x50000000
-#define IXP425_EXPANSION_BUS_CS1_BASE 0x51000000
-
-#define IXP425_EXP_CONFIG_BASE 0xC4000000
-
-/* physical addresses to be used when requesting memory with IX_OSAL_MEM_MAP */
-#define IX_OSAL_IXP400_INTC_PHYS_BASE IXP425_INTC_BASE
-#define IX_OSAL_IXP400_GPIO_PHYS_BASE IXP425_GPIO_BASE
-#define IX_OSAL_IXP400_UART1_PHYS_BASE IXP425_UART1_BASE
-#define IX_OSAL_IXP400_UART2_PHYS_BASE IXP425_UART2_BASE
-#define IX_OSAL_IXP400_ETHA_PHYS_BASE IXP425_EthA_BASE
-#define IX_OSAL_IXP400_ETHB_PHYS_BASE IXP425_EthB_BASE
-#define IX_OSAL_IXP400_NPEA_PHYS_BASE IXP425_NPEA_BASE
-#define IX_OSAL_IXP400_NPEB_PHYS_BASE IXP425_NPEB_BASE
-#define IX_OSAL_IXP400_NPEC_PHYS_BASE IXP425_NPEC_BASE
-#define IX_OSAL_IXP400_PERIPHERAL_PHYS_BASE IXP425_PERIPHERAL_BASE
-#define IX_OSAL_IXP400_QMGR_PHYS_BASE IXP425_QMGR_BASE
-#define IX_OSAL_IXP400_OSTS_PHYS_BASE IXP425_TIMER_BASE
-#define IX_OSAL_IXP400_USB_PHYS_BASE IXP425_USB_BASE
-#define IX_OSAL_IXP400_EXP_CFG_PHYS_BASE IXP425_EXP_CFG_BASE
-#define IX_OSAL_IXP400_EXP_BUS_PHYS_BASE IXP425_EXP_BUS_BASE2
-#define IX_OSAL_IXP400_EXP_BUS_BOOT_PHYS_BASE IXP425_EXP_BUS_BASE1
-#define IX_OSAL_IXP400_EXP_BUS_CS0_PHYS_BASE IXP425_EXP_BUS_CS0_BASE
-#define IX_OSAL_IXP400_EXP_BUS_CS1_PHYS_BASE IXP425_EXP_BUS_CS1_BASE
-#define IX_OSAL_IXP400_EXP_BUS_CS4_PHYS_BASE IXP425_EXP_BUS_CS4_BASE
-#define IX_OSAL_IXP400_EXP_BUS_REGS_PHYS_BASE IXP425_EXP_CFG_BASE
-#define IX_OSAL_IXP400_PCI_CFG_PHYS_BASE IXP425_PCI_CFG_BASE
-
-/* map sizes to be used when requesting memory with IX_OSAL_MEM_MAP */
-#define IX_OSAL_IXP400_QMGR_MAP_SIZE (0x4000) /**< Queue Manager map size */
-#define IX_OSAL_IXP400_PERIPHERAL_MAP_SIZE (0xC000) /**< Peripheral space map size */
-#define IX_OSAL_IXP400_UART1_MAP_SIZE (0x1000) /**< UART1 map size */
-#define IX_OSAL_IXP400_UART2_MAP_SIZE (0x1000) /**< UART2 map size */
-#define IX_OSAL_IXP400_PMU_MAP_SIZE (0x1000) /**< PMU map size */
-#define IX_OSAL_IXP400_OSTS_MAP_SIZE (0x1000) /**< OS Timers map size */
-#define IX_OSAL_IXP400_NPEA_MAP_SIZE (0x1000) /**< NPE A map size */
-#define IX_OSAL_IXP400_NPEB_MAP_SIZE (0x1000) /**< NPE B map size */
-#define IX_OSAL_IXP400_NPEC_MAP_SIZE (0x1000) /**< NPE C map size */
-#define IX_OSAL_IXP400_ETHA_MAP_SIZE (0x1000) /**< Eth A map size */
-#define IX_OSAL_IXP400_ETHB_MAP_SIZE (0x1000) /**< Eth B map size */
-#define IX_OSAL_IXP400_USB_MAP_SIZE (0x1000) /**< USB map size */
-#define IX_OSAL_IXP400_GPIO_MAP_SIZE (0x1000) /**< GPIO map size */
-#define IX_OSAL_IXP400_EXP_REG_MAP_SIZE (0x1000) /**< Exp Bus Config Registers map size */
-#define IX_OSAL_IXP400_EXP_BUS_MAP_SIZE (0x08000000) /**< Expansion bus map size */
-#define IX_OSAL_IXP400_EXP_BUS_CS0_MAP_SIZE (0x01000000) /**< CS0 map size */
-#define IX_OSAL_IXP400_EXP_BUS_CS1_MAP_SIZE (0x01000000) /**< CS1 map size */
-#define IX_OSAL_IXP400_EXP_BUS_CS4_MAP_SIZE (0x01000000) /**< CS4 map size */
-#define IX_OSAL_IXP400_PCI_CFG_MAP_SIZE (0x1000) /**< PCI Bus Config Registers map size */
-
-#define IX_OSAL_IXP400_EXP_FUSE (IXP425_EXP_CONFIG_BASE + 0x28)
-#define IX_OSAL_IXP400_ETH_NPEA_PHYS_BASE 0xC800C000
-#define IX_OSAL_IXP400_ETH_NPEA_MAP_SIZE 0x1000
-
-/*
- * Interrupt Levels
- */
-#define IX_OSAL_IXP400_NPEA_IRQ_LVL (0)
-#define IX_OSAL_IXP400_NPEB_IRQ_LVL (1)
-#define IX_OSAL_IXP400_NPEC_IRQ_LVL (2)
-#define IX_OSAL_IXP400_QM1_IRQ_LVL (3)
-#define IX_OSAL_IXP400_QM2_IRQ_LVL (4)
-#define IX_OSAL_IXP400_TIMER1_IRQ_LVL (5)
-#define IX_OSAL_IXP400_GPIO0_IRQ_LVL (6)
-#define IX_OSAL_IXP400_GPIO1_IRQ_LVL (7)
-#define IX_OSAL_IXP400_PCI_INT_IRQ_LVL (8)
-#define IX_OSAL_IXP400_PCI_DMA1_IRQ_LVL (9)
-#define IX_OSAL_IXP400_PCI_DMA2_IRQ_LVL (10)
-#define IX_OSAL_IXP400_TIMER2_IRQ_LVL (11)
-#define IX_OSAL_IXP400_USB_IRQ_LVL (12)
-#define IX_OSAL_IXP400_UART2_IRQ_LVL (13)
-#define IX_OSAL_IXP400_TIMESTAMP_IRQ_LVL (14)
-#define IX_OSAL_IXP400_UART1_IRQ_LVL (15)
-#define IX_OSAL_IXP400_WDOG_IRQ_LVL (16)
-#define IX_OSAL_IXP400_AHB_PMU_IRQ_LVL (17)
-#define IX_OSAL_IXP400_XSCALE_PMU_IRQ_LVL (18)
-#define IX_OSAL_IXP400_GPIO2_IRQ_LVL (19)
-#define IX_OSAL_IXP400_GPIO3_IRQ_LVL (20)
-#define IX_OSAL_IXP400_GPIO4_IRQ_LVL (21)
-#define IX_OSAL_IXP400_GPIO5_IRQ_LVL (22)
-#define IX_OSAL_IXP400_GPIO6_IRQ_LVL (23)
-#define IX_OSAL_IXP400_GPIO7_IRQ_LVL (24)
-#define IX_OSAL_IXP400_GPIO8_IRQ_LVL (25)
-#define IX_OSAL_IXP400_GPIO9_IRQ_LVL (26)
-#define IX_OSAL_IXP400_GPIO10_IRQ_LVL (27)
-#define IX_OSAL_IXP400_GPIO11_IRQ_LVL (28)
-#define IX_OSAL_IXP400_GPIO12_IRQ_LVL (29)
-#define IX_OSAL_IXP400_SW_INT1_IRQ_LVL (30)
-#define IX_OSAL_IXP400_SW_INT2_IRQ_LVL (31)
-
-/* USB interrupt level mask */
-#define IX_OSAL_IXP400_INT_LVL_USB IRQ_IXP425_USB
-
-/* USB IRQ */
-#define IX_OSAL_IXP400_USB_IRQ IRQ_IXP425_USB
-
-/*
- * OS name retrieval
- */
-#define IX_OSAL_OEM_OS_NAME_GET(name, limit) \
-ixOsalOsIxp400NameGet((INT8*)(name), (INT32) (limit))
-
-/*
- * OS version retrieval
- */
-#define IX_OSAL_OEM_OS_VERSION_GET(version, limit) \
-ixOsalOsIxp400VersionGet((INT8*)(version), (INT32) (limit))
-
-/*
- * Function to retrieve the OS name
- */
-PUBLIC IX_STATUS ixOsalOsIxp400NameGet(INT8* osName, INT32 maxSize);
-
-/*
- * Function to retrieve the OS version
- */
-PUBLIC IX_STATUS ixOsalOsIxp400VersionGet(INT8* osVersion, INT32 maxSize);
-
-/*
- * TimestampGet
- */
-PUBLIC UINT32 ixOsalOsIxp400TimestampGet (void);
-
-/*
- * Timestamp
- */
-#define IX_OSAL_OEM_TIMESTAMP_GET ixOsalOsIxp400TimestampGet
-
-
-/*
- * Timestamp resolution
- */
-PUBLIC UINT32 ixOsalOsIxp400TimestampResolutionGet (void);
-
-#define IX_OSAL_OEM_TIMESTAMP_RESOLUTION_GET ixOsalOsIxp400TimestampResolutionGet
-
-/*
- * Retrieves the system clock rate
- */
-PUBLIC UINT32 ixOsalOsIxp400SysClockRateGet (void);
-
-#define IX_OSAL_OEM_SYS_CLOCK_RATE_GET ixOsalOsIxp400SysClockRateGet
-
-/*
- * required by FS but is not really platform-specific.
- */
-#define IX_OSAL_OEM_TIME_GET(pTv) ixOsalTimeGet(pTv)
-
-
-
-/* linux map/unmap functions */
-PUBLIC void ixOsalLinuxMemMap (IxOsalMemoryMap * map);
-
-PUBLIC void ixOsalLinuxMemUnmap (IxOsalMemoryMap * map);
-
-
-/*********************
- * Memory map
- ********************/
-
-/* Global memmap only visible to IO MEM module */
-
-#ifdef IxOsalIoMem_C
-
-IxOsalMemoryMap ixOsalGlobalMemoryMap[] = {
- {
- /* Global BE and LE_AC map */
- IX_OSAL_STATIC_MAP, /* type */
- 0x00000000, /* physicalAddress */
- 0x30000000, /* size */
- 0x00000000, /* virtualAddress */
- NULL, /* mapFunction */
- NULL, /* unmapFunction */
- 0, /* refCount */
- IX_OSAL_BE | IX_OSAL_LE_AC,/* endianType */
- "global_low" /* name */
- },
-
- /* SDRAM LE_DC alias */
- {
- IX_OSAL_STATIC_MAP, /* type */
- 0x00000000, /* physicalAddress */
- 0x10000000, /* size */
- 0x30000000, /* virtualAddress */
- NULL, /* mapFunction */
- NULL, /* unmapFunction */
- 0, /* refCount */
- IX_OSAL_LE_DC, /* endianType */
- "sdram_dc" /* name */
- },
-
- /* QMGR LE_DC alias */
- {
- IX_OSAL_STATIC_MAP, /* type */
- 0x60000000, /* physicalAddress */
- 0x00100000, /* size */
- 0x60000000, /* virtualAddress */
- NULL, /* mapFunction */
- NULL, /* unmapFunction */
- 0, /* refCount */
- IX_OSAL_LE_DC, /* endianType */
- "qmgr_dc" /* name */
- },
-
- /* QMGR BE alias */
- {
- IX_OSAL_STATIC_MAP, /* type */
- 0x60000000, /* physicalAddress */
- 0x00100000, /* size */
- 0x60000000, /* virtualAddress */
- NULL, /* mapFunction */
- NULL, /* unmapFunction */
- 0, /* refCount */
- IX_OSAL_BE | IX_OSAL_LE_AC,/* endianType */
- "qmgr_be" /* name */
- },
-
- /* Global BE and LE_AC map */
- {
- IX_OSAL_STATIC_MAP, /* type */
- 0x40000000, /* physicalAddress */
- 0x20000000, /* size */
- 0x40000000, /* virtualAddress */
- NULL, /* mapFunction */
- NULL, /* unmapFunction */
- 0, /* refCount */
- IX_OSAL_BE | IX_OSAL_LE_AC,/* endianType */
- "Misc Cfg" /* name */
- },
-
- /* Global BE and LE_AC map */
- {
- IX_OSAL_STATIC_MAP, /* type */
- 0x70000000, /* physicalAddress */
- 0x8FFFFFFF, /* size */
- 0x70000000, /* virtualAddress */
- NULL, /* mapFunction */
- NULL, /* unmapFunction */
- 0, /* refCount */
- IX_OSAL_BE | IX_OSAL_LE_AC,/* endianType */
- "Exp Cfg" /* name */
- },
-};
-
-#endif /* IxOsalIoMem_C */
-#endif /* #define IxOsalOsIxp400_H */
+++ /dev/null
-/**
- * @file IxOsalOsIxp400CustomizedMapping.h
- *
- * @brief Set LE coherency modes for components.
- * The default setting is IX_OSAL_NO_MAPPING for LE.
- *
- *
- * By default IX_OSAL_STATIC_MEMORY_MAP is defined for all the components.
- * If any component uses a dynamic memory map it must define
- * IX_OSAL_DYNAMIC_MEMORY_MAP in its corresponding section.
- *
- *
- * @par
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsalOsIxp400CustomizedMapping_H
-#define IxOsalOsIxp400CustomizedMapping_H
-
-/*
- * only include this file in Little Endian
- */
-
-#if defined (IX_OSAL_LINUX_BE)
-#error Only include IxOsalOsIxp400CustomizedMapping.h in Little Endian
-#endif
-
- /*
- * Components don't have to be in this list if
- * the default mapping is OK.
- */
-#define ix_osal 1
-#define ix_dmaAcc 2
-#define ix_atmdAcc 3
-
-#define ix_atmsch 5
-#define ix_ethAcc 6
-#define ix_npeMh 7
-#define ix_qmgr 8
-#define ix_npeDl 9
-#define ix_atmm 10
-#define ix_hssAcc 11
-#define ix_ethDB 12
-#define ix_ethMii 13
-#define ix_timerCtrl 14
-#define ix_adsl 15
-#define ix_usb 16
-#define ix_uartAcc 17
-#define ix_featureCtrl 18
-#define ix_cryptoAcc 19
-#define ix_unloadAcc 33
-#define ix_perfProfAcc 34
-#define ix_parityENAcc 49
-#define ix_sspAcc 51
-#define ix_timeSyncAcc 52
-#define ix_i2c 53
-
-#define ix_codelets_uartAcc 21
-#define ix_codelets_timers 22
-#define ix_codelets_atm 23
-#define ix_codelets_ethAal5App 24
-#define ix_codelets_demoUtils 26
-#define ix_codelets_usb 27
-#define ix_codelets_hssAcc 28
-#define ix_codelets_dmaAcc 40
-#define ix_codelets_cryptoAcc 41
-#define ix_codelets_perfProfAcc 42
-#define ix_codelets_ethAcc 43
-#define ix_codelets_parityENAcc 54
-#define ix_codelets_timeSyncAcc 55
-
-
-#endif /* IxOsalOsIxp400CustomizedMapping_H */
-
-
-/***************************
- * osal
- ***************************/
-#if (IX_COMPONENT_NAME == ix_osal)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* osal */
-
-/***************************
- * dmaAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_dmaAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* dmaAcc */
-
-/***************************
- * atmdAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_atmdAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* atmdAcc */
-
-/***************************
- * atmsch
- ***************************/
-#if (IX_COMPONENT_NAME == ix_atmsch)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* atmsch */
-
-/***************************
- * ethAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_ethAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* ethAcc */
-
-/***************************
- * npeMh
- ***************************/
-#if (IX_COMPONENT_NAME == ix_npeMh)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* npeMh */
-
-/***************************
- * qmgr
- ***************************/
-#if (IX_COMPONENT_NAME == ix_qmgr)
-
-#define IX_OSAL_LE_DC_MAPPING
-
-#endif /* qmgr */
-
-/***************************
- * npeDl
- ***************************/
-#if (IX_COMPONENT_NAME == ix_npeDl)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* npeDl */
-
-/***************************
- * atmm
- ***************************/
-#if (IX_COMPONENT_NAME == ix_atmm)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* atmm */
-
-/***************************
- * ethMii
- ***************************/
-#if (IX_COMPONENT_NAME == ix_ethMii)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* ethMii */
-
-
-/***************************
- * adsl
- ***************************/
-#if (IX_COMPONENT_NAME == ix_adsl)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* adsl */
-
-/***************************
- * usb
- ***************************/
-#if (IX_COMPONENT_NAME == ix_usb)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* usb */
-
-/***************************
- * uartAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_uartAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* uartAcc */
-
-/***************************
- * featureCtrl
- ***************************/
-#if (IX_COMPONENT_NAME == ix_featureCtrl)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* featureCtrl */
-
-/***************************
- * cryptoAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_cryptoAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* cryptoAcc */
-
-/***************************
- * codelets_usb
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_usb)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* codelets_usb */
-
-
-/***************************
- * codelets_uartAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_uartAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* codelets_uartAcc */
-
-
-
-/***************************
- * codelets_timers
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_timers)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* codelets_timers */
-
-/***************************
- * codelets_atm
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_atm)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* codelets_atm */
-
-/***************************
- * codelets_ethAal5App
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_ethAal5App)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* codelets_ethAal5App */
-
-/***************************
- * codelets_ethAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_ethAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* codelets_ethAcc */
-
-
-/***************************
- * codelets_demoUtils
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_demoUtils)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* codelets_demoUtils */
-
-
-
-/***************************
- * perfProfAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_perfProfAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* perfProfAcc */
-
-
-/***************************
- * unloadAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_unloadAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* unloadAcc */
-
-
-
-
-
-/***************************
- * parityENAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_parityENAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* parityENAcc */
-
-/***************************
- * codelets_parityENAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_parityENAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* codelets_parityENAcc */
-
-
-
-
-/***************************
- * timeSyncAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_timeSyncAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* timeSyncAcc */
-
-
-/***************************
- * codelets_timeSyncAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_timeSyncAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* codelets_timeSyncAcc */
-
-
-
-
-/***************************
- * i2c
- ***************************/
-#if (IX_COMPONENT_NAME == ix_i2c)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* i2c */
-
-
-
-/***************************
- * sspAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_sspAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* sspAcc */
-
-
+++ /dev/null
-#ifndef IxOsalOsTypes_H
-#define IxOsalOsTypes_H
-
-#include <asm/types.h>
-
-typedef s64 INT64;
-typedef u64 UINT64;
-typedef s32 INT32;
-typedef u32 UINT32;
-typedef s16 INT16;
-typedef u16 UINT16;
-typedef s8 INT8;
-typedef u8 UINT8;
-
-typedef u32 ULONG;
-typedef u16 USHORT;
-typedef u8 UCHAR;
-typedef u32 BOOL;
-
-#if 0 /* FIXME */
-
-/* Default stack limit is 10 KB */
-#define IX_OSAL_OS_THREAD_DEFAULT_STACK_SIZE (10240)
-
-/* Maximum stack limit is 32 MB */
-#define IX_OSAL_OS_THREAD_MAX_STACK_SIZE (33554432) /* 32 MBytes */
-
-/* Default thread priority */
-#define IX_OSAL_OS_DEFAULT_THREAD_PRIORITY (90)
-
-/* Thread maximum priority (0 - 255). 0 - highest priority */
-#define IX_OSAL_OS_MAX_THREAD_PRIORITY (255)
-
-#endif /* FIXME */
-
-#define IX_OSAL_OS_WAIT_FOREVER (-1L)
-#define IX_OSAL_OS_WAIT_NONE 0
-
-
-/* Thread handle is eventually an int type */
-typedef int IxOsalOsThread;
-
-/* Semaphore handle FIXME */
-typedef int IxOsalOsSemaphore;
-
-/* Mutex handle */
-typedef int IxOsalOsMutex;
-
-/*
- * Fast mutex handle - fast mutex operations are implemented in
- * native assembler code using atomic test-and-set instructions
- */
-typedef int IxOsalOsFastMutex;
-
-typedef struct
-{
-} IxOsalOsMessageQueue;
-
-
-#endif /* IxOsalOsTypes_H */
+++ /dev/null
-#ifndef IxOsalOsUtilitySymbols_H
-#define IxOsalOsUtilitySymbols_H
-
-#endif /* IxOsalOsUtilitySymbols_H */
+++ /dev/null
-/**
- * @file IxOsalTypes.h
- *
- * @brief Define OSAL basic data types.
- *
- * This file contains fundamental data types used by OSAL.
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#ifndef IxOsalTypes_H
-#define IxOsalTypes_H
-
-#include <config.h>
-#include <common.h>
-
-#define __ixp42X /* sr: U-Boot needs this define */
-#define IXP425_EXP_CFG_BASE 0xC4000000
-#define diag_printf debug
-
-#undef SIMSPARCSOLARIS
-#define SIMSPARCSOLARIS 0xaffe /* sr: U-Boot gets confused with this solaris define */
-
-/*
- * Include the OS-specific type definitions
- */
-#include "IxOsalOsTypes.h"
-/**
- * @defgroup IxOsalTypes Osal basic data types.
- *
- * @brief Basic data types for Osal
- *
- * @{
- */
-
-/**
- * @brief OSAL status
- *
- * @note Possible OSAL return status include IX_SUCCESS and IX_FAIL.
- */
-typedef UINT32 IX_STATUS;
-
-/**
- * @brief VUINT32
- *
- * @note volatile UINT32
- */
-typedef volatile UINT32 VUINT32;
-
-/**
- * @brief VINT32
- *
- * @note volatile INT32
- */
-typedef volatile INT32 VINT32;
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_BILLION
- *
- * @brief Alias for 1,000,000,000
- *
- */
-#define IX_OSAL_BILLION (1000000000)
-
-#ifndef NULL
-#define NULL 0L
-#endif
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_SUCCESS
- *
- * @brief Success status
- *
- */
-#ifndef IX_SUCCESS
-#define IX_SUCCESS 0L /**< #defined as 0L */
-#endif
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_FAIL
- *
- * @brief Failure status
- *
- */
-#ifndef IX_FAIL
-#define IX_FAIL 1L /**< #defined as 1L */
-#endif
-
-
-#ifndef PRIVATE
-#ifdef IX_PRIVATE_OFF
-#define PRIVATE /* nothing */
-#else
-#define PRIVATE static /**< #defined as static, except for debug builds */
-#endif /* IX_PRIVATE_OFF */
-#endif /* PRIVATE */
-
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_INLINE
- *
- * @brief Alias for __inline
- *
- */
-#ifndef IX_OSAL_INLINE
-#define IX_OSAL_INLINE __inline
-#endif /* IX_OSAL_INLINE */
-
-
-#ifndef __inline__
-#define __inline__ IX_OSAL_INLINE
-#endif
-
-
-/* Each OS can define its own PUBLIC, otherwise it will be empty. */
-#ifndef PUBLIC
-#define PUBLIC
-#endif /* PUBLIC */
-
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_INLINE_EXTERN
- *
- * @brief Alias for __inline extern
- *
- */
-#ifndef IX_OSAL_INLINE_EXTERN
-#define IX_OSAL_INLINE_EXTERN IX_OSAL_INLINE extern
-#endif
-
-/**
- * @ingroup IxOsalTypes
- * @enum IxOsalLogDevice
- * @brief This is an emum for OSAL log devices.
- */
-typedef enum
-{
- IX_OSAL_LOG_DEV_STDOUT = 0, /**< standard output (implemented by default) */
- IX_OSAL_LOG_DEV_STDERR = 1, /**< standard error (implemented */
- IX_OSAL_LOG_DEV_HEX_DISPLAY = 2, /**< hexadecimal display (not implemented) */
- IX_OSAL_LOG_DEV_ASCII_DISPLAY = 3 /**< ASCII-capable display (not implemented) */
-} IxOsalLogDevice;
-
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_LOG_ERROR
- *
- * @brief Alias for -1, used as log function error status
- *
- */
-#define IX_OSAL_LOG_ERROR (-1)
-
-/**
- * @ingroup IxOsalTypes
- * @enum IxOsalLogLevel
- * @brief This is an emum for OSAL log trace level.
- */
-typedef enum
-{
- IX_OSAL_LOG_LVL_NONE = 0, /**<No trace level */
- IX_OSAL_LOG_LVL_USER = 1, /**<Set trace level to user */
- IX_OSAL_LOG_LVL_FATAL = 2, /**<Set trace level to fatal */
- IX_OSAL_LOG_LVL_ERROR = 3, /**<Set trace level to error */
- IX_OSAL_LOG_LVL_WARNING = 4, /**<Set trace level to warning */
- IX_OSAL_LOG_LVL_MESSAGE = 5, /**<Set trace level to message */
- IX_OSAL_LOG_LVL_DEBUG1 = 6, /**<Set trace level to debug1 */
- IX_OSAL_LOG_LVL_DEBUG2 = 7, /**<Set trace level to debug2 */
- IX_OSAL_LOG_LVL_DEBUG3 = 8, /**<Set trace level to debug3 */
- IX_OSAL_LOG_LVL_ALL /**<Set trace level to all */
-} IxOsalLogLevel;
-
-
-/**
- * @ingroup IxOsalTypes
- * @brief Void function pointer prototype
- *
- * @note accepts a void pointer parameter
- * and does not return a value.
- */
-typedef void (*IxOsalVoidFnVoidPtr) (void *);
-
-typedef void (*IxOsalVoidFnPtr) (void);
-
-
-/**
- * @brief Timeval structure
- *
- * @note Contain subfields of seconds and nanoseconds..
- */
-typedef struct
-{
- UINT32 secs; /**< seconds */
- UINT32 nsecs; /**< nanoseconds */
-} IxOsalTimeval;
-
-
-/**
- * @ingroup IxOsalTypes
- * @brief IxOsalTimer
- *
- * @note OSAL timer handle
- *
- */
-typedef UINT32 IxOsalTimer;
-
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_WAIT_FOREVER
- *
- * @brief Definition for timeout forever, OS-specific.
- *
- */
-#define IX_OSAL_WAIT_FOREVER IX_OSAL_OS_WAIT_FOREVER
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_WAIT_NONE
- *
- * @brief Definition for timeout 0, OS-specific.
- *
- */
-#define IX_OSAL_WAIT_NONE IX_OSAL_OS_WAIT_NONE
-
-
-/**
- * @ingroup IxOsalTypes
- * @brief IxOsalMutex
- *
- * @note Mutex handle, OS-specific
- *
- */
-typedef IxOsalOsMutex IxOsalMutex;
-
-/**
- * @ingroup IxOsalTypes
- * @brief IxOsalFastMutex
- *
- * @note FastMutex handle, OS-specific
- *
- */
-typedef IxOsalOsFastMutex IxOsalFastMutex;
-
-/**
- * @ingroup IxOsalTypes
- * @brief IxOsalThread
- *
- * @note Thread handle, OS-specific
- *
- */
-typedef IxOsalOsThread IxOsalThread;
-
-/**
- * @ingroup IxOsalTypes
- * @brief IxOsalSemaphore
- *
- * @note Semaphore handle, OS-specific
- *
- */
-typedef IxOsalOsSemaphore IxOsalSemaphore;
-
-/**
- * @ingroup IxOsalTypes
- * @brief IxOsalMessageQueue
- *
- * @note Message Queue handle, OS-specific
- *
- */
-typedef IxOsalOsMessageQueue IxOsalMessageQueue;
-
-
-/**
- * @brief Thread Attribute
- * @note Default thread attribute
- */
-typedef struct
-{
- char *name; /**< name */
- UINT32 stackSize; /**< stack size */
- UINT32 priority; /**< priority */
-} IxOsalThreadAttr;
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_THREAD_DEFAULT_STACK_SIZE
- *
- * @brief Default thread stack size, OS-specific.
- *
- */
-#define IX_OSAL_THREAD_DEFAULT_STACK_SIZE (IX_OSAL_OS_THREAD_DEFAULT_STACK_SIZE)
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_THREAD_MAX_STACK_SIZE
- *
- * @brief Max stack size, OS-specific.
- *
- */
-#define IX_OSAL_THREAD_MAX_STACK_SIZE (IX_OSAL_OS_THREAD_MAX_STACK_SIZE)
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_DEFAULT_THREAD_PRIORITY
- *
- * @brief Default thread priority, OS-specific.
- *
- */
-#define IX_OSAL_DEFAULT_THREAD_PRIORITY (IX_OSAL_OS_DEFAULT_THREAD_PRIORITY)
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_MAX_THREAD_PRIORITY
- *
- * @brief Max thread priority, OS-specific.
- *
- */
-#define IX_OSAL_MAX_THREAD_PRIORITY (IX_OSAL_OS_MAX_THREAD_PRIORITY)
-
-/**
- * @} IxOsalTypes
- */
-
-
-#endif /* IxOsalTypes_H */
+++ /dev/null
-/**
- * @file
- *
- * @brief OSAL Configuration header file
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsalUtilitySymbols_H
-#define IxOsalUtilitySymbols_H
-
-#include "IxOsalOsUtilitySymbols.h" /* OS-specific utility symbol definitions */
-
-#endif /* IxOsalUtilitySymbols_H */
+++ /dev/null
-/**
- * @file IxParityENAcc.h
- *
- * @author Intel Corporation
- * @date 24 Mar 2004
- *
- * @brief This file contains the public API for the IXP400 Parity Error
- * Notifier access component.
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxParityENAcc IXP400 Parity Error Notifier (IxParityENAcc) API
- *
- * @brief The public API for the Parity Error Notifier
- *
- * @{
- */
-
-#ifndef IXPARITYENACC_H
-#define IXPARITYENACC_H
-
-#ifdef __ixp46X
-
-#include "IxOsal.h"
-
-/*
- * #defines for function return types, etc.
- */
-
-/**
- * @ingroup IxParityENAcc
- *
- * @enum IxParityENAccStatus
- *
- * @brief The status as returend from the API
- */
-typedef enum /**< IxParityENAccStatus */
-{
- IX_PARITYENACC_SUCCESS = IX_SUCCESS, /**< The request is successful */
- IX_PARITYENACC_INVALID_PARAMETERS, /**< Invalid or NULL parameters passed */
- IX_PARITYENACC_NOT_INITIALISED, /**< Access layer has not been initialised before accessing the APIs */
- IX_PARITYENACC_ALREADY_INITIALISED, /**< Access layer has already been initialised */
- IX_PARITYENACC_OPERATION_FAILED, /**< Operation did not succeed due to hardware failure */
- IX_PARITYENACC_NO_PARITY /**< No parity condition exits or has already been cleared */
-} IxParityENAccStatus;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @enum IxParityENAccParityType
- *
- * @brief Odd or Even Parity Type
- */
-typedef enum /**< IxParityENAccParityType */
-{
- IX_PARITYENACC_EVEN_PARITY, /**< Even Parity */
- IX_PARITYENACC_ODD_PARITY /**< Odd Parity */
-} IxParityENAccParityType;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @enum IxParityENAccConfigOption
- *
- * @brief The parity error enable/disable configuration option
- */
-typedef enum /**< IxParityENAccConfigOption */
-{
- IX_PARITYENACC_DISABLE, /**< Disable parity error detection */
- IX_PARITYENACC_ENABLE /**< Enable parity error detection */
-} IxParityENAccConfigOption;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccNpeConfig
- *
- * @brief NPE parity detection is to be enabled/disabled
- */
-typedef struct /**< IxParityENAccNpeConfig */
-{
- IxParityENAccConfigOption ideEnabled; /**< NPE IMem, DMem and External */
- IxParityENAccParityType parityOddEven; /**< Parity - Odd or Even */
-} IxParityENAccNpeConfig ;
-
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccMcuConfig
- *
- * @brief MCU pairty detection is to be enabled/disabled
- */
-typedef struct /**< IxParityENAccMcuConfig */
-{
- IxParityENAccConfigOption singlebitDetectEnabled; /**< Single-bit parity error detection */
- IxParityENAccConfigOption singlebitCorrectionEnabled; /**< Single-bit parity error correction */
- IxParityENAccConfigOption multibitDetectionEnabled; /**< Multi-bit parity error detection */
-} IxParityENAccMcuConfig ;
-
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccEbcConfig
- *
- * @brief Expansion Bus Controller parity detection is to be enabled or disabled
- *
- * Note: All the Chip Select(s) and External Masters will have the same parity
- */
-typedef struct /**< IxParityENAccEbcConfig */
-{
- IxParityENAccConfigOption ebcCs0Enabled; /**< Expansion Bus Controller - Chip Select 0 */
- IxParityENAccConfigOption ebcCs1Enabled; /**< Expansion Bus Controller - Chip Select 1 */
- IxParityENAccConfigOption ebcCs2Enabled; /**< Expansion Bus Controller - Chip Select 2 */
- IxParityENAccConfigOption ebcCs3Enabled; /**< Expansion Bus Controller - Chip Select 3 */
- IxParityENAccConfigOption ebcCs4Enabled; /**< Expansion Bus Controller - Chip Select 4 */
- IxParityENAccConfigOption ebcCs5Enabled; /**< Expansion Bus Controller - Chip Select 5 */
- IxParityENAccConfigOption ebcCs6Enabled; /**< Expansion Bus Controller - Chip Select 6 */
- IxParityENAccConfigOption ebcCs7Enabled; /**< Expansion Bus Controller - Chip Select 7 */
- IxParityENAccConfigOption ebcExtMstEnabled; /**< External Master on Expansion bus */
- IxParityENAccParityType parityOddEven; /**< Parity - Odd or Even */
-} IxParityENAccEbcConfig ;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccHWParityConfig
- *
- * @brief Parity error configuration of the Hardware Blocks
- */
-typedef struct /**< IxParityENAccHWParityConfig */
-{
- IxParityENAccNpeConfig npeAConfig; /**< NPE A parity detection is to be enabled/disabled */
- IxParityENAccNpeConfig npeBConfig; /**< NPE B parity detection is to be enabled/disabled */
- IxParityENAccNpeConfig npeCConfig; /**< NPE C parity detection is to be enabled/disabled */
- IxParityENAccMcuConfig mcuConfig; /**< MCU pairty detection is to be enabled/disabled */
- IxParityENAccConfigOption swcpEnabled; /**< SWCP parity detection is to be enabled */
- IxParityENAccConfigOption aqmEnabled; /**< AQM parity detection is to be enabled */
- IxParityENAccEbcConfig ebcConfig; /**< Expansion Bus Controller parity detection is to be enabled/disabled */
-} IxParityENAccHWParityConfig;
-
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccNpeParityErrorStats
- *
- * @brief NPE parity error statistics
- */
-typedef struct /* IxParityENAccNpeParityErrorStats */
-{
- UINT32 parityErrorsIMem; /**< Parity errors in Instruction Memory */
- UINT32 parityErrorsDMem; /**< Parity errors in Data Memory */
- UINT32 parityErrorsExternal; /**< Parity errors in NPE External Entities */
-} IxParityENAccNpeParityErrorStats;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccMcuParityErrorStats
- *
- * @brief DDR Memory Control Unit parity error statistics
- *
- * Note: There could be two outstanding parity errors at any given time whose address
- * details captured. If there is no room for the new interrupt then it would be treated
- * as overflow parity condition.
- */
-typedef struct /* IxParityENAccMcuParityErrorStats */
-{
- UINT32 parityErrorsSingleBit; /**< Parity errors of the type Single-Bit */
- UINT32 parityErrorsMultiBit; /**< Parity errors of the type Multi-Bit */
- UINT32 parityErrorsOverflow; /**< Parity errors when more than two parity errors occured */
-} IxParityENAccMcuParityErrorStats;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccEbcParityErrorStats
- *
- * @brief Expansion Bus Controller parity error statistics
- */
-typedef struct /* IxParityENAccEbcParityErrorStats */
-{
- UINT32 parityErrorsInbound; /**< Odd bit parity errors on inbound transfers */
- UINT32 parityErrorsOutbound; /**< Odd bit parity errors on outbound transfers */
-} IxParityENAccEbcParityErrorStats;
-
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccParityErrorStats
- *
- * @brief Parity Error Statistics for the all the hardware blocks
- */
-typedef struct /**< IxParityENAccParityErrorStats */
-{
- IxParityENAccNpeParityErrorStats npeStats; /**< NPE parity error statistics */
- IxParityENAccMcuParityErrorStats mcuStats; /**< MCU parity error statistics */
- IxParityENAccEbcParityErrorStats ebcStats; /**< EBC parity error statistics */
- UINT32 swcpStats; /**< SWCP parity error statistics */
- UINT32 aqmStats; /**< AQM parity error statistics */
-} IxParityENAccParityErrorStats;
-
-
-/**
- * @ingroup IxParityENAcc
- *
- * @enum IxParityENAccParityErrorSource
- *
- * @brief The source of the parity error notification
- */
-typedef enum /**< IxParityENAccParityErrorSource */
-{
- IX_PARITYENACC_NPE_A_IMEM, /**< NPE A - Instruction memory */
- IX_PARITYENACC_NPE_A_DMEM, /**< NPE A - Data memory */
- IX_PARITYENACC_NPE_A_EXT, /**< NPE A - External Entity*/
- IX_PARITYENACC_NPE_B_IMEM, /**< NPE B - Instruction memory */
- IX_PARITYENACC_NPE_B_DMEM, /**< NPE B - Data memory */
- IX_PARITYENACC_NPE_B_EXT, /**< NPE B - External Entity*/
- IX_PARITYENACC_NPE_C_IMEM, /**< NPE C - Instruction memory */
- IX_PARITYENACC_NPE_C_DMEM, /**< NPE C - Data memory */
- IX_PARITYENACC_NPE_C_EXT, /**< NPE C - External Entity*/
- IX_PARITYENACC_SWCP, /**< SWCP */
- IX_PARITYENACC_AQM, /**< AQM */
- IX_PARITYENACC_MCU_SBIT, /**< DDR Memory Controller Unit - Single bit parity */
- IX_PARITYENACC_MCU_MBIT, /**< DDR Memory Controller Unit - Multi bit parity */
- IX_PARITYENACC_MCU_OVERFLOW, /**< DDR Memory Controller Unit - Parity errors in excess of two */
- IX_PARITYENACC_EBC_CS, /**< Expansion Bus Controller - Chip Select */
- IX_PARITYENACC_EBC_EXTMST /**< Expansion Bus Controller - External Master */
-} IxParityENAccParityErrorSource;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @enum IxParityENAccParityErrorAccess
- *
- * @brief The type of access resulting in parity error
- */
-typedef enum /**< IxParityENAccParityErrorAccess */
-{
- IX_PARITYENACC_READ, /**< Read Access */
- IX_PARITYENACC_WRITE /**< Write Access */
-} IxParityENAccParityErrorAccess;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @typedef IxParityENAccParityErrorAddress
- *
- * @brief The memory location which has parity error
- */
-typedef UINT32 IxParityENAccParityErrorAddress;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @typedef IxParityENAccParityErrorData
- *
- * @brief The data read from the memory location which has parity error
- */
-typedef UINT32 IxParityENAccParityErrorData;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @enum IxParityENAccParityErrorRequester
- *
- * @brief The requester interface through which the SDRAM memory access
- * resulted in the parity error.
- */
-typedef enum /**< IxParityENAccParityErrorRequester */
-{
- IX_PARITYENACC_MPI, /**< Direct Memory Port Interface */
- IX_PARITYENACC_AHB_BUS /**< South or North AHB Bus */
-} IxParityENAccParityErrorRequester;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @enum IxParityENAccAHBErrorMaster
- *
- * @brief The Master on the AHB bus interface whose transaction might have
- * resulted in the parity error notification to XScale.
- */
-typedef enum /**< IxParityENAccAHBErrorMaster */
-{
- IX_PARITYENACC_AHBN_MST_NPE_A, /**< NPE - A */
- IX_PARITYENACC_AHBN_MST_NPE_B, /**< NPE - B */
- IX_PARITYENACC_AHBN_MST_NPE_C, /**< NPE - C */
- IX_PARITYENACC_AHBS_MST_XSCALE, /**< XScale Bus Interface Unit */
- IX_PARITYENACC_AHBS_MST_PBC, /**< PCI Bus Controller */
- IX_PARITYENACC_AHBS_MST_EBC, /**< Expansion Bus Controller */
- IX_PARITYENACC_AHBS_MST_AHB_BRIDGE, /**< AHB Bridge */
- IX_PARITYENACC_AHBS_MST_USBH /**< USB Host Controller */
-} IxParityENAccAHBErrorMaster;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @enum IxParityENAccAHBErrorSlave
- *
- * @brief The Slave on the AHB bus interface whose transaction might have
- * resulted in the parity error notification to XScale.
- */
-typedef enum /**< IxParityENAccAHBErrorSlave */
-{
- IX_PARITYENACC_AHBN_SLV_MCU, /**< Memory Control Unit */
- IX_PARITYENACC_AHBN_SLV_AHB_BRIDGE, /**< AHB Bridge */
- IX_PARITYENACC_AHBS_SLV_MCU, /**< XScale Bus Interface Unit */
- IX_PARITYENACC_AHBS_SLV_APB_BRIDGE, /**< APB Bridge */
- IX_PARITYENACC_AHBS_SLV_AQM, /**< AQM */
- IX_PARITYENACC_AHBS_SLV_RSA, /**< RSA (Crypto Bus) */
- IX_PARITYENACC_AHBS_SLV_PBC, /**< PCI Bus Controller */
- IX_PARITYENACC_AHBS_SLV_EBC, /**< Expansion Bus Controller */
- IX_PARITYENACC_AHBS_SLV_USBH /**< USB Host Controller */
-} IxParityENAccAHBErrorSlave;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccAHBErrorTransaction
- *
- * @brief The Master and Slave on the AHB bus interface whose transaction might
- * have resulted in the parity error notification to XScale.
- *
- * NOTE: This information may be used in the data abort exception handler
- * to differentiate between the XScale and non-XScale access to the SDRAM
- * memory.
- */
-typedef struct /**< IxParityENAccAHBErrorTransaction */
-{
- IxParityENAccAHBErrorMaster ahbErrorMaster; /**< Master on AHB bus */
- IxParityENAccAHBErrorSlave ahbErrorSlave; /**< Slave on AHB bus */
-} IxParityENAccAHBErrorTransaction;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccParityErrorContextMessage
- *
- * @brief Parity Error Context Message
- */
-typedef struct /**< IxParityENAccParityErrorContextMessage */
-{
- IxParityENAccParityErrorSource pecParitySource; /**< Source info of parity error */
- IxParityENAccParityErrorAccess pecAccessType; /**< Read or Write Access
- Read - NPE, SWCP, AQM, DDR MCU,
- Exp Bus Ctrlr (Outbound)
- Write - DDR MCU,
- Exp Bus Ctrlr (Inbound
- i.e., External Master) */
- IxParityENAccParityErrorAddress pecAddress; /**< Address faulty location
- Valid only for AQM, DDR MCU,
- Exp Bus Ctrlr */
- IxParityENAccParityErrorData pecData; /**< Data read from the faulty location
- Valid only for AQM and DDR MCU
- For DDR MCU it is the bit location
- of the Single-bit parity */
- IxParityENAccParityErrorRequester pecRequester; /**< Requester of SDRAM memory access
- Valid only for the DDR MCU */
- IxParityENAccAHBErrorTransaction ahbErrorTran; /**< Master and Slave information on the
- last AHB Error Transaction */
-} IxParityENAccParityErrorContextMessage;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @typedef IxParityENAccCallback
- *
- * @brief This prototype shows the format of a callback function.
- *
- * The callback will be used to notify the parity error to the client application.
- * The callback will be registered by @ref ixParityENAccCallbackRegister.
- *
- * It will be called from an ISR when a parity error is detected and thus
- * needs to follow the interrupt callable function conventions.
- *
- */
-typedef void (*IxParityENAccCallback) (void);
-
-
-/*
- * Prototypes for interface functions.
- */
-
-/**
- * @ingroup IxParityENAcc
- *
- * @fn IxParityENAccStatus ixParityENAccInit(void)
- *
- * @brief This function will initialise the IxParityENAcc component.
- *
- * This function will initialise the IxParityENAcc component. It should only be
- * called once, prior to using the IxParityENAcc component.
- *
- * <OL><LI>It initialises the internal data structures, registers the ISR that
- * will be triggered when a parity error occurs in IXP4xx silicon.</LI></OL>
- *
- * @li Re-entrant : No
- * @li ISR Callable : No
- *
- * @return @li IX_PARITYENACC_SUCCESS - Initialization is successful
- * @li IX_PARITYENACC_ALREADY_INITIALISED - The access layer has already
- * been initialized
- * @li IX_PARITYENACC_OPERATION_FAILED - The request failed because the
- * operation didn't succeed on the hardware. Refer to error trace/log
- * for details.
- */
-
-PUBLIC IxParityENAccStatus ixParityENAccInit(void);
-
-/**
- * @ingroup IxParityENAcc
- *
- * @fn IxParityENAccStatus ixParityENAccCallbackRegister (
- IxParityENAccCallback parityErrNfyCallBack)
- *
- * @brief This function will register a new callback with IxParityENAcc component.
- * It can also reregister a new callback replacing the old callback.
- *
- * @param parityErrNfyCallBack [in] - This parameter will specify the call-back
- * function supplied by the client application.
- *
- * This interface registers the user application supplied call-back handler with
- * the parity error handling access component after the init.
- *
- * The callback function will be called from an ISR that will be triggered by the
- * parity error in the IXP400 silicon.
- *
- * The following actions will be performed by this function:
- * <OL><LI>Check for the prior initialisation of the module before registering or
- * re-registering of the callback.
- * Check for parity error detection disabled before re-registration of the callback.
- * </LI></OL>
- *
- * @li Re-entrant : No
- * @li ISR Callable : No
- *
- * @return @li IX_PARITYENACC_SUCCESS - The parameters check passed and the
- * registration is successful.
- * @li IX_PARITYENACC_INVALID_PARAMETERS - Request failed due to NULL
- * parameter passed.
- * @li IX_PARITYENACC_OPERATION_FAILED - The request failed because the
- * parity error detection not yet disabled.
- * @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior to
- * the initialisation of the access layer.
- */
-
-PUBLIC IxParityENAccStatus ixParityENAccCallbackRegister (
- IxParityENAccCallback parityErrNfyCallBack);
-
-/**
- * @ingroup IxParityENAcc
- *
- * @fn IxParityENAccStatus ixParityENAccParityDetectionConfigure (
- const IxParityENAccHWParityConfig *hwParityConfig)
- *
- * @brief This interface allows the client application to enable the parity
- * error detection on the underlying hardware block.
- *
- * @param hwParityConfig [in] - Hardware blocks for which the parity error
- * detection is to be enabled or disabled.
- *
- * The client application allocates and provides the reference to the buffer.
- *
- * It will also verify whether the specific hardware block is functional or not.
- *
- * NOTE: Failure in enabling or disabling of one or more components result in
- * trace message but still returns IX_PARITYENACC_SUCCESS. Refer to the function
- * @ref ixParityENAccParityDetectionQuery on how to verify the failures while
- * enabling/disabling paritys error detection.
- *
- * It shall be invoked after the Init and CallbackRegister functions but before
- * any other function of the IxParityENAcc layer.
- *
- * @li Re-entrant : No
- * @li ISR Callable : No
- *
- * @return @li IX_PARITYENACC_SUCCESS - The parameters check passed and the
- * request to enable/disable is successful.
- * @li IX_PARITYENACC_INVALID_PARAMETERS-The request failed due to
- * NULL parameter supplied.
- * @li IX_PARITYENACC_OPERATION_FAILED - The request failed because the
- * operation didn't succeed on the hardware.
- * @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior to
- * the initialisation of the access layer.
- */
-
-PUBLIC IxParityENAccStatus ixParityENAccParityDetectionConfigure (
- const IxParityENAccHWParityConfig *hwParityConfig);
-
-/**
- * @ingroup IxParityENAcc
- *
- * @fn IxParityENAccStatus ixParityENAccParityDetectionQuery (
- IxParityENAccHWParityConfig * const hwParityConfig)
- *
- * @brief This interface allows the client application to determine the
- * status of the parity error detection on the specified hardware blocks
- *
- * @param hwParityConfig [out] - Hardware blocks whose parity error detection
- * has been enabled or disabled.
- *
- * The client application allocates and provides the reference to the buffer.
- *
- * This interface can be used immediately after the interface @ref
- * ixParityENAccParityDetectionConfigure to see on which of the hardware blocks
- * the parity error detection has either been enabled or disabled based on the
- * client application request.
- *
- * @li Re-entrant : No
- * @li ISR Callable : No
- *
- * @return @li IX_PARITYENACC_SUCCESS - The parameters check passed and the
- * request to query on whether the hardware parity error detection
- * is enabled or disabled is successful.
- * @li IX_PARITYENACC_INVALID_PARAMETERS-The request failed due to
- * NULL parameter or invalid values supplied.
- * @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior
- * to the initialisation of the access layer.
- */
-
-PUBLIC IxParityENAccStatus ixParityENAccParityDetectionQuery(
- IxParityENAccHWParityConfig * const hwParityConfig);
-
-/**
- * @ingroup IxParityENAcc
- *
- * @fn IxParityENAccStatus ixParityENAccParityErrorContextGet(
- IxParityENAccParityErrorContextMessage * const pecMessage)
- *
- * @brief This interface allows the client application to determine the
- * status of the parity error context on hardware block for which the
- * current parity error interrupt triggered.
- *
- * @param pecMessage [out] - The parity error context information of the
- * parity interrupt currently being process.
- *
- * The client application allocates and provides the reference to the buffer.
- *
- * Refer to the data structure @ref IxParityENAccParityErrorContextMessage
- * for details.
- *
- * The routine will will fetch the parity error context in the following
- * priority, if multiple parity errors observed.
- *
- * <pre>
- * 0 - MCU (Multi-bit and single-bit in that order)
- * 1 - NPE-A
- * 2 - NPE-B
- * 3 - NPE-C
- * 4 - SWCP
- * 5 - QM
- * 6 - EXP
- *
- * NOTE: The information provided in the @ref IxParityENAccAHBErrorTransaction
- * may be of help for the client application to decide on the course of action
- * to take. This info is taken from the Performance Monitoring Unit register
- * which records most recent error observed on the AHB bus. This information
- * might have been overwritten by some other error by the time it is retrieved.
- * </pre>
- *
- * @li Re-entrant : No
- * @li ISR Callable : Yes
- *
- * @return @li IX_PARITYENACC_SUCCESS-The parameters check passed and the
- * request to get the parity error context information is successful.
- * @li IX_PARITYENACC_INVALID_PARAMETERS-The request failed due to
- * NULL parameter is passed
- * @li IX_PARITYENACC_OPERATION_FAILED - The request failed because
- * the operation didn't succeed on the hardware.
- * @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior
- * to the initialisation of the access layer.
- * @li IX_PARITYENACC_NO_PARITY - No parity condition exits or has
- * already been cleared
- */
-
-PUBLIC IxParityENAccStatus ixParityENAccParityErrorContextGet(
- IxParityENAccParityErrorContextMessage * const pecMessage);
-
-/**
- * @ingroup IxParityENAcc
- *
- * @fn IxParityENAccStatus ixParityENAccParityErrorInterruptClear (
- const IxParityENAccParityErrorContextMessage *pecMessage)
- *
- * @brief This interface helps the client application to clear off the
- * interrupt condition on the hardware block identified in the parity
- * error context message. Please refer to the table below as the operation
- * varies depending on the interrupt source.
- *
- * @param pecMessage [in] - The parity error context information of the
- * hardware block whose parity error interrupt condition is to disabled.
- *
- * The client application allocates and provides the reference to the buffer.
- *
- * <pre>
- * ****************************************************************************
- * Following actions will be taken during the interrupt clear for respective
- * hardware blocks.
- *
- * Parity Source Actions taken during Interrupt clear
- * ------------- -------------------------------------------------------
- * NPE-A Interrupt will be masked off at the interrupt controller
- * so that it will not trigger continuously.
- * Client application has to take appropriate action and
- * re-configure the parity error detection subsequently.
- * The client application will not be notified of further
- * interrupts, until the re-configuration is done using
- * @ref ixParityENAccParityDetectionConfigure.
- *
- * NPE-B Interrupt will be masked off at the interrupt controller
- * so that it will not trigger continuously.
- * Client application has to take appropriate action and
- * re-configure the parity error detection subsequently.
- * The client application will not be notified of further
- * interrupts, until the re-configuration is done using
- * @ref ixParityENAccParityDetectionConfigure.
- *
- * NPE-C Interrupt will be masked off at the interrupt controller
- * Client application has to take appropriate action and
- * re-configure the parity error detection subsequently.
- * The client application will not be notified of further
- * interrupts, until the re-configuration is done using
- * @ref ixParityENAccParityDetectionConfigure.
- *
- * SWCP Interrupt will be masked off at the interrupt controller.
- * Client application has to take appropriate action and
- * re-configure the parity error detection subsequently.
- * The client application will not be notified of further
- * interrupts, until the re-configuration is done using
- * @ref ixParityENAccParityDetectionConfigure.
- *
- * AQM Interrupt will be masked off at the interrupt controller.
- * Client application has to take appropriate action and
- * re-configure the parity error detection subsequently.
- * The client application will not be notified of further
- * interrupts, until the re-configuration is done using
- * @ref ixParityENAccParityDetectionConfigure.
- *
- * MCU Parity interrupt condition is cleared at the SDRAM MCU for
- * the following:
- * 1. Single-bit
- * 2. Multi-bit
- * 3. Overflow condition i.e., more than two parity conditions
- * occurred
- * Note that single-parity errors do not result in data abort
- * and not all data aborts caused by multi-bit parity error.
- *
- * EXP Parity interrupt condition is cleared at the expansion bus
- * controller for the following:
- * 1. External master initiated Inbound write
- * 2. Internal master (IXP400) initiated Outbound read
- * ****************************************************************************
- * </pre>
- * @li Re-entrant : No
- * @li ISR Callable : No
- *
- * @return @li IX_PARITYENACC_SUCCESS-The parameters check passed and the request
- * to clear the parity error interrupt condition is successful.
- * @li IX_PARITYENACC_INVALID_PARAMETERS-The request failed due to
- * NULL parameters have been passed or contents have been
- * supplied with invalid values.
- * @li IX_PARITYENACC_OPERATION_FAILED - The request failed because
- * the operation didn't succeed on the hardware.
- * @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior
- * to the initialisation of the access layer.
- */
-
-PUBLIC IxParityENAccStatus ixParityENAccParityErrorInterruptClear (
- const IxParityENAccParityErrorContextMessage *pecMessage);
-
-/**
- * @ingroup IxParityENAcc
- *
- * @fn IxParityENAccStatus ixParityENAccStatsGet (
- IxParityENAccParityErrorStats * const ixParityErrorStats)
- *
- * @brief This interface allows the client application to retrieve parity
- * error statistics for all the hardware blocks
- *
- * @param ixParityErrorStats - [out] The statistics for all the hardware blocks.
- *
- * The client application allocates and provides the reference to the buffer.
- *
- * @li Re-entrant : No
- * @li ISR Callable : Yes
- *
- * @return @li IX_PARITYENACC_SUCCESS-The parameters check passed and the
- * request to retrieve parity error statistics for the hardware
- * block is successful.
- * @li IX_PARITYENACC_INVALID_PARAMETERS-The request failed due to a
- * NULL parameter passed.
- * @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior
- * to the initialisation of the access layer.
- */
-
-PUBLIC IxParityENAccStatus ixParityENAccStatsGet (
- IxParityENAccParityErrorStats * const ixParityErrorStats);
-
-/**
- * @ingroup IxParityENAcc
- *
- * @fn IxParityENAccStatus ixParityENAccStatsShow (void)
- *
- * @brief This interface allows the client application to print all the
- * parity error statistics.
- *
- * @li Re-entrant : No
- * @li ISR Callable : No
- *
- * @return @li IX_PARITYENACC_SUCCESS - The request to show the pairty
- * error statistics is successful.
- * @li IX_PARITYENACC_NOT_INITIALISED - The operation requested
- * prior to the initialisation of the access layer.
- */
-
-PUBLIC IxParityENAccStatus ixParityENAccStatsShow (void);
-
-/**
- * @ingroup IxParityENAcc
- *
- * @fn IxParityENAccStatus ixParityENAccStatsReset (void)
- *
- * @brief This interface allows the client application to reset all the
- * parity error statistics.
- *
- * @li Re-entrant : No
- * @li ISR Callable : No
- *
- * @return @li IX_PARITYENACC_SUCCESS - The request to reset the parity
- * error statistics is successful.
- * @li IX_PARITYENACC_NOT_INITIALISED - The operation requested
- * prior to the initialisation of the access layer.
- */
-
-PUBLIC IxParityENAccStatus ixParityENAccStatsReset (void);
-
-#endif /* IXPARITYENACC_H */
-#endif /* __ixp46X */
-
-/**
- * @} defgroup IxParityENAcc
- */
-
+++ /dev/null
-/**
- * @file IxPerfProfAcc.h
- *
- * @brief Header file for the IXP400 Perf Prof component (IxPerfProfAcc)
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxPerfProfAcc IXP400 Performance Profiling (IxPerfProfAcc) API
- *
- * @brief IXP400 Performance Profiling Utility component Public API.
- * @li NOTE: Xcycle measurement is not supported in Linux.
- *
- *
- * @{
- */
-#ifndef IXPERFPROFACC_H
-#define IXPERFPROFACC_H
-
-#include "IxOsal.h"
-
-#ifdef __linux
-#include <linux/proc_fs.h>
-#endif
-
-/*
- * Section for #define
- */
-/**
- * @ingroup IxPerfProfAcc
- *
- * @def IX_PERFPROF_ACC_XSCALE_PMU_MAX_PROFILE_SAMPLES
- *
- * @brief This is the maximum number of profiling samples allowed, which can be
- * modified according to the user's discretion
- */
-#define IX_PERFPROF_ACC_XSCALE_PMU_MAX_PROFILE_SAMPLES 0xFFFF
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @def IX_PERFPROF_ACC_BUS_PMU_MAX_PECS
- *
- * @brief This is the maximum number of Programmable Event Counters available.
- * This is a hardware specific and fixed value. Do not change.
- *
- */
-#define IX_PERFPROF_ACC_BUS_PMU_MAX_PECS 7
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @def IX_PERFPROF_ACC_XCYCLE_MAX_NUM_OF_MEASUREMENTS
- *
- * @brief Max number of measurement allowed. This constant is used when
- * creating storage array for Xcycle. When run in continuous mode,
- * Xcycle will wrap around and re-use buffer.
- */
-#define IX_PERFPROF_ACC_XCYCLE_MAX_NUM_OF_MEASUREMENTS 600
-
-#ifdef __linux
-/**
- * @ingroup IxPerfProfAcc
- *
- * @def IX_PERFPROF_ACC_XSCALE_PMU_SYMBOL_ACCURACY
- *
- * @brief Level of accuracy required for matching the PC Address to
- * symbol address. This is used when the XScale PMU time/event
- * sampling functions get the PC address and search for the
- * corresponding symbol address.
- */
-#define IX_PERFPROF_ACC_XSCALE_PMU_SYMBOL_ACCURACY 0xffff
-
-#endif /*__linux*/
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @def IX_PERFPROF_ACC_LOG
- *
- * @brief Mechanism for logging a formatted message for the PerfProfAcc component
- *
- * @param level UINT32 [in] - trace level
- * @param device UINT32 [in] - output device
- * @param str char* [in] - format string, similar to printf().
- * @param a UINT32 [in] - first argument to display
- * @param b UINT32 [in] - second argument to display
- * @param c UINT32 [in] - third argument to display
- * @param d UINT32 [in] - fourth argument to display
- * @param e UINT32 [in] - fifth argument to display
- * @param f UINT32 [in] - sixth argument to display
- *
- * @return none
- */
-#ifndef NDEBUG
-#define IX_PERFPROF_ACC_LOG(level, device, str, a, b, c, d, e, f)\
- (ixOsalLog (level, device, str, a, b, c, d, e, f))
-#else /*do nothing*/
-#define IX_PERFPROF_ACC_LOG(level, device, str, a, b, c, d, e, f)
-#endif /*ifdef NDEBUG */
-
-/*
- * Section for struct
- */
-
-/**
- * @brief contains summary of samples taken
- *
- * Structure contains all details of each program counter value - frequency
- * that PC occurs
- */
-typedef struct
-{
- UINT32 programCounter; /**<the program counter value of the sample*/
- UINT32 freq; /**<the frequency of the occurence of the sample*/
-} IxPerfProfAccXscalePmuSamplePcProfile;
-
-/**
- * @brief contains results of a counter
- *
- * Structure contains the results of a counter, which are split into the lower
- * and upper 32 bits of the final count
- */
-typedef struct
-{
- UINT32 lower32BitsEventCount; /**<lower 32bits value of the event counter*/
- UINT32 upper32BitsEventCount; /**<upper 32bits value of the event counter*/
-} IxPerfProfAccXscalePmuEvtCnt;
-
-/**
- * @brief contains results of counters and their overflow
- *
- * Structure contains all values of counters and associated overflows. The
- * specific event and clock counters are determined by the user
- */
-typedef struct
-{
- UINT32 clk_value; /**<current value of clock counter*/
- UINT32 clk_samples; /**<number of clock counter overflows*/
- UINT32 event1_value; /**<current value of event 1 counter*/
- UINT32 event1_samples; /**<number of event 1 counter overflows*/
- UINT32 event2_value; /**<current value of event 2 counter*/
- UINT32 event2_samples; /**<number of event 2 counter overflows*/
- UINT32 event3_value; /**<current value of event 3 counter*/
- UINT32 event3_samples; /**<number of event 3 counter overflows*/
- UINT32 event4_value; /**<current value of event 4 counter*/
- UINT32 event4_samples; /**<number of event 4 counter overflows*/
-} IxPerfProfAccXscalePmuResults;
-
-/**
- *
- * @brief Results obtained from Xcycle run
- */
-typedef struct
-{
- float maxIdlePercentage; /**<maximum percentage of Idle cycles*/
- float minIdlePercentage; /**<minimum percentage of Idle cycles*/
- float aveIdlePercentage; /**<average percentage of Idle cycles*/
- UINT32 totalMeasurements; /**<total number of measurement made */
-} IxPerfProfAccXcycleResults;
-
-/**
- *
- * @brief Results obtained from running the Bus Pmu component. The results
- * are obtained when the get functions is called.
- *
- */
-typedef struct
-{
- UINT32 statsToGetLower27Bit[IX_PERFPROF_ACC_BUS_PMU_MAX_PECS]; /**<Lower 27 Bit of counter value */
- UINT32 statsToGetUpper32Bit[IX_PERFPROF_ACC_BUS_PMU_MAX_PECS]; /**<Upper 32 Bit of counter value */
-} IxPerfProfAccBusPmuResults;
-
-/*
- * Section for enum
- */
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @enum IxPerfProfAccBusPmuEventCounters1
- *
- * @brief Type of bus pmu events supported on PEC 1.
- *
- * Lists all bus pmu events.
- */
-typedef enum
-{
- IX_PERFPROF_ACC_BUS_PMU_PEC1_NORTH_NPEA_GRANT_SELECT = 1, /**< Select North NPEA grant on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_NORTH_NPEB_GRANT_SELECT, /**< Select North NPEB grant on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_NORTH_NPEC_GRANT_SELECT, /**< Select North NPEC grant on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_NORTH_BUS_IDLE_SELECT, /**< Select North bus idle on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_NORTH_NPEA_REQ_SELECT, /**< Select North NPEA req on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_NORTH_NPEB_REQ_SELECT, /**< Select North NPEB req on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_NORTH_NPEC_REQ_SELECT, /**< Select North NPEC req on PEC1*/
-
- IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_GSKT_GRANT_SELECT, /**< Select south gasket grant on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_ABB_GRANT_SELECT, /**< Select south abb grant on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_PCI_GRANT_SELECT, /**< Select south pci grant on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_APB_GRANT_SELECT, /**< Select south apb grant on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_GSKT_REQ_SELECT, /**< Select south gasket request on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_ABB_REQ_SELECT, /**< Select south abb request on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_PCI_REQ_SELECT, /**< Select south pci request on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_APB_REQ_SELECT, /**< Select south apb request on PEC1*/
-
- IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_0_HIT_SELECT, /**< Select sdram0 hit on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_1_HIT_SELECT, /**< Select sdram1 hit on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_2_HIT_SELECT, /**< Select sdram2 hit on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_3_HIT_SELECT, /**< Select sdram3 hit on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_4_MISS_SELECT, /**< Select sdram4 miss on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_5_MISS_SELECT, /**< Select sdram5 miss on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_6_MISS_SELECT, /**< Select sdram6 miss on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_7_MISS_SELECT /**< Select sdram7 miss on PEC1*/
-} IxPerfProfAccBusPmuEventCounters1;
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @enum IxPerfProfAccBusPmuEventCounters2
- *
- * @brief Type of bus pmu events supported on PEC 2.
- *
- * Lists all bus pmu events.
- */
-typedef enum
-{
- IX_PERFPROF_ACC_BUS_PMU_PEC2_NORTH_NPEA_XFER_SELECT = 24, /**< Select North NPEA transfer on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_NORTH_NPEB_XFER_SELECT, /**< Select North NPEB transfer on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_NORTH_NPEC_XFER_SELECT, /**< Select North NPEC transfer on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_NORTH_BUS_WRITE_SELECT, /**< Select North bus write on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_NORTH_NPEA_OWN_SELECT, /**< Select North NPEA own on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_NORTH_NPEB_OWN_SELECT, /**< Select North NPEB own on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_NORTH_NPEC_OWN_SELECT, /**< Select North NPEC own on PEC2*/
-
- IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_GSKT_XFER_SELECT, /**< Select South gasket transfer on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_ABB_XFER_SELECT, /**< Select South abb transfer on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_PCI_XFER_SELECT, /**< Select South pci transfer on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_APB_XFER_SELECT, /**< Select South apb transfer on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_GSKT_OWN_SELECT, /**< Select South gasket own on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_ABB_OWN_SELECT, /**< Select South abb own on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_PCI_OWN_SELECT, /**< Select South pci own on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_APB_OWN_SELECT, /**< Select South apb own transfer on PEC2*/
-
- IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_1_HIT_SELECT, /**< Select sdram1 hit on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_2_HIT_SELECT, /**< Select sdram2 hit on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_3_HIT_SELECT, /**< Select sdram3 hit on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_4_HIT_SELECT, /**< Select sdram4 hit on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_5_MISS_SELECT, /**< Select sdram5 miss on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_6_MISS_SELECT, /**< Select sdram6 miss on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_7_MISS_SELECT, /**< Select sdram7 miss on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_0_MISS_SELECT /**< Select sdram0 miss on PEC2*/
-} IxPerfProfAccBusPmuEventCounters2;
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @enum IxPerfProfAccBusPmuEventCounters3
- *
- * @brief Type of bus pmu events supported on PEC 3.
- *
- * Lists all bus pmu events.
- */
-typedef enum
-{
- IX_PERFPROF_ACC_BUS_PMU_PEC3_NORTH_NPEA_RETRY_SELECT = 47, /**< Select north NPEA retry on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_NORTH_NPEB_RETRY_SELECT, /**< Select north NPEB retry on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_NORTH_NPEC_RETRY_SELECT, /**< Select north NPEC retry on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_NORTH_BUS_READ_SELECT, /**< Select north bus read on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_NORTH_NPEA_WRITE_SELECT, /**< Select north NPEA write on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_NORTH_NPEB_WRITE_SELECT, /**< Select north NPEB write on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_NORTH_NPEC_WRITE_SELECT, /**< Select north NPEC wirte on PEC3*/
-
- IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_GSKT_RETRY_SELECT, /**< Select south gasket retry on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_ABB_RETRY_SELECT, /**< Select south abb retry on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_PCI_RETRY_SELECT, /**< Select south pci retry on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_APB_RETRY_SELECT, /**< Select south apb retry on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_GSKT_WRITE_SELECT, /**< Select south gasket write on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_ABB_WRITE_SELECT, /**< Select south abb write on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_PCI_WRITE_SELECT, /**< Select south pci write on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_APB_WRITE_SELECT, /**< Select south apb write on PEC3*/
-
- IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_2_HIT_SELECT, /**< Select sdram2 hit on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_3_HIT_SELECT, /**< Select sdram3 hit on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_4_HIT_SELECT, /**< Select sdram4 hit on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_5_HIT_SELECT, /**< Select sdram5 hit on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_6_MISS_SELECT, /**< Select sdram6 miss on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_7_MISS_SELECT, /**< Select sdram7 miss on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_0_MISS_SELECT, /**< Select sdram0 miss on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_1_MISS_SELECT /**< Select sdram1 miss on PEC3*/
-} IxPerfProfAccBusPmuEventCounters3;
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @enum IxPerfProfAccBusPmuEventCounters4
- *
- * @brief Type of bus pmu events supported on PEC 4.
- *
- * Lists all bus pmu events.
- */
-typedef enum
-{
- IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_PCI_SPLIT_SELECT = 70, /**< Select south pci split on PEC4*/
- IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_EXP_SPLIT_SELECT, /**< Select south expansion split on PEC4*/
- IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_APB_GRANT_SELECT, /**< Select south apb grant on PEC4*/
- IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_APB_XFER_SELECT, /**< Select south apb transfer on PEC4*/
- IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_GSKT_READ_SELECT, /**< Select south gasket read on PEC4*/
- IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_ABB_READ_SELECT, /**< Select south abb read on PEC4*/
- IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_PCI_READ_SELECT, /**< Select south pci read on PEC4*/
- IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_APB_READ_SELECT, /**< Select south apb read on PEC4*/
-
- IX_PERFPROF_ACC_BUS_PMU_PEC4_NORTH_ABB_SPLIT_SELECT, /**< Select north abb split on PEC4*/
- IX_PERFPROF_ACC_BUS_PMU_PEC4_NORTH_NPEA_REQ_SELECT, /**< Select north NPEA req on PEC4*/
- IX_PERFPROF_ACC_BUS_PMU_PEC4_NORTH_NPEA_READ_SELECT, /**< Select north NPEA read on PEC4*/
- IX_PERFPROF_ACC_BUS_PMU_PEC4_NORTH_NPEB_READ_SELECT, /**< Select north NPEB read on PEC4*/
- IX_PERFPROF_ACC_BUS_PMU_PEC4_NORTH_NPEC_READ_SELECT, /**< Select north NPEC read on PEC4*/
-
- IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_3_HIT_SELECT, /**< Select sdram3 hit on PEC4*/
- IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_4_HIT_SELECT, /**< Select sdram4 hit on PEC4*/
- IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_5_HIT_SELECT, /**< Select sdram5 hit on PEC4*/
- IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_6_HIT_SELECT, /**< Select sdram6 hit on PEC4*/
- IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_7_MISS_SELECT, /**< Select sdram7 miss on PEC4*/
- IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_0_MISS_SELECT, /**< Select sdram0 miss on PEC4*/
- IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_1_MISS_SELECT, /**< Select sdram1 miss on PEC4*/
- IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_2_MISS_SELECT /**< Select sdram2 miss on PEC4*/
-} IxPerfProfAccBusPmuEventCounters4;
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @enum IxPerfProfAccBusPmuEventCounters5
- *
- * @brief Type of bus pmu events supported on PEC 5.
- *
- * Lists all bus pmu events.
- */
-typedef enum
-{
- IX_PERFPROF_ACC_BUS_PMU_PEC5_SOUTH_ABB_GRANT_SELECT = 91, /**< Select south abb grant on PEC5*/
- IX_PERFPROF_ACC_BUS_PMU_PEC5_SOUTH_ABB_XFER_SELECT, /**< Select south abb transfer on PEC5*/
- IX_PERFPROF_ACC_BUS_PMU_PEC5_SOUTH_ABB_RETRY_SELECT, /**< Select south abb retry on PEC5*/
- IX_PERFPROF_ACC_BUS_PMU_PEC5_SOUTH_EXP_SPLIT_SELECT, /**< Select south expansion split on PEC5*/
- IX_PERFPROF_ACC_BUS_PMU_PEC5_SOUTH_ABB_REQ_SELECT, /**< Select south abb request on PEC5*/
- IX_PERFPROF_ACC_BUS_PMU_PEC5_SOUTH_ABB_OWN_SELECT, /**< Select south abb own on PEC5*/
- IX_PERFPROF_ACC_BUS_PMU_PEC5_SOUTH_BUS_IDLE_SELECT, /**< Select south bus idle on PEC5*/
-
- IX_PERFPROF_ACC_BUS_PMU_PEC5_NORTH_NPEB_GRANT_SELECT, /**< Select north NPEB grant on PEC5*/
- IX_PERFPROF_ACC_BUS_PMU_PEC5_NORTH_NPEB_XFER_SELECT, /**< Select north NPEB transfer on PEC5*/
- IX_PERFPROF_ACC_BUS_PMU_PEC5_NORTH_NPEB_RETRY_SELECT, /**< Select north NPEB retry on PEC5*/
- IX_PERFPROF_ACC_BUS_PMU_PEC5_NORTH_NPEB_REQ_SELECT, /**< Select north NPEB request on PEC5*/
- IX_PERFPROF_ACC_BUS_PMU_PEC5_NORTH_NPEB_OWN_SELECT, /**< Select north NPEB own on PEC5*/
- IX_PERFPROF_ACC_BUS_PMU_PEC5_NORTH_NPEB_WRITE_SELECT, /**< Select north NPEB write on PEC5*/
- IX_PERFPROF_ACC_BUS_PMU_PEC5_NORTH_NPEB_READ_SELECT, /**< Select north NPEB read on PEC5*/
-
- IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_4_HIT_SELECT, /**< Select north sdram4 hit on PEC5*/
- IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_5_HIT_SELECT, /**< Select north sdram5 hit on PEC5*/
- IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_6_HIT_SELECT, /**< Select north sdram6 hit on PEC5*/
- IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_7_HIT_SELECT, /**< Select north sdram7 hit on PEC5*/
- IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_0_MISS_SELECT, /**< Select north sdram0 miss on PEC5*/
- IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_1_MISS_SELECT, /**< Select north sdram1 miss on PEC5*/
- IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_2_MISS_SELECT, /**< Select north sdram2 miss on PEC5*/
- IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_3_MISS_SELECT /**< Select north sdram3 miss on PEC5*/
-} IxPerfProfAccBusPmuEventCounters5;
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @enum IxPerfProfAccBusPmuEventCounters6
- *
- * @brief Type of bus pmu events supported on PEC 6.
- *
- * Lists all bus pmu events.
- */
-typedef enum
-{
- IX_PERFPROF_ACC_BUS_PMU_PEC6_SOUTH_PCI_GRANT_SELECT = 113, /**< Select south pci grant on PEC6*/
- IX_PERFPROF_ACC_BUS_PMU_PEC6_SOUTH_PCI_XFER_SELECT, /**< Select south pci transfer on PEC6*/
- IX_PERFPROF_ACC_BUS_PMU_PEC6_SOUTH_PCI_RETRY_SELECT, /**< Select south pci retry on PEC6*/
- IX_PERFPROF_ACC_BUS_PMU_PEC6_SOUTH_PCI_SPLIT_SELECT, /**< Select south pci split on PEC6*/
- IX_PERFPROF_ACC_BUS_PMU_PEC6_SOUTH_PCI_REQ_SELECT, /**< Select south pci request on PEC6*/
- IX_PERFPROF_ACC_BUS_PMU_PEC6_SOUTH_PCI_OWN_SELECT, /**< Select south pci own on PEC6*/
- IX_PERFPROF_ACC_BUS_PMU_PEC6_SOUTH_BUS_WRITE_SELECT, /**< Select south pci write on PEC6*/
-
- IX_PERFPROF_ACC_BUS_PMU_PEC6_NORTH_NPEC_GRANT_SELECT, /**< Select north NPEC grant on PEC6*/
- IX_PERFPROF_ACC_BUS_PMU_PEC6_NORTH_NPEC_XFER_SELECT, /**< Select north NPEC transfer on PEC6*/
- IX_PERFPROF_ACC_BUS_PMU_PEC6_NORTH_NPEC_RETRY_SELECT, /**< Select north NPEC retry on PEC6*/
- IX_PERFPROF_ACC_BUS_PMU_PEC6_NORTH_NPEC_REQ_SELECT, /**< Select north NPEC request on PEC6*/
- IX_PERFPROF_ACC_BUS_PMU_PEC6_NORTH_NPEC_OWN_SELECT, /**< Select north NPEC own on PEC6*/
- IX_PERFPROF_ACC_BUS_PMU_PEC6_NORTH_NPEB_WRITE_SELECT, /**< Select north NPEB write on PEC6*/
- IX_PERFPROF_ACC_BUS_PMU_PEC6_NORTH_NPEC_READ_SELECT, /**< Select north NPEC read on PEC6*/
-
- IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_5_HIT_SELECT, /**< Select sdram5 hit on PEC6*/
- IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_6_HIT_SELECT, /**< Select sdram6 hit on PEC6*/
- IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_7_HIT_SELECT, /**< Select sdram7 hit on PEC6*/
- IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_0_HIT_SELECT, /**< Select sdram0 hit on PEC6*/
- IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_1_MISS_SELECT, /**< Select sdram1 miss on PEC6*/
- IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_2_MISS_SELECT, /**< Select sdram2 miss on PEC6*/
- IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_3_MISS_SELECT, /**< Select sdram3 miss on PEC6*/
- IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_4_MISS_SELECT /**< Select sdram4 miss on PEC6*/
-} IxPerfProfAccBusPmuEventCounters6;
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @enum IxPerfProfAccBusPmuEventCounters7
- *
- * @brief Type of bus pmu events supported on PEC 7.
- *
- * Lists all bus pmu events.
- */
-typedef enum
-{
- IX_PERFPROF_ACC_BUS_PMU_PEC7_SOUTH_APB_RETRY_SELECT = 135, /**< Select south apb retry on PEC7*/
- IX_PERFPROF_ACC_BUS_PMU_PEC7_SOUTH_APB_REQ_SELECT, /**< Select south apb request on PEC7*/
- IX_PERFPROF_ACC_BUS_PMU_PEC7_SOUTH_APB_OWN_SELECT, /**< Select south apb own on PEC7*/
- IX_PERFPROF_ACC_BUS_PMU_PEC7_SOUTH_BUS_READ_SELECT, /**< Select south bus read on PEC7*/
- IX_PERFPROF_ACC_BUS_PMU_PEC7_CYCLE_COUNT_SELECT /**< Select cycle count on PEC7*/
-} IxPerfProfAccBusPmuEventCounters7;
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @enum IxPerfProfAccXscalePmuEvent
- *
- * @brief Type of xscale pmu events supported
- *
- * Lists all xscale pmu events. The maximum is a default value that the user
- * should not exceed.
- */
-typedef enum
-{
- IX_PERFPROF_ACC_XSCALE_PMU_EVENT_CACHE_MISS=0, /**< cache miss*/
- IX_PERFPROF_ACC_XSCALE_PMU_EVENT_CACHE_INSTRUCTION,/**< cache instruction*/
- IX_PERFPROF_ACC_XSCALE_PMU_EVENT_STALL, /**< event stall*/
- IX_PERFPROF_ACC_XSCALE_PMU_EVENT_INST_TLB_MISS, /**< instruction tlb miss*/
- IX_PERFPROF_ACC_XSCALE_PMU_EVENT_DATA_TLB_MISS, /**< data tlb miss*/
- IX_PERFPROF_ACC_XSCALE_PMU_EVENT_BRANCH_EXEC, /**< branch executed*/
- IX_PERFPROF_ACC_XSCALE_PMU_EVENT_BRANCH_MISPREDICT, /**<branch mispredict*/
- IX_PERFPROF_ACC_XSCALE_PMU_EVENT_INST_EXEC, /**< instruction executed*/
- IX_PERFPROF_ACC_XSCALE_PMU_EVENT_FULL_EVERYCYCLE, /**<
- *Stall - data cache
- *buffers are full.
- *This event occurs
- *every cycle where
- *condition present
- */
- IX_PERFPROF_ACC_XSCALE_PMU_EVENT_ONCE, /**<
- *Stall - data cache buffers are
- *full.This event occurs once
- *for each contiguous sequence
- */
- IX_PERFPROF_ACC_XSCALE_PMU_EVENT_DATA_CACHE_ACCESS, /**< data cache access*/
- IX_PERFPROF_ACC_XSCALE_PMU_EVENT_DATA_CACHE_MISS, /**< data cache miss*/
- IX_PERFPROF_ACC_XSCALE_PMU_EVENT_DATA_CACHE_WRITEBACK, /**<data cache
- *writeback
- */
- IX_PERFPROF_ACC_XSCALE_PMU_EVENT_SW_CHANGE_PC, /**< sw change pc*/
- IX_PERFPROF_ACC_XSCALE_PMU_EVENT_MAX /**< max value*/
-} IxPerfProfAccXscalePmuEvent;
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @enum IxPerfProfAccStatus
- *
- * @brief Invalid Status Definitions
- *
- * These status will be used by the APIs to return to the user.
- */
-typedef enum
-{
- IX_PERFPROF_ACC_STATUS_SUCCESS = IX_SUCCESS, /**< success*/
- IX_PERFPROF_ACC_STATUS_FAIL = IX_FAIL, /**< fail*/
- IX_PERFPROF_ACC_STATUS_ANOTHER_UTIL_IN_PROGRESS,/**<another utility in
- *progress
- */
- IX_PERFPROF_ACC_STATUS_XCYCLE_MEASUREMENT_IN_PROGRESS, /**<measurement in
- *progress
- */
- IX_PERFPROF_ACC_STATUS_XCYCLE_NO_BASELINE, /**<no baseline yet*/
- IX_PERFPROF_ACC_STATUS_XCYCLE_MEASUREMENT_REQUEST_OUT_OF_RANGE, /**<
- * Measurement chosen
- * is out of range
- */
- IX_PERFPROF_ACC_STATUS_XCYCLE_PRIORITY_SET_FAIL, /**<
- * Cannot set
- * task priority
- */
- IX_PERFPROF_ACC_STATUS_XCYCLE_THREAD_CREATE_FAIL, /**<
- * Fail create thread
- */
- IX_PERFPROF_ACC_STATUS_XCYCLE_PRIORITY_RESTORE_FAIL, /**<
- *cannot restore
- *priority
- */
- IX_PERFPROF_ACC_STATUS_XCYCLE_MEASUREMENT_NOT_RUNNING, /**< xcycle not running*/
- IX_PERFPROF_ACC_STATUS_XSCALE_PMU_NUM_INVALID, /**< invalid number
- *entered
- */
- IX_PERFPROF_ACC_STATUS_XSCALE_PMU_EVENT_INVALID, /**< invalid pmu event*/
- IX_PERFPROF_ACC_STATUS_XSCALE_PMU_START_NOT_CALLED, /**<a start process
- *was not called
- *before attempting
- *a stop or results
- *get
- */
- IX_PERFPROF_ACC_STATUS_BUS_PMU_MODE_ERROR, /**< invalid mode*/
- IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC1_ERROR, /**< invalid pec1 entered*/
- IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC2_ERROR, /**< invalid pec2 entered*/
- IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC3_ERROR, /**< invalid pec3 entered*/
- IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC4_ERROR, /**< invalid pec4 entered*/
- IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC5_ERROR, /**< invalid pec5 entered*/
- IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC6_ERROR, /**< invalid pec6 entered*/
- IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC7_ERROR, /**< invalid pec7 entered*/
- IX_PERFPROF_ACC_STATUS_BUS_PMU_START_NOT_CALLED, /**<a start process
- *was not called
- *before attempting
- *a stop
- */
- IX_PERFPROF_ACC_STATUS_COMPONENT_NOT_SUPPORTED /**<Device or OS does not support component*/
-} IxPerfProfAccStatus;
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @enum IxPerfProfAccBusPmuMode
- *
- * @brief State selection of counters.
- *
- * These states will be used to determine the counters whose values are to be
- * read.
- */
-typedef enum
-{
- IX_PERFPROF_ACC_BUS_PMU_MODE_HALT=0, /**< halt state*/
- IX_PERFPROF_ACC_BUS_PMU_MODE_SOUTH, /**< south state*/
- IX_PERFPROF_ACC_BUS_PMU_MODE_NORTH, /**< north state*/
- IX_PERFPROF_ACC_BUS_PMU_MODE_SDRAM /**< SDRAM state*/
-} IxPerfProfAccBusPmuMode;
-
-/*
- * Section for prototypes interface functions
- */
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXscalePmuEventCountStart(
- BOOL clkCntDiv,
- UINT32 numEvents,
- IxPerfProfAccXscalePmuEvent pmuEvent1,
- IxPerfProfAccXscalePmuEvent pmuEvent2,
- IxPerfProfAccXscalePmuEvent pmuEvent3,
- IxPerfProfAccXscalePmuEvent pmuEvent4 )
- *
- * @brief This API will start the clock and event counting
- *
- * @param clkCntDiv BOOL [in] - enables/disables the clock divider. When
- * true, the divider is enabled and the clock count will be incremented
- * by one at each 64th processor clock cycle. When false, the divider
- * is disabled and the clock count will be incremented at every
- * processor clock cycle.
- * @param numEvents UINT32 [in] - the number of PMU events that are to be
- * monitored as specified by the user. For clock counting only, this
- * is set to zero.
- * @param pmuEvent1 @ref IxPerfProfAccXscalePmuEvent [in] - the specific PMU
- * event to be monitored by counter 1
- * @param pmuEvent2 @ref IxPerfProfAccXscalePmuEvent [in] - the specific PMU
- * event to be monitored by counter 2
- * @param pmuEvent3 @ref IxPerfProfAccXscalePmuEvent [in] - the specific PMU
- * event to be monitored by counter 3
- * @param pmuEvent4 @ref IxPerfProfAccXscalePmuEvent [in] - the specific PMU
- * event to be monitored by counter 4
- *
- * This API will start the clock and xscale PMU event counting. Up to
- * 4 events can be monitored simultaneously. This API has to be called before
- * ixPerfProfAccXscalePmuEventCountStop can be called.
- *
- * @return
- * - IX_PERFPROF_ACC_STATUS_SUCCESS if clock and events counting are
- * started successfully
- * - IX_PERFPROF_ACC_STATUS_FAIL if unable to start the counting
- * - IX_PERFPROF_ACC_STATUS_XSCALE_PMU_NUM_INVALID if the number of events
- * specified is out of the valid range
- * - IX_PERFPROF_ACC_STATUS_XSCALE_PMU_EVENT_INVALID if the value of the PMU
- * event specified does not exist
- * - IX_PERFPROF_ACC_STATUS_ANOTHER_UTIL_IN_PROGRESS - another utility is
- * running
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-PUBLIC IxPerfProfAccStatus
-ixPerfProfAccXscalePmuEventCountStart(
- BOOL clkCntDiv,
- UINT32 numEvents,
- IxPerfProfAccXscalePmuEvent pmuEvent1,
- IxPerfProfAccXscalePmuEvent pmuEvent2,
- IxPerfProfAccXscalePmuEvent pmuEvent3,
- IxPerfProfAccXscalePmuEvent pmuEvent4 );
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXscalePmuEventCountStop (
- IxPerfProfAccXscalePmuResults *eventCountStopResults)
- *
- * @brief This API will stop the clock and event counting
- *
- * @param *eventCountStopResults @ref IxPerfProfAccXscalePmuResults [out] - pointer
- * to struct containing results of counters and their overflow. It is the
- * users's responsibility to allocate the memory for this pointer.
- *
- * This API will stop the clock and xscale PMU events that are being counted.
- * The results of the clock and events count will be stored in the pointer
- * allocated by the user. It can only be called once
- * IxPerfProfAccEventCountStart has been called.
- *
- * @return
- * - IX_PERFPROF_ACC_STATUS_SUCCESS if clock and events counting are
- * stopped successfully
- * - IX_PERFPROF_ACC_STATUS_XSCALE_PMU_START_NOT_CALLED if
- * ixPerfProfAccXscalePmuEventCountStart is not called first.
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-
-PUBLIC IxPerfProfAccStatus
-ixPerfProfAccXscalePmuEventCountStop(
- IxPerfProfAccXscalePmuResults *eventCountStopResults);
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXscalePmuTimeSampStart(
- UINT32 samplingRate,
- BOOL clkCntDiv)
- *
- * @brief Starts the time based sampling
- *
- * @param samplingRate UINT32 [in] - sampling rate is the number of
- * clock counts before a counter overflow interrupt is generated,
- * at which, a sample is taken; the rate specified cannot be greater
- * than the counter size of 32bits or set to zero.
- * @param clkCntDiv BOOL [in] - enables/disables the clock divider. When
- * true, the divider is enabled and the clock count will be incremented
- * by one at each 64th processor clock cycle. When false, the divider
- * is disabled and the clock count will be incremented at every
- * processor clock cycle.
- *
- * This API starts the time based sampling to determine the frequency with
- * which lines of code are being executed. Sampling is done at the rate
- * specified by the user. At each sample,the value of the program counter
- * is determined. Each of these occurrences are recorded to determine the
- * frequency with which the Xscale code is being executed. This API has to be
- * called before ixPerfProfAccXscalePmuTimeSampStop can be called.
- *
- * @return
- * - IX_PERFPROF_ACC_STATUS_SUCCESS if time based sampling is started
- * successfully
- * - IX_PERFPROF_ACC_STATUS_FAIL if unable to start the sampling
- * - IX_PERFPROF_ACC_STATUS_ANOTHER_UTIL_IN_PROGRESS - another utility is
- * running
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-PUBLIC IxPerfProfAccStatus
-ixPerfProfAccXscalePmuTimeSampStart(
- UINT32 samplingRate,
- BOOL clkCntDiv);
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXscalePmuTimeSampStop(
- IxPerfProfAccXscalePmuEvtCnt *clkCount,
- IxPerfProfAccXscalePmuSamplePcProfile *timeProfile)
- *
- * @brief Stops the time based sampling
- *
- * @param *clkCount @ref IxPerfProfAccXscalePmuEvtCnt [out] - pointer to the
- * struct containing the final clock count and its overflow. It is the
- * user's responsibility to allocate the memory for this pointer.
- * @param *timeProfile @ref IxPerfProfAccXscalePmuSamplePcProfile [out] -
- * pointer to the array of profiles for each program counter value;
- * the user should set the size of the array to
- * IX_PERFPROF_ACC_XSCALE_PMU_MAX_PROFILE_SAMPLES. It is the user's
- * responsibility to allocate the memory for this pointer.
- *
- * This API stops the time based sampling. The results are stored in the
- * pointers allocated by the user. It can only be called once
- * ixPerfProfAccXscalePmuTimeSampStart has been called.
- *
- * @return
- * - IX_PERFPROF_ACC_STATUS_SUCCESS if time based sampling is stopped
- * successfully
- * - IX_PERFPROF_ACC_STATUS_XSCALE_PMU_START_NOT_CALLED if
- * ixPerfProfAccXscalePmuTimeSampStart not called first
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-PUBLIC IxPerfProfAccStatus
-ixPerfProfAccXscalePmuTimeSampStop(
- IxPerfProfAccXscalePmuEvtCnt *clkCount,
- IxPerfProfAccXscalePmuSamplePcProfile *timeProfile);
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXscalePmuEventSampStart(
- UINT32 numEvents,
- IxPerfProfAccXscalePmuEvent pmuEvent1,
- UINT32 eventRate1,
- IxPerfProfAccXscalePmuEvent pmuEvent2,
- UINT32 eventRate2,
- IxPerfProfAccXscalePmuEvent pmuEvent3,
- UINT32 eventRate3,
- IxPerfProfAccXscalePmuEvent pmuEvent4,
- UINT32 eventRate4)
- *
- * @brief Starts the event based sampling
- *
- * @param numEvents UINT32 [in] - the number of PMU events that are
- * to be monitored as specified by the user. The value should be
- * between 1-4 events at a time.
- * @param pmuEvent1 @ref IxPerfProfAccXscalePmuEvent [in] - the specific PMU
- * event to be monitored by counter 1
- * @param eventRate1 UINT32 [in] - sampling rate of counter 1. The rate is
- * the number of events before a sample taken. If 0 is specified, the
- * the full counter value (0xFFFFFFFF) is used. The rate must not be
- * greater than the full counter value.
- * @param pmuEvent2 @ref IxPerfProfAccXscalePmuEvent [in] - the specific PMU
- * event to be monitored by counter 2
- * @param eventRate2 UINT32 [in] - sampling rate of counter 2. The rate is
- * the number of events before a sample taken. If 0 is specified, the
- * full counter value (0xFFFFFFFF) is used. The rate must not be
- * greater than the full counter value.
- * @param pmuEvent3 @ref IxPerfProfAccXscalePmuEvent [in] - the specific PMU
- * event to be monitored by counter 3
- * @param eventRate3 UINT32 [in] - sampling rate of counter 3. The rate is
- * the number of events before a sample taken. If 0 is specified, the
- * full counter value (0xFFFFFFFF) is used. The rate must not be
- * greater than the full counter value.
- * @param pmuEvent4 @ref IxPerfProfAccXscalePmuEvent [in] - the specific PMU
- * event to be monitored by counter 4
- * @param eventRate4 UINT32 [in] - sampling rate of counter 4. The rate is
- * the number of events before a sample taken. If 0 is specified, the
- * full counter value (0xFFFFFFFF) is used. The rate must not be
- * greater than the full counter value.
- *
- * Starts the event based sampling to determine the frequency with
- * which events are being executed. The sampling rate is the number of events,
- * as specified by the user, before a counter overflow interrupt is
- * generated. A sample is taken at each counter overflow interrupt. At each
- * sample,the value of the program counter determines the corresponding
- * location in the code. Each of these occurrences are recorded to determine
- * the frequency with which the Xscale code in each event is executed. This API
- * has to be called before ixPerfProfAccXscalePmuEventSampStop can be called.
- *
- * @return
- * - IX_PERFPROF_ACC_STATUS_SUCCESS if event based sampling is started
- * successfully
- * - IX_PERFPROF_ACC_STATUS_FAIL if unable to start the sampling
- * - IX_PERFPROF_ACC_STATUS_XSCALE_PMU_NUM_INVALID if the number of events
- * specified is out of the valid range
- * - IX_PERFPROF_ACC_STATUS_XSCALE_PMU_EVENT_INVALID if the value of the
- * PMU event specified does not exist
- * - IX_PERFPROF_ACC_STATUS_ANOTHER_UTIL_IN_PROGRESS - another utility is
- * running
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-PUBLIC IxPerfProfAccStatus
-ixPerfProfAccXscalePmuEventSampStart(
- UINT32 numEvents,
- IxPerfProfAccXscalePmuEvent pmuEvent1,
- UINT32 eventRate1,
- IxPerfProfAccXscalePmuEvent pmuEvent2,
- UINT32 eventRate2,
- IxPerfProfAccXscalePmuEvent pmuEvent3,
- UINT32 eventRate3,
- IxPerfProfAccXscalePmuEvent pmuEvent4,
- UINT32 eventRate4);
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXscalePmuEventSampStop(
- IxPerfProfAccXscalePmuSamplePcProfile *eventProfile1,
- IxPerfProfAccXscalePmuSamplePcProfile *eventProfile2,
- IxPerfProfAccXscalePmuSamplePcProfile *eventProfile3,
- IxPerfProfAccXscalePmuSamplePcProfile *eventProfile4)
- *
- * @brief Stops the event based sampling
- *
- * @param *eventProfile1 @ref IxPerfProfAccXscalePmuSamplePcProfile [out] -
- * pointer to the array of profiles for each program counter value;
- * the user should set the size of the array to
- * IX_PERFPROF_ACC_XSCALE_PMU_MAX_PROFILE_SAMPLES. It is the
- * users's responsibility to allocate memory for this pointer.
- * @param *eventProfile2 @ref IxPerfProfAccXscalePmuSamplePcProfile [out] -
- * pointer to the array of profiles for each program counter value;
- * the user should set the size of the array to
- * IX_PERFPROF_ACC_XSCALE_PMU_MAX_PROFILE_SAMPLES. It is the
- * users's responsibility to allocate memory for this pointer.
- * @param *eventProfile3 @ref IxPerfProfAccXscalePmuSamplePcProfile [out] -
- * pointer to the array of profiles for each program counter value;
- * the user should set the size of the array to
- * IX_PERFPROF_ACC_XSCALE_PMU_MAX_PROFILE_SAMPLES. It is the
- * users's responsibility to allocate memory for this pointer.
- * @param *eventProfile4 @ref IxPerfProfAccXscalePmuSamplePcProfile [out] -
- * pointer to the array of profiles for each program counter value;
- * the user should set the size of the array to
- * IX_PERFPROF_ACC_XSCALE_PMU_MAX_PROFILE_SAMPLES. It is the
- * users's responsibility to allocate memory for this pointer.
- *
- * This API stops the event based sampling. The results are stored in the
- * pointers allocated by the user. It can only be called once
- * ixPerfProfAccEventSampStart has been called.
- *
- * @return
- * - IX_PERFPROF_ACC_STATUS_SUCCESS if event based sampling is stopped
- * successfully
- * - IX_PERFPROF_ACC_STATUS_XSCALE_PMU_START_NOT_CALLED if
- * ixPerfProfAccEventSampStart not called first.
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-PUBLIC IxPerfProfAccStatus
-ixPerfProfAccXscalePmuEventSampStop(
- IxPerfProfAccXscalePmuSamplePcProfile *eventProfile1,
- IxPerfProfAccXscalePmuSamplePcProfile *eventProfile2,
- IxPerfProfAccXscalePmuSamplePcProfile *eventProfile3,
- IxPerfProfAccXscalePmuSamplePcProfile *eventProfile4);
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXscalePmuResultsGet(IxPerfProfAccXscalePmuResults *results)
- *
- * @brief Reads the current value of the counters and their overflow
- *
- * @param *results @ref IxPerfProfAccXscalePmuResults [out] - pointer to the
- results struct. It is the user's responsibility to allocate memory
- for this pointer
- *
- * This API reads the value of all four event counters and the clock counter,
- * and the associated overflows. It does not give results associated with
- * sampling, i.e. PC and their frequencies. This API can be called at any time
- * once a process has been started. If it is called before a process has started
- * the user should be aware that the values it contains are default values and
- * might be meaningless. The values of the counters are stored in the pointer
- * allocated by the client.
- *
- * @return - none
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-PUBLIC void
-ixPerfProfAccXscalePmuResultsGet(IxPerfProfAccXscalePmuResults *results);
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccBusPmuStart(
- IxPerfProfAccBusPmuMode mode,
- IxPerfProfAccBusPmuEventCounters1 pecEvent1,
- IxPerfProfAccBusPmuEventCounters2 pecEvent2,
- IxPerfProfAccBusPmuEventCounters3 pecEvent3,
- IxPerfProfAccBusPmuEventCounters4 pecEvent4,
- IxPerfProfAccBusPmuEventCounters5 pecEvent5,
- IxPerfProfAccBusPmuEventCounters6 pecEvent6,
- IxPerfProfAccBusPmuEventCounters7 pecEvent7)
- * @brief Initializes all the counters and selects events to be monitored.
- *
- * Function initializes all the counters and assigns the events associated
- * with the counters. Users send in the mode and events they want to count.
- * This API verifies if the combination chosen is appropriate
- * and sets all the registers accordingly. Selecting HALT mode will result
- * in an error. User should use ixPerfProfAccBusPmuStop() to HALT.
- *
- *
- * @param mode @ref IxPerfProfAccStateBusPmuMode [in] - Mode selection.
- * @param pecEvent1 @ref IxPerfProfAccBusPmuEventCounters1 [in] - Event for PEC1.
- * @param pecEvent2 @ref IxPerfProfAccBusPmuEventCounters2 [in] - Event for PEC2.
- * @param pecEvent3 @ref IxPerfProfAccBusPmuEventCounters3 [in] - Event for PEC3.
- * @param pecEvent4 @ref IxPerfProfAccBusPmuEventCounters4 [in] - Event for PEC4.
- * @param pecEvent5 @ref IxPerfProfAccBusPmuEventCounters5 [in] - Event for PEC5.
- * @param pecEvent6 @ref IxPerfProfAccBusPmuEventCounters6 [in] - Event for PEC6.
- * @param pecEvent7 @ref IxPerfProfAccBusPmuEventCounters7 [in] - Event for PEC7.
- *
- * @return
- * - IX_PERFPROF_ACC_STATUS_SUCCESS - Initialization executed
- * successfully.
- * - IX_PERFPROF_ACC_STATUS_BUS_PMU_MODE_ERROR - Error in selection of
- * mode. Only NORTH, SOUTH and SDRAM modes are allowed.
- * - IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC1_ERROR - Error in selection of
- * event for PEC1
- * - IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC2_ERROR - Error in selection of
- * event for PEC2
- * - IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC3_ERROR - Error in selection of
- * event for PEC3
- * - IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC4_ERROR - Error in selection of
- * event for PEC4
- * - IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC5_ERROR - Error in selection of
- * event for PEC5
- * - IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC6_ERROR - Error in selection of
- * event for PEC6
- * - IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC7_ERROR - Error in selection of
- * event for PEC7
- * - IX_PERFPROF_ACC_STATUS_ANOTHER_UTIL_IN_PROGRESS - another utility
- * is running
- * - IX_PERFPROF_ACC_STATUS_FAIL - Failed to start because interrupt
- * service routine fails to bind.
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- **/
-PUBLIC
-IxPerfProfAccStatus ixPerfProfAccBusPmuStart (
- IxPerfProfAccBusPmuMode mode,
- IxPerfProfAccBusPmuEventCounters1 pecEvent1,
- IxPerfProfAccBusPmuEventCounters2 pecEvent2,
- IxPerfProfAccBusPmuEventCounters3 pecEvent3,
- IxPerfProfAccBusPmuEventCounters4 pecEvent4,
- IxPerfProfAccBusPmuEventCounters5 pecEvent5,
- IxPerfProfAccBusPmuEventCounters6 pecEvent6,
- IxPerfProfAccBusPmuEventCounters7 pecEvent7);
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccBusPmuStop(void)
- * @brief Stops all counters.
- *
- * This function stops all the PECs by setting the halt bit in the ESR.
- *
- *
- * @return
- * - IX_PERFPROF_ACC_STATUS_SUCCESS - Counters successfully halted.
- * - IX_PERFPROF_ACC_STATUS_FAIL - Counters could'nt be halted.
- * - IX_PERFPROF_ACC_STATUS_BUS_PMU_START_NOT_CALLED - the
- * ixPerfProfAccBusPmuStart() function is not called.
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- **/
-PUBLIC IxPerfProfAccStatus
-ixPerfProfAccBusPmuStop (void);
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccBusPmuResultsGet (
- IxPerfProfAccBusPmuResults *busPmuResults)
- * @brief Gets values of all counters
- *
- * This function is responsible for getting all the counter values from the
- * lower API and putting it into an array for the user.
- *
- * @param *busPmuResults @ref IxPerfProfAccBusPmuResults [out]
- * - Pointer to a structure of arrays to store all counter values.
- *
- * @return none
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- **/
-PUBLIC void
-ixPerfProfAccBusPmuResultsGet (IxPerfProfAccBusPmuResults *BusPmuResults);
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccBusPmuPMSRGet (
- UINT32 *pmsrValue)
- * @brief Get values of PMSR
- *
- * This API gets the Previous Master Slave Register
- * value and returns it to the calling function. This value indicates
- * which master or slave accessed the north, south bus or sdram last.
- * The value returned by this function is a 32 bit value and is read
- * from location of an offset 0x0024 of the base value.
- *
- * The PMSR value returned indicate the following:
- * <pre>
- *
- * *************************************************************************************
- * * Bit * Name * Description *
- * * *
- * *************************************************************************************
- * * [31:18] *Reserved* *
- * *************************************************************************************
- * * [17:12] * PSS * Indicates which of the slaves on *
- * * * * ARBS was previously *
- * * * * accessed by the AHBS. *
- * * * * [000001] Expansion Bus *
- * * * * [000010] SDRAM Controller *
- * * * * [000100] PCI *
- * * * * [001000] Queue Manager *
- * * * * [010000] AHB-APB Bridge *
- * * * * [100000] Reserved *
- * *************************************************************************************
- * * [11:8] * PSN * Indicates which of the Slaves on *
- * * * * ARBN was previously *
- * * * * accessed the AHBN. *
- * * * * [0001] SDRAM Controller *
- * * * * [0010] AHB-AHB Bridge *
- * * * * [0100] Reserved *
- * * * * [1000] Reserved *
- * *************************************************************************************
- * * [7:4] * PMS * Indicates which of the Masters on *
- * * * * ARBS was previously *
- * * * * accessing the AHBS. *
- * * * * [0001] Gasket *
- * * * * [0010] AHB-AHB Bridge *
- * * * * [0100] PCI *
- * * * * [1000] APB *
- * *************************************************************************************
- * * [3:0] * PMN * Indicates which of the Masters on *
- * * * * ARBN was previously *
- * * * * accessing the AHBN. *
- * * * * [0001] NPEA *
- * * * * [0010] NPEB *
- * * * * [0100] NPEC *
- * * * * [1000] Reserved *
- * *************************************************************************************
- * </pre>
- *
- * @param *pmsrValue UINT32 [out] - Pointer to return PMSR value. Users need to
- * allocate storage for psmrValue.
- *
- * @return none
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- **/
-PUBLIC void
-ixPerfProfAccBusPmuPMSRGet (
-UINT32 *pmsrValue);
-
-
-/**
- * The APIs below are specifically used for Xcycle module.
- **/
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXcycleBaselineRun (
- UINT32 *numBaselineCycle)
- *
- * @brief Perform baseline for Xcycle
- *
- * @param *numBaselineCycle UINT32 [out] - pointer to baseline value after
- * calibration. Calling function are responsible for
- * allocating memory space for this pointer.
- *
- * Global Data :
- * - None.
- *
- * This function MUST be run before the Xcycle tool can be used. This
- * function must be run immediately when the OS boots up with no other
- * addition programs running.
- * Addition note : This API will measure the time needed to perform
- * a fix amount of CPU instructions (~ 1 second worth of loops) as a
- * highest priority task and with interrupt disabled. The time measured
- * is known as the baseline - interpreted as the shortest time
- * needed to complete the amount of CPU instructions. The baseline is
- * returned as unit of time in 66Mhz clock tick.
- *
- * @return
- * - IX_PERFPROF_ACC_STATUS_SUCCESS - successful run, result is returned
- * - IX_PERFPROF_ACC_STATUS_XCYCLE_PRIORITY_SET_FAIL - failed to change
- * task priority
- * - IX_PERFPROF_ACC_STATUS_XCYCLE_PRIORITY_RESTORE_FAIL - failed to
- * restore task priority
- * - IX_PERFPROF_ACC_STATUS_ANOTHER_UTIL_IN_PROGRESS - another utility
- * is running
- * - IX_PERFPROF_ACC_STATUS_XCYCLE_MEASUREMENT_IN_PROGRESS - Xcycle
- * tool has already started
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-PUBLIC IxPerfProfAccStatus
-ixPerfProfAccXcycleBaselineRun(
- UINT32 *numBaselineCycle);
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXcycleStart(
- UINT32 numMeasurementsRequested);
- *
- * @brief Start the measurement
- *
- * @param numMeasurementsRequested UINT32 [in] - number of measurements
- * to perform. Value can be 0 to
- * IX_PERFPROF_ACC_XCYCLE_MAX_NUM_OF_MEASUREMENTS.
- * 0 indicate continuous measurement.
- *
- * Global Data :
- * - None.
- *
- *
- * Start the measurements immediately.
- * numMeasurementsRequested specifies number of measurements to run.
- * If numMeasurementsRequested is set to 0, the measurement will
- * be performed continuously until IxPerfProfAccXcycleStop()
- * is called.
- * It is estimated that 1 measurement takes approximately 1 second during
- * low CPU utilization, therefore 128 measurement takes approximately 128 sec.
- * When CPU utilization is high, the measurement will take longer.
- * This function spawn a task the perform the measurement and returns.
- * The measurement may continue even if this function returns.
- *
- * IMPORTANT: Under heavy CPU utilization, the task spawn by this
- * function may starve and fail to respond to stop command. User
- * may need to kill the task manually in this case.
- *
- * There are only IX_PERFPROF_ACC_XCYCLE_MAX_NUM_OF_MEASUREMENTS
- * storage available so storing is wrapped around if measurements are
- * more than IX_PERFPROF_ACC_XCYCLE_MAX_NUM_OF_MEASUREMENTS.
- *
- *
- * @return
- * - IX_PERFPROF_ACC_STATUS_SUCCESS - successful start, a thread is created
- * in the background to perform measurement.
- * - IX_PERFPROF_ACC_STATUS_XCYCLE_PRIORITY_SET_FAIL - failed to set
- * task priority
- * - IX_PERFPROF_ACC_STATUS_XCYCLE_THREAD_CREATE_FAIL - failed to create
- * thread to perform measurement.
- * - IX_PERFPROF_ACC_STATUS_XCYCLE_NO_BASELINE - baseline is not available
- * - IX_PERFPROF_ACC_STATUS_XCYCLE_MEASUREMENT_REQUEST_OUT_OF_RANGE -
- * value is larger than IX_PERFPROF_ACC_XCYCLE_MAX_NUM_OF_MEASUREMENTS
- * - IX_PERFPROF_ACC_STATUS_XCYCLE_MEASUREMENT_IN_PROGRESS - Xcycle tool
- * has already started
- * - IX_PERFPROF_ACC_STATUS_ANOTHER_UTIL_IN_PROGRESS - another utility is
- * running
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-PUBLIC IxPerfProfAccStatus
-ixPerfProfAccXcycleStart (
- UINT32 numMeasurementsRequested);
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXcycleStop(void);
- *
- * @brief Stop the Xcycle measurement
- *
- * @param None
- *
- * Global Data :
- * - None.
- *
- * Stop Xcycle measurements immediately. If the measurements have stopped
- * or not started, return IX_PERFPROF_STATUS_XCYCLE_MEASUREMENT_NOT_RUNNING.
- * Note: This function does not stop measurement cold. The measurement thread
- * may need a few seconds to complete the last measurement. User needs to use
- * ixPerfProfAccXcycleInProgress() to determine if measurement is indeed
- * completed.
- *
- * @return
- * - IX_PERFPROF_ACC_STATUS_SUCCESS - successful measurement is stopped
- * - IX_PERFPROF_STATUS_XCYCLE_MEASUREMENT_NOT_RUNNING - no measurement running
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-PUBLIC IxPerfProfAccStatus
-ixPerfProfAccXcycleStop(void);
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXcycleResultsGet(
- IxPerfProfAccXcycleResults *xcycleResult )
- *
- * @brief Get the results of Xcycle measurement
- *
- * @param *xcycleResult @ref IxPerfProfAccXcycleResults [out] - Pointer to
- * results of last measurements. Calling function are
- * responsible for allocating memory space for this pointer.
- *
- * Global Data :
- * - None.
- *
- * Retrieve the results of last measurement. User should use
- * ixPerfProfAccXcycleInProgress() to check if measurement is completed
- * before getting the results.
- *
- * @return
- * - IX_PERFPROF_ACC_STATUS_SUCCESS - successful
- * - IX_PERFPROF_ACC_STATUS_FAIL - result is not complete.
- * - IX_PERFPROF_ACC_STATUS_XCYCLE_NO_BASELINE - baseline is performed
- * - IX_PERFPROF_ACC_STATUS_XCYCLE_MEASUREMENT_IN_PROGRESS - Xcycle
- * tool is still running
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-PUBLIC IxPerfProfAccStatus
-ixPerfProfAccXcycleResultsGet (
- IxPerfProfAccXcycleResults *xcycleResult);
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXcycleInProgress (void)
- *
- * @brief Check if Xcycle is running
- *
- * @param None
- * Global Data :
- * - None.
- *
- * Check if Xcycle measuring task is running.
- *
- * @return
- * - true - Xcycle is running
- * - false - Xcycle is not running
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-PUBLIC BOOL
-ixPerfProfAccXcycleInProgress(void);
-
-#ifdef __linux
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXscalePmuTimeSampCreateProcFile
- *
- * @brief Enables proc file to call module function
- *
- * @param None
- *
- * Global Data :
- * - None.
- *
- * This function is declared globally to enable /proc directory system to call
- * and execute the function when the registered file is called. This function is not meant to
- * be called by the user.
- *
- * @return
- * - Length of data written to file.
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-int
-ixPerfProfAccXscalePmuTimeSampCreateProcFile (char *buf, char **start, off_t offset,
- int count, int *eof, void *data);
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXscalePmuEventSampCreateProcFile
- *
- * @brief Enables proc file to call module function
- *
- * @param None
- *
- * Global Data :
- * - None.
- *
- * This function is declared globally to enable /proc directory system to call
- * and execute the function when the registered file is called. This function is not meant to
- * be called by the user.
- *
- * @return
- * - Length of data written to file.
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-int
-ixPerfProfAccXscalePmuEventSampCreateProcFile (char *buf, char **start, off_t offset,
- int count, int *eof, void *data);
-
-
-#endif /* ifdef __linux */
-
-#endif /* ndef IXPERFPROFACC_H */
-
-/**
- *@} defgroup IxPerfProfAcc
- */
-
-
+++ /dev/null
-/**
- * @file IxQMgr.h
- *
- * @date 30-Oct-2001
- *
- * @brief This file contains the public API of IxQMgr component.
- *
- * Some functions contained in this module are inline to achieve better
- * data-path performance. For this to work, the function definitions are
- * contained in this header file. The "normal" use of inline functions
- * is to use the inline functions in the module in which they are
- * defined. In this case these inline functions are used in external
- * modules and therefore the use of "inline extern". What this means
- * is as follows: if a function foo is declared as "inline extern" this
- * definition is only used for inlining, in no case is the function
- * compiled on its own. If the compiler cannot inline the function it
- * becomes an external reference. Therefore in IxQMgrQAccess.c all
- * inline functions are defined without the "inline extern" specifier
- * and so define the external references. In all other source files
- * including this header file, these funtions are defined as "inline
- * extern".
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/* ------------------------------------------------------
- Doxygen group definitions
- ------------------------------------------------------ */
-/**
- * @defgroup IxQMgrAPI IXP400 Queue Manager (IxQMgr) API
- *
- * @brief The public API for the IXP400 QMgr component.
- *
- * IxQMgr is a low level interface to the AHB Queue Manager
- *
- * @{
- */
-
-#ifndef IXQMGR_H
-#define IXQMGR_H
-
-/*
- * User defined include files
- */
-
-#include "IxOsal.h"
-
-/*
- * Define QMgr's IoMem macros, in DC mode if in LE
- * regular if in BE. (Note: For Linux LSP gold release
- * may need to adjust mode.
- */
-#if defined (__BIG_ENDIAN)
-
-#define IX_QMGR_INLINE_READ_LONG IX_OSAL_READ_LONG_BE
-#define IX_QMGR_INLINE_WRITE_LONG IX_OSAL_WRITE_LONG_BE
-
-#else
-
-#define IX_QMGR_INLINE_READ_LONG IX_OSAL_READ_LONG_LE_DC
-#define IX_QMGR_INLINE_WRITE_LONG IX_OSAL_WRITE_LONG_LE_DC
-
-#endif
-
-/*
- * #defines and macros
- */
-
-/**
-*
-* @ingroup IxQMgrAPI
-*
-* @def IX_QMGR_INLINE
-*
-* @brief Inline definition, for inlining of Queue Access functions on API
-*
-* Please read the header information in this file for more details on the
-* use of function inlining in this component.
-*
-*/
-
-#ifndef __wince
-
-#ifdef IXQMGRQACCESS_C
-/* If IXQMGRQACCESS_C is set then the IxQmgrQAccess.c is including this file
- and must instantiate a concrete definition for each inlineable API function
- whether or not that function actually gets inlined. */
-# ifdef NO_INLINE_APIS
-# undef NO_INLINE_APIS
-# endif
-# define IX_QMGR_INLINE /* Empty Define */
-#else
-# ifndef NO_INLINE_APIS
-# define IX_QMGR_INLINE IX_OSAL_INLINE_EXTERN
-# else
-# define IX_QMGR_INLINE /* Empty Define */
-# endif
-#endif
-
-#else /* ndef __wince */
-
-# ifndef NO_INLINE_APIS
-# define NO_INLINE_APIS
-# endif
-# define IX_QMGR_INLINE
-
-#endif
-
-
-/**
-*
-* @ingroup IxQMgrAPI
-*
-* @def IX_QMGR_MAX_NUM_QUEUES
-*
-* @brief Number of queues supported by the AQM.
-*
-* This constant is used to indicate the number of AQM queues
-*
-*/
-#define IX_QMGR_MAX_NUM_QUEUES 64
-
-/**
-*
-* @ingroup IxQMgrAPI
-*
-* @def IX_QMGR_MIN_QID
-*
-* @brief Minimum queue identifier.
-*
-* This constant is used to indicate the smallest queue identifier
-*
-*/
-#define IX_QMGR_MIN_QID IX_QMGR_QUEUE_0
-
-/**
-*
-* @ingroup IxQMgrAPI
-*
-* @def IX_QMGR_MAX_QID
-*
-* @brief Maximum queue identifier.
-*
-* This constant is used to indicate the largest queue identifier
-*
-*/
-#define IX_QMGR_MAX_QID IX_QMGR_QUEUE_63
-
-/**
-*
-* @ingroup IxQMgrAPI
-*
-* @def IX_QMGR_MIN_QUEUPP_QID
-*
-* @brief Minimum queue identifier for reduced functionality queues.
-*
-* This constant is used to indicate Minimum queue identifier for reduced
-* functionality queues
-*
-*/
-#define IX_QMGR_MIN_QUEUPP_QID 32
-
-/**
-*
-* @ingroup IxQMgrAPI
-*
-* @def IX_QMGR_MAX_QNAME_LEN
-*
-* @brief Maximum queue name length.
-*
-* This constant is used to indicate the maximum null terminated string length
-* (excluding '\0') for a queue name
-*
-*/
-#define IX_QMGR_MAX_QNAME_LEN 16
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_WARNING
- *
- * @brief Warning return code.
- *
- * Execution complete, but there is a special case to handle
- *
- */
-#define IX_QMGR_WARNING 2
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_PARAMETER_ERROR
- *
- * @brief Parameter error return code (NULL pointer etc..).
- *
- * parameter error out of range/invalid
- *
- */
-#define IX_QMGR_PARAMETER_ERROR 3
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_INVALID_Q_ENTRY_SIZE
- *
- * @brief Invalid entry size return code.
- *
- * Invalid queue entry size for a queue read/write
- *
- */
-#define IX_QMGR_INVALID_Q_ENTRY_SIZE 4
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_INVALID_Q_ID
- *
- * @brief Invalid queue identifier return code.
- *
- * Invalid queue id, not in range 0-63
- *
- */
-#define IX_QMGR_INVALID_Q_ID 5
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_INVALID_CB_ID
- *
- * @brief Invalid callback identifier return code.
- *
- * Invalid callback id
- */
-#define IX_QMGR_INVALID_CB_ID 6
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_CB_ALREADY_SET
- *
- * @brief Callback set error return code.
- *
- * The specified callback has already been for this queue
- *
- */
-#define IX_QMGR_CB_ALREADY_SET 7
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_NO_AVAILABLE_SRAM
- *
- * @brief Sram consumed return code.
- *
- * All AQM Sram is consumed by queue configuration
- *
- */
-#define IX_QMGR_NO_AVAILABLE_SRAM 8
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_INVALID_INT_SOURCE_ID
- *
- * @brief Invalid queue interrupt source identifier return code.
- *
- * Invalid queue interrupt source given for notification enable
- */
-#define IX_QMGR_INVALID_INT_SOURCE_ID 9
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_INVALID_QSIZE
- *
- * @brief Invalid queue size error code.
- *
- * Invalid queue size not one of 16,32, 64, 128
- *
- *
- */
-#define IX_QMGR_INVALID_QSIZE 10
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_INVALID_Q_WM
- *
- * @brief Invalid queue watermark return code.
- *
- * Invalid queue watermark given for watermark set
- */
-#define IX_QMGR_INVALID_Q_WM 11
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_Q_NOT_CONFIGURED
- *
- * @brief Queue not configured return code.
- *
- * Returned to the client when a function has been called on an unconfigured
- * queue
- *
- */
-#define IX_QMGR_Q_NOT_CONFIGURED 12
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_Q_ALREADY_CONFIGURED
- *
- * @brief Queue already configured return code.
- *
- * Returned to client to indicate that a queue has already been configured
- */
-#define IX_QMGR_Q_ALREADY_CONFIGURED 13
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_Q_UNDERFLOW
- *
- * @brief Underflow return code.
- *
- * Underflow on a queue read has occurred
- *
- */
-#define IX_QMGR_Q_UNDERFLOW 14
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_Q_OVERFLOW
- *
- * @brief Overflow return code.
- *
- * Overflow on a queue write has occurred
- *
- */
-#define IX_QMGR_Q_OVERFLOW 15
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_Q_INVALID_PRIORITY
- *
- * @brief Invalid priority return code.
- *
- * Invalid priority, not one of 0,1,2
- */
-#define IX_QMGR_Q_INVALID_PRIORITY 16
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_ENTRY_INDEX_OUT_OF_BOUNDS
- *
- * @brief Entry index out of bounds return code.
- *
- * Entry index is greater than number of entries in queue.
- */
-#define IX_QMGR_ENTRY_INDEX_OUT_OF_BOUNDS 17
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def ixQMgrDispatcherLoopRun
- *
- * @brief Map old function name ixQMgrDispatcherLoopRun ()
- * to @ref ixQMgrDispatcherLoopRunA0 ().
- *
- */
-#define ixQMgrDispatcherLoopRun ixQMgrDispatcherLoopRunA0
-
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_QUEUE
- *
- * @brief Definition of AQM queue numbers
- *
- */
-#define IX_QMGR_QUEUE_0 (0) /**< Queue Number 0 */
-#define IX_QMGR_QUEUE_1 (1) /**< Queue Number 1 */
-#define IX_QMGR_QUEUE_2 (2) /**< Queue Number 2 */
-#define IX_QMGR_QUEUE_3 (3) /**< Queue Number 3 */
-#define IX_QMGR_QUEUE_4 (4) /**< Queue Number 4 */
-#define IX_QMGR_QUEUE_5 (5) /**< Queue Number 5 */
-#define IX_QMGR_QUEUE_6 (6) /**< Queue Number 6 */
-#define IX_QMGR_QUEUE_7 (7) /**< Queue Number 7 */
-#define IX_QMGR_QUEUE_8 (8) /**< Queue Number 8 */
-#define IX_QMGR_QUEUE_9 (9) /**< Queue Number 9 */
-#define IX_QMGR_QUEUE_10 (10) /**< Queue Number 10 */
-#define IX_QMGR_QUEUE_11 (11) /**< Queue Number 11 */
-#define IX_QMGR_QUEUE_12 (12) /**< Queue Number 12 */
-#define IX_QMGR_QUEUE_13 (13) /**< Queue Number 13 */
-#define IX_QMGR_QUEUE_14 (14) /**< Queue Number 14 */
-#define IX_QMGR_QUEUE_15 (15) /**< Queue Number 15 */
-#define IX_QMGR_QUEUE_16 (16) /**< Queue Number 16 */
-#define IX_QMGR_QUEUE_17 (17) /**< Queue Number 17 */
-#define IX_QMGR_QUEUE_18 (18) /**< Queue Number 18 */
-#define IX_QMGR_QUEUE_19 (19) /**< Queue Number 19 */
-#define IX_QMGR_QUEUE_20 (20) /**< Queue Number 20 */
-#define IX_QMGR_QUEUE_21 (21) /**< Queue Number 21 */
-#define IX_QMGR_QUEUE_22 (22) /**< Queue Number 22 */
-#define IX_QMGR_QUEUE_23 (23) /**< Queue Number 23 */
-#define IX_QMGR_QUEUE_24 (24) /**< Queue Number 24 */
-#define IX_QMGR_QUEUE_25 (25) /**< Queue Number 25 */
-#define IX_QMGR_QUEUE_26 (26) /**< Queue Number 26 */
-#define IX_QMGR_QUEUE_27 (27) /**< Queue Number 27 */
-#define IX_QMGR_QUEUE_28 (28) /**< Queue Number 28 */
-#define IX_QMGR_QUEUE_29 (29) /**< Queue Number 29 */
-#define IX_QMGR_QUEUE_30 (30) /**< Queue Number 30 */
-#define IX_QMGR_QUEUE_31 (31) /**< Queue Number 31 */
-#define IX_QMGR_QUEUE_32 (32) /**< Queue Number 32 */
-#define IX_QMGR_QUEUE_33 (33) /**< Queue Number 33 */
-#define IX_QMGR_QUEUE_34 (34) /**< Queue Number 34 */
-#define IX_QMGR_QUEUE_35 (35) /**< Queue Number 35 */
-#define IX_QMGR_QUEUE_36 (36) /**< Queue Number 36 */
-#define IX_QMGR_QUEUE_37 (37) /**< Queue Number 37 */
-#define IX_QMGR_QUEUE_38 (38) /**< Queue Number 38 */
-#define IX_QMGR_QUEUE_39 (39) /**< Queue Number 39 */
-#define IX_QMGR_QUEUE_40 (40) /**< Queue Number 40 */
-#define IX_QMGR_QUEUE_41 (41) /**< Queue Number 41 */
-#define IX_QMGR_QUEUE_42 (42) /**< Queue Number 42 */
-#define IX_QMGR_QUEUE_43 (43) /**< Queue Number 43 */
-#define IX_QMGR_QUEUE_44 (44) /**< Queue Number 44 */
-#define IX_QMGR_QUEUE_45 (45) /**< Queue Number 45 */
-#define IX_QMGR_QUEUE_46 (46) /**< Queue Number 46 */
-#define IX_QMGR_QUEUE_47 (47) /**< Queue Number 47 */
-#define IX_QMGR_QUEUE_48 (48) /**< Queue Number 48 */
-#define IX_QMGR_QUEUE_49 (49) /**< Queue Number 49 */
-#define IX_QMGR_QUEUE_50 (50) /**< Queue Number 50 */
-#define IX_QMGR_QUEUE_51 (51) /**< Queue Number 51 */
-#define IX_QMGR_QUEUE_52 (52) /**< Queue Number 52 */
-#define IX_QMGR_QUEUE_53 (53) /**< Queue Number 53 */
-#define IX_QMGR_QUEUE_54 (54) /**< Queue Number 54 */
-#define IX_QMGR_QUEUE_55 (55) /**< Queue Number 55 */
-#define IX_QMGR_QUEUE_56 (56) /**< Queue Number 56 */
-#define IX_QMGR_QUEUE_57 (57) /**< Queue Number 57 */
-#define IX_QMGR_QUEUE_58 (58) /**< Queue Number 58 */
-#define IX_QMGR_QUEUE_59 (59) /**< Queue Number 59 */
-#define IX_QMGR_QUEUE_60 (60) /**< Queue Number 60 */
-#define IX_QMGR_QUEUE_61 (61) /**< Queue Number 61 */
-#define IX_QMGR_QUEUE_62 (62) /**< Queue Number 62 */
-#define IX_QMGR_QUEUE_63 (63) /**< Queue Number 63 */
-#define IX_QMGR_QUEUE_INVALID (64) /**< AQM Queue Number Delimiter */
-
-
-/*
- * Typedefs
- */
-
-/**
- * @typedef IxQMgrQId
- *
- * @ingroup IxQMgrAPI
- *
- * @brief Used in the API to identify the AQM queues.
- *
- */
-typedef int IxQMgrQId;
-
-/**
- * @typedef IxQMgrQStatus
- *
- * @ingroup IxQMgrAPI
- *
- * @brief Queue status.
- *
- * A queues status is defined by its relative fullness or relative emptiness.
- * Each of the queues 0-31 have Nearly Empty, Nearly Full, Empty, Full,
- * Underflow and Overflow status flags. Queues 32-63 have just Nearly Empty and
- * Full status flags.
- * The flags bit positions are outlined below:
- *
- * OF - bit-5<br>
- * UF - bit-4<br>
- * F - bit-3<br>
- * NF - bit-2<br>
- * NE - bit-1<br>
- * E - bit-0<br>
- *
- */
-typedef UINT32 IxQMgrQStatus;
-
-/**
- * @enum IxQMgrQStatusMask
- *
- * @ingroup IxQMgrAPI
- *
- * @brief Queue status mask.
- *
- * Masks for extracting the individual status flags from the IxQMgrStatus
- * word.
- *
- */
-typedef enum
-{
- IX_QMGR_Q_STATUS_E_BIT_MASK = 0x1,
- IX_QMGR_Q_STATUS_NE_BIT_MASK = 0x2,
- IX_QMGR_Q_STATUS_NF_BIT_MASK = 0x4,
- IX_QMGR_Q_STATUS_F_BIT_MASK = 0x8,
- IX_QMGR_Q_STATUS_UF_BIT_MASK = 0x10,
- IX_QMGR_Q_STATUS_OF_BIT_MASK = 0x20
-} IxQMgrQStatusMask;
-
-/**
- * @enum IxQMgrSourceId
- *
- * @ingroup IxQMgrAPI
- *
- * @brief Queue interrupt source select.
- *
- * This enum defines the different source conditions on a queue that result in
- * an interrupt being fired by the AQM. Interrupt source is configurable for
- * queues 0-31 only. The interrupt source for queues 32-63 is hardwired to the
- * NE(Nearly Empty) status flag.
- *
- */
-typedef enum
-{
- IX_QMGR_Q_SOURCE_ID_E = 0, /**< Queue Empty due to last read */
- IX_QMGR_Q_SOURCE_ID_NE, /**< Queue Nearly Empty due to last read */
- IX_QMGR_Q_SOURCE_ID_NF, /**< Queue Nearly Full due to last write */
- IX_QMGR_Q_SOURCE_ID_F, /**< Queue Full due to last write */
- IX_QMGR_Q_SOURCE_ID_NOT_E, /**< Queue Not Empty due to last write */
- IX_QMGR_Q_SOURCE_ID_NOT_NE, /**< Queue Not Nearly Empty due to last write */
- IX_QMGR_Q_SOURCE_ID_NOT_NF, /**< Queue Not Nearly Full due to last read */
- IX_QMGR_Q_SOURCE_ID_NOT_F /**< Queue Not Full due to last read */
-} IxQMgrSourceId;
-
-/**
- * @enum IxQMgrQEntrySizeInWords
- *
- * @ingroup IxQMgrAPI
- *
- * @brief QMgr queue entry sizes.
- *
- * The entry size of a queue specifies the size of a queues entry in words.
- *
- */
-typedef enum
-{
- IX_QMGR_Q_ENTRY_SIZE1 = 1, /**< 1 word entry */
- IX_QMGR_Q_ENTRY_SIZE2 = 2, /**< 2 word entry */
- IX_QMGR_Q_ENTRY_SIZE4 = 4 /**< 4 word entry */
-} IxQMgrQEntrySizeInWords;
-
-/**
- * @enum IxQMgrQSizeInWords
- *
- * @ingroup IxQMgrAPI
- *
- * @brief QMgr queue sizes.
- *
- * These values define the allowed queue sizes for AQM queue. The sizes are
- * specified in words.
- *
- */
-typedef enum
-{
- IX_QMGR_Q_SIZE16 = 16, /**< 16 word buffer */
- IX_QMGR_Q_SIZE32 = 32, /**< 32 word buffer */
- IX_QMGR_Q_SIZE64 = 64, /**< 64 word buffer */
- IX_QMGR_Q_SIZE128 = 128, /**< 128 word buffer */
- IX_QMGR_Q_SIZE_INVALID = 129 /**< Insure that this is greater than largest
- * queue size supported by the hardware
- */
-} IxQMgrQSizeInWords;
-
-/**
- * @enum IxQMgrWMLevel
- *
- * @ingroup IxQMgrAPI
- *
- * @brief QMgr watermark levels.
- *
- * These values define the valid watermark levels(in ENTRIES) for queues. Each
- * queue 0-63 have configurable Nearly full and Nearly empty watermarks. For
- * queues 32-63 the Nearly full watermark has NO EFFECT.
- * If the Nearly full watermark is set to IX_QMGR_Q_WM_LEVEL16 this means that
- * the nearly full flag will be set by the hardware when there are >= 16 empty
- * entries in the specified queue.
- * If the Nearly empty watermark is set to IX_QMGR_Q_WM_LEVEL16 this means that
- * the Nearly empty flag will be set by the hardware when there are <= 16 full
- * entries in the specified queue.
- */
-typedef enum
-{
- IX_QMGR_Q_WM_LEVEL0 = 0, /**< 0 entry watermark */
- IX_QMGR_Q_WM_LEVEL1 = 1, /**< 1 entry watermark */
- IX_QMGR_Q_WM_LEVEL2 = 2, /**< 2 entry watermark */
- IX_QMGR_Q_WM_LEVEL4 = 4, /**< 4 entry watermark */
- IX_QMGR_Q_WM_LEVEL8 = 8, /**< 8 entry watermark */
- IX_QMGR_Q_WM_LEVEL16 = 16, /**< 16 entry watermark */
- IX_QMGR_Q_WM_LEVEL32 = 32, /**< 32 entry watermark */
- IX_QMGR_Q_WM_LEVEL64 = 64 /**< 64 entry watermark */
-} IxQMgrWMLevel;
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @enum IxQMgrDispatchGroup
- *
- * @brief QMgr dispatch group select identifiers.
- *
- * This enum defines the groups over which the dispatcher will process when
- * called. One of the enum values must be used as a input to
- * @a ixQMgrDispatcherLoopRunA0, @a ixQMgrDispatcherLoopRunB0
- * or @a ixQMgrDispatcherLoopRunB0LLP.
- *
- */
-typedef enum
-{
- IX_QMGR_QUELOW_GROUP = 0, /**< Queues 0-31 */
- IX_QMGR_QUEUPP_GROUP /**< Queues 32-63 */
-} IxQMgrDispatchGroup;
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @enum IxQMgrPriority
- *
- * @brief Dispatcher priority levels.
- *
- * This enum defines the different queue dispatch priority levels.
- * The lowest priority number (0) is the highest priority level.
- *
- */
-typedef enum
-{
- IX_QMGR_Q_PRIORITY_0 = 0, /**< Priority level 0 */
- IX_QMGR_Q_PRIORITY_1, /**< Priority level 1 */
- IX_QMGR_Q_PRIORITY_2, /**< Priority level 2 */
- IX_QMGR_Q_PRIORITY_INVALID /**< Invalid Priority level */
-} IxQMgrPriority;
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @enum IxQMgrType
- *
- * @brief Callback types as used with livelock prevention
- *
- * This enum defines the different callback types.
- * These types are only used when Livelock prevention is enabled.
- * The default is IX_QMGR_TYPE_REALTIME_OTHER.
- *
- */
-
-typedef enum
-{
- IX_QMGR_TYPE_REALTIME_OTHER = 0, /**< Real time callbacks-always allowed run*/
- IX_QMGR_TYPE_REALTIME_PERIODIC, /**< Periodic callbacks-always allowed run */
- IX_QMGR_TYPE_REALTIME_SPORADIC /**< Sporadic callbacks-only run if no
- periodic callbacks are in progress */
-} IxQMgrType;
-
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @typedef IxQMgrCallbackId
- *
- * @brief Uniquely identifies a callback function.
- *
- * A unique callback identifier associated with each callback
- * registered by clients.
- *
- */
-typedef unsigned IxQMgrCallbackId;
-
-/**
- * @typedef IxQMgrCallback
- *
- * @brief QMgr notification callback type.
- *
- * This defines the interface to all client callback functions.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier
- * @param cbId @ref IxQMgrCallbackId [in] - the callback identifier
- */
-typedef void (*IxQMgrCallback)(IxQMgrQId qId,
- IxQMgrCallbackId cbId);
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @typedef IxQMgrDispatcherFuncPtr
- *
- * @brief QMgr Dispatcher Loop function pointer.
- *
- * This defines the interface for QMgr Dispather functions.
- *
- * @param group @ref IxQMgrDispatchGroup [in] - the group of the
- * queue of which the dispatcher will run
- */
-typedef void (*IxQMgrDispatcherFuncPtr)(IxQMgrDispatchGroup group);
-
-/*
- * Function Prototypes
- */
-
-/* ------------------------------------------------------------
- Initialisation related functions
- ---------------------------------------------------------- */
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrInit (void)
- *
- * @brief Initialise the QMgr.
- *
- * This function must be called before and other QMgr function. It
- * sets up internal data structures.
- *
- * @return @li IX_SUCCESS, the IxQMgr successfully initialised
- * @return @li IX_FAIL, failed to initialize the Qmgr
- *
- */
-PUBLIC IX_STATUS
-ixQMgrInit (void);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrUnload (void)
- *
- * @brief Uninitialise the QMgr.
- *
- * This function will perform the tasks required to unload the QMgr component
- * cleanly. This includes unmapping kernel memory.
- * This should be called before a soft reboot or unloading of a kernel module.
- *
- * @pre It should only be called if @ref ixQMgrInit has already been called.
- *
- * @post No QMgr functions should be called until ixQMgrInit is called again.
- *
- * @return @li IX_SUCCESS, the IxQMgr successfully uninitialised
- * @return @li IX_FAIL, failed to uninitialize the Qmgr
- *
- */
-PUBLIC IX_STATUS
-ixQMgrUnload (void);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrShow (void)
- *
- * @brief Describe queue configuration and statistics for active queues.
- *
- * This function shows active queues, their configurations and statistics.
- *
- * @return @li void
- *
- */
-PUBLIC void
-ixQMgrShow (void);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrQShow (IxQMgrQId qId)
- *
- * @brief Display aqueue configuration and statistics for a queue.
- *
- * This function shows queue configuration and statistics for a queue.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier.
- *
- * @return @li IX_SUCCESS, success
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, queue not configured for this QId
- *
- */
-PUBLIC IX_STATUS
-ixQMgrQShow (IxQMgrQId qId);
-
-
-/* ------------------------------------------------------------
- Configuration related functions
- ---------------------------------------------------------- */
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrQConfig (char *qName,
- IxQMgrQId qId,
- IxQMgrQSizeInWords qSizeInWords,
- IxQMgrQEntrySizeInWords qEntrySizeInWords)
- *
- * @brief Configure an AQM queue.
- *
- * This function is called by a client to setup a queue. The size and entrySize
- * qId and qName(NULL pointer) are checked for valid values. This function must
- * be called for each queue, before any queue accesses are made and after
- * ixQMgrInit() has been called. qName is assumed to be a '\0' terminated array
- * of 16 charachters or less.
- *
- * @param *qName char [in] - is the name provided by the client and is associated
- * with a QId by the QMgr.
- * @param qId @ref IxQMgrQId [in] - the qId of this queue
- * @param qSizeInWords @ref IxQMgrQSize [in] - the size of the queue can be one of 16,32
- * 64, 128 words.
- * @param qEntrySizeInWords @ref IxQMgrQEntrySizeInWords [in] - the size of a queue entry
- * can be one of 1,2,4 words.
- *
- * @return @li IX_SUCCESS, a specified queue has been successfully configured.
- * @return @li IX_FAIL, IxQMgr has not been initialised.
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid parameter(s).
- * @return @li IX_QMGR_INVALID_QSIZE, invalid queue size
- * @return @li IX_QMGR_INVALID_Q_ID, invalid queue id
- * @return @li IX_QMGR_INVALID_Q_ENTRY_SIZE, invalid queue entry size
- * @return @li IX_QMGR_Q_ALREADY_CONFIGURED, queue already configured
- *
- */
-PUBLIC IX_STATUS
-ixQMgrQConfig (char *qName,
- IxQMgrQId qId,
- IxQMgrQSizeInWords qSizeInWords,
- IxQMgrQEntrySizeInWords qEntrySizeInWords);
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrQSizeInEntriesGet (IxQMgrQId qId,
- unsigned *qSizeInEntries)
- *
- * @brief Return the size of a queue in entries.
- *
- * This function returns the the size of the queue in entriese.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier
- * @param *qSizeInEntries @ref IxQMgrQSize [out] - queue size in entries
- *
- * @return @li IX_SUCCESS, successfully retrieved the number of full entrie
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, queue not configured for this QId
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid parameter(s).
- *
- */
-PUBLIC IX_STATUS
-ixQMgrQSizeInEntriesGet (IxQMgrQId qId,
- unsigned *qSizeInEntries);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrWatermarkSet (IxQMgrQId qId,
- IxQMgrWMLevel ne,
- IxQMgrWMLevel nf)
- *
- * @brief Set the Nearly Empty and Nearly Full Watermarks fo a queue.
- *
- * This function is called by a client to set the watermarks NE and NF for the
- * queue specified by qId.
- * The queue must be empty at the time this function is called, it is the clients
- * responsibility to ensure that the queue is empty.
- * This function will read the status of the queue before the watermarks are set
- * and again after the watermarks are set. If the status register has changed,
- * due to a queue access by an NPE for example, a warning is returned.
- * Queues 32-63 only support the NE flag, therefore the value of nf will be ignored
- * for these queues.
- *
- * @param qId @ref IxQMgrQId [in] - the QId of the queue.
- * @param ne @ref IxQMgrWMLevel [in] - the NE(Nearly Empty) watermark for this
- * queue. Valid values are 0,1,2,4,8,16,32 and
- * 64 entries.
- * @param nf @ref IxQMgrWMLevel [in] - the NF(Nearly Full) watermark for this queue.
- * Valid values are 0,1,2,4,8,16,32 and 64
- * entries.
- *
- * @return @li IX_SUCCESS, watermarks have been set for the queu
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, queue not configured for this QId
- * @return @li IX_QMGR_INVALID_Q_WM, invalid watermark
- * @return @li IX_QMGR_WARNING, the status register may not be constistent
- *
- */
-PUBLIC IX_STATUS
-ixQMgrWatermarkSet (IxQMgrQId qId,
- IxQMgrWMLevel ne,
- IxQMgrWMLevel nf);
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrAvailableSramAddressGet (UINT32 *address,
- unsigned *sizeOfFreeSram)
- *
- * @brief Return the address of available AQM SRAM.
- *
- * This function returns the starting address in AQM SRAM not used by the
- * current queue configuration and should only be called after all queues
- * have been configured.
- * Calling this function before all queues have been configured will will return
- * the currently available SRAM. A call to configure another queue will use some
- * of the available SRAM.
- * The amount of SRAM available is specified in sizeOfFreeSram. The address is the
- * address of the bottom of available SRAM. Available SRAM extends from address
- * from address to address + sizeOfFreeSram.
- *
- * @param **address UINT32 [out] - the address of the available SRAM, NULL if
- * none available.
- * @param *sizeOfFreeSram unsigned [out]- the size in words of available SRAM
- *
- * @return @li IX_SUCCESS, there is available SRAM and is pointed to by address
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid parameter(s)
- * @return @li IX_QMGR_NO_AVAILABLE_SRAM, all AQM SRAM is consumed by the queue
- * configuration.
- *
- */
-PUBLIC IX_STATUS
-ixQMgrAvailableSramAddressGet (UINT32 *address,
- unsigned *sizeOfFreeSram);
-
-
-/* ------------------------------------------------------------
- Queue access related functions
- ---------------------------------------------------------- */
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrQReadWithChecks (IxQMgrQId qId,
- UINT32 *entry)
- *
- * @brief Read an entry from a queue.
- *
- * This function reads an entire entry from a queue returning it in entry. The
- * queue configuration word is read to determine what entry size this queue is
- * configured for and then the number of words specified by the entry size is
- * read. entry must be a pointer to a previously allocated array of sufficient
- * size to hold an entry.
- *
- * @note - IX_QMGR_Q_UNDERFLOW is only returned for queues 0-31 as queues 32-63
- * do not have an underflow status maintained.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier.
- * @param *entry UINT32 [out] - pointer to the entry word(s).
- *
- * @return @li IX_SUCCESS, entry was successfully read.
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid paramter(s).
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, queue not configured for this QId
- * @return @li IX_QMGR_Q_UNDERFLOW, attempt to read from an empty queue
- *
- */
-PUBLIC IX_STATUS
-ixQMgrQReadWithChecks (IxQMgrQId qId,
- UINT32 *entry);
-
-
-
-/**
- * @brief Internal structure to facilitate inlining functions in IxQMgr.h
- */
-typedef struct
-{
- /* fields related to write functions */
- UINT32 qOflowStatBitMask; /**< overflow status mask */
- UINT32 qWriteCount; /**< queue write count */
-
- /* fields related to read and write functions */
- volatile UINT32 *qAccRegAddr; /**< access register */
- volatile UINT32 *qUOStatRegAddr; /**< status register */
- volatile UINT32 *qConfigRegAddr; /**< config register */
- UINT32 qEntrySizeInWords; /**< queue entry size in words */
- UINT32 qSizeInEntries; /**< queue size in entries */
-
- /* fields related to read functions */
- UINT32 qUflowStatBitMask; /**< underflow status mask */
- UINT32 qReadCount; /**< queue read count */
-} IxQMgrQInlinedReadWriteInfo;
-
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrQReadMWordsMinus1 (IxQMgrQId qId,
- UINT32 *entry)
- *
- * @brief This function reads the remaining of the q entry
- * for queues configured with many words.
- * (the first word of the entry is already read
- * in the inlined function and the entry pointer already
- * incremented
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier.
- * @param *entry UINT32 [out] - pointer to the entry word(s).
- *
- * @return @li IX_SUCCESS, entry was successfully read.
- * @return @li IX_QMGR_Q_UNDERFLOW, attempt to read from an empty queue
- *
- */
-PUBLIC IX_STATUS
-ixQMgrQReadMWordsMinus1 (IxQMgrQId qId,
- UINT32 *entry);
-
-
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrQRead (IxQMgrQId qId,
- UINT32 *entry)
- *
- * @brief Fast read of an entry from a queue.
- *
- * This function is a heavily streamlined version of ixQMgrQReadWithChecks(),
- * but performs essentially the same task. It reads an entire entry from a
- * queue, returning it in entry which must be a pointer to a previously
- * allocated array of sufficient size to hold an entry.
- *
- * @note - This function is inlined, to reduce unnecessary function call
- * overhead. It does not perform any parameter checks, or update any statistics.
- * Also, it does not check that the queue specified by qId has been configured.
- * or is in range. It simply reads an entry from the queue, and checks for
- * underflow.
- *
- * @note - IX_QMGR_Q_UNDERFLOW is only returned for queues 0-31 as queues 32-63
- * do not have an underflow status maintained.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier.
- * @param *entry UINT32 [out] - pointer to the entry word(s).
- *
- * @return @li IX_SUCCESS, entry was successfully read.
- * @return @li IX_QMGR_Q_UNDERFLOW, attempt to read from an empty queue
- *
- */
-#ifdef NO_INLINE_APIS
-PUBLIC IX_STATUS
-ixQMgrQRead (IxQMgrQId qId,
- UINT32 *entryPtr);
-#else
-extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[];
-extern IX_STATUS ixQMgrQReadMWordsMinus1 (IxQMgrQId qId, UINT32 *entryPtr);
-
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQRead (IxQMgrQId qId,
- UINT32 *entryPtr);
-#endif
-
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQRead (IxQMgrQId qId,
- UINT32 *entryPtr)
-#ifdef NO_INLINE_APIS
- ;
-#else
-{
- IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
- UINT32 entry, entrySize;
-
- /* get a new entry */
- entrySize = infoPtr->qEntrySizeInWords;
- entry = IX_QMGR_INLINE_READ_LONG(infoPtr->qAccRegAddr);
-
- if (entrySize != IX_QMGR_Q_ENTRY_SIZE1)
- {
- *entryPtr = entry;
- /* process the remaining part of the entry */
- return ixQMgrQReadMWordsMinus1(qId, entryPtr);
- }
-
- /* underflow is available for lower queues only */
- if (qId < IX_QMGR_MIN_QUEUPP_QID)
- {
- /* the counter of queue entries is decremented. In happy
- * day scenario there are many entries in the queue
- * and the counter does not reach zero.
- */
- if (infoPtr->qReadCount-- == 0)
- {
- /* There is maybe no entry in the queue
- * qReadCount is now negative, but will be corrected before
- * the function returns.
- */
- UINT32 qPtrs; /* queue internal pointers */
-
- /* when a queue is empty, the hw guarantees to return
- * a null value. If the value is not null, the queue is
- * not empty.
- */
- if (entry == 0)
- {
- /* get the queue status */
- UINT32 status = IX_QMGR_INLINE_READ_LONG(infoPtr->qUOStatRegAddr);
-
- /* check the underflow status */
- if (status & infoPtr->qUflowStatBitMask)
- {
- /* the queue is empty
- * clear the underflow status bit if it was set
- */
- IX_QMGR_INLINE_WRITE_LONG(infoPtr->qUOStatRegAddr,
- status & ~infoPtr->qUflowStatBitMask);
- *entryPtr = 0;
- infoPtr->qReadCount = 0;
- return IX_QMGR_Q_UNDERFLOW;
- }
- }
- /* store the result */
- *entryPtr = entry;
-
- /* No underflow occured : someone is filling the queue
- * or the queue contains null entries.
- * The current counter needs to be
- * updated from the current number of entries in the queue
- */
-
- /* get snapshot of queue pointers */
- qPtrs = IX_QMGR_INLINE_READ_LONG(infoPtr->qConfigRegAddr);
-
- /* Mod subtraction of pointers to get number of words in Q. */
- qPtrs = (qPtrs - (qPtrs >> 7)) & 0x7f;
-
- if (qPtrs == 0)
- {
- /* no entry in the queue */
- infoPtr->qReadCount = 0;
- }
- else
- {
- /* convert the number of words inside the queue
- * to a number of entries
- */
- infoPtr->qReadCount = qPtrs & (infoPtr->qSizeInEntries - 1);
- }
- return IX_SUCCESS;
- }
- }
- *entryPtr = entry;
- return IX_SUCCESS;
-}
-#endif
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrQBurstRead (IxQMgrQId qId,
- UINT32 numEntries,
- UINT32 *entries)
- *
- * @brief Read a number of entries from an AQM queue.
- *
- * This function will burst read a number of entries from the specified queue.
- * The entry size of queue is auto-detected. The function will attempt to
- * read as many entries as specified by the numEntries parameter and will
- * return an UNDERFLOW if any one of the individual entry reads fail.
- *
- * @warning
- * IX_QMGR_Q_UNDERFLOW is only returned for queues 0-31 as queues 32-63
- * do not have an underflow status maintained, hence there is a potential for
- * silent failure here. This function must be used with caution.
- *
- * @note
- * This function is intended for fast draining of queues, so to make it
- * as efficient as possible, it has the following features:
- * - This function is inlined, to reduce unnecessary function call overhead.
- * - It does not perform any parameter checks, or update any statistics.
- * - It does not check that the queue specified by qId has been configured.
- * - It does not check that the queue has the number of full entries that
- * have been specified to be read. It will read until it finds a NULL entry or
- * until the number of specified entries have been read. It always checks for
- * underflow after all the reads have been performed.
- * Therefore, the client should ensure before calling this function that there
- * are enough entries in the queue to read. ixQMgrQNumEntriesGet() will
- * provide the number of full entries in a queue.
- * ixQMgrQRead() or ixQMgrQReadWithChecks(), which only reads
- * a single queue entry per call, should be used instead if the user requires
- * checks for UNDERFLOW after each entry read.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier.
- * @param numEntries unsigned [in] - the number of entries to read.
- * This number should be greater than 0
- * @param *entries UINT32 [out] - the word(s) read.
- *
- * @return @li IX_SUCCESS, entries were successfully read.
- * @return @li IX_QMGR_Q_UNDERFLOW, attempt to read from an empty queue
- *
- */
-#ifdef NO_INLINE_APIS
-PUBLIC IX_STATUS
-ixQMgrQBurstRead (IxQMgrQId qId,
- UINT32 numEntries,
- UINT32 *entries);
-#else
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQBurstRead (IxQMgrQId qId,
- UINT32 numEntries,
- UINT32 *entries);
-#endif /* endif NO_INLINE_APIS */
-
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQBurstRead (IxQMgrQId qId,
- UINT32 numEntries,
- UINT32 *entries)
-#ifdef NO_INLINE_APIS
-;
-#else
-{
- IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
- UINT32 nullCheckEntry;
-
- if (infoPtr->qEntrySizeInWords == IX_QMGR_Q_ENTRY_SIZE1)
- {
- volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr;
-
- /* the code is optimized to take care of data dependencies:
- * Durig a read, there are a few cycles needed to get the
- * read complete. During these cycles, it is poossible to
- * do some CPU, e.g. increment pointers and decrement
- * counters.
- */
-
- /* fetch a queue entry */
- nullCheckEntry = IX_QMGR_INLINE_READ_LONG(infoPtr->qAccRegAddr);
-
- /* iterate the specified number of queue entries */
- while (--numEntries)
- {
- /* check the result of the previous read */
- if (nullCheckEntry == 0)
- {
- /* if we read a NULL entry, stop. We have underflowed */
- break;
- }
- else
- {
- /* write the entry */
- *entries = nullCheckEntry;
- /* fetch next entry */
- nullCheckEntry = IX_QMGR_INLINE_READ_LONG(qAccRegAddr);
- /* increment the write address */
- entries++;
- }
- }
- /* write the pre-fetched entry */
- *entries = nullCheckEntry;
- }
- else
- {
- IxQMgrQEntrySizeInWords entrySizeInWords = infoPtr->qEntrySizeInWords;
- /* read the specified number of queue entries */
- nullCheckEntry = 0;
- while (numEntries--)
- {
- UINT32 i;
-
- for (i = 0; i < (UINT32)entrySizeInWords; i++)
- {
- *entries = IX_QMGR_INLINE_READ_LONG(infoPtr->qAccRegAddr + i);
- nullCheckEntry |= *entries++;
- }
-
- /* if we read a NULL entry, stop. We have underflowed */
- if (nullCheckEntry == 0)
- {
- break;
- }
- nullCheckEntry = 0;
- }
- }
-
- /* reset the current read count : next access to the read function
- * will force a underflow status check
- */
- infoPtr->qReadCount = 0;
-
- /* Check if underflow occurred on the read */
- if (nullCheckEntry == 0 && qId < IX_QMGR_MIN_QUEUPP_QID)
- {
- /* get the queue status */
- UINT32 status = IX_QMGR_INLINE_READ_LONG(infoPtr->qUOStatRegAddr);
-
- if (status & infoPtr->qUflowStatBitMask)
- {
- /* clear the underflow status bit if it was set */
- IX_QMGR_INLINE_WRITE_LONG(infoPtr->qUOStatRegAddr,
- status & ~infoPtr->qUflowStatBitMask);
- return IX_QMGR_Q_UNDERFLOW;
- }
- }
-
- return IX_SUCCESS;
-}
-#endif
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrQPeek (IxQMgrQId qId,
- unsigned int entryIndex,
- UINT32 *entry)
- *
- * @brief Read an entry from a queue without moving the read pointer.
- *
- * This function inspects an entry in a queue. The entry is inspected directly
- * in AQM SRAM and is not read from queue access registers. The entry is NOT removed
- * from the queue and the read/write pointers are unchanged.
- * N.B: The queue should not be accessed when this function is called.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier.
- * @param entryIndex unsigned int [in] - index of entry in queue in the range
- * [0].......[current number of entries in queue].
- * @param *entry UINT32 [out] - pointer to the entry word(s).
- *
- * @return @li IX_SUCCESS, entry was successfully inspected.
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid paramter(s).
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, queue not configured for this QId.
- * @return @li IX_QMGR_ENTRY_INDEX_OUT_OF_BOUNDS, an entry does not exist at
- * specified index.
- * @return @li IX_FAIL, failed to inpected the queue entry.
- */
-PUBLIC IX_STATUS
-ixQMgrQPeek (IxQMgrQId qId,
- unsigned int entryIndex,
- UINT32 *entry);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrQWriteWithChecks (IxQMgrQId qId,
- UINT32 *entry)
- *
- * @brief Write an entry to an AQM queue.
- *
- * This function will write the entry size number of words pointed to by entry to
- * the queue specified by qId. The queue configuration word is read to
- * determine the entry size of queue and the corresponding number of words is
- * then written to the queue.
- *
- * @note - IX_QMGR_Q_OVERFLOW is only returned for queues 0-31 as queues 32-63
- * do not have an overflow status maintained.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier.
- * @param *entry UINT32 [in] - the word(s) to write.
- *
- * @return @li IX_SUCCESS, value was successfully written.
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid paramter(s).
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, queue not configured for this QId
- * @return @li IX_QMGR_Q_OVERFLOW, attempt to write to a full queue
- *
- */
-PUBLIC IX_STATUS
-ixQMgrQWriteWithChecks (IxQMgrQId qId,
- UINT32 *entry);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrQWrite (IxQMgrQId qId,
- UINT32 *entry)
- *
- * @brief Fast write of an entry to a queue.
- *
- * This function is a heavily streamlined version of ixQMgrQWriteWithChecks(),
- * but performs essentially the same task. It will write the entry size number
- * of words pointed to by entry to the queue specified by qId.
- *
- * @note - This function is inlined, to reduce unnecessary function call
- * overhead. It does not perform any parameter checks, or update any
- * statistics. Also, it does not check that the queue specified by qId has
- * been configured. It simply writes an entry to the queue, and checks for
- * overflow.
- *
- * @note - IX_QMGR_Q_OVERFLOW is only returned for queues 0-31 as queues 32-63
- * do not have an overflow status maintained.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier.
- * @param *entry UINT32 [in] - pointer to the entry word(s).
- *
- * @return @li IX_SUCCESS, entry was successfully read.
- * @return @li IX_QMGR_Q_OVERFLOW, attempt to write to a full queue
- *
- */
-#ifdef NO_INLINE_APIS
-PUBLIC IX_STATUS
-ixQMgrQWrite (IxQMgrQId qId,
- UINT32 *entry);
-#else
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQWrite (IxQMgrQId qId,
- UINT32 *entry);
-#endif /* NO_INLINE_APIS */
-
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQWrite (IxQMgrQId qId,
- UINT32 *entry)
-#ifdef NO_INLINE_APIS
- ;
-#else
-{
- IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
- UINT32 entrySize;
-
- /* write the entry */
- IX_QMGR_INLINE_WRITE_LONG(infoPtr->qAccRegAddr, *entry);
- entrySize = infoPtr->qEntrySizeInWords;
-
- if (entrySize != IX_QMGR_Q_ENTRY_SIZE1)
- {
- /* process the remaining part of the entry */
- volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr;
- while (--entrySize)
- {
- ++entry;
- IX_QMGR_INLINE_WRITE_LONG(++qAccRegAddr, *entry);
- }
- entrySize = infoPtr->qEntrySizeInWords;
- }
-
- /* overflow is available for lower queues only */
- if (qId < IX_QMGR_MIN_QUEUPP_QID)
- {
- UINT32 qSize = infoPtr->qSizeInEntries;
- /* increment the current number of entries in the queue
- * and check for overflow
- */
- if (infoPtr->qWriteCount++ == qSize)
- {
- /* the queue may have overflow */
- UINT32 qPtrs; /* queue internal pointers */
-
- /* get the queue status */
- UINT32 status = IX_QMGR_INLINE_READ_LONG(infoPtr->qUOStatRegAddr);
-
- /* read the status twice because the status may
- * not be immediately ready after the write operation
- */
- if ((status & infoPtr->qOflowStatBitMask) ||
- ((status = IX_QMGR_INLINE_READ_LONG(infoPtr->qUOStatRegAddr))
- & infoPtr->qOflowStatBitMask))
- {
- /* the queue is full, clear the overflow status
- * bit if it was set
- */
- IX_QMGR_INLINE_WRITE_LONG(infoPtr->qUOStatRegAddr,
- status & ~infoPtr->qOflowStatBitMask);
- infoPtr->qWriteCount = infoPtr->qSizeInEntries;
- return IX_QMGR_Q_OVERFLOW;
- }
- /* No overflow occured : someone is draining the queue
- * and the current counter needs to be
- * updated from the current number of entries in the queue
- */
-
- /* get q pointer snapshot */
- qPtrs = IX_QMGR_INLINE_READ_LONG(infoPtr->qConfigRegAddr);
-
- /* Mod subtraction of pointers to get number of words in Q. */
- qPtrs = (qPtrs - (qPtrs >> 7)) & 0x7f;
-
- if (qPtrs == 0)
- {
- /* the queue may be full at the time of the
- * snapshot. Next access will check
- * the overflow status again.
- */
- infoPtr->qWriteCount = qSize;
- }
- else
- {
- /* convert the number of words to a number of entries */
- if (entrySize == IX_QMGR_Q_ENTRY_SIZE1)
- {
- infoPtr->qWriteCount = qPtrs & (qSize - 1);
- }
- else
- {
- infoPtr->qWriteCount = (qPtrs / entrySize) & (qSize - 1);
- }
- }
- }
- }
- return IX_SUCCESS;
-}
-#endif
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrQBurstWrite (IxQMgrQId qId,
- unsigned numEntries,
- UINT32 *entries)
- *
- * @brief Write a number of entries to an AQM queue.
- *
- * This function will burst write a number of entries to the specified queue.
- * The entry size of queue is auto-detected. The function will attempt to
- * write as many entries as specified by the numEntries parameter and will
- * return an OVERFLOW if any one of the individual entry writes fail.
- *
- * @warning
- * IX_QMGR_Q_OVERFLOW is only returned for queues 0-31 as queues 32-63
- * do not have an overflow status maintained, hence there is a potential for
- * silent failure here. This function must be used with caution.
- *
- * @note
- * This function is intended for fast population of queues, so to make it
- * as efficient as possible, it has the following features:
- * - This function is inlined, to reduce unnecessary function call overhead.
- * - It does not perform any parameter checks, or update any statistics.
- * - It does not check that the queue specified by qId has been configured.
- * - It does not check that the queue has enough free space to hold the entries
- * before writing, and only checks for overflow after all writes have been
- * performed. Therefore, the client should ensure before calling this function
- * that there is enough free space in the queue to hold the number of entries
- * to be written. ixQMgrQWrite() or ixQMgrQWriteWithChecks(), which only writes
- * a single queue entry per call, should be used instead if the user requires
- * checks for OVERFLOW after each entry written.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier.
- * @param numEntries unsigned [in] - the number of entries to write.
- * @param *entries UINT32 [in] - the word(s) to write.
- *
- * @return @li IX_SUCCESS, value was successfully written.
- * @return @li IX_QMGR_Q_OVERFLOW, attempt to write to a full queue
- *
- */
-#ifdef NO_INLINE_APIS
-PUBLIC IX_STATUS
-ixQMgrQBurstWrite (IxQMgrQId qId,
- unsigned numEntries,
- UINT32 *entries);
-#else
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQBurstWrite (IxQMgrQId qId,
- unsigned numEntries,
- UINT32 *entries);
-#endif /* NO_INLINE_APIS */
-
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQBurstWrite (IxQMgrQId qId,
- unsigned numEntries,
- UINT32 *entries)
-#ifdef NO_INLINE_APIS
-;
-#else
-{
- IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
- UINT32 status;
-
- /* update the current write count */
- infoPtr->qWriteCount += numEntries;
-
- if (infoPtr->qEntrySizeInWords == IX_QMGR_Q_ENTRY_SIZE1)
- {
- volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr;
- while (numEntries--)
- {
- IX_QMGR_INLINE_WRITE_LONG(qAccRegAddr, *entries);
- entries++;
- }
- }
- else
- {
- IxQMgrQEntrySizeInWords entrySizeInWords = infoPtr->qEntrySizeInWords;
- UINT32 i;
-
- /* write each queue entry */
- while (numEntries--)
- {
- /* write the queueEntrySize number of words for each entry */
- for (i = 0; i < (UINT32)entrySizeInWords; i++)
- {
- IX_QMGR_INLINE_WRITE_LONG((infoPtr->qAccRegAddr + i), *entries);
- entries++;
- }
- }
- }
-
- /* check if the write count overflows */
- if (infoPtr->qWriteCount > infoPtr->qSizeInEntries)
- {
- /* reset the current write count */
- infoPtr->qWriteCount = infoPtr->qSizeInEntries;
- }
-
- /* Check if overflow occurred on the write operation */
- if (qId < IX_QMGR_MIN_QUEUPP_QID)
- {
- /* get the queue status */
- status = IX_QMGR_INLINE_READ_LONG(infoPtr->qUOStatRegAddr);
-
- /* read the status twice because the status may
- * not be ready at the time of the write
- */
- if ((status & infoPtr->qOflowStatBitMask) ||
- ((status = IX_QMGR_INLINE_READ_LONG(infoPtr->qUOStatRegAddr))
- & infoPtr->qOflowStatBitMask))
- {
- /* clear the underflow status bit if it was set */
- IX_QMGR_INLINE_WRITE_LONG(infoPtr->qUOStatRegAddr,
- status & ~infoPtr->qOflowStatBitMask);
- return IX_QMGR_Q_OVERFLOW;
- }
- }
-
- return IX_SUCCESS;
-}
-#endif
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrQPoke (IxQMgrQId qId,
- unsigned int entryIndex,
- UINT32 *entry)
- *
- * @brief Write an entry to a queue without moving the write pointer.
- *
- * This function modifies an entry in a queue. The entry is modified directly
- * in AQM SRAM and not using the queue access registers. The entry is NOT added to the
- * queue and the read/write pointers are unchanged.
- * N.B: The queue should not be accessed when this function is called.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier.
- * @param entryIndex unsigned int [in] - index of entry in queue in the range
- * [0].......[current number of entries in queue].
- * @param *entry UINT32 [in] - pointer to the entry word(s).
- *
- * @return @li IX_SUCCESS, entry was successfully modified.
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid paramter(s).
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, queue not configured for this QId.
- * @return @li IX_QMGR_ENTRY_INDEX_OUT_OF_BOUNDS, an entry does not exist at
- * specified index.
- * @return @li IX_FAIL, failed to modify the queue entry.
- */
-PUBLIC IX_STATUS
-ixQMgrQPoke (IxQMgrQId qId,
- unsigned int entryIndex,
- UINT32 *entry);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrQNumEntriesGet (IxQMgrQId qId,
- unsigned *numEntries)
- *
- * @brief Get a snapshot of the number of entries in a queue.
- *
- * This function gets the number of entries in a queue.
- *
- * @param qId @ref IxQMgrQId [in] qId - the queue idenfifier
- * @param *numEntries unsigned [out] - the number of entries in a queue
- *
- * @return @li IX_SUCCESS, got the number of entries for the queue
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid paramter(s).
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, the specified qId has not been configured
- * @return @li IX_QMGR_WARNING, could not determine num entries at this time
- *
- */
-PUBLIC IX_STATUS
-ixQMgrQNumEntriesGet (IxQMgrQId qId,
- unsigned *numEntries);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrQStatusGetWithChecks (IxQMgrQId qId,
- IxQMgrQStatus *qStatus)
- *
- * @brief Get a queues status.
- *
- * This function reads the specified queues status. A queues status is defined
- * by its status flags. For queues 0-31 these flags are E,NE,NF,F. For
- * queues 32-63 these flags are NE and F.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier.
- * @param &qStatus @ref IxQMgrQStatus [out] - the status of the specified queue.
- *
- * @return @li IX_SUCCESS, queue status was successfully read.
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, the specified qId has not been configured
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid paramter.
- *
- */
-PUBLIC IX_STATUS
-ixQMgrQStatusGetWithChecks (IxQMgrQId qId,
- IxQMgrQStatus *qStatus);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrQStatusGet (IxQMgrQId qId,
- IxQMgrQStatus *qStatus)
- *
- * @brief Fast get of a queue's status.
- *
- * This function is a streamlined version of ixQMgrQStatusGetWithChecks(), but
- * performs essentially the same task. It reads the specified queue's status.
- * A queues status is defined by its status flags. For queues 0-31 these flags
- * are E,NE,NF,F. For queues 32-63 these flags are NE and F.
- *
- * @note - This function is inlined, to reduce unnecessary function call
- * overhead. It does not perform any parameter checks, or update any
- * statistics. Also, it does not check that the queue specified by qId has
- * been configured. It simply reads the specified queue's status.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier.
- * @param *qStatus @ref IxQMgrQStatus [out] - the status of the specified queue.
- *
- * @return @li void.
- *
- */
-
-#ifdef NO_INLINE_APIS
-PUBLIC IX_STATUS
-ixQMgrQStatusGet (IxQMgrQId qId,
- IxQMgrQStatus *qStatus);
-#else
-extern UINT32 ixQMgrAqmIfQueLowStatRegAddr[];
-extern UINT32 ixQMgrAqmIfQueLowStatBitsOffset[];
-extern UINT32 ixQMgrAqmIfQueLowStatBitsMask;
-extern UINT32 ixQMgrAqmIfQueUppStat0RegAddr;
-extern UINT32 ixQMgrAqmIfQueUppStat1RegAddr;
-extern UINT32 ixQMgrAqmIfQueUppStat0BitMask[];
-extern UINT32 ixQMgrAqmIfQueUppStat1BitMask[];
-
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQStatusGet (IxQMgrQId qId,
- IxQMgrQStatus *qStatus);
-#endif /* endif NO_INLINE_APIS */
-
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQStatusGet (IxQMgrQId qId,
- IxQMgrQStatus *qStatus)
-#ifdef NO_INLINE_APIS
- ;
-#else
-{
- /* read the status of a queue in the range 0-31 */
- if (qId < IX_QMGR_MIN_QUEUPP_QID)
- {
- volatile UINT32 *lowStatRegAddr = (UINT32*)ixQMgrAqmIfQueLowStatRegAddr[qId];
-
- UINT32 lowStatBitsOffset = ixQMgrAqmIfQueLowStatBitsOffset[qId];
- UINT32 lowStatBitsMask = ixQMgrAqmIfQueLowStatBitsMask;
-
- /* read the status register for this queue */
- *qStatus = IX_QMGR_INLINE_READ_LONG(lowStatRegAddr);
-
- /* mask out the status bits relevant only to this queue */
- *qStatus = (*qStatus >> lowStatBitsOffset) & lowStatBitsMask;
-
- }
- else /* read status of a queue in the range 32-63 */
- {
-
- volatile UINT32 *qNearEmptyStatRegAddr = (UINT32*)ixQMgrAqmIfQueUppStat0RegAddr;
- volatile UINT32 *qFullStatRegAddr = (UINT32*)ixQMgrAqmIfQueUppStat1RegAddr;
- int maskIndex = qId - IX_QMGR_MIN_QUEUPP_QID;
- UINT32 qNearEmptyStatBitMask = ixQMgrAqmIfQueUppStat0BitMask[maskIndex];
- UINT32 qFullStatBitMask = ixQMgrAqmIfQueUppStat1BitMask[maskIndex];
-
- /* Reset the status bits */
- *qStatus = 0;
-
- /* Check if the queue is nearly empty */
- if (IX_QMGR_INLINE_READ_LONG(qNearEmptyStatRegAddr) & qNearEmptyStatBitMask)
- {
- *qStatus |= IX_QMGR_Q_STATUS_NE_BIT_MASK;
- }
-
- /* Check if the queue is full */
- if (IX_QMGR_INLINE_READ_LONG(qFullStatRegAddr) & qFullStatBitMask)
- {
- *qStatus |= IX_QMGR_Q_STATUS_F_BIT_MASK;
- }
- }
- return IX_SUCCESS;
-}
-#endif
-
-/* ------------------------------------------------------------
- Queue dispatch related functions
- ---------------------------------------------------------- */
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrDispatcherPrioritySet (IxQMgrQId qId,
- IxQMgrPriority priority)
- *
- * @brief Set the dispatch priority of a queue.
- *
- * This function is called to set the dispatch priority of queue. The effect of
- * this function is to add a priority change request to a queue. This queue is
- * serviced by @a ixQMgrDispatcherLoopRunA0, @a ixQMgrDispatcherLoopRunB0 or
- * @a ixQMgrDispatcherLoopRunB0LLP.
- *
- * This function is re-entrant. and can be used from an interrupt context
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier
- * @param priority @ref IxQMgrPriority [in] - the new queue dispatch priority
- *
- * @return @li IX_SUCCESS, priority change request is queued
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, the specified qId has not been configured
- * @return @li IX_QMGR_Q_INVALID_PRIORITY, specified priority is invalid
- *
- */
-PUBLIC IX_STATUS
-ixQMgrDispatcherPrioritySet (IxQMgrQId qId,
- IxQMgrPriority priority);
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrNotificationEnable (IxQMgrQId qId,
- IxQMgrSourceId sourceId)
- *
- * @brief Enable notification on a queue for a specified queue source flag.
- *
- * This function is called by a client of the QMgr to enable notifications on a
- * specified condition.
- * If the condition for the notification is set after the client has called this
- * function but before the function has enabled the interrupt source, then the
- * notification will not occur.
- * For queues 32-63 the notification source is fixed to the NE(Nearly Empty) flag
- * and cannot be changed so the sourceId parameter is ignored for these queues.
- * The status register is read before the notofication is enabled and is read again
- * after the notification has been enabled, if they differ then the warning status
- * is returned.
- *
- * This function is re-entrant. and can be used from an interrupt context
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier
- * @param sourceId @ref IxQMgrSourceId [in] - the interrupt src condition identifier
- *
- * @return @li IX_SUCCESS, the interrupt has been enabled for the specified source
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, the specified qId has not been configured
- * @return @li IX_QMGR_INVALID_INT_SOURCE_ID, interrupt source invalid for this queue
- * @return @li IX_QMGR_WARNING, the status register may not be constistent
- *
- */
-PUBLIC IX_STATUS
-ixQMgrNotificationEnable (IxQMgrQId qId,
- IxQMgrSourceId sourceId);
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrNotificationDisable (IxQMgrQId qId)
- *
- * @brief Disable notifications on a queue.
- *
- * This function is called to disable notifications on a specified queue.
- *
- * This function is re-entrant. and can be used from an interrupt context
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier
- *
- * @return @li IX_SUCCESS, the interrupt has been disabled
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, the specified qId has not been configured
- *
- */
-PUBLIC IX_STATUS
-ixQMgrNotificationDisable (IxQMgrQId qId);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrDispatcherLoopRunA0 (IxQMgrDispatchGroup group)
- *
- * @brief Run the callback dispatcher.
- *
- * This function runs the dispatcher for a group of queues.
- * Callbacks are made for interrupts that have occurred on queues within
- * the group that have registered callbacks. The order in which queues are
- * serviced depends on the queue priorities set by the client.
- * This function may be called from interrupt or task context.
- * For optimisations that were introduced in IXP42X B0 and supported IXP46X
- * the @a ixQMgrDispatcherLoopRunB0, or @a ixQMgrDispatcherLoopRunB0LLP
- * should be used.
- *
- * This function is not re-entrant.
- *
- * @param group @ref IxQMgrDispatchGroup [in] - the group of queues over which the
- * dispatcher will run
- *
- * @return @li void
- *
- * @note This function may be called from interrupt or task context.
- * However, for optimal performance the choice of context depends also on the
- * operating system used.
- *
- */
-PUBLIC void
-ixQMgrDispatcherLoopRunA0 (IxQMgrDispatchGroup group);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrDispatcherLoopRunB0 (IxQMgrDispatchGroup group)
- *
- * @brief Run the callback dispatcher.
- *
- * The enhanced version of @a ixQMgrDispatcherLoopRunA0 that is optimised for
- * features introduced in IXP42X B0 silicon and supported on IXP46X.
- * This is the default dispatcher for IXP42X B0 and IXP46X silicon.
- * The function runs the dispatcher for a group of queues.
- * Callbacks are made for interrupts that have occurred on queues within
- * the group that have registered callbacks. The order in which queues are
- * serviced depends on the queue priorities set by the client.
- * This function may be called from interrupt or task context.
- *
- * This function is not re-entrant.
- *
- * @param group @ref IxQMgrDispatchGroup [in] - the group of queues over which the
- * dispatcher will run
- *
- * @return @li void
- *
- *
- * @note This function may be called from interrupt or task context.
- * However, for optimal performance the choice of context depends also on the
- * operating system used.
- *
- */
-PUBLIC void
-ixQMgrDispatcherLoopRunB0 (IxQMgrDispatchGroup group);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrDispatcherLoopRunB0LLP (IxQMgrDispatchGroup group)
- *
- * @brief Run the callback dispatcher.
- *
- * This is a version of the optimised dispatcher for IXP42X B0 and IXP46X,
- * @a ixQMgrDispatcherLoopRunB0, with added support for livelock prevention.
- * This dispatcher will only be used for the IXP42X B0 or IXP46X silicon if
- * feature control indicates that IX_FEATURECTRL_ORIGB0_DISPATCHER is set to
- * IX_FEATURE_CTRL_SWCONFIG_DISABLED. Otherwise the @a ixQMgrDispatcherLoopRunB0
- * dispatcher will be used (Default).
- *
- * When this dispatcher notifies for a queue that is type
- * IX_QMGR_TYPE_REALTIME_PERIODIC, notifications for queues that are set
- * as type IX_QMGR_REALTIME_SPORADIC are not processed and disabled.
- * This helps prevent any tasks resulting from the notification of the
- * IX_QMGR_TYPE_REALTIME_PERIODIC type queue to being subject to livelock.
- * The function runs the dispatcher for a group of queues.
- * Callbacks are made for interrupts that have occurred on queues within
- * the group that have registered callbacks. The order in which queues are
- * serviced depends on their type along with the queue priorities set by the
- * client. This function may be called from interrupt or task context.
- *
- * This function is not re-entrant.
- *
- * @param group @ref IxQMgrDispatchGroup [in] - the group of queues over which
- * the dispatcher will run
- *
- * @return @li void
- *
- * @note This function may be called from interrupt or task context.
- * However, for optimal performance the choice of context depends also on the
- * operating system used.
- *
- */
-PUBLIC void
-ixQMgrDispatcherLoopRunB0LLP (IxQMgrDispatchGroup group);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrNotificationCallbackSet (IxQMgrQId qId,
- IxQMgrCallback callback,
- IxQMgrCallbackId callbackId)
- *
- * @brief Set the notification callback for a queue.
- *
- * This function sets the callback for the specified queue. This callback will
- * be called by the dispatcher, and may be called in the context of a interrupt
- * If callback has a value of NULL the previously registered callback, if one
- * exists will be unregistered.
- *
- * @param qId @ref IxQMgrQId [in] - the queue idenfifier
- * @param callback @ref IxQMgrCallback [in] - the callback registered for this queue
- * @param callbackId @ref IxQMgrCallbackId [in] - the callback identifier
- *
- * @return @li IX_SUCCESS, the callback for the specified queue has been set
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, the specified qId has not been configured
- *
- */
-PUBLIC IX_STATUS
-ixQMgrNotificationCallbackSet (IxQMgrQId qId,
- IxQMgrCallback callback,
- IxQMgrCallbackId callbackId);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrDispatcherLoopGet (IxQMgrDispatcherFuncPtr *qDispatcherFuncPtr)
- *
- * @brief Get QMgr DispatcherLoopRun for respective silicon device
- *
- * This function gets a function pointer to ixQMgrDispatcherLoopRunA0() for IXP42X A0
- * Silicon. If the IXP42X B0 or 46X Silicon, the default is the ixQMgrDispatcherLoopRunB0()
- * function, however if live lock prevention is enabled a function pointer to
- * ixQMgrDispatcherLoopRunB0LLP() is given.
- *
- * @param *qDispatchFuncPtr @ref IxQMgrDispatcherFuncPtr [out] -
- * the function pointer of QMgr Dispatcher
- *
- */
-PUBLIC void
-ixQMgrDispatcherLoopGet (IxQMgrDispatcherFuncPtr *qDispatcherFuncPtr);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrStickyInterruptRegEnable(void)
- *
- * @brief Enable AQM's sticky interrupt register behaviour only available
- * on B0 Silicon.
- *
- * When AQM's sticky interrupt register is enabled, interrupt register bit will
- * only be cleared when a '1' is written to interrupt register bit and the
- * interrupting condition is satisfied, i.e.queue condition does not exist.
- *
- * @note This function must be called before any queue is enabled.
- * Calling this function after queue is enabled will cause
- * undefined results.
- *
- * @return none
- *
- */
-PUBLIC void
-ixQMgrStickyInterruptRegEnable(void);
-
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrCallbackTypeSet(IxQMgrQId qId,
- IxQMgrType type)
- *
- * @brief Set the Callback Type of a queue.
- *
- * This function is only used for live lock prevention.
- * This function allows the callback type of a queue to be set. The default for
- * all queues is IX_QMGR_TYPE_REALTIME_OTHER. Setting the type to
- * IX_QMGR_TYPE_REALTIME_SPORADIC means that this queue will have it's
- * notifications disabled while there is a task associated with a
- * queue of type IX_QMGR_TYPE_REALTIME_PERIODIC running. As live lock
- * prevention operates on lower queues, this function should
- * be called for lower queues only.
- * This function is not re-entrant.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier
- * @param type @ref IxQMgrType [in] - the type of callback
- *
- * @return @li IX_SUCCESS, successfully set callback type for the queue entry
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, queue not configured for this QId
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid parameter(s).
- *
- */
-PUBLIC IX_STATUS
-ixQMgrCallbackTypeSet(IxQMgrQId qId,
- IxQMgrType type);
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrCallbackTypeGet(IxQMgrQId qId,
- IxQMgrType *type)
- *
- * @brief Get the Callback Type of a queue.
- *
- * This function allows the callback type of a queue to be got. As live lock
- * prevention operates on lower queues, this function should
- * be called for lower queues only.
- * This function is re-entrant.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier
- * @param *type @ref IxQMgrType [out] - the type of callback
- *
- * @return @li IX_SUCCESS, successfully set callback type for the queue entry
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, queue not configured for this QId
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid parameter(s)
- *
- */
-PUBLIC IX_STATUS
-ixQMgrCallbackTypeGet(IxQMgrQId qId,
- IxQMgrType *type);
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrPeriodicDone(void)
- *
- * @brief Indicate that the Periodic task is completed for LLP
- *
- * This function is used as part of live lock prevention.
- * A periodic task is a task that results from a queue that
- * is set as type IX_QMGR_TYPE_REALTIME_PERIODIC. This function
- * should be called to indicate to the dispatcher that the
- * the periodic task is completed. This ensures that the notifications
- * for queues set as type sporadic queues are re-enabled.
- * This function is re-entrant.
- *
- */
-PUBLIC void
-ixQMgrPeriodicDone(void);
-
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrLLPShow(int resetStats)
- *
- * @brief Print out the live lock prevention statistics when in debug mode.
- *
- * This function prints out statistics related to the livelock. These
- * statistics are only collected in debug mode.
- * This function is not re-entrant.
- *
- * @param resetStats @ref int [in] - if set the the stats are reset.
- *
- */
-PUBLIC void
-ixQMgrLLPShow(int resetStats);
-
-
-#endif /* IXQMGR_H */
-
-/**
- * @} defgroup IxQMgrAPI
- */
-
-
+++ /dev/null
-/**
- * @file IxQMgrAqmIf_p.h
- *
- * @author Intel Corporation
- * @date 30-Oct-2001
- *
- * @brief The IxQMgrAqmIf sub-component provides a number of inline
- * functions for performing I/O on the AQM.
- *
- * Because some functions contained in this module are inline and are
- * used in other modules (within the QMgr component) the definitions are
- * contained in this header file. The "normal" use of inline functions
- * is to use the inline functions in the module in which they are
- * defined. In this case these inline functions are used in external
- * modules and therefore the use of "inline extern". What this means
- * is as follows: if a function foo is declared as "inline extern"this
- * definition is only used for inlining, in no case is the function
- * compiled on its own. If the compiler cannot inline the function it
- * becomes an external reference. Therefore in IxQMgrAqmIf.c all
- * inline functions are defined without the "inline extern" specifier
- * and so define the external references. In all other modules these
- * funtions are defined as "inline extern".
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-#ifndef IXQMGRAQMIF_P_H
-#define IXQMGRAQMIF_P_H
-
-#include "IxOsalTypes.h"
-
-/*
- * inline definition
- */
-
-#ifdef IX_OSAL_INLINE_ALL
-/* If IX_OSAL_INLINE_ALL is set then each inlineable API functions will be defined as
- inline functions */
-#define IX_QMGR_AQMIF_INLINE IX_OSAL_INLINE_EXTERN
-#else
-#ifdef IXQMGRAQMIF_C
-#ifndef IX_QMGR_AQMIF_INLINE
-#define IX_QMGR_AQMIF_INLINE
-#endif
-#else
-#ifndef IX_QMGR_AQMIF_INLINE
-#define IX_QMGR_AQMIF_INLINE IX_OSAL_INLINE_EXTERN
-#endif
-#endif /* IXQMGRAQMIF_C */
-#endif /* IX_OSAL_INLINE */
-
-
-/*
- * User defined include files.
- */
-#include "IxQMgr.h"
-#include "IxQMgrLog_p.h"
-#include "IxQMgrQCfg_p.h"
-
-/* Because this file contains inline functions which will be compiled into
- * other components, we need to ensure that the IX_COMPONENT_NAME define
- * is set to ix_qmgr while this code is being compiled. This will ensure
- * that the correct implementation is provided for the memory access macros
- * IX_OSAL_READ_LONG and IX_OSAL_WRITE_LONG which are used in this file.
- * This must be done before including "IxOsalMemAccess.h"
- */
-#define IX_QMGR_AQMIF_SAVED_COMPONENT_NAME IX_COMPONENT_NAME
-#undef IX_COMPONENT_NAME
-#define IX_COMPONENT_NAME ix_qmgr
-#include "IxOsal.h"
-
-/*
- * #defines and macros used in this file.
- */
-
-/* Number of bytes per word */
-#define IX_QMGR_NUM_BYTES_PER_WORD 4
-
-/* Underflow bit mask */
-#define IX_QMGR_UNDERFLOW_BIT_OFFSET 0x0
-
-/* Overflow bit mask */
-#define IX_QMGR_OVERFLOW_BIT_OFFSET 0x1
-
-/* Queue access register, queue 0 */
-#define IX_QMGR_QUEACC0_OFFSET 0x0000
-
-/* Size of queue access register in words */
-#define IX_QMGR_QUEACC_SIZE 0x4/*words*/
-
-/* Queue status register, queues 0-7 */
-#define IX_QMGR_QUELOWSTAT0_OFFSET (IX_QMGR_QUEACC0_OFFSET +\
-(IX_QMGR_MAX_NUM_QUEUES * IX_QMGR_QUEACC_SIZE * IX_QMGR_NUM_BYTES_PER_WORD))
-
-/* Queue status register, queues 8-15 */
-#define IX_QMGR_QUELOWSTAT1_OFFSET (IX_QMGR_QUELOWSTAT0_OFFSET +\
- IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue status register, queues 16-23 */
-#define IX_QMGR_QUELOWSTAT2_OFFSET (IX_QMGR_QUELOWSTAT1_OFFSET +\
- IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue status register, queues 24-31 */
-#define IX_QMGR_QUELOWSTAT3_OFFSET (IX_QMGR_QUELOWSTAT2_OFFSET +\
- IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue status register Q status bits mask */
-#define IX_QMGR_QUELOWSTAT_QUE_STS_BITS_MASK 0xF
-
-/* Size of queue 0-31 status register */
-#define IX_QMGR_QUELOWSTAT_SIZE 0x4 /*words*/
-
-/* The number of queues' status specified per word */
-#define IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD 0x8
-
-/* Queue UF/OF status register queues 0-15 */
-#define IX_QMGR_QUEUOSTAT0_OFFSET (IX_QMGR_QUELOWSTAT3_OFFSET +\
- IX_QMGR_NUM_BYTES_PER_WORD)
-/* Queue UF/OF status register queues 16-31 */
-#define IX_QMGR_QUEUOSTAT1_OFFSET (IX_QMGR_QUEUOSTAT0_OFFSET +\
- IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* The number of queues' underflow/overflow status specified per word */
-#define IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD 0x10
-
-/* Queue NE status register, queues 32-63 */
-#define IX_QMGR_QUEUPPSTAT0_OFFSET (IX_QMGR_QUEUOSTAT1_OFFSET +\
- IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue F status register, queues 32-63 */
-#define IX_QMGR_QUEUPPSTAT1_OFFSET (IX_QMGR_QUEUPPSTAT0_OFFSET +\
- IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Size of queue 32-63 status register */
-#define IX_QMGR_QUEUPPSTAT_SIZE 0x2 /*words*/
-
-/* The number of queues' status specified per word */
-#define IX_QMGR_QUEUPPSTAT_NUM_QUE_PER_WORD 0x20
-
-/* Queue INT source select register, queues 0-7 */
-#define IX_QMGR_INT0SRCSELREG0_OFFSET (IX_QMGR_QUEUPPSTAT1_OFFSET +\
- IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue INT source select register, queues 8-15 */
-#define IX_QMGR_INT0SRCSELREG1_OFFSET (IX_QMGR_INT0SRCSELREG0_OFFSET+\
- IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue INT source select register, queues 16-23 */
-#define IX_QMGR_INT0SRCSELREG2_OFFSET (IX_QMGR_INT0SRCSELREG1_OFFSET+\
- IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue INT source select register, queues 24-31 */
-#define IX_QMGR_INT0SRCSELREG3_OFFSET (IX_QMGR_INT0SRCSELREG2_OFFSET+\
- IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Size of interrupt source select reegister */
-#define IX_QMGR_INT0SRCSELREG_SIZE 0x4 /*words*/
-
-/* The number of queues' interrupt source select specified per word*/
-#define IX_QMGR_INTSRC_NUM_QUE_PER_WORD 0x8
-
-/* Queue INT enable register, queues 0-31 */
-#define IX_QMGR_QUEIEREG0_OFFSET (IX_QMGR_INT0SRCSELREG3_OFFSET +\
- IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue INT enable register, queues 32-63 */
-#define IX_QMGR_QUEIEREG1_OFFSET (IX_QMGR_QUEIEREG0_OFFSET +\
- IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue INT register, queues 0-31 */
-#define IX_QMGR_QINTREG0_OFFSET (IX_QMGR_QUEIEREG1_OFFSET +\
- IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue INT register, queues 32-63 */
-#define IX_QMGR_QINTREG1_OFFSET (IX_QMGR_QINTREG0_OFFSET +\
- IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Size of interrupt register */
-#define IX_QMGR_QINTREG_SIZE 0x2 /*words*/
-
-/* Number of queues' status specified per word */
-#define IX_QMGR_QINTREG_NUM_QUE_PER_WORD 0x20
-
-/* Number of bits per queue interrupt status */
-#define IX_QMGR_QINTREG_BITS_PER_QUEUE 0x1
-#define IX_QMGR_QINTREG_BIT_OFFSET 0x1
-
-/* Size of address space not used by AQM */
-#define IX_QMGR_AQM_UNUSED_ADDRESS_SPACE_SIZE_IN_BYTES 0x1bC0
-
-/* Queue config register, queue 0 */
-#define IX_QMGR_QUECONFIG_BASE_OFFSET (IX_QMGR_QINTREG1_OFFSET +\
- IX_QMGR_NUM_BYTES_PER_WORD +\
- IX_QMGR_AQM_UNUSED_ADDRESS_SPACE_SIZE_IN_BYTES)
-
-/* Total size of configuration words */
-#define IX_QMGR_QUECONFIG_SIZE 0x100
-
-/* Start of SRAM queue buffer space */
-#define IX_QMGR_QUEBUFFER_SPACE_OFFSET (IX_QMGR_QUECONFIG_BASE_OFFSET +\
- IX_QMGR_MAX_NUM_QUEUES * IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Total bits in a word */
-#define BITS_PER_WORD 32
-
-/* Size of queue buffer space */
-#define IX_QMGR_QUE_BUFFER_SPACE_SIZE 0x1F00
-
-/*
- * This macro will return the address of the access register for the
- * queue specified by qId
- */
-#define IX_QMGR_Q_ACCESS_ADDR_GET(qId)\
- (((qId) * (IX_QMGR_QUEACC_SIZE * IX_QMGR_NUM_BYTES_PER_WORD))\
- + IX_QMGR_QUEACC0_OFFSET)
-
-/*
- * Bit location of bit-3 of INT0SRCSELREG0 register to enabled
- * sticky interrupt register.
- */
-#define IX_QMGR_INT0SRCSELREG0_BIT3 3
-
-/*
- * Variable declerations global to this file. Externs are followed by
- * statics.
- */
-extern UINT32 aqmBaseAddress;
-
-/*
- * Function declarations.
- */
-void
-ixQMgrAqmIfInit (void);
-
-void
-ixQMgrAqmIfUninit (void);
-
-unsigned
-ixQMgrAqmIfLog2 (unsigned number);
-
-void
-ixQMgrAqmIfQRegisterBitsWrite (IxQMgrQId qId,
- UINT32 registerBaseAddrOffset,
- unsigned queuesPerRegWord,
- UINT32 value);
-
-void
-ixQMgrAqmIfQStatusCheckValsCalc (IxQMgrQId qId,
- IxQMgrSourceId srcSel,
- unsigned int *statusWordOffset,
- UINT32 *checkValue,
- UINT32 *mask);
-/*
- * The Xscale software allways deals with logical addresses and so the
- * base address of the AQM memory space is not a hardcoded value. This
- * function must be called before any other function in this component.
- * NO CHECKING is performed to ensure that the base address has been
- * set.
- */
-void
-ixQMgrAqmIfBaseAddressSet (UINT32 address);
-
-/*
- * Get the base address of the AQM memory space.
- */
-void
-ixQMgrAqmIfBaseAddressGet (UINT32 *address);
-
-/*
- * Get the sram base address
- */
-void
-ixQMgrAqmIfSramBaseAddressGet (UINT32 *address);
-
-/*
- * Read a queue status
- */
-void
-ixQMgrAqmIfQueStatRead (IxQMgrQId qId,
- IxQMgrQStatus* status);
-
-
-/*
- * Set INT0SRCSELREG0 Bit3
- */
-void ixQMgrAqmIfIntSrcSelReg0Bit3Set (void);
-
-
-/*
- * Set the interrupt source
- */
-void
-ixQMgrAqmIfIntSrcSelWrite (IxQMgrQId qId,
- IxQMgrSourceId sourceId);
-
-/*
- * Enable interruptson a queue
- */
-void
-ixQMgrAqmIfQInterruptEnable (IxQMgrQId qId);
-
-/*
- * Disable interrupt on a quee
- */
-void
-ixQMgrAqmIfQInterruptDisable (IxQMgrQId qId);
-
-/*
- * Write the config register of the specified queue
- */
-void
-ixQMgrAqmIfQueCfgWrite (IxQMgrQId qId,
- IxQMgrQSizeInWords qSizeInWords,
- IxQMgrQEntrySizeInWords entrySizeInWords,
- UINT32 freeSRAMAddress);
-
-/*
- * read fields from the config of the specified queue.
- */
-void
-ixQMgrAqmIfQueCfgRead (IxQMgrQId qId,
- unsigned int numEntries,
- UINT32 *baseAddress,
- unsigned int *ne,
- unsigned int *nf,
- UINT32 *readPtr,
- UINT32 *writePtr);
-
-/*
- * Set the ne and nf watermark level on a queue.
- */
-void
-ixQMgrAqmIfWatermarkSet (IxQMgrQId qId,
- unsigned ne,
- unsigned nf);
-
-/* Inspect an entry without moving the read pointer */
-IX_STATUS
-ixQMgrAqmIfQPeek (IxQMgrQId qId,
- unsigned int entryIndex,
- unsigned int *entry);
-
-/* Modify an entry without moving the write pointer */
-IX_STATUS
-ixQMgrAqmIfQPoke (IxQMgrQId qId,
- unsigned int entryIndex,
- unsigned int *entry);
-
-/*
- * Function prototype for inline functions. For description refers to
- * the functions defintion below.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfWordWrite (VUINT32 *address,
- UINT32 word);
-
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfWordRead (VUINT32 *address,
- UINT32 *word);
-
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQPop (IxQMgrQId qId,
- IxQMgrQEntrySizeInWords numWords,
- UINT32 *entry);
-
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQPush (IxQMgrQId qId,
- IxQMgrQEntrySizeInWords numWords,
- UINT32 *entry);
-
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQStatusRegsRead (IxQMgrDispatchGroup group,
- UINT32 *qStatusWords);
-
-IX_QMGR_AQMIF_INLINE BOOL
-ixQMgrAqmIfQStatusCheck (UINT32 *oldQStatusWords,
- UINT32 *newQStatusWords,
- unsigned int statusWordOffset,
- UINT32 checkValue,
- UINT32 mask);
-
-IX_QMGR_AQMIF_INLINE BOOL
-ixQMgrAqmIfRegisterBitCheck (IxQMgrQId qId,
- UINT32 registerBaseAddrOffset,
- unsigned queuesPerRegWord,
- unsigned relativeBitOffset,
- BOOL reset);
-
-IX_QMGR_AQMIF_INLINE BOOL
-ixQMgrAqmIfUnderflowCheck (IxQMgrQId qId);
-
-IX_QMGR_AQMIF_INLINE BOOL
-ixQMgrAqmIfOverflowCheck (IxQMgrQId qId);
-
-IX_QMGR_AQMIF_INLINE UINT32
-ixQMgrAqmIfQRegisterBitsRead (IxQMgrQId qId,
- UINT32 registerBaseAddrOffset,
- unsigned queuesPerRegWord);
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQInterruptRegWrite (IxQMgrDispatchGroup group,
- UINT32 reg);
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQInterruptRegRead (IxQMgrDispatchGroup group,
- UINT32 *regVal);
-
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQueLowStatRead (IxQMgrQId qId,
- IxQMgrQStatus *status);
-
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQueUppStatRead (IxQMgrQId qId,
- IxQMgrQStatus *status);
-
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQueStatRead (IxQMgrQId qId,
- IxQMgrQStatus *qStatus);
-
-IX_QMGR_AQMIF_INLINE unsigned
-ixQMgrAqmIfPow2NumDivide (unsigned numerator,
- unsigned denominator);
-
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQInterruptEnableRegRead (IxQMgrDispatchGroup group,
- UINT32 *regVal);
-/*
- * Inline functions
- */
-
-/*
- * This inline function is used by other QMgr components to write one
- * word to the specified address.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfWordWrite (VUINT32 *address,
- UINT32 word)
-{
- IX_OSAL_WRITE_LONG(address, word);
-}
-
-/*
- * This inline function is used by other QMgr components to read a
- * word from the specified address.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfWordRead (VUINT32 *address,
- UINT32 *word)
-{
- *word = IX_OSAL_READ_LONG(address);
-}
-
-
-/*
- * This inline function is used by other QMgr components to pop an
- * entry off the specified queue.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQPop (IxQMgrQId qId,
- IxQMgrQEntrySizeInWords numWords,
- UINT32 *entry)
-{
- volatile UINT32 *accRegAddr;
-
- accRegAddr = (UINT32*)(aqmBaseAddress +
- IX_QMGR_Q_ACCESS_ADDR_GET(qId));
-
- switch (numWords)
- {
- case IX_QMGR_Q_ENTRY_SIZE1:
- ixQMgrAqmIfWordRead (accRegAddr, entry);
- break;
- case IX_QMGR_Q_ENTRY_SIZE2:
- ixQMgrAqmIfWordRead (accRegAddr++, entry++);
- ixQMgrAqmIfWordRead (accRegAddr, entry);
- break;
- case IX_QMGR_Q_ENTRY_SIZE4:
- ixQMgrAqmIfWordRead (accRegAddr++, entry++);
- ixQMgrAqmIfWordRead (accRegAddr++, entry++);
- ixQMgrAqmIfWordRead (accRegAddr++, entry++);
- ixQMgrAqmIfWordRead (accRegAddr, entry);
- break;
- default:
- IX_QMGR_LOG_ERROR0("Invalid Q Entry size passed to ixQMgrAqmIfQPop");
- break;
- }
-}
-
-/*
- * This inline function is used by other QMgr components to push an
- * entry to the specified queue.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQPush (IxQMgrQId qId,
- IxQMgrQEntrySizeInWords numWords,
- UINT32 *entry)
-{
- volatile UINT32 *accRegAddr;
-
- accRegAddr = (UINT32*)(aqmBaseAddress +
- IX_QMGR_Q_ACCESS_ADDR_GET(qId));
-
- switch (numWords)
- {
- case IX_QMGR_Q_ENTRY_SIZE1:
- ixQMgrAqmIfWordWrite (accRegAddr, *entry);
- break;
- case IX_QMGR_Q_ENTRY_SIZE2:
- ixQMgrAqmIfWordWrite (accRegAddr++, *entry++);
- ixQMgrAqmIfWordWrite (accRegAddr, *entry);
- break;
- case IX_QMGR_Q_ENTRY_SIZE4:
- ixQMgrAqmIfWordWrite (accRegAddr++, *entry++);
- ixQMgrAqmIfWordWrite (accRegAddr++, *entry++);
- ixQMgrAqmIfWordWrite (accRegAddr++, *entry++);
- ixQMgrAqmIfWordWrite (accRegAddr, *entry);
- break;
- default:
- IX_QMGR_LOG_ERROR0("Invalid Q Entry size passed to ixQMgrAqmIfQPush");
- break;
- }
-}
-
-/*
- * The AQM interrupt registers contains a bit for each AQM queue
- * specifying the queue (s) that cause an interrupt to fire. This
- * function is called by IxQMGrDispatcher component.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQStatusRegsRead (IxQMgrDispatchGroup group,
- UINT32 *qStatusWords)
-{
- volatile UINT32 *regAddress = NULL;
-
- if (group == IX_QMGR_QUELOW_GROUP)
- {
- regAddress = (UINT32*)(aqmBaseAddress +
- IX_QMGR_QUELOWSTAT0_OFFSET);
-
- ixQMgrAqmIfWordRead (regAddress++, qStatusWords++);
- ixQMgrAqmIfWordRead (regAddress++, qStatusWords++);
- ixQMgrAqmIfWordRead (regAddress++, qStatusWords++);
- ixQMgrAqmIfWordRead (regAddress, qStatusWords);
- }
- else /* We have the upper queues */
- {
- /* Only need to read the Nearly Empty status register for
- * queues 32-63 as for therse queues the interrtupt source
- * condition is fixed to Nearly Empty
- */
- regAddress = (UINT32*)(aqmBaseAddress +
- IX_QMGR_QUEUPPSTAT0_OFFSET);
- ixQMgrAqmIfWordRead (regAddress, qStatusWords);
- }
-}
-
-
-/*
- * This function check if the status for a queue has changed between
- * 2 snapshots and if it has, that the status matches a particular
- * value after masking.
- */
-IX_QMGR_AQMIF_INLINE BOOL
-ixQMgrAqmIfQStatusCheck (UINT32 *oldQStatusWords,
- UINT32 *newQStatusWords,
- unsigned int statusWordOffset,
- UINT32 checkValue,
- UINT32 mask)
-{
- if (((oldQStatusWords[statusWordOffset] & mask) !=
- (newQStatusWords[statusWordOffset] & mask)) &&
- ((newQStatusWords[statusWordOffset] & mask) == checkValue))
- {
- return true;
- }
-
- return false;
-}
-
-/*
- * The AQM interrupt register contains a bit for each AQM queue
- * specifying the queue (s) that cause an interrupt to fire. This
- * function is called by IxQMgrDispatcher component.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQInterruptRegRead (IxQMgrDispatchGroup group,
- UINT32 *regVal)
-{
- volatile UINT32 *regAddress;
-
- if (group == IX_QMGR_QUELOW_GROUP)
- {
- regAddress = (UINT32*)(aqmBaseAddress +
- IX_QMGR_QINTREG0_OFFSET);
- }
- else
- {
- regAddress = (UINT32*)(aqmBaseAddress +
- IX_QMGR_QINTREG1_OFFSET);
- }
-
- ixQMgrAqmIfWordRead (regAddress, regVal);
-}
-
-/*
- * The AQM interrupt enable register contains a bit for each AQM queue.
- * This function reads the interrupt enable register. This
- * function is called by IxQMgrDispatcher component.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQInterruptEnableRegRead (IxQMgrDispatchGroup group,
- UINT32 *regVal)
-{
- volatile UINT32 *regAddress;
-
- if (group == IX_QMGR_QUELOW_GROUP)
- {
- regAddress = (UINT32*)(aqmBaseAddress +
- IX_QMGR_QUEIEREG0_OFFSET);
- }
- else
- {
- regAddress = (UINT32*)(aqmBaseAddress +
- IX_QMGR_QUEIEREG1_OFFSET);
- }
-
- ixQMgrAqmIfWordRead (regAddress, regVal);
-}
-
-
-/*
- * This inline function will read the status bit of a queue
- * specified by qId. If reset is true the bit is cleared.
- */
-IX_QMGR_AQMIF_INLINE BOOL
-ixQMgrAqmIfRegisterBitCheck (IxQMgrQId qId,
- UINT32 registerBaseAddrOffset,
- unsigned queuesPerRegWord,
- unsigned relativeBitOffset,
- BOOL reset)
-{
- UINT32 actualBitOffset;
- volatile UINT32 *registerAddress;
- UINT32 registerWord;
-
- /*
- * Calculate the registerAddress
- * multiple queues split accross registers
- */
- registerAddress = (UINT32*)(aqmBaseAddress +
- registerBaseAddrOffset +
- ((qId / queuesPerRegWord) *
- IX_QMGR_NUM_BYTES_PER_WORD));
-
- /*
- * Get the status word
- */
- ixQMgrAqmIfWordRead (registerAddress, ®isterWord);
-
- /*
- * Calculate the actualBitOffset
- * status for multiple queues stored in one register
- */
- actualBitOffset = (relativeBitOffset + 1) <<
- ((qId & (queuesPerRegWord - 1)) * (BITS_PER_WORD / queuesPerRegWord));
-
- /* Check if the status bit is set */
- if (registerWord & actualBitOffset)
- {
- /* Clear the bit if reset */
- if (reset)
- {
- ixQMgrAqmIfWordWrite (registerAddress, registerWord & (~actualBitOffset));
- }
- return true;
- }
-
- /* Bit not set */
- return false;
-}
-
-
-/*
- * @ingroup IxQmgrAqmIfAPI
- *
- * @brief Read the underflow status of a queue
- *
- * This inline function will read the underflow status of a queue
- * specified by qId.
- *
- */
-IX_QMGR_AQMIF_INLINE BOOL
-ixQMgrAqmIfUnderflowCheck (IxQMgrQId qId)
-{
- if (qId < IX_QMGR_MIN_QUEUPP_QID)
- {
- return (ixQMgrAqmIfRegisterBitCheck (qId,
- IX_QMGR_QUEUOSTAT0_OFFSET,
- IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD,
- IX_QMGR_UNDERFLOW_BIT_OFFSET,
- true/*reset*/));
- }
- else
- {
- /* Qs 32-63 have no underflow status */
- return false;
- }
-}
-
-/*
- * This inline function will read the overflow status of a queue
- * specified by qId.
- */
-IX_QMGR_AQMIF_INLINE BOOL
-ixQMgrAqmIfOverflowCheck (IxQMgrQId qId)
-{
- if (qId < IX_QMGR_MIN_QUEUPP_QID)
- {
- return (ixQMgrAqmIfRegisterBitCheck (qId,
- IX_QMGR_QUEUOSTAT0_OFFSET,
- IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD,
- IX_QMGR_OVERFLOW_BIT_OFFSET,
- true/*reset*/));
- }
- else
- {
- /* Qs 32-63 have no overflow status */
- return false;
- }
-}
-
-/*
- * This inline function will read the status bits of a queue
- * specified by qId.
- */
-IX_QMGR_AQMIF_INLINE UINT32
-ixQMgrAqmIfQRegisterBitsRead (IxQMgrQId qId,
- UINT32 registerBaseAddrOffset,
- unsigned queuesPerRegWord)
-{
- volatile UINT32 *registerAddress;
- UINT32 registerWord;
- UINT32 statusBitsMask;
- UINT32 bitsPerQueue;
-
- bitsPerQueue = BITS_PER_WORD / queuesPerRegWord;
-
- /*
- * Calculate the registerAddress
- * multiple queues split accross registers
- */
- registerAddress = (UINT32*)(aqmBaseAddress +
- registerBaseAddrOffset +
- ((qId / queuesPerRegWord) *
- IX_QMGR_NUM_BYTES_PER_WORD));
- /*
- * Read the status word
- */
- ixQMgrAqmIfWordRead (registerAddress, ®isterWord);
-
-
- /*
- * Calculate the mask for the status bits for this queue.
- */
- statusBitsMask = ((1 << bitsPerQueue) - 1);
-
- /*
- * Shift the status word so it is right justified
- */
- registerWord >>= ((qId & (queuesPerRegWord - 1)) * bitsPerQueue);
-
- /*
- * Mask out all bar the status bits for this queue
- */
- return (registerWord &= statusBitsMask);
-}
-
-/*
- * This function is called by IxQMgrDispatcher to set the contents of
- * the AQM interrupt register.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQInterruptRegWrite (IxQMgrDispatchGroup group,
- UINT32 reg)
-{
- volatile UINT32 *address;
-
- if (group == IX_QMGR_QUELOW_GROUP)
- {
- address = (UINT32*)(aqmBaseAddress +
- IX_QMGR_QINTREG0_OFFSET);
- }
- else
- {
- address = (UINT32*)(aqmBaseAddress +
- IX_QMGR_QINTREG1_OFFSET);
- }
-
- ixQMgrAqmIfWordWrite (address, reg);
-}
-
-/*
- * Read the status of a queue in the range 0-31.
- *
- * This function is used by other QMgr components to read the
- * status of the queue specified by qId.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQueLowStatRead (IxQMgrQId qId,
- IxQMgrQStatus *status)
-{
- /* Read the general status bits */
- *status = ixQMgrAqmIfQRegisterBitsRead (qId,
- IX_QMGR_QUELOWSTAT0_OFFSET,
- IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD);
-}
-
-/*
- * This function will read the status of the queue specified
- * by qId.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQueUppStatRead (IxQMgrQId qId,
- IxQMgrQStatus *status)
-{
- /* Reset the status bits */
- *status = 0;
-
- /*
- * Check if the queue is nearly empty,
- * N.b. QUPP stat register contains status for regs 32-63 at each
- * bit position so subtract 32 to get bit offset
- */
- if (ixQMgrAqmIfRegisterBitCheck ((qId - IX_QMGR_MIN_QUEUPP_QID),
- IX_QMGR_QUEUPPSTAT0_OFFSET,
- IX_QMGR_QUEUPPSTAT_NUM_QUE_PER_WORD,
- 0/*relativeBitOffset*/,
- false/*!reset*/))
- {
- *status |= IX_QMGR_Q_STATUS_NE_BIT_MASK;
- }
-
- /*
- * Check if the queue is full,
- * N.b. QUPP stat register contains status for regs 32-63 at each
- * bit position so subtract 32 to get bit offset
- */
- if (ixQMgrAqmIfRegisterBitCheck ((qId - IX_QMGR_MIN_QUEUPP_QID),
- IX_QMGR_QUEUPPSTAT1_OFFSET,
- IX_QMGR_QUEUPPSTAT_NUM_QUE_PER_WORD,
- 0/*relativeBitOffset*/,
- false/*!reset*/))
- {
- *status |= IX_QMGR_Q_STATUS_F_BIT_MASK;
- }
-}
-
-/*
- * This function is used by other QMgr components to read the
- * status of the queue specified by qId.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQueStatRead (IxQMgrQId qId,
- IxQMgrQStatus *qStatus)
-{
- if (qId < IX_QMGR_MIN_QUEUPP_QID)
- {
- ixQMgrAqmIfQueLowStatRead (qId, qStatus);
- }
- else
- {
- ixQMgrAqmIfQueUppStatRead (qId, qStatus);
- }
-}
-
-
-/*
- * This function performs a mod division
- */
-IX_QMGR_AQMIF_INLINE unsigned
-ixQMgrAqmIfPow2NumDivide (unsigned numerator,
- unsigned denominator)
-{
- /* Number is evenly divisable by 2 */
- return (numerator >> ixQMgrAqmIfLog2 (denominator));
-}
-
-/* Restore IX_COMPONENT_NAME */
-#undef IX_COMPONENT_NAME
-#define IX_COMPONENT_NAME IX_QMGR_AQMIF_SAVED_COMPONENT_NAME
-
-#endif/*IXQMGRAQMIF_P_H*/
+++ /dev/null
-/**
- * @file IxQMgrDefines_p.h
- *
- * @author Intel Corporation
- * @date 19-Jul-2002
- *
- * @brief IxQMgr Defines and tuneable constants
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-#ifndef IXQMGRDEFINES_P_H
-#define IXQMGRDEFINES_P_H
-
-#define IX_QMGR_PARM_CHECKS_ENABLED 1
-#define IX_QMGR_STATS_UPDATE_ENABLED 1
-
-#endif /* IXQMGRDEFINES_P_H */
+++ /dev/null
-/**
- * @file IxQMgrDispatcher_p.h
- *
- * @author Intel Corporation
- * @date 07-Feb-2002
- *
- * @brief This file contains the internal functions for dispatcher
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-#ifndef IXQMGRDISPATCHER_P_H
-#define IXQMGRDISPATCHER_P_H
-
-/*
- * User defined include files
- */
-#include "IxQMgr.h"
-
-/*
- * This structure defines the statistic data for a queue
- */
-typedef struct
-{
- unsigned callbackCnt; /* Call count of callback */
- unsigned priorityChangeCnt; /* Priority change count */
- unsigned intNoCallbackCnt; /* Interrupt fired but no callback set count */
- unsigned intLostCallbackCnt; /* Interrupt lost and detected ; SCR541 */
- BOOL notificationEnabled; /* Interrupt enabled for this queue */
- IxQMgrSourceId srcSel; /* interrupt source */
- unsigned enableCount; /* num times notif enabled by LLP */
- unsigned disableCount; /* num of times notif disabled by LLP */
-} IxQMgrDispatcherQStats;
-
-/*
- * This structure defines statistic data for the disatcher
- */
-typedef struct
- {
- unsigned loopRunCnt; /* ixQMgrDispatcherLoopRun count */
-
- IxQMgrDispatcherQStats queueStats[IX_QMGR_MAX_NUM_QUEUES];
-
-} IxQMgrDispatcherStats;
-
-/*
- * Initialise the dispatcher component
- */
-void
-ixQMgrDispatcherInit (void);
-
-/*
- * Get the dispatcher statistics
- */
-IxQMgrDispatcherStats*
-ixQMgrDispatcherStatsGet (void);
-
-/**
- * Retrieve the number of leading zero bits starting from the MSB
- * This function is implemented as an (extremely fast) asm routine
- * for XSCALE processor (see clz instruction) and as a (slower) C
- * function for other systems.
- */
-unsigned int
-ixQMgrCountLeadingZeros(unsigned int value);
-
-#endif/*IXQMGRDISPATCHER_P_H*/
-
-
+++ /dev/null
-/**
- * @file IxQMgrLog_p.h
- *
- * @author Intel Corporation
- * @date 07-Feb-2002
- *
- * @brief This file contains the internal functions for config
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-#ifndef IXQMGRLOG_P_H
-#define IXQMGRLOG_P_H
-
-/*
- * User defined header files
- */
-#include "IxOsal.h"
-
-/*
- * Macros
- */
-
-#define IX_QMGR_LOG0(string) do\
-{\
- ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, string, 0, 0, 0, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG1(string, arg1) do\
-{\
- ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, string, (int)arg1, 0, 0, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG2(string, arg1, arg2) do\
-{\
- ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, string, (int)arg1, (int)arg2, 0, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG3(string, arg1, arg2, arg3) do\
-{\
- ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, string, (int)arg1, (int)arg2, (int)arg3, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG6(string, arg1, arg2, arg3, arg4, arg5, arg6) do\
-{\
- ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, string, (int)arg1, (int)arg2, (int)arg3, (int)arg4, (int)arg5, (int)arg6); \
-}while(0);
-
-#define IX_QMGR_LOG_WARNING0(string) do\
-{\
- ixOsalLog(IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT, string, 0, 0, 0, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG_WARNING1(string, arg1) do\
-{\
- ixOsalLog(IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT, string, (int)arg1, 0, 0, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG_WARNING2(string, arg1, arg2) do\
-{\
- ixOsalLog(IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT, string, (int)arg1, (int)arg2, 0, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG_ERROR0(string) do\
-{\
- ixOsalLog(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, string, 0, 0, 0, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG_ERROR1(string, arg1) do\
-{\
- ixOsalLog(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, string, (int)arg1, 0, 0, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG_ERROR2(string, arg1, arg2) do\
-{\
- ixOsalLog(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, string, (int)arg1, (int)arg2, 0, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG_ERROR3(string, arg1, arg2, arg3) do\
-{\
- ixOsalLog(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, string, (int)arg1, (int)arg2, (int)arg3, 0, 0, 0);\
-}while(0);
-#endif /* IX_QMGRLOG_P_H */
-
-
-
-
+++ /dev/null
-/**
- * @file IxQMgrQAccess_p.h
- *
- * @author Intel Corporation
- * @date 30-Oct-2001
- *
- * @brief QAccess private header file
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-#ifndef IXQMGRQACCESS_P_H
-#define IXQMGRQACCESS_P_H
-
-/*
- * User defined header files
- */
-#include "IxQMgr.h"
-
-/*
- * Global variables declarations.
- */
-extern volatile UINT32 * ixQMgrAqmIfQueAccRegAddr[];
-
-/*
- * Initialise the Queue Access component
- */
-void
-ixQMgrQAccessInit (void);
-
-/*
- * read the remainder of a multi-word queue entry
- * (the first word is already read)
- */
-IX_STATUS
-ixQMgrQReadMWordsMinus1 (IxQMgrQId qId,
- UINT32 *entry);
-
-/*
- * Fast access : pop a q entry from a single word queue
- */
-extern __inline__ UINT32 ixQMgrQAccessPop(IxQMgrQId qId);
-
-extern __inline__ UINT32 ixQMgrQAccessPop(IxQMgrQId qId)
-{
- return *(ixQMgrAqmIfQueAccRegAddr[qId]);
-}
-
-/*
- * Fast access : push a q entry in a single word queue
- */
-extern __inline__ void ixQMgrQAccessPush(IxQMgrQId qId, UINT32 entry);
-
-extern __inline__ void ixQMgrQAccessPush(IxQMgrQId qId, UINT32 entry)
-{
- *(ixQMgrAqmIfQueAccRegAddr[qId]) = entry;
-}
-
-#endif/*IXQMGRQACCESS_P_H*/
+++ /dev/null
-/**
- * @file IxQMgrQCfg_p.h
- *
- * @author Intel Corporation
- * @date 07-Feb-2002
- *
- * @brief This file contains the internal functions for config
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-#ifndef IXQMGRQCFG_P_H
-#define IXQMGRQCFG_P_H
-
-/*
- * User defined header files
- */
-#include "IxQMgr.h"
-
-/*
- * Typedefs
- */
-typedef struct
-{
- unsigned wmSetCnt;
-
- struct
- {
- char *qName;
- BOOL isConfigured;
- unsigned int qSizeInWords;
- unsigned int qEntrySizeInWords;
- unsigned int ne;
- unsigned int nf;
- unsigned int numEntries;
- UINT32 baseAddress;
- UINT32 readPtr;
- UINT32 writePtr;
- } qStats[IX_QMGR_MAX_NUM_QUEUES];
-
-} IxQMgrQCfgStats;
-
-/*
- * Initialize the QCfg subcomponent
- */
-void
-ixQMgrQCfgInit (void);
-
-/*
- * Uninitialize the QCfg subcomponent
- */
-void
-ixQMgrQCfgUninit (void);
-
-/*
- * Get the Q size in words
- */
-IxQMgrQSizeInWords
-ixQMgrQSizeInWordsGet (IxQMgrQId qId);
-
-/*
- * Get the Q entry size in words
- */
-IxQMgrQEntrySizeInWords
-ixQMgrQEntrySizeInWordsGet (IxQMgrQId qId);
-
-/*
- * Get the generic cfg stats
- */
-IxQMgrQCfgStats*
-ixQMgrQCfgStatsGet (void);
-
-/*
- * Get queue specific stats
- */
-IxQMgrQCfgStats*
-ixQMgrQCfgQStatsGet (IxQMgrQId qId);
-
-/*
- * Check is the queue configured
- */
-BOOL
-ixQMgrQIsConfigured(IxQMgrQId qId);
-
-#endif /* IX_QMGRQCFG_P_H */
+++ /dev/null
-/**
- * @file IxQueueAssignments.h
- *
- * @author Intel Corporation
- * @date 29-Oct-2004
- *
- * @brief Central definition for queue assignments
- *
- * Design Notes:
- * This file contains queue assignments used by Ethernet (EthAcc),
- * HSS (HssAcc), ATM (atmdAcc) and DMA (dmaAcc) access libraries.
- *
- * Note: Ethernet QoS traffic class definitions are managed separately
- * by EthDB in IxEthDBQoS.h.
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxQueueAssignments_H
-#define IxQueueAssignments_H
-
-#include "IxQMgr.h"
-
-/***************************************************************************
- * Queue assignments for ATM
- ***************************************************************************/
-
-/**
- * @brief Global compiler switch to select between 3 possible NPE Modes
- * Define this macro to enable MPHY mode
- *
- * Default(No Switch) = MultiPHY Utopia2
- * IX_UTOPIAMODE = 1 for single Phy Utopia1
- * IX_MPHYSINGLEPORT = 1 for single Phy Utopia2
- */
-#define IX_NPE_MPHYMULTIPORT 1
-#if IX_UTOPIAMODE == 1
-#undef IX_NPE_MPHYMULTIPORT
-#endif
-#if IX_MPHYSINGLEPORT == 1
-#undef IX_NPE_MPHYMULTIPORT
-#endif
-
-/**
- * @def IX_NPE_A_TXDONE_QUEUE_HIGHWATERMARK
- *
- * @brief The NPE reserves the High Watermark for its operation. But it must be set by the Xscale
- */
-#define IX_NPE_A_TXDONE_QUEUE_HIGHWATERMARK 2
-
-/**
- * @def IX_NPE_A_QMQ_ATM_TX_DONE
- *
- * @brief Queue ID for ATM Transmit Done queue
- */
-#define IX_NPE_A_QMQ_ATM_TX_DONE IX_QMGR_QUEUE_1
-
-/**
- * @def IX_NPE_A_QMQ_ATM_TX0
- *
- * @brief Queue ID for ATM transmit Queue in a single phy configuration
- */
-#define IX_NPE_A_QMQ_ATM_TX0 IX_QMGR_QUEUE_2
-
-
-/**
- * @def IX_NPE_A_QMQ_ATM_TXID_MIN
- *
- * @brief Queue Manager Queue ID for ATM transmit Queue with minimum number of queue
- *
- */
-
-/**
- * @def IX_NPE_A_QMQ_ATM_TXID_MAX
- *
- * @brief Queue Manager Queue ID for ATM transmit Queue with maximum number of queue
- *
- */
-
-/**
- * @def IX_NPE_A_QMQ_ATM_RX_HI
- *
- * @brief Queue Manager Queue ID for ATM Receive high Queue
- *
- */
-
-/**
- * @def IX_NPE_A_QMQ_ATM_RX_LO
- *
- * @brief Queue Manager Queue ID for ATM Receive low Queue
- */
-
-#ifdef IX_NPE_MPHYMULTIPORT
-/**
- * @def IX_NPE_A_QMQ_ATM_TX1
- *
- * @brief Queue ID for ATM transmit Queue Multiphy from 1 to 11
- */
-#define IX_NPE_A_QMQ_ATM_TX1 IX_NPE_A_QMQ_ATM_TX0+1
-#define IX_NPE_A_QMQ_ATM_TX2 IX_NPE_A_QMQ_ATM_TX1+1
-#define IX_NPE_A_QMQ_ATM_TX3 IX_NPE_A_QMQ_ATM_TX2+1
-#define IX_NPE_A_QMQ_ATM_TX4 IX_NPE_A_QMQ_ATM_TX3+1
-#define IX_NPE_A_QMQ_ATM_TX5 IX_NPE_A_QMQ_ATM_TX4+1
-#define IX_NPE_A_QMQ_ATM_TX6 IX_NPE_A_QMQ_ATM_TX5+1
-#define IX_NPE_A_QMQ_ATM_TX7 IX_NPE_A_QMQ_ATM_TX6+1
-#define IX_NPE_A_QMQ_ATM_TX8 IX_NPE_A_QMQ_ATM_TX7+1
-#define IX_NPE_A_QMQ_ATM_TX9 IX_NPE_A_QMQ_ATM_TX8+1
-#define IX_NPE_A_QMQ_ATM_TX10 IX_NPE_A_QMQ_ATM_TX9+1
-#define IX_NPE_A_QMQ_ATM_TX11 IX_NPE_A_QMQ_ATM_TX10+1
-#define IX_NPE_A_QMQ_ATM_TXID_MIN IX_NPE_A_QMQ_ATM_TX0
-#define IX_NPE_A_QMQ_ATM_TXID_MAX IX_NPE_A_QMQ_ATM_TX11
-#define IX_NPE_A_QMQ_ATM_RX_HI IX_QMGR_QUEUE_21
-#define IX_NPE_A_QMQ_ATM_RX_LO IX_QMGR_QUEUE_22
-#else
-#define IX_NPE_A_QMQ_ATM_TXID_MIN IX_NPE_A_QMQ_ATM_TX0
-#define IX_NPE_A_QMQ_ATM_TXID_MAX IX_NPE_A_QMQ_ATM_TX0
-#define IX_NPE_A_QMQ_ATM_RX_HI IX_QMGR_QUEUE_10
-#define IX_NPE_A_QMQ_ATM_RX_LO IX_QMGR_QUEUE_11
-#endif /* MPHY */
-
-/**
- * @def IX_NPE_A_QMQ_ATM_FREE_VC0
- *
- * @brief Hardware QMgr Queue ID for ATM Free VC Queue.
- *
- * There are 32 Hardware QMgr Queue ID; from IX_NPE_A_QMQ_ATM_FREE_VC1 to
- * IX_NPE_A_QMQ_ATM_FREE_VC30
- */
-#define IX_NPE_A_QMQ_ATM_FREE_VC0 IX_QMGR_QUEUE_32
-#define IX_NPE_A_QMQ_ATM_FREE_VC1 IX_NPE_A_QMQ_ATM_FREE_VC0+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC2 IX_NPE_A_QMQ_ATM_FREE_VC1+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC3 IX_NPE_A_QMQ_ATM_FREE_VC2+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC4 IX_NPE_A_QMQ_ATM_FREE_VC3+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC5 IX_NPE_A_QMQ_ATM_FREE_VC4+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC6 IX_NPE_A_QMQ_ATM_FREE_VC5+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC7 IX_NPE_A_QMQ_ATM_FREE_VC6+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC8 IX_NPE_A_QMQ_ATM_FREE_VC7+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC9 IX_NPE_A_QMQ_ATM_FREE_VC8+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC10 IX_NPE_A_QMQ_ATM_FREE_VC9+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC11 IX_NPE_A_QMQ_ATM_FREE_VC10+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC12 IX_NPE_A_QMQ_ATM_FREE_VC11+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC13 IX_NPE_A_QMQ_ATM_FREE_VC12+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC14 IX_NPE_A_QMQ_ATM_FREE_VC13+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC15 IX_NPE_A_QMQ_ATM_FREE_VC14+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC16 IX_NPE_A_QMQ_ATM_FREE_VC15+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC17 IX_NPE_A_QMQ_ATM_FREE_VC16+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC18 IX_NPE_A_QMQ_ATM_FREE_VC17+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC19 IX_NPE_A_QMQ_ATM_FREE_VC18+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC20 IX_NPE_A_QMQ_ATM_FREE_VC19+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC21 IX_NPE_A_QMQ_ATM_FREE_VC20+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC22 IX_NPE_A_QMQ_ATM_FREE_VC21+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC23 IX_NPE_A_QMQ_ATM_FREE_VC22+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC24 IX_NPE_A_QMQ_ATM_FREE_VC23+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC25 IX_NPE_A_QMQ_ATM_FREE_VC24+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC26 IX_NPE_A_QMQ_ATM_FREE_VC25+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC27 IX_NPE_A_QMQ_ATM_FREE_VC26+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC28 IX_NPE_A_QMQ_ATM_FREE_VC27+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC29 IX_NPE_A_QMQ_ATM_FREE_VC28+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC30 IX_NPE_A_QMQ_ATM_FREE_VC29+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC31 IX_NPE_A_QMQ_ATM_FREE_VC30+1
-
-/**
- * @def IX_NPE_A_QMQ_ATM_RXFREE_MIN
- *
- * @brief The minimum queue ID for FreeVC queue
- */
-#define IX_NPE_A_QMQ_ATM_RXFREE_MIN IX_NPE_A_QMQ_ATM_FREE_VC0
-
-/**
- * @def IX_NPE_A_QMQ_ATM_RXFREE_MAX
- *
- * @brief The maximum queue ID for FreeVC queue
- */
-#define IX_NPE_A_QMQ_ATM_RXFREE_MAX IX_NPE_A_QMQ_ATM_FREE_VC31
-
-/**
- * @def IX_NPE_A_QMQ_OAM_FREE_VC
- * @brief OAM Rx Free queue ID
- */
-#ifdef IX_NPE_MPHYMULTIPORT
-#define IX_NPE_A_QMQ_OAM_FREE_VC IX_QMGR_QUEUE_14
-#else
-#define IX_NPE_A_QMQ_OAM_FREE_VC IX_QMGR_QUEUE_3
-#endif /* MPHY */
-
-/****************************************************************************
- * Queue assignments for HSS
- ****************************************************************************/
-
-/**** HSS Port 0 ****/
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_CHL_RX_TRIG
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Channelized Receive trigger
- */
-#define IX_NPE_A_QMQ_HSS0_CHL_RX_TRIG IX_QMGR_QUEUE_12
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_RX
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_RX IX_QMGR_QUEUE_13
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_TX0
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 0
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_TX0 IX_QMGR_QUEUE_14
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_TX1
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 1
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_TX1 IX_QMGR_QUEUE_15
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_TX2
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 2
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_TX2 IX_QMGR_QUEUE_16
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_TX3
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 3
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_TX3 IX_QMGR_QUEUE_17
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE0
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 0
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE0 IX_QMGR_QUEUE_18
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE1
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 1
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE1 IX_QMGR_QUEUE_19
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE2
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 2
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE2 IX_QMGR_QUEUE_20
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE3
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 3
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE3 IX_QMGR_QUEUE_21
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_TX_DONE
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit Done queue
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_TX_DONE IX_QMGR_QUEUE_22
-
-/**** HSS Port 1 ****/
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_CHL_RX_TRIG
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Channelized Receive trigger
- */
-#define IX_NPE_A_QMQ_HSS1_CHL_RX_TRIG IX_QMGR_QUEUE_10
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_RX
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_RX IX_QMGR_QUEUE_0
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_TX0
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 0
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_TX0 IX_QMGR_QUEUE_5
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_TX1
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 1
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_TX1 IX_QMGR_QUEUE_6
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_TX2
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 2
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_TX2 IX_QMGR_QUEUE_7
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_TX3
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 3
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_TX3 IX_QMGR_QUEUE_8
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE0
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 0
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE0 IX_QMGR_QUEUE_1
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE1
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 1
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE1 IX_QMGR_QUEUE_2
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE2
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 2
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE2 IX_QMGR_QUEUE_3
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE3
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 3
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE3 IX_QMGR_QUEUE_4
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_TX_DONE
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit Done queue
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_TX_DONE IX_QMGR_QUEUE_9
-
-/*****************************************************************************************
- * Queue assignments for DMA
- *****************************************************************************************/
-
-#define IX_DMA_NPE_A_REQUEST_QID IX_QMGR_QUEUE_19 /**< Queue Id for NPE A DMA Request */
-#define IX_DMA_NPE_A_DONE_QID IX_QMGR_QUEUE_20 /**< Queue Id for NPE A DMA Done */
-#define IX_DMA_NPE_B_REQUEST_QID IX_QMGR_QUEUE_24 /**< Queue Id for NPE B DMA Request */
-#define IX_DMA_NPE_B_DONE_QID IX_QMGR_QUEUE_26 /**< Queue Id for NPE B DMA Done */
-#define IX_DMA_NPE_C_REQUEST_QID IX_QMGR_QUEUE_25 /**< Queue Id for NPE C DMA Request */
-#define IX_DMA_NPE_C_DONE_QID IX_QMGR_QUEUE_27 /**< Queue Id for NPE C DMA Done */
-
-
-/*****************************************************************************************
- * Queue assignments for Ethernet
- *
- * Note: Rx queue definitions, which include QoS traffic class definitions
- * are managed by EthDB and declared in IxEthDBQoS.h
- *****************************************************************************************/
-
-/**
-*
-* @def IX_ETH_ACC_RX_FRAME_ETH_Q
-*
-* @brief Eth0/Eth1 NPE Frame Receive Q.
-*
-* @note THIS IS NOT USED - the Rx queues are read from EthDB QoS configuration
-*
-*/
-#define IX_ETH_ACC_RX_FRAME_ETH_Q (IX_QMGR_QUEUE_4)
-
-/**
-*
-* @def IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q
-*
-* @brief Supply Rx Buffers Ethernet Q for NPEB - Eth 0 - Port 1
-*
-*/
-#define IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q (IX_QMGR_QUEUE_27)
-
-/**
-*
-* @def IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q
-*
-* @brief Supply Rx Buffers Ethernet Q for NPEC - Eth 1 - Port 2
-*
-*/
-#define IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q (IX_QMGR_QUEUE_28)
-
-/**
-*
-* @def IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q
-*
-* @brief Supply Rx Buffers Ethernet Q for NPEA - Eth 2 - Port 3
-*
-*/
-#define IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q (IX_QMGR_QUEUE_26)
-
-
-/**
-*
-* @def IX_ETH_ACC_TX_FRAME_ENET0_Q
-*
-* @brief Submit frame Q for NPEB Eth 0 - Port 1
-*
-*/
-#define IX_ETH_ACC_TX_FRAME_ENET0_Q (IX_QMGR_QUEUE_24)
-
-
-/**
-*
-* @def IX_ETH_ACC_TX_FRAME_ENET1_Q
-*
-* @brief Submit frame Q for NPEC Eth 1 - Port 2
-*
-*/
-#define IX_ETH_ACC_TX_FRAME_ENET1_Q (IX_QMGR_QUEUE_25)
-
-/**
-*
-* @def IX_ETH_ACC_TX_FRAME_ENET2_Q
-*
-* @brief Submit frame Q for NPEA Eth 2 - Port 3
-*
-*/
-#define IX_ETH_ACC_TX_FRAME_ENET2_Q (IX_QMGR_QUEUE_23)
-
-/**
-*
-* @def IX_ETH_ACC_TX_FRAME_DONE_ETH_Q
-*
-* @brief Transmit complete Q for NPE Eth 0/1, Port 1&2
-*
-*/
-#define IX_ETH_ACC_TX_FRAME_DONE_ETH_Q (IX_QMGR_QUEUE_31)
-
-/*****************************************************************************************
- * Queue assignments for Crypto
- *****************************************************************************************/
-
-/** Crypto Service Request Queue */
-#define IX_CRYPTO_ACC_CRYPTO_REQ_Q (IX_QMGR_QUEUE_29)
-
-/** Crypto Service Done Queue */
-#define IX_CRYPTO_ACC_CRYPTO_DONE_Q (IX_QMGR_QUEUE_30)
-
-/** Crypto Req Q CB tag */
-#define IX_CRYPTO_ACC_CRYPTO_REQ_Q_CB_TAG (0)
-
-/** Crypto Done Q CB tag */
-#define IX_CRYPTO_ACC_CRYPTO_DONE_Q_CB_TAG (1)
-
-/** WEP Service Request Queue */
-#define IX_CRYPTO_ACC_WEP_REQ_Q (IX_QMGR_QUEUE_21)
-
-/** WEP Service Done Queue */
-#define IX_CRYPTO_ACC_WEP_DONE_Q (IX_QMGR_QUEUE_22)
-
-/** WEP Req Q CB tag */
-#define IX_CRYPTO_ACC_WEP_REQ_Q_CB_TAG (2)
-
-/** WEP Done Q CB tag */
-#define IX_CRYPTO_ACC_WEP_DONE_Q_CB_TAG (3)
-
-/** Number of queues allocate to crypto hardware accelerator services */
-#define IX_CRYPTO_ACC_NUM_OF_CRYPTO_Q (2)
-
-/** Number of queues allocate to WEP NPE services */
-#define IX_CRYPTO_ACC_NUM_OF_WEP_NPE_Q (2)
-
-/** Number of queues allocate to CryptoAcc component */
-#define IX_CRYPTO_ACC_NUM_OF_Q (IX_CRYPTO_ACC_NUM_OF_CRYPTO_Q + IX_CRYPTO_ACC_NUM_OF_WEP_NPE_Q)
-
-#endif /* IxQueueAssignments_H */
+++ /dev/null
-/**
- * @file IxSspAcc.h
- *
- * @brief Header file for the IXP400 SSP Serial Port Access (IxSspAcc)
- *
- * @version $Revision: 0.1 $
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxSspAcc IXP400 SSP Serial Port Access (IxSspAcc) API
- *
- * @brief IXP400 SSP Serial Port Access Public API
- *
- * @{
- */
-#ifndef IXSSPACC_H
-#define IXSSPACC_H
-
-#ifdef __ixp46X
-
-#include "IxOsal.h"
-
-/*
- * Section for enum
- */
-/**
- * @ingroup IxSspAcc
- *
- * @enum IxSspAccDataSize
- *
- * @brief The data sizes in bits that are supported by the protocol
- */
-typedef enum
-{
- DATA_SIZE_TOO_SMALL = 0x2,
- DATA_SIZE_4 = 0x3,
- DATA_SIZE_5,
- DATA_SIZE_6,
- DATA_SIZE_7,
- DATA_SIZE_8,
- DATA_SIZE_9,
- DATA_SIZE_10,
- DATA_SIZE_11,
- DATA_SIZE_12,
- DATA_SIZE_13,
- DATA_SIZE_14,
- DATA_SIZE_15,
- DATA_SIZE_16,
- DATA_SIZE_TOO_BIG
-} IxSspAccDataSize;
-
-/**
- * @ingroup IxSspAcc
- *
- * @enum IxSspAccPortStatus
- *
- * @brief The status of the SSP port to be set to enable/disable
- */
-typedef enum
-{
- SSP_PORT_DISABLE = 0x0,
- SSP_PORT_ENABLE,
- INVALID_SSP_PORT_STATUS
-} IxSspAccPortStatus;
-
-/**
- * @ingroup IxSspAcc
- *
- * @enum IxSspAccFrameFormat
- *
- * @brief The frame format that is to be used - SPI, SSP, or Microwire
- */
-typedef enum
-{
- SPI_FORMAT = 0x0,
- SSP_FORMAT,
- MICROWIRE_FORMAT,
- INVALID_FORMAT
-} IxSspAccFrameFormat;
-
-/**
- * @ingroup IxSspAcc
- *
- * @enum IxSspAccClkSource
- *
- * @brief The source to produce the SSP serial clock
- */
-typedef enum
-{
- ON_CHIP_CLK = 0x0,
- EXTERNAL_CLK,
- INVALID_CLK_SOURCE
-} IxSspAccClkSource;
-
-/**
- * @ingroup IxSspAcc
- *
- * @enum IxSspAccSpiSclkPhase
- *
- * @brief The SPI SCLK Phase:
- * 0 - SCLK is inactive one cycle at the start of a frame and 1/2 cycle at the
- * end of a frame.
- * 1 - SCLK is inactive 1/2 cycle at the start of a frame and one cycle at the
- * end of a frame.
- */
-typedef enum
-{
- START_ONE_END_HALF = 0x0,
- START_HALF_END_ONE,
- INVALID_SPI_PHASE
-} IxSspAccSpiSclkPhase;
-
-/**
- * @ingroup IxSspAcc
- *
- * @enum IxSspAccSpiSclkPolarity
- *
- * @brief The SPI SCLK Polarity can be set to either low or high.
- */
-typedef enum
-{
- SPI_POLARITY_LOW = 0x0,
- SPI_POLARITY_HIGH,
- INVALID_SPI_POLARITY
-} IxSspAccSpiSclkPolarity;
-
-/**
- * @ingroup IxSspAcc
- *
- * @enum IxSspAccMicrowireCtlWord
- *
- * @brief The Microwire control word can be either 8 or 16 bit.
- */
-typedef enum
-{
- MICROWIRE_8_BIT = 0x0,
- MICROWIRE_16_BIT,
- INVALID_MICROWIRE_CTL_WORD
-} IxSspAccMicrowireCtlWord;
-
-/**
- * @ingroup IxSspAcc
- *
- * @enum IxSspAccFifoThreshold
- *
- * @brief The threshold in frames (each frame is defined by IxSspAccDataSize)
- * that can be set for the FIFO to trigger a threshold exceed when
- * checking with the ExceedThresholdCheck functions or an interrupt
- * when it is enabled.
- */
-typedef enum
-{
- FIFO_TSHLD_1 = 0x0,
- FIFO_TSHLD_2,
- FIFO_TSHLD_3,
- FIFO_TSHLD_4,
- FIFO_TSHLD_5,
- FIFO_TSHLD_6,
- FIFO_TSHLD_7,
- FIFO_TSHLD_8,
- FIFO_TSHLD_9,
- FIFO_TSHLD_10,
- FIFO_TSHLD_11,
- FIFO_TSHLD_12,
- FIFO_TSHLD_13,
- FIFO_TSHLD_14,
- FIFO_TSHLD_15,
- FIFO_TSHLD_16,
- INVALID_FIFO_TSHLD
-} IxSspAccFifoThreshold;
-
-/**
- * @ingroup IxSspAcc
- *
- * @enum IX_SSP_STATUS
- *
- * @brief The statuses that can be returned in a SSP Serial Port Access
- */
-typedef enum
-{
- IX_SSP_SUCCESS = IX_SUCCESS, /**< Success status */
- IX_SSP_FAIL, /**< Fail status */
- IX_SSP_RX_FIFO_OVERRUN_HANDLER_MISSING, /**<
- Rx FIFO Overrun handler is NULL. */
- IX_SSP_RX_FIFO_HANDLER_MISSING, /**<
- Rx FIFO threshold hit or above handler is NULL
- */
- IX_SSP_TX_FIFO_HANDLER_MISSING, /**<
- Tx FIFO threshold hit or below handler is NULL
- */
- IX_SSP_FIFO_NOT_EMPTY_FOR_SETTING_CTL_CMD, /**<
- Tx FIFO not empty and therefore microwire
- control command size setting is not allowed. */
- IX_SSP_INVALID_FRAME_FORMAT_ENUM_VALUE, /**<
- frame format selected is invalid. */
- IX_SSP_INVALID_DATA_SIZE_ENUM_VALUE, /**<
- data size selected is invalid. */
- IX_SSP_INVALID_CLOCK_SOURCE_ENUM_VALUE, /**<
- source clock selected is invalid. */
- IX_SSP_INVALID_TX_FIFO_THRESHOLD_ENUM_VALUE, /**<
- Tx FIFO threshold selected is invalid. */
- IX_SSP_INVALID_RX_FIFO_THRESHOLD_ENUM_VALUE, /**<
- Rx FIFO threshold selected is invalid. */
- IX_SSP_INVALID_SPI_PHASE_ENUM_VALUE, /**<
- SPI phase selected is invalid. */
- IX_SSP_INVALID_SPI_POLARITY_ENUM_VALUE, /**<
- SPI polarity selected is invalid. */
- IX_SSP_INVALID_MICROWIRE_CTL_CMD_ENUM_VALUE, /**<
- Microwire control command selected is invalid
- */
- IX_SSP_INT_UNBIND_FAIL, /**< Interrupt unbind fail to unbind SSP
- interrupt */
- IX_SSP_INT_BIND_FAIL, /**< Interrupt bind fail during init */
- IX_SSP_RX_FIFO_NOT_EMPTY, /**<
- Rx FIFO not empty while trying to change data
- size. */
- IX_SSP_TX_FIFO_NOT_EMPTY, /**<
- Rx FIFO not empty while trying to change data
- size or microwire control command size. */
- IX_SSP_POLL_MODE_BLOCKING, /**<
- poll mode selected blocks interrupt mode from
- being selected. */
- IX_SSP_TX_FIFO_HIT_BELOW_THRESHOLD, /**<
- Tx FIFO level hit or below threshold. */
- IX_SSP_TX_FIFO_EXCEED_THRESHOLD, /**<
- Tx FIFO level exceeded threshold. */
- IX_SSP_RX_FIFO_HIT_ABOVE_THRESHOLD, /**<
- Rx FIFO level hit or exceeded threshold. */
- IX_SSP_RX_FIFO_BELOW_THRESHOLD, /**<
- Rx FIFO level below threshold. */
- IX_SSP_BUSY, /**< SSP is busy. */
- IX_SSP_IDLE, /**< SSP is idle. */
- IX_SSP_OVERRUN_OCCURRED, /**<
- SSP has experienced an overrun. */
- IX_SSP_NO_OVERRUN, /**<
- SSP did not experience an overrun. */
- IX_SSP_NOT_SUPORTED, /**< hardware does not support SSP */
- IX_SSP_NOT_INIT, /**< SSP Access not intialized */
- IX_SSP_NULL_POINTER /**< parameter passed in is NULL */
-} IX_SSP_STATUS;
-
-/**
- * @ingroup IxSspAcc
- *
- * @brief SSP Rx FIFO Overrun handler
- *
- * This function is called for the client to handle Rx FIFO Overrun that occurs
- * in the SSP hardware
- */
-typedef void (*RxFIFOOverrunHandler)(void);
-
-/**
- * @ingroup IxSspAcc
- *
- * @brief SSP Rx FIFO Threshold hit or above handler
- *
- * This function is called for the client to handle Rx FIFO threshold hit or
- * or above that occurs in the SSP hardware
- */
-typedef void (*RxFIFOThresholdHandler)(void);
-
-/**
- * @ingroup IxSspAcc
- *
- * @brief SSP Tx FIFO Threshold hit or below handler
- *
- * This function is called for the client to handle Tx FIFO threshold hit or
- * or below that occurs in the SSP hardware
- */
-typedef void (*TxFIFOThresholdHandler)(void);
-
-
-/*
- * Section for struct
- */
-/**
- * @ingroup IxSspAcc
- *
- * @brief contains all the variables required to initialize the SSP serial port
- * hardware.
- *
- * Structure to be filled and used for calling initialization
- */
-typedef struct
-{
- IxSspAccFrameFormat FrameFormatSelected;/**<Select between SPI, SSP and
- Microwire. */
- IxSspAccDataSize DataSizeSelected; /**<Select between 4 and 16. */
- IxSspAccClkSource ClkSourceSelected; /**<Select clock source to be
- on-chip or external. */
- IxSspAccFifoThreshold TxFIFOThresholdSelected;
- /**<Select Tx FIFO threshold
- between 1 to 16. */
- IxSspAccFifoThreshold RxFIFOThresholdSelected;
- /**<Select Rx FIFO threshold
- between 1 to 16. */
- BOOL RxFIFOIntrEnable; /**<Enable/disable Rx FIFO
- threshold interrupt. Disabling
- this interrupt will require
- the use of the polling function
- RxFIFOExceedThresholdCheck. */
- BOOL TxFIFOIntrEnable; /**<Enable/disable Tx FIFO
- threshold interrupt. Disabling
- this interrupt will require
- the use of the polling function
- TxFIFOExceedThresholdCheck. */
- RxFIFOThresholdHandler RxFIFOThsldHdlr; /**<Pointer to function to handle
- a Rx FIFO interrupt. */
- TxFIFOThresholdHandler TxFIFOThsldHdlr; /**<Pointer to function to handle
- a Tx FIFO interrupt. */
- RxFIFOOverrunHandler RxFIFOOverrunHdlr; /**<Pointer to function to handle
- a Rx FIFO overrun interrupt. */
- BOOL LoopbackEnable; /**<Select operation mode to be
- normal or loopback mode. */
- IxSspAccSpiSclkPhase SpiSclkPhaseSelected;
- /**<Select SPI SCLK phase to start
- with one inactive cycle and end
- with 1/2 inactive cycle or
- start with 1/2 inactive cycle
- and end with one inactive
- cycle. (Only used in
- SPI format). */
- IxSspAccSpiSclkPolarity SpiSclkPolaritySelected;
- /**<Select SPI SCLK idle state
- to be low or high. (Only used in
- SPI format). */
- IxSspAccMicrowireCtlWord MicrowireCtlWordSelected;
- /**<Select Microwire control
- format to be 8 or 16-bit. (Only
- used in Microwire format). */
- UINT8 SerialClkRateSelected; /**<Select between 0 (1.8432Mbps)
- and 255 (7.2Kbps). The
- formula used is Bit rate =
- 3.6864x10^6 /
- (2 x (SerialClkRateSelect + 1))
- */
-} IxSspInitVars;
-
-/**
- * @ingroup IxSspAcc
- *
- * @brief contains counters of the SSP statistics
- *
- * Structure contains all values of counters and associated overflows.
- */
-typedef struct
-{
- UINT32 ixSspRcvCounter; /**<Total frames received. */
- UINT32 ixSspXmitCounter; /**<Total frames transmitted. */
- UINT32 ixSspOverflowCounter;/**<Total occurrences of overflow. */
-} IxSspAccStatsCounters;
-
-
-/*
- * Section for prototypes interface functions
- */
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccInit (
- IxSspInitVars *initVarsSelected);
- *
- * @brief Initializes the SSP Access module.
- *
- * @param "IxSspAccInitVars [in] *initVarsSelected" - struct containing required
- * variables for initialization
- *
- * Global Data :
- * - None.
- *
- * This API will initialize the SSP Serial Port hardware to the user specified
- * configuration. Then it will enable the SSP Serial Port.
- * *NOTE*: Once interrupt or polling mode is selected, the mode cannot be
- * changed via the interrupt enable/disable function but the init needs to be
- * called again to change it.
- *
- * @return
- * - IX_SSP_SUCCESS - Successfully initialize and enable the SSP
- * serial port.
- * - IX_SSP_RX_FIFO_HANDLER_MISSING - interrupt mode is selected but RX FIFO
- * handler pointer is NULL
- * - IX_SSP_TX_FIFO_HANDLER_MISSING - interrupt mode is selected but TX FIFO
- * handler pointer is NULL
- * - IX_SSP_RX_FIFO_OVERRUN_HANDLER_MISSING - interrupt mode is selected but
- * RX FIFO Overrun handler pointer is NULL
- * - IX_SSP_RX_FIFO_NOT_EMPTY - Rx FIFO not empty, data size change is not
- * allowed.
- * - IX_SSP_TX_FIFO_NOT_EMPTY - Tx FIFO not empty, data size change is not
- * allowed.
- * - IX_SSP_INVALID_FRAME_FORMAT_ENUM_VALUE - frame format selected is invalid
- * - IX_SSP_INVALID_DATA_SIZE_ENUM_VALUE - data size selected is invalid
- * - IX_SSP_INVALID_CLOCK_SOURCE_ENUM_VALUE - clock source selected is invalid
- * - IX_SSP_INVALID_TX_FIFO_THRESHOLD_ENUM_VALUE - Tx FIFO threshold level
- * selected is invalid
- * - IX_SSP_INVALID_RX_FIFO_THRESHOLD_ENUM_VALUE - Rx FIFO threshold level
- * selected is invalid
- * - IX_SSP_INVALID_SPI_PHASE_ENUM_VALUE - SPI phase selected is invalid
- * - IX_SSP_INVALID_SPI_POLARITY_ENUM_VALUE - SPI polarity selected is invalid
- * - IX_SSP_INVALID_MICROWIRE_CTL_CMD_ENUM_VALUE - microwire control command
- * size is invalid
- * - IX_SSP_INT_UNBIND_FAIL - interrupt handler failed to unbind SSP interrupt
- * - IX_SSP_INT_BIND_FAIL - interrupt handler failed to bind to SSP interrupt
- * hardware trigger
- * - IX_SSP_NOT_SUPORTED - hardware does not support SSP
- * - IX_SSP_NULL_POINTER - parameter passed in is NULL
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccInit (IxSspInitVars *initVarsSelected);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccUninit (
- void)
- *
- * @brief Un-initializes the SSP Serial Port Access component
- *
- * @param - None
- *
- * Global Data :
- * - None.
- *
- * This API will disable the SSP Serial Port hardware. The client can call the
- * init function again if they wish to enable the SSP.
- *
- * @return
- * - IX_SSP_SUCCESS - successfully uninit SSP component
- * - IX_SSP_INT_UNBIND_FAIL - interrupt handler failed to unbind SSP interrupt
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccUninit (void);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccFIFODataSubmit (
- UINT16 *data,
- UINT32 amtOfData)
- *
- * @brief Inserts data into the SSP Serial Port's FIFO
- *
- * @param "UINT16 [in] *data" - pointer to the location to transmit the data
- * from
- * "UINT32 [in] amtOfData" - number of data to be transmitted.
- *
- * Global Data :
- * - None.
- *
- * This API will insert the amount of data specified by "amtOfData" from buffer
- * pointed to by "data" into the FIFO to be transmitted by the hardware.
- *
- * @return
- * - IX_SSP_SUCCESS - Data inserted successfully into FIFO
- * - IX_SSP_FAIL - FIFO insufficient space
- * - IX_SSP_NULL_POINTER - data pointer passed by client is NULL
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccFIFODataSubmit (
- UINT16* data,
- UINT32 amtOfData);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccFIFODataReceive (
- UINT16 *data,
- UINT32 amtOfData)
- *
- * @brief Extract data from the SSP Serial Port's FIFO
- *
- * @param "UINT16 [in] *data" - pointer to the location to receive the data into
- * "UINT32 [in] amtOfData" - number of data to be received.
- *
- * Global Data :
- * - None.
- *
- * This API will extract the amount of data specified by "amtOfData" from the
- * FIFO already received by the hardware into the buffer pointed to by "data".
- *
- * @return
- * - IX_SSP_SUCCESS - Data extracted successfully from FIFO
- * - IX_SSP_FAIL - FIFO has no data
- * - IX_SSP_NULL_POINTER - data pointer passed by client is NULL
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccFIFODataReceive (
- UINT16* data,
- UINT32 amtOfData);
-
-
-/**
- * Polling Functions
- */
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccTxFIFOHitOrBelowThresholdCheck (
- void)
- *
- * @brief Check if the Tx FIFO threshold has been hit or fallen below.
- *
- * @param - None
- *
- * Global Data :
- * - None.
- *
- * This API will return whether the Tx FIFO threshold has been exceeded or not
- *
- * @return
- * - IX_SSP_TX_FIFO_HIT_BELOW_THRESHOLD - Tx FIFO level hit or below threshold .
- * - IX_SSP_TX_FIFO_EXCEED_THRESHOLD - Tx FIFO level exceeded threshold.
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccTxFIFOHitOrBelowThresholdCheck (
- void);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccRxFIFOHitOrAboveThresholdCheck (
- void)
- *
- * @brief Check if the Rx FIFO threshold has been hit or exceeded.
- *
- * @param - None
- *
- * Global Data :
- * - None.
- *
- * This API will return whether the Rx FIFO level is below threshold or not
- *
- * @return
- * - IX_SSP_RX_FIFO_HIT_ABOVE_THRESHOLD - Rx FIFO level hit or exceeded threshold
- * - IX_SSP_RX_FIFO_BELOW_THRESHOLD - Rx FIFO level below threshold
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccRxFIFOHitOrAboveThresholdCheck (
- void);
-
-
-/**
- * Configuration functions
- *
- * NOTE: These configurations are not required to be called once init is called
- * unless configurations need to be changed on the fly.
- */
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccSSPPortStatusSet (
- IxSspAccPortStatus portStatusSelected)
- *
- * @brief Enables/disables the SSP Serial Port hardware.
- *
- * @param "IxSspAccPortStatus [in] portStatusSelected" - Set the SSP port to
- * enable or disable
- *
- * Global Data :
- * - None.
- *
- * This API will enable/disable the SSP Serial Port hardware.
- * NOTE: This function is called by init to enable the SSP after setting up the
- * configurations and by uninit to disable the SSP.
- *
- * @return
- * - IX_SSP_SUCCESS - Port status set with valid enum value
- * - IX_SSP_FAIL - invalid enum value
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccSSPPortStatusSet (
- IxSspAccPortStatus portStatusSelected);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccFrameFormatSelect (
- IxSspAccFrameFormat frameFormatSelected)
- *
- * @brief Sets the frame format for the SSP Serial Port hardware
- *
- * @param "IxSspAccFrameFormat [in] frameFormatSelected" - The frame format of
- * SPI, SSP or Microwire can be selected as the format
- *
- * Global Data :
- * - None.
- *
- * This API will set the format for the transfers via user input.
- * *NOTE*: The SSP hardware will be disabled to clear the FIFOs. Then its
- * previous state (enabled/disabled) restored after changing the format.
- *
- * @return
- * - IX_SSP_SUCCESS - frame format set with valid enum value
- * - IX_SSP_INVALID_FRAME_FORMAT_ENUM_VALUE - invalid frame format value
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccFrameFormatSelect (
- IxSspAccFrameFormat frameFormatSelected);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccDataSizeSelect (
- IxSspAccDataSize dataSizeSelected)
- *
- * @brief Sets the data size for transfers
- *
- * @param "IxSspAccDataSize [in] dataSizeSelected" - The data size between 4
- * and 16 that can be selected for data transfers
- *
- * Global Data :
- * - None.
- *
- * This API will set the data size for the transfers via user input. It will
- * disallow the change of the data size if either of the Rx/Tx FIFO is not
- * empty to prevent data loss.
- * *NOTE*: The SSP port will be disabled if the FIFOs are found to be empty and
- * if between the check and disabling of the SSP (which clears the
- * FIFOs) data is received into the FIFO, it might be lost.
- * *NOTE*: The FIFOs can be cleared by disabling the SSP Port if necessary to
- * force the data size change.
- *
- * @return
- * - IX_SSP_SUCCESS - data size set with valid enum value
- * - IX_SSP_RX_FIFO_NOT_EMPTY - Rx FIFO not empty, data size change is not
- * allowed.
- * - IX_SSP_TX_FIFO_NOT_EMPTY - Tx FIFO not empty, data size change is not
- * allowed.
- * - IX_SSP_INVALID_DATA_SIZE_ENUM_VALUE - invalid enum value
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccDataSizeSelect (
- IxSspAccDataSize dataSizeSelected);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccClockSourceSelect(
- IxSspAccClkSource clkSourceSelected)
- *
- * @brief Sets the clock source of the SSP Serial Port hardware
- *
- * @param "IxSspAccClkSource [in] clkSourceSelected" - The clock source from
- * either external source on on-chip can be selected as the source
- *
- * Global Data :
- * - None.
- *
- * This API will set the clock source for the transfers via user input.
- *
- * @return
- * - IX_SSP_SUCCESS - clock source set with valid enum value
- * - IX_SSP_INVALID_CLOCK_SOURCE_ENUM_VALUE - invalid enum value
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccClockSourceSelect (
- IxSspAccClkSource clkSourceSelected);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccSerialClockRateConfigure (
- UINT8 serialClockRateSelected)
- *
- * @brief Sets the on-chip Serial Clock Rate of the SSP Serial Port hardware.
- *
- * @param "UINT8 [in] serialClockRateSelected" - The serial clock rate that can
- * be set is between 7.2Kbps and 1.8432Mbps. The formula used is
- * Bit rate = 3.6864x10^6 / (2 x (SerialClockRateSelected + 1))
- *
- * Global Data :
- * - None.
- *
- * This API will set the serial clock rate for the transfers via user input.
- *
- * @return
- * - IX_SSP_SUCCESS - Serial clock rate configured successfully
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccSerialClockRateConfigure (
- UINT8 serialClockRateSelected);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccRxFIFOIntEnable (
- RxFIFOThresholdHandler rxFIFOIntrHandler)
- *
- * @brief Enables service request interrupt whenever the Rx FIFO hits its
- * threshold
- *
- * @param "void [in] *rxFIFOIntrHandler(UINT32)" - function pointer to the
- * interrupt handler for the Rx FIFO exceeded.
- *
- * Global Data :
- * - None.
- *
- * This API will enable the service request interrupt for the Rx FIFO
- *
- * @return
- * - IX_SSP_SUCCESS - Rx FIFO level interrupt enabled successfully
- * - IX_SSP_RX_FIFO_HANDLER_MISSING - missing handler for Rx FIFO level interrupt
- * - IX_SSP_POLL_MODE_BLOCKING - poll mode is selected at init, interrupt not
- * allowed to be enabled. Use init to enable interrupt mode.
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccRxFIFOIntEnable (
- RxFIFOThresholdHandler rxFIFOIntrHandler);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccRxFIFOIntDisable (
- void)
- *
- * @brief Disables service request interrupt of the Rx FIFO.
- *
- * @param - None
- *
- * Global Data :
- * - None.
- *
- * This API will disable the service request interrupt of the Rx FIFO.
- *
- * @return
- * - IX_SSP_SUCCESS - Rx FIFO Interrupt disabled successfully
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccRxFIFOIntDisable (
- void);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccTxFIFOIntEnable (
- TxFIFOThresholdHandler txFIFOIntrHandler)
- *
- * @brief Enables service request interrupt of the Tx FIFO.
- *
- * @param "void [in] *txFIFOIntrHandler(UINT32)" - function pointer to the
- * interrupt handler for the Tx FIFO exceeded.
- *
- * Global Data :
- * - None.
- *
- * This API will enable the service request interrupt of the Tx FIFO.
- *
- * @return
- * - IX_SSP_SUCCESS - Tx FIFO level interrupt enabled successfully
- * - IX_SSP_TX_FIFO_HANDLER_MISSING - missing handler for Tx FIFO level interrupt
- * - IX_SSP_POLL_MODE_BLOCKING - poll mode is selected at init, interrupt not
- * allowed to be enabled. Use init to enable interrupt mode.
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccTxFIFOIntEnable (
- TxFIFOThresholdHandler txFIFOIntrHandler);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccTxFIFOIntDisable (
- void)
- *
- * @brief Disables service request interrupt of the Tx FIFO
- *
- * @param - None
- *
- * Global Data :
- * - None.
- *
- * This API will disable the service request interrupt of the Tx FIFO
- *
- * @return
- * - IX_SSP_SUCCESS - Tx FIFO Interrupt disabled successfuly.
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccTxFIFOIntDisable (
- void);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccLoopbackEnable (
- BOOL loopbackEnable)
- *
- * @brief Enables/disables the loopback mode
- *
- * @param "BOOL [in] loopbackEnable" - true to enable and false to disable.
- *
- * Global Data :
- * - None.
- *
- * This API will set the mode of operation to either loopback or normal mode
- * according to the user input.
- *
- * @return
- * - IX_SSP_SUCCESS - Loopback enabled successfully
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccLoopbackEnable (
- BOOL loopbackEnable);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccSpiSclkPolaritySet (
- IxSspAccSpiSclkPolarity spiSclkPolaritySelected)
- *
- * @brief Sets the SPI SCLK Polarity to Low or High
- *
- * @param - "IxSspAccSpiSclkPolarity [in] spiSclkPolaritySelected" - SPI SCLK
- * polarity that can be selected to either high or low
- *
- * Global Data :
- * - None.
- *
- * This API is only used for the SPI frame format and will set the SPI SCLK polarity
- * to either low or high
- *
- * @return
- * - IX_SSP_SUCCESS - SPI Sclk polarity set with valid enum value
- * - IX_SSP_INVALID_SPI_POLARITY_ENUM_VALUE - invalid SPI polarity value
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccSpiSclkPolaritySet (
- IxSspAccSpiSclkPolarity spiSclkPolaritySelected);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccSpiSclkPhaseSet (
- IxSspAccSpiSclkPhase spiSclkPhaseSelected)
- *
- * @brief Sets the SPI SCLK Phase
- *
- * @param "IxSspAccSpiSclkPhase [in] spiSclkPhaseSelected" - Phase of either
- * the SCLK is inactive one cycle at the start of a frame and 1/2
- * cycle at the end of a frame, OR
- * the SCLK is inactive 1/2 cycle at the start of a frame and one
- * cycle at the end of a frame.
- *
- * Global Data :
- * - IX_SSP_SUCCESS - SPI Sclk phase set with valid enum value
- * - IX_SSP_INVALID_SPI_PHASE_ENUM_VALUE - invalid SPI phase value
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * This API is only used for the SPI frame format and will set the SPI SCLK
- * phase according to user input.
- *
- * @return
- * - None
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccSpiSclkPhaseSet (
- IxSspAccSpiSclkPhase spiSclkPhaseSelected);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccMicrowireControlWordSet (
- IxSspAccMicrowireCtlWord microwireCtlWordSelected)
- *
- * @brief Sets the Microwire control word to 8 or 16 bit format
- *
- * @param "IxSspAccMicrowireCtlWord [in] microwireCtlWordSelected" - Microwire
- * control word format can be either 8 or 16 bit format
- *
- * Global Data :
- * - None.
- *
- * This API is only used for the Microwire frame format and will set the
- * control word to 8 or 16 bit format
- *
- * @return
- * - IX_SSP_SUCCESS - Microwire Control Word set with valid enum value
- * - IX_SSP_TX_FIFO_NOT_EMPTY - Tx FIFO not empty, data size change is not
- * allowed.
- * - IX_SSP_INVALID_MICROWIRE_CTL_CMD_ENUM_VALUE - invalid enum value
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccMicrowireControlWordSet (
- IxSspAccMicrowireCtlWord microwireCtlWordSelected);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccTxFIFOThresholdSet (
- IxSspAccFifoThreshold txFIFOThresholdSelected)
- *
- * @brief Sets the Tx FIFO Threshold.
- *
- * @param "IxSspAccFifoThreshold [in] txFIFOThresholdSelected" - Threshold that
- * is set for a Tx FIFO service request to be triggered
- *
- * Global Data :
- * - None.
- *
- * This API will set the threshold for a Tx FIFO threshold to be triggered
- *
- * @return
- * - IX_SSP_SUCCESS - Tx FIFO Threshold set with valid enum value
- * - IX_SSP_INVALID_TX_FIFO_THRESHOLD_ENUM_VALUE - invalid enum value
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccTxFIFOThresholdSet (
- IxSspAccFifoThreshold txFIFOThresholdSelected);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccRxFIFOThresholdSet (
- IxSspAccFifoThreshold rxFIFOThresholdSelected)
- *
- * @brief Sets the Rx FIFO Threshold.
- *
- * @param "IxSspAccFifoThreshold [in] rxFIFOThresholdSelected" - Threshold that
- * is set for a Tx FIFO service request to be triggered
- *
- * Global Data :
- * - None.
- *
- * This API will will set the threshold for a Rx FIFO threshold to be triggered
- *
- * @return
- * - IX_SSP_SUCCESS - Rx FIFO Threshold set with valid enum value
- * - IX_SSP_INVALID_RX_FIFO_THRESHOLD_ENUM_VALUE - invalid enum value
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccRxFIFOThresholdSet (
- IxSspAccFifoThreshold rxFIFOThresholdSelected);
-
-
-/**
- * Debug functions
- */
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccStatsGet (
- IxSspAccStatsCounters *sspStats)
- *
- * @brief Returns the SSP Statistics through the pointer passed in
- *
- * @param "IxSspAccStatsCounters [in] *sspStats" - SSP statistics counter will
- * be read and written to the location pointed by this pointer.
- *
- * Global Data :
- * - None.
- *
- * This API will return the statistics counters of the SSP transfers.
- *
- * @return
- * - IX_SSP_SUCCESS - Stats obtained into the pointer provided successfully
- * - IX_SSP_FAIL - client provided pointer is NULL
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccStatsGet (
- IxSspAccStatsCounters *sspStats);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccStatsReset (
- void)
- *
- * @brief Resets the SSP Statistics
- *
- * @param - None
- *
- * Global Data :
- * - None.
- *
- * This API will reset the SSP statistics counters.
- *
- * @return
- * - None
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC void
-ixSspAccStatsReset (
- void);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccShow (
- void)
- *
- * @brief Display SSP status registers and statistics counters.
- *
- * @param - None
- *
- * Global Data :
- * - None.
- *
- * This API will display the status registers of the SSP and the statistics
- * counters.
- *
- * @return
- * - IX_SSP_SUCCESS - SSP show called successfully.
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccShow (
- void);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccSSPBusyCheck (
- void)
- *
- * @brief Determine the state of the SSP serial port hardware.
- *
- * @param - None
- *
- * Global Data :
- * - None.
- *
- * This API will return the state of the SSP serial port hardware - busy or
- * idle
- *
- * @return
- * - IX_SSP_BUSY - SSP is busy
- * - IX_SSP_IDLE - SSP is idle.
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccSSPBusyCheck (
- void);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccTxFIFOLevelGet (
- void)
- *
- * @brief Obtain the Tx FIFO's level
- *
- * @param - None
- *
- * Global Data :
- * - None.
- *
- * This API will return the level of the Tx FIFO
- *
- * @return
- * - 0..16; 0 can also mean SSP not initialized and will need to be init.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC UINT8
-ixSspAccTxFIFOLevelGet (
- void);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccRxFIFOLevelGet (
- void)
- *
- * @brief Obtain the Rx FIFO's level
- *
- * @param - None
- *
- * Global Data :
- * - None.
- *
- * This API will return the level of the Rx FIFO
- *
- * @return
- * - 0..16; 0 can also mean SSP not initialized and will need to be init.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC UINT8
-ixSspAccRxFIFOLevelGet (
- void);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccRxFIFOOverrunCheck (
- void)
- *
- * @brief Check if the Rx FIFO has overrun its FIFOs
- *
- * @param - None
- *
- * Global Data :
- * - None.
- *
- * This API will return whether the Rx FIFO has overrun its 16 FIFOs
- *
- * @return
- * - IX_SSP_OVERRUN_OCCURRED - Rx FIFO overrun occurred
- * - IX_SSP_NO_OVERRUN - Rx FIFO did not overrun
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccRxFIFOOverrunCheck (
- void);
-
-#endif /* __ixp46X */
-#endif /* IXSSPACC_H */
+++ /dev/null
-/**
- * @file IxTimeSyncAcc.h
- *
- * @author Intel Corporation
- * @date 07 May 2004
- *
- * @brief Header file for IXP400 Access Layer to IEEE 1588(TM) Precision
- * Clock Synchronisation Protocol Hardware Assist
- *
- * @version 1
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxTimeSyncAcc IXP400 Time Sync Access Component API
- *
- * @brief Public API for IxTimeSyncAcc
- *
- * @{
- */
-#ifndef IXTIMESYNCACC_H
-#define IXTIMESYNCACC_H
-
-#ifdef __ixp46X
-
-#include "IxOsal.h"
-
-/**
- * Section for enum
- */
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @enum IxTimeSyncAccStatus
- *
- * @brief The status as returned from the API
- */
-typedef enum /**< IxTimeSyncAccStatus */
-{
- IX_TIMESYNCACC_SUCCESS = IX_SUCCESS, /**< Requested operation successful */
- IX_TIMESYNCACC_INVALIDPARAM, /**< An invalid parameter was passed */
- IX_TIMESYNCACC_NOTIMESTAMP, /**< While polling no time stamp available */
- IX_TIMESYNCACC_INTERRUPTMODEINUSE, /**< Polling not allowed while operating in interrupt mode */
- IX_TIMESYNCACC_FAILED /**< Internal error occurred */
-}IxTimeSyncAccStatus;
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @enum IxTimeSyncAccAuxMode
- *
- * @brief Master or Slave Auxiliary Time Stamp (Snap Shot)
- */
-typedef enum /**< IxTimeSyncAccAuxMode */
-{
- IX_TIMESYNCACC_AUXMODE_MASTER, /**< Auxiliary Master Mode */
- IX_TIMESYNCACC_AUXMODE_SLAVE, /**< Auxiliary Slave Mode */
- IX_TIMESYNCACC_AUXMODE_INVALID /**< Invalid Auxiliary Mode */
-}IxTimeSyncAccAuxMode;
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @enum IxTimeSyncAcc1588PTPPort
- *
- * @brief IEEE 1588 PTP Communication Port(Channel)
- */
-typedef enum /**< IxTimeSyncAcc1588PTPPort */
-{
- IX_TIMESYNCACC_NPE_A_1588PTP_PORT, /**< PTP Communication Port on NPE-A */
- IX_TIMESYNCACC_NPE_B_1588PTP_PORT, /**< PTP Communication Port on NPE-B */
- IX_TIMESYNCACC_NPE_C_1588PTP_PORT, /**< PTP Communication Port on NPE-C */
- IX_TIMESYNCACC_NPE_1588PORT_INVALID /**< Invalid PTP Communication Port */
-} IxTimeSyncAcc1588PTPPort;
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @enum IxTimeSyncAcc1588PTPPortMode
- *
- * @brief Master or Slave mode for IEEE 1588 PTP Communication Port
- */
-typedef enum /**< IxTimeSyncAcc1588PTPPortMode */
-{
- IX_TIMESYNCACC_1588PTP_PORT_MASTER, /**< PTP Communication Port in Master Mode */
- IX_TIMESYNCACC_1588PTP_PORT_SLAVE, /**< PTP Communication Port in Slave Mode */
- IX_TIMESYNCACC_1588PTP_PORT_ANYMODE, /**< PTP Communication Port in ANY Mode
- allows time stamping of all messages
- including non-1588 PTP */
- IX_TIMESYNCACC_1588PTP_PORT_MODE_INVALID /**< Invalid PTP Port Mode */
-}IxTimeSyncAcc1588PTPPortMode;
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @enum IxTimeSyncAcc1588PTPMsgType
- *
- * @brief 1588 PTP Messages types that can be detected on communication port
- *
- * Note that client code can determine this based on master/slave mode in which
- * it is already operating in and this information is made available for the sake
- * of convenience only.
- */
-typedef enum /**< IxTimeSyncAcc1588PTPMsgType */
-{
- IX_TIMESYNCACC_1588PTP_MSGTYPE_SYNC, /**< PTP Sync message sent by Master or received by Slave */
- IX_TIMESYNCACC_1588PTP_MSGTYPE_DELAYREQ, /**< PTP Delay_Req message sent by Slave or received by Master */
- IX_TIMESYNCACC_1588PTP_MSGTYPE_UNKNOWN /**< Other PTP and non-PTP message sent or received by both
- Master and/or Slave */
-} IxTimeSyncAcc1588PTPMsgType;
-
-/**
- * Section for struct
- */
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @struct IxTimeSyncAccTimeValue
- *
- * @brief Struct to hold 64 bit SystemTime and TimeStamp values
- */
-typedef struct /**< IxTimeSyncAccTimeValue */
-{
- UINT32 timeValueLowWord; /**< Lower 32 bits of the time value */
- UINT32 timeValueHighWord; /**< Upper 32 bits of the time value */
-} IxTimeSyncAccTimeValue;
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @struct IxTimeSyncAccUuid
- *
- * @brief Struct to hold 48 bit UUID values captured in Sync or Delay_Req messages
- */
-typedef struct /**< IxTimeSyncAccUuid */
-{
- UINT32 uuidValueLowWord; /**<The lower 32 bits of the UUID */
- UINT16 uuidValueHighHalfword; /**<The upper 16 bits of the UUID */
-} IxTimeSyncAccUuid;
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @struct IxTimeSyncAccPtpMsgData
- *
- * @brief Struct for data from the PTP message returned when TimeStamp available
- */
-typedef struct /**< IxTimeSyncAccPtpMsgData */
-{
- IxTimeSyncAcc1588PTPMsgType ptpMsgType; /**< PTP Messages type */
- IxTimeSyncAccTimeValue ptpTimeStamp; /**< 64 bit TimeStamp value from PTP Message */
- IxTimeSyncAccUuid ptpUuid; /**< 48 bit UUID value from the PTP Message */
- UINT16 ptpSequenceNumber; /**< 16 bit Sequence Number from PTP Message */
-} IxTimeSyncAccPtpMsgData;
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @struct IxTimeSyncAccStats
- *
- * @brief Statistics for the PTP messages
- */
-typedef struct /**< IxTimeSyncAccStats */
-{
- UINT32 rxMsgs; /**< Count of timestamps for received PTP Messages */
- UINT32 txMsgs; /**< Count of timestamps for transmitted PTP Messages */
-} IxTimeSyncAccStats;
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @typedef IxTimeSyncAccTargetTimeCallback
- *
- * @brief Callback for use by target time stamp interrupt
- */
-typedef void (*IxTimeSyncAccTargetTimeCallback)(IxTimeSyncAccTimeValue targetTime);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @typedef IxTimeSyncAccAuxTimeCallback
- *
- * @brief Callback for use by auxiliary time interrupts
- */
-typedef void (*IxTimeSyncAccAuxTimeCallback)(IxTimeSyncAccAuxMode auxMode,
- IxTimeSyncAccTimeValue auxTime);
-
-/*
- * Section for prototypes interface functions
- */
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccPTPPortConfigSet(
- IxTimeSyncAcc1588PTPPort ptpPort,
- IxTimeSyncAcc1588PTPPortMode ptpPortMode)
- *
- * @brief Configures the IEEE 1588 message detect on particular PTP port.
- *
- * @param ptpPort [in] - PTP port to config
- * @param ptpPortMode [in]- Port to operate in Master or Slave mode
- *
- * This API will enable the time stamping on a particular PTP port.
- *
- * @li Re-entrant : No
- * @li ISR Callable : No
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- * @li IX_TIMESYNCACC_INVALIDPARAM - Invalid parameters passed
- * @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccPTPPortConfigSet(IxTimeSyncAcc1588PTPPort ptpPort,
- IxTimeSyncAcc1588PTPPortMode ptpPortMode);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccPTPPortConfigGet(
- IxTimeSyncAcc1588PTPPort ptpPort,
- IxTimeSyncAcc1588PTPPortMode *ptpPortMode)
- *
- * @brief Retrieves IEEE 1588 PTP operation mode on particular PTP port.
- *
- * @param ptpPort [in] - PTP port
- * @param ptpPortMode [in]- Mode of operation of PTP port (Master or Slave)
- *
- * This API will identify the time stamping capability of a PTP port by means
- * of obtaining its mode of operation.
- *
- * @li Re-entrant : No
- * @li ISR Callable : No
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- * @li IX_TIMESYNCACC_INVALIDPARAM - Invalid parameters passed
- * @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccPTPPortConfigGet(IxTimeSyncAcc1588PTPPort ptpPort,
- IxTimeSyncAcc1588PTPPortMode *ptpPortMode);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccPTPRxPoll(
- IxTimeSyncAcc1588PTPPort ptpPort,
- IxTimeSyncAccPtpMsgData *ptpMsgData)
- *
- * @brief Polls the IEEE 1588 message/time stamp detect status on a particular
- * PTP Port on the Receive side.
- *
- * @param ptpPort [in] - PTP port to poll
- * @param ptpMsgData [out] - Current TimeStamp and other Data
- *
- * This API will poll for the availability of a time stamp on the received Sync
- * (Slave) or Delay_Req (Master) messages.
- * The client application will provide the buffer.
- *
- * @li Re-entrant : No
- * @li ISR Callable : No
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- * @li IX_TIMESYNCACC_INVALIDPARAM - Invalid parameters passed
- * @li IX_TIMESYNCACC_NOTIMESTAMP - No time stamp available
- * @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccPTPRxPoll(IxTimeSyncAcc1588PTPPort ptpPort,
- IxTimeSyncAccPtpMsgData *ptpMsgData);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccPTPTxPoll(
- IxTimeSyncAcc1588PTPPort ptpPort,
- IxTimeSyncAccPtpMsgData *ptpMsgData)
- *
- *
- * @brief Polls the IEEE 1588 message/time stamp detect status on a particular
- * PTP Port on the Transmit side.
- *
- * @param ptpPort [in] - PTP port to poll
- * @param ptpMsgData [out] - Current TimeStamp and other Data
- *
- * This API will poll for the availability of a time stamp on the transmitted
- * Sync (Master) or Delay_Req (Slave) messages.
- * The client application will provide the buffer.
- *
- * @li Re-entrant : No
- * @li ISR Callable : No
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- * @li IX_TIMESYNCACC_INVALIDPARAM - Invalid parameters passed
- * @li IX_TIMESYNCACC_NOTIMESTAMP - No time stamp available
- * @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccPTPTxPoll(IxTimeSyncAcc1588PTPPort ptpPort,
- IxTimeSyncAccPtpMsgData *ptpMsgData);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccSystemTimeSet(
- IxTimeSyncAccTimeValue systemTime)
- *
- * @brief Sets the System Time in the IEEE 1588 hardware assist block
- *
- * @param systemTime [in] - Value to set System Time
- *
- * This API will set the SystemTime to given value.
- *
- * @li Re-entrant : yes
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- * @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccSystemTimeSet(IxTimeSyncAccTimeValue systemTime);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccSystemTimeGet(
- IxTimeSyncAccTimeValue *systemTime)
- *
- * @brief Gets the System Time from the IEEE 1588 hardware assist block
- *
- * @param systemTime [out] - Copy the current System Time into the client
- * application provided buffer
- *
- * This API will get the SystemTime from IEEE1588 block and return to client
- *
- * @li Re-entrant : no
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- * @li IX_TIMESYNCACC_INVALIDPARAM - Invalid parameters passed
- * @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccSystemTimeGet(IxTimeSyncAccTimeValue *systemTime);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccTickRateSet(
- UINT32 tickRate)
- *
- * @brief Sets the Tick Rate (Frequency Scaling Value) in the IEEE 1588
- * hardware assist block
- *
- * @param tickRate [in] - Value to set Tick Rate
- *
- * This API will set the Tick Rate (Frequency Scaling Value) in the IEEE
- * 1588 block to the given value. The Accumulator register (not client
- * visible) is incremented by this TickRate value every clock cycle. When
- * the Accumulator overflows, the SystemTime is incremented by one. This
- * TickValue can therefore be used to adjust the system timer.
- *
- * @li Re-entrant : yes
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- * @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccTickRateSet(UINT32 tickRate);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccTickRateGet(
- UINT32 *tickRate)
- *
- * @brief Gets the Tick Rate (Frequency Scaling Value) from the IEEE 1588
- * hardware assist block
- *
- * @param tickRate [out] - Current Tick Rate value in the IEEE 1588 block
- *
- * This API will get the TickRate on IEE15588 block. Refer to @ref
- * ixTimeSyncAccTickRateSet for notes on usage of this value.
- *
- * @li Reentrant : yes
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- * @li IX_TIMESYNCACC_INVALIDPARAM - Invalid parameters passed
- * @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccTickRateGet(UINT32 *tickRate);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccTargetTimeInterruptEnable(
- IxTimeSyncAccTargetTimeCallback targetTimeCallback)
- *
- * @brief Enables the interrupt to verify the condition where the System Time
- * greater or equal to the Target Time in the IEEE 1588 hardware assist block.
- * If the condition is true an interrupt will be sent to XScale.
- *
- * @param targetTimeCallback [in] - Callback to be invoked when interrupt fires
- *
- * This API will enable the Target Time reached/hit condition interrupt.
- *
- * NOTE: The client application needs to ensure that the APIs
- * @ref ixTimeSyncAccTargetTimeInterruptEnable, @ref ixTimeSyncAccTargetTimeSet and
- * @ref ixTimeSyncAccTargetTimeInterruptDisable are accessed in mutual exclusive
- * manner with respect to each other.
- *
- * @li Re-entrant : no
- * @li ISR Callable : yes
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- * @li IX_TIMESYNCACC_INVALIDPARAM - Null parameter passed for callback
- * @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccTargetTimeInterruptEnable(IxTimeSyncAccTargetTimeCallback targetTimeCallback);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccTargetTimeInterruptDisable(
- void)
- *
- * @brief Disables the interrupt for the condition explained in the function
- * description of @ref ixTimeSyncAccTargetTimeInterruptEnable.
- *
- * This API will disable the Target Time interrupt.
- *
- * NOTE: The client application needs to ensure that the APIs
- * @ref ixTimeSyncAccTargetTimeInterruptEnable, @ref ixTimeSyncAccTargetTimeSet and
- * @ref ixTimeSyncAccTargetTimeInterruptDisable are accessed in mutual exclusive
- * manner with respect to each other.
- *
- * @li Re-entrant : no
- * @li ISR Callable : yes
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- * @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccTargetTimeInterruptDisable(void);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccTargetTimePoll(
- BOOL *ttmPollFlag,
- IxTimeSyncAccTimeValue *targetTime)
- *
- * @brief Poll to verify the condition where the System Time greater or equal to
- * the Target Time in the IEEE 1588 hardware assist block. If the condition is
- * true an event flag is set in the hardware.
- *
- * @param ttmPollFlag [out] - true if the target time reached/hit condition event set
- * false if the target time reached/hit condition event is
- not set
- * @param targetTime [out] - Capture current targetTime into client provided buffer
- *
- * Poll the target time reached/hit condition status. Return true and the current
- * target time value, if the condition is true else return false.
- *
- * NOTE: The client application will need to clear the event flag that will be set
- * as long as the condition that the System Time greater or equal to the Target Time is
- * valid, in one of the following ways:
- * 1) Invoke the API to change the target time
- * 2) Change the system timer value
- *
- * @li Re-entrant : yes
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- * @li IX_TIMESYNCACC_INVALIDPARAM - Null parameter passed
- * @li IX_TIMESYNCACC_FAILED - Internal error occurred
- * @li IX_TIMESYNCACC_INTERRUPTMODEINUSE - Interrupt mode in use
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccTargetTimePoll(BOOL *ttmPollFlag,
- IxTimeSyncAccTimeValue *targetTime);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccTargetTimeSet(
- IxTimeSyncAccTimeValue targetTime)
- *
- * @brief Sets the Target Time in the IEEE 1588 hardware assist block
- *
- * @param targetTime [in] - Value to set Target Time
- *
- * This API will set the Target Time to a given value.
- *
- * NOTE: The client application needs to ensure that the APIs
- * @ref ixTimeSyncAccTargetTimeInterruptEnable, @ref ixTimeSyncAccTargetTimeSet and
- * @ref ixTimeSyncAccTargetTimeInterruptDisable are accessed in mutual exclusive
- * manner with respect to each other.
- *
- * @li Reentrant : no
- * @li ISR Callable : yes
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- * @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccTargetTimeSet(IxTimeSyncAccTimeValue targetTime);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccTargetTimeGet(
- IxTimeSyncAccTimeValue *targetTime)
- *
- * @brief Gets the Target Time in the IEEE 1588 hardware assist block
- *
- * @param targetTime [out] - Copy current time to client provided buffer
- *
- * This API will get the Target Time from IEEE 1588 block and return to the
- * client application
- *
- * @li Re-entrant : yes
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- * @li IX_TIMESYNCACC_INVALIDPARAM - Null parameter passed
- * @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccTargetTimeGet(IxTimeSyncAccTimeValue *targetTime);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccAuxTimeInterruptEnable(
- IxTimeSyncAccAuxMode auxMode,
- IxTimeSyncAccAuxTimeCallback auxTimeCallback)
- *
- * @brief Enables the interrupt notification for the given mode of Auxiliary Time
- * Stamp in the IEEE 1588 hardware assist block
- *
- * @param auxMode [in] - Auxiliary time stamp register (slave or master) to use
- * @param auxTimeCallback [in] - Callback to be invoked when interrupt fires
- *
- * This API will enable the Auxiliary Master/Slave Time stamp Interrupt.
- *
- * <pre>
- * NOTE: 1) An individual callback is to be registered for each Slave and Master
- * Auxiliary Time Stamp registers. Thus to register for both Master and Slave time
- * stamp interrupts either the same callback or two separate callbacks the API has
- * to be invoked twice.
- * 2) On the IXDP465 Development Platform, the Auxiliary Timestamp signal for
- * slave mode is tied to GPIO 8 pin. This signal is software routed by default to
- * PCI for backwards compatibility with the IXDP425 Development Platform. This
- * routing must be disabled for the auxiliary slave time stamp register to work
- * properly. The following commands may be used to accomplish this. However, refer
- * to the IXDP465 Development Platform Users Guide or the BSP/LSP documentation for
- * more specific information.
- *
- * For Linux (at the Redboot prompt i.e., before loading zImage):
- * mfill -b 0x54100000 -1 -l 1 -p 8
- * mfill -b 0x54100001 -1 -l 1 -p 0x7f
- * For vxWorks, at the prompt:
- * intDisable(25)
- * ixdp400FpgaIODetach(8)
- * </pre>
- *
- * @li Re-entrant : no
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- * @li IX_TIMESYNCACC_INVALIDPARAM - Null parameter passed for callback or
- invalid auxiliary snapshot mode
- * @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccAuxTimeInterruptEnable(IxTimeSyncAccAuxMode auxMode,
- IxTimeSyncAccAuxTimeCallback auxTimeCallback);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccAuxTimeInterruptDisable(
- IxTimeSyncAccAuxMode auxMode)
- *
- * @brief Disables the interrupt for the indicated mode of Auxiliary Time Stamp
- * in the IEEE 1588 hardware assist block
- *
- * @param auxMode [in] - Auxiliary time stamp mode (slave or master) using which
- * the interrupt will be disabled.
- *
- * This API will disable the Auxiliary Time Stamp Interrupt (Master or Slave)
- *
- * @li Re-entrant : yes
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- * @li IX_TIMESYNCACC_INVALIDPARAM - Invalid parameters passed
- * @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccAuxTimeInterruptDisable(IxTimeSyncAccAuxMode auxMode);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccAuxTimePoll(
- IxTimeSyncAccAuxMode auxMode,
- BOOL *auxPollFlag,
- IxTimeSyncAccTimeValue *auxTime)
- *
- * @brief Poll for the Auxiliary Time Stamp captured for the mode indicated
- * (Master or Slave)
- *
- * @param auxMode [in] - Auxiliary Snapshot Register (Slave or Master) to be checked
- * @param auxPollFlag [out] - true if the time stamp captured in auxiliary
- snapshot register
- * false if the time stamp not captured in
- auxiliary snapshot register
- * @param auxTime [out] - Copy the current Auxiliary Snapshot Register value into the
- * client provided buffer
- *
- * Polls for the Time stamp in the appropriate Auxiliary Snapshot Registers based
- * on the mode specified. Return true and the contents of the Auxiliary snapshot,
- * if it is available else return false.
- *
- * Please refer to the note #2 of the API @ref ixTimeSyncAccAuxTimeInterruptEnable
- * for more information for Auxiliary Slave mode.
- *
- * @li Re-entrant : yes
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- * @li IX_TIMESYNCACC_INVALIDPARAM - Null parameter passed for auxPollFlag,
- callback or invalid auxiliary snapshot mode
- * @li IX_TIMESYNCACC_FAILED - Internal error occurred
- * @li IX_TIMESYNCACC_INTERRUPTMODEINUSE - Interrupt mode in use
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccAuxTimePoll(IxTimeSyncAccAuxMode auxMode,
- BOOL *auxPollFlag,
- IxTimeSyncAccTimeValue *auxTime);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccReset(void)
- *
- * @brief Resets the IEEE 1588 hardware assist block
- *
- * Sets the reset bit in the IEEE1588 silicon which fully resets the silicon block
- *
- * @li Reentrant : yes
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- * @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccReset(void);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccStatsGet(IxTimeSyncAccStats
- *timeSyncStats)
- *
- * @brief Returns the IxTimeSyncAcc Statistics in the client supplied buffer
- *
- * @param timeSyncStats [out] - TimeSync statistics counter values
- *
- * This API will return the statistics of the received or transmitted messages.
- *
- * NOTE: 1) These counters are updated only when the client polls for the time
- * stamps or interrupt are enabled. This is because the IxTimeSyncAcc module
- * does not either transmit or receive messages and does only run the code
- * when explicit requests received by client application.
- *
- * 2) These statistics reflect the number of valid PTP messages exchanged
- * in Master and Slave modes but includes all the messages (including valid
- * non-PTP messages) while operating in the Any mode.
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- * @li IX_TIMESYNCACC_INVALIDPARAM - NULL parameter passed
- * @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccStatsGet(IxTimeSyncAccStats *timeSyncStats);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn void ixTimeSyncAccStatsReset(void)
- *
- * @brief Reset Time Sync statistics
- *
- * This API will reset the statistics counters of the TimeSync access layer.
- *
- * @li Reentrant : yes
- * @li ISR Callable: no
- *
- * @return @li None
- */
-PUBLIC void
-ixTimeSyncAccStatsReset(void);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccShow(void)
- *
- * @brief Displays the Time Sync current status
- *
- * This API will display status on the current configuration of the IEEE
- * 1588 hardware assist block, contents of the various time stamp registers,
- * outstanding interrupts and/or events.
- *
- * Note that this is intended for debug only, and in contrast to the other
- * functions, it does not clear the any of the status bits associated with
- * active timestamps and so is passive in its nature.
- *
- * @li Reentrant : yes
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- * @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccShow(void);
-
-#endif /* __ixp46X */
-#endif /* IXTIMESYNCACC_H */
-
-/**
- * @} defgroup IxTimeSyncAcc
- */
-
+++ /dev/null
-/**
- * @file IxTimerCtrl.h
- * @brief
- * This is the header file for the Timer Control component.
- *
- * The timer callback control component provides a mechanism by which different
- * client components can start a timer and have a supplied callback function
- * invoked when the timer expires.
- * The callbacks are all dispatched from one thread inside this component.
- * Any component that needs to be called periodically should use this facility
- * rather than create its own task with a sleep loop.
- *
- * @par
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxTimerCtrl IXP400 Timer Control (IxTimerCtrl) API
- *
- * @brief The public API for the IXP400 Timer Control Component.
- *
- * @{
- */
-
-#ifndef IxTimerCtrl_H
-#define IxTimerCtrl_H
-
-
-#include "IxTypes.h"
-/* #include "Ossl.h" */
-
-/*
- * #defines and macros used in this file.
- */
-
-/**
- * @ingroup IxTimerCtrl
- *
- * @def IX_TIMERCTRL_NO_FREE_TIMERS
- *
- * @brief Timer schedule return code.
- *
- * Indicates that the request to start a timer failed because
- * all available timer resources are used.
- */
-#define IX_TIMERCTRL_NO_FREE_TIMERS 2
-
-
-/**
- * @ingroup IxTimerCtrl
- *
- * @def IX_TIMERCTRL_PARAM_ERROR
- *
- * @brief Timer schedule return code.
- *
- * Indicates that the request to start a timer failed because
- * the client has supplied invalid parameters.
- */
-#define IX_TIMERCTRL_PARAM_ERROR 3
-
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/**
- * @ingroup IxTimerCtrl
- *
- * @brief A typedef for a pointer to a timer callback function.
- * @para void * - This parameter is supplied by the client when the
- * timer is started and passed back to the client in the callback.
- * @note in general timer callback functions should not block or
- * take longer than 100ms. This constraint is required to ensure that
- * higher priority callbacks are not held up.
- * All callbacks are called from the same thread.
- * This thread is a shared resource.
- * The parameter passed is provided when the timer is scheduled.
- */
-typedef void (*IxTimerCtrlTimerCallback)(void *userParam);
-
-
-/**
- * @ingroup IxTimerCtrl
- *
- * @brief List used to identify the users of timers.
- * @note The order in this list indicates priority. Components appearing
- * higher in the list will be given priority over components lower in the
- * list. When adding components, please insert at an appropriate position
- * for priority ( i.e values should be less than IxTimerCtrlMaxPurpose ) .
- */
-typedef enum
-{
- IxTimerCtrlAdslPurpose,
- /* Insert new purposes above this line only
- */
- IxTimerCtrlMaxPurpose
-}
-IxTimerCtrlPurpose;
-
-
-/*
- * Function definition
- */
-
-/**
- * @ingroup IxTimerCtrl
- *
- * @fn ixTimerCtrlSchedule(IxTimerCtrlTimerCallback func,
- void *userParam,
- IxTimerCtrlPurpose purpose,
- UINT32 relativeTime,
- unsigned *timerId )
- *
- * @brief Schedules a callback function to be called after a period of "time".
- * The callback function should not block or run for more than 100ms.
- * This function
- *
- * @param func @ref IxTimerCtrlTimerCallback [in] - the callback function to be called.
- * @param userParam void [in] - a parameter to send to the callback function, can be NULL.
- * @param purpose @ref IxTimerCtrlPurpose [in] - the purpose of the callback, internally this component will
- * decide the priority of callbacks with different purpose.
- * @param relativeTime UINT32 [in] - time relative to now in milliseconds after which the callback
- * will be called. The time must be greater than the duration of one OS tick.
- * @param *timerId unsigned [out] - An id for the callback scheduled.
- * This id can be used to cancel the callback.
- * @return
- * @li IX_SUCCESS - The timer was started successfully.
- * @li IX_TIMERCTRL_NO_FREE_TIMERS - The timer was not started because the maximum number
- * of running timers has been exceeded.
- * @li IX_TIMERCTRL_PARAM_ERROR - The timer was not started because the client has supplied
- * a NULL callback func, or the requested timeout is less than one OS tick.
- * @note This function is re-entrant. The function accesses a list of running timers
- * and may suspend the calling thread if this list is being accesed by another thread.
- */
-PUBLIC IX_STATUS
-ixTimerCtrlSchedule(IxTimerCtrlTimerCallback func,
- void *userParam,
- IxTimerCtrlPurpose purpose,
- UINT32 relativeTime,
- unsigned *timerId );
-
-
-/**
- * @ingroup IxTimerCtrl
- *
- * @fn ixTimerCtrlScheduleRepeating(IxTimerCtrlTimerCallback func,
- void *param,
- IxTimerCtrlPurpose purpose,
- UINT32 interval,
- unsigned *timerId )
- *
- * @brief Schedules a callback function to be called after a period of "time".
- * The callback function should not block or run for more than 100ms.
- *
- * @param func @ref IxTimerCtrlTimerCallback [in] - the callback function to be called.
- * @param userParam void [in] - a parameter to send to the callback function, can be NULL.
- * @param purpose @ref IxTimerCtrlPurpose [in] - the purpose of the callback, internally this component will
- * decide the priority of callbacks with different purpose.
- * @param interval UINT32 [in] - the interval in milliseconds between calls to func.
- * @param timerId unsigned [out] - An id for the callback scheduled.
- * This id can be used to cancel the callback.
- * @return
- * @li IX_SUCCESS - The timer was started successfully.
- * @li IX_TIMERCTRL_NO_FREE_TIMERS - The timer was not started because the maximum number
- * of running timers has been exceeded.
- * @li IX_TIMERCTRL_PARAM_ERROR - The timer was not started because the client has supplied
- * a NULL callback func, or the requested timeout is less than one OS tick.
- * @note This function is re-entrant. The function accesses a list of running timers
- * and may suspend the calling thread if this list is being accesed by another thread.
- */
-PUBLIC IX_STATUS
-ixTimerCtrlScheduleRepeating(IxTimerCtrlTimerCallback func,
- void *param,
- IxTimerCtrlPurpose purpose,
- UINT32 interval,
- unsigned *timerId );
-
-/**
- * @ingroup IxTimerCtrl
- *
- * @fn ixTimerCtrlCancel (unsigned id)
- *
- * @brief Cancels a scheduled callback.
- *
- * @param id unsigned [in] - the id of the callback to be cancelled.
- * @return
- * @li IX_SUCCESS - The timer was successfully stopped.
- * @li IX_FAIL - The id parameter did not corrrespond to any running timer..
- * @note This function is re-entrant. The function accesses a list of running timers
- * and may suspend the calling thread if this list is being accesed by another thread.
- */
-PUBLIC IX_STATUS
-ixTimerCtrlCancel (unsigned id);
-
-/**
- * @ingroup IxTimerCtrl
- *
- * @fn ixTimerCtrlInit(void)
- *
- * @brief Initialise the Timer Control Component.
- * @return
- * @li IX_SUCCESS - The timer control component initialized successfully.
- * @li IX_FAIL - The timer control component initialization failed,
- * or the component was already initialized.
- * @note This must be done before any other API function is called.
- * This function should be called once only and is not re-entrant.
- */
-PUBLIC IX_STATUS
-ixTimerCtrlInit(void);
-
-
-/**
- * @ingroup IxTimerCtrl
- *
- * @fn ixTimerCtrlShow( void )
- *
- * @brief Display the status of the Timer Control Component.
- * @return void
- * @note Displays a list of running timers.
- * This function is not re-entrant. This function does not suspend the calling thread.
- */
-PUBLIC void
-ixTimerCtrlShow( void );
-
-#endif /* IXTIMERCTRL_H */
-
+++ /dev/null
-/**
- * @file IxTypes.h (Replaced by OSAL)
- *
- * @date 28-NOV-2001
-
- * @brief This file contains basic types used by the IXP400 software
- *
- * Design Notes:
- * This file shall only include fundamental types and definitions to be
- * shared by all the IXP400 components.
- * Please DO NOT add component-specific types here.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxTypes IXP400 Types (IxTypes)
- *
- * @brief Basic data types used by the IXP400 project
- *
- * @{
- */
-
-#ifndef IxTypes_H
-
-#ifndef __doxygen_HIDE
-
-#define IxTypes_H
-
-#endif /* __doxygen_HIDE */
-
-
-/* WR51880: Undefined data types workaround for backward compatibility */
-#ifdef __linux
-#ifndef __INCvxTypesOldh
-typedef int (*FUNCPTR)(void);
-typedef int STATUS;
-#define OK (0)
-#define ERROR (-1)
-#endif
-#endif
-
-#include "IxOsalBackward.h"
-
-#endif /* IxTypes_H */
-
-/**
- * @} addtogroup IxTypes
- */
+++ /dev/null
-/**
- * @file IxUART.h
- *
- * @date 12-OCT-01
- *
- * @brief Public header for the Intel IXP400 internal UART, generic driver.
- *
- * Design Notes:
- * This driver allows you to perform the following functions:
- * Device Initialization,
- * send/receive characters.
- *
- * Perform Uart IOCTL for the following:
- * Set/Get the current baud rate,
- * set parity,
- * set the number of Stop bits,
- * set the character Length (5,6,7,8),
- * enable/disable Hardware flow control.
- *
- * Only Polled mode is supported for now.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxUARTAccAPI IXP400 UART Access (IxUARTAcc) API
- *
- * @brief IXP400 UARTAcc Driver Public API
- *
- * @{
- */
-
-
-/* Defaults */
-
-/**
- * @defgroup DefaultDefines Defines for Default Values
- *
- * @brief Default values which can be used for UART configuration
- *
- * @sa ixUARTDev
- */
-
-/**
- * @def IX_UART_DEF_OPTS
- *
- * @brief The default hardware options to set the UART to -
- * no flow control, 8 bit word, 1 stop bit, no parity
- *
- * @ingroup DefaultDefines
- */
-#define IX_UART_DEF_OPTS (CLOCAL | CS8)
-
-/**
- * @def IX_UART_DEF_XMIT
- *
- * @brief The default UART FIFO size - must be no bigger than 64
- *
- * @ingroup DefaultDefines
- */
-#define IX_UART_DEF_XMIT 64
-
-/**
- * @def IX_UART_DEF_BAUD
- *
- * @brief The default UART baud rate - 9600
- *
- * @ingroup DefaultDefines
- */
-#define IX_UART_DEF_BAUD 9600
-
-/**
- * @def IX_UART_MIN_BAUD
- *
- * @brief The minimum UART baud rate - 9600
- *
- * @ingroup DefaultDefines
- */
-#define IX_UART_MIN_BAUD 9600
-
-/**
- * @def IX_UART_MAX_BAUD
- *
- * @brief The maximum UART baud rate - 926100
- *
- * @ingroup DefaultDefines
- */
-#define IX_UART_MAX_BAUD 926100
-
-/**
- * @def IX_UART_XTAL
- *
- * @brief The UART clock speed
- *
- * @ingroup DefaultDefines
- */
-#define IX_UART_XTAL 14745600
-
-
-
-/* IOCTL commands (Request codes) */
-
-/**
- * @defgroup IoctlCommandDefines Defines for IOCTL Commands
- *
- * @brief IOCTL Commands (Request codes) which can be used
- * with @ref ixUARTIoctl
- */
-
-
-/**
- * @ingroup IoctlCommandDefines
- *
- * @def IX_BAUD_SET
- *
- * @brief Set the baud rate
- */
-#define IX_BAUD_SET 0
-
-/**
- * @ingroup IoctlCommandDefines
- *
- * @def IX_BAUD_GET
- *
- * @brief Get the baud rate
- */
-#define IX_BAUD_GET 1
-
-/**
- * @ingroup IoctlCommandDefines
- * @def IX_MODE_SET
- * @brief Set the UART mode of operation
- */
-#define IX_MODE_SET 2
-
-/**
- * @ingroup IoctlCommandDefines
- *
- * @def IX_MODE_GET
- *
- * @brief Get the current UART mode of operation
- */
-#define IX_MODE_GET 3
-
-/**
- * @ingroup IoctlCommandDefines
- *
- * @def IX_OPTS_SET
- *
- * @brief Set the UART device options
- */
-#define IX_OPTS_SET 4
-
-/**
- * @ingroup IoctlCommandDefines
- *
- * @def IX_OPTS_GET
- *
- * @brief Get the UART device options
- */
-#define IX_OPTS_GET 5
-
-/**
- * @ingroup IoctlCommandDefines
- *
- * @def IX_STATS_GET
- *
- * @brief Get the UART statistics
- */
-#define IX_STATS_GET 6
-
-
-/* POSIX style ioctl arguments */
-
-/**
- * @defgroup IoctlArgDefines Defines for IOCTL Arguments
- *
- * @brief POSIX style IOCTL arguments which can be used
- * with @ref ixUARTIoctl
- *
- * @sa ixUARTMode
- */
-
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def CLOCAL
- *
- * @brief Software flow control
- */
-#ifdef CLOCAL
-#undef CLOCAL
-#endif
-#define CLOCAL 0x1
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def CREAD
- *
- * @brief Enable interrupt receiver
- */
-#ifdef CREAD
-#undef CREAD
-#endif
-#define CREAD 0x2
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def CSIZE
- *
- * @brief Characters size
- */
-#ifdef CSIZE
-#undef CSIZE
-#endif
-#define CSIZE 0xc
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def CS5
- *
- * @brief 5 bits
- */
-#ifdef CS5
-#undef CS5
-#endif
-#define CS5 0x0
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def CS6
- *
- * @brief 6 bits
- */
-#ifdef CS6
-#undef CS6
-#endif
-#define CS6 0x4
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def CS7
- *
- * @brief 7 bits
- */
-#ifdef CS7
-#undef CS7
-#endif
-#define CS7 0x8
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def CS8
- *
- * @brief 8 bits
- */
-#ifdef CS8
-#undef CS8
-#endif
-#define CS8 0xc
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def STOPB
- *
- * @brief Send two stop bits (else one)
- */
-#define STOPB 0x20
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def PARENB
- *
- * @brief Parity detection enabled (else disabled)
- */
-#ifdef PARENB
-#undef PARENB
-#endif
-#define PARENB 0x40
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def PARODD
- *
- * @brief Odd parity (else even)
- */
-#ifdef PARODD
-#undef PARODD
-#endif
-#define PARODD 0x80
-
-/**
- * @enum ixUARTMode
- * @brief The mode to set to UART to.
- */
-typedef enum
-{
- INTERRUPT=0, /**< Interrupt mode */
- POLLED, /**< Polled mode */
- LOOPBACK /**< Loopback mode */
-} ixUARTMode;
-
-/**
- * @struct ixUARTStats
- * @brief Statistics for the UART.
- */
-typedef struct
-{
- UINT32 rxCount;
- UINT32 txCount;
- UINT32 overrunErr;
- UINT32 parityErr;
- UINT32 framingErr;
- UINT32 breakErr;
-} ixUARTStats;
-
-/**
- * @struct ixUARTDev
- * @brief Device descriptor for the UART.
- */
-typedef struct
-{
- UINT8 *addr; /**< device base address */
- ixUARTMode mode; /**< interrupt, polled or loopback */
- int baudRate; /**< baud rate */
- int freq; /**< UART clock frequency */
- int options; /**< hardware options */
- int fifoSize; /**< FIFO xmit size */
-
- ixUARTStats stats; /**< device statistics */
-} ixUARTDev;
-
-/**
- * @ingroup IxUARTAccAPI
- *
- * @fn IX_STATUS ixUARTInit(ixUARTDev* pUART)
- *
- * @param pUART @ref ixUARTDev [in] - pointer to UART structure describing our device.
- *
- * @brief Initialise the UART. This puts the chip in a quiescent state.
- *
- * @pre The base address for the UART must contain a valid value.
- * Also the baud rate and hardware options must contain sensible values
- * otherwise the defaults will be used as defined in ixUART.h
- *
- * @post UART is initialized and ready to send and receive data.
- *
- * @note This function should only be called once per device.
- *
- * @retval IX_SUCCESS - UART device successfully initialised.
- * @retval IX_FAIL - Critical error, device not initialised.
- ***************************************************************************/
-PUBLIC IX_STATUS ixUARTInit(ixUARTDev* pUART);
-
-/**
- * @ingroup IxUARTAccAPI
- *
- * @fn IX_STATUS ixUARTPollOutput(ixUARTDev* pUART, int outChar)
- *
- * @param pUART @ref ixUARTDev [out] - pointer to UART structure describing our device.
- * @param outChar int [out] - character to transmit.
- *
- * @brief Transmit a character in polled mode.
- *
- * @pre UART device must be initialised.
- *
- * @retval IX_SUCCESS - character was successfully transmitted.
- * @retval IX_FAIL - output buffer is full (try again).
- ***************************************************************************/
-PUBLIC IX_STATUS ixUARTPollOutput(ixUARTDev* pUART, int outChar);
-
-/**
- * @ingroup IxUARTAccAPI
- *
- * @fn IX_STATUS ixUARTPollInput(ixUARTDev* pUART, char *inChar)
- *
- * @param pUART @ref ixUARTDev [in] - pointer to UART structure describing our device.
- * @param *inChar char [in] - character read from the device.
- *
- * @brief Receive a character in polled mode.
- *
- * @pre UART device must be initialised.
- *
- * @retval IX_SUCCESS - character was successfully read.
- * @retval IX_FAIL - input buffer empty (try again).
- ***************************************************************************/
-PUBLIC IX_STATUS ixUARTPollInput(ixUARTDev* pUART, char *inChar);
-
-/**
- * @ingroup IxUARTAccAPI
- *
- * @fn IX_STATUS ixUARTIoctl(ixUARTDev* pUART, int cmd, void* arg)
- *
- * @param pUART @ref ixUARTDev [in] - pointer to UART structure describing our device.
- * @param cmd int [in] - an ioctl request code.
- * @param arg void* [in] - optional argument used to set the device mode,
- * baud rate, and hardware options.
- *
- * @brief Perform I/O control routines on the device.
- *
- * @retval IX_SUCCESS - requested feature was set/read successfully.
- * @retval IX_FAIL - error setting/reading the requested feature.
- *
- * @sa IoctlCommandDefines
- * @sa IoctlArgDefines
- ***************************************************************************/
-PUBLIC IX_STATUS ixUARTIoctl(ixUARTDev* pUART, int cmd, void* arg);
-
-/**
- * @} defgroup IxUARTAcc
- */
+++ /dev/null
-/**
- * @file IxVersionId.h
- *
- * @date 22-Aug-2002
- *
- * @brief This file contains the IXP400 Software version identifier
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxVersionId IXP400 Version ID (IxVersionId)
- *
- * @brief Version Identifiers
- *
- * @{
- */
-
-#ifndef IXVERSIONID_H
-#define IXVERSIONID_H
-
-/**
- * @brief Version Identifier String
- *
- * This string will be updated with each customer release of the IXP400
- * Software.
- */
-#define IX_VERSION_ID "2_0"
-
-/**
- * This string will be updated with each customer release of the IXP400
- * ADSL driver package.
- */
-#define IX_VERSION_ADSL_ID "1_12"
-
-
-/**
- * This string will be updated with each customer release of the IXP400
- * USB Client driver package.
- */
-#define IX_VERSION_USBRNDIS_ID "1_9"
-
-/**
- * This string will be updated with each customer release of the IXP400
- * I2C Linux driver package.
- */
-#define IX_VERSION_I2C_LINUX_ID "1_0"
-
-/**
- * @brief Linux Ethernet Driver Patch Version Identifier String
- *
- * This string will be updated with each release of Linux Ethernet Patch
- */
-#define LINUX_ETHERNET_DRIVER_PATCH_ID "1_4"
-
-/**
- * @brief Linux Integration Patch Version Identifier String
- *
- * This String will be updated with each release of Linux Integration Patch
- */
-#define LINUX_INTEGRATION_PATCH_ID "1_3"
-
-/**
- * @brief Linux Ethernet Readme version Identifier String
- *
- * This string will be updated with each release of Linux Ethernet Readme
- */
-#define LINUX_ETHERNET_README_ID "1_3"
-
-/**
- * @brief Linux Integration Readme version Identifier String
- *
- * This string will be updated with each release of Linux Integration Readme
- */
-
-#define LINUX_INTEGRATION_README_ID "1_3"
-
-/**
- * @brief Linux I2C driver Readme version Identifier String
- *
- * This string will be updated with each release of Linux I2C Driver Readme
- */
-#define LINUX_I2C_DRIVER_README_ID "1_0"
-
-/**
- * @brief ixp425_eth_update_nf_bridge.patch version Identifier String
- *
- * This string will be updated with each release of ixp425_eth_update_nf_bridge.
-patch
- *
- */
-
-#define IXP425_ETH_UPDATE_NF_BRIDGE_ID "1_3"
-
-/**
- * @brief Internal Release Identifier String
- *
- * This string will be updated with each internal release (SQA drop)
- * of the IXP400 Software.
- */
-#define IX_VERSION_INTERNAL_ID "SQA3_5"
-
-/**
- * @brief Compatible Tornado Version Identifier
- */
-#define IX_VERSION_COMPATIBLE_TORNADO "Tornado2_2_1-PNE2_0"
-
-/**
- * @brief Compatible Linux Version Identifier
- */
-#define IX_VERSION_COMPATIBLE_LINUX "MVL3_1"
-
-
-#endif /* IXVERSIONID_H */
-
-/**
- * @} addtogroup IxVersionId
- */
+++ /dev/null
-/**
- * ============================================================================
- * = COPYRIGHT
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- * = PRODUCT
- * Intel(r) IXP425 Software Release
- *
- * = FILENAME
- * ix_error.h (Replaced by OSAL)
- *
- * = DESCRIPTION
- * This file will describe the basic error type and support functions that
- * will be used by the IXA SDK Framework API.
- *
- * = AUTHOR
- * Intel Corporation
- *
- * = CHANGE HISTORY
- * 4/22/2002 4:19:03 PM - creation time
- * ============================================================================
- */
-
-#if !defined(__IX_ERROR_H__)
-#define __IX_ERROR_H__
-
-#include "IxOsalBackward.h"
-
-#endif /* end !defined(__IX_ERROR_H__) */
-
+++ /dev/null
-/**
- * ============================================================================
- * = COPYRIGHT
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- * = PRODUCT
- * Intel(r) IXP425 Software Release
- *
- * = FILENAME
- * ix_macros.h
- *
- * = DESCRIPTION
- * This file will define the basic preprocessor macros that are going to be used
- * the IXA SDK Framework API.
- *
- * = AUTHOR
- * Intel Corporation
- *
- * = CHANGE HISTORY
- * 4/22/2002 4:41:05 PM - creation time
- * ============================================================================
- */
-
-#if !defined(__IX_MACROS_H__)
-#define __IX_MACROS_H__
-
-
-#if defined(__cplusplus)
-extern "C"
-{
-#endif /* end defined(__cplusplus) */
-
-
-/**
- * MACRO NAME: IX_BIT_FIELD_MASK16
- *
- * DESCRIPTION: Builds the mask required to extract the bit field from a 16 bit unsigned integer value.
- *
- * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant
- * bit of the bit field.
- * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant
- * bit of the bit field.
- *
- * @Return: Returns a 16 bit mask that will extract the bit field from a 16 bit unsigned integer value.
- */
-#define IX_BIT_FIELD_MASK16( \
- arg_FieldLSBBit, \
- arg_FieldMSBBit \
- ) \
- ((ix_bit_mask16)((((ix_uint16)1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - \
- (ix_uint16)1) << arg_FieldLSBBit))
-
-
-
-/**
- * MACRO NAME: IX_GET_BIT_FIELD16
- *
- * DESCRIPTION: Extracts a bit field from 16 bit unsigned integer. The returned value is normalized in
- * in the sense that will be right aligned.
- *
- * @Param: - IN arg_PackedData16 a 16 bit unsigned integer that contains the bit field of interest.
- * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant
- * bit of the bit field.
- * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant
- * bit of the bit field.
- *
- * @Return: Returns the value of the bit field. The value can be from 0 to (1 << (arg_FieldMSBBit + 1 -
- * arg_FieldLSBBit)) - 1.
- */
-#define IX_GET_BIT_FIELD16( \
- arg_PackedData16, \
- arg_FieldLSBBit, \
- arg_FieldMSBBit \
- ) \
- (((ix_uint16)(arg_PackedData16) & IX_BIT_FIELD_MASK16(arg_FieldLSBBit, arg_FieldMSBBit)) >> \
- arg_FieldLSBBit)
-
-
-/**
- * MACRO NAME: IX_MAKE_BIT_FIELD16
- *
- * DESCRIPTION: This macro will create a temporary 16 bit value with the bit field
- * desired set to the desired value.
- *
- * @Param: - IN arg_BitFieldValue is the new value of the bit field. The value can be from 0 to
- * (1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - 1.
- * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant
- * bit of the bit field.
- * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant
- * bit of the bit field.
- *
- * @Return: Returns a temporary ix_uint16 value that has the bit field set to the appropriate value.
- */
-#define IX_MAKE_BIT_FIELD16( \
- arg_BitFieldValue, \
- arg_FieldLSBBit, \
- arg_FieldMSBBit \
- ) \
- (((ix_uint16)(arg_BitFieldValue) << arg_FieldLSBBit) & \
- IX_BIT_FIELD_MASK16(arg_FieldLSBBit, arg_FieldMSBBit))
-
-/**
- * MACRO NAME: IX_SET_BIT_FIELD16
- *
- * DESCRIPTION: Sets a new value for a bit field from a 16 bit unsigned integer.
- *
- * @Param: - IN arg_PackedData16 a 16 bit unsigned integer that contains the bit field of interest.
- * @Param: - IN arg_BitFieldValue is the new vale of the bit field. The value can be from 0 to
- * (1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - 1.
- * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant
- * bit of the bit field.
- * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant
- * bit of the bit field.
- *
- * @Return: Returns the updated value of arg_PackedData16.
- */
-#define IX_SET_BIT_FIELD16( \
- arg_PackedData16, \
- arg_BitFieldValue, \
- arg_FieldLSBBit, \
- arg_FieldMSBBit \
- ) \
- (arg_PackedData16 = (((ix_uint16)(arg_PackedData16) & \
- ~(IX_BIT_FIELD_MASK16(arg_FieldLSBBit, arg_FieldMSBBit))) | \
- IX_MAKE_BIT_FIELD16(arg_BitFieldValue, arg_FieldLSBBit, arg_FieldMSBBit)))
-
-
-/**
- * MACRO NAME: IX_BIT_FIELD_MASK32
- *
- * DESCRIPTION: Builds the mask required to extract the bit field from a 32 bit unsigned integer value.
- *
- * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant
- * bit of the bit field.
- * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant
- * bit of the bit field.
- *
- * @Return: Returns a 32 bit mask that will extract the bit field from a 32 bit unsigned integer value.
- */
-#define IX_BIT_FIELD_MASK32( \
- arg_FieldLSBBit, \
- arg_FieldMSBBit \
- ) \
- ((ix_bit_mask32)((((ix_uint32)1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - \
- (ix_uint32)1) << arg_FieldLSBBit))
-
-
-
-/**
- * MACRO NAME: IX_GET_BIT_FIELD32
- *
- * DESCRIPTION: Extracts a bit field from 32 bit unsigned integer. The returned value is normalized in
- * in the sense that will be right aligned.
- *
- * @Param: - IN arg_PackedData32 a 32 bit unsigned integer that contains the bit field of interest.
- * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant
- * bit of the bit field.
- * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant
- * bit of the bit field.
- *
- * @Return: Returns the value of the bit field. The value can be from 0 to (1 << (arg_FieldMSBBit + 1 -
- * arg_FieldLSBBit)) - 1.
- */
-#define IX_GET_BIT_FIELD32( \
- arg_PackedData32, \
- arg_FieldLSBBit, \
- arg_FieldMSBBit \
- ) \
- (((ix_uint32)(arg_PackedData32) & IX_BIT_FIELD_MASK32(arg_FieldLSBBit, arg_FieldMSBBit)) >> \
- arg_FieldLSBBit)
-
-
-
-
-/**
- * MACRO NAME: IX_MAKE_BIT_FIELD32
- *
- * DESCRIPTION: This macro will create a temporary 32 bit value with the bit field
- * desired set to the desired value.
- *
- * @Param: - IN arg_BitFieldValue is the new value of the bit field. The value can be from 0 to
- * (1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - 1.
- * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant
- * bit of the bit field.
- * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant
- * bit of the bit field.
- *
- * @Return: Returns a temporary ix_uint32 value that has the bit field set to the appropriate value.
- */
-#define IX_MAKE_BIT_FIELD32( \
- arg_BitFieldValue, \
- arg_FieldLSBBit, \
- arg_FieldMSBBit \
- ) \
- (((ix_uint32)(arg_BitFieldValue) << arg_FieldLSBBit) & \
- IX_BIT_FIELD_MASK32(arg_FieldLSBBit, arg_FieldMSBBit))
-
-
-/**
- * MACRO NAME: IX_SET_BIT_FIELD32
- *
- * DESCRIPTION: Sets a new value for a bit field from a 32 bit unsigned integer.
- *
- * @Param: - IN arg_PackedData32 a 32 bit unsigned integer that contains the bit field of interest.
- * @Param: - IN arg_BitFieldValue is the new value of the bit field. The value can be from 0 to
- * (1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - 1.
- * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant
- * bit of the bit field.
- * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant
- * bit of the bit field.
- *
- * @Return: Returns the updated value of arg_PackedData32.
- */
-#define IX_SET_BIT_FIELD32( \
- arg_PackedData32, \
- arg_BitFieldValue, \
- arg_FieldLSBBit, \
- arg_FieldMSBBit \
- ) \
- (arg_PackedData32 = (((ix_uint32)(arg_PackedData32) & \
- ~(IX_BIT_FIELD_MASK32(arg_FieldLSBBit, arg_FieldMSBBit))) | \
- IX_MAKE_BIT_FIELD32(arg_BitFieldValue, arg_FieldLSBBit, arg_FieldMSBBit)))
-
-
-
-#if defined(__cplusplus)
-}
-#endif /* end defined(__cplusplus) */
-
-#endif /* end !defined(__IX_MACROS_H__) */
+++ /dev/null
-/**
- * ============================================================================
- * = COPYRIGHT
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- * = PRODUCT
- * Intel(r) IXP425 Software Release
- *
- * = FILENAME
- * ix_os_type.h (Replaced by OSAL)
- *
- * = DESCRIPTION
- * This file provides protable symbol definitions for the current OS type.
- *
- * = AUTHOR
- * Intel Corporation
- *
- * = CHANGE HISTORY
- * 4/22/2002 4:43:30 PM - creation time
- * ============================================================================
- */
-
-#if !defined(__IX_OS_TYPE_H__)
-#define __IX_OS_TYPE_H__
-
-#include "IxOsalBackward.h"
-
-#endif /* end !defined(__IX_OS_TYPE_H__) */
-
+++ /dev/null
-/**
- * ============================================================================
- * = COPYRIGHT
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- * = PRODUCT
- * Intel(r) IXP425 Software Release
- *
- * = LIBRARY
- * OSSL - Operating System Services Library
- *
- * = MODULE
- * OSSL Abstraction layer header file
- *
- * = FILENAME
- * ix_ossl.h (Replaced by OSAL)
- *
- * = DESCRIPTION
- * This file contains the prototypes of OS-independent wrapper
- * functions which allow the programmer not to be tied to a specific
- * operating system. The OSSL functions can be divided into three classes:
- *
- * 1) synchronization-related wrapper functions around thread system calls
- * 2) thread-related wrapper functions around thread calls
- * 3) transactor/workbench osapi calls -- defined in osApi.h
- *
- * Both 1 and 2 classes of functions provide Thread Management, Thread
- * Synchronization, Mutual Exclusion and Timer primitives. Namely,
- * creation and deletion functions as well as the standard "wait" and
- * "exit". Additionally, a couple of utility functions which enable to
- * pause the execution of a thread are also provided.
- *
- * The 3rd class provides a slew of other OSAPI functions to handle
- * Transactor/WorkBench OS calls.
- *
- *
- * OSSL Thread APIs:
- * The OSSL thread functions that allow for thread creation,
- * get thread id, thread deletion and set thread priroity.
- *
- * ix_ossl_thread_create
- * ix_ossl_thread_get_id
- * ix_ossl_thread_exit
- * ix_ossl_thread_kill
- * ix_ossl_thread_set_priority
- * ix_ossl_thread__delay
- *
- * OSSL Semaphore APIs:
- * The OSSL semaphore functions that allow for initialization,
- * posting, waiting and deletion of semaphores.
- *
- * ix_ossl_sem_init
- * ix_ossl_sem_fini
- * ix_ossl_sem_take
- * ix_ossl_sem_give
- * ix_ossl_sem_flush
- *
- * OSSL Mutex APIs:
- * The OSSL wrapper functions that allow for initialization,
- * posting, waiting and deletion of mutexes.
- *
- * ix_ossl_mutex_init
- * ix_ossl_mutex_fini
- * ix_ossl_mutex_lock
- * ix_ossl_mutex_unlock
- *
- * OSSL Timer APIs:
- * The timer APIs provide sleep and get time functions.
- *
- * ix_ossl_sleep
- * ix_ossl_sleep_tick
- * ix_ossl_time_get
- *
- * OSAPIs for Transactor/WorkBench:
- * These OSAPI functions are used for transator OS calls.
- * They are defined in osApi.h.
- *
- * Sem_Init
- * Sem_Destroy
- * Sem_Wait
- * Sem_Wait
- * Thread_Create
- * Thread_Cancel
- * Thread_SetPriority
- * delayMs
- * delayTick
- *
- *
- *
- **********************************************************************
- *
- *
- * = AUTHOR
- * Intel Corporation
- *
- * = ACKNOWLEDGEMENTS
- *
- *
- * = CREATION TIME
- * 1/8/2002 1:53:42 PM
- *
- * = CHANGE HISTORY
- * 02/22/2002 : Renamed osapi.h os_api.h
- * Moved OS header file includes from OSSL.h to os_api.h
- * Moved OS specific datatypes to os_api.h
- * Modified data types, macros and functions as per
- * 'C' coding guidelines.
- *
- *
- * ============================================================================
- */
-
-#ifndef _IX_OSSL_H
-#ifndef __doxygen_hide
-#define _IX_OSSL_H
-#endif /* __doxygen_hide */
-
-#include "IxOsalBackward.h"
-
-#endif /* _IX_OSSL_H */
-
-/**
- * @} defgroup IxOSSL
- */
+++ /dev/null
-/**
- * ============================================================================
- * = COPYRIGHT
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- * = PRODUCT
- * Intel(r) IXP425 Software Release
- *
- * = FILENAME
- * ix_symbols.h
- *
- * = DESCRIPTION
- * This file declares all the global preprocessor symbols required by
- * the IXA SDK Framework API.
- *
- * = AUTHOR
- * Intel Corporation
- *
- * = CHANGE HISTORY
- * 4/23/2002 10:41:13 AM - creation time
- * ============================================================================
- */
-
-#if !defined(__IX_SYMBOLS_H__)
-#define __IX_SYMBOLS_H__
-
-
-#if defined(__cplusplus)
-extern "C"
-{
-#endif /* end defined(__cplusplus) */
-
-/**
- * The IX_EXPORT_FUNCTION symbol will be used for compilation on different platforms.
- * We are planning to provide a simulation version of the library that should work
- * with the Transactor rather than the hardware. This implementation will be done on
- * WIN32 in the form of a DLL that will need to export functions and symbols.
- */
-#if (_IX_OS_TYPE_ == _IX_OS_WIN32_)
-# if defined(_IX_LIB_INTERFACE_IMPLEMENTATION_)
-# define IX_EXPORT_FUNCTION __declspec( dllexport )
-# elif defined(_IX_LIB_INTERFACE_IMPORT_DLL_)
-# define IX_EXPORT_FUNCTION __declspec( dllimport )
-# else
-# define IX_EXPORT_FUNCTION extern
-# endif
-#elif (_IX_OS_TYPE_ == _IX_OS_WINCE_)
-# define IX_EXPORT_FUNCTION __declspec(dllexport)
-#else
-# define IX_EXPORT_FUNCTION extern
-#endif
-
-
-/**
- * This symbols should be defined when we want to build for a multithreaded environment
- */
-#define _IX_MULTI_THREADED_ 1
-
-
-/**
- * This symbol should be defined in the case we to buils for a multithreaded environment
- * but we want that our modules to work as if they are used in a single threaded environment.
- */
-/* #define _IX_RM_EXPLICIT_SINGLE_THREADED_ 1 */
-
-#if defined(__cplusplus)
-}
-#endif /* end defined(__cplusplus) */
-
-#endif /* end !defined(__IX_SYMBOLS_H__) */
+++ /dev/null
-/**
- * ============================================================================
- * = COPYRIGHT
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- * = PRODUCT
- * Intel(r) IXP425 Software Release
- *
- * = FILENAME
- * ix_types.h
- *
- * = DESCRIPTION
- * This file will define generic types that will guarantee the protability
- * between different architectures and compilers. It should be used the entire
- * IXA SDK Framework API.
- *
- * = AUTHOR
- * Intel Corporation
- *
- * = CHANGE HISTORY
- * 4/22/2002 4:44:17 PM - creation time
- * ============================================================================
- */
-
-#if !defined(__IX_TYPES_H__)
-#define __IX_TYPES_H__
-
-
-#if defined(__cplusplus)
-extern "C"
-{
-#endif /* end defined(__cplusplus) */
-
-
-/**
- * Define generic integral data types that will guarantee the size.
- */
-
-/**
- * TYPENAME: ix_int8
- *
- * DESCRIPTION: This type defines an 8 bit signed integer value.
- *
- */
-typedef signed char ix_int8;
-
-
-/**
- * TYPENAME: ix_uint8
- *
- * DESCRIPTION: This type defines an 8 bit unsigned integer value.
- *
- */
-typedef unsigned char ix_uint8;
-
-
-/**
- * TYPENAME: ix_int16
- *
- * DESCRIPTION: This type defines an 16 bit signed integer value.
- *
- */
-typedef signed short int ix_int16;
-
-
-/**
- * TYPENAME: ix_uint16
- *
- * DESCRIPTION: This type defines an 16 bit unsigned integer value.
- *
- */
-typedef unsigned short int ix_uint16;
-
-
-/**
- * TYPENAME: ix_int32
- *
- * DESCRIPTION: This type defines an 32 bit signed integer value.
- *
- */
-typedef signed int ix_int32;
-
-
-/**
- * TYPENAME: ix_uint32
- *
- * DESCRIPTION: This type defines an 32 bit unsigned integer value.
- *
- */
-#ifndef __wince
-typedef unsigned int ix_uint32;
-#else
-typedef unsigned long ix_uint32;
-#endif
-
-/**
- * TYPENAME: ix_int64
- *
- * DESCRIPTION: This type defines an 64 bit signed integer value.
- *
- */
-#ifndef __wince
-__extension__ typedef signed long long int ix_int64;
-#endif
-
-/**
- * TYPENAME: ix_uint64
- *
- * DESCRIPTION: This type defines an 64 bit unsigned integer value.
- *
- */
-#ifndef __wince
-__extension__ typedef unsigned long long int ix_uint64;
-#endif
-
-
-/**
- * TYPENAME: ix_bit_mask8
- *
- * DESCRIPTION: This is a generic type for a 8 bit mask.
- */
-typedef ix_uint8 ix_bit_mask8;
-
-
-/**
- * TYPENAME: ix_bit_mask16
- *
- * DESCRIPTION: This is a generic type for a 16 bit mask.
- */
-typedef ix_uint16 ix_bit_mask16;
-
-
-/**
- * TYPENAME: ix_bit_mask32
- *
- * DESCRIPTION: This is a generic type for a 32 bit mask.
- */
-typedef ix_uint32 ix_bit_mask32;
-
-
-/**
- * TYPENAME: ix_bit_mask64
- *
- * DESCRIPTION: This is a generic type for a 64 bit mask.
- */
-#ifndef __wince
-typedef ix_uint64 ix_bit_mask64;
-#endif
-
-
-/**
- * TYPENAME: ix_handle
- *
- * DESCRIPTION: This type defines a generic handle.
- *
- */
-typedef ix_uint32 ix_handle;
-
-
-
-/**
- * DESCRIPTION: This symbol defines a NULL handle
- *
- */
-#define IX_NULL_HANDLE ((ix_handle)0)
-
-
-#if defined(__cplusplus)
-}
-#endif /* end defined(__cplusplus) */
-
-#endif /* end !defined(__IX_TYPES_H__) */
+++ /dev/null
-/*
- * (C) Copyright 2005
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef NPE_H
-#define NPE_H
-
-/*
- * defines...
- */
-#define CONFIG_SYS_NPE_NUMS 1
-#ifdef CONFIG_HAS_ETH1
-#undef CONFIG_SYS_NPE_NUMS
-#define CONFIG_SYS_NPE_NUMS 2
-#endif
-
-#define NPE_NUM_PORTS 3
-#define ACTIVE_PORTS 1
-
-#define NPE_PKT_SIZE 1600
-
-#define CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS 64
-#define CONFIG_DEVS_ETH_INTEL_NPE_MAX_TX_DESCRIPTORS 2
-
-#define NPE_MBUF_POOL_SIZE \
- ((CONFIG_DEVS_ETH_INTEL_NPE_MAX_TX_DESCRIPTORS + \
- CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS) * \
- sizeof(IX_OSAL_MBUF) * ACTIVE_PORTS)
-
-#define NPE_PKT_POOL_SIZE \
- ((CONFIG_DEVS_ETH_INTEL_NPE_MAX_TX_DESCRIPTORS + \
- CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS) * \
- NPE_PKT_SIZE * ACTIVE_PORTS)
-
-#define NPE_MEM_POOL_SIZE (NPE_MBUF_POOL_SIZE + NPE_PKT_POOL_SIZE)
-
-#define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */
-
-/*
- * structs...
- */
-struct npe {
- u8 active; /* NPE active */
- u8 eth_id; /* IX_ETH_PORT_1 or IX_ETH_PORT_2 */
- u8 phy_no; /* which PHY (0 - 31) */
- u8 mac_address[6];
-
- IX_OSAL_MBUF *rxQHead;
- IX_OSAL_MBUF *txQHead;
-
- u8 *tx_pkts;
- u8 *rx_pkts;
- IX_OSAL_MBUF *rx_mbufs;
- IX_OSAL_MBUF *tx_mbufs;
-
- int print_speed;
-
- int rx_read;
- int rx_write;
- int rx_len[PKTBUFSRX];
-};
-
-/*
- * prototypes...
- */
-extern int npe_miiphy_read (const char *devname, unsigned char addr,
- unsigned char reg, unsigned short *value);
-extern int npe_miiphy_write (const char *devname, unsigned char addr,
- unsigned char reg, unsigned short value);
-
-#endif /* ifndef NPE_H */
+++ /dev/null
-/**
- * ============================================================================
- * = COPYRIGHT
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- * = PRODUCT
- * Intel(r) IXP425 Software Release
- *
- * = LIBRARY
- * OSSL - Operating System Services Library
- *
- * = MODULE
- * OS Specific Data Types header file
- *
- * = FILENAME
- * OSSL.h (Replaced by OSAL)
- *
- * = DESCRIPTION
- * This file contains definitions and encapsulations for OS specific data types. These
- * encapsulated data types are used by OSSL header files and OS API functions.
- *
- *
- **********************************************************************
- *
- *
- * = AUTHOR
- * Intel Corporation
- *
- * = AKNOWLEDGEMENTS
- *
- *
- * = CREATION TIME
- * 1/8/2002 1:53:42 PM
- *
- * = CHANGE HISTORY
-
- * ============================================================================
- */
-
-#ifndef _OS_DATATYPES_H
-#define _OS_DATATYPES_H
-
-#include "IxOsalBackward.h"
-
-#endif /* _OS_DATATYPES_H */
-
+++ /dev/null
-/*
- * SPDX-License-Identifier: GPL-2.0 IBM-pibs
- */
-/*-----------------------------------------------------------------------------+
- |
- | File Name: miiphy.c
- |
- | Function: This module has utilities for accessing the MII PHY through
- | the EMAC3 macro.
- |
- | Author: Mark Wisner
- |
- | Change Activity-
- |
- | Date Description of Change BY
- | --------- --------------------- ---
- | 05-May-99 Created MKW
- | 01-Jul-99 Changed clock setting of sta_reg from 66MHz to 50MHz to
- | better match OPB speed. Also modified delay times. JWB
- | 29-Jul-99 Added Full duplex support MKW
- | 24-Aug-99 Removed printf from dp83843_duplex() JWB
- | 19-Jul-00 Ported to esd cpci405 sr
- | 23-Dec-03 Ported from miiphy.c to 440GX Travis Sawyer TBS
- | <travis.sawyer@sandburst.com>
- |
- +-----------------------------------------------------------------------------*/
-
-#include <common.h>
-#include <miiphy.h>
-#include "IxOsal.h"
-#include "IxEthAcc.h"
-#include "IxEthAcc_p.h"
-#include "IxEthAccMac_p.h"
-#include "IxEthAccMii_p.h"
-
-/***********************************************************/
-/* Dump out to the screen PHY regs */
-/***********************************************************/
-
-void miiphy_dump (char *devname, unsigned char addr)
-{
- unsigned long i;
- unsigned short data;
-
-
- for (i = 0; i < 0x1A; i++) {
- if (miiphy_read (devname, addr, i, &data)) {
- printf ("read error for reg %lx\n", i);
- return;
- }
- printf ("Phy reg %lx ==> %4x\n", i, data);
-
- /* jump to the next set of regs */
- if (i == 0x07)
- i = 0x0f;
-
- } /* end for loop */
-} /* end dump */
-
-
-/***********************************************************/
-/* (Re)start autonegotiation */
-/***********************************************************/
-int phy_setup_aneg (char *devname, unsigned char addr)
-{
- unsigned short ctl, adv;
-
- /* Setup standard advertise */
- miiphy_read (devname, addr, MII_ADVERTISE, &adv);
- adv |= (LPA_LPACK | LPA_RFAULT | LPA_100BASE4 |
- LPA_100FULL | LPA_100HALF | LPA_10FULL |
- LPA_10HALF);
- miiphy_write (devname, addr, MII_ADVERTISE, adv);
-
- /* Start/Restart aneg */
- miiphy_read (devname, addr, MII_BMCR, &ctl);
- ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
- miiphy_write (devname, addr, MII_BMCR, ctl);
-
- return 0;
-}
-
-
-int npe_miiphy_read (const char *devname, unsigned char addr,
- unsigned char reg, unsigned short *value)
-{
- u16 val;
-
- ixEthAccMiiReadRtn(addr, reg, &val);
- *value = val;
-
- return 0;
-} /* phy_read */
-
-
-int npe_miiphy_write (const char *devname, unsigned char addr,
- unsigned char reg, unsigned short value)
-{
- ixEthAccMiiWriteRtn(addr, reg, value);
- return 0;
-} /* phy_write */
+++ /dev/null
-/*
- * (C) Copyright 2005-2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#if 0
-#define DEBUG /* define for debug output */
-#endif
-
-#include <config.h>
-#include <common.h>
-#include <net.h>
-#include <miiphy.h>
-#include <malloc.h>
-#include <asm/processor.h>
-#include <asm/arch-ixp/ixp425.h>
-
-#include <IxOsal.h>
-#include <IxEthAcc.h>
-#include <IxEthDB.h>
-#include <IxNpeDl.h>
-#include <IxQMgr.h>
-#include <IxNpeMh.h>
-#include <ix_ossl.h>
-#include <IxFeatureCtrl.h>
-
-#include <npe.h>
-
-static IxQMgrDispatcherFuncPtr qDispatcherFunc = NULL;
-static int npe_exists[NPE_NUM_PORTS];
-static int npe_used[NPE_NUM_PORTS];
-
-/* A little extra so we can align to cacheline. */
-static u8 npe_alloc_pool[NPE_MEM_POOL_SIZE + CONFIG_SYS_CACHELINE_SIZE - 1];
-static u8 *npe_alloc_end;
-static u8 *npe_alloc_free;
-
-static void *npe_alloc(int size)
-{
- static int count = 0;
- void *p = NULL;
-
- size = (size + (CONFIG_SYS_CACHELINE_SIZE-1)) & ~(CONFIG_SYS_CACHELINE_SIZE-1);
- count++;
-
- if ((npe_alloc_free + size) < npe_alloc_end) {
- p = npe_alloc_free;
- npe_alloc_free += size;
- } else {
- printf("npe_alloc: failed (count=%d, size=%d)!\n", count, size);
- }
- return p;
-}
-
-/* Not interrupt safe! */
-static void mbuf_enqueue(IX_OSAL_MBUF **q, IX_OSAL_MBUF *new)
-{
- IX_OSAL_MBUF *m = *q;
-
- IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(new) = NULL;
-
- if (m) {
- while(IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m))
- m = IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m);
- IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m) = new;
- } else
- *q = new;
-}
-
-/* Not interrupt safe! */
-static IX_OSAL_MBUF *mbuf_dequeue(IX_OSAL_MBUF **q)
-{
- IX_OSAL_MBUF *m = *q;
- if (m)
- *q = IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m);
- return m;
-}
-
-static void reset_tx_mbufs(struct npe* p_npe)
-{
- IX_OSAL_MBUF *m;
- int i;
-
- p_npe->txQHead = NULL;
-
- for (i = 0; i < CONFIG_DEVS_ETH_INTEL_NPE_MAX_TX_DESCRIPTORS; i++) {
- m = &p_npe->tx_mbufs[i];
-
- memset(m, 0, sizeof(*m));
-
- IX_OSAL_MBUF_MDATA(m) = (void *)&p_npe->tx_pkts[i * NPE_PKT_SIZE];
- IX_OSAL_MBUF_MLEN(m) = IX_OSAL_MBUF_PKT_LEN(m) = NPE_PKT_SIZE;
- mbuf_enqueue(&p_npe->txQHead, m);
- }
-}
-
-static void reset_rx_mbufs(struct npe* p_npe)
-{
- IX_OSAL_MBUF *m;
- int i;
-
- p_npe->rxQHead = NULL;
-
- HAL_DCACHE_INVALIDATE(p_npe->rx_pkts, NPE_PKT_SIZE *
- CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS);
-
- for (i = 0; i < CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS; i++) {
- m = &p_npe->rx_mbufs[i];
-
- memset(m, 0, sizeof(*m));
-
- IX_OSAL_MBUF_MDATA(m) = (void *)&p_npe->rx_pkts[i * NPE_PKT_SIZE];
- IX_OSAL_MBUF_MLEN(m) = IX_OSAL_MBUF_PKT_LEN(m) = NPE_PKT_SIZE;
-
- if(ixEthAccPortRxFreeReplenish(p_npe->eth_id, m) != IX_SUCCESS) {
- printf("ixEthAccPortRxFreeReplenish failed for port %d\n", p_npe->eth_id);
- break;
- }
- }
-}
-
-static void init_rx_mbufs(struct npe* p_npe)
-{
- p_npe->rxQHead = NULL;
-
- p_npe->rx_pkts = npe_alloc(NPE_PKT_SIZE *
- CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS);
- if (p_npe->rx_pkts == NULL) {
- printf("alloc of packets failed.\n");
- return;
- }
-
- p_npe->rx_mbufs = (IX_OSAL_MBUF *)
- npe_alloc(sizeof(IX_OSAL_MBUF) *
- CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS);
- if (p_npe->rx_mbufs == NULL) {
- printf("alloc of mbufs failed.\n");
- return;
- }
-
- reset_rx_mbufs(p_npe);
-}
-
-static void init_tx_mbufs(struct npe* p_npe)
-{
- p_npe->tx_pkts = npe_alloc(NPE_PKT_SIZE *
- CONFIG_DEVS_ETH_INTEL_NPE_MAX_TX_DESCRIPTORS);
- if (p_npe->tx_pkts == NULL) {
- printf("alloc of packets failed.\n");
- return;
- }
-
- p_npe->tx_mbufs = (IX_OSAL_MBUF *)
- npe_alloc(sizeof(IX_OSAL_MBUF) *
- CONFIG_DEVS_ETH_INTEL_NPE_MAX_TX_DESCRIPTORS);
- if (p_npe->tx_mbufs == NULL) {
- printf("alloc of mbufs failed.\n");
- return;
- }
-
- reset_tx_mbufs(p_npe);
-}
-
-/* Convert IX_ETH_PORT_n to IX_NPEMH_NPEID_NPEx */
-static int __eth_to_npe(int eth_id)
-{
- switch(eth_id) {
- case IX_ETH_PORT_1:
- return IX_NPEMH_NPEID_NPEB;
-
- case IX_ETH_PORT_2:
- return IX_NPEMH_NPEID_NPEC;
-
- case IX_ETH_PORT_3:
- return IX_NPEMH_NPEID_NPEA;
- }
- return 0;
-}
-
-/* Poll the CSR machinery. */
-static void npe_poll(int eth_id)
-{
- if (qDispatcherFunc != NULL) {
- ixNpeMhMessagesReceive(__eth_to_npe(eth_id));
- (*qDispatcherFunc)(IX_QMGR_QUELOW_GROUP);
- }
-}
-
-/* ethAcc RX callback */
-static void npe_rx_callback(u32 cbTag, IX_OSAL_MBUF *m, IxEthAccPortId portid)
-{
- struct npe* p_npe = (struct npe *)cbTag;
-
- if (IX_OSAL_MBUF_MLEN(m) > 0) {
- mbuf_enqueue(&p_npe->rxQHead, m);
-
- if (p_npe->rx_write == ((p_npe->rx_read-1) & (PKTBUFSRX-1))) {
- debug("Rx overflow: rx_write=%d rx_read=%d\n",
- p_npe->rx_write, p_npe->rx_read);
- } else {
- debug("Received message #%d (len=%d)\n", p_npe->rx_write,
- IX_OSAL_MBUF_MLEN(m));
- memcpy((void *)NetRxPackets[p_npe->rx_write], IX_OSAL_MBUF_MDATA(m),
- IX_OSAL_MBUF_MLEN(m));
- p_npe->rx_len[p_npe->rx_write] = IX_OSAL_MBUF_MLEN(m);
- p_npe->rx_write++;
- if (p_npe->rx_write == PKTBUFSRX)
- p_npe->rx_write = 0;
-
-#ifdef CONFIG_PRINT_RX_FRAMES
- {
- u8 *ptr = IX_OSAL_MBUF_MDATA(m);
- int i;
-
- for (i=0; i<60; i++) {
- debug("%02x ", *ptr++);
- }
- debug("\n");
- }
-#endif
- }
-
- m = mbuf_dequeue(&p_npe->rxQHead);
- } else {
- debug("Received frame with length 0!!!\n");
- m = mbuf_dequeue(&p_npe->rxQHead);
- }
-
- /* Now return mbuf to NPE */
- IX_OSAL_MBUF_MLEN(m) = IX_OSAL_MBUF_PKT_LEN(m) = NPE_PKT_SIZE;
- IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(m) = NULL;
- IX_OSAL_MBUF_FLAGS(m) = 0;
-
- if(ixEthAccPortRxFreeReplenish(p_npe->eth_id, m) != IX_SUCCESS) {
- debug("npe_rx_callback: Error returning mbuf.\n");
- }
-}
-
-/* ethAcc TX callback */
-static void npe_tx_callback(u32 cbTag, IX_OSAL_MBUF *m)
-{
- struct npe* p_npe = (struct npe *)cbTag;
-
- debug("%s\n", __FUNCTION__);
-
- IX_OSAL_MBUF_MLEN(m) = IX_OSAL_MBUF_PKT_LEN(m) = NPE_PKT_SIZE;
- IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(m) = NULL;
- IX_OSAL_MBUF_FLAGS(m) = 0;
-
- mbuf_enqueue(&p_npe->txQHead, m);
-}
-
-
-static int npe_set_mac_address(struct eth_device *dev)
-{
- struct npe *p_npe = (struct npe *)dev->priv;
- IxEthAccMacAddr npeMac;
-
- debug("%s\n", __FUNCTION__);
-
- /* Set MAC address */
- memcpy(npeMac.macAddress, dev->enetaddr, 6);
-
- if (ixEthAccPortUnicastMacAddressSet(p_npe->eth_id, &npeMac) != IX_ETH_ACC_SUCCESS) {
- printf("Error setting unicast address! %02x:%02x:%02x:%02x:%02x:%02x\n",
- npeMac.macAddress[0], npeMac.macAddress[1],
- npeMac.macAddress[2], npeMac.macAddress[3],
- npeMac.macAddress[4], npeMac.macAddress[5]);
- return 0;
- }
-
- return 1;
-}
-
-/* Boot-time CSR library initialization. */
-static int npe_csr_load(void)
-{
- int i;
-
- if (ixQMgrInit() != IX_SUCCESS) {
- debug("Error initialising queue manager!\n");
- return 0;
- }
-
- ixQMgrDispatcherLoopGet(&qDispatcherFunc);
-
- if(ixNpeMhInitialize(IX_NPEMH_NPEINTERRUPTS_YES) != IX_SUCCESS) {
- printf("Error initialising NPE Message handler!\n");
- return 0;
- }
-
- if (npe_used[IX_ETH_PORT_1] && npe_exists[IX_ETH_PORT_1] &&
- ixNpeDlNpeInitAndStart(IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS)
- != IX_SUCCESS) {
- printf("Error downloading firmware to NPE-B!\n");
- return 0;
- }
-
- if (npe_used[IX_ETH_PORT_2] && npe_exists[IX_ETH_PORT_2] &&
- ixNpeDlNpeInitAndStart(IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS)
- != IX_SUCCESS) {
- printf("Error downloading firmware to NPE-C!\n");
- return 0;
- }
-
- /* don't need this for U-Boot */
- ixFeatureCtrlSwConfigurationWrite(IX_FEATURECTRL_ETH_LEARNING, false);
-
- if (ixEthAccInit() != IX_ETH_ACC_SUCCESS) {
- printf("Error initialising Ethernet access driver!\n");
- return 0;
- }
-
- for (i = 0; i < IX_ETH_ACC_NUMBER_OF_PORTS; i++) {
- if (!npe_used[i] || !npe_exists[i])
- continue;
- if (ixEthAccPortInit(i) != IX_ETH_ACC_SUCCESS) {
- printf("Error initialising Ethernet port%d!\n", i);
- }
- if (ixEthAccTxSchedulingDisciplineSet(i, FIFO_NO_PRIORITY) != IX_ETH_ACC_SUCCESS) {
- printf("Error setting scheduling discipline for port %d.\n", i);
- }
- if (ixEthAccPortRxFrameAppendFCSDisable(i) != IX_ETH_ACC_SUCCESS) {
- printf("Error disabling RX FCS for port %d.\n", i);
- }
- if (ixEthAccPortTxFrameAppendFCSEnable(i) != IX_ETH_ACC_SUCCESS) {
- printf("Error enabling TX FCS for port %d.\n", i);
- }
- }
-
- return 1;
-}
-
-static int npe_init(struct eth_device *dev, bd_t * bis)
-{
- struct npe *p_npe = (struct npe *)dev->priv;
- int i;
- u16 reg_short;
- int speed;
- int duplex;
-
- debug("%s: 1\n", __FUNCTION__);
-
-#ifdef CONFIG_MII_NPE0_FIXEDLINK
- if (0 == p_npe->eth_id) {
- speed = CONFIG_MII_NPE0_SPEED;
- duplex = CONFIG_MII_NPE0_FULLDUPLEX ? FULL : HALF;
- } else
-#endif
-#ifdef CONFIG_MII_NPE1_FIXEDLINK
- if (1 == p_npe->eth_id) {
- speed = CONFIG_MII_NPE1_SPEED;
- duplex = CONFIG_MII_NPE1_FULLDUPLEX ? FULL : HALF;
- } else
-#endif
- {
- miiphy_read(dev->name, p_npe->phy_no, MII_BMSR, ®_short);
-
- /*
- * Wait if PHY is capable of autonegotiation and
- * autonegotiation is not complete
- */
- if ((reg_short & BMSR_ANEGCAPABLE) &&
- !(reg_short & BMSR_ANEGCOMPLETE)) {
- puts("Waiting for PHY auto negotiation to complete");
- i = 0;
- while (!(reg_short & BMSR_ANEGCOMPLETE)) {
- /*
- * Timeout reached ?
- */
- if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
- puts(" TIMEOUT !\n");
- break;
- }
-
- if ((i++ % 1000) == 0) {
- putc('.');
- miiphy_read(dev->name, p_npe->phy_no,
- MII_BMSR, ®_short);
- }
- udelay(1000); /* 1 ms */
- }
- puts(" done\n");
- /* another 500 ms (results in faster booting) */
- udelay(500000);
- }
- speed = miiphy_speed(dev->name, p_npe->phy_no);
- duplex = miiphy_duplex(dev->name, p_npe->phy_no);
- }
-
- if (p_npe->print_speed) {
- p_npe->print_speed = 0;
- printf ("ENET Speed is %d Mbps - %s duplex connection\n",
- (int) speed, (duplex == HALF) ? "HALF" : "FULL");
- }
-
- npe_alloc_end = npe_alloc_pool + sizeof(npe_alloc_pool);
- npe_alloc_free = (u8 *)(((unsigned)npe_alloc_pool +
- CONFIG_SYS_CACHELINE_SIZE - 1) & ~(CONFIG_SYS_CACHELINE_SIZE - 1));
-
- /* initialize mbuf pool */
- init_rx_mbufs(p_npe);
- init_tx_mbufs(p_npe);
-
- if (ixEthAccPortRxCallbackRegister(p_npe->eth_id, npe_rx_callback,
- (u32)p_npe) != IX_ETH_ACC_SUCCESS) {
- printf("can't register RX callback!\n");
- return -1;
- }
-
- if (ixEthAccPortTxDoneCallbackRegister(p_npe->eth_id, npe_tx_callback,
- (u32)p_npe) != IX_ETH_ACC_SUCCESS) {
- printf("can't register TX callback!\n");
- return -1;
- }
-
- npe_set_mac_address(dev);
-
- if (ixEthAccPortEnable(p_npe->eth_id) != IX_ETH_ACC_SUCCESS) {
- printf("can't enable port!\n");
- return -1;
- }
-
- p_npe->active = 1;
-
- return 0;
-}
-
-#if 0 /* test-only: probably have to deal with it when booting linux (for a clean state) */
-/* Uninitialize CSR library. */
-static void npe_csr_unload(void)
-{
- ixEthAccUnload();
- ixEthDBUnload();
- ixNpeMhUnload();
- ixQMgrUnload();
-}
-
-/* callback which is used by ethAcc to recover RX buffers when stopping */
-static void npe_rx_stop_callback(u32 cbTag, IX_OSAL_MBUF *m, IxEthAccPortId portid)
-{
- debug("%s\n", __FUNCTION__);
-}
-
-/* callback which is used by ethAcc to recover TX buffers when stopping */
-static void npe_tx_stop_callback(u32 cbTag, IX_OSAL_MBUF *m)
-{
- debug("%s\n", __FUNCTION__);
-}
-#endif
-
-static void npe_halt(struct eth_device *dev)
-{
- struct npe *p_npe = (struct npe *)dev->priv;
- int i;
-
- debug("%s\n", __FUNCTION__);
-
- /* Delay to give time for recovery of mbufs */
- for (i = 0; i < 100; i++) {
- npe_poll(p_npe->eth_id);
- udelay(100);
- }
-
-#if 0 /* test-only: probably have to deal with it when booting linux (for a clean state) */
- if (ixEthAccPortRxCallbackRegister(p_npe->eth_id, npe_rx_stop_callback,
- (u32)p_npe) != IX_ETH_ACC_SUCCESS) {
- debug("Error registering rx callback!\n");
- }
-
- if (ixEthAccPortTxDoneCallbackRegister(p_npe->eth_id, npe_tx_stop_callback,
- (u32)p_npe) != IX_ETH_ACC_SUCCESS) {
- debug("Error registering tx callback!\n");
- }
-
- if (ixEthAccPortDisable(p_npe->eth_id) != IX_ETH_ACC_SUCCESS) {
- debug("npe_stop: Error disabling NPEB!\n");
- }
-
- /* Delay to give time for recovery of mbufs */
- for (i = 0; i < 100; i++) {
- npe_poll(p_npe->eth_id);
- udelay(10000);
- }
-
- /*
- * For U-Boot only, we are probably launching Linux or other OS that
- * needs a clean slate for its NPE library.
- */
-#if 0 /* test-only */
- for (i = 0; i < IX_ETH_ACC_NUMBER_OF_PORTS; i++) {
- if (npe_used[i] && npe_exists[i])
- if (ixNpeDlNpeStopAndReset(__eth_to_npe(i)) != IX_SUCCESS)
- printf("Failed to stop and reset NPE B.\n");
- }
-#endif
-
-#endif
- p_npe->active = 0;
-}
-
-
-static int npe_send(struct eth_device *dev, void *packet, int len)
-{
- struct npe *p_npe = (struct npe *)dev->priv;
- u8 *dest;
- int err;
- IX_OSAL_MBUF *m;
-
- debug("%s\n", __FUNCTION__);
- m = mbuf_dequeue(&p_npe->txQHead);
- dest = IX_OSAL_MBUF_MDATA(m);
- IX_OSAL_MBUF_PKT_LEN(m) = IX_OSAL_MBUF_MLEN(m) = len;
- IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m) = NULL;
-
- memcpy(dest, (char *)packet, len);
-
- if ((err = ixEthAccPortTxFrameSubmit(p_npe->eth_id, m, IX_ETH_ACC_TX_DEFAULT_PRIORITY))
- != IX_ETH_ACC_SUCCESS) {
- printf("npe_send: Can't submit frame. err[%d]\n", err);
- mbuf_enqueue(&p_npe->txQHead, m);
- return 0;
- }
-
-#ifdef DEBUG_PRINT_TX_FRAMES
- {
- u8 *ptr = IX_OSAL_MBUF_MDATA(m);
- int i;
-
- for (i=0; i<IX_OSAL_MBUF_MLEN(m); i++) {
- printf("%02x ", *ptr++);
- }
- printf(" (tx-len=%d)\n", IX_OSAL_MBUF_MLEN(m));
- }
-#endif
-
- npe_poll(p_npe->eth_id);
-
- return len;
-}
-
-static int npe_rx(struct eth_device *dev)
-{
- struct npe *p_npe = (struct npe *)dev->priv;
-
- debug("%s\n", __FUNCTION__);
- npe_poll(p_npe->eth_id);
-
- debug("%s: rx_write=%d rx_read=%d\n", __FUNCTION__, p_npe->rx_write, p_npe->rx_read);
- while (p_npe->rx_write != p_npe->rx_read) {
- debug("Reading message #%d\n", p_npe->rx_read);
- NetReceive(NetRxPackets[p_npe->rx_read], p_npe->rx_len[p_npe->rx_read]);
- p_npe->rx_read++;
- if (p_npe->rx_read == PKTBUFSRX)
- p_npe->rx_read = 0;
- }
-
- return 0;
-}
-
-int npe_initialize(bd_t * bis)
-{
- static int virgin = 0;
- struct eth_device *dev;
- int eth_num = 0;
- struct npe *p_npe = NULL;
- uchar enetaddr[6];
-
- for (eth_num = 0; eth_num < CONFIG_SYS_NPE_NUMS; eth_num++) {
-
- /* See if we can actually bring up the interface, otherwise, skip it */
-#ifdef CONFIG_HAS_ETH1
- if (eth_num == 1) {
- if (!eth_getenv_enetaddr("eth1addr", enetaddr))
- continue;
- } else
-#endif
- if (!eth_getenv_enetaddr("ethaddr", enetaddr))
- continue;
-
- /* Allocate device structure */
- dev = (struct eth_device *)malloc(sizeof(*dev));
- if (dev == NULL) {
- printf ("%s: Cannot allocate eth_device %d\n", __FUNCTION__, eth_num);
- return -1;
- }
- memset(dev, 0, sizeof(*dev));
-
- /* Allocate our private use data */
- p_npe = (struct npe *)malloc(sizeof(struct npe));
- if (p_npe == NULL) {
- printf("%s: Cannot allocate private hw data for eth_device %d",
- __FUNCTION__, eth_num);
- free(dev);
- return -1;
- }
- memset(p_npe, 0, sizeof(struct npe));
-
- p_npe->eth_id = eth_num;
- memcpy(dev->enetaddr, enetaddr, 6);
-#ifdef CONFIG_HAS_ETH1
- if (eth_num == 1)
- p_npe->phy_no = CONFIG_PHY1_ADDR;
- else
-#endif
- p_npe->phy_no = CONFIG_PHY_ADDR;
-
- sprintf(dev->name, "NPE%d", eth_num);
- dev->priv = (void *)p_npe;
- dev->init = npe_init;
- dev->halt = npe_halt;
- dev->send = npe_send;
- dev->recv = npe_rx;
-
- p_npe->print_speed = 1;
-
- if (0 == virgin) {
- virgin = 1;
-
- if (ixFeatureCtrlDeviceRead() == IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X) {
- switch (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK) {
- case IX_FEATURE_CTRL_SILICON_TYPE_B0:
- default: /* newer than B0 */
- /*
- * If it is B0 or newer Silicon, we
- * only enable port when its
- * corresponding Eth Coprocessor is
- * available.
- */
- if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) ==
- IX_FEATURE_CTRL_COMPONENT_ENABLED)
- npe_exists[IX_ETH_PORT_1] = true;
-
- if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) ==
- IX_FEATURE_CTRL_COMPONENT_ENABLED)
- npe_exists[IX_ETH_PORT_2] = true;
- break;
- case IX_FEATURE_CTRL_SILICON_TYPE_A0:
- /*
- * If it is A0 Silicon, we enable both as both Eth Coprocessors
- * are available.
- */
- npe_exists[IX_ETH_PORT_1] = true;
- npe_exists[IX_ETH_PORT_2] = true;
- break;
- }
- } else if (ixFeatureCtrlDeviceRead() == IX_FEATURE_CTRL_DEVICE_TYPE_IXP46X) {
- if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) ==
- IX_FEATURE_CTRL_COMPONENT_ENABLED)
- npe_exists[IX_ETH_PORT_1] = true;
-
- if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) ==
- IX_FEATURE_CTRL_COMPONENT_ENABLED)
- npe_exists[IX_ETH_PORT_2] = true;
- }
-
- npe_used[IX_ETH_PORT_1] = 1;
- npe_used[IX_ETH_PORT_2] = 1;
-
- npe_alloc_end = npe_alloc_pool + sizeof(npe_alloc_pool);
- npe_alloc_free = (u8 *)(((unsigned)npe_alloc_pool +
- CONFIG_SYS_CACHELINE_SIZE - 1)
- & ~(CONFIG_SYS_CACHELINE_SIZE - 1));
-
- if (!npe_csr_load())
- return 0;
- }
-
- eth_register(dev);
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
- miiphy_register(dev->name, npe_miiphy_read, npe_miiphy_write);
-#endif
-
- } /* end for each supported device */
-
- return 1;
-}
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
+ phydev->supported = phydev->drv->features;
return 0;
}
.uid = 0x4dd074,
.mask = 0xffffffef,
.features = PHY_GBIT_FEATURES,
- .config = ar8021_config,
+ .config = genphy_config,
.startup = genphy_startup,
.shutdown = genphy_shutdown,
};
#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1))))
#elif CONFIG_BLACKFIN
#define SMC_inw(a,r) ({ word __v = (*((volatile word *)((a)->iobase+(r)))); SSYNC(); __v;})
+#elif CONFIG_ARM64
+#define SMC_inw(a, r) (*((volatile word*)((a)->iobase+((dword)(r)))))
#else
-#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+(r))))
+#define SMC_inw(a, r) (*((volatile word*)((a)->iobase+(r))))
#endif
#define SMC_inb(a,r) (((r)&1) ? SMC_inw((a),(r)&~1)>>8 : SMC_inw((a),(r)&0xFF))
#ifdef CONFIG_ADNPESC1
#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+((r)<<1))) = d)
#elif CONFIG_BLACKFIN
-#define SMC_outw(a,d,r) {(*((volatile word *)((a)->iobase+(r))) = d); SSYNC();}
+#define SMC_outw(a, d, r) \
+ ({ (*((volatile word*)((a)->iobase+((r)))) = d); \
+ SSYNC(); \
+ })
+#elif CONFIG_ARM64
+#define SMC_outw(a, d, r) \
+ (*((volatile word*)((a)->iobase+((dword)(r)))) = d)
#else
-#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r))) = d)
+#define SMC_outw(a, d, r) \
+ (*((volatile word*)((a)->iobase+(r))) = d)
#endif
#define SMC_outb(a,d,r) ({ word __d = (byte)(d); \
word __w = SMC_inw((a),(r)&~1); \
phydev->dev->name);
return 0;
}
+ if (!phydev->link) {
+ printf("%s: No link.\n", phydev->dev->name);
+ return 0;
+ }
switch (phydev->speed) {
case 1000:
#define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000
#define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000
+/* Clock frequencies for different speeds */
+#define ZYNQ_GEM_FREQUENCY_10 2500000UL
+#define ZYNQ_GEM_FREQUENCY_100 25000000UL
+#define ZYNQ_GEM_FREQUENCY_1000 125000000UL
+
/* Device registers */
struct zynq_gem_regs {
u32 nwctrl; /* Network Control reg */
static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
{
- u32 i, rclk, clk = 0;
+ u32 i;
+ unsigned long clk_rate = 0;
struct phy_device *phydev;
const u32 stat_size = (sizeof(struct zynq_gem_regs) -
offsetof(struct zynq_gem_regs, stat)) / 4;
phy_config(phydev);
phy_startup(phydev);
+ if (!phydev->link) {
+ printf("%s: No link.\n", phydev->dev->name);
+ return -1;
+ }
+
switch (phydev->speed) {
case SPEED_1000:
writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000,
®s->nwcfg);
- rclk = (0 << 4) | (1 << 0);
- clk = (1 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
+ clk_rate = ZYNQ_GEM_FREQUENCY_1000;
break;
case SPEED_100:
clrsetbits_le32(®s->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000,
ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100);
- rclk = 1 << 0;
- clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
+ clk_rate = ZYNQ_GEM_FREQUENCY_100;
break;
case SPEED_10:
- rclk = 1 << 0;
- /* FIXME untested */
- clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
+ clk_rate = ZYNQ_GEM_FREQUENCY_10;
break;
}
/* Change the rclk and clk only not using EMIO interface */
if (!priv->emio)
zynq_slcr_gem_clk_setup(dev->iobase !=
- ZYNQ_GEM_BASEADDR0, rclk, clk);
+ ZYNQ_GEM_BASEADDR0, clk_rate);
setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
ZYNQ_GEM_NWCTRL_TXEN_MASK);
obj-$(CONFIG_PCI_MSC01) += pci_msc01.o
obj-$(CONFIG_PCIE_IMX) += pcie_imx.o
obj-$(CONFIG_FTPCI100) += pci_ftpci100.o
-obj-$(CONFIG_IXP_PCI) += pci_ixp.o
obj-$(CONFIG_SH4_PCI) += pci_sh4.o
obj-$(CONFIG_SH7751_PCI) +=pci_sh7751.o
obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o
/* Print the negotiated PCIe link width */
pci_hose_read_config_word(hose, dev, pci_lsr, &temp16);
- printf("x%d, regs @ 0x%lx\n", (temp16 & 0x3f0 ) >> 4,
- pci_info->regs);
+ printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4,
+ (temp16 & 0xf), pci_info->regs);
hose->current_busno++; /* Start scan with secondary */
pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
+++ /dev/null
-/*
- * IXP PCI Init
- *
- * (C) Copyright 2011
- * Michael Schwingen, michael@schwingen.org
- * (C) Copyright 2004 eslab.whut.edu.cn
- * Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <pci.h>
-#include <asm/arch/ixp425.h>
-#include <asm/arch/ixp425pci.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void non_prefetch_read(unsigned int addr, unsigned int cmd,
- unsigned int *data);
-static void non_prefetch_write(unsigned int addr, unsigned int cmd,
- unsigned int data);
-
-/*define the sub vendor and subsystem to be used */
-#define IXP425_PCI_SUB_VENDOR_SYSTEM 0x00000000
-
-#define PCI_MEMORY_BUS 0x00000000
-#define PCI_MEMORY_PHY 0x00000000
-#define PCI_MEMORY_SIZE 0x04000000
-
-#define PCI_MEM_BUS 0x48000000
-#define PCI_MEM_PHY 0x00000000
-#define PCI_MEM_SIZE 0x04000000
-
-#define PCI_IO_BUS 0x00000000
-#define PCI_IO_PHY 0x00000000
-#define PCI_IO_SIZE 0x00010000
-
-/* build address value for config sycle */
-static unsigned int pci_config_addr(pci_dev_t bdf, unsigned int reg)
-{
- unsigned int bus = PCI_BUS(bdf);
- unsigned int dev = PCI_DEV(bdf);
- unsigned int func = PCI_FUNC(bdf);
- unsigned int addr;
-
- if (bus) { /* secondary bus, use type 1 config cycle */
- addr = bdf | (reg & ~3) | 1;
- } else {
- /*
- primary bus, type 0 config cycle. address bits 31:28
- specify the device 10:8 specify the function
- */
- addr = BIT((31 - dev)) | (func << 8) | (reg & ~3);
- }
-
- return addr;
-}
-
-static int pci_config_status(void)
-{
- unsigned int regval;
-
- regval = readl(PCI_CSR_BASE + PCI_ISR_OFFSET);
- if ((regval & PCI_ISR_PFE) == 0)
- return OK;
-
- /* no device present, make sure that the master abort bit is reset */
- writel(PCI_ISR_PFE, PCI_CSR_BASE + PCI_ISR_OFFSET);
- return ERROR;
-}
-
-static int pci_ixp_hose_read_config_dword(struct pci_controller *hose,
- pci_dev_t bdf, int where, unsigned int *val)
-{
- unsigned int retval;
- unsigned int addr;
- int stat;
-
- debug("pci_ixp_hose_read_config_dword: bdf %x, reg %x", bdf, where);
- /*Set the address to be read */
- addr = pci_config_addr(bdf, where);
- non_prefetch_read(addr, NP_CMD_CONFIGREAD, &retval);
- *val = retval;
-
- stat = pci_config_status();
- if (stat < 0)
- *val = -1;
- debug("-> val %x, status %x\n", *val, stat);
- return stat;
-}
-
-static int pci_ixp_hose_read_config_word(struct pci_controller *hose,
- pci_dev_t bdf, int where, unsigned short *val)
-{
- unsigned int n;
- unsigned int retval;
- unsigned int addr;
- unsigned int byteEnables;
- int stat;
-
- debug("pci_ixp_hose_read_config_word: bdf %x, reg %x", bdf, where);
- n = where % 4;
- /*byte enables are 4 bits active low, the position of each
- bit maps to the byte that it enables */
- byteEnables =
- (~(BIT(n) | BIT((n + 1)))) &
- IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
- byteEnables = byteEnables << PCI_NP_CBE_BESL;
- /*Set the address to be read */
- addr = pci_config_addr(bdf, where);
- non_prefetch_read(addr, byteEnables | NP_CMD_CONFIGREAD, &retval);
-
- /*Pick out the word we are interested in */
- *val = retval >> (8 * n);
-
- stat = pci_config_status();
- if (stat < 0)
- *val = -1;
- debug("-> val %x, status %x\n", *val, stat);
- return stat;
-}
-
-static int pci_ixp_hose_read_config_byte(struct pci_controller *hose,
- pci_dev_t bdf, int where, unsigned char *val)
-{
- unsigned int retval;
- unsigned int n;
- unsigned int byteEnables;
- unsigned int addr;
- int stat;
-
- debug("pci_ixp_hose_read_config_byte: bdf %x, reg %x", bdf, where);
- n = where % 4;
- /*byte enables are 4 bits, active low, the position of each
- bit maps to the byte that it enables */
- byteEnables = (~BIT(n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
- byteEnables = byteEnables << PCI_NP_CBE_BESL;
-
- /*Set the address to be read */
- addr = pci_config_addr(bdf, where);
- non_prefetch_read(addr, byteEnables | NP_CMD_CONFIGREAD, &retval);
- /*Pick out the byte we are interested in */
- *val = retval >> (8 * n);
-
- stat = pci_config_status();
- if (stat < 0)
- *val = -1;
- debug("-> val %x, status %x\n", *val, stat);
- return stat;
-}
-
-static int pci_ixp_hose_write_config_byte(struct pci_controller *hose,
- pci_dev_t bdf, int where, unsigned char val)
-{
- unsigned int addr;
- unsigned int byteEnables;
- unsigned int n;
- unsigned int ldata;
- int stat;
-
- debug("pci_ixp_hose_write_config_byte: bdf %x, reg %x, val %x",
- bdf, where, val);
- n = where % 4;
- /*byte enables are 4 bits active low, the position of each
- bit maps to the byte that it enables */
- byteEnables = (~BIT(n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
- byteEnables = byteEnables << PCI_NP_CBE_BESL;
- ldata = val << (8 * n);
- /*Set the address to be written */
- addr = pci_config_addr(bdf, where);
- non_prefetch_write(addr, byteEnables | NP_CMD_CONFIGWRITE, ldata);
-
- stat = pci_config_status();
- debug("-> status %x\n", stat);
- return stat;
-}
-
-static int pci_ixp_hose_write_config_word(struct pci_controller *hose,
- pci_dev_t bdf, int where, unsigned short val)
-{
- unsigned int addr;
- unsigned int byteEnables;
- unsigned int n;
- unsigned int ldata;
- int stat;
-
- debug("pci_ixp_hose_write_config_word: bdf %x, reg %x, val %x",
- bdf, where, val);
- n = where % 4;
- /*byte enables are 4 bits active low, the position of each
- bit maps to the byte that it enables */
- byteEnables =
- (~(BIT(n) | BIT((n + 1)))) &
- IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
- byteEnables = byteEnables << PCI_NP_CBE_BESL;
- ldata = val << (8 * n);
- /*Set the address to be written */
- addr = pci_config_addr(bdf, where);
- non_prefetch_write(addr, byteEnables | NP_CMD_CONFIGWRITE, ldata);
-
- stat = pci_config_status();
- debug("-> status %x\n", stat);
- return stat;
-}
-
-static int pci_ixp_hose_write_config_dword(struct pci_controller *hose,
- pci_dev_t bdf, int where, unsigned int val)
-{
- unsigned int addr;
- int stat;
-
- debug("pci_ixp_hose_write_config_dword: bdf %x, reg %x, val %x",
- bdf, where, val);
- /*Set the address to be written */
- addr = pci_config_addr(bdf, where);
- non_prefetch_write(addr, NP_CMD_CONFIGWRITE, val);
-
- stat = pci_config_status();
- debug("-> status %x\n", stat);
- return stat;
-}
-
-static void non_prefetch_read(unsigned int addr,
- unsigned int cmd, unsigned int *data)
-{
- writel(addr, PCI_CSR_BASE + PCI_NP_AD_OFFSET);
-
- /*set up and execute the read */
- writel(cmd, PCI_CSR_BASE + PCI_NP_CBE_OFFSET);
-
- /*The result of the read is now in np_rdata */
- *data = readl(PCI_CSR_BASE + PCI_NP_RDATA_OFFSET);
-
- return;
-}
-
-static void non_prefetch_write(unsigned int addr,
- unsigned int cmd, unsigned int data)
-{
-
- writel(addr, PCI_CSR_BASE + PCI_NP_AD_OFFSET);
- /*set up the write */
- writel(cmd, PCI_CSR_BASE + PCI_NP_CBE_OFFSET);
- /*Execute the write by writing to NP_WDATA */
- writel(data, PCI_CSR_BASE + PCI_NP_WDATA_OFFSET);
-
- return;
-}
-
-static void crp_write(unsigned int offset, unsigned int data)
-{
- /*
- * The CRP address register bit 16 indicates that we want to do a
- * write
- */
- writel(PCI_CRP_WRITE | offset, PCI_CSR_BASE + PCI_CRP_AD_CBE_OFFSET);
- writel(data, PCI_CSR_BASE + PCI_CRP_WDATA_OFFSET);
-}
-
-void pci_ixp_init(struct pci_controller *hose)
-{
- unsigned int csr;
-
- /*
- * Specify that the AHB bus is operating in big endian mode. Set up
- * byte lane swapping between little-endian PCI and the big-endian
- * AHB bus
- */
-#ifdef __ARMEB__
- csr = PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS;
-#else
- csr = PCI_CSR_ABE;
-#endif
- writel(csr, PCI_CSR_BASE + PCI_CSR_OFFSET);
-
- writel(0, PCI_CSR_BASE + PCI_INTEN_OFFSET);
-
- /*
- * We configure the PCI inbound memory windows to be
- * 1:1 mapped to SDRAM
- */
- crp_write(PCI_CFG_BASE_ADDRESS_0, 0x00000000);
- crp_write(PCI_CFG_BASE_ADDRESS_1, 0x01000000);
- crp_write(PCI_CFG_BASE_ADDRESS_2, 0x02000000);
- crp_write(PCI_CFG_BASE_ADDRESS_3, 0x03000000);
-
- /*
- * Enable CSR window at 64 MiB to allow PCI masters
- * to continue prefetching past 64 MiB boundary.
- */
- crp_write(PCI_CFG_BASE_ADDRESS_4, 0x04000000);
- /*
- * Enable the IO window to be way up high, at 0xfffffc00
- */
- crp_write(PCI_CFG_BASE_ADDRESS_5, 0xfffffc01);
-
- /*Setup PCI-AHB and AHB-PCI address mappings */
- writel(0x00010203, PCI_CSR_BASE + PCI_AHBMEMBASE_OFFSET);
-
- writel(0x00000000, PCI_CSR_BASE + PCI_AHBIOBASE_OFFSET);
-
- writel(0x48494a4b, PCI_CSR_BASE + PCI_PCIMEMBASE_OFFSET);
-
- crp_write(PCI_CFG_SUB_VENDOR_ID, IXP425_PCI_SUB_VENDOR_SYSTEM);
-
- crp_write(PCI_CFG_COMMAND, PCI_CFG_CMD_MAE | PCI_CFG_CMD_BME);
- udelay(1000);
-
- /* clear error bits in status register */
- writel(PCI_ISR_PSE | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE,
- PCI_CSR_BASE + PCI_ISR_OFFSET);
-
- /*
- * Set Initialize Complete in PCI Control Register: allow IXP4XX to
- * respond to PCI configuration cycles.
- */
- csr |= PCI_CSR_IC;
- writel(csr, PCI_CSR_BASE + PCI_CSR_OFFSET);
-
- hose->first_busno = 0;
- hose->last_busno = 0;
-
- /* System memory space */
- pci_set_region(hose->regions + 0,
- PCI_MEMORY_BUS,
- PCI_MEMORY_PHY, PCI_MEMORY_SIZE, PCI_REGION_SYS_MEMORY);
-
- /* PCI memory space */
- pci_set_region(hose->regions + 1,
- PCI_MEM_BUS,
- PCI_MEM_PHY, PCI_MEM_SIZE, PCI_REGION_MEM);
- /* PCI I/O space */
- pci_set_region(hose->regions + 2,
- PCI_IO_BUS, PCI_IO_PHY, PCI_IO_SIZE, PCI_REGION_IO);
-
- hose->region_count = 3;
-
- pci_set_ops(hose,
- pci_ixp_hose_read_config_byte,
- pci_ixp_hose_read_config_word,
- pci_ixp_hose_read_config_dword,
- pci_ixp_hose_write_config_byte,
- pci_ixp_hose_write_config_word,
- pci_ixp_hose_write_config_dword);
-
- pci_register_hose(hose);
- hose->last_busno = pci_hose_scan(hose);
-}
#include <common.h>
#include <power/pmic.h>
#include <power/battery.h>
-#include <power/max8997_pmic.h>
+#include <power/max77693_pmic.h>
#include <errno.h>
static struct battery battery_trats;
return CMD_RET_SUCCESS;
}
+ if (argc < 3)
+ return CMD_RET_USAGE;
+
name = argv[1];
cmd = argv[2];
# SPDX-License-Identifier: GPL-2.0+
#
-#CFLAGS += -DDEBUG
+#ccflags-y += -DDEBUG
obj-$(CONFIG_RTC_AT91SAM9_RTT) += at91sam9_rtt.o
obj-$(CONFIG_RTC_BFIN) += bfin_rtc.o
obj-$(CONFIG_S5P) += serial_s5p.o
obj-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o
obj-$(CONFIG_IMX_SERIAL) += serial_imx.o
-obj-$(CONFIG_IXP_SERIAL) += serial_ixp.o
obj-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o
obj-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o
obj-$(CONFIG_MXC_UART) += serial_mxc.o
obj-$(CONFIG_BFIN_SERIAL) += serial_bfin.o
obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o
obj-$(CONFIG_MXS_AUART) += mxs_auart.o
+obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_USB_TTY) += usbtty.o
#include <watchdog.h>
#include <asm/io.h>
#include <nios2-yanu.h>
+#include <serial.h>
DECLARE_GLOBAL_DATA_PTR;
static yanu_uart_t *uart = (yanu_uart_t *)CONFIG_SYS_NIOS_CONSOLE;
-#if defined(CONFIG_SYS_NIOS_FIXEDBAUD)
-
-/* Everything's already setup for fixed-baud PTF assignment*/
-
static void oc_serial_setbrg(void)
{
int n, k;
const unsigned max_uns = 0xFFFFFFFF;
unsigned best_n, best_m, baud;
+ unsigned baudrate;
- /* compute best N and M couple */
- best_n = YANU_MAX_PRESCALER_N;
- for (n = YANU_MAX_PRESCALER_N; n >= 0; n--) {
- if ((unsigned)CONFIG_SYS_CLK_FREQ / (1 << (n + 4)) >=
- (unsigned)CONFIG_BAUDRATE) {
- best_n = n;
- break;
- }
- }
- for (k = 0;; k++) {
- if ((unsigned)CONFIG_BAUDRATE <= (max_uns >> (15+n-k)))
- break;
- }
- best_m =
- ((unsigned)CONFIG_BAUDRATE * (1 << (15 + n - k))) /
- ((unsigned)CONFIG_SYS_CLK_FREQ >> k);
-
- baud = best_m + best_n * YANU_BAUDE;
- writel(baud, &uart->baud);
-
- return;
-}
-
+#if defined(CONFIG_SYS_NIOS_FIXEDBAUD)
+ /* Everything's already setup for fixed-baud PTF assignment */
+ baudrate = CONFIG_BAUDRATE;
#else
-
-static void oc_serial_setbrg(void)
-{
- int n, k;
- const unsigned max_uns = 0xFFFFFFFF;
- unsigned best_n, best_m, baud;
-
+ baudrate = gd->baudrate;
+#endif
/* compute best N and M couple */
best_n = YANU_MAX_PRESCALER_N;
for (n = YANU_MAX_PRESCALER_N; n >= 0; n--) {
if ((unsigned)CONFIG_SYS_CLK_FREQ / (1 << (n + 4)) >=
- gd->baudrate) {
+ baudrate) {
best_n = n;
break;
}
}
for (k = 0;; k++) {
- if (gd->baudrate <= (max_uns >> (15+n-k)))
+ if (baudrate <= (max_uns >> (15+n-k)))
break;
}
best_m =
- (gd->baudrate * (1 << (15 + n - k))) /
+ (baudrate * (1 << (15 + n - k))) /
((unsigned)CONFIG_SYS_CLK_FREQ >> k);
baud = best_m + best_n * YANU_BAUDE;
return;
}
-
-#endif /* CONFIG_SYS_NIOS_FIXEDBAUD */
-
static int oc_serial_init(void)
{
unsigned action,control;
((1 << YANU_RFIFO_CHARS_N) - 1)) > 0);
}
-statoc int oc_serial_getc(void)
+static int oc_serial_getc(void)
{
while (serial_tstc() == 0)
WATCHDOG_RESET ();
serial_initfunc(sandbox_serial_initialize);
serial_initfunc(clps7111_serial_initialize);
serial_initfunc(imx_serial_initialize);
-serial_initfunc(ixp_serial_initialize);
serial_initfunc(ks8695_serial_initialize);
serial_initfunc(lh7a40x_serial_initialize);
serial_initfunc(max3100_serial_initialize);
serial_initfunc(sh_serial_initialize);
serial_initfunc(arm_dcc_initialize);
serial_initfunc(mxs_auart_initialize);
+serial_initfunc(arc_serial_initialize);
/**
* serial_register() - Register serial driver with serial driver core
sandbox_serial_initialize();
clps7111_serial_initialize();
imx_serial_initialize();
- ixp_serial_initialize();
ks8695_serial_initialize();
lh7a40x_serial_initialize();
max3100_serial_initialize();
sh_serial_initialize();
arm_dcc_initialize();
mxs_auart_initialize();
+ arc_serial_initialize();
serial_assign(default_serial_console()->name);
}
--- /dev/null
+/*
+ * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <common.h>
+#include <serial.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct arc_serial_regs {
+ unsigned int id0;
+ unsigned int id1;
+ unsigned int id2;
+ unsigned int id3;
+ unsigned int data;
+ unsigned int status;
+ unsigned int baudl;
+ unsigned int baudh;
+};
+
+/* Bit definitions of STATUS register */
+#define UART_RXEMPTY (1 << 5)
+#define UART_OVERFLOW_ERR (1 << 1)
+#define UART_TXEMPTY (1 << 7)
+
+struct arc_serial_regs *regs;
+
+static void arc_serial_setbrg(void)
+{
+ int arc_console_baud;
+
+ if (!gd->baudrate)
+ gd->baudrate = CONFIG_BAUDRATE;
+
+ arc_console_baud = gd->cpu_clk / (gd->baudrate * 4) - 1;
+ writeb(arc_console_baud & 0xff, ®s->baudl);
+
+#ifdef CONFIG_ARC
+ /*
+ * UART ISS(Instruction Set simulator) emulation has a subtle bug:
+ * A existing value of Baudh = 0 is used as a indication to startup
+ * it's internal state machine.
+ * Thus if baudh is set to 0, 2 times, it chokes.
+ * This happens with BAUD=115200 and the formaula above
+ * Until that is fixed, when running on ISS, we will set baudh to !0
+ */
+ if (gd->arch.running_on_hw)
+ writeb((arc_console_baud & 0xff00) >> 8, ®s->baudh);
+ else
+ writeb(1, ®s->baudh);
+#else
+ writeb((arc_console_baud & 0xff00) >> 8, ®s->baudh);
+#endif
+}
+
+static int arc_serial_init(void)
+{
+ regs = (struct arc_serial_regs *)CONFIG_ARC_UART_BASE;
+ serial_setbrg();
+ return 0;
+}
+
+static void arc_serial_putc(const char c)
+{
+ if (c == '\n')
+ arc_serial_putc('\r');
+
+ while (!(readb(®s->status) & UART_TXEMPTY))
+ ;
+
+ writeb(c, ®s->data);
+}
+
+static int arc_serial_tstc(void)
+{
+ return !(readb(®s->status) & UART_RXEMPTY);
+}
+
+static int arc_serial_getc(void)
+{
+ while (!arc_serial_tstc())
+ ;
+
+ /* Check for overflow errors */
+ if (readb(®s->status) & UART_OVERFLOW_ERR)
+ return 0;
+
+ return readb(®s->data) & 0xFF;
+}
+
+static struct serial_device arc_serial_drv = {
+ .name = "arc_serial",
+ .start = arc_serial_init,
+ .stop = NULL,
+ .setbrg = arc_serial_setbrg,
+ .putc = arc_serial_putc,
+ .puts = default_serial_puts,
+ .getc = arc_serial_getc,
+ .tstc = arc_serial_tstc,
+};
+
+void arc_serial_initialize(void)
+{
+ serial_register(&arc_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &arc_serial_drv;
+}
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/ixp425.h>
-#include <watchdog.h>
-#include <serial.h>
-#include <linux/compiler.h>
-
-/*
- * 14.7456 MHz
- * Baud Rate = --------------
- * 16 x Divisor
- */
-#define SERIAL_CLOCK 921600
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void ixp_serial_setbrg(void)
-{
- unsigned int quot = 0;
- int uart = CONFIG_SYS_IXP425_CONSOLE;
-
- if ((gd->baudrate <= SERIAL_CLOCK) && (SERIAL_CLOCK % gd->baudrate == 0))
- quot = SERIAL_CLOCK / gd->baudrate;
- else
- hang ();
-
- IER(uart) = 0; /* Disable for now */
- FCR(uart) = 0; /* No fifos enabled */
-
- /* set baud rate */
- LCR(uart) = LCR_WLS0 | LCR_WLS1 | LCR_DLAB;
- DLL(uart) = quot & 0xff;
- DLH(uart) = quot >> 8;
- LCR(uart) = LCR_WLS0 | LCR_WLS1;
-#ifdef CONFIG_SERIAL_RTS_ACTIVE
- MCR(uart) = MCR_RTS; /* set RTS active */
-#else
- MCR(uart) = 0; /* set RTS inactive */
-#endif
- IER(uart) = IER_UUE;
-}
-
-/*
- * Initialise the serial port with the given baudrate. The settings
- * are always 8 data bits, no parity, 1 stop bit, no start bits.
- *
- */
-static int ixp_serial_init(void)
-{
- serial_setbrg ();
-
- return (0);
-}
-
-
-/*
- * Output a single byte to the serial port.
- */
-static void ixp_serial_putc(const char c)
-{
- /* wait for room in the tx FIFO on UART */
- while ((LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_TEMT) == 0)
- WATCHDOG_RESET(); /* Reset HW Watchdog, if needed */
-
- THR(CONFIG_SYS_IXP425_CONSOLE) = c;
-
- /* If \n, also do \r */
- if (c == '\n')
- serial_putc ('\r');
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-static int ixp_serial_tstc(void)
-{
- return LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_DR;
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-static int ixp_serial_getc(void)
-{
- while (!(LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_DR))
- WATCHDOG_RESET(); /* Reset HW Watchdog, if needed */
-
- return (char) RBR(CONFIG_SYS_IXP425_CONSOLE) & 0xff;
-}
-
-static struct serial_device ixp_serial_drv = {
- .name = "ixp_serial",
- .start = ixp_serial_init,
- .stop = NULL,
- .setbrg = ixp_serial_setbrg,
- .putc = ixp_serial_putc,
- .puts = default_serial_puts,
- .getc = ixp_serial_getc,
- .tstc = ixp_serial_tstc,
-};
-
-void ixp_serial_initialize(void)
-{
- serial_register(&ixp_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
- return &ixp_serial_drv;
-}
{
struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
- /* enable FIFOs */
- writel(0x1, &uart->ufcon);
+ /* enable FIFOs, auto clear Rx FIFO */
+ writel(0x3, &uart->ufcon);
writel(0, &uart->umcon);
/* 8N1 */
writel(0x3, &uart->ulcon);
#define SR_RX_FIFO_VALID_DATA 0x01 /* data in receive FIFO */
#define SR_RX_FIFO_FULL 0x02 /* receive FIFO full */
+#define ULITE_CONTROL_RST_TX 0x01
+#define ULITE_CONTROL_RST_RX 0x02
+
struct uartlite {
unsigned int rx_fifo;
unsigned int tx_fifo;
unsigned int status;
+ unsigned int control;
};
static struct uartlite *userial_ports[4] = {
static int uartlite_serial_init(const int port)
{
- if (userial_ports[port])
+ struct uartlite *regs = userial_ports[port];
+
+ if (regs) {
+ out_be32(®s->control, 0);
+ out_be32(®s->control,
+ ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX);
+ in_be32(®s->control);
return 0;
+ }
+
return -1;
}
#include <asm/io.h>
#include <linux/compiler.h>
#include <serial.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/hardware.h>
#define ZYNQ_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
#define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
};
static struct uart_zynq *uart_zynq_ports[2] = {
-#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0
- [0] = (struct uart_zynq *)CONFIG_ZYNQ_SERIAL_BASEADDR0,
+ [0] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR0,
+ [1] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR1,
+};
+
+#if !defined(CONFIG_ZYNQ_SERIAL_BAUDRATE0)
+# define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE
#endif
-#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR1
- [1] = (struct uart_zynq *)CONFIG_ZYNQ_SERIAL_BASEADDR1,
+#if !defined(CONFIG_ZYNQ_SERIAL_BAUDRATE1)
+# define CONFIG_ZYNQ_SERIAL_BAUDRATE1 CONFIG_BAUDRATE
#endif
-};
struct uart_zynq_params {
u32 baudrate;
- u32 clock;
};
static struct uart_zynq_params uart_zynq_ports_param[2] = {
-#if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE0) && defined(CONFIG_ZYNQ_SERIAL_CLOCK0)
[0].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE0,
- [0].clock = CONFIG_ZYNQ_SERIAL_CLOCK0,
-#endif
-#if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE1) && defined(CONFIG_ZYNQ_SERIAL_CLOCK1)
[1].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE1,
- [1].clock = CONFIG_ZYNQ_SERIAL_CLOCK1,
-#endif
};
/* Set up the baud rate in gd struct */
unsigned int calc_bauderror, bdiv, bgen;
unsigned long calc_baud = 0;
unsigned long baud = uart_zynq_ports_param[port].baudrate;
- unsigned long clock = uart_zynq_ports_param[port].clock;
+ unsigned long clock = get_uart_clk(port);
struct uart_zynq *regs = uart_zynq_ports[port];
/* master clock
__weak struct serial_device *default_serial_console(void)
{
+#if defined(CONFIG_ZYNQ_SERIAL_UART0)
if (uart_zynq_ports[0])
return &uart_zynq_serial0_device;
+#endif
+#if defined(CONFIG_ZYNQ_SERIAL_UART1)
if (uart_zynq_ports[1])
return &uart_zynq_serial1_device;
-
+#endif
return NULL;
}
void zynq_serial_initalize(void)
{
-#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0
serial_register(&uart_zynq_serial0_device);
-#endif
-#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR1
serial_register(&uart_zynq_serial1_device);
-#endif
}
#include <usb/pxa27x_udc.h>
#elif defined(CONFIG_DW_UDC)
#include <usb/designware_udc.h>
-#elif defined(CONFIG_MV_UDC)
-#include <usb/mv_udc.h>
+#elif defined(CONFIG_CI_UDC)
+#include <usb/ci_udc.h>
#endif
#include <usb/udc.h>
#include <spi.h>
#include <asm/blackfin.h>
+#include <asm/clock.h>
#include <asm/gpio.h>
#include <asm/portmux.h>
#include <asm/mach-common/bits/spi.h>
void spi_set_speed(struct spi_slave *slave, uint hz)
{
struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
- ulong sclk;
+ ulong clk;
u32 baud;
- sclk = get_sclk();
+ clk = get_spi_clk();
/* baud should be rounded up */
- baud = DIV_ROUND_UP(sclk, 2 * hz);
+ baud = DIV_ROUND_UP(clk, 2 * hz);
if (baud < 2)
baud = 2;
else if (baud > (u16)-1)
#include <spi.h>
#include <asm/blackfin.h>
+#include <asm/clock.h>
#include <asm/gpio.h>
#include <asm/portmux.h>
#include <asm/mach-common/bits/spi6xx.h>
void spi_set_speed(struct spi_slave *slave, uint hz)
{
struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
- ulong sclk;
+ ulong clk;
u32 clock;
- sclk = get_sclk1();
- clock = sclk / hz;
+ clk = get_spi_clk();
+ clock = clk / hz;
if (clock)
clock--;
bss->clock = clock;
{
u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
s32 reg_ctrl, reg_config;
- u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, pre_div = 0, post_div = 0;
+ u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0;
+ u32 pre_div = 0, post_div = 0;
struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
if (max_hz == 0) {
if (mode & SPI_CS_HIGH)
ss_pol = 1;
- if (mode & SPI_CPOL)
+ if (mode & SPI_CPOL) {
sclkpol = 1;
+ sclkctl = 1;
+ }
if (mode & SPI_CPHA)
sclkpha = 1;
(ss_pol << (cs + MXC_CSPICON_SSPOL));
reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) |
(sclkpol << (cs + MXC_CSPICON_POL));
+ reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) |
+ (sclkctl << (cs + MXC_CSPICON_CTL));
reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) |
(sclkpha << (cs + MXC_CSPICON_PHA));
#include <asm/arch/omap.h>
#include <malloc.h>
#include <spi.h>
+#include <asm/gpio.h>
+#include <asm/omap_gpio.h>
/* ti qpsi register bit masks */
#define QSPI_TIMEOUT 2000000
#define MM_SWITCH 0x01
#define MEM_CS 0x100
#define MEM_CS_UNSELECT 0xfffff0ff
-#define MMAP_START_ADDR 0x5c000000
+#define MMAP_START_ADDR_DRA 0x5c000000
+#define MMAP_START_ADDR_AM43x 0x30000000
#define CORE_CTRL_IO 0x4a002558
#define QSPI_CMD_READ (0x3 << 0)
struct spi_slave *slave = &qslave->slave;
u32 memval = 0;
- slave->memory_map = (void *)MMAP_START_ADDR;
+#ifdef CONFIG_DRA7XX
+ slave->memory_map = (void *)MMAP_START_ADDR_DRA;
+#else
+ slave->memory_map = (void *)MMAP_START_ADDR_AM43x;
+#endif
memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
{
struct ti_qspi_slave *qslave;
+#ifdef CONFIG_AM43XX
+ gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
+ gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
+#endif
+
qslave = spi_alloc_slave(struct ti_qspi_slave, bus, cs);
if (!qslave) {
printf("SPI_error: Fail to allocate ti_qspi_slave\n");
const uchar *txp = dout;
uchar *rxp = din;
uint status;
- int timeout, val;
+ int timeout;
+
+#ifdef CONFIG_DRA7XX
+ int val;
+#endif
debug("spi_xfer: bus:%i cs:%i bitlen:%i words:%i flags:%lx\n",
slave->bus, slave->cs, bitlen, words, flags);
/* Setup mmap flags */
if (flags & SPI_XFER_MMAP) {
writel(MM_SWITCH, &qslave->base->memswitch);
+#ifdef CONFIG_DRA7XX
val = readl(CORE_CTRL_IO);
val |= MEM_CS;
writel(val, CORE_CTRL_IO);
+#endif
return 0;
} else if (flags & SPI_XFER_MMAP_END) {
writel(~MM_SWITCH, &qslave->base->memswitch);
+#ifdef CONFIG_DRA7XX
val = readl(CORE_CTRL_IO);
val &= MEM_CS_UNSELECT;
writel(val, CORE_CTRL_IO);
+#endif
return 0;
}
qslave->cmd |= QSPI_3_PIN;
qslave->cmd |= 0xfff;
+/* FIXME: This delay is required for successfull
+ * completion of read/write/erase. Once its root
+ * caused, it will be remove from the driver.
+ */
+#ifdef CONFIG_AM43XX
+ udelay(100);
+#endif
while (words--) {
if (txp) {
debug("tx cmd %08x dc %08x data %02x\n",
const unsigned char *txp = dout;
unsigned char *rxp = din;
unsigned rxecount = 17; /* max. 16 elements in FIFO, leftover 1 */
+ unsigned global_timeout;
debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
slave->bus, slave->cs, bitlen, bytes, flags);
if (flags & SPI_XFER_BEGIN)
spi_cs_activate(slave);
- while (bytes--) {
- unsigned timeout = /* at least 1usec or greater, leftover 1 */
- xilspi->freq > XILSPI_MAX_XFER_BITS * 1000000 ? 2 :
+ /* at least 1usec or greater, leftover 1 */
+ global_timeout = xilspi->freq > XILSPI_MAX_XFER_BITS * 1000000 ? 2 :
(XILSPI_MAX_XFER_BITS * 1000000 / xilspi->freq) + 1;
+ while (bytes--) {
+ unsigned timeout = global_timeout;
/* get Tx element from data out buffer and count up */
unsigned char d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL;
debug("%s: tx:%x ", __func__, d);
ifdef CONFIG_USB_ETHER
obj-y += ether.o
obj-$(CONFIG_USB_ETH_RNDIS) += rndis.o
-obj-$(CONFIG_MV_UDC) += mv_udc.o
+obj-$(CONFIG_CI_UDC) += ci_udc.o
obj-$(CONFIG_CPU_PXA25X) += pxa25x_udc.o
else
# Devices not related to the new gadget layer depend on CONFIG_USB_DEVICE
#include <linux/types.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
-#include <usb/mv_udc.h>
+#include <usb/ci_udc.h>
#include "../host/ehci.h"
-#include "mv_udc.h"
+#include "ci_udc.h"
/*
* Check if the system has too long cachelines. If the cachelines are
.bmAttributes = USB_ENDPOINT_XFER_CONTROL,
};
-static int mv_pullup(struct usb_gadget *gadget, int is_on);
-static int mv_ep_enable(struct usb_ep *ep,
+static int ci_pullup(struct usb_gadget *gadget, int is_on);
+static int ci_ep_enable(struct usb_ep *ep,
const struct usb_endpoint_descriptor *desc);
-static int mv_ep_disable(struct usb_ep *ep);
-static int mv_ep_queue(struct usb_ep *ep,
+static int ci_ep_disable(struct usb_ep *ep);
+static int ci_ep_queue(struct usb_ep *ep,
struct usb_request *req, gfp_t gfp_flags);
static struct usb_request *
-mv_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags);
-static void mv_ep_free_request(struct usb_ep *ep, struct usb_request *_req);
+ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags);
+static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *_req);
-static struct usb_gadget_ops mv_udc_ops = {
- .pullup = mv_pullup,
+static struct usb_gadget_ops ci_udc_ops = {
+ .pullup = ci_pullup,
};
-static struct usb_ep_ops mv_ep_ops = {
- .enable = mv_ep_enable,
- .disable = mv_ep_disable,
- .queue = mv_ep_queue,
- .alloc_request = mv_ep_alloc_request,
- .free_request = mv_ep_free_request,
+static struct usb_ep_ops ci_ep_ops = {
+ .enable = ci_ep_enable,
+ .disable = ci_ep_disable,
+ .queue = ci_ep_queue,
+ .alloc_request = ci_ep_alloc_request,
+ .free_request = ci_ep_free_request,
};
/* Init values for USB endpoints. */
-static const struct usb_ep mv_ep_init[2] = {
+static const struct usb_ep ci_ep_init[2] = {
[0] = { /* EP 0 */
.maxpacket = 64,
.name = "ep0",
- .ops = &mv_ep_ops,
+ .ops = &ci_ep_ops,
},
[1] = { /* EP 1..n */
.maxpacket = 512,
.name = "ep-",
- .ops = &mv_ep_ops,
+ .ops = &ci_ep_ops,
},
};
-static struct mv_drv controller = {
+static struct ci_drv controller = {
.gadget = {
- .name = "mv_udc",
- .ops = &mv_udc_ops,
+ .name = "ci_udc",
+ .ops = &ci_udc_ops,
.is_dualspeed = 1,
},
};
/**
- * mv_get_qh() - return queue head for endpoint
+ * ci_get_qh() - return queue head for endpoint
* @ep_num: Endpoint number
* @dir_in: Direction of the endpoint (IN = 1, OUT = 0)
*
* This function returns the QH associated with particular endpoint
* and it's direction.
*/
-static struct ept_queue_head *mv_get_qh(int ep_num, int dir_in)
+static struct ept_queue_head *ci_get_qh(int ep_num, int dir_in)
{
return &controller.epts[(ep_num * 2) + dir_in];
}
/**
- * mv_get_qtd() - return queue item for endpoint
+ * ci_get_qtd() - return queue item for endpoint
* @ep_num: Endpoint number
* @dir_in: Direction of the endpoint (IN = 1, OUT = 0)
*
* This function returns the QH associated with particular endpoint
* and it's direction.
*/
-static struct ept_queue_item *mv_get_qtd(int ep_num, int dir_in)
+static struct ept_queue_item *ci_get_qtd(int ep_num, int dir_in)
{
return controller.items[(ep_num * 2) + dir_in];
}
/**
- * mv_flush_qh - flush cache over queue head
+ * ci_flush_qh - flush cache over queue head
* @ep_num: Endpoint number
*
* This function flushes cache over QH for particular endpoint.
*/
-static void mv_flush_qh(int ep_num)
+static void ci_flush_qh(int ep_num)
{
- struct ept_queue_head *head = mv_get_qh(ep_num, 0);
+ struct ept_queue_head *head = ci_get_qh(ep_num, 0);
const uint32_t start = (uint32_t)head;
const uint32_t end = start + 2 * sizeof(*head);
}
/**
- * mv_invalidate_qh - invalidate cache over queue head
+ * ci_invalidate_qh - invalidate cache over queue head
* @ep_num: Endpoint number
*
* This function invalidates cache over QH for particular endpoint.
*/
-static void mv_invalidate_qh(int ep_num)
+static void ci_invalidate_qh(int ep_num)
{
- struct ept_queue_head *head = mv_get_qh(ep_num, 0);
+ struct ept_queue_head *head = ci_get_qh(ep_num, 0);
uint32_t start = (uint32_t)head;
uint32_t end = start + 2 * sizeof(*head);
}
/**
- * mv_flush_qtd - flush cache over queue item
+ * ci_flush_qtd - flush cache over queue item
* @ep_num: Endpoint number
*
* This function flushes cache over qTD pair for particular endpoint.
*/
-static void mv_flush_qtd(int ep_num)
+static void ci_flush_qtd(int ep_num)
{
- struct ept_queue_item *item = mv_get_qtd(ep_num, 0);
+ struct ept_queue_item *item = ci_get_qtd(ep_num, 0);
const uint32_t start = (uint32_t)item;
const uint32_t end_raw = start + 2 * sizeof(*item);
const uint32_t end = roundup(end_raw, ARCH_DMA_MINALIGN);
}
/**
- * mv_invalidate_qtd - invalidate cache over queue item
+ * ci_invalidate_qtd - invalidate cache over queue item
* @ep_num: Endpoint number
*
* This function invalidates cache over qTD pair for particular endpoint.
*/
-static void mv_invalidate_qtd(int ep_num)
+static void ci_invalidate_qtd(int ep_num)
{
- struct ept_queue_item *item = mv_get_qtd(ep_num, 0);
+ struct ept_queue_item *item = ci_get_qtd(ep_num, 0);
const uint32_t start = (uint32_t)item;
const uint32_t end_raw = start + 2 * sizeof(*item);
const uint32_t end = roundup(end_raw, ARCH_DMA_MINALIGN);
}
static struct usb_request *
-mv_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags)
+ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags)
{
- struct mv_ep *mv_ep = container_of(ep, struct mv_ep, ep);
- return &mv_ep->req;
+ struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
+ return &ci_ep->req;
}
-static void mv_ep_free_request(struct usb_ep *ep, struct usb_request *_req)
+static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *_req)
{
return;
}
static void ep_enable(int num, int in, int maxpacket)
{
- struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor;
+ struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
unsigned n;
n = readl(&udc->epctrl[num]);
n |= (CTRL_RXE | CTRL_RXR | CTRL_RXT_BULK);
if (num != 0) {
- struct ept_queue_head *head = mv_get_qh(num, in);
+ struct ept_queue_head *head = ci_get_qh(num, in);
head->config = CONFIG_MAX_PKT(maxpacket) | CONFIG_ZLT;
- mv_flush_qh(num);
+ ci_flush_qh(num);
}
writel(n, &udc->epctrl[num]);
}
-static int mv_ep_enable(struct usb_ep *ep,
+static int ci_ep_enable(struct usb_ep *ep,
const struct usb_endpoint_descriptor *desc)
{
- struct mv_ep *mv_ep = container_of(ep, struct mv_ep, ep);
+ struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
int num, in;
num = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
in = (desc->bEndpointAddress & USB_DIR_IN) != 0;
- mv_ep->desc = desc;
+ ci_ep->desc = desc;
if (num) {
int max = get_unaligned_le16(&desc->wMaxPacketSize);
return 0;
}
-static int mv_ep_disable(struct usb_ep *ep)
+static int ci_ep_disable(struct usb_ep *ep)
{
- struct mv_ep *mv_ep = container_of(ep, struct mv_ep, ep);
+ struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
- mv_ep->desc = NULL;
+ ci_ep->desc = NULL;
return 0;
}
-static int mv_bounce(struct mv_ep *ep, int in)
+static int ci_bounce(struct ci_ep *ep, int in)
{
uint32_t addr = (uint32_t)ep->req.buf;
uint32_t ba;
return 0;
}
-static void mv_debounce(struct mv_ep *ep, int in)
+static void ci_debounce(struct ci_ep *ep, int in)
{
uint32_t addr = (uint32_t)ep->req.buf;
uint32_t ba = (uint32_t)ep->b_buf;
free(ep->b_buf);
}
-static int mv_ep_queue(struct usb_ep *ep,
+static int ci_ep_queue(struct usb_ep *ep,
struct usb_request *req, gfp_t gfp_flags)
{
- struct mv_ep *mv_ep = container_of(ep, struct mv_ep, ep);
- struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor;
+ struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
+ struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
struct ept_queue_item *item;
struct ept_queue_head *head;
int bit, num, len, in, ret;
- num = mv_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
- in = (mv_ep->desc->bEndpointAddress & USB_DIR_IN) != 0;
- item = mv_get_qtd(num, in);
- head = mv_get_qh(num, in);
+ num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
+ in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0;
+ item = ci_get_qtd(num, in);
+ head = ci_get_qh(num, in);
len = req->length;
- ret = mv_bounce(mv_ep, in);
+ ret = ci_bounce(ci_ep, in);
if (ret)
return ret;
item->next = TERMINATE;
item->info = INFO_BYTES(len) | INFO_IOC | INFO_ACTIVE;
- item->page0 = (uint32_t)mv_ep->b_buf;
- item->page1 = ((uint32_t)mv_ep->b_buf & 0xfffff000) + 0x1000;
- mv_flush_qtd(num);
+ item->page0 = (uint32_t)ci_ep->b_buf;
+ item->page1 = ((uint32_t)ci_ep->b_buf & 0xfffff000) + 0x1000;
+ ci_flush_qtd(num);
head->next = (unsigned) item;
head->info = 0;
DBG("ept%d %s queue len %x, buffer %p\n",
- num, in ? "in" : "out", len, mv_ep->b_buf);
- mv_flush_qh(num);
+ num, in ? "in" : "out", len, ci_ep->b_buf);
+ ci_flush_qh(num);
if (in)
bit = EPT_TX(num);
return 0;
}
-static void handle_ep_complete(struct mv_ep *ep)
+static void handle_ep_complete(struct ci_ep *ep)
{
struct ept_queue_item *item;
int num, in, len;
in = (ep->desc->bEndpointAddress & USB_DIR_IN) != 0;
if (num == 0)
ep->desc = &ep0_out_desc;
- item = mv_get_qtd(num, in);
- mv_invalidate_qtd(num);
+ item = ci_get_qtd(num, in);
+ ci_invalidate_qtd(num);
if (item->info & 0xff)
printf("EP%d/%s FAIL info=%x pg0=%x\n",
len = (item->info >> 16) & 0x7fff;
ep->req.length -= len;
- mv_debounce(ep, in);
+ ci_debounce(ep, in);
DBG("ept%d %s complete %x\n",
num, in ? "in" : "out", len);
static void handle_setup(void)
{
struct usb_request *req = &controller.ep[0].req;
- struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor;
+ struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
struct ept_queue_head *head;
struct usb_ctrlrequest r;
int status = 0;
int num, in, _num, _in, i;
char *buf;
- head = mv_get_qh(0, 0); /* EP0 OUT */
+ head = ci_get_qh(0, 0); /* EP0 OUT */
- mv_invalidate_qh(0);
+ ci_invalidate_qh(0);
memcpy(&r, head->setup_data, sizeof(struct usb_ctrlrequest));
writel(EPT_RX(0), &udc->epstat);
DBG("handle setup %s, %x, %x index %x value %x\n", reqname(r.bRequest),
if ((r.wValue == 0) && (r.wLength == 0)) {
req->length = 0;
for (i = 0; i < NUM_ENDPOINTS; i++) {
- struct mv_ep *ep = &controller.ep[i];
+ struct ci_ep *ep = &controller.ep[i];
if (!ep->desc)
continue;
{
int i, num, in;
struct ept_queue_head *head;
- struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor;
+ struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
writel(readl(&udc->epcomp), &udc->epcomp);
writel(readl(&udc->epstat), &udc->epstat);
writel(0xffffffff, &udc->epflush);
& USB_ENDPOINT_NUMBER_MASK;
in = (controller.ep[i].desc->bEndpointAddress
& USB_DIR_IN) != 0;
- head = mv_get_qh(num, in);
+ head = ci_get_qh(num, in);
head->info = INFO_ACTIVE;
- mv_flush_qh(num);
+ ci_flush_qh(num);
}
}
}
void udc_irq(void)
{
- struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor;
+ struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
unsigned n = readl(&udc->usbsts);
writel(n, &udc->usbsts);
int bit, i, num, in;
int usb_gadget_handle_interrupts(void)
{
u32 value;
- struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor;
+ struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
value = readl(&udc->usbsts);
if (value)
return value;
}
-static int mv_pullup(struct usb_gadget *gadget, int is_on)
+static int ci_pullup(struct usb_gadget *gadget, int is_on)
{
- struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor;
+ struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
if (is_on) {
/* RESET */
writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RST, &udc->usbcmd);
void udc_disconnect(void)
{
- struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor;
+ struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
/* disable pullup */
stop_activity();
writel(USBCMD_FS2, &udc->usbcmd);
controller.driver->disconnect(&controller.gadget);
}
-static int mvudc_probe(void)
+static int ci_udc_probe(void)
{
struct ept_queue_head *head;
uint8_t *imem;
controller.items[i] = (struct ept_queue_item *)imem;
if (i & 1) {
- mv_flush_qh(i - 1);
- mv_flush_qtd(i - 1);
+ ci_flush_qh(i - 1);
+ ci_flush_qtd(i - 1);
}
}
INIT_LIST_HEAD(&controller.gadget.ep_list);
/* Init EP 0 */
- memcpy(&controller.ep[0].ep, &mv_ep_init[0], sizeof(*mv_ep_init));
+ memcpy(&controller.ep[0].ep, &ci_ep_init[0], sizeof(*ci_ep_init));
controller.ep[0].desc = &ep0_in_desc;
controller.gadget.ep0 = &controller.ep[0].ep;
INIT_LIST_HEAD(&controller.gadget.ep0->ep_list);
/* Init EP 1..n */
for (i = 1; i < NUM_ENDPOINTS; i++) {
- memcpy(&controller.ep[i].ep, &mv_ep_init[1],
- sizeof(*mv_ep_init));
+ memcpy(&controller.ep[i].ep, &ci_ep_init[1],
+ sizeof(*ci_ep_init));
list_add_tail(&controller.ep[i].ep.ep_list,
&controller.gadget.ep_list);
}
int usb_gadget_register_driver(struct usb_gadget_driver *driver)
{
- struct mv_udc *udc;
+ struct ci_udc *udc;
int ret;
if (!driver)
if (ret)
return ret;
- ret = mvudc_probe();
+ ret = ci_udc_probe();
if (!ret) {
- udc = (struct mv_udc *)controller.ctrl->hcor;
+ udc = (struct ci_udc *)controller.ctrl->hcor;
/* select ULPI phy */
writel(PTS(PTS_ENABLE) | PFSC, &udc->portsc);
*
* Licensed under the GPL-2 or later.
*/
-#ifndef __GADGET__MV_UDC_H__
-#define __GADGET__MV_UDC_H__
+#ifndef __GADGET__CI_UDC_H__
+#define __GADGET__CI_UDC_H__
#define NUM_ENDPOINTS 6
-struct mv_udc {
+struct ci_udc {
#define MICRO_8FRAME 0x8
#define USBCMD_ITC(x) ((((x) > 0xff) ? 0xff : x) << 16)
#define USBCMD_FS2 (1 << 15)
u32 epctrl[16]; /* 0x1c0 */
};
-struct mv_ep {
+struct ci_ep {
struct usb_ep ep;
struct list_head queue;
const struct usb_endpoint_descriptor *desc;
uint8_t b_fast[64] __aligned(ARCH_DMA_MINALIGN);
};
-struct mv_drv {
+struct ci_drv {
struct usb_gadget gadget;
struct usb_gadget_driver *driver;
struct ehci_ctrl *ctrl;
struct ept_queue_head *epts;
struct ept_queue_item *items[2 * NUM_ENDPOINTS];
uint8_t *items_mem;
- struct mv_ep ep[NUM_ENDPOINTS];
+ struct ci_ep ep[NUM_ENDPOINTS];
};
struct ept_queue_head {
buffhds_first_it:
bh->inreq_busy = 0;
bh->outreq_busy = 0;
- bh->buf = kmalloc(FSG_BUFLEN, GFP_KERNEL);
+ bh->buf = memalign(CONFIG_SYS_CACHELINE_SIZE, FSG_BUFLEN);
if (unlikely(!bh->buf)) {
rc = -ENOMEM;
goto error_release;
bytes += (*tmp)->bLength;
bytes += (n_desc + 1) * sizeof(*tmp);
- mem = kmalloc(bytes, GFP_KERNEL);
+ mem = memalign(CONFIG_SYS_CACHELINE_SIZE, bytes);
if (!mem)
return NULL;
{
struct usb_request *req;
- req = alloc_ep_req(ep, ep->maxpacket);
+ req = alloc_ep_req(ep, THOR_PACKET_SIZE);
debug("%s: ep:%p req:%p\n", __func__, ep, req);
if (!req)
memset(req->buf, 0, req->length);
req->complete = thor_rx_tx_complete;
- memset(req->buf, 0x55, req->length);
-
return req;
}
#define gadget_is_m66592(g) 0
#endif
-#ifdef CONFIG_MV_UDC
-#define gadget_is_mv(g) (!strcmp("mv_udc", (g)->name))
+#ifdef CONFIG_CI_UDC
+#define gadget_is_ci(g) (!strcmp("ci_udc", (g)->name))
#else
-#define gadget_is_mv(g) 0
+#define gadget_is_ci(g) 0
#endif
#ifdef CONFIG_USB_GADGET_FOTG210
return 0x19;
else if (gadget_is_m66592(gadget))
return 0x20;
- else if (gadget_is_mv(gadget))
+ else if (gadget_is_ci(gadget))
return 0x21;
else if (gadget_is_fotg210(gadget))
return 0x22;
int s3c_udc_probe(struct s3c_plat_otg_data *pdata)
{
struct s3c_udc *dev = &memory;
- int retval = 0, i;
+ int retval = 0;
debug("%s: %p\n", __func__, pdata);
the_controller = dev;
- for (i = 0; i < S3C_MAX_ENDPOINTS+1; i++) {
- dev->dma_buf[i] = memalign(CONFIG_SYS_CACHELINE_SIZE,
- DMA_BUFFER_SIZE);
- dev->dma_addr[i] = (dma_addr_t) dev->dma_buf[i];
- invalidate_dcache_range((unsigned long) dev->dma_buf[i],
- (unsigned long) (dev->dma_buf[i]
- + DMA_BUFFER_SIZE));
+ usb_ctrl = memalign(CONFIG_SYS_CACHELINE_SIZE,
+ ROUND(sizeof(struct usb_ctrlrequest),
+ CONFIG_SYS_CACHELINE_SIZE));
+ if (!usb_ctrl) {
+ error("No memory available for UDC!\n");
+ return -ENOMEM;
}
- usb_ctrl = dev->dma_buf[0];
- usb_ctrl_dma_addr = dev->dma_addr[0];
+
+ usb_ctrl_dma_addr = (dma_addr_t) usb_ctrl;
udc_reinit(dev);
{
u32 ep_ctrl;
- flush_dcache_range((unsigned long) usb_ctrl_dma_addr,
- (unsigned long) usb_ctrl_dma_addr
- + DMA_BUFFER_SIZE);
-
writel(usb_ctrl_dma_addr, ®->in_endp[EP0_CON].diepdma);
writel(DIEPT_SIZ_PKT_CNT(1), ®->in_endp[EP0_CON].dieptsiz);
debug_cond(DEBUG_IN_EP,
"%s : Prepare Setup packets.\n", __func__);
- invalidate_dcache_range((unsigned long) usb_ctrl_dma_addr,
- (unsigned long) usb_ctrl_dma_addr
- + DMA_BUFFER_SIZE);
-
writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
®->out_endp[EP0_CON].doeptsiz);
writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma);
debug_cond(DEBUG_IN_EP,
"%s : Prepare Complete Out packet.\n", __func__);
- invalidate_dcache_range((unsigned long) usb_ctrl_dma_addr,
- (unsigned long) usb_ctrl_dma_addr
- + DMA_BUFFER_SIZE);
-
writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
®->out_endp[EP0_CON].doeptsiz);
writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma);
u32 ep_num = ep_index(ep);
buf = req->req.buf + req->req.actual;
-
- length = min(req->req.length - req->req.actual, (int)ep->ep.maxpacket);
+ length = min(req->req.length - req->req.actual,
+ ep_num ? DMA_BUFFER_SIZE : ep->ep.maxpacket);
ep->len = length;
ep->dma_buf = buf;
- invalidate_dcache_range((unsigned long) ep->dev->dma_buf[ep_num],
- (unsigned long) ep->dev->dma_buf[ep_num]
- + ROUND(ep->ep.maxpacket,
- CONFIG_SYS_CACHELINE_SIZE));
-
- if (length == 0)
+ if (ep_num == EP0_CON || length == 0)
pktcnt = 1;
else
pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
- pktcnt = 1;
ctrl = readl(®->out_endp[ep_num].doepctl);
- writel(the_controller->dma_addr[ep_index(ep)+1],
- ®->out_endp[ep_num].doepdma);
+ writel((unsigned int) ep->dma_buf, ®->out_endp[ep_num].doepdma);
writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length),
®->out_endp[ep_num].doeptsiz);
writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, ®->out_endp[ep_num].doepctl);
u32 *buf, ctrl = 0;
u32 length, pktcnt;
u32 ep_num = ep_index(ep);
- u32 *p = the_controller->dma_buf[ep_index(ep)+1];
buf = req->req.buf + req->req.actual;
length = req->req.length - req->req.actual;
ep->len = length;
ep->dma_buf = buf;
- memcpy(p, ep->dma_buf, length);
- flush_dcache_range((unsigned long) p ,
- (unsigned long) p + DMA_BUFFER_SIZE);
+ flush_dcache_range((unsigned long) ep->dma_buf,
+ (unsigned long) ep->dma_buf +
+ ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE));
if (length == 0)
pktcnt = 1;
while (readl(®->grstctl) & TX_FIFO_FLUSH)
;
- writel(the_controller->dma_addr[ep_index(ep)+1],
- ®->in_endp[ep_num].diepdma);
+ writel((unsigned long) ep->dma_buf, ®->in_endp[ep_num].diepdma);
writel(DIEPT_SIZ_PKT_CNT(pktcnt) | DIEPT_SIZ_XFER_SIZE(length),
®->in_endp[ep_num].dieptsiz);
struct s3c_ep *ep = &dev->ep[ep_num];
struct s3c_request *req = NULL;
u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
- u32 *p = the_controller->dma_buf[ep_index(ep)+1];
if (list_empty(&ep->queue)) {
debug_cond(DEBUG_OUT_EP != 0,
xfer_size = ep->len - xfer_size;
- invalidate_dcache_range((unsigned long) p,
- (unsigned long) p + DMA_BUFFER_SIZE);
-
- memcpy(ep->dma_buf, p, ep->len);
+ /*
+ * NOTE:
+ *
+ * Please be careful with proper buffer allocation for USB request,
+ * which needs to be aligned to CONFIG_SYS_CACHELINE_SIZE, not only
+ * with starting address, but also its size shall be a cache line
+ * multiplication.
+ *
+ * This will prevent from corruption of data allocated immediatelly
+ * before or after the buffer.
+ *
+ * For armv7, the cache_v7.c provides proper code to emit "ERROR"
+ * message to warn users.
+ */
+ invalidate_dcache_range((unsigned long) ep->dma_buf,
+ (unsigned long) ep->dma_buf +
+ ROUND(xfer_size, CONFIG_SYS_CACHELINE_SIZE));
req->req.actual += min(xfer_size, req->req.length - req->req.actual);
is_short = (xfer_size < ep->ep.maxpacket);
int s3c_fifo_read(struct s3c_ep *ep, u32 *cp, int max)
{
- u32 bytes;
-
- bytes = sizeof(struct usb_ctrlrequest);
-
- invalidate_dcache_range((unsigned long) ep->dev->dma_buf[ep_index(ep)],
- (unsigned long) ep->dev->dma_buf[ep_index(ep)]
- + DMA_BUFFER_SIZE);
+ invalidate_dcache_range((unsigned long)cp, (unsigned long)cp +
+ ROUND(max, CONFIG_SYS_CACHELINE_SIZE));
debug_cond(DEBUG_EP0 != 0,
- "%s: bytes=%d, ep_index=%d %p\n", __func__,
- bytes, ep_index(ep), ep->dev->dma_buf[ep_index(ep)]);
+ "%s: bytes=%d, ep_index=%d 0x%p\n", __func__,
+ max, ep_index(ep), cp);
- return bytes;
+ return max;
}
/**
return 1;
}
-u16 g_status;
-
int s3c_udc_get_status(struct s3c_udc *dev,
struct usb_ctrlrequest *crq)
{
u8 ep_num = crq->wIndex & 0x7F;
+ u16 g_status = 0;
u32 ep_ctrl;
- u32 *p = the_controller->dma_buf[1];
debug_cond(DEBUG_SETUP != 0,
"%s: *** USB_REQ_GET_STATUS\n", __func__);
return 1;
}
- memcpy(p, &g_status, sizeof(g_status));
+ memcpy(usb_ctrl, &g_status, sizeof(g_status));
- flush_dcache_range((unsigned long) p,
- (unsigned long) p + DMA_BUFFER_SIZE);
+ flush_dcache_range((unsigned long) usb_ctrl,
+ (unsigned long) usb_ctrl +
+ ROUND(sizeof(g_status), CONFIG_SYS_CACHELINE_SIZE));
- writel(the_controller->dma_addr[1], ®->in_endp[EP0_CON].diepdma);
+ writel(usb_ctrl_dma_addr, ®->in_endp[EP0_CON].diepdma);
writel(DIEPT_SIZ_PKT_CNT(1) | DIEPT_SIZ_XFER_SIZE(2),
®->in_endp[EP0_CON].dieptsiz);
obj-$(CONFIG_USB_EHCI_MX6) += ehci-mx6.o
obj-$(CONFIG_USB_EHCI_OMAP) += ehci-omap.o
obj-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
-obj-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o
obj-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o
obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o
#endif
}
- if (!strcmp(phy_type, "utmi")) {
+ if (!strncmp(phy_type, "utmi", 4)) {
#if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
setbits_be32(&ehci->control, PHY_CLK_SEL_UTMI);
setbits_be32(&ehci->control, UTMI_PHY_EN);
+++ /dev/null
-/*
- * (C) Copyright 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
- *
- * Author: Michael Trimarchi <trimarchimichael@yahoo.it>
- * This code is based on ehci freescale driver
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <usb.h>
-
-#include "ehci.h"
-/*
- * Create the appropriate control structures to manage
- * a new EHCI host controller.
- */
-int ehci_hcd_init(int index, enum usb_init_type init,
- struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
- *hccr = (struct ehci_hccr *)(0xcd000100);
- *hcor = (struct ehci_hcor *)((uint32_t) *hccr
- + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
-
- printf("IXP4XX init hccr %x and hcor %x hc_length %d\n",
- (uint32_t)*hccr, (uint32_t)*hcor,
- (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
- return 0;
-}
-
-/*
- * Destroy the appropriate control structures corresponding
- * the the EHCI host controller.
- */
-int ehci_hcd_stop(int index)
-{
- return 0;
-}
obj-$(CONFIG_USB_MUSB_AM35X) += am35x.o
obj-$(CONFIG_USB_MUSB_OMAP2PLUS) += omap2430.o
-CFLAGS_NO_WARN := $(call cc-option,-Wno-unused-variable) \
- $(call cc-option,-Wno-unused-but-set-variable) \
- $(call cc-option,-Wno-unused-label)
-CFLAGS += $(CFLAGS_NO_WARN)
+ccflags-y := $(call cc-option,-Wno-unused-variable) \
+ $(call cc-option,-Wno-unused-but-set-variable) \
+ $(call cc-option,-Wno-unused-label)
#include <usb.h>
#include <asm/blackfin.h>
+#include <asm/clock.h>
#include <asm/mach-common/bits/usb.h>
#include "musb_core.h"
lcd_set_flush_dcache(1);
}
-#ifdef CONFIG_CMD_BMP
-static void draw_logo(void)
-{
- int x, y;
- ulong addr;
-
- if (panel_width >= panel_info.logo_width) {
- x = ((panel_width - panel_info.logo_width) >> 1);
- } else {
- x = 0;
- printf("Warning: image width is bigger than display width\n");
- }
-
- if (panel_height >= panel_info.logo_height) {
- y = ((panel_height - panel_info.logo_height) >> 1) - 4;
- } else {
- y = 0;
- printf("Warning: image height is bigger than display height\n");
- }
-
- addr = panel_info.logo_addr;
- bmp_display(addr, x, y);
-}
-#endif
-
void __exynos_cfg_lcd_gpio(void)
{
}
if (panel_info.logo_on) {
memset((void *) gd->fb_base, 0, panel_width * panel_height *
(NBITS(panel_info.vl_bpix) >> 3));
-#ifdef CONFIG_CMD_BMP
- draw_logo();
-#endif
}
lcd_panel_on(&panel_info);
/* DATAPATH is DMA */
cfg |= EXYNOS_WINCON_DATAPATH_DMA;
- if (pvid->logo_on) /* To get proprietary LOGO */
- cfg |= EXYNOS_WINCON_WSWP_ENABLE;
- else /* To get output console on LCD */
- cfg |= EXYNOS_WINCON_HAWSWP_ENABLE;
+ cfg |= EXYNOS_WINCON_HAWSWP_ENABLE;
/* dma burst is 16 */
cfg |= EXYNOS_WINCON_BURSTLEN_16WORD;
- if (pvid->logo_on) /* To get proprietary LOGO */
- cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
- else /* To get output console on LCD */
+ switch (pvid->vl_bpix) {
+ case 4:
cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565;
+ break;
+ default:
+ cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
+ break;
+ }
writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
EXYNOS_WINCON(win_id));
--- /dev/null
+*.dtb
+*.dtb.S
# This Makefile builds the internal U-Boot fdt if CONFIG_OF_CONTROL is
# enabled. See doc/README.fdt-control for more details.
+DEVICE_TREE ?= $(CONFIG_DEFAULT_DEVICE_TREE:"%"=%)
ifeq ($(DEVICE_TREE),)
-$(if $(CONFIG_DEFAULT_DEVICE_TREE),,\
-$(error Please define CONFIG_DEFAULT_DEVICE_TREE in your board header file))
-DEVICE_TREE = $(CONFIG_DEFAULT_DEVICE_TREE:"%"=%)
+DEVICE_TREE := unset
endif
-DTS_INCDIRS = $(SRCTREE)/board/$(VENDOR)/$(BOARD)/dts
-DTS_INCDIRS += $(SRCTREE)/board/$(VENDOR)/dts
-DTS_INCDIRS += $(SRCTREE)/arch/$(ARCH)/dts
+DTB := arch/$(ARCH)/dts/$(DEVICE_TREE).dtb
-DTS_CPPFLAGS := -x assembler-with-cpp -undef -D__DTS__ \
- -nostdinc $(addprefix -I,$(DTS_INCDIRS))
+quiet_cmd_copy = COPY $@
+ cmd_copy = cp $< $@
-DTC_FLAGS := -R 4 -p 0x1000 \
- $(addprefix -i ,$(DTS_INCDIRS))
+$(obj)/dt.dtb: $(DTB) FORCE
+ $(call if_changed,copy)
-# Use a constant name for this so we can access it from C code.
-# objcopy doesn't seem to allow us to set the symbol name independently of
-# the filename.
-DT_BIN := $(obj)dt.dtb
+targets += dt.dtb
-$(DT_BIN): $(TOPDIR)/board/$(VENDOR)/dts/$(DEVICE_TREE).dts
- $(CPP) $(DTS_CPPFLAGS) $< -o $(DT_BIN).dts.tmp
- $(DTC) $(DTC_FLAGS) -O dtb -o ${DT_BIN} $(DT_BIN).dts.tmp
+$(DTB): arch-dtbs
+ $(Q)test -e $@ || ( \
+ echo >&2; \
+ echo >&2 "Device Tree Source is not correctly specified."; \
+ echo >&2 "Please define 'CONFIG_DEFAULT_DEVICE_TREE'"; \
+ echo >&2 "or build with 'DEVICE_TREE=<device_tree>' argument"; \
+ echo >&2; \
+ /bin/false)
-process_lds = \
- $(1) | sed -r -n 's/^OUTPUT_$(2)[ ("]*([^")]*).*/\1/p'
+arch-dtbs:
+ $(Q)$(MAKE) $(build)=arch/$(ARCH)/dts dtbs
-# Run the compiler and get the link script from the linker
-GET_LDS = $(CC) $(CFLAGS) $(LDFLAGS) -Wl,--verbose 2>&1
+.SECONDARY: $(obj)/dt.dtb.S
-$(obj)dt.o: $(DT_BIN)
- # We want the output format and arch.
- # We also hope to win a prize for ugliest Makefile / shell interaction
- # We look in the LDSCRIPT first.
- # Then try the linker which should give us the answer.
- # Then check it worked.
- [ -n "$(LDSCRIPT)" ] && \
- oformat=`$(call process_lds,cat $(LDSCRIPT),FORMAT)` && \
- oarch=`$(call process_lds,cat $(LDSCRIPT),ARCH)` ;\
- \
- [ -z $${oformat} ] && \
- oformat=`$(call process_lds,$(GET_LDS),FORMAT)` ;\
- [ -z $${oarch} ] && \
- oarch=`$(call process_lds,$(GET_LDS),ARCH)` ;\
- \
- [ -z $${oformat} ] && \
- echo "Cannot read OUTPUT_FORMAT from lds file $(LDSCRIPT)" && \
- exit 1 || true ;\
- [ -z $${oarch} ] && \
- echo "Cannot read OUTPUT_ARCH from lds file $(LDSCRIPT)" && \
- exit 1 || true ;\
- \
- cd $(dir ${DT_BIN}) && \
- $(OBJCOPY) -I binary -O $${oformat} -B $${oarch} \
- $(notdir ${DT_BIN}) $@
- rm $(DT_BIN)
+obj-$(CONFIG_OF_EMBED) := dt.dtb.o
-obj-$(CONFIG_OF_EMBED) := dt.o
+dtbs: $(obj)/dt.dtb
+ @:
-binary: $(DT_BIN)
+clean-files := dt.dtb.S
+
+# Let clean descend into dts directories
+subdir- += ../arch/*/dts
--- /dev/null
+ifndef CONFIG_SANDBOX
+
+ifdef FTRACE
+subdir-ccflags-y += -finstrument-functions -DFTRACE
+endif
+
+subdir-y += standalone
+subdir-$(CONFIG_API) += api
+endif
LOAD_ADDR = 0x1000000
endif
-include $(TOPDIR)/config.mk
-
# Resulting ELF and binary exectuables will be named demo and demo.bin
-OUTPUT = $(obj)demo
+extra-y = demo
# Source files located in the examples/api directory
-SOBJ_FILES-y += crt0.o
-COBJ_FILES-y += demo.o
-COBJ_FILES-y += glue.o
-COBJ_FILES-y += libgenwrap.o
+OBJ-y += crt0.o
+OBJ-y += demo.o
+OBJ-y += glue.o
+OBJ-y += libgenwrap.o
# Source files which exist outside the examples/api directory
-EXT_COBJ_FILES-y += lib/crc32.o
-EXT_COBJ_FILES-y += lib/ctype.o
-EXT_COBJ_FILES-y += lib/div64.o
-EXT_COBJ_FILES-y += lib/string.o
-EXT_COBJ_FILES-y += lib/time.o
-EXT_COBJ_FILES-y += lib/vsprintf.o
-EXT_SOBJ_FILES-$(CONFIG_PPC) += arch/powerpc/lib/ppcstring.o
-
-# Create a list of source files so their dependencies can be auto-generated
-SRCS += $(addprefix $(SRCTREE)/,$(EXT_COBJ_FILES-y:.o=.c))
-SRCS += $(addprefix $(SRCTREE)/,$(EXT_SOBJ_FILES-y:.o=.S))
-SRCS += $(addprefix $(SRCTREE)/examples/api/,$(COBJ_FILES-y:.o=.c))
-SRCS += $(addprefix $(SRCTREE)/examples/api/,$(SOBJ_FILES-y:.o=.S))
+EXT_COBJ-y += lib/crc32.o
+EXT_COBJ-y += lib/ctype.o
+EXT_COBJ-y += lib/div64.o
+EXT_COBJ-y += lib/string.o
+EXT_COBJ-y += lib/time.o
+EXT_COBJ-y += lib/vsprintf.o
+EXT_SOBJ-$(CONFIG_PPC) += arch/powerpc/lib/ppcstring.o
# Create a list of object files to be compiled
-OBJS += $(addprefix $(obj),$(SOBJ_FILES-y))
-OBJS += $(addprefix $(obj),$(COBJ_FILES-y))
-OBJS += $(addprefix $(obj),$(notdir $(EXT_COBJ_FILES-y)))
-OBJS += $(addprefix $(obj),$(notdir $(EXT_SOBJ_FILES-y)))
-
-all: $(obj).depend $(OUTPUT)
+OBJS := $(OBJ-y) $(notdir $(EXT_COBJ-y) $(EXT_SOBJ-y))
+targets += $(OBJS)
+OBJS := $(addprefix $(obj)/,$(OBJS))
#########################################################################
-$(OUTPUT): $(OBJS)
- $(LD) --gc-sections -Ttext $(LOAD_ADDR) -o $@ $^ $(PLATFORM_LIBS)
- $(OBJCOPY) -O binary $@ $(OUTPUT).bin 2>/dev/null
+quiet_cmd_link_demo = LD $@
+cmd_link_demo = $(LD) --gc-sections -Ttext $(LOAD_ADDR) -o $@ $(filter-out $(PHONY), $^) $(PLATFORM_LIBS)
-# Rule to build generic library C files
-$(obj)%.o: $(SRCTREE)/lib/%.c
- $(CC) -g $(CFLAGS) -c -o $@ $<
+$(obj)/demo: $(OBJS) FORCE
+ $(call if_changed,link_demo)
-# Rule to build architecture-specific library assembly files
-$(obj)%.o: $(SRCTREE)/arch/$(ARCH)/lib/%.S
- $(CC) -g $(CFLAGS) -c -o $@ $<
+# demo.bin is never genrated. Is this necessary?
+OBJCOPYFLAGS_demo.bin := -O binary
+$(obj)/demo.bin: $(obj)/demo FORCE
+ $(call if_changed,objcopy)
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
+# Rule to build generic library C files
+$(addprefix $(obj)/,$(notdir $(EXT_COBJ-y))): $(obj)/%.o: lib/%.c FORCE
+ $(call cmd,force_checksrc)
+ $(call if_changed_rule,cc_o_c)
-#########################################################################
+# Rule to build architecture-specific library assembly files
+$(addprefix $(obj)/,$(notdir $(EXT_SOBJ-y))): $(obj)/%.o: arch/powerpc/lib/%.S FORCE
+ $(call if_changed_dep,as_o_S)
# SPDX-License-Identifier: GPL-2.0+
#
-include $(TOPDIR)/config.mk
-
-ELF-y := hello_world
-
-ELF-$(CONFIG_SMC91111) += smc91111_eeprom
-ELF-$(CONFIG_SMC911X) += smc911x_eeprom
-ELF-$(CONFIG_SPI_FLASH_ATMEL) += atmel_df_pow2
-ELF-$(CONFIG_MPC5xxx) += interrupt
-ELF-$(CONFIG_8xx) += test_burst timer
-ELF-$(CONFIG_8260) += mem_to_mem_idma2intr
-ELF-$(CONFIG_PPC) += sched
+extra-y := hello_world
+extra-$(CONFIG_SMC91111) += smc91111_eeprom
+extra-$(CONFIG_SMC911X) += smc911x_eeprom
+extra-$(CONFIG_SPI_FLASH_ATMEL) += atmel_df_pow2
+extra-$(CONFIG_MPC5xxx) += interrupt
+extra-$(CONFIG_8xx) += test_burst timer
+extra-$(CONFIG_8260) += mem_to_mem_idma2intr
+extra-$(CONFIG_PPC) += sched
#
# Some versions of make do not handle trailing white spaces properly;
# leading to build failures. The problem was found with GNU Make 3.80.
# Using 'strip' as a workaround for the problem.
#
-ELF := $(strip $(ELF-y))
+ELF := $(strip $(extra-y))
-SREC := $(addsuffix .srec,$(ELF))
-BIN := $(addsuffix .bin,$(ELF))
+extra-y += $(addsuffix .srec,$(extra-y)) $(addsuffix .bin,$(extra-y))
+clean-files := $(extra-) $(addsuffix .srec,$(extra-)) $(addsuffix .bin,$(extra-))
COBJS := $(ELF:=.o)
-LIB = $(obj)libstubs.o
+LIB = $(obj)/libstubs.o
-LIBAOBJS-$(CONFIG_PPC) += ppc_longjmp.o ppc_setjmp.o
-LIBAOBJS-$(CONFIG_8xx) += test_burst_lib.o
-LIBAOBJS := $(LIBAOBJS-y)
+LIBOBJS-$(CONFIG_PPC) += ppc_longjmp.o ppc_setjmp.o
+LIBOBJS-$(CONFIG_8xx) += test_burst_lib.o
+LIBOBJS-y += stubs.o
-LIBCOBJS = stubs.o
+.SECONDARY: $(call objectify,$(COBJS))
+targets += $(patsubst $(obj)/%,%,$(LIB)) $(COBJS) $(LIBOBJS-y)
-LIBOBJS = $(addprefix $(obj),$(LIBAOBJS) $(LIBCOBJS))
-
-SRCS := $(COBJS:.o=.c) $(LIBCOBJS:.o=.c) $(LIBAOBJS:.o=.S)
-OBJS := $(addprefix $(obj),$(COBJS))
-ELF := $(addprefix $(obj),$(ELF))
-BIN := $(addprefix $(obj),$(BIN))
-SREC := $(addprefix $(obj),$(SREC))
+LIBOBJS := $(addprefix $(obj)/,$(LIBOBJS-y))
+ELF := $(addprefix $(obj)/,$(ELF))
gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
# also causes the entry point of the standalone application to be
# inconsistent.
ifeq ($(ARCH),powerpc)
-AFLAGS := $(filter-out $(RELFLAGS),$(AFLAGS))
-CFLAGS := $(filter-out $(RELFLAGS),$(CFLAGS))
-CPPFLAGS := $(filter-out $(RELFLAGS),$(CPPFLAGS))
+# FIX ME
+CPPFLAGS := $(filter-out $(RELFLAGS), $(CPPFLAGS))
endif
# We don't want gcc reordering functions if possible. This ensures that an
# application's entry point will be the first function in the application's
# source file.
-CFLAGS_NTR := $(call cc-option,-fno-toplevel-reorder)
-CFLAGS += $(CFLAGS_NTR)
-
-all: $(obj).depend $(OBJS) $(LIB) $(SREC) $(BIN) $(ELF)
+ccflags-y += $(call cc-option,-fno-toplevel-reorder)
#########################################################################
-$(LIB): $(obj).depend $(LIBOBJS)
- $(call cmd_link_o_target, $(LIBOBJS))
-$(ELF):
-$(obj)%: $(obj)%.o $(LIB)
- $(LD) $(LDFLAGS) -g -Ttext $(CONFIG_STANDALONE_LOAD_ADDR) \
- -o $@ -e $(SYM_PREFIX)$(notdir $(<:.o=)) $< $(LIB) \
- -L$(gcclibdir) -lgcc
+quiet_cmd_link_lib = LD $@
+ cmd_link_lib = $(LD) $(ld_flags) -r -o $@ $(filter $(LIBOBJS), $^)
-$(SREC):
-$(obj)%.srec: $(obj)%
- $(OBJCOPY) -O srec $< $@ 2>/dev/null
+$(LIB): $(LIBOBJS) FORCE
+ $(call if_changed,link_lib)
-$(BIN):
-$(obj)%.bin: $(obj)%
- $(OBJCOPY) -O binary $< $@ 2>/dev/null
+quiet_cmd_link_elf = LD $@
+ cmd_link_elf = $(LD) $(LDFLAGS) -g -Ttext $(CONFIG_STANDALONE_LOAD_ADDR) \
+ -o $@ -e $(SYM_PREFIX)$(@F) $< $(LIB) -L$(gcclibdir) -lgcc
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
+$(ELF): $(obj)/%: $(obj)/%.o $(LIB) FORCE
+ $(call if_changed,link_elf)
-sinclude $(obj).depend
+$(obj)/%.srec: OBJCOPYFLAGS := -O srec
+$(obj)/%.srec: $(obj)/% FORCE
+ $(call if_changed,objcopy)
-#########################################################################
+$(obj)/%.bin: OBJCOPYFLAGS := -O binary
+$(obj)/%.bin: $(obj)/% FORCE
+ $(call if_changed,objcopy)
" l.jr r13\n" \
" l.nop\n" \
: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r13");
+#elif defined(CONFIG_ARC)
+/*
+ * r25 holds the pointer to the global_data. r10 is call clobbered.
+ */
+#define EXPORT_FUNC(x) \
+ asm volatile( \
+" .align 4\n" \
+" .globl " #x "\n" \
+#x ":\n" \
+" ld r10, [r25, %0]\n" \
+" ld r10, [r10, %1]\n" \
+" j [r10]\n" \
+ : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r10");
#else
/*" addi $sp, $sp, -24\n" \
" br $r16\n" \*/
obj-$(CONFIG_CMD_CRAMFS) += cramfs/
obj-$(CONFIG_FS_EXT4) += ext4/
obj-y += fat/
-obj-$(CONFIG_CMD_FDOS) += fdos/
obj-$(CONFIG_CMD_JFFS2) += jffs2/
obj-$(CONFIG_CMD_REISER) += reiserfs/
obj-$(CONFIG_SANDBOX) += sandbox/
return 0;
}
+int ext4fs_exists(const char *filename)
+{
+ int file_len;
+
+ file_len = ext4fs_open(filename);
+ return file_len >= 0;
+}
+
int ext4fs_read(char *buf, unsigned len)
{
if (ext4fs_root == NULL || ext4fs_file == NULL)
long
do_fat_read_at(const char *filename, unsigned long pos, void *buffer,
- unsigned long maxsize, int dols)
+ unsigned long maxsize, int dols, int dogetsize)
{
char fnamecopy[2048];
boot_sector bs;
subname = nextname;
}
- ret = get_contents(mydata, dentptr, pos, buffer, maxsize);
+ if (dogetsize)
+ ret = FAT2CPU32(dentptr->size);
+ else
+ ret = get_contents(mydata, dentptr, pos, buffer, maxsize);
debug("Size: %d, got: %ld\n", FAT2CPU32(dentptr->size), ret);
exit:
long
do_fat_read(const char *filename, void *buffer, unsigned long maxsize, int dols)
{
- return do_fat_read_at(filename, 0, buffer, maxsize, dols);
+ return do_fat_read_at(filename, 0, buffer, maxsize, dols, 0);
}
int file_fat_detectfs(void)
return do_fat_read(dir, NULL, 0, LS_YES);
}
+int fat_exists(const char *filename)
+{
+ int sz;
+ sz = do_fat_read_at(filename, 0, NULL, 0, LS_NO, 1);
+ return sz >= 0;
+}
+
long file_fat_read_at(const char *filename, unsigned long pos, void *buffer,
unsigned long maxsize)
{
printf("reading %s\n", filename);
- return do_fat_read_at(filename, pos, buffer, maxsize, LS_NO);
+ return do_fat_read_at(filename, pos, buffer, maxsize, LS_NO, 0);
}
long file_fat_read(const char *filename, void *buffer, unsigned long maxsize)
+++ /dev/null
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2002
-# Stäubli Faverges - <www.staubli.com>
-# Pierre AUBERT p.aubert@staubli.com
-#
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := fat.o vfat.o dev.o fdos.o fs.o subdir.o
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Stäubli Faverges - <www.staubli.com>
- * Pierre AUBERT p.aubert@staubli.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-
-#include "dos.h"
-#include "fdos.h"
-
-#define NB_HEADS 2
-#define NB_TRACKS 80
-#define NB_SECTORS 18
-
-
-static int lastwhere;
-
-/*-----------------------------------------------------------------------------
- * dev_open --
- *-----------------------------------------------------------------------------
- */
-int dev_open (void)
-{
- lastwhere = 0;
- return (0);
-}
-
-/*-----------------------------------------------------------------------------
- * dev_read -- len and where are sectors number
- *-----------------------------------------------------------------------------
- */
-int dev_read (void *buffer, int where, int len)
-{
- PRINTF ("dev_read (len = %d, where = %d)\n", len, where);
-
- /* Si on ne desire pas lire a la position courante, il faut un seek */
- if (where != lastwhere) {
- if (!fdc_fdos_seek (where)) {
- PRINTF ("seek error in dev_read");
- lastwhere = -1;
- return (-1);
- }
- }
-
- if (!fdc_fdos_read (buffer, len)) {
- PRINTF ("read error\n");
- lastwhere = -1;
- return (-1);
- }
- lastwhere = where + len;
- return (0);
-}
-/*-----------------------------------------------------------------------------
- * check_dev -- verify the diskette format
- *-----------------------------------------------------------------------------
- */
-int check_dev (BootSector_t *boot, Fs_t *fs)
-{
- unsigned int heads, sectors, tracks;
- int BootP, Infp0, InfpX, InfTm;
- int sect_per_track;
-
- /* Display Boot header */
- PRINTF ("Jump to boot code 0x%02x 0x%02x 0x%02x\n",
- boot -> jump [0], boot -> jump [1], boot -> jump[2]);
- PRINTF ("OEM name & version '%*.*s'\n",
- BANNER_LG, BANNER_LG, boot -> banner );
- PRINTF ("Bytes per sector hopefully 512 %d\n",
- __le16_to_cpu (boot -> secsiz));
- PRINTF ("Cluster size in sectors %d\n",
- boot -> clsiz);
- PRINTF ("Number of reserved (boot) sectors %d\n",
- __le16_to_cpu (boot -> nrsvsect));
- PRINTF ("Number of FAT tables hopefully 2 %d\n",
- boot -> nfat);
- PRINTF ("Number of directory slots %d\n",
- __le16_to_cpu (boot -> dirents));
- PRINTF ("Total sectors on disk %d\n",
- __le16_to_cpu (boot -> psect));
- PRINTF ("Media descriptor=first byte of FAT %d\n",
- boot -> descr);
- PRINTF ("Sectors in FAT %d\n",
- __le16_to_cpu (boot -> fatlen));
- PRINTF ("Sectors/track %d\n",
- __le16_to_cpu (boot -> nsect));
- PRINTF ("Heads %d\n",
- __le16_to_cpu (boot -> nheads));
- PRINTF ("number of hidden sectors %d\n",
- __le32_to_cpu (boot -> nhs));
- PRINTF ("big total sectors %d\n",
- __le32_to_cpu (boot -> bigsect));
- PRINTF ("physical drive ? %d\n",
- boot -> physdrive);
- PRINTF ("reserved %d\n",
- boot -> reserved);
- PRINTF ("dos > 4.0 diskette %d\n",
- boot -> dos4);
- PRINTF ("serial number %d\n",
- __le32_to_cpu (boot -> serial));
- PRINTF ("disk label %*.*s\n",
- LABEL_LG, LABEL_LG, boot -> label);
- PRINTF ("FAT type %8.8s\n",
- boot -> fat_type);
- PRINTF ("reserved by 2M %d\n",
- boot -> res_2m);
- PRINTF ("2M checksum (not used) %d\n",
- boot -> CheckSum);
- PRINTF ("2MF format version %d\n",
- boot -> fmt_2mf);
- PRINTF ("1 if write track after format %d\n",
- boot -> wt);
- PRINTF ("data transfer rate on track 0 %d\n",
- boot -> rate_0);
- PRINTF ("data transfer rate on track<>0 %d\n",
- boot -> rate_any);
- PRINTF ("offset to boot program %d\n",
- __le16_to_cpu (boot -> BootP));
- PRINTF ("T1: information for track 0 %d\n",
- __le16_to_cpu (boot -> Infp0));
- PRINTF ("T2: information for track<>0 %d\n",
- __le16_to_cpu (boot -> InfpX));
- PRINTF ("T3: track sectors size table %d\n",
- __le16_to_cpu (boot -> InfTm));
- PRINTF ("Format date 0x%04x\n",
- __le16_to_cpu (boot -> DateF));
- PRINTF ("Format time 0x%04x\n",
- __le16_to_cpu (boot -> TimeF));
-
-
- /* information is extracted from boot sector */
- heads = __le16_to_cpu (boot -> nheads);
- sectors = __le16_to_cpu (boot -> nsect);
- fs -> tot_sectors = __le32_to_cpu (boot -> bigsect);
- if (__le16_to_cpu (boot -> psect) != 0) {
- fs -> tot_sectors = __le16_to_cpu (boot -> psect);
- }
-
- sect_per_track = heads * sectors;
- tracks = (fs -> tot_sectors + sect_per_track - 1) / sect_per_track;
-
- BootP = __le16_to_cpu (boot -> BootP);
- Infp0 = __le16_to_cpu (boot -> Infp0);
- InfpX = __le16_to_cpu (boot -> InfpX);
- InfTm = __le16_to_cpu (boot -> InfTm);
-
- if (boot -> dos4 == EXTENDED_BOOT &&
- strncmp( boot->banner,"2M", 2 ) == 0 &&
- BootP < SZ_STD_SECTOR &&
- Infp0 < SZ_STD_SECTOR &&
- InfpX < SZ_STD_SECTOR &&
- InfTm < SZ_STD_SECTOR &&
- BootP >= InfTm + 2 &&
- InfTm >= InfpX &&
- InfpX >= Infp0 &&
- Infp0 >= 76 ) {
-
- return (-1);
- }
-
- if (heads != NB_HEADS ||
- tracks != NB_TRACKS ||
- sectors != NB_SECTORS ||
- __le16_to_cpu (boot -> secsiz) != SZ_STD_SECTOR ||
- fs -> tot_sectors == 0 ||
- (fs -> tot_sectors % sectors) != 0) {
- return (-1);
- }
-
- return (0);
-}
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Stäubli Faverges - <www.staubli.com>
- * Pierre AUBERT p.aubert@staubli.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _DOS_H_
-#define _DOS_H_
-
-/* Definitions for Dos diskettes */
-
-/* General definitions */
-#define SZ_STD_SECTOR 512 /* Standard sector size */
-#define MDIR_SIZE 32 /* Direntry size */
-#define FAT_BITS 12 /* Diskette use 12 bits fat */
-
-#define MAX_PATH 128 /* Max size of the MSDOS PATH */
-#define MAX_DIR_SECS 64 /* Taille max d'un repertoire (en */
- /* secteurs) */
-/* Misc. definitions */
-#define DELMARK '\xe5'
-#define EXTENDED_BOOT (0x29)
-#define MEDIA_STD (0xf0)
-#define JUMP_0_1 (0xe9)
-#define JUMP_0_2 (0xeb)
-
-/* Boot size is 256 bytes, but we need to read almost a sector, then
- assume bootsize is 512 */
-#define BOOTSIZE 512
-
-/* Fat definitions for 12 bits fat */
-#define FAT12_MAX_NB 4086
-#define FAT12_LAST 0x0ff6
-#define FAT12_END 0x0fff
-
-/* file attributes */
-#define ATTR_READONLY 0x01
-#define ATTR_HIDDEN 0x02
-#define ATTR_SYSTEM 0x04
-#define ATTR_VOLUME 0x08
-#define ATTR_DIRECTORY 0x10
-#define ATTR_ARCHIVE 0x20
-#define ATTR_VSE 0x0f
-
-/* Name format */
-#define EXTCASE 0x10
-#define BASECASE 0x8
-
-/* Definition of the boot sector */
-#define BANNER_LG 8
-#define LABEL_LG 11
-
-typedef struct bootsector
-{
- unsigned char jump [3]; /* 0 Jump to boot code */
- char banner [BANNER_LG]; /* 3 OEM name & version */
- unsigned short secsiz; /* 11 Bytes per sector hopefully 512 */
- unsigned char clsiz; /* 13 Cluster size in sectors */
- unsigned short nrsvsect; /* 14 Number of reserved (boot) sectors */
- unsigned char nfat; /* 16 Number of FAT tables hopefully 2 */
- unsigned short dirents; /* 17 Number of directory slots */
- unsigned short psect; /* 19 Total sectors on disk */
- unsigned char descr; /* 21 Media descriptor=first byte of FAT */
- unsigned short fatlen; /* 22 Sectors in FAT */
- unsigned short nsect; /* 24 Sectors/track */
- unsigned short nheads; /* 26 Heads */
- unsigned int nhs; /* 28 number of hidden sectors */
- unsigned int bigsect; /* 32 big total sectors */
- unsigned char physdrive; /* 36 physical drive ? */
- unsigned char reserved; /* 37 reserved */
- unsigned char dos4; /* 38 dos > 4.0 diskette */
- unsigned int serial; /* 39 serial number */
- char label [LABEL_LG]; /* 43 disk label */
- char fat_type [8]; /* 54 FAT type */
- unsigned char res_2m; /* 62 reserved by 2M */
- unsigned char CheckSum; /* 63 2M checksum (not used) */
- unsigned char fmt_2mf; /* 64 2MF format version */
- unsigned char wt; /* 65 1 if write track after format */
- unsigned char rate_0; /* 66 data transfer rate on track 0 */
- unsigned char rate_any; /* 67 data transfer rate on track<>0 */
- unsigned short BootP; /* 68 offset to boot program */
- unsigned short Infp0; /* 70 T1: information for track 0 */
- unsigned short InfpX; /* 72 T2: information for track<>0 */
- unsigned short InfTm; /* 74 T3: track sectors size table */
- unsigned short DateF; /* 76 Format date */
- unsigned short TimeF; /* 78 Format time */
- unsigned char junk [BOOTSIZE - 80]; /* 80 remaining data */
-} __attribute__ ((packed)) BootSector_t;
-
-/* Structure d'une entree de repertoire */
-typedef struct directory {
- char name [8]; /* file name */
- char ext [3]; /* file extension */
- unsigned char attr; /* attribute byte */
- unsigned char Case; /* case of short filename */
- unsigned char reserved [9]; /* ?? */
- unsigned char time [2]; /* time stamp */
- unsigned char date [2]; /* date stamp */
- unsigned short start; /* starting cluster number */
- unsigned int size; /* size of the file */
-} __attribute__ ((packed)) Directory_t;
-
-
-#define MAX_VFAT_SUBENTRIES 20
-#define VSE_NAMELEN 13
-
-#define VSE1SIZE 5
-#define VSE2SIZE 6
-#define VSE3SIZE 2
-
-#define VBUFSIZE ((MAX_VFAT_SUBENTRIES * VSE_NAMELEN) + 1)
-
-#define MAX_VNAMELEN (255)
-
-#define VSE_PRESENT 0x01
-#define VSE_LAST 0x40
-#define VSE_MASK 0x1f
-
-/* Flag used by vfat_lookup */
-#define DO_OPEN 1
-#define ACCEPT_PLAIN 0x20
-#define ACCEPT_DIR 0x10
-#define ACCEPT_LABEL 0x08
-#define SINGLE 2
-#define MATCH_ANY 0x40
-
-struct vfat_subentry {
- unsigned char id; /* VSE_LAST pour la fin, VSE_MASK */
- /* pour un VSE */
- char text1 [VSE1SIZE * 2]; /* Caracteres encodes sur 16 bits */
- unsigned char attribute; /* 0x0f pour les VFAT */
- unsigned char hash1; /* toujours 0 */
- unsigned char sum; /* Checksum du nom court */
- char text2 [VSE2SIZE * 2]; /* Caracteres encodes sur 16 bits */
- unsigned char sector_l; /* 0 pour les VFAT */
- unsigned char sector_u; /* 0 pour les VFAT */
- char text3 [VSE3SIZE * 2]; /* Caracteres encodes sur 16 bits */
-} __attribute__ ((packed)) ;
-
-struct vfat_state {
- char name [VBUFSIZE];
- int status; /* is now a bit map of 32 bits */
- int subentries;
- unsigned char sum; /* no need to remember the sum for each */
- /* entry, it is the same anyways */
-} __attribute__ ((packed)) ;
-
-/* Conversion macros */
-#define DOS_YEAR(dir) (((dir)->date[1] >> 1) + 1980)
-#define DOS_MONTH(dir) (((((dir)->date[1]&0x1) << 3) + ((dir)->date[0] >> 5)))
-#define DOS_DAY(dir) ((dir)->date[0] & 0x1f)
-#define DOS_HOUR(dir) ((dir)->time[1] >> 3)
-#define DOS_MINUTE(dir) (((((dir)->time[1]&0x7) << 3) + ((dir)->time[0] >> 5)))
-#define DOS_SEC(dir) (((dir)->time[0] & 0x1f) * 2)
-
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Stäubli Faverges - <www.staubli.com>
- * Pierre AUBERT p.aubert@staubli.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <malloc.h>
-
-#include "dos.h"
-#include "fdos.h"
-
-
-/*-----------------------------------------------------------------------------
- * fat_decode --
- *-----------------------------------------------------------------------------
- */
-unsigned int fat_decode (Fs_t *fs, unsigned int num)
-{
- unsigned int start = num * 3 / 2;
- unsigned char *address = fs -> fat_buf + start;
-
- if (num < 2 || start + 1 > (fs -> fat_len * SZ_STD_SECTOR))
- return 1;
-
- if (num & 1)
- return ((address [1] & 0xff) << 4) | ((address [0] & 0xf0 ) >> 4);
- else
- return ((address [1] & 0xf) << 8) | (address [0] & 0xff );
-}
-/*-----------------------------------------------------------------------------
- * check_fat --
- *-----------------------------------------------------------------------------
- */
-static int check_fat (Fs_t *fs)
-{
- int i, f;
-
- /* Cluster verification */
- for (i = 3 ; i < fs -> num_clus; i++){
- f = fat_decode (fs, i);
- if (f < FAT12_LAST && f > fs -> num_clus){
- /* Wrong cluster number detected */
- return (-1);
- }
- }
- return (0);
-}
-/*-----------------------------------------------------------------------------
- * read_one_fat --
- *-----------------------------------------------------------------------------
- */
-static int read_one_fat (BootSector_t *boot, Fs_t *fs, int nfat)
-{
- if (dev_read (fs -> fat_buf,
- (fs -> fat_start + nfat * fs -> fat_len),
- fs -> fat_len) < 0) {
- return (-1);
- }
-
- if (fs -> fat_buf [0] || fs -> fat_buf [1] || fs -> fat_buf [2]) {
- if ((fs -> fat_buf [0] != boot -> descr &&
- (fs -> fat_buf [0] != 0xf9 || boot -> descr != MEDIA_STD)) ||
- fs -> fat_buf [0] < MEDIA_STD){
- /* Unknown Media */
- return (-1);
- }
- if (fs -> fat_buf [1] != 0xff || fs -> fat_buf [2] != 0xff){
- /* FAT doesn't start with good values */
- return (-1);
- }
- }
-
- if (fs -> num_clus >= FAT12_MAX_NB) {
- /* Too much clusters */
- return (-1);
- }
-
- return check_fat (fs);
-}
-/*-----------------------------------------------------------------------------
- * read_fat --
- *-----------------------------------------------------------------------------
- */
-int read_fat (BootSector_t *boot, Fs_t *fs)
-{
- unsigned int buflen;
- int i;
-
- /* Allocate Fat Buffer */
- buflen = fs -> fat_len * SZ_STD_SECTOR;
- if (fs -> fat_buf) {
- free (fs -> fat_buf);
- }
-
- if ((fs -> fat_buf = malloc (buflen)) == NULL) {
- return (-1);
- }
-
- /* Try to read each Fat */
- for (i = 0; i< fs -> nb_fat; i++){
- if (read_one_fat (boot, fs, i) == 0) {
- /* Fat is OK */
- fs -> num_fat = i;
- break;
- }
- }
-
- if (i == fs -> nb_fat){
- return (-1);
- }
-
- if (fs -> fat_len > (((fs -> num_clus + 2) *
- (FAT_BITS / 4) -1 ) / 2 /
- SZ_STD_SECTOR + 1)) {
- return (-1);
- }
- return (0);
-}
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Stäubli Faverges - <www.staubli.com>
- * Pierre AUBERT p.aubert@staubli.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <malloc.h>
-
-#include "dos.h"
-#include "fdos.h"
-
-
-const char *month [] = {"Jan", "Feb", "Mar", "Apr", "May", "Jun", "Jul", "Aug", "Sep", "Oct", "Nov", "Dec"};
-
-Fs_t fs;
-File_t file;
-
-/*-----------------------------------------------------------------------------
- * dos_open --
- *-----------------------------------------------------------------------------
- */
-int dos_open(char *name)
-{
- int lg;
- int entry;
- char *fname;
-
- /* We need to suppress the " char around the name */
- if (name [0] == '"') {
- name ++;
- }
- lg = strlen (name);
- if (name [lg - 1] == '"') {
- name [lg - 1] = '\0';
- }
-
- /* Open file system */
- if (fs_init (&fs) < 0) {
- return -1;
- }
-
- /* Init the file descriptor */
- file.name = name;
- file.fs = &fs;
-
- /* find the subdirectory containing the file */
- if (open_subdir (&file) < 0) {
- return (-1);
- }
-
- fname = basename (name);
-
- /* if we try to open root directory */
- if (*fname == '\0') {
- file.file = file.subdir;
- return (0);
- }
-
- /* find the file in the subdir */
- entry = 0;
- if (vfat_lookup (&file.subdir,
- file.fs,
- &file.file.dir,
- &entry,
- 0,
- fname,
- ACCEPT_DIR | ACCEPT_PLAIN | SINGLE | DO_OPEN,
- 0,
- &file.file) != 0) {
- /* File not found */
- printf ("File not found\n");
- return (-1);
- }
-
- return 0;
-}
-
-/*-----------------------------------------------------------------------------
- * dos_read --
- *-----------------------------------------------------------------------------
- */
-int dos_read (ulong addr)
-{
- int read = 0, nb;
-
- /* Try to boot a directory ? */
- if (file.file.dir.attr & (ATTR_DIRECTORY | ATTR_VOLUME)) {
- printf ("Unable to boot %s !!\n", file.name);
- return (-1);
- }
- while (read < file.file.FileSize) {
- PRINTF ("read_file (%ld)\n", (file.file.FileSize - read));
- nb = read_file (&fs,
- &file.file,
- (char *)addr + read,
- read,
- (file.file.FileSize - read));
- PRINTF ("read_file -> %d\n", nb);
- if (nb < 0) {
- printf ("read error\n");
- return (-1);
- }
- read += nb;
- }
- return (read);
-}
-/*-----------------------------------------------------------------------------
- * dos_dir --
- *-----------------------------------------------------------------------------
- */
-int dos_dir (void)
-{
- int entry;
- Directory_t dir;
- char *name;
-
-
- if ((file.file.dir.attr & ATTR_DIRECTORY) == 0) {
- printf ("%s: not a directory !!\n", file.name);
- return (1);
- }
- entry = 0;
- if ((name = malloc (MAX_VNAMELEN + 1)) == NULL) {
- PRINTF ("Allcation error\n");
- return (1);
- }
-
- while (vfat_lookup (&file.file,
- file.fs,
- &dir,
- &entry,
- 0,
- NULL,
- ACCEPT_DIR | ACCEPT_PLAIN | MATCH_ANY,
- name,
- NULL) == 0) {
- /* Display file info */
- printf ("%3.3s %9d %s %02d %04d %02d:%02d:%02d %s\n",
- (dir.attr & ATTR_DIRECTORY) ? "dir" : " ",
- __le32_to_cpu (dir.size),
- month [DOS_MONTH (&dir) - 1],
- DOS_DAY (&dir),
- DOS_YEAR (&dir),
- DOS_HOUR (&dir),
- DOS_MINUTE (&dir),
- DOS_SEC (&dir),
- name);
-
- }
- free (name);
- return (0);
-}
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Stäubli Faverges - <www.staubli.com>
- * Pierre AUBERT p.aubert@staubli.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _FDOS_H_
-#define _FDOS_H_
-
-
-#undef FDOS_DEBUG
-
-#ifdef FDOS_DEBUG
-#define PRINTF(fmt,args...) printf (fmt ,##args)
-#else
-#define PRINTF(fmt,args...)
-#endif
-
-/* Data structure describing media */
-typedef struct fs
-{
- unsigned long tot_sectors;
-
- int cluster_size;
- int num_clus;
-
- int fat_start;
- int fat_len;
- int nb_fat;
- int num_fat;
-
- int dir_start;
- int dir_len;
-
- unsigned char *fat_buf;
-
-} Fs_t;
-
-/* Data structure describing one file system slot */
-typedef struct slot {
- int (*map) (struct fs *fs,
- struct slot *file,
- int where,
- int *len);
- unsigned long FileSize;
-
- unsigned short int FirstAbsCluNr;
- unsigned short int PreviousAbsCluNr;
- unsigned short int PreviousRelCluNr;
-
- Directory_t dir;
-} Slot_t;
-
-typedef struct file {
- char *name;
- int Case;
- Fs_t *fs;
- Slot_t subdir;
- Slot_t file;
-} File_t;
-
-
-/* dev.c */
-int dev_read (void *buffer, int where, int len);
-int dev_open (void);
-int check_dev (BootSector_t *boot, Fs_t *fs);
-
-/* fat.c */
-unsigned int fat_decode (Fs_t *fs, unsigned int num);
-int read_fat (BootSector_t *boot, Fs_t *fs);
-
-/* vfat.c */
-int vfat_lookup (Slot_t *dir,
- Fs_t *fs,
- Directory_t *dirent,
- int *entry,
- int *vfat_start,
- char *filename,
- int flags,
- char *outname,
- Slot_t *file);
-
-/* subdir.c */
-char *basename (char *name);
-int open_subdir (File_t *desc);
-int open_file (Slot_t *file, Directory_t *dir);
-int read_file (Fs_t *fs,
- Slot_t *file,
- char *buf,
- int where,
- int len);
-void init_subdir (void);
-
-/* fs.c */
-int fs_init (Fs_t *fs);
-
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Stäubli Faverges - <www.staubli.com>
- * Pierre AUBERT p.aubert@staubli.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <malloc.h>
-
-#include "dos.h"
-#include "fdos.h"
-
-
-/*-----------------------------------------------------------------------------
- * fill_fs -- Read info on file system
- *-----------------------------------------------------------------------------
- */
-static int fill_fs (BootSector_t *boot, Fs_t *fs)
-{
-
- fs -> fat_start = __le16_to_cpu (boot -> nrsvsect);
- fs -> fat_len = __le16_to_cpu (boot -> fatlen);
- fs -> nb_fat = boot -> nfat;
-
- fs -> dir_start = fs -> fat_start + fs -> nb_fat * fs -> fat_len;
- fs -> dir_len = __le16_to_cpu (boot -> dirents) * MDIR_SIZE / SZ_STD_SECTOR;
- fs -> cluster_size = boot -> clsiz;
- fs -> num_clus = (fs -> tot_sectors - fs -> dir_start - fs -> dir_len) / fs -> cluster_size;
-
- return (0);
-}
-
-/*-----------------------------------------------------------------------------
- * fs_init --
- *-----------------------------------------------------------------------------
- */
-int fs_init (Fs_t *fs)
-{
- BootSector_t *boot;
-
- /* Initialize physical device */
- if (dev_open () < 0) {
- PRINTF ("Unable to initialize the fdc\n");
- return (-1);
- }
- init_subdir ();
-
- /* Allocate space for read the boot sector */
- if ((boot = (BootSector_t *)malloc (sizeof (BootSector_t))) == NULL) {
- PRINTF ("Unable to allocate space for boot sector\n");
- return (-1);
- }
-
- /* read boot sector */
- if (dev_read (boot, 0, 1)){
- PRINTF ("Error during boot sector read\n");
- free (boot);
- return (-1);
- }
-
- /* we verify it'a a DOS diskette */
- if (boot -> jump [0] != JUMP_0_1 && boot -> jump [0] != JUMP_0_2) {
- PRINTF ("Not a DOS diskette\n");
- free (boot);
- return (-1);
- }
-
- if (boot -> descr < MEDIA_STD) {
- /* We handle only recent medias (type F0) */
- PRINTF ("unrecognized diskette type\n");
- free (boot);
- return (-1);
- }
-
- if (check_dev (boot, fs) < 0) {
- PRINTF ("Bad diskette\n");
- free (boot);
- return (-1);
- }
-
- if (fill_fs (boot, fs) < 0) {
- free (boot);
-
- return (-1);
- }
-
- /* Read FAT */
- if (read_fat (boot, fs) < 0) {
- free (boot);
- return (-1);
- }
-
- free (boot);
- return (0);
-}
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Stäubli Faverges - <www.staubli.com>
- * Pierre AUBERT p.aubert@staubli.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <malloc.h>
-
-#include "dos.h"
-#include "fdos.h"
-
-static int cache_sect;
-static unsigned char cache [SZ_STD_SECTOR];
-
-
-#define min(x,y) ((x)<(y)?(x):(y))
-
-static int descend (Slot_t *parent,
- Fs_t *fs,
- char *path);
-
-/*-----------------------------------------------------------------------------
- * init_subdir --
- *-----------------------------------------------------------------------------
- */
-void init_subdir (void)
-{
- cache_sect = -1;
-}
-/*-----------------------------------------------------------------------------
- * basename --
- *-----------------------------------------------------------------------------
- */
-char *basename (char *name)
-{
- register char *cptr;
-
- if (!name || !*name) {
- return ("");
- }
-
- for (cptr= name; *cptr++; );
- while (--cptr >= name) {
- if (*cptr == '/') {
- return (cptr + 1);
- }
- }
- return(name);
-}
-/*-----------------------------------------------------------------------------
- * root_map --
- *-----------------------------------------------------------------------------
- */
-static int root_map (Fs_t *fs, Slot_t *file, int where, int *len)
-{
- *len = min (*len, fs -> dir_len * SZ_STD_SECTOR - where);
- if (*len < 0 ) {
- *len = 0;
- return (-1);
- }
- return fs -> dir_start * SZ_STD_SECTOR + where;
-}
-/*-----------------------------------------------------------------------------
- * normal_map --
- *-----------------------------------------------------------------------------
- */
-static int normal_map (Fs_t *fs, Slot_t *file, int where, int *len)
-{
- int offset;
- int NrClu;
- unsigned short RelCluNr;
- unsigned short CurCluNr;
- unsigned short NewCluNr;
- unsigned short AbsCluNr;
- int clus_size;
-
- clus_size = fs -> cluster_size * SZ_STD_SECTOR;
- offset = where % clus_size;
-
- *len = min (*len, file -> FileSize - where);
-
- if (*len < 0 ) {
- *len = 0;
- return (0);
- }
-
- if (file -> FirstAbsCluNr < 2){
- *len = 0;
- return (0);
- }
-
- RelCluNr = where / clus_size;
-
- if (RelCluNr >= file -> PreviousRelCluNr){
- CurCluNr = file -> PreviousRelCluNr;
- AbsCluNr = file -> PreviousAbsCluNr;
- } else {
- CurCluNr = 0;
- AbsCluNr = file -> FirstAbsCluNr;
- }
-
-
- NrClu = (offset + *len - 1) / clus_size;
- while (CurCluNr <= RelCluNr + NrClu) {
- if (CurCluNr == RelCluNr){
- /* we have reached the beginning of our zone. Save
- * coordinates */
- file -> PreviousRelCluNr = RelCluNr;
- file -> PreviousAbsCluNr = AbsCluNr;
- }
- NewCluNr = fat_decode (fs, AbsCluNr);
- if (NewCluNr == 1 || NewCluNr == 0) {
- PRINTF("Fat problem while decoding %d %x\n",
- AbsCluNr, NewCluNr);
- return (-1);
- }
- if (CurCluNr == RelCluNr + NrClu) {
- break;
- }
-
- if (CurCluNr < RelCluNr && NewCluNr == FAT12_END) {
- *len = 0;
- return 0;
- }
-
- if (CurCluNr >= RelCluNr && NewCluNr != AbsCluNr + 1)
- break;
- CurCluNr++;
- AbsCluNr = NewCluNr;
- }
-
- *len = min (*len, (1 + CurCluNr - RelCluNr) * clus_size - offset);
-
- return (((file -> PreviousAbsCluNr - 2) * fs -> cluster_size +
- fs -> dir_start + fs -> dir_len) *
- SZ_STD_SECTOR + offset);
-}
-/*-----------------------------------------------------------------------------
- * open_subdir -- open the subdir containing the file
- *-----------------------------------------------------------------------------
- */
-int open_subdir (File_t *desc)
-{
- char *pathname;
- char *tmp, *s, *path;
- char terminator;
-
- if ((pathname = (char *)malloc (MAX_PATH)) == NULL) {
- return (-1);
- }
-
- strcpy (pathname, desc -> name);
-
- /* Suppress file name */
- tmp = basename (pathname);
- *tmp = '\0';
-
- /* root directory init */
- desc -> subdir.FirstAbsCluNr = 0;
- desc -> subdir.FileSize = -1;
- desc -> subdir.map = root_map;
- desc -> subdir.dir.attr = ATTR_DIRECTORY;
-
- tmp = pathname;
- for (s = tmp; ; ++s) {
- if (*s == '/' || *s == '\0') {
- path = tmp;
- terminator = *s;
- *s = '\0';
- if (s != tmp && strcmp (path,".")) {
- if (descend (&desc -> subdir, desc -> fs, path) < 0) {
- free (pathname);
- return (-1);
- }
- }
- if (terminator == 0) {
- break;
- }
- tmp = s + 1;
- }
- }
- free (pathname);
- return (0);
-}
-/*-----------------------------------------------------------------------------
- * descend --
- *-----------------------------------------------------------------------------
- */
-static int descend (Slot_t *parent,
- Fs_t *fs,
- char *path)
-{
- int entry;
- Slot_t SubDir;
-
- if(path[0] == '\0' || strcmp (path, ".") == 0) {
- return (0);
- }
-
-
- entry = 0;
- if (vfat_lookup (parent,
- fs,
- &(SubDir.dir),
- &entry,
- 0,
- path,
- ACCEPT_DIR | SINGLE | DO_OPEN,
- 0,
- &SubDir) == 0) {
- *parent = SubDir;
- return (0);
- }
-
- if (strcmp(path, "..") == 0) {
- parent -> FileSize = -1;
- parent -> FirstAbsCluNr = 0;
- parent -> map = root_map;
- return (0);
- }
- return (-1);
-}
-/*-----------------------------------------------------------------------------
- * open_file --
- *-----------------------------------------------------------------------------
- */
-int open_file (Slot_t *file, Directory_t *dir)
-{
- int first;
- unsigned long size;
-
- first = __le16_to_cpu (dir -> start);
-
- if(first == 0 &&
- (dir -> attr & ATTR_DIRECTORY) != 0) {
- file -> FirstAbsCluNr = 0;
- file -> FileSize = -1;
- file -> map = root_map;
- return (0);
- }
-
- if ((dir -> attr & ATTR_DIRECTORY) != 0) {
- size = (1UL << 31) - 1;
- }
- else {
- size = __le32_to_cpu (dir -> size);
- }
-
- file -> map = normal_map;
- file -> FirstAbsCluNr = first;
- file -> PreviousRelCluNr = 0xffff;
- file -> FileSize = size;
- return (0);
-}
-/*-----------------------------------------------------------------------------
- * read_file --
- *-----------------------------------------------------------------------------
- */
-int read_file (Fs_t *fs,
- Slot_t *file,
- char *buf,
- int where,
- int len)
-{
- int pos;
- int read, nb, sect, offset;
-
- pos = file -> map (fs, file, where, &len);
- if (pos < 0) {
- return -1;
- }
- if (len == 0) {
- return (0);
- }
-
- /* Compute sector number */
- sect = pos / SZ_STD_SECTOR;
- offset = pos % SZ_STD_SECTOR;
- read = 0;
-
- if (offset) {
- /* Read doesn't start at the sector beginning. We need to use our */
- /* cache */
- if (sect != cache_sect) {
- if (dev_read (cache, sect, 1) < 0) {
- return (-1);
- }
- cache_sect = sect;
- }
- nb = min (len, SZ_STD_SECTOR - offset);
-
- memcpy (buf, cache + offset, nb);
- read += nb;
- len -= nb;
- sect += 1;
- }
-
- if (len > SZ_STD_SECTOR) {
- nb = (len - 1) / SZ_STD_SECTOR;
- if (dev_read (buf + read, sect, nb) < 0) {
- return ((read) ? read : -1);
- }
- /* update sector position */
- sect += nb;
-
- /* Update byte position */
- nb *= SZ_STD_SECTOR;
- read += nb;
- len -= nb;
- }
-
- if (len) {
- if (sect != cache_sect) {
- if (dev_read (cache, sect, 1) < 0) {
- return ((read) ? read : -1);
- cache_sect = -1;
- }
- cache_sect = sect;
- }
-
- memcpy (buf + read, cache, len);
- read += len;
- }
- return (read);
-}
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Stäubli Faverges - <www.staubli.com>
- * Pierre AUBERT p.aubert@staubli.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <linux/ctype.h>
-
-#include "dos.h"
-#include "fdos.h"
-
-static int dir_read (Fs_t *fs,
- Slot_t *dir,
- Directory_t *dirent,
- int num,
- struct vfat_state *v);
-
-static int unicode_read (char *in, char *out, int num);
-static int match (const char *s, const char *p);
-static unsigned char sum_shortname (char *name);
-static int check_vfat (struct vfat_state *v, Directory_t *dir);
-static char *conv_name (char *name, char *ext, char Case, char *ans);
-
-
-/*-----------------------------------------------------------------------------
- * clear_vfat --
- *-----------------------------------------------------------------------------
- */
-static void clear_vfat (struct vfat_state *v)
-{
- v -> subentries = 0;
- v -> status = 0;
-}
-
-/*-----------------------------------------------------------------------------
- * vfat_lookup --
- *-----------------------------------------------------------------------------
- */
-int vfat_lookup (Slot_t *dir,
- Fs_t *fs,
- Directory_t *dirent,
- int *entry,
- int *vfat_start,
- char *filename,
- int flags,
- char *outname,
- Slot_t *file)
-{
- int found;
- struct vfat_state vfat;
- char newfile [VSE_NAMELEN];
- int vfat_present = 0;
-
- if (*entry == -1) {
- return -1;
- }
-
- found = 0;
- clear_vfat (&vfat);
- while (1) {
- if (dir_read (fs, dir, dirent, *entry, &vfat) < 0) {
- if (vfat_start) {
- *vfat_start = *entry;
- }
- break;
- }
- (*entry)++;
-
- /* Empty slot */
- if (dirent -> name[0] == '\0'){
- if (vfat_start == 0) {
- break;
- }
- continue;
- }
-
- if (dirent -> attr == ATTR_VSE) {
- /* VSE entry, continue */
- continue;
- }
- if ( (dirent -> name [0] == DELMARK) ||
- ((dirent -> attr & ATTR_DIRECTORY) != 0 &&
- (flags & ACCEPT_DIR) == 0) ||
- ((dirent -> attr & ATTR_VOLUME) != 0 &&
- (flags & ACCEPT_LABEL) == 0) ||
- (((dirent -> attr & (ATTR_DIRECTORY | ATTR_VOLUME)) == 0) &&
- (flags & ACCEPT_PLAIN) == 0)) {
- clear_vfat (&vfat);
- continue;
- }
-
- vfat_present = check_vfat (&vfat, dirent);
- if (vfat_start) {
- *vfat_start = *entry - 1;
- if (vfat_present) {
- *vfat_start -= vfat.subentries;
- }
- }
-
- if (dirent -> attr & ATTR_VOLUME) {
- strncpy (newfile, dirent -> name, 8);
- newfile [8] = '\0';
- strncat (newfile, dirent -> ext, 3);
- newfile [11] = '\0';
- }
- else {
- conv_name (dirent -> name, dirent -> ext, dirent -> Case, newfile);
- }
-
- if (flags & MATCH_ANY) {
- found = 1;
- break;
- }
-
- if ((vfat_present && match (vfat.name, filename)) ||
- (match (newfile, filename))) {
- found = 1;
- break;
- }
- clear_vfat (&vfat);
- }
-
- if (found) {
- if ((flags & DO_OPEN) && file) {
- if (open_file (file, dirent) < 0) {
- return (-1);
- }
- }
- if (outname) {
- if (vfat_present) {
- strcpy (outname, vfat.name);
- }
- else {
- strcpy (outname, newfile);
- }
- }
- return (0); /* File found */
- } else {
- *entry = -1;
- return -1; /* File not found */
- }
-}
-
-/*-----------------------------------------------------------------------------
- * dir_read -- Read one directory entry
- *-----------------------------------------------------------------------------
- */
-static int dir_read (Fs_t *fs,
- Slot_t *dir,
- Directory_t *dirent,
- int num,
- struct vfat_state *v)
-{
-
- /* read the directory entry */
- if (read_file (fs,
- dir,
- (char *)dirent,
- num * MDIR_SIZE,
- MDIR_SIZE) != MDIR_SIZE) {
- return (-1);
- }
-
- if (v && (dirent -> attr == ATTR_VSE)) {
- struct vfat_subentry *vse;
- unsigned char id, last_flag;
- char *c;
-
- vse = (struct vfat_subentry *) dirent;
- id = vse -> id & VSE_MASK;
- last_flag = (vse -> id & VSE_LAST);
- if (id > MAX_VFAT_SUBENTRIES) {
- /* Invalid VSE entry */
- return (-1);
- }
-
-
- /* Decode VSE */
- if(v -> sum != vse -> sum) {
- clear_vfat (v);
- v -> sum = vse -> sum;
- }
-
-
- v -> status |= 1 << (id - 1);
- if (last_flag) {
- v -> subentries = id;
- }
-
- c = &(v -> name [VSE_NAMELEN * (id - 1)]);
- c += unicode_read (vse->text1, c, VSE1SIZE);
- c += unicode_read (vse->text2, c, VSE2SIZE);
- c += unicode_read (vse->text3, c, VSE3SIZE);
-
- if (last_flag) {
- *c = '\0'; /* Null terminate long name */
- }
-
- }
- return (0);
-}
-
-/*-----------------------------------------------------------------------------
- * unicode_read --
- *-----------------------------------------------------------------------------
- */
-static int unicode_read (char *in, char *out, int num)
-{
- int j;
-
- for (j = 0; j < num; ++j) {
- if (in [1])
- *out = '_';
- else
- *out = in [0];
- out ++;
- in += 2;
- }
- return num;
-}
-
-/*-----------------------------------------------------------------------------
- * match --
- *-----------------------------------------------------------------------------
- */
-static int match (const char *s, const char *p)
-{
-
- for (; *p != '\0'; ) {
- if (toupper (*s) != toupper (*p)) {
- return (0);
- }
- p++;
- s++;
- }
-
- if (*s != '\0') {
- return (0);
- }
- else {
- return (1);
- }
-}
-/*-----------------------------------------------------------------------------
- * sum_shortname --
- *-----------------------------------------------------------------------------
- */
-static unsigned char sum_shortname (char *name)
-{
- unsigned char sum;
- int j;
-
- for (j = sum = 0; j < 11; ++j) {
- sum = ((sum & 1) ? 0x80 : 0) + (sum >> 1) +
- (name [j] ? name [j] : ' ');
- }
- return (sum);
-}
-/*-----------------------------------------------------------------------------
- * check_vfat --
- * Return 1 if long name is valid, 0 else
- *-----------------------------------------------------------------------------
- */
-static int check_vfat (struct vfat_state *v, Directory_t *dir)
-{
- char name[12];
-
- if (v -> subentries == 0) {
- return 0;
- }
-
- strncpy (name, dir -> name, 8);
- strncpy (name + 8, dir -> ext, 3);
- name [11] = '\0';
-
- if (v -> sum != sum_shortname (name)) {
- return 0;
- }
-
- if( (v -> status & ((1 << v -> subentries) - 1)) !=
- (1 << v -> subentries) - 1) {
- return 0;
- }
- v->name [VSE_NAMELEN * v -> subentries] = 0;
-
- return 1;
-}
-/*-----------------------------------------------------------------------------
- * conv_name --
- *-----------------------------------------------------------------------------
- */
-static char *conv_name (char *name, char *ext, char Case, char *ans)
-{
- char tname [9], text [4];
- int i;
-
- i = 0;
- while (i < 8 && name [i] != ' ' && name [i] != '\0') {
- tname [i] = name [i];
- i++;
- }
- tname [i] = '\0';
-
- if (Case & BASECASE) {
- for (i = 0; i < 8 && tname [i]; i++) {
- tname [i] = tolower (tname [i]);
- }
- }
-
- i = 0;
- while (i < 3 && ext [i] != ' ' && ext [i] != '\0') {
- text [i] = ext [i];
- i++;
- }
- text [i] = '\0';
-
- if (Case & EXTCASE){
- for (i = 0; i < 3 && text [i]; i++) {
- text [i] = tolower (text [i]);
- }
- }
-
- if (*text) {
- strcpy (ans, tname);
- strcat (ans, ".");
- strcat (ans, text);
- }
- else {
- strcpy(ans, tname);
- }
- return (ans);
-}
return -1;
}
+static inline int fs_exists_unsupported(const char *filename)
+{
+ return 0;
+}
+
static inline int fs_read_unsupported(const char *filename, void *buf,
int offset, int len)
{
struct fstype_info {
int fstype;
+ /*
+ * Is it legal to pass NULL as .probe()'s fs_dev_desc parameter? This
+ * should be false in most cases. For "virtual" filesystems which
+ * aren't based on a U-Boot block device (e.g. sandbox), this can be
+ * set to true. This should also be true for the dumm entry at the end
+ * of fstypes[], since that is essentially a "virtual" (non-existent)
+ * filesystem.
+ */
+ bool null_dev_desc_ok;
int (*probe)(block_dev_desc_t *fs_dev_desc,
disk_partition_t *fs_partition);
int (*ls)(const char *dirname);
+ int (*exists)(const char *filename);
int (*read)(const char *filename, void *buf, int offset, int len);
int (*write)(const char *filename, void *buf, int offset, int len);
void (*close)(void);
#ifdef CONFIG_FS_FAT
{
.fstype = FS_TYPE_FAT,
+ .null_dev_desc_ok = false,
.probe = fat_set_blk_dev,
.close = fat_close,
.ls = file_fat_ls,
+ .exists = fat_exists,
.read = fat_read_file,
+ .write = fs_write_unsupported,
},
#endif
#ifdef CONFIG_FS_EXT4
{
.fstype = FS_TYPE_EXT,
+ .null_dev_desc_ok = false,
.probe = ext4fs_probe,
.close = ext4fs_close,
.ls = ext4fs_ls,
+ .exists = ext4fs_exists,
.read = ext4_read_file,
+ .write = fs_write_unsupported,
},
#endif
#ifdef CONFIG_SANDBOX
{
.fstype = FS_TYPE_SANDBOX,
+ .null_dev_desc_ok = true,
.probe = sandbox_fs_set_blk_dev,
.close = sandbox_fs_close,
.ls = sandbox_fs_ls,
+ .exists = sandbox_fs_exists,
.read = fs_read_sandbox,
.write = fs_write_sandbox,
},
#endif
{
.fstype = FS_TYPE_ANY,
+ .null_dev_desc_ok = true,
.probe = fs_probe_unsupported,
.close = fs_close_unsupported,
.ls = fs_ls_unsupported,
+ .exists = fs_exists_unsupported,
.read = fs_read_unsupported,
.write = fs_write_unsupported,
},
fstype != info->fstype)
continue;
+ if (!fs_dev_desc && !info->null_dev_desc_ok)
+ continue;
+
if (!info->probe(fs_dev_desc, &fs_partition)) {
fs_type = info->fstype;
return 0;
return ret;
}
+int fs_exists(const char *filename)
+{
+ int ret;
+
+ struct fstype_info *info = fs_get_info(fs_type);
+
+ ret = info->exists(filename);
+
+ fs_close();
+
+ return ret;
+}
+
int fs_read(const char *filename, ulong addr, int offset, int len)
{
struct fstype_info *info = fs_get_info(fs_type);
void *buf;
int ret;
- /*
- * We don't actually know how many bytes are being read, since len==0
- * means read the whole file.
- */
buf = map_sysmem(addr, len);
ret = info->write(filename, buf, offset, len);
unmap_sysmem(buf);
- /* If we requested a specific number of bytes, check we got it */
- if (ret >= 0 && len && ret != len) {
+ if (ret >= 0 && ret != len) {
printf("** Unable to write file %s **\n", filename);
ret = -1;
}
return 0;
}
+int file_exists(const char *dev_type, const char *dev_part, const char *file,
+ int fstype)
+{
+ if (fs_set_blk_dev(dev_type, dev_part, fstype))
+ return 0;
+
+ return fs_exists(file);
+}
+
int do_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
int fstype)
{
return 0;
}
+int sandbox_fs_exists(const char *filename)
+{
+ ssize_t sz;
+
+ sz = os_get_filesize(filename);
+ return sz >= 0;
+}
+
void sandbox_fs_close(void)
{
}
obj-y += lpt_commit.o scan.o lprops.o
obj-y += tnc.o tnc_misc.o debug.o crc16.o budget.o
obj-y += log.o orphan.o recovery.o replay.o
-
-# SEE README.arm-unaligned-accesses
-$(obj)super.o: CFLAGS += $(PLATFORM_NO_UNALIGNED)
int ubifs_decompress(const void *buf, int len, void *out, int *out_len,
int compr_type);
+/* these are used in cmd_ubifs.c */
+int ubifs_init(void);
+int ubifs_mount(char *vol_name);
+void ubifs_umount(struct ubifs_info *c);
+int ubifs_ls(char *dir_name);
+int ubifs_load(char *filename, u32 addr, u32 size);
+
#include "debug.h"
#include "misc.h"
#include "key.h"
yaffs_summary.o yaffs_tagscompat.o yaffs_verify.o yaffs_yaffs1.o \
yaffs_yaffs2.o yaffs_mtdif.o yaffs_mtdif2.o
-YCFLAGS = -DCONFIG_YAFFS_DIRECT -DCONFIG_YAFFS_SHORT_NAMES_IN_RAM
-YCFLAGS += -DCONFIG_YAFFS_YAFFS2 -DNO_Y_INLINE
-YCFLAGS += -DCONFIG_YAFFS_PROVIDE_DEFS -DCONFIG_YAFFSFS_PROVIDE_VALUES
-
-CFLAGS += $(YCFLAGS)
-CPPFLAGS += $(YCFLAGS)
+ccflags-y = -DCONFIG_YAFFS_DIRECT -DCONFIG_YAFFS_SHORT_NAMES_IN_RAM \
+ -DCONFIG_YAFFS_YAFFS2 -DNO_Y_INLINE \
+ -DCONFIG_YAFFS_PROVIDE_DEFS -DCONFIG_YAFFSFS_PROVIDE_VALUES
/autoconf.mk*
-/asm
/bmp_logo.h
/bmp_logo_data.h
/config.h
extern void _start(void);
/*
- * ARM needs to use offsets for symbols, since the values of some symbols
- * are not resolved prior to relocation (and are just 0). Maybe this can be
- * resolved, or maybe other architectures are similar, iwc this should be
- * promoted to an architecture option.
+ * ARM defines its symbols as char[]. Other arches define them as ulongs.
*/
#ifdef CONFIG_ARM
-#define CONFIG_SYS_SYM_OFFSETS
-#endif
-
-#ifdef CONFIG_SYS_SYM_OFFSETS
-/* Start/end of the relocation entries, as an offset from _start */
-extern ulong _rel_dyn_start_ofs;
-extern ulong _rel_dyn_end_ofs;
-
-/* End of the region to be relocated, as an offset form _start */
-extern ulong _image_copy_end_ofs;
-extern ulong _bss_start_ofs; /* BSS start relative to _start */
-extern ulong _bss_end_ofs; /* BSS end relative to _start */
-extern ulong _end_ofs; /* end of image relative to _start */
-
-extern ulong _TEXT_BASE; /* code start */
+extern char __bss_start[];
+extern char __bss_end[];
+extern char __image_copy_start[];
+extern char __image_copy_end[];
+extern char __rel_dyn_start[];
+extern char __rel_dyn_end[];
#else /* don't use offsets: */
--- /dev/null
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Bitfield operations
+ *
+ * These are generic bitfield operations which allow manipulation of variable
+ * width bitfields within a word. One use of this would be to use data tables
+ * to determine how to reprogram fields within R/W hardware registers.
+ *
+ * Example:
+ *
+ * old_reg_val
+ * +--------+----+---+--+-----+----------+
+ * | | | | | old | |
+ * +--------+----+---+--+-----+----------+
+ *
+ * new_reg_val
+ * +--------+----+---+--+-----+----------+
+ * | | | | | new | |
+ * +--------+----+---+--+-----+----------+
+ *
+ * mask = bitfield_mask(10, 5);
+ * old = bitfield_extract(old_reg_val, 10, 5);
+ * new_reg_val = bitfield_replace(old_reg_val, 10, 5, new);
+ *
+ * The numbers 10 and 5 could for example come from data
+ * tables which describe all bitfields in all registers.
+ */
+
+#include <linux/types.h>
+
+/* Produces a mask of set bits covering a range of a uint value */
+static inline uint bitfield_mask(uint shift, uint width)
+{
+ return ((1 << width) - 1) << shift;
+}
+
+/* Extract the value of a bitfield found within a given register value */
+static inline uint bitfield_extract(uint reg_val, uint shift, uint width)
+{
+ return (reg_val & bitfield_mask(shift, width)) >> shift;
+}
+
+/*
+ * Replace the value of a bitfield found within a given register value
+ * Returns the newly modified uint value with the replaced field.
+ */
+static inline uint bitfield_replace(uint reg_val, uint shift, uint width,
+ uint bitfield_val)
+{
+ uint mask = bitfield_mask(shift, width);
+
+ return (reg_val & ~mask) | (bitfield_val << shift);
+}
--- /dev/null
+#ifndef _CLK_H_
+#define _CLK_H_
+
+int soc_clk_dump(void);
+
+#endif /* _CLK_H_ */
int last_stage_init(void);
extern ulong monitor_flash_len;
int mac_read_from_eeprom(void);
-extern u8 _binary_dt_dtb_start[]; /* embedded device tree blob */
+extern u8 __dtb_dt_begin[]; /* embedded device tree blob */
int set_cpu_clk_info(void);
+#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void);
+#else
+static inline int print_cpuinfo(void)
+{
+ return 0;
+}
+#endif
int update_flash_size(int flash_size);
/**
#ifdef CONFIG_MIPS
# include <asm/u-boot-mips.h>
#endif /* CONFIG_MIPS */
+#ifdef CONFIG_ARC
+# include <asm/u-boot-arc.h>
+#endif /* CONFIG_ARC */
#ifdef CONFIG_AUTO_COMPLETE
int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf);
/* common/memsize.c */
long get_ram_size (long *, long);
+phys_size_t get_effective_memsize(void);
/* $(BOARD)/$(BOARD).c */
void reset_phy (void);
#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
+/*
+ * Divide positive or negative dividend by positive divisor and round
+ * to closest integer. Result is undefined for negative divisors and
+ * for negative dividends if the divisor variable type is unsigned.
+ */
+#define DIV_ROUND_CLOSEST(x, divisor)( \
+{ \
+ typeof(x) __x = x; \
+ typeof(divisor) __d = divisor; \
+ (((typeof(x))-1) > 0 || \
+ ((typeof(divisor))-1) > 0 || (__x) > 0) ? \
+ (((__x) + ((__d) / 2)) / (__d)) : \
+ (((__x) - ((__d) / 2)) / (__d)); \
+} \
+)
+
#define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1)
#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
#define CONFIG_CMD_BSP /* Board Specific functions */
#define CONFIG_CMD_CACHE /* icache, dcache */
#define CONFIG_CMD_CDP /* Cisco Discovery Protocol */
+#define CONFIG_CMD_CLK /* Clock support */
#define CONFIG_CMD_CONSOLE /* coninfo */
#define CONFIG_CMD_DATE /* support for RTC, date/time...*/
#define CONFIG_CMD_DHCP /* DHCP Support */
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_FDC /* Floppy Disk Support */
-#define CONFIG_CMD_FDOS /* Floppy DOS support */
#define CONFIG_CMD_FLASH /* flinfo, erase, protect */
#define CONFIG_CMD_FPGA /* FPGA configuration Support */
#define CONFIG_CMD_FUSE /* Device fuse support */
--- /dev/null
+/*
+ * Copyright 2013-2014 Red Hat, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CONFIG_CMD_DISTRO_DEFAULTS_H
+#define _CONFIG_CMD_DISTRO_DEFAULTS_H
+
+/*
+ * List of all commands and options that when defined enables support for
+ * features required by distros to support boards in a standardised and
+ * consitant manner.
+ */
+
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_PXE
+#define CONFIG_BOOTP_SUBNETMASK
+
+#if defined(__arm__)
+#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100
+#if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__)
+#define CONFIG_BOOTP_VCI_STRING "U-boot.armv7"
+#else
+#define CONFIG_BOOTP_VCI_STRING "U-boot.arm"
+#endif
+#endif
+
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_PXE
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_BOOTDELAY 2
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_MENU
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_SUPPORT_RAW_INITRD
+#define CONFIG_SYS_HUSH_PARSER
+
+#endif /* _CONFIG_CMD_DISTRO_DEFAULTS_H */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
#define CONFIG_SYS_NAND_SELECT_DEVICE
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/* Network configuration */
/* End of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
#define CONFIG_SYS_INIT_RAM_CTRL 0x221
-/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE 256
#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \
- CONFIG_SYS_GBL_DATA_SIZE) - 32)
+ GENERATED_GBL_DATA_SIZE) - 32)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE -\
- CONFIG_SYS_GBL_DATA_SIZE)
+ GENERATED_GBL_DATA_SIZE)
/*
* Local Bus Configuration & Clock Setup
#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
#else
-#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
+#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
#define CONFIG_SYS_TEXT_BASE 0xf8f82000
#endif /* CONFIG_NAND_SPL */
#endif
#endif
#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#define CONFIG_SYS_TEXT_BASE 0xeff40000
#endif
#ifndef CONFIG_RESET_VECTOR_ADDRESS
/* NAND boot: 4K NAND loader config */
#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
#define CONFIG_SYS_NAND_U_BOOT_START \
(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
#if defined(CONFIG_RAMBOOT_NAND)
#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
#elif defined(CONFIG_RAMBOOT_SPIFLASH)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#endif
#else
#define CONFIG_ENV_IS_IN_FLASH 1
- #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
- #define CONFIG_ENV_ADDR 0xfff80000
- #else
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
- #endif
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#endif
#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
#else
-#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
+#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
#define CONFIG_SYS_TEXT_BASE 0xf8f82000
#endif
#endif
#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
#else
-#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
+#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
#define CONFIG_SYS_TEXT_BASE 0xf8f82000
#endif /* CONFIG_NAND_SPL */
#endif
#define CONFIG_NAND_FSL_IFC
#ifdef CONFIG_SDCARD
-#define CONFIG_RAMBOOT_SDCARD
-#define CONFIG_SYS_TEXT_BASE 0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE 0x11001000
+#define CONFIG_SPL_TEXT_BASE 0xD0001000
+#define CONFIG_SPL_PAD_TO 0x18000
+#define CONFIG_SPL_MAX_SIZE (96 * 1024)
+#define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#define CONFIG_SPL_MMC_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#endif
#endif
#ifdef CONFIG_SPIFLASH
+#ifdef CONFIG_SECURE_BOOT
#define CONFIG_RAMBOOT_SPIFLASH
#define CONFIG_SYS_TEXT_BASE 0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
+#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
+#else
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE 0x11001000
+#define CONFIG_SPL_TEXT_BASE 0xD0001000
+#define CONFIG_SPL_PAD_TO 0x18000
+#define CONFIG_SPL_MAX_SIZE (96 * 1024)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#define CONFIG_SPL_SPI_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#endif
+#endif
#endif
#ifdef CONFIG_NAND
#define CONFIG_SPL
+#ifdef CONFIG_SECURE_BOOT
#define CONFIG_SPL_INIT_MINIMAL
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#else
+#define CONFIG_TPL
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SPL_NAND_BOOT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NAND_INIT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SPL_MAX_SIZE (128 << 10)
+#define CONFIG_SPL_TEXT_BASE 0xD0001000
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
+#elif defined(CONFIG_SPL_BUILD)
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TEXT_BASE 0xff800000
+#define CONFIG_SPL_MAX_SIZE 8192
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000
+#define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
+#endif
+#define CONFIG_SPL_PAD_TO 0x20000
+#define CONFIG_TPL_PAD_TO 0x20000
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SYS_TEXT_BASE 0x11001000
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#endif
#endif
-
#ifdef CONFIG_NAND_SECBOOT /* NAND Boot */
#define CONFIG_RAMBOOT_NAND
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
+/*
+ * Config the L2 Cache as L2 SRAM
+ */
+#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE (256 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE (16 << 10)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10)
+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE (256 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
+#else
+#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE (256 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
+#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+#endif
+#endif
+#endif
+
/* Serial Port */
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
#define CONFIG_NS16550_MIN_FUNCTIONS
#endif
/*
* Environment
*/
-#if defined(CONFIG_RAMBOOT_SDCARD)
+#if defined(CONFIG_SDCARD)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_FSL_FIXED_MMC_LOCATION
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
-#elif defined(CONFIG_RAMBOOT_SPIFLASH)
+#elif defined(CONFIG_SPIFLASH)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SIZE 0x2000
#elif defined(CONFIG_NAND)
#define CONFIG_ENV_IS_IN_NAND
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#else
#if defined(CONFIG_P1010RDB_PA)
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
#define CONFIG_ENV_SIZE (16 * 1024)
#define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */
#endif
-#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#endif
+#define CONFIG_ENV_OFFSET (1024 * 1024)
#elif defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x11001000
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
-#define CONFIG_SPL_PAD_TO 0x18000
-#define CONFIG_SPL_MAX_SIZE (96 * 1024)
+#define CONFIG_SPL_PAD_TO 0x20000
+#define CONFIG_SPL_MAX_SIZE (128 * 1024)
#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
-#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
#define CONFIG_SPL_MMC_BOOT
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x11001000
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
-#define CONFIG_SPL_PAD_TO 0x18000
-#define CONFIG_SPL_MAX_SIZE (96 * 1024)
+#define CONFIG_SPL_PAD_TO 0x20000
+#define CONFIG_SPL_MAX_SIZE (128 * 1024)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
#define CONFIG_SPL_SPI_BOOT
#define CONFIG_SYS_L2_SIZE (256 << 10)
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
-#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
-#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
#elif defined(CONFIG_NAND)
#ifdef CONFIG_TPL_BUILD
#ifdef CONFIG_NAND_SPL
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
#else
-#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
+#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif /* CONFIG_NAND_SPL */
#endif
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+ (CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
#else
-#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
+#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
#define CONFIG_SYS_TEXT_BASE 0xf8f82000
#endif /* CONFIG_NAND_SPL */
#endif
#endif
#ifdef CONFIG_FMAN_ENET
-#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10
-#define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11
-#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
+#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01
+#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02
#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/
/*
* For booting Linux, the board info and command line data
#if defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_SPI_BUS 0
-#define CONFIG_ENV_SPI_CS 0
-#define CONFIG_ENV_SPI_MAX_HZ 10000000
-#define CONFIG_ENV_SPI_MODE 0
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
#define CONFIG_ENV_SECT_SIZE 0x10000
/* CPLD on IFC */
#define CONFIG_SYS_CPLD_BASE 0xffdf0000
#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
+#define CONFIG_SYS_CSPR2_EXT (0xf)
#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 10000000
+#define CONFIG_ENV_SPI_MODE 0
/*
* General PCI
#endif
#ifdef CONFIG_FMAN_ENET
-#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
-#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
-#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
-#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
+#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
+#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
+#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
#define CONFIG_MII /* MII PHY management */
-#define CONFIG_ETHPRIME "FM1@DTSEC1"
+#define CONFIG_ETHPRIME "FM1@DTSEC4"
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/
/*
* For booting Linux, the board info and command line data
#define __USB_PHY_TYPE utmi
#define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
- "bank_intlv=cs0_cs1;" \
- "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+ "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
+ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
+ "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
"netdev=eth0\0" \
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
#if defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_SPI_BUS 0
-#define CONFIG_ENV_SPI_CS 0
-#define CONFIG_ENV_SPI_MAX_HZ 10000000
-#define CONFIG_ENV_SPI_MODE 0
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
#define CONFIG_ENV_SECT_SIZE 0x10000
/* CPLD on IFC */
#define CONFIG_SYS_CPLD_BASE 0xffdf0000
#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
+#define CONFIG_SYS_CSPR2_EXT (0xf)
#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 10000000
+#define CONFIG_ENV_SPI_MODE 0
/*
* General PCI
#endif
#ifdef CONFIG_FMAN_ENET
+#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
+#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
+
#define CONFIG_MII /* MII PHY management */
-#define CONFIG_ETHPRIME "FM1@DTSEC1"
+#define CONFIG_ETHPRIME "FM1@DTSEC4"
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/
/*
* For booting Linux, the board info and command line data
#define __USB_PHY_TYPE utmi
#define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
- "bank_intlv=cs0_cs1;" \
- "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+ "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
+ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
+ "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
"netdev=eth0\0" \
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
*/
/*
- * T2080 QDS board configuration file
+ * T2080/T2081 QDS board configuration file
*/
-#ifndef __T2080QDS_H
-#define __T2080QDS_H
+#ifndef __T208xQDS_H
+#define __T208xQDS_H
-#define CONFIG_T2080QDS
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
#define CONFIG_MMC
#define CONFIG_SPI_FLASH
#define CONFIG_USB_EHCI
+#if defined(CONFIG_PPC_T2080)
+#define CONFIG_T2080QDS
#define CONFIG_FSL_SATA_V2
#define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */
+#elif defined(CONFIG_PPC_T2081)
+#define CONFIG_T2081QDS
+#endif
/* High Level Configuration Options */
#define CONFIG_PHYS_64BIT
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t2080qds/t2080_pbi.cfg
-#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t2080qds/t2080_rcw.cfg
+#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t208xqds/t208x_pbi.cfg
+#if defined(CONFIG_PPC_T2080)
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t208xqds/t2080_rcw.cfg
+#elif defined(CONFIG_PPC_T2081)
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t208xqds/t2081_rcw.cfg
+#endif
#endif
#define CONFIG_SRIO_PCIE_BOOT_MASTER
#define CONFIG_FSL_ESPI
#define CONFIG_SPI_FLASH_SST
#define CONFIG_SPI_FLASH_STMICRO
+#if defined(CONFIG_T2080QDS)
#define CONFIG_SPI_FLASH_SPANSION
+#elif defined(CONFIG_T2081QDS)
+#define CONFIG_SPI_FLASH_EON
+#endif
+
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */
+#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_NET_MULTI
#define CONFIG_E1000
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/
/*
* For booting Linux, the board info and command line data
#undef CONFIG_CMD_USB
#endif
-#endif /* __T2080QDS_H */
+#endif /* __T208xQDS_H */
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE
#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE
-#define CONFIG_SYS_GBL_DATA_SIZE 0x100
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
- CONFIG_SYS_GBL_DATA_SIZE)
+ GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * Configuration settings for the AcTux-1 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_IXP425 1
-#define CONFIG_ACTUX1 1
-
-#define CONFIG_MACH_TYPE 1479
-
-#define CONFIG_DISPLAY_CPUINFO 1
-#define CONFIG_DISPLAY_BOARDINFO 1
-
-#define CONFIG_IXP_SERIAL
-#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART2
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_BOARD_EARLY_INIT_F 1
-#define CONFIG_SYS_LDSCRIPT "board/actux1/u-boot.lds"
-
-/***************************************************************
- * U-boot generic defines start here.
- ***************************************************************/
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/* Command line configuration. */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ELF
-#ifdef CONFIG_PCI
-#define CONFIG_CMD_PCI
-#define CONFIG_PCI_PNP
-#define CONFIG_IXP_PCI
-#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_CMD_PCI_ENUM
-#endif
-
-#define CONFIG_BOOTCOMMAND "run boot_flash"
-/* enable passing of ATAGs */
-#define CONFIG_CMDLINE_TAG 1
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-#define CONFIG_REVISION_TAG 1
-
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_KGDB_BAUDRATE 230400
-#endif
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP
-/* Console I/O Buffer Size */
-#define CONFIG_SYS_CBSIZE 256
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-/* max number of command args */
-#define CONFIG_SYS_MAXARGS 16
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START 0x00400000
-#define CONFIG_SYS_MEMTEST_END 0x00800000
-
-/* timer clock - 2* OSC_IN system clock */
-#define CONFIG_IXP425_TIMER_CLK 66666666
-
-/* default load address */
-#define CONFIG_SYS_LOAD_ADDR 0x00010000
-
-/* valid baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
- 115200, 230400 }
-#define CONFIG_SERIAL_RTS_ACTIVE 1
-
-/* Expansion bus settings */
-#define CONFIG_SYS_EXP_CS0 0xbd113842
-
-/* SDRAM settings */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 0x00000000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-
-#ifdef CONFIG_RAM_32MB
-# define CONFIG_SYS_SDR_CONFIG 0x18
-# define PHYS_SDRAM_1_SIZE 0x02000000
-# define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a
-# define CONFIG_SYS_SDR_MODE_CONFIG 0x1
-# define CONFIG_SYS_DRAM_SIZE 0x02000000
-#else /* 16MB SDRAM */
-# define CONFIG_SYS_SDR_CONFIG 0x3A
-# define PHYS_SDRAM_1_SIZE 0x01000000
-# define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a
-# define CONFIG_SYS_SDR_MODE_CONFIG 0x1
-# define CONFIG_SYS_DRAM_SIZE 0x01000000
-#endif
-
-/* FLASH organization */
-#define CONFIG_SYS_TEXT_BASE 0x50000000
-#ifdef CONFIG_FLASH2X2
-# define CONFIG_SYS_MAX_FLASH_BANKS 2
-/* max number of sectors on one chip */
-# define CONFIG_SYS_MAX_FLASH_SECT 40
-# define PHYS_FLASH_1 0x50000000
-# define PHYS_FLASH_2 0x50200000
-# define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
-#endif
-#ifdef CONFIG_FLASH1X8
-# define CONFIG_SYS_MAX_FLASH_BANKS 1
-/* max number of sectors on one chip */
-# define CONFIG_SYS_MAX_FLASH_SECT 140
-# define PHYS_FLASH_1 0x50000000
-# define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 }
-#endif
-
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
-#define CONFIG_SYS_MONITOR_LEN (256 << 10)
-#define CONFIG_BOARD_SIZE_LIMIT 262144
-
-/* Use common CFI driver */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-/* no byte writes on IXP4xx */
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-/* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-/* Ethernet */
-
-/* include IXP4xx NPE support */
-#define CONFIG_IXP4XX_NPE 1
-/* NPE0 PHY address */
-#define CONFIG_PHY_ADDR 0
-/* NPE1 PHY address (HW Release E only) */
-#define CONFIG_PHY1_ADDR 1
-/* MII PHY management */
-#define CONFIG_MII 1
-/* Number of ethernet rx buffers & descriptors */
-#define CONFIG_SYS_RX_ETH_BUFFER 16
-#define CONFIG_RESET_PHY_R 1
-
-#define CONFIG_HAS_ETH1 1
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#undef CONFIG_CMD_NFS
-
-/* BOOTP options */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/* Cache Configuration */
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
-/*
- * environment organization:
- * one flash sector, embedded in uboot area (bottom bootblock flash)
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x4000)
-#define CONFIG_SYS_USE_PPCENV 1
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "npe_ucode=50040000\0" \
- "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \
- "kerneladdr=50050000\0" \
- "kernelfile=actux1/uImage\0" \
- "rootfile=actux1/rootfs\0" \
- "rootaddr=50170000\0" \
- "loadaddr=10000\0" \
- "updateboot_ser=mw.b 10000 ff 40000;" \
- " loady ${loadaddr};" \
- " run eraseboot writeboot\0" \
- "updateboot_net=mw.b 10000 ff 40000;" \
- " tftp ${loadaddr} actux1/u-boot.bin;" \
- " run eraseboot writeboot\0" \
- "eraseboot=protect off 50000000 50003fff;" \
- " protect off 50006000 5003ffff;" \
- " erase 50000000 50003fff;" \
- " erase 50006000 5003ffff\0" \
- "writeboot=cp.b 10000 50000000 4000;" \
- " cp.b 16000 50006000 3a000\0" \
- "updateucode=loady;" \
- " era ${npe_ucode} +${filesize};" \
- " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \
- "updateroot=tftp ${loadaddr} ${rootfile};" \
- " era ${rootaddr} +${filesize};" \
- " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \
- "updatekern=tftp ${loadaddr} ${kernelfile};" \
- " era ${kerneladdr} +${filesize};" \
- " cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \
- "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \
- " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
- "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \
- " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0" \
- "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \
- "boot_flash=run flashargs addtty addeth;" \
- " bootm ${kerneladdr}\0" \
- "boot_net=run netargs addtty addeth;" \
- " tftpboot ${loadaddr} ${kernelfile};" \
- " bootm\0"
-
-/* additions for new relocation code, must be added to all boards */
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * Configuration settings for the AcTux-2 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_IXP425 1
-#define CONFIG_ACTUX2 1
-
-#define CONFIG_MACH_TYPE 1480
-
-#define CONFIG_DISPLAY_CPUINFO 1
-#define CONFIG_DISPLAY_BOARDINFO 1
-
-#define CONFIG_IXP_SERIAL
-#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART2
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_BOOTDELAY 5
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_BOARD_EARLY_INIT_F 1
-#define CONFIG_SYS_LDSCRIPT "board/actux2/u-boot.lds"
-
-/***************************************************************
- * U-boot generic defines start here.
- ***************************************************************/
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/* Command line configuration. */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ELF
-#undef CONFIG_CMD_PCI
-#undef CONFIG_PCI
-
-#define CONFIG_BOOTCOMMAND "run boot_flash"
-/* enable passing of ATAGs */
-#define CONFIG_CMDLINE_TAG 1
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-#define CONFIG_REVISION_TAG 1
-
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_KGDB_BAUDRATE 230400
-#endif
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP
-/* Console I/O Buffer Size */
-#define CONFIG_SYS_CBSIZE 256
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-/* max number of command args */
-#define CONFIG_SYS_MAXARGS 16
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START 0x00400000
-#define CONFIG_SYS_MEMTEST_END 0x00800000
-
-/* timer clock - 2* OSC_IN system clock */
-#define CONFIG_IXP425_TIMER_CLK 66666666
-
-/* default load address */
-#define CONFIG_SYS_LOAD_ADDR 0x00010000
-
-/* valid baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
- 115200, 230400 }
-#define CONFIG_SERIAL_RTS_ACTIVE 1
-
-/* Expansion bus settings */
-#define CONFIG_SYS_EXP_CS0 0xbd113042
-
-/* SDRAM settings */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 0x00000000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-
-/* 16MB SDRAM */
-#define CONFIG_SYS_SDR_CONFIG 0x3A
-#define PHYS_SDRAM_1_SIZE 0x01000000
-#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a
-#define CONFIG_SYS_SDR_MODE_CONFIG 0x1
-#define CONFIG_SYS_DRAM_SIZE 0x01000000
-
-/* FLASH organization */
-#define CONFIG_SYS_TEXT_BASE 0x50000000
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-/* max number of sectors on one chip */
-#define CONFIG_SYS_MAX_FLASH_SECT 140
-#define PHYS_FLASH_1 0x50000000
-#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 }
-
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
-#define CONFIG_SYS_MONITOR_LEN (256 << 10)
-#define CONFIG_BOARD_SIZE_LIMIT 262144
-
-/* Use common CFI driver */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-/* no byte writes on IXP4xx */
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-
-/* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-/* Ethernet */
-
-/* include IXP4xx NPE support */
-#define CONFIG_IXP4XX_NPE 1
-/* NPE0 PHY address */
-#define CONFIG_PHY_ADDR 0x00
-/* MII PHY management */
-#define CONFIG_MII 1
-/* fixed-speed switch without standard PHY registers on MII */
-#define CONFIG_MII_NPE0_FIXEDLINK 1
-#define CONFIG_MII_NPE0_SPEED 100
-#define CONFIG_MII_NPE0_FULLDUPLEX 1
-
-/* Number of ethernet rx buffers & descriptors */
-#define CONFIG_SYS_RX_ETH_BUFFER 16
-#define CONFIG_RESET_PHY_R 1
-/* ethernet switch connected to MII port */
-#define CONFIG_MII_ETHSWITCH 1
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#undef CONFIG_CMD_NFS
-
-/* BOOTP options */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/* Cache Configuration */
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
-/*
- * environment organization:
- * one flash sector, embedded in uboot area (bottom bootblock flash)
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x4000)
-#define CONFIG_SYS_USE_PPCENV 1
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "npe_ucode=50040000\0" \
- "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \
- "kerneladdr=50050000\0" \
- "kernelfile=actux2/uImage\0" \
- "rootfile=actux2/rootfs\0" \
- "rootaddr=50170000\0" \
- "loadaddr=10000\0" \
- "updateboot_ser=mw.b 10000 ff 40000;" \
- " loady ${loadaddr};" \
- " run eraseboot writeboot\0" \
- "updateboot_net=mw.b 10000 ff 40000;" \
- " tftp ${loadaddr} actux2/u-boot.bin;" \
- " run eraseboot writeboot\0" \
- "eraseboot=protect off 50000000 50003fff;" \
- " protect off 50006000 5003ffff;" \
- " erase 50000000 50003fff;" \
- " erase 50006000 5003ffff\0" \
- "writeboot=cp.b 10000 50000000 4000;" \
- " cp.b 16000 50006000 3a000\0" \
- "updateucode=loady;" \
- " era ${npe_ucode} +${filesize};" \
- " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \
- "updateroot=tftp ${loadaddr} ${rootfile};" \
- " era ${rootaddr} +${filesize};" \
- " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \
- "updatekern=tftp ${loadaddr} ${kernelfile};" \
- " era ${kerneladdr} +${filesize};" \
- " cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \
- "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \
- " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
- "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \
- " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
- "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \
- "boot_flash=run flashargs addtty addeth;" \
- " bootm ${kerneladdr}\0" \
- "boot_net=run netargs addtty addeth;" \
- " tftpboot ${loadaddr} ${kernelfile};" \
- " bootm\0"
-
-/* additions for new relocation code, must be added to all boards */
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * Configuration settings for the AcTux-3 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_IXP425 1
-#define CONFIG_ACTUX3 1
-
-#define CONFIG_MACH_TYPE 1481
-
-#define CONFIG_DISPLAY_CPUINFO 1
-#define CONFIG_DISPLAY_BOARDINFO 1
-
-#define CONFIG_IXP_SERIAL
-#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART2
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_BOARD_EARLY_INIT_F 1
-#define CONFIG_SYS_LDSCRIPT "board/actux3/u-boot.lds"
-
-/***************************************************************
- * U-boot generic defines start here.
- ***************************************************************/
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/* Command line configuration. */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ELF
-
-#define CONFIG_BOOTCOMMAND "run boot_flash"
-/* enable passing of ATAGs */
-#define CONFIG_CMDLINE_TAG 1
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-#define CONFIG_REVISION_TAG 1
-
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_KGDB_BAUDRATE 230400
-#endif
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP
-/* Console I/O Buffer Size */
-#define CONFIG_SYS_CBSIZE 256
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-/* max number of command args */
-#define CONFIG_SYS_MAXARGS 16
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START 0x00400000
-#define CONFIG_SYS_MEMTEST_END 0x00800000
-
-/* timer clock - 2* OSC_IN system clock */
-#define CONFIG_IXP425_TIMER_CLK 66666666
-
-/* default load address */
-#define CONFIG_SYS_LOAD_ADDR 0x00010000
-
-/* valid baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
- 115200, 230400 }
-#define CONFIG_SERIAL_RTS_ACTIVE 1
-
-/* Expansion bus settings */
-#define CONFIG_SYS_EXP_CS0 0xbd113442
-
-/* SDRAM settings */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 0x00000000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-
-/* 16MB SDRAM */
-#define CONFIG_SYS_SDR_CONFIG 0x3A
-#define PHYS_SDRAM_1_SIZE 0x01000000
-#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a
-#define CONFIG_SYS_SDR_MODE_CONFIG 0x1
-#define CONFIG_SYS_DRAM_SIZE 0x01000000
-
-/* FLASH organization */
-#define CONFIG_SYS_TEXT_BASE 0x50000000
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-/* max number of sectors on one chip */
-#define CONFIG_SYS_MAX_FLASH_SECT 140
-#define PHYS_FLASH_1 0x50000000
-#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 }
-
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
-#define CONFIG_SYS_MONITOR_LEN (256 << 10)
-#define CONFIG_BOARD_SIZE_LIMIT 262144
-
-/* Use common CFI driver */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-/* no byte writes on IXP4xx */
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-
-/* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-/* Ethernet */
-
-/* include IXP4xx NPE support */
-#define CONFIG_IXP4XX_NPE 1
-
-/* NPE0 PHY address */
-#define CONFIG_PHY_ADDR 0x10
-/* MII PHY management */
-#define CONFIG_MII 1
-/* fixed-speed switch without standard PHY registers on MII */
-#define CONFIG_MII_NPE0_FIXEDLINK 1
-#define CONFIG_MII_NPE0_SPEED 100
-#define CONFIG_MII_NPE0_FULLDUPLEX 1
-
-/* Number of ethernet rx buffers & descriptors */
-#define CONFIG_SYS_RX_ETH_BUFFER 16
-#define CONFIG_RESET_PHY_R 1
-/* ethernet switch connected to MII port */
-#define CONFIG_MII_ETHSWITCH 1
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#undef CONFIG_CMD_NFS
-
-/* BOOTP options */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/* Cache Configuration */
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
-/*
- * environment organization:
- * one flash sector, embedded in uboot area (bottom bootblock flash)
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x4000)
-#define CONFIG_SYS_USE_PPCENV 1
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "npe_ucode=50040000\0" \
- "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \
- "kerneladdr=50050000\0" \
- "kernelfile=actux3/uImage\0" \
- "rootfile=actux3/rootfs\0" \
- "rootaddr=50170000\0" \
- "loadaddr=10000\0" \
- "updateboot_ser=mw.b 10000 ff 40000;" \
- " loady ${loadaddr};" \
- " run eraseboot writeboot\0" \
- "updateboot_net=mw.b 10000 ff 40000;" \
- " tftp ${loadaddr} actux3/u-boot.bin;" \
- " run eraseboot writeboot\0" \
- "eraseboot=protect off 50000000 50003fff;" \
- " protect off 50006000 5003ffff;" \
- " erase 50000000 50003fff;" \
- " erase 50006000 5003ffff\0" \
- "writeboot=cp.b 10000 50000000 4000;" \
- " cp.b 16000 50006000 3a000\0" \
- "updateucode=loady;" \
- " era ${npe_ucode} +${filesize};" \
- " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \
- "updateroot=tftp ${loadaddr} ${rootfile};" \
- " era ${rootaddr} +${filesize};" \
- " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \
- "updatekern=tftp ${loadaddr} ${kernelfile};" \
- " era ${kerneladdr} +${filesize};" \
- " cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \
- "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \
- " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
- "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \
- " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0" \
- "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \
- "boot_flash=run flashargs addtty addeth;" \
- " bootm ${kerneladdr}\0" \
- "boot_net=run netargs addtty addeth;" \
- " tftpboot ${loadaddr} ${kernelfile};" \
- " bootm\0"
-
-/* additions for new relocation code, must be added to all boards */
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * Configuration settings for the AcTux-4 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_IXP425 1
-#define CONFIG_ACTUX4 1
-
-#define CONFIG_MACH_TYPE 1532
-
-#define CONFIG_DISPLAY_CPUINFO 1
-#define CONFIG_DISPLAY_BOARDINFO 1
-
-#define CONFIG_IXP_SERIAL
-#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART1
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_BOARD_EARLY_INIT_F 1
-
-/***************************************************************
- * U-boot generic defines start here.
- ***************************************************************/
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/* Command line configuration */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ELF
-
-#define CONFIG_PCI
-#ifdef CONFIG_PCI
-#define CONFIG_CMD_PCI
-#define CONFIG_PCI_PNP
-#define CONFIG_IXP_PCI
-#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_CMD_PCI_ENUM
-#endif
-
-#define CONFIG_BOOTCOMMAND "run boot_flash"
-/* enable passing of ATAGs */
-#define CONFIG_CMDLINE_TAG 1
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_KGDB_BAUDRATE 230400
-#endif
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP
-/* Console I/O Buffer Size */
-#define CONFIG_SYS_CBSIZE 256
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-/* max number of command args */
-#define CONFIG_SYS_MAXARGS 16
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START 0x00400000
-#define CONFIG_SYS_MEMTEST_END 0x00800000
-
-/* timer clock - 2* OSC_IN system clock */
-#define CONFIG_IXP425_TIMER_CLK 66000000
-
-/* default load address */
-#define CONFIG_SYS_LOAD_ADDR 0x00010000
-
-/* valid baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
- 115200, 230400 }
-#define CONFIG_SERIAL_RTS_ACTIVE 1
-
-/* Expansion bus settings */
-#define CONFIG_SYS_EXP_CS0 0xbd113003
-
-/* SDRAM settings */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 0x00000000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-
-/* 32MB SDRAM */
-#define CONFIG_SYS_SDR_CONFIG 0x18
-#define PHYS_SDRAM_1_SIZE 0x02000000
-#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a
-#define CONFIG_SYS_SDR_MODE_CONFIG 0x1
-#define CONFIG_SYS_DRAM_SIZE 0x02000000
-
-/* FLASH organization */
-#define CONFIG_SYS_TEXT_BASE 0x50000000
-#define CONFIG_SYS_MAX_FLASH_BANKS 2
-/* max # of sectors per chip */
-#define CONFIG_SYS_MAX_FLASH_SECT 70
-#define PHYS_FLASH_1 0x50000000
-#define PHYS_FLASH_2 0x51000000
-#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
-
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
-#define CONFIG_SYS_MONITOR_LEN (252 << 10)
-#define CONFIG_BOARD_SIZE_LIMIT 258048
-
-/* Use common CFI driver */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-/* board provides its own flash_init code */
-#define CONFIG_FLASH_CFI_LEGACY 1
-/* no byte writes on IXP4xx */
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-/* SST 39VF020 etc. support */
-#define CONFIG_SYS_FLASH_LEGACY_256Kx8 1
-
-/* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-/* Ethernet */
-
-/* include IXP4xx NPE support */
-#define CONFIG_IXP4XX_NPE 1
-
-/* NPE0 PHY address */
-#define CONFIG_PHY_ADDR 0x1C
-/* MII PHY management */
-#define CONFIG_MII 1
-
-/* Number of ethernet rx buffers & descriptors */
-#define CONFIG_SYS_RX_ETH_BUFFER 16
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#undef CONFIG_CMD_NFS
-
-/* BOOTP options */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/* Cache Configuration */
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
-/* environment organization: one complete 4k flash sector */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SIZE 0x1000
-#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x3f000)
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "npe_ucode=51000000\0" \
- "mtd=IXP4XX-Flash.0:252k(uboot),4k(uboot_env);" \
- "IXP4XX-Flash.1:128k(ucode),1280k(linux),-(root)\0" \
- "kerneladdr=51020000\0" \
- "kernelfile=actux4/uImage\0" \
- "rootfile=actux4/rootfs\0" \
- "rootaddr=51160000\0" \
- "loadaddr=10000\0" \
- "updateboot_ser=mw.b 10000 ff 40000;" \
- " loady ${loadaddr};" \
- " run eraseboot writeboot\0" \
- "updateboot_net=mw.b 10000 ff 40000;" \
- " tftp ${loadaddr} actux4/u-boot.bin;" \
- " run eraseboot writeboot\0" \
- "eraseboot=protect off 50000000 5003efff;" \
- " erase 50000000 +${filesize}\0" \
- "writeboot=cp.b 10000 50000000 ${filesize}\0" \
- "updateucode=loady;" \
- " era ${npe_ucode} +${filesize};" \
- " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \
- "updateroot=tftp ${loadaddr} ${rootfile};" \
- " era ${rootaddr} +${filesize};" \
- " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \
- "updatekern=tftp ${loadaddr} ${kernelfile};" \
- " era ${kerneladdr} +${filesize};" \
- " cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \
- "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock4" \
- " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
- "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock4" \
- " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
- "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \
- "boot_flash=run flashargs addtty addeth;" \
- " bootm ${kerneladdr}\0" \
- "boot_net=run netargs addtty addeth;" \
- " tftpboot ${loadaddr} ${kernelfile};" \
- " bootm\0"
-
-/* additions for new relocation code, must be added to all boards */
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
-
-#endif /* __CONFIG_H */
/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
#define CONFIG_SYS_MALLOC_LEN (512 << 10)
-/*
- * size in bytes reserved for initial data
- */
-#define CONFIG_SYS_GBL_DATA_SIZE 128
-
/*
* AHB Controller configuration
*/
/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
#define CONFIG_SYS_MALLOC_LEN (512 << 10)
-/*
- * size in bytes reserved for initial data
- */
-#define CONFIG_SYS_GBL_DATA_SIZE 128
-
/*
* AHB Controller configuration
*/
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
-/*
- * size in bytes reserved for initial data
-*/
-#define CONFIG_SYS_GBL_DATA_SIZE 128
-
/*
* AHB Controller configuration
*/
#define MACH_TYPE_TIAM335EVM 3589 /* Until the next sync */
#define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM
+#define CONFIG_BOARD_LATE_INIT
/* Clock Defines */
#define V_OSCK 24000000 /* Clock output from T2 */
/* Always 128 KiB env size */
#define CONFIG_ENV_SIZE (128 << 10)
+/* Enhance our eMMC support / experience. */
+#define CONFIG_CMD_GPT
+#define CONFIG_EFI_PARTITION
+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_CMD_PART
+
#ifdef CONFIG_NAND
#define NANDARGS \
"mtdids=" MTDIDS_DEFAULT "\0" \
"bootfile=zImage\0" \
"fdtfile=undefined\0" \
"console=ttyO0,115200n8\0" \
+ "partitions=" \
+ "uuid_disk=${uuid_gpt_disk};" \
+ "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \
"optargs=\0" \
"mmcdev=0\0" \
"mmcroot=/dev/mmcblk0p2 ro\0" \
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)
/* disable host part of MUSB in SPL */
#undef CONFIG_MUSB_HOST
+/* disable EFI partitions and partition UUID support */
+#undef CONFIG_PARTITION_UUIDS
+#undef CONFIG_EFI_PARTITION
/*
* Disable CPSW SPL support so we fit within the 101KiB limit.
*/
/* Network. */
#define CONFIG_PHY_GIGE
#define CONFIG_PHYLIB
-#define CONFIG_PHY_ADDR 0
#define CONFIG_PHY_SMSC
/* NAND support */
#define CONFIG_NET_RETRY_COUNT 10
#define CONFIG_NET_MULTI
#define CONFIG_PHYLIB
-#define CONFIG_PHY_ADDR 0
#define CONFIG_PHY_SMSC
/* NAND support */
#define CONFIG_OMAP_USB_PHY
#define CONFIG_AM437X_USB2PHY2_HOST
+/* SPI */
+#undef CONFIG_OMAP3_SPI
+#define CONFIG_TI_QSPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_MACRONIX
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_TI_SPI_MMAP
+#define CONFIG_QSPI_SEL_GPIO 48
+#define CONFIG_SF_DEFAULT_SPEED 48000000
+#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3
+
+/* SPI SPL */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS 0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
+
+/* Enhance our eMMC support / experience. */
+#define CONFIG_CMD_GPT
+#define CONFIG_EFI_PARTITION
+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_CMD_PART
+
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x80200000\0" \
"bootdir=/boot\0" \
"bootfile=zImage\0" \
"console=ttyO0,115200n8\0" \
+ "partitions=" \
+ "uuid_disk=${uuid_gpt_disk};" \
+ "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \
"optargs=\0" \
"mmcdev=0\0" \
"mmcroot=/dev/mmcblk0p2 rw\0" \
"run usbboot;"
#endif
+
+/* CPSW Ethernet */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_DRIVER_TI_CPSW
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_NET_RETRY_COUNT 10
+#define CONFIG_NET_MULTI
+#define CONFIG_PHY_GIGE
+#define CONFIG_PHYLIB
+
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NET_VCI_STRING "AM43xx U-Boot SPL"
+
+#define CONFIG_SPL_ETH_SUPPORT
+#define CONFIG_SPL_NET_SUPPORT
+#define CONFIG_SYS_RX_ETH_BUFFER 64
+
#endif /* __CONFIG_AM43XX_EVM_H */
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
/* Size of DRAM reserved for malloc() use */
#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
-/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE (256)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* ENV setting */
#define CONFIG_SYS_RTC_BUS_NUM 0
#endif /* CONFIG_CMD_DATE */
-/*
- * Clocks
- */
-#define CONFIG_SYS_HZ 1000 /* Ticks per second */
-
/*
* PLL
*
--- /dev/null
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CONFIG_ARCANGEL4_H_
+#define _CONFIG_ARCANGEL4_H_
+
+/*
+ * CPU configuration
+ */
+#define CONFIG_SYS_BIG_ENDIAN
+#define CONFIG_ARC700
+#define CONFIG_ARC_MMU_VER 3
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_SYS_CLK_FREQ 70000000
+#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
+
+/*
+ * Board configuration
+ */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */
+
+#define CONFIG_ARCH_EARLY_INIT_R
+
+/*
+ * Memory configuration
+ */
+#define CONFIG_SYS_TEXT_BASE 0x81000000
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 Mb */
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN 0x200000 /* 2 MB */
+#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */
+#define CONFIG_SYS_LOAD_ADDR 0x82000000
+
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * UART configuration
+ *
+ */
+#define CONFIG_ARC_SERIAL
+#define CONFIG_ARC_UART_BASE 0xC0FC1000
+#define CONFIG_BAUDRATE 115200
+
+/*
+ * Command line configuration
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_MAXARGS 16
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE 0x00200 /* 512 bytes */
+#define CONFIG_ENV_OFFSET 0
+
+/*
+ * Environment configuration
+ */
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_BOOTARGS "console=ttyARC0,115200n8"
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
+
+/*
+ * Console configuration
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "arcangel4# "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#endif /* _CONFIG_ARCANGEL4_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CONFIG_ARCANGEL4_H_
+#define _CONFIG_ARCANGEL4_H_
+
+/*
+ * CPU configuration
+ */
+#define CONFIG_ARC700
+#define CONFIG_ARC_MMU_VER 3
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_SYS_CLK_FREQ 70000000
+#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
+
+/*
+ * Board configuration
+ */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */
+
+#define CONFIG_ARCH_EARLY_INIT_R
+
+/*
+ * Memory configuration
+ */
+#define CONFIG_SYS_TEXT_BASE 0x81000000
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 Mb */
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN 0x200000 /* 2 MB */
+#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */
+#define CONFIG_SYS_LOAD_ADDR 0x82000000
+
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * UART configuration
+ *
+ */
+#define CONFIG_ARC_SERIAL
+#define CONFIG_ARC_UART_BASE 0xC0FC1000
+#define CONFIG_BAUDRATE 115200
+
+/*
+ * Command line configuration
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_MAXARGS 16
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE 0x00200 /* 512 bytes */
+#define CONFIG_ENV_OFFSET 0
+
+/*
+ * Environment configuration
+ */
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_BOOTARGS "console=ttyARC0,115200n8"
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
+
+/*
+ * Console configuration
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "arcangel4# "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#endif /* _CONFIG_ARCANGEL4_H_ */
#define CONFIG_SYS_MONITOR_BASE 0x00000000
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
-#define CONFIG_SYS_GBL_DATA_SIZE (256)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
#define CONFIG_SYS_TEXT_BASE 0xE80C0000
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
-/* Enable fdt support for Exynos5250 */
-#define CONFIG_ARCH_DEVICE_TREE exynos5250
#define CONFIG_OF_CONTROL
#define CONFIG_OF_SEPARATE
--- /dev/null
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CONFIG_AXS101_H_
+#define _CONFIG_AXS101_H_
+
+/*
+ * CPU configuration
+ */
+#define CONFIG_ARC700
+#define CONFIG_ARC_MMU_VER 3
+#define CONFIG_SYS_CACHELINE_SIZE 32
+#define CONFIG_SYS_CLK_FREQ 750000000
+#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
+
+/* dwgmac doesn't work with D$ enabled now */
+#define CONFIG_SYS_DCACHE_OFF
+
+/*
+ * Board configuration
+ */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */
+
+#define CONFIG_ARCH_EARLY_INIT_R
+
+#define ARC_FPGA_PERIPHERAL_BASE 0xE0000000
+#define ARC_APB_PERIPHERAL_BASE 0xF0000000
+#define ARC_DWMMC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x15000)
+#define ARC_DWGMAC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x18000)
+
+/*
+ * Memory configuration
+ */
+#define CONFIG_SYS_TEXT_BASE 0x81000000
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 Mb */
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN 0x200000 /* 2 MB */
+#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */
+#define CONFIG_SYS_LOAD_ADDR 0x82000000
+
+/*
+ * NAND Flash configuration
+ */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_NAND_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x16000)
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+
+/*
+ * UART configuration
+ *
+ * CONFIG_CONS_INDEX = 1 - Debug UART
+ * CONFIG_CONS_INDEX = 4 - FPGA UART connected to FTDI/USB
+ */
+#define CONFIG_CONS_INDEX 4
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#if (CONFIG_CONS_INDEX == 1)
+ /* Debug UART */
+# define CONFIG_SYS_NS16550_CLK 33333000
+#else
+ /* FPGA UARTs use different clock */
+# define CONFIG_SYS_NS16550_CLK 33333333
+#endif
+#define CONFIG_SYS_NS16550_COM1 (ARC_APB_PERIPHERAL_BASE + 0x5000)
+#define CONFIG_SYS_NS16550_COM2 (ARC_FPGA_PERIPHERAL_BASE + 0x20000)
+#define CONFIG_SYS_NS16550_COM3 (ARC_FPGA_PERIPHERAL_BASE + 0x21000)
+#define CONFIG_SYS_NS16550_COM4 (ARC_FPGA_PERIPHERAL_BASE + 0x22000)
+#define CONFIG_SYS_NS16550_MEM32
+
+#define CONFIG_BAUDRATE 115200
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_DW_I2C
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_ENV_EEPROM_BUS 2
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0
+#define CONFIG_SYS_I2C_BASE 0xE001D000
+#define CONFIG_SYS_I2C_BASE1 0xE001E000
+#define CONFIG_SYS_I2C_BASE2 0xE001F000
+#define CONFIG_SYS_I2C_BUS_MAX 3
+#define IC_CLK 50
+
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR (0xA8 >> 1)
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 32
+
+/*
+ * SD/MMC configuration
+ */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DWMMC
+#define CONFIG_DOS_PARTITION
+
+/*
+ * Ethernet PHY configuration
+ */
+#define CONFIG_PHYLIB
+#define CONFIG_MII
+#define CONFIG_PHY_GIGE
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_DESIGNWARE_ETH
+#define CONFIG_DW_AUTONEG
+#define CONFIG_DW_SEARCH_PHY
+#define CONFIG_NET_MULTI
+
+/*
+ * Command line configuration
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_RARP
+
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_MAXARGS 16
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_EEPROM
+#define CONFIG_ENV_SIZE 0x00200 /* 512 bytes */
+#define CONFIG_ENV_OFFSET 0
+
+/*
+ * Environment configuration
+ */
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_BOOTARGS "console=ttyS3,115200n8"
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
+
+/*
+ * Console configuration
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "AXS# "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/*
+ * Misc utility configuration
+ */
+#define CONFIG_BOUNCE_BUFFER
+
+#endif /* _CONFIG_AXS101_H_ */
* Clock Configuration
*/
#undef CONFIG_SYS_CLKS_IN_HZ
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */
/*
--- /dev/null
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __BCM28155_AP_H
+#define __BCM28155_AP_H
+
+#include <asm/sizes.h>
+#include <asm/arch/sysmap.h>
+
+/* Architecture, CPU, chip, mach, etc */
+#define CONFIG_ARMV7
+#define CONFIG_KONA
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * Memory configuration
+ */
+#define CONFIG_SYS_TEXT_BASE 0xae000000
+
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_SDRAM_SIZE 0x80000000
+#define CONFIG_NR_DRAM_BANKS 1
+
+#define CONFIG_SYS_MALLOC_LEN SZ_4M /* see armv7/start.S. */
+#define CONFIG_STACKSIZE SZ_256K
+
+/* GPIO Driver */
+#define CONFIG_KONA_GPIO
+
+/* MMC/SD Driver */
+#define CONFIG_SDHCI
+#define CONFIG_MMC_SDMA
+#define CONFIG_KONA_SDHCI
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+
+#define CONFIG_SYS_SDIO_BASE0 SDIO1_BASE_ADDR
+#define CONFIG_SYS_SDIO_BASE1 SDIO2_BASE_ADDR
+#define CONFIG_SYS_SDIO_BASE2 SDIO3_BASE_ADDR
+#define CONFIG_SYS_SDIO_BASE3 SDIO4_BASE_ADDR
+#define CONFIG_SYS_SDIO0_MAX_CLK 48000000
+#define CONFIG_SYS_SDIO1_MAX_CLK 48000000
+#define CONFIG_SYS_SDIO2_MAX_CLK 48000000
+#define CONFIG_SYS_SDIO3_MAX_CLK 48000000
+#define CONFIG_SYS_SDIO0 "sdio1"
+#define CONFIG_SYS_SDIO1 "sdio2"
+#define CONFIG_SYS_SDIO2 "sdio3"
+#define CONFIG_SYS_SDIO3 "sdio4"
+
+/* I2C Driver */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_KONA
+#define CONFIG_SYS_SPD_BUS_NUM 3 /* Start with PMU bus */
+#define CONFIG_SYS_MAX_I2C_BUS 4
+#define CONFIG_SYS_I2C_BASE0 BSC1_BASE_ADDR
+#define CONFIG_SYS_I2C_BASE1 BSC2_BASE_ADDR
+#define CONFIG_SYS_I2C_BASE2 BSC3_BASE_ADDR
+#define CONFIG_SYS_I2C_BASE3 PMU_BSC_BASE_ADDR
+
+/* Timer Driver */
+#define CONFIG_SYS_TIMER_RATE 32000
+#define CONFIG_SYS_TIMER_COUNTER (TIMER_BASE_ADDR + 4) /* STCLO offset */
+
+/* Init functions */
+#define CONFIG_MISC_INIT_R /* board's misc_init_r function */
+
+/* Some commands use this as the default load address */
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
+
+/* No mtest functions as recommended */
+#undef CONFIG_CMD_MEMORY
+
+/*
+ * This is the initial SP which is used only briefly for relocating the u-boot
+ * image to the top of SDRAM. After relocation u-boot moves the stack to the
+ * proper place.
+ */
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
+
+/* Serial Info */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+/* Post pad 3 bytes after each reg addr */
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK 13000000
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550_COM1 0x3e000000
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_ENV_SIZE 0x10000
+#define CONFIG_ENV_IS_NOWHERE
+
+#define CONFIG_SYS_NO_FLASH /* Not using NAND/NOR unmanaged flash */
+
+/* console configuration */
+#define CONFIG_SYS_CBSIZE 1024 /* Console buffer size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16) /* Printbuffer size */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/*
+ * One partition type must be defined for part.c
+ * This is necessary for the fatls command to work on an SD card
+ * for example.
+ */
+#define CONFIG_DOS_PARTITION
+
+/* version string, parser, etc */
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/* Initial upstream - boot to cmd prompt only */
+#define CONFIG_BOOTCOMMAND ""
+
+/* Commands */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_FAT_WRITE
+
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+#endif /* __BCM28155_AP_H */
#define CONFIG_NET_MULTI
#define CONFIG_HOSTNAME "bf609-ezkit"
#define CONFIG_DESIGNWARE_ETH
+#define CONFIG_PHY_ADDR 1
#define CONFIG_DW_PORTS 1
-#define CONFIG_DW_AUTONEG
#define CONFIG_DW_ALTDESCRIPTOR
#define CONFIG_CMD_NET
#define CONFIG_CMD_MII
#define CONFIG_MII
+#define CONFIG_PHYLIB
/* i2c Settings */
#define CONFIG_BFIN_TWI_I2C
--- /dev/null
+/*
+ * bur_am335x_common.h
+ *
+ * common parts used by B&R AM335x based boards
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at> -
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __BUR_AM335X_COMMON_H__
+#define __BUR_AM335X_COMMON_H__
+/* ------------------------------------------------------------------------- */
+#define CONFIG_AM33XX
+#define CONFIG_OMAP
+#define CONFIG_OMAP_COMMON
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
+
+/* Timer information */
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
+
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_POWER_TPS65217
+
+#define CONFIG_SYS_NO_FLASH /* have no NOR-flash */
+
+#include <asm/arch/omap.h>
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK 48000000
+#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
+#define CONFIG_BAUDRATE 115200
+
+/* Network defines */
+#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_NET_RETRY_COUNT 4
+#define CONFIG_CMD_PING
+#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */
+#define CONFIG_MII /* Required in net/eth.c */
+#define CONFIG_SPL_ETH_SUPPORT
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_NATSEMI
+#define CONFIG_SPL_NET_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT /* used for a fetching MAC-Address */
+#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"
+
+/*
+ * SPL related defines. The Public RAM memory map the ROM defines the
+ * area between 0x402F0400 and 0x4030B800 as a download area and
+ * 0x4030B800 to 0x4030CE00 as a public stack area. The ROM also
+ * supports X-MODEM loading via UART, and we leverage this and then use
+ * Y-MODEM to load u-boot.img, when booted over UART.
+ */
+#define CONFIG_SPL_TEXT_BASE 0x402F0400
+#define CONFIG_SPL_MAX_SIZE (0x4030B800 - CONFIG_SPL_TEXT_BASE)
+
+/*
+ * Since SPL did pll and ddr initialization for us,
+ * we don't need to do it twice.
+ */
+#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif /* !CONFIG_SPL_BUILD, ... */
+/*
+ * Our DDR memory always starts at 0x80000000 and U-Boot shall have
+ * relocated itself to higher in memory by the time this value is used.
+ */
+#define CONFIG_SYS_LOAD_ADDR 0x80000000
+/*
+ * ----------------------------------------------------------------------------
+ * DDR information. We say (for simplicity) that we have 1 bank,
+ * always, even when we have more. We always start at 0x80000000,
+ * and we place the initial stack pointer in our SRAM.
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
+ GENERATED_GBL_DATA_SIZE)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_OMAP24XX
+
+/* GPIO */
+#define CONFIG_OMAP_GPIO
+#define CONFIG_CMD_GPIO
+/*
+ * ----------------------------------------------------------------------------
+ * The following are general good-enough settings for U-Boot. We set a
+ * large malloc pool as we generally have a lot of DDR, and we opt for
+ * function over binary size in the main portion of U-Boot as this is
+ * generally easily constrained later if needed. We enable the config
+ * options that give us information in the environment about what board
+ * we are on so we do not need to rely on the command prompt. We set a
+ * console baudrate of 115200 and use the default baud rate table.
+ */
+#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT "U-Boot (BuR V2.0)# "
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_ENV_OVERWRITE /* Overwrite ethaddr / serial# */
+
+/* As stated above, the following choices are optional. */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_VERSION_VARIABLE
+
+/* We set the max number of command args high to avoid HUSH bugs. */
+#define CONFIG_SYS_MAXARGS 64
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 512
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE +\
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+/*
+ * For commands to use, we take the default list and add a few other
+ * useful commands. Note that we must have set CONFIG_SYS_NO_FLASH
+ * prior to this include, in order to skip a few commands. When we do
+ * have flash, if we expect these commands they must be enabled in that
+ * config. If desired, a specific list of desired commands can be used
+ * instead.
+ */
+#include <config_cmd_default.h>
+/* undefine commands, which we do not need */
+#undef CONFIG_CMD_EDITENV
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_ITEST
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+#undef CONFIG_CMD_CRC32
+/* define command we need always */
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_SOURCE
+
+/*
+ * Our platforms make use of SPL to initalize the hardware (primarily
+ * memory) enough for full U-Boot to be loaded. We also support Falcon
+ * Mode so that the Linux kernel can be booted directly from SPL
+ * instead, if desired. We make use of the general SPL framework found
+ * under common/spl/. Given our generally common memory map, we set a
+ * number of related defaults and sizes here.
+ */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+/*
+ * Place the image at the start of the ROM defined image space.
+ * We limit our size to the ROM-defined downloaded image area, and use the
+ * rest of the space for stack. We load U-Boot itself into memory at
+ * 0x80800000 for legacy reasons (to not conflict with older SPLs). We
+ * have our BSS be placed 1MiB after this, to allow for the default
+ * Linux kernel address of 0x80008000 to work, in the Falcon Mode case.
+ * We have the SPL malloc pool at the end of the BSS area.
+ *
+ * ----------------------------------------------------------------------------
+ */
+#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
+#undef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0x80800000
+#define CONFIG_SPL_BSS_START_ADDR 0x80A00000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
+#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
+ CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
+
+/* General parts of the framework, required. */
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_YMODEM_SUPPORT
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
+
+#endif /* ! __BUR_AM335X_COMMON_H__ */
#define V_PROMPT "Tegra30 (Cardhu) # "
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Cardhu"
+#define BOARD_EXTRA_ENV_SETTINGS \
+ "board_name=cardhu-a04\0" \
+ "fdtfile=tegra30-cardhu-a04.dtb\0"
+
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA_ENABLE_UARTA
/* Network. */
#define CONFIG_PHY_GIGE
#define CONFIG_PHYLIB
-#define CONFIG_PHY_ADDR 0
#define CONFIG_PHY_ATHEROS
/* NAND support */
#define CONFIG_MISC_INIT_R
#define CONFIG_OF_LIBFDT 1
-/*
- * The early kernel mapping on ARM currently only maps from the base of DRAM
- * to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000.
- * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
- * so that leaves DRAM base to DRAM base + 0x4000 available.
- */
-#define CONFIG_SYS_BOOTMAPSZ 0x4000
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
-#define CONFIG_SYS_HZ 1000
#define CONFIG_AT91FAMILY
*/
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_MALLOC_LEN SZ_1M
-#define CONFIG_SYS_GBL_DATA_SIZE 128
#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
#define CONFIG_SYS_SDRAM_SIZE SZ_64M
#define CONFIG_SYS_TEXT_BASE 0x83FA0000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size/bytes res'd for init data*/
#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+ (CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
#define CONFIG_SYS_OMAP_ABE_SYSCK
+/* Define the default GPT table for eMMC */
+#define PARTS_DEFAULT \
+ "uuid_disk=${uuid_gpt_disk};" \
+ "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}"
+
#include <configs/ti_omap5_common.h>
+/* Enhance our eMMC support / experience. */
+#define CONFIG_CMD_GPT
+#define CONFIG_EFI_PARTITION
+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_CMD_PART
+
/* CPSW Ethernet */
#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */
#define CONFIG_CMD_DHCP
#define CONFIG_MII /* Required in net/eth.c */
#define CONFIG_PHY_GIGE /* per-board part of CPSW */
#define CONFIG_PHYLIB
-#define CONFIG_PHY_ADDR 2
/* SPI */
#undef CONFIG_OMAP3_SPI
#define CONFIG_SPL_SPI_CS 0
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
+#define CONFIG_SUPPORT_EMMC_BOOT
+
/* USB xHCI HOST */
#define CONFIG_CMD_USB
#define CONFIG_USB_HOST
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Michael Schwingen, michael@schwingen.org
- *
- * Configuration settings for the
- * dLAN200 AV Wireless G ("dvlhost") board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_IXP425 1
-#define CONFIG_DVLHOST 1
-
-#define CONFIG_MACH_TYPE 1343
-
-#define CONFIG_DISPLAY_CPUINFO 1
-#define CONFIG_DISPLAY_BOARDINFO 1
-
-#define CONFIG_IXP_SERIAL
-#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART2
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_BOARD_EARLY_INIT_F 1
-#define CONFIG_SYS_LDSCRIPT "board/dvlhost/u-boot.lds"
-
-/***************************************************************
- * U-boot generic defines start here.
- ***************************************************************/
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/* Command line configuration. */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ELF
-#define CONFIG_PCI
-#ifdef CONFIG_PCI
-#define CONFIG_CMD_PCI
-#define CONFIG_PCI_PNP
-#define CONFIG_IXP_PCI
-#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_CMD_PCI_ENUM
-#endif
-
-#define CONFIG_BOOTCOMMAND "run boot_flash"
-/* enable passing of ATAGs */
-#define CONFIG_CMDLINE_TAG 1
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_KGDB_BAUDRATE 230400
-#endif
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP
-/* Console I/O Buffer Size */
-#define CONFIG_SYS_CBSIZE 256
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-/* max number of command args */
-#define CONFIG_SYS_MAXARGS 16
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START 0x00000000
-#define CONFIG_SYS_MEMTEST_END 0x01D80000
-
-/* timer clock - 2* OSC_IN system clock */
-#define CONFIG_IXP425_TIMER_CLK 66666666
-
-/* default load address */
-#define CONFIG_SYS_LOAD_ADDR 0x00010000
-
-/* valid baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
- 115200, 230400 }
-#define CONFIG_SERIAL_RTS_ACTIVE 1
-
-/* Expansion bus settings */
-#define CONFIG_SYS_EXP_CS0 0xbd113442
-
-/* SDRAM settings */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 0x00000000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-
-/* 32MB SDRAM: 2* 8Mx16, CL3 */
-#define CONFIG_SYS_SDR_CONFIG 0x18
-#define PHYS_SDRAM_1_SIZE 0x02000000
-#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x800
-#define CONFIG_SYS_SDR_MODE_CONFIG 0x1
-#define CONFIG_SYS_DRAM_SIZE PHYS_SDRAM_1_SIZE
-
-/* FLASH organization: one Spansion S29AL032D-04 Flash */
-#define CONFIG_SYS_TEXT_BASE 0x50000000
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-/* max number of sectors on one chip */
-#define CONFIG_SYS_MAX_FLASH_SECT 140
-#define PHYS_FLASH_1 0x50000000
-#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 }
-
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
-#define CONFIG_SYS_MONITOR_LEN (256 << 10)
-#define CONFIG_BOARD_SIZE_LIMIT 262144
-
-/* Use common CFI driver */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-/* no byte writes on IXP4xx */
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-
-/* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-/* Ethernet */
-
-/* include IXP4xx NPE support */
-#define CONFIG_IXP4XX_NPE 1
-
-/* NPE0 PHY: MII dLAN200 AVmodule, 100BaseT-FDX fixed */
-#define CONFIG_PHY_ADDR 0x18
-/* NPE1 PHY: MII IP175 switch, port 5 is host port */
-#define CONFIG_PHY1_ADDR 0x05
-/* MII PHY management */
-#define CONFIG_MII 1
-/* fixed-speed powerline modem without standard PHY registers on MII */
-#define CONFIG_MII_NPE0_FIXEDLINK 1
-#define CONFIG_MII_NPE0_SPEED 100
-#define CONFIG_MII_NPE0_FULLDUPLEX 1
-/* fixed-speed switch without standard PHY registers on MII */
-#define CONFIG_MII_NPE1_FIXEDLINK 1
-#define CONFIG_MII_NPE1_SPEED 100
-#define CONFIG_MII_NPE1_FULLDUPLEX 1
-
-/* Number of ethernet rx buffers & descriptors */
-#define CONFIG_SYS_RX_ETH_BUFFER 16
-#define CONFIG_RESET_PHY_R 1
-/* ethernet switch connected to MII port */
-#define CONFIG_MII_ETHSWITCH 1
-#define CONFIG_HAS_ETH1 1
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#undef CONFIG_CMD_NFS
-
-/* BOOTP options */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/* Cache Configuration */
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
-/*
- * environment organization:
- * one flash sector, embedded in uboot area (bottom bootblock flash)
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x4000)
-#define CONFIG_SYS_USE_PPCENV 1
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "npe_ucode=50040000\0" \
- "ethprime=NPE1\0" \
- "ethrotate=no\0" \
- "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root),\0" \
- "kerneladdr=50050000\0" \
- "kernelfile=dvlhost/uImage\0" \
- "rootfile=dvlhost/rootfs\0" \
- "rootaddr=50170000\0" \
- "loadaddr=10000\0" \
- "updateboot_ser=mw.b 10000 ff 40000;" \
- " loady ${loadaddr};" \
- " run eraseboot writeboot\0" \
- "updateboot_net=mw.b 10000 ff 40000;" \
- " tftp ${loadaddr} dvlhost/u-boot.bin;" \
- " run eraseboot writeboot\0" \
- "eraseboot=protect off 50000000 50003fff;" \
- " protect off 50006000 5003ffff;" \
- " erase 50000000 50003fff;" \
- " erase 50006000 5003ffff\0" \
- "writeboot=cp.b 10000 50000000 4000;" \
- " cp.b 16000 50006000 3a000\0" \
- "updateucode=loady;" \
- " era ${npe_ucode} +${filesize};" \
- " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \
- "updateroot=tftp ${loadaddr} ${rootfile};" \
- " era ${rootaddr} +${filesize};" \
- " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \
- "updatekern=tftp ${loadaddr} ${kernelfile};" \
- " era ${kerneladdr} +${filesize};" \
- " cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \
- "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \
- " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
- "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \
- " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
- "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \
- "boot_flash=run flashargs addtty addeth;" \
- " bootm ${kerneladdr}\0" \
- "boot_net=run netargs addtty addeth;" \
- " tftpboot ${loadaddr} ${kernelfile};" \
- " bootm\0"
-
-/* additions for new relocation code, must be added to all boards */
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
-
-#endif /* __CONFIG_H */
#define BOARD_DFU_BUTTON_GPIO 27
#define BOARD_DFU_BUTTON_LED 64
+#define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */
#undef CONFIG_DOS_PARTITION
#undef CONFIG_CMD_FAT
#undef CONFIG_MII
#undef CONFIG_PHY_GIGE
-#define CONFIG_PHY_ADDR 0
#define CONFIG_PHY_SMSC
#define CONFIG_FACTORYSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
/* Size of DRAM reserved for malloc() use */
#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
-/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE (256)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* ENV setting */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_SYS_HZ 1000
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size/bytes res'd for init data*/
#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+ (CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size/bytes res'd for init data*/
#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+ (CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
#endif /* CONFIG_KM_UBI_PARTITION_NAME_BOOT */
+#ifndef CONFIG_KM_UBI_PART_BOOT_OPTS
+#define CONFIG_KM_UBI_PART_BOOT_OPTS ""
+#endif /* CONFIG_KM_UBI_PART_BOOT_OPTS */
+
#ifndef CONFIG_KM_UBI_PARTITION_NAME_APP
/* one flash chip only called boot */
/* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */
# define CONFIG_KM_UBI_LINUX_MTD \
- "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT
+ "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT \
+ CONFIG_KM_UBI_PART_BOOT_OPTS
# define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI \
"ubiattach=ubi part " CONFIG_KM_UBI_PARTITION_NAME_BOOT "\0"
#else /* CONFIG_KM_UBI_PARTITION_NAME_APP */
/* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */
/* app: CONFIG_KM_UBI_PARTITION_NAME_APP */
# define CONFIG_KM_UBI_LINUX_MTD \
- "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT " " \
+ "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT \
+ CONFIG_KM_UBI_PART_BOOT_OPTS " " \
"ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_APP
# define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI \
"ubiattach=if test ${boot_bank} -eq 0; then; " \
* - 'release': for a standalone system kernel/rootfs from flash
*/
#define CONFIG_KM_DEF_ENV_BOOTTARGETS \
- "subbootcmds=ubiattach ubicopy cramfsloadfdt cramfsloadkernel " \
- "flashargs add_default addpanic boot\0" \
+ "subbootcmds=ubiattach ubicopy cramfsloadfdt set_fdthigh " \
+ "cramfsloadkernel flashargs add_default addpanic boot\0"\
"develop=" \
"tftp 200000 scripts/develop-${arch}.txt && " \
"env import -t 200000 ${filesize} && " \
CONFIG_KM_DEF_ENV_FLASH_BOOT \
CONFIG_KM_DEF_ENV_CONSTANTS \
"altbootcmd=run bootcmd\0" \
+ "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \
"bootcmd=km_checkbidhwk && " \
"setenv bootcmd \'if km_checktestboot; then; " \
"setenv boot_bank ${test_bank}; else; " \
"run ${subbootcmds}; reset\' && " \
"saveenv && saveenv && boot\0" \
"bootlimit=3\0" \
+ "cramfsloadfdt=" \
+ "cramfsload ${fdt_addr_r} " \
+ "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
+ "fdt_addr_r="__stringify(CONFIG_KM_FDT_ADDR) "\0" \
"init=/sbin/init-overlay.sh\0" \
"load_addr_r="__stringify(CONFIG_KM_KERNEL_ADDR) "\0" \
"load=tftpboot ${load_addr_r} ${u-boot}\0" \
#define CONFIG_KM_DEF_BOOT_ARGS_CPU ""
#define CONFIG_KM_DEF_ENV_CPU \
- "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \
- "cramfsloadfdt=" \
- "cramfsload ${fdt_addr_r} " \
- "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
- "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \
"u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
"update=" \
"protect off " __stringify(BOOTFLASH_START) " +${filesize} && "\
"cp.b ${load_addr_r} " __stringify(BOOTFLASH_START) \
" ${filesize} && " \
"protect on " __stringify(BOOTFLASH_START) " +${filesize}\0"\
+ "set_fdthigh=true\0" \
""
#endif /* __CONFIG_KEYMILE_POWERPC_H */
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_KM_PHRAM 0x17F000
#define CONFIG_KM_CRAMFS_ADDR 0x2400000
-#define CONFIG_KM_KERNEL_ADDR 0x2000000 /* 4096KBytes */
+#define CONFIG_KM_KERNEL_ADDR 0x2000000 /* 3098KBytes */
+#define CONFIG_KM_FDT_ADDR 0x23E0000 /* 128KBytes */
/* architecture specific default bootargs */
#define CONFIG_KM_DEF_BOOT_ARGS_CPU \
" boardid=0x${IVM_BoardId} hwkey=0x${IVM_HWKey}"
#define CONFIG_KM_DEF_ENV_CPU \
- "boot=bootm ${load_addr_r} - -\0" \
- "cramfsloadfdt=true\0" \
"u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.kwb\0" \
CONFIG_KM_UPDATE_UBOOT \
+ "set_fdthigh=setenv fdt_high ${kernelmem}\0" \
""
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
#define CONFIG_MISC_INIT_R
+/* Pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+
/*
* NS16550 Configuration
*/
" ${addr} " __stringify(CONFIG_ENV_OFFSET_REDUND) " 4\0"
#endif
+#ifndef CONFIG_KM_BOARD_EXTRA_ENV
+#define CONFIG_KM_BOARD_EXTRA_ENV ""
+#endif
+
/*
* Default environment variables
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_KM_BOARD_EXTRA_ENV \
CONFIG_KM_DEF_ENV \
CONFIG_KM_NEW_ENV \
"arch=arm\0" \
#define CONFIG_KM_DEF_NETDEV "netdev=eth0\0"
+/* an additionnal option is required for UBI as subpage access is
+ * supported in u-boot */
+#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048"
+
#define CONFIG_NAND_ECC_BCH
/* common KM defines */
#define CONFIG_KM_KERNEL_ADDR 0x1000000 /* max kernel size 15.5Mbytes */
#define CONFIG_KM_FDT_ADDR 0x1F80000 /* max dtb size 0.5Mbytes */
-#define CONFIG_BOOTCOUNT_LIMIT
-
/*
* Local Bus Definitions
*/
#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */
+/* bootcounter in QRIO */
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_QRIO_BASE + 0x20)
+
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
+#define CONFIG_MISC_INIT_F
#define CONFIG_MISC_INIT_R
#define CONFIG_LAST_STAGE_INIT
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
/* I2C */
+
#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_SYS_I2C_SPEED 100000 /* deblocking */
#define CONFIG_SYS_NUM_I2C_BUSES 3
#define CONFIG_SYS_I2C_MAX_HOPS 1
#define CONFIG_SYS_I2C_FSL /* Use FSL I2C driver */
{0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
{0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \
}
+#ifndef __ASSEMBLY__
+void set_sda(int state);
+void set_scl(int state);
+int get_sda(void);
+int get_scl(void);
+#endif
#define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_BAR /* 4 byte-addressing */
#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 20000000
#define CONFIG_SF_DEFAULT_MODE 0
"update=" \
"sf probe 0;sf erase 0 +${filesize};" \
"sf write ${load_addr_r} 0 ${filesize};\0" \
+ "set_fdthigh=true\0" \
""
#define CONFIG_HW_ENV_SETTINGS \
#define CONFIG_KM_DISABLE_PCIE
#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
-/* KM_NUSA */
-#elif defined(CONFIG_KM_NUSA)
+/* KM_NUSA / KM_SUGP1 */
+#elif defined(CONFIG_KM_NUSA) || defined(CONFIG_KM_SUGP1)
#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
+
+# if defined(CONFIG_KM_NUSA)
#define CONFIG_IDENT_STRING "\nKeymile NUSA"
#define CONFIG_HOSTNAME kmnusa
+# elif defined(CONFIG_KM_SUGP1)
+#define CONFIG_IDENT_STRING "\nKeymile SUGP1"
+#define CONFIG_HOSTNAME kmsugp1
+#define KM_PCIE_RESET_MPP7
+#endif
+
#undef CONFIG_SYS_KWD_CONFIG
#define CONFIG_SYS_KWD_CONFIG \
$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
#define CONFIG_IDENT_STRING "\nKeymile SUV31"
#define CONFIG_HOSTNAME kmsuv31
+#undef CONFIG_SYS_KWD_CONFIG
+#define CONFIG_SYS_KWD_CONFIG \
+ $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
#define CONFIG_KM_ENV_IS_IN_SPI_NOR
#define CONFIG_KM_FPGA_CONFIG
#define CONFIG_HOSTNAME kmlion1
#define CONFIG_KM_BOARD_NAME "kmlion1"
+/* KMCOGE4 */
+#elif defined(CONFIG_KMCOGE4)
+#define CONFIG_HOSTNAME kmcoge4
+#define CONFIG_KM_BOARD_NAME "kmcoge4"
+
#else
#error ("Board not supported")
#endif
#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_LBAPP1_BR_PRELIM
/* Local bus app1 Options */
#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_LBAPP1_OR_PRELIM
+#endif
/* App2 Local bus */
#define CONFIG_SYS_LBAPP2_BASE 0xE0000000
#define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_LBAPP2_BR_PRELIM
/* Local bus app2 Options */
#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_LBAPP2_OR_PRELIM
-#endif
#endif /* __CONFIG_H */
#define CONFIG_SYS_MONITOR_BASE 0x00000000
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
-#define CONFIG_SYS_GBL_DATA_SIZE (256)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* FLASH */
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ 14745600
#define CONFIG_SYS_TMU_CLK_DIV 4
-#define CONFIG_SYS_HZ 1000
/* i2c */
#define CONFIG_CMD_I2C
--- /dev/null
+/*
+ * kwb.h
+ *
+ * specific parts for B&R KWB Motherboard
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at> -
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_KWB_H__
+#define __CONFIG_KWB_H__
+
+#include <configs/bur_am335x_common.h>
+/* ------------------------------------------------------------------------- */
+/* Clock Defines */
+#define V_OSCK 26000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK)
+
+#define CONFIG_POWER_TPS65217
+
+#define CONFIG_MACH_TYPE 3589
+/* I2C IP block */
+#define CONFIG_SYS_OMAP24_I2C_SPEED_PSOC 20000
+
+/* GPIO */
+#define CONFIG_SPL_GPIO_SUPPORT
+
+/* MMC/SD IP block */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_CMD_MMC
+#define CONFIG_SUPPORT_EMMC_BOOT
+/* RAW SD card / eMMC locations. */
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /*addr. 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
+#define CONFIG_SPL_MMC_SUPPORT
+
+#undef CONFIG_SPL_OS_BOOT
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_SYS_SPL_ARGS_ADDR 0x80F80000
+
+/* RAW SD card / eMMC */
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */
+
+#endif /* CONFIG_SPL_OS_BOOT */
+
+/* Always 128 KiB env size */
+#define CONFIG_ENV_SIZE (128 << 10)
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "autoload=0\0" \
+ "loadaddr=0x80100000\0" \
+ "bootfile=arimg\0" \
+ "usbboot=echo Booting from USB-Stick ...; " \
+ "usb start; " \
+ "fatload usb 0 ${loadaddr} ${bootfile}; " \
+ "usb stop; " \
+ "go ${loadaddr};\0" \
+ "netboot=echo Booting from network ...; " \
+ "setenv autoload 0; " \
+ "dhcp; " \
+ "tftp ${loadaddr} arimg; " \
+ "go ${loadaddr}\0" \
+ "usbupdate=echo Updating UBOOT from USB-Stick ...; " \
+ "usb start; " \
+ "fatload usb 0 0x80000000 updateubootusb.img; " \
+ "source;\0" \
+ "netupdate=echo Updating UBOOT from Network (TFTP) ...; " \
+ "setenv autoload 0; " \
+ "dhcp;" \
+ "tftp 0x80000000 updateUBOOT.img;" \
+ "source;\0"
+#endif /* !CONFIG_SPL_BUILD*/
+
+#define CONFIG_BOOTCOMMAND \
+ "run usbupdate;"
+#define CONFIG_BOOTDELAY 1 /* TODO: für release auf 0 setzen */
+
+/* undefine command which we not need here */
+#undef CONFIG_BOOTM_LINUX
+#undef CONFIG_BOOTM_NETBSD
+#undef CONFIG_BOOTM_PLAN9
+#undef CONFIG_BOOTM_RTEMS
+#undef CONFIG_GZIP
+#undef CONFIG_ZLIB
+#undef CONFIG_CMD_CRC32
+
+/* USB configuration */
+#define CONFIG_USB_MUSB_DSPS
+#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_MUSB_PIO_ONLY
+#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT
+/* attention! not only for gadget, enables also highspeed in hostmode */
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_MUSB_HOST
+#define CONFIG_AM335X_USB0
+#define CONFIG_AM335X_USB0_MODE MUSB_HOST
+
+#ifdef CONFIG_MUSB_HOST
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#endif /* CONFIG_MUSB_HOST */
+
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 1
+#define CONFIG_SYS_MMC_ENV_PART 2
+#define CONFIG_ENV_OFFSET 0x40000 /* TODO: Adresse definieren */
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+/*
+ * Common filesystems support. When we have removable storage we
+ * enabled a number of useful commands and support.
+ */
+#if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE)
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+#define CONFIG_FAT_WRITE
+#define CONFIG_CMD_FS_GENERIC
+#endif /* CONFIG_MMC, ... */
+
+#endif /* ! __CONFIG_TSERIES_H__ */
#define CONFIG_SYS_MONITOR_BASE (KZM_FLASH_BASE)
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
-#define CONFIG_SYS_GBL_DATA_SIZE (256)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
#define CONFIG_SYS_TEXT_BASE 0x00000000
#define CONFIG_SYS_MONITOR_BASE 0x00000000
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
-#define CONFIG_SYS_GBL_DATA_SIZE (256)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
#if defined(CONFIG_SYS_USE_BOOT_NORFLASH)
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_MP_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV 4
-#define CONFIG_SYS_HZ 1000
#endif /* __LAGER_H */
/* EHCI */
#define CONFIG_USB_STORAGE
+#define CONFIG_OMAP3_GPIO_2
#define CONFIG_OMAP3_GPIO_5
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_OMAP
"${mtdparts} " \
"vram=6M omapfb.vram=1:2M,2:2M,3:2M " \
"omapdss.def_disp=lcd;" \
- "bootm 0x82000000 0x84000000\0"
-
-#define CONFIG_BOOTCOMMAND \
- "run nandboot"
+ "bootm 0x82000000 0x84000000\0" \
+ "bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;" \
+ "then source 82000000;else run nandboot;fi\0"
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_NAND_ECCSIZE 256
#define CONFIG_SYS_NAND_ECCBYTES 3
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
+#define CONFIG_SPL_NAND_SOFTECC
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
# define CONFIG_SYS_MAX_FLASH_SECT 512
/* hardware flash protection */
# define CONFIG_SYS_FLASH_PROTECTION
-
+/* use buffered writes (20x faster) */
+# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
# ifdef RAMENV
# define CONFIG_ENV_IS_NOWHERE 1
# define CONFIG_ENV_SIZE 0x1000
# undef CONFIG_PHYLIB
#endif
+/* SPL part */
+#define CONFIG_SPL
+#define CONFIG_CMD_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_BOARD_INIT
+
+#define CONFIG_SPL_LDSCRIPT "arch/microblaze/cpu/u-boot-spl.lds"
+
+#define CONFIG_SPL_RAM_DEVICE
+#define CONFIG_SPL_NOR_SUPPORT
+
+/* for booting directly linux */
+#define CONFIG_SPL_OS_BOOT
+
+#define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + \
+ 0x60000)
+#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \
+ 0x40000)
+#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \
+ 0x1000000)
+
+/* SP location before relocation, must use scratch RAM */
+/* BRAM start */
+#define CONFIG_SYS_INIT_RAM_ADDR 0x0
+/* BRAM size - will be generated */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
+/* Stack pointer prior relocation, must situated at on-chip RAM */
+#define CONFIG_SYS_SPL_MALLOC_END (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100
+
+/*
+ * The main reason to do it in this way is that MALLOC_START
+ * can't be defined - common/spl/spl.c
+ */
+#if (CONFIG_SYS_SPL_MALLOC_SIZE != 0)
+# define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_SPL_MALLOC_END - \
+ CONFIG_SYS_SPL_MALLOC_SIZE)
+# define CONFIG_SPL_STACK_ADDR CONFIG_SYS_SPL_MALLOC_START
+#else
+# define CONFIG_SPL_STACK_ADDR CONFIG_SYS_SPL_MALLOC_END
+#endif
+
+/* Just for sure that there is a space for stack */
+#define CONFIG_SPL_STACK_SIZE 0x100
+
+#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \
+ CONFIG_SYS_INIT_RAM_ADDR - \
+ GENERATED_GBL_DATA_SIZE - \
+ CONFIG_SYS_SPL_MALLOC_SIZE - \
+ CONFIG_SPL_STACK_SIZE)
+
#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- * Gary Jennejohn <gj@denx.de>
- * David Mueller <d.mueller@elsoft.ch>
- *
- * (C) Copyright 2009-2010
- * Michel Pollet <buserror@gmail.com>
- *
- * (C) Copyright 2012
- * Gabriel Huau <contact@huau-gabriel.fr>
- *
- * Configuation settings for the MINI2440 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_SYS_TEXT_BASE 0x0
-#define CONFIG_S3C2440_GPIO
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_ARM920T /* This is an ARM920T Core */
-#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24X0 SoC */
-#define CONFIG_S3C2440 /* in a SAMSUNG S3C2440 SoC */
-#define CONFIG_MINI2440 /* on a MIN2440 Board */
-
-#define MACH_TYPE_MINI2440 1999
-#define CONFIG_MACH_TYPE MACH_TYPE_MINI2440
-
-/*
- * We don't use lowlevel_init
- */
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_BOARD_EARLY_INIT_F
-
-/*
- * input clock of PLL
- */
-/* MINI2440 has 12.0000MHz input clock */
-#define CONFIG_SYS_CLK_FREQ 12000000
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048*1024)
-
-/*
- * Hardware drivers
- */
-#define CONFIG_DRIVER_DM9000
-#define CONFIG_DRIVER_DM9000_NO_EEPROM
-#define CONFIG_DM9000_BASE 0x20000300
-#define DM9000_IO CONFIG_DM9000_BASE
-#define DM9000_DATA (CONFIG_DM9000_BASE+4)
-
-/*
- * select serial console configuration
- */
-#define CONFIG_S3C24X0_SERIAL
-#define CONFIG_SERIAL1
-
-/*
- * allow to overwrite serial and ethaddr
- */
-#define CONFIG_ENV_OVERWRITE
-
-/*
- * Command definition
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PORTIO
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SAVES
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_LONGHELP
-#define CONFIG_SYS_PROMPT "MINI2440 => "
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 32
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START 0x30000000
-#define CONFIG_SYS_MEMTEST_END 0x34000000 /* 64MB in DRAM */
-
-/* default load address */
-#define CONFIG_SYS_LOAD_ADDR 0x32000000
-
-/* boot parameters address */
-#define CONFIG_BOOT_PARAM_ADDR 0x30000100
-
-/*
- * the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need
- * it to wrap 100 times (total 1562500) to get 1 sec.
- */
-#define CONFIG_SYS_HZ 1562500
-
-/*
- * valid baudrates
- */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-#define CONFIG_BAUDRATE 115200
-
-/*
- * Stack sizes
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_SIZE (64*1024*1024) /* 64MB of DRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x30000000
-#define CONFIG_SYS_FLASH_BASE 0x0
-
-/*
- * Stack should be on the SRAM because
- * DRAM is not init
- */
-#define CONFIG_SYS_INIT_SP_ADDR (0x40001000 - GENERATED_GBL_DATA_SIZE)
-
-/*
- * NOR FLASH organization
- * Now uses the standard CFI interface
- * FLASH and environment organization
- */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#define CONFIG_SYS_MONITOR_BASE 0x0
-/* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-/* 512 * 4096 sectors, or 32 * 64k blocks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512
-#define CONFIG_FLASH_SHOW_PROGRESS 1
-
-/*
- * Config for NOR flash
- */
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_MY_ENV_OFFSET 0x40000
-/* addr of environment */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_MY_ENV_OFFSET)
-/* 16k Total Size of Environment Sector */
-#define CONFIG_ENV_SIZE 0x4000
-
-/* ATAG configuration */
-#define CONFIG_INITRD_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_AUTO_COMPLETE
-
-#endif /* __CONFIG_H */
/* Memory sizes */
#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */
#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */
#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_MISC_INIT_R
#define CONFIG_MXC_GPIO
-#define CONFIG_MV_UDC
+#define CONFIG_CI_UDC
#define CONFIG_USBD_HS
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_ETHER
#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
#endif
-/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE 128
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
- CONFIG_SYS_GBL_DATA_SIZE)
+ GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_PARTITION_UUIDS
#define CONFIG_CMD_PART
#define CONFIG_HSMMC2_8BIT
+#define CONFIG_SUPPORT_EMMC_BOOT
/* Required support for the TCA642X GPIO we have on the uEVM */
#define CONFIG_TCA642X
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x11001000
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
-#define CONFIG_SPL_PAD_TO 0x18000
-#define CONFIG_SPL_MAX_SIZE (96 * 1024)
+#define CONFIG_SPL_PAD_TO 0x20000
+#define CONFIG_SPL_MAX_SIZE (128 * 1024)
#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
-#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
#define CONFIG_SPL_MMC_BOOT
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x11001000
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
-#define CONFIG_SPL_PAD_TO 0x18000
-#define CONFIG_SPL_MAX_SIZE (96 * 1024)
+#define CONFIG_SPL_PAD_TO 0x20000
+#define CONFIG_SPL_MAX_SIZE (128 * 1024)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
#define CONFIG_SPL_SPI_BOOT
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
-#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
-#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
-#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
+#if defined(CONFIG_P2020RDB)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
+#else
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
+#endif
#elif defined(CONFIG_NAND)
#ifdef CONFIG_TPL_BUILD
#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
#define CONFIG_OF_BOARD_SETUP
#define CONFIG_OF_STDOUT_VIA_ALIAS
-#define CONFIG_SYS_64BIT_VSPRINTF
-#define CONFIG_SYS_64BIT_STRTOUL
-
/* new uImage format support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
* Clock Configuration
*/
#undef CONFIG_SYS_CLKS_IN_HZ
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CPUSPEED 0x210 /* 416MHz ; N=2,L=16 */
/*
* Clock Configuration
*/
#undef CONFIG_SYS_CLKS_IN_HZ
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CPUSPEED 0x161 /* 400MHz;L=1 M=3 T=1 */
/*
#define CONFIG_NET_MULTI
#define CONFIG_PHY_GIGE
#define CONFIG_PHYLIB
-#define CONFIG_PHY_ADDR 0
#define CONFIG_PHY_SMSC
#endif /* ! __CONFIG_PCM051_H */
--- /dev/null
+/*
+ * pengwyn.h
+ *
+ * Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
+ *
+ * based on am335x_evm.h, Copyright (C) 2011 Texas Instruments Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_PENGWYN_H
+#define __CONFIG_PENGWYN_H
+
+#define CONFIG_NAND
+#define CONFIG_SERIAL1
+#define CONFIG_CONS_INDEX 1
+
+#include <configs/ti_am335x_common.h>
+
+/* Clock Defines */
+#define V_OSCK 24000000
+#define V_SCLK V_OSCK
+
+/* set env size */
+#define CONFIG_ENV_SIZE 0x4000
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x80200000\0" \
+ "fdtaddr=0x80F80000\0" \
+ "bootpart=0:2\0" \
+ "bootdir=/boot\0" \
+ "bootfile=zImage\0" \
+ "fdtfile=am335x-pengwyn.dtb\0" \
+ "console=ttyO0,115200n8\0" \
+ "optargs=\0" \
+ "mmcdev=0\0" \
+ "mmcroot=/dev/mmcblk0p2 ro\0" \
+ "mmcrootfstype=ext4 rootwait\0" \
+ "rootpath=/export/rootfs\0" \
+ "nfsopts=nolock\0" \
+ "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \
+ "::off\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "${optargs} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype}\0" \
+ "netargs=setenv bootargs console=${console} " \
+ "${optargs} " \
+ "root=/dev/nfs " \
+ "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
+ "ip=dhcp\0" \
+ "bootenv=uEnv.txt\0" \
+ "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
+ "importbootenv=echo Importing environment from mmc ...; " \
+ "env import -t $loadaddr $filesize\0" \
+ "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+ "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+ "mmcloados=run mmcargs; " \
+ "bootz ${loadaddr} - ${fdtaddr};\0" \
+ "mmcboot=mmc dev ${mmcdev}; " \
+ "if mmc rescan; then " \
+ "echo SD/MMC found on device ${mmcdev};" \
+ "if run loadbootenv; then " \
+ "echo Loaded environment from ${bootenv};" \
+ "run importbootenv;" \
+ "fi;" \
+ "if test -n $uenvcmd; then " \
+ "echo Running uenvcmd ...;" \
+ "run uenvcmd;" \
+ "fi;" \
+ "if run loadimage; then " \
+ "run loadfdt;" \
+ "run mmcloados;" \
+ "fi;" \
+ "fi;\0" \
+ "netboot=echo Booting from network ...; " \
+ "setenv autoload no; " \
+ "dhcp; " \
+ "tftp ${loadaddr} ${bootfile}; " \
+ "tftp ${fdtaddr} ${fdtfile}; " \
+ "run netargs; " \
+ "bootz ${loadaddr} - ${fdtaddr}\0" \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "nandargs=setenv bootargs console=${console} " \
+ "${optargs} " \
+ "root=${nandroot} " \
+ "rootfstype=${nandrootfstype}\0" \
+ "nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \
+ "nandrootfstype=ubifs rootwait=1\0" \
+ "nandboot=echo Booting from nand ...; " \
+ "run nandargs; " \
+ "nand read ${fdtaddr} u-boot-spl-os; " \
+ "nand read ${loadaddr} kernel; " \
+ "bootz ${loadaddr} - ${fdtaddr}\0"
+#endif
+
+#define CONFIG_BOOTCOMMAND \
+ "run mmcboot;" \
+ "run nandboot;"
+
+/* NS16550 Configuration: primary UART via FDTI */
+#define CONFIG_SYS_NS16550_COM1 0x44e09000
+#define CONFIG_BAUDRATE 115200
+
+/* I2C Configuration */
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+
+/* SPL */
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_YMODEM_SUPPORT
+
+/* General network SPL */
+#define CONFIG_SPL_NET_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"
+
+/* NAND support */
+#define CONFIG_CMD_NAND
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_NAND_OMAP_ELM
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
+ CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+ 10, 11, 12, 13, 14, 15, 16, 17, \
+ 18, 19, 20, 21, 22, 23, 24, 25, \
+ 26, 27, 28, 29, 30, 31, 32, 33, \
+ 34, 35, 36, 37, 38, 39, 40, 41, \
+ 42, 43, 44, 45, 46, 47, 48, 49, \
+ 50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE 512
+#define CONFIG_SYS_NAND_ECCBYTES 14
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
+
+#define GPMC_NAND_ECC_LP_x8_LAYOUT 1
+#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
+#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \
+ "128k(SPL.backup1)," \
+ "128k(SPL.backup2)," \
+ "128k(SPL.backup3),1792k(u-boot)," \
+ "128k(u-boot-spl-os)," \
+ "128k(u-boot-env),5m(kernel),-(rootfs)"
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+
+/*
+ * USB configuration. We enable MUSB support, both for host and for
+ * gadget. We set USB0 as peripheral and USB1 as host, based on the
+ * board schematic and physical port wired to each. Then for host we
+ * add mass storage support.
+ */
+#define CONFIG_USB_MUSB_DSPS
+#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_MUSB_GADGET
+#define CONFIG_MUSB_PIO_ONLY
+#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+#define CONFIG_MUSB_HOST
+#define CONFIG_AM335X_USB0
+#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
+#define CONFIG_AM335X_USB1
+#define CONFIG_AM335X_USB1_MODE MUSB_HOST
+
+#if defined(CONFIG_MUSB_HOST)
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#endif
+
+#if defined(CONFIG_SPL_BUILD)
+/* disable host part of MUSB in SPL */
+#undef CONFIG_MUSB_HOST
+/* Disable CPSW SPL support so we fit within the 101KiB limit. */
+#undef CONFIG_SPL_ETH_SUPPORT
+#endif
+
+/* Network */
+#define CONFIG_CMD_MII
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_RESET 1
+#define CONFIG_PHY_NATSEMI
+
+/* CPSW support */
+#define CONFIG_SPL_ETH_SUPPORT
+
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
+
+#endif /* ! __CONFIG_PENGWYN_H */
#undef CONFIG_SPL_NET_VCI_STRING
#undef CONFIG_SPL_ETH_SUPPORT
-#define CONFIG_PHY_ADDR 0
#define CONFIG_PHY_ATHEROS
#define CONFIG_FACTORYSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
/* Size of DRAM reserved for malloc() use */
#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
-/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE (256)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* ENV setting */
#define CONFIG_SYS_LOAD_ADDR 0x1000000
#define CONFIG_CONSOLE_MUX
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_PREBOOT \
+ "if load mmc 0:1 ${loadaddr} /uEnv.txt; then " \
+ "env import -t ${loadaddr} ${filesize}; " \
+ "fi"
+
+#define ENV_DEVICE_SETTINGS \
+ "stdin=serial,lcd\0" \
+ "stdout=serial,lcd\0" \
+ "stderr=serial,lcd\0"
+
/*
* Memory layout for where various images get loaded by boot scripts:
*
* scriptaddr can be pretty much anywhere that doesn't conflict with something
* else. Put it low in memory to avoid conflicts.
*
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ * something else. Put it low in memory to avoid conflicts.
+ *
* kernel_addr_r must be within the first 128M of RAM in order for the
* kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
* decompress itself to 0x8000 after the start of RAM, kernel_addr_r
* ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
* for the FDT/DTB to be up to 1M, which is hopefully plenty.
*/
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "stdin=serial\0" \
- "stderr=serial,lcd\0" \
- "stdout=serial,lcd\0" \
+#define ENV_MEM_LAYOUT_SETTINGS \
"scriptaddr=0x00000000\0" \
+ "pxefile_addr_r=0x00100000\0" \
"kernel_addr_r=0x01000000\0" \
"fdt_addr_r=0x02000000\0" \
+ "fdtfile=bcm2835-rpi-b.dtb\0" \
"ramdisk_addr_r=0x02100000\0" \
- "boot_targets=mmc0\0" \
- \
- "script_boot=" \
- "if fatload ${devtype} ${devnum}:1 " \
- "${scriptaddr} boot.scr.uimg; then " \
- "source ${scriptaddr}; " \
- "fi;\0" \
- \
+
+#define BOOTCMDS_MMC \
"mmc_boot=" \
"setenv devtype mmc; " \
"if mmc dev ${devnum}; then " \
- "run script_boot; " \
+ "run scan_boot; " \
"fi\0" \
+ "bootcmd_mmc0=setenv devnum 0; run mmc_boot;\0"
+#define BOOT_TARGETS_MMC "mmc0"
+
+#define BOOTCMDS_COMMON \
+ "rootpart=1\0" \
+ \
+ "do_script_boot=" \
+ "load ${devtype} ${devnum}:${rootpart} " \
+ "${scriptaddr} ${prefix}${script}; " \
+ "source ${scriptaddr}\0" \
+ \
+ "script_boot=" \
+ "for script in ${boot_scripts}; do " \
+ "if test -e ${devtype} ${devnum}:${rootpart} " \
+ "${prefix}${script}; then " \
+ "echo Found ${prefix}${script}; " \
+ "run do_script_boot; " \
+ "echo SCRIPT FAILED: continuing...; " \
+ "fi; " \
+ "done\0" \
+ \
+ "do_sysboot_boot=" \
+ "sysboot ${devtype} ${devnum}:${rootpart} any " \
+ "${scriptaddr} ${prefix}extlinux/extlinux.conf\0" \
+ \
+ "sysboot_boot=" \
+ "if test -e ${devtype} ${devnum}:${rootpart} " \
+ "${prefix}extlinux/extlinux.conf; then " \
+ "echo Found ${prefix}extlinux/extlinux.conf; " \
+ "run do_sysboot_boot; " \
+ "echo SCRIPT FAILED: continuing...; " \
+ "fi\0" \
+ \
+ "scan_boot=" \
+ "echo Scanning ${devtype} ${devnum}...; " \
+ "for prefix in ${boot_prefixes}; do " \
+ "run sysboot_boot; " \
+ "run script_boot; " \
+ "done\0" \
+ \
+ "boot_targets=" \
+ BOOT_TARGETS_MMC " " \
+ "\0" \
+ \
+ "boot_prefixes=/\0" \
+ \
+ "boot_scripts=boot.scr.uimg\0" \
\
- "bootcmd_mmc0=setenv devnum 0; run mmc_boot\0" \
+ BOOTCMDS_MMC
#define CONFIG_BOOTCOMMAND \
"for target in ${boot_targets}; do run bootcmd_${target}; done"
-#define CONFIG_BOOTDELAY 2
+#define CONFIG_BOOTCOMMAND \
+ "for target in ${boot_targets}; do run bootcmd_${target}; done"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ ENV_DEVICE_SETTINGS \
+ ENV_MEM_LAYOUT_SETTINGS \
+ BOOTCMDS_COMMON
+
+#define CONFIG_BOOTDELAY 2
/* Shell */
-#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_MAXARGS 8
#define CONFIG_SYS_PROMPT "U-Boot> "
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CMDLINE_EDITING
#define CONFIG_COMMAND_HISTORY
-#define CONFIG_AUTO_COMPLETE
/* Commands */
#include <config_cmd_default.h>
-#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_GPIO
#define CONFIG_CMD_MMC
-#define CONFIG_DOS_PARTITION
#define CONFIG_PARTITION_UUIDS
#define CONFIG_CMD_PART
-#define CONFIG_CMD_FS_GENERIC
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT
-/* Some things don't make sense on this HW or yet */
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_SAVEENV
-/* Device tree support for bootm/bootz */
-#define CONFIG_OF_LIBFDT
+/* Device tree support */
#define CONFIG_OF_BOARD_SETUP
/* ATAGs support for bootm/bootz */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#define CONFIG_INITRD_TAG
+#include <config_distro_defaults.h>
+
+/* Some things don't make sense on this HW or yet */
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_SAVEENV
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_PING
+
#endif
#undef CONFIG_SPL_NET_VCI_STRING
#undef CONFIG_SPL_ETH_SUPPORT
-#define CONFIG_PHY_ADDR 1
#define CONFIG_PHY_NATSEMI
#define CONFIG_FACTORYSET
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
+#define CONFIG_REVISION_TAG
#define CONFIG_INITRD_TAG
#define CONFIG_CMDLINE_EDITING
#define CONFIG_UBIFS_OPTION "rootflags=bulk_read,no_chk_data_crc"
+#define CONFIG_MISC_COMMON
+#define CONFIG_MISC_INIT_R
+
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_UPDATEB \
"updatek=" \
/*
* I2C Settings
*/
-#define CONFIG_SOFT_I2C_GPIO_SCL s5pc110_gpio_get_nr(j4, 3)
-#define CONFIG_SOFT_I2C_GPIO_SDA s5pc110_gpio_get_nr(j4, 0)
+#define CONFIG_SOFT_I2C_GPIO_SCL s5pc110_gpio_get(j4, 3)
+#define CONFIG_SOFT_I2C_GPIO_SDA s5pc110_gpio_get(j4, 0)
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
#define CONFIG_EXTRA_ENV_SETTINGS \
"updateb=" \
"onenand erase 0x0 0x100000;" \
/*
* I2C Settings
*/
-#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_part1_get_nr(b, 7)
-#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_part1_get_nr(b, 6)
+#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_get(1, b, 7)
+#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_get(1, b, 6)
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
*/
#define CONFIG_SOFT_SPI
#define CONFIG_SOFT_SPI_MODE SPI_MODE_3
-#define CONFIG_SOFT_SPI_GPIO_SCLK exynos4_gpio_part2_get_nr(y3, 1)
-#define CONFIG_SOFT_SPI_GPIO_MOSI exynos4_gpio_part2_get_nr(y3, 3)
-#define CONFIG_SOFT_SPI_GPIO_MISO exynos4_gpio_part2_get_nr(y3, 0)
-#define CONFIG_SOFT_SPI_GPIO_CS exynos4_gpio_part2_get_nr(y4, 3)
+#define CONFIG_SOFT_SPI_GPIO_SCLK exynos4_gpio_get(2, y3, 1)
+#define CONFIG_SOFT_SPI_GPIO_MOSI exynos4_gpio_get(2, y3, 3)
+#define CONFIG_SOFT_SPI_GPIO_MISO exynos4_gpio_get(2, y3, 0)
+#define CONFIG_SOFT_SPI_GPIO_CS exynos4_gpio_get(2, y4, 3)
#define SPI_DELAY udelay(1)
#undef SPI_INIT
int universal_spi_read(void);
#endif
+/* Common misc for Samsung */
+#define CONFIG_MISC_COMMON
+
+#define CONFIG_MISC_INIT_R
+
+/* Download menu - Samsung common */
+#define CONFIG_LCD_MENU
+#define CONFIG_LCD_MENU_BOARD
+
+/* Download menu - definitions for check keys */
+#ifndef __ASSEMBLY__
+#include <power/max8998_pmic.h>
+
+#define KEY_PWR_PMIC_NAME "MAX8998_PMIC"
+#define KEY_PWR_STATUS_REG MAX8998_REG_STATUS1
+#define KEY_PWR_STATUS_MASK (1 << 7)
+#define KEY_PWR_INTERRUPT_REG MAX8998_REG_IRQ1
+#define KEY_PWR_INTERRUPT_MASK (1 << 7)
+
+#define KEY_VOL_UP_GPIO exynos4_gpio_get(2, x2, 0)
+#define KEY_VOL_DOWN_GPIO exynos4_gpio_get(2, x2, 1)
+#endif /* __ASSEMBLY__ */
+
+/* LCD console */
+#define LCD_BPP LCD_COLOR16
+#define CONFIG_SYS_WHITE_ON_BLACK
+
/*
* LCD Settings
*/
#define CONFIG_EXYNOS_FB
#define CONFIG_LCD
#define CONFIG_CMD_BMP
-#define CONFIG_BMP_32BPP
+#define CONFIG_BMP_16BPP
#define CONFIG_LD9040
#define CONFIG_EXYNOS_MIPI_DSIM
#define CONFIG_VIDEO_BMP_GZIP
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((520 * 120 * 4) + (1 << 12))
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
#endif /* __CONFIG_H */
#define CONFIG_CMD_PART
#define CONFIG_DOS_PARTITION
#define CONFIG_HOST_MAX_DEVICES 4
+#define CONFIG_CMD_FS_GENERIC
#define CONFIG_SYS_VSNPRINTF
#define CONFIG_EHCI_MXS_PORT0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_MV_UDC /* ChipIdea CI13xxx UDC */
+#define CONFIG_CI_UDC /* ChipIdea CI13xxx UDC */
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_ETHER
#define CONFIG_SYS_MEMTEST_START 0x08100000 /* memtest test area */
#define CONFIG_SYS_MEMTEST_END 0x08F00000
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CPUSPEED 0x141 /* core clock - register value */
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_MONITOR_BASE (SHMIN_FLASH_BASE_1 + CONFIG_ENV_SECT_SIZE)
#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 256
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* FLASH */
#undef CONFIG_DEFAULT_DEVICE_TREE
#define CONFIG_DEFAULT_DEVICE_TREE exynos5420-smdk5420
-#define CONFIG_ARCH_DEVICE_TREE exynos5420
-
#define CONFIG_VAR_SIZE_SPL
#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_ENV_SIZE (8*1024)
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */
-
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_CMD_ENV
#define CONFIG_CMD_SAVEENV
/* Ethernet driver configuration */
#define CONFIG_MII
#define CONFIG_DESIGNWARE_ETH
-#define CONFIG_DW_SEARCH_PHY
-#define CONFIG_DW0_PHY 1
#define CONFIG_NET_MULTI
+#define CONFIG_PHYLIB
#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
-#define CONFIG_DW_AUTONEG
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
/* USBD driver configuration */
/* I2C driver configuration */
#define CONFIG_HARD_I2C
#define CONFIG_DW_I2C
+#if defined(CONFIG_SPEAR600)
+#define CONFIG_SYS_I2C_BASE 0xD0200000
+#elif defined(CONFIG_SPEAR300)
+#define CONFIG_SYS_I2C_BASE 0xD0180000
+#elif defined(CONFIG_SPEAR310)
+#define CONFIG_SYS_I2C_BASE 0xD0180000
+#elif defined(CONFIG_SPEAR320)
+#define CONFIG_SYS_I2C_BASE 0xD0180000
+#endif
#define CONFIG_SYS_I2C_SPEED 400000
#define CONFIG_SYS_I2C_SLAVE 0x02
#define CONFIG_SYS_FSMC_NAND_8BIT
#define CONFIG_SYS_NAND_BASE 0xD2000000
+/* Ethernet PHY configuration */
+#define CONFIG_PHY_NATSEMI
+
/* Environment Settings */
#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY
#define CONFIG_OMAP_HSMMC
#define CONFIG_DOS_PARTITION
+/* GPIO banks */
+#define CONFIG_OMAP3_GPIO_2 /* GPIO32 ..63 is in GPIO bank 2 */
+#define CONFIG_OMAP3_GPIO_3 /* GPIO64 ..95 is in GPIO bank 3 */
+#define CONFIG_OMAP3_GPIO_4 /* GPIO96 ..127 is in GPIO bank 4 */
+#define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */
+#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */
+
/* commands to include */
#include <config_cmd_default.h>
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */
-#define CONFIG_SYS_HZ 1000
/* Misc CPU related */
#define CONFIG_ARCH_CPU_INIT
BOOTCMDS_DHCP
#define CONFIG_BOOTCOMMAND \
+ "set usb_need_init; " \
"for target in ${boot_targets}; do run bootcmd_${target}; done"
#endif
"stderr=serial" STDOUT_LCD "\0" \
""
+#ifndef BOARD_EXTRA_ENV_SETTINGS
+#define BOARD_EXTRA_ENV_SETTINGS
+#endif
+
#define CONFIG_EXTRA_ENV_SETTINGS \
TEGRA_DEVICE_SETTINGS \
MEM_LAYOUT_ENV_SETTINGS \
- BOOTCMDS_COMMON
+ BOOTCMDS_COMMON \
+ BOARD_EXTRA_ENV_SETTINGS
#if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK) || defined(CONFIG_TEGRA114_SPI)
#define CONFIG_FDT_SPI
--- /dev/null
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA124_COMMON_H_
+#define _TEGRA124_COMMON_H_
+
+#include "tegra-common.h"
+
+/* Cortex-A15 uses a cache line size of 64 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_TEGRA124 /* is an NVIDIA Tegra124 core */
+
+/* Environment information, boards can override if required */
+#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */
+#define CONFIG_STACKBASE 0x82800000 /* 40MB */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_SYS_TEXT_BASE 0x8010E000
+
+/*
+ * Memory layout for where various images get loaded by boot scripts:
+ *
+ * scriptaddr can be pretty much anywhere that doesn't conflict with something
+ * else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ * something else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * kernel_addr_r must be within the first 128M of RAM in order for the
+ * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
+ * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
+ * should not overlap that area, or the kernel will have to copy itself
+ * somewhere else before decompression. Similarly, the address of any other
+ * data passed to the kernel shouldn't overlap the start of RAM. Pushing
+ * this up to 16M allows for a sizable kernel to be decompressed below the
+ * compressed load address.
+ *
+ * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
+ * the compressed kernel to be up to 16M too.
+ *
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
+ * for the FDT/DTB to be up to 1M, which is hopefully plenty.
+ */
+#define MEM_LAYOUT_ENV_SETTINGS \
+ "scriptaddr=0x90000000\0" \
+ "pxefile_addr_r=0x90100000\0" \
+ "kernel_addr_r=0x81000000\0" \
+ "fdt_addr_r=0x82000000\0" \
+ "ramdisk_addr_r=0x82100000\0"
+
+/* Defines for SPL */
+#define CONFIG_SPL_TEXT_BASE 0x80108000
+#define CONFIG_SYS_SPL_MALLOC_START 0x80090000
+#define CONFIG_SPL_STACK 0x800ffffc
+
+/* Total I2C ports on Tegra124 */
+#define TEGRA_I2C_NUM_CONTROLLERS 5
+
+/* For USB EHCI controller */
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
+
+#endif /* _TEGRA124_COMMON_H_ */
#define CONFIG_NET_MULTI
#define CONFIG_PHY_GIGE
#define CONFIG_PHYLIB
-#define CONFIG_PHY_ADDR 1
#define CONFIG_PHY_ET1011C
#define CONFIG_PHY_ET1011C_TX_CLK_FIX
#define __CONFIG_TI_AM335X_COMMON_H__
#define CONFIG_AM33XX
-#define CONFIG_BOARD_LATE_INIT
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
/* Network defines. */
#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */
#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */
#endif
+#ifdef CONFIG_SPL_BUILD
+/* No need for i2c in SPL mode as we will use SRI2C for PMIC access on OMAP4 */
+#undef CONFIG_SYS_I2C
+#undef CONFIG_SYS_I2C_OMAP24XX
+#endif
+
#endif /* __CONFIG_TI_OMAP4_COMMON_H */
""PARTS_BOOT" part 0 2;" \
""PARTS_ROOT" part 0 5;" \
""PARTS_DATA" part 0 6;" \
- ""PARTS_UMS" part 0 7\0"
+ ""PARTS_UMS" part 0 7;" \
+ "params.bin mmc 0x38 0x8\0"
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootk=" \
- "run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \
+ "run loaduimage;" \
+ "if run loaddtb; then " \
+ "bootm 0x40007FC0 - ${fdtaddr};" \
+ "fi;" \
+ "bootm 0x40007FC0;\0" \
"updatemmc=" \
"mmc boot 0 1 1 1; mmc write 0 0x42008000 0 0x200;" \
"mmc boot 0 1 1 0\0" \
"mmcboot=" \
"setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
- "run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \
+ "run bootk\0" \
"bootchart=setenv opts init=/sbin/bootchartd; run bootcmd\0" \
"boottrace=setenv opts initcall_debug; run bootcmd\0" \
"mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \
"setenv spl_imgaddr;" \
"setenv spl_addr_tmp;\0" \
"fdtaddr=40800000\0" \
- "fdtfile=exynos4210-trats.dtb\0"
/* Miscellaneous configurable options */
#include <asm/arch/gpio.h>
/* I2C FG */
-#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_part2_get_nr(y4, 1)
-#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_part2_get_nr(y4, 0)
+#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_get(2, y4, 1)
+#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_get(2, y4, 0)
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_USB_CABLE_CHECK
+/* Common misc for Samsung */
+#define CONFIG_MISC_COMMON
+
+#define CONFIG_MISC_INIT_R
+
+/* Download menu - Samsung common */
+#define CONFIG_LCD_MENU
+#define CONFIG_LCD_MENU_BOARD
+
+/* Download menu - definitions for check keys */
+#ifndef __ASSEMBLY__
+#include <power/max8997_pmic.h>
+
+#define KEY_PWR_PMIC_NAME "MAX8997_PMIC"
+#define KEY_PWR_STATUS_REG MAX8997_REG_STATUS1
+#define KEY_PWR_STATUS_MASK (1 << 0)
+#define KEY_PWR_INTERRUPT_REG MAX8997_REG_INT1
+#define KEY_PWR_INTERRUPT_MASK (1 << 0)
+
+#define KEY_VOL_UP_GPIO exynos4_gpio_get(2, x2, 0)
+#define KEY_VOL_DOWN_GPIO exynos4_gpio_get(2, x2, 1)
+#endif /* __ASSEMBLY__ */
+
+/* LCD console */
+#define LCD_BPP LCD_COLOR16
+#define CONFIG_SYS_WHITE_ON_BLACK
+
/* LCD */
#define CONFIG_EXYNOS_FB
#define CONFIG_LCD
#define CONFIG_CMD_BMP
-#define CONFIG_BMP_32BPP
+#define CONFIG_BMP_16BPP
#define CONFIG_FB_ADDR 0x52504000
#define CONFIG_S6E8AX0
#define CONFIG_EXYNOS_MIPI_DSIM
#define CONFIG_VIDEO_BMP_GZIP
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 120 * 4) + (1 << 12))
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
#define CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_USB_GADGET_MASS_STORAGE
#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
/* Tizen - partitions definitions */
#define PARTS_CSA "csa"
#define PARTS_BOOT "boot"
""PARTS_BOOT" part 0 2;" \
""PARTS_ROOT" part 0 5;" \
""PARTS_DATA" part 0 6;" \
- ""PARTS_UMS" part 0 7\0"
+ ""PARTS_UMS" part 0 7;" \
+ "params.bin mmc 0x38 0x8\0"
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootk=" \
- "run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \
+ "run loaduimage;" \
+ "if run loaddtb; then " \
+ "bootm 0x40007FC0 - ${fdtaddr};" \
+ "fi;" \
+ "bootm 0x40007FC0;\0" \
"updatemmc=" \
"mmc boot 0 1 1 1; mmc write 0x42008000 0 0x200;" \
"mmc boot 0 1 1 0\0" \
"mmcboot=" \
"setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
- "run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \
+ "run bootk\0" \
"bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \
"boottrace=setenv opts initcall_debug; run bootcmd\0" \
"verify=n\0" \
"setenv spl_imgaddr;" \
"setenv spl_addr_tmp;\0" \
"fdtaddr=40800000\0" \
- "fdtfile=exynos4412-trats2.dtb\0"
/*
* Miscellaneous configurable options
#define CONFIG_EFI_PARTITION
#define CONFIG_PARTITION_UUIDS
-#define CONFIG_MISC_INIT_R
#define CONFIG_BOARD_EARLY_INIT_F
/* I2C */
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_USB_CABLE_CHECK
+/* Common misc for Samsung */
+#define CONFIG_MISC_COMMON
+
+#define CONFIG_MISC_INIT_R
+
+/* Download menu - Samsung common */
+#define CONFIG_LCD_MENU
+#define CONFIG_LCD_MENU_BOARD
+
+/* Download menu - definitions for check keys */
+#ifndef __ASSEMBLY__
+#include <power/max77686_pmic.h>
+
+#define KEY_PWR_PMIC_NAME "MAX77686_PMIC"
+#define KEY_PWR_STATUS_REG MAX77686_REG_PMIC_STATUS1
+#define KEY_PWR_STATUS_MASK (1 << 0)
+#define KEY_PWR_INTERRUPT_REG MAX77686_REG_PMIC_INT1
+#define KEY_PWR_INTERRUPT_MASK (1 << 1)
+
+#define KEY_VOL_UP_GPIO exynos4x12_gpio_get(2, x2, 2)
+#define KEY_VOL_DOWN_GPIO exynos4x12_gpio_get(2, x3, 3)
+#endif /* __ASSEMBLY__ */
+
+/* LCD console */
+#define LCD_BPP LCD_COLOR16
+#define CONFIG_SYS_WHITE_ON_BLACK
+
/* LCD */
#define CONFIG_EXYNOS_FB
#define CONFIG_LCD
#define CONFIG_CMD_BMP
-#define CONFIG_BMP_32BPP
+#define CONFIG_BMP_16BPP
#define CONFIG_FB_ADDR 0x52504000
#define CONFIG_S6E8AX0
#define CONFIG_EXYNOS_MIPI_DSIM
#define CONFIG_VIDEO_BMP_GZIP
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 250 * 4) + (1 << 12))
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
#define CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_USB_GADGET_MASS_STORAGE
--- /dev/null
+/*
+ * tseries.h
+ *
+ * specific parts for B&R T-Series Motherboard
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at> -
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_TSERIES_H__
+#define __CONFIG_TSERIES_H__
+
+#include <configs/bur_am335x_common.h>
+/* ------------------------------------------------------------------------- */
+/* Clock Defines */
+#define V_OSCK 26000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK)
+
+#define CONFIG_POWER_TPS65217
+
+/* Support both device trees and ATAGs. */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMD_BOOTZ
+/*#define CONFIG_MACH_TYPE 3589*/
+#define CONFIG_MACH_TYPE 0xFFFFFFFF /* TODO: check with kernel*/
+
+/* MMC/SD IP block */
+#if defined(CONFIG_EMMC_BOOT)
+ #define CONFIG_MMC
+ #define CONFIG_GENERIC_MMC
+ #define CONFIG_OMAP_HSMMC
+ #define CONFIG_CMD_MMC
+ #define CONFIG_SUPPORT_EMMC_BOOT
+/* RAW SD card / eMMC locations. */
+ #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /*addr. 0x60000 */
+ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
+ #define CONFIG_SPL_MMC_SUPPORT
+#endif /* CONFIG_EMMC_BOOT */
+
+/*
+ * When we have SPI or NAND flash we expect to be making use of mtdparts,
+ * both for ease of use in U-Boot and for passing information on to
+ * the Linux kernel.
+ */
+#if defined(CONFIG_SPI_BOOT) || defined(CONFIG_NAND)
+#define CONFIG_MTD_DEVICE /* Required for mtdparts */
+#define CONFIG_CMD_MTDPARTS
+#endif /* CONFIG_SPI_BOOT, ... */
+
+#undef CONFIG_SPL_OS_BOOT
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_SYS_SPL_ARGS_ADDR 0x80F80000
+
+/* RAW SD card / eMMC */
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */
+
+/* NAND */
+#ifdef CONFIG_NAND
+#define CONFIG_CMD_SPL_NAND_OFS 0x080000 /* end of u-boot */
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x140000
+#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
+#endif /* CONFIG_NAND */
+#endif /* CONFIG_SPL_OS_BOOT */
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL_NAND_AM33XX_BCH /* OMAP4 and later ELM support */
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
+#endif /* CONFIG_NAND */
+
+/* Always 128 KiB env size */
+#define CONFIG_ENV_SIZE (128 << 10)
+
+#ifdef CONFIG_NAND
+#define NANDARGS \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "nandargs=setenv bootargs console=${console} " \
+ "${optargs} " \
+ "root=${nandroot} " \
+ "rootfstype=${nandrootfstype}\0" \
+ "nandroot=ubi0:rootfs rw ubi.mtd=8,2048\0" \
+ "nandrootfstype=ubifs rootwait=1\0" \
+ "nandimgsize=0x500000\0" \
+ "nandboot=echo Booting from nand ...; " \
+ "run nandargs; " \
+ "nand read ${loadaddr} kernel ${nandimgsize}; " \
+ "bootz ${loadaddr}\0"
+#else
+#define NANDARGS ""
+#endif /* CONFIG_NAND */
+
+#ifdef CONFIG_MMC
+#define MMCARGS \
+ "silent=1\0"
+#else
+#define MMCARGS ""
+#endif /* CONFIG_MMC */
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "autoload=0\0" \
+ "loadaddr=0x80200000\0" \
+ "bootfile=zImage\0" \
+ "console=ttyO0,115200n8\0" \
+ "optargs=\0" \
+ "rootpath=/tftpboot/tseries/rootfs-small\0" \
+ "nfsopts=nolock\0" \
+ "netargs=setenv bootargs console=${console} " \
+ "${optargs} " \
+ "root=/dev/nfs " \
+ "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
+ "ip=dhcp\0" \
+ "netboot=echo Booting from network ...; " \
+ "setenv autoload no; " \
+ "dhcp; " \
+ "tftp ${loadaddr} ${bootfile}; " \
+ "run netargs; " \
+ "bootm ${loadaddr}\0" \
+ "usbupdate=echo Updating UBOOT from USB-Stick ...; " \
+ "usb start; " \
+ "fatload usb 0 0x80000000 updateubootusb.img; " \
+ "source;\0" \
+ "netupdate=echo Updating UBOOT from Network (TFTP) ...; " \
+ "setenv autoload 0; " \
+ "dhcp;" \
+ "tftp 0x80000000 updateUBOOT.img;" \
+ "source;\0" \
+ NANDARGS \
+ MMCARGS
+#endif /* !CONFIG_SPL_BUILD*/
+
+#define CONFIG_BOOTCOMMAND \
+ "run mmcboot1;"
+#define CONFIG_BOOTDELAY 1 /* TODO: für release auf 0 setzen */
+
+#ifdef CONFIG_NAND
+/*
+ * GPMC block. We support 1 device and the physical address to
+ * access CS0 at is 0x8000000.
+ */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x8000000
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_CMD_NAND
+/* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */
+#define CONFIG_NAND_OMAP_ELM
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
+#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
+#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
+ CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, \
+ 10, 11, 12, 13, 14, 15, 16, 17, \
+ 18, 19, 20, 21, 22, 23, 24, 25, \
+ 26, 27, 28, 29, 30, 31, 32, 33, \
+ 34, 35, 36, 37, 38, 39, 40, 41, \
+ 42, 43, 44, 45, 46, 47, 48, 49, \
+ 50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE 512
+#define CONFIG_SYS_NAND_ECCBYTES 14
+
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
+
+#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
+#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \
+ "128k(SPL)," \
+ "128k(SPL.backup1)," \
+ "128k(SPL.backup2)," \
+ "128k(SPL.backup3)," \
+ "512k(u-boot)," \
+ "128k(u-boot-spl-os)," \
+ "128k(u-boot-env)," \
+ "5m(kernel),"\
+ "-(rootfs)"
+#endif /* CONFIG_NAND */
+
+/* USB configuration */
+#define CONFIG_USB_MUSB_DSPS
+#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_MUSB_PIO_ONLY
+#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT
+/* attention! not only for gadget, enables also highspeed in hostmode */
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_MUSB_HOST
+#define CONFIG_AM335X_USB0
+#define CONFIG_AM335X_USB0_MODE MUSB_HOST
+#define CONFIG_AM335X_USB1
+#define CONFIG_AM335X_USB1_MODE MUSB_HOST
+
+#ifdef CONFIG_MUSB_HOST
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#endif /* CONFIG_MUSB_HOST */
+
+#if defined(CONFIG_SPI_BOOT)
+/* McSPI IP block */
+#define CONFIG_SPI
+#define CONFIG_OMAP3_SPI
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SF_DEFAULT_SPEED 24000000
+
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS 0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+#define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */
+#define CONFIG_ENV_OFFSET (768 << 10) /* 768 KiB in */
+#define CONFIG_ENV_OFFSET_REDUND (896 << 10) /* 896 KiB in */
+
+#elif defined(CONFIG_EMMC_BOOT)
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 1
+#define CONFIG_SYS_MMC_ENV_PART 2
+#define CONFIG_ENV_OFFSET 0x40000 /* TODO: Adresse definieren */
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+
+#elif defined(CONFIG_NAND)
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET 0x120000 /* TODO: Adresse definieren */
+#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_ENV_SIZE
+#else
+#error "no storage for Environment defined!"
+#endif
+/*
+ * Common filesystems support. When we have removable storage we
+ * enabled a number of useful commands and support.
+ */
+#if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE)
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+#define CONFIG_FAT_WRITE
+#define CONFIG_CMD_FS_GENERIC
+#endif /* CONFIG_MMC, ... */
+
+#endif /* ! __CONFIG_TSERIES_H__ */
#define CONFIG_ENV_SIZE (128*1024)
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024)
#endif
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */
/*
* PL011 Configuration
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_SYS_HZ 1000
#define CONFIG_CMDLINE_EDITING
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
-#define CONFIG_SYS_HZ 1000
#define CONFIG_MACH_TYPE MACH_TYPE_USB_A9263
--- /dev/null
+/*
+ * (C) Copyright 2013-2014
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/sizes.h>
+
+#include "tegra124-common.h"
+
+/* Enable fdt support for Venice2. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE tegra124-venice2
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* High-level configuration options */
+#define V_PROMPT "Tegra124 (Venice2) # "
+#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Venice2"
+
+/* Board-specific serial config */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_TEGRA_ENABLE_UARTA
+#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* I2C */
+#define CONFIG_SYS_I2C_TEGRA
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_MAX_I2C_BUS TEGRA_I2C_NUM_CONTROLLERS
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA_MMC
+#define CONFIG_CMD_MMC
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 2
+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
+
+/* SPI */
+#define CONFIG_TEGRA114_SPI /* Compatible w/ Tegra114 SPI */
+#define CONFIG_TEGRA114_SPI_CTRLS 6
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED 24000000
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_SIZE (4 << 20)
+
+/* USB Host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+
+/* General networking support */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* our CLE is AD22 */
#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PB(0)
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/* Ethernet */
*/
#define CONFIG_SYS_MALLOC_LEN \
ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
#ifndef CONFIG_RAMLOAD
#define CONFIG_BOOTCOMMAND "run nfsboot"
/* Ethernet config options */
#define CONFIG_MII
#define CONFIG_DESIGNWARE_ETH
-#define CONFIG_DW_SEARCH_PHY
#define CONFIG_NET_MULTI
+#define CONFIG_PHYLIB
#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
-#define CONFIG_DW_AUTONEG
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
/* I2C config options */
#define CONFIG_HARD_I2C
#define CONFIG_DW_I2C
+#define CONFIG_SYS_I2C_BASE 0xD0200000
#define CONFIG_SYS_I2C_SPEED 400000
#define CONFIG_SYS_I2C_SLAVE 0x02
#define CONFIG_I2C_CHIPADDRESS 0x50
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_LOAD_ADDR 0x00800000
#define CONFIG_SYS_CONSOLE_INFO_QUIET
-#define CONFIG_SYS_64BIT_VSPRINTF
/* Use last 2 lwords in internal SRAM for bootcounter */
#define CONFIG_BOOTCOUNT_LIMIT
#define CONFIG_EHCI_MXS_PORT0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_MV_UDC /* ChipIdea CI13xxx UDC */
+#define CONFIG_CI_UDC /* ChipIdea CI13xxx UDC */
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_ETHER
* Clock Configuration
*/
#undef CONFIG_SYS_CLKS_IN_HZ
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */
/*
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-/* Zynq Serial driver */
-#ifdef CONFIG_ZYNQ_SERIAL_UART0
-# define CONFIG_ZYNQ_SERIAL_BASEADDR0 0xE0000000
-# define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE
-# define CONFIG_ZYNQ_SERIAL_CLOCK0 50000000
-#endif
-
-#ifdef CONFIG_ZYNQ_SERIAL_UART1
-# define CONFIG_ZYNQ_SERIAL_BASEADDR1 0xE0001000
-# define CONFIG_ZYNQ_SERIAL_BAUDRATE1 CONFIG_BAUDRATE
-# define CONFIG_ZYNQ_SERIAL_CLOCK1 50000000
-#endif
-
-#if defined(CONFIG_ZYNQ_SERIAL_UART0) || defined(CONFIG_ZYNQ_SERIAL_UART1)
-# define CONFIG_ZYNQ_SERIAL
-#endif
-
/* DCC driver */
#if defined(CONFIG_ZYNQ_DCC)
# define CONFIG_ARM_DCC
# define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */
+#else
+# define CONFIG_ZYNQ_SERIAL
#endif
/* Ethernet driver */
# define CONFIG_DOS_PARTITION
#endif
+#define CONFIG_SYS_I2C_ZYNQ
/* I2C */
-#if defined(CONFIG_ZYNQ_I2C0) || defined(CONFIG_ZYNQ_I2C1)
+#if defined(CONFIG_SYS_I2C_ZYNQ)
# define CONFIG_CMD_I2C
# define CONFIG_SYS_I2C
-# define CONFIG_SYS_I2C_ZYNQ
# define CONFIG_SYS_I2C_ZYNQ_SPEED 100000
-# define CONFIG_SYS_I2C_ZYNQ_SLAVE 1
+# define CONFIG_SYS_I2C_ZYNQ_SLAVE 0
#endif
/* EEPROM */
"fatload mmc 0 ${load_addr} ${fit_image} && " \
"bootm ${load_addr}\0" \
"jtagboot=echo TFTPing FIT to RAM... && " \
- "tftp ${load_addr} ${fit_image} && " \
+ "tftpboot ${load_addr} ${fit_image} && " \
"bootm ${load_addr}\0"
#define CONFIG_BOOTCOMMAND "run $modeboot"
#define CONFIG_BOOTDELAY 3 /* -1 to Disable autoboot */
#define CONFIG_AUTO_COMPLETE
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_SYS_LONGHELP
+#define CONFIG_CLOCKS
+#define CONFIG_CMD_CLK
#define CONFIG_SYS_MAXARGS 15 /* max number of command args */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
#define CONFIG_FIT_SIGNATURE
#define CONFIG_RSA
+/* Extend size of kernel image for uncompression */
+#define CONFIG_SYS_BOOTM_LEN (20 * 1024 * 1024)
+
/* Boot FreeBSD/vxWorks from an ELF image */
#if defined(CONFIG_ZYNQ_BOOT_FREEBSD)
# define CONFIG_API
# define CONFIG_SYS_MMC_MAX_DEVICE 1
#endif
+#define CONFIG_SYS_LDSCRIPT "arch/arm/cpu/armv7/zynq/u-boot.lds"
+
/* Commands */
#include <config_cmd_default.h>
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
+#define CONFIG_CMD_TFTPPUT
+
+/* SPL part */
+#define CONFIG_SPL
+#define CONFIG_CMD_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/zynq/u-boot-spl.lds"
+
+/* Disable dcache for SPL just for sure */
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_DCACHE_OFF
+#undef CONFIG_FPGA
+#endif
+
+/* MMC support */
+#ifdef CONFIG_ZYNQ_SDHCI0
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
+#endif
+
+/* Address in RAM where the parameters must be copied by SPL. */
+#define CONFIG_SYS_SPL_ARGS_ADDR 0x10000000
+
+#define CONFIG_SPL_FAT_LOAD_ARGS_NAME "system.dtb"
+#define CONFIG_SPL_FAT_LOAD_KERNEL_NAME "uImage"
+
+/* Not using MMC raw mode - just for compilation purpose */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0
+
+/* qspi mode is working fine */
+#ifdef CONFIG_ZYNQ_QSPI
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x100000
+#define CONFIG_SPL_SPI_CS 0
+#endif
+
+/* for booting directly linux */
+#define CONFIG_SPL_OS_BOOT
+
+/* SP location before relocation, must use scratch RAM */
+#define CONFIG_SPL_TEXT_BASE 0x0
+
+/* 3 * 64kB blocks of OCM - one is on the top because of bootrom */
+#define CONFIG_SPL_MAX_SIZE 0x30000
+
+/* The highest 64k OCM address */
+#define OCM_HIGH_ADDR 0xffff0000
+
+/* Just define any reasonable size */
+#define CONFIG_SPL_STACK_SIZE 0x1000
+
+/* SPL stack position - and stack goes down */
+#define CONFIG_SPL_STACK (OCM_HIGH_ADDR + CONFIG_SPL_STACK_SIZE)
+
+/* On the top of OCM space */
+#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_STACK + \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x1000
+
+/* BSS setup */
+#define CONFIG_SPL_BSS_START_ADDR 0x100000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x100000
+
+#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
#endif /* __CONFIG_ZYNQ_COMMON_H */
* (C) Copyright 2013 Xilinx, Inc.
*
* Configuration settings for the Xilinx Zynq ZC702 and ZC706 boards
- * See zynq_common.h for Zynq common configs
+ * See zynq-common.h for Zynq common configs
*
* SPDX-License-Identifier: GPL-2.0+
*/
* (C) Copyright 2013 Xilinx, Inc.
*
* Configuration for Zynq Evaluation and Development Board - ZedBoard
- * See zynq_common.h for Zynq common configs
+ * See zynq-common.h for Zynq common configs
*
* SPDX-License-Identifier: GPL-2.0+
*/
struct cpsw_slave_data {
u32 slave_reg_ofs;
u32 sliver_reg_ofs;
- int phy_id;
+ int phy_addr;
int phy_if;
};
void (*clksel)(struct dwmci_host *host);
void (*board_init)(struct dwmci_host *host);
- unsigned int (*get_mmc_clk)(int dev_index);
+ unsigned int (*get_mmc_clk)(struct dwmci_host *host);
};
struct dwmci_idmac {
int ext4fs_mount(unsigned part_length);
void ext4fs_close(void);
int ext4fs_ls(const char *dirname);
+int ext4fs_exists(const char *filename);
void ext4fs_free_node(struct ext2fs_node *node, struct ext2fs_node *currroot);
int ext4fs_devread(lbaint_t sector, int byte_offset, int byte_len, char *buf);
void ext4fs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info);
int file_cd(const char *path);
int file_fat_detectfs(void);
int file_fat_ls(const char *dir);
+int fat_exists(const char *filename);
long file_fat_read_at(const char *filename, unsigned long pos, void *buffer,
unsigned long maxsize);
long file_fat_read(const char *filename, void *buffer, unsigned long maxsize);
COMPAT_NVIDIA_TEGRA20_NAND, /* Tegra2 NAND controller */
COMPAT_NVIDIA_TEGRA20_PWM, /* Tegra 2 PWM controller */
COMPAT_NVIDIA_TEGRA20_DC, /* Tegra 2 Display controller */
+ COMPAT_NVIDIA_TEGRA124_SDMMC, /* Tegra124 SDMMC controller */
COMPAT_NVIDIA_TEGRA30_SDMMC, /* Tegra30 SDMMC controller */
COMPAT_NVIDIA_TEGRA20_SDMMC, /* Tegra20 SDMMC controller */
COMPAT_NVIDIA_TEGRA20_SFLASH, /* Tegra 2 SPI flash controller */
*/
int fs_ls(const char *dirname);
+/*
+ * Determine whether a file exists
+ *
+ * Returns 1 if the file exists, 0 if it doesn't exist.
+ */
+int fs_exists(const char *filename);
+
/*
* Read file "filename" from the partition previously set by fs_set_blk_dev(),
* to address "addr", starting at byte offset "offset", and reading "len"
*/
int fs_read(const char *filename, ulong addr, int offset, int len);
+/*
+ * Write file "filename" to the partition previously set by fs_set_blk_dev(),
+ * from address "addr", starting at byte offset "offset", and writing "len"
+ * bytes. "offset" may be 0 to write to the start of the file. Note that not
+ * all filesystem types support offset!=0.
+ *
+ * Returns number of bytes read on success. Returns <= 0 on error.
+ */
+int fs_write(const char *filename, ulong addr, int offset, int len);
+
/*
* Common implementation for various filesystem commands, optionally limited
* to a specific filesystem type via the fstype parameter.
int fstype);
int do_ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
int fstype);
+int file_exists(const char *dev_type, const char *dev_part, const char *file,
+ int fstype);
int do_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
int fstype);
#include <common_timing_params.h>
+#ifdef CONFIG_SYS_FSL_DDR_LE
+#define ddr_in32(a) in_le32(a)
+#define ddr_out32(a, v) out_le32(a, v)
+#else
+#define ddr_in32(a) in_be32(a)
+#define ddr_out32(a, v) out_be32(a, v)
+#endif
+
#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
/*
* Bind the main DDR setup driver's generic names
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr);
+void board_add_ram_info(int use_default);
/* processor specific function */
void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
#define FSL_DDR_PAGE_INTERLEAVING 0x1
#define FSL_DDR_BANK_INTERLEAVING 0x2
#define FSL_DDR_SUPERBANK_INTERLEAVING 0x3
+#define FSL_DDR_256B_INTERLEAVING 0x8
#define FSL_DDR_3WAY_1KB_INTERLEAVING 0xA
#define FSL_DDR_3WAY_4KB_INTERLEAVING 0xC
#define FSL_DDR_3WAY_8KB_INTERLEAVING 0xD
#include <config.h>
#include <common.h>
+
+#ifdef CONFIG_SYS_FSL_IFC_LE
+#define ifc_in32(a) in_le32(a)
+#define ifc_out32(a, v) out_le32(a, v)
+#define ifc_in16(a) in_le16(a)
+#elif defined(CONFIG_SYS_FSL_IFC_BE)
+#define ifc_in32(a) in_be32(a)
+#define ifc_out32(a, v) out_be32(a, v)
+#define ifc_in16(a) in_be16(a)
+#else
+#error Neither CONFIG_SYS_FSL_IFC_LE nor CONFIG_SYS_FSL_IFC_BE is defined
+#endif
+
+
/*
* CSPR - Chip Select Property Register
*/
#define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR)
-#define get_ifc_cspr_ext(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext))
-#define get_ifc_cspr(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr))
-#define get_ifc_csor_ext(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext))
-#define get_ifc_csor(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor))
-#define get_ifc_amask(i) (in_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask))
-#define get_ifc_ftim(i, j) (in_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j]))
-
-#define set_ifc_cspr_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v))
-#define set_ifc_cspr(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v))
-#define set_ifc_csor_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v))
-#define set_ifc_csor(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v))
-#define set_ifc_amask(i, v) (out_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v))
+#define get_ifc_cspr_ext(i) (ifc_in32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext))
+#define get_ifc_cspr(i) (ifc_in32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr))
+#define get_ifc_csor_ext(i) (ifc_in32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext))
+#define get_ifc_csor(i) (ifc_in32(&(IFC_BASE_ADDR)->csor_cs[i].csor))
+#define get_ifc_amask(i) (ifc_in32(&(IFC_BASE_ADDR)->amask_cs[i].amask))
+#define get_ifc_ftim(i, j) (ifc_in32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j]))
+
+#define set_ifc_cspr_ext(i, v) \
+ (ifc_out32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v))
+#define set_ifc_cspr(i, v) (ifc_out32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v))
+#define set_ifc_csor_ext(i, v) \
+ (ifc_out32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v))
+#define set_ifc_csor(i, v) (ifc_out32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v))
+#define set_ifc_amask(i, v) (ifc_out32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v))
#define set_ifc_ftim(i, j, v) \
- (out_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v))
+ (ifc_out32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v))
enum ifc_chip_sel {
IFC_CS0,
uint (*set_bus_speed)(struct i2c_adapter *adap,
uint speed);
int speed;
+ int waitdelay;
int slaveaddr;
int init_done;
int hwadapnr;
#endif
#ifdef CONFIG_OF_BOARD_SETUP
-# define IMAAGE_OF_BOARD_SETUP 1
+# define IMAGE_OF_BOARD_SETUP 1
#else
-# define IMAAGE_OF_BOARD_SETUP 0
+# define IMAGE_OF_BOARD_SETUP 0
#endif
/*
#define IH_ARCH_NDS32 20 /* ANDES Technology - NDS32 */
#define IH_ARCH_OPENRISC 21 /* OpenRISC 1000 */
#define IH_ARCH_ARM64 22 /* ARM64 */
+#define IH_ARCH_ARC 23 /* Synopsys DesignWare ARC */
/*
* Image Types
unsigned int logo_on;
unsigned int logo_width;
unsigned int logo_height;
+ int logo_x_offset;
+ int logo_y_offset;
unsigned long logo_addr;
unsigned int rgb_mode;
unsigned int resolution;
* SPDX-License-Identifier: GPL-2.0+
*/
+#ifndef __LINKER_LISTS_H__
+#define __LINKER_LISTS_H__
+
/*
* There is no use in including this from ASM files, but that happens
* anyway, e.g. PPC kgdb.S includes command.h which incluse us.
* %u_boot_list_2_drivers_3
*/
-#ifndef __LINKER_LISTS_H__
-#define __LINKER_LISTS_H__
-
/**
* ll_entry_declare() - Declare linker-generated array entry
* @_type: Data type of the entry
#define EXT_CSD_BOOT_PART_NUM(x) (x << 3)
#define EXT_CSD_PARTITION_ACCESS(x) (x << 0)
+#define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3)
+#define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
+#define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
#define R1_ILLEGAL_COMMAND (1 << 22)
#define R1_APP_CMD (1 << 5)
/* Function to change the size of boot partition and rpmb partitions */
int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
unsigned long rpmbsize);
-/* Function to send commands to open/close the specified boot partition */
-int mmc_boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
+/* Function to modify the PARTITION_CONFIG field of EXT_CSD */
+int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
+/* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
+int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
/**
* Start device initialization and return immediately; it does not block on
int cs8900_initialize(u8 dev_num, int base_addr);
int davinci_emac_initialize(void);
int dc21x4x_initialize(bd_t *bis);
-int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface);
+int designware_initialize(ulong base_addr, u32 interface);
int dm9000_initialize(bd_t *bis);
int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr);
int e1000_initialize(bd_t *bis);
#ifndef __MAX77686_H_
#define __MAX77686_H_
+#include <power/pmic.h>
+
enum {
MAX77686_REG_PMIC_ID = 0x0,
MAX77686_REG_PMIC_INTSRC,
#ifndef __CORE_PMIC_H_
#define __CORE_PMIC_H_
-#include <common.h>
#include <linux/list.h>
#include <i2c.h>
#include <power/power_chrg.h>
--- /dev/null
+#ifndef __SAMSUNG_MISC_COMMON_H__
+#define __SAMSUNG_MISC_COMMON_H__
+
+#ifdef CONFIG_REVISION_TAG
+u32 get_board_rev(void);
+#endif
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+void set_board_info(void);
+#endif
+
+#ifdef CONFIG_LCD_MENU
+enum {
+ BOOT_MODE_INFO,
+ BOOT_MODE_THOR,
+ BOOT_MODE_UMS,
+ BOOT_MODE_DFU,
+ BOOT_MODE_EXIT,
+};
+
+void keys_init(void);
+void check_boot_mode(void);
+#endif /* CONFIG_LCD_MENU */
+
+#ifdef CONFIG_CMD_BMP
+void draw_logo(void);
+#endif
+
+#endif /* __SAMSUNG_MISC_COMMON_H__ */
void sandbox_fs_close(void);
int sandbox_fs_ls(const char *dirname);
+int sandbox_fs_exists(const char *filename);
int fs_read_sandbox(const char *filename, void *buf, int offset, int len);
int fs_write_sandbox(const char *filename, void *buf, int offset, int len);
#define MMCSD_MODE_UNDEFINED 0
#define MMCSD_MODE_RAW 1
#define MMCSD_MODE_FAT 2
+#define MMCSD_MODE_EMMCBOOT 3
struct spl_image_info {
const char *name;
/* USB SPL functions */
void spl_usb_load_image(void);
+/* SATA SPL functions */
+void spl_sata_load_image(void);
+
/* SPL FAT image functions */
int spl_load_image_fat(block_dev_desc_t *block_dev, int partition, const char *filename);
int spl_load_image_fat_os(block_dev_desc_t *block_dev, int partition);
*/
-#ifndef __MV_UDC_H__
-#define __MV_UDC_H__
+#ifndef __CI_UDC_H__
+#define __CI_UDC_H__
#define EP_MAX_PACKET_SIZE 0x200
#define EP0_MAX_PACKET_SIZE 64
-#endif /* __MV_UDC_H__ */
+#endif /* __CI_UDC_H__ */
#define __S3C_USB_GADGET
#include <asm/errno.h>
+#include <asm/sizes.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <linux/list.h>
/*-------------------------------------------------------------------------*/
/* DMA bounce buffer size, 16K is enough even for mass storage */
-#define DMA_BUFFER_SIZE (4096*4)
+#define DMA_BUFFER_SIZE (16*SZ_1K)
#define EP0_FIFO_SIZE 64
#define EP_FIFO_SIZE 512
struct s3c_plat_otg_data *pdata;
- void *dma_buf[S3C_MAX_ENDPOINTS+1];
- dma_addr_t dma_addr[S3C_MAX_ENDPOINTS+1];
-
int ep0state;
struct s3c_ep ep[S3C_MAX_ENDPOINTS];
extern int zynq_info(Xilinx_desc *desc);
#define XILINX_ZYNQ_7010 0x2
+#define XILINX_ZYNQ_7015 0x1b
#define XILINX_ZYNQ_7020 0x7
#define XILINX_ZYNQ_7030 0xc
#define XILINX_ZYNQ_7045 0x11
/* Device Image Sizes */
#define XILINX_XC7Z010_SIZE 16669920/8
+#define XILINX_XC7Z015_SIZE 28085344/8
#define XILINX_XC7Z020_SIZE 32364512/8
#define XILINX_XC7Z030_SIZE 47839328/8
#define XILINX_XC7Z045_SIZE 106571232/8
#define XILINX_XC7Z010_DESC(cookie) \
{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, "7z010" }
+#define XILINX_XC7Z015_DESC(cookie) \
+{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, "7z015" }
+
#define XILINX_XC7Z020_DESC(cookie) \
{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, "7z020" }
obj-$(CONFIG_RANDOM_MACADDR) += rand.o
obj-$(CONFIG_BOOTP_RANDOM_DELAY) += rand.o
obj-$(CONFIG_CMD_LINK_LOCAL) += rand.o
-
-# SEE README.arm-unaligned-accesses
-$(obj)bzlib.o: CFLAGS += $(PLATFORM_NO_UNALIGNED)
COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),
COMPAT(NVIDIA_TEGRA20_PWM, "nvidia,tegra20-pwm"),
COMPAT(NVIDIA_TEGRA20_DC, "nvidia,tegra20-dc"),
+ COMPAT(NVIDIA_TEGRA124_SDMMC, "nvidia,tegra124-sdhci"),
COMPAT(NVIDIA_TEGRA30_SDMMC, "nvidia,tegra30-sdhci"),
COMPAT(NVIDIA_TEGRA20_SDMMC, "nvidia,tegra20-sdhci"),
COMPAT(NVIDIA_TEGRA20_SFLASH, "nvidia,tegra20-sflash"),
# SPDX-License-Identifier: GPL-2.0+
#
-CFLAGS += -D_LZMA_PROB32
+ccflags-y += -D_LZMA_PROB32
obj-y += LzmaDec.o LzmaTools.o
#include <lcd.h>
#include <libtizen.h>
-#include "tizen_hd_logo.h"
-#include "tizen_hd_logo_data.h"
+#include "tizen_logo_16bpp.h"
+#include "tizen_logo_16bpp_gzip.h"
void get_tizen_logo_info(vidinfo_t *vid)
{
- switch (vid->resolution) {
- case HD_RESOLUTION:
- vid->logo_width = TIZEN_HD_LOGO_WIDTH;
- vid->logo_height = TIZEN_HD_LOGO_HEIGHT;
- vid->logo_addr = (ulong)tizen_hd_logo;
+ switch (vid->vl_bpix) {
+ case 4:
+ vid->logo_width = TIZEN_LOGO_16BPP_WIDTH;
+ vid->logo_height = TIZEN_LOGO_16BPP_HEIGHT;
+ vid->logo_x_offset = TIZEN_LOGO_16BPP_X_OFFSET;
+ vid->logo_y_offset = TIZEN_LOGO_16BPP_Y_OFFSET;
+#if defined(CONFIG_VIDEO_BMP_GZIP)
+ vid->logo_addr = (ulong)tizen_logo_16bpp_gzip;
+#else
+ vid->logo_addr = (ulong)tizen_logo_16bpp;
+#endif
break;
default:
+ vid->logo_addr = 0;
break;
}
}
+++ /dev/null
-/*
- * (C) Copyright 2012 Samsung Electronics
- * Donghwa Lee <dh09.lee@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _TIZEN_HD_LOGO_H_
-#define _TIZEN_HD_LOGO_H_
-
-unsigned char tizen_hd_logo[]={
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-};
-
-#endif /* _TIZEN_HD_LOGO_H_ */
+++ /dev/null
-/*
- * (C) Copyright 2012 Samsung Electronics
- * Donghwa Lee <dh09.lee@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _TIZEN_HD_LOGO_DATA_H_
-#define _TIZEN_HD_LOGO_DATA_H_
-
-#define TIZEN_HD_LOGO_WIDTH 520
-#define TIZEN_HD_LOGO_HEIGHT 120
-#define TIZEN_HD_LOGO_BPP 32
-
-#endif /* _TIZEN_HD_LOGO_DATA_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2013 Samsung Electronics
+ * Przemyslaw Marczak <p.marczak@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+*/
+
+#ifndef __TIZEN_LOGO_16BPP__
+#define __TIZEN_LOGO_16BPP__
+
+#define TIZEN_LOGO_16BPP_WIDTH 500
+#define TIZEN_LOGO_16BPP_HEIGHT 160
+
+/* Center align offsets for word "TIZEN" */
+#define TIZEN_LOGO_16BPP_X_OFFSET (30)
+#define TIZEN_LOGO_16BPP_Y_OFFSET (-26)
+
+/* Format: BMP RGB565 16BPP 500x160 */
+unsigned char tizen_logo_16bpp[] = {
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+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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+0x00,0x00,0x00,0x00,0x00,0x00};
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2013 Samsung Electronics
+ * Przemyslaw Marczak <p.marczak@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+*/
+
+#ifndef __TIZEN_LOGO_16BPP_GZIP__
+#define __TIZEN_LOGO_16BPP_GZIP__
+
+/* Format: GZIP: BMP RGB565 16BPP 500x160 */
+unsigned char tizen_logo_16bpp_gzip[] = {
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+0x4c,0x6f,0x63,0x6b,0x75,0x70,0x2d,0x4f,0x6e,0x2d,0x44,0x61,0x72,0x6b,0x2d,0x52,
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+0xeb,0xb2,0xa7,0x5a,0x1e,0x6f,0x19,0xcb,0xc4,0x75,0x16,0xa3,0xcf,0x5c,0x3c,0x71,
+0xca,0xfa,0x33,0x44,0xfa,0xc5,0x74,0x8f,0x7e,0x24,0x43,0xba,0xc8,0xf9,0x0b,0xa8,
+0x37,0x7f,0xd4,0xf1,0x07,0x56,0xea,0xb7,0x53,0x51,0x55,0x93,0x8e,0x3a,0x17,0x67,
+0x27,0x85,0xa8,0xcd,0x2f,0x27,0x4e,0xb5,0x9e,0xb2,0x3e,0x6c,0xdb,0x6a,0xfd,0xb7,
+0xf4,0xef,0xf6,0x09,0x9c,0x8b,0xf7,0x34,0xb0,0xc2,0xb3,0xe0,0x12,0x77,0xdd,0xf7,
+0x3d,0xf4,0x9a,0x97,0x6c,0xef,0x08,0x9c,0xcb,0x7b,0xf4,0x07,0x76,0x98,0xd1,0xff,
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+0xb7,0x04,0x98,0xec,0xfd,0x6a,0xe2,0x89,0xf3,0x8f,0x97,0x1b,0x9b,0x7e,0x60,0x1d,
+0x40,0x9c,0x67,0x3d,0x77,0x20,0x9d,0xb5,0xc3,0x0a,0xfd,0xa2,0x95,0xde,0x8f,0x4c,
+0x45,0x55,0x8d,0x7a,0xb5,0xe7,0x54,0x2c,0x92,0xea,0xbc,0x04,0x71,0xa4,0x3a,0x50,
+0x4f,0x7d,0xd1,0x06,0x31,0x67,0xbe,0x68,0xfd,0x8a,0xe5,0xee,0x13,0x6b,0xf2,0xcd,
+0xec,0x69,0xda,0x3b,0x2f,0xfd,0x66,0xd3,0x47,0xd6,0x97,0x72,0xe6,0xe2,0x58,0xfb,
+0x1e,0xc7,0x33,0xf6,0xef,0xd0,0xbb,0x91,0xa9,0xa8,0xaa,0x54,0xc7,0x5b,0xc2,0x91,
+0x26,0xe4,0xb3,0xbf,0x8d,0xfa,0x72,0xf0,0xc7,0x81,0x5f,0xb8,0x31,0xed,0x5f,0xac,
+0x33,0x5f,0x81,0x79,0xb8,0x65,0xd1,0x6b,0x4f,0xaf,0xbd,0xb1,0xa9,0x48,0xb2,0xf3,
+0xd2,0x4b,0x4d,0x87,0x05,0xcf,0xfd,0x51,0xc4,0xf9,0x25,0x7b,0xc2,0xce,0x6e,0x3e,
+0xd4,0xf0,0x2c,0xf5,0xd7,0xa9,0xa8,0xaa,0x56,0x47,0x5d,0x8b,0xf3,0x8f,0x5c,0x6a,
+0x6c,0x78,0xd8,0x36,0x27,0x78,0xe3,0xd2,0xb8,0xfb,0x3d,0xfb,0x75,0xdb,0x77,0xbf,
+0xbd,0x65,0x66,0x71,0x76,0x6b,0xf0,0x50,0x88,0x09,0x27,0x23,0x60,0xed,0xd1,0x53,
+0xcc,0x29,0xe6,0xed,0xd7,0x7e,0xdb,0xf6,0x4e,0xc3,0x67,0x0d,0x47,0x36,0xa3,0xde,
+0x7c,0xf3,0x6f,0x9b,0x42,0x8f,0x1c,0xa3,0xe7,0xd6,0xa8,0xa8,0xaa,0x5a,0x57,0x47,
+0x3a,0x0e,0x3d,0x93,0x99,0x5b,0x13,0x29,0x87,0x3d,0xad,0x9d,0xf6,0xaf,0xd5,0x59,
+0x9c,0x53,0xce,0x29,0xd7,0x65,0xd7,0x8d,0x46,0x9b,0x77,0x5f,0xcb,0x8b,0xbb,0x6e,
+0x76,0x38,0xf7,0x0e,0xf5,0xbc,0x3f,0xd0,0xf0,0xed,0x83,0x9d,0x1f,0x3e,0xf5,0xe5,
+0xd6,0xc5,0xaf,0x7e,0xe7,0x91,0x7b,0xf4,0x34,0x0b,0x15,0x55,0xd5,0xeb,0x4a,0xcf,
+0xa9,0xa6,0xf1,0xf4,0x78,0xdb,0x97,0xa6,0x1c,0x4e,0xad,0x1e,0xb6,0xff,0xab,0xfa,
+0x1f,0x39,0xff,0xb3,0xab,0xcb,0x09,0x66,0x5e,0x3a,0xa9,0xa8,0xa8,0x8c,0xeb,0x87,
+0xbb,0xfa,0x1a,0x24,0x7f,0x7d,0x77,0x66,0x4d,0x3c,0x85,0x38,0x47,0xfd,0x39,0x3d,
+0x95,0x42,0x45,0xb5,0x21,0xf4,0xa6,0xeb,0x7b,0xdb,0x76,0xdb,0x3f,0xb3,0x49,0x3d,
+0xb9,0xb8,0x22,0xbe,0xc3,0x31,0x4e,0x39,0xa7,0xa2,0xda,0x40,0x3a,0xfb,0x8d,0x23,
+0x9b,0x77,0xe7,0x50,0x0e,0x2b,0x65,0x13,0x94,0x73,0x2a,0xaa,0x0d,0xa4,0x17,0xbd,
+0xbf,0x6d,0x7a,0x2f,0xed,0xaf,0x4b,0xfb,0xd5,0xf7,0x38,0xe6,0x29,0xe7,0x54,0x54,
+0x1b,0x4a,0xc3,0x5f,0x09,0x6e,0x4e,0xc8,0x28,0x87,0x5d,0xac,0xef,0x52,0xce,0xa9,
+0xa8,0x36,0x98,0x66,0xbe,0x34,0xfe,0xe5,0x1d,0x0e,0x36,0x73,0x26,0x05,0x4e,0x93,
+0x3f,0x4b,0x39,0xa7,0xa2,0xda,0x58,0x72,0xfe,0xd3,0x17,0xdf,0xb6,0xed,0x71,0xec,
+0x70,0x48,0x27,0x4c,0x29,0xe7,0x54,0x54,0x1b,0x51,0xf7,0x2c,0x3f,0xb5,0xee,0x40,
+0x3d,0xf9,0x1e,0xc4,0xf9,0x7b,0x8e,0xcf,0x04,0xce,0x69,0x6c,0x47,0x2a,0xaa,0x8d,
+0x26,0xaf,0x25,0x54,0x7f,0xd1,0x9e,0x10,0x22,0xc3,0x34,0x39,0x28,0xe7,0x54,0x54,
+0x1b,0x55,0x7f,0x59,0x77,0xc7,0x96,0x70,0xbc,0xf0,0xd0,0xf3,0x8e,0x17,0x29,0xe7,
+0x54,0x54,0x1b,0x56,0xdf,0xb7,0xfc,0xc4,0xfa,0x9e,0x63,0xb7,0x83,0x8e,0xcf,0xa9,
+0xa8,0x36,0xb6,0x42,0xf5,0x3f,0xb1,0xde,0x30,0x9c,0x88,0xff,0x0f,0xa8,0x0b,0x24,
+0x15,0x46,0x71,0x02,0x00};
+#endif
if [ \( $# -eq 2 \) -a \( "$1" = "-A" \) ] ; then
# Automatic mode
- line=`awk '($0 !~ /^#/ && $7 ~ /^'"$2"'$/) { print $1, $2, $3, $4, $5, $6, $7, $8 }' boards.cfg`
+ line=`awk '($0 !~ /^#/ && $7 ~ /^'"$2"'$/) { print $1, $2, $3, $4, $5, $6, $7, $8 }' $srctree/boards.cfg`
if [ -z "$line" ] ; then
echo "make: *** No rule to make target \`$2_config'. Stop." >&2
exit 1
# SPDX-License-Identifier: GPL-2.0+
#
-include $(TOPDIR)/config.mk
include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
$(LDFLAGS_FINAL)
-AFLAGS += -DCONFIG_NAND_SPL
-CFLAGS += -DCONFIG_NAND_SPL
+asflags-y += -DCONFIG_NAND_SPL
+ccflags-y += -DCONFIG_NAND_SPL
SOBJS = start.o resetvec.o cache.o
COBJS = gpio.o nand_boot.o nand_ecc.o memory.o ndfc.o pll.o
-SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(nandobj)board/$(BOARDDIR)
+targets += $(__OBJS)
+
all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin \
$(nandobj)System.map
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+ $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+ $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
sort > $@
$(nandobj)u-boot.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+ $(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
# create symbolic links for common files
# from cpu directory
-$(obj)cache.S:
+$(obj)/cache.S:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/cache.S $@
-$(obj)gpio.c:
+$(obj)/gpio.c:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/gpio.c $@
-$(obj)ndfc.c:
+$(obj)/ndfc.c:
@rm -f $@
ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@
-$(obj)resetvec.S:
+$(obj)/resetvec.S:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@
-$(obj)start.S:
+$(obj)/start.S:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@
# from board directory
-$(obj)memory.c:
+$(obj)/memory.c:
@rm -f $@
ln -s $(SRCTREE)/board/amcc/acadia/memory.c $@
-$(obj)pll.c:
+$(obj)/pll.c:
@rm -f $@
ln -s $(SRCTREE)/board/amcc/acadia/pll.c $@
# from nand_spl directory
-$(obj)nand_boot.c:
+$(obj)/nand_boot.c:
@rm -f $@
ln -s $(SRCTREE)/nand_spl/nand_boot.c $@
# from drivers/mtd/nand directory
-$(obj)nand_ecc.c:
+$(obj)/nand_ecc.c:
@rm -f $@
ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@
-
-#########################################################################
-
-$(obj)%.o: $(obj)%.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(obj)%.c
- $(CC) $(CFLAGS) -c -o $@ $<
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
# SPDX-License-Identifier: GPL-2.0+
#
-include $(TOPDIR)/config.mk
include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
$(LDFLAGS_FINAL)
-AFLAGS += -DCONFIG_NAND_SPL
-CFLAGS += -DCONFIG_NAND_SPL
+asflags-y += -DCONFIG_NAND_SPL
+ccflags-y += -DCONFIG_NAND_SPL
SOBJS = start.o init.o resetvec.o
COBJS = nand_boot.o nand_ecc.o ndfc.o sdram.o
-SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(nandobj)board/$(BOARDDIR)
+targets += $(__OBJS)
+
all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+ $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+ $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-Map $(nandobj)u-boot-spl.map -o $@
$(nandobj)u-boot.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+ $(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
# create symbolic links for common files
# from cpu directory
-$(obj)ndfc.c:
+$(obj)/ndfc.c:
@rm -f $@
ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@
-$(obj)resetvec.S:
+$(obj)/resetvec.S:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@
-$(obj)start.S:
+$(obj)/start.S:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@
# from board directory
-$(obj)init.S:
+$(obj)/init.S:
@rm -f $@
ln -s $(SRCTREE)/board/amcc/bamboo/init.S $@
# from nand_spl directory
-$(obj)nand_boot.c:
+$(obj)/nand_boot.c:
@rm -f $@
ln -s $(SRCTREE)/nand_spl/nand_boot.c $@
# from drivers/mtd/nand directory
-$(obj)nand_ecc.c:
+$(obj)/nand_ecc.c:
@rm -f $@
ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@
-
-ifneq ($(OBJTREE), $(SRCTREE))
-$(obj)sdram.c:
- @rm -f $@
- ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/sdram.c $@
-endif
-
-#########################################################################
-
-$(obj)%.o: $(obj)%.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(obj)%.c
- $(CC) $(CFLAGS) -c -o $@ $<
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
# SPDX-License-Identifier: GPL-2.0+
#
-include $(TOPDIR)/config.mk
include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
$(LDFLAGS_FINAL)
-AFLAGS += -DCONFIG_NAND_SPL
-CFLAGS += -DCONFIG_NAND_SPL
+asflags-y += -DCONFIG_NAND_SPL
+ccflags-y += -DCONFIG_NAND_SPL
SOBJS := start.o
SOBJS += init.o
COBJS += nand_ecc.o
COBJS += ndfc.o
-SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(nandobj)board/$(BOARDDIR)
+targets += $(__OBJS)
+
all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+ $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+ $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-Map $(nandobj)u-boot-spl.map -o $@
$(nandobj)u-boot.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+ $(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
# create symbolic links for common files
# from cpu directory
-$(obj)ndfc.c:
+$(obj)/ndfc.c:
@rm -f $@
ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@
-$(obj)resetvec.S:
+$(obj)/resetvec.S:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@
-$(obj)start.S:
+$(obj)/start.S:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@
# from board directory
-$(obj)init.S:
+$(obj)/init.S:
@rm -f $@
ln -s $(SRCTREE)/board/amcc/canyonlands/init.S $@
# from nand_spl directory
-$(obj)nand_boot.c:
+$(obj)/nand_boot.c:
@rm -f $@
ln -s $(SRCTREE)/nand_spl/nand_boot.c $@
# from drivers/mtd/nand directory
-$(obj)nand_ecc.c:
+$(obj)/nand_ecc.c:
@rm -f $@
ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@
-
-ifneq ($(OBJTREE), $(SRCTREE))
-$(obj)ddr2_fixed.c:
- @rm -f $@
- ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/ddr2_fixed.c $@
-endif
-
-#########################################################################
-
-$(obj)%.o: $(obj)%.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(obj)%.c
- $(CC) $(CFLAGS) -c -o $@ $<
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
# SPDX-License-Identifier: GPL-2.0+
#
-include $(TOPDIR)/config.mk
include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
$(LDFLAGS_FINAL)
-AFLAGS += -DCONFIG_NAND_SPL
-CFLAGS += -DCONFIG_NAND_SPL
+asflags-y += -DCONFIG_NAND_SPL
+ccflags-y += -DCONFIG_NAND_SPL
SOBJS = start.o resetvec.o cache.o
COBJS = 44x_spd_ddr2.o nand_boot.o nand_ecc.o ndfc.o
-SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(nandobj)board/$(BOARDDIR)
+targets += $(__OBJS)
+
all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+ $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+ $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-Map $(nandobj)u-boot-spl.map -o $@
$(nandobj)u-boot.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+ $(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
# create symbolic links for common files
# from cpu directory
-$(obj)44x_spd_ddr2.c: $(obj)ecc.h
+$(obj)/44x_spd_ddr2.c: $(obj)/ecc.h
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c $@
-$(obj)cache.S:
+$(obj)/cache.S:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/cache.S $@
-$(obj)ecc.h:
+$(obj)/ecc.h:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/ecc.h $@
-$(obj)ndfc.c:
+$(obj)/ndfc.c:
@rm -f $@
ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@
-$(obj)resetvec.S:
+$(obj)/resetvec.S:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@
-$(obj)start.S:
+$(obj)/start.S:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@
# from nand_spl directory
-$(obj)nand_boot.c:
+$(obj)/nand_boot.c:
@rm -f $@
ln -s $(SRCTREE)/nand_spl/nand_boot.c $@
# from drivers/nand directory
-$(obj)nand_ecc.c:
+$(obj)/nand_ecc.c:
@rm -f $@
ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@
-
-#########################################################################
-
-$(obj)%.o: $(obj)%.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(obj)%.c
- $(CC) $(CFLAGS) -c -o $@ $<
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
# SPDX-License-Identifier: GPL-2.0+
#
-include $(TOPDIR)/config.mk
include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
$(LDFLAGS_FINAL)
-AFLAGS += -DCONFIG_NAND_SPL
-CFLAGS += -DCONFIG_NAND_SPL
+asflags-y += -DCONFIG_NAND_SPL
+ccflags-y += -DCONFIG_NAND_SPL
SOBJS = start.o init.o resetvec.o
COBJS = denali_data_eye.o nand_boot.o nand_ecc.o ndfc.o sdram.o
-SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(nandobj)board/$(BOARDDIR)
+targets += $(__OBJS)
+
all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+ $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+ $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-Map $(nandobj)u-boot-spl.map -o $@
$(nandobj)u-boot.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+ $(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
# create symbolic links for common files
# from cpu directory
-$(obj)denali_data_eye.c:
+$(obj)/denali_data_eye.c:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/denali_data_eye.c $@
-$(obj)ndfc.c:
+$(obj)/ndfc.c:
@rm -f $@
ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@
-$(obj)resetvec.S:
+$(obj)/resetvec.S:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@
-$(obj)start.S:
+$(obj)/start.S:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@
# from board directory
-$(obj)init.S:
+$(obj)/init.S:
@rm -f $@
ln -s $(SRCTREE)/board/amcc/sequoia/init.S $@
-$(obj)sdram.c:
+$(obj)/sdram.c:
@rm -f $@
- @rm -f $(obj)sdram.h
+ @rm -f $(obj)/sdram.h
ln -s $(SRCTREE)/board/amcc/sequoia/sdram.c $@
- ln -s $(SRCTREE)/board/amcc/sequoia/sdram.h $(obj)sdram.h
+ ln -s $(SRCTREE)/board/amcc/sequoia/sdram.h $(obj)/sdram.h
# from nand_spl directory
-$(obj)nand_boot.c:
+$(obj)/nand_boot.c:
@rm -f $@
ln -s $(SRCTREE)/nand_spl/nand_boot.c $@
# from drivers/mtd/nand directory
-$(obj)nand_ecc.c:
+$(obj)/nand_ecc.c:
@rm -f $@
ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@
-
-#########################################################################
-
-$(obj)%.o: $(obj)%.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(obj)%.c
- $(CC) $(CFLAGS) -c -o $@ $<
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
# SPDX-License-Identifier: GPL-2.0+
#
-NAND_SPL := y
PAD_TO := 0xfff04000
-include $(TOPDIR)/config.mk
-
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
$(LDFLAGS) $(LDFLAGS_FINAL)
-AFLAGS += -DCONFIG_NAND_SPL
-CFLAGS += -DCONFIG_NAND_SPL
+asflags-y += -DCONFIG_NAND_SPL
+ccflags-y += -DCONFIG_NAND_SPL
SOBJS = start.o ticks.o
COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o spl_minimal.o \
time.o cache.o
-SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(nandobj)board/$(BOARDDIR)
+targets += $(__OBJS)
+
all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+ $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+ $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-Map $(nandobj)u-boot-spl.map -o $@
$(nandobj)u-boot.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+ $(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
# create symbolic links for common files
-$(obj)start.S:
+$(obj)/start.S:
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc83xx/start.S $@
-$(obj)nand_boot_fsl_elbc.c:
+$(obj)/nand_boot_fsl_elbc.c:
ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@
-$(obj)sdram.c:
+$(obj)/sdram.c:
ln -sf $(SRCTREE)/board/$(BOARDDIR)/sdram.c $@
-$(obj)$(BOARD).c:
+$(obj)/$(BOARD).c:
ln -sf $(SRCTREE)/board/$(BOARDDIR)/$(BOARD).c $@
-$(obj)ns16550.c:
+$(obj)/ns16550.c:
ln -sf $(SRCTREE)/drivers/serial/ns16550.c $@
-$(obj)spl_minimal.c:
+$(obj)/spl_minimal.c:
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc83xx/spl_minimal.c $@
-$(obj)cache.c:
+$(obj)/cache.c:
ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $@
-$(obj)time.c:
+$(obj)/time.c:
ln -sf $(SRCTREE)/arch/powerpc/lib/time.c $@
-$(obj)ticks.S:
+$(obj)/ticks.S:
ln -sf $(SRCTREE)/arch/powerpc/lib/ticks.S $@
-
-#########################################################################
-
-$(obj)%.o: $(obj)%.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(obj)%.c
- $(CC) $(CFLAGS) -c -o $@ $<
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
# SPDX-License-Identifier: GPL-2.0+
#
-NAND_SPL := y
CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000
PAD_TO := 0xfff01000
-include $(TOPDIR)/config.mk
-
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
$(LDFLAGS) $(LDFLAGS_FINAL)
-AFLAGS += -DCONFIG_NAND_SPL
-CFLAGS += -DCONFIG_NAND_SPL
+asflags-y += -DCONFIG_NAND_SPL
+ccflags-y += -DCONFIG_NAND_SPL
SOBJS = start.o resetvec.o
COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
-SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(nandobj)board/$(BOARDDIR)
+targets += $(__OBJS)
+
all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+ $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+ $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-Map $(nandobj)u-boot-spl.map -o $@
$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
+ $(CPP) $(cpp_flags) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
-ansi -D__ASSEMBLY__ -P - <$< >$@
# create symbolic links for common files
-$(obj)cache.c:
+$(obj)/cache.c:
@rm -f $@
ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $@
-$(obj)cpu_init_early.c:
+$(obj)/cpu_init_early.c:
@rm -f $@
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@
-$(obj)spl_minimal.c:
+$(obj)/spl_minimal.c:
@rm -f $@
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@
-$(obj)fsl_law.c:
+$(obj)/fsl_law.c:
@rm -f $@
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $@
-$(obj)law.c:
+$(obj)/law.c:
@rm -f $@
ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $@
-$(obj)nand_boot_fsl_elbc.c:
+$(obj)/nand_boot_fsl_elbc.c:
@rm -f $@
ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@
-$(obj)ns16550.c:
+$(obj)/ns16550.c:
@rm -f $@
ln -sf $(SRCTREE)/drivers/serial/ns16550.c $@
-$(obj)resetvec.S:
+$(obj)/resetvec.S:
@rm -f $@
ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $@
-$(obj)fixed_ivor.S:
+$(obj)/fixed_ivor.S:
@rm -f $@
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@
-$(obj)start.S: $(obj)fixed_ivor.S
+$(obj)/start.S: $(obj)/fixed_ivor.S
@rm -f $@
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $@
-$(obj)tlb.c:
+$(obj)/tlb.c:
@rm -f $@
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $@
-$(obj)tlb_table.c:
+$(obj)/tlb_table.c:
@rm -f $@
ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $@
-
-ifneq ($(OBJTREE), $(SRCTREE))
-$(obj)nand_boot.c:
- @rm -f $@
- ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $@
-endif
-
-#########################################################################
-
-$(obj)%.o: $(obj)%.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(obj)%.c
- $(CC) $(CFLAGS) -c -o $@ $<
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
# SPDX-License-Identifier: GPL-2.0+
#
-NAND_SPL := y
CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000
PAD_TO := 0xfff01000
-include $(TOPDIR)/config.mk
-
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
$(LDFLAGS) $(LDFLAGS_FINAL)
-AFLAGS += -DCONFIG_NAND_SPL
-CFLAGS += -DCONFIG_NAND_SPL
+asflags-y += -DCONFIG_NAND_SPL
+ccflags-y += -DCONFIG_NAND_SPL
SOBJS = start.o resetvec.o
COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
-SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(nandobj)board/$(BOARDDIR)
+targets += $(__OBJS)
+
all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+ $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+ $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-Map $(nandobj)u-boot-spl.map -o $@
$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
+ $(CPP) $(cpp_flags) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
-ansi -D__ASSEMBLY__ -P - <$< >$@
# create symbolic links for common files
-$(obj)cache.c:
+$(obj)/cache.c:
@rm -f $@
ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $@
-$(obj)cpu_init_early.c:
+$(obj)/cpu_init_early.c:
@rm -f $@
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@
-$(obj)spl_minimal.c:
+$(obj)/spl_minimal.c:
@rm -f $@
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@
-$(obj)fsl_law.c:
+$(obj)/fsl_law.c:
@rm -f $@
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $@
-$(obj)law.c:
+$(obj)/law.c:
@rm -f $@
ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $@
-$(obj)nand_boot_fsl_elbc.c:
+$(obj)/nand_boot_fsl_elbc.c:
@rm -f $@
ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@
-$(obj)ns16550.c:
+$(obj)/ns16550.c:
@rm -f $@
ln -sf $(SRCTREE)/drivers/serial/ns16550.c $@
-$(obj)resetvec.S:
+$(obj)/resetvec.S:
@rm -f $@
ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $@
-$(obj)fixed_ivor.S:
+$(obj)/fixed_ivor.S:
@rm -f $@
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@
-$(obj)start.S: $(obj)fixed_ivor.S
+$(obj)/start.S: $(obj)/fixed_ivor.S
@rm -f $@
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $@
-$(obj)tlb.c:
+$(obj)/tlb.c:
@rm -f $@
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $@
-$(obj)tlb_table.c:
+$(obj)/tlb_table.c:
@rm -f $@
ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $@
-
-ifneq ($(OBJTREE), $(SRCTREE))
-$(obj)nand_boot.c:
- @rm -f $@
- ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $@
-endif
-
-#########################################################################
-
-$(obj)%.o: $(obj)%.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(obj)%.c
- $(CC) $(CFLAGS) -c -o $@ $<
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
# SPDX-License-Identifier: GPL-2.0+
#
-NAND_SPL := y
CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000
PAD_TO := 0xfff01000
-include $(TOPDIR)/config.mk
-
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
$(LDFLAGS) $(LDFLAGS_FINAL)
-AFLAGS += -DCONFIG_NAND_SPL
-CFLAGS += -DCONFIG_NAND_SPL
+asflags-y += -DCONFIG_NAND_SPL
+ccflags-y += -DCONFIG_NAND_SPL
SOBJS = start.o resetvec.o
COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
-SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(nandobj)board/$(BOARDDIR)
+targets += $(__OBJS)
+
all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+ $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+ $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-Map $(nandobj)u-boot-spl.map -o $@
$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
+ $(CPP) $(cpp_flags) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
-ansi -D__ASSEMBLY__ -P - <$< >$@
# create symbolic links for common files
-$(obj)cache.c:
+$(obj)/cache.c:
@rm -f $@
ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $@
-$(obj)cpu_init_early.c:
+$(obj)/cpu_init_early.c:
@rm -f $@
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@
-$(obj)spl_minimal.c:
+$(obj)/spl_minimal.c:
@rm -f $@
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@
-$(obj)fsl_law.c:
+$(obj)/fsl_law.c:
@rm -f $@
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $@
-$(obj)law.c:
+$(obj)/law.c:
@rm -f $@
ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $@
-$(obj)nand_boot_fsl_elbc.c:
+$(obj)/nand_boot_fsl_elbc.c:
@rm -f $@
ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@
-$(obj)ns16550.c:
+$(obj)/ns16550.c:
@rm -f $@
ln -sf $(SRCTREE)/drivers/serial/ns16550.c $@
-$(obj)resetvec.S:
+$(obj)/resetvec.S:
@rm -f $@
ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $@
-$(obj)fixed_ivor.S:
+$(obj)/fixed_ivor.S:
@rm -f $@
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@
-$(obj)start.S: $(obj)fixed_ivor.S
+$(obj)/start.S: $(obj)/fixed_ivor.S
@rm -f $@
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $@
-$(obj)tlb.c:
+$(obj)/tlb.c:
@rm -f $@
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $@
-$(obj)tlb_table.c:
+$(obj)/tlb_table.c:
@rm -f $@
ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $@
-
-ifneq ($(OBJTREE), $(SRCTREE))
-$(obj)nand_boot.c:
- @rm -f $@
- ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $@
-endif
-
-#########################################################################
-
-$(obj)%.o: $(obj)%.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(obj)%.c
- $(CC) $(CFLAGS) -c -o $@ $<
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
#
# SPDX-License-Identifier: GPL-2.0+
#
-NAND_SPL := y
-PAD_TO := 0xfff01000
-include $(TOPDIR)/config.mk
+PAD_TO := 0xfff01000
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
$(LDFLAGS) $(LDFLAGS_FINAL)
-AFLAGS += -DCONFIG_NAND_SPL
-CFLAGS += -DCONFIG_NAND_SPL
+asflags-y += -DCONFIG_NAND_SPL
+ccflags-y += -DCONFIG_NAND_SPL
SOBJS = start.o resetvec.o
COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
-SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(nandobj)board/$(BOARDDIR)
+targets += $(__OBJS)
+
all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+ $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+ $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-Map $(nandobj)u-boot-spl.map -o $@
$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
+ $(CPP) $(cpp_flags) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
-ansi -D__ASSEMBLY__ -P - <$< >$@
# create symbolic links for common files
-$(obj)cache.c:
+$(obj)/cache.c:
@rm -f $@
ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $@
-$(obj)cpu_init_early.c:
+$(obj)/cpu_init_early.c:
@rm -f $@
ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $@
-$(obj)spl_minimal.c:
+$(obj)/spl_minimal.c:
@rm -f $@
ln -sf $(SRCTREE)/$(CPUDIR)/spl_minimal.c $@
-$(obj)fsl_law.c:
+$(obj)/fsl_law.c:
@rm -f $@
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $@
-$(obj)law.c:
+$(obj)/law.c:
@rm -f $@
ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $@
-$(obj)nand_boot_fsl_elbc.c:
+$(obj)/nand_boot_fsl_elbc.c:
@rm -f $@
ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@
-$(obj)ns16550.c:
+$(obj)/ns16550.c:
@rm -f $@
ln -sf $(SRCTREE)/drivers/serial/ns16550.c $@
-$(obj)resetvec.S:
+$(obj)/resetvec.S:
@rm -f $@
ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $@
-$(obj)fixed_ivor.S:
+$(obj)/fixed_ivor.S:
@rm -f $@
ln -sf $(SRCTREE)/$(CPUDIR)/fixed_ivor.S $@
-$(obj)start.S: $(obj)fixed_ivor.S
+$(obj)/start.S: $(obj)/fixed_ivor.S
@rm -f $@
ln -sf $(SRCTREE)/$(CPUDIR)/start.S $@
-$(obj)tlb.c:
+$(obj)/tlb.c:
@rm -f $@
ln -sf $(SRCTREE)/$(CPUDIR)/tlb.c $@
-$(obj)tlb_table.c:
+$(obj)/tlb_table.c:
@rm -f $@
ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $@
-
-ifneq ($(OBJTREE), $(SRCTREE))
-$(obj)nand_boot.c:
- @rm -f $@
- ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $@
-endif
-
-#########################################################################
-
-$(obj)%.o: $(obj)%.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(obj)%.c
- $(CC) $(CFLAGS) -c -o $@ $<
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
# SPDX-License-Identifier: GPL-2.0+
#
-NAND_SPL := y
CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000
PAD_TO := 0xfff01000
-include $(TOPDIR)/config.mk
-
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
$(LDFLAGS) $(LDFLAGS_FINAL)
-AFLAGS += -DCONFIG_NAND_SPL
-CFLAGS += -DCONFIG_NAND_SPL
+asflags-y += -DCONFIG_NAND_SPL
+ccflags-y += -DCONFIG_NAND_SPL
SOBJS = start.o resetvec.o
COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
-SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(nandobj)board/$(BOARDDIR)
+targets += $(__OBJS)
+
all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+ $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+ $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-Map $(nandobj)u-boot-spl.map -o $@
$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
+ $(CPP) $(cpp_flags) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
-ansi -D__ASSEMBLY__ -P - <$< >$@
# create symbolic links for common files
-$(obj)cache.c:
+$(obj)/cache.c:
@rm -f $@
ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $@
-$(obj)cpu_init_early.c:
+$(obj)/cpu_init_early.c:
@rm -f $@
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@
-$(obj)spl_minimal.c:
+$(obj)/spl_minimal.c:
@rm -f $@
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@
-$(obj)fsl_law.c:
+$(obj)/fsl_law.c:
@rm -f $@
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $@
-$(obj)law.c:
+$(obj)/law.c:
@rm -f $@
ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $@
-$(obj)nand_boot_fsl_elbc.c:
+$(obj)/nand_boot_fsl_elbc.c:
@rm -f $@
ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@
-$(obj)ns16550.c:
+$(obj)/ns16550.c:
@rm -f $@
ln -sf $(SRCTREE)/drivers/serial/ns16550.c $@
-$(obj)resetvec.S:
+$(obj)/resetvec.S:
@rm -f $@
ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $@
-$(obj)fixed_ivor.S:
+$(obj)/fixed_ivor.S:
@rm -f $@
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@
-$(obj)start.S: $(obj)fixed_ivor.S
+$(obj)/start.S: $(obj)/fixed_ivor.S
@rm -f $@
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $@
-$(obj)tlb.c:
+$(obj)/tlb.c:
@rm -f $@
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $@
-$(obj)tlb_table.c:
+$(obj)/tlb_table.c:
@rm -f $@
ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $@
-
-ifneq ($(OBJTREE), $(SRCTREE))
-$(obj)nand_boot.c:
- @rm -f $@
- ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $@
-endif
-
-#########################################################################
-
-$(obj)%.o: $(obj)%.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(obj)%.c
- $(CC) $(CFLAGS) -c -o $@ $<
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
# SPDX-License-Identifier: GPL-2.0+
#
-NAND_SPL := y
-
-include $(TOPDIR)/config.mk
-
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
$(LDFLAGS) $(LDFLAGS_FINAL)
-AFLAGS += -DCONFIG_NAND_SPL
-CFLAGS += -DCONFIG_NAND_SPL
+asflags-y += -DCONFIG_NAND_SPL
+ccflags-y += -DCONFIG_NAND_SPL
SOBJS = start.o ticks.o
COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o spl_minimal.o \
time.o cache.o
-SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(nandobj)board/$(BOARDDIR)
+targets += $(__OBJS)
+
all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+ $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+ $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-Map $(nandobj)u-boot-spl.map -o $@
$(nandobj)u-boot.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+ $(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
# create symbolic links for common files
-$(obj)start.S:
+$(obj)/start.S:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/cpu/mpc83xx/start.S $@
-$(obj)nand_boot_fsl_elbc.c:
+$(obj)/nand_boot_fsl_elbc.c:
@rm -f $@
ln -s $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@
-$(obj)sdram.c:
+$(obj)/sdram.c:
@rm -f $@
ln -s $(SRCTREE)/board/$(BOARDDIR)/sdram.c $@
-$(obj)$(BOARD).c:
+$(obj)/$(BOARD).c:
@rm -f $@
ln -s $(SRCTREE)/board/$(BOARDDIR)/$(BOARD).c $@
-$(obj)ns16550.c:
+$(obj)/ns16550.c:
@rm -f $@
ln -s $(SRCTREE)/drivers/serial/ns16550.c $@
-$(obj)spl_minimal.c:
+$(obj)/spl_minimal.c:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/cpu/mpc83xx/spl_minimal.c $@
-$(obj)cache.c:
+$(obj)/cache.c:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/lib/cache.c $@
-$(obj)time.c:
+$(obj)/time.c:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/lib/time.c $@
-$(obj)ticks.S:
+$(obj)/ticks.S:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/lib/ticks.S $@
-
-#########################################################################
-
-$(obj)%.o: $(obj)%.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(obj)%.c
- $(CC) $(CFLAGS) -c -o $@ $<
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
# SPDX-License-Identifier: GPL-2.0+
#
-# CFLAGS += -DDEBUG
+#ccflags-y += -DDEBUG
obj-$(CONFIG_CMD_NET) += arp.o
obj-$(CONFIG_CMD_NET) += bootp.o
eth_current = NULL;
bootstage_mark(BOOTSTAGE_ID_NET_ETH_START);
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
miiphy_init();
#endif
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += 20001122-1.o
-obj-y += 20010114-2.o
-obj-y += 20010226-1.o
-obj-y += 980619-1.o
-obj-y += acc1.o
-obj-y += compare-fp-1.o
-obj-y += fpu.o
-obj-y += mul-subnormal-single-1.o
-obj-y += darwin-ldouble.o
+objs-before-objcopy := 20001122-1.o 20010114-2.o 20010226-1.o 980619-1.o \
+ acc1.o compare-fp-1.o fpu.o mul-subnormal-single-1.o darwin-ldouble.o
+targets += $(objs-before-objcopy)
-CFLAGS := $(shell echo $(CFLAGS) | sed s/-msoft-float//)
-CFLAGS += -mhard-float -fkeep-inline-functions
+# remove -msoft-float flag
+$(foreach m, $(objs-before-objcopy), $(eval CFLAGS_REMOVE_$m := -msoft-float))
+ccflags-y := -mhard-float -fkeep-inline-functions
-$(obj)%.o: %.c
- $(CC) $(ALL_CFLAGS) -o $@.fp $< -c
- $(OBJCOPY) -R .gnu.attributes $@.fp $@
- rm -f $@.fp
+# Do not delete intermidiate files (*.o)
+.SECONDARY: $(call objectify, $(objs-before-objcopy))
+
+obj-y := $(objs-before-objcopy:.o=_.o)
+
+OBJCOPYFLAGS := -R .gnu.attributes
+$(obj)/%_.o: $(obj)/%.o
+ $(call if_changed,objcopy)
+++ /dev/null
-#
-# (C) Copyright 2006-2013
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-#########################################################################
-
-_depend: $(obj).depend
-
-# Split the source files into two camps: those in the current directory, and
-# those somewhere else. For the first camp we want to support CPPFLAGS_<fname>
-# and for the second we don't / can't.
-PWD_SRCS := $(filter $(notdir $(SRCS)),$(SRCS))
-OTHER_SRCS := $(filter-out $(notdir $(SRCS)),$(SRCS))
-
-# This is a list of dependency files to generate
-DEPS := $(basename $(patsubst %,$(obj).depend.%,$(PWD_SRCS)))
-
-# Join all the dependencies into a single file, in three parts
-# 1 .Concatenate all the generated depend files together
-# 2. Add in the deps from OTHER_SRCS which we couldn't process
-# 3. Add in the HOSTSRCS
-$(obj).depend: $(src)Makefile $(TOPDIR)/config.mk $(DEPS) $(OTHER_SRCS) \
- $(HOSTSRCS)
- cat /dev/null $(DEPS) >$@
- @for f in $(OTHER_SRCS); do \
- g=`basename $$f | sed -e 's/\(.*\)\.[[:alnum:]_]/\1.o/'`; \
- $(CC) -M $(CPPFLAGS) -MQ $(obj)$$g $$f >> $@ ; \
- done
- @for f in $(HOSTSRCS); do \
- g=`basename $$f | sed -e 's/\(.*\)\.[[:alnum:]_]/\1.o/'`; \
- $(HOSTCC) -M $(HOSTCPPFLAGS) -MQ $(obj)$$g $$f >> $@ ; \
- done
-
-MAKE_DEPEND = $(CC) -M $(CPPFLAGS) $(EXTRA_CPPFLAGS_DEP) \
- -MQ $(addsuffix .o,$(obj)$(basename $<)) $< >$@
-
-
-$(obj).depend.%: %.c
- $(MAKE_DEPEND)
-
-$(obj).depend.%: %.S
- $(MAKE_DEPEND)
-
-$(HOSTOBJS): $(obj)%.o: %.c
- $(HOSTCC) $(HOSTCFLAGS) $(HOSTCFLAGS_$(@F)) $(HOSTCFLAGS_$(BCURDIR)) -o $@ $< -c
-$(NOPEDOBJS): $(obj)%.o: %.c
- $(HOSTCC) $(HOSTCFLAGS_NOPED) $(HOSTCFLAGS_$(@F)) $(HOSTCFLAGS_$(BCURDIR)) -o $@ $< -c
-
-#########################################################################
--- /dev/null
+#
+# Generated files
+#
+docproc
--- /dev/null
+####
+# kbuild: Generic definitions
+
+# Convenient variables
+comma := ,
+squote := '
+empty :=
+space := $(empty) $(empty)
+
+###
+# Name of target with a '.' as filename prefix. foo/bar.o => foo/.bar.o
+dot-target = $(dir $@).$(notdir $@)
+
+###
+# The temporary file to save gcc -MD generated dependencies must not
+# contain a comma
+depfile = $(subst $(comma),_,$(dot-target).d)
+
+###
+# filename of target with directory and extension stripped
+basetarget = $(basename $(notdir $@))
+
+###
+# filename of first prerequisite with directory and extension stripped
+baseprereq = $(basename $(notdir $<))
+
+###
+# Escape single quote for use in echo statements
+escsq = $(subst $(squote),'\$(squote)',$1)
+
+###
+# Easy method for doing a status message
+ kecho := :
+ quiet_kecho := echo
+silent_kecho := :
+kecho := $($(quiet)kecho)
+
+###
+# filechk is used to check if the content of a generated file is updated.
+# Sample usage:
+# define filechk_sample
+# echo $KERNELRELEASE
+# endef
+# version.h : Makefile
+# $(call filechk,sample)
+# The rule defined shall write to stdout the content of the new file.
+# The existing file will be compared with the new one.
+# - If no file exist it is created
+# - If the content differ the new file is used
+# - If they are equal no change, and no timestamp update
+# - stdin is piped in from the first prerequisite ($<) so one has
+# to specify a valid file as first prerequisite (often the kbuild file)
+define filechk
+ $(Q)set -e; \
+ $(kecho) ' CHK $@'; \
+ mkdir -p $(dir $@); \
+ $(filechk_$(1)) < $< > $@.tmp; \
+ if [ -r $@ ] && cmp -s $@ $@.tmp; then \
+ rm -f $@.tmp; \
+ else \
+ $(kecho) ' UPD $@'; \
+ mv -f $@.tmp $@; \
+ fi
+endef
+
+######
+# gcc support functions
+# See documentation in Documentation/kbuild/makefiles.txt
+
+# cc-cross-prefix
+# Usage: CROSS_COMPILE := $(call cc-cross-prefix, m68k-linux-gnu- m68k-linux-)
+# Return first prefix where a prefix$(CC) is found in PATH.
+# If no $(CC) found in PATH with listed prefixes return nothing
+cc-cross-prefix = \
+ $(word 1, $(foreach c,$(1), \
+ $(shell set -e; \
+ if (which $(strip $(c))$(CC)) > /dev/null 2>&1 ; then \
+ echo $(c); \
+ fi)))
+
+# output directory for tests below
+TMPOUT := $(if $(KBUILD_EXTMOD),$(firstword $(KBUILD_EXTMOD))/)
+
+# try-run
+# Usage: option = $(call try-run, $(CC)...-o "$$TMP",option-ok,otherwise)
+# Exit code chooses option. "$$TMP" is can be used as temporary file and
+# is automatically cleaned up.
+# modifed for U-Boot: prevent cc-option from leaving .*.su files
+try-run = $(shell set -e; \
+ TMP="$(TMPOUT).$$$$.tmp"; \
+ TMPO="$(TMPOUT).$$$$.o"; \
+ TMPSU="$(TMPOUT).$$$$.su"; \
+ if ($(1)) >/dev/null 2>&1; \
+ then echo "$(2)"; \
+ else echo "$(3)"; \
+ fi; \
+ rm -f "$$TMP" "$$TMPO" "$$TMPSU")
+
+# as-option
+# Usage: cflags-y += $(call as-option,-Wa$(comma)-isa=foo,)
+
+as-option = $(call try-run,\
+ $(CC) $(KBUILD_CFLAGS) $(1) -c -x assembler /dev/null -o "$$TMP",$(1),$(2))
+
+# as-instr
+# Usage: cflags-y += $(call as-instr,instr,option1,option2)
+
+as-instr = $(call try-run,\
+ printf "%b\n" "$(1)" | $(CC) $(KBUILD_AFLAGS) -c -x assembler -o "$$TMP" -,$(2),$(3))
+
+# cc-option
+# Usage: cflags-y += $(call cc-option,-march=winchip-c6,-march=i586)
+
+cc-option = $(call try-run,\
+ $(CC) $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) $(1) -c -x c /dev/null -o "$$TMP",$(1),$(2))
+
+# cc-option-yn
+# Usage: flag := $(call cc-option-yn,-march=winchip-c6)
+cc-option-yn = $(call try-run,\
+ $(CC) $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) $(1) -c -x c /dev/null -o "$$TMP",y,n)
+
+# cc-option-align
+# Prefix align with either -falign or -malign
+cc-option-align = $(subst -functions=0,,\
+ $(call cc-option,-falign-functions=0,-malign-functions=0))
+
+# cc-disable-warning
+# Usage: cflags-y += $(call cc-disable-warning,unused-but-set-variable)
+cc-disable-warning = $(call try-run,\
+ $(CC) $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) -W$(strip $(1)) -c -x c /dev/null -o "$$TMP",-Wno-$(strip $(1)))
+
+# cc-version
+# Usage gcc-ver := $(call cc-version)
+cc-version = $(shell $(CONFIG_SHELL) $(srctree)/scripts/gcc-version.sh $(CC))
+
+# cc-fullversion
+# Usage gcc-ver := $(call cc-fullversion)
+cc-fullversion = $(shell $(CONFIG_SHELL) \
+ $(srctree)/scripts/gcc-version.sh -p $(CC))
+
+# cc-ifversion
+# Usage: EXTRA_CFLAGS += $(call cc-ifversion, -lt, 0402, -O1)
+cc-ifversion = $(shell [ $(call cc-version, $(CC)) $(1) $(2) ] && echo $(3))
+
+# added for U-Boot
+binutils-version = $(shell $(CONFIG_SHELL) $(srctree)/scripts/binutils-version.sh $(AS))
+dtc-version = $(shell $(CONFIG_SHELL) $(srctree)/scripts/dtc-version.sh $(DTC))
+
+# cc-ldoption
+# Usage: ldflags += $(call cc-ldoption, -Wl$(comma)--hash-style=both)
+cc-ldoption = $(call try-run,\
+ $(CC) $(1) -nostdlib -x c /dev/null -o "$$TMP",$(1),$(2))
+
+# ld-option
+# Usage: LDFLAGS += $(call ld-option, -X)
+ld-option = $(call try-run,\
+ $(CC) -x c /dev/null -c -o "$$TMPO" ; $(LD) $(1) "$$TMPO" -o "$$TMP",$(1),$(2))
+
+# ar-option
+# Usage: KBUILD_ARFLAGS := $(call ar-option,D)
+# Important: no spaces around options
+ar-option = $(call try-run, $(AR) rc$(1) "$$TMP",$(1),$(2))
+
+######
+
+###
+# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.build obj=
+# Usage:
+# $(Q)$(MAKE) $(build)=dir
+build := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.build obj
+
+###
+# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.modbuiltin obj=
+# Usage:
+# $(Q)$(MAKE) $(modbuiltin)=dir
+modbuiltin := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.modbuiltin obj
+
+# Prefix -I with $(srctree) if it is not an absolute path.
+# skip if -I has no parameter
+addtree = $(if $(patsubst -I%,%,$(1)), \
+$(if $(filter-out -I/%,$(1)),$(patsubst -I%,-I$(srctree)/%,$(1))) $(1))
+
+# Find all -I options and call addtree
+flags = $(foreach o,$($(1)),$(if $(filter -I%,$(o)),$(call addtree,$(o)),$(o)))
+
+# echo command.
+# Short version is used, if $(quiet) equals `quiet_', otherwise full one.
+echo-cmd = $(if $($(quiet)cmd_$(1)),\
+ echo ' $(call escsq,$($(quiet)cmd_$(1)))$(echo-why)';)
+
+# printing commands
+cmd = @$(echo-cmd) $(cmd_$(1))
+
+# Add $(obj)/ for paths that are not absolute
+objectify = $(foreach o,$(1),$(if $(filter /%,$(o)),$(o),$(obj)/$(o)))
+
+###
+# if_changed - execute command if any prerequisite is newer than
+# target, or command line has changed
+# if_changed_dep - as if_changed, but uses fixdep to reveal dependencies
+# including used config symbols
+# if_changed_rule - as if_changed but execute rule instead
+# See Documentation/kbuild/makefiles.txt for more info
+
+ifneq ($(KBUILD_NOCMDDEP),1)
+# Check if both arguments has same arguments. Result is empty string if equal.
+# User may override this check using make KBUILD_NOCMDDEP=1
+arg-check = $(strip $(filter-out $(cmd_$(1)), $(cmd_$@)) \
+ $(filter-out $(cmd_$@), $(cmd_$(1))) )
+else
+arg-check = $(if $(strip $(cmd_$@)),,1)
+endif
+
+# >'< substitution is for echo to work,
+# >$< substitution to preserve $ when reloading .cmd file
+# note: when using inline perl scripts [perl -e '...$$t=1;...']
+# in $(cmd_xxx) double $$ your perl vars
+make-cmd = $(subst \\,\\\\,$(subst \#,\\\#,$(subst $$,$$$$,$(call escsq,$(cmd_$(1))))))
+
+# Find any prerequisites that is newer than target or that does not exist.
+# PHONY targets skipped in both cases.
+any-prereq = $(filter-out $(PHONY),$?) $(filter-out $(PHONY) $(wildcard $^),$^)
+
+# Execute command if command has changed or prerequisite(s) are updated.
+#
+if_changed = $(if $(strip $(any-prereq) $(arg-check)), \
+ @set -e; \
+ $(echo-cmd) $(cmd_$(1)); \
+ echo 'cmd_$@ := $(make-cmd)' > $(dot-target).cmd)
+
+# Execute the command and also postprocess generated .d dependencies file.
+if_changed_dep = $(if $(strip $(any-prereq) $(arg-check) ), \
+ @set -e; \
+ $(echo-cmd) $(cmd_$(1)); \
+ scripts/basic/fixdep $(depfile) $@ '$(make-cmd)' > $(dot-target).tmp;\
+ rm -f $(depfile); \
+ mv -f $(dot-target).tmp $(dot-target).cmd)
+
+# Usage: $(call if_changed_rule,foo)
+# Will check if $(cmd_foo) or any of the prerequisites changed,
+# and if so will execute $(rule_foo).
+if_changed_rule = $(if $(strip $(any-prereq) $(arg-check) ), \
+ @set -e; \
+ $(rule_$(1)))
+
+###
+# why - tell why a a target got build
+# enabled by make V=2
+# Output (listed in the order they are checked):
+# (1) - due to target is PHONY
+# (2) - due to target missing
+# (3) - due to: file1.h file2.h
+# (4) - due to command line change
+# (5) - due to missing .cmd file
+# (6) - due to target not in $(targets)
+# (1) PHONY targets are always build
+# (2) No target, so we better build it
+# (3) Prerequisite is newer than target
+# (4) The command line stored in the file named dir/.target.cmd
+# differed from actual command line. This happens when compiler
+# options changes
+# (5) No dir/.target.cmd file (used to store command line)
+# (6) No dir/.target.cmd file and target not listed in $(targets)
+# This is a good hint that there is a bug in the kbuild file
+ifeq ($(KBUILD_VERBOSE),2)
+why = \
+ $(if $(filter $@, $(PHONY)),- due to target is PHONY, \
+ $(if $(wildcard $@), \
+ $(if $(strip $(any-prereq)),- due to: $(any-prereq), \
+ $(if $(arg-check), \
+ $(if $(cmd_$@),- due to command line change, \
+ $(if $(filter $@, $(targets)), \
+ - due to missing .cmd file, \
+ - due to $(notdir $@) not in $$(targets) \
+ ) \
+ ) \
+ ) \
+ ), \
+ - due to target missing \
+ ) \
+ )
+
+echo-why = $(call escsq, $(strip $(why)))
+endif
--- /dev/null
+###
+# scripts contains sources for various helper programs used throughout
+# the kernel for the build process.
+# ---------------------------------------------------------------------------
+# docproc: Used in Documentation/DocBook
+
+# The following hostprogs-y programs are only build on demand
+hostprogs-y += docproc
+
+# These targets are used internally to avoid "is up to date" messages
+PHONY += build_docproc
+build_docproc: scripts/docproc
+ @:
+
+# Let clean descend into subdirs
+subdir- += basic
-# our default target
-.PHONY: all
-all:
+# ==========================================================================
+# Building
+# ==========================================================================
-include $(TOPDIR)/config.mk
+# Modified for U-Boot
+ifeq ($(CONFIG_TPL_BUILD),y)
+ src := $(patsubst tpl/%,%,$(obj))
+else
+ ifeq ($(CONFIG_SPL_BUILD),y)
+ src := $(patsubst spl/%,%,$(obj))
+ else
+ src := $(obj)
+ endif
+endif
+
+PHONY := __build
+__build:
+
+# Init all relevant variables used in kbuild files so
+# 1) they have correct type
+# 2) they do not inherit any value from the environment
+obj-y :=
+obj-m :=
+lib-y :=
+lib-m :=
+always :=
+targets :=
+subdir-y :=
+subdir-m :=
+EXTRA_AFLAGS :=
+EXTRA_CFLAGS :=
+EXTRA_CPPFLAGS :=
+EXTRA_LDFLAGS :=
+asflags-y :=
+ccflags-y :=
+cppflags-y :=
+ldflags-y :=
+
+subdir-asflags-y :=
+subdir-ccflags-y :=
+
+# Read auto.conf if it exists, otherwise ignore
+-include include/config/auto.conf
+
+# Added for U-Boot: Load U-Boot configuration
+ifeq ($(CONFIG_TPL_BUILD),y)
+ -include include/tpl-autoconf.mk
+else
+ ifeq ($(CONFIG_SPL_BUILD),y)
+ -include include/spl-autoconf.mk
+ else
+ -include include/autoconf.mk
+ endif
+endif
+
+include scripts/Kbuild.include
+
+# Added for U-Boot
+# We must include config.mk after Kbuild.include
+# so that some config.mk can use cc-option.
+include config.mk
+
+# For backward compatibility check that these variables do not change
+save-cflags := $(CFLAGS)
+
+# The filename Kbuild has precedence over Makefile
+kbuild-dir := $(if $(filter /%,$(src)),$(src),$(srctree)/$(src))
+kbuild-file := $(if $(wildcard $(kbuild-dir)/Kbuild),$(kbuild-dir)/Kbuild,$(kbuild-dir)/Makefile)
+include $(kbuild-file)
+
+# If the save-* variables changed error out
+ifeq ($(KBUILD_NOPEDANTIC),)
+ ifneq ("$(save-cflags)","$(CFLAGS)")
+ $(error CFLAGS was changed in "$(kbuild-file)". Fix it to use ccflags-y)
+ endif
+endif
+
+#
+# make W=... settings
+#
+# W=1 - warnings that may be relevant and does not occur too often
+# W=2 - warnings that occur quite often but may still be relevant
+# W=3 - the more obscure warnings, can most likely be ignored
+#
+# $(call cc-option, -W...) handles gcc -W.. options which
+# are not supported by all versions of the compiler
+ifdef KBUILD_ENABLE_EXTRA_GCC_CHECKS
+warning- := $(empty)
+
+warning-1 := -Wextra -Wunused -Wno-unused-parameter
+warning-1 += -Wmissing-declarations
+warning-1 += -Wmissing-format-attribute
+warning-1 += -Wmissing-prototypes
+warning-1 += -Wold-style-definition
+warning-1 += $(call cc-option, -Wmissing-include-dirs)
+warning-1 += $(call cc-option, -Wunused-but-set-variable)
+warning-1 += $(call cc-disable-warning, missing-field-initializers)
+
+warning-2 := -Waggregate-return
+warning-2 += -Wcast-align
+warning-2 += -Wdisabled-optimization
+warning-2 += -Wnested-externs
+warning-2 += -Wshadow
+warning-2 += $(call cc-option, -Wlogical-op)
+warning-2 += $(call cc-option, -Wmissing-field-initializers)
+
+warning-3 := -Wbad-function-cast
+warning-3 += -Wcast-qual
+warning-3 += -Wconversion
+warning-3 += -Wpacked
+warning-3 += -Wpadded
+warning-3 += -Wpointer-arith
+warning-3 += -Wredundant-decls
+warning-3 += -Wswitch-default
+warning-3 += $(call cc-option, -Wpacked-bitfield-compat)
+warning-3 += $(call cc-option, -Wvla)
+
+warning := $(warning-$(findstring 1, $(KBUILD_ENABLE_EXTRA_GCC_CHECKS)))
+warning += $(warning-$(findstring 2, $(KBUILD_ENABLE_EXTRA_GCC_CHECKS)))
+warning += $(warning-$(findstring 3, $(KBUILD_ENABLE_EXTRA_GCC_CHECKS)))
-LIB := $(obj)built-in.o
-LIBGCC = $(obj)libgcc.o
-SRCS :=
+ifeq ("$(strip $(warning))","")
+ $(error W=$(KBUILD_ENABLE_EXTRA_GCC_CHECKS) is unknown)
+endif
-include Makefile
+KBUILD_CFLAGS += $(warning)
+endif
-# Going forward use the following
-obj-y := $(sort $(obj-y))
-extra-y := $(sort $(extra-y))
-lib-y := $(sort $(lib-y))
+include scripts/Makefile.lib
-subdir-y := $(patsubst %/,%,$(filter %/, $(obj-y)))
-obj-y := $(patsubst %/, %/built-in.o, $(obj-y))
-subdir-obj-y := $(filter %/built-in.o, $(obj-y))
-subdir-obj-y := $(addprefix $(obj),$(subdir-obj-y))
+ifdef host-progs
+ifneq ($(hostprogs-y),$(host-progs))
+$(warning kbuild: $(obj)/Makefile - Usage of host-progs is deprecated. Please replace with hostprogs-y!)
+hostprogs-y += $(host-progs)
+endif
+endif
-SRCS += $(wildcard $(obj-y:.o=.c) $(obj-y:.o=.S) $(lib-y:.o=.c) \
- $(lib-y:.o=.S) $(extra-y:.o=.c) $(extra-y:.o=.S))
-OBJS := $(addprefix $(obj),$(obj-y))
+# Do not include host rules unless needed
+ifneq ($(hostprogs-y)$(hostprogs-m),)
+include scripts/Makefile.host
+endif
-# $(obj-dirs) is a list of directories that contain object files
-obj-dirs := $(dir $(OBJS))
+# Uncommented for U-Boot
+# We need to create output dicrectory for SPL and TPL even for in-tree build
+#ifneq ($(KBUILD_SRC),)
+# Create output directory if not already present
+_dummy := $(shell [ -d $(obj) ] || mkdir -p $(obj))
# Create directories for object files if directory does not exist
# Needed when obj-y := dir/file.o syntax is used
_dummy := $(foreach d,$(obj-dirs), $(shell [ -d $(d) ] || mkdir -p $(d)))
+#endif
+
+ifndef obj
+$(warning kbuild: Makefile.build is included improperly)
+endif
+
+# ===========================================================================
+
+ifneq ($(strip $(lib-y) $(lib-m) $(lib-n) $(lib-)),)
+lib-target := $(obj)/lib.a
+endif
-LGOBJS := $(addprefix $(obj),$(sort $(lib-y)))
+ifneq ($(strip $(obj-y) $(obj-m) $(obj-n) $(obj-) $(subdir-m) $(lib-target)),)
+builtin-target := $(obj)/built-in.o
+endif
-all: $(LIB) $(addprefix $(obj),$(extra-y))
+modorder-target := $(obj)/modules.order
-$(LIB): $(obj).depend $(OBJS)
- $(call cmd_link_o_target, $(OBJS))
+# We keep a list of all modules in $(MODVERDIR)
-ifneq ($(strip $(lib-y)),)
-all: $(LIBGCC)
+__build: $(if $(KBUILD_BUILTIN),$(builtin-target) $(lib-target) $(extra-y)) \
+ $(if $(KBUILD_MODULES),$(obj-m) $(modorder-target)) \
+ $(subdir-ym) $(always)
+ @:
-$(LIBGCC): $(obj).depend $(LGOBJS)
- $(call cmd_link_o_target, $(LGOBJS))
+# Linus' kernel sanity checking tool
+ifneq ($(KBUILD_CHECKSRC),0)
+ ifeq ($(KBUILD_CHECKSRC),2)
+ quiet_cmd_force_checksrc = CHECK $<
+ cmd_force_checksrc = $(CHECK) $(CHECKFLAGS) $(c_flags) $< ;
+ else
+ quiet_cmd_checksrc = CHECK $<
+ cmd_checksrc = $(CHECK) $(CHECKFLAGS) $(c_flags) $< ;
+ endif
endif
-ifneq ($(subdir-obj-y),)
-# Descending
-$(subdir-obj-y): $(subdir-y)
+# Do section mismatch analysis for each module/built-in.o
+ifdef CONFIG_DEBUG_SECTION_MISMATCH
+ cmd_secanalysis = ; scripts/mod/modpost $@
+endif
+
+# Compile C sources (.c)
+# ---------------------------------------------------------------------------
+
+# Default is built-in, unless we know otherwise
+modkern_cflags = \
+ $(if $(part-of-module), \
+ $(KBUILD_CFLAGS_MODULE) $(CFLAGS_MODULE), \
+ $(KBUILD_CFLAGS_KERNEL) $(CFLAGS_KERNEL))
+quiet_modtag := $(empty) $(empty)
+
+$(real-objs-m) : part-of-module := y
+$(real-objs-m:.o=.i) : part-of-module := y
+$(real-objs-m:.o=.s) : part-of-module := y
+$(real-objs-m:.o=.lst): part-of-module := y
+
+$(real-objs-m) : quiet_modtag := [M]
+$(real-objs-m:.o=.i) : quiet_modtag := [M]
+$(real-objs-m:.o=.s) : quiet_modtag := [M]
+$(real-objs-m:.o=.lst): quiet_modtag := [M]
+
+$(obj-m) : quiet_modtag := [M]
+
+# Default for not multi-part modules
+modname = $(basetarget)
+
+$(multi-objs-m) : modname = $(modname-multi)
+$(multi-objs-m:.o=.i) : modname = $(modname-multi)
+$(multi-objs-m:.o=.s) : modname = $(modname-multi)
+$(multi-objs-m:.o=.lst) : modname = $(modname-multi)
+$(multi-objs-y) : modname = $(modname-multi)
+$(multi-objs-y:.o=.i) : modname = $(modname-multi)
+$(multi-objs-y:.o=.s) : modname = $(modname-multi)
+$(multi-objs-y:.o=.lst) : modname = $(modname-multi)
+
+quiet_cmd_cc_s_c = CC $(quiet_modtag) $@
+cmd_cc_s_c = $(CC) $(c_flags) -fverbose-asm -S -o $@ $<
+
+$(obj)/%.s: $(src)/%.c FORCE
+ $(call if_changed_dep,cc_s_c)
+
+quiet_cmd_cc_i_c = CPP $(quiet_modtag) $@
+cmd_cc_i_c = $(CPP) $(c_flags) -o $@ $<
+
+$(obj)/%.i: $(src)/%.c FORCE
+ $(call if_changed_dep,cc_i_c)
+
+cmd_gensymtypes = \
+ $(CPP) -D__GENKSYMS__ $(c_flags) $< | \
+ $(GENKSYMS) $(if $(1), -T $(2)) \
+ $(patsubst y,-s _,$(CONFIG_HAVE_UNDERSCORE_SYMBOL_PREFIX)) \
+ $(if $(KBUILD_PRESERVE),-p) \
+ -r $(firstword $(wildcard $(2:.symtypes=.symref) /dev/null))
+
+quiet_cmd_cc_symtypes_c = SYM $(quiet_modtag) $@
+cmd_cc_symtypes_c = \
+ set -e; \
+ $(call cmd_gensymtypes,true,$@) >/dev/null; \
+ test -s $@ || rm -f $@
+
+$(obj)/%.symtypes : $(src)/%.c FORCE
+ $(call cmd,cc_symtypes_c)
+
+# C (.c) files
+# The C file is compiled and updated dependency information is generated.
+# (See cmd_cc_o_c + relevant part of rule_cc_o_c)
+
+quiet_cmd_cc_o_c = CC $(quiet_modtag) $@
+
+ifndef CONFIG_MODVERSIONS
+cmd_cc_o_c = $(CC) $(c_flags) -c -o $@ $<
-$(subdir-y): FORCE
- $(MAKE) -C $@ -f $(TOPDIR)/scripts/Makefile.build
+else
+# When module versioning is enabled the following steps are executed:
+# o compile a .tmp_<file>.o from <file>.c
+# o if .tmp_<file>.o doesn't contain a __ksymtab version, i.e. does
+# not export symbols, we just rename .tmp_<file>.o to <file>.o and
+# are done.
+# o otherwise, we calculate symbol versions using the good old
+# genksyms on the preprocessed source and postprocess them in a way
+# that they are usable as a linker script
+# o generate <file>.o from .tmp_<file>.o using the linker to
+# replace the unresolved symbols __crc_exported_symbol with
+# the actual value of the checksum generated by genksyms
+
+cmd_cc_o_c = $(CC) $(c_flags) -c -o $(@D)/.tmp_$(@F) $<
+cmd_modversions = \
+ if $(OBJDUMP) -h $(@D)/.tmp_$(@F) | grep -q __ksymtab; then \
+ $(call cmd_gensymtypes,$(KBUILD_SYMTYPES),$(@:.o=.symtypes)) \
+ > $(@D)/.tmp_$(@F:.o=.ver); \
+ \
+ $(LD) $(LDFLAGS) -r -o $@ $(@D)/.tmp_$(@F) \
+ -T $(@D)/.tmp_$(@F:.o=.ver); \
+ rm -f $(@D)/.tmp_$(@F) $(@D)/.tmp_$(@F:.o=.ver); \
+ else \
+ mv -f $(@D)/.tmp_$(@F) $@; \
+ fi;
+endif
+
+ifdef CONFIG_FTRACE_MCOUNT_RECORD
+ifdef BUILD_C_RECORDMCOUNT
+ifeq ("$(origin RECORDMCOUNT_WARN)", "command line")
+ RECORDMCOUNT_FLAGS = -w
endif
+# Due to recursion, we must skip empty.o.
+# The empty.o file is created in the make process in order to determine
+# the target endianness and word size. It is made before all other C
+# files, including recordmcount.
+sub_cmd_record_mcount = \
+ if [ $(@) != "scripts/mod/empty.o" ]; then \
+ $(objtree)/scripts/recordmcount $(RECORDMCOUNT_FLAGS) "$(@)"; \
+ fi;
+recordmcount_source := $(srctree)/scripts/recordmcount.c \
+ $(srctree)/scripts/recordmcount.h
+else
+sub_cmd_record_mcount = set -e ; perl $(srctree)/scripts/recordmcount.pl "$(ARCH)" \
+ "$(if $(CONFIG_CPU_BIG_ENDIAN),big,little)" \
+ "$(if $(CONFIG_64BIT),64,32)" \
+ "$(OBJDUMP)" "$(OBJCOPY)" "$(CC) $(KBUILD_CFLAGS)" \
+ "$(LD)" "$(NM)" "$(RM)" "$(MV)" \
+ "$(if $(part-of-module),1,0)" "$(@)";
+recordmcount_source := $(srctree)/scripts/recordmcount.pl
+endif
+cmd_record_mcount = \
+ if [ "$(findstring -pg,$(_c_flags))" = "-pg" ]; then \
+ $(sub_cmd_record_mcount) \
+ fi;
+endif
+
+define rule_cc_o_c
+ $(call echo-cmd,checksrc) $(cmd_checksrc) \
+ $(call echo-cmd,cc_o_c) $(cmd_cc_o_c); \
+ $(cmd_modversions) \
+ $(call echo-cmd,record_mcount) \
+ $(cmd_record_mcount) \
+ scripts/basic/fixdep $(depfile) $@ '$(call make-cmd,cc_o_c)' > \
+ $(dot-target).tmp; \
+ rm -f $(depfile); \
+ mv -f $(dot-target).tmp $(dot-target).cmd
+endef
+
+# Built-in and composite module parts
+$(obj)/%.o: $(src)/%.c $(recordmcount_source) FORCE
+ $(call cmd,force_checksrc)
+ $(call if_changed_rule,cc_o_c)
+
+# Single-part modules are special since we need to mark them in $(MODVERDIR)
+
+$(single-used-m): $(obj)/%.o: $(src)/%.c $(recordmcount_source) FORCE
+ $(call cmd,force_checksrc)
+ $(call if_changed_rule,cc_o_c)
+ @{ echo $(@:.o=.ko); echo $@; } > $(MODVERDIR)/$(@F:.o=.mod)
+
+quiet_cmd_cc_lst_c = MKLST $@
+ cmd_cc_lst_c = $(CC) $(c_flags) -g -c -o $*.o $< && \
+ $(CONFIG_SHELL) $(srctree)/scripts/makelst $*.o \
+ System.map $(OBJDUMP) > $@
+
+$(obj)/%.lst: $(src)/%.c FORCE
+ $(call if_changed_dep,cc_lst_c)
+
+# Compile assembler sources (.S)
+# ---------------------------------------------------------------------------
+
+modkern_aflags := $(KBUILD_AFLAGS_KERNEL) $(AFLAGS_KERNEL)
+
+$(real-objs-m) : modkern_aflags := $(KBUILD_AFLAGS_MODULE) $(AFLAGS_MODULE)
+$(real-objs-m:.o=.s): modkern_aflags := $(KBUILD_AFLAGS_MODULE) $(AFLAGS_MODULE)
+
+quiet_cmd_as_s_S = CPP $(quiet_modtag) $@
+cmd_as_s_S = $(CPP) $(a_flags) -o $@ $<
+
+$(obj)/%.s: $(src)/%.S FORCE
+ $(call if_changed_dep,as_s_S)
+
+quiet_cmd_as_o_S = AS $(quiet_modtag) $@
+cmd_as_o_S = $(CC) $(a_flags) -c -o $@ $<
+
+$(obj)/%.o: $(src)/%.S FORCE
+ $(call if_changed_dep,as_o_S)
+
+targets += $(real-objs-y) $(real-objs-m) $(lib-y)
+targets += $(extra-y) $(MAKECMDGOALS) $(always)
+
+# Linker scripts preprocessor (.lds.S -> .lds)
+# ---------------------------------------------------------------------------
+quiet_cmd_cpp_lds_S = LDS $@
+ cmd_cpp_lds_S = $(CPP) $(cpp_flags) -P -C -U$(ARCH) \
+ -D__ASSEMBLY__ -DLINKER_SCRIPT -o $@ $<
+
+$(obj)/%.lds: $(src)/%.lds.S FORCE
+ $(call if_changed_dep,cpp_lds_S)
+
+# ASN.1 grammar
+# ---------------------------------------------------------------------------
+quiet_cmd_asn1_compiler = ASN.1 $@
+ cmd_asn1_compiler = $(objtree)/scripts/asn1_compiler $< \
+ $(subst .h,.c,$@) $(subst .c,.h,$@)
+
+.PRECIOUS: $(objtree)/$(obj)/%-asn1.c $(objtree)/$(obj)/%-asn1.h
+
+$(obj)/%-asn1.c $(obj)/%-asn1.h: $(src)/%.asn1 $(objtree)/scripts/asn1_compiler
+ $(call cmd,asn1_compiler)
-#########################################################################
+# Build the compiled-in targets
+# ---------------------------------------------------------------------------
-# defines $(obj).depend target
+# To build objects in subdirs, we need to descend into the directories
+$(sort $(subdir-obj-y)): $(subdir-ym) ;
-include $(TOPDIR)/rules.mk
+#
+# Rule to compile a set of .o files into one .o file
+#
+ifdef builtin-target
+quiet_cmd_link_o_target = LD $@
+# If the list of objects to link is empty, just create an empty built-in.o
+cmd_link_o_target = $(if $(strip $(obj-y)),\
+ $(LD) $(ld_flags) -r -o $@ $(filter $(obj-y), $^) \
+ $(cmd_secanalysis),\
+ rm -f $@; $(AR) rcs$(KBUILD_ARFLAGS) $@)
-sinclude $(obj).depend
+$(builtin-target): $(obj-y) FORCE
+ $(call if_changed,link_o_target)
+
+targets += $(builtin-target)
+endif # builtin-target
+
+#
+# Rule to create modules.order file
+#
+# Create commands to either record .ko file or cat modules.order from
+# a subdirectory
+modorder-cmds = \
+ $(foreach m, $(modorder), \
+ $(if $(filter %/modules.order, $m), \
+ cat $m;, echo kernel/$m;))
+
+$(modorder-target): $(subdir-ym) FORCE
+ $(Q)(cat /dev/null; $(modorder-cmds)) > $@
+
+#
+# Rule to compile a set of .o files into one .a file
+#
+ifdef lib-target
+quiet_cmd_link_l_target = AR $@
+cmd_link_l_target = rm -f $@; $(AR) rcs$(KBUILD_ARFLAGS) $@ $(lib-y)
+
+$(lib-target): $(lib-y) FORCE
+ $(call if_changed,link_l_target)
+
+targets += $(lib-target)
+endif
+
+#
+# Rule to link composite objects
+#
+# Composite objects are specified in kbuild makefile as follows:
+# <composite-object>-objs := <list of .o files>
+# or
+# <composite-object>-y := <list of .o files>
+link_multi_deps = \
+$(filter $(addprefix $(obj)/, \
+$($(subst $(obj)/,,$(@:.o=-objs))) \
+$($(subst $(obj)/,,$(@:.o=-y)))), $^)
+
+quiet_cmd_link_multi-y = LD $@
+cmd_link_multi-y = $(LD) $(ld_flags) -r -o $@ $(link_multi_deps) $(cmd_secanalysis)
+
+quiet_cmd_link_multi-m = LD [M] $@
+cmd_link_multi-m = $(cmd_link_multi-y)
+
+# We would rather have a list of rules like
+# foo.o: $(foo-objs)
+# but that's not so easy, so we rather make all composite objects depend
+# on the set of all their parts
+$(multi-used-y) : %.o: $(multi-objs-y) FORCE
+ $(call if_changed,link_multi-y)
+
+$(multi-used-m) : %.o: $(multi-objs-m) FORCE
+ $(call if_changed,link_multi-m)
+ @{ echo $(@:.o=.ko); echo $(link_multi_deps); } > $(MODVERDIR)/$(@F:.o=.mod)
+
+targets += $(multi-used-y) $(multi-used-m)
+
+
+# Descending
+# ---------------------------------------------------------------------------
+
+PHONY += $(subdir-ym)
+$(subdir-ym):
+ $(Q)$(MAKE) $(build)=$@
+
+# Add FORCE to the prequisites of a target to force it to be always rebuilt.
+# ---------------------------------------------------------------------------
+
+PHONY += FORCE
+
+FORCE:
+
+# Read all saved command lines and dependencies for the $(targets) we
+# may be building above, using $(if_changed{,_dep}). As an
+# optimization, we don't need to read them if the target does not
+# exist, we will rebuild anyway in that case.
+
+targets := $(wildcard $(sort $(targets)))
+cmd_files := $(wildcard $(foreach f,$(targets),$(dir $(f)).$(notdir $(f)).cmd))
+
+ifneq ($(cmd_files),)
+ include $(cmd_files)
+endif
-#########################################################################
+# Declare the contents of the .PHONY variable as phony. We keep that
+# information in a variable se we can use it in if_changed and friends.
-.PHONY: FORCE
+.PHONY: $(PHONY)
--- /dev/null
+# ==========================================================================
+# Cleaning up
+# ==========================================================================
+
+src := $(obj)
+
+PHONY := __clean
+__clean:
+
+# Shorthand for $(Q)$(MAKE) scripts/Makefile.clean obj=dir
+# Usage:
+# $(Q)$(MAKE) $(clean)=dir
+clean := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.clean obj
+
+# The filename Kbuild has precedence over Makefile
+kbuild-dir := $(if $(filter /%,$(src)),$(src),$(srctree)/$(src))
+include $(if $(wildcard $(kbuild-dir)/Kbuild), $(kbuild-dir)/Kbuild, $(kbuild-dir)/Makefile)
+
+# Figure out what we need to build from the various variables
+# ==========================================================================
+
+__subdir-y := $(patsubst %/,%,$(filter %/, $(obj-y)))
+subdir-y += $(__subdir-y)
+__subdir-m := $(patsubst %/,%,$(filter %/, $(obj-m)))
+subdir-m += $(__subdir-m)
+__subdir-n := $(patsubst %/,%,$(filter %/, $(obj-n)))
+subdir-n += $(__subdir-n)
+__subdir- := $(patsubst %/,%,$(filter %/, $(obj-)))
+subdir- += $(__subdir-)
+
+# Subdirectories we need to descend into
+
+subdir-ym := $(sort $(subdir-y) $(subdir-m))
+subdir-ymn := $(sort $(subdir-ym) $(subdir-n) $(subdir-))
+
+# Add subdir path
+
+subdir-ymn := $(addprefix $(obj)/,$(subdir-ymn))
+
+# Temporal work-around for U-Boot
+
+subdir-ymn := $(foreach f, $(subdir-ymn), $(if $(wildcard $f/Makefile),$f))
+
+# build a list of files to remove, usually relative to the current
+# directory
+
+__clean-files := $(extra-y) $(always) \
+ $(targets) $(clean-files) \
+ $(host-progs) \
+ $(hostprogs-y) $(hostprogs-m) $(hostprogs-)
+
+__clean-files := $(filter-out $(no-clean-files), $(__clean-files))
+
+# as clean-files is given relative to the current directory, this adds
+# a $(obj) prefix, except for absolute paths
+
+__clean-files := $(wildcard \
+ $(addprefix $(obj)/, $(filter-out /%, $(__clean-files))) \
+ $(filter /%, $(__clean-files)))
+
+# as clean-dirs is given relative to the current directory, this adds
+# a $(obj) prefix, except for absolute paths
+
+__clean-dirs := $(wildcard \
+ $(addprefix $(obj)/, $(filter-out /%, $(clean-dirs))) \
+ $(filter /%, $(clean-dirs)))
+
+# ==========================================================================
+
+quiet_cmd_clean = CLEAN $(obj)
+ cmd_clean = rm -f $(__clean-files)
+quiet_cmd_cleandir = CLEAN $(__clean-dirs)
+ cmd_cleandir = rm -rf $(__clean-dirs)
+
+
+__clean: $(subdir-ymn)
+ifneq ($(strip $(__clean-files)),)
+ +$(call cmd,clean)
+endif
+ifneq ($(strip $(__clean-dirs)),)
+ +$(call cmd,cleandir)
+endif
+ifneq ($(strip $(clean-rule)),)
+ +$(clean-rule)
+endif
+ @:
+
+
+# ===========================================================================
+# Generic stuff
+# ===========================================================================
+
+# Descending
+# ---------------------------------------------------------------------------
+
+PHONY += $(subdir-ymn)
+$(subdir-ymn):
+ $(Q)$(MAKE) $(clean)=$@
+
+# If quiet is set, only print short version of command
+
+cmd = @$(if $($(quiet)cmd_$(1)),echo ' $($(quiet)cmd_$(1))' &&) $(cmd_$(1))
+
+
+# Declare the contents of the .PHONY variable as phony. We keep that
+# information in a variable se we can use it in if_changed and friends.
+
+.PHONY: $(PHONY)
--- /dev/null
+# ==========================================================================
+# Building binaries on the host system
+# Binaries are used during the compilation of the kernel, for example
+# to preprocess a data file.
+#
+# Both C and C++ are supported, but preferred language is C for such utilities.
+#
+# Sample syntax (see Documentation/kbuild/makefiles.txt for reference)
+# hostprogs-y := bin2hex
+# Will compile bin2hex.c and create an executable named bin2hex
+#
+# hostprogs-y := lxdialog
+# lxdialog-objs := checklist.o lxdialog.o
+# Will compile lxdialog.c and checklist.c, and then link the executable
+# lxdialog, based on checklist.o and lxdialog.o
+#
+# hostprogs-y := qconf
+# qconf-cxxobjs := qconf.o
+# qconf-objs := menu.o
+# Will compile qconf as a C++ program, and menu as a C program.
+# They are linked as C++ code to the executable qconf
+
+# hostprogs-y := conf
+# conf-objs := conf.o libkconfig.so
+# libkconfig-objs := expr.o type.o
+# Will create a shared library named libkconfig.so that consists of
+# expr.o and type.o (they are both compiled as C code and the object files
+# are made as position independent code).
+# conf.c is compiled as a C program, and conf.o is linked together with
+# libkconfig.so as the executable conf.
+# Note: Shared libraries consisting of C++ files are not supported
+
+__hostprogs := $(sort $(hostprogs-y) $(hostprogs-m))
+
+# C code
+# Executables compiled from a single .c file
+host-csingle := $(foreach m,$(__hostprogs),$(if $($(m)-objs),,$(m)))
+
+# C executables linked based on several .o files
+host-cmulti := $(foreach m,$(__hostprogs),\
+ $(if $($(m)-cxxobjs),,$(if $($(m)-objs),$(m))))
+
+# Object (.o) files compiled from .c files
+host-cobjs := $(sort $(foreach m,$(__hostprogs),$($(m)-objs)))
+
+# C++ code
+# C++ executables compiled from at least on .cc file
+# and zero or more .c files
+host-cxxmulti := $(foreach m,$(__hostprogs),$(if $($(m)-cxxobjs),$(m)))
+
+# C++ Object (.o) files compiled from .cc files
+host-cxxobjs := $(sort $(foreach m,$(host-cxxmulti),$($(m)-cxxobjs)))
+
+# Shared libaries (only .c supported)
+# Shared libraries (.so) - all .so files referenced in "xxx-objs"
+host-cshlib := $(sort $(filter %.so, $(host-cobjs)))
+# Remove .so files from "xxx-objs"
+host-cobjs := $(filter-out %.so,$(host-cobjs))
+
+#Object (.o) files used by the shared libaries
+host-cshobjs := $(sort $(foreach m,$(host-cshlib),$($(m:.so=-objs))))
+
+# output directory for programs/.o files
+# hostprogs-y := tools/build may have been specified. Retrieve directory
+host-objdirs := $(foreach f,$(__hostprogs), $(if $(dir $(f)),$(dir $(f))))
+# directory of .o files from prog-objs notation
+host-objdirs += $(foreach f,$(host-cmulti), \
+ $(foreach m,$($(f)-objs), \
+ $(if $(dir $(m)),$(dir $(m)))))
+# directory of .o files from prog-cxxobjs notation
+host-objdirs += $(foreach f,$(host-cxxmulti), \
+ $(foreach m,$($(f)-cxxobjs), \
+ $(if $(dir $(m)),$(dir $(m)))))
+
+host-objdirs := $(strip $(sort $(filter-out ./,$(host-objdirs))))
+
+
+__hostprogs := $(addprefix $(obj)/,$(__hostprogs))
+host-csingle := $(addprefix $(obj)/,$(host-csingle))
+host-cmulti := $(addprefix $(obj)/,$(host-cmulti))
+host-cobjs := $(addprefix $(obj)/,$(host-cobjs))
+host-cxxmulti := $(addprefix $(obj)/,$(host-cxxmulti))
+host-cxxobjs := $(addprefix $(obj)/,$(host-cxxobjs))
+host-cshlib := $(addprefix $(obj)/,$(host-cshlib))
+host-cshobjs := $(addprefix $(obj)/,$(host-cshobjs))
+host-objdirs := $(addprefix $(obj)/,$(host-objdirs))
+
+obj-dirs += $(host-objdirs)
+
+#####
+# Handle options to gcc. Support building with separate output directory
+
+_hostc_flags = $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) \
+ $(HOSTCFLAGS_$(basetarget).o)
+_hostcxx_flags = $(HOSTCXXFLAGS) $(HOST_EXTRACXXFLAGS) \
+ $(HOSTCXXFLAGS_$(basetarget).o)
+
+ifeq ($(KBUILD_SRC),)
+__hostc_flags = $(_hostc_flags)
+__hostcxx_flags = $(_hostcxx_flags)
+else
+__hostc_flags = -I$(obj) $(call flags,_hostc_flags)
+__hostcxx_flags = -I$(obj) $(call flags,_hostcxx_flags)
+endif
+
+hostc_flags = -Wp,-MD,$(depfile) $(__hostc_flags)
+hostcxx_flags = -Wp,-MD,$(depfile) $(__hostcxx_flags)
+
+#####
+# Compile programs on the host
+
+# Create executable from a single .c file
+# host-csingle -> Executable
+quiet_cmd_host-csingle = HOSTCC $@
+ cmd_host-csingle = $(HOSTCC) $(hostc_flags) -o $@ $< \
+ $(HOST_LOADLIBES) $(HOSTLOADLIBES_$(@F))
+$(host-csingle): $(obj)/%: $(src)/%.c FORCE
+ $(call if_changed_dep,host-csingle)
+
+# Link an executable based on list of .o files, all plain c
+# host-cmulti -> executable
+quiet_cmd_host-cmulti = HOSTLD $@
+ cmd_host-cmulti = $(HOSTCC) $(HOSTLDFLAGS) -o $@ \
+ $(addprefix $(obj)/,$($(@F)-objs)) \
+ $(HOST_LOADLIBES) $(HOSTLOADLIBES_$(@F))
+$(host-cmulti): $(obj)/%: $(host-cobjs) $(host-cshlib) FORCE
+ $(call if_changed,host-cmulti)
+
+# Create .o file from a single .c file
+# host-cobjs -> .o
+quiet_cmd_host-cobjs = HOSTCC $@
+ cmd_host-cobjs = $(HOSTCC) $(hostc_flags) -c -o $@ $<
+$(host-cobjs): $(obj)/%.o: $(src)/%.c FORCE
+ $(call if_changed_dep,host-cobjs)
+
+# Link an executable based on list of .o files, a mixture of .c and .cc
+# host-cxxmulti -> executable
+quiet_cmd_host-cxxmulti = HOSTLD $@
+ cmd_host-cxxmulti = $(HOSTCXX) $(HOSTLDFLAGS) -o $@ \
+ $(foreach o,objs cxxobjs,\
+ $(addprefix $(obj)/,$($(@F)-$(o)))) \
+ $(HOST_LOADLIBES) $(HOSTLOADLIBES_$(@F))
+$(host-cxxmulti): $(obj)/%: $(host-cobjs) $(host-cxxobjs) $(host-cshlib) FORCE
+ $(call if_changed,host-cxxmulti)
+
+# Create .o file from a single .cc (C++) file
+quiet_cmd_host-cxxobjs = HOSTCXX $@
+ cmd_host-cxxobjs = $(HOSTCXX) $(hostcxx_flags) -c -o $@ $<
+$(host-cxxobjs): $(obj)/%.o: $(src)/%.cc FORCE
+ $(call if_changed_dep,host-cxxobjs)
+
+# Compile .c file, create position independent .o file
+# host-cshobjs -> .o
+quiet_cmd_host-cshobjs = HOSTCC -fPIC $@
+ cmd_host-cshobjs = $(HOSTCC) $(hostc_flags) -fPIC -c -o $@ $<
+$(host-cshobjs): $(obj)/%.o: $(src)/%.c FORCE
+ $(call if_changed_dep,host-cshobjs)
+
+# Link a shared library, based on position independent .o files
+# *.o -> .so shared library (host-cshlib)
+quiet_cmd_host-cshlib = HOSTLLD -shared $@
+ cmd_host-cshlib = $(HOSTCC) $(HOSTLDFLAGS) -shared -o $@ \
+ $(addprefix $(obj)/,$($(@F:.so=-objs))) \
+ $(HOST_LOADLIBES) $(HOSTLOADLIBES_$(@F))
+$(host-cshlib): $(obj)/%: $(host-cshobjs) FORCE
+ $(call if_changed,host-cshlib)
+
+targets += $(host-csingle) $(host-cmulti) $(host-cobjs)\
+ $(host-cxxmulti) $(host-cxxobjs) $(host-cshlib) $(host-cshobjs)
+
--- /dev/null
+# Backward compatibility
+asflags-y += $(EXTRA_AFLAGS)
+ccflags-y += $(EXTRA_CFLAGS)
+cppflags-y += $(EXTRA_CPPFLAGS)
+ldflags-y += $(EXTRA_LDFLAGS)
+
+#
+# flags that take effect in sub directories
+export KBUILD_SUBDIR_ASFLAGS := $(KBUILD_SUBDIR_ASFLAGS) $(subdir-asflags-y)
+export KBUILD_SUBDIR_CCFLAGS := $(KBUILD_SUBDIR_CCFLAGS) $(subdir-ccflags-y)
+
+# Figure out what we need to build from the various variables
+# ===========================================================================
+
+# When an object is listed to be built compiled-in and modular,
+# only build the compiled-in version
+
+obj-m := $(filter-out $(obj-y),$(obj-m))
+
+# Libraries are always collected in one lib file.
+# Filter out objects already built-in
+
+lib-y := $(filter-out $(obj-y), $(sort $(lib-y) $(lib-m)))
+
+
+# Handle objects in subdirs
+# ---------------------------------------------------------------------------
+# o if we encounter foo/ in $(obj-y), replace it by foo/built-in.o
+# and add the directory to the list of dirs to descend into: $(subdir-y)
+# o if we encounter foo/ in $(obj-m), remove it from $(obj-m)
+# and add the directory to the list of dirs to descend into: $(subdir-m)
+
+# Determine modorder.
+# Unfortunately, we don't have information about ordering between -y
+# and -m subdirs. Just put -y's first.
+modorder := $(patsubst %/,%/modules.order, $(filter %/, $(obj-y)) $(obj-m:.o=.ko))
+
+__subdir-y := $(patsubst %/,%,$(filter %/, $(obj-y)))
+subdir-y += $(__subdir-y)
+__subdir-m := $(patsubst %/,%,$(filter %/, $(obj-m)))
+subdir-m += $(__subdir-m)
+obj-y := $(patsubst %/, %/built-in.o, $(obj-y))
+obj-m := $(filter-out %/, $(obj-m))
+
+# Subdirectories we need to descend into
+
+subdir-ym := $(sort $(subdir-y) $(subdir-m))
+
+# if $(foo-objs) exists, foo.o is a composite object
+multi-used-y := $(sort $(foreach m,$(obj-y), $(if $(strip $($(m:.o=-objs)) $($(m:.o=-y))), $(m))))
+multi-used-m := $(sort $(foreach m,$(obj-m), $(if $(strip $($(m:.o=-objs)) $($(m:.o=-y))), $(m))))
+multi-used := $(multi-used-y) $(multi-used-m)
+single-used-m := $(sort $(filter-out $(multi-used-m),$(obj-m)))
+
+# Build list of the parts of our composite objects, our composite
+# objects depend on those (obviously)
+multi-objs-y := $(foreach m, $(multi-used-y), $($(m:.o=-objs)) $($(m:.o=-y)))
+multi-objs-m := $(foreach m, $(multi-used-m), $($(m:.o=-objs)) $($(m:.o=-y)))
+multi-objs := $(multi-objs-y) $(multi-objs-m)
+
+# $(subdir-obj-y) is the list of objects in $(obj-y) which uses dir/ to
+# tell kbuild to descend
+subdir-obj-y := $(filter %/built-in.o, $(obj-y))
+
+# $(obj-dirs) is a list of directories that contain object files
+obj-dirs := $(dir $(multi-objs) $(obj-y))
+
+# Replace multi-part objects by their individual parts, look at local dir only
+real-objs-y := $(foreach m, $(filter-out $(subdir-obj-y), $(obj-y)), $(if $(strip $($(m:.o=-objs)) $($(m:.o=-y))),$($(m:.o=-objs)) $($(m:.o=-y)),$(m))) $(extra-y)
+real-objs-m := $(foreach m, $(obj-m), $(if $(strip $($(m:.o=-objs)) $($(m:.o=-y))),$($(m:.o=-objs)) $($(m:.o=-y)),$(m)))
+
+# Add subdir path
+
+extra-y := $(addprefix $(obj)/,$(extra-y))
+always := $(addprefix $(obj)/,$(always))
+targets := $(addprefix $(obj)/,$(targets))
+modorder := $(addprefix $(obj)/,$(modorder))
+obj-y := $(addprefix $(obj)/,$(obj-y))
+obj-m := $(addprefix $(obj)/,$(obj-m))
+lib-y := $(addprefix $(obj)/,$(lib-y))
+subdir-obj-y := $(addprefix $(obj)/,$(subdir-obj-y))
+real-objs-y := $(addprefix $(obj)/,$(real-objs-y))
+real-objs-m := $(addprefix $(obj)/,$(real-objs-m))
+single-used-m := $(addprefix $(obj)/,$(single-used-m))
+multi-used-y := $(addprefix $(obj)/,$(multi-used-y))
+multi-used-m := $(addprefix $(obj)/,$(multi-used-m))
+multi-objs-y := $(addprefix $(obj)/,$(multi-objs-y))
+multi-objs-m := $(addprefix $(obj)/,$(multi-objs-m))
+subdir-ym := $(addprefix $(obj)/,$(subdir-ym))
+obj-dirs := $(addprefix $(obj)/,$(obj-dirs))
+
+# These flags are needed for modversions and compiling, so we define them here
+# already
+# $(modname_flags) #defines KBUILD_MODNAME as the name of the module it will
+# end up in (or would, if it gets compiled in)
+# Note: Files that end up in two or more modules are compiled without the
+# KBUILD_MODNAME definition. The reason is that any made-up name would
+# differ in different configs.
+name-fix = $(subst $(comma),_,$(subst -,_,$1))
+basename_flags = -D"KBUILD_BASENAME=KBUILD_STR($(call name-fix,$(basetarget)))"
+modname_flags = $(if $(filter 1,$(words $(modname))),\
+ -D"KBUILD_MODNAME=KBUILD_STR($(call name-fix,$(modname)))")
+
+# U-Boot also uses $(CPPFLAGS)
+orig_c_flags = $(KBUILD_CPPFLAGS) $(CPPFLAGS) $(KBUILD_CFLAGS) $(KBUILD_SUBDIR_CCFLAGS) \
+ $(ccflags-y) $(CFLAGS_$(basetarget).o)
+_c_flags = $(filter-out $(CFLAGS_REMOVE_$(basetarget).o), $(orig_c_flags))
+_a_flags = $(KBUILD_CPPFLAGS) $(CPPFLAGS) $(KBUILD_AFLAGS) $(KBUILD_SUBDIR_ASFLAGS) \
+ $(asflags-y) $(AFLAGS_$(basetarget).o)
+_cpp_flags = $(KBUILD_CPPFLAGS) $(CPPFLAGS) $(cppflags-y) $(CPPFLAGS_$(@F))
+
+#
+# Enable gcov profiling flags for a file, directory or for all files depending
+# on variables GCOV_PROFILE_obj.o, GCOV_PROFILE and CONFIG_GCOV_PROFILE_ALL
+# (in this order)
+#
+ifeq ($(CONFIG_GCOV_KERNEL),y)
+_c_flags += $(if $(patsubst n%,, \
+ $(GCOV_PROFILE_$(basetarget).o)$(GCOV_PROFILE)$(CONFIG_GCOV_PROFILE_ALL)), \
+ $(CFLAGS_GCOV))
+endif
+
+# If building the kernel in a separate objtree expand all occurrences
+# of -Idir to -I$(srctree)/dir except for absolute paths (starting with '/').
+
+ifeq ($(KBUILD_SRC),)
+__c_flags = $(_c_flags)
+__a_flags = $(_a_flags)
+__cpp_flags = $(_cpp_flags)
+else
+
+# -I$(obj) locates generated .h files
+# $(call addtree,-I$(obj)) locates .h files in srctree, from generated .c files
+# and locates generated .h files
+# FIXME: Replace both with specific CFLAGS* statements in the makefiles
+__c_flags = $(call addtree,-I$(obj)) $(call flags,_c_flags)
+__a_flags = $(call flags,_a_flags)
+__cpp_flags = $(call flags,_cpp_flags)
+endif
+
+# Modified for U-Boot: LINUXINCLUDE -> UBOOTINCLUDE
+c_flags = -Wp,-MD,$(depfile) $(NOSTDINC_FLAGS) $(UBOOTINCLUDE) \
+ $(__c_flags) $(modkern_cflags) \
+ -D"KBUILD_STR(s)=\#s" $(basename_flags) $(modname_flags)
+
+a_flags = -Wp,-MD,$(depfile) $(NOSTDINC_FLAGS) $(UBOOTINCLUDE) \
+ $(__a_flags) $(modkern_aflags)
+
+cpp_flags = -Wp,-MD,$(depfile) $(NOSTDINC_FLAGS) $(UBOOTINCLUDE) \
+ $(__cpp_flags)
+
+ld_flags = $(LDFLAGS) $(ldflags-y)
+
+# Modified for U-Boot
+dtc_cpp_flags = -Wp,-MD,$(depfile).pre.tmp -nostdinc \
+ -I$(srctree)/arch/$(ARCH)/dts \
+ -undef -D__DTS__
+
+# Finds the multi-part object the current object will be linked into
+modname-multi = $(sort $(foreach m,$(multi-used),\
+ $(if $(filter $(subst $(obj)/,,$*.o), $($(m:.o=-objs)) $($(m:.o=-y))),$(m:.o=))))
+
+ifdef REGENERATE_PARSERS
+
+# GPERF
+# ---------------------------------------------------------------------------
+quiet_cmd_gperf = GPERF $@
+ cmd_gperf = gperf -t --output-file $@ -a -C -E -g -k 1,3,$$ -p -t $<
+
+.PRECIOUS: $(src)/%.hash.c_shipped
+$(src)/%.hash.c_shipped: $(src)/%.gperf
+ $(call cmd,gperf)
+
+# LEX
+# ---------------------------------------------------------------------------
+LEX_PREFIX = $(if $(LEX_PREFIX_${baseprereq}),$(LEX_PREFIX_${baseprereq}),yy)
+
+quiet_cmd_flex = LEX $@
+ cmd_flex = flex -o$@ -L -P $(LEX_PREFIX) $<
+
+.PRECIOUS: $(src)/%.lex.c_shipped
+$(src)/%.lex.c_shipped: $(src)/%.l
+ $(call cmd,flex)
+
+# YACC
+# ---------------------------------------------------------------------------
+YACC_PREFIX = $(if $(YACC_PREFIX_${baseprereq}),$(YACC_PREFIX_${baseprereq}),yy)
+
+quiet_cmd_bison = YACC $@
+ cmd_bison = bison -o$@ -t -l -p $(YACC_PREFIX) $<
+
+.PRECIOUS: $(src)/%.tab.c_shipped
+$(src)/%.tab.c_shipped: $(src)/%.y
+ $(call cmd,bison)
+
+quiet_cmd_bison_h = YACC $@
+ cmd_bison_h = bison -o/dev/null --defines=$@ -t -l -p $(YACC_PREFIX) $<
+
+.PRECIOUS: $(src)/%.tab.h_shipped
+$(src)/%.tab.h_shipped: $(src)/%.y
+ $(call cmd,bison_h)
+
+endif
+
+# Shipped files
+# ===========================================================================
+
+quiet_cmd_shipped = SHIPPED $@
+cmd_shipped = cat $< > $@
+
+$(obj)/%: $(src)/%_shipped
+ $(call cmd,shipped)
+
+# Commands useful for building a boot image
+# ===========================================================================
+#
+# Use as following:
+#
+# target: source(s) FORCE
+# $(if_changed,ld/objcopy/gzip)
+#
+# and add target to extra-y so that we know we have to
+# read in the saved command line
+
+# Linking
+# ---------------------------------------------------------------------------
+
+quiet_cmd_ld = LD $@
+cmd_ld = $(LD) $(LDFLAGS) $(ldflags-y) $(LDFLAGS_$(@F)) \
+ $(filter-out FORCE,$^) -o $@
+
+# Objcopy
+# ---------------------------------------------------------------------------
+
+quiet_cmd_objcopy = OBJCOPY $@
+cmd_objcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@
+
+# Gzip
+# ---------------------------------------------------------------------------
+
+quiet_cmd_gzip = GZIP $@
+cmd_gzip = (cat $(filter-out FORCE,$^) | gzip -n -f -9 > $@) || \
+ (rm -f $@ ; false)
+
+# DTC
+# ---------------------------------------------------------------------------
+
+# Generate an assembly file to wrap the output of the device tree compiler
+quiet_cmd_dt_S_dtb= DTB $@
+# Modified for U-Boot
+cmd_dt_S_dtb= \
+( \
+ echo '.section .dtb.init.rodata,"a"'; \
+ echo '.global __dtb_$(*F)_begin'; \
+ echo '__dtb_$(*F)_begin:'; \
+ echo '.incbin "$<" '; \
+ echo '__dtb_$(*F)_end:'; \
+ echo '.global __dtb_$(*F)_end'; \
+) > $@
+
+$(obj)/%.dtb.S: $(obj)/%.dtb
+ $(call cmd,dt_S_dtb)
+
+quiet_cmd_dtc = DTC $@
+# Modified for U-Boot
+cmd_dtc = $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \
+ dtc -O dtb -o $@ -b 0 \
+ -i $(dir $<) $(DTC_FLAGS) \
+ -d $(depfile).dtc.tmp $(dtc-tmp) ; \
+ cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile)
+
+$(obj)/%.dtb: $(src)/%.dts FORCE
+ $(call if_changed_dep,dtc)
+
+dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp)
+
+# Bzip2
+# ---------------------------------------------------------------------------
+
+# Bzip2 and LZMA do not include size in file... so we have to fake that;
+# append the size as a 32-bit littleendian number as gzip does.
+size_append = printf $(shell \
+dec_size=0; \
+for F in $1; do \
+ fsize=$$(stat -c "%s" $$F); \
+ dec_size=$$(expr $$dec_size + $$fsize); \
+done; \
+printf "%08x\n" $$dec_size | \
+ sed 's/\(..\)/\1 /g' | { \
+ read ch0 ch1 ch2 ch3; \
+ for ch in $$ch3 $$ch2 $$ch1 $$ch0; do \
+ printf '%s%03o' '\\' $$((0x$$ch)); \
+ done; \
+ } \
+)
+
+quiet_cmd_bzip2 = BZIP2 $@
+cmd_bzip2 = (cat $(filter-out FORCE,$^) | \
+ bzip2 -9 && $(call size_append, $(filter-out FORCE,$^))) > $@ || \
+ (rm -f $@ ; false)
+
+# Lzma
+# ---------------------------------------------------------------------------
+
+quiet_cmd_lzma = LZMA $@
+cmd_lzma = (cat $(filter-out FORCE,$^) | \
+ lzma -9 && $(call size_append, $(filter-out FORCE,$^))) > $@ || \
+ (rm -f $@ ; false)
+
+quiet_cmd_lzo = LZO $@
+cmd_lzo = (cat $(filter-out FORCE,$^) | \
+ lzop -9 && $(call size_append, $(filter-out FORCE,$^))) > $@ || \
+ (rm -f $@ ; false)
+
+quiet_cmd_lz4 = LZ4 $@
+cmd_lz4 = (cat $(filter-out FORCE,$^) | \
+ lz4c -l -c1 stdin stdout && $(call size_append, $(filter-out FORCE,$^))) > $@ || \
+ (rm -f $@ ; false)
+
+# U-Boot mkimage
+# ---------------------------------------------------------------------------
+
+MKIMAGE := $(srctree)/scripts/mkuboot.sh
+
+# SRCARCH just happens to match slightly more than ARCH (on sparc), so reduces
+# the number of overrides in arch makefiles
+UIMAGE_ARCH ?= $(SRCARCH)
+UIMAGE_COMPRESSION ?= $(if $(2),$(2),none)
+UIMAGE_OPTS-y ?=
+UIMAGE_TYPE ?= kernel
+UIMAGE_LOADADDR ?= arch_must_set_this
+UIMAGE_ENTRYADDR ?= $(UIMAGE_LOADADDR)
+UIMAGE_NAME ?= 'Linux-$(KERNELRELEASE)'
+UIMAGE_IN ?= $<
+UIMAGE_OUT ?= $@
+
+quiet_cmd_uimage = UIMAGE $(UIMAGE_OUT)
+ cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A $(UIMAGE_ARCH) -O linux \
+ -C $(UIMAGE_COMPRESSION) $(UIMAGE_OPTS-y) \
+ -T $(UIMAGE_TYPE) \
+ -a $(UIMAGE_LOADADDR) -e $(UIMAGE_ENTRYADDR) \
+ -n $(UIMAGE_NAME) -d $(UIMAGE_IN) $(UIMAGE_OUT)
+
+# XZ
+# ---------------------------------------------------------------------------
+# Use xzkern to compress the kernel image and xzmisc to compress other things.
+#
+# xzkern uses a big LZMA2 dictionary since it doesn't increase memory usage
+# of the kernel decompressor. A BCJ filter is used if it is available for
+# the target architecture. xzkern also appends uncompressed size of the data
+# using size_append. The .xz format has the size information available at
+# the end of the file too, but it's in more complex format and it's good to
+# avoid changing the part of the boot code that reads the uncompressed size.
+# Note that the bytes added by size_append will make the xz tool think that
+# the file is corrupt. This is expected.
+#
+# xzmisc doesn't use size_append, so it can be used to create normal .xz
+# files. xzmisc uses smaller LZMA2 dictionary than xzkern, because a very
+# big dictionary would increase the memory usage too much in the multi-call
+# decompression mode. A BCJ filter isn't used either.
+quiet_cmd_xzkern = XZKERN $@
+cmd_xzkern = (cat $(filter-out FORCE,$^) | \
+ sh $(srctree)/scripts/xz_wrap.sh && \
+ $(call size_append, $(filter-out FORCE,$^))) > $@ || \
+ (rm -f $@ ; false)
+
+quiet_cmd_xzmisc = XZMISC $@
+cmd_xzmisc = (cat $(filter-out FORCE,$^) | \
+ xz --check=crc32 --lzma2=dict=1MiB) > $@ || \
+ (rm -f $@ ; false)
+
+# misc stuff
+# ---------------------------------------------------------------------------
+quote:="
--- /dev/null
+###
+# Makefile.basic lists the most basic programs used during the build process.
+# The programs listed herein are what are needed to do the basic stuff,
+# such as fix file dependencies.
+# This initial step is needed to avoid files to be recompiled
+# when kernel configuration changes (which is what happens when
+# .config is included by main Makefile.
+# ---------------------------------------------------------------------------
+# fixdep: Used to generate dependency information during build process
+
+hostprogs-y := fixdep
+always := $(hostprogs-y)
+
+# fixdep is needed to compile other host programs
+$(addprefix $(obj)/,$(filter-out fixdep,$(always))): $(obj)/fixdep
--- /dev/null
+/*
+ * "Optimize" a list of dependencies as spit out by gcc -MD
+ * for the kernel build
+ * ===========================================================================
+ *
+ * Author Kai Germaschewski
+ * Copyright 2002 by Kai Germaschewski <kai.germaschewski@gmx.de>
+ *
+ * This software may be used and distributed according to the terms
+ * of the GNU General Public License, incorporated herein by reference.
+ *
+ *
+ * Introduction:
+ *
+ * gcc produces a very nice and correct list of dependencies which
+ * tells make when to remake a file.
+ *
+ * To use this list as-is however has the drawback that virtually
+ * every file in the kernel includes autoconf.h.
+ *
+ * If the user re-runs make *config, autoconf.h will be
+ * regenerated. make notices that and will rebuild every file which
+ * includes autoconf.h, i.e. basically all files. This is extremely
+ * annoying if the user just changed CONFIG_HIS_DRIVER from n to m.
+ *
+ * So we play the same trick that "mkdep" played before. We replace
+ * the dependency on autoconf.h by a dependency on every config
+ * option which is mentioned in any of the listed prequisites.
+ *
+ * kconfig populates a tree in include/config/ with an empty file
+ * for each config symbol and when the configuration is updated
+ * the files representing changed config options are touched
+ * which then let make pick up the changes and the files that use
+ * the config symbols are rebuilt.
+ *
+ * So if the user changes his CONFIG_HIS_DRIVER option, only the objects
+ * which depend on "include/linux/config/his/driver.h" will be rebuilt,
+ * so most likely only his driver ;-)
+ *
+ * The idea above dates, by the way, back to Michael E Chastain, AFAIK.
+ *
+ * So to get dependencies right, there are two issues:
+ * o if any of the files the compiler read changed, we need to rebuild
+ * o if the command line given to the compile the file changed, we
+ * better rebuild as well.
+ *
+ * The former is handled by using the -MD output, the later by saving
+ * the command line used to compile the old object and comparing it
+ * to the one we would now use.
+ *
+ * Again, also this idea is pretty old and has been discussed on
+ * kbuild-devel a long time ago. I don't have a sensibly working
+ * internet connection right now, so I rather don't mention names
+ * without double checking.
+ *
+ * This code here has been based partially based on mkdep.c, which
+ * says the following about its history:
+ *
+ * Copyright abandoned, Michael Chastain, <mailto:mec@shout.net>.
+ * This is a C version of syncdep.pl by Werner Almesberger.
+ *
+ *
+ * It is invoked as
+ *
+ * fixdep <depfile> <target> <cmdline>
+ *
+ * and will read the dependency file <depfile>
+ *
+ * The transformed dependency snipped is written to stdout.
+ *
+ * It first generates a line
+ *
+ * cmd_<target> = <cmdline>
+ *
+ * and then basically copies the .<target>.d file to stdout, in the
+ * process filtering out the dependency on autoconf.h and adding
+ * dependencies on include/config/my/option.h for every
+ * CONFIG_MY_OPTION encountered in any of the prequisites.
+ *
+ * It will also filter out all the dependencies on *.ver. We need
+ * to make sure that the generated version checksum are globally up
+ * to date before even starting the recursive build, so it's too late
+ * at this point anyway.
+ *
+ * The algorithm to grep for "CONFIG_..." is bit unusual, but should
+ * be fast ;-) We don't even try to really parse the header files, but
+ * merely grep, i.e. if CONFIG_FOO is mentioned in a comment, it will
+ * be picked up as well. It's not a problem with respect to
+ * correctness, since that can only give too many dependencies, thus
+ * we cannot miss a rebuild. Since people tend to not mention totally
+ * unrelated CONFIG_ options all over the place, it's not an
+ * efficiency problem either.
+ *
+ * (Note: it'd be easy to port over the complete mkdep state machine,
+ * but I don't think the added complexity is worth it)
+ */
+/*
+ * Note 2: if somebody writes HELLO_CONFIG_BOOM in a file, it will depend onto
+ * CONFIG_BOOM. This could seem a bug (not too hard to fix), but please do not
+ * fix it! Some UserModeLinux files (look at arch/um/) call CONFIG_BOOM as
+ * UML_CONFIG_BOOM, to avoid conflicts with /usr/include/linux/autoconf.h,
+ * through arch/um/include/uml-config.h; this fixdep "bug" makes sure that
+ * those files will have correct dependencies.
+ */
+
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <sys/mman.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <string.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <limits.h>
+#include <ctype.h>
+#include <arpa/inet.h>
+
+#define INT_CONF ntohl(0x434f4e46)
+#define INT_ONFI ntohl(0x4f4e4649)
+#define INT_NFIG ntohl(0x4e464947)
+#define INT_FIG_ ntohl(0x4649475f)
+
+char *target;
+char *depfile;
+char *cmdline;
+
+static void usage(void)
+{
+ fprintf(stderr, "Usage: fixdep <depfile> <target> <cmdline>\n");
+ exit(1);
+}
+
+/*
+ * Print out the commandline prefixed with cmd_<target filename> :=
+ */
+static void print_cmdline(void)
+{
+ printf("cmd_%s := %s\n\n", target, cmdline);
+}
+
+struct item {
+ struct item *next;
+ unsigned int len;
+ unsigned int hash;
+ char name[0];
+};
+
+#define HASHSZ 256
+static struct item *hashtab[HASHSZ];
+
+static unsigned int strhash(const char *str, unsigned int sz)
+{
+ /* fnv32 hash */
+ unsigned int i, hash = 2166136261U;
+
+ for (i = 0; i < sz; i++)
+ hash = (hash ^ str[i]) * 0x01000193;
+ return hash;
+}
+
+/*
+ * Lookup a value in the configuration string.
+ */
+static int is_defined_config(const char *name, int len, unsigned int hash)
+{
+ struct item *aux;
+
+ for (aux = hashtab[hash % HASHSZ]; aux; aux = aux->next) {
+ if (aux->hash == hash && aux->len == len &&
+ memcmp(aux->name, name, len) == 0)
+ return 1;
+ }
+ return 0;
+}
+
+/*
+ * Add a new value to the configuration string.
+ */
+static void define_config(const char *name, int len, unsigned int hash)
+{
+ struct item *aux = malloc(sizeof(*aux) + len);
+
+ if (!aux) {
+ perror("fixdep:malloc");
+ exit(1);
+ }
+ memcpy(aux->name, name, len);
+ aux->len = len;
+ aux->hash = hash;
+ aux->next = hashtab[hash % HASHSZ];
+ hashtab[hash % HASHSZ] = aux;
+}
+
+/*
+ * Clear the set of configuration strings.
+ */
+static void clear_config(void)
+{
+ struct item *aux, *next;
+ unsigned int i;
+
+ for (i = 0; i < HASHSZ; i++) {
+ for (aux = hashtab[i]; aux; aux = next) {
+ next = aux->next;
+ free(aux);
+ }
+ hashtab[i] = NULL;
+ }
+}
+
+/*
+ * Record the use of a CONFIG_* word.
+ */
+static void use_config(const char *m, int slen)
+{
+ unsigned int hash = strhash(m, slen);
+ int c, i;
+
+ if (is_defined_config(m, slen, hash))
+ return;
+
+ define_config(m, slen, hash);
+
+ printf(" $(wildcard include/config/");
+ for (i = 0; i < slen; i++) {
+ c = m[i];
+ if (c == '_')
+ c = '/';
+ else
+ c = tolower(c);
+ putchar(c);
+ }
+ printf(".h) \\\n");
+}
+
+static void parse_config_file(const char *map, size_t len)
+{
+ const int *end = (const int *) (map + len);
+ /* start at +1, so that p can never be < map */
+ const int *m = (const int *) map + 1;
+ const char *p, *q;
+
+ for (; m < end; m++) {
+ if (*m == INT_CONF) { p = (char *) m ; goto conf; }
+ if (*m == INT_ONFI) { p = (char *) m-1; goto conf; }
+ if (*m == INT_NFIG) { p = (char *) m-2; goto conf; }
+ if (*m == INT_FIG_) { p = (char *) m-3; goto conf; }
+ continue;
+ conf:
+ if (p > map + len - 7)
+ continue;
+ if (memcmp(p, "CONFIG_", 7))
+ continue;
+ for (q = p + 7; q < map + len; q++) {
+ if (!(isalnum(*q) || *q == '_'))
+ goto found;
+ }
+ continue;
+
+ found:
+ if (!memcmp(q - 7, "_MODULE", 7))
+ q -= 7;
+ if( (q-p-7) < 0 )
+ continue;
+ use_config(p+7, q-p-7);
+ }
+}
+
+/* test is s ends in sub */
+static int strrcmp(char *s, char *sub)
+{
+ int slen = strlen(s);
+ int sublen = strlen(sub);
+
+ if (sublen > slen)
+ return 1;
+
+ return memcmp(s + slen - sublen, sub, sublen);
+}
+
+static void do_config_file(const char *filename)
+{
+ struct stat st;
+ int fd;
+ void *map;
+
+ fd = open(filename, O_RDONLY);
+ if (fd < 0) {
+ fprintf(stderr, "fixdep: error opening config file: ");
+ perror(filename);
+ exit(2);
+ }
+ fstat(fd, &st);
+ if (st.st_size == 0) {
+ close(fd);
+ return;
+ }
+ map = mmap(NULL, st.st_size, PROT_READ, MAP_PRIVATE, fd, 0);
+ if ((long) map == -1) {
+ perror("fixdep: mmap");
+ close(fd);
+ return;
+ }
+
+ parse_config_file(map, st.st_size);
+
+ munmap(map, st.st_size);
+
+ close(fd);
+}
+
+/*
+ * Important: The below generated source_foo.o and deps_foo.o variable
+ * assignments are parsed not only by make, but also by the rather simple
+ * parser in scripts/mod/sumversion.c.
+ */
+static void parse_dep_file(void *map, size_t len)
+{
+ char *m = map;
+ char *end = m + len;
+ char *p;
+ char s[PATH_MAX];
+ int is_target;
+ int saw_any_target = 0;
+ int is_first_dep = 0;
+
+ clear_config();
+
+ while (m < end) {
+ /* Skip any "white space" */
+ while (m < end && (*m == ' ' || *m == '\\' || *m == '\n'))
+ m++;
+ /* Find next "white space" */
+ p = m;
+ while (p < end && *p != ' ' && *p != '\\' && *p != '\n')
+ p++;
+ /* Is the token we found a target name? */
+ is_target = (*(p-1) == ':');
+ /* Don't write any target names into the dependency file */
+ if (is_target) {
+ /* The /next/ file is the first dependency */
+ is_first_dep = 1;
+ } else {
+ /* Save this token/filename */
+ memcpy(s, m, p-m);
+ s[p - m] = 0;
+
+ /* Ignore certain dependencies */
+ if (strrcmp(s, "include/generated/autoconf.h") &&
+ strrcmp(s, "arch/um/include/uml-config.h") &&
+ strrcmp(s, "include/linux/kconfig.h") &&
+ strrcmp(s, ".ver")) {
+ /*
+ * Do not list the source file as dependency,
+ * so that kbuild is not confused if a .c file
+ * is rewritten into .S or vice versa. Storing
+ * it in source_* is needed for modpost to
+ * compute srcversions.
+ */
+ if (is_first_dep) {
+ /*
+ * If processing the concatenation of
+ * multiple dependency files, only
+ * process the first target name, which
+ * will be the original source name,
+ * and ignore any other target names,
+ * which will be intermediate temporary
+ * files.
+ */
+ if (!saw_any_target) {
+ saw_any_target = 1;
+ printf("source_%s := %s\n\n",
+ target, s);
+ printf("deps_%s := \\\n",
+ target);
+ }
+ is_first_dep = 0;
+ } else
+ printf(" %s \\\n", s);
+ do_config_file(s);
+ }
+ }
+ /*
+ * Start searching for next token immediately after the first
+ * "whitespace" character that follows this token.
+ */
+ m = p + 1;
+ }
+
+ if (!saw_any_target) {
+ fprintf(stderr, "fixdep: parse error; no targets found\n");
+ exit(1);
+ }
+
+ printf("\n%s: $(deps_%s)\n\n", target, target);
+ printf("$(deps_%s):\n", target);
+}
+
+static void print_deps(void)
+{
+ struct stat st;
+ int fd;
+ void *map;
+
+ fd = open(depfile, O_RDONLY);
+ if (fd < 0) {
+ fprintf(stderr, "fixdep: error opening depfile: ");
+ perror(depfile);
+ exit(2);
+ }
+ if (fstat(fd, &st) < 0) {
+ fprintf(stderr, "fixdep: error fstat'ing depfile: ");
+ perror(depfile);
+ exit(2);
+ }
+ if (st.st_size == 0) {
+ fprintf(stderr,"fixdep: %s is empty\n",depfile);
+ close(fd);
+ return;
+ }
+ map = mmap(NULL, st.st_size, PROT_READ, MAP_PRIVATE, fd, 0);
+ if ((long) map == -1) {
+ perror("fixdep: mmap");
+ close(fd);
+ return;
+ }
+
+ parse_dep_file(map, st.st_size);
+
+ munmap(map, st.st_size);
+
+ close(fd);
+}
+
+static void traps(void)
+{
+ static char test[] __attribute__((aligned(sizeof(int)))) = "CONF";
+ int *p = (int *)test;
+
+ if (*p != INT_CONF) {
+ fprintf(stderr, "fixdep: sizeof(int) != 4 or wrong endianness? %#x\n",
+ *p);
+ exit(2);
+ }
+}
+
+int main(int argc, char *argv[])
+{
+ traps();
+
+ if (argc != 4)
+ usage();
+
+ depfile = argv[1];
+ target = argv[2];
+ cmdline = argv[3];
+
+ print_cmdline();
+ print_deps();
+
+ return 0;
+}
WARN("PREFER_PACKED",
"__packed is preferred over __attribute__((packed))\n" . $herecurr);
}
+# Check for new packed members, warn to use care
+ if ($line =~ /\b(__attribute__\s*\(\s*\(.*\bpacked|__packed)\b/) {
+ WARN("NEW_PACKED",
+ "Adding new packed members is to be done with care\n" . $herecurr);
+ }
# Check for __attribute__ aligned, prefer __aligned
if ($line =~ /\b__attribute__\s*\(\s*\(.*aligned/) {
#define MAXLINESZ 2048
#define MAXFILES 250
-#define KERNELDOCPATH "tools/kernel-doc/"
+#define KERNELDOCPATH "scripts/"
#define KERNELDOC "kernel-doc"
#define DOCBOOK "-docbook"
#define LIST "-list"
#define FUNCTION "-function"
#define NOFUNCTION "-nofunction"
#define NODOCSECTIONS "-no-doc-sections"
+#define SHOWNOTFOUND "-show-not-found"
static char *srctree, *kernsrctree;
static void add_new_symbol(struct symfile *sym, char * symname)
{
sym->symbollist =
- realloc(sym->symbollist, (sym->symbolcnt + 1) * sizeof(char *));
+ realloc(sym->symbollist, (sym->symbolcnt + 1) * sizeof(char *));
sym->symbollist[sym->symbolcnt++].name = strdup(symname);
}
char *p;
char *e;
if (((p = strstr(line, "EXPORT_SYMBOL_GPL")) != NULL) ||
- ((p = strstr(line, "EXPORT_SYMBOL")) != NULL)) {
+ ((p = strstr(line, "EXPORT_SYMBOL")) != NULL)) {
/* Skip EXPORT_SYMBOL{_GPL} */
while (isalnum(*p) || *p == '_')
p++;
static void singfunc(char * filename, char * line)
{
char *vec[200]; /* Enough for specific functions */
- int i, idx = 0;
- int startofsym = 1;
+ int i, idx = 0;
+ int startofsym = 1;
vec[idx++] = KERNELDOC;
vec[idx++] = DOCBOOK;
-
- /* Split line up in individual parameters preceded by FUNCTION */
- for (i=0; line[i]; i++) {
- if (isspace(line[i])) {
- line[i] = '\0';
- startofsym = 1;
- continue;
- }
- if (startofsym) {
- startofsym = 0;
- vec[idx++] = FUNCTION;
- vec[idx++] = &line[i];
- }
- }
+ vec[idx++] = SHOWNOTFOUND;
+
+ /* Split line up in individual parameters preceded by FUNCTION */
+ for (i=0; line[i]; i++) {
+ if (isspace(line[i])) {
+ line[i] = '\0';
+ startofsym = 1;
+ continue;
+ }
+ if (startofsym) {
+ startofsym = 0;
+ vec[idx++] = FUNCTION;
+ vec[idx++] = &line[i];
+ }
+ }
for (i = 0; i < idx; i++) {
- if (strcmp(vec[i], FUNCTION))
- continue;
+ if (strcmp(vec[i], FUNCTION))
+ continue;
consume_symbol(vec[i + 1]);
}
vec[idx++] = filename;
*/
static void docsect(char *filename, char *line)
{
- char *vec[6]; /* kerneldoc -docbook -function "section" file NULL */
+ /* kerneldoc -docbook -show-not-found -function "section" file NULL */
+ char *vec[7];
char *s;
for (s = line; *s; s++)
vec[0] = KERNELDOC;
vec[1] = DOCBOOK;
- vec[2] = FUNCTION;
- vec[3] = line;
- vec[4] = filename;
- vec[5] = NULL;
+ vec[2] = SHOWNOTFOUND;
+ vec[3] = FUNCTION;
+ vec[4] = line;
+ vec[5] = filename;
+ vec[6] = NULL;
exec_kernel_doc(vec);
}
break;
case 'D':
while (*s && !isspace(*s)) s++;
- *s = '\0';
- symbolsonly(line+2);
- break;
+ *s = '\0';
+ symbolsonly(line+2);
+ break;
case 'F':
/* filename */
while (*s && !isspace(*s)) s++;
*s++ = '\0';
- /* function names */
+ /* function names */
while (isspace(*s))
s++;
singlefunctions(line +2, s);
}
/* Open file, exit on error */
infile = fopen(argv[2], "r");
- if (infile == NULL) {
- fprintf(stderr, "docproc: ");
- perror(argv[2]);
- exit(2);
- }
+ if (infile == NULL) {
+ fprintf(stderr, "docproc: ");
+ perror(argv[2]);
+ exit(2);
+ }
if (strcmp("doc", argv[1]) == 0) {
/* Need to do this in two passes.
--- /dev/null
+#!/bin/sh
+# Test for gcc '-fstack-usage' support
+# Copyright (C) 2013, Masahiro Yamada <yamada.m@jp.panasonic.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+TMP="$$"
+
+cat <<END | $@ -Werror -fstack-usage -x c - -c -o $TMP >/dev/null 2>&1 \
+ && echo "y"
+int main(void)
+{
+ return 0;
+}
+END
+
+rm -f $TMP $TMP.su
# should document the "Context:" of the function, e.g. whether the functions
# can be called form interrupts. Unlike other sections you can end it with an
# empty line.
+# A non-void function should have a "Return:" section describing the return
+# value(s).
# Example-sections should contain the string EXAMPLE so that they are marked
# appropriately in DocBook.
#
my $verbose = 0;
my $output_mode = "man";
+my $output_preformatted = 0;
my $no_doc_sections = 0;
my %highlights = %highlights_man;
my $blankline = $blankline_man;
'July', 'August', 'September', 'October',
'November', 'December')[(localtime)[4]] .
" " . ((localtime)[5]+1900);
+my $show_not_found = 0;
# Essentially these are globals.
# They probably want to be tidied up, made more localised or something.
my $doc_start = '^/\*\*\s*$'; # Allow whitespace at end of comment start.
my $doc_end = '\*/';
my $doc_com = '\s*\*\s*';
+my $doc_com_body = '\s*\* ?';
my $doc_decl = $doc_com . '(\w+)';
my $doc_sect = $doc_com . '([' . $doc_special . ']?[\w\s]+):(.*)';
-my $doc_content = $doc_com . '(.*)';
+my $doc_content = $doc_com_body . '(.*)';
my $doc_block = $doc_com . 'DOC:\s*(.*)?';
my %constants;
my $section_intro = "Introduction";
my $section = $section_default;
my $section_context = "Context";
+my $section_return = "Return";
my $undescribed = "-- undescribed --";
usage();
} elsif ($cmd eq '-no-doc-sections') {
$no_doc_sections = 1;
+ } elsif ($cmd eq '-show-not-found') {
+ $show_not_found = 1;
}
}
sub get_kernel_version() {
my $version = 'unknown kernel version';
- if (defined($ENV{'U_BOOT_VERSION'})) {
- $version = $ENV{'U_BOOT_VERSION'};
+ if (defined($ENV{'UBOOTVERSION'})) {
+ $version = $ENV{'UBOOTVERSION'};
}
return $version;
}
my $contents = join "\n", @_;
if ($no_doc_sections) {
- return;
+ return;
}
if (($function_only == 0) ||
$contents =~ s/\s+$//;
}
foreach $line (split "\n", $contents) {
+ if (! $output_preformatted) {
+ $line =~ s/^\s*//;
+ }
if ($line eq ""){
- print $lineprefix, local_unescape($blankline);
+ if (! $output_preformatted) {
+ print $lineprefix, local_unescape($blankline);
+ }
} else {
$line =~ s/\\\\\\/\&/g;
if ($output_mode eq "man" && substr($line, 0, 1) eq ".") {
print "<title>$section</title>\n";
if ($section =~ m/EXAMPLE/i) {
print "<informalexample><programlisting>\n";
+ $output_preformatted = 1;
} else {
print "<para>\n";
}
output_highlight($args{'sections'}{$section});
+ $output_preformatted = 0;
if ($section =~ m/EXAMPLE/i) {
print "</programlisting></informalexample>\n";
} else {
}
if ($section =~ m/EXAMPLE/i) {
print "<example><para>\n";
+ $output_preformatted = 1;
} else {
print "<para>\n";
}
output_highlight($args{'sections'}{$section});
+ $output_preformatted = 0;
if ($section =~ m/EXAMPLE/i) {
print "</para></example>\n";
} else {
print "<simplesect>\n <title>$section</title>\n";
if ($section =~ m/EXAMPLE/i) {
print "<example><programlisting>\n";
+ $output_preformatted = 1;
} else {
}
print "<para>\n";
output_highlight($args{'sections'}{$section});
+ $output_preformatted = 0;
print "</para>\n";
if ($section =~ m/EXAMPLE/i) {
print "</programlisting></example>\n";
# strip kmemcheck_bitfield_{begin,end}.*;
$members =~ s/kmemcheck_bitfield_.*?;//gos;
# strip attributes
- $members =~ s/__aligned\s*\(\d+\)//gos;
+ $members =~ s/__aligned\s*\(.+\)//gos;
create_parameterlist($members, ';', $file);
check_sections($file, $declaration_name, "struct", $sectcheck, $struct_actual, $nested);
}
}
+##
+# Checks the section describing the return value of a function.
+sub check_return_section {
+ my $file = shift;
+ my $declaration_name = shift;
+ my $return_type = shift;
+
+ # Ignore an empty return type (It's a macro)
+ # Ignore functions with a "void" return type. (But don't ignore "void *")
+ if (($return_type eq "") || ($return_type =~ /void\s*\w*\s*$/)) {
+ return;
+ }
+
+ if (!defined($sections{$section_return}) ||
+ $sections{$section_return} eq "") {
+ print STDERR "Warning(${file}:$.): " .
+ "No description found for return value of " .
+ "'$declaration_name'\n";
+ ++$warnings;
+ }
+}
+
##
# takes a function prototype and the name of the current file being
# processed and spits out all the details stored in the global
$prototype =~ s/^__inline +//;
$prototype =~ s/^__always_inline +//;
$prototype =~ s/^noinline +//;
- $prototype =~ s/__devinit +//;
$prototype =~ s/__init +//;
$prototype =~ s/__init_or_module +//;
$prototype =~ s/__must_check +//;
create_parameterlist($args, ',', $file);
} else {
- print STDERR "Error(${file}:$.): cannot understand prototype: '$prototype'\n";
- ++$errors;
+ print STDERR "Warning(${file}:$.): cannot understand function prototype: '$prototype'\n";
return;
}
my $prms = join " ", @parameterlist;
check_sections($file, $declaration_name, "function", $sectcheck, $prms, "");
+ # This check emits a lot of warnings at the moment, because many
+ # functions don't have a 'Return' doc section. So until the number
+ # of warnings goes sufficiently down, the check is only performed in
+ # verbose mode.
+ # TODO: always perform the check.
+ if ($verbose) {
+ check_return_section($file, $declaration_name, $return_type);
+ }
+
output_declaration($declaration_name,
'function',
{'function' => $declaration_name,
$section_counter = 0;
while (<IN>) {
+ while (s/\\\s*$//) {
+ $_ .= <IN>;
+ }
if ($state == 0) {
if (/$doc_start/o) {
$state = 1; # next line is always the function name
$descr= $1;
$descr =~ s/^\s*//;
$descr =~ s/\s*$//;
- $descr =~ s/\s+/ /;
+ $descr =~ s/\s+/ /g;
$declaration_purpose = xml_escape($descr);
$in_purpose = 1;
} else {
# Continued declaration purpose
chomp($declaration_purpose);
$declaration_purpose .= " " . xml_escape($1);
- } elsif ($section =~ m/^Example/) {
- $_ =~ s/^\s*\*//;
- $contents .= $_;
+ $declaration_purpose =~ s/\s+/ /g;
} else {
$contents .= $1 . "\n";
}
}
if ($initial_section_counter == $section_counter) {
print STDERR "Warning(${file}): no structured comments found\n";
+ if (($function_only == 1) && ($show_not_found == 1)) {
+ print STDERR " Was looking for '$_'.\n" for keys %function_table;
+ }
if ($output_mode eq "xml") {
# The template wants at least one RefEntry here; make one.
print "<refentry>\n";
--- /dev/null
+#!/bin/sh
+# Generates a small Makefile used in the root of the output
+# directory, to allow make to be started from there.
+# The Makefile also allow for more convinient build of external modules
+
+# Usage
+# $1 - Kernel src directory
+# $2 - Output directory
+# $3 - version
+# $4 - patchlevel
+
+
+test ! -r $2/Makefile -o -O $2/Makefile || exit 0
+# Only overwrite automatically generated Makefiles
+# (so we do not overwrite kernel Makefile)
+if test -e $2/Makefile && ! grep -q Automatically $2/Makefile
+then
+ exit 0
+fi
+if [ "${quiet}" != "silent_" ]; then
+ echo " GEN $2/Makefile"
+fi
+
+cat << EOF > $2/Makefile
+# Automatically generated by $0: don't edit
+
+VERSION = $3
+PATCHLEVEL = $4
+
+lastword = \$(word \$(words \$(1)),\$(1))
+makedir := \$(dir \$(call lastword,\$(MAKEFILE_LIST)))
+
+ifeq ("\$(origin V)", "command line")
+VERBOSE := \$(V)
+endif
+ifneq (\$(VERBOSE),1)
+Q := @
+endif
+
+MAKEARGS := -C $1
+MAKEARGS += O=\$(if \$(patsubst /%,,\$(makedir)),\$(CURDIR)/)\$(patsubst %/,%,\$(makedir))
+
+MAKEFLAGS += --no-print-directory
+
+.PHONY: all \$(MAKECMDGOALS)
+
+all := \$(filter-out all Makefile,\$(MAKECMDGOALS))
+
+all:
+ \$(Q)\$(MAKE) \$(MAKEARGS) \$(all)
+
+Makefile:;
+
+\$(all): all
+ @:
+
+%/: all
+ @:
+EOF
# Based on top-level Makefile.
#
+src := $(obj)
+
+# Create output directory if not already present
+_dummy := $(shell [ -d $(obj) ] || mkdir -p $(obj))
+
+include $(srctree)/scripts/Kbuild.include
+
CONFIG_SPL_BUILD := y
export CONFIG_SPL_BUILD
+KBUILD_CPPFLAGS += -DCONFIG_SPL_BUILD
+ifeq ($(CONFIG_TPL_BUILD),y)
+KBUILD_CPPFLAGS += -DCONFIG_TPL_BUILD
+endif
+
+# Enable garbage collection of un-used sections for SPL
+KBUILD_CFLAGS += -ffunction-sections -fdata-sections
+LDFLAGS_FINAL += --gc-sections
+
ifeq ($(CONFIG_TPL_BUILD),y)
export CONFIG_TPL_BUILD
SPL_BIN := u-boot-tpl
SPL_BIN := u-boot-spl
endif
-include $(TOPDIR)/config.mk
+include include/config.mk
-# We want the final binaries in this directory
ifeq ($(CONFIG_TPL_BUILD),y)
-obj := $(OBJTREE)/tpl/
-SPLTREE := $(TPLTREE)
+ -include include/tpl-autoconf.mk
else
-obj := $(OBJTREE)/spl/
+ -include include/spl-autoconf.mk
endif
+include $(TOPDIR)/config.mk
+
+# FIX ME
+c_flags := $(KBUILD_CFLAGS) $(KBUILD_CPPFLAGS) $(CPPFLAGS) $(UBOOTINCLUDE) $(NOSTDINC_FLAGS)
+
+# Auto-generate the spl-autoconf.mk file (which is included by all makefiles for SPL)
+quiet_cmd_autoconf = GEN $@
+ cmd_autoconf = \
+ $(CPP) $(c_flags) -DDO_DEPS_ONLY -dM $(srctree)/include/common.h > $@.tmp && \
+ sed -n -f $(srctree)/tools/scripts/define2mk.sed $@.tmp > $@; \
+ rm $@.tmp
+
+include/tpl-autoconf.mk: include/config.h
+ $(call cmd,autoconf)
+
+include/spl-autoconf.mk: include/config.h
+ $(call cmd,autoconf)
+
HAVE_VENDOR_COMMON_LIB = $(if $(wildcard $(SRCTREE)/board/$(VENDOR)/common/Makefile),y,n)
ifdef CONFIG_SPL_START_S_PATH
head-$(CONFIG_4xx) += $(START_PATH)/resetvec.o
head-$(CONFIG_MPC85xx) += $(START_PATH)/resetvec.o
-LIBS-y += arch/$(ARCH)/lib/
+libs-y += arch/$(ARCH)/lib/
-LIBS-y += $(CPUDIR)/
+libs-y += $(CPUDIR)/
ifdef SOC
-LIBS-y += $(CPUDIR)/$(SOC)/
-endif
-LIBS-y += board/$(BOARDDIR)/
-LIBS-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/
-
-LIBS-$(CONFIG_SPL_FRAMEWORK) += common/spl/
-LIBS-$(CONFIG_SPL_LIBCOMMON_SUPPORT) += common/
-LIBS-$(CONFIG_SPL_LIBDISK_SUPPORT) += disk/
-LIBS-$(CONFIG_SPL_I2C_SUPPORT) += drivers/i2c/
-LIBS-$(CONFIG_SPL_GPIO_SUPPORT) += drivers/gpio/
-LIBS-$(CONFIG_SPL_MMC_SUPPORT) += drivers/mmc/
-LIBS-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += drivers/ddr/fsl/
-LIBS-$(CONFIG_SPL_SERIAL_SUPPORT) += drivers/serial/
-LIBS-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += drivers/mtd/spi/
-LIBS-$(CONFIG_SPL_SPI_SUPPORT) += drivers/spi/
-LIBS-y += fs/
-LIBS-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/
-LIBS-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/ \
- drivers/power/pmic/
-LIBS-$(if $(CONFIG_CMD_NAND),$(CONFIG_SPL_NAND_SUPPORT)) += drivers/mtd/nand/
-LIBS-$(CONFIG_SPL_DRIVERS_MISC_SUPPORT) += drivers/misc/
-LIBS-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/
-LIBS-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/
-LIBS-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/
-LIBS-$(CONFIG_SPL_NET_SUPPORT) += net/
-LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/
-LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/phy/
-LIBS-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/net/phy/
-LIBS-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += drivers/usb/musb-new/
-LIBS-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/usb/gadget/
-LIBS-$(CONFIG_SPL_WATCHDOG_SUPPORT) += drivers/watchdog/
-LIBS-$(CONFIG_SPL_USB_HOST_SUPPORT) += drivers/usb/host/
-LIBS-$(CONFIG_OMAP_USB_PHY) += drivers/usb/phy/
+libs-y += $(CPUDIR)/$(SOC)/
+endif
+libs-y += board/$(BOARDDIR)/
+libs-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/
+
+libs-$(CONFIG_SPL_FRAMEWORK) += common/spl/
+libs-$(CONFIG_SPL_LIBCOMMON_SUPPORT) += common/
+libs-$(CONFIG_SPL_LIBDISK_SUPPORT) += disk/
+libs-$(CONFIG_SPL_I2C_SUPPORT) += drivers/i2c/
+libs-$(CONFIG_SPL_GPIO_SUPPORT) += drivers/gpio/
+libs-$(CONFIG_SPL_MMC_SUPPORT) += drivers/mmc/
+libs-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += drivers/ddr/fsl/
+libs-$(CONFIG_SPL_SERIAL_SUPPORT) += drivers/serial/
+libs-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += drivers/mtd/spi/
+libs-$(CONFIG_SPL_SPI_SUPPORT) += drivers/spi/
+libs-y += fs/
+libs-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/
+libs-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/ drivers/power/pmic/
+libs-$(if $(CONFIG_CMD_NAND),$(CONFIG_SPL_NAND_SUPPORT)) += drivers/mtd/nand/
+libs-$(CONFIG_SPL_DRIVERS_MISC_SUPPORT) += drivers/misc/
+libs-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/
+libs-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/
+libs-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/
+libs-$(CONFIG_SPL_NET_SUPPORT) += net/
+libs-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/
+libs-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/phy/
+libs-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/net/phy/
+libs-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += drivers/usb/musb-new/
+libs-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/usb/gadget/
+libs-$(CONFIG_SPL_WATCHDOG_SUPPORT) += drivers/watchdog/
+libs-$(CONFIG_SPL_USB_HOST_SUPPORT) += drivers/usb/host/
+libs-$(CONFIG_OMAP_USB_PHY) += drivers/usb/phy/
+libs-$(CONFIG_SPL_SATA_SUPPORT) += drivers/block/
ifneq (,$(CONFIG_MX23)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))
-LIBS-y += arch/$(ARCH)/imx-common/
+libs-y += arch/$(ARCH)/imx-common/
endif
-LIBS-$(CONFIG_ARM) += arch/arm/cpu/
-LIBS-$(CONFIG_PPC) += arch/powerpc/cpu/
+libs-$(CONFIG_ARM) += arch/arm/cpu/
+libs-$(CONFIG_PPC) += arch/powerpc/cpu/
-LIBS-y := $(patsubst %/, %/built-in.o, $(LIBS-y))
+head-y := $(addprefix $(obj)/,$(head-y))
+libs-y := $(addprefix $(obj)/,$(libs-y))
+u-boot-spl-dirs := $(patsubst %/,%,$(filter %/, $(libs-y)))
+
+libs-y := $(patsubst %/, %/built-in.o, $(libs-y))
# Add GCC lib
ifeq ("$(USE_PRIVATE_LIBGCC)", "yes")
-PLATFORM_LIBGCC = $(SPLTREE)/arch/$(ARCH)/lib/libgcc.o
-PLATFORM_LIBS := $(filter-out %/libgcc.o, $(filter-out -lgcc, $(PLATFORM_LIBS))) $(PLATFORM_LIBGCC)
+PLATFORM_LIBGCC = $(SPLTREE)/arch/$(ARCH)/lib/lib.a
+PLATFORM_LIBS := $(filter-out %/lib.a, $(filter-out -lgcc, $(PLATFORM_LIBS))) $(PLATFORM_LIBGCC)
endif
-START := $(addprefix $(SPLTREE)/,$(head-y))
-LIBS := $(addprefix $(SPLTREE)/,$(sort $(LIBS-y)))
-
-__START := $(subst $(obj),,$(START))
-__LIBS := $(subst $(obj),,$(LIBS))
+u-boot-spl-init := $(head-y)
+u-boot-spl-main := $(libs-y)
# Linker Script
ifdef CONFIG_SPL_LDSCRIPT
$(error could not find linker script)
endif
-build := -f $(TOPDIR)/scripts/Makefile.build -C
-
# Special flags for CPP when processing the linker script.
# Pass the version down so we can handle backwards compatibility
# on the fly.
$(shell $(LD) --version | \
sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p')
-$(OBJTREE)/MLO: $(obj)u-boot-spl.bin
- $(OBJTREE)/tools/mkimage -T omapimage \
- -a $(CONFIG_SPL_TEXT_BASE) -d $< $@
+quiet_cmd_mkimage = UIMAGE $@
+cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
+ $(if $(KBUILD_VERBOSE:1=), >/dev/null)
+
+MKIMAGEFLAGS_MLO = -T omapimage -a $(CONFIG_SPL_TEXT_BASE)
-$(OBJTREE)/MLO.byteswap: $(obj)u-boot-spl.bin
- $(OBJTREE)/tools/mkimage -T omapimage -n byteswap \
- -a $(CONFIG_SPL_TEXT_BASE) -d $< $@
+MKIMAGEFLAGS_MLO.byteswap = -T omapimage -n byteswap -a $(CONFIG_SPL_TEXT_BASE)
-$(OBJTREE)/SPL : $(obj)u-boot-spl.bin depend
- $(MAKE) $(build) $(SRCTREE)/arch/arm/imx-common $@
+MLO MLO.byteswap: $(obj)/u-boot-spl.bin
+ $(call if_changed,mkimage)
-ALL-y += $(obj)$(SPL_BIN).bin
+ALL-y += $(obj)/$(SPL_BIN).bin
ifdef CONFIG_SAMSUNG
-ALL-y += $(obj)$(BOARD)-spl.bin
+ALL-y += $(obj)/$(BOARD)-spl.bin
endif
all: $(ALL-y)
else
VAR_SIZE_PARAM =
endif
-$(obj)$(BOARD)-spl.bin: $(obj)u-boot-spl.bin
- $(OBJTREE)/tools/mk$(BOARD)spl $(VAR_SIZE_PARAM) $< $@
+$(obj)/$(BOARD)-spl.bin: $(obj)/u-boot-spl.bin
+ $(if $(wildcard $(OBJTREE)/spl/board/samsung/$(BOARD)/tools/mk$(BOARD)spl),\
+ $(OBJTREE)/spl/board/samsung/$(BOARD)/tools/mk$(BOARD)spl,\
+ $(OBJTREE)/tools/mkexynosspl) $(VAR_SIZE_PARAM) $< $@
+endif
+
+quiet_cmd_objcopy = OBJCOPY $@
+cmd_objcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@
+
+OBJCOPYFLAGS_$(SPL_BIN).bin = $(SPL_OBJCFLAGS) -O binary
+
+$(obj)/$(SPL_BIN).bin: $(obj)/$(SPL_BIN) FORCE
+ $(call if_changed,objcopy)
+
+LDFLAGS_$(SPL_BIN) += -T u-boot-spl.lds $(LDFLAGS_FINAL)
+ifneq ($(CONFIG_SPL_TEXT_BASE),)
+LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_SPL_TEXT_BASE)
endif
-$(obj)$(SPL_BIN).bin: $(obj)$(SPL_BIN)
- $(OBJCOPY) $(OBJCFLAGS) $(SPL_OBJCFLAGS) -O binary $< $@
+quiet_cmd_u-boot-spl = LD $@
+ cmd_u-boot-spl = cd $(obj) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) \
+ $(patsubst $(obj)/%,%,$(u-boot-spl-init)) --start-group \
+ $(patsubst $(obj)/%,%,$(u-boot-spl-main)) --end-group \
+ $(PLATFORM_LIBS) -Map $(SPL_BIN).map -o $(SPL_BIN)
+
+$(obj)/$(SPL_BIN): $(u-boot-spl-init) $(u-boot-spl-main) $(obj)/u-boot-spl.lds
+ $(call cmd,u-boot-spl)
+
+$(sort $(u-boot-spl-init) $(u-boot-spl-main)): $(u-boot-spl-dirs) ;
-GEN_UBOOT = \
- cd $(obj) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) $(__START) \
- --start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \
- -Map $(SPL_BIN).map -o $(SPL_BIN)
+PHONY += $(u-boot-spl-dirs)
+$(u-boot-spl-dirs):
+ $(Q)$(MAKE) $(build)=$@
-$(obj)$(SPL_BIN): depend $(START) $(LIBS) $(obj)u-boot-spl.lds
- $(GEN_UBOOT)
+# FIX ME
+cpp_flags := $(KBUILD_CPPFLAGS) $(CPPFLAGS) $(UBOOTINCLUDE) $(NOSTDINC_FLAGS)
-$(START):
- @:
+quiet_cmd_cpp_lds = LDS $@
+cmd_cpp_lds = $(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ \
+ -x assembler-with-cpp -P -o $@ $<
-$(LIBS): depend
- $(MAKE) $(build) $(SRCTREE)$(dir $(subst $(SPLTREE),,$@))
+$(obj)/u-boot-spl.lds: $(LDSCRIPT) FORCE
+ $(call if_changed,cpp_lds)
-$(obj)u-boot-spl.lds: $(LDSCRIPT) depend
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj). -ansi -D__ASSEMBLY__ -P - < $< > $@
+# read all saved command lines
+
+targets := $(wildcard $(sort $(targets)))
+cmd_files := $(wildcard $(obj)/.*.cmd $(foreach f,$(targets),$(dir $(f)).$(notdir $(f)).cmd))
+
+ifneq ($(cmd_files),)
+ $(cmd_files): ; # Do not try to update included dependency files
+ include $(cmd_files)
+endif
-depend: $(obj).depend
-.PHONY: depend
+PHONY += FORCE
+FORCE:
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
+# Declare the contents of the .PHONY variable as phony. We keep that
+# information in a variable so we can use it in if_changed and friends.
+.PHONY: $(PHONY)
static int do_ut_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
printf("%s: Testing commands\n", __func__);
- run_command("env default -f", 0);
+ run_command("env default -f -a", 0);
/* run a single command */
run_command("setenv single 1", 0);
"setenv list ${list}3", strlen("setenv list 1"), 0);
assert(!strcmp("1", getenv("list")));
+#ifdef CONFIG_SYS_HUSH_PARSER
+ /* Test the 'test' command */
+
+#define HUSH_TEST(name, expr, expected_result) \
+ run_command("if test " expr " ; then " \
+ "setenv " #name "_" #expected_result " y; else " \
+ "setenv " #name "_" #expected_result " n; fi", 0); \
+ assert(!strcmp(#expected_result, getenv(#name "_" #expected_result)));
+
+ /* Basic operators */
+ HUSH_TEST(streq, "aaa = aaa", y);
+ HUSH_TEST(streq, "aaa = bbb", n);
+
+ HUSH_TEST(strneq, "aaa != bbb", y);
+ HUSH_TEST(strneq, "aaa != aaa", n);
+
+ HUSH_TEST(strlt, "aaa < bbb", y);
+ HUSH_TEST(strlt, "bbb < aaa", n);
+
+ HUSH_TEST(strgt, "bbb > aaa", y);
+ HUSH_TEST(strgt, "aaa > bbb", n);
+
+ HUSH_TEST(eq, "123 -eq 123", y);
+ HUSH_TEST(eq, "123 -eq 456", n);
+
+ HUSH_TEST(ne, "123 -ne 456", y);
+ HUSH_TEST(ne, "123 -ne 123", n);
+
+ HUSH_TEST(lt, "123 -lt 456", y);
+ HUSH_TEST(lt_eq, "123 -lt 123", n);
+ HUSH_TEST(lt, "456 -lt 123", n);
+
+ HUSH_TEST(le, "123 -le 456", y);
+ HUSH_TEST(le_eq, "123 -le 123", y);
+ HUSH_TEST(le, "456 -le 123", n);
+
+ HUSH_TEST(gt, "456 -gt 123", y);
+ HUSH_TEST(gt_eq, "123 -gt 123", n);
+ HUSH_TEST(gt, "123 -gt 456", n);
+
+ HUSH_TEST(ge, "456 -ge 123", y);
+ HUSH_TEST(ge_eq, "123 -ge 123", y);
+ HUSH_TEST(ge, "123 -ge 456", n);
+
+ HUSH_TEST(z, "-z \"\"", y);
+ HUSH_TEST(z, "-z \"aaa\"", n);
+
+ HUSH_TEST(n, "-n \"aaa\"", y);
+ HUSH_TEST(n, "-n \"\"", n);
+
+ /* Inversion of simple tests */
+ HUSH_TEST(streq_inv, "! aaa = aaa", n);
+ HUSH_TEST(streq_inv, "! aaa = bbb", y);
+
+ HUSH_TEST(streq_inv_inv, "! ! aaa = aaa", y);
+ HUSH_TEST(streq_inv_inv, "! ! aaa = bbb", n);
+
+ /* Binary operators */
+ HUSH_TEST(or_0_0, "aaa != aaa -o bbb != bbb", n);
+ HUSH_TEST(or_0_1, "aaa != aaa -o bbb = bbb", y);
+ HUSH_TEST(or_1_0, "aaa = aaa -o bbb != bbb", y);
+ HUSH_TEST(or_1_1, "aaa = aaa -o bbb = bbb", y);
+
+ HUSH_TEST(and_0_0, "aaa != aaa -a bbb != bbb", n);
+ HUSH_TEST(and_0_1, "aaa != aaa -a bbb = bbb", n);
+ HUSH_TEST(and_1_0, "aaa = aaa -a bbb != bbb", n);
+ HUSH_TEST(and_1_1, "aaa = aaa -a bbb = bbb", y);
+
+ /* Inversion within binary operators */
+ HUSH_TEST(or_0_0_inv, "! aaa != aaa -o ! bbb != bbb", y);
+ HUSH_TEST(or_0_1_inv, "! aaa != aaa -o ! bbb = bbb", y);
+ HUSH_TEST(or_1_0_inv, "! aaa = aaa -o ! bbb != bbb", y);
+ HUSH_TEST(or_1_1_inv, "! aaa = aaa -o ! bbb = bbb", n);
+
+ HUSH_TEST(or_0_0_inv_inv, "! ! aaa != aaa -o ! ! bbb != bbb", n);
+ HUSH_TEST(or_0_1_inv_inv, "! ! aaa != aaa -o ! ! bbb = bbb", y);
+ HUSH_TEST(or_1_0_inv_inv, "! ! aaa = aaa -o ! ! bbb != bbb", y);
+ HUSH_TEST(or_1_1_inv_inv, "! ! aaa = aaa -o ! ! bbb = bbb", y);
+
+#ifdef CONFIG_SANDBOX
+ /*
+ * File existence
+ * This assume U-Boot sandbox is run from the U-Boot build directory
+ */
+ HUSH_TEST(e, "-e host - u-boot", y);
+ HUSH_TEST(e, "-e host - creating_this_file_breaks_uboot_unit_test", n);
+#endif
+#endif
+
printf("%s: Everything went swimmingly\n", __func__);
return 0;
}
/dumpimage
/mkenvimage
/mkimage
+/mkexynosspl
/mpc86x_clk
/mxsboot
/ncb
/xway-swap-bytes
/*.exe
/easylogo/easylogo
-/env/crc32.c
-/env/fw_printenv
/gdb/gdbcont
/gdb/gdbsend
-/kernel-doc/docproc
# SPDX-License-Identifier: GPL-2.0+
#
-TOOLSUBDIRS = kernel-doc
-
-#
-# Include this after HOSTOS HOSTARCH check
-# so that we can act intelligently.
-#
-include $(TOPDIR)/config.mk
-
#
# toolchains targeting win32 generate .exe files
#
CONFIG_SHA1_CHECK_UB_IMG = y
endif
+subdir-$(HOST_TOOLS_ALL) += easylogo
+subdir-$(HOST_TOOLS_ALL) += gdb
+
# Merge all the different vars for envcrc into one
ENVCRC-$(CONFIG_ENV_IS_EMBEDDED) = y
ENVCRC-$(CONFIG_ENV_IS_IN_DATAFLASH) = y
ENVCRC-$(CONFIG_ENV_IS_IN_SPI_FLASH) = y
CONFIG_BUILD_ENVCRC ?= $(ENVCRC-y)
-# Generated executable files
-BIN_FILES-$(CONFIG_LCD_LOGO) += bmp_logo$(SFX)
-BIN_FILES-$(CONFIG_VIDEO_LOGO) += bmp_logo$(SFX)
-BIN_FILES-$(CONFIG_BUILD_ENVCRC) += envcrc$(SFX)
-BIN_FILES-$(CONFIG_CMD_NET) += gen_eth_addr$(SFX)
-BIN_FILES-$(CONFIG_CMD_LOADS) += img2srec$(SFX)
-BIN_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes$(SFX)
-BIN_FILES-y += dumpimage$(SFX)
-BIN_FILES-y += mkenvimage$(SFX)
-BIN_FILES-y += mkimage$(SFX)
-BIN_FILES-$(CONFIG_EXYNOS5250) += mk$(BOARD)spl$(SFX)
-BIN_FILES-$(CONFIG_EXYNOS5420) += mk$(BOARD)spl$(SFX)
-BIN_FILES-$(CONFIG_MX23) += mxsboot$(SFX)
-BIN_FILES-$(CONFIG_MX28) += mxsboot$(SFX)
-BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX)
-BIN_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX)
-BIN_FILES-$(CONFIG_KIRKWOOD) += kwboot$(SFX)
-BIN_FILES-y += proftool(SFX)
-BIN_FILES-$(CONFIG_STATIC_RELA) += relocate-rela$(SFX)
-
-# Source files which exist outside the tools directory
-EXT_OBJ_FILES-$(CONFIG_BUILD_ENVCRC) += common/env_embedded.o
-EXT_OBJ_FILES-y += common/image.o
-EXT_OBJ_FILES-$(CONFIG_FIT) += common/image-fit.o
-EXT_OBJ_FILES-y += common/image-sig.o
-EXT_OBJ_FILES-y += lib/crc32.o
-EXT_OBJ_FILES-y += lib/md5.o
-EXT_OBJ_FILES-y += lib/sha1.o
-
-# Source files located in the tools directory
-NOPED_OBJ_FILES-y += aisimage.o
-NOPED_OBJ_FILES-y += default_image.o
-NOPED_OBJ_FILES-y += dumpimage.o
-NOPED_OBJ_FILES-y += fit_image.o
-NOPED_OBJ_FILES-y += image-host.o
-NOPED_OBJ_FILES-y += imximage.o
-NOPED_OBJ_FILES-y += kwbimage.o
-NOPED_OBJ_FILES-y += imagetool.o
-NOPED_OBJ_FILES-y += mkenvimage.o
-NOPED_OBJ_FILES-y += mkimage.o
-NOPED_OBJ_FILES-y += mxsimage.o
-NOPED_OBJ_FILES-y += omapimage.o
-NOPED_OBJ_FILES-y += os_support.o
-NOPED_OBJ_FILES-y += pblimage.o
-NOPED_OBJ_FILES-y += proftool.o
-NOPED_OBJ_FILES-y += ublimage.o
-NOPED_OBJ_FILES-y += relocate-rela.o
-OBJ_FILES-$(CONFIG_BUILD_ENVCRC) += envcrc.o
-OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o
-OBJ_FILES-$(CONFIG_CMD_NET) += gen_eth_addr.o
-OBJ_FILES-$(CONFIG_EXYNOS_SPL) += mkexynosspl.o
-OBJ_FILES-$(CONFIG_KIRKWOOD) += kwboot.o
-OBJ_FILES-$(CONFIG_LCD_LOGO) += bmp_logo.o
-OBJ_FILES-$(CONFIG_MX23) += mxsboot.o
-OBJ_FILES-$(CONFIG_MX28) += mxsboot.o
-OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o
-OBJ_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1.o
-OBJ_FILES-$(CONFIG_SMDK5250) += mkexynosspl.o
-OBJ_FILES-$(CONFIG_VIDEO_LOGO) += bmp_logo.o
-OBJ_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes.o
+# TODO: CONFIG_CMD_LICENSE does not work
+hostprogs-$(CONFIG_CMD_LICENSE) += bin2header$(SFX)
-# Don't build by default
-#ifeq ($(ARCH),ppc)
-#BIN_FILES-y += mpc86x_clk$(SFX)
-#OBJ_FILES-y += mpc86x_clk.o
-#endif
+hostprogs-$(CONFIG_LCD_LOGO) += bmp_logo$(SFX)
+hostprogs-$(CONFIG_VIDEO_LOGO) += bmp_logo$(SFX)
+HOSTCFLAGS_bmp_logo$(SFX).o := -pedantic
+
+hostprogs-$(CONFIG_BUILD_ENVCRC) += envcrc$(SFX)
+envcrc$(SFX)-objs := crc32.o env_embedded.o envcrc.o sha1.o
+hostprogs-$(CONFIG_CMD_NET) += gen_eth_addr$(SFX)
+HOSTCFLAGS_gen_eth_addr$(SFX).o := -pedantic
+
+hostprogs-$(CONFIG_CMD_LOADS) += img2srec$(SFX)
+HOSTCFLAGS_img2srec$(SFX).o := -pedantic
+
+hostprogs-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes$(SFX)
+HOSTCFLAGS_xway-swap-bytes$(SFX).o := -pedantic
+
+hostprogs-y += mkenvimage$(SFX)
+mkenvimage$(SFX)-objs := crc32.o mkenvimage.o os_support.o
+
+hostprogs-y += dumpimage$(SFX) mkimage$(SFX)
+
+FIT_SIG_OBJS-$(CONFIG_FIT_SIGNATURE) := image-sig.o
# Flattened device tree objects
-LIBFDT_OBJ_FILES-y += fdt.o
-LIBFDT_OBJ_FILES-y += fdt_ro.o
-LIBFDT_OBJ_FILES-y += fdt_rw.o
-LIBFDT_OBJ_FILES-y += fdt_strerror.o
-LIBFDT_OBJ_FILES-y += fdt_wip.o
+LIBFDT_OBJS := fdt.o fdt_ro.o fdt_rw.o fdt_strerror.o fdt_wip.o
+RSA_OBJS-$(CONFIG_FIT_SIGNATURE) := rsa-sign.o
+
+# common objs for dumpimage and mkimage
+dumpimage-mkimage-objs := aisimage.o \
+ $(FIT_SIG_OBJS-y) \
+ crc32.o \
+ default_image.o \
+ fit_image.o \
+ image-fit.o \
+ image-host.o \
+ image.o \
+ imagetool.o \
+ imximage.o \
+ kwbimage.o \
+ md5.o \
+ mxsimage.o \
+ omapimage.o \
+ os_support.o \
+ pblimage.o \
+ sha1.o \
+ ublimage.o \
+ $(LIBFDT_OBJS) \
+ $(RSA_OBJS-y)
+
+dumpimage$(SFX)-objs := $(dumpimage-mkimage-objs) dumpimage.o
+mkimage$(SFX)-objs := $(dumpimage-mkimage-objs) mkimage.o
+
+# TODO(sjg@chromium.org): Is this correct on Mac OS?
+
+# MXSImage needs LibSSL
+ifneq ($(CONFIG_MX23)$(CONFIG_MX28),)
+HOSTLOADLIBES_dumpimage$(SFX) := -lssl -lcrypto
+HOSTLOADLIBES_mkimage$(SFX) := -lssl -lcrypto
+# Add CONFIG_MXS into host CFLAGS, so we can check whether or not register
+# the mxsimage support within tools/mxsimage.c .
+HOSTCFLAGS_mxsimage.o += -DCONFIG_MXS
+endif
+
+ifdef CONFIG_FIT_SIGNATURE
+HOSTLOADLIBES_dumpimage$(SFX) := -lssl -lcrypto
+HOSTLOADLIBES_mkimage$(SFX) := -lssl -lcrypto
+
+# This affects include/image.h, but including the board config file
+# is tricky, so manually define this options here.
+HOST_EXTRACFLAGS += -DCONFIG_FIT_SIGNATURE
+endif
+
+hostprogs-$(CONFIG_EXYNOS5250) += mkexynosspl$(SFX)
+hostprogs-$(CONFIG_EXYNOS5420) += mkexynosspl$(SFX)
+HOSTCFLAGS_mkexynosspl$(SFX).o := -pedantic
+
+hostprogs-$(CONFIG_MX23) += mxsboot$(SFX)
+hostprogs-$(CONFIG_MX28) += mxsboot$(SFX)
+HOSTCFLAGS_mxsboot$(SFX).o := -pedantic
+
+hostprogs-$(CONFIG_NETCONSOLE) += ncb$(SFX)
+hostprogs-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX)
+
+ubsha1$(SFX)-objs := os_support.o sha1.o ubsha1.o
+
+HOSTCFLAGS_ubsha1.o := -pedantic
+
+hostprogs-$(CONFIG_KIRKWOOD) += kwboot$(SFX)
+hostprogs-y += proftool$(SFX)
+hostprogs-$(CONFIG_STATIC_RELA) += relocate-rela$(SFX)
-# RSA objects
-RSA_OBJ_FILES-$(CONFIG_FIT_SIGNATURE) += rsa-sign.o
+# We build some files with extra pedantic flags to try to minimize things
+# that won't build on some weird host compiler -- though there are lots of
+# exceptions for files that aren't complaint.
+HOSTCFLAGS_crc32.o := -pedantic
+HOSTCFLAGS_md5.o := -pedantic
+HOSTCFLAGS_sha1.o := -pedantic
+
+# Don't build by default
+#hostprogs-$(CONFIG_PPC) += mpc86x_clk$(SFX)
+#HOSTCFLAGS_mpc86x_clk$(SFX).o := -pedantic
+
+always := $(hostprogs-y)
# Generated LCD/video logo
-LOGO_H = $(OBJTREE)/include/bmp_logo.h
-LOGO_DATA_H = $(OBJTREE)/include/bmp_logo_data.h
+LOGO_H = $(objtree)/include/bmp_logo.h
+LOGO_DATA_H = $(objtree)/include/bmp_logo_data.h
LOGO-$(CONFIG_LCD_LOGO) += $(LOGO_H)
LOGO-$(CONFIG_LCD_LOGO) += $(LOGO_DATA_H)
LOGO-$(CONFIG_VIDEO_LOGO) += $(LOGO_H)
# Generic logo
ifeq ($(LOGO_BMP),)
-LOGO_BMP= logos/denx.bmp
+LOGO_BMP= $(srctree)/$(src)/logos/denx.bmp
# Use board logo and fallback to vendor
ifneq ($(wildcard logos/$(BOARD).bmp),)
-LOGO_BMP= logos/$(BOARD).bmp
+LOGO_BMP= $(srctree)/$(src)/logos/$(BOARD).bmp
else
ifneq ($(wildcard logos/$(VENDOR).bmp),)
-LOGO_BMP= logos/$(VENDOR).bmp
+LOGO_BMP= $(srctree)/$(src)/logos/$(VENDOR).bmp
endif
endif
endif # !LOGO_BMP
-# now $(obj) is defined
-HOSTSRCS += $(addprefix $(SRCTREE)/,$(EXT_OBJ_FILES-y:.o=.c))
-HOSTSRCS += $(addprefix $(SRCTREE)/tools/,$(OBJ_FILES-y:.o=.c))
-HOSTSRCS += $(addprefix $(SRCTREE)/lib/libfdt/,$(LIBFDT_OBJ_FILES-y:.o=.c))
-HOSTSRCS += $(addprefix $(SRCTREE)/lib/rsa/,$(RSA_OBJ_FILES-y:.o=.c))
-BINS := $(addprefix $(obj),$(sort $(BIN_FILES-y)))
-LIBFDT_OBJS := $(addprefix $(obj),$(LIBFDT_OBJ_FILES-y))
-RSA_OBJS := $(addprefix $(obj),$(RSA_OBJ_FILES-y))
-
-# We cannot check CONFIG_FIT_SIGNATURE here since it is not set on the host
-FIT_SIG_OBJ_FILES := image-sig.o
-FIT_SIG_OBJS := $(addprefix $(obj),$(FIT_SIG_OBJ_FILES))
-
-HOSTOBJS := $(addprefix $(obj),$(OBJ_FILES-y))
-NOPEDOBJS := $(addprefix $(obj),$(NOPED_OBJ_FILES-y))
-
#
# Use native tools and options
# Define __KERNEL_STRICT_NAMES to prevent typedef overlaps
# Define _GNU_SOURCE to obtain the getline prototype from stdio.h
#
-HOSTCPPFLAGS = -include $(SRCTREE)/include/libfdt_env.h \
- -idirafter $(SRCTREE)/include \
- -idirafter $(SRCTREE)/arch/$(ARCH)/include \
- -idirafter $(OBJTREE)/include \
- -I $(SRCTREE)/lib/libfdt \
- -I $(SRCTREE)/tools \
+HOST_EXTRACFLAGS += -include $(SRCTREE)/include/libfdt_env.h \
+ $(patsubst -I%,-idirafter%, $(UBOOTINCLUDE)) \
+ -I$(SRCTREE)/lib/libfdt \
+ -I$(SRCTREE)/tools \
-DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \
-DUSE_HOSTCC \
-D__KERNEL_STRICT_NAMES \
-D_GNU_SOURCE
+__build: $(LOGO-y)
-all: $(obj).depend $(BINS) $(LOGO-y) subdirs
-
-$(obj)bin2header$(SFX): $(obj)bin2header.o
- $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
- $(HOSTSTRIP) $@
-
-$(obj)bmp_logo$(SFX): $(obj)bmp_logo.o
- $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
- $(HOSTSTRIP) $@
-
-$(obj)proftool(SFX): $(obj)proftool.o
- $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
- $(HOSTSTRIP) $@
-
-$(obj)envcrc$(SFX): $(obj)crc32.o $(obj)env_embedded.o $(obj)envcrc.o $(obj)sha1.o
- $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
-
-$(obj)gen_eth_addr$(SFX): $(obj)gen_eth_addr.o
- $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
- $(HOSTSTRIP) $@
-
-$(obj)img2srec$(SFX): $(obj)img2srec.o
- $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
- $(HOSTSTRIP) $@
-
-$(obj)xway-swap-bytes$(SFX): $(obj)xway-swap-bytes.o
- $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
- $(HOSTSTRIP) $@
-
-$(obj)dumpimage$(SFX): $(obj)aisimage.o \
- $(FIT_SIG_OBJS) \
- $(obj)crc32.o \
- $(obj)default_image.o \
- $(obj)fit_image.o \
- $(obj)image-fit.o \
- $(obj)image.o \
- $(obj)image-host.o \
- $(obj)imagetool.o \
- $(obj)imximage.o \
- $(obj)kwbimage.o \
- $(obj)dumpimage.o \
- $(obj)md5.o \
- $(obj)mxsimage.o \
- $(obj)omapimage.o \
- $(obj)os_support.o \
- $(obj)pblimage.o \
- $(obj)sha1.o \
- $(obj)ublimage.o \
- $(LIBFDT_OBJS) \
- $(RSA_OBJS)
- $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ $(HOSTLIBS)
- $(HOSTSTRIP) $@
-
-$(obj)mkenvimage$(SFX): $(obj)crc32.o $(obj)mkenvimage.o \
- $(obj)os_support.o
- $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
- $(HOSTSTRIP) $@
-
-$(obj)mkimage$(SFX): $(obj)aisimage.o \
- $(FIT_SIG_OBJS) \
- $(obj)crc32.o \
- $(obj)default_image.o \
- $(obj)fit_image.o \
- $(obj)image-fit.o \
- $(obj)image-host.o \
- $(obj)image.o \
- $(obj)imagetool.o \
- $(obj)imximage.o \
- $(obj)kwbimage.o \
- $(obj)md5.o \
- $(obj)mkimage.o \
- $(obj)mxsimage.o \
- $(obj)omapimage.o \
- $(obj)os_support.o \
- $(obj)pblimage.o \
- $(obj)sha1.o \
- $(obj)ublimage.o \
- $(LIBFDT_OBJS) \
- $(RSA_OBJS)
- $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ $(HOSTLIBS)
- $(HOSTSTRIP) $@
-
-$(obj)mk$(BOARD)spl$(SFX): $(obj)mkexynosspl.o
- $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
- $(HOSTSTRIP) $@
-
-$(obj)mpc86x_clk$(SFX): $(obj)mpc86x_clk.o
- $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
- $(HOSTSTRIP) $@
-
-$(obj)mxsboot$(SFX): $(obj)mxsboot.o
- $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
- $(HOSTSTRIP) $@
-
-$(obj)ncb$(SFX): $(obj)ncb.o
- $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
- $(HOSTSTRIP) $@
-
-$(obj)ubsha1$(SFX): $(obj)os_support.o $(obj)sha1.o $(obj)ubsha1.o
- $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
-
-$(obj)kwboot$(SFX): $(obj)kwboot.o
- $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
- $(HOSTSTRIP) $@
-
-$(obj)relocate-rela$(SFX): $(obj)relocate-rela.o
- $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
- $(HOSTSTRIP) $@
-
-# Some of the tool objects need to be accessed from outside the tools directory
-$(obj)%.o: $(SRCTREE)/common/%.c
- $(HOSTCC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $<
-
-$(obj)%.o: $(SRCTREE)/lib/%.c
- $(HOSTCC) -g $(HOSTCFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(SRCTREE)/lib/libfdt/%.c
- $(HOSTCC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $<
-
-$(obj)%.o: $(SRCTREE)/lib/rsa/%.c
- $(HOSTCC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $<
-
-subdirs:
-ifeq ($(TOOLSUBDIRS),)
- @:
-else
- @for dir in $(TOOLSUBDIRS) ; do \
- $(MAKE) \
- HOSTOS=$(HOSTOS) \
- HOSTARCH=$(HOSTARCH) \
- -C $$dir || exit 1 ; \
- done
-endif
-
-$(LOGO_H): $(obj)bmp_logo $(LOGO_BMP)
- $(obj)./bmp_logo --gen-info $(LOGO_BMP) > $@
-
-$(LOGO_DATA_H): $(obj)bmp_logo $(LOGO_BMP)
- $(obj)./bmp_logo --gen-data $(LOGO_BMP) > $@
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
+$(LOGO_H): $(obj)/bmp_logo $(LOGO_BMP)
+ $(obj)/bmp_logo --gen-info $(LOGO_BMP) > $@
-sinclude $(obj).depend
+$(LOGO_DATA_H): $(obj)/bmp_logo $(LOGO_BMP)
+ $(obj)/bmp_logo --gen-data $(LOGO_BMP) > $@
-#########################################################################
+# Let clean descend into subdirs
+subdir- += env
--- /dev/null
+#include "../lib/crc32.c"
-include $(TOPDIR)/config.mk
+hostprogs-y := easylogo
-all: $(obj)easylogo
-
-$(obj)easylogo: $(SRCTREE)/tools/easylogo/easylogo.c
- $(HOSTCC) $(HOSTCFLAGS_NOPED) $(HOSTLDFLAGS) -o $@ $^
-
-clean:
- rm -f $(obj)easylogo
-
-.PHONY: all clean
+always := $(hostprogs-y)
--- /dev/null
+fw_printenv
+fw_printenv_unstripped
# SPDX-License-Identifier: GPL-2.0+
#
-include $(TOPDIR)/config.mk
-
-HOSTSRCS := $(SRCTREE)/lib/crc32.c fw_env.c fw_env_main.c
-HOSTSRCS += $(SRCTREE)/lib/ctype.c $(SRCTREE)/lib/linux_string.c
-HOSTSRCS += $(SRCTREE)/common/env_attr.c $(SRCTREE)/common/env_flags.c
-HEADERS := fw_env.h $(OBJTREE)/include/config.h
+# fw_printenv is supposed to run on the target system, which means it should be
+# built with cross tools. Although it may look weird, we only replace "HOSTCC"
+# with "CC" here for the maximum code reuse of scripts/Makefile.host.
+HOSTCC = $(CC)
# Compile for a hosted environment on the target
-HOSTCPPFLAGS = -idirafter $(SRCTREE)/include \
- -idirafter $(SRCTREE)/arch/$(ARCH)/include \
- -idirafter $(OBJTREE)/include \
+HOST_EXTRACFLAGS = $(patsubst -I%,-idirafter%, $(UBOOTINCLUDE)) \
-idirafter $(SRCTREE)/tools/env \
-DUSE_HOSTCC \
-DTEXT_BASE=$(TEXT_BASE)
ifeq ($(MTD_VERSION),old)
-HOSTCPPFLAGS += -DMTD_OLD
+HOST_EXTRACFLAGS += -DMTD_OLD
endif
-all: $(obj)fw_printenv
-
-# Some files complain if compiled with -pedantic, use HOSTCFLAGS_NOPED
-$(obj)fw_printenv: $(HOSTSRCS) $(HEADERS)
- $(HOSTCC) $(HOSTCFLAGS_NOPED) $(HOSTLDFLAGS) -o $@ $(HOSTSRCS)
- $(HOSTSTRIP) $@
-
-clean:
- rm -f $(obj)fw_printenv
-
-#########################################################################
+always := fw_printenv
+hostprogs-y := fw_printenv_unstripped
-include $(TOPDIR)/rules.mk
+fw_printenv_unstripped-objs := fw_env.o fw_env_main.o \
+ crc32.o ctype.o linux_string.o \
+ env_attr.o env_flags.o
-sinclude $(obj).depend
+quiet_cmd_strip = STRIP $@
+ cmd_strip = $(STRIP) -o $@ $<
-#########################################################################
+$(obj)/fw_printenv: $(obj)/fw_printenv_unstripped FORCE
+ $(call if_changed,strip)
This is a demo implementation of a Linux command line tool to access
the U-Boot's environment variables.
-In the current version, there is an issue in cross-compilation.
In order to cross-compile fw_printenv, run
- make HOSTCC=<your CC cross-compiler> env
+ make CROSS_COMPILE=<your cross-compiler prefix> env
in the root directory of the U-Boot distribution. For example,
- make HOSTCC=arm-linux-gcc env
+ make CROSS_COMPILE=arm-linux- env
For the run-time utility configuration uncomment the line
#define CONFIG_FILE "/etc/fw_env.config"
--- /dev/null
+#include "../../lib/crc32.c"
--- /dev/null
+#include "../../lib/ctype.c"
--- /dev/null
+#include "../../common/env_attr.c"
--- /dev/null
+#include "../../common/env_flags.c"
--- /dev/null
+#include "../../lib/linux_string.c"
--- /dev/null
+#include "../common/env_embedded.c"
--- /dev/null
+#include "../lib/libfdt/fdt.c"
--- /dev/null
+#include "../lib/libfdt/fdt_ro.c"
--- /dev/null
+#include "../lib/libfdt/fdt_rw.c"
--- /dev/null
+#include "../lib/libfdt/fdt_strerror.c"
--- /dev/null
+#include "../lib/libfdt/fdt_wip.c"
# SPDX-License-Identifier: GPL-2.0+
#
-include $(TOPDIR)/config.mk
-
-BINS = gdbsend gdbcont
-
-COBJS = gdbsend.o gdbcont.o error.o remote.o serial.o
-
-HOSTOBJS := $(addprefix $(obj),$(COBJS))
-HOSTSRCS := $(COBJS:.o=.c)
-BINS := $(addprefix $(obj),$(BINS))
+ifneq ($(HOSTOS),cygwin)
+
+# Location of a usable BFD library, where we define "usable" as
+# "built for ${HOST}, supports ${TARGET}". Sensible values are
+# - When cross-compiling: the root of the cross-environment
+# - Linux/ppc (native): /usr
+# - NetBSD/ppc (native): you lose ... (must extract these from the
+# binutils build directory, plus the native and U-Boot include
+# files don't like each other)
+
+ifeq ($(HOSTOS),darwin)
+BFD_ROOT_DIR = /usr/local/tools
+else
+ifeq ($(HOSTARCH),$(ARCH))
+# native
+BFD_ROOT_DIR = /usr
+else
+#BFD_ROOT_DIR = /LinuxPPC/CDK # Linux/i386
+#BFD_ROOT_DIR = /usr/pkg/cross # NetBSD/i386
+BFD_ROOT_DIR = /opt/powerpc
+endif
+endif
#
# Use native tools and options
#
-HOSTCPPFLAGS = -I$(BFD_ROOT_DIR)/include
-
-ifeq ($(HOSTOS),cygwin)
-
-all:
-$(obj).depend:
-
-else # ! CYGWIN
-
-all: $(obj).depend $(BINS)
-
-$(obj)gdbsend: $(obj)gdbsend.o $(obj)error.o $(obj)remote.o $(obj)serial.o
- $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
-
-$(obj)gdbcont: $(obj)gdbcont.o $(obj)error.o $(obj)remote.o $(obj)serial.o
- $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
-
-clean:
- rm -f $(HOSTOBJS)
-
-distclean: clean
- rm -f $(BINS) $(obj)core $(obj)*.bak $(obj).depend
-
-#########################################################################
+HOST_EXTRACFLAGS := -I$(BFD_ROOT_DIR)/include -pedantic
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
+hostprogs-y := gdbsend gdbcont
-sinclude $(obj).depend
+gdbsend-objs := gdbsend.o error.o remote.o serial.o
+gdbcont-objs := gdbcont.o error.o remote.o serial.o
-#########################################################################
+always := $(hostprogs-y)
endif # cygwin
--- /dev/null
+#include "../common/image-fit.c"
--- /dev/null
+#include "../common/image-sig.c"
--- /dev/null
+#include "../common/image.c"
+++ /dev/null
-#
-# Copyright (C) 2012 Marek Vasut <marex@denx.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-all: $(obj)docproc
-
-$(obj)docproc: docproc.c
- $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
- $(HOSTSTRIP) $@
-
-clean:
- rm -rf docproc
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
--- /dev/null
+#include "../lib/md5.c"
}
if (rela_start > rela_end || rela_start < text_base ||
- (rela_end - rela_start) % 24) {
+ (rela_end - rela_start) % sizeof(Elf64_Rela)) {
fprintf(stderr, "%s: bad rela bounds\n", argv[0]);
return 3;
}
--- /dev/null
+#include "../lib/rsa/rsa-sign.c"
+++ /dev/null
-#!/bin/sh
-
-# Adapted from Linux kernel's "Kbuild":
-# commit 1cdf25d704f7951d02a04064c97db547d6021872
-# Author: Christoph Lameter <clameter@sgi.com>
-
-mkdir -p $(dirname $2)
-
-# Default sed regexp - multiline due to syntax constraints
-SED_CMD="/^->/{s:->#\(.*\):/* \1 */:; \
- s:^->\([^ ]*\) [\$#]*\([-0-9]*\) \(.*\):#define \1 (\2) /* \3 */:; \
- s:^->\([^ ]*\) [\$#]*\([^ ]*\) \(.*\):#define \1 \2 /* \3 */:; \
- s:->::; p;}"
-
-(set -e
- echo "#ifndef __ASM_OFFSETS_H__"
- echo "#define __ASM_OFFSETS_H__"
- echo "/*"
- echo " * DO NOT MODIFY."
- echo " *"
- echo " * This file was generated by $(basename $0)"
- echo " *"
- echo " */"
- echo ""
- sed -ne "${SED_CMD}" $1
- echo ""
- echo "#endif" ) > $2
--- /dev/null
+#include "../lib/sha1.c"
projects / karo-tx-uboot.git / commitdiff