/spl/*
/tpl/
+#
+# Generated include files
+#
+/include/config/
/include/generated/
/include/spl-autoconf.mk
/include/tpl-autoconf.mk
VERSION = 2014
PATCHLEVEL = 04
SUBLEVEL =
-EXTRAVERSION = -rc1
+EXTRAVERSION = -rc2
NAME =
# *DOCUMENTATION*
export srctree objtree VPATH
-OBJTREE := $(objtree)
-SPLTREE := $(OBJTREE)/spl
-TPLTREE := $(OBJTREE)/tpl
-SRCTREE := $(srctree)
-TOPDIR := $(SRCTREE)
-export TOPDIR SRCTREE OBJTREE SPLTREE TPLTREE
-
-MKCONFIG := $(SRCTREE)/mkconfig
+MKCONFIG := $(srctree)/mkconfig
export MKCONFIG
# Make sure CDPATH settings don't interfere
UBOOTVERSION = $(VERSION)$(if $(PATCHLEVEL),.$(PATCHLEVEL)$(if $(SUBLEVEL),.$(SUBLEVEL)))$(EXTRAVERSION)
export VERSION PATCHLEVEL SUBLEVEL UBOOTRELEASE UBOOTVERSION
-export ARCH CPU BOARD VENDOR SOC
+export ARCH CPU BOARD VENDOR SOC CPUDIR BOARDDIR
export CONFIG_SHELL HOSTCC HOSTCFLAGS HOSTLDFLAGS CROSS_COMPILE AS LD CC
export CPP AR NM LDR STRIP OBJCOPY OBJDUMP
export MAKE AWK
export DTC CHECK CHECKFLAGS
-export KBUILD_CPPFLAGS NOSTDINC_FLAGS UBOOTINCLUDE
+export KBUILD_CPPFLAGS NOSTDINC_FLAGS UBOOTINCLUDE OBJCOPYFLAGS LDFLAGS
export KBUILD_CFLAGS KBUILD_AFLAGS
# When compiling out-of-tree modules, put MODVERDIR in the module
# that (or fail if absent). Otherwise, search for a linker script in a
# standard location.
-LDSCRIPT_MAKEFILE_DIR = $(dir $(LDSCRIPT))
-
ifndef LDSCRIPT
- #LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds.debug
+ #LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot.lds.debug
ifdef CONFIG_SYS_LDSCRIPT
# need to strip off double quotes
LDSCRIPT := $(srctree)/$(CONFIG_SYS_LDSCRIPT:"%"=%)
# If there is no specified link script, we look in a number of places for it
ifndef LDSCRIPT
ifeq ($(CONFIG_NAND_U_BOOT),y)
- LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
+ LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot-nand.lds
ifeq ($(wildcard $(LDSCRIPT)),)
- LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
+ LDSCRIPT := $(srctree)/$(CPUDIR)/u-boot-nand.lds
endif
endif
ifeq ($(wildcard $(LDSCRIPT)),)
- LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+ LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot.lds
endif
ifeq ($(wildcard $(LDSCRIPT)),)
- LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot.lds
+ LDSCRIPT := $(srctree)/$(CPUDIR)/u-boot.lds
endif
ifeq ($(wildcard $(LDSCRIPT)),)
- LDSCRIPT := $(TOPDIR)/arch/$(ARCH)/cpu/u-boot.lds
- # We don't expect a Makefile here
- LDSCRIPT_MAKEFILE_DIR =
+ LDSCRIPT := $(srctree)/arch/$(ARCH)/cpu/u-boot.lds
endif
endif
# Use UBOOTINCLUDE when you must reference the include/ directory.
# Needed to be compatible with the O= option
-UBOOTINCLUDE :=
-ifneq ($(OBJTREE),$(SRCTREE))
-UBOOTINCLUDE += -I$(OBJTREE)/include
-endif
-UBOOTINCLUDE += -I$(srctree)/include \
+UBOOTINCLUDE := \
+ -Iinclude \
+ $(if $(KBUILD_SRC), -I$(srctree)/include) \
-I$(srctree)/arch/$(ARCH)/include
NOSTDINC_FLAGS += -nostdinc -isystem $(shell $(CC) -print-file-name=include)
CHECKFLAGS += $(NOSTDINC_FLAGS)
# FIX ME
-cpp_flags := $(KBUILD_CPPFLAGS) $(CPPFLAGS) $(UBOOTINCLUDE) $(NOSTDINC_FLAGS)
+cpp_flags := $(KBUILD_CPPFLAGS) $(PLATFORM_CPPFLAGS) $(UBOOTINCLUDE) \
+ $(NOSTDINC_FLAGS)
c_flags := $(KBUILD_CFLAGS) $(cpp_flags)
#########################################################################
libs-y += net/
libs-y += disk/
libs-y += drivers/
+libs-$(CONFIG_DM) += drivers/core/
libs-y += drivers/dma/
libs-y += drivers/gpio/
libs-y += drivers/i2c/
libs-$(CONFIG_API) += api/
libs-$(CONFIG_HAS_POST) += post/
libs-y += test/
+libs-y += test/dm/
+libs-$(CONFIG_DM_DEMO) += drivers/demo/
ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610))
libs-y += arch/$(ARCH)/imx-common/
libs-$(CONFIG_ARM) += arch/arm/cpu/
libs-$(CONFIG_PPC) += arch/powerpc/cpu/
-libs-y += board/$(BOARDDIR)/
+libs-y += $(if $(BOARDDIR),board/$(BOARDDIR)/)
libs-y := $(sort $(libs-y))
# Add GCC lib
-ifdef USE_PRIVATE_LIBGCC
-ifeq ("$(USE_PRIVATE_LIBGCC)", "yes")
-PLATFORM_LIBGCC = $(OBJTREE)/arch/$(ARCH)/lib/lib.a
+ifdef CONFIG_USE_PRIVATE_LIBGCC
+ifeq ($(CONFIG_USE_PRIVATE_LIBGCC),y)
+PLATFORM_LIBGCC = arch/$(ARCH)/lib/lib.a
else
-PLATFORM_LIBGCC = -L $(USE_PRIVATE_LIBGCC) -lgcc
+PLATFORM_LIBGCC = -L $(CONFIG_USE_PRIVATE_LIBGCC) -lgcc
endif
else
PLATFORM_LIBGCC := -L $(shell dirname `$(CC) $(c_flags) -print-libgcc-file-name`) -lgcc
# Pass the version down so we can handle backwards compatibility
# on the fly.
LDPPFLAGS += \
- -include $(TOPDIR)/include/u-boot/u-boot.lds.h \
+ -include $(srctree)/include/u-boot/u-boot.lds.h \
-DCPUDIR=$(CPUDIR) \
$(shell $(LD) --version | \
sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p')
ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img
ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin
ALL-$(CONFIG_OF_SEPARATE) += u-boot.dtb u-boot-dtb.bin
+ALL-$(CONFIG_OF_HOSTFILE) += u-boot.dtb
ifneq ($(CONFIG_SPL_TARGET),)
ALL-$(CONFIG_SPL) += $(CONFIG_SPL_TARGET:"%"=%)
endif
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
-MKIMAGEFLAGS_u-boot.kwb = -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \
- -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE)
+MKIMAGEFLAGS_u-boot.kwb = -n $(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) \
+ -T kwbimage -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE)
-MKIMAGEFLAGS_u-boot.pbl = -n $(CONFIG_SYS_FSL_PBL_RCW) \
- -R $(CONFIG_SYS_FSL_PBL_PBI) -T pblimage
+MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
+ -R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage
u-boot.img u-boot.kwb u-boot.pbl: u-boot.bin FORCE
$(call if_changed,mkimage)
$(call if_changed,pad_cat)
u-boot.sb: u-boot.bin spl/u-boot-spl.bin
- $(Q)$(MAKE) $(build)=arch/arm/cpu/arm926ejs/mxs $(objtree)/u-boot.sb
+ $(Q)$(MAKE) $(build)=arch/arm/cpu/arm926ejs/mxs u-boot.sb
# On x600 (SPEAr600) U-Boot is appended to U-Boot SPL.
# Both images are created using mkimage (crc etc), so that the ROM
LC_ALL=C date +'#define U_BOOT_TIME "%T"')
endef
-$(version_h): $(srctree)/Makefile FORCE
+$(version_h): include/config/uboot.release FORCE
$(call filechk,version.h)
$(timestamp_h): $(srctree)/Makefile FORCE
PHONY += nand_spl
nand_spl: prepare
$(Q)$(MAKE) $(build)=nand_spl/board/$(BOARDDIR) all
+ @echo >&2
+ @echo >&2 "==================== WARNING ====================="
+ @echo >&2 "nand_spl will not be included in v2014.07 release."
+ @echo >&2 "Please switch over to SPL."
+ @echo >&2 "Otherwise, this board will be removed."
+ @echo >&2 "=================================================="
+ @echo >&2
nand_spl/u-boot-spl-16k.bin: nand_spl
@:
System.map: u-boot
@$(call SYSTEM_MAP,$<) > $@
-checkthumb:
- @if test $(call cc-version) -lt 0404; then \
- echo -n '*** Your GCC does not produce working '; \
- echo 'binaries in THUMB mode.'; \
- echo '*** Your board is configured for THUMB mode.'; \
- false; \
- fi
-
-# GCC 3.x is reported to have problems generating the type of relocation
-# that U-Boot wants.
-# See http://lists.denx.de/pipermail/u-boot/2012-September/135156.html
-checkgcc4:
- @if test $(call cc-version) -lt 0400; then \
- echo -n '*** Your GCC is too old, please upgrade to GCC 4.x or newer'; \
- false; \
- fi
-
checkdtc:
@if test $(call dtc-version) -lt 0104; then \
echo '*** Your dtc is too old, please upgrade to dtc 1.4 or newer'; \
env: scripts_basic
$(Q)$(MAKE) $(build)=tools/$@
-tools-all: HOST_TOOLS_ALL=y
+tools-all: export HOST_TOOLS_ALL=y
tools-all: env tools ;
+cross_tools: export CROSS_BUILD_TOOLS=y
+cross_tools: tools ;
+
.PHONY : CHANGELOG
CHANGELOG:
git log --no-merges U-Boot-1_1_5.. | \
# Directories & files removed with 'make clean'
CLEAN_DIRS += $(MODVERDIR)
CLEAN_FILES += u-boot.lds include/bmp_logo.h include/bmp_logo_data.h \
- board/*/config.tmp board/*/*/config.tmp \
include/autoconf.mk* include/spl-autoconf.mk \
include/tpl-autoconf.mk
@find $(srctree) $(RCS_FIND_IGNORE) \
\( -name '*.orig' -o -name '*.rej' -o -name '*~' \
-o -name '*.bak' -o -name '#*#' -o -name '.*.orig' \
- -o -name '.*.rej' \
+ -o -name '.*.rej' -o -name '*.pyc' \
-o -name '*%' -o -name '.*.cmd' -o -name 'core' \) \
-type f -print | xargs rm -f
backup:
- F=`basename $(TOPDIR)` ; cd .. ; \
+ F=`basename $(srctree)` ; cd .. ; \
gtar --force-local -zcvf `LC_ALL=C date "+$$F-%Y-%m-%d-%T.tar.gz"` $$F
help:
Configuration Settings:
-----------------------
+- CONFIG_SYS_SUPPORT_64BIT_DATA: Defined automatically if compiled as 64-bit.
+ Optionally it can be defined to support 64-bit memory commands.
+
- CONFIG_SYS_LONGHELP: Defined when you want long help messages included;
undefine this when you're short of memory.
si->clk_bus = gd->bus_clk;
si->clk_cpu = gd->cpu_clk;
-#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) || \
+#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_MPC8260) || \
defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
#define bi_bar bi_immr_base
#elif defined(CONFIG_MPC5xxx)
endif
ifdef CONFIG_SYS_LITTLE_ENDIAN
-CROSS_COMPILE ?= arc-buildroot-linux-uclibc-
+ARC_CROSS_COMPILE := arc-buildroot-linux-uclibc-
endif
ifdef CONFIG_SYS_BIG_ENDIAN
-CROSS_COMPILE ?= arceb-buildroot-linux-uclibc-
+ARC_CROSS_COMPILE := arceb-buildroot-linux-uclibc-
PLATFORM_LDFLAGS += -EB
endif
-PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -DCONFIG_ARC -gdwarf-2
+ifeq ($(CROSS_COMPILE),)
+CROSS_COMPILE := $(ARC_CROSS_COMPILE)
+endif
-LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
+PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -DCONFIG_ARC -gdwarf-2
# Needed for relocation
LDFLAGS_FINAL += -pie
# SPDX-License-Identifier: GPL-2.0+
#
-CROSS_COMPILE ?= arm-linux-
+ifeq ($(CROSS_COMPILE),)
+CROSS_COMPILE := arm-linux-
+endif
ifndef CONFIG_STANDALONE_LOAD_ADDR
ifneq ($(CONFIG_OMAP_COMMON),)
# Only test once
ifneq ($(CONFIG_SPL_BUILD),y)
-ALL-$(CONFIG_SYS_THUMB_BUILD) += checkthumb
+ifeq ($(CONFIG_SYS_THUMB_BUILD),y)
+archprepare: checkthumb
+
+checkthumb:
+ @if test "$(call cc-version)" -lt "0404"; then \
+ echo -n '*** Your GCC does not produce working '; \
+ echo 'binaries in THUMB mode.'; \
+ echo '*** Your board is configured for THUMB mode.'; \
+ false; \
+ fi
+endif
endif
# Try if EABI is supported, else fall back to old API,
# times. Also, the prefix needs to be different based on whether
# CONFIG_SPL_BUILD is defined or not. 'filter-out' the existing entry
# before adding the correct one.
-ifdef CONFIG_SPL_BUILD
-PLATFORM_LIBS := $(SPLTREE)/arch/arm/lib/eabi_compat.o \
- $(filter-out %/arch/arm/lib/eabi_compat.o, $(PLATFORM_LIBS))
-else
-PLATFORM_LIBS := $(OBJTREE)/arch/arm/lib/eabi_compat.o \
- $(filter-out %/arch/arm/lib/eabi_compat.o, $(PLATFORM_LIBS))
-endif
+PLATFORM_LIBS := arch/arm/lib/eabi_compat.o \
+ $(filter-out arch/arm/lib/eabi_compat.o, $(PLATFORM_LIBS))
endif
# needed for relocation
void halt_avp(void)
{
for (;;) {
- writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \
- | HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)),
- FLOW_CTLR_HALT_COP_EVENTS);
+ writel(HALT_COP_EVENT_JTAG | (FLOW_MODE_STOP << 29),
+ FLOW_CTLR_HALT_COP_EVENTS);
}
}
+++ /dev/null
-#
-# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-USE_PRIVATE_LIBGCC = yes
+++ /dev/null
-#
-# (C) Copyright 2010-2013
-# NVIDIA Corporation <www.nvidia.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#/
-USE_PRIVATE_LIBGCC = yes
tegra124_init_clocks();
/* Set power-gating timer multiplier */
- clrbits_le32(&pmc->pmc_pwrgate_timer_mult, TIMER_MULT_MASK);
- setbits_le32(&pmc->pmc_pwrgate_timer_mult, MULT_8);
+ writel((MULT_8 << TIMER_MULT_SHIFT) | (MULT_8 << TIMER_MULT_CPU_SHIFT),
+ &pmc->pmc_pwrgate_timer_mult);
enable_cpu_power_rail();
enable_cpu_clocks();
+++ /dev/null
-#
-# (C) Copyright 2010,2011
-# NVIDIA Corporation <www.nvidia.com>
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-USE_PRIVATE_LIBGCC = yes
+++ /dev/null
-#
-# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-USE_PRIVATE_LIBGCC = yes
}
#endif
+#if defined(CONFIG_GENERIC_ATMEL_MCI)
+void at91_mci_hw_init(void)
+{
+ /* Enable mci clock */
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ writel(1 << ATMEL_ID_MCI1, &pmc->pcer);
+
+ at91_set_a_periph(AT91_PIO_PORTA, 6, PUP); /* MCI1_CK */
+
+#if defined(CONFIG_ATMEL_MCI_PORTB)
+ at91_set_a_periph(AT91_PIO_PORTA, 21, PUP); /* MCI1_CDB */
+ at91_set_a_periph(AT91_PIO_PORTA, 22, PUP); /* MCI1_DB0 */
+ at91_set_a_periph(AT91_PIO_PORTA, 23, PUP); /* MCI1_DB1 */
+ at91_set_a_periph(AT91_PIO_PORTA, 24, PUP); /* MCI1_DB2 */
+ at91_set_a_periph(AT91_PIO_PORTA, 25, PUP); /* MCI1_DB3 */
+#else
+ at91_set_a_periph(AT91_PIO_PORTA, 7, PUP); /* MCI1_CDA */
+ at91_set_a_periph(AT91_PIO_PORTA, 8, PUP); /* MCI1_DA0 */
+ at91_set_a_periph(AT91_PIO_PORTA, 9, PUP); /* MCI1_DA1 */
+ at91_set_a_periph(AT91_PIO_PORTA, 10, PUP); /* MCI1_DA2 */
+ at91_set_a_periph(AT91_PIO_PORTA, 11, PUP); /* MCI1_DA3 */
+#endif
+}
+#endif
+
#ifdef CONFIG_MACB
void at91_macb_hw_init(void)
{
endif
# Specify the target for use in elftosb call
-MKIMAGE_TARGET-$(CONFIG_MX23) = mx23
-MKIMAGE_TARGET-$(CONFIG_MX28) = mx28
+MKIMAGE_TARGET-$(CONFIG_MX23) = mxsimage.mx23.cfg
+MKIMAGE_TARGET-$(CONFIG_MX28) = mxsimage.mx28.cfg
-$(OBJTREE)/mxsimage.cfg: $(SRCTREE)/$(CPUDIR)/$(SOC)/mxsimage.$(MKIMAGE_TARGET-y).cfg
- sed "s@OBJTREE@$(OBJTREE)@g" $^ > $@
+quiet_cmd_mkimage_mxs = UIMAGE $@
+cmd_mkimage_mxs = $(objtree)/tools/mkimage -n $< -T mxsimage $@ \
+ $(if $(KBUILD_VERBOSE:1=), >/dev/null)
-$(OBJTREE)/u-boot.sb: $(OBJTREE)/u-boot.bin $(OBJTREE)/spl/u-boot-spl.bin $(OBJTREE)/mxsimage.cfg
- $(OBJTREE)/tools/mkimage -n $(OBJTREE)/mxsimage.cfg -T mxsimage $@
+u-boot.sb: $(src)/$(MKIMAGE_TARGET-y) u-boot.bin spl/u-boot-spl.bin FORCE
+ $(call if_changed,mkimage_mxs)
SECTION 0x0 BOOTABLE
TAG LAST
- LOAD 0x1000 OBJTREE/spl/u-boot-spl.bin
+ LOAD 0x1000 spl/u-boot-spl.bin
CALL 0x1000 0x0
- LOAD 0x40002000 OBJTREE/u-boot.bin
+ LOAD 0x40002000 u-boot.bin
CALL 0x40002000 0x0
SECTION 0x0 BOOTABLE
TAG LAST
- LOAD 0x1000 OBJTREE/spl/u-boot-spl.bin
+ LOAD 0x1000 spl/u-boot-spl.bin
LOAD IVT 0x8000 0x1000
CALL HAB 0x8000 0x0
- LOAD 0x40002000 OBJTREE/u-boot.bin
+ LOAD 0x40002000 u-boot.bin
LOAD IVT 0x8000 0x40002000
CALL HAB 0x8000 0x0
}
sources {
- u_boot_spl="OBJTREE/spl/u-boot-spl.bin";
- u_boot="OBJTREE/u-boot.bin";
+ u_boot_spl="spl/u-boot-spl.bin";
+ u_boot="u-boot.bin";
}
section (0) {
sources {
- u_boot_spl="OBJTREE/spl/u-boot-spl.bin";
- u_boot="OBJTREE/u-boot.bin";
+ u_boot_spl="spl/u-boot-spl.bin";
+ u_boot="u-boot.bin";
}
section (0) {
}
#endif
+#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
void s_init(void)
{
/*
#ifdef CONFIG_SPL_BUILD
save_omap_boot_params();
#endif
-#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
watchdog_disable();
timer_init();
set_uart_mux_conf();
setup_clocks_for_console();
uart_soft_reset();
-#endif
#ifdef CONFIG_NOR_BOOT
gd->baudrate = CONFIG_BAUDRATE;
serial_init();
gd->have_console = 1;
-#else
+#elif defined(CONFIG_SPL_BUILD)
gd = &gdata;
preloader_console_init();
#endif
-#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
prcm_init();
set_mux_conf_regs();
#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
rtc32k_enable();
#endif
sdram_init();
-#endif
}
+#endif
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
start = 4;
count = 2;
break;
+ default:
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return;
}
for (i = start; i < start + count; i++) {
s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
start = 4;
count = 2;
break;
+ default:
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return;
}
for (i = start; i < start + count; i++) {
bank = &gpio1->c4;
bank_ext = NULL;
break;
+ default:
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return -1;
}
if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
debug("SDMMC device %d does not support 8bit mode",
start = 4;
count = 2;
break;
+ default:
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return;
}
for (i = start; i < start + count; i++) {
s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
}
#ifdef CONFIG_OF_CONTROL
+static int exynos4_pinmux_decode_periph_id(const void *blob, int node)
+{
+ int err;
+ u32 cell[3];
+
+ err = fdtdec_get_int_array(blob, node, "interrupts", cell,
+ ARRAY_SIZE(cell));
+ if (err) {
+ debug(" invalid peripheral id\n");
+ return PERIPH_ID_NONE;
+ }
+
+ return cell[1];
+}
+
static int exynos5_pinmux_decode_periph_id(const void *blob, int node)
{
int err;
{
if (cpu_is_exynos5())
return exynos5_pinmux_decode_periph_id(blob, node);
+ else if (cpu_is_exynos4())
+ return exynos4_pinmux_decode_periph_id(blob, node);
else
return PERIPH_ID_NONE;
}
*/
#include <common.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
#include <common.h>
#include <spl.h>
#include <asm/arch/sys_proto.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#include <asm/emif.h>
#include <asm/omap_common.h>
#include <linux/compiler.h>
#include <asm/armv7.h>
#include <asm/arch/cpu.h>
#include <asm/arch/sys_proto.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#include <asm/emif.h>
#include <asm/arch/gpio.h>
#include <asm/omap_common.h>
#include <asm/arch/cpu.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/clock.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#include <asm/utils.h>
#include <asm/arch/gpio.h>
#include <asm/emif.h>
#include <common.h>
#include <asm/io.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <watchdog.h>
{
#ifdef CONFIG_SYS_USE_MMC
return BOOT_DEVICE_MMC1;
+#elif CONFIG_SYS_USE_NANDFLASH
+ return BOOT_DEVICE_NAND;
+#elif CONFIG_SYS_USE_SERIALFLASH
+ return BOOT_DEVICE_SPI;
#endif
return BOOT_DEVICE_NONE;
}
+dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
+ exynos4210-universal_c210.dtb \
+ exynos4210-trats.dtb \
+ exynos4412-trats2.dtb
+
dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
exynos5250-snow.dtb \
exynos5250-smdk5250.dtb \
--- /dev/null
+/*
+ * Samsung's Exynos4 SoC common device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ serial@13800000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x13800000 0x3c>;
+ id = <0>;
+ };
+
+ serial@13810000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x13810000 0x3c>;
+ id = <1>;
+ };
+
+ serial@13820000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x13820000 0x3c>;
+ id = <2>;
+ };
+
+ serial@13830000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x13830000 0x3c>;
+ id = <3>;
+ };
+
+ serial@13840000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x13840000 0x3c>;
+ id = <4>;
+ };
+
+ i2c@13860000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ interrupts = <0 0 0>;
+ };
+
+ i2c@13870000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ interrupts = <1 1 0>;
+ };
+
+ i2c@13880000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ interrupts = <2 2 0>;
+ };
+
+ i2c@13890000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ interrupts = <3 3 0>;
+ };
+
+ i2c@138a0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ interrupts = <4 4 0>;
+ };
+
+ i2c@138b0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ interrupts = <5 5 0>;
+ };
+
+ i2c@138c0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ interrupts = <6 6 0>;
+ };
+
+ i2c@138d0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ interrupts = <7 7 0>;
+ };
+
+ sdhci@12510000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos-mmc";
+ reg = <0x12510000 0x1000>;
+ interrupts = <0 75 0>;
+ };
+
+ sdhci@12520000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos-mmc";
+ reg = <0x12520000 0x1000>;
+ interrupts = <0 76 0>;
+ };
+
+ sdhci@12530000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos-mmc";
+ reg = <0x12530000 0x1000>;
+ interrupts = <0 77 0>;
+ };
+
+ sdhci@12540000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos-mmc";
+ reg = <0x12540000 0x1000>;
+ interrupts = <0 78 0>;
+ };
+
+ gpio: gpio {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
--- /dev/null
+/*
+ * Samsung's Exynos4210 based Origen board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "skeleton.dtsi"
+/include/ "exynos4.dtsi"
+
+/ {
+ model = "Insignal Origen evaluation board based on Exynos4210";
+ compatible = "insignal,origen", "samsung,exynos4210";
+
+ chosen {
+ bootargs ="";
+ };
+
+ aliases {
+ serial0 = "/serial@13800000";
+ console = "/serial@13820000";
+ mmc2 = "sdhci@12530000";
+ };
+
+ sdhci@12510000 {
+ status = "disabled";
+ };
+
+ sdhci@12520000 {
+ status = "disabled";
+ };
+
+ sdhci@12530000 {
+ samsung,bus-width = <4>;
+ samsung,timing = <1 2 3>;
+ cd-gpios = <&gpio 0x2008002 0>;
+ };
+
+ sdhci@12540000 {
+ status = "disabled";
+ };
+};
\ No newline at end of file
--- /dev/null
+/*
+ * Samsung's Exynos4210 based Trats board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "exynos4.dtsi"
+
+/ {
+ model = "Samsung Trats based on Exynos4210";
+ compatible = "samsung,trats", "samsung,exynos4210";
+
+ config {
+ samsung,dsim-device-name = "s6e8ax0";
+ };
+
+ aliases {
+ i2c0 = "/i2c@13860000";
+ i2c1 = "/i2c@13870000";
+ i2c2 = "/i2c@13880000";
+ i2c3 = "/i2c@13890000";
+ i2c4 = "/i2c@138a0000";
+ i2c5 = "/i2c@138b0000";
+ i2c6 = "/i2c@138c0000";
+ i2c7 = "/i2c@138d0000";
+ serial0 = "/serial@13800000";
+ console = "/serial@13820000";
+ mmc0 = "sdhci@12510000";
+ mmc2 = "sdhci@12530000";
+ };
+
+ fimd@11c00000 {
+ compatible = "samsung,exynos-fimd";
+ reg = <0x11c00000 0xa4>;
+
+ samsung,vl-freq = <60>;
+ samsung,vl-col = <720>;
+ samsung,vl-row = <1280>;
+ samsung,vl-width = <720>;
+ samsung,vl-height = <1280>;
+
+ samsung,vl-clkp = <0>;
+ samsung,vl-oep = <0>;
+ samsung,vl-hsp = <1>;
+ samsung,vl-vsp = <1>;
+ samsung,vl-dp = <1>;
+ samsung,vl-bpix = <4>;
+
+ samsung,vl-hspw = <5>;
+ samsung,vl-hbpd = <10>;
+ samsung,vl-hfpd = <10>;
+ samsung,vl-vspw = <2>;
+ samsung,vl-vbpd = <1>;
+ samsung,vl-vfpd = <13>;
+ samsung,vl-cmd-allow-len = <0xf>;
+
+ samsung,winid = <3>;
+ samsung,power-on-delay = <30>;
+ samsung,interface-mode = <1>;
+ samsung,mipi-enabled = <1>;
+ samsung,dp-enabled;
+ samsung,dual-lcd-enabled;
+
+ samsung,logo-on = <1>;
+ samsung,resolution = <0>;
+ samsung,rgb-mode = <0>;
+ };
+
+ mipidsi@11c80000 {
+ compatible = "samsung,exynos-mipi-dsi";
+ reg = <0x11c80000 0x5c>;
+
+ samsung,dsim-config-e-interface = <1>;
+ samsung,dsim-config-e-virtual-ch = <0>;
+ samsung,dsim-config-e-pixel-format = <7>;
+ samsung,dsim-config-e-burst-mode = <1>;
+ samsung,dsim-config-e-no-data-lane = <3>;
+ samsung,dsim-config-e-byte-clk = <0>;
+ samsung,dsim-config-hfp = <1>;
+
+ samsung,dsim-config-p = <3>;
+ samsung,dsim-config-m = <120>;
+ samsung,dsim-config-s = <1>;
+
+ samsung,dsim-config-pll-stable-time = <500>;
+ samsung,dsim-config-esc-clk = <20000000>;
+ samsung,dsim-config-stop-holding-cnt = <0x7ff>;
+ samsung,dsim-config-bta-timeout = <0xff>;
+ samsung,dsim-config-rx-timeout = <0xffff>;
+
+ samsung,dsim-device-id = <0xffffffff>;
+ samsung,dsim-device-bus-id = <0>;
+
+ samsung,dsim-device-reverse-panel = <1>;
+ };
+
+ sdhci@12510000 {
+ samsung,bus-width = <8>;
+ samsung,timing = <1 3 3>;
+ pwr-gpios = <&gpio 0x2008002 0>;
+ };
+
+ sdhci@12520000 {
+ status = "disabled";
+ };
+
+ sdhci@12530000 {
+ samsung,bus-width = <4>;
+ samsung,timing = <1 2 3>;
+ cd-gpios = <&gpio 0x20c6004 0>;
+ };
+
+ sdhci@12540000 {
+ status = "disabled";
+ };
+};
\ No newline at end of file
--- /dev/null
+/*
+ * Samsung's Exynos4210 based Universal C210 board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "exynos4.dtsi"
+
+/ {
+ model = "Samsung Universal C210 based on Exynos4210 rev0";
+ compatible = "samsung,universal_c210", "samsung,exynos4210";
+
+ aliases {
+ serial0 = "/serial@13800000";
+ console = "/serial@13820000";
+ mmc0 = "sdhci@12510000";
+ mmc2 = "sdhci@12530000";
+ };
+
+ sdhci@12510000 {
+ samsung,bus-width = <8>;
+ samsung,timing = <1 3 3>;
+ pwr-gpios = <&gpio 0x2008002 0>;
+ };
+
+ sdhci@12520000 {
+ status = "disabled";
+ };
+
+ sdhci@12530000 {
+ samsung,bus-width = <4>;
+ samsung,timing = <1 2 3>;
+ cd-gpios = <&gpio 0x20c6004 0>;
+ };
+
+ sdhci@12540000 {
+ status = "disabled";
+ };
+
+ fimd@11c00000 {
+ compatible = "samsung,exynos-fimd";
+ reg = <0x11c00000 0xa4>;
+
+ samsung,vl-freq = <60>;
+ samsung,vl-col = <480>;
+ samsung,vl-row = <800>;
+ samsung,vl-width = <480>;
+ samsung,vl-height = <800>;
+
+ samsung,vl-clkp = <0>;
+ samsung,vl-oep = <0>;
+ samsung,vl-hsp = <1>;
+ samsung,vl-vsp = <1>;
+ samsung,vl-dp = <1>;
+ samsung,vl-bpix = <4>;
+
+ samsung,vl-hspw = <2>;
+ samsung,vl-hbpd = <16>;
+ samsung,vl-hfpd = <16>;
+ samsung,vl-vspw = <2>;
+ samsung,vl-vbpd = <8>;
+ samsung,vl-vfpd = <8>;
+ samsung,vl-cmd-allow-len = <0xf>;
+
+ samsung,pclk_name = <1>;
+ samsung,sclk_div = <1>;
+
+ samsung,winid = <0>;
+ samsung,power-on-delay = <10000>;
+ samsung,interface-mode = <1>;
+ samsung,mipi-enabled = <0>;
+ samsung,dp-enabled;
+ samsung,dual-lcd-enabled;
+
+ samsung,logo-on = <1>;
+ samsung,resolution = <0>;
+ samsung,rgb-mode = <0>;
+ };
+};
--- /dev/null
+/*
+ * Samsung's Exynos4412 based Trats2 board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "exynos4.dtsi"
+
+/ {
+ model = "Samsung Trats2 based on Exynos4412";
+ compatible = "samsung,trats2", "samsung,exynos4412";
+
+ config {
+ samsung,dsim-device-name = "s6e8ax0";
+ };
+
+ aliases {
+ i2c0 = "/i2c@13860000";
+ i2c1 = "/i2c@13870000";
+ i2c2 = "/i2c@13880000";
+ i2c3 = "/i2c@13890000";
+ i2c4 = "/i2c@138a0000";
+ i2c5 = "/i2c@138b0000";
+ i2c6 = "/i2c@138c0000";
+ i2c7 = "/i2c@138d0000";
+ serial0 = "/serial@13800000";
+ console = "/serial@13820000";
+ mmc0 = "sdhci@12510000";
+ mmc2 = "sdhci@12530000";
+ };
+
+ i2c@138d0000 {
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-slave-addr = <0x10>;
+ samsung,i2c-max-bus-freq = <100000>;
+ status = "okay";
+
+ max77686_pmic@09 {
+ compatible = "maxim,max77686_pmic";
+ interrupts = <7 0>;
+ reg = <0x09 0 0>;
+ #clock-cells = <1>;
+
+ voltage-regulators {
+ ldo1_reg: ldo1 {
+ regulator-compatible = "LDO1";
+ regulator-name = "VALIVE_1.0V_AP";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo2_reg: ldo2 {
+ regulator-compatible = "LDO2";
+ regulator-name = "VM1M2_1.2V_AP";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo3_reg: ldo3 {
+ regulator-compatible = "LDO3";
+ regulator-name = "VCC_1.8V_AP";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo4_reg: ldo4 {
+ regulator-compatible = "LDO4";
+ regulator-name = "VCC_2.8V_AP";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo5_reg: ldo5 {
+ regulator-compatible = "LDO5";
+ regulator-name = "VCC_1.8V_IO";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo6_reg: ldo6 {
+ regulator-compatible = "LDO6";
+ regulator-name = "VMPLL_1.0V_AP";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo7_reg: ldo7 {
+ regulator-compatible = "LDO7";
+ regulator-name = "VPLL_1.0V_AP";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo8_reg: ldo8 {
+ regulator-compatible = "LDO8";
+ regulator-name = "VMIPI_1.0V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-mem-off;
+ };
+
+ ldo9_reg: ldo9 {
+ regulator-compatible = "LDO9";
+ regulator-name = "CAM_ISP_MIPI_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-mem-idle;
+ };
+
+ ldo10_reg: ldo10 {
+ regulator-compatible = "LDO10";
+ regulator-name = "VMIPI_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-off;
+ };
+
+ ldo11_reg: ldo11 {
+ regulator-compatible = "LDO11";
+ regulator-name = "VABB1_1.95V";
+ regulator-min-microvolt = <1950000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-always-on;
+ regulator-mem-off;
+ };
+
+ ldo12_reg: ldo12 {
+ regulator-compatible = "LDO12";
+ regulator-name = "VUOTG_3.0V";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-mem-off;
+ };
+
+ ldo13_reg: ldo13 {
+ regulator-compatible = "LDO13";
+ regulator-name = "NFC_AVDD_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-idle;
+ };
+
+ ldo14_reg: ldo14 {
+ regulator-compatible = "LDO14";
+ regulator-name = "VABB2_1.95V";
+ regulator-min-microvolt = <1950000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-always-on;
+ regulator-mem-off;
+ };
+
+ ldo15_reg: ldo15 {
+ regulator-compatible = "LDO15";
+ regulator-name = "VHSIC_1.0V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-mem-off;
+ };
+
+ ldo16_reg: ldo16 {
+ regulator-compatible = "LDO16";
+ regulator-name = "VHSIC_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-off;
+ };
+
+ ldo17_reg: ldo17 {
+ regulator-compatible = "LDO17";
+ regulator-name = "CAM_SENSOR_CORE_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-mem-idle;
+ };
+
+ ldo18_reg: ldo18 {
+ regulator-compatible = "LDO18";
+ regulator-name = "CAM_ISP_SEN_IO_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-idle;
+ };
+
+ ldo19_reg: ldo19 {
+ regulator-compatible = "LDO19";
+ regulator-name = "VT_CAM_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-idle;
+ };
+
+ ldo20_reg: ldo20 {
+ regulator-compatible = "LDO20";
+ regulator-name = "VDDQ_PRE_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-idle;
+ };
+
+ ldo21_reg: ldo21 {
+ regulator-compatible = "LDO21";
+ regulator-name = "VTF_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-mem-idle;
+ };
+
+ ldo22_reg: ldo22 {
+ regulator-compatible = "LDO22";
+ regulator-name = "VMEM_VDD_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ regulator-mem-off;
+ };
+
+ ldo23_reg: ldo23 {
+ regulator-compatible = "LDO23";
+ regulator-name = "TSP_AVDD_3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-mem-idle;
+ };
+
+ ldo24_reg: ldo24 {
+ regulator-compatible = "LDO24";
+ regulator-name = "TSP_VDD_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-idle;
+ };
+
+ ldo25_reg: ldo25 {
+ regulator-compatible = "LDO25";
+ regulator-name = "LCD_VCC_3.3V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-mem-idle;
+ };
+
+ ldo26_reg: ldo26 {
+ regulator-compatible = "LDO26";
+ regulator-name = "MOTOR_VCC_3.0V";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-mem-idle;
+ };
+
+ buck1_reg: buck1 {
+ regulator-compatible = "BUCK1";
+ regulator-name = "vdd_mif";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-mem-off;
+ };
+
+ buck2_reg: buck2 {
+ regulator-compatible = "BUCK2";
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-mem-off;
+ };
+
+ buck3_reg: buck3 {
+ regulator-compatible = "BUCK3";
+ regulator-name = "vdd_int";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-mem-off;
+ };
+
+ buck4_reg: buck4 {
+ regulator-compatible = "BUCK4";
+ regulator-name = "vdd_g3d";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-mem-off;
+ };
+
+ buck5_reg: buck5 {
+ regulator-compatible = "BUCK5";
+ regulator-name = "VMEM_1.2V_AP";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ buck6_reg: buck6 {
+ regulator-compatible = "BUCK6";
+ regulator-name = "VCC_SUB_1.35V";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ };
+
+ buck7_reg: buck7 {
+ regulator-compatible = "BUCK7";
+ regulator-name = "VCC_SUB_2.0V";
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-always-on;
+ };
+
+ buck8_reg: buck8 {
+ regulator-compatible = "BUCK8";
+ regulator-name = "VMEM_VDDF_3.0V";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ regulator-mem-off;
+ };
+
+ buck9_reg: buck9 {
+ regulator-compatible = "BUCK9";
+ regulator-name = "CAM_ISP_CORE_1.2V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-mem-off;
+ };
+ };
+ };
+ };
+
+ fimd@11c00000 {
+ compatible = "samsung,exynos-fimd";
+ reg = <0x11c00000 0xa4>;
+
+ samsung,vl-freq = <60>;
+ samsung,vl-col = <720>;
+ samsung,vl-row = <1280>;
+ samsung,vl-width = <720>;
+ samsung,vl-height = <1280>;
+
+ samsung,vl-clkp = <0>;
+ samsung,vl-oep = <0>;
+ samsung,vl-hsp = <1>;
+ samsung,vl-vsp = <1>;
+ samsung,vl-dp = <1>;
+ samsung,vl-bpix = <4>;
+
+ samsung,vl-hspw = <5>;
+ samsung,vl-hbpd = <10>;
+ samsung,vl-hfpd = <10>;
+ samsung,vl-vspw = <2>;
+ samsung,vl-vbpd = <1>;
+ samsung,vl-vfpd = <13>;
+ samsung,vl-cmd-allow-len = <0xf>;
+
+ samsung,winid = <0>;
+ samsung,power-on-delay = <30>;
+ samsung,interface-mode = <1>;
+ samsung,mipi-enabled = <1>;
+ samsung,dp-enabled;
+ samsung,dual-lcd-enabled;
+
+ samsung,logo-on = <1>;
+ samsung,resolution = <0>;
+ samsung,rgb-mode = <0>;
+ };
+
+ mipidsi@11c80000 {
+ compatible = "samsung,exynos-mipi-dsi";
+ reg = <0x11c80000 0x5c>;
+
+ samsung,dsim-config-e-interface = <1>;
+ samsung,dsim-config-e-virtual-ch = <0>;
+ samsung,dsim-config-e-pixel-format = <7>;
+ samsung,dsim-config-e-burst-mode = <1>;
+ samsung,dsim-config-e-no-data-lane = <3>;
+ samsung,dsim-config-e-byte-clk = <0>;
+ samsung,dsim-config-hfp = <1>;
+
+ samsung,dsim-config-p = <3>;
+ samsung,dsim-config-m = <120>;
+ samsung,dsim-config-s = <1>;
+
+ samsung,dsim-config-pll-stable-time = <500>;
+ samsung,dsim-config-esc-clk = <20000000>;
+ samsung,dsim-config-stop-holding-cnt = <0x7ff>;
+ samsung,dsim-config-bta-timeout = <0xff>;
+ samsung,dsim-config-rx-timeout = <0xffff>;
+
+ samsung,dsim-device-id = <0xffffffff>;
+ samsung,dsim-device-bus-id = <0>;
+
+ samsung,dsim-device-reverse-panel = <1>;
+ };
+
+ sdhci@12510000 {
+ samsung,bus-width = <8>;
+ samsung,timing = <1 3 3>;
+ pwr-gpios = <&gpio 0x2004002 0>;
+ };
+
+ sdhci@12520000 {
+ status = "disabled";
+ };
+
+ sdhci@12530000 {
+ samsung,bus-width = <4>;
+ samsung,timing = <1 2 3>;
+ cd-gpios = <&gpio 0x20C6004 0>;
+ };
+
+ sdhci@12540000 {
+ status = "disabled";
+ };
+};
#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
-struct gpmc_cs {
- u32 config1; /* 0x00 */
- u32 config2; /* 0x04 */
- u32 config3; /* 0x08 */
- u32 config4; /* 0x0C */
- u32 config5; /* 0x10 */
- u32 config6; /* 0x14 */
- u32 config7; /* 0x18 */
- u32 nand_cmd; /* 0x1C */
- u32 nand_adr; /* 0x20 */
- u32 nand_dat; /* 0x24 */
- u8 res[8]; /* blow up to 0x30 byte */
-};
-
-struct bch_res_0_3 {
- u32 bch_result_x[4];
-};
-
-struct gpmc {
- u8 res1[0x10];
- u32 sysconfig; /* 0x10 */
- u8 res2[0x4];
- u32 irqstatus; /* 0x18 */
- u32 irqenable; /* 0x1C */
- u8 res3[0x20];
- u32 timeout_control; /* 0x40 */
- u8 res4[0xC];
- u32 config; /* 0x50 */
- u32 status; /* 0x54 */
- u8 res5[0x8]; /* 0x58 */
- struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */
- u8 res6[0x14]; /* 0x1E0 */
- u32 ecc_config; /* 0x1F4 */
- u32 ecc_control; /* 0x1F8 */
- u32 ecc_size_config; /* 0x1FC */
- u32 ecc1_result; /* 0x200 */
- u32 ecc2_result; /* 0x204 */
- u32 ecc3_result; /* 0x208 */
- u32 ecc4_result; /* 0x20C */
- u32 ecc5_result; /* 0x210 */
- u32 ecc6_result; /* 0x214 */
- u32 ecc7_result; /* 0x218 */
- u32 ecc8_result; /* 0x21C */
- u32 ecc9_result; /* 0x220 */
- u8 res7[12]; /* 0x224 */
- u32 testmomde_ctrl; /* 0x230 */
- u8 res8[12]; /* 0x234 */
- struct bch_res_0_3 bch_result_0_3[2]; /* 0x240 */
-};
-/* Used for board specific gpmc initialization */
-extern struct gpmc *gpmc_cfg;
#ifndef CONFIG_AM43XX
/* Encapsulating core pll registers */
+++ /dev/null
-/*
- * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
- * Rohit Choraria <rohitkc@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __ASM_ARCH_OMAP_GPMC_H
-#define __ASM_ARCH_OMAP_GPMC_H
-
-/* These GPMC_NAND_HW_BCHx_ECC_LAYOUT defines are based on AM33xx ELM */
-#define GPMC_NAND_HW_BCH4_ECC_LAYOUT {\
- .eccbytes = 32,\
- .eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
- 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
- 28, 29, 30, 31, 32, 33},\
- .oobfree = {\
- {.offset = 34,\
- .length = 30 } } \
-}
-
-#define GPMC_NAND_HW_BCH8_ECC_LAYOUT {\
- .eccbytes = 56,\
- .eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
- 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
- 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\
- 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,\
- 52, 53, 54, 55, 56, 57},\
- .oobfree = {\
- {.offset = 58,\
- .length = 6 } } \
-}
-
-#define GPMC_NAND_HW_BCH16_ECC_LAYOUT {\
- .eccbytes = 104,\
- .eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
- 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
- 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\
- 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,\
- 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,\
- 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,\
- 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,\
- 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,\
- 100, 101, 102, 103, 104, 105},\
- .oobfree = {\
- {.offset = 106,\
- .length = 8 } } \
-}
-#endif /* __ASM_ARCH_OMAP_GPMC_H */
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
+#include <linux/mtd/omap_gpmc.h>
#include <asm/arch/cpu.h>
#define BOARD_REV_ID 0x0
/* The following macros are need for backward compatibility */
#define at91_set_GPIO_periph(x, y) \
- at91_set_gpio_periph((x - PIN_BASE) / 32,(x % 32), y)
+ at91_set_pio_periph((x - PIN_BASE) / 32,(x % 32), y)
#define at91_set_A_periph(x, y) \
at91_set_a_periph((x - PIN_BASE) / 32,(x % 32), y)
#define at91_set_B_periph(x, y) \
BOOT_DEVICE_MMC1,
BOOT_DEVICE_MMC2,
BOOT_DEVICE_MMC2_2,
+#elif CONFIG_SYS_USE_NANDFLASH
+ BOOT_DEVICE_NAND,
+#elif CONFIG_SYS_USE_SERIALFLASH
+ BOOT_DEVICE_SPI,
#endif
};
#define __ASM_ARCH_HARDWARE_H
#include <config.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#define REG(addr) (*(volatile unsigned int *)(addr))
#define REG_P(addr) ((volatile unsigned int *)(addr))
*/
int exynos_init(void);
+/*
+ * Exynos board specific changes for
+ * board_early_init_f
+ */
+int exynos_early_init_f(void);
+
+/*
+ * Exynos board specific changes for
+ * board_power_init
+ */
+int exynos_power_init(void);
+
#endif /* EXYNOS_BOARD_H */
#include <linux/list.h>
#include <linux/fb.h>
+#include <lcd.h>
#define PANEL_NAME_SIZE (32)
*lcd_dev);
void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd);
+void exynos_init_dsim_platform_data(vidinfo_t *vid);
/* panel driver init based on mipi dsi interface */
void s6e8ax0_init(void);
+#ifdef CONFIG_OF_CONTROL
+extern int mipi_power(void);
+#endif
#endif /* _DSIM_H */
#define SDHCI_CTRL4_DRIVE_MASK(_x) ((_x) << 16)
#define SDHCI_CTRL4_DRIVE_SHIFT (16)
+#define SDHCI_MAX_HOSTS 4
+
int s5p_sdhci_init(u32 regbase, int index, int bus_width);
static inline int s5p_mmc_init(int index, int bus_width)
return s5p_sdhci_init(base, index, bus_width);
}
+
+#ifdef CONFIG_OF_CONTROL
+int exynos_mmc_init(const void *blob);
+#endif
+
#endif
* CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
*/
#ifndef CONFIG_SYS_KWD_CONFIG
-#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.cfg
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
#endif /* CONFIG_SYS_KWD_CONFIG */
/* Kirkwood has 2k of Security SRAM, use it for SP */
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#include <asm/arch/mb86r0x.h>
#endif
#define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0)
#ifndef __KERNEL_STRICT_NAMES
-#ifndef __ASSEMBLY__
-struct gpmc_cs {
- u32 config1; /* 0x00 */
- u32 config2; /* 0x04 */
- u32 config3; /* 0x08 */
- u32 config4; /* 0x0C */
- u32 config5; /* 0x10 */
- u32 config6; /* 0x14 */
- u32 config7; /* 0x18 */
- u32 nand_cmd; /* 0x1C */
- u32 nand_adr; /* 0x20 */
- u32 nand_dat; /* 0x24 */
- u8 res[8]; /* blow up to 0x30 byte */
-};
-
-struct bch_res_0_3 {
- u32 bch_result_x[4];
-};
-
-struct gpmc {
- u8 res1[0x10];
- u32 sysconfig; /* 0x10 */
- u8 res2[0x4];
- u32 irqstatus; /* 0x18 */
- u32 irqenable; /* 0x1C */
- u8 res3[0x20];
- u32 timeout_control; /* 0x40 */
- u8 res4[0xC];
- u32 config; /* 0x50 */
- u32 status; /* 0x54 */
- u8 res5[0x8]; /* 0x58 */
- struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */
- u8 res6[0x14]; /* 0x1E0 */
- u32 ecc_config; /* 0x1F4 */
- u32 ecc_control; /* 0x1F8 */
- u32 ecc_size_config; /* 0x1FC */
- u32 ecc1_result; /* 0x200 */
- u32 ecc2_result; /* 0x204 */
- u32 ecc3_result; /* 0x208 */
- u32 ecc4_result; /* 0x20C */
- u32 ecc5_result; /* 0x210 */
- u32 ecc6_result; /* 0x214 */
- u32 ecc7_result; /* 0x218 */
- u32 ecc8_result; /* 0x21C */
- u32 ecc9_result; /* 0x220 */
- u8 res7[0x1C]; /* fill up to 0x240 */
- struct bch_res_0_3 bch_result_0_3[7]; /* 0x240 */
-};
-
-/* Used for board specific gpmc initialization */
-extern struct gpmc *gpmc_cfg;
-
-#else /* __ASSEMBLY__ */
+#ifdef __ASSEMBLY__
#define GPMC_CONFIG1 0x00
#define GPMC_CONFIG2 0x04
#define GPMC_CONFIG3 0x08
#define NET_GPMC_CONFIG6 0x00000FCF
#define NET_GPMC_CONFIG7 0x00000f6c
+/* GPMC CS configuration for an SMSC LAN9221 ethernet controller */
+#define NET_LAN9221_GPMC_CONFIG1 0x00001000
+#define NET_LAN9221_GPMC_CONFIG2 0x00060700
+#define NET_LAN9221_GPMC_CONFIG3 0x00020201
+#define NET_LAN9221_GPMC_CONFIG4 0x06000700
+#define NET_LAN9221_GPMC_CONFIG5 0x0006090A
+#define NET_LAN9221_GPMC_CONFIG6 0x87030000
+#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c
+
+
/* max number of GPMC Chip Selects */
#define GPMC_MAX_CS 8
/* max number of GPMC regs */
+++ /dev/null
-/*
- * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
- * Rohit Choraria <rohitkc@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __ASM_ARCH_OMAP_GPMC_H
-#define __ASM_ARCH_OMAP_GPMC_H
-
-/*
- * These GPMC_NAND_HW_BCHx_ECC_LAYOUT defines using the BCH library.
- * The OOB layout was first defined by linx kernel in commit
- * 0e618ef0a6a33cf7ef96c2c824402088dd8ef48c, we have to reuse it here cause
- * we want to be compatible.
- */
-#define GPMC_NAND_HW_BCH8_ECC_LAYOUT {\
- .eccbytes = 56,\
- .eccpos = {12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,\
- 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,\
- 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50,\
- 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63},\
- .oobfree = {\
- {.offset = 2,\
- .length = 10 } } \
-}
-
-/* GPMC CS configuration for an SMSC LAN9221 ethernet controller */
-#define NET_LAN9221_GPMC_CONFIG1 0x00001000
-#define NET_LAN9221_GPMC_CONFIG2 0x00060700
-#define NET_LAN9221_GPMC_CONFIG3 0x00020201
-#define NET_LAN9221_GPMC_CONFIG4 0x06000700
-#define NET_LAN9221_GPMC_CONFIG5 0x0006090A
-#define NET_LAN9221_GPMC_CONFIG6 0x87030000
-#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c
-
-#endif /* __ASM_ARCH_OMAP_GPMC_H */
*/
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
+#include <linux/mtd/omap_gpmc.h>
typedef struct {
u32 mtype;
#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
-struct gpmc_cs {
- u32 config1; /* 0x00 */
- u32 config2; /* 0x04 */
- u32 config3; /* 0x08 */
- u32 config4; /* 0x0C */
- u32 config5; /* 0x10 */
- u32 config6; /* 0x14 */
- u32 config7; /* 0x18 */
- u32 nand_cmd; /* 0x1C */
- u32 nand_adr; /* 0x20 */
- u32 nand_dat; /* 0x24 */
- u8 res[8]; /* blow up to 0x30 byte */
-};
-
-struct gpmc {
- u8 res1[0x10];
- u32 sysconfig; /* 0x10 */
- u8 res2[0x4];
- u32 irqstatus; /* 0x18 */
- u32 irqenable; /* 0x1C */
- u8 res3[0x20];
- u32 timeout_control; /* 0x40 */
- u8 res4[0xC];
- u32 config; /* 0x50 */
- u32 status; /* 0x54 */
- u8 res5[0x8]; /* 0x58 */
- struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */
- u8 res6[0x14]; /* 0x1E0 */
- u32 ecc_config; /* 0x1F4 */
- u32 ecc_control; /* 0x1F8 */
- u32 ecc_size_config; /* 0x1FC */
- u32 ecc1_result; /* 0x200 */
- u32 ecc2_result; /* 0x204 */
- u32 ecc3_result; /* 0x208 */
- u32 ecc4_result; /* 0x20C */
- u32 ecc5_result; /* 0x210 */
- u32 ecc6_result; /* 0x214 */
- u32 ecc7_result; /* 0x218 */
- u32 ecc8_result; /* 0x21C */
- u32 ecc9_result; /* 0x220 */
-};
-
-/* Used for board specific gpmc initialization */
-extern struct gpmc *gpmc_cfg;
-
struct gptimer {
u32 tidr; /* 0x00 r */
u8 res[0xc];
#include <asm/arch/clock.h>
#include <asm/io.h>
#include <asm/omap_common.h>
+#include <linux/mtd/omap_gpmc.h>
#include <asm/arch/mux_omap4.h>
DECLARE_GLOBAL_DATA_PTR;
#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
-struct gpmc_cs {
- u32 config1; /* 0x00 */
- u32 config2; /* 0x04 */
- u32 config3; /* 0x08 */
- u32 config4; /* 0x0C */
- u32 config5; /* 0x10 */
- u32 config6; /* 0x14 */
- u32 config7; /* 0x18 */
- u32 nand_cmd; /* 0x1C */
- u32 nand_adr; /* 0x20 */
- u32 nand_dat; /* 0x24 */
- u8 res[8]; /* blow up to 0x30 byte */
-};
-
-struct gpmc {
- u8 res1[0x10];
- u32 sysconfig; /* 0x10 */
- u8 res2[0x4];
- u32 irqstatus; /* 0x18 */
- u32 irqenable; /* 0x1C */
- u8 res3[0x20];
- u32 timeout_control; /* 0x40 */
- u8 res4[0xC];
- u32 config; /* 0x50 */
- u32 status; /* 0x54 */
- u8 res5[0x8]; /* 0x58 */
- struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */
- u8 res6[0x14]; /* 0x1E0 */
- u32 ecc_config; /* 0x1F4 */
- u32 ecc_control; /* 0x1F8 */
- u32 ecc_size_config; /* 0x1FC */
- u32 ecc1_result; /* 0x200 */
- u32 ecc2_result; /* 0x204 */
- u32 ecc3_result; /* 0x208 */
- u32 ecc4_result; /* 0x20C */
- u32 ecc5_result; /* 0x210 */
- u32 ecc6_result; /* 0x214 */
- u32 ecc7_result; /* 0x218 */
- u32 ecc8_result; /* 0x21C */
- u32 ecc9_result; /* 0x220 */
-};
-
-/* Used for board specific gpmc initialization */
-extern struct gpmc *gpmc_cfg;
-
struct gptimer {
u32 tidr; /* 0x00 r */
u8 res1[0xc];
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/omap_common.h>
+#include <linux/mtd/omap_gpmc.h>
#include <asm/arch/clock.h>
DECLARE_GLOBAL_DATA_PTR;
#define PMC_XOFS_SHIFT 1
#define PMC_XOFS_MASK (0x3F << PMC_XOFS_SHIFT)
+#if defined(CONFIG_TEGRA114)
#define TIMER_MULT_SHIFT 0
#define TIMER_MULT_MASK (3 << TIMER_MULT_SHIFT)
#define TIMER_MULT_CPU_SHIFT 2
#define TIMER_MULT_CPU_MASK (3 << TIMER_MULT_CPU_SHIFT)
+#elif defined(CONFIG_TEGRA124)
+#define TIMER_MULT_SHIFT 0
+#define TIMER_MULT_MASK (7 << TIMER_MULT_SHIFT)
+#define TIMER_MULT_CPU_SHIFT 3
+#define TIMER_MULT_CPU_MASK (7 << TIMER_MULT_CPU_SHIFT)
+#endif
+
#define MULT_1 0
#define MULT_2 1
#define MULT_4 2
#define MULT_8 3
+#if defined(CONFIG_TEGRA124)
+#define MULT_16 4
+#endif
#define AMAP_WRITE_SHIFT 20
#define AMAP_WRITE_ON (1 << AMAP_WRITE_SHIFT)
#define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400)
#define NV_PA_EMC_BASE (NV_PA_APB_MISC_BASE + 0xF400)
#define NV_PA_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800)
+#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \
+ defined(CONFIG_TEGRA114)
#define NV_PA_CSITE_BASE 0x70040000
+#else
+#define NV_PA_CSITE_BASE 0x70800000
+#endif
#define TEGRA_USB_ADDR_MASK 0xFFFFC000
#define NV_PA_SDRC_CS0 NV_PA_SDRAM_BASE
#ifndef _TEGRA114_H_
#define _TEGRA114_H_
+#define CONFIG_TEGRA114
+
#define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T114 */
#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */
#ifndef _TEGRA124_H_
#define _TEGRA124_H_
+#define CONFIG_TEGRA124
+
#define NV_PA_SDRAM_BASE 0x80000000
#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */
#define NV_PA_MC_BASE 0x70019000 /* Mem Ctlr regs (MCB, etc.) */
#ifndef _TEGRA20_H_
#define _TEGRA20_H_
+#define CONFIG_TEGRA20
+
#define NV_PA_SDRAM_BASE 0x00000000
#include <asm/arch-tegra/tegra.h>
#ifndef _TEGRA30_H_
#define _TEGRA30_H_
+#define CONFIG_TEGRA30
+
#define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T30 */
#include <asm/arch-tegra/tegra.h>
#ifndef __ASSEMBLY__
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#define ASYNC_EMIF_NUM_CS 4
#define ASYNC_EMIF_MODE_NOR 0
/* Driver extern functions */
extern int zynq_sdhci_init(u32 regbase);
+extern int zynq_sdhci_of_init(const void *blob);
#endif /* _SYS_PROTO_H_ */
+++ /dev/null
-/*
- * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
- * Rohit Choraria <rohitkc@ti.com>
- *
- * (C) Copyright 2013 Andreas Bießmann <andreas.devel@googlemail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __ASM_OMAP_GPMC_H
-#define __ASM_OMAP_GPMC_H
-
-#include <asm/arch/omap_gpmc.h>
-
-#define GPMC_BUF_EMPTY 0
-#define GPMC_BUF_FULL 1
-
-#define ECCCLEAR (0x1 << 8)
-#define ECCRESULTREG1 (0x1 << 0)
-#define ECCSIZE512BYTE 0xFF
-#define ECCSIZE1 (ECCSIZE512BYTE << 22)
-#define ECCSIZE0 (ECCSIZE512BYTE << 12)
-#define ECCSIZE0SEL (0x000 << 0)
-
-/* Generic ECC Layouts */
-/* Large Page x8 NAND device Layout */
-#ifdef GPMC_NAND_ECC_LP_x8_LAYOUT
-#define GPMC_NAND_HW_ECC_LAYOUT {\
- .eccbytes = 12,\
- .eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\
- 9, 10, 11, 12},\
- .oobfree = {\
- {.offset = 13,\
- .length = 51 } } \
-}
-#endif
-
-/* Large Page x16 NAND device Layout */
-#ifdef GPMC_NAND_ECC_LP_x16_LAYOUT
-#define GPMC_NAND_HW_ECC_LAYOUT {\
- .eccbytes = 12,\
- .eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\
- 10, 11, 12, 13},\
- .oobfree = {\
- {.offset = 14,\
- .length = 50 } } \
-}
-#endif
-
-/* Small Page x8 NAND device Layout */
-#ifdef GPMC_NAND_ECC_SP_x8_LAYOUT
-#define GPMC_NAND_HW_ECC_LAYOUT {\
- .eccbytes = 3,\
- .eccpos = {1, 2, 3},\
- .oobfree = {\
- {.offset = 4,\
- .length = 12 } } \
-}
-#endif
-
-/* Small Page x16 NAND device Layout */
-#ifdef GPMC_NAND_ECC_SP_x16_LAYOUT
-#define GPMC_NAND_HW_ECC_LAYOUT {\
- .eccbytes = 3,\
- .eccpos = {2, 3, 4},\
- .oobfree = {\
- {.offset = 5,\
- .length = 11 } } \
-}
-#endif
-
-enum omap_ecc {
- /* 1-bit ECC calculation by Software, Error detection by Software */
- OMAP_ECC_HAM1_CODE_SW = 1, /* avoid un-initialized int can be 0x0 */
- /* 1-bit ECC calculation by GPMC, Error detection by Software */
- /* ECC layout compatible to legacy ROMCODE. */
- OMAP_ECC_HAM1_CODE_HW,
- /* 4-bit ECC calculation by GPMC, Error detection by Software */
- OMAP_ECC_BCH4_CODE_HW_DETECTION_SW,
- /* 4-bit ECC calculation by GPMC, Error detection by ELM */
- OMAP_ECC_BCH4_CODE_HW,
- /* 8-bit ECC calculation by GPMC, Error detection by Software */
- OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
- /* 8-bit ECC calculation by GPMC, Error detection by ELM */
- OMAP_ECC_BCH8_CODE_HW,
-};
-
-#endif /* __ASM_OMAP_GPMC_H */
+++ /dev/null
-/*
- * SPDX-License-Identifier: GPL-2.0+
- */
-/* Size defintions
- * Copyright (C) ARM Limited 1998. All rights reserved.
- */
-
-#ifndef __sizes_h
-#define __sizes_h 1
-
-/* handy sizes */
-#define SZ_1K 0x00000400
-#define SZ_4K 0x00001000
-#define SZ_8K 0x00002000
-#define SZ_16K 0x00004000
-#define SZ_32K 0x00008000
-#define SZ_64K 0x00010000
-#define SZ_128K 0x00020000
-#define SZ_256K 0x00040000
-#define SZ_512K 0x00080000
-
-#define SZ_1M 0x00100000
-#define SZ_2M 0x00200000
-#define SZ_4M 0x00400000
-#define SZ_8M 0x00800000
-#define SZ_16M 0x01000000
-#define SZ_31M 0x01F00000
-#define SZ_32M 0x02000000
-#define SZ_64M 0x04000000
-#define SZ_128M 0x08000000
-#define SZ_256M 0x10000000
-#define SZ_512M 0x20000000
-
-#define SZ_1G 0x40000000
-#define SZ_2G 0x80000000
-
-#endif
-
-/* END */
# SPDX-License-Identifier: GPL-2.0+
#
-# Build private libgcc only when asked for
-ifdef USE_PRIVATE_LIBGCC
-lib-y += _ashldi3.o
-lib-y += _ashrdi3.o
-lib-y += _divsi3.o
-lib-y += _lshrdi3.o
-lib-y += _modsi3.o
-lib-y += _udivsi3.o
-lib-y += _umodsi3.o
-lib-y += div0.o
-endif
+lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _ashldi3.o _ashrdi3.o _divsi3.o \
+ _lshrdi3.o _modsi3.o _udivsi3.o _umodsi3.o div0.o
ifdef CONFIG_ARM64
obj-y += crt0_64.o
#include <nand.h>
#include <onenand_uboot.h>
#include <mmc.h>
+#include <scsi.h>
#include <libfdt.h>
#include <fdtdec.h>
#include <post.h>
mmc_initialize(gd->bd);
#endif
+#ifdef CONFIG_CMD_SCSI
+ puts("SCSI: ");
+ scsi_init();
+#endif
+
#ifdef CONFIG_HAS_DATAFLASH
AT91F_DataflashInit();
dataflash_print_info();
# SPDX-License-Identifier: GPL-2.0+
#
-CROSS_COMPILE ?= avr32-linux-
+ifeq ($(CROSS_COMPILE),)
+CROSS_COMPILE := avr32-linux-
+endif
+
PLATFORM_CPPFLAGS += -DCONFIG_AVR32
CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000
# SPDX-License-Identifier: GPL-2.0+
#
-CROSS_COMPILE ?= bfin-uclinux-
+ifeq ($(CROSS_COMPILE),)
+CROSS_COMPILE := bfin-uclinux-
+endif
CONFIG_STANDALONE_LOAD_ADDR ?= 0x1000 -m elf32bfin
endif
SYM_PREFIX = _
+export SYM_PREFIX
LDR_FLAGS-y :=
LDR_FLAGS-$(CONFIG_BFIN_BOOTROM_USES_EVT1) += -J
# SPDX-License-Identifier: GPL-2.0+
#
-CROSS_COMPILE ?= m68k-elf-
+ifeq ($(CROSS_COMPILE),)
+CROSS_COMPILE := m68k-elf-
+endif
CONFIG_STANDALONE_LOAD_ADDR ?= 0x20000
PLATFORM_CPPFLAGS += -DCONFIG_M68K -D__M68K__
PLATFORM_LDFLAGS += -n
-PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
+PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
+PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
LDFLAGS_FINAL += --gc-sections
# SPDX-License-Identifier: GPL-2.0+
#
-PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
PLATFORM_CPPFLAGS += -mcpu=52277 -fPIC
# SPDX-License-Identifier: GPL-2.0+
#
-PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
PLATFORM_CPPFLAGS += -mcpu=5235 -fPIC
# SPDX-License-Identifier: GPL-2.0+
#
-PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
-
-cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
-is5208:=$(shell grep CONFIG_M5208 $(TOPDIR)/include/$(cfg))
-is5249:=$(shell grep CONFIG_M5249 $(TOPDIR)/include/$(cfg))
-is5253:=$(shell grep CONFIG_M5253 $(TOPDIR)/include/$(cfg))
-is5271:=$(shell grep CONFIG_M5271 $(TOPDIR)/include/$(cfg))
-is5272:=$(shell grep CONFIG_M5272 $(TOPDIR)/include/$(cfg))
-is5275:=$(shell grep CONFIG_M5275 $(TOPDIR)/include/$(cfg))
-is5282:=$(shell grep CONFIG_M5282 $(TOPDIR)/include/$(cfg))
+cfg=$(shell grep configs $(objtree)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
+is5208:=$(shell grep CONFIG_M5208 $(srctree)/include/$(cfg))
+is5249:=$(shell grep CONFIG_M5249 $(srctree)/include/$(cfg))
+is5253:=$(shell grep CONFIG_M5253 $(srctree)/include/$(cfg))
+is5271:=$(shell grep CONFIG_M5271 $(srctree)/include/$(cfg))
+is5272:=$(shell grep CONFIG_M5272 $(srctree)/include/$(cfg))
+is5275:=$(shell grep CONFIG_M5275 $(srctree)/include/$(cfg))
+is5282:=$(shell grep CONFIG_M5282 $(srctree)/include/$(cfg))
ifneq (,$(findstring CONFIG_M5208,$(is5208)))
PLATFORM_CPPFLAGS += -mcpu=5208
# SPDX-License-Identifier: GPL-2.0+
#
-PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
-
-cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
-is5301x:=$(shell grep CONFIG_MCF5301x $(TOPDIR)/include/$(cfg))
-is532x:=$(shell grep CONFIG_MCF532x $(TOPDIR)/include/$(cfg))
+cfg=$(shell grep configs $(objtree)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
+is5301x:=$(shell grep CONFIG_MCF5301x $(srctree)/include/$(cfg))
+is532x:=$(shell grep CONFIG_MCF532x $(srctree)/include/$(cfg))
ifneq (,$(findstring CONFIG_MCF5301x,$(is5301x)))
PLATFORM_CPPFLAGS += -mcpu=53015 -fPIC
# SPDX-License-Identifier: GPL-2.0+
#
-PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
-
-cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
-is5441x:=$(shell grep CONFIG_MCF5441x $(TOPDIR)/include/$(cfg))
+cfg=$(shell grep configs $(objtree)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
+is5441x:=$(shell grep CONFIG_MCF5441x $(srctree)/include/$(cfg))
ifneq (,$(findstring CONFIG_MCF5441x,$(is5441x)))
PLATFORM_CPPFLAGS += -mcpu=54418 -fPIC
# SPDX-License-Identifier: GPL-2.0+
#
-PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
PLATFORM_CPPFLAGS += -mcpu=5485 -fPIC
ifneq (,$(findstring -linux-,$(shell $(CC) --version)))
# SPDX-License-Identifier: GPL-2.0+
#
-CROSS_COMPILE ?= mb-
+ifeq ($(CROSS_COMPILE),)
+CROSS_COMPILE := mb-
+endif
CONFIG_STANDALONE_LOAD_ADDR ?= 0x80F00000
PLATFORM_CPPFLAGS += -ffixed-r31 -D__microblaze__
-
-LDSCRIPT ?= $(SRCTREE)/$(CPUDIR)/u-boot.lds
# SPDX-License-Identifier: GPL-2.0+
#
-CROSS_COMPILE ?= mips_4KC-
+ifeq ($(CROSS_COMPILE),)
+CROSS_COMPILE := mips_4KC-
+endif
# Handle special prefix in ELDK 4.0 toolchain
ifneq (,$(findstring 4KCle,$(CROSS_COMPILE)))
* Virtual Root Hub
*-------------------------------------------------------------------------*/
-/* Device descriptor */
-static __u8 root_hub_dev_des[] =
-{
- 0x12, /* __u8 bLength; */
- 0x01, /* __u8 bDescriptorType; Device */
- 0x10, /* __u16 bcdUSB; v1.1 */
- 0x01,
- 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
- 0x00, /* __u8 bDeviceSubClass; */
- 0x00, /* __u8 bDeviceProtocol; */
- 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
- 0x00, /* __u16 idVendor; */
- 0x00,
- 0x00, /* __u16 idProduct; */
- 0x00,
- 0x00, /* __u16 bcdDevice; */
- 0x00,
- 0x00, /* __u8 iManufacturer; */
- 0x01, /* __u8 iProduct; */
- 0x00, /* __u8 iSerialNumber; */
- 0x01 /* __u8 bNumConfigurations; */
-};
-
-
-/* Configuration descriptor */
-static __u8 root_hub_config_des[] =
-{
- 0x09, /* __u8 bLength; */
- 0x02, /* __u8 bDescriptorType; Configuration */
- 0x19, /* __u16 wTotalLength; */
- 0x00,
- 0x01, /* __u8 bNumInterfaces; */
- 0x01, /* __u8 bConfigurationValue; */
- 0x00, /* __u8 iConfiguration; */
- 0x40, /* __u8 bmAttributes;
- Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
- 0x00, /* __u8 MaxPower; */
-
- /* interface */
- 0x09, /* __u8 if_bLength; */
- 0x04, /* __u8 if_bDescriptorType; Interface */
- 0x00, /* __u8 if_bInterfaceNumber; */
- 0x00, /* __u8 if_bAlternateSetting; */
- 0x01, /* __u8 if_bNumEndpoints; */
- 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
- 0x00, /* __u8 if_bInterfaceSubClass; */
- 0x00, /* __u8 if_bInterfaceProtocol; */
- 0x00, /* __u8 if_iInterface; */
-
- /* endpoint */
- 0x07, /* __u8 ep_bLength; */
- 0x05, /* __u8 ep_bDescriptorType; Endpoint */
- 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
- 0x03, /* __u8 ep_bmAttributes; Interrupt */
- 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
- 0x00,
- 0xff /* __u8 ep_bInterval; 255 ms */
-};
-
-static unsigned char root_hub_str_index0[] =
-{
- 0x04, /* __u8 bLength; */
- 0x03, /* __u8 bDescriptorType; String-descriptor */
- 0x09, /* __u8 lang ID */
- 0x04, /* __u8 lang ID */
-};
-
-static unsigned char root_hub_str_index1[] =
-{
- 28, /* __u8 bLength; */
- 0x03, /* __u8 bDescriptorType; String-descriptor */
- 'O', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'H', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'C', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'I', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- ' ', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'R', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'o', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'o', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 't', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- ' ', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'H', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'u', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'b', /* __u8 Unicode */
- 0, /* __u8 Unicode */
-};
+#include <usbroothubdes.h>
/* Hub class-specific descriptor is constructed dynamically */
# Note: Toolchains with binutils prior to v2.16
# are no longer supported by U-Boot MIPS tree!
#
-MIPSFLAGS := -march=mips32r2
-
-PLATFORM_CPPFLAGS += $(MIPSFLAGS)
+PLATFORM_CPPFLAGS += -DCONFIG_MIPS32 -march=mips32r2
PLATFORM_CPPFLAGS += -mabi=32 -DCONFIG_32BIT
ifdef CONFIG_SYS_BIG_ENDIAN
PLATFORM_LDFLAGS += -m elf32btsmip
PLATFORM_LDFLAGS += -m elf32ltsmip
endif
-CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T $(srctree)/$(src)/mips.lds
+CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 \
+ -T $(srctree)/examples/standalone/mips.lds
# Note: Toolchains with binutils prior to v2.16
# are no longer supported by U-Boot MIPS tree!
#
-MIPSFLAGS = -march=mips64
-
-PLATFORM_CPPFLAGS += $(MIPSFLAGS)
+PLATFORM_CPPFLAGS += -DCONFIG_MIPS64 -march=mips64
PLATFORM_CPPFLAGS += -mabi=64 -DCONFIG_64BIT
ifdef CONFIG_SYS_BIG_ENDIAN
PLATFORM_LDFLAGS += -m elf64btsmip
PLATFORM_LDFLAGS += -m elf64ltsmip
endif
-CONFIG_STANDALONE_LOAD_ADDR ?= 0xffffffff80200000 -T $(srctree)/$(src)/mips64.lds
+CONFIG_STANDALONE_LOAD_ADDR ?= 0xffffffff80200000 \
+ -T $(srctree)/examples/standalone/mips64.lds
PLATFORM_LDFLAGS += -m elf32ltsmip
endif
-CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T $(srctree)/$(src)/mips.lds
+CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 \
+ -T $(srctree)/examples/standalone/mips.lds
typedef __signed__ int __s32;
typedef unsigned int __u32;
-#if (_MIPS_SZLONG == 64)
-
-typedef __signed__ long __s64;
-typedef unsigned long __u64;
-
-#else
-
#if defined(__GNUC__)
__extension__ typedef __signed__ long long __s64;
__extension__ typedef unsigned long long __u64;
-#endif
-
+#else
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
#endif
#endif /* __ASSEMBLY__ */
typedef __signed int s32;
typedef unsigned int u32;
-#if (_MIPS_SZLONG == 64)
-
-typedef __signed__ long s64;
-typedef unsigned long u64;
-
-#else
-
-#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
typedef __signed__ long long s64;
typedef unsigned long long u64;
-#endif
-
-#endif
#if (defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) \
|| defined(CONFIG_64BIT)
obj-y += board.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
-# Build private libgcc only when asked for
-ifdef USE_PRIVATE_LIBGCC
-lib-y += ashldi3.o
-lib-y += ashrdi3.o
-lib-y += lshrdi3.o
-endif
+lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o
#
# SPDX-License-Identifier: GPL-2.0+
-CROSS_COMPILE ?= nds32le-linux-
+ifeq ($(CROSS_COMPILE),)
+CROSS_COMPILE := nds32le-linux-
+endif
-CONFIG_STANDALONE_LOAD_ADDR = 0x300000 -T $(srctree)/$(src)/nds32.lds
+CONFIG_STANDALONE_LOAD_ADDR = 0x300000 \
+ -T $(srctree)/examples/standalone/nds32.lds
PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -mrelax
PLATFORM_RELFLAGS += -gdwarf-2
# SPDX-License-Identifier: GPL-2.0+
#
-CROSS_COMPILE ?= nios2-elf-
+ifeq ($(CROSS_COMPILE),)
+CROSS_COMPILE := nios2-elf-
+endif
CONFIG_STANDALONE_LOAD_ADDR ?= 0x02000000
# SPDX-License-Identifier: GPL-2.0+
#
-CROSS_COMPILE ?= or32-elf-
+ifeq ($(CROSS_COMPILE),)
+CROSS_COMPILE := or32-elf-
+endif
# r10 used for global object pointer, already set in OR32 GCC but just to be
# clear
PLATFORM_CPPFLAGS += -DCONFIG_OPENRISC -D__OR1K__ -ffixed-r10
CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000
-
-LDSCRIPT ?= $(SRCTREE)/$(CPUDIR)/u-boot.lds
# SPDX-License-Identifier: GPL-2.0+
#
-CROSS_COMPILE ?= ppc_8xx-
+ifeq ($(CROSS_COMPILE),)
+CROSS_COMPILE := ppc_8xx-
+endif
CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000
LDFLAGS_FINAL += --gc-sections
# Only test once
ifneq ($(CONFIG_SPL_BUILD),y)
-ALL-y += checkgcc4
+archprepare: checkgcc4
+
+# GCC 3.x is reported to have problems generating the type of relocation
+# that U-Boot wants.
+# See http://lists.denx.de/pipermail/u-boot/2012-September/135156.html
+checkgcc4:
+ @if test $(call cc-version) -lt 0400; then \
+ echo -n '*** Your GCC is too old, please upgrade to GCC 4.x or newer'; \
+ false; \
+ fi
endif
* Virtual Root Hub
*-------------------------------------------------------------------------*/
-/* Device descriptor */
-static __u8 root_hub_dev_des[] =
-{
- 0x12, /* __u8 bLength; */
- 0x01, /* __u8 bDescriptorType; Device */
- 0x10, /* __u16 bcdUSB; v1.1 */
- 0x01,
- 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
- 0x00, /* __u8 bDeviceSubClass; */
- 0x00, /* __u8 bDeviceProtocol; */
- 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
- 0x00, /* __u16 idVendor; */
- 0x00,
- 0x00, /* __u16 idProduct; */
- 0x00,
- 0x00, /* __u16 bcdDevice; */
- 0x00,
- 0x00, /* __u8 iManufacturer; */
- 0x01, /* __u8 iProduct; */
- 0x00, /* __u8 iSerialNumber; */
- 0x01 /* __u8 bNumConfigurations; */
-};
-
-
-/* Configuration descriptor */
-static __u8 root_hub_config_des[] =
-{
- 0x09, /* __u8 bLength; */
- 0x02, /* __u8 bDescriptorType; Configuration */
- 0x19, /* __u16 wTotalLength; */
- 0x00,
- 0x01, /* __u8 bNumInterfaces; */
- 0x01, /* __u8 bConfigurationValue; */
- 0x00, /* __u8 iConfiguration; */
- 0x40, /* __u8 bmAttributes;
- Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
- 0x00, /* __u8 MaxPower; */
-
- /* interface */
- 0x09, /* __u8 if_bLength; */
- 0x04, /* __u8 if_bDescriptorType; Interface */
- 0x00, /* __u8 if_bInterfaceNumber; */
- 0x00, /* __u8 if_bAlternateSetting; */
- 0x01, /* __u8 if_bNumEndpoints; */
- 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
- 0x00, /* __u8 if_bInterfaceSubClass; */
- 0x00, /* __u8 if_bInterfaceProtocol; */
- 0x00, /* __u8 if_iInterface; */
-
- /* endpoint */
- 0x07, /* __u8 ep_bLength; */
- 0x05, /* __u8 ep_bDescriptorType; Endpoint */
- 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
- 0x03, /* __u8 ep_bmAttributes; Interrupt */
- 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
- 0x00,
- 0xff /* __u8 ep_bInterval; 255 ms */
-};
-
-static unsigned char root_hub_str_index0[] =
-{
- 0x04, /* __u8 bLength; */
- 0x03, /* __u8 bDescriptorType; String-descriptor */
- 0x09, /* __u8 lang ID */
- 0x04, /* __u8 lang ID */
-};
-
-static unsigned char root_hub_str_index1[] =
-{
- 28, /* __u8 bLength; */
- 0x03, /* __u8 bDescriptorType; String-descriptor */
- 'O', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'H', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'C', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'I', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- ' ', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'R', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'o', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'o', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 't', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- ' ', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'H', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'u', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'b', /* __u8 Unicode */
- 0, /* __u8 Unicode */
-};
+#include <usbroothubdes.h>
/* Hub class-specific descriptor is constructed dynamically */
# SPDX-License-Identifier: GPL-2.0+
#
-PLATFORM_CPPFLAGS += -DCONFIG_8260 -DCONFIG_CPM2 \
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8260 -DCONFIG_CPM2 \
-mstring -mcpu=603e -mmultiple
#include <mpc8260.h>
#include <version.h>
-#define CONFIG_8260 1 /* needed for Linux kernel header files */
-
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <mpc8260.h>
#include <version.h>
-#define CONFIG_8260 1 /* needed for Linux kernel header files */
-
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#ifdef CONFIG_PPC_B4860
static struct serdes_config serdes1_cfg_tbl[] = {
/* SerDes 1 */
+ {0x02, {AURORA, AURORA, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1} },
+ {0x04, {AURORA, AURORA, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1} },
+ {0x05, {AURORA, AURORA, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1} },
+ {0x06, {AURORA, AURORA, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1} },
+ {0x08, {AURORA, AURORA, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1} },
+ {0x09, {AURORA, AURORA, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1} },
+ {0x0A, {AURORA, AURORA, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1} },
+ {0x0B, {AURORA, AURORA, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1} },
+ {0x0C, {AURORA, AURORA, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1} },
{0x0D, {CPRI8, CPRI7, CPRI6, CPRI5,
CPRI4, CPRI3, CPRI2, CPRI1}},
{0x0E, {CPRI8, CPRI7, CPRI6, CPRI5,
CPRI4, CPRI3, CPRI2, CPRI1}},
{0x12, {CPRI8, CPRI7, CPRI6, CPRI5,
CPRI4, CPRI3, CPRI2, CPRI1}},
+ {0x29, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1} },
{0x2a, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
{0x2C, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
{0x2E, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
+ {0x2F, {AURORA, AURORA,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ CPRI4, CPRI3, CPRI2, CPRI1} },
{0x30, {AURORA, AURORA,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
CPRI4, CPRI3, CPRI2, CPRI1}},
{0x34, {AURORA, AURORA,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
CPRI4, CPRI3, CPRI2, CPRI1}},
+ {0x39, {AURORA, AURORA, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1} },
+ {0x3A, {AURORA, AURORA, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1} },
+ {0x3C, {AURORA, AURORA, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1} },
+ {0x3D, {AURORA, AURORA, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1} },
{0x3E, {CPRI8, CPRI7, CPRI6, CPRI5,
CPRI4, CPRI3, CPRI2, CPRI1}},
+ {0x5C, {AURORA, AURORA,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ CPRI4, CPRI3, CPRI2, CPRI1} },
+ {0x5D, {AURORA, AURORA,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ CPRI4, CPRI3, CPRI2, CPRI1} },
{}
};
static struct serdes_config serdes2_cfg_tbl[] = {
/* SerDes 2 */
+ {0x17, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ AURORA, AURORA, SRIO1, SRIO1} },
{0x18, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
AURORA, AURORA, SRIO1, SRIO1}},
{0x1D, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
AURORA, AURORA, SRIO1, SRIO1}},
+ {0x2A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SRIO2, SRIO2,
+ AURORA, AURORA, SRIO1, SRIO1} },
{0x2B, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SRIO2, SRIO2,
AURORA, AURORA, SRIO1, SRIO1}},
SRIO2, SRIO2,
AURORA, AURORA,
SRIO1, SRIO1}},
+ {0x48, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, AURORA,
+ SRIO1, SRIO1, SRIO1, SRIO1} },
{0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, AURORA,
SRIO1, SRIO1, SRIO1, SRIO1}},
{0x4E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, AURORA,
SRIO1, SRIO1, SRIO1, SRIO1}},
+ {0x79, {SRIO2, SRIO2, SRIO2, SRIO2,
+ SRIO1, SRIO1, SRIO1, SRIO1} },
{0x7A, {SRIO2, SRIO2, SRIO2, SRIO2,
SRIO1, SRIO1, SRIO1, SRIO1}},
+ {0x83, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SRIO2, SRIO2, AURORA, AURORA,
+ XFI_FM1_MAC9, XFI_FM1_MAC10} },
{0x84, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SRIO2, SRIO2, AURORA, AURORA,
XFI_FM1_MAC9, XFI_FM1_MAC10}},
{0x85, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SRIO2, SRIO2, AURORA, AURORA,
XFI_FM1_MAC9, XFI_FM1_MAC10}},
+ {0x86, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SRIO2, SRIO2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ XFI_FM1_MAC9, XFI_FM1_MAC10} },
{0x87, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SRIO2, SRIO2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
XFI_FM1_MAC9, XFI_FM1_MAC10}},
+ {0x8C, {SRIO2, SRIO2, SRIO2, SRIO2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ XFI_FM1_MAC9, XFI_FM1_MAC10} },
{0x8D, {SRIO2, SRIO2, SRIO2, SRIO2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
XFI_FM1_MAC9, XFI_FM1_MAC10}},
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
XAUI_FM1_MAC10, XAUI_FM1_MAC10,
XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
+ {0xB1, {PCIE1, PCIE1, PCIE1, PCIE1,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ XFI_FM1_MAC9, XFI_FM1_MAC10} },
{0xB2, {PCIE1, PCIE1, PCIE1, PCIE1,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
XFI_FM1_MAC9, XFI_FM1_MAC10}},
if (IS_SVR_REV(svr, 1, 0))
puts("Work-around for Erratum A005871 enabled\n");
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006475
+ if (SVR_MAJ(get_svr()) == 1)
+ puts("Work-around for Erratum A006475 enabled\n");
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006384
+ if (SVR_MAJ(get_svr()) == 1)
+ puts("Work-around for Erratum A006384 enabled\n");
+#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A004849
/* This work-around is implemented in PBI, so just check for it */
check_erratum_a4849(svr);
if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
(SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
puts("Work-around for Erratum I2C-A004447 enabled\n");
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
+ if (has_erratum_a006261())
+ puts("Work-around for Erratum A006261 enabled\n");
#endif
return 0;
}
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
+void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
+{
+#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
+ u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg);
+
+ /* Increase Disconnect Threshold by 50mV */
+ xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
+ INC_DCNT_THRESHOLD_50MV;
+ /* Enable programming of USB High speed Disconnect threshold */
+ xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
+ out_be32(&usb_phy->port1.xcvrprg, xcvrprg);
+
+ xcvrprg = in_be32(&usb_phy->port2.xcvrprg);
+ /* Increase Disconnect Threshold by 50mV */
+ xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
+ INC_DCNT_THRESHOLD_50MV;
+ /* Enable programming of USB High speed Disconnect threshold */
+ xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
+ out_be32(&usb_phy->port2.xcvrprg, xcvrprg);
+#else
+
+ u32 temp = 0;
+ u32 status = in_be32(&usb_phy->status1);
+
+ u32 squelch_prog_rd_0_2 =
+ (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
+ & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
+
+ u32 squelch_prog_rd_3_5 =
+ (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
+ & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
+
+ setbits_be32(&usb_phy->config1,
+ CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
+ setbits_be32(&usb_phy->config2,
+ CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
+
+ temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
+ out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
+
+ temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
+ out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
+#endif
+}
+#endif
+
+
#ifdef CONFIG_QE
extern qe_iop_conf_t qe_iop_conf_tab[];
extern void qe_config_iopin(u8 port, u8 pin, int dir,
{
struct ccsr_usb_phy __iomem *usb_phy1 =
(void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
+ if (has_erratum_a006261())
+ fsl_erratum_a006261_workaround(usb_phy1);
+#endif
out_be32(&usb_phy1->usb_enable_override,
CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
}
{
struct ccsr_usb_phy __iomem *usb_phy2 =
(void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
+ if (has_erratum_a006261())
+ fsl_erratum_a006261_workaround(usb_phy2);
+#endif
out_be32(&usb_phy2->usb_enable_override,
CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
}
CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
setbits_be32(&usb_phy->port2.pwrfltcfg,
CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
+ if (has_erratum_a006261())
+ fsl_erratum_a006261_workaround(usb_phy);
#endif
+#endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
+
#ifdef CONFIG_FMAN_ENET
fman_enet_init();
#endif
"SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
} while (0)
-#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
static void update_rdcc(void)
{
u32 val;
}
}
}
-#endif
#if defined(CONFIG_440)
/*
#define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
-#if !defined(CONFIG_NAND_SPL)
/*-----------------------------------------------------------------------------+
* sdram_memsize
*-----------------------------------------------------------------------------*/
val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
printf(", CL%d)", val);
}
-#endif /* !CONFIG_NAND_SPL */
#if defined(CONFIG_SPD_EEPROM)
*---------------------------------------------------------------------------*/
phys_size_t initdram(int board_type)
{
- /*
- * Only run this SDRAM init code once. For NAND booting
- * targets like Kilauea, we call initdram() early from the
- * 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot().
- * Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT)
- * which calls initdram() again. This time the controller
- * mustn't be reconfigured again since we're already running
- * from SDRAM.
- */
-#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
unsigned long val;
#if defined(CONFIG_440)
#endif
#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
/*------------------------------------------------------------------
| DQS calibration.
+-----------------------------------------------------------------*/
DQS_autocalibration();
-#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
/*
set_mcsr(get_mcsr());
#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
-#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
-
return (CONFIG_SYS_MBYTES_SDRAM << 20);
}
#endif /* CONFIG_SPD_EEPROM */
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#if defined(CONFIG_440)
u32 mfdcr_any(u32 dcr)
{
}
}
#endif /* defined(CONFIG_440) */
-#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
inline void ppc4xx_ibm_ddr2_register_dump(void)
{
#include "ecc.h"
-/*
- * Only compile the DDR auto-calibration code for NOR boot and
- * not for NAND boot (NAND SPL and NAND U-Boot - NUB)
- */
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
-
#define MAXBXCF 4
#define SDRAM_RXBAS_SHIFT_1M 20
return 0;
}
-#else /* defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
-u32 DQS_autocalibration(void)
-{
- return 0;
-}
-#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
obj-y += 40x_spd_sdram.o
-ifndef CONFIG_NAND_SPL
-ifndef CONFIG_NAND_U_BOOT
obj-y += 44x_spd_ddr.o
-endif
-endif
obj-$(CONFIG_SDRAM_PPC4xx_IBM_DDR2) += 44x_spd_ddr2.o
obj-$(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) += 4xx_ibm_ddr2_autocalib.o
obj-y += 4xx_pci.o
PLATFORM_CPPFLAGS += -DCONFIG_4xx -mstring -msoft-float
-cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
-is440:=$(shell grep CONFIG_440 $(TOPDIR)/include/$(cfg))
+cfg=$(shell grep configs $(objtree)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
+is440:=$(shell grep CONFIG_440 $(srctree)/include/$(cfg))
ifneq (,$(findstring CONFIG_440,$(is440)))
PLATFORM_CPPFLAGS += -Wa,-m440 -mcpu=440
.extern ext_bus_cntlr_init
-#ifdef CONFIG_NAND_U_BOOT
- .extern reconfig_tlb0
-#endif
/*
* Set up GOT: Global Offset Table
*
* Use r12 to access the GOT
*/
-#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_SPL_BUILD)
START_GOT
GOT_ENTRY(_GOT2_TABLE_)
GOT_ENTRY(_FIXUP_TABLE_)
GOT_ENTRY(__bss_end)
GOT_ENTRY(__bss_start)
END_GOT
-#endif /* CONFIG_NAND_SPL */
-
-#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
- !defined(CONFIG_SPL_BUILD)
- /*
- * NAND U-Boot image is started from offset 0
- */
- .text
-#if defined(CONFIG_440)
- bl reconfig_tlb0
-#endif
- GET_GOT
- bl cpu_init_f /* run low-level CPU init code (from Flash) */
- bl board_init_f
- /* NOTREACHED - board_init_f() does not return */
-#endif
+#endif /* CONFIG_SPL_BUILD */
#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_BOOT_FROM_XMD)
/*
*/
#if defined(CONFIG_440)
-#if !defined(CONFIG_NAND_SPL)
.section .bootpg,"ax"
-#endif
.globl _start_440
/**************************************************************************/
* r3 - 1st arg to board_init(): IMMP pointer
* r4 - 2nd arg to board_init(): boot flag
*/
-#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_SPL_BUILD)
.text
.long 0x27051956 /* U-Boot Magic Number */
.globl version_string
stwu r1,-8(r1) /* Save back chain and move SP */
stw r0,+12(r1) /* Save return addr (underflow vect) */
-#ifdef CONFIG_NAND_SPL
- bl nand_boot_common /* will not return */
-#else
#ifndef CONFIG_SPL_BUILD
GET_GOT
#endif
bl cpu_init_f /* run low-level CPU init code (from Flash) */
bl board_init_f
/* NOTREACHED - board_init_f() does not return */
-#endif
#endif /* CONFIG_440 */
stw r0, +12(r1) /* Save return addr (underflow vect) */
#endif /* CONFIG_SYS_INIT_DCACHE_CS */
-#ifdef CONFIG_NAND_SPL
- bl nand_boot_common /* will not return */
-#else
GET_GOT /* initialize GOT access */
bl cpu_init_f /* run low-level CPU init code (from Flash) */
bl board_init_f /* run first part of init code (from Flash) */
/* NOTREACHED - board_init_f() does not return */
-#endif /* CONFIG_NAND_SPL */
-
#endif /* CONFIG_405GP || CONFIG_405 || CONFIG_405EP */
/*----------------------------------------------------------------------- */
-#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_SPL_BUILD)
/*
* This code finishes saving the registers to the exception frame
* and jumps to the appropriate handler for the exception.
blr
function_epilog(dcbz_area)
#endif /* CONFIG_440 */
-#endif /* CONFIG_NAND_SPL */
+#endif /* CONFIG_SPL_BUILD */
/*------------------------------------------------------------------------------- */
/* Function: in8 */
blr
function_epilog(mftlb1)
#endif /* CONFIG_440 */
-
-#if defined(CONFIG_NAND_SPL)
-/*
- * void nand_boot_relocate(dst, src, bytes)
- *
- * r3 = Destination address to copy code to (in SDRAM)
- * r4 = Source address to copy code from
- * r5 = size to copy in bytes
- */
-nand_boot_relocate:
- mr r6,r3
- mr r7,r4
- mflr r8
-
- /*
- * Copy SPL from icache into SDRAM
- */
- subi r3,r3,4
- subi r4,r4,4
- srwi r5,r5,2
- mtctr r5
-..spl_loop:
- lwzu r0,4(r4)
- stwu r0,4(r3)
- bdnz ..spl_loop
-
- /*
- * Calculate "corrected" link register, so that we "continue"
- * in execution in destination range
- */
- sub r3,r7,r6 /* r3 = src - dst */
- sub r8,r8,r3 /* r8 = link-reg - (src - dst) */
- mtlr r8
- blr
-
-nand_boot_common:
- /*
- * First initialize SDRAM. It has to be available *before* calling
- * nand_boot().
- */
- lis r3,CONFIG_SYS_SDRAM_BASE@h
- ori r3,r3,CONFIG_SYS_SDRAM_BASE@l
- bl initdram
-
- /*
- * Now copy the 4k SPL code into SDRAM and continue execution
- * from there.
- */
- lis r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h
- ori r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l
- lis r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h
- ori r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l
- lis r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h
- ori r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l
- bl nand_boot_relocate
-
- /*
- * We're running from SDRAM now!!!
- *
- * It is necessary for 4xx systems to relocate from running at
- * the original location (0xfffffxxx) to somewhere else (SDRAM
- * preferably). This is because CS0 needs to be reconfigured for
- * NAND access. And we can't reconfigure this CS when currently
- * "running" from it.
- */
-
- /*
- * Finally call nand_boot() to load main NAND U-Boot image from
- * NAND and jump to it.
- */
- bl nand_boot /* will not return */
-#endif /* CONFIG_NAND_SPL */
* Virtual Root Hub
*-------------------------------------------------------------------------*/
-/* Device descriptor */
-static __u8 root_hub_dev_des[] =
-{
- 0x12, /* __u8 bLength; */
- 0x01, /* __u8 bDescriptorType; Device */
- 0x10, /* __u16 bcdUSB; v1.1 */
- 0x01,
- 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
- 0x00, /* __u8 bDeviceSubClass; */
- 0x00, /* __u8 bDeviceProtocol; */
- 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
- 0x00, /* __u16 idVendor; */
- 0x00,
- 0x00, /* __u16 idProduct; */
- 0x00,
- 0x00, /* __u16 bcdDevice; */
- 0x00,
- 0x00, /* __u8 iManufacturer; */
- 0x01, /* __u8 iProduct; */
- 0x00, /* __u8 iSerialNumber; */
- 0x01 /* __u8 bNumConfigurations; */
-};
-
-
-/* Configuration descriptor */
-static __u8 root_hub_config_des[] =
-{
- 0x09, /* __u8 bLength; */
- 0x02, /* __u8 bDescriptorType; Configuration */
- 0x19, /* __u16 wTotalLength; */
- 0x00,
- 0x01, /* __u8 bNumInterfaces; */
- 0x01, /* __u8 bConfigurationValue; */
- 0x00, /* __u8 iConfiguration; */
- 0x40, /* __u8 bmAttributes;
- Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
- 0x00, /* __u8 MaxPower; */
-
- /* interface */
- 0x09, /* __u8 if_bLength; */
- 0x04, /* __u8 if_bDescriptorType; Interface */
- 0x00, /* __u8 if_bInterfaceNumber; */
- 0x00, /* __u8 if_bAlternateSetting; */
- 0x01, /* __u8 if_bNumEndpoints; */
- 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
- 0x00, /* __u8 if_bInterfaceSubClass; */
- 0x00, /* __u8 if_bInterfaceProtocol; */
- 0x00, /* __u8 if_iInterface; */
-
- /* endpoint */
- 0x07, /* __u8 ep_bLength; */
- 0x05, /* __u8 ep_bDescriptorType; Endpoint */
- 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
- 0x03, /* __u8 ep_bmAttributes; Interrupt */
- 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
- 0x00,
- 0xff /* __u8 ep_bInterval; 255 ms */
-};
-
-static unsigned char root_hub_str_index0[] =
-{
- 0x04, /* __u8 bLength; */
- 0x03, /* __u8 bDescriptorType; String-descriptor */
- 0x09, /* __u8 lang ID */
- 0x04, /* __u8 lang ID */
-};
-
-static unsigned char root_hub_str_index1[] =
-{
- 28, /* __u8 bLength; */
- 0x03, /* __u8 bDescriptorType; String-descriptor */
- 'O', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'H', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'C', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'I', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- ' ', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'R', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'o', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'o', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 't', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- ' ', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'H', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'u', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'b', /* __u8 Unicode */
- 0, /* __u8 Unicode */
-};
+#include <usbroothubdes.h>
/* Hub class-specific descriptor is constructed dynamically */
#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
+#define CONFIG_SYS_FSL_ERRATUM_A006261
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
#define CONFIG_ESDHC_HC_BLK_ADDR
#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
#define CONFIG_SYS_FSL_ERRATUM_A004849
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
+#define CONFIG_SYS_FSL_ERRATUM_A006261
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
#elif defined(CONFIG_PPC_P3041)
#define CONFIG_SYS_FSL_ERRATUM_A004849
#define CONFIG_SYS_FSL_ERRATUM_A005812
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
+#define CONFIG_SYS_FSL_ERRATUM_A006261
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
+#define CONFIG_SYS_FSL_ERRATUM_A006261
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
#elif defined(CONFIG_PPC_P5040)
#define CONFIG_SYS_FSL_ERRATUM_A004699
#define CONFIG_SYS_FSL_ERRATUM_A004510
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
+#define CONFIG_SYS_FSL_ERRATUM_A006261
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#define CONFIG_SYS_FSL_ERRATUM_A005812
#define CONFIG_SYS_FSL_ERRATUM_A004468
#define CONFIG_SYS_FSL_ERRATUM_A_004934
#define CONFIG_SYS_FSL_ERRATUM_A005871
+#define CONFIG_SYS_FSL_ERRATUM_A006261
#define CONFIG_SYS_FSL_ERRATUM_A006379
#define CONFIG_SYS_FSL_ERRATUM_A006593
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_ERRATUM_A005871
#define CONFIG_SYS_FSL_ERRATUM_A006379
#define CONFIG_SYS_FSL_ERRATUM_A006593
+#define CONFIG_SYS_FSL_ERRATUM_A006475
+#define CONFIG_SYS_FSL_ERRATUM_A006384
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#ifdef CONFIG_PPC_B4860
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
#define CONFIG_MAX_CPUS 4
+#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 6
#define CONFIG_SYS_FSL_SRIO_LIODN
#else
#define CONFIG_MAX_CPUS 2
+#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_FSL_ERRATUM_A006261
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
}
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
+static inline bool has_erratum_a006261(void)
+{
+ u32 svr = get_svr();
+ u32 soc = SVR_SOC_VER(svr);
+
+ switch (soc) {
+ case SVR_P1010:
+ return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+ case SVR_P2041:
+ case SVR_P2040:
+ return IS_SVR_REV(svr, 1, 0) ||
+ IS_SVR_REV(svr, 1, 1) || IS_SVR_REV(svr, 2, 1);
+ case SVR_P3041:
+ return IS_SVR_REV(svr, 1, 0) ||
+ IS_SVR_REV(svr, 1, 1) ||
+ IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 2, 1);
+ case SVR_P5010:
+ case SVR_P5020:
+ case SVR_P5021:
+ return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+ case SVR_T4240:
+ case SVR_T4160:
+ return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+ case SVR_T1040:
+ return IS_SVR_REV(svr, 1, 0);
+ case SVR_P5040:
+ return IS_SVR_REV(svr, 1, 0);
+ }
+
+ return false;
+}
+#endif
+
#endif
u32 rstrqpblsr; /* Reset request preboot loader status */
u8 res11[8];
u32 rstrqmr1; /* Reset request mask */
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#define FSL_CORENET_RSTRQMR1_SRDS_RST_MSK 0x00000800
+#endif
u8 res12[4];
u32 rstrqsr1; /* Reset request status */
u8 res13[4];
#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL 0x00000080
#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH 0x00000000
#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x80000000
+#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28
+#define PXCKEN_MASK 0x80000000
+#define PXCK_MASK 0x00FF0000
+#define PXCK_BITS_START 16
#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
#define SRDS_RSTCTL_SDEN 0x00000020
#define SRDS_RSTCTL_SDRST_B 0x00000040
#define SRDS_RSTCTL_PLLRST_B 0x00000080
+#define SRDS_RSTCTL_RSTERR_SHIFT 29
u32 pllcr0; /* PLL Control Register 0 */
#define SRDS_PLLCR0_POFF 0x80000000
#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
#define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000
+#define SRDS_PLLCR0_DCBIAS_OUT_EN 0x02000000
#define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000
#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
#define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000
#define SRDS_PLLCR0_FRATE_SEL_4 0x00070000
#define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000
#define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000
+#define SRDS_PLLCR0_DCBIAS_OVRD 0x000000F0
+#define SRDS_PLLCR0_DCBIAS_OVRD_SHIFT 4
u32 pllcr1; /* PLL Control Register 1 */
-#define SRDS_PLLCR1_PLL_BWSEL 0x08000000
- u32 res_0c; /* 0x00c */
+#define SRDS_PLLCR1_BCAP_EN 0x20000000
+#define SRDS_PLLCR1_BCAP_OVD 0x10000000
+#define SRDS_PLLCR1_PLL_FCAP 0x001F8000
+#define SRDS_PLLCR1_PLL_FCAP_SHIFT 15
+#define SRDS_PLLCR1_PLL_BWSEL 0x08000000
+#define SRDS_PLLCR1_BYP_CAL 0x02000000
+ u32 pllsr2; /* At 0x00c, PLL Status Register 2 */
+#define SRDS_PLLSR2_BCAP_EN 0x00800000
+#define SRDS_PLLSR2_BCAP_EN_SHIFT 23
+#define SRDS_PLLSR2_FCAP 0x003F0000
+#define SRDS_PLLSR2_FCAP_SHIFT 16
+#define SRDS_PLLSR2_DCBIAS 0x000F0000
+#define SRDS_PLLSR2_DCBIAS_SHIFT 16
u32 pllcr3;
u32 pllcr4;
u8 res_18[0x20-0x18];
#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
#define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000
#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
+#define CONFIG_SYS_FSL_SCFG_OFFSET 0xFC000
#define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000
#define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000
#define CONFIG_SYS_MPC85xx_DMA3_OFFSET 0x102000
#define CONFIG_SYS_FSL_CPC_ADDR \
(CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
+#define CONFIG_SYS_FSL_SCFG_ADDR \
+ (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET)
+#define CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR \
+ (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET)
#define CONFIG_SYS_FSL_QMAN_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
#define CONFIG_SYS_FSL_BMAN_ADDR \
#elif defined(CONFIG_GEMINI)
#define _machine _MACH_gemini
#define have_of 0
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
#define _machine _MACH_8260
#define have_of 0
#elif defined(CONFIG_SANDPOINT)
#ifndef CONFIG_BOARD_SPECIFIC_LED
# if defined(CONFIG_8xx)
# include <mpc8xx.h>
-# elif defined(CONFIG_8260)
+# elif defined(CONFIG_MPC8260)
# include <mpc8260.h>
# elif defined(CONFIG_5xx)
# include <mpc5xx.h>
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
-#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \
+#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_MPC8260) \
|| defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
unsigned long bi_immr_base; /* base of IMMR register */
#endif
## Build a couple of necessary functions into a private libgcc
## if the user asked for it
-ifdef USE_PRIVATE_LIBGCC
-lib-y += _ashldi3.o
-lib-y += _ashrdi3.o
-lib-y += _lshrdi3.o
-endif
+lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _ashldi3.o _ashrdi3.o _lshrdi3.o
MINIMAL=
serial_init,
console_init_f,
display_options,
-#if defined(CONFIG_8260)
+#if defined(CONFIG_MPC8260)
prt_8260_rsr,
prt_8260_clks,
-#endif /* CONFIG_8260 */
+#endif /* CONFIG_MPC8260 */
#if defined(CONFIG_MPC83xx)
prt_83xx_rsr,
#endif
bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
#endif
-#if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \
+#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260) || defined(CONFIG_5xx) || \
defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
#endif
bootstage_mark(BOOTSTAGE_ID_RUN_OS);
+#ifdef CONFIG_BOOTSTAGE_FDT
+ bootstage_fdt_add_report();
+#endif
+#ifdef CONFIG_BOOTSTAGE_REPORT
+ bootstage_report();
+#endif
+
#if defined(CONFIG_SYS_INIT_RAM_LOCK) && !defined(CONFIG_E500)
unlock_ram_in_cache();
#endif
#define SPACE_REQUIRED ((32*4)+(32*8)+(6*4))
-#ifdef CONFIG_8260
+#ifdef CONFIG_MPC8260
/* store floating double indexed */
#define STFDI(n,p) __asm__ __volatile__ ("stfd " #n ",%0" : "=o"(p[2*n]))
/* store floating double multiple */
*ptr++ = regs->gpr[i];
/* Floating Point Regs */
-#ifdef CONFIG_8260
+#ifdef CONFIG_MPC8260
STFDM(ptr);
ptr += 32*2;
#else
/* set the value of the CPU registers */
-#ifdef CONFIG_8260
+#ifdef CONFIG_MPC8260
/* load floating double */
#define LFD(n,v) __asm__ __volatile__ ("lfd " #n ",%0" :: "o"(v))
/* load floating double indexed */
regs->gpr[regno] = *ptr;
else switch (regno) {
-#ifdef CONFIG_8260
+#ifdef CONFIG_MPC8260
#define caseF(n) \
case (n) + 32: LFD(n, *ptr); break;
regs->gpr[i] = *ptr++;
/* Floating Point Regs */
-#ifdef CONFIG_8260
+#ifdef CONFIG_MPC8260
LFDM(ptr);
#endif
ptr += 32*2;
PLATFORM_CPPFLAGS += -DCONFIG_ARCH_MAP_SYSMEM -DCONFIG_SYS_GENERIC_BOARD
PLATFORM_LIBS += -lrt
+ifdef CONFIG_SANDBOX_SDL
+PLATFORM_LIBS += $(shell sdl-config --libs)
+PLATFORM_CPPFLAGS += $(shell sdl-config --cflags)
+endif
+
# Support generic board on sandbox
__HAVE_ARCH_GENERIC_BOARD := y
cmd_u-boot__ = $(CC) -o $@ -T u-boot.lds \
-Wl,--start-group $(u-boot-main) -Wl,--end-group \
$(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map
+
+CONFIG_ARCH_DEVICE_TREE := sandbox
#
obj-y := cpu.o os.o start.o state.o
+obj-$(CONFIG_SANDBOX_SDL) += sdl.o
# os.c is build in the system environment, so needs standard includes
# CFLAGS_REMOVE_os.o cannot be used to drop header include path
$(obj)/os.o: $(src)/os.c FORCE
$(call if_changed_dep,cc_os.o)
+$(obj)/sdl.o: $(src)/sdl.c FORCE
+ $(call if_changed_dep,cc_os.o)
return (void *)(gd->arch.ram_buf + paddr);
}
-phys_addr_t map_to_sysmem(void *ptr)
+phys_addr_t map_to_sysmem(const void *ptr)
{
return (u8 *)ptr - gd->arch.ram_buf;
}
return close(fd);
}
+int os_unlink(const char *pathname)
+{
+ return unlink(pathname);
+}
+
void os_exit(int exit_code)
{
exit(exit_code);
/* Restore tty state when we exit */
static struct termios orig_term;
+static bool term_setup;
static void os_fd_restore(void)
{
- tcsetattr(0, TCSANOW, &orig_term);
+ if (term_setup)
+ tcsetattr(0, TCSANOW, &orig_term);
}
/* Put tty into raw mode so <tab> and <ctrl+c> work */
-void os_tty_raw(int fd)
+void os_tty_raw(int fd, bool allow_sigs)
{
- static int setup = 0;
struct termios term;
- if (setup)
+ if (term_setup)
return;
- setup = 1;
+ term_setup = true;
/* If not a tty, don't complain */
if (tcgetattr(fd, &orig_term))
term.c_iflag = IGNBRK | IGNPAR;
term.c_oflag = OPOST | ONLCR;
term.c_cflag = CS8 | CREAD | CLOCAL;
- term.c_lflag = 0;
+ term.c_lflag = allow_sigs ? ISIG : 0;
if (tcsetattr(fd, TCSANOW, &term))
return;
return 0;
}
+
+static int make_exec(char *fname, const void *data, int size)
+{
+ int fd;
+
+ strcpy(fname, "/tmp/u-boot.jump.XXXXXX");
+ fd = mkstemp(fname);
+ if (fd < 0)
+ return -ENOENT;
+ if (write(fd, data, size) < 0)
+ return -EIO;
+ close(fd);
+ if (chmod(fname, 0777))
+ return -ENOEXEC;
+
+ return 0;
+}
+
+static int add_args(char ***argvp, const char *add_args[], int count)
+{
+ char **argv;
+ int argc;
+
+ for (argv = *argvp, argc = 0; (*argvp)[argc]; argc++)
+ ;
+
+ argv = malloc((argc + count + 1) * sizeof(char *));
+ if (!argv) {
+ printf("Out of memory for %d argv\n", count);
+ return -ENOMEM;
+ }
+ memcpy(argv, *argvp, argc * sizeof(char *));
+ memcpy(argv + argc, add_args, count * sizeof(char *));
+ argv[argc + count] = NULL;
+
+ *argvp = argv;
+ return 0;
+}
+
+int os_jump_to_image(const void *dest, int size)
+{
+ struct sandbox_state *state = state_get_current();
+ char fname[30], mem_fname[30];
+ int fd, err;
+ const char *extra_args[5];
+ char **argv = state->argv;
+#ifdef DEBUG
+ int argc, i;
+#endif
+
+ err = make_exec(fname, dest, size);
+ if (err)
+ return err;
+
+ strcpy(mem_fname, "/tmp/u-boot.mem.XXXXXX");
+ fd = mkstemp(mem_fname);
+ if (fd < 0)
+ return -ENOENT;
+ close(fd);
+ err = os_write_ram_buf(mem_fname);
+ if (err)
+ return err;
+
+ os_fd_restore();
+
+ extra_args[0] = "-j";
+ extra_args[1] = fname;
+ extra_args[2] = "-m";
+ extra_args[3] = mem_fname;
+ extra_args[4] = "--rm_memory";
+ err = add_args(&argv, extra_args,
+ sizeof(extra_args) / sizeof(extra_args[0]));
+ if (err)
+ return err;
+
+#ifdef DEBUG
+ for (i = 0; argv[i]; i++)
+ printf("%d %s\n", i, argv[i]);
+#endif
+
+ if (state_uninit())
+ os_exit(2);
+
+ err = execv(fname, argv);
+ free(argv);
+ if (err)
+ return err;
+
+ return unlink(fname);
+}
--- /dev/null
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <errno.h>
+#include <linux/input.h>
+#include <SDL/SDL.h>
+#include <sound.h>
+#include <asm/state.h>
+
+static struct sdl_info {
+ SDL_Surface *screen;
+ int width;
+ int height;
+ int depth;
+ int pitch;
+ uint frequency;
+ uint audio_pos;
+ uint audio_size;
+ uint8_t *audio_data;
+ bool audio_active;
+ bool inited;
+} sdl;
+
+static void sandbox_sdl_poll_events(void)
+{
+ /*
+ * We don't want to include common.h in this file since it uses
+ * system headers. So add a declation here.
+ */
+ extern void reset_cpu(unsigned long addr);
+ SDL_Event event;
+
+ while (SDL_PollEvent(&event)) {
+ switch (event.type) {
+ case SDL_QUIT:
+ puts("LCD window closed - quitting\n");
+ reset_cpu(1);
+ break;
+ }
+ }
+}
+
+static int sandbox_sdl_ensure_init(void)
+{
+ if (!sdl.inited) {
+ if (SDL_Init(0) < 0) {
+ printf("Unable to initialize SDL: %s\n",
+ SDL_GetError());
+ return -EIO;
+ }
+
+ atexit(SDL_Quit);
+
+ sdl.inited = true;
+ }
+ return 0;
+}
+
+int sandbox_sdl_init_display(int width, int height, int log2_bpp)
+{
+ struct sandbox_state *state = state_get_current();
+ int err;
+
+ if (!width || !state->show_lcd)
+ return 0;
+ err = sandbox_sdl_ensure_init();
+ if (err)
+ return err;
+ if (SDL_InitSubSystem(SDL_INIT_VIDEO) < 0) {
+ printf("Unable to initialize SDL LCD: %s\n", SDL_GetError());
+ return -EPERM;
+ }
+ SDL_WM_SetCaption("U-Boot", "U-Boot");
+
+ sdl.width = width;
+ sdl.height = height;
+ sdl.depth = 1 << log2_bpp;
+ sdl.pitch = sdl.width * sdl.depth / 8;
+ sdl.screen = SDL_SetVideoMode(width, height, 0, 0);
+ sandbox_sdl_poll_events();
+
+ return 0;
+}
+
+int sandbox_sdl_sync(void *lcd_base)
+{
+ SDL_Surface *frame;
+
+ frame = SDL_CreateRGBSurfaceFrom(lcd_base, sdl.width, sdl.height,
+ sdl.depth, sdl.pitch,
+ 0x1f << 11, 0x3f << 5, 0x1f << 0, 0);
+ SDL_BlitSurface(frame, NULL, sdl.screen, NULL);
+ SDL_FreeSurface(frame);
+ SDL_UpdateRect(sdl.screen, 0, 0, 0, 0);
+ sandbox_sdl_poll_events();
+
+ return 0;
+}
+
+#define NONE (-1)
+#define NUM_SDL_CODES (SDLK_UNDO + 1)
+
+static int16_t sdl_to_keycode[NUM_SDL_CODES] = {
+ /* 0 */
+ NONE, NONE, NONE, NONE, NONE,
+ NONE, NONE, NONE, KEY_BACKSPACE, KEY_TAB,
+ NONE, NONE, NONE, KEY_ENTER, NONE,
+ NONE, NONE, NONE, NONE, KEY_POWER, /* use PAUSE as POWER */
+
+ /* 20 */
+ NONE, NONE, NONE, NONE, NONE,
+ NONE, NONE, KEY_ESC, NONE, NONE,
+ NONE, NONE, KEY_SPACE, NONE, NONE,
+ NONE, NONE, NONE, NONE, NONE,
+
+ /* 40 */
+ NONE, NONE, NONE, NONE, KEY_COMMA,
+ KEY_MINUS, KEY_DOT, KEY_SLASH, KEY_0, KEY_1,
+ KEY_2, KEY_3, KEY_4, KEY_5, KEY_6,
+ KEY_7, KEY_8, KEY_9, NONE, KEY_SEMICOLON,
+
+ /* 60 */
+ NONE, KEY_EQUAL, NONE, NONE, NONE,
+ NONE, NONE, NONE, NONE, NONE,
+ NONE, NONE, NONE, NONE, NONE,
+ NONE, NONE, NONE, NONE, NONE,
+
+ /* 80 */
+ NONE, NONE, NONE, NONE, NONE,
+ NONE, NONE, NONE, NONE, NONE,
+ NONE, NONE, KEY_BACKSLASH, NONE, NONE,
+ NONE, KEY_GRAVE, KEY_A, KEY_B, KEY_C,
+
+ /* 100 */
+ KEY_D, KEY_E, KEY_F, KEY_G, KEY_H,
+ KEY_I, KEY_J, KEY_K, KEY_L, KEY_M,
+ KEY_N, KEY_O, KEY_P, KEY_Q, KEY_R,
+ KEY_S, KEY_T, KEY_U, KEY_V, KEY_W,
+
+ /* 120 */
+ KEY_X, KEY_Y, KEY_Z, NONE, NONE,
+ NONE, NONE, KEY_DELETE, NONE, NONE,
+ NONE, NONE, NONE, NONE, NONE,
+ NONE, NONE, NONE, NONE, NONE,
+
+ /* 140 */
+ NONE, NONE, NONE, NONE, NONE,
+ NONE, NONE, NONE, NONE, NONE,
+ NONE, NONE, NONE, NONE, NONE,
+ NONE, NONE, NONE, NONE, NONE,
+
+ /* 160 */
+ NONE, NONE, NONE, NONE, NONE,
+ NONE, NONE, NONE, NONE, NONE,
+ NONE, NONE, NONE, NONE, NONE,
+ NONE, NONE, NONE, NONE, NONE,
+
+ /* 180 */
+ NONE, NONE, NONE, NONE, NONE,
+ NONE, NONE, NONE, NONE, NONE,
+ NONE, NONE, NONE, NONE, NONE,
+ NONE, NONE, NONE, NONE, NONE,
+
+ /* 200 */
+ NONE, NONE, NONE, NONE, NONE,
+ NONE, NONE, NONE, NONE, NONE,
+ NONE, NONE, NONE, NONE, NONE,
+ NONE, NONE, NONE, NONE, NONE,
+
+ /* 220 */
+ NONE, NONE, NONE, NONE, NONE,
+ NONE, NONE, NONE, NONE, NONE,
+ NONE, NONE, NONE, NONE, NONE,
+ NONE, NONE, NONE, NONE, NONE,
+
+ /* 240 */
+ NONE, NONE, NONE, NONE, NONE,
+ NONE, NONE, NONE, NONE, NONE,
+ NONE, NONE, NONE, NONE, NONE,
+ NONE, KEY_KP0, KEY_KP1, KEY_KP2, KEY_KP3,
+
+ /* 260 */
+ KEY_KP4, KEY_KP5, KEY_KP6, KEY_KP7, KEY_KP8,
+ KEY_KP9, KEY_KPDOT, KEY_KPSLASH, KEY_KPASTERISK, KEY_KPMINUS,
+ KEY_KPPLUS, KEY_KPENTER, KEY_KPEQUAL, KEY_UP, KEY_DOWN,
+ KEY_RIGHT, KEY_LEFT, KEY_INSERT, KEY_HOME, KEY_END,
+
+ /* 280 */
+ KEY_PAGEUP, KEY_PAGEDOWN, KEY_F1, KEY_F2, KEY_F3,
+ KEY_F4, KEY_F5, KEY_F6, KEY_F7, KEY_F8,
+ KEY_F9, KEY_F10, KEY_F11, KEY_F12, NONE,
+ NONE, NONE, NONE, NONE, NONE,
+
+ /* 300 */
+ KEY_NUMLOCK, KEY_CAPSLOCK, KEY_SCROLLLOCK, KEY_RIGHTSHIFT,
+ KEY_LEFTSHIFT,
+ KEY_RIGHTCTRL, KEY_LEFTCTRL, KEY_RIGHTALT, KEY_LEFTALT, KEY_RIGHTMETA,
+ KEY_LEFTMETA, NONE, KEY_FN, NONE, KEY_COMPOSE,
+ NONE, KEY_PRINT, KEY_SYSRQ, KEY_PAUSE, NONE,
+
+ /* 320 */
+ NONE, NONE, NONE,
+};
+
+int sandbox_sdl_scan_keys(int key[], int max_keys)
+{
+ Uint8 *keystate;
+ int i, count;
+
+ sandbox_sdl_poll_events();
+ keystate = SDL_GetKeyState(NULL);
+ for (i = count = 0; i < NUM_SDL_CODES; i++) {
+ if (count >= max_keys)
+ break;
+ else if (keystate[i])
+ key[count++] = sdl_to_keycode[i];
+ }
+
+ return count;
+}
+
+int sandbox_sdl_key_pressed(int keycode)
+{
+ int key[8]; /* allow up to 8 keys to be pressed at once */
+ int count;
+ int i;
+
+ count = sandbox_sdl_scan_keys(key, sizeof(key) / sizeof(key[0]));
+ for (i = 0; i < count; i++) {
+ if (key[i] == keycode)
+ return 0;
+ }
+
+ return -ENOENT;
+}
+
+void sandbox_sdl_fill_audio(void *udata, Uint8 *stream, int len)
+{
+ int avail;
+
+ avail = sdl.audio_size - sdl.audio_pos;
+ if (avail < len)
+ len = avail;
+
+ SDL_MixAudio(stream, sdl.audio_data + sdl.audio_pos, len,
+ SDL_MIX_MAXVOLUME);
+ sdl.audio_pos += len;
+
+ /* Loop if we are at the end */
+ if (sdl.audio_pos == sdl.audio_size)
+ sdl.audio_pos = 0;
+}
+
+int sandbox_sdl_sound_init(void)
+{
+ SDL_AudioSpec wanted;
+
+ if (sandbox_sdl_ensure_init())
+ return -1;
+
+ if (sdl.audio_active)
+ return 0;
+
+ /*
+ * At present all sandbox sounds crash. This is probably due to
+ * symbol name conflicts with U-Boot. We can remove the malloc()
+ * probles with:
+ *
+ * #define USE_DL_PREFIX
+ *
+ * and get this:
+ *
+ * Assertion 'e->pollfd->fd == e->fd' failed at pulse/mainloop.c:676,
+ * function dispatch_pollfds(). Aborting.
+ *
+ * The right solution is probably to make U-Boot's names private or
+ * link os.c and sdl.c against their libraries before liking with
+ * U-Boot. TBD. For now sound is disabled.
+ */
+ printf("(Warning: sandbox sound disabled)\n");
+ return 0;
+
+ /* Set the audio format */
+ wanted.freq = 22050;
+ wanted.format = AUDIO_S16;
+ wanted.channels = 1; /* 1 = mono, 2 = stereo */
+ wanted.samples = 1024; /* Good low-latency value for callback */
+ wanted.callback = sandbox_sdl_fill_audio;
+ wanted.userdata = NULL;
+
+ sdl.audio_size = sizeof(uint16_t) * wanted.freq;
+ sdl.audio_data = malloc(sdl.audio_size);
+ if (!sdl.audio_data) {
+ printf("%s: Out of memory\n", __func__);
+ return -1;
+ }
+ sdl.audio_pos = 0;
+
+ if (SDL_InitSubSystem(SDL_INIT_AUDIO) < 0) {
+ printf("Unable to initialize SDL audio: %s\n", SDL_GetError());
+ goto err;
+ }
+
+ /* Open the audio device, forcing the desired format */
+ if (SDL_OpenAudio(&wanted, NULL) < 0) {
+ printf("Couldn't open audio: %s\n", SDL_GetError());
+ goto err;
+ }
+ sdl.audio_active = true;
+
+ return 0;
+
+err:
+ free(sdl.audio_data);
+ return -1;
+}
+
+int sandbox_sdl_sound_start(uint frequency)
+{
+ if (!sdl.audio_active)
+ return -1;
+ sdl.frequency = frequency;
+ sound_create_square_wave((unsigned short *)sdl.audio_data,
+ sdl.audio_size, frequency);
+ sdl.audio_pos = 0;
+ SDL_PauseAudio(0);
+
+ return 0;
+}
+
+int sandbox_sdl_sound_stop(void)
+{
+ if (!sdl.audio_active)
+ return -1;
+ SDL_PauseAudio(1);
+
+ return 0;
+}
SANDBOX_CMDLINE_OPT_SHORT(interactive, 'i', 0, "Enter interactive mode");
+static int sandbox_cmdline_cb_jump(struct sandbox_state *state,
+ const char *arg)
+{
+ /* Remember to delete this U-Boot image later */
+ state->jumped_fname = arg;
+
+ return 0;
+}
+SANDBOX_CMDLINE_OPT_SHORT(jump, 'j', 1, "Jumped from previous U-Boot");
+
static int sandbox_cmdline_cb_memory(struct sandbox_state *state,
const char *arg)
{
SANDBOX_CMDLINE_OPT_SHORT(memory, 'm', 1,
"Read/write ram_buf memory contents from file");
+static int sandbox_cmdline_cb_rm_memory(struct sandbox_state *state,
+ const char *arg)
+{
+ state->ram_buf_rm = true;
+
+ return 0;
+}
+SANDBOX_CMDLINE_OPT(rm_memory, 0, "Remove memory file after reading");
+
static int sandbox_cmdline_cb_state(struct sandbox_state *state,
const char *arg)
{
SANDBOX_CMDLINE_OPT_SHORT(ignore_missing, 'n', 0,
"Ignore missing state on read");
+static int sandbox_cmdline_cb_show_lcd(struct sandbox_state *state,
+ const char *arg)
+{
+ state->show_lcd = true;
+ return 0;
+}
+SANDBOX_CMDLINE_OPT_SHORT(show_lcd, 'l', 0,
+ "Show the sandbox LCD display");
+
+static const char *term_args[STATE_TERM_COUNT] = {
+ "raw-with-sigs",
+ "raw",
+ "cooked",
+};
+
+static int sandbox_cmdline_cb_terminal(struct sandbox_state *state,
+ const char *arg)
+{
+ int i;
+
+ for (i = 0; i < STATE_TERM_COUNT; i++) {
+ if (!strcmp(arg, term_args[i])) {
+ state->term_raw = i;
+ return 0;
+ }
+ }
+
+ printf("Unknown terminal setting '%s' (", arg);
+ for (i = 0; i < STATE_TERM_COUNT; i++)
+ printf("%s%s", i ? ", " : "", term_args[i]);
+ puts(")\n");
+
+ return 1;
+}
+SANDBOX_CMDLINE_OPT_SHORT(terminal, 't', 1,
+ "Set terminal to raw/cooked mode");
+
int main(int argc, char *argv[])
{
struct sandbox_state *state;
if (ret)
goto err;
+ /* Remove old memory file if required */
+ if (state->ram_buf_rm && state->ram_buf_fname)
+ os_unlink(state->ram_buf_fname);
+
/* Do pre- and post-relocation init */
board_init_f(0);
state = &main_state;
- if (state->write_ram_buf) {
+ if (state->write_ram_buf && !state->ram_buf_rm) {
err = os_write_ram_buf(state->ram_buf_fname);
if (err) {
printf("Failed to write RAM buffer\n");
}
}
+ /* Delete this at the last moment so as not to upset gdb too much */
+ if (state->jumped_fname)
+ os_unlink(state->jumped_fname);
+
if (state->state_fdt)
os_free(state->state_fdt);
memset(state, '\0', sizeof(*state));
--- /dev/null
+dtb-$(CONFIG_SANDBOX) += sandbox.dtb
+
+targets += $(dtb-y)
+
+DTC_FLAGS += -R 4 -p 0x1000
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+ @:
+
+clean-files := *.dtb
--- /dev/null
+/dts-v1/;
+
+/ {
+ triangle {
+ compatible = "demo-shape";
+ colour = "cyan";
+ sides = <3>;
+ character = <83>;
+ };
+ square {
+ compatible = "demo-shape";
+ colour = "blue";
+ sides = <4>;
+ };
+ hexagon {
+ compatible = "demo-simple";
+ colour = "white";
+ sides = <6>;
+ };
+
+ host@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "sandbox,host-emulation";
+ cros-ec@0 {
+ reg = <0>;
+ compatible = "google,cros-ec";
+
+ /*
+ * This describes the flash memory within the EC. Note
+ * that the STM32L flash erases to 0, not 0xff.
+ */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ flash@8000000 {
+ reg = <0x08000000 0x20000>;
+ erase-value = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* Information for sandbox */
+ ro {
+ reg = <0 0xf000>;
+ };
+ wp-ro {
+ reg = <0xf000 0x1000>;
+ };
+ rw {
+ reg = <0x10000 0x10000>;
+ };
+ };
+ };
+ };
+
+ lcd {
+ compatible = "sandbox,lcd-sdl";
+ xres = <800>;
+ yres = <600>;
+ };
+
+ cros-ec-keyb {
+ compatible = "google,cros-ec-keyb";
+ google,key-rows = <8>;
+ google,key-columns = <13>;
+ google,repeat-delay-ms = <240>;
+ google,repeat-rate-ms = <30>;
+ google,ghost-filter;
+ /*
+ * Keymap entries take the form of 0xRRCCKKKK where
+ * RR=Row CC=Column KKKK=Key Code
+ * The values below are for a US keyboard layout and
+ * are taken from the Linux driver. Note that the
+ * 102ND key is not used for US keyboards.
+ */
+ linux,keymap = <
+ /* CAPSLCK F1 B F10 */
+ 0x0001003a 0x0002003b 0x00030030 0x00040044
+ /* N = R_ALT ESC */
+ 0x00060031 0x0008000d 0x000a0064 0x01010001
+ /* F4 G F7 H */
+ 0x0102003e 0x01030022 0x01040041 0x01060023
+ /* ' F9 BKSPACE L_CTRL */
+ 0x01080028 0x01090043 0x010b000e 0x0200001d
+ /* TAB F3 T F6 */
+ 0x0201000f 0x0202003d 0x02030014 0x02040040
+ /* ] Y 102ND [ */
+ 0x0205001b 0x02060015 0x02070056 0x0208001a
+ /* F8 GRAVE F2 5 */
+ 0x02090042 0x03010029 0x0302003c 0x03030006
+ /* F5 6 - \ */
+ 0x0304003f 0x03060007 0x0308000c 0x030b002b
+ /* R_CTRL A D F */
+ 0x04000061 0x0401001e 0x04020020 0x04030021
+ /* S K J ; */
+ 0x0404001f 0x04050025 0x04060024 0x04080027
+ /* L ENTER Z C */
+ 0x04090026 0x040b001c 0x0501002c 0x0502002e
+ /* V X , M */
+ 0x0503002f 0x0504002d 0x05050033 0x05060032
+ /* L_SHIFT / . SPACE */
+ 0x0507002a 0x05080035 0x05090034 0x050B0039
+ /* 1 3 4 2 */
+ 0x06010002 0x06020004 0x06030005 0x06040003
+ /* 8 7 0 9 */
+ 0x06050009 0x06060008 0x0608000b 0x0609000a
+ /* L_ALT DOWN RIGHT Q */
+ 0x060a0038 0x060b006c 0x060c006a 0x07010010
+ /* E R W I */
+ 0x07020012 0x07030013 0x07040011 0x07050017
+ /* U R_SHIFT P O */
+ 0x07060016 0x07070036 0x07080019 0x07090018
+ /* UP LEFT */
+ 0x070b0067 0x070c0069>;
+ };
+
+};
--- /dev/null
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __SANDBOX_SOUND_H
+#define __SANDBOX_SOUND_H
+
+int sound_play(unsigned int msec, unsigned int frequency);
+
+int sound_init(const void *blob);
+
+#endif
* @param gp GPIO number
* @return -1 on error, 0 if GPIO is low, >0 if high
*/
-int sandbox_gpio_get_value(unsigned gp);
+int sandbox_gpio_get_value(struct device *dev, unsigned int offset);
/**
* Set the simulated value of a GPIO (used only in sandbox test code)
* @param value value to set (0 for low, non-zero for high)
* @return -1 on error, 0 if ok
*/
-int sandbox_gpio_set_value(unsigned gp, int value);
+int sandbox_gpio_set_value(struct device *dev, unsigned int offset, int value);
/**
* Return the simulated direction of a GPIO (used only in sandbox test code)
* @param gp GPIO number
* @return -1 on error, 0 if GPIO is input, >0 if output
*/
-int sandbox_gpio_get_direction(unsigned gp);
+int sandbox_gpio_get_direction(struct device *dev, unsigned int offset);
/**
* Set the simulated direction of a GPIO (used only in sandbox test code)
* @param output 0 to set as input, 1 to set as output
* @return -1 on error, 0 if ok
*/
-int sandbox_gpio_set_direction(unsigned gp, int output);
-
-/* Display information about each GPIO */
-void gpio_info(void);
-
-#define gpio_status() gpio_info()
+int sandbox_gpio_set_direction(struct device *dev, unsigned int offset,
+ int output);
#endif
--- /dev/null
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __SANDBOX_SDL_H
+#define __SANDBOX_SDL_H
+
+#include <errno.h>
+
+#ifdef CONFIG_SANDBOX_SDL
+
+/**
+ * sandbox_sdl_init_display() - Set up SDL video ready for use
+ *
+ * @width: Window width in pixels
+ * @height Window height in pixels
+ * @log2_bpp: Log to base 2 of the number of bits per pixel. So a 32bpp
+ * display will pass 5, since 2*5 = 32
+ * @return 0 if OK, -ENODEV if no device, -EIO if SDL failed to initialize
+ * and -EPERM if the video failed to come up.
+ */
+int sandbox_sdl_init_display(int width, int height, int log2_bpp);
+
+/**
+ * sandbox_sdl_sync() - Sync current U-Boot LCD frame buffer to SDL
+ *
+ * This must be called periodically to update the screen for SDL so that the
+ * user can see it.
+ *
+ * @lcd_base: Base of frame buffer
+ * @return 0 if screen was updated, -ENODEV is there is no screen.
+ */
+int sandbox_sdl_sync(void *lcd_base);
+
+/**
+ * sandbox_sdl_scan_keys() - scan for pressed keys
+ *
+ * Works out which keys are pressed and returns a list
+ *
+ * @key: Array to receive keycodes
+ * @max_keys: Size of array
+ * @return number of keycodes found, 0 if none, -ENODEV if no keyboard
+ */
+int sandbox_sdl_scan_keys(int key[], int max_keys);
+
+/**
+ * sandbox_sdl_key_pressed() - check if a particular key is pressed
+ *
+ * @keycode: Keycode to check (KEY_... - see include/linux/input.h
+ * @return 0 if pressed, -ENOENT if not pressed. -ENODEV if keybord not
+ * available,
+ */
+int sandbox_sdl_key_pressed(int keycode);
+
+/**
+ * sandbox_sdl_sound_start() - start playing a sound
+ *
+ * @frequency: Frequency of sounds in Hertz
+ * @return 0 if OK, -ENODEV if no sound is available
+ */
+int sandbox_sdl_sound_start(uint frequency);
+
+/**
+ * sandbox_sdl_sound_stop() - stop playing a sound
+ *
+ * @return 0 if OK, -ENODEV if no sound is available
+ */
+int sandbox_sdl_sound_stop(void);
+
+/**
+ * sandbox_sdl_sound_init() - set up the sound system
+ *
+ * @return 0 if OK, -ENODEV if no sound is available
+ */
+int sandbox_sdl_sound_init(void);
+
+#else
+static inline int sandbox_sdl_init_display(int width, int height,
+ int log2_bpp)
+{
+ return -ENODEV;
+}
+
+static inline int sandbox_sdl_sync(void *lcd_base)
+{
+ return -ENODEV;
+}
+
+static inline int sandbox_sdl_scan_keys(int key[], int max_keys)
+{
+ return -ENODEV;
+}
+
+static inline int sandbox_sdl_key_pressed(int keycode)
+{
+ return -ENODEV;
+}
+
+static inline int sandbox_sdl_sound_start(uint frequency)
+{
+ return -ENODEV;
+}
+
+static inline int sandbox_sdl_sound_stop(void)
+{
+ return -ENODEV;
+}
+
+static inline int sandbox_sdl_sound_init(void)
+{
+ return -ENODEV;
+}
+
+#endif
+
+#endif
STATE_EXIT_POWER_OFF,
};
+/**
+ * Selects the behavior of the serial terminal.
+ *
+ * If Ctrl-C is processed by U-Boot, then the only way to quit sandbox is with
+ * the 'reset' command, or equivalent.
+ *
+ * If the terminal is cooked, then Ctrl-C will terminate U-Boot, and the
+ * command line will not be quite such a faithful emulation.
+ *
+ * Options are:
+ *
+ * raw-with-sigs - Raw, but allow signals (Ctrl-C will quit)
+ * raw - Terminal is always raw
+ * cooked - Terminal is always cooked
+ */
+enum state_terminal_raw {
+ STATE_TERM_RAW_WITH_SIGS, /* Default */
+ STATE_TERM_RAW,
+ STATE_TERM_COOKED,
+
+ STATE_TERM_COUNT,
+};
+
struct sandbox_spi_info {
const char *spec;
const struct sandbox_spi_emu_ops *ops;
enum exit_type_id exit_type; /* How we exited U-Boot */
const char *parse_err; /* Error to report from parsing */
int argc; /* Program arguments */
- char **argv;
+ char **argv; /* Command line arguments */
+ const char *jumped_fname; /* Jumped from previous U_Boot */
uint8_t *ram_buf; /* Emulated RAM buffer */
unsigned int ram_size; /* Size of RAM buffer */
const char *ram_buf_fname; /* Filename to use for RAM buffer */
+ bool ram_buf_rm; /* Remove RAM buffer file after read */
bool write_ram_buf; /* Write RAM buffer on exit */
const char *state_fname; /* File containing sandbox state */
void *state_fdt; /* Holds saved state for sandbox */
bool read_state; /* Read sandbox state on startup */
bool write_state; /* Write sandbox state on exit */
bool ignore_missing_state_on_read; /* No error if state missing */
+ bool show_lcd; /* Show LCD on start-up */
+ enum state_terminal_raw term_raw; /* Terminal raw/cooked */
/* Pointer to information for each SPI bus/cs */
struct sandbox_spi_info spi[CONFIG_SANDBOX_SPI_MAX_BUS]
int cleanup_before_linux(void);
+/* drivers/video/sandbox_sdl.c */
+int sandbox_lcd_sdl_early_init(void);
+
#endif /* _U_BOOT_SANDBOX_H_ */
# SPDX-License-Identifier: GPL-2.0+
#
-CROSS_COMPILE ?= sh4-linux-
+ifeq ($(CROSS_COMPILE),)
+CROSS_COMPILE := sh4-linux-
+endif
CONFIG_STANDALONE_LOAD_ADDR ?= 0x8C000000
ifeq ($(CPU),sh2)
PLATFORM_CPPFLAGS += -DCONFIG_SH -D__SH__
PLATFORM_LDFLAGS += -e $(CONFIG_SYS_TEXT_BASE) --defsym reloc_dst=$(CONFIG_SYS_TEXT_BASE)
LDFLAGS_FINAL = --gc-sections
+PLATFORM_RELFLAGS += -ffixed-r13
ENDIANNESS += -EB
ifdef CONFIG_SH2A
-PLATFORM_CPPFLAGS += -m2a -m2a-nofpu -mb -ffreestanding
+PLATFORM_CPPFLAGS += -m2a -m2a-nofpu -mb
else # SH2
PLATFORM_CPPFLAGS += -m3e -mb
endif
PLATFORM_CPPFLAGS += -DCONFIG_SH2 $(call cc-option,-mno-fdpic)
-PLATFORM_RELFLAGS += -ffixed-r13
PLATFORM_LDFLAGS += $(ENDIANNESS)
#
#
PLATFORM_CPPFLAGS += -DCONFIG_SH3 -m3
-PLATFORM_RELFLAGS += -ffixed-r13
#
#
PLATFORM_CPPFLAGS += -DCONFIG_SH4 -m4-nofpu
-PLATFORM_RELFLAGS += -ffixed-r13
#define PUDR 0xA4050162
#define PVDR 0xA4050164
#define PWDR 0xA4050166
-#define PYDR 0xA4050168
-#define PZDR 0xA405016A
+#define PXDR 0xA4050168
+#define PYDR 0xA405016A
+#define PZDR 0xA405016C
/* UBC */
#define CBR0 0xFF200000
#define PUDR 0xA4050162
#define PVDR 0xA4050164
#define PWDR 0xA4050166
-#define PYDR 0xA4050168
-#define PZDR 0xA405016A
+#define PXDR 0xA4050168
+#define PYDR 0xA405016A
+#define PZDR 0xA405016C
/* UBC */
/* H-UDI */
#define PUDR 0xA4050162
#define PVDR 0xA4050164
#define PWDR 0xA4050166
-#define PYDR 0xA4050168
-#define PZDR 0xA405016A
+#define PXDR 0xA4050168
+#define PYDR 0xA405016A
+#define PZDR 0xA405016C
/* Ether */
#define EDMR 0xA4600000
endif
obj-$(CONFIG_CMD_SH_ZIMAGEBOOT) += zimageboot.o
-
-
-# Build private libgcc only when asked for
-ifdef USE_PRIVATE_LIBGCC
-lib-y += ashiftrt.o
-lib-y += ashiftlt.o
-lib-y += lshiftrt.o
-lib-y += ashldi3.o
-lib-y += ashrsi3.o
-lib-y += lshrdi3.o
-lib-y += movmem.o
-endif
+lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashiftrt.o ashiftlt.o lshiftrt.o \
+ ashldi3.o ashrsi3.o lshrdi3.o movmem.o
# SPDX-License-Identifier: GPL-2.0+
#
-CROSS_COMPILE ?= sparc-elf-
+ifeq ($(CROSS_COMPILE),)
+CROSS_COMPILE := sparc-elf-
+endif
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000 -L $(gcclibdir) \
- -T $(srctree)/$(src)/sparc.lds
+ -T $(srctree)/examples/standalone/sparc.lds
PLATFORM_CPPFLAGS += -DCONFIG_SPARC -D__sparc__
}
#endif
-static unsigned char root_hub_dev_des[] = {
- 0x12, /* __u8 bLength; */
- 0x01, /* __u8 bDescriptorType; Device */
- 0x00, /* __u16 bcdUSB; v1.0 */
- 0x01,
- 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
- 0x00, /* __u8 bDeviceSubClass; */
- 0x00, /* __u8 bDeviceProtocol; */
- 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
- 0x00, /* __u16 idVendor; */
- 0x00,
- 0x00, /* __u16 idProduct; */
- 0x00,
- 0x00, /* __u16 bcdDevice; */
- 0x00,
- 0x01, /* __u8 iManufacturer; */
- 0x00, /* __u8 iProduct; */
- 0x00, /* __u8 iSerialNumber; */
- 0x01 /* __u8 bNumConfigurations; */
-};
-
-/* Configuration descriptor */
-static unsigned char root_hub_config_des[] = {
- 0x09, /* __u8 bLength; */
- 0x02, /* __u8 bDescriptorType; Configuration */
- 0x19, /* __u16 wTotalLength; */
- 0x00,
- 0x01, /* __u8 bNumInterfaces; */
- 0x01, /* __u8 bConfigurationValue; */
- 0x00, /* __u8 iConfiguration; */
- 0x40, /* __u8 bmAttributes;
- Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
- 0x00, /* __u8 MaxPower; */
-
- /* interface */
- 0x09, /* __u8 if_bLength; */
- 0x04, /* __u8 if_bDescriptorType; Interface */
- 0x00, /* __u8 if_bInterfaceNumber; */
- 0x00, /* __u8 if_bAlternateSetting; */
- 0x01, /* __u8 if_bNumEndpoints; */
- 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
- 0x00, /* __u8 if_bInterfaceSubClass; */
- 0x00, /* __u8 if_bInterfaceProtocol; */
- 0x00, /* __u8 if_iInterface; */
-
- /* endpoint */
- 0x07, /* __u8 ep_bLength; */
- 0x05, /* __u8 ep_bDescriptorType; Endpoint */
- 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
- 0x03, /* __u8 ep_bmAttributes; Interrupt */
- 0x08, /* __u16 ep_wMaxPacketSize; 8 Bytes */
- 0x00,
- 0xff /* __u8 ep_bInterval; 255 ms */
-};
-
-static unsigned char root_hub_hub_des[] = {
- 0x09, /* __u8 bLength; */
- 0x29, /* __u8 bDescriptorType; Hub-descriptor */
- 0x02, /* __u8 bNbrPorts; */
- 0x00, /* __u16 wHubCharacteristics; */
- 0x00,
- 0x01, /* __u8 bPwrOn2pwrGood; 2ms */
- 0x00, /* __u8 bHubContrCurrent; 0 mA */
- 0x00, /* __u8 DeviceRemovable; *** 7 Ports max *** */
- 0xff /* __u8 PortPwrCtrlMask; *** 7 ports max *** */
-};
-
-static unsigned char root_hub_str_index0[] = {
- 0x04, /* __u8 bLength; */
- 0x03, /* __u8 bDescriptorType; String-descriptor */
- 0x09, /* __u8 lang ID */
- 0x04, /* __u8 lang ID */
-};
-
-static unsigned char root_hub_str_index1[] = {
- 28, /* __u8 bLength; */
- 0x03, /* __u8 bDescriptorType; String-descriptor */
- 'U', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'H', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'C', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'I', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- ' ', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'R', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'o', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'o', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 't', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- ' ', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'H', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'u', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'b', /* __u8 Unicode */
- 0, /* __u8 Unicode */
-};
+#define WANT_USB_ROOT_HUB_HUB_DES
+#include <usbroothubdes.h>
+#undef WANT_USB_ROOT_HUB_HUB_DES
/*
* Root Hub Control Pipe (interrupt Pipes are not supported)
CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000
PLATFORM_CPPFLAGS += -fno-strict-aliasing
-PLATFORM_CPPFLAGS += -Wstrict-prototypes
PLATFORM_CPPFLAGS += -mregparm=3
PLATFORM_CPPFLAGS += -fomit-frame-pointer
-PF_CPPFLAGS_X86 := $(call cc-option, -ffreestanding) \
- $(call cc-option, -fno-toplevel-reorder, \
+PF_CPPFLAGS_X86 := $(call cc-option, -fno-toplevel-reorder, \
$(call cc-option, -fno-unit-at-a-time)) \
- $(call cc-option, -fno-stack-protector) \
$(call cc-option, -mpreferred-stack-boundary=2)
PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_X86)
PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm
LDFLAGS_FINAL += --wrap=__moddi3 --wrap=__umoddi3
export NORMAL_LIBGCC = $(shell $(CC) $(CFLAGS) -print-libgcc-file-name)
-PREFIXED_LIBGCC = $(OBJTREE)/arch/$(ARCH)/lib/$(shell basename $(NORMAL_LIBGCC))
-
-export USE_PRIVATE_LIBGCC=$(shell dirname $(PREFIXED_LIBGCC))
+CONFIG_USE_PRIVATE_LIBGCC := arch/x86/lib
LIBGCC := $(notdir $(NORMAL_LIBGCC))
extra-y := $(LIBGCC)
-$(obj)/$(LIBGCC): $(NORMAL_LIBGCC)
- $(OBJCOPY) $< $@ --prefix-symbols=__normal_
+OBJCOPYFLAGS := --prefix-symbols=__normal_
+$(obj)/$(LIBGCC): $(NORMAL_LIBGCC) FORCE
+ $(call if_changed,objcopy)
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
- .phy_addr = 0,
+ .phy_addr = 1,
},
{
.slave_reg_ofs = 0x308,
.sliver_reg_ofs = 0xdc0,
- .phy_addr = 1,
+ .phy_addr = 2,
},
};
/* power-ON 3V3 via Resetcontroller */
oldspeed = i2c_get_bus_speed();
- if (0 != i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC)) {
+ if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
buf = RSTCTRL_FORCE_PWR_NEN;
i2c_write(RSTCTRL_ADDR, RSTCTRL_CTRLREG, 1,
(uint8_t *)&buf, sizeof(buf));
TPS65217_WLEDCTRL1, 0x09, 0xFF);
/* write bootinfo into scratchregister of resetcontroller */
oldspeed = i2c_get_bus_speed();
- if (0 != i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC)) {
+ if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
i2c_write(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1,
(uint8_t *)&buf, sizeof(buf));
i2c_set_bus_speed(oldspeed);
#include <config.h>
#include <common.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/hardware.h>
# (mem base + reserved)
#
-UBL_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/ublimage.cfg
+UBL_CONFIG = $(srctree)/board/$(BOARDDIR)/ublimage.cfg
ifndef CONFIG_SPL_BUILD
ALL-y += u-boot.ubl
else
extern void board_pll_init_f(void);
-#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
static void cram_bcr_write(u32 wr_val)
{
wr_val <<= 2;
return;
}
-#endif
phys_size_t initdram(int board_type)
{
-#if defined(CONFIG_NAND_SPL)
- u32 reg;
-
- /* don't reinit PLL when booting via I2C bootstrap option */
- mfsdr(SDR0_PINSTP, reg);
- if (reg != 0xf0000000)
- board_pll_init_f();
-#endif
-
-#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
int i;
u32 val;
/* Wait a short while, since for NAND booting this is too fast */
for (i=0; i<200000; i++)
;
-#endif
return (CONFIG_SYS_MBYTES_RAM << 20);
}
mtcpr(CPR0_CLKUP, 0x40000000);
}
#endif /* CPU_<speed>_405EZ */
-
-#if defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL)
-/*
- * Get timebase clock frequency
- */
-unsigned long get_tbclk(void)
-{
- unsigned long cpr_plld;
- unsigned long cpr_primad;
- unsigned long primad_cpudv;
- unsigned long pllFbkDiv;
- unsigned long freqProcessor;
-
- /*
- * Read PLL Mode registers
- */
- mfcpr(CPR0_PLLD, cpr_plld);
-
- /*
- * Read CPR_PRIMAD register
- */
- mfcpr(CPR0_PRIMAD, cpr_primad);
-
- /*
- * Determine CPU clock frequency
- */
- primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24);
- if (primad_cpudv == 0)
- primad_cpudv = 16;
-
- /*
- * Determine FBK_DIV.
- */
- pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);
- if (pllFbkDiv == 0)
- pllFbkDiv = 256;
-
- freqProcessor = (CONFIG_SYS_CLK_FREQ * pllFbkDiv) / primad_cpudv;
-
- return (freqProcessor);
-}
-#endif /* defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) */
void configure_ppc440ep_pins(void);
int is_nand_selected(void);
-#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
/*************************************************************************
*
* Bamboo has one bank onboard sdram (plus DIMM)
0,
0
};
-#endif
#if 0
{ /* GPIO Alternate1 Alternate2 Alternate3 */
phys_size_t initdram (int board_type)
{
-#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
long dram_size;
dram_size = spd_sdram();
return dram_size;
-#else
- return CONFIG_SYS_MBYTES_SDRAM << 20;
-#endif
}
/*----------------------------------------------------------------------------+
if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
{
update_ndfc_ios(gpio_tab);
-
-#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL |
SDR0_CUST0_NDFC_ENABLE |
SDR0_CUST0_NDFC_BW_8_BIT |
SDR0_CUST0_NDFC_ARE_MASK |
SDR0_CUST0_CHIPSELGAT_EN1 |
SDR0_CUST0_CHIPSELGAT_EN2);
-#else
- mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL |
- SDR0_CUST0_NDFC_ENABLE |
- SDR0_CUST0_NDFC_BW_8_BIT |
- SDR0_CUST0_NDFC_ARE_MASK |
- SDR0_CUST0_CHIPSELGAT_EN0 |
- SDR0_CUST0_CHIPSELGAT_EN2);
-#endif
-
ndfc_selection_in_fpga();
}
else
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
-#ifndef CONFIG_NAND_SPL
tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G)
-#else
- tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 0, AC_RWX | SA_G)
- tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG)
-#endif
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
tlbentry(CONFIG_SYS_USB_DEVICE, SZ_1K, CONFIG_SYS_USB_DEVICE, 0, AC_RW | SA_IG)
tlbtab_end
-
-#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
- /*
- * For NAND booting the first TLB has to be reconfigured to full size
- * and with caching disabled after running from RAM!
- */
-#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
-#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 0)
-#define TLB02 TLB2(AC_RWX | SA_IG)
-
- .globl reconfig_tlb0
-reconfig_tlb0:
- sync
- isync
- addi r4,r0,0x0000 /* TLB entry #0 */
- lis r5,TLB00@h
- ori r5,r5,TLB00@l
- tlbwe r5,r4,0x0000 /* Save it out */
- lis r5,TLB01@h
- ori r5,r5,TLB01@l
- tlbwe r5,r4,0x0001 /* Save it out */
- lis r5,TLB02@h
- ori r5,r5,TLB02@l
- tlbwe r5,r4,0x0002 /* Save it out */
- sync
- isync
- blr
-#endif
*/
/* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
- mtebc(PB3CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
-#else
mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
-#endif
/* Remove TLB entry of boot EBC mapping */
remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
* use the speed up boot process. It is patched after relocation to
* enable SA_I
*/
-#ifndef CONFIG_NAND_SPL
tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_RWX | SA_G) /* TLB 0 */
-#else
- tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 4, AC_RWX | SA_G)
- tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG)
- tlbentry(256 << 20, SZ_256M, 256 << 20, 0, AC_RWX | SA_IG)
-#endif
/*
* TLB entries for SDRAM are not needed on this platform.
#endif
tlbtab_end
-
-#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
- /*
- * For NAND booting the first TLB has to be reconfigured to full size
- * and with caching disabled after running from RAM!
- */
-#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
-#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
-#define TLB02 TLB2(AC_RWX | SA_IG)
-
- .globl reconfig_tlb0
-reconfig_tlb0:
- sync
- isync
- addi r4,r0,0x0000 /* TLB entry #0 */
- lis r5,TLB00@h
- ori r5,r5,TLB00@l
- tlbwe r5,r4,0x0000 /* Save it out */
- lis r5,TLB01@h
- ori r5,r5,TLB01@l
- tlbwe r5,r4,0x0001 /* Save it out */
- lis r5,TLB02@h
- ori r5,r5,TLB02@l
- tlbwe r5,r4,0x0002 /* Save it out */
- sync
- isync
- blr
-#endif
/* BOOT_CS (FLASH) must be forth. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
-#ifndef CONFIG_NAND_SPL
tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
-#else
- tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_RWX | SA_G )
-#endif
#ifdef CONFIG_SYS_INIT_RAM_DCACHE
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG)
tlbtab_end
-
-#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
- /*
- * For NAND booting the first TLB has to be reconfigured to full size
- * and with caching disabled after running from RAM!
- */
-#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
-#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
-#define TLB02 TLB2(AC_RWX | SA_IG)
-
- .globl reconfig_tlb0
-reconfig_tlb0:
- sync
- isync
- addi r4,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* TLB entry # */
- lis r5,TLB00@h
- ori r5,r5,TLB00@l
- tlbwe r5,r4,0x0000 /* Save it out */
- lis r5,TLB01@h
- ori r5,r5,TLB01@l
- tlbwe r5,r4,0x0001 /* Save it out */
- lis r5,TLB02@h
- ori r5,r5,TLB02@l
- tlbwe r5,r4,0x0002 /* Save it out */
- sync
- isync
- blr
-#endif
extern int denali_wait_for_dlllock(void);
extern void denali_core_search_data_eye(void);
-#if defined(CONFIG_NAND_SPL)
-/* Using arch/powerpc/cpu/ppc4xx/speed.c to calculate the bus frequency is too big
- * for the 4k NAND boot image so define bus_frequency to 133MHz here
- * which is save for the refresh counter setup.
- */
-#define get_bus_freq(val) 133333333
-#endif
-
/*************************************************************************
*
* initdram -- 440EPx's DDR controller is a DENALI Core
************************************************************************/
phys_size_t initdram (int board_type)
{
-#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)) || \
- defined(CONFIG_NAND_SPL)
+#if !defined(CONFIG_SYS_RAMBOOT)
ulong speed = get_bus_freq(0);
mtsdram(DDR0_02, 0x00000000);
mtsdram(DDR0_02, 0x00000001);
denali_wait_for_dlllock();
-#endif /* #ifndef CONFIG_NAND_U_BOOT */
+#endif /* #ifndef CONFIG_SYS_RAMBOOT */
#ifdef CONFIG_DDR_DATA_EYE
/* -----------------------------------------------------------+
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
- defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT)
mtdcr(EBC0_CFGADDR, PB3CR);
#else
mtdcr(EBC0_CFGADDR, PB0CR);
pbcr = mfdcr(EBC0_CFGDATA);
size_val = ffs(gd->bd->bi_flashsize) - 21;
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
- defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT)
mtdcr(EBC0_CFGADDR, PB3CR);
#else
mtdcr(EBC0_CFGADDR, PB0CR);
}
#endif
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT)
/*
* On NAND-booting sequoia, we need to patch the chips select numbers
* in the dtb (CS0 - NAND, CS3 - NOR)
return;
}
}
-#endif /* CONFIG_NAND_U_BOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
*/
#include <common.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#include <asm/arch/at91sam9263.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <net.h>
#endif
#include <netdev.h>
+#include <atmel_mci.h>
DECLARE_GLOBAL_DATA_PTR;
#endif /* CONFIG_LCD_INFO */
#endif
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int board_mmc_init(bd_t *bd)
+{
+ at91_mci_hw_init();
+
+ return atmel_mci_init((void *)ATMEL_BASE_MCI1);
+}
+#endif
+
int board_early_init_f(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
--- /dev/null
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# (C) Copyright 2014
+# Bo Shen <voice.shen@atmel.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += sama5d3_xplained.o
--- /dev/null
+/*
+ * Copyright (C) 2014 Atmel Corporation
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mmc.h>
+#include <asm/io.h>
+#include <asm/arch/sama5d3_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clk.h>
+#include <atmel_mci.h>
+#include <net.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_NAND_ATMEL
+void sama5d3_xplained_nand_hw_init(void)
+{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+
+ at91_periph_clk_enable(ATMEL_ID_SMC);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
+ AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
+ AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) |
+ AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3)|
+ AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+ AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+ AT91_SMC_MODE_DBW_8 |
+#endif
+ AT91_SMC_MODE_TDF_CYCLE(3),
+ &smc->cs[3].mode);
+}
+#endif
+
+#ifdef CONFIG_CMD_USB
+static void sama5d3_xplained_usb_hw_init(void)
+{
+ at91_set_pio_output(AT91_PIO_PORTE, 3, 0);
+ at91_set_pio_output(AT91_PIO_PORTE, 4, 0);
+}
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+static void sama5d3_xplained_mci0_hw_init(void)
+{
+ at91_mci_hw_init();
+
+ at91_set_pio_output(AT91_PIO_PORTE, 2, 0); /* MCI0 Power */
+}
+#endif
+
+int board_early_init_f(void)
+{
+ at91_periph_clk_enable(ATMEL_ID_PIOA);
+ at91_periph_clk_enable(ATMEL_ID_PIOB);
+ at91_periph_clk_enable(ATMEL_ID_PIOC);
+ at91_periph_clk_enable(ATMEL_ID_PIOD);
+ at91_periph_clk_enable(ATMEL_ID_PIOE);
+
+ at91_seriald_hw_init();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_NAND_ATMEL
+ sama5d3_xplained_nand_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+ sama5d3_xplained_usb_hw_init();
+#endif
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+ sama5d3_xplained_mci0_hw_init();
+#endif
+#ifdef CONFIG_MACB
+ at91_gmac_hw_init();
+ at91_macb_hw_init();
+#endif
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_MACB
+ macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
+ macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int board_mmc_init(bd_t *bis)
+{
+ atmel_mci_init((void *)ATMEL_BASE_MCI0);
+
+ return 0;
+}
+#endif
{
#ifdef CONFIG_SYS_USE_MMC
sama5d3xek_mci_hw_init();
+#elif CONFIG_SYS_USE_NANDFLASH
+ sama5d3xek_nand_hw_init();
+#elif CONFIG_SYS_USE_SERIALFLASH
+ at91_spi0_hw_init(1 << 0);
#endif
}
+++ /dev/null
-config.tmp
obj-y += fx12mm.o
-include $(SRCTREE)/board/xilinx/ppc405-generic/Makefile
+include $(srctree)/board/xilinx/ppc405-generic/Makefile
+++ /dev/null
-/config.tmp
obj-y += v5fx30teval.o
-include $(SRCTREE)/board/xilinx/ppc440-generic/Makefile
+include $(srctree)/board/xilinx/ppc440-generic/Makefile
+++ /dev/null
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
+++ /dev/null
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
+++ /dev/null
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
+++ /dev/null
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
+++ /dev/null
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
# SPDX-License-Identifier: GPL-2.0+
#
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
-
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 6
# SPDX-License-Identifier: GPL-2.0+
#
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
-
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
# SPDX-License-Identifier: GPL-2.0+
#
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
-
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
# SPDX-License-Identifier: GPL-2.0+
#
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
-
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6
# SPDX-License-Identifier: GPL-2.0+
#
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
-
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
# SPDX-License-Identifier: GPL-2.0+
#
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
-
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --dma 6
LDR_FLAGS-BFIN_BOOT_FIFO := --dma 1
# SPDX-License-Identifier: GPL-2.0+
#
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
-
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
# SPDX-License-Identifier: GPL-2.0+
#
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
-
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
+++ /dev/null
-#
-# Copyright (c) Switchfin Org. <dpn@switchfin.org>
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
+++ /dev/null
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
# SPDX-License-Identifier: GPL-2.0+
#
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
-
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
# SPDX-License-Identifier: GPL-2.0+
#
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
-
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
# SPDX-License-Identifier: GPL-2.0+
#
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
-
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
# SPDX-License-Identifier: GPL-2.0+
#
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
-
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --dma 6
LDR_FLAGS-BFIN_BOOT_FIFO := --dma 1
# SPDX-License-Identifier: GPL-2.0+
#
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
-
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
/* ------------------------------------------------------------------------- */
-#if defined(CONFIG_8260)
+#if defined(CONFIG_MPC8260)
#include <ioports.h>
}
};
-#endif /* CONFIG_8260 */
+#endif /* CONFIG_MPC8260 */
/* ------------------------------------------------------------------------- */
#if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR)
#if (defined(CONFIG_8xx) && defined(CONFIG_8xx_CONS_NONE)) || \
- (defined(CONFIG_8260) && defined(CONFIG_CONS_NONE))
+ (defined(CONFIG_MPC8260) && defined(CONFIG_CONS_NONE))
#if CONFIG_CONS_INDEX == 1
#define CMA_MB_SERIAL_BASE CMA_MB_SERIALA_BASE
#include <asm/arch/clocks_am33xx.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware_am33xx.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
const struct ctrl_ioregs ioregs = {
.cm0ioctl = MT41J128MJT125_IOCTRL_VALUE,
--- /dev/null
+bootscript.c
+bootscript.image
obj-y += init.o
obj-y += bootscript.o
-$(obj)/bootscript.c: $(obj)/bootscript.image
- od -t x1 -v -A x $^ | awk -f $(srctree)/$(src)/x2c.awk > $@
+quiet_cmd_awk = AWK $@
+ cmd_awk = od -t x1 -v -A x $< | $(AWK) -f $(filter-out $<,$^) > $@
+$(obj)/bootscript.c: $(obj)/bootscript.image $(src)/x2c.awk
+ $(call cmd,awk)
+
+quiet_cmd_mkimage = UIMAGE $@
+cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
+ $(if $(KBUILD_VERBOSE:1=), >/dev/null)
+
+MKIMAGEFLAGS_bootscript.image := -A ppc -O linux -T script -C none \
+ -a 0 -e 0 -n bootscript
$(obj)/bootscript.image: $(src)/bootscript.hush
- -$(OBJTREE)/tools/mkimage -A ppc -O linux -T script -C none -a 0 -e 0 -n bootscript -d $< $@
+ $(call cmd,mkimage)
clean-files := bootscript.c bootscript.image
\ No newline at end of file
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
-#ifndef CONFIG_NAND_SPL
tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
-#else
- tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_RWX | SA_G )
-#endif
/* TLB entries for DDR2 SDRAM are generated dynamically */
/* TODO: what about high IO space */
tlbtab_end
-
-#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
- /*
- * For NAND booting the first TLB has to be reconfigured to full size
- * and with caching disabled after running from RAM!
- */
-#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
-#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
-#define TLB02 TLB2(AC_RWX | SA_IG)
-
- .globl reconfig_tlb0
-reconfig_tlb0:
- sync
- isync
- addi r4,r0,0x0000 /* TLB entry #0 */
- lis r5,TLB00@h
- ori r5,r5,TLB00@l
- tlbwe r5,r4,0x0000 /* Save it out */
- lis r5,TLB01@h
- ori r5,r5,TLB01@l
- tlbwe r5,r4,0x0001 /* Save it out */
- lis r5,TLB02@h
- ori r5,r5,TLB02@l
- tlbwe r5,r4,0x0002 /* Save it out */
- sync
- isync
- blr
-#endif
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
- mtdcr(EBC0_CFGADDR, PB2CR);
-#else
mtdcr(EBC0_CFGADDR, PB0CR);
-#endif
pbcr = mfdcr(EBC0_CFGDATA);
size_val = ffs(gd->bd->bi_flashsize) - 21;
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
- mtdcr(EBC0_CFGADDR, PB2CR);
-#else
mtdcr(EBC0_CFGADDR, PB0CR);
-#endif
mtdcr(EBC0_CFGDATA, pbcr);
/*
#include <linux/compiler.h>
#include <asm/mmu.h>
#include <asm/processor.h>
+#include <asm/errno.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#define CLK_MUX_SEL_MASK 0x4
#define ETH_PHY_CLK_OUT 0x4
-#define PLL_NUM 2
DECLARE_GLOBAL_DATA_PTR;
debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
switch (serdes1_prtcl) {
+ case 0x29:
case 0x2a:
case 0x2C:
case 0x2D:
}
break;
+ case 0x02:
+ case 0x04:
+ case 0x05:
+ case 0x06:
+ case 0x08:
+ case 0x09:
+ case 0x0A:
+ case 0x0B:
+ case 0x0C:
+ case 0x30:
+ case 0x32:
+ case 0x33:
+ case 0x34:
+ case 0x39:
+ case 0x3A:
+ case 0x3C:
+ case 0x3D:
+ case 0x5C:
+ case 0x5D:
+ /*
+ * Configuration:
+ * SERDES: 1
+ * Lanes: A,B: AURORA
+ * Lanes: C,d: SGMII
+ * Lanes: E,F,G,H: CPRI
+ */
+ debug("Configuring crossbar for Aurora, SGMII 3 and 4,"
+ " and CPRI. srds_prctl:%x\n", serdes1_prtcl);
+ num_vsc16_con = NUM_CON_VSC3316;
+ /* Configure VSC3316 crossbar switch */
+ ret = select_i2c_ch_pca(I2C_CH_VSC3316);
+ if (!ret) {
+ ret = vsc3316_config(VSC3316_TX_ADDRESS,
+ vsc16_tx_sfp_sgmii_aurora,
+ num_vsc16_con);
+ if (ret)
+ return ret;
+ ret = vsc3316_config(VSC3316_RX_ADDRESS,
+ vsc16_rx_sfp_sgmii_aurora,
+ num_vsc16_con);
+ if (ret)
+ return ret;
+ } else {
+ return ret;
+ }
+ break;
+
#ifdef CONFIG_PPC_B4420
+ case 0x17:
case 0x18:
/*
* Configuration:
return 0;
}
+static int calibrate_pll(serdes_corenet_t *srds_regs, int pll_num)
+{
+ u32 rst_err;
+
+ /* Steps For SerDes PLLs reset and reconfiguration
+ * or PLL power-up procedure
+ */
+ debug("CALIBRATE PLL:%d\n", pll_num);
+ clrbits_be32(&srds_regs->bank[pll_num].rstctl,
+ SRDS_RSTCTL_SDRST_B);
+ udelay(10);
+ clrbits_be32(&srds_regs->bank[pll_num].rstctl,
+ (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
+ udelay(10);
+ setbits_be32(&srds_regs->bank[pll_num].rstctl,
+ SRDS_RSTCTL_RST);
+ setbits_be32(&srds_regs->bank[pll_num].rstctl,
+ (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
+ | SRDS_RSTCTL_SDRST_B));
+
+ udelay(20);
+
+ /* Check whether PLL has been locked or not */
+ rst_err = in_be32(&srds_regs->bank[pll_num].rstctl) &
+ SRDS_RSTCTL_RSTERR;
+ rst_err >>= SRDS_RSTCTL_RSTERR_SHIFT;
+ debug("RST_ERR value for PLL %d is: 0x%x:\n", pll_num, rst_err);
+ if (rst_err)
+ return rst_err;
+
+ return rst_err;
+}
+
+static int check_pll_locks(serdes_corenet_t *srds_regs, int pll_num)
+{
+ int ret = 0;
+ u32 fcap, dcbias, bcap, pllcr1, pllcr0;
+
+ if (calibrate_pll(srds_regs, pll_num)) {
+ /* STEP 1 */
+ /* Read fcap, dcbias and bcap value */
+ clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
+ SRDS_PLLCR0_DCBIAS_OUT_EN);
+ fcap = in_be32(&srds_regs->bank[pll_num].pllsr2) &
+ SRDS_PLLSR2_FCAP;
+ fcap >>= SRDS_PLLSR2_FCAP_SHIFT;
+ bcap = in_be32(&srds_regs->bank[pll_num].pllsr2) &
+ SRDS_PLLSR2_BCAP_EN;
+ bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT;
+ setbits_be32(&srds_regs->bank[pll_num].pllcr0,
+ SRDS_PLLCR0_DCBIAS_OUT_EN);
+ dcbias = in_be32(&srds_regs->bank[pll_num].pllsr2) &
+ SRDS_PLLSR2_DCBIAS;
+ dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT;
+ debug("values of bcap:%x, fcap:%x and dcbias:%x\n",
+ bcap, fcap, dcbias);
+ if (fcap == 0 && bcap == 1) {
+ /* Step 3 */
+ clrbits_be32(&srds_regs->bank[pll_num].rstctl,
+ (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
+ | SRDS_RSTCTL_SDRST_B));
+ clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
+ SRDS_PLLCR1_BCAP_EN);
+ setbits_be32(&srds_regs->bank[pll_num].pllcr1,
+ SRDS_PLLCR1_BCAP_OVD);
+ if (calibrate_pll(srds_regs, pll_num)) {
+ /*save the fcap, dcbias and bcap values*/
+ clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
+ SRDS_PLLCR0_DCBIAS_OUT_EN);
+ fcap = in_be32(&srds_regs->bank[pll_num].pllsr2)
+ & SRDS_PLLSR2_FCAP;
+ fcap >>= SRDS_PLLSR2_FCAP_SHIFT;
+ bcap = in_be32(&srds_regs->bank[pll_num].pllsr2)
+ & SRDS_PLLSR2_BCAP_EN;
+ bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT;
+ setbits_be32(&srds_regs->bank[pll_num].pllcr0,
+ SRDS_PLLCR0_DCBIAS_OUT_EN);
+ dcbias = in_be32
+ (&srds_regs->bank[pll_num].pllsr2) &
+ SRDS_PLLSR2_DCBIAS;
+ dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT;
+
+ /* Step 4*/
+ clrbits_be32(&srds_regs->bank[pll_num].rstctl,
+ (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
+ | SRDS_RSTCTL_SDRST_B));
+ setbits_be32(&srds_regs->bank[pll_num].pllcr1,
+ SRDS_PLLCR1_BYP_CAL);
+ clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
+ SRDS_PLLCR1_BCAP_EN);
+ setbits_be32(&srds_regs->bank[pll_num].pllcr1,
+ SRDS_PLLCR1_BCAP_OVD);
+ /* change the fcap and dcbias to the saved
+ * values from Step 3 */
+ clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
+ SRDS_PLLCR1_PLL_FCAP);
+ pllcr1 = (in_be32
+ (&srds_regs->bank[pll_num].pllcr1)|
+ (fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT));
+ out_be32(&srds_regs->bank[pll_num].pllcr1,
+ pllcr1);
+ clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
+ SRDS_PLLCR0_DCBIAS_OVRD);
+ pllcr0 = (in_be32
+ (&srds_regs->bank[pll_num].pllcr0)|
+ (dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT));
+ out_be32(&srds_regs->bank[pll_num].pllcr0,
+ pllcr0);
+ ret = calibrate_pll(srds_regs, pll_num);
+ if (ret)
+ return ret;
+ } else {
+ goto out;
+ }
+ } else { /* Step 5 */
+ clrbits_be32(&srds_regs->bank[pll_num].rstctl,
+ (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
+ | SRDS_RSTCTL_SDRST_B));
+ udelay(10);
+ /* Change the fcap, dcbias, and bcap to the
+ * values from Step 1 */
+ setbits_be32(&srds_regs->bank[pll_num].pllcr1,
+ SRDS_PLLCR1_BYP_CAL);
+ clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
+ SRDS_PLLCR1_PLL_FCAP);
+ pllcr1 = (in_be32(&srds_regs->bank[pll_num].pllcr1)|
+ (fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT));
+ out_be32(&srds_regs->bank[pll_num].pllcr1,
+ pllcr1);
+ clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
+ SRDS_PLLCR0_DCBIAS_OVRD);
+ pllcr0 = (in_be32(&srds_regs->bank[pll_num].pllcr0)|
+ (dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT));
+ out_be32(&srds_regs->bank[pll_num].pllcr0,
+ pllcr0);
+ clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
+ SRDS_PLLCR1_BCAP_EN);
+ setbits_be32(&srds_regs->bank[pll_num].pllcr1,
+ SRDS_PLLCR1_BCAP_OVD);
+ ret = calibrate_pll(srds_regs, pll_num);
+ if (ret)
+ return ret;
+ }
+ }
+out:
+ return 0;
+}
+
+static int check_serdes_pll_locks(void)
+{
+ serdes_corenet_t *srds1_regs =
+ (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ serdes_corenet_t *srds2_regs =
+ (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
+ int i, ret1, ret2;
+
+ debug("\nSerDes1 Lock check\n");
+ for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
+ ret1 = check_pll_locks(srds1_regs, i);
+ if (ret1) {
+ printf("SerDes1, PLL:%d didnt lock\n", i);
+ return ret1;
+ }
+ }
+ debug("\nSerDes2 Lock check\n");
+ for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
+ ret2 = check_pll_locks(srds2_regs, i);
+ if (ret2) {
+ printf("SerDes2, PLL:%d didnt lock\n", i);
+ return ret2;
+ }
+ }
+
+ return 0;
+}
+
int config_serdes1_refclks(void)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
serdes_corenet_t *srds_regs =
(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
u32 serdes1_prtcl, lane;
- unsigned int flag_sgmii_prtcl = 0;
- int ret, i;
+ unsigned int flag_sgmii_aurora_prtcl = 0;
+ int i;
+ int ret = 0;
serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
- /* Clear SRDS_RSTCTL_RST bit for both PLLs before changing refclks
+ /* To prevent generation of reset request from SerDes
+ * while changing the refclks, By setting SRDS_RST_MSK bit,
+ * SerDes reset event cannot cause a reset request
*/
- for (i = 0; i < PLL_NUM; i++)
- clrbits_be32(&srds_regs->bank[i].rstctl, SRDS_RSTCTL_RST);
+ setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
+
/* Reconfigure IDT idt8t49n222a device for CPRI to work
* For this SerDes1's Refclk1 and refclk2 need to be set
* to 122.88MHz
case 0x2C:
case 0x2D:
case 0x2E:
+ case 0x02:
+ case 0x04:
+ case 0x05:
+ case 0x06:
+ case 0x08:
+ case 0x09:
+ case 0x0A:
+ case 0x0B:
+ case 0x0C:
+ case 0x30:
+ case 0x32:
+ case 0x33:
+ case 0x34:
+ case 0x39:
+ case 0x3A:
+ case 0x3C:
+ case 0x3D:
+ case 0x5C:
+ case 0x5D:
debug("Configuring idt8t49n222a for CPRI SerDes clks:"
" for srds_prctl:%x\n", serdes1_prtcl);
ret = select_i2c_ch_pca(I2C_CH_IDT);
SERDES_REFCLK_122_88, 0);
if (ret) {
printf("IDT8T49N222A configuration failed.\n");
- return ret;
+ goto out;
} else
- printf("IDT8T49N222A configured.\n");
+ debug("IDT8T49N222A configured.\n");
} else {
- return ret;
+ goto out;
}
select_i2c_ch_pca(I2C_CH_DEFAULT);
/* Change SerDes1's Refclk1 to 125MHz for on board
- * SGMIIs to work
+ * SGMIIs or Aurora to work
*/
for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
enum srds_prtcl lane_prtcl = serdes_get_prtcl
case SGMII_FM1_DTSEC4:
case SGMII_FM1_DTSEC5:
case SGMII_FM1_DTSEC6:
- flag_sgmii_prtcl++;
+ case AURORA:
+ flag_sgmii_aurora_prtcl++;
break;
default:
break;
}
}
- if (flag_sgmii_prtcl)
+ if (flag_sgmii_aurora_prtcl)
QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
/* Steps For SerDes PLLs reset and reconfiguration after
* changing SerDes's refclks
*/
- for (i = 0; i < PLL_NUM; i++) {
+ for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
debug("For PLL%d reset and reconfiguration after"
" changing refclks\n", i+1);
clrbits_be32(&srds_regs->bank[i].rstctl,
printf("WARNING:IDT8T49N222A configuration not"
" supported for:%x SerDes1 Protocol.\n",
serdes1_prtcl);
- return -1;
}
- return 0;
+out:
+ /* Clearing SRDS_RST_MSK bit as now
+ * SerDes reset event can cause a reset request
+ */
+ clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
+ return ret;
+}
+
+int config_serdes2_refclks(void)
+{
+ ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ serdes_corenet_t *srds2_regs =
+ (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
+ u32 serdes2_prtcl;
+ int ret = 0;
+ int i;
+
+ serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+ if (!serdes2_prtcl) {
+ debug("SERDES2 is not enabled\n");
+ return -ENODEV;
+ }
+ serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+ debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
+
+ /* To prevent generation of reset request from SerDes
+ * while changing the refclks, By setting SRDS_RST_MSK bit,
+ * SerDes reset event cannot cause a reset request
+ */
+ setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
+
+ /* Reconfigure IDT idt8t49n222a device for PCIe SATA to work
+ * For this SerDes2's Refclk1 need to be set to 100MHz
+ */
+ switch (serdes2_prtcl) {
+ case 0x9E:
+ case 0x9A:
+ case 0xb2:
+ debug("Configuring IDT for PCIe SATA for srds_prctl:%x\n",
+ serdes2_prtcl);
+ ret = select_i2c_ch_pca(I2C_CH_IDT);
+ if (!ret) {
+ ret = set_serdes_refclk(IDT_SERDES2_ADDRESS, 2,
+ SERDES_REFCLK_100,
+ SERDES_REFCLK_156_25, 0);
+ if (ret) {
+ printf("IDT8T49N222A configuration failed.\n");
+ goto out;
+ } else
+ debug("IDT8T49N222A configured.\n");
+ } else {
+ goto out;
+ }
+ select_i2c_ch_pca(I2C_CH_DEFAULT);
+
+ /* Steps For SerDes PLLs reset and reconfiguration after
+ * changing SerDes's refclks
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
+ clrbits_be32(&srds2_regs->bank[i].rstctl,
+ SRDS_RSTCTL_SDRST_B);
+ udelay(10);
+ clrbits_be32(&srds2_regs->bank[i].rstctl,
+ (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
+ udelay(10);
+ setbits_be32(&srds2_regs->bank[i].rstctl,
+ SRDS_RSTCTL_RST);
+ setbits_be32(&srds2_regs->bank[i].rstctl,
+ (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
+ | SRDS_RSTCTL_SDRST_B));
+
+ udelay(10);
+ }
+ break;
+ default:
+ printf("IDT configuration not supported for:%x S2 Protocol.\n",
+ serdes2_prtcl);
+ }
+
+out:
+ /* Clearing SRDS_RST_MSK bit as now
+ * SerDes reset event can cause a reset request
+ */
+ clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
+ return ret;
}
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+ int ret;
/*
* Remap Boot flash + PROMJET region to caching-inhibited
else
printf("SerDes1 Refclks have been set.\n");
+ /* SerDes2 refclks need to be set again, as default clks
+ * are not suitable for PCIe SATA to work
+ * This function will set SerDes2's Refclk1 and refclk2
+ * for SerDes2 protocols having PCIe in them
+ * for PCIe SATA to work
+ */
+ ret = config_serdes2_refclks();
+ if (!ret)
+ printf("SerDes2 Refclks have been set.\n");
+ else if (ret == -ENODEV)
+ printf("SerDes disable, Refclks couldn't change.\n");
+ else
+ printf("SerDes2 Refclk reconfiguring failed.\n");
+
+#if defined(CONFIG_SYS_FSL_ERRATUM_A006384) || \
+ defined(CONFIG_SYS_FSL_ERRATUM_A006475)
+ /* Rechecking the SerDes locks after all SerDes configurations
+ * are done, As SerDes PLLs may not lock reliably at 5 G VCO
+ * and at cold temperatures.
+ * Following sequence ensure the proper locking of SerDes PLLs.
+ */
+ if (SVR_MAJ(get_svr()) == 1) {
+ if (check_serdes_pll_locks())
+ printf("SerDes plls still not locked properly.\n");
+ else
+ printf("SerDes plls have been locked well.\n");
+ }
+#endif
+
/* Configure VSC3316 and VSC3308 crossbar switches */
if (configure_vsc3316_3308())
printf("VSC:failed to configure VSC3316/3308.\n");
{7, 8}, {9, 0}, {5, 14}, {4, 15},
{-1, -1}, {-1, -1} };
+static int8_t vsc16_tx_sfp_sgmii_aurora[8][2] = { {15, 7}, {0, 1},
+ {7, 8}, {9, 0}, {5, 14},
+ {4, 15}, {2, 12}, {12, 13} };
+
#ifdef CONFIG_PPC_B4420
static int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
{7, 8}, {1, 9}, {14, 11}, {15, 10},
{-1, -1}, {-1, -1} };
+static int8_t vsc16_rx_sfp_sgmii_aurora[8][2] = { {8, 15}, {0, 1},
+ {7, 8}, {1, 9}, {14, 11},
+ {15, 10}, {13, 3}, {12, 12} };
+
#ifdef CONFIG_PPC_B4420
static int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
serdes2_prtcl);
switch (serdes2_prtcl) {
+ case 0x17:
case 0x18:
/*
* Configuration:
fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
switch (serdes1_prtcl) {
+ case 0x29:
case 0x2a:
/* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */
debug("Setting phy addresses for FM1_DTSEC5: %x and"
CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
break;
#ifdef CONFIG_PPC_B4420
+ case 0x17:
case 0x18:
/* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */
debug("Setting phy addresses for FM1_DTSEC3: %x and"
break;
}
switch (serdes2_prtcl) {
+ case 0x17:
case 0x18:
debug("Setting phy addresses on SGMII Riser card for"
"FM1_DTSEC ports: \n");
fm_info_set_phy_address(FM1_DTSEC4,
CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR);
break;
+ case 0x48:
case 0x49:
debug("Setting phy addresses on SGMII Riser card for"
"FM1_DTSEC ports: \n");
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = m5271evb.o
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-CONFIG_SYS_TEXT_BASE = 0xffe00000
+++ /dev/null
-/*
- * (C) Copyright 2000-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/immap.h>
-
-int checkboard (void) {
- puts ("Board: Freescale M5271EVB\n");
- return 0;
-};
-
-phys_size_t initdram (int board_type) {
-
- int i;
-
- /* Enable Address lines 23-21 and lower 16bits of data path */
- mbar_writeByte(MCF_GPIO_PAR_AD, MCF_GPIO_AD_ADDR23 |
- MCF_GPIO_AD_ADDR22 | MCF_GPIO_AD_ADDR21 |
- MCF_GPIO_AD_DATAL);
-
- /* Set CS2 pin to be SD_CS0 */
- mbar_writeByte(MCF_GPIO_PAR_CS, mbar_readByte(MCF_GPIO_PAR_CS)
- | MCF_GPIO_PAR_CS_PAR_CS2);
-
- /* Configure SDRAM Control Pin Assignemnt Register */
- mbar_writeByte(MCF_GPIO_PAR_SDRAM, MCF_GPIO_SDRAM_CSSDCS_00 |
- MCF_GPIO_SDRAM_SDWE | MCF_GPIO_SDRAM_SCAS |
- MCF_GPIO_SDRAM_SRAS | MCF_GPIO_SDRAM_SCKE |
- MCF_GPIO_SDRAM_SDCS_11);
- asm(" nop");
-
- /*
- * Check to see if the SDRAM has already been initialized
- * by a run control tool
- */
- if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE)) {
- /* Initialize DRAM Control Register: DCR */
- mbar_writeShort(MCF_SDRAMC_DCR,
- MCF_SDRAMC_DCR_RTIM(2)
- | MCF_SDRAMC_DCR_RC(0x2E));
- asm(" nop");
-
- /*
- * Initialize DACR0
- *
- * CASL: 01
- * CBM: cmd at A20, bank select bits 21 and up
- * PS: 32bit port size
- */
- mbar_writeLong(MCF_SDRAMC_DACR0,
- MCF_SDRAMC_DACRn_BA(CONFIG_SYS_SDRAM_BASE>>18)
- | MCF_SDRAMC_DACRn_CASL(1)
- | MCF_SDRAMC_DACRn_CBM(3)
- | MCF_SDRAMC_DACRn_PS(0));
- asm(" nop");
-
- /* Initialize DMR0 */
- mbar_writeLong(MCF_SDRAMC_DMR0,
- MCF_SDRAMC_DMRn_BAM_16M
- | MCF_SDRAMC_DMRn_V);
- asm(" nop");
-
- /* Set IP bit in DACR */
- mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
- | MCF_SDRAMC_DACRn_IP);
- asm(" nop");
-
- /* Wait at least 20ns to allow banks to precharge */
- for (i = 0; i < 5; i++)
- asm(" nop");
-
- /* Write to this block to initiate precharge */
- *(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
- asm(" nop");
-
- /* Set RE bit in DACR */
- mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
- | MCF_SDRAMC_DACRn_RE);
-
- /* Wait for at least 8 auto refresh cycles to occur */
- for (i = 0; i < 2000; i++)
- asm(" nop");
-
- /* Finish the configuration by issuing the MRS */
- mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
- | MCF_SDRAMC_DACRn_MRS);
- asm(" nop");
-
- /*
- * Write to the SDRAM Mode Register A0-A11 = 0x400
- *
- * Write Burst Mode = Programmed Burst Length
- * Op Mode = Standard Op
- * CAS Latency = 2
- * Burst Type = Sequential
- * Burst Length = 1
- */
- *(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xa5a5a5a5;
- asm(" nop");
- }
-
- return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-};
-
-int testdram (void) {
-
- /* TODO: XXX XXX XXX */
- printf ("DRAM test not implemented!\n");
-
- return (0);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(m68k)
-
-SECTIONS
-{
- .text :
- {
- arch/m68k/cpu/mcf52x2/start.o (.text*)
-
- . = DEFINED(env_offset) ? env_offset : .;
- common/env_embedded.o (.ppcenv)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
-
- .reloc :
- {
- __got_start = .;
- KEEP(*(.got))
- __got_end = .;
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- _sbss = .;
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- _ebss = .;
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
# SPDX-License-Identifier: GPL-2.0+
#
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/io.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#include <common.h>
#include <fsl_esdhc.h>
#include <mmc.h>
obj-y += law.o
obj-y += tlb.o
obj-y += eth.o
+obj-y += diu.o
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Author: Priyanka Jain <Priyanka.Jain@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <linux/ctype.h>
+#include <asm/io.h>
+#include <stdio_dev.h>
+#include <video_fb.h>
+#include <fsl_diu_fb.h>
+#include "../common/qixis.h"
+#include "t1040qds.h"
+#include "t1040qds_qixis.h"
+#include <i2c.h>
+
+
+#define I2C_DVI_INPUT_DATA_FORMAT_REG 0x1F
+#define I2C_DVI_PLL_CHARGE_CNTL_REG 0x33
+#define I2C_DVI_PLL_DIVIDER_REG 0x34
+#define I2C_DVI_PLL_SUPPLY_CNTL_REG 0x35
+#define I2C_DVI_PLL_FILTER_REG 0x36
+#define I2C_DVI_TEST_PATTERN_REG 0x48
+#define I2C_DVI_POWER_MGMT_REG 0x49
+#define I2C_DVI_LOCK_STATE_REG 0x4D
+#define I2C_DVI_SYNC_POLARITY_REG 0x56
+
+/*
+ * Set VSYNC/HSYNC to active high. This is polarity of sync signals
+ * from DIU->DVI. The DIU default is active igh, so DVI is set to
+ * active high.
+ */
+#define I2C_DVI_INPUT_DATA_FORMAT_VAL 0x98
+
+#define I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL 0x06
+#define I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL 0x26
+#define I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL 0xA0
+#define I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL 0x08
+#define I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL 0x16
+#define I2C_DVI_PLL_FILTER_LOW_SPEED_VAL 0x60
+
+/* Clear test pattern */
+#define I2C_DVI_TEST_PATTERN_VAL 0x18
+/* Exit Power-down mode */
+#define I2C_DVI_POWER_MGMT_VAL 0xC0
+
+/* Monitor polarity is handled via DVI Sync Polarity Register */
+#define I2C_DVI_SYNC_POLARITY_VAL 0x00
+
+/*
+ * DIU Area Descriptor
+ *
+ * Note that we need to byte-swap the value before it's written to the AD
+ * register. So even though the registers don't look like they're in the same
+ * bit positions as they are on the MPC8610, the same value is written to the
+ * AD register on the MPC8610 and on the P1022.
+ */
+#define AD_BYTE_F 0x10000000
+#define AD_ALPHA_C_SHIFT 25
+#define AD_BLUE_C_SHIFT 23
+#define AD_GREEN_C_SHIFT 21
+#define AD_RED_C_SHIFT 19
+#define AD_PIXEL_S_SHIFT 16
+#define AD_COMP_3_SHIFT 12
+#define AD_COMP_2_SHIFT 8
+#define AD_COMP_1_SHIFT 4
+#define AD_COMP_0_SHIFT 0
+
+/* Programming of HDMI Chrontel CH7301 connector */
+int diu_set_dvi_encoder(unsigned int pixclock)
+{
+ int ret;
+ u8 temp;
+ select_i2c_ch_pca9547(I2C_MUX_CH_DIU);
+
+ temp = I2C_DVI_TEST_PATTERN_VAL;
+ ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1,
+ &temp, 1);
+ if (ret) {
+ puts("I2C: failed to select proper dvi test pattern\n");
+ return ret;
+ }
+ temp = I2C_DVI_INPUT_DATA_FORMAT_VAL;
+ ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_INPUT_DATA_FORMAT_REG,
+ 1, &temp, 1);
+ if (ret) {
+ puts("I2C: failed to select dvi input data format\n");
+ return ret;
+ }
+
+ /* Set Sync polarity register */
+ temp = I2C_DVI_SYNC_POLARITY_VAL;
+ ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_SYNC_POLARITY_REG, 1,
+ &temp, 1);
+ if (ret) {
+ puts("I2C: failed to select dvi syc polarity\n");
+ return ret;
+ }
+
+ /* Set PLL registers based on pixel clock rate*/
+ if (pixclock > 65000000) {
+ temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL;
+ ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+ I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1);
+ if (ret) {
+ puts("I2C: failed to select dvi pll charge_cntl\n");
+ return ret;
+ }
+ temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL;
+ ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+ I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
+ if (ret) {
+ puts("I2C: failed to select dvi pll divider\n");
+ return ret;
+ }
+ temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL;
+ ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+ I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
+ if (ret) {
+ puts("I2C: failed to select dvi pll filter\n");
+ return ret;
+ }
+ } else {
+ temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL;
+ ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+ I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1);
+ if (ret) {
+ puts("I2C: failed to select dvi pll charge_cntl\n");
+ return ret;
+ }
+ temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL;
+ ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+ I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
+ if (ret) {
+ puts("I2C: failed to select dvi pll divider\n");
+ return ret;
+ }
+ temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL;
+ ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+ I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
+ if (ret) {
+ puts("I2C: failed to select dvi pll filter\n");
+ return ret;
+ }
+ }
+
+ temp = I2C_DVI_POWER_MGMT_VAL;
+ ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_POWER_MGMT_REG, 1,
+ &temp, 1);
+ if (ret) {
+ puts("I2C: failed to select dvi power mgmt\n");
+ return ret;
+ }
+
+ udelay(500);
+
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+ return 0;
+}
+
+void diu_set_pixel_clock(unsigned int pixclock)
+{
+ unsigned long speed_ccb, temp;
+ u32 pixval;
+ int ret = 0;
+ speed_ccb = get_bus_freq(0);
+ temp = 1000000000 / pixclock;
+ temp *= 1000;
+ pixval = speed_ccb / temp;
+
+ /* Program HDMI encoder */
+ ret = diu_set_dvi_encoder(temp);
+ if (ret) {
+ puts("Failed to set DVI encoder\n");
+ return;
+ }
+
+ /* Program pixel clock */
+ out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR,
+ ((pixval << PXCK_BITS_START) & PXCK_MASK));
+ /* enable clock*/
+ out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK |
+ ((pixval << PXCK_BITS_START) & PXCK_MASK));
+}
+
+int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
+{
+ u32 pixel_format;
+ u8 sw;
+
+ /*Route I2C4 to DIU system as HSYNC/VSYNC*/
+ sw = QIXIS_READ(brdcfg[5]);
+ QIXIS_WRITE(brdcfg[5],
+ ((sw & ~(BRDCFG5_IMX_MASK)) | (BRDCFG5_IMX_DIU)));
+
+ /*Configure Display ouput port as HDMI*/
+ sw = QIXIS_READ(brdcfg[15]);
+ QIXIS_WRITE(brdcfg[15],
+ ((sw & ~(BRDCFG15_LCDPD_MASK | BRDCFG15_DIUSEL_MASK))
+ | (BRDCFG15_LCDPD_ENABLED | BRDCFG15_DIUSEL_HDMI)));
+
+ pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
+ (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
+ (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
+ (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
+ (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
+
+ printf("DIU: Switching to monitor @ %ux%u\n", xres, yres);
+
+
+ return fsl_diu_init(xres, yres, pixel_format, 0);
+}
void fdt_fixup_board_enet(void *blob);
void pci_of_setup(void *blob, bd_t *bd);
+int select_i2c_ch_pca9547(u8 ch);
#endif
#define BRDCFG4_EMISEL_MASK 0xE0
#define BRDCFG4_EMISEL_SHIFT 5
+/* BRDCFG5[0:1] controls routing and use of I2C3 & I2C4 ports*/
+#define BRDCFG5_IMX_MASK 0xC0
+#define BRDCFG5_IMX_DIU 0x80
+
+/* BRDCFG15[3] controls LCD Panel Powerdown*/
+#define BRDCFG15_LCDPD_MASK 0x10
+#define BRDCFG15_LCDPD_ENABLED 0x00
+
+/* BRDCFG15[6:7] controls DIU MUX selction*/
+#define BRDCFG15_DIUSEL_MASK 0x03
+#define BRDCFG15_DIUSEL_HDMI 0x00
+
/* SYSCLK */
#define QIXIS_SYSCLK_66 0x0
#define QIXIS_SYSCLK_83 0x1
pbsp = udimms[0];
- /* Get clk_adjust, cpo, write_data_delay,2t, according to the board ddr
+ /* Get clk_adjust according to the board ddr
* freqency and n_banks specified in board_specific_parameters table.
*/
ddr_freq = get_ddr_freq(0) / 1000000;
if (pbsp->n_ranks == pdimm->n_ranks &&
(pdimm->rank_density >> 30) >= pbsp->rank_gb) {
if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->cpo_override = pbsp->cpo;
- popts->write_data_delay =
- pbsp->write_data_delay;
popts->clk_adjust = pbsp->clk_adjust;
popts->wrlvl_start = pbsp->wrlvl_start;
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- popts->twot_en = pbsp->force_2t;
goto found;
}
pbsp_highest = pbsp;
printf("for data rate %lu MT/s\n", ddr_freq);
printf("Trying to use the highest speed (%u) parameters\n",
pbsp_highest->datarate_mhz_high);
- popts->cpo_override = pbsp_highest->cpo;
- popts->write_data_delay = pbsp_highest->write_data_delay;
popts->clk_adjust = pbsp_highest->clk_adjust;
popts->wrlvl_start = pbsp_highest->wrlvl_start;
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- popts->twot_en = pbsp_highest->force_2t;
} else {
panic("DIMM is not supported by this board");
}
popts->zq_en = 1;
/* DHC_EN =1, ODT = 75 Ohm */
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_OFF);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_OFF);
}
phys_size_t initdram(int board_type)
#ifndef __DDR_H__
#define __DDR_H__
-
dimm_params_t ddr_raw_timing = {
.n_ranks = 2,
.rank_density = 2147483648u,
.primary_sdram_width = 64,
.ec_sdram_width = 8,
.registered_dimm = 0,
- .mirrored_dimm = 1,
+ .mirrored_dimm = 0,
.n_row_addr = 15,
.n_col_addr = 10,
.n_banks_per_sdram_device = 8,
.edc_config = 2, /* ECC */
.burst_lengths_bitmask = 0x0c,
-
.tckmin_x_ps = 1071,
- .caslat_x = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */
- .taa_ps = 13910,
+ .caslat_x = 0xfe << 4, /* 5,6,7,8,9,10,11 */
+ .taa_ps = 13125,
.twr_ps = 15000,
- .trcd_ps = 13910,
+ .trcd_ps = 13125,
.trrd_ps = 6000,
- .trp_ps = 13910,
+ .trp_ps = 13125,
.tras_ps = 34000,
- .trc_ps = 48910,
+ .trc_ps = 48125,
.trfc_ps = 260000,
.twtr_ps = 7500,
.trtp_ps = 7500,
u32 wrlvl_start;
u32 wrlvl_ctl_2;
u32 wrlvl_ctl_3;
- u32 cpo;
- u32 write_data_delay;
- u32 force_2t;
};
/*
static const struct board_specific_parameters udimm0[] = {
/*
* memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
+ * num| hi| rank| clk| wrlvl | wrlvl
+ * ranks| mhz| GB |adjst| start | ctl2
*/
- {2, 1066, 4, 8, 4, 0x05070609, 0x08090a08, 0xff, 2, 0},
- {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
- {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0},
- {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0},
- {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0},
+ {2, 833, 4, 4, 6, 0x06060607, 0x08080807},
+ {2, 833, 0, 4, 6, 0x06060607, 0x08080807},
+ {2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09},
+ {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09},
+ {2, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A},
+ {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A},
+ {1, 833, 4, 4, 6, 0x06060607, 0x08080807},
+ {1, 833, 0, 4, 6, 0x06060607, 0x08080807},
+ {1, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09},
+ {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09},
+ {1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A},
+ {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A},
{}
};
#define EMI1_SLOT3 3
#define EMI1_SLOT4 4
#define EMI1_SLOT5 5
+#define EMI2 7
#elif defined(CONFIG_T2081QDS)
#define EMI1_SLOT2 3
#define EMI1_SLOT3 4
#define EMI1_SLOT5 5
#define EMI1_SLOT6 6
#define EMI1_SLOT7 7
-#endif
#define EMI2 8
+#endif
static int mdio_mux[NUM_FM_PORTS];
--- /dev/null
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_T2080RDB) += t208xrdb.o
+obj-$(CONFIG_T2080RDB) += eth_t208xrdb.o
+obj-$(CONFIG_T2080RDB) += cpld.o
+obj-$(CONFIG_PCI) += pci.o
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
--- /dev/null
+T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC.
+It can work in two mode: standalone mode and PCIe endpoint mode.
+
+T2080 SoC Overview
+------------------
+The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
+Architecture processor cores with high-performance datapath acceleration
+logic and network and peripheral bus interfaces required for networking,
+telecom/datacom, wireless infrastructure, and mil/aerospace applications.
+
+T2080 includes the following functions and features:
+ - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
+ - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
+ - Hierarchical interconnect fabric
+ - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
+ - Data Path Acceleration Architecture (DPAA) incorporating acceleration
+ - 16 SerDes lanes up to 10.3125 GHz
+ - 8 Ethernet interfaces, supporting combinations of the following:
+ - Up to four 10 Gbps Ethernet MACs
+ - Up to eight 1 Gbps Ethernet MACs
+ - Up to four 2.5 Gbps Ethernet MACs
+ - High-speed peripheral interfaces
+ - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
+ - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
+ - Additional peripheral interfaces
+ - Two serial ATA (SATA 2.0) controllers
+ - Two high-speed USB 2.0 controllers with integrated PHY
+ - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
+ - Enhanced serial peripheral interface (eSPI)
+ - Four I2C controllers
+ - Four 2-pin UARTs or two 4-pin UARTs
+ - Integrated Flash Controller supporting NAND and NOR flash
+ - Three eight-channel DMA engines
+ - Support for hardware virtualization and partitioning enforcement
+ - QorIQ Platform's Trust Architecture 2.0
+
+Differences between T2080 and T2081
+-----------------------------------
+ Feature T2080 T2081
+ 1G Ethernet numbers: 8 6
+ 10G Ethernet numbers: 4 2
+ SerDes lanes: 16 8
+ Serial RapidIO,RMan: 2 no
+ SATA Controller: 2 no
+ Aurora: yes no
+ SoC Package: 896-pins 780-pins
+
+
+T2080PCIe-RDB board Overview
+----------------------------
+ - SERDES Configuration
+ - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10)
+ - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2)
+ - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3)
+ - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2)
+ - SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2)
+ - SerDes-2 Lane G-H: to SATA1 & SATA2
+ - Ethernet
+ - Two on-board 10M/100M/1G RGMII ethernet ports
+ - Two on-board 10Gbps XFI fiber ports
+ - Two on-board 10Gbps Base-T copper ports
+ - DDR Memory
+ - Supports 72bit 4GB DDR3-LP SODIMM
+ - PCIe
+ - One PCIe x4 gold-finger
+ - One PCIe x4 connector
+ - One PCIe x2 end-point device (C293 Crypto co-processor)
+ - IFC/Local Bus
+ - NOR: 128MB 16-bit NOR Flash
+ - NAND: 512MB 8-bit NAND flash
+ - CPLD: for system controlling with programable header on-board
+ - SATA
+ - Two SATA 2.0 onnectors on-board
+ - USB
+ - Supports two USB 2.0 ports with integrated PHYs
+ - Two type A ports with 5V@1.5A per port.
+ - SDHC
+ - one TF-card connector on-board
+ - SPI
+ - On-board 64MB SPI flash
+ - Other
+ - Two Serial ports
+ - Four I2C ports
+
+
+System Memory map
+-----------------
+Start Address End Address Description Size
+0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
+0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
+0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
+0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB
+0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
+0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
+0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
+0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
+0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
+0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
+0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
+0xC_4000_0000 0xC_4FFF_FFFF PCI Express 4 Mem Space 256MB
+0xC_3000_0000 0xC_3FFF_FFFF PCI Express 3 Mem Space 256MB
+0xC_2000_0000 0xC_2FFF_FFFF PCI Express 2 Mem Space 256MB
+0xC_0000_0000 0xC_1FFF_FFFF PCI Express 1 Mem Space 512MB
+0x0_0000_0000 0x0_ffff_ffff DDR 4GB
+
+
+128M NOR Flash memory Map
+-------------------------
+Start Address End Address Definition Max size
+0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB
+0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB
+0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
+0xEFE00000 0xEFE3FFFF PHY CS4315 firmware 256KB
+0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
+0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
+0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
+0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
+0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB
+0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB
+0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
+0xEBE00000 0xEBE3FFFF PHY CS4315 firmware (alt bank) 256KB
+0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
+0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB
+0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
+0xE8000000 0xE801FFFF RCW (current bank) 128KB
+
+
+T2080PCIe-RDB Ethernet Port Map
+-------------------------------
+Label In Uboot In Linux FMan Address Comments PHY
+ETH0 FM1@GTEC1 fm1-mac9 0xfe4f0000 10G SFP+ (CS4315)
+ETH1 FM1@GTEC2 fm1-mac10 0xfe4f2000 10G SFP+ (CS4315)
+ETH2 FM1@GTEC3 fm1-mac1 0xfe4e0000 10G Base-T (AQ1202)
+ETH3 FM1@GTEC4 fm1-mac2 0xfe4e2000 10G Base-T (AQ1202)
+ETH4 FM1@DTSEC3 fm1-mac3 0xfe4e4000 1G RGMII (RTL8211E)
+ETH5 FM1@DTSEC4 fm1-mac4 0xfe4e6000 1G RGMII (RTL8211E)
+
+
+T2080PCIe-RDB Default DIP-Switch setting
+----------------------------------------
+SW1[1:8] = '00010011'
+SW2[1:8] = '10111111'
+SW3[1:8] = '11100001'
+
+Software configurations and board settings
+------------------------------------------
+1. NOR boot:
+ a. build NOR boot image
+ $ make T2080RDB
+ b. program u-boot.bin image to NOR flash
+ => tftp 1000000 u-boot.bin
+ => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
+ set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
+
+ Switching between default bank and alternate bank on NOR flash
+ To change boot source to vbank4:
+ via software: run command 'cpld reset altbank' in u-boot.
+ via DIP-switch: set SW3[5:7] = '011'
+
+ To change boot source to vbank0:
+ via software: run command 'cpld reset' in u-boot.
+ via DIP-Switch: set SW3[5:7] = '111'
+
+2. NAND Boot:
+ a. build PBL image for NAND boot
+ $ make T2080RDB_NAND_config
+ $ make u-boot.pbl
+ b. program u-boot.pbl to NAND flash
+ => tftp 1000000 u-boot.pbl
+ => nand erase 0 d0000
+ => nand write 1000000 0 $filesize
+ set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
+
+3. SPI Boot:
+ a. build PBL image for SPI boot
+ $ make T2080RDB_SPIFLASH_config
+ $ make u-boot.pbl
+ b. program u-boot.pbl to SPI flash
+ => tftp 1000000 u-boot.pbl
+ => sf probe 0
+ => sf erase 0 d0000
+ => sf write 1000000 0 $filesize
+ set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
+
+4. SD Boot:
+ a. build PBL image for SD boot
+ $ make T2080RDB_SDCARD_config
+ $ make u-boot.pbl
+ b. program u-boot.pbl to TF card
+ => tftp 1000000 u-boot.pbl
+ => mmc write 1000000 8 1650
+ set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
+
+
+How to update the ucode of Cortina CS4315/CS4340 10G PHY
+--------------------------------------------------------
+=> tftp 1000000 CS4315-CS4340-PHY-ucode.txt
+=> pro off all;era 0xefe00000 0xefefffff;cp.b 1000000 0xefe00000 $filesize
+
+
+How to update the ucode of Freescale FMAN
+-----------------------------------------
+=> tftp 1000000 fsl_fman_ucode_t2080_r1.0.bin
+=> pro off all;erase 0xeff00000 0xeff1ffff;cp 1000000 0xeff00000 $filesize
+
+
+For more details, please refer to T2080PCIe-RDB User Guide and access
+website www.freescale.com and Freescale QorIQ SDK Infocenter document.
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Freescale T2080RDB board-specific CPLD controlling supports.
+ */
+
+#include <common.h>
+#include <command.h>
+#include "cpld.h"
+
+u8 cpld_read(unsigned int reg)
+{
+ void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+ return in_8(p + reg);
+}
+
+void cpld_write(unsigned int reg, u8 value)
+{
+ void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+ out_8(p + reg, value);
+}
+
+/* Set the boot bank to the alternate bank */
+void cpld_set_altbank(void)
+{
+ u8 reg = CPLD_READ(flash_csr);
+
+ reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK;
+ CPLD_WRITE(flash_csr, reg);
+ CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET);
+}
+
+/* Set the boot bank to the default bank */
+void cpld_set_defbank(void)
+{
+ u8 reg = CPLD_READ(flash_csr);
+
+ reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK;
+ CPLD_WRITE(flash_csr, reg);
+ CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET);
+}
+
+int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int rc = 0;
+
+ if (argc <= 1)
+ return cmd_usage(cmdtp);
+
+ if (strcmp(argv[1], "reset") == 0) {
+ if (strcmp(argv[2], "altbank") == 0)
+ cpld_set_altbank();
+ else
+ cpld_set_defbank();
+ } else {
+ rc = cmd_usage(cmdtp);
+ }
+
+ return rc;
+}
+
+U_BOOT_CMD(
+ cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
+ "Reset the board or alternate bank",
+ "reset: reset to default bank\n"
+ "cpld reset altbank: reset to alternate bank\n"
+);
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * CPLD register set of T2080RDB board-specific.
+ */
+struct cpld_data {
+ u8 chip_id1; /* 0x00 - Chip ID1 register */
+ u8 chip_id2; /* 0x01 - Chip ID2 register */
+ u8 hw_ver; /* 0x02 - Hardware Revision Register */
+ u8 sw_ver; /* 0x03 - Software Revision register */
+ u8 res0[12]; /* 0x04 - 0x0F - not used */
+ u8 reset_ctl; /* 0x10 - Reset control Register */
+ u8 flash_csr; /* 0x11 - Flash control and status register */
+ u8 thermal_csr; /* 0x12 - Thermal control and status register */
+ u8 led_csr; /* 0x13 - LED control and status register */
+ u8 sfp_csr; /* 0x14 - SFP+ control and status register */
+ u8 misc_csr; /* 0x15 - Misc control and status register */
+ u8 boot_or; /* 0x16 - Boot config override register */
+ u8 boot_cfg1; /* 0x17 - Boot configuration register 1 */
+ u8 boot_cfg2; /* 0x18 - Boot configuration register 2 */
+} cpld_data_t;
+
+u8 cpld_read(unsigned int reg);
+void cpld_write(unsigned int reg, u8 value);
+
+#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
+#define CPLD_WRITE(reg, value) \
+ cpld_write(offsetof(struct cpld_data, reg), value)
+
+/* CPLD on IFC */
+#define CPLD_LBMAP_MASK 0x3F
+#define CPLD_BANK_SEL_MASK 0x07
+#define CPLD_BANK_OVERRIDE 0x40
+#define CPLD_LBMAP_ALTBANK 0x43 /* BANK OR | BANK 4 */
+#define CPLD_LBMAP_DFLTBANK 0x47 /* BANK OR | BANK 0 */
+#define CPLD_LBMAP_RESET 0xFF
+#define CPLD_LBMAP_SHIFT 0x03
+#define CPLD_BOOT_SEL 0x80
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 or later as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+
+ if (ctrl_num > 1) {
+ printf("Not supported controller number %d\n", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ pbsp = udimms[0];
+
+ /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks &&
+ (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found");
+ printf("for data rate %lu MT/s\n", ddr_freq);
+ printf("Trying to use the highest speed (%u) parameters\n",
+ pbsp_highest->datarate_mhz_high);
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+found:
+ debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+ "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
+ "wrlvl_ctrl_3 0x%x\n",
+ pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+ pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+ pbsp->wrlvl_ctl_3);
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+ /*
+ * Write leveling override
+ */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+
+ /*
+ * Rtt and Rtt_WR override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+ /* DHC_EN =1, ODT = 75 Ohm */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size;
+
+ puts("Initializing....using SPD\n");
+
+ dram_size = fsl_ddr_sdram();
+
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
+ puts(" DDR: ");
+ return dram_size;
+}
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 rank_gb;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 wrlvl_ctl_2;
+ u32 wrlvl_ctl_3;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
+ */
+ {2, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a},
+ {2, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09},
+ {2, 1600, 2, 5, 8, 0x0808070b, 0x0c0d0e0a},
+ {2, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
+ {2, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c},
+ {1, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a},
+ {1, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09},
+ {1, 1600, 2, 5, 8, 0x0808070b, 0x0c0d0e0a},
+ {1, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
+ {1, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c},
+ {}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+};
+#endif
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * Shengzhou Liu <Shengzhou.Liu@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <malloc.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <asm/fsl_dtsec.h>
+#include <asm/fsl_serdes.h>
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_FMAN_ENET)
+ int i, interface;
+ struct memac_mdio_info dtsec_mdio_info;
+ struct memac_mdio_info tgec_mdio_info;
+ struct mii_dev *dev;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 srds_s1;
+
+ srds_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+ srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+ dtsec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+
+ dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+ /* Register the 1G MDIO bus */
+ fm_memac_mdio_init(bis, &dtsec_mdio_info);
+
+ tgec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+ tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+ /* Register the 10G MDIO bus */
+ fm_memac_mdio_init(bis, &tgec_mdio_info);
+
+ /* Set the two on-board RGMII PHY address */
+ fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
+
+ switch (srds_s1) {
+ case 0x66:
+ case 0x6b:
+ fm_info_set_phy_address(FM1_10GEC1, CORTINA_PHY_ADDR1);
+ fm_info_set_phy_address(FM1_10GEC2, CORTINA_PHY_ADDR2);
+ fm_info_set_phy_address(FM1_10GEC3, FM1_10GEC3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_10GEC4, FM1_10GEC4_PHY_ADDR);
+ break;
+ default:
+ printf("SerDes1 protocol 0x%x is not supported on T208xRDB\n",
+ srds_s1);
+ break;
+ }
+
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ interface = fm_info_get_enet_if(i);
+ switch (interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+ fm_info_set_mdio(i, dev);
+ break;
+ default:
+ break;
+ }
+ }
+
+ for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_XGMII:
+ dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
+ fm_info_set_mdio(i, dev);
+ break;
+ default:
+ break;
+ }
+ }
+
+ cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+ return pci_eth_init(bis);
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+ return;
+}
--- /dev/null
+/*
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef CONFIG_SYS_CPLD_BASE_PHYS
+ SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ /* Limit DCSR to 32M to access NPC Trace Buffer */
+ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
--- /dev/null
+/*
+ * Copyright 2007-2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+ FT_FSL_PCI_SETUP;
+}
--- /dev/null
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer doc/README.pblimage for more details about how-to configure
+# and create PBL boot image
+#
+
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#512KB SRAM
+09010100 00000000
+09010104 fff80009
+09010f00 08000000
+#enable CPC1
+09010000 80000000
+#Configure LAW for CPC1
+09000d00 00000000
+09000d04 fff80000
+09000d08 81000012
+#Initialize eSPI controller, default configuration is slow for eSPI to
+#load data, this configuration comes from u-boot eSPI driver.
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Errata for slowing down the MDC clock to make it <= 2.5 MHZ
+094fc030 00008148
+094fd030 00008148
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Flush PBL data
+09138000 00000000
+091380c0 00000000
--- /dev/null
+#PBL preamble and RCW header for T2080RDB
+aa55aa55 010e0100
+#SerDes Protocol: 0x66_0x16
+#Core/DDR: 1533Mhz/1600MT/s
+120c0017 15000000 00000000 00000000
+66160002 00008400 ec104000 c1000000
+00000000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004
--- /dev/null
+/*
+ * Copyright 2009-2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+#include "t208xrdb.h"
+#include "cpld.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ struct cpu_type *cpu = gd->arch.cpu;
+ static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
+
+ printf("Board: %sRDB, ", cpu->name);
+ printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ",
+ CPLD_READ(hw_ver), CPLD_READ(sw_ver));
+
+#ifdef CONFIG_SDCARD
+ puts("SD/MMC\n");
+#elif CONFIG_SPIFLASH
+ puts("SPI\n");
+#else
+ u8 reg;
+
+ reg = CPLD_READ(flash_csr);
+
+ if (reg & CPLD_BOOT_SEL) {
+ puts("NAND\n");
+ } else {
+ reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
+ printf("NOR vBank%d\n", ~reg & 0x7);
+ }
+#endif
+
+ puts("SERDES Reference Clocks:\n");
+ printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
+ printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[0], freq[0]);
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+ /*
+ * Remap Boot flash + PROMJET region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* invalidate existing TLB entry for flash + promjet */
+ disable_tlb(flash_esel);
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+ set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ setup_portals();
+#endif
+
+ return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ return CONFIG_SYS_CLK_FREQ;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ return CONFIG_DDR_CLK_FREQ;
+}
+
+int misc_init_r(void)
+{
+ return 0;
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+ pci_of_setup(blob, bd);
+#endif
+
+ fdt_fixup_liodn(blob);
+ fdt_fixup_dr_usb(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ fdt_fixup_fman_ethernet(blob);
+ fdt_fixup_board_enet(blob);
+#endif
+}
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CORENET_DS_H__
+#define __CORENET_DS_H__
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, bd_t *bd);
+
+#endif
--- /dev/null
+/*
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+ /*
+ * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
+ * SRAM is at 0xfff00000, it covered the 0xfffff000.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+ /*
+ * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
+ * space is at 0xfff00000, it covered the 0xfffff000.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+ CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
+#else
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_16M, 1),
+
+ /* *I*G* - Flash, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCIe 1, 0x80000000 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_512M, 1),
+
+ /* *I*G* - PCIe 2, 0xa0000000 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCIe 3, 0xb0000000 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256M, 1),
+
+
+ /* *I*G* - PCIe 4, 0xc0000000 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_256K, 1),
+
+ /* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 9, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 11, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 12, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 13, BOOKE_PAGESZ_32M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+ /*
+ * *I*G - NAND
+ * entry 14 and 15 has been used hard coded, they will be disabled
+ * in cpu_init_f, so we use entry 16 for nand.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 16, BOOKE_PAGESZ_64K, 1),
+#endif
+#ifdef CONFIG_SYS_CPLD_BASE
+ SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 17, BOOKE_PAGESZ_4K, 1),
+#endif
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+ /*
+ * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
+ * fetching ucode and ENV from master
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
+ CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+ 0, 18, BOOKE_PAGESZ_1M, 1),
+#endif
+#if defined(CONFIG_SYS_RAMBOOT)
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 19, BOOKE_PAGESZ_2G, 1)
+#endif
+
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
# U-BOOT IN SDRAM
#CONFIG_SYS_TEXT_BASE = 0x60000000
-
-PLATFORM_CPPFLAGS += -I$(TOPDIR)/board
# U-BOOT IN SDRAM
#CONFIG_SYS_TEXT_BASE = 0x40000000
-
-PLATFORM_CPPFLAGS += -I$(TOPDIR)/board
# U-BOOT IN RAM
#CONFIG_SYS_TEXT_BASE = 0x40000000
-
-PLATFORM_CPPFLAGS += -I$(TOPDIR)/board
# U-BOOT IN RAM
#CONFIG_SYS_TEXT_BASE = 0x40000000
-
-PLATFORM_CPPFLAGS += -I$(TOPDIR)/board
# RUN U-BOOT FROM RAM
#CONFIG_SYS_TEXT_BASE = 0x40000000
-
-PLATFORM_CPPFLAGS += -I$(TOPDIR)/board
#include <netdev.h>
#include <scsi.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#include <asm/io.h>
#define HB_AHCI_BASE 0xffe08000
return rc;
}
-#ifdef CONFIG_MISC_INIT_R
-int misc_init_r(void)
+#ifdef CONFIG_SCSI_AHCI_PLAT
+void scsi_init(void)
{
- char envbuffer[16];
- u32 boot_choice;
u32 reg = readl(HB_SREG_A9_PWRDOM_STAT);
if (reg & PWRDOM_STAT_SATA) {
ahci_init(HB_AHCI_BASE);
scsi_scan(1);
}
+}
+#endif
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+ char envbuffer[16];
+ u32 boot_choice;
boot_choice = readl(HB_SREG_A9_BOOT_SRC_STAT) & 0xff;
sprintf(envbuffer, "bootcmd%d", boot_choice);
# HYMOD boards
#
-PLATFORM_CPPFLAGS += -I$(TOPDIR)
+PLATFORM_CPPFLAGS += -I$(srctree)
OBJCOPYFLAGS = --remove-section=.ppcenv
#ifndef _HYMOD_H_
#define _HYMOD_H_
-#ifdef CONFIG_8260
+#ifdef CONFIG_MPC8260
#include <asm/iopin_8260.h>
#endif
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = idmr.o flash.o
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-CONFIG_SYS_TEXT_BASE = 0xff800000
+++ /dev/null
-/*
- * (C) Copyright 2000-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
-#define FLASH_BANK_SIZE 0x800000
-#define EN29LV640 0x227e227e
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-void flash_print_info (flash_info_t * info)
-{
- int i;
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case (AMD_MANUFACT & FLASH_VENDMASK):
- printf ("AMD: ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case (EN29LV640 & FLASH_TYPEMASK):
- printf ("EN29LV640 (16Mbit)\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- goto Done;
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; i++) {
- if ((i % 5) == 0) {
- printf ("\n ");
- }
- printf (" %08lX%s", info->start[i],
- info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
-
- Done:
- return;
-}
-
-
-unsigned long flash_init (void)
-{
- int i, j;
- ulong size = 0;
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- ulong flashbase = 0;
-
- flash_info[i].flash_id =
- (AMD_MANUFACT & FLASH_VENDMASK) |
- (EN29LV640 & FLASH_TYPEMASK);
- flash_info[i].size = FLASH_BANK_SIZE;
- flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
- if (i == 0)
- flashbase = PHYS_FLASH_1;
- else
- panic ("configured to many flash banks!\n");
-
- for (j = 0; j < flash_info[i].sector_count; j++) {
- flash_info[i].start[j] = flashbase + 0x10000 * j;
- }
- size += flash_info[i].size;
- }
-
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_FLASH_BASE,
- CONFIG_SYS_FLASH_BASE + 0x2ffff, &flash_info[0]);
-
- return size;
-}
-
-
-#define CMD_READ_ARRAY 0x00F0
-#define CMD_UNLOCK1 0x00AA
-#define CMD_UNLOCK2 0x0055
-#define CMD_ERASE_SETUP 0x0080
-#define CMD_ERASE_CONFIRM 0x0030
-#define CMD_PROGRAM 0x00A0
-#define CMD_UNLOCK_BYPASS 0x0020
-
-#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555<<1)))
-#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA<<1)))
-
-#define BIT_ERASE_DONE 0x0080
-#define BIT_RDY_MASK 0x0080
-#define BIT_PROGRAM_ERROR 0x0020
-#define BIT_TIMEOUT 0x80000000 /* our flag */
-
-#define READY 1
-#define ERR 2
-#define TMO 4
-
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- ulong result;
- int iflag, prot, sect;
- int rc = ERR_OK;
- int chip1;
- ulong start;
-
- /* first look for protection bits */
-
- if (info->flash_id == FLASH_UNKNOWN)
- return ERR_UNKNOWN_FLASH_TYPE;
-
- if ((s_first < 0) || (s_first > s_last)) {
- return ERR_INVAL;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) !=
- (AMD_MANUFACT & FLASH_VENDMASK)) {
- return ERR_UNKNOWN_FLASH_VENDOR;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
- if (prot)
- return ERR_PROTECTED;
-
- /*
- * Disable interrupts which might cause a timeout
- * here. Remember that our exception vectors are
- * at address 0 in the flash, and we don't want a
- * (ticker) exception to happen while the flash
- * chip is in programming mode.
- */
- iflag = disable_interrupts ();
-
- printf ("\n");
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
- printf ("Erasing sector %2d ... ", sect);
-
- /* arm simple, non interrupt dependent timer */
- start = get_timer(0);
-
- if (info->protect[sect] == 0) { /* not protected */
- volatile u16 *addr =
- (volatile u16 *) (info->start[sect]);
-
- MEM_FLASH_ADDR1 = CMD_UNLOCK1;
- MEM_FLASH_ADDR2 = CMD_UNLOCK2;
- MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
-
- MEM_FLASH_ADDR1 = CMD_UNLOCK1;
- MEM_FLASH_ADDR2 = CMD_UNLOCK2;
- *addr = CMD_ERASE_CONFIRM;
-
- /* wait until flash is ready */
- chip1 = 0;
-
- do {
- result = *addr;
-
- /* check timeout */
- if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT * CONFIG_SYS_HZ / 1000) {
- MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
- chip1 = TMO;
- break;
- }
-
- if (!chip1
- && (result & 0xFFFF) & BIT_ERASE_DONE)
- chip1 = READY;
-
- } while (!chip1);
-
- MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
-
- if (chip1 == ERR) {
- rc = ERR_PROG_ERROR;
- goto outahere;
- }
- if (chip1 == TMO) {
- rc = ERR_TIMOUT;
- goto outahere;
- }
-
- printf ("ok.\n");
- } else { /* it was protected */
-
- printf ("protected!\n");
- }
- }
-
- if (ctrlc ())
- printf ("User Interrupt!\n");
-
- outahere:
- /* allow flash to settle - wait 10 ms */
- printf("Waiting 10 ms...");
- udelay (10000);
-
-/* for (i = 0; i < 10 * 1000 * 1000; ++i)
- asm(" nop");
-*/
-
- printf("done\n");
- if (iflag)
- enable_interrupts ();
-
-
- return rc;
-}
-
-static int write_word (flash_info_t * info, ulong dest, ulong data)
-{
- volatile u16 *addr = (volatile u16 *) dest;
- ulong result;
- int rc = ERR_OK;
- int iflag;
- int chip1;
- ulong start;
-
- /*
- * Check if Flash is (sufficiently) erased
- */
- result = *addr;
- if ((result & data) != data)
- return ERR_NOT_ERASED;
-
-
- /*
- * Disable interrupts which might cause a timeout
- * here. Remember that our exception vectors are
- * at address 0 in the flash, and we don't want a
- * (ticker) exception to happen while the flash
- * chip is in programming mode.
- */
- iflag = disable_interrupts ();
-
- MEM_FLASH_ADDR1 = CMD_UNLOCK1;
- MEM_FLASH_ADDR2 = CMD_UNLOCK2;
- MEM_FLASH_ADDR1 = CMD_PROGRAM;
- *addr = data;
-
- /* arm simple, non interrupt dependent timer */
- start = get_timer(0);
-
- /* wait until flash is ready */
- chip1 = 0;
- do {
- result = *addr;
-
- /* check timeout */
- if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT * CONFIG_SYS_HZ / 1000) {
- chip1 = ERR | TMO;
- break;
- }
- if (!chip1 && ((result & 0x80) == (data & 0x80)))
- chip1 = READY;
-
- } while (!chip1);
-
- *addr = CMD_READ_ARRAY;
-
- if (chip1 == ERR || *addr != data)
- rc = ERR_PROG_ERROR;
-
- if (iflag)
- enable_interrupts ();
-
- return rc;
-}
-
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong wp, data;
- int rc;
-
- if (addr & 1) {
- printf ("unaligned destination not supported\n");
- return ERR_ALIGN;
- }
-
-#if 0
- if (cnt & 1) {
- printf ("odd transfer sizes not supported\n");
- return ERR_ALIGN;
- }
-#endif
-
- wp = addr;
-
- if (addr & 1) {
- data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *)
- src);
- if ((rc = write_word (info, wp - 1, data)) != 0) {
- return (rc);
- }
- src += 1;
- wp += 1;
- cnt -= 1;
- }
-
- while (cnt >= 2) {
- data = *((volatile u16 *) src);
- if ((rc = write_word (info, wp, data)) != 0) {
- return (rc);
- }
- src += 2;
- wp += 2;
- cnt -= 2;
- }
-
- if (cnt == 1) {
- data = (*((volatile u8 *) src) << 8) |
- *((volatile u8 *) (wp + 1));
- if ((rc = write_word (info, wp, data)) != 0) {
- return (rc);
- }
- src += 1;
- wp += 1;
- cnt -= 1;
- }
-
- return ERR_OK;
-}
+++ /dev/null
-/*
- * (C) Copyright 2000-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/immap.h>
-
-int checkboard (void) {
- puts ("Board: iDMR\n");
- return 0;
-};
-
-phys_size_t initdram (int board_type) {
- int i;
-
- /*
- * After reset, CS0 is configured to cover entire address space. We
- * need to configure it to its proper values, so that writes to
- * CONFIG_SYS_SDRAM_BASE and vicinity during SDRAM controller setup below do
- * now fall under CS0 (see 16.3.1 of the MCF5271 Reference Manual).
- */
-
- /* Flash chipselect, CS0 */
- /* ;CSAR0: Flash at 0xFF800000 */
- mbar_writeShort(0x0080, 0xFF80);
-
- /* CSCR0: Flash 6 waits, 16bit */
- mbar_writeShort(0x008A, 0x1980);
-
- /* CSMR0: Flash 8MB, R/W, valid */
- mbar_writeLong(0x0084, 0x007F0001);
-
-
- /*
- * SDRAM configuration proper
- */
-
- /*
- * Address/Data Pin Assignment Reg.: enable address lines 23-21; do
- * not enable data pins D[15:0], as we have 16 bit port to SDRAM
- */
- mbar_writeByte(MCF_GPIO_PAR_AD,
- MCF_GPIO_AD_ADDR23 |
- MCF_GPIO_AD_ADDR22 |
- MCF_GPIO_AD_ADDR21);
-
- /* No need to configure BS pins - reset values are OK */
-
- /* Chip Select Pin Assignment Reg.: set CS[1-7] to GPIO */
- mbar_writeByte(MCF_GPIO_PAR_CS, 0x00);
-
- /* SDRAM Control Pin Assignment Reg. */
- mbar_writeByte(MCF_GPIO_PAR_SDRAM,
- MCF_GPIO_SDRAM_CSSDCS_00 | /* no matter: PAR_CS=0 */
- MCF_GPIO_SDRAM_SDWE |
- MCF_GPIO_SDRAM_SCAS |
- MCF_GPIO_SDRAM_SRAS |
- MCF_GPIO_SDRAM_SCKE |
- MCF_GPIO_SDRAM_SDCS_01);
-
- /*
- * Wait 100us. We run the bus at 50MHz, one cycle is 20ns. So 5
- * iterations will do, but we do 10 just to be safe.
- */
- for (i = 0; i < 10; ++i)
- asm(" nop");
-
-
- /* 1. Initialize DRAM Control Register: DCR */
- mbar_writeShort(MCF_SDRAMC_DCR,
- MCF_SDRAMC_DCR_RTIM(0x10) | /* 65ns */
- MCF_SDRAMC_DCR_RC(0x60)); /* 1562 cycles */
-
-
- /*
- * 2. Initialize DACR0
- *
- * CL: 11 (CL=3: 0x03, 0x02; CL=2: 0x1)
- * CBM: cmd at A20, bank select bits 21 and up
- * PS: 16 bit
- */
- mbar_writeLong(MCF_SDRAMC_DACR0,
- MCF_SDRAMC_DACRn_BA(CONFIG_SYS_SDRAM_BASE>>18) |
- MCF_SDRAMC_DACRn_BA(0x00) |
- MCF_SDRAMC_DACRn_CASL(0x03) |
- MCF_SDRAMC_DACRn_CBM(0x03) |
- MCF_SDRAMC_DACRn_PS(0x03));
-
- /* Initialize DMR0 */
- mbar_writeLong(MCF_SDRAMC_DMR0,
- MCF_SDRAMC_DMRn_BAM_16M |
- MCF_SDRAMC_DMRn_V);
-
-
- /* 3. Set IP bit in DACR to initiate PALL command */
- mbar_writeLong(MCF_SDRAMC_DACR0,
- mbar_readLong(MCF_SDRAMC_DACR0) |
- MCF_SDRAMC_DACRn_IP);
-
- /* Write to this block to initiate precharge */
- *(volatile u16 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5;
-
- /*
- * Wait at least 20ns to allow banks to precharge (t_RP = 20ns). We
- * wait a wee longer, just to be safe.
- */
- for (i = 0; i < 5; ++i)
- asm(" nop");
-
-
- /* 4. Set RE bit in DACR */
- mbar_writeLong(MCF_SDRAMC_DACR0,
- mbar_readLong(MCF_SDRAMC_DACR0) |
- MCF_SDRAMC_DACRn_RE);
-
- /*
- * Wait for at least 8 auto refresh cycles to occur, i.e. at least
- * 781 bus cycles.
- */
- for (i = 0; i < 1000; ++i)
- asm(" nop");
-
- /* Finish the configuration by issuing the MRS */
- mbar_writeLong(MCF_SDRAMC_DACR0,
- mbar_readLong(MCF_SDRAMC_DACR0) |
- MCF_SDRAMC_DACRn_MRS);
-
- /*
- * Write to the SDRAM Mode Register A0-A11 = 0x400
- *
- * Write Burst Mode = Programmed Burst Length
- * Op Mode = Standard Op
- * CAS Latency = 3
- * Burst Type = Sequential
- * Burst Length = 1
- */
- *(volatile u32 *)(CONFIG_SYS_SDRAM_BASE + 0x1800) = 0xa5a5a5a5;
-
- return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-};
-
-
-int testdram (void) {
-
- /* TODO: XXX XXX XXX */
- printf ("DRAM test not implemented!\n");
-
- return (0);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(m68k)
-
-SECTIONS
-{
- .text :
- {
- arch/m68k/cpu/mcf52x2/start.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
-
- .reloc :
- {
- __got_start = .;
- KEEP(*(.got))
- __got_end = .;
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- _sbss = .;
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- _ebss = .;
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
# SPDX-License-Identifier: GPL-2.0+
#
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
-
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6
#include <twl4030.h>
#include <netdev.h>
#include <asm/gpio.h>
-#include <asm/omap_gpmc.h>
#include <asm/io.h>
#include <asm/arch/mem.h>
#include <asm/arch/mmc_host_def.h>
endif
ifndef CONFIG_KORAT_PERMANENT
-LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-F7FC.lds
+LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot-F7FC.lds
endif
--- /dev/null
+bootscript.img
extra-y := bootscript.img
+quiet_cmd_mkimage = UIMAGE $@
+cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
+ $(if $(KBUILD_VERBOSE:1=), >/dev/null)
+
+MKIMAGEFLAGS_bootscript.image := -T script -C none -n M7_script
+
$(obj)/bootscript.img: $(src)/bootscript
- @mkimage -T script -C none -n M7_script -d $< $@
+ $(call cmd,mkimage)
--- /dev/null
+bootscript.img
extra-y := bootscript.img
+quiet_cmd_mkimage = UIMAGE $@
+cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
+ $(if $(KBUILD_VERBOSE:1=), >/dev/null)
+
+MKIMAGEFLAGS_bootscript.image := -T script -C none -n mvSMR_Script
+
$(obj)/bootscript.img: $(src)/bootscript
- @mkimage -T script -C none -n mvSMR_Script -d $< $@
+ $(call cmd,mkimage)
# vct_xxx boards with MIPS 4Kc CPU core
#
-sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
-
ifndef CONFIG_SYS_TEXT_BASE
CONFIG_SYS_TEXT_BASE = 0x87000000
endif
static void usb_display_Req(unsigned short req) {}
#endif
-static unsigned char root_hub_dev_des[] =
-{
- 0x12, /* __u8 bLength; */
- 0x01, /* __u8 bDescriptorType; Device */
- 0x00, /* __u16 bcdUSB; v1.0 */
- 0x01,
- 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
- 0x00, /* __u8 bDeviceSubClass; */
- 0x00, /* __u8 bDeviceProtocol; */
- 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
- 0x00, /* __u16 idVendor; */
- 0x00,
- 0x00, /* __u16 idProduct; */
- 0x00,
- 0x00, /* __u16 bcdDevice; */
- 0x00,
- 0x01, /* __u8 iManufacturer; */
- 0x00, /* __u8 iProduct; */
- 0x00, /* __u8 iSerialNumber; */
- 0x01 /* __u8 bNumConfigurations; */
-};
-
-
-/* Configuration descriptor */
-static unsigned char root_hub_config_des[] =
-{
- 0x09, /* __u8 bLength; */
- 0x02, /* __u8 bDescriptorType; Configuration */
- 0x19, /* __u16 wTotalLength; */
- 0x00,
- 0x01, /* __u8 bNumInterfaces; */
- 0x01, /* __u8 bConfigurationValue; */
- 0x00, /* __u8 iConfiguration; */
- 0x40, /* __u8 bmAttributes;
- Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
- 0x00, /* __u8 MaxPower; */
-
- /* interface */
- 0x09, /* __u8 if_bLength; */
- 0x04, /* __u8 if_bDescriptorType; Interface */
- 0x00, /* __u8 if_bInterfaceNumber; */
- 0x00, /* __u8 if_bAlternateSetting; */
- 0x01, /* __u8 if_bNumEndpoints; */
- 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
- 0x00, /* __u8 if_bInterfaceSubClass; */
- 0x00, /* __u8 if_bInterfaceProtocol; */
- 0x00, /* __u8 if_iInterface; */
-
- /* endpoint */
- 0x07, /* __u8 ep_bLength; */
- 0x05, /* __u8 ep_bDescriptorType; Endpoint */
- 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
- 0x03, /* __u8 ep_bmAttributes; Interrupt */
- 0x08, /* __u16 ep_wMaxPacketSize; 8 Bytes */
- 0x00,
- 0xff /* __u8 ep_bInterval; 255 ms */
-};
-
-
-static unsigned char root_hub_hub_des[] =
-{
- 0x09, /* __u8 bLength; */
- 0x29, /* __u8 bDescriptorType; Hub-descriptor */
- 0x02, /* __u8 bNbrPorts; */
- 0x00, /* __u16 wHubCharacteristics; */
- 0x00,
- 0x01, /* __u8 bPwrOn2pwrGood; 2ms */
- 0x00, /* __u8 bHubContrCurrent; 0 mA */
- 0x00, /* __u8 DeviceRemovable; *** 7 Ports max *** */
- 0xff /* __u8 PortPwrCtrlMask; *** 7 ports max *** */
-};
-
-static unsigned char root_hub_str_index0[] =
-{
- 0x04, /* __u8 bLength; */
- 0x03, /* __u8 bDescriptorType; String-descriptor */
- 0x09, /* __u8 lang ID */
- 0x04, /* __u8 lang ID */
-};
-
-static unsigned char root_hub_str_index1[] =
-{
- 28, /* __u8 bLength; */
- 0x03, /* __u8 bDescriptorType; String-descriptor */
- 'U', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'H', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'C', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'I', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- ' ', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'R', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'o', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'o', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 't', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- ' ', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'H', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'u', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'b', /* __u8 Unicode */
- 0, /* __u8 Unicode */
-};
-
+#define WANT_USB_ROOT_HUB_HUB_DES
+#include <usbroothubdes.h>
+#undef WANT_USB_ROOT_HUB_HUB_DES
/*
* Root Hub Control Pipe (interrupt Pipes are not supported)
DEFAULT_PINMUX(ULPI_STP, ULPI, NORMAL, NORMAL, OUTPUT),
/* I2C3 pinmux */
- I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
- I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+ I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* VI pinmux */
VI_PINMUX(CAM_MCLK, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
VI_PINMUX(GPIO_PBB4, VGP4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
/* I2C2 pinmux */
- I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
- I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+ I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* UARTD pinmux */
DEFAULT_PINMUX(GMI_A16, UARTD, NORMAL, NORMAL, OUTPUT),
DEFAULT_PINMUX(KB_ROW9, UARTA, NORMAL, NORMAL, OUTPUT),
/* I2CPWR pinmux (I2C5) */
- I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
- I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+ I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* SYSCLK pinmux */
DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT),
DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
/* I2C1 pinmux */
- I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
- I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+ I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* UARTB pinmux */
DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(ULPI_STP, SPI1, NORMAL, NORMAL, INPUT),
/* I2C3 (TPM) pinmux */
- I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
- I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+ I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* I2C2 pinmux */
- I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
- I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+ I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* UARTD pinmux (UART4 on Servo board, unused) */
DEFAULT_PINMUX(GPIO_PJ7, UARTD, NORMAL, NORMAL, OUTPUT),
DEFAULT_PINMUX(KB_ROW10, UARTA, UP, TRISTATE, INPUT),
/* I2CPWR pinmux (I2C5) */
- I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
- I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+ I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* RTCK pinmux */
DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
/* I2C1 pinmux */
- I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
- I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+ I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* UARTB, GPS */
DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, TRISTATE, INPUT),
#include <asm/arch/mux.h>
#include <asm/arch/mem.h>
#include <asm/arch/sys_proto.h>
-#include <asm/omap_gpmc.h>
#include <asm/gpio.h>
#include <asm/mach-types.h>
#include "overo.h"
+++ /dev/null
-#
-# Copyright (c) Switchfin Org. <dpn@switchfin.org>
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
lowlevel_init:
- /* jump to 0xA0020000 if bit 1 of PVDR_A */
+ /* jump to CONFIG_ECOVEC_ROMIMAGE_ADDR if bit 1 of PVDR_A */
mov.l PVDR_A, r1
mov.l PVDR_D, r2
mov.b @r1, r0
*/
#include <common.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/at91sam9_smc.h>
*/
#include <common.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/at91sam9_smc.h>
*/
#include <common.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/power.h>
#include <power/pmic.h>
#include <asm/arch/sromc.h>
-#include <power/max77686_pmic.h>
+#include <lcd.h>
+#include <samsung/misc.h>
DECLARE_GLOBAL_DATA_PTR;
-struct local_info {
- struct cros_ec_dev *cros_ec_dev; /* Pointer to cros_ec device */
- int cros_ec_err; /* Error for cros_ec, 0 if ok */
-};
+int __exynos_early_init_f(void)
+{
+ return 0;
+}
+int exynos_early_init_f(void)
+ __attribute__((weak, alias("__exynos_early_init_f")));
-static struct local_info local;
+int __exynos_power_init(void)
+{
+ return 0;
+}
+int exynos_power_init(void)
+ __attribute__((weak, alias("__exynos_power_init")));
#if defined CONFIG_EXYNOS_TMU
/* Boot Time Thermal Analysis for SoC temperature threshold breach */
board_i2c_init(gd->fdt_blob);
#endif
- return err;
-}
-#endif
-
-struct cros_ec_dev *board_get_cros_ec_dev(void)
-{
- return local.cros_ec_dev;
-}
-
-#ifdef CONFIG_CROS_EC
-static int board_init_cros_ec_devices(const void *blob)
-{
- local.cros_ec_err = cros_ec_init(blob, &local.cros_ec_dev);
- if (local.cros_ec_err)
- return -1; /* Will report in board_late_init() */
-
- return 0;
+ return exynos_early_init_f();
}
#endif
#if defined(CONFIG_POWER)
-#ifdef CONFIG_POWER_MAX77686
-static int pmic_reg_update(struct pmic *p, int reg, uint regval)
-{
- u32 val;
- int ret = 0;
-
- ret = pmic_reg_read(p, reg, &val);
- if (ret) {
- debug("%s: PMIC %d register read failed\n", __func__, reg);
- return -1;
- }
- val |= regval;
- ret = pmic_reg_write(p, reg, val);
- if (ret) {
- debug("%s: PMIC %d register write failed\n", __func__, reg);
- return -1;
- }
- return 0;
-}
-
-static int max77686_init(void)
-{
- struct pmic *p;
-
- if (pmic_init(I2C_PMIC))
- return -1;
-
- p = pmic_get("MAX77686_PMIC");
- if (!p)
- return -ENODEV;
-
- if (pmic_probe(p))
- return -1;
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
- return -1;
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
- MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
- return -1;
-
- /* VDD_MIF */
- if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
- MAX77686_BUCK1OUT_1V)) {
- debug("%s: PMIC %d register write failed\n", __func__,
- MAX77686_REG_PMIC_BUCK1OUT);
- return -1;
- }
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
- MAX77686_BUCK1CTRL_EN))
- return -1;
-
- /* VDD_ARM */
- if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
- MAX77686_BUCK2DVS1_1_3V)) {
- debug("%s: PMIC %d register write failed\n", __func__,
- MAX77686_REG_PMIC_BUCK2DVS1);
- return -1;
- }
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
- MAX77686_BUCK2CTRL_ON))
- return -1;
-
- /* VDD_INT */
- if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
- MAX77686_BUCK3DVS1_1_0125V)) {
- debug("%s: PMIC %d register write failed\n", __func__,
- MAX77686_REG_PMIC_BUCK3DVS1);
- return -1;
- }
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
- MAX77686_BUCK3CTRL_ON))
- return -1;
-
- /* VDD_G3D */
- if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
- MAX77686_BUCK4DVS1_1_2V)) {
- debug("%s: PMIC %d register write failed\n", __func__,
- MAX77686_REG_PMIC_BUCK4DVS1);
- return -1;
- }
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
- MAX77686_BUCK3CTRL_ON))
- return -1;
-
- /* VDD_LDO2 */
- if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
- MAX77686_LD02CTRL1_1_5V | EN_LDO))
- return -1;
-
- /* VDD_LDO3 */
- if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
- MAX77686_LD03CTRL1_1_8V | EN_LDO))
- return -1;
-
- /* VDD_LDO5 */
- if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
- MAX77686_LD05CTRL1_1_8V | EN_LDO))
- return -1;
-
- /* VDD_LDO10 */
- if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
- MAX77686_LD10CTRL1_1_8V | EN_LDO))
- return -1;
-
- return 0;
-}
-#endif
-
int power_init_board(void)
{
- int ret = 0;
-
set_ps_hold_ctrl();
-#ifdef CONFIG_POWER_MAX77686
- ret = max77686_init();
-#endif
-
- return ret;
+ return exynos_power_init();
}
#endif
#ifdef CONFIG_OF_CONTROL
+#ifdef CONFIG_SMC911X
static int decode_sromc(const void *blob, struct fdt_sromc *config)
{
int err;
}
return 0;
}
+#endif
int board_eth_init(bd_t *bis)
{
{
int ret;
+#ifdef CONFIG_SDHCI
+ /* mmc initializattion for available channels */
+ ret = exynos_mmc_init(gd->fdt_blob);
+ if (ret)
+ debug("mmc init failed\n");
+#endif
+#ifdef CONFIG_DWMMC
/* dwmmc initializattion for available channels */
ret = exynos_dwmmc_init(gd->fdt_blob);
if (ret)
debug("dwmmc init failed\n");
+#endif
return ret;
}
#endif
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+ const char *board_name;
+
+ board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
+ printf("Board: %s\n", board_name ? board_name : "unknown");
+
+ return 0;
+}
#endif
+#endif /* CONFIG_OF_CONTROL */
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
stdio_print_current_devices();
- if (local.cros_ec_err) {
+ if (cros_ec_get_error()) {
/* Force console on */
gd->flags &= ~GD_FLG_SILENT;
printf("cros-ec communications failure %d\n",
- local.cros_ec_err);
+ cros_ec_get_error());
puts("\nPlease reset with Power+Refresh\n\n");
panic("Cannot init cros-ec device");
return -1;
int arch_early_init_r(void)
{
#ifdef CONFIG_CROS_EC
- if (board_init_cros_ec_devices(gd->fdt_blob)) {
+ if (cros_ec_board_init()) {
printf("%s: Failed to init EC\n", __func__);
return 0;
}
return 0;
}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ set_board_info();
+#endif
+#ifdef CONFIG_LCD_MENU
+ keys_init();
+ check_boot_mode();
+#endif
+#ifdef CONFIG_CMD_BMP
+ if (panel_info.logo_on)
+ draw_logo();
+#endif
+ return 0;
+}
+#endif
#include <samsung/misc.h>
#include <errno.h>
#include <version.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#include <asm/arch/cpu.h>
#include <asm/arch/gpio.h>
#include <asm/gpio.h>
#include <asm/arch/mmc.h>
#include <asm/arch/periph.h>
#include <asm/arch/pinmux.h>
+#include <usb.h>
DECLARE_GLOBAL_DATA_PTR;
-struct exynos4_gpio_part1 *gpio1;
-struct exynos4_gpio_part2 *gpio2;
-int board_init(void)
+u32 get_board_rev(void)
{
- gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
- gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
-
- gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
return 0;
}
-static int board_uart_init(void)
+int exynos_init(void)
{
- int err;
-
- err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE);
- if (err) {
- debug("UART0 not configured\n");
- return err;
- }
-
- err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE);
- if (err) {
- debug("UART1 not configured\n");
- return err;
- }
-
- err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE);
- if (err) {
- debug("UART2 not configured\n");
- return err;
- }
-
- err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
- if (err) {
- debug("UART3 not configured\n");
- return err;
- }
-
return 0;
}
-#ifdef CONFIG_BOARD_EARLY_INIT_F
-int board_early_init_f(void)
-{
- int err;
- err = board_uart_init();
- if (err) {
- debug("UART init failed\n");
- return err;
- }
- return err;
-}
-#endif
-
-int dram_init(void)
+int board_usb_init(int index, enum usb_init_type init)
{
- gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
- + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
- + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
- + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
-
return 0;
}
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, \
- PHYS_SDRAM_1_SIZE);
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, \
- PHYS_SDRAM_2_SIZE);
- gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
- gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, \
- PHYS_SDRAM_3_SIZE);
- gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
- gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, \
- PHYS_SDRAM_4_SIZE);
-}
-
-#ifdef CONFIG_DISPLAY_BOARDINFO
-int checkboard(void)
+#ifdef CONFIG_USB_CABLE_CHECK
+int usb_cable_connected(void)
{
- printf("\nBoard: ORIGEN\n");
return 0;
}
#endif
-#ifdef CONFIG_GENERIC_MMC
-int board_mmc_init(bd_t *bis)
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int exynos_early_init_f(void)
{
- int i, err;
-
- /*
- * MMC2 SD card GPIO:
- *
- * GPK2[0] SD_2_CLK(2)
- * GPK2[1] SD_2_CMD(2)
- * GPK2[2] SD_2_CDn
- * GPK2[3:6] SD_2_DATA[0:3](2)
- */
- for (i = 0; i < 7; i++) {
- /* GPK2[0:6] special function 2 */
- s5p_gpio_cfg_pin(&gpio2->k2, i, GPIO_FUNC(0x2));
-
- /* GPK2[0:6] drv 4x */
- s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X);
-
- /* GPK2[0:1] pull disable */
- if (i == 0 || i == 1) {
- s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE);
- continue;
- }
-
- /* GPK2[2:6] pull up */
- s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_UP);
- }
-
- err = s5p_mmc_init(2, 4);
- return err;
+ return 0;
}
#endif
*/
#include <common.h>
-#include <cros_ec.h>
#include <fdtdec.h>
#include <asm/io.h>
#include <errno.h>
return 0;
}
-#ifdef CONFIG_DISPLAY_BOARDINFO
-int checkboard(void)
-{
- const char *board_name;
-
- board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
- if (board_name == NULL)
- printf("\nUnknown Board\n");
- else
- printf("\nBoard: %s\n", board_name);
-
- return 0;
-}
-#endif
-
#ifdef CONFIG_LCD
void exynos_cfg_lcd_gpio(void)
{
}
}
+#if defined(CONFIG_POWER)
+#ifdef CONFIG_POWER_MAX77686
+static int pmic_reg_update(struct pmic *p, int reg, uint regval)
+{
+ u32 val;
+ int ret = 0;
+
+ ret = pmic_reg_read(p, reg, &val);
+ if (ret) {
+ debug("%s: PMIC %d register read failed\n", __func__, reg);
+ return -1;
+ }
+ val |= regval;
+ ret = pmic_reg_write(p, reg, val);
+ if (ret) {
+ debug("%s: PMIC %d register write failed\n", __func__, reg);
+ return -1;
+ }
+ return 0;
+}
+
+static int max77686_init(void)
+{
+ struct pmic *p;
+
+ if (pmic_init(I2C_PMIC))
+ return -1;
+
+ p = pmic_get("MAX77686_PMIC");
+ if (!p)
+ return -ENODEV;
+
+ if (pmic_probe(p))
+ return -1;
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
+ return -1;
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
+ MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
+ return -1;
+
+ /* VDD_MIF */
+ if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
+ MAX77686_BUCK1OUT_1V)) {
+ debug("%s: PMIC %d register write failed\n", __func__,
+ MAX77686_REG_PMIC_BUCK1OUT);
+ return -1;
+ }
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
+ MAX77686_BUCK1CTRL_EN))
+ return -1;
+
+ /* VDD_ARM */
+ if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
+ MAX77686_BUCK2DVS1_1_3V)) {
+ debug("%s: PMIC %d register write failed\n", __func__,
+ MAX77686_REG_PMIC_BUCK2DVS1);
+ return -1;
+ }
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
+ MAX77686_BUCK2CTRL_ON))
+ return -1;
+
+ /* VDD_INT */
+ if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
+ MAX77686_BUCK3DVS1_1_0125V)) {
+ debug("%s: PMIC %d register write failed\n", __func__,
+ MAX77686_REG_PMIC_BUCK3DVS1);
+ return -1;
+ }
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
+ MAX77686_BUCK3CTRL_ON))
+ return -1;
+
+ /* VDD_G3D */
+ if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
+ MAX77686_BUCK4DVS1_1_2V)) {
+ debug("%s: PMIC %d register write failed\n", __func__,
+ MAX77686_REG_PMIC_BUCK4DVS1);
+ return -1;
+ }
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
+ MAX77686_BUCK3CTRL_ON))
+ return -1;
+
+ /* VDD_LDO2 */
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
+ MAX77686_LD02CTRL1_1_5V | EN_LDO))
+ return -1;
+
+ /* VDD_LDO3 */
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
+ MAX77686_LD03CTRL1_1_8V | EN_LDO))
+ return -1;
+
+ /* VDD_LDO5 */
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
+ MAX77686_LD05CTRL1_1_8V | EN_LDO))
+ return -1;
+
+ /* VDD_LDO10 */
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
+ MAX77686_LD10CTRL1_1_8V | EN_LDO))
+ return -1;
+
+ return 0;
+}
+#endif /* CONFIG_POWER_MAX77686 */
+
+int exynos_power_init(void)
+{
+ int ret = 0;
+
+#ifdef CONFIG_POWER_MAX77686
+ ret = max77686_init();
+#endif
+ return ret;
+}
+#endif /* CONFIG_POWER */
+
#ifdef CONFIG_LCD
void exynos_cfg_lcd_gpio(void)
{
{
return 0;
}
-
-#ifdef CONFIG_DISPLAY_BOARDINFO
-int checkboard(void)
-{
- const char *board_name;
-
- board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
- if (board_name == NULL)
- printf("\nUnknown Board\n");
- else
- printf("\nBoard: %s\n", board_name);
-
- return 0;
-}
-#endif
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/gpio.h>
-#include <asm/arch/mmc.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/clock.h>
-#include <asm/arch/clk.h>
#include <asm/arch/mipi_dsim.h>
#include <asm/arch/watchdog.h>
#include <asm/arch/power.h>
#include <power/pmic.h>
#include <usb/s3c_udc.h>
#include <power/max8997_pmic.h>
-#include <libtizen.h>
#include <power/max8997_muic.h>
#include <power/battery.h>
#include <power/max17042_fg.h>
+#include <libtizen.h>
#include <usb.h>
#include <usb_mass_storage.h>
-#include <samsung/misc.h>
#include "setup.h"
static void check_hw_revision(void);
struct s3c_plat_otg_data s5pc210_otg_data;
-int board_init(void)
+int exynos_init(void)
{
- gd->bd->bi_boot_params = CONFIG_SYS_SPL_ARGS_ADDR;
-
check_hw_revision();
printf("HW Revision:\t0x%x\n", board_rev);
return 0;
}
-int power_init_board(void)
+int exynos_power_init(void)
{
int chrg, ret;
struct power_battery *pb;
return 0;
}
-int dram_init(void)
-{
- gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
- get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) +
- get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) +
- get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
-
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
- gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
- gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
- gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
- gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-}
-
static unsigned int get_hw_revision(void)
{
struct exynos4_gpio_part1 *gpio =
board_rev |= hwrev;
}
-#ifdef CONFIG_DISPLAY_BOARDINFO
-int checkboard(void)
-{
- puts("Board:\tTRATS\n");
- return 0;
-}
-#endif
-
-#ifdef CONFIG_GENERIC_MMC
-int board_mmc_init(bd_t *bis)
-{
- struct exynos4_gpio_part2 *gpio =
- (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
- int err;
-
- /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
- s5p_gpio_direction_output(&gpio->k0, 2, 1);
- s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE);
-
- /*
- * MMC device init
- * mmc0 : eMMC (8-bit buswidth)
- * mmc2 : SD card (4-bit buswidth)
- */
- err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
- if (err)
- debug("SDMMC0 not configured\n");
- else
- err = s5p_mmc_init(0, 8);
-
- /* T-flash detect */
- s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf);
- s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP);
-
- /*
- * Check the T-flash detect pin
- * GPX3[4] T-flash detect pin
- */
- if (!s5p_gpio_get_value(&gpio->x3, 4)) {
- err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
- if (err)
- debug("SDMMC2 not configured\n");
- else
- err = s5p_mmc_init(2, 4);
- }
-
- return err;
-}
-#endif
#ifdef CONFIG_USB_GADGET
static int s5pc210_phy_control(int on)
writel(0, (unsigned int)&pwr->arm_core1_configuration);
}
-static void board_uart_init(void)
+static void exynos_uart_init(void)
{
- struct exynos4_gpio_part1 *gpio1 =
- (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
struct exynos4_gpio_part2 *gpio2 =
(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
- int i;
-
- /*
- * UART2 GPIOs
- * GPA1CON[0] = UART_2_RXD(2)
- * GPA1CON[1] = UART_2_TXD(2)
- * GPA1CON[2] = I2C_3_SDA (3)
- * GPA1CON[3] = I2C_3_SCL (3)
- */
-
- for (i = 0; i < 4; i++) {
- s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE);
- s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2));
- }
/* UART_SEL GPY4[7] (part2) at EXYNOS4 */
s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP);
s5p_gpio_direction_output(&gpio2->y4, 7, 1);
}
-int board_early_init_f(void)
+int exynos_early_init_f(void)
{
wdt_stop();
pmic_reset();
board_clock_init();
- board_uart_init();
+ exynos_uart_init();
board_power_init();
return 0;
s5p_gpio_direction_output(&gpio2->y4, 5, 1);
}
-static int lcd_power(void)
+int lcd_power(void)
{
int ret = 0;
struct pmic *p = pmic_get("MAX8997_PMIC");
return 0;
}
-static struct mipi_dsim_config dsim_config = {
- .e_interface = DSIM_VIDEO,
- .e_virtual_ch = DSIM_VIRTUAL_CH_0,
- .e_pixel_format = DSIM_24BPP_888,
- .e_burst_mode = DSIM_BURST_SYNC_EVENT,
- .e_no_data_lane = DSIM_DATA_LANE_4,
- .e_byte_clk = DSIM_PLL_OUT_DIV8,
- .hfp = 1,
-
- .p = 3,
- .m = 120,
- .s = 1,
-
- /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
- .pll_stable_time = 500,
-
- /* escape clk : 10MHz */
- .esc_clk = 20 * 1000000,
-
- /* stop state holding counter after bta change count 0 ~ 0xfff */
- .stop_holding_cnt = 0x7ff,
- /* bta timeout 0 ~ 0xff */
- .bta_timeout = 0xff,
- /* lp rx timeout 0 ~ 0xffff */
- .rx_timeout = 0xffff,
-};
-
-static struct exynos_platform_mipi_dsim s6e8ax0_platform_data = {
- .lcd_panel_info = NULL,
- .dsim_config = &dsim_config,
-};
-
-static struct mipi_dsim_lcd_device mipi_lcd_device = {
- .name = "s6e8ax0",
- .id = -1,
- .bus_id = 0,
- .platform_data = (void *)&s6e8ax0_platform_data,
-};
-
-static int mipi_power(void)
+int mipi_power(void)
{
int ret = 0;
struct pmic *p = pmic_get("MAX8997_PMIC");
return 0;
}
-vidinfo_t panel_info = {
- .vl_freq = 60,
- .vl_col = 720,
- .vl_row = 1280,
- .vl_width = 720,
- .vl_height = 1280,
- .vl_clkp = CONFIG_SYS_HIGH,
- .vl_hsp = CONFIG_SYS_LOW,
- .vl_vsp = CONFIG_SYS_LOW,
- .vl_dp = CONFIG_SYS_LOW,
- .vl_bpix = 4, /* Bits per pixel, 2^4 = 16 */
-
- /* s6e8ax0 Panel infomation */
- .vl_hspw = 5,
- .vl_hbpd = 10,
- .vl_hfpd = 10,
-
- .vl_vspw = 2,
- .vl_vbpd = 1,
- .vl_vfpd = 13,
- .vl_cmd_allow_len = 0xf,
-
- .win_id = 3,
- .dual_lcd_enabled = 0,
-
- .init_delay = 0,
- .power_on_delay = 0,
- .reset_delay = 0,
- .interface_mode = FIMD_RGB_INTERFACE,
- .mipi_enabled = 1,
-};
-
-void init_panel_info(vidinfo_t *vid)
+void exynos_lcd_misc_init(vidinfo_t *vid)
{
- vid->logo_on = 1,
- vid->resolution = HD_RESOLUTION,
- vid->rgb_mode = MODE_RGB_P,
-
#ifdef CONFIG_TIZEN
get_tizen_logo_info(vid);
#endif
- mipi_lcd_device.reverse_panel = 1;
-
- strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name);
- s6e8ax0_platform_data.lcd_power = lcd_power;
- s6e8ax0_platform_data.mipi_power = mipi_power;
- s6e8ax0_platform_data.phy_enable = set_mipi_phy_ctrl;
- s6e8ax0_platform_data.lcd_panel_info = (void *)vid;
- exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device);
+#ifdef CONFIG_S6E8AX0
s6e8ax0_init();
- exynos_set_dsim_platform_data(&s6e8ax0_platform_data);
-
setenv("lcdinfo", "lcd=s6e8ax0");
-}
-
-#ifdef CONFIG_MISC_INIT_R
-int misc_init_r(void)
-{
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
- set_board_info();
-#endif
-#ifdef CONFIG_LCD_MENU
- keys_init();
- check_boot_mode();
#endif
-#ifdef CONFIG_CMD_BMP
- if (panel_info.logo_on)
- draw_logo();
-#endif
- return 0;
}
-#endif
#include <common.h>
#include <lcd.h>
-#include <asm/io.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/mmc.h>
-#include <asm/arch/power.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/mipi_dsim.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/power.h>
+#include <asm/arch/mipi_dsim.h>
#include <power/pmic.h>
#include <power/max77686_pmic.h>
#include <power/battery.h>
#include <usb.h>
#include <usb/s3c_udc.h>
#include <usb_mass_storage.h>
-#include <samsung/misc.h>
DECLARE_GLOBAL_DATA_PTR;
board_rev = modelrev << 8;
}
-#ifdef CONFIG_DISPLAY_BOARDINFO
-int checkboard(void)
-{
- puts("Board:\tTRATS2\n");
- printf("HW Revision:\t0x%04x\n", board_rev);
-
- return 0;
-}
-#endif
-
u32 get_board_rev(void)
{
return board_rev;
}
#endif
-int board_early_init_f(void)
+int exynos_early_init_f(void)
{
- check_hw_revision();
board_external_gpio_init();
- gd->flags |= GD_FLG_DISABLE_CONSOLE;
-
return 0;
}
static int pmic_init_max77686(void);
-int board_init(void)
+int exynos_init(void)
{
- struct exynos4_power *pwr =
- (struct exynos4_power *)samsung_get_base_power();
-
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- /* workaround: clear INFORM4..5 */
- writel(0, (unsigned int)&pwr->inform4);
- writel(0, (unsigned int)&pwr->inform5);
+ check_hw_revision();
+ printf("HW Revision:\t0x%04x\n", board_rev);
return 0;
}
-int power_init_board(void)
+int exynos_power_init(void)
{
int chrg;
struct power_battery *pb;
return 0;
}
-int dram_init(void)
-{
- u32 size_mb;
-
- size_mb = (get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
- get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) +
- get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) +
- get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE)) >> 20;
-
- gd->ram_size = size_mb << 20;
-
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
- gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
- gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
- gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
- gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- int err0, err2 = 0;
-
- gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2();
-
- /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
- s5p_gpio_direction_output(&gpio2->k0, 2, 1);
- s5p_gpio_set_pull(&gpio2->k0, 2, GPIO_PULL_NONE);
-
- /*
- * eMMC GPIO:
- * SDR 8-bit@48MHz at MMC0
- * GPK0[0] SD_0_CLK(2)
- * GPK0[1] SD_0_CMD(2)
- * GPK0[2] SD_0_CDn -> Not used
- * GPK0[3:6] SD_0_DATA[0:3](2)
- * GPK1[3:6] SD_0_DATA[0:3](3)
- *
- * DDR 4-bit@26MHz at MMC4
- * GPK0[0] SD_4_CLK(3)
- * GPK0[1] SD_4_CMD(3)
- * GPK0[2] SD_4_CDn -> Not used
- * GPK0[3:6] SD_4_DATA[0:3](3)
- * GPK1[3:6] SD_4_DATA[4:7](4)
- */
-
- err0 = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
-
- /*
- * MMC device init
- * mmc0 : eMMC (8-bit buswidth)
- * mmc2 : SD card (4-bit buswidth)
- */
- if (err0)
- debug("SDMMC0 not configured\n");
- else
- err0 = s5p_mmc_init(0, 8);
-
- /* T-flash detect */
- s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf);
- s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP);
-
- /*
- * Check the T-flash detect pin
- * GPX3[4] T-flash detect pin
- */
- if (!s5p_gpio_get_value(&gpio2->x3, 4)) {
- err2 = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
- if (err2)
- debug("SDMMC2 not configured\n");
- else
- err2 = s5p_mmc_init(2, 4);
- }
-
- return err0 & err2;
-}
-
#ifdef CONFIG_USB_GADGET
static int s5pc210_phy_control(int on)
{
*/
#ifdef CONFIG_LCD
-static struct mipi_dsim_config dsim_config = {
- .e_interface = DSIM_VIDEO,
- .e_virtual_ch = DSIM_VIRTUAL_CH_0,
- .e_pixel_format = DSIM_24BPP_888,
- .e_burst_mode = DSIM_BURST_SYNC_EVENT,
- .e_no_data_lane = DSIM_DATA_LANE_4,
- .e_byte_clk = DSIM_PLL_OUT_DIV8,
- .hfp = 1,
-
- .p = 3,
- .m = 120,
- .s = 1,
-
- /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
- .pll_stable_time = 500,
-
- /* escape clk : 10MHz */
- .esc_clk = 20 * 1000000,
-
- /* stop state holding counter after bta change count 0 ~ 0xfff */
- .stop_holding_cnt = 0x7ff,
- /* bta timeout 0 ~ 0xff */
- .bta_timeout = 0xff,
- /* lp rx timeout 0 ~ 0xffff */
- .rx_timeout = 0xffff,
-};
-
-static struct exynos_platform_mipi_dsim dsim_platform_data = {
- .lcd_panel_info = NULL,
- .dsim_config = &dsim_config,
-};
-
-static struct mipi_dsim_lcd_device mipi_lcd_device = {
- .name = "s6e8ax0",
- .id = -1,
- .bus_id = 0,
- .platform_data = (void *)&dsim_platform_data,
-};
-
-static int mipi_power(void)
+int mipi_power(void)
{
struct pmic *p = pmic_get("MAX77686_PMIC");
s5p_gpio_set_value(&gpio1->f2, 1, 1);
}
-vidinfo_t panel_info = {
- .vl_freq = 60,
- .vl_col = 720,
- .vl_row = 1280,
- .vl_width = 720,
- .vl_height = 1280,
- .vl_clkp = CONFIG_SYS_HIGH,
- .vl_hsp = CONFIG_SYS_LOW,
- .vl_vsp = CONFIG_SYS_LOW,
- .vl_dp = CONFIG_SYS_LOW,
- .vl_bpix = 4, /* Bits per pixel, 2^4 = 16 */
-
- /* s6e8ax0 Panel infomation */
- .vl_hspw = 5,
- .vl_hbpd = 10,
- .vl_hfpd = 10,
-
- .vl_vspw = 2,
- .vl_vbpd = 1,
- .vl_vfpd = 13,
- .vl_cmd_allow_len = 0xf,
- .mipi_enabled = 1,
-
- .dual_lcd_enabled = 0,
-
- .init_delay = 0,
- .power_on_delay = 25,
- .reset_delay = 0,
- .interface_mode = FIMD_RGB_INTERFACE,
-};
-
-void init_panel_info(vidinfo_t *vid)
+void exynos_lcd_misc_init(vidinfo_t *vid)
{
- vid->logo_on = 1;
- vid->resolution = HD_RESOLUTION;
- vid->rgb_mode = MODE_RGB_P;
-
- vid->power_on_delay = 30;
-
- mipi_lcd_device.reverse_panel = 1;
-
#ifdef CONFIG_TIZEN
get_tizen_logo_info(vid);
#endif
-
- strcpy(dsim_platform_data.lcd_panel_name, mipi_lcd_device.name);
- dsim_platform_data.mipi_power = mipi_power;
- dsim_platform_data.phy_enable = set_mipi_phy_ctrl;
- dsim_platform_data.lcd_panel_info = (void *)vid;
- exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device);
-
+#ifdef CONFIG_S6E8AX0
s6e8ax0_init();
-
- exynos_set_dsim_platform_data(&dsim_platform_data);
-}
-#endif /* LCD */
-
-#ifdef CONFIG_MISC_INIT_R
-int misc_init_r(void)
-{
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
- set_board_info();
-#endif
-#ifdef CONFIG_LCD_MENU
- keys_init();
- check_boot_mode();
#endif
-#ifdef CONFIG_CMD_BMP
- if (panel_info.logo_on)
- draw_logo();
-#endif
- return 0;
}
-#endif
+#endif /* LCD */
#include <asm/gpio.h>
#include <asm/arch/adc.h>
#include <asm/arch/gpio.h>
-#include <asm/arch/mmc.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/watchdog.h>
-#include <libtizen.h>
#include <ld9040.h>
#include <power/pmic.h>
+#include <usb.h>
#include <usb/s3c_udc.h>
#include <asm/arch/cpu.h>
#include <power/max8998_pmic.h>
+#include <libtizen.h>
#include <samsung/misc.h>
+#include <usb_mass_storage.h>
DECLARE_GLOBAL_DATA_PTR;
static void init_pmic_lcd(void);
-int power_init_board(void)
+int exynos_power_init(void)
{
int ret;
return 0;
}
-int dram_init(void)
-{
- gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
- get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
-
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-}
-
static unsigned short get_adc_value(int channel)
{
struct s5p_adc *adc = (struct s5p_adc *)samsung_get_base_adc();
board_rev |= hwrev;
}
-#ifdef CONFIG_DISPLAY_BOARDINFO
-int checkboard(void)
-{
- puts("Board:\tUniversal C210\n");
- return 0;
-}
-#endif
-
-#ifdef CONFIG_GENERIC_MMC
-int board_mmc_init(bd_t *bis)
-{
- int err;
-
- switch (get_hwrev()) {
- case 0:
- /*
- * Set the low to enable LDO_EN
- * But when you use the test board for eMMC booting
- * you should set it HIGH since it removes the inverter
- */
- /* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */
- s5p_gpio_direction_output(&gpio1->e3, 6, 0);
- break;
- default:
- /*
- * Default reset state is High and there's no inverter
- * But set it as HIGH to ensure
- */
- /* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */
- s5p_gpio_direction_output(&gpio1->e1, 3, 1);
- break;
- }
-
- /*
- * MMC device init
- * mmc0 : eMMC (8-bit buswidth)
- * mmc2 : SD card (4-bit buswidth)
- */
- err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
- if (err)
- debug("SDMMC0 not configured\n");
- else
- err = s5p_mmc_init(0, 8);
-
- /* T-flash detect */
- s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf);
- s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP);
-
- /*
- * Check the T-flash detect pin
- * GPX3[4] T-flash detect pin
- */
- if (!s5p_gpio_get_value(&gpio2->x3, 4)) {
- err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
- if (err)
- debug("SDMMC2 not configured\n");
- else
- err = s5p_mmc_init(2, 4);
- }
-
- return err;
-
-}
-#endif
-
#ifdef CONFIG_USB_GADGET
static int s5pc210_phy_control(int on)
{
};
#endif
-int board_early_init_f(void)
+int board_usb_init(int index, enum usb_init_type init)
+{
+ debug("USB_udc_probe\n");
+ return s3c_udc_probe(&s5pc210_otg_data);
+}
+
+#ifdef CONFIG_USB_CABLE_CHECK
+int usb_cable_connected(void)
+{
+ return 0;
+}
+#endif
+
+int exynos_early_init_f(void)
{
wdt_stop();
spi_init();
}
+int mipi_power(void)
+{
+ return 0;
+}
+
void exynos_reset_lcd(void)
{
s5p_gpio_set_value(&gpio2->y4, 5, 1);
pmic_set_output(p, MAX8998_REG_ONOFF2, MAX8998_LDO7, LDO_ON);
}
-vidinfo_t panel_info = {
- .vl_freq = 60,
- .vl_col = 480,
- .vl_row = 800,
- .vl_width = 480,
- .vl_height = 800,
- .vl_clkp = CONFIG_SYS_HIGH,
- .vl_hsp = CONFIG_SYS_HIGH,
- .vl_vsp = CONFIG_SYS_HIGH,
- .vl_dp = CONFIG_SYS_HIGH,
-
- .vl_bpix = 4, /* Bits per pixel */
-
- /* LD9040 LCD Panel */
- .vl_hspw = 2,
- .vl_hbpd = 16,
- .vl_hfpd = 16,
-
- .vl_vspw = 2,
- .vl_vbpd = 8,
- .vl_vfpd = 8,
- .vl_cmd_allow_len = 0xf,
-
- .win_id = 0,
- .dual_lcd_enabled = 0,
-
- .init_delay = 0,
- .power_on_delay = 10000,
- .reset_delay = 10000,
- .interface_mode = FIMD_RGB_INTERFACE,
- .mipi_enabled = 0,
-};
-
void exynos_cfg_ldo(void)
{
ld9040_cfg_ldo();
ld9040_enable_ldo(onoff);
}
-void init_panel_info(vidinfo_t *vid)
-{
- vid->logo_on = 1;
- vid->resolution = HD_RESOLUTION;
- vid->rgb_mode = MODE_RGB_P;
-
-#ifdef CONFIG_TIZEN
- get_tizen_logo_info(vid);
-#endif
-
- /* for LD9040. */
- vid->pclk_name = 1; /* MPLL */
- vid->sclk_div = 1;
-
- setenv("lcdinfo", "lcd=ld9040");
-}
-
-int board_init(void)
+int exynos_init(void)
{
gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ switch (get_hwrev()) {
+ case 0:
+ /*
+ * Set the low to enable LDO_EN
+ * But when you use the test board for eMMC booting
+ * you should set it HIGH since it removes the inverter
+ */
+ /* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */
+ s5p_gpio_direction_output(&gpio1->e3, 6, 0);
+ break;
+ default:
+ /*
+ * Default reset state is High and there's no inverter
+ * But set it as HIGH to ensure
+ */
+ /* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */
+ s5p_gpio_direction_output(&gpio1->e1, 3, 1);
+ break;
+ }
#ifdef CONFIG_SOFT_SPI
soft_spi_init();
return 0;
}
-#ifdef CONFIG_MISC_INIT_R
-int misc_init_r(void)
+void exynos_lcd_misc_init(vidinfo_t *vid)
{
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
- set_board_info();
-#endif
-#ifdef CONFIG_LCD_MENU
- keys_init();
- check_boot_mode();
-#endif
-#ifdef CONFIG_CMD_BMP
- if (panel_info.logo_on)
- draw_logo();
+#ifdef CONFIG_TIZEN
+ get_tizen_logo_info(vid);
#endif
- return 0;
+
+ /* for LD9040. */
+ vid->pclk_name = 1; /* MPLL */
+ vid->sclk_div = 1;
+
+ setenv("lcdinfo", "lcd=ld9040");
}
-#endif
*/
#include <common.h>
-
+#include <cros_ec.h>
+#include <dm.h>
#include <os.h>
+#include <asm/u-boot-sandbox.h>
/*
* Pointer to initial global data area
*/
gd_t *gd;
+/* Add a simple GPIO device */
+U_BOOT_DEVICE(gpio_sandbox) = {
+ .name = "gpio_sandbox",
+};
+
void flush_cache(unsigned long start, unsigned long size)
{
}
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
return 0;
}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_VIDEO_SANDBOX_SDL
+ int ret;
+
+ ret = sandbox_lcd_sdl_early_init();
+ if (ret) {
+ puts("Could not init sandbox LCD emulation\n");
+ return ret;
+ }
+#endif
+
+ return 0;
+}
+#endif
+
+int arch_early_init_r(void)
+{
+#ifdef CONFIG_CROS_EC
+ if (cros_ec_board_init()) {
+ printf("%s: Failed to init EC\n", __func__);
+ return 0;
+ }
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ if (cros_ec_get_error()) {
+ /* Force console on */
+ gd->flags &= ~GD_FLG_SILENT;
+
+ printf("cros-ec communications failure %d\n",
+ cros_ec_get_error());
+ puts("\nPlease reset with Power+Refresh\n\n");
+ panic("Cannot init cros-ec device");
+ return -1;
+ }
+ return 0;
+}
+#endif
factoryset_setenv();
- /* Reset SMSC LAN9303 switch for default configuration */
- gpio_request(GPIO_LAN9303_NRST, "nRST");
- gpio_direction_output(GPIO_LAN9303_NRST, 0);
- /* assert active low reset for 200us */
- udelay(200);
- gpio_set_value(GPIO_LAN9303_NRST, 1);
-
/* Set rgmii mode and enable rmii clock to be sourced from chip */
writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
n += rv;
return n;
}
+
+static int do_switch_reset(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ /* Reset SMSC LAN9303 switch for default configuration */
+ gpio_request(GPIO_LAN9303_NRST, "nRST");
+ gpio_direction_output(GPIO_LAN9303_NRST, 0);
+ /* assert active low reset for 200us */
+ udelay(200);
+ gpio_set_value(GPIO_LAN9303_NRST, 1);
+
+ return 0;
+};
+
+U_BOOT_CMD(
+ switch_rst, CONFIG_SYS_MAXARGS, 1, do_switch_reset,
+ "Reset LAN9303 switch via its reset pin",
+ ""
+);
#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
+++ /dev/null
-#
-# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# This board is mostly used for debugging U-Boot in simulation (ISS).
-# The only peripheral which is used on this board is a serial port which
-# requires no initialization except those in "include/configs/arcangel4.h".
-# And now there's no specific initializations for this board.
-# So this Makefile is only required for satisfaction of U-Boot build system.
+++ /dev/null
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
# SPDX-License-Identifier: GPL-2.0+
#
-# FIX ME
-ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),)
-ccflags-y := -O2
-endif
-
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
The AM335x GP EVM ships with a 256MiB NAND available in most profiles. In
this example to program the NAND we assume that an SD card has been
inserted with the files to write in the first SD slot and that mtdparts
-have been configured correctly for the board. As a time saving measure we
-load MLO into memory in one location, copy it into the three locatations
-that the ROM checks for additional valid copies, then load U-Boot into
-memory. We then write that whole section of memory to NAND.
-
-U-Boot # mmc rescan
-U-Boot # env default -f -a
-U-Boot # nand erase.chip
-U-Boot # saveenv
-U-Boot # load mmc 0 81000000 MLO
-U-Boot # cp.b 81000000 81020000 20000
-U-Boot # cp.b 81000000 81040000 20000
-U-Boot # cp.b 81000000 81060000 20000
-U-Boot # load mmc 0 81080000 u-boot.img
-U-Boot # nand write 81000000 0 260000
-U-Boot # load mmc 0 ${loadaddr} uImage
-U-Boot # nand write ${loadaddr} kernel 500000
+have been configured correctly for the board. All images are first loaded
+into memory, then written to NAND.
+
+Step-1: Building u-boot for NAND boot
+ Set following CONFIGxx options for NAND device.
+ CONFIG_SYS_NAND_PAGE_SIZE number of main bytes in NAND page
+ CONFIG_SYS_NAND_OOBSIZE number of OOB bytes in NAND page
+ CONFIG_SYS_NAND_BLOCK_SIZE number of bytes in NAND erase-block
+ CONFIG_SYS_NAND_ECCPOS ECC map for NAND page
+ CONFIG_NAND_OMAP_ECCSCHEME (refer doc/README.nand)
+
+Step-2: Flashing NAND via MMC/SD
+ # select BOOTSEL to MMC/SD boot and boot from MMC/SD card
+ U-Boot # mmc rescan
+ # erase flash
+ U-Boot # nand erase.chip
+ U-Boot # env default -f -a
+ U-Boot # saveenv
+ # flash MLO. Redundant copies of MLO are kept for failsafe
+ U-Boot # load mmc 0 0x82000000 MLO
+ U-Boot # nand write 0x82000000 0x00000 0x20000
+ U-Boot # nand write 0x82000000 0x20000 0x20000
+ U-Boot # nand write 0x82000000 0x40000 0x20000
+ U-Boot # nand write 0x82000000 0x60000 0x20000
+ # flash u-boot.img
+ U-Boot # load mmc 0 0x82000000 u-boot.img
+ U-Boot # nand write 0x82000000 0x80000 0x60000
+ # flash kernel image
+ U-Boot # load mmc 0 0x82000000 uImage
+ U-Boot # nand write 0x82000000 ${nandsrcaddr} ${nandimgsize}
+ # flash filesystem image
+ U-Boot # load mmc 0 0x82000000 filesystem.img
+ U-Boot # nand write 0x82000000 ${loadaddress} 0x300000
+
+Step-3: Set BOOTSEL pin to select NAND boot, and POR the device.
+ The device should boot from images flashed on NAND device.
NOR
===
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/io.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#include <common.h>
#include <fsl_esdhc.h>
#include <ipu_pixfmt.h>
+++ /dev/null
-/config.tmp
obj-y += ml507.o
-include $(SRCTREE)/board/xilinx/ppc440-generic/Makefile
+include $(srctree)/board/xilinx/ppc440-generic/Makefile
+++ /dev/null
-config.tmp
+++ /dev/null
-/config.tmp
*/
#include <common.h>
+#include <fdtdec.h>
#include <netdev.h>
#include <zynqpl.h>
#include <asm/arch/hardware.h>
int dram_init(void)
{
+#ifdef CONFIG_OF_CONTROL
+ int node;
+ fdt_addr_t addr;
+ fdt_size_t size;
+ const void *blob = gd->fdt_blob;
+
+ node = fdt_node_offset_by_prop_value(blob, -1, "device_type",
+ "memory", 7);
+ if (node == -FDT_ERR_NOTFOUND) {
+ debug("ZYNQ DRAM: Can't get memory node\n");
+ return -1;
+ }
+ addr = fdtdec_get_addr_size(blob, node, "reg", &size);
+ if (addr == FDT_ADDR_T_NONE || size == 0) {
+ debug("ZYNQ DRAM: Can't get base address or size\n");
+ return -1;
+ }
+ gd->ram_size = size;
+#else
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
-
+#endif
zynq_ddrc_init();
return 0;
###########################################################################################################
Active aarch64 armv8 - armltd vexpress64 vexpress_aemv8a vexpress_aemv8a:ARM64 David Feng <fenghua@phytium.com.cn>
-Active arc arc700 - synopsys - arcangel4 - Alexey Brodkin <abrodkin@synopsys.com>
Active arc arc700 - synopsys - axs101 - Alexey Brodkin <abrodkin@synopsys.com>
-Active arc arc700 - synopsys arcangel4 arcangel4-be - Alexey Brodkin <abrodkin@synopsys.com>
+Active arc arc700 - synopsys <none> arcangel4 - Alexey Brodkin <abrodkin@synopsys.com>
+Active arc arc700 - synopsys <none> arcangel4-be - Alexey Brodkin <abrodkin@synopsys.com>
Active arm arm1136 - armltd integrator integratorcp_cm1136 integratorcp:CM1136 Linus Walleij <linus.walleij@linaro.org>
Active arm arm1136 mx31 - - imx31_phycore - -
Active arm arm1136 mx31 davedenx - qong - Wolfgang Denk <wd@denx.de>
Active arm armv7 - armltd vexpress vexpress_ca15_tc2 - -
Active arm armv7 - armltd vexpress vexpress_ca5x2 - Matt Waddel <matt.waddel@linaro.org>
Active arm armv7 - armltd vexpress vexpress_ca9x4 - Matt Waddel <matt.waddel@linaro.org>
+Active arm armv7 am33xx BuR kwb kwb kwb:SERIAL1,CONS_INDEX=1 Hannes Petermaier <hannes.petermaier@br-automation.com>
+Active arm armv7 am33xx BuR tseries tseries_mmc tseries:SERIAL1,CONS_INDEX=1,EMMC_BOOT Hannes Petermaier <hannes.petermaier@br-automation.com>
+Active arm armv7 am33xx BuR tseries tseries_nand tseries:SERIAL1,CONS_INDEX=1,NAND Hannes Petermaier <hannes.petermaier@br-automation.com>
+Active arm armv7 am33xx BuR tseries tseries_spi tseries:SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT Hannes Petermaier <hannes.petermaier@br-automation.com>
Active arm armv7 am33xx compulab cm_t335 cm_t335 - Igor Grinberg <grinberg@compulab.co.il>
Active arm armv7 am33xx isee igep0033 am335x_igep0033 - Enric Balletbo i Serra <eballetbo@iseebcn.com>
Active arm armv7 am33xx phytec pcm051 pcm051_rev1 pcm051:REV1 Lars Poeschel <poeschel@lemonage.de>
Active arm armv7 am33xx siemens pxm2 pxm2 - Roger Meier <r.meier@siemens.com>
Active arm armv7 am33xx siemens rut rut - Roger Meier <r.meier@siemens.com>
Active arm armv7 am33xx silica pengwyn pengwyn - Lothar Felten <lothar.felten@gmail.com>
-Active arm armv7 am33xx BuR tseries tseries_nand tseries:SERIAL1,CONS_INDEX=1,NAND Hannes Petermaier <hannes.petermaier@br-automation.com>
-Active arm armv7 am33xx BuR tseries tseries_mmc tseries:SERIAL1,CONS_INDEX=1,EMMC_BOOT Hannes Petermaier <hannes.petermaier@br-automation.com>
-Active arm armv7 am33xx BuR tseries tseries_spi tseries:SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT Hannes Petermaier <hannes.petermaier@br-automation.com>
-Active arm armv7 am33xx BuR kwb kwb kwb:SERIAL1,CONS_INDEX=1 Hannes Petermaier <hannes.petermaier@br-automation.com>
Active arm armv7 am33xx ti am335x am335x_boneblack am335x_evm:SERIAL1,CONS_INDEX=1,EMMC_BOOT Tom Rini <trini@ti.com>
Active arm armv7 am33xx ti am335x am335x_evm am335x_evm:SERIAL1,CONS_INDEX=1,NAND Tom Rini <trini@ti.com>
Active arm armv7 am33xx ti am335x am335x_evm_nor am335x_evm:SERIAL1,CONS_INDEX=1,NAND,NOR Tom Rini <trini@ti.com>
Active arm armv7 am33xx ti am43xx am43xx_evm am43xx_evm:SERIAL1,CONS_INDEX=1 Lokesh Vutla <lokeshvutla@ti.com>
Active arm armv7 am33xx ti ti814x ti814x_evm - Matt Porter <matt.porter@linaro.org>
Active arm armv7 am33xx ti ti816x ti816x_evm - -
+Active arm armv7 at91 atmel sama5d3_xplained sama5d3_xplained_mmc sama5d3_xplained:SAMA5D3,SYS_USE_MMC Bo Shen <voice.shen@atmel.com>
+Active arm armv7 at91 atmel sama5d3_xplained sama5d3_xplained_nandflash sama5d3_xplained:SAMA5D3,SYS_USE_NANDFLASH Bo Shen <voice.shen@atmel.com>
Active arm armv7 at91 atmel sama5d3xek sama5d3xek_mmc sama5d3xek:SAMA5D3,SYS_USE_MMC Bo Shen <voice.shen@atmel.com>
Active arm armv7 at91 atmel sama5d3xek sama5d3xek_nandflash sama5d3xek:SAMA5D3,SYS_USE_NANDFLASH Bo Shen <voice.shen@atmel.com>
Active arm armv7 at91 atmel sama5d3xek sama5d3xek_spiflash sama5d3xek:SAMA5D3,SYS_USE_SERIALFLASH Bo Shen <voice.shen@atmel.com>
Active avr32 at32ap at32ap700x mimc - mimc200 - Mark Jackson <mpfj@mimc.co.uk>
Active avr32 at32ap at32ap700x miromico - hammerhead - Julien May <julien.may@miromico.ch>:Alex Raimondi <alex.raimondi@miromico.ch>
Active blackfin blackfin - - - bct-brettl2 - Peter Meerwald <devel@bct-electronic.com>
-Active blackfin blackfin - - - bf506f-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
-Active blackfin blackfin - - - bf518f-ezbrd - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
+Active blackfin blackfin - - - bf506f-ezkit - Sonic Zhang <sonic.adi@gmail.com>
+Active blackfin blackfin - - - bf518f-ezbrd - Sonic Zhang <sonic.adi@gmail.com>
Active blackfin blackfin - - - bf525-ucr2 - Haitao Zhang <hzhang@ucrobotics.com>:Chong Huang <chuang@ucrobotics.com>
-Active blackfin blackfin - - - bf526-ezbrd - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
-Active blackfin blackfin - - - bf527-ad7160-eval - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
-Active blackfin blackfin - - - bf527-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
-Active blackfin blackfin - - - bf527-sdp - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
-Active blackfin blackfin - - - bf533-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
-Active blackfin blackfin - - - bf533-stamp - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
+Active blackfin blackfin - - - bf526-ezbrd - Sonic Zhang <sonic.adi@gmail.com>
+Active blackfin blackfin - - - bf527-ad7160-eval - Sonic Zhang <sonic.adi@gmail.com>
+Active blackfin blackfin - - - bf527-ezkit - Sonic Zhang <sonic.adi@gmail.com>
+Active blackfin blackfin - - - bf527-sdp - Sonic Zhang <sonic.adi@gmail.com>
+Active blackfin blackfin - - - bf533-ezkit - Sonic Zhang <sonic.adi@gmail.com>
+Active blackfin blackfin - - - bf533-stamp - Sonic Zhang <sonic.adi@gmail.com>
Active blackfin blackfin - - - bf537-minotaur - Martin Strubel <strubel@section5.ch>
-Active blackfin blackfin - - - bf537-pnav - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
+Active blackfin blackfin - - - bf537-pnav - Sonic Zhang <sonic.adi@gmail.com>
Active blackfin blackfin - - - bf537-srv1 - Martin Strubel <strubel@section5.ch>
-Active blackfin blackfin - - - bf537-stamp - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
-Active blackfin blackfin - - - bf538f-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
-Active blackfin blackfin - - - bf548-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
+Active blackfin blackfin - - - bf537-stamp - Sonic Zhang <sonic.adi@gmail.com>
+Active blackfin blackfin - - - bf538f-ezkit - Sonic Zhang <sonic.adi@gmail.com>
+Active blackfin blackfin - - - bf548-ezkit - Sonic Zhang <sonic.adi@gmail.com>
Active blackfin blackfin - - - bf561-acvilon - Anton Shurpin <shurpin.aa@niistt.ru>:Valentin Yakovenkov <yakovenkov@niistt.ru>
-Active blackfin blackfin - - - bf561-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
-Active blackfin blackfin - - - bf609-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
+Active blackfin blackfin - - - bf561-ezkit - Sonic Zhang <sonic.adi@gmail.com>
+Active blackfin blackfin - - - bf609-ezkit - Sonic Zhang <sonic.adi@gmail.com>
Active blackfin blackfin - - - blackstamp - Wojtek Skulski <skulski@pas.rochester.edu>:Wojtek Skulski <info@skutek.com>:Benjamin Matthews <mben12@gmail.com>
Active blackfin blackfin - - - blackvme - Wojtek Skulski <skulski@pas.rochester.edu>:Wojtek Skulski <info@skutek.com>:Benjamin Matthews <mben12@gmail.com>
Active blackfin blackfin - - - br4 - Dimitar Penev <dpn@switchfin.org>
-Active blackfin blackfin - - - cm-bf527 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-Active blackfin blackfin - - - cm-bf533 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-Active blackfin blackfin - - - cm-bf537e - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-Active blackfin blackfin - - - cm-bf537u - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-Active blackfin blackfin - - - cm-bf548 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-Active blackfin blackfin - - - cm-bf561 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
Active blackfin blackfin - - - dnp5370 - M.Hasewinkel (MHA) <info@ssv-embedded.de>
Active blackfin blackfin - - - ibf-dsp561 - I-SYST Micromodule <support@i-syst.com>
Active blackfin blackfin - - - ip04 - Brent Kandetzki <brentk@teleco.com>
Active blackfin blackfin - - - pr1 - Dimitar Penev <dpn@switchfin.org>
-Active blackfin blackfin - - - tcm-bf518 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-Active blackfin blackfin - - - tcm-bf537 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-Active blackfin blackfin - - bf527-ezkit bf527-ezkit-v2 bf527-ezkit:BF527_EZKIT_REV_2_1 Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
+Active blackfin blackfin - - bf527-ezkit bf527-ezkit-v2 bf527-ezkit:BF527_EZKIT_REV_2_1 Sonic Zhang <sonic.adi@gmail.com>
Active m68k mcf5227x - freescale m52277evb M52277EVB M52277EVB:SYS_SPANSION_BOOT,SYS_TEXT_BASE=0x00000000 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Active m68k mcf5227x - freescale m52277evb M52277EVB_stmicro M52277EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x43E00000 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Active m68k mcf523x - freescale m5235evb M5235EVB M5235EVB:SYS_TEXT_BASE=0xFFE00000 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Active m68k mcf523x - freescale m5235evb M5235EVB_Flash32 M5235EVB:NORFLASH_PS32BIT,SYS_TEXT_BASE=0xFFC00000 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
-Active m68k mcf52x2 - - - idmr - -
Active m68k mcf52x2 - - cobra5272 cobra5272 - -
Active m68k mcf52x2 - BuS eb_cpu5282 eb_cpu5282 eb_cpu5282:SYS_TEXT_BASE=0xFF000000,SYS_MONITOR_BASE=0xFF000400 Jens Scharsig <esw@bus-elektronik.de>
Active m68k mcf52x2 - BuS eb_cpu5282 eb_cpu5282_internal eb_cpu5282:SYS_TEXT_BASE=0xF0000000,SYS_MONITOR_BASE=0xF0000418 Jens Scharsig <esw@bus-elektronik.de>
Active m68k mcf52x2 - freescale m5249evb M5249EVB - -
Active m68k mcf52x2 - freescale m5253demo M5253DEMO - TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Active m68k mcf52x2 - freescale m5253evbe M5253EVBE - Hayden Fraser <Hayden.Fraser@freescale.com>
-Active m68k mcf52x2 - freescale m5271evb M5271EVB - -
Active m68k mcf52x2 - freescale m5272c3 M5272C3 - -
Active m68k mcf52x2 - freescale m5275evb M5275EVB - -
Active m68k mcf52x2 - freescale m5282evb M5282EVB - -
Active microblaze microblaze - xilinx microblaze-generic microblaze-generic - Michal Simek <monstr@monstr.eu>
Active mips mips32 - - qemu-mips qemu_mips qemu-mips:SYS_BIG_ENDIAN Vlad Lungu <vlad.lungu@windriver.com>
Active mips mips32 - - qemu-mips qemu_mipsel qemu-mips:SYS_LITTLE_ENDIAN -
-Active mips mips32 - imgtec malta malta malta:
MIPS32,SYS_BIG_ENDIAN Paul Burton <paul.burton@imgtec.com>
-Active mips mips32 - imgtec malta maltael malta:
MIPS32,SYS_LITTLE_ENDIAN Paul Burton <paul.burton@imgtec.com>
+Active mips mips32 - imgtec malta malta malta:
SYS_BIG_ENDIAN Paul Burton <paul.burton@imgtec.com>
+Active mips mips32 - imgtec malta maltael malta:
SYS_LITTLE_ENDIAN Paul Burton <paul.burton@imgtec.com>
Active mips mips32 - micronas vct vct_platinum vct:VCT_PLATINUM -
Active mips mips32 - micronas vct vct_platinum_onenand vct:VCT_PLATINUM,VCT_ONENAND -
Active mips mips32 - micronas vct vct_platinum_onenand_small vct:VCT_PLATINUM,VCT_ONENAND,VCT_SMALL_IMAGE -
Active powerpc mpc5xxx - manroland - hmi1001 - -
Active powerpc mpc5xxx - manroland - mucmc52 - Heiko Schocher <hs@denx.de>
Active powerpc mpc5xxx - manroland - uc101 - Heiko Schocher <hs@denx.de>
-Active powerpc mpc5xxx - matrix_vision mvbc_p MVBC_P MVBC_P:MVBC_P Andre Schwarz <andre.schwarz@matrix-vision.de>
-Active powerpc mpc5xxx - matrix_vision mvsmr MVSMR - Andre Schwarz <andre.schwarz@matrix-vision.de>
Active powerpc mpc5xxx - phytec pcm030 pcm030 - Jon Smirl <jonsmirl@gmail.com>
Active powerpc mpc5xxx - phytec pcm030 pcm030_LOWBOOT pcm030:SYS_TEXT_BASE=0xFF000000 Jon Smirl <jonsmirl@gmail.com>
Active powerpc mpc5xxx - tqc tqm5200 aev - -
Active powerpc mpc824x - - cpc45 CPC45_ROMBOOT CPC45:BOOT_ROM Josef Wagner <Wagner@Microsys.de>
Active powerpc mpc824x - - cu824 CU824 - Wolfgang Denk <wd@denx.de>
Active powerpc mpc824x - - eXalion eXalion - Torsten Demke <torsten.demke@fci.com>
-Active powerpc mpc824x - - hidden_dragon HIDDEN_DRAGON - Yusdi Santoso <yusdi_santoso@adaptec.com>
Active powerpc mpc824x - - musenki MUSENKI - Jim Thompson <jim@musenki.com>
Active powerpc mpc824x - - mvblue MVBLUE - -
Active powerpc mpc824x - - sandpoint Sandpoint8240 - Wolfgang Denk <wd@denx.de>
Active powerpc mpc824x - - sandpoint Sandpoint8245 - Jim Thompson <jim@musenki.com>
-Active powerpc mpc824x - etin - debris - Sangmoon Kim <dogoil@etinsys.com>
-Active powerpc mpc824x - etin - kvme080 - Sangmoon Kim <dogoil@etinsys.com>
Active powerpc mpc8260 - - - atc - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8260 - - - ep8260 - Frank Panno <fpanno@delphintech.com>
Active powerpc mpc8260 - - - ep82xxm - -
Active powerpc mpc8260 - - cpu86 CPU86_ROMBOOT CPU86:BOOT_ROM Wolfgang Denk <wd@denx.de>
Active powerpc mpc8260 - - cpu87 CPU87 - -
Active powerpc mpc8260 - - cpu87 CPU87_ROMBOOT CPU87:BOOT_ROM -
-Active powerpc mpc8260 - - ep8248 ep8248 - Yuli Barcohen <yuli@arabellasw.com>
Active powerpc mpc8260 - - ids8247 IDS8247 - Heiko Schocher <hs@denx.de>
Active powerpc mpc8260 - - iphase4539 IPHASE4539 - Wolfgang Grandegger <wg@denx.de>
-Active powerpc mpc8260 - - ispan ISPAN - Yuli Barcohen <yuli@arabellasw.com>
-Active powerpc mpc8260 - - ispan ISPAN_REVB ISPAN:SYS_REV_B Yuli Barcohen <yuli@arabellasw.com>
Active powerpc mpc8260 - - muas3001 muas3001 - Heiko Schocher <hs@denx.de>
Active powerpc mpc8260 - - muas3001 muas3001_dev muas3001:MUAS_DEV_BOARD Heiko Schocher <hs@denx.de>
Active powerpc mpc8260 - - pm826 PM825 PM826:PCI,SYS_TEXT_BASE=0xFF000000 Wolfgang Denk <wd@denx.de>
Active powerpc mpc8260 - - pm828 PM828_PCI PM828:PCI -
Active powerpc mpc8260 - - pm828 PM828_ROMBOOT PM828:BOOT_ROM,SYS_TEXT_BASE=0xFF800000 -
Active powerpc mpc8260 - - pm828 PM828_ROMBOOT_PCI PM828:PCI,BOOT_ROM,SYS_TEXT_BASE=0xFF800000 -
-Active powerpc mpc8260 - - rattler Rattler - Yuli Barcohen <yuli@arabellasw.com>
-Active powerpc mpc8260 - - rattler Rattler8248 Rattler:MPC8248 Yuli Barcohen <yuli@arabellasw.com>
-Active powerpc mpc8260 - - zpc1900 ZPC1900 - Yuli Barcohen <yuli@arabellasw.com>
-Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS Yuli Barcohen <yuli@arabellasw.com>
-Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000 Yuli Barcohen <yuli@arabellasw.com>
-Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
-Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000 Yuli Barcohen <yuli@arabellasw.com>
-Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
-Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
-Active powerpc mpc8260 - freescale mpc8260ads MPC8272ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS Yuli Barcohen <yuli@arabellasw.com>
-Active powerpc mpc8260 - freescale mpc8260ads MPC8272ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
-Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen <yuli@arabellasw.com>
-Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen <yuli@arabellasw.com>
-Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
-Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen <yuli@arabellasw.com>
-Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen <yuli@arabellasw.com>
-Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
-Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
-Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
Active powerpc mpc8260 - freescale mpc8266ads MPC8266ADS - Rune Torgersen <runet@innovsys.com>
Active powerpc mpc8260 - funkwerk vovpn-gw VoVPN-GW_66MHz VoVPN-GW:CLKIN_66MHz -
Active powerpc mpc8260 - keymile km82xx mgcoge km82xx:MGCOGE Holger Brunck <holger.brunck@keymile.com>
Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_HOST_33 MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_33M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com>
Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_HOST_66 MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_66M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com>
Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_SLAVE MPC8360EMDS:CLKIN_66MHZ,PCI,PCISLAVE Dave Liu <daveliu@freescale.com>
-Active powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK - Anton Vorontsov <avorontsov@ru.mvista.com>
-Active powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK_33 MPC8360ERDK:CLKIN_33MHZ Anton Vorontsov <avorontsov@ru.mvista.com>
Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS - Dave Liu <daveliu@freescale.com>
Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS_HOST MPC837XEMDS:PCI Dave Liu <daveliu@freescale.com>
Active powerpc mpc83xx - freescale mpc837xerdb MPC837XERDB - Joe D'Abbraccio <ljd015@freescale.com>
Active powerpc mpc83xx - keymile km83xx suvd3 suvd3:SUVD3 Holger Brunck <holger.brunck@keymile.com>
Active powerpc mpc83xx - keymile km83xx tuge1 tuxx1:TUGE1 Holger Brunck <holger.brunck@keymile.com>
Active powerpc mpc83xx - keymile km83xx tuxx1 tuxx1:TUXX1 Holger Brunck <holger.brunck@keymile.com>
-Active powerpc mpc83xx - matrix_vision mergerbox MERGERBOX - Andre Schwarz <andre.schwarz@matrix-vision.de>
-Active powerpc mpc83xx - matrix_vision mvblm7 MVBLM7 - Andre Schwarz <andre.schwarz@matrix-vision.de>
Active powerpc mpc83xx - sheldon simpc8313 SIMPC8313_LP SIMPC8313:NAND_LP Ron Madrid <info@sheldoninst.com>
Active powerpc mpc83xx - sheldon simpc8313 SIMPC8313_SP SIMPC8313:NAND_SP Ron Madrid <info@sheldoninst.com>
Active powerpc mpc83xx - tqc tqm834x TQM834x - -
Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Poonam Aggrwal <poonam.aggrwal@freescale.com>
Active powerpc mpc85xx - freescale t104xrdb T1040RDB T1040RDB:PPC_T1040 Poonam Aggrwal <poonam.aggrwal@freescale.com>
Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T1042RDB_PI:PPC_T1042 Poonam Aggrwal <poonam.aggrwal@freescale.com>
-Active powerpc mpc85xx - freescale t208xqds T2080QDS T208xQDS:PPC_T2080
-Active powerpc mpc85xx - freescale t208xqds T2080QDS_SDCARD T208xQDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000
-Active powerpc mpc85xx - freescale t208xqds T2080QDS_SPIFLASH T208xQDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000
-Active powerpc mpc85xx - freescale t208xqds T2080QDS_NAND T208xQDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000
-Active powerpc mpc85xx - freescale t208xqds T2080QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000
-Active powerpc mpc85xx - freescale t208xqds T2081QDS T208xQDS:PPC_T2081
-Active powerpc mpc85xx - freescale t208xqds T2081QDS_SDCARD T208xQDS:PPC_T2081,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000
-Active powerpc mpc85xx - freescale t208xqds T2081QDS_SPIFLASH T208xQDS:PPC_T2081,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000
-Active powerpc mpc85xx - freescale t208xqds T2081QDS_NAND T208xQDS:PPC_T2081,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000
-Active powerpc mpc85xx - freescale t208xqds T2081QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000
+Active powerpc mpc85xx - freescale t208xqds T2080QDS T208xQDS:PPC_T2080 -
+Active powerpc mpc85xx - freescale t208xqds T2080QDS_NAND T208xQDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale t208xqds T2080QDS_SDCARD T208xQDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale t208xqds T2080QDS_SPIFLASH T208xQDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale t208xqds T2080QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale t208xqds T2081QDS T208xQDS:PPC_T2081 -
+Active powerpc mpc85xx - freescale t208xqds T2081QDS_NAND T208xQDS:PPC_T2081,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale t208xqds T2081QDS_SDCARD T208xQDS:PPC_T2081,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale t208xqds T2081QDS_SPIFLASH T208xQDS:PPC_T2081,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale t208xqds T2081QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale t208xrdb T2080RDB T208xRDB:PPC_T2080 -
+Active powerpc mpc85xx - freescale t208xrdb T2080RDB_NAND T208xRDB:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SDCARD T208xRDB:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SPIFLASH T208xRDB:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SRIO_PCIE_BOOT T208xRDB:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale t4qds T4160QDS T4240QDS:PPC_T4160 -
Active powerpc mpc85xx - freescale t4qds T4160QDS_SDCARD T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale t4qds T4160QDS_SPIFLASH T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc8xx - - - spc1920 - -
Active powerpc mpc8xx - - - svm_sc8xx - John Zhan <zhanz@sinovee.com>
Active powerpc mpc8xx - - - v37 - -
-Active powerpc mpc8xx - - adder Adder - Yuli Barcohen <yuli@arabellasw.com>
-Active powerpc mpc8xx - - adder AdderII Adder:MPC852T Yuli Barcohen <yuli@arabellasw.com>
Active powerpc mpc8xx - - cogent cogent_mpc8xx - Murray Jensen <Murray.Jensen@csiro.au>
Active powerpc mpc8xx - - esteem192e ESTEEM192E - Conn Clark <clark@esteem.com>
Active powerpc mpc8xx - - fads MPC86xADS - -
Active powerpc ppc4xx - - w7o W7OLMG - Erik Theisen <etheisen@mindspring.com>
Active powerpc ppc4xx - amcc - acadia - Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc - bamboo - Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc - bluestone - Tirumala Marri <tmarri@apm.com>
Active powerpc ppc4xx - amcc - bubinga - -
Active powerpc ppc4xx - amcc - ebony - Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc - katmai - Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc - taihu - John Otken <jotken@softadvances.com>
Active powerpc ppc4xx - amcc - taishan - Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc - yucca - -
-Active powerpc ppc4xx - amcc acadia acadia_nand acadia:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc bamboo bamboo_nand bamboo:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc canyonlands arches canyonlands:ARCHES Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc canyonlands canyonlands canyonlands:CANYONLANDS Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc canyonlands canyonlands_nand canyonlands:CANYONLANDS,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc canyonlands glacier canyonlands:GLACIER Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc canyonlands glacier_nand canyonlands:GLACIER,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc kilauea haleakala kilauea:HALEAKALA Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc kilauea haleakala_nand kilauea:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc kilauea kilauea kilauea:KILAUEA Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc kilauea kilauea_nand kilauea:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc sequoia rainier sequoia:RAINIER Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc sequoia rainier_nand sequoia:RAINIER,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc sequoia rainier_ramboot sequoia:RAINIER,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc sequoia sequoia sequoia:SEQUOIA Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc sequoia sequoia_nand sequoia:SEQUOIA,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc sequoia sequoia_ramboot sequoia:SEQUOIA,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc walnut sycamore walnut Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc walnut walnut - Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - avnet fx12mm fx12mm_flash fx12mm:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc405-generic/init.o Georg Schardt <schardt@team-ctech.de>
Active powerpc ppc4xx - avnet v5fx30teval v5fx30teval v5fx30teval:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda@uam.es>
Active powerpc ppc4xx - avnet v5fx30teval v5fx30teval_flash v5fx30teval:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda@uam.es>
-Active powerpc ppc4xx - cray L1 CRAYL1 - David Updegraff <dave@cray.com>
Active powerpc ppc4xx - dave PPChameleonEVB CATcenter CATcenter:PPCHAMELEON_MODULE_MODEL=1 -
Active powerpc ppc4xx - dave PPChameleonEVB CATcenter_25 CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25 -
Active powerpc ppc4xx - dave PPChameleonEVB CATcenter_33 CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33 -
Active powerpc ppc4xx - mpl pip405 PIP405 - Denis Peter <d.peter@mpl.ch>
Active powerpc ppc4xx - prodrive - alpr - Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - prodrive - p3p440 - Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - sandburst karef KAREF - Travis Sawyer (travis.sawyer@sandburst.com>
-Active powerpc ppc4xx - sandburst metrobox METROBOX - Travis Sawyer (travis.sawyer@sandburst.com>
Active powerpc ppc4xx - xes - xpedite1000 - Peter Tyser <ptyser@xes-inc.com>
Active powerpc ppc4xx - xilinx ml507 ml507 ml507:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda@uam.es>
Active powerpc ppc4xx - xilinx ml507 ml507_flash ml507:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda@uam.es>
Active sparc leon3 - gaisler - gr_xc3s_1500 - -
Active sparc leon3 - gaisler - grsim - -
Active x86 x86 coreboot chromebook-x86 coreboot coreboot-x86 coreboot:SYS_TEXT_BASE=0x01110000 -
+# The following were moved to "Orphan" in March, 2014
+Orphan blackfin blackfin - - - cm-bf527 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Orphan blackfin blackfin - - - cm-bf533 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Orphan blackfin blackfin - - - cm-bf537e - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Orphan blackfin blackfin - - - cm-bf537u - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Orphan blackfin blackfin - - - cm-bf548 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Orphan blackfin blackfin - - - cm-bf561 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Orphan blackfin blackfin - - - tcm-bf518 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Orphan blackfin blackfin - - - tcm-bf537 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Orphan powerpc mpc5xxx - matrix_vision mvbc_p MVBC_P MVBC_P:MVBC_P Andre Schwarz <andre.schwarz@matrix-vision.de>
+Orphan powerpc mpc5xxx - matrix_vision mvsmr MVSMR - Andre Schwarz <andre.schwarz@matrix-vision.de>
+Orphan powerpc mpc824x - - hidden_dragon HIDDEN_DRAGON - Yusdi Santoso <yusdi_santoso@adaptec.com>
+Orphan powerpc mpc824x - etin - debris - Sangmoon Kim <dogoil@etinsys.com>
+Orphan powerpc mpc824x - etin - kvme080 - Sangmoon Kim <dogoil@etinsys.com>
+Orphan powerpc mpc8260 - - ep8248 ep8248 - Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - - ispan ISPAN - Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - - ispan ISPAN_REVB ISPAN:SYS_REV_B Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - - rattler Rattler - Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - - rattler Rattler8248 Rattler:MPC8248 Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - - zpc1900 ZPC1900 - Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000 Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000 Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - freescale mpc8260ads MPC8272ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - freescale mpc8260ads MPC8272ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK - Anton Vorontsov <avorontsov@ru.mvista.com>
+Orphan powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK_33 MPC8360ERDK:CLKIN_33MHZ Anton Vorontsov <avorontsov@ru.mvista.com>
+Orphan powerpc mpc83xx - matrix_vision mergerbox MERGERBOX - Andre Schwarz <andre.schwarz@matrix-vision.de>
+Orphan powerpc mpc83xx - matrix_vision mvblm7 MVBLM7 - Andre Schwarz <andre.schwarz@matrix-vision.de>
+Orphan powerpc mpc8xx - - adder Adder - Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc mpc8xx - - adder AdderII Adder:MPC852T Yuli Barcohen <yuli@arabellasw.com>
+Orphan powerpc ppc4xx - amcc - bluestone - Tirumala Marri <tmarri@apm.com>
+Orphan powerpc ppc4xx - cray L1 CRAYL1 - David Updegraff <dave@cray.com>
+Orphan powerpc ppc4xx - sandburst karef KAREF - Travis Sawyer <travis.sawyer@sandburst.com>
+Orphan powerpc ppc4xx - sandburst metrobox METROBOX - Travis Sawyer <travis.sawyer@sandburst.com>
+# The following were move to "Orphan" in September, 2013
Orphan arm arm1136 mx31 - imx31_phycore imx31_phycore_eet imx31_phycore:IMX31_PHYCORE_EET (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Orphan arm arm1136 mx31 freescale - mx31ads - (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Orphan arm pxa - - - lubbock - (dead address) Kyle Harris <kharris@nexus-tech.net>
obj-$(CONFIG_CMD_CPLBINFO) += cmd_cplbinfo.o
obj-$(CONFIG_DATAFLASH_MMC_SELECT) += cmd_dataflash_mmc_mux.o
obj-$(CONFIG_CMD_DATE) += cmd_date.o
+obj-$(CONFIG_CMD_DEMO) += cmd_demo.o
obj-$(CONFIG_CMD_SOUND) += cmd_sound.o
ifdef CONFIG_4xx
obj-$(CONFIG_CMD_SETGETDCR) += cmd_dcr.o
obj-$(CONFIG_HWCONFIG) += hwconfig.o
obj-$(CONFIG_BOUNCE_BUFFER) += bouncebuf.o
obj-y += console.o
+obj-$(CONFIG_CROS_EC) += cros_ec.o
obj-y += dlmalloc.o
obj-y += image.o
obj-$(CONFIG_OF_LIBFDT) += image-fdt.o
#ifdef CONFIG_OF_HOSTFILE
-#define CHECK(x) err = (x); if (err) goto failed;
-
-/* Create an empty device tree blob */
-static int make_empty_fdt(void *fdt)
-{
- int err;
-
- CHECK(fdt_create(fdt, 256));
- CHECK(fdt_finish_reservemap(fdt));
- CHECK(fdt_begin_node(fdt, ""));
- CHECK(fdt_end_node(fdt));
- CHECK(fdt_finish(fdt));
-
- return 0;
-failed:
- printf("Unable to create empty FDT: %s\n", fdt_strerror(err));
- return -EACCES;
-}
-
static int read_fdt_from_file(void)
{
struct sandbox_state *state = state_get_current();
+ const char *fname = state->fdt_fname;
void *blob;
- int size;
+ ssize_t size;
int err;
+ int fd;
blob = map_sysmem(CONFIG_SYS_FDT_LOAD_ADDR, 0);
if (!state->fdt_fname) {
- err = make_empty_fdt(blob);
+ err = fdt_create_empty_tree(blob, 256);
if (!err)
goto done;
- return err;
+ printf("Unable to create empty FDT: %s\n", fdt_strerror(err));
+ return -EINVAL;
+ }
+
+ size = os_get_filesize(fname);
+ if (size < 0) {
+ printf("Failed to file FDT file '%s'\n", fname);
+ return -ENOENT;
+ }
+ fd = os_open(fname, OS_O_RDONLY);
+ if (fd < 0) {
+ printf("Failed to open FDT file '%s'\n", fname);
+ return -EACCES;
}
- err = fs_set_blk_dev("host", NULL, FS_TYPE_SANDBOX);
- if (err)
- return err;
- size = fs_read(state->fdt_fname, CONFIG_SYS_FDT_LOAD_ADDR, 0, 0);
- if (size < 0)
+ if (os_read(fd, blob, size) != size) {
+ os_close(fd);
return -EIO;
+ }
+ os_close(fd);
done:
gd->fdt_blob = blob;
bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
#endif
-#if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \
+#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260) || defined(CONFIG_5xx) || \
defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
#endif
#endif
display_options, /* say that we are here */
display_text_info, /* show debugging info if required */
-#if defined(CONFIG_8260)
+#if defined(CONFIG_MPC8260)
prt_8260_rsr,
prt_8260_clks,
-#endif /* CONFIG_8260 */
+#endif /* CONFIG_MPC8260 */
#if defined(CONFIG_MPC83xx)
prt_83xx_rsr,
#endif
#ifdef CONFIG_HAS_DATAFLASH
#include <dataflash.h>
#endif
+#include <dm.h>
#include <environment.h>
#include <fdtdec.h>
#if defined(CONFIG_CMD_IDE)
#ifdef CONFIG_X86
#include <asm/init_helpers.h>
#endif
+#include <dm/root.h>
#include <linux/compiler.h>
+#include <linux/err.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
+#ifdef CONFIG_DM
+static int initr_dm(void)
+{
+ int ret;
+
+ ret = dm_init();
+ if (ret) {
+ debug("dm_init() failed: %d\n", ret);
+ return ret;
+ }
+ ret = dm_scan_platdata();
+ if (ret) {
+ debug("dm_scan_platdata() failed: %d\n", ret);
+ return ret;
+ }
+#ifdef CONFIG_OF_CONTROL
+ ret = dm_scan_fdt(gd->fdt_blob);
+ if (ret) {
+ debug("dm_scan_fdt() failed: %d\n", ret);
+ return ret;
+ }
+#endif
+
+ return 0;
+}
+#endif
+
__weak int power_init_board(void)
{
return 0;
initr_barrier,
initr_malloc,
bootstage_relocate,
+#ifdef CONFIG_DM
+ initr_dm,
+#endif
#ifdef CONFIG_ARCH_EARLY_INIT_R
arch_early_init_r,
#endif
print_num("sramstart", bd->bi_sramstart);
print_num("sramsize", bd->bi_sramsize);
#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || \
- defined(CONFIG_8260) || defined(CONFIG_E500)
+ defined(CONFIG_MPC8260) || defined(CONFIG_E500)
print_num("immr_base", bd->bi_immr_base);
#endif
print_num("bootflags", bd->bi_bootflags);
--- /dev/null
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm-demo.h>
+#include <asm/io.h>
+
+struct device *demo_dev;
+
+static int do_demo_hello(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ int ch = 0;
+
+ if (argc)
+ ch = *argv[0];
+
+ return demo_hello(demo_dev, ch);
+}
+
+static int do_demo_status(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ int status;
+ int ret;
+
+ ret = demo_status(demo_dev, &status);
+ if (ret)
+ return ret;
+
+ printf("Status: %d\n", status);
+
+ return 0;
+}
+
+int do_demo_list(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ struct device *dev;
+ int i, ret;
+
+ puts("Demo uclass entries:\n");
+
+ for (i = 0, ret = uclass_first_device(UCLASS_DEMO, &dev);
+ dev;
+ ret = uclass_next_device(&dev)) {
+ printf("entry %d - instance %08x, ops %08x, platdata %08x\n",
+ i++, map_to_sysmem(dev),
+ map_to_sysmem(dev->driver->ops),
+ map_to_sysmem(dev_get_platdata(dev)));
+ }
+
+ return cmd_process_error(cmdtp, ret);
+}
+
+static cmd_tbl_t demo_commands[] = {
+ U_BOOT_CMD_MKENT(list, 0, 1, do_demo_list, "", ""),
+ U_BOOT_CMD_MKENT(hello, 2, 1, do_demo_hello, "", ""),
+ U_BOOT_CMD_MKENT(status, 1, 1, do_demo_status, "", ""),
+};
+
+static int do_demo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ cmd_tbl_t *demo_cmd;
+ int devnum = 0;
+ int ret;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+ demo_cmd = find_cmd_tbl(argv[1], demo_commands,
+ ARRAY_SIZE(demo_commands));
+ argc -= 2;
+ argv += 2;
+ if (!demo_cmd || argc > demo_cmd->maxargs)
+ return CMD_RET_USAGE;
+
+ if (argc) {
+ devnum = simple_strtoul(argv[0], NULL, 10);
+ ret = uclass_get_device(UCLASS_DEMO, devnum, &demo_dev);
+ if (ret)
+ return cmd_process_error(cmdtp, ret);
+ argc--;
+ argv++;
+ }
+
+ ret = demo_cmd->cmd(demo_cmd, flag, argc, argv);
+
+ return cmd_process_error(demo_cmd, ret);
+}
+
+U_BOOT_CMD(
+ demo, 4, 1, do_demo,
+ "Driver model (dm) demo operations",
+ "list List available demo devices\n"
+ "demo hello <num> [<char>] Say hello\n"
+ "demo status <num> Get demo device status"
+);
#include <common.h>
#include <command.h>
-
+#include <dm.h>
#include <asm/gpio.h>
#ifndef name_to_gpio
GPIO_TOGGLE,
};
+#if defined(CONFIG_DM_GPIO) && !defined(gpio_status)
+static const char * const gpio_function[] = {
+ "input",
+ "output",
+ "unknown",
+};
+
+static void show_gpio(struct device *dev, const char *bank_name, int offset)
+{
+ struct dm_gpio_ops *ops = gpio_get_ops(dev);
+ char buf[80];
+ int ret;
+
+ *buf = '\0';
+ if (ops->get_state) {
+ ret = ops->get_state(dev, offset, buf, sizeof(buf));
+ if (ret) {
+ puts("<unknown>");
+ return;
+ }
+ } else {
+ int func = GPIOF_UNKNOWN;
+ int ret;
+
+ if (ops->get_function) {
+ ret = ops->get_function(dev, offset);
+ if (ret >= 0 && ret < ARRAY_SIZE(gpio_function))
+ func = ret;
+ }
+ sprintf(buf, "%s%u: %8s %d", bank_name, offset,
+ gpio_function[func], ops->get_value(dev, offset));
+ }
+
+ puts(buf);
+ puts("\n");
+}
+
+static int do_gpio_status(const char *gpio_name)
+{
+ struct device *dev;
+ int newline = 0;
+ int ret;
+
+ if (gpio_name && !*gpio_name)
+ gpio_name = NULL;
+ for (ret = uclass_first_device(UCLASS_GPIO, &dev);
+ dev;
+ ret = uclass_next_device(&dev)) {
+ const char *bank_name;
+ int num_bits;
+
+ bank_name = gpio_get_bank_info(dev, &num_bits);
+
+ if (!gpio_name || !bank_name ||
+ !strncmp(gpio_name, bank_name, strlen(bank_name))) {
+ const char *p = NULL;
+ int offset;
+
+ if (bank_name) {
+ if (newline)
+ putc('\n');
+ printf("Bank %s:\n", bank_name);
+ }
+ newline = 1;
+ if (gpio_name && bank_name) {
+ p = gpio_name + strlen(bank_name);
+ offset = simple_strtoul(p, NULL, 10);
+ show_gpio(dev, bank_name, offset);
+ } else {
+ for (offset = 0; offset < num_bits; offset++)
+ show_gpio(dev, bank_name, offset);
+ }
+ }
+ }
+
+ return ret;
+}
+#endif
+
static int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- int gpio;
+ unsigned int gpio;
enum gpio_cmd sub_cmd;
ulong value;
- const char *str_cmd, *str_gpio;
+ const char *str_cmd, *str_gpio = NULL;
+#ifdef CONFIG_DM_GPIO
+ int ret;
+#endif
+ if (argc < 2)
+ show_usage:
+ return CMD_RET_USAGE;
+ str_cmd = argv[1];
+ if (argc > 2)
+ str_gpio = argv[2];
+ if (!strcmp(str_cmd, "status")) {
+ /* Support deprecated gpio_status() */
#ifdef gpio_status
- if (argc == 2 && !strcmp(argv[1], "status")) {
gpio_status();
return 0;
- }
+#elif defined(CONFIG_DM_GPIO)
+ return cmd_process_error(cmdtp, do_gpio_status(str_gpio));
+#else
+ goto show_usage;
#endif
+ }
- if (argc != 3)
- show_usage:
- return CMD_RET_USAGE;
- str_cmd = argv[1];
- str_gpio = argv[2];
+ if (!str_gpio)
+ goto show_usage;
/* parse the behavior */
switch (*str_cmd) {
default: goto show_usage;
}
+#if defined(CONFIG_DM_GPIO)
+ /*
+ * TODO(sjg@chromium.org): For now we must fit into the existing GPIO
+ * framework, so we look up the name here and convert it to a GPIO number.
+ * Once all GPIO drivers are converted to driver model, we can change the
+ * code here to use the GPIO uclass interface instead of the numbered
+ * GPIO compatibility layer.
+ */
+ ret = gpio_lookup_name(str_gpio, NULL, NULL, &gpio);
+ if (ret)
+ return cmd_process_error(cmdtp, ret);
+#else
/* turn the gpio name into a gpio number */
gpio = name_to_gpio(str_gpio);
if (gpio < 0)
goto show_usage;
-
+#endif
/* grab the pin before we tweak it */
if (gpio_request(gpio, "cmd_gpio")) {
printf("gpio: requesting pin %u failed\n", gpio);
}
U_BOOT_CMD(gpio, 3, 0, do_gpio,
- "input/set/clear/toggle gpio pins",
+ "query and control gpio pins",
"<input|set|clear|toggle> <pin>\n"
- " - input/set/clear/toggle the specified pin");
+ " - input/set/clear/toggle the specified pin\n"
+ "gpio status [<bank> | <pin>]");
#include <common.h>
#include <command.h>
-#if defined(CONFIG_8xx) || defined(CONFIG_8260)
+#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260)
#if defined(CONFIG_8xx)
#include <asm/8xx_immap.h>
#include <commproc.h>
#include <asm/iopin_8xx.h>
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
#include <asm/immap_8260.h>
#include <asm/cpm_8260.h>
#include <asm/iopin_8260.h>
#if defined(CONFIG_8xx)
volatile sysconf8xx_t *sc = &immap->im_siu_conf;
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
volatile sysconf8260_t *sc = &immap->im_siu_conf;
#endif
printf ("SIPEND= %08x SIMASK= %08x\n", sc->sc_sipend, sc->sc_simask);
printf ("SIEL = %08x SIVEC = %08x\n", sc->sc_siel, sc->sc_sivec);
printf ("TESR = %08x SDCR = %08x\n", sc->sc_tesr, sc->sc_sdcr);
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
printf ("BCR = %08x\n", sc->sc_bcr);
printf ("P_ACR = %02x P_ALRH= %08x P_ALRL= %08x\n",
sc->sc_ppc_acr, sc->sc_ppc_alrh, sc->sc_ppc_alrl);
#if defined(CONFIG_8xx)
volatile memctl8xx_t *memctl = &immap->im_memctl;
int nbanks = 8;
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
volatile memctl8260_t *memctl = &immap->im_memctl;
int nbanks = 12;
#endif
printf ("MAR = %08x", memctl->memc_mar);
#if defined(CONFIG_8xx)
printf (" MCR = %08x\n", memctl->memc_mcr);
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
putc ('\n');
#endif
printf ("MAMR = %08x MBMR = %08x",
memctl->memc_mamr, memctl->memc_mbmr);
#if defined(CONFIG_8xx)
printf ("\nMSTAT = %04x\n", memctl->memc_mstat);
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
printf (" MCMR = %08x\n", memctl->memc_mcmr);
#endif
printf ("MPTPR = %04x MDR = %08x\n",
memctl->memc_mptpr, memctl->memc_mdr);
-#if defined(CONFIG_8260)
+#if defined(CONFIG_MPC8260)
printf ("PSDMR = %08x LSDMR = %08x\n",
memctl->memc_psdmr, memctl->memc_lsdmr);
printf ("PURT = %02x PSRT = %02x\n",
return 0;
}
-#ifdef CONFIG_8260
+#ifdef CONFIG_MPC8260
int
do_icinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
#if defined(CONFIG_8xx)
volatile car8xx_t *car = &immap->im_clkrst;
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
volatile car8260_t *car = &immap->im_clkrst;
#endif
printf ("SCCR = %08x\n", car->car_sccr);
printf ("PLPRCR= %08x\n", car->car_plprcr);
printf ("RSR = %08x\n", car->car_rsr);
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
printf ("SCCR = %08x\n", car->car_sccr);
printf ("SCMR = %08x\n", car->car_scmr);
printf ("RSR = %08x\n", car->car_rsr);
#define PB_NB_ODR 16
#define PC_NBITS 12
#define PD_NBITS 13
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
#define PA_NBITS 32
#define PA_NB_ODR 32
#define PB_NBITS 28
#if defined(CONFIG_8xx)
volatile iop8xx_t *iop = &immap->im_ioport;
volatile ushort *l, *r;
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
volatile iop8260_t *iop = &immap->im_ioport;
volatile uint *l, *r;
#endif
#if defined(CONFIG_8xx)
l = &iop->iop_padir;
R = &immap->im_cpm.cp_pbdir;
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
l = &iop->iop_pdira;
R = &iop->iop_pdirb;
#endif
binary ("PB_DIR", *R++, PB_NBITS);
binary ("PA_PAR", *l++, PA_NBITS);
binary ("PB_PAR", *R++, PB_NBITS);
-#if defined(CONFIG_8260)
+#if defined(CONFIG_MPC8260)
binary ("PA_SOR", *l++, PA_NBITS);
binary ("PB_SOR", *R++, PB_NBITS);
#endif
#if defined(CONFIG_8xx)
l = &iop->iop_pcdir;
r = &iop->iop_pddir;
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
l = &iop->iop_pdirc;
r = &iop->iop_pdird;
#endif
binary ("PC_SO ", *l++, PC_NBITS);
binary (" ", 0, 0);
r++;
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
binary ("PC_SOR", *l++, PC_NBITS);
binary ("PD_SOR", *r++, PD_NBITS);
binary ("PC_ODR", *l++, PC_NBITS);
#if defined(CONFIG_8xx)
ulong clock = gd->cpu_clk;
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
ulong clock = gd->arch.brg_clk;
#endif
#if defined(CONFIG_8xx)
volatile cpm8xx_t *cp = &immap->im_cpm;
volatile uint *p = &cp->cp_brgc1;
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
volatile uint *p = &immap->im_brgc1;
#endif
int i = 1;
while (i <= 4)
prbrg (i++, *p++);
-#if defined(CONFIG_8260)
+#if defined(CONFIG_MPC8260)
p = &immap->im_brgc5;
while (i <= 8)
prbrg (i++, *p++);
volatile i2c8xx_t *i2c = &immap->im_i2c;
volatile cpm8xx_t *cp = &immap->im_cpm;
volatile iic_t *iip = (iic_t *) & cp->cp_dparam[PROFF_IIC];
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
volatile i2c8260_t *i2c = &immap->im_i2c;
volatile iic_t *iip;
uint dpaddr;
""
);
-#ifdef CONFIG_8260
+#ifdef CONFIG_MPC8260
U_BOOT_CMD(
icinfo, 1, 1, do_icinfo,
"print Interrupt Controller registers",
/* Memory Display
*
* Syntax:
- * md{.b, .w, .l} {addr} {len}
+ * md{.b, .w, .l, .q} {addr} {len}
*/
#define DISP_LINE_LEN 16
static int do_mem_md(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
static int do_mem_mw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- ulong addr, writeval, count;
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+ u64 writeval;
+#else
+ ulong writeval;
+#endif
+ ulong addr, count;
int size;
void *buf;
ulong bytes;
/* Get the value to write.
*/
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+ writeval = simple_strtoull(argv[2], NULL, 16);
+#else
writeval = simple_strtoul(argv[2], NULL, 16);
+#endif
/* Count ? */
if (argc == 4) {
while (count-- > 0) {
if (size == 4)
*((u32 *)buf) = (u32)writeval;
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+ else if (size == 8)
+ *((u64 *)buf) = (u64)writeval;
+#endif
else if (size == 2)
*((u16 *)buf) = (u16)writeval;
else
int rcode = 0;
const char *type;
const void *buf1, *buf2, *base;
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+ u64 word1, word2;
+#else
+ ulong word1, word2;
+#endif
if (argc != 4)
return CMD_RET_USAGE;
*/
if ((size = cmd_get_data_size(argv[0], 4)) < 0)
return 1;
- type = size == 4 ? "word" : size == 2 ? "halfword" : "byte";
+ type = size == 8 ? "double word" :
+ size == 4 ? "word" :
+ size == 2 ? "halfword" : "byte";
addr1 = simple_strtoul(argv[1], NULL, 16);
addr1 += base_address;
base = buf1 = map_sysmem(addr1, bytes);
buf2 = map_sysmem(addr2, bytes);
for (ngood = 0; ngood < count; ++ngood) {
- ulong word1, word2;
if (size == 4) {
word1 = *(u32 *)buf1;
word2 = *(u32 *)buf2;
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+ } else if (size == 8) {
+ word1 = *(u64 *)buf1;
+ word2 = *(u64 *)buf2;
+#endif
} else if (size == 2) {
word1 = *(u16 *)buf1;
word2 = *(u16 *)buf2;
}
if (word1 != word2) {
ulong offset = buf1 - base;
-
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+ printf("%s at 0x%p (%#0*llx) != %s at 0x%p (%#0*llx)\n",
+ type, (void *)(addr1 + offset), size, word1,
+ type, (void *)(addr2 + offset), size, word2);
+#else
printf("%s at 0x%08lx (%#0*lx) != %s at 0x%08lx (%#0*lx)\n",
type, (ulong)(addr1 + offset), size, word1,
type, (ulong)(addr2 + offset), size, word2);
+#endif
rcode = 1;
break;
}
while (count-- > 0) {
if (size == 4)
*((u32 *)buf) = *((u32 *)src);
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+ else if (size == 8)
+ *((u64 *)buf) = *((u64 *)src);
+#endif
else if (size == 2)
*((u16 *)buf) = *((u16 *)src);
else
{
ulong addr, length, i, bytes;
int size;
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+ volatile u64 *llp;
+#endif
volatile u32 *longp;
volatile u16 *shortp;
volatile u8 *cp;
* If we have only one object, just run infinite loops.
*/
if (length == 1) {
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+ if (size == 8) {
+ llp = (u64 *)buf;
+ for (;;)
+ i = *llp;
+ }
+#endif
if (size == 4) {
longp = (u32 *)buf;
for (;;)
i = *cp;
}
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+ if (size == 8) {
+ for (;;) {
+ llp = (u64 *)buf;
+ i = length;
+ while (i-- > 0)
+ *llp++;
+ }
+ }
+#endif
if (size == 4) {
for (;;) {
longp = (u32 *)buf;
#ifdef CONFIG_LOOPW
int do_mem_loopw (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- ulong addr, length, i, data, bytes;
+ ulong addr, length, i, bytes;
int size;
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+ volatile u64 *llp;
+ u64 data;
+#else
+ ulong data;
+#endif
volatile u32 *longp;
volatile u16 *shortp;
volatile u8 *cp;
length = simple_strtoul(argv[2], NULL, 16);
/* data to write */
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+ data = simple_strtoull(argv[3], NULL, 16);
+#else
data = simple_strtoul(argv[3], NULL, 16);
+#endif
bytes = size * length;
buf = map_sysmem(addr, bytes);
* If we have only one object, just run infinite loops.
*/
if (length == 1) {
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+ if (size == 8) {
+ llp = (u64 *)buf;
+ for (;;)
+ *llp = data;
+ }
+#endif
if (size == 4) {
longp = (u32 *)buf;
for (;;)
*longp = data;
- }
+ }
if (size == 2) {
shortp = (u16 *)buf;
for (;;)
*cp = data;
}
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+ if (size == 8) {
+ for (;;) {
+ llp = (u64 *)buf;
+ i = length;
+ while (i-- > 0)
+ *llp++ = data;
+ }
+ }
+#endif
if (size == 4) {
for (;;) {
longp = (u32 *)buf;
/* Modify memory.
*
* Syntax:
- * mm{.b, .w, .l} {addr}
- * nm{.b, .w, .l} {addr}
+ * mm{.b, .w, .l, .q} {addr}
+ * nm{.b, .w, .l, .q} {addr}
*/
static int
mod_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const argv[])
{
- ulong addr, i;
+ ulong addr;
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+ u64 i;
+#else
+ ulong i;
+#endif
int nbytes, size;
void *ptr = NULL;
printf("%08lx:", addr);
if (size == 4)
printf(" %08x", *((u32 *)ptr));
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+ else if (size == 8)
+ printf(" %016llx", *((u64 *)ptr));
+#endif
else if (size == 2)
printf(" %04x", *((u16 *)ptr));
else
#endif
else {
char *endp;
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+ i = simple_strtoull(console_buffer, &endp, 16);
+#else
i = simple_strtoul(console_buffer, &endp, 16);
+#endif
nbytes = endp - console_buffer;
if (nbytes) {
#ifdef CONFIG_BOOT_RETRY_TIME
#endif
if (size == 4)
*((u32 *)ptr) = i;
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+ else if (size == 8)
+ *((u64 *)ptr) = i;
+#endif
else if (size == 2)
*((u16 *)ptr) = i;
else
U_BOOT_CMD(
md, 3, 1, do_mem_md,
"memory display",
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+ "[.b, .w, .l, .q] address [# of objects]"
+#else
"[.b, .w, .l] address [# of objects]"
+#endif
);
U_BOOT_CMD(
mm, 2, 1, do_mem_mm,
"memory modify (auto-incrementing address)",
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+ "[.b, .w, .l, .q] address"
+#else
"[.b, .w, .l] address"
+#endif
);
U_BOOT_CMD(
nm, 2, 1, do_mem_nm,
"memory modify (constant address)",
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+ "[.b, .w, .l, .q] address"
+#else
"[.b, .w, .l] address"
+#endif
);
U_BOOT_CMD(
mw, 4, 1, do_mem_mw,
"memory write (fill)",
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+ "[.b, .w, .l, .q] address value [count]"
+#else
"[.b, .w, .l] address value [count]"
+#endif
);
U_BOOT_CMD(
cp, 4, 1, do_mem_cp,
"memory copy",
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+ "[.b, .w, .l, .q] source target count"
+#else
"[.b, .w, .l] source target count"
+#endif
);
U_BOOT_CMD(
cmp, 4, 1, do_mem_cmp,
"memory compare",
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+ "[.b, .w, .l, .q] addr1 addr2 count"
+#else
"[.b, .w, .l] addr1 addr2 count"
+#endif
);
#ifdef CONFIG_CMD_CRC32
U_BOOT_CMD(
loop, 3, 1, do_mem_loop,
"infinite loop on address range",
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+ "[.b, .w, .l, .q] address number_of_objects"
+#else
"[.b, .w, .l] address number_of_objects"
+#endif
);
#ifdef CONFIG_LOOPW
U_BOOT_CMD(
loopw, 4, 1, do_mem_loopw,
"infinite write loop on address range",
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+ "[.b, .w, .l, .q] address number_of_objects data_to_write"
+#else
"[.b, .w, .l] address number_of_objects data_to_write"
+#endif
);
#endif /* CONFIG_LOOPW */
U_BOOT_CMD(
mdc, 4, 1, do_mem_mdc,
"memory display cyclic",
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+ "[.b, .w, .l, .q] address count delay(ms)"
+#else
"[.b, .w, .l] address count delay(ms)"
+#endif
);
U_BOOT_CMD(
mwc, 4, 1, do_mem_mwc,
"memory write cyclic",
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+ "[.b, .w, .l, .q] address value delay(ms)"
+#else
"[.b, .w, .l] address value delay(ms)"
+#endif
);
#endif /* CONFIG_MX_CYCLIC */
if (argc == 2) {
size = simple_strtoul(argv[1], NULL, 16);
+ } else if (argc == 1 && chk) {
+ puts("## Error: external checksum format must pass size\n");
+ return CMD_RET_FAILURE;
} else {
char *s = addr;
return 2;
case 'l':
return 4;
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+ case 'q':
+ return 8;
+#endif
case 's':
return -2;
default:
rc = cmd_usage(cmdtp);
return rc;
}
+
+int cmd_process_error(cmd_tbl_t *cmdtp, int err)
+{
+ if (err) {
+ printf("Command '%s' failed: Error %d\n", cmdtp->name, err);
+ return 1;
+ }
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
+ */
+
+#include <common.h>
+#include <cros_ec.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+struct local_info {
+ struct cros_ec_dev *cros_ec_dev; /* Pointer to cros_ec device */
+ int cros_ec_err; /* Error for cros_ec, 0 if ok */
+};
+
+static struct local_info local;
+
+struct cros_ec_dev *board_get_cros_ec_dev(void)
+{
+ return local.cros_ec_dev;
+}
+
+static int board_init_cros_ec_devices(const void *blob)
+{
+ local.cros_ec_err = cros_ec_init(blob, &local.cros_ec_dev);
+ if (local.cros_ec_err)
+ return -1; /* Will report in board_late_init() */
+
+ return 0;
+}
+
+int cros_ec_board_init(void)
+{
+ return board_init_cros_ec_devices(gd->fdt_blob);
+}
+
+int cros_ec_get_error(void)
+{
+ return local.cros_ec_err;
+}
pid_t pid; /* 0 if exited */
#endif
char **argv; /* program name and arguments */
+ /* was quoted when parsed; copy of struct o_string.nonnull field */
+ int *argv_nonnull;
#ifdef __U_BOOT__
int argc; /* number of program arguments */
#endif
static int parse_group(o_string *dest, struct p_context *ctx, struct in_str *input, int ch);
#endif
static char *lookup_param(char *src);
-static char *make_string(char **inp);
+static char *make_string(char **inp, int *nonnull);
static int handle_dollar(o_string *dest, struct p_context *ctx, struct in_str *input);
#ifndef __U_BOOT__
static int parse_string(o_string *dest, struct p_context *ctx, const char *src);
if (child->sp) {
char * str = NULL;
- str = make_string((child->argv + i));
+ str = make_string(child->argv + i,
+ child->argv_nonnull + i);
parse_string_outer(str, FLAG_EXIT_FROM_LOOP | FLAG_REPARSING);
free(str);
return last_return_code;
for (a = 0; a < child->argc; a++) {
free(child->argv[a]);
}
- free(child->argv);
+ free(child->argv);
+ free(child->argv_nonnull);
child->argc = 0;
#endif
child->argv=NULL;
argc = ++child->argc;
child->argv = realloc(child->argv, (argc+1)*sizeof(*child->argv));
if (child->argv == NULL) return 1;
+ child->argv_nonnull = realloc(child->argv_nonnull,
+ (argc+1)*sizeof(*child->argv_nonnull));
+ if (child->argv_nonnull == NULL)
+ return 1;
child->argv[argc-1]=str;
+ child->argv_nonnull[argc-1] = dest->nonnull;
child->argv[argc]=NULL;
+ child->argv_nonnull[argc] = 0;
for (s = dest->data; s && *s; s++,str++) {
if (*s == '\\') s++;
*str = *s;
prog->redirects = NULL;
#endif
prog->argv = NULL;
+ prog->argv_nonnull = NULL;
#ifndef __U_BOOT__
prog->is_stopped = 0;
#endif
return list;
}
-/* Make new string for parser */
-static char * make_string(char ** inp)
+/*
+ * Make new string for parser
+ * inp - array of argument strings to flatten
+ * nonnull - indicates argument was quoted when originally parsed
+ */
+static char *make_string(char **inp, int *nonnull)
{
char *p;
char *str = NULL;
noeval = 1;
for (n = 0; inp[n]; n++) {
p = insert_var_value_sub(inp[n], noeval);
- str = xrealloc(str, (len + strlen(p)));
+ str = xrealloc(str, (len + strlen(p) + (2 * nonnull[n])));
if (n) {
strcat(str, " ");
} else {
*str = '\0';
}
+ if (nonnull[n])
+ strcat(str, "'");
strcat(str, p);
+ if (nonnull[n])
+ strcat(str, "'");
len = strlen(str) + 3;
if (p != inp[n]) free(p);
}
#include <watchdog.h>
#include <asm/unaligned.h>
#include <splash.h>
+#include <asm/io.h>
+#include <asm/unaligned.h>
#if defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \
defined(CONFIG_CPU_MONAHANS)
# endif
#endif
+#ifdef CONFIG_SANDBOX
+#include <asm/sdl.h>
+#endif
+
#ifndef CONFIG_LCD_ALIGNMENT
#define CONFIG_LCD_ALIGNMENT PAGE_SIZE
#endif
if (lcd_flush_dcache)
flush_dcache_range((u32)lcd_base,
(u32)(lcd_base + lcd_get_size(&line_length)));
+#elif defined(CONFIG_SANDBOX) && defined(CONFIG_VIDEO_SANDBOX_SDL)
+ static ulong last_sync;
+
+ if (get_timer(last_sync) > 10) {
+ sandbox_sdl_sync(lcd_base);
+ last_sync = get_timer(0);
+ }
#endif
}
struct stdio_dev lcddev;
int rc;
- lcd_base = (void *) gd->fb_base;
+ lcd_base = map_sysmem(gd->fb_base, 0);
lcd_init(lcd_base); /* LCD initialization */
* by setting up gd->fb_base. Check for this condition and fixup
* 'lcd_base' address.
*/
- if ((unsigned long)lcdbase != gd->fb_base)
- lcd_base = (void *)gd->fb_base;
+ if (map_to_sysmem(lcdbase) != gd->fb_base)
+ lcd_base = map_sysmem(gd->fb_base, 0);
debug("[LCD] Using LCD frambuffer at %p\n", lcd_base);
ushort *cmap_base = NULL;
ushort i, j;
uchar *fb;
- bmp_image_t *bmp=(bmp_image_t *)bmp_image;
+ bmp_image_t *bmp = (bmp_image_t *)map_sysmem(bmp_image, 0);
uchar *bmap;
ushort padded_width;
unsigned long width, height, byte_width;
#
#########################################################################
-# clean the slate ...
-PLATFORM_RELFLAGS =
-PLATFORM_CPPFLAGS =
-PLATFORM_LDFLAGS =
-
+# This file is included from ./Makefile and spl/Makefile.
+# Clean the state to avoid the same flags added twice.
+#
+# (Tegra needs different flags for SPL.
+# That's the reason why this file must be included from spl/Makefile too.
+# If we did not have Tegra SoCs, build system would be much simpler...)
+PLATFORM_RELFLAGS :=
+PLATFORM_CPPFLAGS :=
+PLATFORM_LDFLAGS :=
+LDFLAGS :=
+LDFLAGS_FINAL :=
+OBJCOPYFLAGS :=
#########################################################################
# Some architecture config.mk files need to know what CPUDIR is set to,
# Check if arch/$ARCH/cpu/$CPU exists, otherwise assume arch/$ARCH/cpu contains
# CPU-specific code.
CPUDIR=arch/$(ARCH)/cpu/$(CPU)
-ifneq ($(SRCTREE)/$(CPUDIR),$(wildcard $(SRCTREE)/$(CPUDIR)))
+ifneq ($(srctree)/$(CPUDIR),$(wildcard $(srctree)/$(CPUDIR)))
CPUDIR=arch/$(ARCH)/cpu
endif
-sinclude $(TOPDIR)/arch/$(ARCH)/config.mk # include architecture dependend rules
-sinclude $(TOPDIR)/$(CPUDIR)/config.mk # include CPU specific rules
+sinclude $(srctree)/arch/$(ARCH)/config.mk # include architecture dependend rules
+sinclude $(srctree)/$(CPUDIR)/config.mk # include CPU specific rules
ifdef SOC
-sinclude $(TOPDIR)/$(CPUDIR)/$(SOC)/config.mk # include SoC specific rules
+sinclude $(srctree)/$(CPUDIR)/$(SOC)/config.mk # include SoC specific rules
endif
+ifneq ($(BOARD),)
ifdef VENDOR
BOARDDIR = $(VENDOR)/$(BOARD)
else
BOARDDIR = $(BOARD)
endif
+endif
ifdef BOARD
-sinclude $(TOPDIR)/board/$(BOARDDIR)/config.mk # include board specific rules
+sinclude $(srctree)/board/$(BOARDDIR)/config.mk # include board specific rules
endif
#########################################################################
-RELFLAGS= $(PLATFORM_RELFLAGS)
+RELFLAGS := $(PLATFORM_RELFLAGS)
OBJCOPYFLAGS += --gap-fill=0xff
-CPPFLAGS = $(RELFLAGS)
-CPPFLAGS += -pipe $(PLATFORM_CPPFLAGS)
-
-BCURDIR = $(subst $(SRCTREE)/,,$(CURDIR:$(obj)%=%))
+PLATFORM_CPPFLAGS += $(RELFLAGS)
+PLATFORM_CPPFLAGS += -pipe
LDFLAGS += $(PLATFORM_LDFLAGS)
LDFLAGS_FINAL += -Bstatic
+
+export PLATFORM_CPPFLAGS
+export RELFLAGS
+export LDFLAGS_FINAL
+export CONFIG_STANDALONE_LOAD_ADDR
int part;
disk_partition_t tmpinfo;
- /*
- * For now, we have a special case for sandbox, since there is no
- * real block device support.
- */
- if (0 == strcmp(ifname, "host")) {
- *dev_desc = NULL;
- info->start = info->size = info->blksz = 0;
- info->bootable = 0;
- strcpy((char *)info->type, BOOT_PART_TYPE);
- strcpy((char *)info->name, "Sandbox host");
-#ifdef CONFIG_PARTITION_UUIDS
- info->uuid[0] = 0;
-#endif
-
- return 0;
- }
-
/* If no dev_part_str, use bootdevice environment variable */
if (!dev_part_str || !strlen(dev_part_str) ||
!strcmp(dev_part_str, "-"))
How it works
------------
-There is a new directory TOPDIR/spl which contains only a Makefile.
+There is a new directory $(srctree)/spl which contains only a Makefile.
The object files are built separately for SPL and placed in this directory.
The final binaries which are generated are u-boot-spl, u-boot-spl.bin and
u-boot-spl.map.
How it works
------------
-There has been a directory TOPDIR/spl which contains only a Makefile. The
+There has been a directory $(srctree)/spl which contains only a Makefile. The
Makefile is shared by SPL and TPL.
The object files are built separately for SPL/TPL and placed in the
referenced in the source code as such.
If a new board is defined do not forget to define the command section
-by writing in u-boot.lds ($(TOPDIR)/board/boardname/u-boot.lds) these
+by writing in u-boot.lds ($(srctree)/board/boardname/u-boot.lds) these
3 lines:
.u_boot_list : {
kwbimage.cfg. The name can be set as part of the full path
to the file using CONFIG_SYS_KWD_CONFIG (probably in
include/configs/<yourboard>.h). The path should look like:
- $(SRCTREE)/$(CONFIG_BOARDDIR)/<yourkwbimagename>.cfg
+ $(CONFIG_BOARDDIR)/<yourkwbimagename>.cfg
2. This file can have empty lines and lines starting with "#" as first
character to put comments
3. This file can have configuration command lines as mentioned below,
- Within Navigator Console run the following commands:
- source /path/to/u-boot/board/malta/flash-malta-boot.tcl
+ source /path/to/u-boot/board/imgtec/malta/flash-malta-boot.tcl
reset
flash-boot /path/to/u-boot/u-boot.bin
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
-dvl_host arm ixp - 2014-01-28 Michael Schwingen <michael@schwingen.org>
-actux4 arm ixp - 2014-01-28 Michael Schwingen <michael@schwingen.org>
-actux3 arm ixp - 2014-01-28 Michael Schwingen <michael@schwingen.org>
-actux2 arm ixp - 2014-01-28 Michael Schwingen <michael@schwingen.org>
-actux1 arm ixp - 2014-01-28 Michael Schwingen <michael@schwingen.org>
-mx1ads arm arm920t - 2014-01-13
-mini2440 arm arm920t - 2014-01-13 Gabriel Huau <contact@huau-gabriel.fr>
+idmr m68k mcf52x2 - 2014-01-28
+M5271EVB m68k mcf52x2 - 2014-01-28
+dvl_host arm ixp e317de6b 2014-01-28 Michael Schwingen <michael@schwingen.org>
+actux4 arm ixp 6ff7aafa 2014-01-28 Michael Schwingen <michael@schwingen.org>
+actux3 arm ixp 38da33f3 2014-01-28 Michael Schwingen <michael@schwingen.org>
+actux2 arm ixp 13e0ee7f 2014-01-28 Michael Schwingen <michael@schwingen.org>
+actux1 arm ixp 373ee048 2014-01-28 Michael Schwingen <michael@schwingen.org>
+mx1ads arm arm920t e570aca9 2014-01-13
+mini2440 arm arm920t af5b9b1f 2014-01-13 Gabriel Huau <contact@huau-gabriel.fr>
omap730p2 arm arm926ejs 79c5c08d 2013-11-11
pn62 powerpc mpc824x 649acfe1 2013-11-11 Wolfgang Grandegger <wg@grandegger.com>
pdnb3 arm ixp 304db0b 2013-09-24 Stefan Roese <sr@denx.de>
support USB with CONFIG_CMD_USB enabled and working. You will need to
add some config settings to your board header file:
+#define CONFIG_CMD_USB /* the 'usb' interactive command */
#define CONFIG_USB_HOST_ETHER /* Enable USB Ethernet adapters */
-#define CONFIG_USB_ETHER_ASIX /* Asix, or whatever driver(s) you want */
+
+and one or more of the following for individual adapter hardware:
+
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_MCS7830
+#define CONFIG_USB_ETHER_SMSC95XX
As with built-in networking, you will also want to enable some network
commands, for example:
You can also set the default IP address of your board and the server
as well as the default file to load when a 'bootp' command is issued.
-All of these can be obtained from the bootp server if not set.
+However note that encoding these individual network settings into a
+common exectuable is discouraged, as it leads to potential conflicts,
+and all the parameters can either get stored in the board's external
+environment, or get obtained from the bootp server if not set.
#define CONFIG_IPADDR 10.0.0.2 (replace with your value)
#define CONFIG_SERVERIP 10.0.0.1 (replace with your value)
--- /dev/null
+Exynos MIPI-DSIM Controller
+=========================
+
+Required properties:
+SOC specific:
+ compatible: should be "samsung,exynos-mipi-dsi"
+ reg: Base address of MIPI-DSIM IP.
+
+Board specific:
+ samsung,dsim-config-e-interface: interface to be used (RGB interface
+ for main display or CPU interface for main or sub display).
+ samsung,dsim-config-e-virtual-ch: virtual channel number that main
+ or sub display uses.
+ samsung,dsim-config-e-pixel-format: pixel stream format for main
+ or sub display.
+ samsung,dsim-config-e-burst-mode: selects Burst mode in Video mode.
+ in Non-burst mode, RGB data area is filled with RGB data and
+ NULL packets, according to input bandwidth of RGB interface.
+ samsung,dsim-config-e-no-data-lane: data lane count used by Master.
+ samsung,dsim-config-e-byte-clk: select byte clock source.
+ It must be DSIM_PLL_OUT_DIV8.
+ DSIM_EXT_CLK_DIV8 and DSIM_EXT_CLK_BYPASSS are not supported.
+ samsung,dsim-config-hfp: HFP disable mode.
+ If set, DSI master ignores HFP area in VIDEO mode.
+ In command mode, this variable is ignored.
+ samsung,dsim-config-p: P value for PMS setting.
+ samsung,dsim-config-m: M value for PMS setting.
+ samsung,dsim-config-s: S value for PMS setting.
+ samsung,dsim-config-pll-stable-time: the PLL Timer for stability
+ of the ganerated clock.
+ samsung,dsim-config-esc-clk: escape clock frequency for getting
+ the escape clock prescaler value.
+ samsung,dsim-config-stop-holding-cnt: the interval value between
+ transmitting read packet (or write "set_tear_on" command)
+ and BTA request. After transmitting read packet or write
+ "set_tear_on" command, BTA requests to D-PHY automatically.
+ This counter value specifies the interval between them.
+ samsung,dsim-config-bta-timeout: the timer for BTA. This register
+ specifies time out from BTA request to change the direction
+ with respect to Tx escape clock.
+ samsung,dsim-config-rx-timeout: the timer for LP Rx mode timeout.
+ this register specifies time out on how long RxValid deasserts,
+ after RxLpdt asserts with respect to Tx escape clock.
+ - RxValid specifies Rx data valid indicator.
+ - RxLpdt specifies an indicator that D-PHY is under RxLpdt mode
+ - RxValid and RxLpdt specifies signal from D-PHY.
+ samsung,dsim-device-name: name of the device.
+ samsung,dsim-device-id: unique device id.
+ samsung,dsim-device-bus_id: bus id for identifing connected bus
+ and this bus id should be same as id of mipi_dsim_device.
+
+Optional properties:
+ samsung,dsim-device-reverse-panel: reverse panel.
+
+Example:
+ mipidsi@11c80000 {
+ compatible = "samsung,exynos-mipi-dsi";
+ reg = <0x11c80000 0x5c>;
+
+ samsung,dsim-config-e-interface = <1>;
+ samsung,dsim-config-e-virtual-ch = <0>;
+ samsung,dsim-config-e-pixel-format = <7>;
+ samsung,dsim-config-e-burst-mode = <1>;
+ samsung,dsim-config-e-no-data-lane = <3>;
+ samsung,dsim-config-e-byte-clk = <0>;
+ samsung,dsim-config-hfp = <1>;
+
+ samsung,dsim-config-p = <3>;
+ samsung,dsim-config-m = <120>;
+ samsung,dsim-config-s = <1>;
+
+ samsung,dsim-config-pll-stable-time = <500>;
+ samsung,dsim-config-esc-clk = <20000000>;
+ samsung,dsim-config-stop-holding-cnt = <0x7ff>;
+ samsung,dsim-config-bta-timeout = <0xff>;
+ samsung,dsim-config-rx-timeout = <0xffff>;
+
+ samsung,dsim-device-id = <0xffffffff>;
+ samsung,dsim-device-bus-id = <0>;
+
+ samsung,dsim-device-reverse-panel = <1>;
+ };
--- /dev/null
+Sandbox LCD
+===========
+
+This uses the displaymode.txt binding except that only xres and yres are
+required properties.
+
+Example:
+
+ lcd {
+ compatible = "sandbox,lcd-sdl";
+ xres = <800>;
+ yres = <600>;
+ };
--- /dev/null
+Driver Model
+============
+
+This README contains high-level information about driver model, a unified
+way of declaring and accessing drivers in U-Boot. The original work was done
+by:
+
+ Marek Vasut <marex@denx.de>
+ Pavel Herrmann <morpheus.ibis@gmail.com>
+ Viktor Křivák <viktor.krivak@gmail.com>
+ Tomas Hlavacek <tmshlvck@gmail.com>
+
+This has been both simplified and extended into the current implementation
+by:
+
+ Simon Glass <sjg@chromium.org>
+
+
+Terminology
+-----------
+
+Uclass - a group of devices which operate in the same way. A uclass provides
+ a way of accessing invidual devices within the group, but always
+ using the same interface. For example a GPIO uclass provides
+ operations for get/set value. An I2C uclass may have 10 I2C ports,
+ 4 with one driver, and 6 with another.
+
+Driver - some code which talks to a peripheral and presents a higher-level
+ interface to it.
+
+Device - an instance of a driver, tied to a particular port or peripheral.
+
+
+How to try it
+-------------
+
+Build U-Boot sandbox and run it:
+
+ make sandbox_config
+ make
+ ./u-boot
+
+ (type 'reset' to exit U-Boot)
+
+
+There is a uclass called 'demo'. This uclass handles
+saying hello, and reporting its status. There are two drivers in this
+uclass:
+
+ - simple: Just prints a message for hello, doesn't implement status
+ - shape: Prints shapes and reports number of characters printed as status
+
+The demo class is pretty simple, but not trivial. The intention is that it
+can be used for testing, so it will implement all driver model features and
+provide good code coverage of them. It does have multiple drivers, it
+handles parameter data and platdata (data which tells the driver how
+to operate on a particular platform) and it uses private driver data.
+
+To try it, see the example session below:
+
+=>demo hello 1
+Hello '@' from 07981110: red 4
+=>demo status 2
+Status: 0
+=>demo hello 2
+g
+r@
+e@@
+e@@@
+n@@@@
+g@@@@@
+=>demo status 2
+Status: 21
+=>demo hello 4 ^
+ y^^^
+ e^^^^^
+l^^^^^^^
+l^^^^^^^
+ o^^^^^
+ w^^^
+=>demo status 4
+Status: 36
+=>
+
+
+Running the tests
+-----------------
+
+The intent with driver model is that the core portion has 100% test coverage
+in sandbox, and every uclass has its own test. As a move towards this, tests
+are provided in test/dm. To run them, try:
+
+ ./test/dm/test-dm.sh
+
+You should see something like this:
+
+ <...U-Boot banner...>
+ Running 12 driver model tests
+ Test: dm_test_autobind
+ Test: dm_test_autoprobe
+ Test: dm_test_children
+ Test: dm_test_fdt
+ Test: dm_test_gpio
+ sandbox_gpio: sb_gpio_get_value: error: offset 4 not reserved
+ Test: dm_test_leak
+ Warning: Please add '#define DEBUG' to the top of common/dlmalloc.c
+ Warning: Please add '#define DEBUG' to the top of common/dlmalloc.c
+ Test: dm_test_lifecycle
+ Test: dm_test_operations
+ Test: dm_test_ordering
+ Test: dm_test_platdata
+ Test: dm_test_remove
+ Test: dm_test_uclass
+ Failures: 0
+
+(You can add '#define DEBUG' as suggested to check for memory leaks)
+
+
+What is going on?
+-----------------
+
+Let's start at the top. The demo command is in common/cmd_demo.c. It does
+the usual command procesing and then:
+
+ struct device *demo_dev;
+
+ ret = uclass_get_device(UCLASS_DEMO, devnum, &demo_dev);
+
+UCLASS_DEMO means the class of devices which implement 'demo'. Other
+classes might be MMC, or GPIO, hashing or serial. The idea is that the
+devices in the class all share a particular way of working. The class
+presents a unified view of all these devices to U-Boot.
+
+This function looks up a device for the demo uclass. Given a device
+number we can find the device because all devices have registered with
+the UCLASS_DEMO uclass.
+
+The device is automatically activated ready for use by uclass_get_device().
+
+Now that we have the device we can do things like:
+
+ return demo_hello(demo_dev, ch);
+
+This function is in the demo uclass. It takes care of calling the 'hello'
+method of the relevant driver. Bearing in mind that there are two drivers,
+this particular device may use one or other of them.
+
+The code for demo_hello() is in drivers/demo/demo-uclass.c:
+
+int demo_hello(struct device *dev, int ch)
+{
+ const struct demo_ops *ops = device_get_ops(dev);
+
+ if (!ops->hello)
+ return -ENOSYS;
+
+ return ops->hello(dev, ch);
+}
+
+As you can see it just calls the relevant driver method. One of these is
+in drivers/demo/demo-simple.c:
+
+static int simple_hello(struct device *dev, int ch)
+{
+ const struct dm_demo_pdata *pdata = dev_get_platdata(dev);
+
+ printf("Hello from %08x: %s %d\n", map_to_sysmem(dev),
+ pdata->colour, pdata->sides);
+
+ return 0;
+}
+
+
+So that is a trip from top (command execution) to bottom (driver action)
+but it leaves a lot of topics to address.
+
+
+Declaring Drivers
+-----------------
+
+A driver declaration looks something like this (see
+drivers/demo/demo-shape.c):
+
+static const struct demo_ops shape_ops = {
+ .hello = shape_hello,
+ .status = shape_status,
+};
+
+U_BOOT_DRIVER(demo_shape_drv) = {
+ .name = "demo_shape_drv",
+ .id = UCLASS_DEMO,
+ .ops = &shape_ops,
+ .priv_data_size = sizeof(struct shape_data),
+};
+
+
+This driver has two methods (hello and status) and requires a bit of
+private data (accessible through dev_get_priv(dev) once the driver has
+been probed). It is a member of UCLASS_DEMO so will register itself
+there.
+
+In U_BOOT_DRIVER it is also possible to specify special methods for bind
+and unbind, and these are called at appropriate times. For many drivers
+it is hoped that only 'probe' and 'remove' will be needed.
+
+The U_BOOT_DRIVER macro creates a data structure accessible from C,
+so driver model can find the drivers that are available.
+
+The methods a device can provide are documented in the device.h header.
+Briefly, they are:
+
+ bind - make the driver model aware of a device (bind it to its driver)
+ unbind - make the driver model forget the device
+ ofdata_to_platdata - convert device tree data to platdata - see later
+ probe - make a device ready for use
+ remove - remove a device so it cannot be used until probed again
+
+The sequence to get a device to work is bind, ofdata_to_platdata (if using
+device tree) and probe.
+
+
+Platform Data
+-------------
+
+Where does the platform data come from? See demo-pdata.c which
+sets up a table of driver names and their associated platform data.
+The data can be interpreted by the drivers however they like - it is
+basically a communication scheme between the board-specific code and
+the generic drivers, which are intended to work on any board.
+
+Drivers can acceess their data via dev->info->platdata. Here is
+the declaration for the platform data, which would normally appear
+in the board file.
+
+ static const struct dm_demo_cdata red_square = {
+ .colour = "red",
+ .sides = 4.
+ };
+ static const struct driver_info info[] = {
+ {
+ .name = "demo_shape_drv",
+ .platdata = &red_square,
+ },
+ };
+
+ demo1 = driver_bind(root, &info[0]);
+
+
+Device Tree
+-----------
+
+While platdata is useful, a more flexible way of providing device data is
+by using device tree. With device tree we replace the above code with the
+following device tree fragment:
+
+ red-square {
+ compatible = "demo-shape";
+ colour = "red";
+ sides = <4>;
+ };
+
+
+The easiest way to make this work it to add a few members to the driver:
+
+ .platdata_auto_alloc_size = sizeof(struct dm_test_pdata),
+ .ofdata_to_platdata = testfdt_ofdata_to_platdata,
+ .probe = testfdt_drv_probe,
+
+The 'auto_alloc' feature allowed space for the platdata to be allocated
+and zeroed before the driver's ofdata_to_platdata method is called. This
+method reads the information out of the device tree and puts it in
+dev->platdata. Then the probe method is called to set up the device.
+
+Note that both methods are optional. If you provide an ofdata_to_platdata
+method then it wlil be called first (after bind). If you provide a probe
+method it will be called next.
+
+If you don't want to have the platdata automatically allocated then you
+can leave out platdata_auto_alloc_size. In this case you can use malloc
+in your ofdata_to_platdata (or probe) method to allocate the required memory,
+and you should free it in the remove method.
+
+
+Declaring Uclasses
+------------------
+
+The demo uclass is declared like this:
+
+U_BOOT_CLASS(demo) = {
+ .id = UCLASS_DEMO,
+};
+
+It is also possible to specify special methods for probe, etc. The uclass
+numbering comes from include/dm/uclass.h. To add a new uclass, add to the
+end of the enum there, then declare your uclass as above.
+
+
+Data Structures
+---------------
+
+Driver model uses a doubly-linked list as the basic data structure. Some
+nodes have several lists running through them. Creating a more efficient
+data structure might be worthwhile in some rare cases, once we understand
+what the bottlenecks are.
+
+
+Changes since v1
+----------------
+
+For the record, this implementation uses a very similar approach to the
+original patches, but makes at least the following changes:
+
+- Tried to agressively remove boilerplate, so that for most drivers there
+is little or no 'driver model' code to write.
+- Moved some data from code into data structure - e.g. store a pointer to
+the driver operations structure in the driver, rather than passing it
+to the driver bind function.
+- Rename some structures to make them more similar to Linux (struct device
+instead of struct instance, struct platdata, etc.)
+- Change the name 'core' to 'uclass', meaning U-Boot class. It seems that
+this concept relates to a class of drivers (or a subsystem). We shouldn't
+use 'class' since it is a C++ reserved word, so U-Boot class (uclass) seems
+better than 'core'.
+- Remove 'struct driver_instance' and just use a single 'struct device'.
+This removes a level of indirection that doesn't seem necessary.
+- Built in device tree support, to avoid the need for platdata
+- Removed the concept of driver relocation, and just make it possible for
+the new driver (created after relocation) to access the old driver data.
+I feel that relocation is a very special case and will only apply to a few
+drivers, many of which can/will just re-init anyway. So the overhead of
+dealing with this might not be worth it.
+- Implemented a GPIO system, trying to keep it simple
+
+
+Things to punt for later
+------------------------
+
+- SPL support - this will have to be present before many drivers can be
+converted, but it seems like we can add it once we are happy with the
+core implementation.
+- Pre-relocation support - similar story
+
+That is not to say that no thinking has gone into these - in fact there
+is quite a lot there. However, getting these right is non-trivial and
+there is a high cost associated with going down the wrong path.
+
+For SPL, it may be possible to fit in a simplified driver model with only
+bind and probe methods, to reduce size.
+
+For pre-relocation we can simply call the driver model init function. Then
+post relocation we throw that away and re-init driver model again. For drivers
+which require some sort of continuity between pre- and post-relocation
+devices, we can provide access to the pre-relocation device pointers.
+
+Uclasses are statically numbered at compile time. It would be possible to
+change this to dynamic numbering, but then we would require some sort of
+lookup service, perhaps searching by name. This is slightly less efficient
+so has been left out for now. One small advantage of dynamic numbering might
+be fewer merge conflicts in uclass-id.h.
+
+
+Simon Glass
+sjg@chromium.org
+April 2013
+Updated 7-May-13
+Updated 14-Jun-13
+Updated 18-Oct-13
+Updated 5-Nov-13
+++ /dev/null
-The U-Boot Driver Model Project
-===============================
-Block device subsystem analysis
-===============================
-
-Pavel Herrmann <morpheus.ibis@gmail.com>
-2012-03-08
-
-I) Overview
------------
-
- U-Boot currently implements several distinct APIs for block devices - some
- drivers use the SATA API, some drivers use the IDE API, sym53c8xx and
- AHCI use the SCSI API, mg_disk has a separate API, and systemace also has a
- separate API. There are also MMC and USB APIs used outside of drivers/block,
- those will be detailed in their specific documents.
-
- Block devices are described by block_dev_desc structure, that holds, among
- other things, the read/write/erase callbacks. Block device structures are
- stored in any way depending on the API, but can be accessed by
-
- block_dev_desc_t * $api_get_dev(int dev)
-
- function, as seen in disk/part.c.
-
- 1) SATA interface
- -----------------
-
- The SATA interface drivers implement the following functions:
-
- int init_sata(int dev)
- int scan_sata(int dev)
- ulong sata_read(int dev, ulong blknr, ulong blkcnt, void *buffer)
- ulong sata_write(int dev, ulong blknr, ulong blkcnt, const void *buffer)
-
- Block devices are kept in sata_dev_desc[], which is prefilled with values
- common to all SATA devices in cmd_sata.c, and then modified in init_sata
- function in the drivers. Callbacks of the block device use SATA API
- directly. The sata_get_dev function is defined in cmd_sata.c.
-
- 2) SCSI interface
- -----------------
-
- The SCSI interface drivers implement the following functions:
-
- void scsi_print_error(ccb *pccb)
- int scsi_exec(ccb *pccb)
- void scsi_bus_reset(void)
- void scsi_low_level_init(int busdevfunc)
-
- The SCSI API works through the scsi_exec function, the actual operation
- requested is found in the ccb structure.
-
- Block devices are kept in scsi_dev_desc[], which lives only in cmd_scsi.c.
- Callbacks of the block device use functions from cmd_scsi.c, which in turn
- call scsi_exec of the controller. The scsi_get_dev function is also defined
- in cmd_scsi.c.
-
- 3) mg_disk interface
- --------------------
-
- The mg_disk interface drivers implement the following functions:
-
- struct mg_drv_data* mg_get_drv_data (void)
- uint mg_disk_init (void)
- uint mg_disk_read (u32 addr, u8 *buff, u32 len)
- uint mg_disk_write(u32 addr, u8 *buff, u32 len)
- uint mg_disk_write_sects(void *buff, u32 sect_num, u32 sect_cnt)
- uint mg_disk_read_sects(void *buff, u32 sect_num, u32 sect_cnt)
-
- The mg_get_drv_data function is to be overridden per-board, but there are no
- board in-tree that do this.
-
- Only one driver for this API exists, and it only supports one block device.
- Callbacks for this device are implemented in mg_disk.c and call the mg_disk
- API. The mg_disk_get_dev function is defined in mg_disk.c and ignores the
- device number, always returning the same device.
-
- 4) systemace interface
- ----------------------
-
- The systemace interface does not define any driver API, and has no command
- itself. The single defined function is systemace_get_devs() from
- systemace.c, which returns a single static structure for the only supported
- block device. Callbacks for this device are also implemented in systemace.c.
-
- 5) IDE interface
- ----------------
-
- The IDE interface drivers implement the following functions, but only if
- CONFIG_IDE_AHB is set:
-
- uchar ide_read_register(int dev, unsigned int port);
- void ide_write_register(int dev, unsigned int port, unsigned char val);
- void ide_read_data(int dev, ulong *sect_buf, int words);
- void ide_write_data(int dev, const ulong *sect_buf, int words);
-
- The first two functions are called from ide_inb()/ide_outb(), and will
- default to direct memory access if CONFIG_IDE_AHB is not set, or
- ide_inb()/ide_outb() functions will get overridden by the board altogether.
-
- The second two functions are called from input_data()/output_data()
- functions, and also default to direct memory access, but cannot be
- overridden by the board.
-
- One function shared by IDE drivers (but not defined in ide.h) is
- int ide_preinit(void)
- This function gets called from ide_init in cmd_ide.c if CONFIG_IDE_PREINIT
- is defined, and will do the driver-specific initialization of the device.
-
- Block devices are kept in ide_dev_desc[], which is filled in cmd_ide.c.
- Callbacks of the block device are defined in cmd_ide.c, and use the
- ide_inb()/ide_outb()/input_data()/output_data() functions mentioned above.
- The ide_get_dev function is defined in cmd_ide.c.
-
-II) Approach
-------------
-
- A new block controller core and an associated API will be created to mimic the
- current SATA API, its drivers will have the following ops:
-
- struct block_ctrl_ops {
- int scan(instance *i);
- int reset(instance *i, int port);
- lbaint_t read(instance *i, int port, lbaint_t start, lbatin_t length,
- void *buffer);
- lbaint_t write(instance *i, int port, lbaint_t start, lbatin_t length,
- void*buffer);
- }
-
- The current sata_init() function will be changed into the driver probe()
- function. The read() and write() functions should never be called directly,
- instead they should be called by block device driver for disks.
-
- Other block APIs would either be transformed into this API, or be kept as
- legacy for old drivers, or be dropped altogether.
-
- Legacy driver APIs will each have its own driver core that will contain the
- shared logic, which is currently located mostly in cmd_* files. Callbacks for
- block device drivers will then probably be implemented as a part of the core
- logic, and will use the driver ops (which will copy current state of
- respective APIs) to do the work.
-
- All drivers will be cleaned up, most ifdefs should be converted into
- platform_data, to enable support for multiple devices with different settings.
-
- A new block device core will also be created, and will keep track of all
- block devices on all interfaces.
-
- Current block_dev_desc structure will be changed to fit the driver model, all
- identification and configuration will be placed in private data, and
- a single accessor and modifier will be defined, to accommodate the need for
- different sets of options for different interfaces, while keeping the
- structure small. The new block device drivers will have the following ops
- structure (lbaint_t is either 32bit or 64bit unsigned, depending on
- CONFIG_LBA48):
-
- struct blockdev_ops {
- lbaint_t (*block_read)(struct instance *i, lbaint_t start, lbaint_t blkcnt,
- void *buffer);
- lbaint_t (*block_write)(struct instance *i, lbaint_t start, lbaint_t blkcnt,
- void *buffer);
- lbaint_t (*block_erase)(struct instance *i, lbaint_t start, lbaint_t blkcnt
- );
- int (*get_option)(struct instance *i, enum blockdev_option_code op,
- struct option *res);
- int (*set_option)(struct instance *i, enum blockdev_option_code op,
- struct option *val);
- }
-
- struct option {
- uint32_t flags
- union data {
- uint64_t data_u;
- char* data_s;
- void* data_p;
- }
- }
-
- enum blockdev_option_code {
- BLKD_OPT_IFTYPE=0,
- BLKD_OPT_TYPE,
- BLKD_OPT_BLOCKSIZE,
- BLKD_OPT_BLOCKCOUNT,
- BLKD_OPT_REMOVABLE,
- BLKD_OPT_LBA48,
- BLKD_OPT_VENDOR,
- BLKD_OPT_PRODICT,
- BLKD_OPT_REVISION,
- BLKD_OPT_SCSILUN,
- BLKD_OPT_SCSITARGET,
- BLKD_OPT_OFFSET
- }
-
- Flags in option above will contain the type of returned data (which should be
- checked against what is expected, even though the option requested should
- specify it), and a flag to indicate whether the returned pointer needs to be
- free()'d.
-
- The block device core will contain the logic now located in disk/part.c and
- related files, and will be used to forward requests to block devices. The API
- for the block device core will copy the ops of a block device (with a string
- identifier instead of instance pointer). This means that partitions will also
- be handled by the block device core, and exported as block devices, making
- them transparent to the rest of the code.
-
- Sadly, this will change how file systems can access the devices, and thus will
- affect a lot of places. However, these changes should be localized and easy to
- implement.
-
- AHCI driver will be rewritten to fit the new unified block controller API,
- making SCSI API easy to merge with sym53c8xx, or remove it once the device
- driver has died.
-
- Optionally, IDE core may be changed into one driver with unified block
- controller API, as most of it is already in one place and device drivers are
- just sets of hooks. Additionally, mg_disk driver is unused and may be removed
- in near future.
-
-
-III) Analysis of in-tree drivers
---------------------------------
-
- ahci.c
- ------
- SCSI API, will be rewritten for a different API.
-
- ata_piix.c
- ----------
- SATA API, easy to port.
-
- fsl_sata.c
- ----------
- SATA API, few CONFIG macros, easy to port.
-
- ftide020.c
- ----------
- IDE API, defines CONFIG_IDE_AHB and ide_preinit hook functions.
-
- mg_disk.c
- ---------
- Single driver with mg_disk API, not much to change, easy to port.
-
- mvsata_ide.c
- ------------
- IDE API, only defines ide_preinit hook function.
-
- mxc_ata.c
- ---------
- IDE API, only defines ide_preinit hook function.
-
- pata_bfin.c
- -----------
- SATA API, easy to port.
-
- sata_dwc.c
- ----------
- SATA API, easy to port.
-
- sata_sil3114.c
- --------------
- SATA API, easy to port.
-
- sata_sil.c
- ----------
- SATA API, easy to port.
-
- sil680.c
- --------
- IDE API, only defines ide_preinit hook function.
-
- sym53c8xx.c
- -----------
- SCSI API, may be merged with code from cmd_scsi.
-
- systemace.c
- -----------
- Single driver with systemace API, not much to change, easy to port.
+++ /dev/null
-The U-Boot Driver Model Project
-===============================
-Driver cores API document
-=========================
-
-Pavel Herrmann <morpheus.ibis@gmail.com>
-
-1) Overview
------------
- Driver cores will be used as a wrapper for devices of the same type, and as
- an abstraction for device driver APIs. For each driver API (which roughly
- correspond to device types), there will be one driver core. Each driver core
- will implement three APIs - a driver API (which will be the same as API of
- drivers the core wraps around), a core API (which will be implemented by all
- cores) and a command API (core-specific API which will be exposed to
- commands).
-
- A) Command API
- The command API will provide access to shared functionality for a specific
- device, which is currently located mostly in commands. Commands will be
- rewritten to be more lightweight by using this API. As this API will be
- different for each core, it is out of scope of this document.
-
- B) Driver API
- The driver API will act as a wrapper around actual device drivers,
- providing a single entrypoint for device access. All functions in this API
- have an instance* argument (probably called "this" or "i"), which will be
- examined by the core, and a correct function for the specified driver will
- get called.
-
- If the core gets called with a group instance pointer (as discussed in
- design), it will automatically select the instance that is associated
- with this core, and use it as target of the call. if the group contains
- multiple instances of a single type, the caller must explicitly use an
- accessor to select the correct instance.
-
- This accessor will look like:
- struct instance *get_instance_from_group(struct instance *group, int i)
-
- When called with a non-group instance, it will simply return the instance.
-
- C) Core API
- The core API will be implemented by all cores, and will provide
- functionality for getting driver instances from non-driver code. This API
- will consist of following functions:
-
- int get_count(struct instance *core);
- struct instance* get_instance(struct instance *core, int index);
- int init(struct instance *core);
- int bind(struct instance *core, struct instance *dev, void *ops,
- void *hint);
- int unbind(struct instance *core, instance *dev);
- int replace(struct instance *core, struct_instance *new_dev,
- struct instance *old_dev);
- int destroy(struct instance *core);
- int reloc(struct instance *new_core, struct instance *old_core);
-
- The 'hint' parameter of bind() serves for additional data a driver can
- pass to the core, to help it create the correct internal state for this
- instance. the replace() function will get called during instance
- relocation, and will replace the old instance with the new one, keeping
- the internal state untouched.
-
-
-2) Lifetime of a driver core
-----------------------------
- Driver cores will be initialized at runtime, to limit memory footprint in
- early-init stage, when we have to fit into ~1KB of memory. All active cores
- will be stored in a tree structure (referenced as "Core tree") in global data,
- which provides good tradeoff between size and access time.
- Every core will have a number constant associated with it, which will be used
- to find the instance in Core tree, and to refer to the core in all calls
- working with the Core tree.
- The Core Tree should be implemented using B-tree (or a similar structure)
- to guarantee acceptable time overhead in all cases.
-
- Code for working with the core (i2c in this example) follows:
-
- core_init(CORE_I2C);
- This will check whether we already have a i2c core, and if not it creates
- a new instance and adds it into the Core tree. This will not be exported,
- all code should depend on get_core_instance to init the core when
- necessary.
-
- get_core_instance(CORE_I2C);
- This is an accessor into the Core tree, which will return the instance
- of i2c core, creating it if necessary
-
- core_bind(CORE_I2C, instance, driver_ops);
- This will get called in bind() function of a driver, and will add the
- instance into cores internal list of devices. If the core is not found, it
- will get created.
-
- driver_activate(instance *inst);
- This call will recursively activate all devices necessary for using the
- specified device. the code could be simplified as:
- {
- if (is_activated(inst))
- return;
- driver_activate(inst->bus);
- get_driver(inst)->probe(inst);
- }
-
- The case with multiple parents will need to be handled here as well.
- get_driver is an accessor to available drivers, which will get struct
- driver based on a name in the instance.
-
- i2c_write(instance *inst, ...);
- An actual call to some method of the driver. This code will look like:
- {
- driver_activate(inst);
- struct instance *core = get_core_instance(CORE_I2C);
- device_ops = get_ops(inst);
- device_ops->write(...);
- }
-
- get_ops will not be an exported function, it will be internal and specific
- to the core, as it needs to know how are the ops stored, and what type
- they are.
-
- Please note that above examples represent the algorithm, not the actual code,
- as they are missing checks for validity of return values.
-
- core_init() function will get called the first time the core is requested,
- either by core_link() or core_get_instance(). This way, the cores will get
- created only when they are necessary, which will reduce our memory footprint.
+++ /dev/null
-The U-Boot Driver Model Project
-===============================
-Design document
-===============
-Marek Vasut <marek.vasut@gmail.com>
-Pavel Herrmann <morpheus.ibis@gmail.com>
-2012-05-17
-
-I) The modular concept
-----------------------
-
-The driver core design is done with modularity in mind. The long-term plan is to
-extend this modularity to allow loading not only drivers, but various other
-objects into U-Boot at runtime -- like commands, support for other boards etc.
-
-II) Driver core initialization stages
--------------------------------------
-
-The drivers have to be initialized in two stages, since the U-Boot bootloader
-runs in two stages itself. The first stage is the one which is executed before
-the bootloader itself is relocated. The second stage then happens after
-relocation.
-
- 1) First stage
- --------------
-
- The first stage runs after the bootloader did very basic hardware init. This
- means the stack pointer was configured, caches disabled and that's about it.
- The problem with this part is the memory management isn't running at all. To
- make things even worse, at this point, the RAM is still likely uninitialized
- and therefore unavailable.
-
- 2) Second stage
- ---------------
-
- At this stage, the bootloader has initialized RAM and is running from it's
- final location. Dynamic memory allocations are working at this point. Most of
- the driver initialization is executed here.
-
-III) The drivers
-----------------
-
- 1) The structure of a driver
- ----------------------------
-
- The driver will contain a structure located in a separate section, which
- will allow linker to create a list of compiled-in drivers at compile time.
- Let's call this list "driver_list".
-
- struct driver __attribute__((section(driver_list))) {
- /* The name of the driver */
- char name[STATIC_CONFIG_DRIVER_NAME_LENGTH];
-
- /*
- * This function should connect this driver with cores it depends on and
- * with other drivers, likely bus drivers
- */
- int (*bind)(struct instance *i);
-
- /* This function actually initializes the hardware. */
- int (*probe)(struct instance *i);
-
- /*
- * The function of the driver called when U-Boot finished relocation.
- * This is particularly important to eg. move pointers to DMA buffers
- * and such from the location before relocation to their final location.
- */
- int (*reloc)(struct instance *i);
-
- /*
- * This is called when the driver is shuting down, to deinitialize the
- * hardware.
- */
- int (*remove)(struct instance *i);
-
- /* This is called to remove the driver from the driver tree */
- int (*unbind)(struct instance *i);
-
- /* This is a list of cores this driver depends on */
- struct driver *cores[];
- };
-
- The cores[] array in here is very important. It allows u-boot to figure out,
- in compile-time, which possible cores can be activated at runtime. Therefore
- if there are cores that won't be ever activated, GCC LTO might remove them
- from the final binary. Actually, this information might be used to drive build
- of the cores.
-
- FIXME: Should *cores[] be really struct driver, pointing to drivers that
- represent the cores? Shouldn't it be core instance pointer?
-
- 2) Instantiation of a driver
- ----------------------------
-
- The driver is instantiated by calling:
-
- driver_bind(struct instance *bus, const struct driver_info *di)
-
- The "struct instance *bus" is a pointer to a bus with which this driver should
- be registered with. The "root" bus pointer is supplied to the board init
- functions.
-
- FIXME: We need some functions that will return list of busses of certain type
- registered with the system so the user can find proper instance even if
- he has no bus pointer (this will come handy if the user isn't
- registering the driver from board init function, but somewhere else).
-
- The "const struct driver_info *di" pointer points to a structure defining the
- driver to be registered. The structure is defined as follows:
-
- struct driver_info {
- char name[STATIC_CONFIG_DRIVER_NAME_LENGTH];
- void *platform_data;
- }
-
- The instantiation of a driver by calling driver_bind() creates an instance
- of the driver by allocating "struct driver_instance". Note that only struct
- instance is passed to the driver. The wrapping struct driver_instance is there
- for purposes of the driver core:
-
- struct driver_instance {
- uint32_t flags;
- struct instance i;
- };
-
- struct instance {
- /* Pointer to a driver information passed by driver_register() */
- const struct driver_info *info;
- /* Pointer to a bus this driver is bound with */
- struct instance *bus;
- /* Pointer to this driver's own private data */
- void *private_data;
- /* Pointer to the first block of successor nodes (optional) */
- struct successor_block *succ;
- }
-
- The instantiation of a driver does not mean the hardware is initialized. The
- driver_bind() call only creates the instance of the driver, fills in the "bus"
- pointer and calls the drivers' .bind() function. The .bind() function of the
- driver should hook the driver with the remaining cores and/or drivers it
- depends on.
-
- It's important to note here, that in case the driver instance has multiple
- parents, such parent can be connected with this instance by calling:
-
- driver_link(struct instance *parent, struct instance *dev);
-
- This will connect the other parent driver with the newly instantiated driver.
- Note that this must be called after driver_bind() and before driver_acticate()
- (driver_activate() will be explained below). To allow struct instance to have
- multiple parent pointer, the struct instance *bus will utilize it's last bit
- to indicate if this is a pointer to struct instance or to an array if
- instances, struct successor block. The approach is similar as the approach to
- *succ in struct instance, described in the following paragraph.
-
- The last pointer of the struct instance, the pointer to successor nodes, is
- used only in case of a bus driver. Otherwise the pointer contains NULL value.
- The last bit of this field indicates if this is a bus having a single child
- node (so the last bit is 0) or if this bus has multiple child nodes (the last
- bit is 1). In the former case, the driver core should clear the last bit and
- this pointer points directly to the child node. In the later case of a bus
- driver, the pointer points to an instance of structure:
-
- struct successor_block {
- /* Array of pointers to instances of devices attached to this bus */
- struct instance *dev[BLOCKING_FACTOR];
- /* Pointer to next block of successors */
- struct successor_block *next;
- }
-
- Some of the *dev[] array members might be NULL in case there are no more
- devices attached. The *next is NULL in case the list of attached devices
- doesn't continue anymore. The BLOCKING_FACTOR is used to allocate multiple
- slots for successor devices at once to avoid fragmentation of memory.
-
- 3) The bind() function of a driver
- ----------------------------------
-
- The bind function of a driver connects the driver with various cores the
- driver provides functions for. The driver model related part will look like
- the following example for a bus driver:
-
- int driver_bind(struct instance *in)
- {
- ...
- core_bind(&core_i2c_static_instance, in, i2c_bus_funcs);
- ...
- }
-
- FIXME: What if we need to run-time determine, depending on some hardware
- register, what kind of i2c_bus_funcs to pass?
-
- This makes the i2c core aware of a new bus. The i2c_bus_funcs is a constant
- structure of functions any i2c bus driver must provide to work. This will
- allow the i2c command operate with the bus. The core_i2c_static_instance is
- the pointer to the instance of a core this driver provides function to.
-
- FIXME: Maybe replace "core-i2c" with CORE_I2C global pointer to an instance of
- the core?
-
- 4) The instantiation of a core driver
- -------------------------------------
-
- The core driver is special in the way that it's single-instance driver. It is
- always present in the system, though it might not be activated. The fact that
- it's single instance allows it to be instantiated at compile time.
-
- Therefore, all possible structures of this driver can be in read-only memory,
- especially struct driver and struct driver_instance. But the successor list,
- which needs special treatment.
-
- To solve the problem with a successor list and the core driver flags, a new
- entry in struct gd (global data) will be introduced. This entry will point to
- runtime allocated array of struct driver_instance. It will be possible to
- allocate the exact amount of struct driver_instance necessary, as the number
- of cores that might be activated will be known at compile time. The cores will
- then behave like any usual driver.
-
- Pointers to the struct instance of cores can be computed at compile time,
- therefore allowing the resulting u-boot binary to save some overhead.
-
- 5) The probe() function of a driver
- -----------------------------------
-
- The probe function of a driver allocates necessary resources and does required
- initialization of the hardware itself. This is usually called only when the
- driver is needed, as a part of the defered probe mechanism.
-
- The driver core should implement a function called
-
- int driver_activate(struct instance *in);
-
- which should call the .probe() function of the driver and then configure the
- state of the driver instance to "ACTIVATED". This state of a driver instance
- should be stored in a wrap-around structure for the structure instance, the
- struct driver_instance.
-
- 6) The command side interface to a driver
- -----------------------------------------
-
- The U-Boot command shall communicate only with the specific driver core. The
- driver core in turn exports necessary API towards the command.
-
- 7) Demonstration imaginary board
- --------------------------------
-
- Consider the following computer:
-
- *
- |
- +-- System power management logic
- |
- +-- CPU clock controlling logc
- |
- +-- NAND controller
- | |
- | +-- NAND flash chip
- |
- +-- 128MB of DDR DRAM
- |
- +-- I2C bus #0
- | |
- | +-- RTC
- | |
- | +-- EEPROM #0
- | |
- | +-- EEPROM #1
- |
- +-- USB host-only IP core
- | |
- | +-- USB storage device
- |
- +-- USB OTG-capable IP core
- | |
- | +-- connection to the host PC
- |
- +-- GPIO
- | |
- | +-- User LED #0
- | |
- | +-- User LED #1
- |
- +-- UART0
- |
- +-- UART1
- |
- +-- Ethernet controller #0
- |
- +-- Ethernet controller #1
- |
- +-- Audio codec
- |
- +-- PCI bridge
- | |
- | +-- Ethernet controller #2
- | |
- | +-- SPI host card
- | | |
- | | +-- Audio amplifier (must be operational before codec)
- | |
- | +-- GPIO host card
- | |
- | +-- User LED #2
- |
- +-- LCD controller
- |
- +-- PWM controller (must be enabled after LCD controller)
- |
- +-- SPI host controller
- | |
- | +-- SD/MMC connected via SPI
- | |
- | +-- SPI flash
- |
- +-- CPLD/FPGA with stored configuration of the board
+++ /dev/null
-The U-Boot Driver Model Project
-===============================
-I/O system analysis
-===================
-Marek Vasut <marek.vasut@gmail.com>
-2012-02-21
-
-I) Overview
------------
-
-The current FPGA implementation is handled by command "fpga". This command in
-turn calls the following functions:
-
-fpga_info()
-fpga_load()
-fpga_dump()
-
-These functions are implemented by what appears to be FPGA multiplexer, located
-in drivers/fpga/fpga.c . This code determines which device to operate with
-depending on the device ID.
-
-The fpga_info() function is multiplexer of the functions providing information
-about the particular FPGA device. These functions are implemented in the drivers
-for the particular FPGA device:
-
-xilinx_info()
-altera_info()
-lattice_info()
-
-Similar approach is used for fpga_load(), which multiplexes "xilinx_load()",
-"altera_load()" and "lattice_load()" and is used to load firmware into the FPGA
-device.
-
-The fpga_dump() function, which prints the contents of the FPGA device, is no
-different either, by multiplexing "xilinx_dump()", "altera_dump()" and
-"lattice_dump()" functions.
-
-Finally, each new FPGA device is registered by calling "fpga_add()" function.
-This function takes two arguments, the second one being particularly important,
-because it's basically what will become platform_data. Currently, it's data that
-are passed to the driver from the board/platform code.
-
-II) Approach
-------------
-
-The path to conversion of the FPGA subsystem will be very straightforward, since
-the FPGA subsystem is already quite dynamic. Multiple things will need to be
-modified though.
-
-First is the registration of the new FPGA device towards the FPGA core. This
-will be achieved by calling:
-
- fpga_device_register(struct instance *i, const struct fpga_ops *ops);
-
-The particularly interesting part is the struct fpga_ops, which contains
-operations supported by the FPGA device. These are basically the already used
-calls in the current implementation:
-
-struct fpga_ops {
- int info(struct instance *i);
- int load(struct instance *i, const char *buf, size_t size);
- int dump(struct instance *i, const char *buf, size_t size);
-}
-
-The other piece that'll have to be modified is how the devices are tracked.
-It'll be necessary to introduce a linked list of devices within the FPGA core
-instead of tracking them by ID number.
-
-Next, the "Xilinx_desc", "Lattice_desc" and "Altera_desc" structures will have
-to be moved to driver's private_data. Finally, structures passed from the board
-and/or platform files, like "Xilinx_Virtex2_Slave_SelectMap_fns" would be passed
-via platform_data to the driver.
-
-III) Analysis of in-tree drivers
---------------------------------
-
- 1) Altera driver
- ----------------
- The driver is realized using the following files:
-
- drivers/fpga/altera.c
- drivers/fpga/ACEX1K.c
- drivers/fpga/cyclon2.c
- drivers/fpga/stratixII.c
-
- All of the sub-drivers implement basically the same info-load-dump interface
- and there's no expected problem during the conversion. The driver itself will
- be realised by altera.c and all the sub-drivers will be linked in. The
- distinction will be done by passing different platform data.
-
- 2) Lattice driver
- -----------------
- The driver is realized using the following files:
-
- drivers/fpga/lattice.c
- drivers/fpga/ivm_core.c
-
- This driver also implements the standard interface, but to realise the
- operations with the FPGA device, uses functions from "ivm_core.c" file. This
- file implements the main communications logic and has to be linked in together
- with "lattice.c". No problem converting is expected here.
-
- 3) Xilinx driver
- ----------------
- The driver is realized using the following files:
-
- drivers/fpga/xilinx.c
- drivers/fpga/spartan2.c
- drivers/fpga/spartan3.c
- drivers/fpga/virtex2.c
-
- This set of sub-drivers is special by defining a big set of macros in
- "include/spartan3.h" and similar files. These macros would need to be either
- rewritten or replaced. Otherwise, there are no problems expected during the
- conversion process.
+++ /dev/null
-The U-Boot Driver Model Project
-===============================
-GPIO analysis
-=============
-Viktor Krivak <viktor.krivak@gmail.com>
-2012-02-24
-
-I) Overview
------------
-
- At this moment U-Boot provides standard API that consists of 7 functions.
-
- int gpio_request(unsigned gpio, const char *label)
- int gpio_free(unsigned gpio)
- int gpio_direction_input(unsigned gpio)
- int gpio_direction_output(unsigned gpio, int value)
- int gpio_get_value(unsigned gpio)
- void gpio_set_value(unsigned gpio, int value)
-
- Methods "gpio_request()" and "gpio_free()" are used for claiming and releasing
- GPIOs. First one should check if the desired pin exists and if the pin wasn't
- requested already elsewhere. The method also has a label argument that can be
- used for debug purposes. The label argument should be copied into the internal
- memory, but only if the DEBUG macro is set. The "gpio_free()" is the exact
- opposite. It releases the particular pin. Other methods are used for setting
- input or output direction and obtaining or setting values of the pins.
-
-II) Approach
-------------
-
- 1) Request and free GPIO
- ------------------------
-
- The "gpio_request()" implementation is basically the same for all boards.
- The function checks if the particular GPIO is correct and checks if the
- GPIO pin is still free. If the conditions are met, the method marks the
- GPIO claimed in it's internal structure. If macro DEBUG is defined, the
- function also copies the label argument to the structure. If the pin is
- already locked, the function returns -1 and if DEBUG is defined, certain
- debug output is generated, including the contents of the label argument.
- The "gpio_free()" function releases the lock and eventually deallocates
- data used by the copied label argument.
-
- 2) Internal data
- ----------------
-
- Internal data are driver specific. They have to contain some mechanism to
- realise the locking though. This can be done for example using a bit field.
-
- 3) Operations provided by the driver
- ------------------------------------
-
- The driver operations basically meet API that is already defined and used.
- Except for "gpio_request()" and "gpio_free()", all methods can be converted in
- a simple manner. The driver provides the following structure:
-
- struct gpio_driver_ops {
- int (*gpio_request)(struct instance *i, unsigned gpio,
- const char *label);
- int (*gpio_free)(struct instance *i, unsigned gpio);
- int (*gpio_direction_input)(struct instance *i, unsigned gpio);
- int (*gpio_direction_output)(struct instance *i, unsigned gpio,
- int value);
- int (*gpio_get_value)(struct instance *i, unsigned gpio);
- void (*gpio_set_value)(struct instance *i, unsigned gpio, int value);
- }
-
-III) Analysis of in-tree drivers
---------------------------------
-
- altera_pio.c
- ------------
- Meets standard API. Implements gpio_request() properly. Simple conversion
- possible.
-
- at91_gpio.c
- -----------
- Don't meet standard API. Need some other methods to implement.
-
- da8xx_gpio.c
- ------------
- Meets standard API. Implements gpio_request() properly. Simple conversion
- possible.
-
- kw_gpio.c
- ---------
- Doesn't meet standard API. Needs some other methods to implement and move some
- methods to another file.
-
- mpc83xx_gpio.c
- --------------
- Meets standard API. Doesn't implement gpio_request() properly (only checks
- if the pin is valid). Simple conversion possible.
-
- mvgpio.c
- --------
- Meets standard API. Doesn't implement gpio_request() properly (only checks
- if the pin is valid). Simple conversion possible.
-
- mvgpio.h
- --------
- Wrong placement. Will be moved to another location.
-
- mvmfp.c
- -------
- Wrong placement. Will be moved to another location.
+++ /dev/null
-The U-Boot Driver Model Project
-===============================
-Hwmon device subsystem analysis
-===============================
-
-Tomas Hlavacek <tmshlvck@gmail.com>
-2012-03-02
-
-I) Overview
------------
-
-U-Boot currently implements one API for HW monitoring devices. The
-interface is defined in include/dtt.h and comprises of functions:
-
- void dtt_init(void);
- int dtt_init_one(int);
- int dtt_read(int sensor, int reg);
- int dtt_write(int sensor, int reg, int val);
- int dtt_get_temp(int sensor);
-
-The functions are implemented by a proper device driver in drivers/hwmon
-directory and the driver to be compiled in is selected in a Makefile.
-Drivers are mutually exclusive.
-
-Drivers depends on I2O code and naturally on board specific data. There are
-few ad-hoc constants put in dtt.h file and driver headers and code. This
-has to be consolidated into board specific data or driver headers if those
-constants makes sense globally.
-
-
-II) Approach
-------------
-
- 1) New API
- ----------
- In the UDM each hwmon driver would register itself by a function
-
- int hwmon_device_register(struct instance *i,
- struct hwmon_device_ops *o);
-
- The structure being defined as follows:
-
- struct hwmon_device_ops {
- int (*read)(struct instance *i, int sensor, int reg);
- int (*write)(struct instance *i, int sensor, int reg,
- int val);
- int (*get_temp)(struct instance *i, int sensor);
- };
-
-
- 2) Conversion thougths
- ----------------------
- U-Boot hwmon drivers exports virtually the same functions (with exceptions)
- and we are considering low number of drivers and code anyway. The interface
- is already similar and unified by the interface defined in dtt.h.
- Current initialization functions dtt_init() and dtt_init_one() will be
- converted into probe() and hwmon_device_register(), so the funcionality will
- be kept in more proper places. Besides implementing core registration and
- initialization we need to do code cleanup, especially separate
- driver-specific and HW specific constants.
-
- 3) Special consideration due to early initialization
- ----------------------------------------------------
- The dtt_init() function call is used during early initialization in
- board/gdsys/405ex/io64.c for starting up fans. The dtt code is perfectly
- usable in the early stage because it uses only local variables and no heap
- memory is required at this level. However the underlying code of I2C has to
- keep the same properties with regard to possibility of running in early
- initialization stage.
-
-III) Analysis of in-tree drivers
---------------------------------
-
- drivers/hwmon/lm81.c
- --------------------
- The driver is standard dtt. Simple conversion is possible.
-
-
- drivers/hwmon/ds1722.c
- ----------------------
- The driver is not standard dtt, but interface is similar to dtt.
- The interface has to be changed in order to comply to above mentioned
- specification.
-
-
- drivers/hwmon/ds1775.c
- ----------------------
- The driver is standard dtt. Simple conversion is possible.
-
-
- drivers/hwmon/lm73.c
- --------------------
- The driver is standard dtt. Simple conversion is possible.
-
-
- drivers/hwmon/lm63.c
- --------------------
- The driver is standard dtt. Simple conversion is possible.
-
-
- drivers/hwmon/adt7460.c
- -----------------------
- The driver is standard dtt. Simple conversion is possible.
-
-
- drivers/hwmon/lm75.c
- --------------------
- The driver is standard dtt. Simple conversion is possible.
-
-
- drivers/hwmon/ds1621.c
- ----------------------
- The driver is standard dtt. Simple conversion is possible.
-
-
- drivers/hwmon/adm1021.c
- -----------------------
- The driver is standard dtt. Simple conversion is possible.
+++ /dev/null
-The U-Boot Driver Model Project
-===============================
-Keyboard input analysis
-=======================
-Marek Vasut <marek.vasut@gmail.com>
-2012-02-20
-
-I) Overview
------------
-
-The keyboard drivers are most often registered with STDIO subsystem. There are
-components of the keyboard drivers though, which operate in severe ad-hoc
-manner, often being related to interrupt-driven keypress reception. This
-components will require the most sanitization of all parts of keyboard input
-subsystem.
-
-Otherwise, the keyboard is no different from other standard input but with the
-necessity to decode scancodes. These are decoded using tables provided by
-keyboard drivers. These tables are often driver specific.
-
-II) Approach
-------------
-
-The most problematic part is the interrupt driven keypress reception. For this,
-the buffers that are currently shared throughout the whole U-Boot would need to
-be converted into driver's private data.
-
-III) Analysis of in-tree drivers
---------------------------------
-
- board/mpl/common/kbd.c
- ----------------------
- This driver is a classic STDIO driver, no problem with conversion is expected.
- Only necessary change will be to move this driver to a proper location.
-
- board/rbc823/kbd.c
- ------------------
- This driver is a classic STDIO driver, no problem with conversion is expected.
- Only necessary change will be to move this driver to a proper location.
-
- drivers/input/keyboard.c
- ------------------------
- This driver is special in many ways. Firstly because this is a universal stub
- driver for converting scancodes from i8042 and the likes. Secondly because the
- buffer is filled by various other ad-hoc implementations of keyboard input by
- using this buffer as an extern. This will need to be fixed by allowing drivers
- to pass certain routines to this driver via platform data.
+++ /dev/null
-The U-Boot Driver Model Project
-===============================
-MMC system analysis
-===================
-Marek Vasut <marek.vasut@gmail.com>
-2012-02-25
-
-I) Overview
------------
-
-The MMC subsystem is already quite dynamic in it's nature. It's only necessary
-to flip the subsystem to properly defined API.
-
-The probing process of MMC drivers start by calling "mmc_initialize()",
-implemented by MMC framework, from the architecture initialization file. The
-"mmc_initialize()" function in turn calls "board_mmc_init()" function and if
-this doesn't succeed, "cpu_mmc_init()" function is called. It is important to
-note that both of the "*_mmc_init()" functions have weak aliases to functions
-which automatically fail.
-
-Both of the "*_mmc_init()" functions though serve only one purpose. To call
-driver specific probe function, which in turn actually registers the driver with
-MMC subsystem. Each of the driver specific probe functions is currently done in
-very ad-hoc manner.
-
-The registration with the MMC subsystem is done by calling "mmc_register()",
-whose argument is a runtime configured structure of information about the MMC
-driver. Currently, the information structure is intermixed with driver's internal
-data. The description of the structure follows:
-
-struct mmc {
- /*
- * API: Allows this driver to be a member of the linked list of all MMC drivers
- * registered with MMC subsystem
- */
- struct list_head link;
-
- /* DRIVER: Name of the registered driver */
- char name[32];
-
- /* DRIVER: Driver's private data */
- void *priv;
-
- /* DRIVER: Voltages the host bus can provide */
- uint voltages;
-
- /* API: Version of the card */
- uint version;
-
- /* API: Test if the driver was already initialized */
- uint has_init;
-
- /* DRIVER: Minimum frequency the host bus can provide */
- uint f_min;
-
- /* DRIVER: Maximum frequency the host bus can provide */
- uint f_max;
-
- /* API: Is the card SDHC */
- int high_capacity;
-
- /* API: Actual width of the bus used by the current card */
- uint bus_width;
-
- /*
- * DRIVER: Clock frequency to be configured on the host bus, this is read-only
- * for the driver.
- */
- uint clock;
-
- /* API: Capabilities of the card */
- uint card_caps;
-
- /* DRIVER: MMC bus capabilities */
- uint host_caps;
-
- /* API: Configuration and ID data retrieved from the card */
- uint ocr;
- uint scr[2];
- uint csd[4];
- uint cid[4];
- ushort rca;
-
- /* API: Partition configuration */
- char part_config;
-
- /* API: Number of partitions */
- char part_num;
-
- /* API: Transmission speed */
- uint tran_speed;
-
- /* API: Read block length */
- uint read_bl_len;
-
- /* API: Write block length */
- uint write_bl_len;
-
- /* API: Erase group size */
- uint erase_grp_size;
-
- /* API: Capacity of the card */
- u64 capacity;
-
- /* API: Descriptor of this block device */
- block_dev_desc_t block_dev;
-
- /* DRIVER: Function used to submit command to the card */
- int (*send_cmd)(struct mmc *mmc,
- struct mmc_cmd *cmd, struct mmc_data *data);
-
- /* DRIVER: Function used to configure the host */
- void (*set_ios)(struct mmc *mmc);
-
- /* DRIVER: Function used to initialize the host */
- int (*init)(struct mmc *mmc);
-
- /* DRIVER: Function used to report the status of Card Detect pin */
- int (*getcd)(struct mmc *mmc);
-
- /*
- * DRIVER: Maximum amount of blocks sent during multiblock xfer,
- * set to 0 to autodetect.
- */
- uint b_max;
-};
-
-The API above is the new API used by most of the drivers. There're still drivers
-in the tree that use old, legacy API though.
-
-2) Approach
------------
-
-To convert the MMC subsystem to a proper driver model, the "struct mmc"
-structure will have to be properly split in the first place. The result will
-consist of multiple parts, first will be the structure defining operations
-provided by the MMC driver:
-
-struct mmc_driver_ops {
- /* Function used to submit command to the card */
- int (*send_cmd)(struct mmc *mmc,
- struct mmc_cmd *cmd, struct mmc_data *data);
- /* DRIVER: Function used to configure the host */
- void (*set_ios)(struct mmc *mmc);
- /* Function used to initialize the host */
- int (*init)(struct mmc *mmc);
- /* Function used to report the status of Card Detect pin */
- int (*getcd)(struct mmc *mmc);
-}
-
-The second part will define the parameters of the MMC driver:
-
-struct mmc_driver_params {
- /* Voltages the host bus can provide */
- uint32_t voltages;
- /* Minimum frequency the host bus can provide */
- uint32_t f_min;
- /* Maximum frequency the host bus can provide */
- uint32_t f_max;
- /* MMC bus capabilities */
- uint32_t host_caps;
- /*
- * Maximum amount of blocks sent during multiblock xfer,
- * set to 0 to autodetect.
- */
- uint32_t b_max;
-}
-
-And finally, the internal per-card data of the MMC subsystem core:
-
-struct mmc_card_props {
- /* Version of the card */
- uint32_t version;
- /* Test if the driver was already initializes */
- bool has_init;
- /* Is the card SDHC */
- bool high_capacity;
- /* Actual width of the bus used by the current card */
- uint8_t bus_width;
- /* Capabilities of the card */
- uint32_t card_caps;
- /* Configuration and ID data retrieved from the card */
- uint32_t ocr;
- uint32_t scr[2];
- uint32_t csd[4];
- uint32_t cid[4];
- uint16_t rca;
- /* Partition configuration */
- uint8_t part_config;
- /* Number of partitions */
- uint8_t part_num;
- /* Transmission speed */
- uint32_t tran_speed;
- /* Read block length */
- uint32_t read_bl_len;
- /* Write block length */
- uint32_t write_bl_len;
- /* Erase group size */
- uint32_t erase_grp_size;
- /* Capacity of the card */
- uint64_t capacity;
- /* Descriptor of this block device */
- block_dev_desc_t block_dev;
-}
-
-The probe() function will then register the MMC driver by calling:
-
- mmc_device_register(struct instance *i, struct mmc_driver_ops *o,
- struct mmc_driver_params *p);
-
-The struct mmc_driver_params will have to be dynamic in some cases, but the
-driver shouldn't modify it's contents elsewhere than in probe() call.
-
-Next, since the MMC drivers will now be consistently registered into the driver
-tree from board file, the functions "board_mmc_init()" and "cpu_mmc_init()" will
-disappear altogether.
-
-As for the legacy drivers, these will either be converted or removed altogether.
-
-III) Analysis of in-tree drivers
---------------------------------
-
- arm_pl180_mmci.c
- ----------------
- Follows the new API and also has a good encapsulation of the whole driver. The
- conversion here will be simple.
-
- atmel_mci.c
- -----------
- This driver uses the legacy API and should be removed unless converted. It is
- probably possbible to replace this driver with gen_atmel_mci.c . No conversion
- will be done on this driver.
-
- bfin_sdh.c
- ----------
- Follows the new API and also has a good encapsulation of the whole driver. The
- conversion here will be simple.
-
- davinci_mmc.c
- -------------
- Follows the new API and also has a good encapsulation of the whole driver. The
- conversion here will be simple.
-
- fsl_esdhc.c
- -----------
- Follows the new API and also has a good encapsulation of the whole driver. The
- conversion here will be simple, unless some problem appears due to the FDT
- component of the driver.
-
- ftsdc010_esdhc.c
- ----------------
- Follows the new API and also has a good encapsulation of the whole driver. The
- conversion here will be simple.
-
- gen_atmel_mci.c
- ---------------
- Follows the new API and also has a good encapsulation of the whole driver. The
- conversion here will be simple.
-
- mmc_spi.c
- ---------
- Follows the new API and also has a good encapsulation of the whole driver. The
- conversion here will be simple.
-
- mv_sdhci.c
- ----------
- This is a component of the SDHCI support, allowing it to run on Marvell
- Kirkwood chip. It is probable the SDHCI support will have to be modified to
- allow calling functions from this file based on information passed via
- platform_data.
-
- mxcmmc.c
- --------
- Follows the new API and also has a good encapsulation of the whole driver. The
- conversion here will be simple.
-
- mxsmmc.c
- --------
- Follows the new API and also has a good encapsulation of the whole driver. The
- conversion here will be simple.
-
- omap_hsmmc.c
- ------------
- Follows the new API and also has a good encapsulation of the whole driver. The
- conversion here will be simple.
-
- pxa_mmc.c
- ---------
- This driver uses the legacy API and is written in a severely ad-hoc manner.
- This driver will be removed in favor of pxa_mmc_gen.c, which is proved to work
- better and is already well tested. No conversion will be done on this driver
- anymore.
-
- pxa_mmc_gen.c
- -------------
- Follows the new API and also has a good encapsulation of the whole driver. The
- conversion here will be simple.
-
- s5p_mmc.c
- ---------
- Follows the new API and also has a good encapsulation of the whole driver. The
- conversion here will be simple.
-
- sdhci.c
- -------
- Follows the new API and also has a good encapsulation of the whole driver. The
- conversion here will be simple, though it'd be necessary to modify this driver
- to also support the Kirkwood series and probably also Tegra series of CPUs.
- See the respective parts of this section for details.
-
- sh_mmcif.c
- ----------
- Follows the new API and also has a good encapsulation of the whole driver. The
- conversion here will be simple.
-
- tegra2_mmc.c
- ------------
- Follows the new API and also has a good encapsulation of the whole driver. The
- conversion here will be simple.
+++ /dev/null
-The U-Boot Driver Model Project
-===============================
-Net system analysis
-===================
-Marek Vasut <marek.vasut@gmail.com>
-2012-03-03
-
-I) Overview
------------
-
-The networking subsystem already supports multiple devices. Therefore the
-conversion shall not be very hard.
-
-The network subsystem is operated from net/eth.c, which tracks all registered
-ethernet interfaces and calls their particular functions registered via
-eth_register().
-
-The eth_register() is called from the network driver initialization function,
-which in turn is called most often either from "board_net_init()" or
-"cpu_net_init()". This function has one important argument, which is the
-"struct eth_device", defined at include/net.h:
-
-struct eth_device {
- /* DRIVER: Name of the device */
- char name[NAMESIZE];
- /* DRIVER: MAC address */
- unsigned char enetaddr[6];
- /* DRIVER: Register base address */
- int iobase;
- /* CORE: state of the device */
- int state;
-
- /* DRIVER: Device initialization function */
- int (*init) (struct eth_device*, bd_t*);
- /* DRIVER: Function for sending packets */
- int (*send) (struct eth_device*, volatile void* packet, int length);
- /* DRIVER: Function for receiving packets */
- int (*recv) (struct eth_device*);
- /* DRIVER: Function to cease operation of the device */
- void (*halt) (struct eth_device*);
- /* DRIVER: Function to send multicast packet (OPTIONAL) */
- int (*mcast) (struct eth_device*, u32 ip, u8 set);
- /* DRIVER: Function to change ethernet MAC address */
- int (*write_hwaddr) (struct eth_device*);
- /* CORE: Next device in the linked list of devices managed by net core */
- struct eth_device *next;
- /* CORE: Device index */
- int index;
- /* DRIVER: Driver's private data */
- void *priv;
-};
-
-This structure defines the particular driver, though also contains elements that
-should not be exposed to the driver, like core state.
-
-Small, but important part of the networking subsystem is the PHY management
-layer, whose drivers are contained in drivers/net/phy. These drivers register in
-a very similar manner to network drivers, by calling "phy_register()" with the
-argument of "struct phy_driver":
-
-struct phy_driver {
- /* DRIVER: Name of the PHY driver */
- char *name;
- /* DRIVER: UID of the PHY driver */
- unsigned int uid;
- /* DRIVER: Mask for UID of the PHY driver */
- unsigned int mask;
- /* DRIVER: MMDS of the PHY driver */
- unsigned int mmds;
- /* DRIVER: Features the PHY driver supports */
- u32 features;
- /* DRIVER: Initialize the PHY hardware */
- int (*probe)(struct phy_device *phydev);
- /* DRIVER: Reconfigure the PHY hardware */
- int (*config)(struct phy_device *phydev);
- /* DRIVER: Turn on the PHY hardware, allow it to send/receive */
- int (*startup)(struct phy_device *phydev);
- /* DRIVER: Turn off the PHY hardware */
- int (*shutdown)(struct phy_device *phydev);
- /* CORE: Allows this driver to be part of list of drivers */
- struct list_head list;
-};
-
-II) Approach
-------------
-
-To convert the elements of network subsystem to proper driver model method, the
-"struct eth_device" will have to be split into multiple components. The first
-will be a structure defining the driver operations:
-
-struct eth_driver_ops {
- int (*init)(struct instance*, bd_t*);
- int (*send)(struct instance*, void *packet, int length);
- int (*recv)(struct instance*);
- void (*halt)(struct instance*);
- int (*mcast)(struct instance*, u32 ip, u8 set);
- int (*write_hwaddr)(struct instance*);
-};
-
-Next, there'll be platform data which will be per-driver and will replace the
-"priv" part of "struct eth_device". Last part will be the per-device core state.
-
-With regards to the PHY part of the API, the "struct phy_driver" is almost ready
-to be used with the new driver model approach. The only change will be the
-replacement of per-driver initialization functions and removal of
-"phy_register()" function in favor or driver model approach.
-
-III) Analysis of in-tree drivers
---------------------------------
-
- drivers/net/4xx_enet.c
- ----------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/altera_tse.c
- ------------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/armada100_fec.c
- ---------------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/at91_emac.c
- -----------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/ax88180.c
- ---------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/ax88796.c
- ---------------------
-
- This file contains a components of the NE2000 driver, implementing only
- different parts on the NE2000 clone AX88796. This being no standalone driver,
- no conversion will be done here.
-
- drivers/net/bfin_mac.c
- ----------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/calxedaxgmac.c
- --------------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/cs8900.c
- --------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/davinci_emac.c
- --------------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/dc2114x.c
- ---------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/designware.c
- ------------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/dm9000x.c
- ---------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/dnet.c
- ------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/e1000.c
- -------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/e1000_spi.c
- -----------------------
-
- Driver for the SPI bus integrated on the Intel E1000. This is not part of the
- network stack.
-
- drivers/net/eepro100.c
- ----------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/enc28j60.c
- ----------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/ep93xx_eth.c
- ------------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/ethoc.c
- -------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/fec_mxc.c
- ---------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/fsl_mcdmafec.c
- --------------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/fsl_mdio.c
- ----------------------
-
- This file contains driver for FSL MDIO interface, which is not part of the
- networking stack.
-
- drivers/net/ftgmac100.c
- -----------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/ftmac100.c
- ----------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/greth.c
- -------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/inca-ip_sw.c
- ------------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/ks8695eth.c
- -----------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/lan91c96.c
- ----------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/macb.c
- ------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/mcffec.c
- --------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/mcfmii.c
- --------------------
-
- This file contains MII interface driver for MCF FEC.
-
- drivers/net/mpc512x_fec.c
- -------------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/mpc5xxx_fec.c
- -------------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/mvgbe.c
- -------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/natsemi.c
- ---------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/ne2000_base.c
- -------------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process. This driver contains the core
- implementation of NE2000, which needs a few external functions, implemented by
- AX88796, NE2000 etc.
-
- drivers/net/ne2000.c
- --------------------
-
- This file implements external functions necessary for native NE2000 compatible
- networking card to work.
-
- drivers/net/netconsole.c
- ------------------------
-
- This is actually an STDIO driver.
-
- drivers/net/ns8382x.c
- ---------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/pcnet.c
- -------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/plb2800_eth.c
- -------------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/rtl8139.c
- ---------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/rtl8169.c
- ---------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/sh_eth.c
- --------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/smc91111.c
- ----------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/smc911x.c
- ---------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/tsec.c
- ------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/tsi108_eth.c
- ------------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/uli526x.c
- ---------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/vsc7385.c
- ---------------------
-
- This is a driver that only uploads firmware to a switch. This is not subject
- of conversion.
-
- drivers/net/xilinx_axi_emac.c
- -----------------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
-
- drivers/net/xilinx_emaclite.c
- -----------------------------
-
- This driver uses the standard new networking API, therefore there should be no
- obstacles throughout the conversion process.
+++ /dev/null
-The U-Boot Driver Model Project
-===============================
-PCI subsystem analysis
-======================
-
-Pavel Herrmann <morpheus.ibis@gmail.com>
-2012-03-17
-
-I) Overview
------------
-
- U-Boot already supports multiple PCI busses, stored in a linked-list of
- pci_controller structures. This structure contains generic driver data, bus
- interface operations and private data for the driver.
-
- Bus interface operations for PCI are (names are self-explanatory):
-
- read_byte()
- read_word()
- read_dword()
- write_byte()
- write_word()
- write_dword()
-
- Each driver has to implement dword operations, and either implement word and
- byte operations, or use shared $operation_config_$type_via_dword (eg.
- read_config_byte_via_dword and similar) function. These functions are used
- for config space I/O (read_config_dword and similar functions of the PCI
- subsystem), which is used to configure the connected devices for standard MMIO
- operations. All data transfers by respective device drivers are then done by
- MMIO
-
- Each driver also defines a separate init function, which has unique symbol
- name, and thus more drivers can be compiled in without colliding. This init
- function is typically called from pci_init_board(), different for each
- particular board.
-
- Some boards also define a function called fixup_irq, which gets called after
- scanning the PCI bus for devices, and should dismiss any interrupts.
-
- Several drivers are also located in arch/ and should be moved to drivers/pci.
-
-II) Approach
-------------
-
- The pci_controller structure needs to be broken down to fit the new driver
- model. Due to a large number of members, this will be done through three
- distinct accessors, one for memory regions, one for config table and one for
- everything else. That will make the pci_ops structure look like this:
-
- struct pci_ops {
- int (*read_byte)(struct instance *bus, pci_dev_t *dev, int addr,
- u8 *buf);
- int (*read_word)(struct instance *bus, pci_dev_t *dev, int addr,
- u16 *buf);
- int (*read_dword)(struct instance *bus, pci_dev_t *dev, int addr,
- u32 *buf);
- int (*write_byte)(struct instance *bus, pci_dev_t *dev, int addr,
- u8 val);
- int (*write_byte)(struct instance *bus, pci_dev_t *dev, int addr,
- u8 val);
- int (*write_dword)(struct instance *bus, pci_dev_t *dev, int addr,
- u32 val);
- void (*fixup_irq)(struct instance *bus, pci_dev_t *dev);
- struct pci_region* (*get_region)(struct instance *, uint num);
- struct pci_config_table* (*get_cfg_table)(struct instance *bus);
- uint (*get_option)(struct instance * bus, enum pci_option_code op);
- }
-
- enum pci_option_code {
- PCI_OPT_BUS_NUMBER=0,
- PCI_OPT_REGION_COUNT,
- PCI_OPT_INDIRECT_TYPE,
- PCI_OPT_AUTO_MEM,
- PCI_OPT_AUTO_IO,
- PCI_OPT_AUTO_PREFETCH,
- PCI_OPT_AUTO_FB,
- PCI_OPT_CURRENT_BUS,
- PCI_OPT_CFG_ADDR,
- }
-
- The return value for get_option will be an unsigned integer value for any
- option code. If the option currently is a pointer to pci_region, it will
- return an index for get_region function. Special case has to be made for
- PCI_OPT_CFG_ADDR, which should be interpreted as a pointer, but it is only
- used for equality in find_hose_by_cfg_addr, and thus can be returned as an
- uint. Other function using cfg_addr value are read/write functions for
- specific drivers (especially ops for indirect bridges), and thus have access
- to private_data of the driver instance.
-
- The config table accessor will return a pointer to a NULL-terminated array of
- pci_config_table, which is supplied by the board in platform_data, or NULL if
- the board didn't specify one. This table is used to override PnP
- auto-initialization, or to specific initialization functions for non-PNP
- devices.
-
- Transparent PCI-PCI bridges will get their own driver, and will forward all
- operations to operations of their parent bus. This however makes it
- impossible to use instances to identify devices, as not all devices will be
- directly visible to the respective bus driver.
-
- Init functions of controller drivers will be moved to their respective
- probe() functions, in accordance to the driver model.
-
- The PCI core will handle all mapping functions currently found in pci.c, as
- well as proxy functions for read/write operations of the drivers. The PCI
- core will also handle bus scanning and device configuration.
-
- The PnP helper functions currently in pci_auto.c will also be a part of PCI
- core, but they will be exposed only to PCI controller drivers, not to other
- device drivers.
-
- The PCI API for device drivers will remain largely unchanged, most drivers
- will require no changes at all, and all modifications will be limited to
- changing the pci_controlle into instance*.
-
-III) Analysis of in-tree drivers
---------------------------------
-
- A) drivers in drivers/pci/
- --------------------------
-
- pci_indirect.c
- --------------
- Shared driver for indirect PCI bridges, several CONFIG macros - will
- require significant cleanup.
-
- pci_sh4.c
- ---------
- Shared init function for SH4 drivers, uses dword for read/write ops.
-
- pci_sh7751.c
- ------------
- Standard driver, uses SH4 shared init.
-
- pci_sh7780.c
- ------------
- Standard driver, uses SH4 shared init.
-
- tsi108_pci.c
- ------------
- Standard driver, uses dword for read/write ops.
-
- fsl_pci_init.c
- --------------
- Driver for PCI and PCI-e, uses indirect functions.
-
- pci_ftpci100.c
- --------------
- Standard driver, uses indirect functions, has separate scan/setup
- functions.
-
- B) driver in arch/
- ------------------
-
- x86/lib/pci_type1.c
- -------------------
- Standard driver, specifies all read/write functions separately.
-
- m68k/cpu/mcf5445x/pci.c
- -----------------------
- Standard driver, specifies all read/write functions separately.
-
- m68k/cpu/mcf547x_8x/pci.c
- -------------------------
- Standard driver, specifies all read/write functions separately.
-
- powerpc/cpu/mpc824x/pci.c
- -------------------------
- Standard driver, uses indirect functions, does not setup HW.
-
- powerpc/cpu/mpc8260/pci.c
- -------------------------
- Standard driver, uses indirect functions.
-
- powerpc/cpu/ppc4xx/4xx_pci.c
- ----------------------------
- Standard driver, uses indirect functions.
-
- powerpc/cpu/ppc4xx/4xx_pcie.c
- -----------------------------
- PCI-e driver, specifies all read/write functions separately.
-
- powerpc/cpu/mpc83xx/pci.c
- -------------------------
- Standard driver, uses indirect functions.
-
- powerpc/cpu/mpc83xx/pcie.c
- --------------------------
- PCI-e driver, specifies all read/write functions separately.
-
- powerpc/cpu/mpc5xxx/pci_mpc5200.c
- ---------------------------------
- Standard driver, uses dword for read/write ops.
-
- powerpc/cpu/mpc512x/pci.c
- -------------------------
- Standard driver, uses indirect functions.
-
- powerpc/cpu/mpc85xx/pci.c
- -------------------------
- Standard driver, uses indirect functions, has two busses.
-
- C) drivers in board/
- --------------------
-
- eltec/elppc/pci.c
- -----------------
- Standard driver, uses indirect functions.
-
- amirix/ap1000/pci.c
- -------------------
- Standard driver, specifies all read/write functions separately.
-
- prodrive/p3mx/pci.c
- -------------------
- Standard driver, uses dword for read/write ops, has two busses.
-
- esd/cpci750/pci.c
- -----------------
- Standard driver, uses dword for read/write ops, has two busses.
-
- esd/common/pci.c
- ----------------
- Standard driver, uses dword for read/write ops.
-
- dave/common/pci.c
- -----------------
- Standard driver, uses dword for read/write ops.
-
- ppmc7xx/pci.c
- -------------
- Standard driver, uses indirect functions.
-
- Marvell/db64360/pci.c
- ---------------------
- Standard driver, uses dword for read/write ops, has two busses.
-
- Marvell/db64460/pci.c
- ---------------------
- Standard driver, uses dword for read/write ops, has two busses.
-
- evb64260/pci.c
- --------------
- Standard driver, uses dword for read/write ops, has two busses.
-
- armltd/integrator/pci.c
- -----------------------
- Standard driver, specifies all read/write functions separately.
-
- All drivers will be moved to drivers/pci. Several drivers seem
- similar/identical, especially those located under board, and may be merged
- into one.
+++ /dev/null
-The U-Boot Driver Model Project
-===============================
-PCMCIA analysis
-===============
-Viktor Krivak <viktor.krivak@gmail.com>
-2012-03-17
-
-I) Overview
------------
-
- U-boot implements only 2 methods to interoperate with pcmcia. One to turn
- device on and other to turn device off. Names of these methods are usually
- pcmcia_on() and pcmcia_off() without any parameters. Some files in driver
- directory implements only internal API. These methods aren't used outside
- driver directory and they are not converted to new driver model.
-
-II) Approach
------------
-
- 1) New API
- ----------
-
- Current API is preserved and all internal methods are hiden.
-
- struct ops {
- void (*pcmcia_on)(struct instance *i);
- void (*pcmcia_off)(struct instance *i);
- }
-
- 2) Conversion
- -------------
-
- In header file pcmcia.h are some other variables which are used for
- additional configuration. But all have to be moved to platform data or to
- specific driver implementation.
-
- 3) Platform data
- ----------------
-
- Many boards have custom implementation of internal API. Pointers to these
- methods are stored in platform_data. But the most implementations for Intel
- 82365 and compatible PC Card controllers and Yenta-compatible
- PCI-to-CardBus controllers implement whole API per board. In these cases
- pcmcia_on() and pcmcia_off() behave only as wrappers and call specific
- board methods.
-
-III) Analysis of in-tree drivers
---------------------------------
-
- i82365.c
- --------
- Driver methods have different name i82365_init() and i82365_exit but
- all functionality is the same. Board files board/atc/ti113x.c and
- board/cpc45/pd67290.c use their own implementation of these method.
- In this case all methods in driver behave only as wrappers.
-
- marubun_pcmcia.c
- ----------------
- Meets standard API behaviour. Simple conversion.
-
- mpc8xx_pcmcia.c
- ---------------
- Meets standard API behaviour. Simple conversion.
-
- rpx_pcmcia.c
- ------------
- Implements only internal API used in other drivers. Non of methods
- implemented here are used outside driver model.
-
- ti_pci1410a.c
- -------------
- Has different API but methods in this file are never called. Probably
- dead code.
-
- tqm8xx_pcmcia.c
- ---------------
- Implements only internal API used in other drivers. Non of methods
- implemented here are used outside driver model.
+++ /dev/null
-The U-Boot Driver Model Project
-===============================
-POWER analysis
-==============
-Viktor Krivak <viktor.krivak@gmail.com>
-2012-03-09
-
-I) Overview
------------
-
- 1) Actual state
- ---------------
-
- At this moment power doesn't contain API. There are many methods for
- initialization of some board specific functions but only few does what is
- expected. Basically only one file contains something meaningful for this
- driver.
-
- 2) Current implementation
- -------------------------
-
- In file twl6030.c are methods twl6030_stop_usb_charging() and
- twl6030_start_usb_charging() for start and stop charging from USB. There are
- also methods to get information about battery state and initialization of
- battery charging. Only these methods are used in converted API.
-
-
-II) Approach
-------------
-
- 1) New API
- ----------
-
- New API implements only functions specific for managing power. All board
- specific init methods are moved to other files. Name of methods are
- self-explanatory.
-
- struct ops {
- void (*start_usb_charging)(struct instance *i);
- void (*stop_usb_charging)(struct instance *i);
- int (*get_battery_current)(struct instance *i);
- int (*get_battery_voltage)(struct instance *i);
- void (*init_battery_charging)(struct instance *i);
- }
-
- 2) Conversions of other methods
- -------------------------------
-
- Methods that can't be converted to new API are moved to board file or to
- special file for board hacks.
-
-III) Analysis of in-tree drivers
---------------------------------
-
- ftpmu010.c
- ----------
- All methods of this file are moved to another location.
- void ftpmu010_32768osc_enable(void): Move to boards hacks
- void ftpmu010_mfpsr_select_dev(unsigned int dev): Move to board file
- arch/nds32/lib/board.c
- void ftpmu010_mfpsr_diselect_dev(unsigned int dev): Dead code
- void ftpmu010_dlldis_disable(void): Dead code
- void ftpmu010_sdram_clk_disable(unsigned int cr0): Move to board file
- arch/nds32/lib/board.c
- void ftpmu010_sdramhtc_set(unsigned int val): Move to board file
- arch/nds32/lib/board.c
-
- twl4030.c
- ---------
- All methods of this file are moved to another location.
- void twl4030_power_reset_init(void): Move to board hacks
- void twl4030_pmrecv_vsel_cfg(u8 vsel_reg, u8 vsel_val, u8 dev_grp,
- u8 dev_grp_sel): Move to board hacks
- void twl4030_power_init(void): Move to board hacks
- void twl4030_power_mmc_init(void): Move to board hacks
-
- twl6030.c
- ---------
- Some methods are converted to new API and rest are moved to another location.
- void twl6030_stop_usb_charging(void): Convert to new API
- void twl6030_start_usb_charging(void): Convert to new API
- int twl6030_get_battery_current(void): Convert to new API
- int twl6030_get_battery_voltage(void): Convert to new API
- void twl6030_init_battery_charging(void): Convert to new API
- void twl6030_power_mmc_init(): Move to board file
- drivers/mmc/omap_hsmmc.c
- void twl6030_usb_device_settings(): Move to board file
- drivers/usb/musb/omap3.c
+++ /dev/null
-=============================
-RTC device subsystem analysis
-=============================
-
-Tomas Hlavacek <tmshlvck@gmail.com>
-2012-03-10
-
-I) Overview
------------
-
-U-Boot currently implements one common API for RTC devices. The interface
-is defined in include/rtc.h and comprises of functions and structures:
-
- struct rtc_time {
- int tm_sec;
- int tm_min;
- int tm_hour;
- int tm_mday;
- int tm_mon;
- int tm_year;
- int tm_wday;
- int tm_yday;
- int tm_isdst;
- };
-
- int rtc_get (struct rtc_time *);
- int rtc_set (struct rtc_time *);
- void rtc_reset (void);
-
-The functions are implemented by a proper device driver in drivers/rtc
-directory and the driver to be compiled in is selected in a Makefile.
-Drivers are mutually exclusive.
-
-Drivers depends on date code in drivers/rtc/date.c and naturally on board
-specific data.
-
-II) Approach
-------------
-
- 1) New API
- ----------
- In the UDM each rtc driver would register itself by a function
-
- int rtc_device_register(struct instance *i,
- struct rtc_device_ops *o);
-
- The structure being defined as follows:
-
- struct rtc_device_ops {
- int (*get_time)(struct instance *i, struct rtc_time *t);
- int (*set_time)(struct instance *i, struct rtc_time *t);
- int (*reset)(struct instance *i);
- };
-
-
- 2) Conversion thougths
- ----------------------
- U-Boot RTC drivers exports the same functions and therefore the conversion
- of the drivers is straight-forward. There is no initialization needed.
-
-
-III) Analysis of in-tree drivers
---------------------------------
-
- drivers/rtc/rv3029.c
- --------------------
- The driver is standard rtc. Simple conversion is possible.
-
-
- drivers/rtc/s3c24x0_rtc.c
- -------------------------
- The driver is standard rtc. Simple conversion is possible.
-
-
- drivers/rtc/pt7c4338.c
- ----------------------
- The driver is standard rtc. Simple conversion is possible.
-
-
- drivers/rtc/mvrtc.c
- -------------------
- The driver is standard rtc. Simple conversion is possible.
-
-
- drivers/rtc/ftrtc010.c
- ----------------------
- The driver is standard rtc. Simple conversion is possible.
-
-
- drivers/rtc/mpc5xxx.c
- ---------------------
- The driver is standard rtc. Simple conversion is possible.
-
-
- drivers/rtc/ds164x.c
- --------------------
- The driver is standard rtc. Simple conversion is possible.
-
-
- drivers/rtc/rs5c372.c
- ---------------------
- The driver is standard rtc. Simple conversion is possible.
-
-
- drivers/rtc/m41t94.c
- --------------------
- The driver is standard rtc. Simple conversion is possible.
-
-
- drivers/rtc/mc13xxx-rtc.c
- -------------------------
- The driver is standard rtc. Simple conversion is possible.
-
-
- drivers/rtc/mcfrtc.c
- --------------------
- The driver is standard rtc. Simple conversion is possible.
-
-
- drivers/rtc/davinci.c
- ---------------------
- The driver is standard rtc. Simple conversion is possible.
-
-
- drivers/rtc/rx8025.c
- --------------------
- The driver is standard rtc. Simple conversion is possible.
-
-
- drivers/rtc/bfin_rtc.c
- ----------------------
- The driver is standard rtc. Simple conversion is possible.
-
-
- drivers/rtc/m41t62.c
- --------------------
- The driver is standard rtc. Simple conversion is possible.
-
-
- drivers/rtc/ds1306.c
- --------------------
- The driver is standard rtc. Simple conversion is possible.
-
-
- drivers/rtc/mpc8xx.c
- --------------------
- The driver is standard rtc. Simple conversion is possible.
-
-
- drivers/rtc/ds3231.c
- --------------------
- The driver is standard rtc. Simple conversion is possible.
-
-
- drivers/rtc/ds12887.c
- ---------------------
- The driver is standard rtc. Simple conversion is possible.
-
-
- drivers/rtc/ds1302.c
- --------------------
- The driver is standard rtc. Simple conversion is possible.
-
-
- drivers/rtc/ds1374.c
- --------------------
- The driver is standard rtc. Simple conversion is possible.
-
-
- drivers/rtc/ds174x.c
- --------------------
- The driver is standard rtc. Simple conversion is possible.
-
-
- drivers/rtc/m41t60.c
- --------------------
- The driver is standard rtc. Simple conversion is possible.
-
-
- drivers/rtc/m48t35ax.c
- ----------------------
- The driver is standard rtc. Simple conversion is possible.
-
-
- drivers/rtc/pl031.c
- -------------------
- The driver is standard rtc. Simple conversion is possible.
-
-
- drivers/rtc/x1205.c
- -------------------
- The driver is standard rtc. Simple conversion is possible.
-
-
- drivers/rtc/m41t11.c
- --------------------
- The driver is standard rtc. Simple conversion is possible.
-
-
- drivers/rtc/pcf8563.c
- ---------------------
- The driver is standard rtc. Simple conversion is possible.
-
-
- drivers/rtc/mk48t59.c
- ---------------------
- Macros needs cleanup. Besides that the driver is standard rtc.
- Simple conversion is possible.
-
-
- drivers/rtc/mxsrtc.c
- --------------------
- The driver is standard rtc. Simple conversion is possible.
-
-
- drivers/rtc/ds1307.c
- --------------------
- The driver is standard rtc. Simple conversion is possible.
-
-
- drivers/rtc/ds1556.c
- --------------------
- The driver is standard rtc. Simple conversion is possible.
-
-
- drivers/rtc/rtc4543.c
- ---------------------
- The driver is standard rtc. Simple conversion is possible.
-
-
- drivers/rtc/ds1337.c
- --------------------
- The driver is standard rtc. Simple conversion is possible.
-
-
- drivers/rtc/isl1208.c
- ---------------------
- The driver is standard rtc. Simple conversion is possible.
-
-
- drivers/rtc/max6900.c
- ---------------------
- The driver is standard rtc. Simple conversion is possible.
-
-
- drivers/rtc/mc146818.c
- ----------------------
- The driver is standard rtc. Simple conversion is possible.
-
-
- drivers/rtc/at91sam9_rtt.c
- --------------------------
- The driver is standard rtc. Simple conversion is possible.
+++ /dev/null
-The U-Boot Driver Model Project
-===============================
-Serial I/O analysis
-===================
-Marek Vasut <marek.vasut@gmail.com>
-2012-02-20
-
-I) Overview
------------
-
-The serial port support currently requires the driver to export the following
-functions:
-
- serial_putc() ...... Output a character
- serial_puts() ...... Output string, often done using serial_putc()
- serial_tstc() ...... Test if incoming character is in a buffer
- serial_getc() ...... Retrieve incoming character
- serial_setbrg() .... Configure port options
- serial_init() ...... Initialize the hardware
-
-The simpliest implementation, supporting only one port, simply defines these six
-functions and calls them. Such calls are scattered all around U-Boot, especiall
-serial_putc(), serial_puts(), serial_tstc() and serial_getc(). The serial_init()
-and serial_setbrg() are often called from platform-dependent places.
-
-It's important to consider current implementation of CONFIG_SERIAL_MULTI though.
-This resides in common/serial.c and behaves as a multiplexer for serial ports.
-This, by calling serial_assign(), allows user to switch I/O from one serial port
-to another. Though the environmental variables "stdin", "stdout", "stderr"
-remain set to "serial".
-
-These variables are managed by the IOMUX. This resides in common/iomux.c and
-manages all console input/output from U-Boot. For serial port, only one IOMUX is
-always registered, called "serial" and the switching of different serial ports
-is done by code in common/serial.c.
-
-On a final note, it's important to mention function default_serial_console(),
-which is platform specific and reports the default serial console for the
-platform, unless proper environment variable overrides this.
-
-II) Approach
-------------
-
-Drivers not using CONFIG_SERIAL_MULTI already will have to be converted to
-similar approach. The probe() function of a driver will call a function
-registering the driver with a STDIO subsystem core, stdio_device_register().
-
-The serial_init() function will now be replaced by probe() function of the
-driver, the rest of the components of the driver will be converted to standard
-STDIO driver calls. See [ UDM-stdio.txt ] for details.
-
-The serial_setbrg() function depends on global data pointer. This is wrong,
-since there is likely to be user willing to configure different baudrate on two
-different serial ports. The function will be replaced with STDIO's "conf()"
-call, with STDIO_CONFIG_SERIAL_BAUDRATE argument.
-
-III) Analysis of in-tree drivers
---------------------------------
-
- altera_jtag_uart.c
- ------------------
- No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
-
- altera_uart.c
- -------------
- No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
-
- arm_dcc.c
- ---------
- No support for CONFIG_SERIAL_MULTI. Simple conversion possible, unless used
- with CONFIG_ARM_DCC_MULTI. Then it registers another separate IOMUX.
-
- atmel_usart.c
- -------------
- No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
-
- mcfuart.c
- ---------
- No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
-
- ns16550.c
- ---------
- This driver seems complicated and certain consideration will need to be made
- during conversion. This driver is implemented in very universal manner,
- therefore it'll be necessary to properly design it's platform_data.
-
- opencores_yanu.c
- ----------------
- No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
-
- sandbox.c
- ---------
- No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
-
- serial.c
- --------
- This is a complementary part of NS16550 UART driver, see above.
-
- serial_imx.c
- ------------
- No support for CONFIG_SERIAL_MULTI. Simple conversion possible. This driver
- might be removed in favor of serial_mxc.c .
-
- serial_ks8695.c
- ---------------
- No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
-
- serial_max3100.c
- ----------------
- No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
-
- serial_mxc.c
- ------------
- No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
-
- serial_pl01x.c
- --------------
- No support for CONFIG_SERIAL_MULTI. Simple conversion possible, though this
- driver in fact contains two drivers in total.
-
- serial_pxa.c
- ------------
- This driver is a bit complicated, but due to clean support for
- CONFIG_SERIAL_MULTI, there are no expected obstructions throughout the
- conversion process.
-
- serial_s3c24x0.c
- ----------------
- This driver, being quite ad-hoc might need some work to bring back to shape.
-
- serial_s5p.c
- ------------
- No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
-
- serial_sa1100.c
- ---------------
- No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
-
- serial_sh.c
- -----------
- No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
-
- serial_xuartlite.c
- ------------------
- No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
-
- usbtty.c
- --------
- This driver seems very complicated and entangled with USB framework. The
- conversion might be complicated here.
-
- arch/powerpc/cpu/mpc512x/serial.c
- ---------------------------------
- This driver supports CONFIG_SERIAL_MULTI. This driver will need to be moved to
- proper place.
+++ /dev/null
-The U-Boot Driver Model Project
-===============================
-SPI analysis
-============
-Viktor Krivak <viktor.krivak@gmail.com>
-2012-03-03
-
-I) Overview
------------
-
- 1) The SPI driver
- -----------------
-
- At this moment U-Boot provides standard API that consist of 7 functions:
-
- void spi_init(void);
- struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode);
- void spi_free_slave(struct spi_slave *slave);
- int spi_claim_bus(struct spi_slave *slave);
- void spi_release_bus(struct spi_slave *slave);
- int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
- const void *dout, void *din, unsigned long flags);
- int spi_cs_is_valid(unsigned int bus, unsigned int cs);
- void spi_cs_activate(struct spi_slave *slave);
- void spi_cs_deactivate(struct spi_slave *slave);
- void spi_set_speed(struct spi_slave *slave, uint hz);
-
- Method spi_init() is usually empty. All necessary configuration are sets by
- spi_setup_slave(). But this configuration is usually stored only in memory.
- No real hardware sets are made. All hardware settings are provided by method
- spi_claim_bus(). This method claims the bus and it can't be claimed again
- until it's release. That's mean all calls of method spi_claim_bus() will
- fail. But lots of cpu implementation don't meet this behaviour.
- Method spi_release_bus() does exact opposite. It release bus directly by
- some hardware sets. spi_free_slave() only free memory allocated by
- spi_setup_slave(). Method spi_xfer() do actually read and write operation
- throw specified bus and cs. Other methods are self explanatory.
-
- 2) Current limitations
- ----------------------
-
- Theoretically at this moment api allows use more then one bus per device at
- the time. But in real this can be achieved only when all buses have their
- own base addresses in memory.
-
-
-II) Approach
-------------
-
- 1) Claiming bus
- ---------------
-
- The current api cannot be used because struct spi_slave have to be in
- private data. In that case user are prohibited to use different bus on one
- device at same time. But when base memory address for bus are different.
- It's possible make more instance of this driver. Otherwise it can't can be
- done because of hardware limitation.
-
- 2) API change
- -------------
-
- Method spi_init() is moved to probe. Methods spi_setup_slave() and
- spi_claim_bus() are joined to one method. This method checks if desired bus
- exists and is available then configure necessary hardware and claims bus.
- Method spi_release_bus() and spi_free_slave() are also joined to meet this
- new approach. Other function remain same. Only struct spi_slave was change
- to instance.
-
- struct ops {
- int (*spi_request_bus)(struct instance *i, unsigned int bus,
- unsigned int cs, unsigned int max_hz,
- unsigned int mode);
- void (*spi_release_bus)(struct instance *i);
- int (*spi_xfer) (struct instance *i, unsigned int bitlen,
- const void *dout, void *din, unsigned long flags);
- int (*spi_cs_is_valid)(struct instance *i, unsigned int bus,
- unsigned int cs);
- void (*spi_cs_activate)(struct instance *i);
- void (*spi_cs_deactivate)(struct instance *i);
- void (*spi_set_speed)(struct instance *i, uint hz);
- }
-
- 3) Legacy API
- -------------
-
- To easy conversion of the whole driver. Original and new api can exist next
- to each other. New API is designed to be only a wrapper that extracts
- necessary information from private_data and use old api. When driver can
- use more than one bus at the time. New API require multiple instance. One
- for each bus. In this case spi_slave have to be copied in each instance.
-
- 4) Conversion TIME-LINE
- -----------------------
-
- To prevent build corruption api conversion have to be processed in several
- independent steps. In first step all old API methods are renamed. After that
- new API and core function are implemented. Next step is conversion of all
- board init methods to set platform data. After all these steps it is possible
- to start conversion of all remaining calls. This procedure guarantees that
- build procedure and binaries are never broken.
-
-III) Analysis of in-tree drivers
---------------------------------
-
- altera_spi.c
- ------------
- All methods have designated structure. Simple conversion possible.
-
- andes_spi.c
- -----------
- All methods have designated structure. Simple conversion possible.
-
- andes_spi.h
- -----------
- Support file for andes_spi.c. No conversion is needed.
-
- armada100_spi.c
- ---------------
- All methods have designated structure. Simple conversion possible.
-
- atmel_dataflash_spi.c
- ---------------------
- Wrong placement. Will be moved to another location.
-
- atmel_spi.c
- -----------
- Supports more than one bus. Need some minor change.
-
- atmel_spi.h
- -----------
- Support file for andes_spi.c. No conversion is needed.
-
- bfin_spi.c
- ----------
- Supports more than one bus. Need some minor change.
-
- cf_spi.c
- --------
- Cooperate with some cpu specific methods from other files. Hard conversion.
-
- davinci_spi.c
- -------------
- All methods have designated structure. Simple conversion possible.
-
- davinci_spi.h
- -------------
- Support file for davinci_spi.h. No conversion is needed.
-
- fsl_espi.c
- ----------
- All methods have designated structure. Simple conversion possible.
-
- kirkwood_spi.c
- --------------
- All methods have designated structure. Simple conversion possible.
-
- mpc8xxx_spi.c
- -------------
- All methods have designated structure. Simple conversion possible.
-
- mpc52xx_spi.c
- -------------
- All methods have designated structure. Simple conversion possible.
-
- mxc_spi.c
- ---------
- All methods have designated structure. Simple conversion possible.
-
- mxs_spi.c
- ---------
- All methods have designated structure. Simple conversion possible.
-
- oc_tiny_spi.c
- -------------
- Supports more than one bus. Need some minor change.
-
- omap3_spi.c
- -----------
- Supports more than one bus. Need some minor change.
-
- omap3_spi.h
- -----------
- Support file for omap3_spi.c. No conversion is needed.
-
- sh_spi.c
- --------
- All methods have designated structure. Simple conversion possible.
-
- sh_spi.h
- --------
- Support file for sh_spi.h. No conversion is needed.
-
- soft_spi.c
- ----------
- Use many board specific method linked from other files. Need careful debugging.
-
- tegra2_spi.c
- ------------
- Some hardware specific problem when releasing bus.
+++ /dev/null
-The U-Boot Driver Model Project
-===============================
-I/O system analysis
-===================
-Marek Vasut <marek.vasut@gmail.com>
-2012-02-20
-
-I) Overview
------------
-
-The console input and output is currently done using the STDIO subsystem in
-U-Boot. The design of this subsystem is already flexible enough to be easily
-converted to new driver model approach. Minor changes will need to be done
-though.
-
-Each device that wants to register with STDIO subsystem has to define struct
-stdio_dev, defined in include/stdio_dev.h and containing the following fields:
-
-struct stdio_dev {
- int flags; /* Device flags: input/output/system */
- int ext; /* Supported extensions */
- char name[16]; /* Device name */
-
-/* GENERAL functions */
-
- int (*start) (void); /* To start the device */
- int (*stop) (void); /* To stop the device */
-
-/* OUTPUT functions */
-
- void (*putc) (const char c); /* To put a char */
- void (*puts) (const char *s); /* To put a string (accelerator) */
-
-/* INPUT functions */
-
- int (*tstc) (void); /* To test if a char is ready... */
- int (*getc) (void); /* To get that char */
-
-/* Other functions */
-
- void *priv; /* Private extensions */
- struct list_head list;
-};
-
-Currently used flags are DEV_FLAGS_INPUT, DEV_FLAGS_OUTPUT and DEV_FLAGS_SYSTEM,
-extensions being only one, the DEV_EXT_VIDEO.
-
-The private extensions are now used as a per-device carrier of private data and
-finally list allows this structure to be a member of linked list of STDIO
-devices.
-
-The STDIN, STDOUT and STDERR routing is handled by environment variables
-"stdin", "stdout" and "stderr". By configuring the variable to the name of a
-driver, functions of such driver are called to execute that particular
-operation.
-
-II) Approach
-------------
-
- 1) Similarity of serial, video and keyboard drivers
- ---------------------------------------------------
-
- All of these drivers can be unified under the STDIO subsystem if modified
- slightly. The serial drivers basically define both input and output functions
- and need function to configure baudrate. The keyboard drivers provide only
- input. On the other hand, video drivers provide output, but need to be
- configured in certain way. This configuration might be dynamic, therefore the
- STDIO has to be modified to provide such flexibility.
-
- 2) Unification of serial, video and keyboard drivers
- ----------------------------------------------------
-
- Every STDIO device would register a structure containing operation it supports
- with the STDIO core by calling:
-
- int stdio_device_register(struct instance *i, struct stdio_device_ops *o);
-
- The structure being defined as follows:
-
- struct stdio_device_ops {
- void (*putc)(struct instance *i, const char c);
- void (*puts)(struct instance *i, const char *s); /* OPTIONAL */
-
- int (*tstc)(struct instance *i);
- int (*getc)(struct instance *i);
-
- int (*init)(struct instance *i);
- int (*exit)(struct instance *i);
- int (*conf)(struct instance *i, enum stdio_config c, const void *data);
- };
-
- The "putc()" function will emit a character, the "puts()" function will emit a
- string. If both of these are set to NULL, the device is considered STDIN only,
- aka input only device.
-
- The "getc()" retrieves a character from a STDIN device, while "tstc()" tests
- if there is a character in the buffer of STDIN device. In case these two are
- set to NULL, this device is STDOUT / STDERR device.
-
- Setting all "putc()", "puts()", "getc()" and "tstc()" calls to NULL isn't an
- error condition, though such device does nothing. By instroducing tests for
- these functions being NULL, the "flags" and "ext" fields from original struct
- stdio_dev can be eliminated.
-
- The "init()" and "exit()" calls are replacement for "start()" and "exit()"
- calls in the old approach. The "priv" part of the old struct stdio_dev will be
- replaced by common private data in the driver model and the struct list_head
- list will be eliminated by introducing common STDIO core, that tracks all the
- STDIO devices.
-
- Lastly, the "conf()" call will allow the user to configure various options of
- the driver. The enum stdio_config contains all possible configuration options
- available to the STDIO devices, const void *data being the argument to be
- configured. Currently, the enum stdio_config will contain at least the
- following options:
-
- enum stdio_config {
- STDIO_CONFIG_SERIAL_BAUDRATE,
- };
-
- 3) Transformation of stdio routing
- ----------------------------------
-
- By allowing multiple instances of drivers, the environment variables "stdin",
- "stdout" and "stderr" can no longer be set to the name of the driver.
- Therefore the STDIO core, tracking all of the STDIO devices in the system will
- need to have a small amount of internal data for each device:
-
- struct stdio_device_node {
- struct instance *i;
- struct stdio_device_ops *ops;
- uint8_t id;
- uint8_t flags;
- struct list_head list;
- }
-
- The "id" is the order of the instance of the same driver. The "flags" variable
- allows multiple drivers to be used at the same time and even for different
- purpose. The following flags will be defined:
-
- STDIO_FLG_STDIN ..... This device will be used as an input device. All input
- from all devices with this flag set will be received
- and passed to the upper layers.
- STDIO_FLG_STDOUT .... This device will be used as an output device. All
- output sent to stdout will be routed to all devices
- with this flag set.
- STDIO_FLG_STDERR .... This device will be used as an standard error output
- device. All output sent to stderr will be routed to
- all devices with this flag set.
-
- The "list" member of this structure allows to have a linked list of all
- registered STDIO devices.
-
-III) Analysis of in-tree drivers
---------------------------------
-
-For in-depth analysis of serial port drivers, refer to [ UDM-serial.txt ].
-For in-depth analysis of keyboard drivers, refer to [ UDM-keyboard.txt ].
-For in-depth analysis of video drivers, refer to [ UDM-video.txt ].
-
- arch/blackfin/cpu/jtag-console.c
- --------------------------------
- This driver is a classic STDIO driver, no problem with conversion is expected.
-
- board/mpl/pati/pati.c
- ---------------------
- This driver registers with the STDIO framework, though it uses a lot of ad-hoc
- stuff which will need to be sorted out.
-
- board/netphone/phone_console.c
- ------------------------------
- This driver is a classic STDIO driver, no problem with conversion is expected.
-
- drivers/net/netconsole.c
- ------------------------
- This driver is a classic STDIO driver, no problem with conversion is expected.
-
-IV) Other involved files (To be removed)
-----------------------------------------
-
-common/cmd_console.c
-common/cmd_log.c
-common/cmd_terminal.c
-common/console.c
-common/fdt_support.c
-common/iomux.c
-common/lcd.c
-common/serial.c
-common/stdio.c
-common/usb_kbd.c
-doc/README.iomux
+++ /dev/null
-The U-Boot Driver Model Project
-===============================
-TPM system analysis
-===================
-Marek Vasut <marek.vasut@gmail.com>
-2012-02-23
-
-I) Overview
------------
-
-There is currently only one TPM chip driver available and therefore the API
-controlling it is very much based on this. The API is very simple:
-
- int tis_open(void);
- int tis_close(void);
- int tis_sendrecv(const u8 *sendbuf, size_t send_size,
- u8 *recvbuf, size_t *recv_len);
-
-The command operating the TPM chip only provides operations to send and receive
-bytes from the chip.
-
-II) Approach
-------------
-
-The API can't be generalised too much considering there's only one TPM chip
-supported. But it's a good idea to split the tis_sendrecv() function in two
-functions. Therefore the new API will use register the TPM chip by calling:
-
- tpm_device_register(struct instance *i, const struct tpm_ops *ops);
-
-And the struct tpm_ops will contain the following members:
-
- struct tpm_ops {
- int (*tpm_open)(struct instance *i);
- int (*tpm_close)(struct instance *i);
- int (*tpm_send)(const uint8_t *buf, const size_t size);
- int (*tpm_recv)(uint8_t *buf, size_t *size);
- };
-
-The behaviour of "tpm_open()" and "tpm_close()" will basically copy the
-behaviour of "tis_open()" and "tis_close()". The "tpm_send()" will be based on
-the "tis_senddata()" and "tis_recv()" will be based on "tis_readresponse()".
-
-III) Analysis of in-tree drivers
---------------------------------
-
-There is only one in-tree driver present, the "drivers/tpm/generic_lpc_tpm.c",
-which will be simply converted as outlined in previous chapter.
+++ /dev/null
-==================================
-TWserial device subsystem analysis
-==================================
-
-Tomas Hlavacek<tmshlvck@gmail.com>
-2012-03-21
-
-I) Overview
------------
-
-U-Boot currently implements one common API for TWSerial devices. The interface
-is defined in include/tws.h and comprises of functions:
-
- int tws_read(uchar *buffer, int len);
- int tws_write(uchar *buffer, int len);
-
-The functions are implemented by a proper device driver in drivers/twserial
-directory and the driver to be compiled in is selected in a Makefile. There is
-only one driver present now.
-
-The driver depends on ad-hoc code in board specific data, namely functions:
-
- void tws_ce(unsigned bit);
- void tws_wr(unsigned bit);
- void tws_clk(unsigned bit);
- void tws_data(unsigned bit);
- unsigned tws_data_read(void);
- void tws_data_config_output(unsigned output);
-
-implemented in include/configs/inka4x0.h .
-
-II) Approach
-------------
-
- U-Boot TWserial drivers exports two simple functions and therefore the conversion
- of the driver and creating a core for it is not needed. It should be consolidated
- with include/configs/inka4x0.h and taken to the misc/ dir.
-
-
-III) Analysis of in-tree drivers
---------------------------------
-
- drivers/twserial/soft_tws.c
- ---------------------------
- The driver is the only TWserial driver. The ad-hoc part in
- include/configs/inka4x0.h and the core soft_tws driver should be consolidated
- to one compact driver and moved to misc/ .
+++ /dev/null
-The U-Boot Driver Model Project
-===============================
-USB analysis
-============
-Marek Vasut <marek.vasut@gmail.com>
-2012-02-16
-
-I) Overview
------------
-
- 1) The USB Host driver
- ----------------------
- There are basically four or five USB host drivers. All such drivers currently
- provide at least the following fuctions:
-
- usb_lowlevel_init() ... Do the initialization of the USB controller hardware
- usb_lowlevel_stop() ... Do the shutdown of the USB controller hardware
-
- usb_event_poll() ...... Poll interrupt from USB device, often used by KBD
-
- submit_control_msg() .. Submit message via Control endpoint
- submit_int_msg() ...... Submit message via Interrupt endpoint
- submit_bulk_msg() ..... Submit message via Bulk endpoint
-
-
- This allows for the host driver to be easily abstracted.
-
- 2) The USB hierarchy
- --------------------
-
- In the current implementation, the USB Host driver provides operations to
- communicate via the USB bus. This is realised by providing access to a USB
- root port to which an USB root hub is attached. The USB bus is scanned and for
- each newly found device, a struct usb_device is allocated. See common/usb.c
- and include/usb.h for details.
-
-II) Approach
-------------
-
- 1) The USB Host driver
- ----------------------
-
- Converting the host driver will follow the classic driver model consideration.
- Though, the host driver will have to call a function that registers a root
- port with the USB core in it's probe() function, let's call this function
-
- usb_register_root_port(&ops);
-
- This will allow the USB core to track all available root ports. The ops
- parameter will contain structure describing operations supported by the root
- port:
-
- struct usb_port_ops {
- void (*usb_event_poll)();
- int (*submit_control_msg)();
- int (*submit_int_msg)();
- int (*submit_bulk_msg)();
- }
-
- 2) The USB hierarchy and hub drivers
- ------------------------------------
-
- Converting the USB heirarchy should be fairy simple, considering the already
- dynamic nature of the implementation. The current usb_hub_device structure
- will have to be converted to a struct instance. Every such instance will
- contain components of struct usb_device and struct usb_hub_device in it's
- private data, providing only accessors in order to properly encapsulate the
- driver.
-
- By registering the root port, the USB framework will instantiate a USB hub
- driver, which is always present, the root hub. The root hub and any subsequent
- hub instance is represented by struct instance and it's private data contain
- amongst others common bits from struct usb_device.
-
- Note the USB hub driver is partly defying the usual method of registering a
- set of callbacks to a particular core driver. Instead, a static set of
- functions is defined and the USB hub instance is passed to those. This creates
- certain restrictions as of how the USB hub driver looks, but considering the
- specification for USB hub is given and a different type of USB hub won't ever
- exist, this approach is ok:
-
- - Report how many ports does this hub have:
- uint get_nr_ports(struct instance *hub);
- - Get pointer to device connected to a port:
- struct instance *(*get_child)(struct instance *hub, int port);
- - Instantiate and configure device on port:
- struct instance *(*enum_dev_on_port)(struct instance *hub, int port);
-
- 3) USB device drivers
- ---------------------
-
- The USB device driver, in turn, will have to register various ops structures
- with certain cores. For example, USB disc driver will have to register it's
- ops with core handling USB discs etc.
+++ /dev/null
-The U-Boot Driver Model Project
-===============================
-Video output analysis
-=====================
-Marek Vasut <marek.vasut@gmail.com>
-2012-02-20
-
-I) Overview
------------
-
-The video drivers are most often registered with video subsystem. This subsystem
-often expects to be allowed access to framebuffer of certain parameters. This
-subsystem also provides calls for STDIO subsystem to allow it to output
-characters on the screen. For this part, see [ UDM-stdio.txt ].
-
-Therefore the API has two parts, the video driver part and the part where the
-video driver core registers with STDIO API.
-
-The video driver part will follow the current cfb_console approach, though
-allowing it to be more dynamic.
-
-II) Approach
-------------
-
-Registering the video driver into the video driver core is done by calling the
-following function from the driver probe() function:
-
- video_device_register(struct instance *i, GraphicDevice *gd);
-
-Because the video driver core is in charge or rendering characters as well as
-bitmaps on the screen, it will in turn call stdio_device_register(i, so), where
-"i" is the same instance as the video driver's one. But "so" will be special
-static struct stdio_device_ops handling the character output.
-
-
-III) Analysis of in-tree drivers
---------------------------------
-
- arch/powerpc/cpu/mpc8xx/video.c
- -------------------------------
- This driver copies the cfb_console [ see drivers/video/cfb_console.c ]
- approach and acts only as a STDIO device. Therefore there are currently two
- possible approaches, first being the conversion of this driver to usual STDIO
- device and second, long-term one, being conversion of this driver to video
- driver that provides console.
-
- arch/x86/lib/video.c
- --------------------
- This driver registers two separate STDIO devices and should be therefore
- converted as such.
-
- board/bf527-ezkit/video.c
- -------------------------
- This driver seems bogus as it behaves as STDIO device, but provides no input
- or output capabilities. It relies on DEV_EXT_VIDEO, which is no longer in use
- or present otherwise than as a dead code/define.
-
- board/bf533-stamp/video.c
- -------------------------
- This driver seems bogus as it behaves as STDIO device, but provides no input
- or output capabilities. It relies on DEV_EXT_VIDEO, which is no longer in use
- or present otherwise than as a dead code/define.
-
- board/bf548-ezkit/video.c
- -------------------------
- This driver seems bogus as it behaves as STDIO device, but provides no input
- or output capabilities. It relies on DEV_EXT_VIDEO, which is no longer in use
- or present otherwise than as a dead code/define.
-
- board/cm-bf548/video.c
- ----------------------
- This driver seems bogus as it behaves as STDIO device, but provides no input
- or output capabilities. It relies on DEV_EXT_VIDEO, which is no longer in use
- or present otherwise than as a dead code/define.
+++ /dev/null
-The U-Boot Driver Model Project
-===============================
-Watchdog device subsystem analysis
-==================================
-
-Tomas Hlavacek <tmshlvck@gmail.com>
-2012-03-09
-
-I) Overview
------------
-
-U-Boot currently implements an API for HW watchdog devices as explicit drivers
-in drivers/watchdog directory. There are also drivers for both hardware and
-software watchdog on particular CPUs implemented in arch/*/cpu/*/cpu.c. There
-are macros in include/watchdog.h that selects between SW and HW watchdog and
-assembly SW implementation.
-
-The current common interface comprises of one set out of these two possible
-variants:
-
- 1)
- void watchdog_reset(void);
- int watchdog_disable(void);
- int watchdog_init(void);
-
- 2)
- void hw_watchdog_reset(void);
- void hw_watchdog_init(void);
-
-The watchdog implementations are also spread through board/*/*.c that in
-some cases. The API and semantics is in most cases same as the above
-mentioned common functions.
-
-
-II) Approach
-------------
-
- 1) New API
- ----------
-
- In the UDM each watchdog driver would register itself by a function
-
- int watchdog_device_register(struct instance *i,
- const struct watchdog_device_ops *o);
-
- The structure being defined as follows:
-
- struct watchdog_device_ops {
- int (*disable)(struct instance *i);
- void (*reset)(struct instance *i);
- };
-
- The watchdog_init() function will be dissolved into probe() function.
-
- 2) Conversion thougths
- ----------------------
-
- Conversion of watchdog implementations to a new API could be divided
- to three subsections: a) HW implementations, which are mostly compliant
- to the above mentioned API; b) SW implementations, which are compliant
- to the above mentioned API and c) SW implementations that are not compliant
- to the API and has to be rectified or partially rewritten.
-
-III) Analysis of in-tree drivers
---------------------------------
-
- drivers/watchdog/at91sam9_wdt.c
- -------------------------------
- The driver is standard HW watchdog. Simple conversion is possible.
-
-
- drivers/watchdog/ftwdt010_wdt.c
- -------------------------------
- The driver is ad-hoc HW watchdog. Conversion has to take into account
- driver parts spread in include/faraday/*. Restructuring the driver and
- code cleanup has to be considered.
-
-
- arch/arm/cpu/arm1136/mx31/timer.c
- ---------------------------------
- The driver is semi-standard ad-hoc HW watchdog. Conversion has to take
- into account driver parts spread in the timer.c file.
-
-
- arch/arm/cpu/arm926ejs/davinci/timer.c
- --------------------------------------
- The driver is ad-hoc semi-standard HW watchdog. Conversion has to take
- into account driver parts spread in the timer.c file.
-
-
- arch/arm/cpu/armv7/omap-common/hwinit-common.c
- ----------------------------------------------
- The driver is non-standard ad-hoc HW watchdog. Conversion is possible
- but functions has to be renamed and constants moved to another places.
-
-
- arch/arm/cpu/armv7/omap3/board.c
- --------------------------------
- The driver is non-standard ad-hoc HW watchdog. Conversion is possible
- but functions has to be renamed and constants moved to another places.
-
-
- arch/blackfin/cpu/watchdog.c
- ----------------------------
- The driver is standard HW watchdog. Simple conversion is possible.
-
-
- arch/m68k/cpu/mcf523x/cpu.c
- ---------------------------
- The driver is standard HW watchdog. Simple conversion is possible.
-
-
- arch/m68k/cpu/mcf52x2/cpu.c
- ---------------------------
- The driver is standard HW watchdog. Simple conversion is possible.
-
-
- arch/m68k/cpu/mcf532x/cpu.c
- ---------------------------
- The driver is standard HW watchdog. Simple conversion is possible.
-
-
- arch/m68k/cpu/mcf547x_8x/cpu.c
- ------------------------------
- The driver is standard HW watchdog (there is slight naming convention
- violation that has to be rectified). Simple conversion is possible.
-
-
- arch/powerpc/cpu/74xx_7xx/cpu.c
- -------------------------------
- The driver is standard HW watchdog. Simple conversion is possible.
-
-
- arch/powerpc/cpu/mpc512x/cpu.c
- ------------------------------
- The driver is standard HW watchdog. Simple conversion is possible.
-
-
- arch/powerpc/cpu/mpc5xx/cpu.c
- -----------------------------
- The driver is standard HW watchdog. Simple conversion is possible.
-
-
- arch/powerpc/cpu/mpc5xxx/cpu.c
- ------------------------------
- The driver is standard HW watchdog. Simple conversion is possible.
-
-
- arch/powerpc/cpu/mpc8260/cpu.c
- ------------------------------
- The driver is standard HW watchdog. Simple conversion is possible.
-
-
- arch/powerpc/cpu/mpc83xx/cpu.c
- ------------------------------
- The driver is standard HW watchdog. Simple conversion is possible.
-
-
- arch/powerpc/cpu/mpc85xx/cpu.c
- ------------------------------
- The driver is standard HW watchdog. Simple conversion is possible.
-
-
- arch/powerpc/cpu/mpc86xx/cpu.c
- ------------------------------
- The driver is standard HW watchdog. Simple conversion is possible.
-
-
- arch/powerpc/cpu/mpc8xx/cpu.c
- -----------------------------
- The driver is standard HW watchdog. Simple conversion is possible.
-
-
- arch/powerpc/cpu/ppc4xx/cpu.c
- -----------------------------
- The driver is standard HW watchdog. Simple conversion is possible.
-
-
- arch/sh/cpu/sh2/watchdog.c
- --------------------------
- The driver is standard HW watchdog. Simple conversion is possible.
-
-
- arch/sh/cpu/sh3/watchdog.c
- --------------------------
- The driver is standard HW watchdog. Simple conversion is possible.
-
-
- arch/sh/cpu/sh4/watchdog.c
- --------------------------
- The driver is standard HW watchdog. Simple conversion is possible.
-
-
- board/amcc/luan/luan.c
- ----------------------
- The driver is standard HW watchdog. Simple conversion is possible.
-
-
- board/amcc/yosemite/yosemite.c
- ------------------------------
- The driver is standard HW watchdog. Simple conversion is possible.
-
-
- board/apollon/apollon.c
- -----------------------
- The driver is standard HW watchdog however the watchdog_init()
- function is called in early initialization. Simple conversion is possible.
-
-
- board/bmw/m48t59y.c
- -------------------
- Special watchdog driver. Dead code. To be removed.
-
-
- board/davedenx/qong/qong.c
- --------------------------
- The driver is standard HW watchdog. Simple conversion is possible.
-
-
- board/dvlhost/watchdog.c
- ------------------------
- The driver is standard HW watchdog. Simple conversion is possible.
-
-
- board/eNET/eNET.c
- -----------------
- The driver is standard HW watchdog. Simple conversion is possible.
-
-
- board/eltec/elppc/elppc.c
- -------------------------
- The driver is standard HW watchdog. Simple conversion is possible.
-
-
- board/enbw/enbw_cmc/enbw_cmc.c
- ------------------------------
- Only function proxy call. Code cleanup needed.
-
-
- board/freescale/mx31pdk/mx31pdk.c
- ---------------------------------
- Only function proxy call. Code cleanup needed.
-
-
- board/gth2/gth2.c
- -----------------
- The driver is standard HW watchdog. Simple conversion is possible.
-
-
- board/lwmon5/lwmon5.c
- ---------------------
- The driver is standard HW watchdog. Simple conversion is possible.
-
-
- board/manroland/mucmc52/mucmc52.c
- ---------------------------------
- The driver is standard HW watchdog. Simple conversion is possible.
-
-
- board/manroland/uc101/uc101.c
- -----------------------------
- The driver is standard HW watchdog. Simple conversion is possible.
-
-
- board/mousse/m48t59y.c
- ----------------------
- Special watchdog driver. Dead code. To be removed.
-
-
- board/mvblue/mvblue.c
- ---------------------
- The driver is standard HW watchdog. Simple conversion is possible.
-
-
- board/netphone/netphone.c
- -------------------------
- The driver is standard HW watchdog. Simple conversion is possible.
-
-
- board/netta/netta.c
- -------------------
- The driver is standard HW watchdog. Simple conversion is possible.
-
-
- board/netta2/netta2.c
- ---------------------
- The driver is standard HW watchdog. Simple conversion is possible.
-
-
- board/omicron/calimain/calimain.c
- ---------------------------------
- Only function proxy call. Code cleanup needed.
-
-
- board/pcs440ep/pcs440ep.c
- -------------------------
- The driver is standard HW watchdog. Simple conversion is possible.
-
-
- board/stx/stxxtc/stxxtc.c
- -------------------------
- The driver is standard HW watchdog. Simple conversion is possible.
-
-
- board/ti/omap2420h4/omap2420h4.c
- --------------------------------
- The driver is standard HW watchdog. Simple conversion is possible.
-
-
- board/ttcontrol/vision2/vision2.c
- ---------------------------------
- The driver is standard HW watchdog but namespace is polluted by
- non-standard macros. Simple conversion is possible, code cleanup
- needed.
-
-
- board/v38b/v38b.c
- -----------------
- The driver is standard HW watchdog. Simple conversion is possible.
-
-
- board/ve8313/ve8313.c
- ---------------------
- The driver is standard HW watchdog. Simple conversion is possible.
-
-
- board/w7o/watchdog.c
- --------------------
- The driver is standard HW watchdog. Simple conversion is possible.
#define WAIT_MS_SPINUP 20000
#define WAIT_MS_DATAIO 5000
#define WAIT_MS_FLUSH 5000
-#define WAIT_MS_LINKUP 4
+#define WAIT_MS_LINKUP 40
static inline u32 ahci_port_base(u32 base, u32 port)
{
err_out:
return rc;
}
+
+void __weak scsi_init(void)
+{
+}
+
#endif
/*
--- /dev/null
+#
+# Copyright (c) 2013 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_DM) := device.o lists.o root.o uclass.o util.o
--- /dev/null
+/*
+ * Device manager
+ *
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <dm/device.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/platdata.h>
+#include <dm/uclass.h>
+#include <dm/uclass-internal.h>
+#include <dm/util.h>
+#include <linux/err.h>
+#include <linux/list.h>
+
+/**
+ * device_chld_unbind() - Unbind all device's children from the device
+ *
+ * On error, the function continues to unbind all children, and reports the
+ * first error.
+ *
+ * @dev: The device that is to be stripped of its children
+ * @return 0 on success, -ve on error
+ */
+static int device_chld_unbind(struct device *dev)
+{
+ struct device *pos, *n;
+ int ret, saved_ret = 0;
+
+ assert(dev);
+
+ list_for_each_entry_safe(pos, n, &dev->child_head, sibling_node) {
+ ret = device_unbind(pos);
+ if (ret && !saved_ret)
+ saved_ret = ret;
+ }
+
+ return saved_ret;
+}
+
+/**
+ * device_chld_remove() - Stop all device's children
+ * @dev: The device whose children are to be removed
+ * @return 0 on success, -ve on error
+ */
+static int device_chld_remove(struct device *dev)
+{
+ struct device *pos, *n;
+ int ret;
+
+ assert(dev);
+
+ list_for_each_entry_safe(pos, n, &dev->child_head, sibling_node) {
+ ret = device_remove(pos);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+int device_bind(struct device *parent, struct driver *drv, const char *name,
+ void *platdata, int of_offset, struct device **devp)
+{
+ struct device *dev;
+ struct uclass *uc;
+ int ret = 0;
+
+ *devp = NULL;
+ if (!name)
+ return -EINVAL;
+
+ ret = uclass_get(drv->id, &uc);
+ if (ret)
+ return ret;
+
+ dev = calloc(1, sizeof(struct device));
+ if (!dev)
+ return -ENOMEM;
+
+ INIT_LIST_HEAD(&dev->sibling_node);
+ INIT_LIST_HEAD(&dev->child_head);
+ INIT_LIST_HEAD(&dev->uclass_node);
+ dev->platdata = platdata;
+ dev->name = name;
+ dev->of_offset = of_offset;
+ dev->parent = parent;
+ dev->driver = drv;
+ dev->uclass = uc;
+ if (!dev->platdata && drv->platdata_auto_alloc_size)
+ dev->flags |= DM_FLAG_ALLOC_PDATA;
+
+ /* put dev into parent's successor list */
+ if (parent)
+ list_add_tail(&dev->sibling_node, &parent->child_head);
+
+ ret = uclass_bind_device(dev);
+ if (ret)
+ goto fail_bind;
+
+ /* if we fail to bind we remove device from successors and free it */
+ if (drv->bind) {
+ ret = drv->bind(dev);
+ if (ret) {
+ if (uclass_unbind_device(dev)) {
+ dm_warn("Failed to unbind dev '%s' on error path\n",
+ dev->name);
+ }
+ goto fail_bind;
+ }
+ }
+ if (parent)
+ dm_dbg("Bound device %s to %s\n", dev->name, parent->name);
+ *devp = dev;
+
+ return 0;
+
+fail_bind:
+ list_del(&dev->sibling_node);
+ free(dev);
+ return ret;
+}
+
+int device_bind_by_name(struct device *parent, const struct driver_info *info,
+ struct device **devp)
+{
+ struct driver *drv;
+
+ drv = lists_driver_lookup_name(info->name);
+ if (!drv)
+ return -ENOENT;
+
+ return device_bind(parent, drv, info->name, (void *)info->platdata,
+ -1, devp);
+}
+
+int device_unbind(struct device *dev)
+{
+ struct driver *drv;
+ int ret;
+
+ if (!dev)
+ return -EINVAL;
+
+ if (dev->flags & DM_FLAG_ACTIVATED)
+ return -EINVAL;
+
+ drv = dev->driver;
+ assert(drv);
+
+ if (drv->unbind) {
+ ret = drv->unbind(dev);
+ if (ret)
+ return ret;
+ }
+
+ ret = device_chld_unbind(dev);
+ if (ret)
+ return ret;
+
+ ret = uclass_unbind_device(dev);
+ if (ret)
+ return ret;
+
+ if (dev->parent)
+ list_del(&dev->sibling_node);
+ free(dev);
+
+ return 0;
+}
+
+/**
+ * device_free() - Free memory buffers allocated by a device
+ * @dev: Device that is to be started
+ */
+static void device_free(struct device *dev)
+{
+ int size;
+
+ if (dev->driver->priv_auto_alloc_size) {
+ free(dev->priv);
+ dev->priv = NULL;
+ }
+ if (dev->flags & DM_FLAG_ALLOC_PDATA) {
+ free(dev->platdata);
+ dev->platdata = NULL;
+ }
+ size = dev->uclass->uc_drv->per_device_auto_alloc_size;
+ if (size) {
+ free(dev->uclass_priv);
+ dev->uclass_priv = NULL;
+ }
+}
+
+int device_probe(struct device *dev)
+{
+ struct driver *drv;
+ int size = 0;
+ int ret;
+
+ if (!dev)
+ return -EINVAL;
+
+ if (dev->flags & DM_FLAG_ACTIVATED)
+ return 0;
+
+ drv = dev->driver;
+ assert(drv);
+
+ /* Allocate private data and platdata if requested */
+ if (drv->priv_auto_alloc_size) {
+ dev->priv = calloc(1, drv->priv_auto_alloc_size);
+ if (!dev->priv) {
+ ret = -ENOMEM;
+ goto fail;
+ }
+ }
+ /* Allocate private data if requested */
+ if (dev->flags & DM_FLAG_ALLOC_PDATA) {
+ dev->platdata = calloc(1, drv->platdata_auto_alloc_size);
+ if (!dev->platdata) {
+ ret = -ENOMEM;
+ goto fail;
+ }
+ }
+ size = dev->uclass->uc_drv->per_device_auto_alloc_size;
+ if (size) {
+ dev->uclass_priv = calloc(1, size);
+ if (!dev->uclass_priv) {
+ ret = -ENOMEM;
+ goto fail;
+ }
+ }
+
+ /* Ensure all parents are probed */
+ if (dev->parent) {
+ ret = device_probe(dev->parent);
+ if (ret)
+ goto fail;
+ }
+
+ if (drv->ofdata_to_platdata && dev->of_offset >= 0) {
+ ret = drv->ofdata_to_platdata(dev);
+ if (ret)
+ goto fail;
+ }
+
+ if (drv->probe) {
+ ret = drv->probe(dev);
+ if (ret)
+ goto fail;
+ }
+
+ dev->flags |= DM_FLAG_ACTIVATED;
+
+ ret = uclass_post_probe_device(dev);
+ if (ret) {
+ dev->flags &= ~DM_FLAG_ACTIVATED;
+ goto fail_uclass;
+ }
+
+ return 0;
+fail_uclass:
+ if (device_remove(dev)) {
+ dm_warn("%s: Device '%s' failed to remove on error path\n",
+ __func__, dev->name);
+ }
+fail:
+ device_free(dev);
+
+ return ret;
+}
+
+int device_remove(struct device *dev)
+{
+ struct driver *drv;
+ int ret;
+
+ if (!dev)
+ return -EINVAL;
+
+ if (!(dev->flags & DM_FLAG_ACTIVATED))
+ return 0;
+
+ drv = dev->driver;
+ assert(drv);
+
+ ret = uclass_pre_remove_device(dev);
+ if (ret)
+ return ret;
+
+ ret = device_chld_remove(dev);
+ if (ret)
+ goto err;
+
+ if (drv->remove) {
+ ret = drv->remove(dev);
+ if (ret)
+ goto err_remove;
+ }
+
+ device_free(dev);
+
+ dev->flags &= ~DM_FLAG_ACTIVATED;
+
+ return 0;
+
+err_remove:
+ /* We can't put the children back */
+ dm_warn("%s: Device '%s' failed to remove, but children are gone\n",
+ __func__, dev->name);
+err:
+ ret = uclass_post_probe_device(dev);
+ if (ret) {
+ dm_warn("%s: Device '%s' failed to post_probe on error path\n",
+ __func__, dev->name);
+ }
+
+ return ret;
+}
+
+void *dev_get_platdata(struct device *dev)
+{
+ if (!dev) {
+ dm_warn("%s: null device", __func__);
+ return NULL;
+ }
+
+ return dev->platdata;
+}
+
+void *dev_get_priv(struct device *dev)
+{
+ if (!dev) {
+ dm_warn("%s: null device", __func__);
+ return NULL;
+ }
+
+ return dev->priv;
+}
--- /dev/null
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <dm/device.h>
+#include <dm/device-internal.h>
+#include <dm/platdata.h>
+#include <dm/uclass.h>
+#include <dm/util.h>
+#include <linux/compiler.h>
+
+struct driver *lists_driver_lookup_name(const char *name)
+{
+ struct driver *drv =
+ ll_entry_start(struct driver, driver);
+ const int n_ents = ll_entry_count(struct driver, driver);
+ struct driver *entry;
+ int len;
+
+ if (!drv || !n_ents)
+ return NULL;
+
+ len = strlen(name);
+
+ for (entry = drv; entry != drv + n_ents; entry++) {
+ if (strncmp(name, entry->name, len))
+ continue;
+
+ /* Full match */
+ if (len == strlen(entry->name))
+ return entry;
+ }
+
+ /* Not found */
+ return NULL;
+}
+
+struct uclass_driver *lists_uclass_lookup(enum uclass_id id)
+{
+ struct uclass_driver *uclass =
+ ll_entry_start(struct uclass_driver, uclass);
+ const int n_ents = ll_entry_count(struct uclass_driver, uclass);
+ struct uclass_driver *entry;
+
+ if ((id == UCLASS_INVALID) || !uclass)
+ return NULL;
+
+ for (entry = uclass; entry != uclass + n_ents; entry++) {
+ if (entry->id == id)
+ return entry;
+ }
+
+ return NULL;
+}
+
+int lists_bind_drivers(struct device *parent)
+{
+ struct driver_info *info =
+ ll_entry_start(struct driver_info, driver_info);
+ const int n_ents = ll_entry_count(struct driver_info, driver_info);
+ struct driver_info *entry;
+ struct device *dev;
+ int result = 0;
+ int ret;
+
+ for (entry = info; entry != info + n_ents; entry++) {
+ ret = device_bind_by_name(parent, entry, &dev);
+ if (ret) {
+ dm_warn("No match for driver '%s'\n", entry->name);
+ if (!result || ret != -ENOENT)
+ result = ret;
+ }
+ }
+
+ return result;
+}
+
+#ifdef CONFIG_OF_CONTROL
+/**
+ * driver_check_compatible() - Check if a driver is compatible with this node
+ *
+ * @param blob: Device tree pointer
+ * @param offset: Offset of node in device tree
+ * @param of_matchL List of compatible strings to match
+ * @return 0 if there is a match, -ENOENT if no match, -ENODEV if the node
+ * does not have a compatible string, other error <0 if there is a device
+ * tree error
+ */
+static int driver_check_compatible(const void *blob, int offset,
+ const struct device_id *of_match)
+{
+ int ret;
+
+ if (!of_match)
+ return -ENOENT;
+
+ while (of_match->compatible) {
+ ret = fdt_node_check_compatible(blob, offset,
+ of_match->compatible);
+ if (!ret)
+ return 0;
+ else if (ret == -FDT_ERR_NOTFOUND)
+ return -ENODEV;
+ else if (ret < 0)
+ return -EINVAL;
+ of_match++;
+ }
+
+ return -ENOENT;
+}
+
+int lists_bind_fdt(struct device *parent, const void *blob, int offset)
+{
+ struct driver *driver = ll_entry_start(struct driver, driver);
+ const int n_ents = ll_entry_count(struct driver, driver);
+ struct driver *entry;
+ struct device *dev;
+ const char *name;
+ int result = 0;
+ int ret;
+
+ dm_dbg("bind node %s\n", fdt_get_name(blob, offset, NULL));
+ for (entry = driver; entry != driver + n_ents; entry++) {
+ ret = driver_check_compatible(blob, offset, entry->of_match);
+ if (ret == -ENOENT) {
+ continue;
+ } else if (ret == -ENODEV) {
+ break;
+ } else if (ret) {
+ dm_warn("Device tree error at offset %d\n", offset);
+ if (!result || ret != -ENOENT)
+ result = ret;
+ break;
+ }
+
+ name = fdt_get_name(blob, offset, NULL);
+ dm_dbg(" - found match at '%s'\n", entry->name);
+ ret = device_bind(parent, entry, name, NULL, offset, &dev);
+ if (ret) {
+ dm_warn("No match for driver '%s'\n", entry->name);
+ if (!result || ret != -ENOENT)
+ result = ret;
+ }
+ }
+
+ return result;
+}
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <malloc.h>
+#include <dm/device.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/platdata.h>
+#include <dm/uclass.h>
+#include <dm/util.h>
+#include <linux/list.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct driver_info root_info = {
+ .name = "root_driver",
+};
+
+struct device *dm_root(void)
+{
+ if (!gd->dm_root) {
+ dm_warn("Virtual root driver does not exist!\n");
+ return NULL;
+ }
+
+ return gd->dm_root;
+}
+
+int dm_init(void)
+{
+ int ret;
+
+ if (gd->dm_root) {
+ dm_warn("Virtual root driver already exists!\n");
+ return -EINVAL;
+ }
+ INIT_LIST_HEAD(&gd->uclass_root);
+
+ ret = device_bind_by_name(NULL, &root_info, &gd->dm_root);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+int dm_scan_platdata(void)
+{
+ int ret;
+
+ ret = lists_bind_drivers(gd->dm_root);
+ if (ret == -ENOENT) {
+ dm_warn("Some drivers were not found\n");
+ ret = 0;
+ }
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+#ifdef CONFIG_OF_CONTROL
+int dm_scan_fdt(const void *blob)
+{
+ int offset = 0;
+ int ret = 0, err;
+ int depth = 0;
+
+ do {
+ offset = fdt_next_node(blob, offset, &depth);
+ if (offset > 0 && depth == 1) {
+ err = lists_bind_fdt(gd->dm_root, blob, offset);
+ if (err && !ret)
+ ret = err;
+ }
+ } while (offset > 0);
+
+ if (ret)
+ dm_warn("Some drivers failed to bind\n");
+
+ return ret;
+}
+#endif
+
+/* This is the root driver - all drivers are children of this */
+U_BOOT_DRIVER(root_driver) = {
+ .name = "root_driver",
+ .id = UCLASS_ROOT,
+};
+
+/* This is the root uclass */
+UCLASS_DRIVER(root) = {
+ .name = "root",
+ .id = UCLASS_ROOT,
+};
--- /dev/null
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <malloc.h>
+#include <dm/device.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/uclass.h>
+#include <dm/uclass-internal.h>
+#include <dm/util.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct uclass *uclass_find(enum uclass_id key)
+{
+ struct uclass *uc;
+
+ /*
+ * TODO(sjg@chromium.org): Optimise this, perhaps moving the found
+ * node to the start of the list, or creating a linear array mapping
+ * id to node.
+ */
+ list_for_each_entry(uc, &gd->uclass_root, sibling_node) {
+ if (uc->uc_drv->id == key)
+ return uc;
+ }
+
+ return NULL;
+}
+
+/**
+ * uclass_add() - Create new uclass in list
+ * @id: Id number to create
+ * @ucp: Returns pointer to uclass, or NULL on error
+ * @return 0 on success, -ve on error
+ *
+ * The new uclass is added to the list. There must be only one uclass for
+ * each id.
+ */
+static int uclass_add(enum uclass_id id, struct uclass **ucp)
+{
+ struct uclass_driver *uc_drv;
+ struct uclass *uc;
+ int ret;
+
+ *ucp = NULL;
+ uc_drv = lists_uclass_lookup(id);
+ if (!uc_drv) {
+ dm_warn("Cannot find uclass for id %d: please add the UCLASS_DRIVER() declaration for this UCLASS_... id\n",
+ id);
+ return -ENOENT;
+ }
+ if (uc_drv->ops) {
+ dm_warn("No ops for uclass id %d\n", id);
+ return -EINVAL;
+ }
+ uc = calloc(1, sizeof(*uc));
+ if (!uc)
+ return -ENOMEM;
+ if (uc_drv->priv_auto_alloc_size) {
+ uc->priv = calloc(1, uc_drv->priv_auto_alloc_size);
+ if (!uc->priv) {
+ ret = -ENOMEM;
+ goto fail_mem;
+ }
+ }
+ uc->uc_drv = uc_drv;
+ INIT_LIST_HEAD(&uc->sibling_node);
+ INIT_LIST_HEAD(&uc->dev_head);
+ list_add(&uc->sibling_node, &gd->uclass_root);
+
+ if (uc_drv->init) {
+ ret = uc_drv->init(uc);
+ if (ret)
+ goto fail;
+ }
+
+ *ucp = uc;
+
+ return 0;
+fail:
+ if (uc_drv->priv_auto_alloc_size) {
+ free(uc->priv);
+ uc->priv = NULL;
+ }
+ list_del(&uc->sibling_node);
+fail_mem:
+ free(uc);
+
+ return ret;
+}
+
+int uclass_destroy(struct uclass *uc)
+{
+ struct uclass_driver *uc_drv;
+ struct device *dev, *tmp;
+ int ret;
+
+ list_for_each_entry_safe(dev, tmp, &uc->dev_head, uclass_node) {
+ ret = device_remove(dev);
+ if (ret)
+ return ret;
+ ret = device_unbind(dev);
+ if (ret)
+ return ret;
+ }
+
+ uc_drv = uc->uc_drv;
+ if (uc_drv->destroy)
+ uc_drv->destroy(uc);
+ list_del(&uc->sibling_node);
+ if (uc_drv->priv_auto_alloc_size)
+ free(uc->priv);
+ free(uc);
+
+ return 0;
+}
+
+int uclass_get(enum uclass_id id, struct uclass **ucp)
+{
+ struct uclass *uc;
+
+ *ucp = NULL;
+ uc = uclass_find(id);
+ if (!uc)
+ return uclass_add(id, ucp);
+ *ucp = uc;
+
+ return 0;
+}
+
+int uclass_find_device(enum uclass_id id, int index, struct device **devp)
+{
+ struct uclass *uc;
+ struct device *dev;
+ int ret;
+
+ *devp = NULL;
+ ret = uclass_get(id, &uc);
+ if (ret)
+ return ret;
+
+ list_for_each_entry(dev, &uc->dev_head, uclass_node) {
+ if (!index--) {
+ *devp = dev;
+ return 0;
+ }
+ }
+
+ return -ENODEV;
+}
+
+int uclass_get_device(enum uclass_id id, int index, struct device **devp)
+{
+ struct device *dev;
+ int ret;
+
+ *devp = NULL;
+ ret = uclass_find_device(id, index, &dev);
+ if (ret)
+ return ret;
+
+ ret = device_probe(dev);
+ if (ret)
+ return ret;
+
+ *devp = dev;
+
+ return 0;
+}
+
+int uclass_first_device(enum uclass_id id, struct device **devp)
+{
+ struct uclass *uc;
+ struct device *dev;
+ int ret;
+
+ *devp = NULL;
+ ret = uclass_get(id, &uc);
+ if (ret)
+ return ret;
+ if (list_empty(&uc->dev_head))
+ return 0;
+
+ dev = list_first_entry(&uc->dev_head, struct device, uclass_node);
+ ret = device_probe(dev);
+ if (ret)
+ return ret;
+ *devp = dev;
+
+ return 0;
+}
+
+int uclass_next_device(struct device **devp)
+{
+ struct device *dev = *devp;
+ int ret;
+
+ *devp = NULL;
+ if (list_is_last(&dev->uclass_node, &dev->uclass->dev_head))
+ return 0;
+
+ dev = list_entry(dev->uclass_node.next, struct device, uclass_node);
+ ret = device_probe(dev);
+ if (ret)
+ return ret;
+ *devp = dev;
+
+ return 0;
+}
+
+int uclass_bind_device(struct device *dev)
+{
+ struct uclass *uc;
+ int ret;
+
+ uc = dev->uclass;
+
+ list_add_tail(&dev->uclass_node, &uc->dev_head);
+
+ if (uc->uc_drv->post_bind) {
+ ret = uc->uc_drv->post_bind(dev);
+ if (ret) {
+ list_del(&dev->uclass_node);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+int uclass_unbind_device(struct device *dev)
+{
+ struct uclass *uc;
+ int ret;
+
+ uc = dev->uclass;
+ if (uc->uc_drv->pre_unbind) {
+ ret = uc->uc_drv->pre_unbind(dev);
+ if (ret)
+ return ret;
+ }
+
+ list_del(&dev->uclass_node);
+ return 0;
+}
+
+int uclass_post_probe_device(struct device *dev)
+{
+ struct uclass_driver *uc_drv = dev->uclass->uc_drv;
+
+ if (uc_drv->post_probe)
+ return uc_drv->post_probe(dev);
+
+ return 0;
+}
+
+int uclass_pre_remove_device(struct device *dev)
+{
+ struct uclass_driver *uc_drv;
+ struct uclass *uc;
+ int ret;
+
+ uc = dev->uclass;
+ uc_drv = uc->uc_drv;
+ if (uc->uc_drv->pre_remove) {
+ ret = uc->uc_drv->pre_remove(dev);
+ if (ret)
+ return ret;
+ }
+ if (uc_drv->per_device_auto_alloc_size) {
+ free(dev->uclass_priv);
+ dev->uclass_priv = NULL;
+ }
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <vsprintf.h>
+
+void dm_warn(const char *fmt, ...)
+{
+ va_list args;
+
+ va_start(args, fmt);
+ vprintf(fmt, args);
+ va_end(args);
+}
+
+void dm_dbg(const char *fmt, ...)
+{
+ va_list args;
+
+ va_start(args, fmt);
+ vprintf(fmt, args);
+ va_end(args);
+}
+
+int list_count_items(struct list_head *head)
+{
+ struct list_head *node;
+ int count = 0;
+
+ list_for_each(node, head)
+ count++;
+
+ return count;
+}
--- /dev/null
+#
+# Copyright (c) 2013 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_DM_DEMO) += demo-uclass.o demo-pdata.o
+obj-$(CONFIG_DM_DEMO_SIMPLE) += demo-simple.o
+obj-$(CONFIG_DM_DEMO_SHAPE) += demo-shape.o
--- /dev/null
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm-demo.h>
+
+static const struct dm_demo_pdata red_square = {
+ .colour = "red",
+ .sides = 4.
+};
+static const struct dm_demo_pdata green_triangle = {
+ .colour = "green",
+ .sides = 3.
+};
+static const struct dm_demo_pdata yellow_hexagon = {
+ .colour = "yellow",
+ .sides = 6.
+};
+
+U_BOOT_DEVICE(demo0) = {
+ .name = "demo_shape_drv",
+ .platdata = &red_square,
+};
+
+U_BOOT_DEVICE(demo1) = {
+ .name = "demo_simple_drv",
+ .platdata = &red_square,
+};
+
+U_BOOT_DEVICE(demo2) = {
+ .name = "demo_shape_drv",
+ .platdata = &green_triangle,
+};
+
+U_BOOT_DEVICE(demo3) = {
+ .name = "demo_simple_drv",
+ .platdata = &yellow_hexagon,
+};
+
+U_BOOT_DEVICE(demo4) = {
+ .name = "demo_shape_drv",
+ .platdata = &yellow_hexagon,
+};
--- /dev/null
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <dm-demo.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Shape size */
+#define WIDTH 8
+#define HEIGHT 6
+
+struct shape_data {
+ int num_chars; /* Number of non-space characters output so far */
+};
+
+/* Crazy little function to draw shapes on the console */
+static int shape_hello(struct device *dev, int ch)
+{
+ const struct dm_demo_pdata *pdata = dev_get_platdata(dev);
+ struct shape_data *data = dev_get_priv(dev);
+ static const struct shape {
+ int start;
+ int end;
+ int dstart;
+ int dend;
+ } shapes[3] = {
+ { 0, 1, 0, 1 },
+ { 0, WIDTH, 0, 0 },
+ { HEIGHT / 2 - 1, WIDTH - HEIGHT / 2 + 1, -1, 1},
+ };
+ struct shape shape;
+ unsigned int index;
+ int line, pos, inside;
+ const char *colour = pdata->colour;
+ int first = 0;
+
+ if (!ch)
+ ch = pdata->default_char;
+ if (!ch)
+ ch = '@';
+
+ index = (pdata->sides / 2) - 1;
+ if (index >= ARRAY_SIZE(shapes))
+ return -EIO;
+ shape = shapes[index];
+
+ for (line = 0; line < HEIGHT; line++) {
+ first = 1;
+ for (pos = 0; pos < WIDTH; pos++) {
+ inside = pos >= shape.start && pos < shape.end;
+ if (inside) {
+ putc(first ? *colour++ : ch);
+ data->num_chars++;
+ first = 0;
+ if (!*colour)
+ colour = pdata->colour;
+ } else {
+ putc(' ');
+ }
+ }
+ putc('\n');
+ shape.start += shape.dstart;
+ shape.end += shape.dend;
+ if (shape.start < 0) {
+ shape.dstart = -shape.dstart;
+ shape.dend = -shape.dend;
+ shape.start += shape.dstart;
+ shape.end += shape.dend;
+ }
+ }
+
+ return 0;
+}
+
+static int shape_status(struct device *dev, int *status)
+{
+ struct shape_data *data = dev_get_priv(dev);
+
+ *status = data->num_chars;
+ return 0;
+}
+
+static const struct demo_ops shape_ops = {
+ .hello = shape_hello,
+ .status = shape_status,
+};
+
+static int shape_ofdata_to_platdata(struct device *dev)
+{
+ struct dm_demo_pdata *pdata = dev_get_platdata(dev);
+ int ret;
+
+ /* Parse the data that is common with all demo devices */
+ ret = demo_parse_dt(dev);
+ if (ret)
+ return ret;
+
+ /* Parse the data that only we need */
+ pdata->default_char = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ "character", '@');
+
+ return 0;
+}
+
+static const struct device_id demo_shape_id[] = {
+ { "demo-shape", 0 },
+ { },
+};
+
+U_BOOT_DRIVER(demo_shape_drv) = {
+ .name = "demo_shape_drv",
+ .of_match = demo_shape_id,
+ .id = UCLASS_DEMO,
+ .ofdata_to_platdata = shape_ofdata_to_platdata,
+ .ops = &shape_ops,
+ .priv_auto_alloc_size = sizeof(struct shape_data),
+ .platdata_auto_alloc_size = sizeof(struct dm_demo_pdata),
+};
--- /dev/null
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm-demo.h>
+#include <asm/io.h>
+
+static int simple_hello(struct device *dev, int ch)
+{
+ const struct dm_demo_pdata *pdata = dev_get_platdata(dev);
+
+ printf("Hello from %08x: %s %d\n", map_to_sysmem(dev), pdata->colour,
+ pdata->sides);
+
+ return 0;
+}
+
+static const struct demo_ops simple_ops = {
+ .hello = simple_hello,
+};
+
+static int demo_shape_ofdata_to_platdata(struct device *dev)
+{
+ /* Parse the data that is common with all demo devices */
+ return demo_parse_dt(dev);
+}
+
+static const struct device_id demo_shape_id[] = {
+ { "demo-simple", 0 },
+ { },
+};
+
+U_BOOT_DRIVER(demo_simple_drv) = {
+ .name = "demo_simple_drv",
+ .of_match = demo_shape_id,
+ .id = UCLASS_DEMO,
+ .ofdata_to_platdata = demo_shape_ofdata_to_platdata,
+ .ops = &simple_ops,
+ .platdata_auto_alloc_size = sizeof(struct dm_demo_pdata),
+};
--- /dev/null
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm-demo.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <linux/list.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+UCLASS_DRIVER(demo) = {
+ .id = UCLASS_DEMO,
+};
+
+int demo_hello(struct device *dev, int ch)
+{
+ const struct demo_ops *ops = device_get_ops(dev);
+
+ if (!ops->hello)
+ return -ENOSYS;
+
+ return ops->hello(dev, ch);
+}
+
+int demo_status(struct device *dev, int *status)
+{
+ const struct demo_ops *ops = device_get_ops(dev);
+
+ if (!ops->status)
+ return -ENOSYS;
+
+ return ops->status(dev, status);
+}
+
+int demo_parse_dt(struct device *dev)
+{
+ struct dm_demo_pdata *pdata = dev_get_platdata(dev);
+ int dn = dev->of_offset;
+
+ pdata->sides = fdtdec_get_int(gd->fdt_blob, dn, "sides", 0);
+ pdata->colour = fdt_getprop(gd->fdt_blob, dn, "colour", NULL);
+ if (!pdata->sides || !pdata->colour) {
+ debug("%s: Invalid device tree data\n", __func__);
+ return -EINVAL;
+ }
+
+ return 0;
+}
static bool dfu_reset_request;
static LIST_HEAD(dfu_list);
static int dfu_alt_num;
+static int alt_num_cnt;
bool dfu_reset(void)
{
if (t)
free(t);
INIT_LIST_HEAD(&dfu_list);
+
+ alt_num_cnt = 0;
}
int dfu_config_entities(char *env, char *interface, int num)
for (i = 0; i < dfu_alt_num; i++) {
s = strsep(&env, ";");
- ret = dfu_fill_entity(&dfu[i], s, i, interface, num);
+ ret = dfu_fill_entity(&dfu[i], s, alt_num_cnt, interface, num);
if (ret)
return -1;
list_add_tail(&dfu[i].list, &dfu_list);
+ alt_num_cnt++;
}
return 0;
#include <common.h>
#include <asm/io.h>
#include <zynqpl.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
# SPDX-License-Identifier: GPL-2.0+
#
+obj-$(CONFIG_DM_GPIO) += gpio-uclass.o
+
obj-$(CONFIG_AT91_GPIO) += at91_gpio.o
obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o
obj-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o
#include <config.h>
#include <common.h>
#include <asm/io.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_pio.h>
#include <asm/arch/gpio.h>
--- /dev/null
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/gpio.h>
+
+/**
+ * gpio_to_device() - Convert global GPIO number to device, number
+ * gpio: The numeric representation of the GPIO
+ *
+ * Convert the GPIO number to an entry in the list of GPIOs
+ * or GPIO blocks registered with the GPIO controller. Returns
+ * entry on success, NULL on error.
+ */
+static int gpio_to_device(unsigned int gpio, struct device **devp,
+ unsigned int *offset)
+{
+ struct gpio_dev_priv *uc_priv;
+ struct device *dev;
+ int ret;
+
+ for (ret = uclass_first_device(UCLASS_GPIO, &dev);
+ dev;
+ ret = uclass_next_device(&dev)) {
+ uc_priv = dev->uclass_priv;
+ if (gpio >= uc_priv->gpio_base &&
+ gpio < uc_priv->gpio_base + uc_priv->gpio_count) {
+ *devp = dev;
+ *offset = gpio - uc_priv->gpio_base;
+ return 0;
+ }
+ }
+
+ /* No such GPIO */
+ return ret ? ret : -EINVAL;
+}
+
+int gpio_lookup_name(const char *name, struct device **devp,
+ unsigned int *offsetp, unsigned int *gpiop)
+{
+ struct gpio_dev_priv *uc_priv;
+ struct device *dev;
+ int ret;
+
+ if (devp)
+ *devp = NULL;
+ for (ret = uclass_first_device(UCLASS_GPIO, &dev);
+ dev;
+ ret = uclass_next_device(&dev)) {
+ ulong offset;
+ int len;
+
+ uc_priv = dev->uclass_priv;
+ len = uc_priv->bank_name ? strlen(uc_priv->bank_name) : 0;
+
+ if (!strncmp(name, uc_priv->bank_name, len)) {
+ if (strict_strtoul(name + len, 10, &offset))
+ continue;
+ if (devp)
+ *devp = dev;
+ if (offsetp)
+ *offsetp = offset;
+ if (gpiop)
+ *gpiop = uc_priv->gpio_base + offset;
+ return 0;
+ }
+ }
+
+ return ret ? ret : -EINVAL;
+}
+
+/**
+ * gpio_request() - [COMPAT] Request GPIO
+ * gpio: GPIO number
+ * label: Name for the requested GPIO
+ *
+ * This function implements the API that's compatible with current
+ * GPIO API used in U-Boot. The request is forwarded to particular
+ * GPIO driver. Returns 0 on success, negative value on error.
+ */
+int gpio_request(unsigned gpio, const char *label)
+{
+ unsigned int offset;
+ struct device *dev;
+ int ret;
+
+ ret = gpio_to_device(gpio, &dev, &offset);
+ if (ret)
+ return ret;
+
+ if (!gpio_get_ops(dev)->request)
+ return 0;
+
+ return gpio_get_ops(dev)->request(dev, offset, label);
+}
+
+/**
+ * gpio_free() - [COMPAT] Relinquish GPIO
+ * gpio: GPIO number
+ *
+ * This function implements the API that's compatible with current
+ * GPIO API used in U-Boot. The request is forwarded to particular
+ * GPIO driver. Returns 0 on success, negative value on error.
+ */
+int gpio_free(unsigned gpio)
+{
+ unsigned int offset;
+ struct device *dev;
+ int ret;
+
+ ret = gpio_to_device(gpio, &dev, &offset);
+ if (ret)
+ return ret;
+
+ if (!gpio_get_ops(dev)->free)
+ return 0;
+ return gpio_get_ops(dev)->free(dev, offset);
+}
+
+/**
+ * gpio_direction_input() - [COMPAT] Set GPIO direction to input
+ * gpio: GPIO number
+ *
+ * This function implements the API that's compatible with current
+ * GPIO API used in U-Boot. The request is forwarded to particular
+ * GPIO driver. Returns 0 on success, negative value on error.
+ */
+int gpio_direction_input(unsigned gpio)
+{
+ unsigned int offset;
+ struct device *dev;
+ int ret;
+
+ ret = gpio_to_device(gpio, &dev, &offset);
+ if (ret)
+ return ret;
+
+ return gpio_get_ops(dev)->direction_input(dev, offset);
+}
+
+/**
+ * gpio_direction_output() - [COMPAT] Set GPIO direction to output and set value
+ * gpio: GPIO number
+ * value: Logical value to be set on the GPIO pin
+ *
+ * This function implements the API that's compatible with current
+ * GPIO API used in U-Boot. The request is forwarded to particular
+ * GPIO driver. Returns 0 on success, negative value on error.
+ */
+int gpio_direction_output(unsigned gpio, int value)
+{
+ unsigned int offset;
+ struct device *dev;
+ int ret;
+
+ ret = gpio_to_device(gpio, &dev, &offset);
+ if (ret)
+ return ret;
+
+ return gpio_get_ops(dev)->direction_output(dev, offset, value);
+}
+
+/**
+ * gpio_get_value() - [COMPAT] Sample GPIO pin and return it's value
+ * gpio: GPIO number
+ *
+ * This function implements the API that's compatible with current
+ * GPIO API used in U-Boot. The request is forwarded to particular
+ * GPIO driver. Returns the value of the GPIO pin, or negative value
+ * on error.
+ */
+int gpio_get_value(unsigned gpio)
+{
+ unsigned int offset;
+ struct device *dev;
+ int ret;
+
+ ret = gpio_to_device(gpio, &dev, &offset);
+ if (ret)
+ return ret;
+
+ return gpio_get_ops(dev)->get_value(dev, offset);
+}
+
+/**
+ * gpio_set_value() - [COMPAT] Configure logical value on GPIO pin
+ * gpio: GPIO number
+ * value: Logical value to be set on the GPIO pin.
+ *
+ * This function implements the API that's compatible with current
+ * GPIO API used in U-Boot. The request is forwarded to particular
+ * GPIO driver. Returns 0 on success, negative value on error.
+ */
+int gpio_set_value(unsigned gpio, int value)
+{
+ unsigned int offset;
+ struct device *dev;
+ int ret;
+
+ ret = gpio_to_device(gpio, &dev, &offset);
+ if (ret)
+ return ret;
+
+ return gpio_get_ops(dev)->set_value(dev, offset, value);
+}
+
+const char *gpio_get_bank_info(struct device *dev, int *bit_count)
+{
+ struct gpio_dev_priv *priv;
+
+ /* Must be called on an active device */
+ priv = dev->uclass_priv;
+ assert(priv);
+
+ *bit_count = priv->gpio_count;
+ return priv->bank_name;
+}
+
+/* We need to renumber the GPIOs when any driver is probed/removed */
+static int gpio_renumber(void)
+{
+ struct gpio_dev_priv *uc_priv;
+ struct device *dev;
+ struct uclass *uc;
+ unsigned base;
+ int ret;
+
+ ret = uclass_get(UCLASS_GPIO, &uc);
+ if (ret)
+ return ret;
+
+ /* Ensure that we have a base for each bank */
+ base = 0;
+ uclass_foreach_dev(dev, uc) {
+ if (device_active(dev)) {
+ uc_priv = dev->uclass_priv;
+ uc_priv->gpio_base = base;
+ base += uc_priv->gpio_count;
+ }
+ }
+
+ return 0;
+}
+
+static int gpio_post_probe(struct device *dev)
+{
+ return gpio_renumber();
+}
+
+static int gpio_pre_remove(struct device *dev)
+{
+ return gpio_renumber();
+}
+
+UCLASS_DRIVER(gpio) = {
+ .id = UCLASS_GPIO,
+ .name = "gpio",
+ .post_probe = gpio_post_probe,
+ .pre_remove = gpio_pre_remove,
+ .per_device_auto_alloc_size = sizeof(struct gpio_dev_priv),
+};
*/
#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <malloc.h>
#include <asm/gpio.h>
+DECLARE_GLOBAL_DATA_PTR;
+
/* Flags for each GPIO */
#define GPIOF_OUTPUT (1 << 0) /* Currently set as an output */
#define GPIOF_HIGH (1 << 1) /* Currently set high */
u8 flags; /* flags (GPIOF_...) */
};
-/*
- * State of GPIOs
- * TODO: Put this into sandbox state
- */
-static struct gpio_state state[CONFIG_SANDBOX_GPIO_COUNT];
-
/* Access routines for GPIO state */
-static u8 *get_gpio_flags(unsigned gp)
+static u8 *get_gpio_flags(struct device *dev, unsigned offset)
{
- /* assert()'s could be disabled, so make sure we handle that */
- assert(gp < ARRAY_SIZE(state));
- if (gp >= ARRAY_SIZE(state)) {
+ struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+ struct gpio_state *state = dev_get_priv(dev);
+
+ if (offset >= uc_priv->gpio_count) {
static u8 invalid_flags;
- printf("sandbox_gpio: error: invalid gpio %u\n", gp);
+ printf("sandbox_gpio: error: invalid gpio %u\n", offset);
return &invalid_flags;
}
- return &state[gp].flags;
+ return &state[offset].flags;
}
-static int get_gpio_flag(unsigned gp, int flag)
+static int get_gpio_flag(struct device *dev, unsigned offset, int flag)
{
- return (*get_gpio_flags(gp) & flag) != 0;
+ return (*get_gpio_flags(dev, offset) & flag) != 0;
}
-static int set_gpio_flag(unsigned gp, int flag, int value)
+static int set_gpio_flag(struct device *dev, unsigned offset, int flag,
+ int value)
{
- u8 *gpio = get_gpio_flags(gp);
+ u8 *gpio = get_gpio_flags(dev, offset);
if (value)
*gpio |= flag;
return 0;
}
-static int check_reserved(unsigned gpio, const char *func)
+static int check_reserved(struct device *dev, unsigned offset,
+ const char *func)
{
- if (!get_gpio_flag(gpio, GPIOF_RESERVED)) {
- printf("sandbox_gpio: %s: error: gpio %u not reserved\n",
- func, gpio);
+ if (!get_gpio_flag(dev, offset, GPIOF_RESERVED)) {
+ printf("sandbox_gpio: %s: error: offset %u not reserved\n",
+ func, offset);
return -1;
}
* Back-channel sandbox-internal-only access to GPIO state
*/
-int sandbox_gpio_get_value(unsigned gp)
+int sandbox_gpio_get_value(struct device *dev, unsigned offset)
{
- if (get_gpio_flag(gp, GPIOF_OUTPUT))
- debug("sandbox_gpio: get_value on output gpio %u\n", gp);
- return get_gpio_flag(gp, GPIOF_HIGH);
+ if (get_gpio_flag(dev, offset, GPIOF_OUTPUT))
+ debug("sandbox_gpio: get_value on output gpio %u\n", offset);
+ return get_gpio_flag(dev, offset, GPIOF_HIGH);
}
-int sandbox_gpio_set_value(unsigned gp, int value)
+int sandbox_gpio_set_value(struct device *dev, unsigned offset, int value)
{
- return set_gpio_flag(gp, GPIOF_HIGH, value);
+ return set_gpio_flag(dev, offset, GPIOF_HIGH, value);
}
-int sandbox_gpio_get_direction(unsigned gp)
+int sandbox_gpio_get_direction(struct device *dev, unsigned offset)
{
- return get_gpio_flag(gp, GPIOF_OUTPUT);
+ return get_gpio_flag(dev, offset, GPIOF_OUTPUT);
}
-int sandbox_gpio_set_direction(unsigned gp, int output)
+int sandbox_gpio_set_direction(struct device *dev, unsigned offset, int output)
{
- return set_gpio_flag(gp, GPIOF_OUTPUT, output);
+ return set_gpio_flag(dev, offset, GPIOF_OUTPUT, output);
}
/*
* These functions implement the public interface within U-Boot
*/
-/* set GPIO port 'gp' as an input */
-int gpio_direction_input(unsigned gp)
+/* set GPIO port 'offset' as an input */
+static int sb_gpio_direction_input(struct device *dev, unsigned offset)
{
- debug("%s: gp:%u\n", __func__, gp);
+ debug("%s: offset:%u\n", __func__, offset);
- if (check_reserved(gp, __func__))
+ if (check_reserved(dev, offset, __func__))
return -1;
- return sandbox_gpio_set_direction(gp, 0);
+ return sandbox_gpio_set_direction(dev, offset, 0);
}
-/* set GPIO port 'gp' as an output, with polarity 'value' */
-int gpio_direction_output(unsigned gp, int value)
+/* set GPIO port 'offset' as an output, with polarity 'value' */
+static int sb_gpio_direction_output(struct device *dev, unsigned offset,
+ int value)
{
- debug("%s: gp:%u, value = %d\n", __func__, gp, value);
+ debug("%s: offset:%u, value = %d\n", __func__, offset, value);
- if (check_reserved(gp, __func__))
+ if (check_reserved(dev, offset, __func__))
return -1;
- return sandbox_gpio_set_direction(gp, 1) |
- sandbox_gpio_set_value(gp, value);
+ return sandbox_gpio_set_direction(dev, offset, 1) |
+ sandbox_gpio_set_value(dev, offset, value);
}
-/* read GPIO IN value of port 'gp' */
-int gpio_get_value(unsigned gp)
+/* read GPIO IN value of port 'offset' */
+static int sb_gpio_get_value(struct device *dev, unsigned offset)
{
- debug("%s: gp:%u\n", __func__, gp);
+ debug("%s: offset:%u\n", __func__, offset);
- if (check_reserved(gp, __func__))
+ if (check_reserved(dev, offset, __func__))
return -1;
- return sandbox_gpio_get_value(gp);
+ return sandbox_gpio_get_value(dev, offset);
}
-/* write GPIO OUT value to port 'gp' */
-int gpio_set_value(unsigned gp, int value)
+/* write GPIO OUT value to port 'offset' */
+static int sb_gpio_set_value(struct device *dev, unsigned offset, int value)
{
- debug("%s: gp:%u, value = %d\n", __func__, gp, value);
+ debug("%s: offset:%u, value = %d\n", __func__, offset, value);
- if (check_reserved(gp, __func__))
+ if (check_reserved(dev, offset, __func__))
return -1;
- if (!sandbox_gpio_get_direction(gp)) {
- printf("sandbox_gpio: error: set_value on input gpio %u\n", gp);
+ if (!sandbox_gpio_get_direction(dev, offset)) {
+ printf("sandbox_gpio: error: set_value on input gpio %u\n",
+ offset);
return -1;
}
- return sandbox_gpio_set_value(gp, value);
+ return sandbox_gpio_set_value(dev, offset, value);
}
-int gpio_request(unsigned gp, const char *label)
+static int sb_gpio_request(struct device *dev, unsigned offset,
+ const char *label)
{
- debug("%s: gp:%u, label:%s\n", __func__, gp, label);
+ struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+ struct gpio_state *state = dev_get_priv(dev);
+
+ debug("%s: offset:%u, label:%s\n", __func__, offset, label);
- if (gp >= ARRAY_SIZE(state)) {
- printf("sandbox_gpio: error: invalid gpio %u\n", gp);
+ if (offset >= uc_priv->gpio_count) {
+ printf("sandbox_gpio: error: invalid gpio %u\n", offset);
return -1;
}
- if (get_gpio_flag(gp, GPIOF_RESERVED)) {
- printf("sandbox_gpio: error: gpio %u already reserved\n", gp);
+ if (get_gpio_flag(dev, offset, GPIOF_RESERVED)) {
+ printf("sandbox_gpio: error: gpio %u already reserved\n",
+ offset);
return -1;
}
- state[gp].label = label;
- return set_gpio_flag(gp, GPIOF_RESERVED, 1);
+ state[offset].label = label;
+ return set_gpio_flag(dev, offset, GPIOF_RESERVED, 1);
}
-int gpio_free(unsigned gp)
+static int sb_gpio_free(struct device *dev, unsigned offset)
{
- debug("%s: gp:%u\n", __func__, gp);
+ struct gpio_state *state = dev_get_priv(dev);
+
+ debug("%s: offset:%u\n", __func__, offset);
- if (check_reserved(gp, __func__))
+ if (check_reserved(dev, offset, __func__))
return -1;
- state[gp].label = NULL;
- return set_gpio_flag(gp, GPIOF_RESERVED, 0);
+ state[offset].label = NULL;
+ return set_gpio_flag(dev, offset, GPIOF_RESERVED, 0);
}
-/* Display GPIO information */
-void gpio_info(void)
+static int sb_gpio_get_state(struct device *dev, unsigned int offset,
+ char *buf, int bufsize)
{
- unsigned gpio;
+ struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+ struct gpio_state *state = dev_get_priv(dev);
+ const char *label;
+
+ label = state[offset].label;
+ snprintf(buf, bufsize, "%s%d: %s: %d [%c]%s%s",
+ uc_priv->bank_name ? uc_priv->bank_name : "", offset,
+ sandbox_gpio_get_direction(dev, offset) ? "out" : " in",
+ sandbox_gpio_get_value(dev, offset),
+ get_gpio_flag(dev, offset, GPIOF_RESERVED) ? 'x' : ' ',
+ label ? " " : "",
+ label ? label : "");
- puts("Sandbox GPIOs\n");
+ return 0;
+}
+
+static const struct dm_gpio_ops gpio_sandbox_ops = {
+ .request = sb_gpio_request,
+ .free = sb_gpio_free,
+ .direction_input = sb_gpio_direction_input,
+ .direction_output = sb_gpio_direction_output,
+ .get_value = sb_gpio_get_value,
+ .set_value = sb_gpio_set_value,
+ .get_state = sb_gpio_get_state,
+};
+
+static int sandbox_gpio_ofdata_to_platdata(struct device *dev)
+{
+ struct gpio_dev_priv *uc_priv = dev->uclass_priv;
- for (gpio = 0; gpio < ARRAY_SIZE(state); ++gpio) {
- const char *label = state[gpio].label;
+ uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ "num-gpios", 0);
+ uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset,
+ "gpio-bank-name", NULL);
- printf("%4d: %s: %d [%c] %s\n",
- gpio,
- sandbox_gpio_get_direction(gpio) ? "out" : " in",
- sandbox_gpio_get_value(gpio),
- get_gpio_flag(gpio, GPIOF_RESERVED) ? 'x' : ' ',
- label ? label : "");
+ return 0;
+}
+
+static int gpio_sandbox_probe(struct device *dev)
+{
+ struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+
+ if (dev->of_offset == -1) {
+ /* Tell the uclass how many GPIOs we have */
+ uc_priv->gpio_count = CONFIG_SANDBOX_GPIO_COUNT;
}
+
+ dev->priv = calloc(sizeof(struct gpio_state), uc_priv->gpio_count);
+
+ return 0;
}
+
+static const struct device_id sandbox_gpio_ids[] = {
+ { .compatible = "sandbox,gpio" },
+ { }
+};
+
+U_BOOT_DRIVER(gpio_sandbox) = {
+ .name = "gpio_sandbox",
+ .id = UCLASS_GPIO,
+ .of_match = sandbox_gpio_ids,
+ .ofdata_to_platdata = sandbox_gpio_ofdata_to_platdata,
+ .probe = gpio_sandbox_probe,
+ .ops = &gpio_sandbox_ops,
+};
#include <common.h>
#include <cros_ec.h>
+#include <errno.h>
#include <fdtdec.h>
#include <input.h>
#include <key_matrix.h>
* @param config Keyboard config
* @param keys List of keys that we have detected
* @param max_count Maximum number of keys to return
- * @return number of pressed keys, 0 for none
+ * @param samep Set to true if this scan repeats the last, else false
+ * @return number of pressed keys, 0 for none, -EIO on error
*/
static int check_for_keys(struct keyb *config,
- struct key_matrix_key *keys, int max_count)
+ struct key_matrix_key *keys, int max_count,
+ bool *samep)
{
struct key_matrix_key *key;
+ static struct mbkp_keyscan last_scan;
+ static bool last_scan_valid;
struct mbkp_keyscan scan;
unsigned int row, col, bit, data;
int num_keys;
if (cros_ec_scan_keyboard(config->dev, &scan)) {
debug("%s: keyboard scan failed\n", __func__);
- return -1;
+ return -EIO;
}
+ *samep = last_scan_valid && !memcmp(&last_scan, &scan, sizeof(scan));
+
+ /*
+ * This is a bit odd. The EC has no way to tell us that it has run
+ * out of key scans. It just returns the same scan over and over
+ * again. So the only way to detect that we have run out is to detect
+ * that this scan is the same as the last.
+ */
+ last_scan_valid = true;
+ memcpy(&last_scan, &scan, sizeof(last_scan));
for (col = num_keys = bit = 0; col < config->matrix.num_cols;
col++) {
int keycodes[KBC_MAX_KEYS];
int num_keys, num_keycodes;
int irq_pending, sent;
+ bool same = false;
/*
* Loop until the EC has no more keyscan records, or we have
do {
irq_pending = cros_ec_interrupt_pending(config.dev);
if (irq_pending) {
- num_keys = check_for_keys(&config, keys, KBC_MAX_KEYS);
+ num_keys = check_for_keys(&config, keys, KBC_MAX_KEYS,
+ &same);
+ if (num_keys < 0)
+ return 0;
last_num_keys = num_keys;
memcpy(last_keys, keys, sizeof(keys));
} else {
num_keycodes = key_matrix_decode(&config.matrix, keys,
num_keys, keycodes, KBC_MAX_KEYS);
sent = input_send_keycodes(input, keycodes, num_keycodes);
+
+ /*
+ * For those ECs without an interrupt, stop scanning when we
+ * see that the scan is the same as last time.
+ */
+ if ((irq_pending < 0) && same)
+ break;
} while (irq_pending && !sent);
return 1;
obj-$(CONFIG_CROS_EC) += cros_ec.o
obj-$(CONFIG_CROS_EC_LPC) += cros_ec_lpc.o
obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o
+obj-$(CONFIG_CROS_EC_SANDBOX) += cros_ec_sandbox.o
obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o
obj-$(CONFIG_FSL_IIM) += fsl_iim.o
obj-$(CONFIG_GPIO_LED) += gpio_led.o
*/
/*
- * The Matrix Keyboard Protocol driver handles talking to the keyboard
- * controller chip. Mostly this is for keyboard functions, but some other
- * things have slipped in, so we provide generic services to talk to the
- * KBC.
+ * This is the interface to the Chrome OS EC. It provides keyboard functions,
+ * power control and battery management. Quite a few other functions are
+ * provided to enable the EC software to be updated, talk to the EC's I2C bus
+ * and store a small amount of data in a memory which persists while the EC
+ * is not reset.
*/
#include <common.h>
#include <fdtdec.h>
#include <malloc.h>
#include <spi.h>
+#include <asm/errno.h>
#include <asm/io.h>
#include <asm-generic/gpio.h>
return csum & 0xff;
}
+/**
+ * Create a request packet for protocol version 3.
+ *
+ * The packet is stored in the device's internal output buffer.
+ *
+ * @param dev CROS-EC device
+ * @param cmd Command to send (EC_CMD_...)
+ * @param cmd_version Version of command to send (EC_VER_...)
+ * @param dout Output data (may be NULL If dout_len=0)
+ * @param dout_len Size of output data in bytes
+ * @return packet size in bytes, or <0 if error.
+ */
+static int create_proto3_request(struct cros_ec_dev *dev,
+ int cmd, int cmd_version,
+ const void *dout, int dout_len)
+{
+ struct ec_host_request *rq = (struct ec_host_request *)dev->dout;
+ int out_bytes = dout_len + sizeof(*rq);
+
+ /* Fail if output size is too big */
+ if (out_bytes > (int)sizeof(dev->dout)) {
+ debug("%s: Cannot send %d bytes\n", __func__, dout_len);
+ return -EC_RES_REQUEST_TRUNCATED;
+ }
+
+ /* Fill in request packet */
+ rq->struct_version = EC_HOST_REQUEST_VERSION;
+ rq->checksum = 0;
+ rq->command = cmd;
+ rq->command_version = cmd_version;
+ rq->reserved = 0;
+ rq->data_len = dout_len;
+
+ /* Copy data after header */
+ memcpy(rq + 1, dout, dout_len);
+
+ /* Write checksum field so the entire packet sums to 0 */
+ rq->checksum = (uint8_t)(-cros_ec_calc_checksum(dev->dout, out_bytes));
+
+ cros_ec_dump_data("out", cmd, dev->dout, out_bytes);
+
+ /* Return size of request packet */
+ return out_bytes;
+}
+
+/**
+ * Prepare the device to receive a protocol version 3 response.
+ *
+ * @param dev CROS-EC device
+ * @param din_len Maximum size of response in bytes
+ * @return maximum expected number of bytes in response, or <0 if error.
+ */
+static int prepare_proto3_response_buffer(struct cros_ec_dev *dev, int din_len)
+{
+ int in_bytes = din_len + sizeof(struct ec_host_response);
+
+ /* Fail if input size is too big */
+ if (in_bytes > (int)sizeof(dev->din)) {
+ debug("%s: Cannot receive %d bytes\n", __func__, din_len);
+ return -EC_RES_RESPONSE_TOO_BIG;
+ }
+
+ /* Return expected size of response packet */
+ return in_bytes;
+}
+
+/**
+ * Handle a protocol version 3 response packet.
+ *
+ * The packet must already be stored in the device's internal input buffer.
+ *
+ * @param dev CROS-EC device
+ * @param dinp Returns pointer to response data
+ * @param din_len Maximum size of response in bytes
+ * @return number of bytes of response data, or <0 if error
+ */
+static int handle_proto3_response(struct cros_ec_dev *dev,
+ uint8_t **dinp, int din_len)
+{
+ struct ec_host_response *rs = (struct ec_host_response *)dev->din;
+ int in_bytes;
+ int csum;
+
+ cros_ec_dump_data("in-header", -1, dev->din, sizeof(*rs));
+
+ /* Check input data */
+ if (rs->struct_version != EC_HOST_RESPONSE_VERSION) {
+ debug("%s: EC response version mismatch\n", __func__);
+ return -EC_RES_INVALID_RESPONSE;
+ }
+
+ if (rs->reserved) {
+ debug("%s: EC response reserved != 0\n", __func__);
+ return -EC_RES_INVALID_RESPONSE;
+ }
+
+ if (rs->data_len > din_len) {
+ debug("%s: EC returned too much data\n", __func__);
+ return -EC_RES_RESPONSE_TOO_BIG;
+ }
+
+ cros_ec_dump_data("in-data", -1, dev->din + sizeof(*rs), rs->data_len);
+
+ /* Update in_bytes to actual data size */
+ in_bytes = sizeof(*rs) + rs->data_len;
+
+ /* Verify checksum */
+ csum = cros_ec_calc_checksum(dev->din, in_bytes);
+ if (csum) {
+ debug("%s: EC response checksum invalid: 0x%02x\n", __func__,
+ csum);
+ return -EC_RES_INVALID_CHECKSUM;
+ }
+
+ /* Return error result, if any */
+ if (rs->result)
+ return -(int)rs->result;
+
+ /* If we're still here, set response data pointer and return length */
+ *dinp = (uint8_t *)(rs + 1);
+
+ return rs->data_len;
+}
+
+static int send_command_proto3(struct cros_ec_dev *dev,
+ int cmd, int cmd_version,
+ const void *dout, int dout_len,
+ uint8_t **dinp, int din_len)
+{
+ int out_bytes, in_bytes;
+ int rv;
+
+ /* Create request packet */
+ out_bytes = create_proto3_request(dev, cmd, cmd_version,
+ dout, dout_len);
+ if (out_bytes < 0)
+ return out_bytes;
+
+ /* Prepare response buffer */
+ in_bytes = prepare_proto3_response_buffer(dev, din_len);
+ if (in_bytes < 0)
+ return in_bytes;
+
+ switch (dev->interface) {
+#ifdef CONFIG_CROS_EC_SPI
+ case CROS_EC_IF_SPI:
+ rv = cros_ec_spi_packet(dev, out_bytes, in_bytes);
+ break;
+#endif
+#ifdef CONFIG_CROS_EC_SANDBOX
+ case CROS_EC_IF_SANDBOX:
+ rv = cros_ec_sandbox_packet(dev, out_bytes, in_bytes);
+ break;
+#endif
+ case CROS_EC_IF_NONE:
+ /* TODO: support protocol 3 for LPC, I2C; for now fall through */
+ default:
+ debug("%s: Unsupported interface\n", __func__);
+ rv = -1;
+ }
+ if (rv < 0)
+ return rv;
+
+ /* Process the response */
+ return handle_proto3_response(dev, dinp, din_len);
+}
+
static int send_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version,
const void *dout, int dout_len,
uint8_t **dinp, int din_len)
{
- int ret;
+ int ret = -1;
+
+ /* Handle protocol version 3 support */
+ if (dev->protocol_version == 3) {
+ return send_command_proto3(dev, cmd, cmd_version,
+ dout, dout_len, dinp, din_len);
+ }
switch (dev->interface) {
#ifdef CONFIG_CROS_EC_SPI
int cmd_version, const void *dout, int dout_len, uint8_t **dinp,
int din_len)
{
- uint8_t *din;
+ uint8_t *din = NULL;
int len;
- if (cmd_version != 0 && !dev->cmd_version_is_supported) {
- debug("%s: Command version >0 unsupported\n", __func__);
- return -1;
- }
len = send_command(dev, cmd, cmd_version, dout, dout_len,
&din, din_len);
/* If the command doesn't complete, wait a while */
if (len == -EC_RES_IN_PROGRESS) {
- struct ec_response_get_comms_status *resp;
+ struct ec_response_get_comms_status *resp = NULL;
ulong start;
/* Wait for command to complete */
NULL, 0, &din, din_len);
}
- debug("%s: len=%d, dinp=%p, *dinp=%p\n", __func__, len, dinp, *dinp);
+ debug("%s: len=%d, dinp=%p, *dinp=%p\n", __func__, len, dinp,
+ dinp ? *dinp : NULL);
if (dinp) {
/* If we have any data to return, it must be 64bit-aligned */
assert(len <= 0 || !((uintptr_t)din & 7));
int cros_ec_scan_keyboard(struct cros_ec_dev *dev, struct mbkp_keyscan *scan)
{
- if (ec_command(dev, EC_CMD_CROS_EC_STATE, 0, NULL, 0, scan,
- sizeof(scan->data)) < sizeof(scan->data))
+ if (ec_command(dev, EC_CMD_MKBP_STATE, 0, NULL, 0, scan,
+ sizeof(scan->data)) != sizeof(scan->data))
return -1;
return 0;
struct ec_response_get_version *r;
if (ec_command_inptr(dev, EC_CMD_GET_VERSION, 0, NULL, 0,
- (uint8_t **)&r, sizeof(*r)) < sizeof(*r))
+ (uint8_t **)&r, sizeof(*r)) != sizeof(*r))
return -1;
- if (maxlen > sizeof(r->version_string_ro))
+ if (maxlen > (int)sizeof(r->version_string_ro))
maxlen = sizeof(r->version_string_ro);
switch (r->current_image) {
{
if (ec_command_inptr(dev, EC_CMD_GET_VERSION, 0, NULL, 0,
(uint8_t **)versionp, sizeof(**versionp))
- < sizeof(**versionp))
+ != sizeof(**versionp))
return -1;
return 0;
int cros_ec_read_build_info(struct cros_ec_dev *dev, char **strp)
{
if (ec_command_inptr(dev, EC_CMD_GET_BUILD_INFO, 0, NULL, 0,
- (uint8_t **)strp, EC_HOST_PARAM_SIZE) < 0)
+ (uint8_t **)strp, EC_PROTO2_MAX_PARAM_SIZE) < 0)
return -1;
return 0;
struct ec_response_get_version *r;
if (ec_command_inptr(dev, EC_CMD_GET_VERSION, 0, NULL, 0,
- (uint8_t **)&r, sizeof(*r)) < sizeof(*r))
+ (uint8_t **)&r, sizeof(*r)) != sizeof(*r))
return -1;
*image = r->current_image;
debug("%s: No valid hash (status=%d size=%d). Compute one...\n",
__func__, hash->status, hash->size);
- p.cmd = EC_VBOOT_HASH_RECALC;
+ p.cmd = EC_VBOOT_HASH_START;
p.hash_type = EC_VBOOT_HASH_TYPE_SHA256;
p.nonce_size = 0;
p.offset = EC_VBOOT_HASH_OFFSET_RW;
{
/* no interrupt support : always poll */
if (!fdt_gpio_isvalid(&dev->ec_int))
- return 1;
+ return -ENOENT;
return !gpio_get_value(dev->ec_int.gpio);
}
-int cros_ec_info(struct cros_ec_dev *dev, struct ec_response_cros_ec_info *info)
+int cros_ec_info(struct cros_ec_dev *dev, struct ec_response_mkbp_info *info)
{
- if (ec_command(dev, EC_CMD_CROS_EC_INFO, 0, NULL, 0, info,
- sizeof(*info)) < sizeof(*info))
+ if (ec_command(dev, EC_CMD_MKBP_INFO, 0, NULL, 0, info,
+ sizeof(*info)) != sizeof(*info))
return -1;
return 0;
* used by ACPI/SMI.
*/
if (ec_command_inptr(dev, EC_CMD_HOST_EVENT_GET_B, 0, NULL, 0,
- (uint8_t **)&resp, sizeof(*resp)) < sizeof(*resp))
+ (uint8_t **)&resp, sizeof(*resp)) < (int)sizeof(*resp))
return -1;
if (resp->mask & EC_HOST_EVENT_MASK(EC_HOST_EVENT_INVALID))
if (ec_command(dev, EC_CMD_FLASH_PROTECT, EC_VER_FLASH_PROTECT,
¶ms, sizeof(params),
- resp, sizeof(*resp)) < sizeof(*resp))
+ resp, sizeof(*resp)) != sizeof(*resp))
return -1;
return 0;
*
* So for now, just read all the data anyway.
*/
- dev->cmd_version_is_supported = 1;
+
+ /* Try sending a version 3 packet */
+ dev->protocol_version = 3;
+ if (ec_command_inptr(dev, EC_CMD_HELLO, 0, &req, sizeof(req),
+ (uint8_t **)&resp, sizeof(*resp)) > 0) {
+ return 0;
+ }
+
+ /* Try sending a version 2 packet */
+ dev->protocol_version = 2;
if (ec_command_inptr(dev, EC_CMD_HELLO, 0, &req, sizeof(req),
(uint8_t **)&resp, sizeof(*resp)) > 0) {
- /* It appears to understand new version commands */
- dev->cmd_version_is_supported = 1;
- } else {
- dev->cmd_version_is_supported = 0;
- if (ec_command_inptr(dev, EC_CMD_HELLO, 0, &req,
- sizeof(req), (uint8_t **)&resp,
- sizeof(*resp)) < 0) {
- debug("%s: Failed both old and new command style\n",
- __func__);
- return -1;
- }
+ return 0;
}
- return 0;
+ /*
+ * Fail if we're still here, since the EC doesn't understand any
+ * protcol version we speak. Version 1 interface without command
+ * version is no longer supported, and we don't know about any new
+ * protocol versions.
+ */
+ dev->protocol_version = 0;
+ printf("%s: ERROR: old EC interface not supported\n", __func__);
+ return -1;
}
int cros_ec_test(struct cros_ec_dev *dev)
p.offset = offset;
p.size = size;
- assert(data && p.size <= sizeof(p.data));
- memcpy(p.data, data, p.size);
+ assert(data && p.size <= EC_FLASH_WRITE_VER0_SIZE);
+ memcpy(&p + 1, data, p.size);
return ec_command_inptr(dev, EC_CMD_FLASH_WRITE, 0,
&p, sizeof(p), NULL, 0) >= 0 ? 0 : -1;
*/
static int cros_ec_flash_write_burst_size(struct cros_ec_dev *dev)
{
- struct ec_params_flash_write p;
- return sizeof(p.data);
+ return EC_FLASH_WRITE_VER0_SIZE;
}
/**
if (cros_ec_flash_offset(dev, EC_FLASH_REGION_RW, &rw_offset, &rw_size))
return -1;
- if (image_size > rw_size)
+ if (image_size > (int)rw_size)
return -1;
/* Invalidate the existing hash, just in case the AP reboots
if (ec_command_inptr(dev, EC_CMD_LDO_GET, 0,
¶ms, sizeof(params),
- (uint8_t **)&resp, sizeof(*resp)) < sizeof(*resp))
+ (uint8_t **)&resp, sizeof(*resp)) != sizeof(*resp))
return -1;
*state = resp->state;
}
/**
- * Decode MBKP details from the device tree and allocate a suitable device.
+ * Decode EC interface details from the device tree and allocate a suitable
+ * device.
*
* @param blob Device tree blob
* @param node Node to decode from
case COMPAT_INTEL_LPC:
dev->interface = CROS_EC_IF_LPC;
break;
+#endif
+#ifdef CONFIG_CROS_EC_SANDBOX
+ case COMPAT_SANDBOX_HOST_EMULATION:
+ dev->interface = CROS_EC_IF_SANDBOX;
+ break;
#endif
default:
debug("%s: Unknown compat id %d\n", __func__, compat);
if (cros_ec_lpc_init(dev, blob))
return -CROS_EC_ERR_DEV_INIT;
break;
+#endif
+#ifdef CONFIG_CROS_EC_SANDBOX
+ case CROS_EC_IF_SANDBOX:
+ if (cros_ec_sandbox_init(dev, blob))
+ return -CROS_EC_ERR_DEV_INIT;
+ break;
#endif
case CROS_EC_IF_NONE:
default:
return 0;
}
-#ifdef CONFIG_CMD_CROS_EC
int cros_ec_decode_region(int argc, char * const argv[])
{
if (argc > 0) {
return -1;
}
+int cros_ec_decode_ec_flash(const void *blob, struct fdt_cros_ec *config)
+{
+ int flash_node, node;
+
+ node = fdtdec_next_compatible(blob, 0, COMPAT_GOOGLE_CROS_EC);
+ if (node < 0) {
+ debug("Failed to find chrome-ec node'\n");
+ return -1;
+ }
+
+ flash_node = fdt_subnode_offset(blob, node, "flash");
+ if (flash_node < 0) {
+ debug("Failed to find flash node\n");
+ return -1;
+ }
+
+ if (fdtdec_read_fmap_entry(blob, flash_node, "flash",
+ &config->flash)) {
+ debug("Failed to decode flash node in chrome-ec'\n");
+ return -1;
+ }
+
+ config->flash_erase_value = fdtdec_get_int(blob, flash_node,
+ "erase-value", -1);
+ for (node = fdt_first_subnode(blob, flash_node); node >= 0;
+ node = fdt_next_subnode(blob, node)) {
+ const char *name = fdt_get_name(blob, node, NULL);
+ enum ec_flash_region region;
+
+ if (0 == strcmp(name, "ro")) {
+ region = EC_FLASH_REGION_RO;
+ } else if (0 == strcmp(name, "rw")) {
+ region = EC_FLASH_REGION_RW;
+ } else if (0 == strcmp(name, "wp-ro")) {
+ region = EC_FLASH_REGION_WP_RO;
+ } else {
+ debug("Unknown EC flash region name '%s'\n", name);
+ return -1;
+ }
+
+ if (fdtdec_read_fmap_entry(blob, node, "reg",
+ &config->region[region])) {
+ debug("Failed to decode flash region in chrome-ec'\n");
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
+int cros_ec_i2c_xfer(struct cros_ec_dev *dev, uchar chip, uint addr,
+ int alen, uchar *buffer, int len, int is_read)
+{
+ union {
+ struct ec_params_i2c_passthru p;
+ uint8_t outbuf[EC_PROTO2_MAX_PARAM_SIZE];
+ } params;
+ union {
+ struct ec_response_i2c_passthru r;
+ uint8_t inbuf[EC_PROTO2_MAX_PARAM_SIZE];
+ } response;
+ struct ec_params_i2c_passthru *p = ¶ms.p;
+ struct ec_response_i2c_passthru *r = &response.r;
+ struct ec_params_i2c_passthru_msg *msg = p->msg;
+ uint8_t *pdata;
+ int read_len, write_len;
+ int size;
+ int rv;
+
+ p->port = 0;
+
+ if (alen != 1) {
+ printf("Unsupported address length %d\n", alen);
+ return -1;
+ }
+ if (is_read) {
+ read_len = len;
+ write_len = alen;
+ p->num_msgs = 2;
+ } else {
+ read_len = 0;
+ write_len = alen + len;
+ p->num_msgs = 1;
+ }
+
+ size = sizeof(*p) + p->num_msgs * sizeof(*msg);
+ if (size + write_len > sizeof(params)) {
+ puts("Params too large for buffer\n");
+ return -1;
+ }
+ if (sizeof(*r) + read_len > sizeof(response)) {
+ puts("Read length too big for buffer\n");
+ return -1;
+ }
+
+ /* Create a message to write the register address and optional data */
+ pdata = (uint8_t *)p + size;
+ msg->addr_flags = chip;
+ msg->len = write_len;
+ pdata[0] = addr;
+ if (!is_read)
+ memcpy(pdata + 1, buffer, len);
+ msg++;
+
+ if (read_len) {
+ msg->addr_flags = chip | EC_I2C_FLAG_READ;
+ msg->len = read_len;
+ }
+
+ rv = ec_command(dev, EC_CMD_I2C_PASSTHRU, 0, p, size + write_len,
+ r, sizeof(*r) + read_len);
+ if (rv < 0)
+ return rv;
+
+ /* Parse response */
+ if (r->i2c_status & EC_I2C_STATUS_ERROR) {
+ printf("Transfer failed with status=0x%x\n", r->i2c_status);
+ return -1;
+ }
+
+ if (rv < sizeof(*r) + read_len) {
+ puts("Truncated read response\n");
+ return -1;
+ }
+
+ if (read_len)
+ memcpy(buffer, r->data, read_len);
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_CROS_EC
+
/**
* Perform a flash read or write command
*
return 0;
}
+/**
+ * get_alen() - Small parser helper function to get address length
+ *
+ * Returns the address length.
+ */
+static uint get_alen(char *arg)
+{
+ int j;
+ int alen;
+
+ alen = 1;
+ for (j = 0; j < 8; j++) {
+ if (arg[j] == '.') {
+ alen = arg[j+1] - '0';
+ break;
+ } else if (arg[j] == '\0') {
+ break;
+ }
+ }
+ return alen;
+}
+
+#define DISP_LINE_LEN 16
+
+/*
+ * TODO(sjg@chromium.org): This code copied almost verbatim from cmd_i2c.c
+ * so we can remove it later.
+ */
+static int cros_ec_i2c_md(struct cros_ec_dev *dev, int flag, int argc,
+ char * const argv[])
+{
+ u_char chip;
+ uint addr, alen, length = 0x10;
+ int j, nbytes, linebytes;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ if (1 || (flag & CMD_FLAG_REPEAT) == 0) {
+ /*
+ * New command specified.
+ */
+
+ /*
+ * I2C chip address
+ */
+ chip = simple_strtoul(argv[0], NULL, 16);
+
+ /*
+ * I2C data address within the chip. This can be 1 or
+ * 2 bytes long. Some day it might be 3 bytes long :-).
+ */
+ addr = simple_strtoul(argv[1], NULL, 16);
+ alen = get_alen(argv[1]);
+ if (alen > 3)
+ return CMD_RET_USAGE;
+
+ /*
+ * If another parameter, it is the length to display.
+ * Length is the number of objects, not number of bytes.
+ */
+ if (argc > 2)
+ length = simple_strtoul(argv[2], NULL, 16);
+ }
+
+ /*
+ * Print the lines.
+ *
+ * We buffer all read data, so we can make sure data is read only
+ * once.
+ */
+ nbytes = length;
+ do {
+ unsigned char linebuf[DISP_LINE_LEN];
+ unsigned char *cp;
+
+ linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
+
+ if (cros_ec_i2c_xfer(dev, chip, addr, alen, linebuf, linebytes,
+ 1))
+ puts("Error reading the chip.\n");
+ else {
+ printf("%04x:", addr);
+ cp = linebuf;
+ for (j = 0; j < linebytes; j++) {
+ printf(" %02x", *cp++);
+ addr++;
+ }
+ puts(" ");
+ cp = linebuf;
+ for (j = 0; j < linebytes; j++) {
+ if ((*cp < 0x20) || (*cp > 0x7e))
+ puts(".");
+ else
+ printf("%c", *cp);
+ cp++;
+ }
+ putc('\n');
+ }
+ nbytes -= linebytes;
+ } while (nbytes > 0);
+
+ return 0;
+}
+
+static int cros_ec_i2c_mw(struct cros_ec_dev *dev, int flag, int argc,
+ char * const argv[])
+{
+ uchar chip;
+ ulong addr;
+ uint alen;
+ uchar byte;
+ int count;
+
+ if ((argc < 3) || (argc > 4))
+ return CMD_RET_USAGE;
+
+ /*
+ * Chip is always specified.
+ */
+ chip = simple_strtoul(argv[0], NULL, 16);
+
+ /*
+ * Address is always specified.
+ */
+ addr = simple_strtoul(argv[1], NULL, 16);
+ alen = get_alen(argv[1]);
+ if (alen > 3)
+ return CMD_RET_USAGE;
+
+ /*
+ * Value to write is always specified.
+ */
+ byte = simple_strtoul(argv[2], NULL, 16);
+
+ /*
+ * Optional count
+ */
+ if (argc == 4)
+ count = simple_strtoul(argv[3], NULL, 16);
+ else
+ count = 1;
+
+ while (count-- > 0) {
+ if (cros_ec_i2c_xfer(dev, chip, addr++, alen, &byte, 1, 0))
+ puts("Error writing the chip.\n");
+ /*
+ * Wait for the write to complete. The write can take
+ * up to 10mSec (we allow a little more time).
+ */
+/*
+ * No write delay with FRAM devices.
+ */
+#if !defined(CONFIG_SYS_I2C_FRAM)
+ udelay(11000);
+#endif
+ }
+
+ return 0;
+}
+
+/* Temporary code until we have driver model and can use the i2c command */
+static int cros_ec_i2c_passthrough(struct cros_ec_dev *dev, int flag,
+ int argc, char * const argv[])
+{
+ const char *cmd;
+
+ if (argc < 1)
+ return CMD_RET_USAGE;
+ cmd = *argv++;
+ argc--;
+ if (0 == strcmp("md", cmd))
+ cros_ec_i2c_md(dev, flag, argc, argv);
+ else if (0 == strcmp("mw", cmd))
+ cros_ec_i2c_mw(dev, flag, argc, argv);
+ else
+ return CMD_RET_USAGE;
+
+ return 0;
+}
+
static int do_cros_ec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
struct cros_ec_dev *dev = last_dev;
}
printf("%s\n", id);
} else if (0 == strcmp("info", cmd)) {
- struct ec_response_cros_ec_info info;
+ struct ec_response_mkbp_info info;
if (cros_ec_info(dev, &info)) {
debug("%s: Could not read KBC info\n", __func__);
if (!ret) {
/* Print versions */
printf("RO version: %1.*s\n",
- sizeof(p->version_string_ro),
+ (int)sizeof(p->version_string_ro),
p->version_string_ro);
printf("RW version: %1.*s\n",
- sizeof(p->version_string_rw),
+ (int)sizeof(p->version_string_rw),
p->version_string_rw);
printf("Firmware copy: %s\n",
(p->current_image <
debug("%s: Could not access LDO%d\n", __func__, index);
return ret;
}
+ } else if (0 == strcmp("i2c", cmd)) {
+ ret = cros_ec_i2c_passthrough(dev, flag, argc - 2, argv + 2);
} else {
return CMD_RET_USAGE;
}
}
U_BOOT_CMD(
- crosec, 5, 1, do_cros_ec,
+ crosec, 6, 1, do_cros_ec,
"CROS-EC utility command",
"init Re-init CROS-EC (done on startup automatically)\n"
"crosec id Read CROS-EC ID\n"
"crosec vbnvcontext [hexstring] Read [write] VbNvContext from EC\n"
"crosec ldo <idx> [<state>] Switch/Read LDO state\n"
"crosec test run tests on cros_ec\n"
- "crosec version Read CROS-EC version"
+ "crosec version Read CROS-EC version\n"
+ "crosec i2c md chip address[.0, .1, .2] [# of objects] - read from I2C passthru\n"
+ "crosec i2c mw chip address[.0, .1, .2] value [count] - write to I2C passthru (fill)"
);
#endif
uint8_t *ptr;
/* Receive input data, so that args will be dword aligned */
uint8_t *in_ptr;
- int ret;
+ int len, csum, ret;
old_bus = i2c_get_bus_num();
* will be dword aligned.
*/
in_ptr = dev->din + sizeof(int64_t);
- if (!dev->cmd_version_is_supported) {
- /* Send an old-style command */
- *ptr++ = cmd;
- out_bytes = dout_len + 1;
- in_bytes = din_len + 2;
- in_ptr--; /* Expect just a status byte */
- } else {
- *ptr++ = EC_CMD_VERSION0 + cmd_version;
- *ptr++ = cmd;
- *ptr++ = dout_len;
- in_ptr -= 2; /* Expect status, length bytes */
+
+ if (dev->protocol_version != 2) {
+ /* Something we don't support */
+ debug("%s: Protocol version %d unsupported\n",
+ __func__, dev->protocol_version);
+ return -1;
}
+
+ *ptr++ = EC_CMD_VERSION0 + cmd_version;
+ *ptr++ = cmd;
+ *ptr++ = dout_len;
+ in_ptr -= 2; /* Expect status, length bytes */
+
memcpy(ptr, dout, dout_len);
ptr += dout_len;
- if (dev->cmd_version_is_supported)
- *ptr++ = (uint8_t)
- cros_ec_calc_checksum(dev->dout, dout_len + 3);
+ *ptr++ = (uint8_t)
+ cros_ec_calc_checksum(dev->dout, dout_len + 3);
/* Set to the proper i2c bus */
if (i2c_set_bus_num(dev->bus_num)) {
return -(int)*in_ptr;
}
- if (dev->cmd_version_is_supported) {
- int len, csum;
-
- len = in_ptr[1];
- if (len + 3 > sizeof(dev->din)) {
- debug("%s: Received length %#02x too large\n",
- __func__, len);
- return -1;
- }
- csum = cros_ec_calc_checksum(in_ptr, 2 + len);
- if (csum != in_ptr[2 + len]) {
- debug("%s: Invalid checksum rx %#02x, calced %#02x\n",
- __func__, in_ptr[2 + din_len], csum);
- return -1;
- }
- din_len = min(din_len, len);
- cros_ec_dump_data("in", -1, in_ptr, din_len + 3);
- } else {
- cros_ec_dump_data("in (old)", -1, in_ptr, in_bytes);
+ len = in_ptr[1];
+ if (len + 3 > sizeof(dev->din)) {
+ debug("%s: Received length %#02x too large\n",
+ __func__, len);
+ return -1;
}
+ csum = cros_ec_calc_checksum(in_ptr, 2 + len);
+ if (csum != in_ptr[2 + len]) {
+ debug("%s: Invalid checksum rx %#02x, calced %#02x\n",
+ __func__, in_ptr[2 + din_len], csum);
+ return -1;
+ }
+ din_len = min(din_len, len);
+ cros_ec_dump_data("in", -1, in_ptr, din_len + 3);
/* Return pointer to dword-aligned input data, if any */
*dinp = dev->din + sizeof(int64_t);
{
i2c_init(dev->max_frequency, dev->addr);
- dev->cmd_version_is_supported = 0;
-
return 0;
}
return 0;
}
-/**
- * Send a command to a LPC CROS_EC device and return the reply.
- *
- * The device's internal input/output buffers are used.
- *
- * @param dev CROS_EC device
- * @param cmd Command to send (EC_CMD_...)
- * @param cmd_version Version of command to send (EC_VER_...)
- * @param dout Output data (may be NULL If dout_len=0)
- * @param dout_len Size of output data in bytes
- * @param dinp Place to put pointer to response data
- * @param din_len Maximum size of response in bytes
- * @return number of bytes in response, or -1 on error
- */
-static int old_lpc_command(struct cros_ec_dev *dev, uint8_t cmd,
- const uint8_t *dout, int dout_len,
- uint8_t **dinp, int din_len)
-{
- int ret, i;
-
- if (dout_len > EC_OLD_PARAM_SIZE) {
- debug("%s: Cannot send %d bytes\n", __func__, dout_len);
- return -1;
- }
-
- if (din_len > EC_OLD_PARAM_SIZE) {
- debug("%s: Cannot receive %d bytes\n", __func__, din_len);
- return -1;
- }
-
- if (wait_for_sync(dev)) {
- debug("%s: Timeout waiting ready\n", __func__);
- return -1;
- }
-
- debug_trace("cmd: %02x, ", cmd);
- for (i = 0; i < dout_len; i++) {
- debug_trace("%02x ", dout[i]);
- outb(dout[i], EC_LPC_ADDR_OLD_PARAM + i);
- }
- outb(cmd, EC_LPC_ADDR_HOST_CMD);
- debug_trace("\n");
-
- if (wait_for_sync(dev)) {
- debug("%s: Timeout waiting ready\n", __func__);
- return -1;
- }
-
- ret = inb(EC_LPC_ADDR_HOST_DATA);
- if (ret) {
- debug("%s: CROS_EC result code %d\n", __func__, ret);
- return -ret;
- }
-
- debug_trace("resp: %02x, ", ret);
- for (i = 0; i < din_len; i++) {
- dev->din[i] = inb(EC_LPC_ADDR_OLD_PARAM + i);
- debug_trace("%02x ", dev->din[i]);
- }
- debug_trace("\n");
- *dinp = dev->din;
-
- return din_len;
-}
-
int cros_ec_lpc_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version,
const uint8_t *dout, int dout_len,
uint8_t **dinp, int din_len)
int csum;
int i;
- /* Fall back to old-style command interface if args aren't supported */
- if (!dev->cmd_version_is_supported)
- return old_lpc_command(dev, cmd, dout, dout_len, dinp,
- din_len);
-
if (dout_len > EC_HOST_PARAM_SIZE) {
debug("%s: Cannot send %d bytes\n", __func__, dout_len);
return -1;
(inb(EC_LPC_ADDR_MEMMAP +
EC_MEMMAP_HOST_CMD_FLAGS) &
EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED)) {
- dev->cmd_version_is_supported = 1;
- } else {
- /* We are going to use the old IO ports */
- dev->cmd_version_is_supported = 0;
+ return 0;
}
- debug("lpc: version %s\n", dev->cmd_version_is_supported ?
- "new" : "old");
- return 0;
+ printf("%s: ERROR: old EC interface not supported\n", __func__);
+ return -1;
}
--- /dev/null
+/*
+ * Chromium OS cros_ec driver - sandbox emulation
+ *
+ * Copyright (c) 2013 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <cros_ec.h>
+#include <ec_commands.h>
+#include <errno.h>
+#include <hash.h>
+#include <malloc.h>
+#include <os.h>
+#include <sha256.h>
+#include <spi.h>
+#include <asm/state.h>
+#include <asm/sdl.h>
+#include <linux/input.h>
+
+/*
+ * Ultimately it shold be possible to connect an Chrome OS EC emulation
+ * to U-Boot and remove all of this code. But this provides a test
+ * environment for bringing up chromeos_sandbox and demonstrating its
+ * utility.
+ *
+ * This emulation includes the following:
+ *
+ * 1. Emulation of the keyboard, by converting keypresses received from SDL
+ * into key scan data, passed back from the EC as key scan messages. The
+ * key layout is read from the device tree.
+ *
+ * 2. Emulation of vboot context - so this can be read/written as required.
+ *
+ * 3. Save/restore of EC state, so that the vboot context, flash memory
+ * contents and current image can be preserved across boots. This is important
+ * since the EC is supposed to continue running even if the AP resets.
+ *
+ * 4. Some event support, in particular allowing Escape to be pressed on boot
+ * to enter recovery mode. The EC passes this to U-Boot through the normal
+ * event message.
+ *
+ * 5. Flash read/write/erase support, so that software sync works. The
+ * protect messages are supported but no protection is implemented.
+ *
+ * 6. Hashing of the EC image, again to support software sync.
+ *
+ * Other features can be added, although a better path is probably to link
+ * the EC image in with U-Boot (Vic has demonstrated a prototype for this).
+ */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define KEYBOARD_ROWS 8
+#define KEYBOARD_COLS 13
+
+/* A single entry of the key matrix */
+struct ec_keymatrix_entry {
+ int row; /* key matrix row */
+ int col; /* key matrix column */
+ int keycode; /* corresponding linux key code */
+};
+
+/**
+ * struct ec_state - Information about the EC state
+ *
+ * @vbnv_context: Vboot context data stored by EC
+ * @ec_config: FDT config information about the EC (e.g. flashmap)
+ * @flash_data: Contents of flash memory
+ * @flash_data_len: Size of flash memory
+ * @current_image: Current image the EC is running
+ * @matrix_count: Number of keys to decode in matrix
+ * @matrix: Information about keyboard matrix
+ * @keyscan: Current keyscan information (bit set for each row/column pressed)
+ * @recovery_req: Keyboard recovery requested
+ */
+struct ec_state {
+ uint8_t vbnv_context[EC_VBNV_BLOCK_SIZE];
+ struct fdt_cros_ec ec_config;
+ uint8_t *flash_data;
+ int flash_data_len;
+ enum ec_current_image current_image;
+ int matrix_count;
+ struct ec_keymatrix_entry *matrix; /* the key matrix info */
+ uint8_t keyscan[KEYBOARD_COLS];
+ bool recovery_req;
+} s_state, *state;
+
+/**
+ * cros_ec_read_state() - read the sandbox EC state from the state file
+ *
+ * If data is available, then blob and node will provide access to it. If
+ * not this function sets up an empty EC.
+ *
+ * @param blob: Pointer to device tree blob, or NULL if no data to read
+ * @param node: Node offset to read from
+ */
+static int cros_ec_read_state(const void *blob, int node)
+{
+ struct ec_state *ec = &s_state;
+ const char *prop;
+ int len;
+
+ /* Set everything to defaults */
+ ec->current_image = EC_IMAGE_RO;
+ if (!blob)
+ return 0;
+
+ /* Read the data if available */
+ ec->current_image = fdtdec_get_int(blob, node, "current-image",
+ EC_IMAGE_RO);
+ prop = fdt_getprop(blob, node, "vbnv-context", &len);
+ if (prop && len == sizeof(ec->vbnv_context))
+ memcpy(ec->vbnv_context, prop, len);
+
+ prop = fdt_getprop(blob, node, "flash-data", &len);
+ if (prop) {
+ ec->flash_data_len = len;
+ ec->flash_data = os_malloc(len);
+ if (!ec->flash_data)
+ return -ENOMEM;
+ memcpy(ec->flash_data, prop, len);
+ debug("%s: Loaded EC flash data size %#x\n", __func__, len);
+ }
+
+ return 0;
+}
+
+/**
+ * cros_ec_write_state() - Write out our state to the state file
+ *
+ * The caller will ensure that there is a node ready for the state. The node
+ * may already contain the old state, in which case it is overridden.
+ *
+ * @param blob: Device tree blob holding state
+ * @param node: Node to write our state into
+ */
+static int cros_ec_write_state(void *blob, int node)
+{
+ struct ec_state *ec = &s_state;
+
+ /* We are guaranteed enough space to write basic properties */
+ fdt_setprop_u32(blob, node, "current-image", ec->current_image);
+ fdt_setprop(blob, node, "vbnv-context", ec->vbnv_context,
+ sizeof(ec->vbnv_context));
+ return state_setprop(node, "flash-data", ec->flash_data,
+ ec->ec_config.flash.length);
+}
+
+SANDBOX_STATE_IO(cros_ec, "google,cros-ec", cros_ec_read_state,
+ cros_ec_write_state);
+
+/**
+ * Return the number of bytes used in the specified image.
+ *
+ * This is the actual size of code+data in the image, as opposed to the
+ * amount of space reserved in flash for that image. This code is similar to
+ * that used by the real EC code base.
+ *
+ * @param ec Current emulated EC state
+ * @param entry Flash map entry containing the image to check
+ * @return actual image size in bytes, 0 if the image contains no content or
+ * error.
+ */
+static int get_image_used(struct ec_state *ec, struct fmap_entry *entry)
+{
+ int size;
+
+ /*
+ * Scan backwards looking for 0xea byte, which is by definition the
+ * last byte of the image. See ec.lds.S for how this is inserted at
+ * the end of the image.
+ */
+ for (size = entry->length - 1;
+ size > 0 && ec->flash_data[entry->offset + size] != 0xea;
+ size--)
+ ;
+
+ return size ? size + 1 : 0; /* 0xea byte IS part of the image */
+}
+
+/**
+ * Read the key matrix from the device tree
+ *
+ * Keymap entries in the fdt take the form of 0xRRCCKKKK where
+ * RR=Row CC=Column KKKK=Key Code
+ *
+ * @param ec Current emulated EC state
+ * @param blob Device tree blob containing keyscan information
+ * @param node Keyboard node of device tree containing keyscan information
+ * @return 0 if ok, -1 on error
+ */
+static int keyscan_read_fdt_matrix(struct ec_state *ec, const void *blob,
+ int node)
+{
+ const u32 *cell;
+ int upto;
+ int len;
+
+ cell = fdt_getprop(blob, node, "linux,keymap", &len);
+ ec->matrix_count = len / 4;
+ ec->matrix = calloc(ec->matrix_count, sizeof(*ec->matrix));
+ if (!ec->matrix) {
+ debug("%s: Out of memory for key matrix\n", __func__);
+ return -1;
+ }
+
+ /* Now read the data */
+ for (upto = 0; upto < ec->matrix_count; upto++) {
+ struct ec_keymatrix_entry *matrix = &ec->matrix[upto];
+ u32 word;
+
+ word = fdt32_to_cpu(*cell++);
+ matrix->row = word >> 24;
+ matrix->col = (word >> 16) & 0xff;
+ matrix->keycode = word & 0xffff;
+
+ /* Hard-code some sanity limits for now */
+ if (matrix->row >= KEYBOARD_ROWS ||
+ matrix->col >= KEYBOARD_COLS) {
+ debug("%s: Matrix pos out of range (%d,%d)\n",
+ __func__, matrix->row, matrix->col);
+ return -1;
+ }
+ }
+
+ if (upto != ec->matrix_count) {
+ debug("%s: Read mismatch from key matrix\n", __func__);
+ return -1;
+ }
+
+ return 0;
+}
+
+/**
+ * Return the next keyscan message contents
+ *
+ * @param ec Current emulated EC state
+ * @param scan Place to put keyscan bytes for the keyscan message (must hold
+ * enough space for a full keyscan)
+ * @return number of bytes of valid scan data
+ */
+static int cros_ec_keyscan(struct ec_state *ec, uint8_t *scan)
+{
+ const struct ec_keymatrix_entry *matrix;
+ int bytes = KEYBOARD_COLS;
+ int key[8]; /* allow up to 8 keys to be pressed at once */
+ int count;
+ int i;
+
+ memset(ec->keyscan, '\0', bytes);
+ count = sandbox_sdl_scan_keys(key, ARRAY_SIZE(key));
+
+ /* Look up keycode in matrix */
+ for (i = 0, matrix = ec->matrix; i < ec->matrix_count; i++, matrix++) {
+ bool found;
+ int j;
+
+ for (found = false, j = 0; j < count; j++) {
+ if (matrix->keycode == key[j])
+ found = true;
+ }
+
+ if (found) {
+ debug("%d: %d,%d\n", matrix->keycode, matrix->row,
+ matrix->col);
+ ec->keyscan[matrix->col] |= 1 << matrix->row;
+ }
+ }
+
+ memcpy(scan, ec->keyscan, bytes);
+ return bytes;
+}
+
+/**
+ * Process an emulated EC command
+ *
+ * @param ec Current emulated EC state
+ * @param req_hdr Pointer to request header
+ * @param req_data Pointer to body of request
+ * @param resp_hdr Pointer to place to put response header
+ * @param resp_data Pointer to place to put response data, if any
+ * @return length of response data, or 0 for no response data, or -1 on error
+ */
+static int process_cmd(struct ec_state *ec,
+ struct ec_host_request *req_hdr, const void *req_data,
+ struct ec_host_response *resp_hdr, void *resp_data)
+{
+ int len;
+
+ /* TODO(sjg@chromium.org): Check checksums */
+ debug("EC command %#0x\n", req_hdr->command);
+
+ switch (req_hdr->command) {
+ case EC_CMD_HELLO: {
+ const struct ec_params_hello *req = req_data;
+ struct ec_response_hello *resp = resp_data;
+
+ resp->out_data = req->in_data + 0x01020304;
+ len = sizeof(*resp);
+ break;
+ }
+ case EC_CMD_GET_VERSION: {
+ struct ec_response_get_version *resp = resp_data;
+
+ strcpy(resp->version_string_ro, "sandbox_ro");
+ strcpy(resp->version_string_rw, "sandbox_rw");
+ resp->current_image = ec->current_image;
+ debug("Current image %d\n", resp->current_image);
+ len = sizeof(*resp);
+ break;
+ }
+ case EC_CMD_VBNV_CONTEXT: {
+ const struct ec_params_vbnvcontext *req = req_data;
+ struct ec_response_vbnvcontext *resp = resp_data;
+
+ switch (req->op) {
+ case EC_VBNV_CONTEXT_OP_READ:
+ memcpy(resp->block, ec->vbnv_context,
+ sizeof(resp->block));
+ len = sizeof(*resp);
+ break;
+ case EC_VBNV_CONTEXT_OP_WRITE:
+ memcpy(ec->vbnv_context, resp->block,
+ sizeof(resp->block));
+ len = 0;
+ break;
+ default:
+ printf(" ** Unknown vbnv_context command %#02x\n",
+ req->op);
+ return -1;
+ }
+ break;
+ }
+ case EC_CMD_REBOOT_EC: {
+ const struct ec_params_reboot_ec *req = req_data;
+
+ printf("Request reboot type %d\n", req->cmd);
+ switch (req->cmd) {
+ case EC_REBOOT_DISABLE_JUMP:
+ len = 0;
+ break;
+ case EC_REBOOT_JUMP_RW:
+ ec->current_image = EC_IMAGE_RW;
+ len = 0;
+ break;
+ default:
+ puts(" ** Unknown type");
+ return -1;
+ }
+ break;
+ }
+ case EC_CMD_HOST_EVENT_GET_B: {
+ struct ec_response_host_event_mask *resp = resp_data;
+
+ resp->mask = 0;
+ if (ec->recovery_req) {
+ resp->mask |= EC_HOST_EVENT_MASK(
+ EC_HOST_EVENT_KEYBOARD_RECOVERY);
+ }
+
+ len = sizeof(*resp);
+ break;
+ }
+ case EC_CMD_VBOOT_HASH: {
+ const struct ec_params_vboot_hash *req = req_data;
+ struct ec_response_vboot_hash *resp = resp_data;
+ struct fmap_entry *entry;
+ int ret, size;
+
+ entry = &state->ec_config.region[EC_FLASH_REGION_RW];
+
+ switch (req->cmd) {
+ case EC_VBOOT_HASH_RECALC:
+ case EC_VBOOT_HASH_GET:
+ size = SHA256_SUM_LEN;
+ len = get_image_used(ec, entry);
+ ret = hash_block("sha256",
+ ec->flash_data + entry->offset,
+ len, resp->hash_digest, &size);
+ if (ret) {
+ printf(" ** hash_block() failed\n");
+ return -1;
+ }
+ resp->status = EC_VBOOT_HASH_STATUS_DONE;
+ resp->hash_type = EC_VBOOT_HASH_TYPE_SHA256;
+ resp->digest_size = size;
+ resp->reserved0 = 0;
+ resp->offset = entry->offset;
+ resp->size = len;
+ len = sizeof(*resp);
+ break;
+ default:
+ printf(" ** EC_CMD_VBOOT_HASH: Unknown command %d\n",
+ req->cmd);
+ return -1;
+ }
+ break;
+ }
+ case EC_CMD_FLASH_PROTECT: {
+ const struct ec_params_flash_protect *req = req_data;
+ struct ec_response_flash_protect *resp = resp_data;
+ uint32_t expect = EC_FLASH_PROTECT_ALL_NOW |
+ EC_FLASH_PROTECT_ALL_AT_BOOT;
+
+ printf("mask=%#x, flags=%#x\n", req->mask, req->flags);
+ if (req->flags == expect || req->flags == 0) {
+ resp->flags = req->flags ? EC_FLASH_PROTECT_ALL_NOW :
+ 0;
+ resp->valid_flags = EC_FLASH_PROTECT_ALL_NOW;
+ resp->writable_flags = 0;
+ len = sizeof(*resp);
+ } else {
+ puts(" ** unexpected flash protect request\n");
+ return -1;
+ }
+ break;
+ }
+ case EC_CMD_FLASH_REGION_INFO: {
+ const struct ec_params_flash_region_info *req = req_data;
+ struct ec_response_flash_region_info *resp = resp_data;
+ struct fmap_entry *entry;
+
+ switch (req->region) {
+ case EC_FLASH_REGION_RO:
+ case EC_FLASH_REGION_RW:
+ case EC_FLASH_REGION_WP_RO:
+ entry = &state->ec_config.region[req->region];
+ resp->offset = entry->offset;
+ resp->size = entry->length;
+ len = sizeof(*resp);
+ printf("EC flash region %d: offset=%#x, size=%#x\n",
+ req->region, resp->offset, resp->size);
+ break;
+ default:
+ printf("** Unknown flash region %d\n", req->region);
+ return -1;
+ }
+ break;
+ }
+ case EC_CMD_FLASH_ERASE: {
+ const struct ec_params_flash_erase *req = req_data;
+
+ memset(ec->flash_data + req->offset,
+ ec->ec_config.flash_erase_value,
+ req->size);
+ len = 0;
+ break;
+ }
+ case EC_CMD_FLASH_WRITE: {
+ const struct ec_params_flash_write *req = req_data;
+
+ memcpy(ec->flash_data + req->offset, req + 1, req->size);
+ len = 0;
+ break;
+ }
+ case EC_CMD_MKBP_STATE:
+ len = cros_ec_keyscan(ec, resp_data);
+ break;
+ default:
+ printf(" ** Unknown EC command %#02x\n", req_hdr->command);
+ return -1;
+ }
+
+ return len;
+}
+
+int cros_ec_sandbox_packet(struct cros_ec_dev *dev, int out_bytes,
+ int in_bytes)
+{
+ struct ec_host_request *req_hdr = (struct ec_host_request *)dev->dout;
+ const void *req_data = req_hdr + 1;
+ struct ec_host_response *resp_hdr = (struct ec_host_response *)dev->din;
+ void *resp_data = resp_hdr + 1;
+ int len;
+
+ len = process_cmd(&s_state, req_hdr, req_data, resp_hdr, resp_data);
+ if (len < 0)
+ return len;
+
+ resp_hdr->struct_version = 3;
+ resp_hdr->result = EC_RES_SUCCESS;
+ resp_hdr->data_len = len;
+ resp_hdr->reserved = 0;
+ len += sizeof(*resp_hdr);
+ resp_hdr->checksum = 0;
+ resp_hdr->checksum = (uint8_t)
+ -cros_ec_calc_checksum((const uint8_t *)resp_hdr, len);
+
+ return in_bytes;
+}
+
+int cros_ec_sandbox_decode_fdt(struct cros_ec_dev *dev, const void *blob)
+{
+ return 0;
+}
+
+void cros_ec_check_keyboard(struct cros_ec_dev *dev)
+{
+ struct ec_state *ec = &s_state;
+ ulong start;
+
+ printf("Press keys for EC to detect on reset (ESC=recovery)...");
+ start = get_timer(0);
+ while (get_timer(start) < 1000)
+ ;
+ putc('\n');
+ if (!sandbox_sdl_key_pressed(KEY_ESC)) {
+ ec->recovery_req = true;
+ printf(" - EC requests recovery\n");
+ }
+}
+
+/**
+ * Initialize sandbox EC emulation.
+ *
+ * @param dev CROS_EC device
+ * @param blob Device tree blob
+ * @return 0 if ok, -1 on error
+ */
+int cros_ec_sandbox_init(struct cros_ec_dev *dev, const void *blob)
+{
+ struct ec_state *ec = &s_state;
+ int node;
+ int err;
+
+ state = &s_state;
+ err = cros_ec_decode_ec_flash(blob, &ec->ec_config);
+ if (err)
+ return err;
+
+ node = fdtdec_next_compatible(blob, 0, COMPAT_GOOGLE_CROS_EC_KEYB);
+ if (node < 0) {
+ debug("%s: No cros_ec keyboard found\n", __func__);
+ } else if (keyscan_read_fdt_matrix(ec, blob, node)) {
+ debug("%s: Could not read key matrix\n", __func__);
+ return -1;
+ }
+
+ /* If we loaded EC data, check that the length matches */
+ if (ec->flash_data &&
+ ec->flash_data_len != ec->ec_config.flash.length) {
+ printf("EC data length is %x, expected %x, discarding data\n",
+ ec->flash_data_len, ec->ec_config.flash.length);
+ os_free(ec->flash_data);
+ ec->flash_data = NULL;
+ }
+
+ /* Otherwise allocate the memory */
+ if (!ec->flash_data) {
+ ec->flash_data_len = ec->ec_config.flash.length;
+ ec->flash_data = os_malloc(ec->flash_data_len);
+ if (!ec->flash_data)
+ return -ENOMEM;
+ }
+
+ return 0;
+}
#include <cros_ec.h>
#include <spi.h>
+int cros_ec_spi_packet(struct cros_ec_dev *dev, int out_bytes, int in_bytes)
+{
+ int rv;
+
+ /* Do the transfer */
+ if (spi_claim_bus(dev->spi)) {
+ debug("%s: Cannot claim SPI bus\n", __func__);
+ return -1;
+ }
+
+ rv = spi_xfer(dev->spi, max(out_bytes, in_bytes) * 8,
+ dev->dout, dev->din,
+ SPI_XFER_BEGIN | SPI_XFER_END);
+
+ spi_release_bus(dev->spi);
+
+ if (rv) {
+ debug("%s: Cannot complete SPI transfer\n", __func__);
+ return -1;
+ }
+
+ return in_bytes;
+}
+
/**
* Send a command to a LPC CROS_EC device and return the reply.
*
int csum, len;
int rv;
+ if (dev->protocol_version != 2) {
+ debug("%s: Unsupported EC protcol version %d\n",
+ __func__, dev->protocol_version);
+ return -1;
+ }
+
/*
* Sanity-check input size to make sure it plus transaction overhead
* fits in the internal device buffer.
#include <common.h>
#include <malloc.h>
#include <sdhci.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+#include <asm/gpio.h>
#include <asm/arch/mmc.h>
#include <asm/arch/clk.h>
+#include <errno.h>
+#ifdef CONFIG_OF_CONTROL
+#include <asm/arch/pinmux.h>
+#endif
static char *S5P_NAME = "SAMSUNG SDHCI";
static void s5p_sdhci_set_control_reg(struct sdhci_host *host)
return add_sdhci(host, 52000000, 400000);
}
+
+#ifdef CONFIG_OF_CONTROL
+struct sdhci_host sdhci_host[SDHCI_MAX_HOSTS];
+
+static int do_sdhci_init(struct sdhci_host *host)
+{
+ int dev_id, flag;
+ int err = 0;
+
+ flag = host->bus_width == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
+ dev_id = host->index + PERIPH_ID_SDMMC0;
+
+ if (fdt_gpio_isvalid(&host->pwr_gpio)) {
+ gpio_direction_output(host->pwr_gpio.gpio, 1);
+ err = exynos_pinmux_config(dev_id, flag);
+ if (err) {
+ debug("MMC not configured\n");
+ return err;
+ }
+ }
+
+ if (fdt_gpio_isvalid(&host->cd_gpio)) {
+ gpio_direction_output(host->cd_gpio.gpio, 0xf);
+ if (gpio_get_value(host->cd_gpio.gpio))
+ return -ENODEV;
+
+ err = exynos_pinmux_config(dev_id, flag);
+ if (err) {
+ printf("external SD not configured\n");
+ return err;
+ }
+ }
+
+ host->name = S5P_NAME;
+
+ host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE |
+ SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR |
+ SDHCI_QUIRK_WAIT_SEND_CMD;
+ host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
+ host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
+
+ host->set_control_reg = &s5p_sdhci_set_control_reg;
+ host->set_clock = set_mmc_clk;
+
+ host->host_caps = MMC_MODE_HC;
+
+ return add_sdhci(host, 52000000, 400000);
+}
+
+static int sdhci_get_config(const void *blob, int node, struct sdhci_host *host)
+{
+ int bus_width, dev_id;
+ unsigned int base;
+
+ /* Get device id */
+ dev_id = pinmux_decode_periph_id(blob, node);
+ if (dev_id < PERIPH_ID_SDMMC0 && dev_id > PERIPH_ID_SDMMC3) {
+ debug("MMC: Can't get device id\n");
+ return -1;
+ }
+ host->index = dev_id - PERIPH_ID_SDMMC0;
+
+ /* Get bus width */
+ bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
+ if (bus_width <= 0) {
+ debug("MMC: Can't get bus-width\n");
+ return -1;
+ }
+ host->bus_width = bus_width;
+
+ /* Get the base address from the device node */
+ base = fdtdec_get_addr(blob, node, "reg");
+ if (!base) {
+ debug("MMC: Can't get base address\n");
+ return -1;
+ }
+ host->ioaddr = (void *)base;
+
+ fdtdec_decode_gpio(blob, node, "pwr-gpios", &host->pwr_gpio);
+ fdtdec_decode_gpio(blob, node, "cd-gpios", &host->cd_gpio);
+
+ return 0;
+}
+
+static int process_nodes(const void *blob, int node_list[], int count)
+{
+ struct sdhci_host *host;
+ int i, node;
+
+ debug("%s: count = %d\n", __func__, count);
+
+ /* build sdhci_host[] for each controller */
+ for (i = 0; i < count; i++) {
+ node = node_list[i];
+ if (node <= 0)
+ continue;
+
+ host = &sdhci_host[i];
+
+ if (sdhci_get_config(blob, node, host)) {
+ printf("%s: failed to decode dev %d\n", __func__, i);
+ return -1;
+ }
+ do_sdhci_init(host);
+ }
+ return 0;
+}
+
+int exynos_mmc_init(const void *blob)
+{
+ int count;
+ int node_list[SDHCI_MAX_HOSTS];
+
+ count = fdtdec_find_aliases_for_id(blob, "mmc",
+ COMPAT_SAMSUNG_EXYNOS_MMC, node_list,
+ SDHCI_MAX_HOSTS);
+
+ process_nodes(blob, node_list, count);
+
+ return 1;
+}
+#endif
*/
#include <common.h>
+#include <fdtdec.h>
+#include <libfdt.h>
#include <malloc.h>
#include <sdhci.h>
#include <asm/arch/sys_proto.h>
add_sdhci(host, 52000000, 52000000 >> 9);
return 0;
}
+
+#ifdef CONFIG_OF_CONTROL
+int zynq_sdhci_of_init(const void *blob)
+{
+ int offset = 0;
+ u32 ret = 0;
+ u32 reg;
+
+ debug("ZYNQ SDHCI: Initialization\n");
+
+ do {
+ offset = fdt_node_offset_by_compatible(blob, offset,
+ "arasan,sdhci-8.9a");
+ if (offset != -1) {
+ reg = fdtdec_get_addr(blob, offset, "reg");
+ if (reg != FDT_ADDR_T_NONE) {
+ ret |= zynq_sdhci_init(reg);
+ } else {
+ debug("ZYNQ SDHCI: Can't get base address\n");
+ return -1;
+ }
+ }
+ } while (offset != -1);
+
+ return ret;
+}
+#endif
#ifdef CONFIG_ATMEL_NAND_HW_PMECC
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_SYS_NAND_ONFI_DETECTION
+#endif
+
struct atmel_nand_host {
struct pmecc_regs __iomem *pmecc;
struct pmecc_errloc_regs __iomem *pmerrloc;
}
#endif
+#ifdef CONFIG_SPL_BUILD
+/* The following code is for SPL */
+static nand_info_t mtd;
+static struct nand_chip nand_chip;
+
+static int nand_command(int block, int page, uint32_t offs, u8 cmd)
+{
+ struct nand_chip *this = mtd.priv;
+ int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
+ void (*hwctrl)(struct mtd_info *mtd, int cmd,
+ unsigned int ctrl) = this->cmd_ctrl;
+
+ while (this->dev_ready(&mtd))
+ ;
+
+ if (cmd == NAND_CMD_READOOB) {
+ offs += CONFIG_SYS_NAND_PAGE_SIZE;
+ cmd = NAND_CMD_READ0;
+ }
+
+ hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+
+ if (this->options & NAND_BUSWIDTH_16)
+ offs >>= 1;
+
+ hwctrl(&mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
+ hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE);
+ hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE);
+ hwctrl(&mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE);
+#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
+ hwctrl(&mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE);
+#endif
+ hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+
+ hwctrl(&mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+ hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+
+ while (this->dev_ready(&mtd))
+ ;
+
+ return 0;
+}
+
+static int nand_is_bad_block(int block)
+{
+ struct nand_chip *this = mtd.priv;
+
+ nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
+
+ if (this->options & NAND_BUSWIDTH_16) {
+ if (readw(this->IO_ADDR_R) != 0xffff)
+ return 1;
+ } else {
+ if (readb(this->IO_ADDR_R) != 0xff)
+ return 1;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_SPL_NAND_ECC
+static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
+#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
+ CONFIG_SYS_NAND_ECCSIZE)
+#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
+
+static int nand_read_page(int block, int page, void *dst)
+{
+ struct nand_chip *this = mtd.priv;
+ u_char ecc_calc[ECCTOTAL];
+ u_char ecc_code[ECCTOTAL];
+ u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
+ int eccsize = CONFIG_SYS_NAND_ECCSIZE;
+ int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
+ int eccsteps = ECCSTEPS;
+ int i;
+ uint8_t *p = dst;
+ nand_command(block, page, 0, NAND_CMD_READ0);
+
+ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+ if (this->ecc.mode != NAND_ECC_SOFT)
+ this->ecc.hwctl(&mtd, NAND_ECC_READ);
+ this->read_buf(&mtd, p, eccsize);
+ this->ecc.calculate(&mtd, p, &ecc_calc[i]);
+ }
+ this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
+
+ for (i = 0; i < ECCTOTAL; i++)
+ ecc_code[i] = oob_data[nand_ecc_pos[i]];
+
+ eccsteps = ECCSTEPS;
+ p = dst;
+
+ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
+ this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
+
+ return 0;
+}
+#else
+static int nand_read_page(int block, int page, void *dst)
+{
+ struct nand_chip *this = mtd.priv;
+
+ nand_command(block, page, 0, NAND_CMD_READ0);
+ atmel_nand_pmecc_read_page(&mtd, this, dst, 0, page);
+
+ return 0;
+}
+#endif /* CONFIG_SPL_NAND_ECC */
+
+int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
+{
+ unsigned int block, lastblock;
+ unsigned int page;
+
+ block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
+ lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
+ page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
+
+ while (block <= lastblock) {
+ if (!nand_is_bad_block(block)) {
+ while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
+ nand_read_page(block, page, dst);
+ dst += CONFIG_SYS_NAND_PAGE_SIZE;
+ page++;
+ }
+
+ page = 0;
+ } else {
+ lastblock++;
+ }
+
+ block++;
+ }
+
+ return 0;
+}
+
+int at91_nand_wait_ready(struct mtd_info *mtd)
+{
+ struct nand_chip *this = mtd->priv;
+
+ udelay(this->chip_delay);
+
+ return 0;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+ int ret = 0;
+
+ nand->ecc.mode = NAND_ECC_SOFT;
+#ifdef CONFIG_SYS_NAND_DBW_16
+ nand->options = NAND_BUSWIDTH_16;
+ nand->read_buf = nand_read_buf16;
+#else
+ nand->read_buf = nand_read_buf;
+#endif
+ nand->cmd_ctrl = at91_nand_hwcontrol;
+#ifdef CONFIG_SYS_NAND_READY_PIN
+ nand->dev_ready = at91_nand_ready;
+#else
+ nand->dev_ready = at91_nand_wait_ready;
+#endif
+ nand->chip_delay = 20;
+
+#ifdef CONFIG_ATMEL_NAND_HWECC
+#ifdef CONFIG_ATMEL_NAND_HW_PMECC
+ ret = atmel_pmecc_nand_init_params(nand, &mtd);
+#endif
+#endif
+
+ return ret;
+}
+
+void nand_init(void)
+{
+ mtd.writesize = CONFIG_SYS_NAND_PAGE_SIZE;
+ mtd.oobsize = CONFIG_SYS_NAND_OOBSIZE;
+ mtd.priv = &nand_chip;
+ nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
+ nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
+ board_nand_init(&nand_chip);
+
+#ifdef CONFIG_SPL_NAND_ECC
+ if (nand_chip.ecc.mode == NAND_ECC_SOFT) {
+ nand_chip.ecc.calculate = nand_calculate_ecc;
+ nand_chip.ecc.correct = nand_correct_data;
+ }
+#endif
+
+ if (nand_chip.select_chip)
+ nand_chip.select_chip(&mtd, 0);
+}
+
+void nand_deselect(void)
+{
+ if (nand_chip.select_chip)
+ nand_chip.select_chip(&mtd, -1);
+}
+
+#else
+
#ifndef CONFIG_SYS_NAND_BASE_LIST
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#endif
dev_err(host->dev, "atmel_nand: Fail to initialize #%d chip",
i);
}
+#endif /* CONFIG_SPL_BUILD */
*p++ = in_be32((u32 *)(base + NDFC_DATA));
}
-#ifndef CONFIG_NAND_SPL
/*
* Don't use these speedup functions in NAND boot image, since the image
* has to fit into 4kByte.
}
-#endif /* #ifndef CONFIG_NAND_SPL */
-
void board_nand_select_device(struct nand_chip *nand, int chip)
{
/*
nand->options |= NAND_BUSWIDTH_16;
#endif
-#ifndef CONFIG_NAND_SPL
nand->write_buf = ndfc_write_buf;
nand->verify_buf = ndfc_verify_buf;
nand->read_byte = ndfc_read_byte;
chip++;
-#else
- /*
- * Setup EBC (CS0 only right now)
- */
- mtebc(EBC0_CFG, CONFIG_SYS_NDFC_EBC0_CFG);
-
- mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR);
- mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP);
-#endif
return 0;
}
#include <common.h>
#include <asm/io.h>
#include <asm/errno.h>
-#include <asm/arch/cpu.h>
-#include <asm/omap_gpmc.h>
-#include <asm/omap_elm.h>
+#include <linux/mtd/omap_gpmc.h>
+#include <linux/mtd/omap_elm.h>
+#include <asm/arch/hardware.h>
#define ELM_DEFAULT_POLY (0)
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/mem.h>
-#include <asm/arch/cpu.h>
-#include <asm/omap_gpmc.h>
+#include <linux/mtd/omap_gpmc.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/bch.h>
#include <linux/compiler.h>
#include <nand.h>
-#include <asm/omap_elm.h>
+#include <linux/mtd/omap_elm.h>
#define BADBLOCK_MARKER_LENGTH 2
#define SECTOR_BYTES 512
+#define ECCCLEAR (0x1 << 8)
+#define ECCRESULTREG1 (0x1 << 0)
+/* 4 bit padding to make byte aligned, 56 = 52 + 4 */
+#define BCH4_BIT_PAD 4
+#ifdef CONFIG_BCH
+static u8 bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
+ 0x97, 0x79, 0xe5, 0x24, 0xb5};
+#endif
static uint8_t cs;
static __maybe_unused struct nand_ecclayout omap_ecclayout;
}
#endif
-/*
- * omap_hwecc_init - Initialize the Hardware ECC for NAND flash in
- * GPMC controller
- * @mtd: MTD device structure
- *
- */
-static void __maybe_unused omap_hwecc_init(struct nand_chip *chip)
-{
- /*
- * Init ECC Control Register
- * Clear all ECC | Enable Reg1
- */
- writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
- writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, &gpmc_cfg->ecc_size_config);
-}
/*
* gen_true_ecc - This function will generate true ECC value, which
return 0;
}
-/*
- * omap_calculate_ecc - Generate non-inverted ECC bytes.
- *
- * Using noninverted ECC can be considered ugly since writing a blank
- * page ie. padding will clear the ECC bytes. This is no problem as
- * long nobody is trying to write data on the seemingly unused page.
- * Reading an erased page will produce an ECC mismatch between
- * generated and read ECC bytes that has to be dealt with separately.
- * E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC
- * is used, the result of read will be 0x0 while the ECC offsets of the
- * spare area will be 0xFF which will result in an ECC mismatch.
- * @mtd: MTD structure
- * @dat: unused
- * @ecc_code: ecc_code buffer
- */
-static int __maybe_unused omap_calculate_ecc(struct mtd_info *mtd,
- const uint8_t *dat, uint8_t *ecc_code)
-{
- u_int32_t val;
-
- /* Start Reading from HW ECC1_Result = 0x200 */
- val = readl(&gpmc_cfg->ecc1_result);
-
- ecc_code[0] = val & 0xFF;
- ecc_code[1] = (val >> 16) & 0xFF;
- ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
-
- /*
- * Stop reading anymore ECC vals and clear old results
- * enable will be called if more reads are required
- */
- writel(0x000, &gpmc_cfg->ecc_config);
-
- return 0;
-}
-
-/*
- * omap_enable_ecc - This function enables the hardware ecc functionality
- * @mtd: MTD device structure
- * @mode: Read/Write mode
- */
-static void __maybe_unused omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
-{
- struct nand_chip *chip = mtd->priv;
- uint32_t val, dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1;
-
- switch (mode) {
- case NAND_ECC_READ:
- case NAND_ECC_WRITE:
- /* Clear the ecc result registers, select ecc reg as 1 */
- writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
-
- /*
- * Size 0 = 0xFF, Size1 is 0xFF - both are 512 bytes
- * tell all regs to generate size0 sized regs
- * we just have a single ECC engine for all CS
- */
- writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL,
- &gpmc_cfg->ecc_size_config);
- val = (dev_width << 7) | (cs << 1) | (0x1);
- writel(val, &gpmc_cfg->ecc_config);
- break;
- default:
- printf("Error: Unrecognized Mode[%d]!\n", mode);
- break;
- }
-}
-
/*
* Generic BCH interface
*/
#define ECC_BCH8 1
#define ECC_BCH16 2
-/* GPMC ecc engine settings */
-#define BCH_WRAPMODE_1 1 /* BCH wrap mode 1 */
-#define BCH_WRAPMODE_6 6 /* BCH wrap mode 6 */
-
/* BCH nibbles for diff bch levels */
-#define NAND_ECC_HW_BCH ((uint8_t)(NAND_ECC_HW_OOB_FIRST) + 1)
#define ECC_BCH4_NIBBLES 13
#define ECC_BCH8_NIBBLES 26
#define ECC_BCH16_NIBBLES 52
* When some users with other BCH strength will exists this have to change!
*/
static __maybe_unused struct nand_bch_priv bch_priv = {
- .mode = NAND_ECC_HW_BCH,
.type = ECC_BCH8,
.nibbles = ECC_BCH8_NIBBLES,
.control = NULL
};
/*
- * omap_hwecc_init_bch - Initialize the BCH Hardware ECC for NAND flash in
- * GPMC controller
- * @mtd: MTD device structure
- * @mode: Read/Write mode
- */
-__maybe_unused
-static void omap_hwecc_init_bch(struct nand_chip *chip, int32_t mode)
+ * omap_reverse_list - re-orders list elements in reverse order [internal]
+ * @list: pointer to start of list
+ * @length: length of list
+*/
+void omap_reverse_list(u8 *list, unsigned int length)
{
- uint32_t val;
- uint32_t dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1;
- uint32_t unused_length = 0;
- uint32_t wr_mode = BCH_WRAPMODE_6;
- struct nand_bch_priv *bch = chip->priv;
-
- /* Clear the ecc result registers, select ecc reg as 1 */
- writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
-
- if (bch->ecc_scheme == OMAP_ECC_BCH8_CODE_HW) {
- wr_mode = BCH_WRAPMODE_1;
-
- switch (bch->nibbles) {
- case ECC_BCH4_NIBBLES:
- unused_length = 3;
- break;
- case ECC_BCH8_NIBBLES:
- unused_length = 2;
- break;
- case ECC_BCH16_NIBBLES:
- unused_length = 0;
- break;
- }
-
- /*
- * This is ecc_size_config for ELM mode. Here we are using
- * different settings for read and write access and also
- * depending on BCH strength.
- */
- switch (mode) {
- case NAND_ECC_WRITE:
- /* write access only setup eccsize1 config */
- val = ((unused_length + bch->nibbles) << 22);
- break;
-
- case NAND_ECC_READ:
- default:
- /*
- * by default eccsize0 selected for ecc1resultsize
- * eccsize0 config.
- */
- val = (bch->nibbles << 12);
- /* eccsize1 config */
- val |= (unused_length << 22);
- break;
- }
- } else {
- /*
- * This ecc_size_config setting is for BCH sw library.
- *
- * Note: we only support BCH8 currently with BCH sw library!
- * Should be really easy to adobt to BCH4, however some omap3
- * have flaws with BCH4.
- *
- * Here we are using wrapping mode 6 both for reading and
- * writing, with:
- * size0 = 0 (no additional protected byte in spare area)
- * size1 = 32 (skip 32 nibbles = 16 bytes per sector in
- * spare area)
- */
- val = (32 << 22) | (0 << 12);
+ unsigned int i, j;
+ unsigned int half_length = length / 2;
+ u8 tmp;
+ for (i = 0, j = length - 1; i < half_length; i++, j--) {
+ tmp = list[i];
+ list[i] = list[j];
+ list[j] = tmp;
}
- /* ecc size configuration */
- writel(val, &gpmc_cfg->ecc_size_config);
-
- /*
- * Configure the ecc engine in gpmc
- * We assume 512 Byte sector pages for access to NAND.
- */
- val = (1 << 16); /* enable BCH mode */
- val |= (bch->type << 12); /* setup BCH type */
- val |= (wr_mode << 8); /* setup wrapping mode */
- val |= (dev_width << 7); /* setup device width (16 or 8 bit) */
- val |= (cs << 1); /* setup chip select to work on */
- debug("set ECC_CONFIG=0x%08x\n", val);
- writel(val, &gpmc_cfg->ecc_config);
}
/*
- * omap_enable_ecc_bch - This function enables the bch h/w ecc functionality
+ * omap_enable_hwecc - configures GPMC as per ECC scheme before read/write
* @mtd: MTD device structure
* @mode: Read/Write mode
*/
__maybe_unused
-static void omap_enable_ecc_bch(struct mtd_info *mtd, int32_t mode)
-{
- struct nand_chip *chip = mtd->priv;
-
- omap_hwecc_init_bch(chip, mode);
- /* enable ecc */
- writel((readl(&gpmc_cfg->ecc_config) | 0x1), &gpmc_cfg->ecc_config);
-}
-
-/*
- * omap_ecc_disable - Disable H/W ECC calculation
- *
- * @mtd: MTD device structure
- */
-static void __maybe_unused omap_ecc_disable(struct mtd_info *mtd)
+static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
{
- writel((readl(&gpmc_cfg->ecc_config) & ~0x1), &gpmc_cfg->ecc_config);
+ struct nand_chip *nand = mtd->priv;
+ struct nand_bch_priv *bch = nand->priv;
+ unsigned int dev_width = (nand->options & NAND_BUSWIDTH_16) ? 1 : 0;
+ unsigned int ecc_algo = 0;
+ unsigned int bch_type = 0;
+ unsigned int eccsize1 = 0x00, eccsize0 = 0x00, bch_wrapmode = 0x00;
+ u32 ecc_size_config_val = 0;
+ u32 ecc_config_val = 0;
+
+ /* configure GPMC for specific ecc-scheme */
+ switch (bch->ecc_scheme) {
+ case OMAP_ECC_HAM1_CODE_SW:
+ return;
+ case OMAP_ECC_HAM1_CODE_HW:
+ ecc_algo = 0x0;
+ bch_type = 0x0;
+ bch_wrapmode = 0x00;
+ eccsize0 = 0xFF;
+ eccsize1 = 0xFF;
+ break;
+ case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
+ case OMAP_ECC_BCH8_CODE_HW:
+ ecc_algo = 0x1;
+ bch_type = 0x1;
+ if (mode == NAND_ECC_WRITE) {
+ bch_wrapmode = 0x01;
+ eccsize0 = 0; /* extra bits in nibbles per sector */
+ eccsize1 = 28; /* OOB bits in nibbles per sector */
+ } else {
+ bch_wrapmode = 0x01;
+ eccsize0 = 26; /* ECC bits in nibbles per sector */
+ eccsize1 = 2; /* non-ECC bits in nibbles per sector */
+ }
+ break;
+ default:
+ return;
+ }
+ /* Clear ecc and enable bits */
+ writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
+ /* Configure ecc size for BCH */
+ ecc_size_config_val = (eccsize1 << 22) | (eccsize0 << 12);
+ writel(ecc_size_config_val, &gpmc_cfg->ecc_size_config);
+
+ /* Configure device details for BCH engine */
+ ecc_config_val = ((ecc_algo << 16) | /* HAM1 | BCHx */
+ (bch_type << 12) | /* BCH4/BCH8/BCH16 */
+ (bch_wrapmode << 8) | /* wrap mode */
+ (dev_width << 7) | /* bus width */
+ (0x0 << 4) | /* number of sectors */
+ (cs << 1) | /* ECC CS */
+ (0x1)); /* enable ECC */
+ writel(ecc_config_val, &gpmc_cfg->ecc_config);
}
/*
- * BCH support using ELM module
- */
-#ifdef CONFIG_NAND_OMAP_ELM
-/*
- * omap_read_bch8_result - Read BCH result for BCH8 level
- *
- * @mtd: MTD device structure
- * @big_endian: When set read register 3 first
- * @ecc_code: Read syndrome from BCH result registers
+ * omap_calculate_ecc - Read ECC result
+ * @mtd: MTD structure
+ * @dat: unused
+ * @ecc_code: ecc_code buffer
+ * Using noninverted ECC can be considered ugly since writing a blank
+ * page ie. padding will clear the ECC bytes. This is no problem as
+ * long nobody is trying to write data on the seemingly unused page.
+ * Reading an erased page will produce an ECC mismatch between
+ * generated and read ECC bytes that has to be dealt with separately.
+ * E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC
+ * is used, the result of read will be 0x0 while the ECC offsets of the
+ * spare area will be 0xFF which will result in an ECC mismatch.
*/
-static void omap_read_bch8_result(struct mtd_info *mtd, uint8_t big_endian,
+static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
uint8_t *ecc_code)
{
- uint32_t *ptr;
+ struct nand_chip *chip = mtd->priv;
+ struct nand_bch_priv *bch = chip->priv;
+ uint32_t *ptr, val = 0;
int8_t i = 0, j;
- if (big_endian) {
+ switch (bch->ecc_scheme) {
+ case OMAP_ECC_HAM1_CODE_HW:
+ val = readl(&gpmc_cfg->ecc1_result);
+ ecc_code[0] = val & 0xFF;
+ ecc_code[1] = (val >> 16) & 0xFF;
+ ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
+ break;
+#ifdef CONFIG_BCH
+ case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
+#endif
+ case OMAP_ECC_BCH8_CODE_HW:
ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3];
- ecc_code[i++] = readl(ptr) & 0xFF;
+ val = readl(ptr);
+ ecc_code[i++] = (val >> 0) & 0xFF;
ptr--;
for (j = 0; j < 3; j++) {
- ecc_code[i++] = (readl(ptr) >> 24) & 0xFF;
- ecc_code[i++] = (readl(ptr) >> 16) & 0xFF;
- ecc_code[i++] = (readl(ptr) >> 8) & 0xFF;
- ecc_code[i++] = readl(ptr) & 0xFF;
+ val = readl(ptr);
+ ecc_code[i++] = (val >> 24) & 0xFF;
+ ecc_code[i++] = (val >> 16) & 0xFF;
+ ecc_code[i++] = (val >> 8) & 0xFF;
+ ecc_code[i++] = (val >> 0) & 0xFF;
ptr--;
}
- } else {
- ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[0];
- for (j = 0; j < 3; j++) {
- ecc_code[i++] = readl(ptr) & 0xFF;
- ecc_code[i++] = (readl(ptr) >> 8) & 0xFF;
- ecc_code[i++] = (readl(ptr) >> 16) & 0xFF;
- ecc_code[i++] = (readl(ptr) >> 24) & 0xFF;
- ptr++;
- }
- ecc_code[i++] = readl(ptr) & 0xFF;
- ecc_code[i++] = 0; /* 14th byte is always zero */
+ break;
+ default:
+ return -EINVAL;
}
-}
-
-/*
- * omap_rotate_ecc_bch - Rotate the syndrome bytes
- *
- * @mtd: MTD device structure
- * @calc_ecc: ECC read from ECC registers
- * @syndrome: Rotated syndrome will be retuned in this array
- *
- */
-static void omap_rotate_ecc_bch(struct mtd_info *mtd, uint8_t *calc_ecc,
- uint8_t *syndrome)
-{
- struct nand_chip *chip = mtd->priv;
- struct nand_bch_priv *bch = chip->priv;
- uint8_t n_bytes = 0;
- int8_t i, j;
-
- switch (bch->type) {
- case ECC_BCH4:
- n_bytes = 8;
+ /* ECC scheme specific syndrome customizations */
+ switch (bch->ecc_scheme) {
+ case OMAP_ECC_HAM1_CODE_HW:
break;
+#ifdef CONFIG_BCH
+ case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
- case ECC_BCH16:
- n_bytes = 28;
+ for (i = 0; i < chip->ecc.bytes; i++)
+ *(ecc_code + i) = *(ecc_code + i) ^
+ bch8_polynomial[i];
break;
-
- case ECC_BCH8:
- default:
- n_bytes = 13;
+#endif
+ case OMAP_ECC_BCH8_CODE_HW:
+ ecc_code[chip->ecc.bytes - 1] = 0x00;
break;
+ default:
+ return -EINVAL;
}
-
- for (i = 0, j = (n_bytes-1); i < n_bytes; i++, j--)
- syndrome[i] = calc_ecc[j];
-}
-
-/*
- * omap_calculate_ecc_bch - Read BCH ECC result
- *
- * @mtd: MTD structure
- * @dat: unused
- * @ecc_code: ecc_code buffer
- */
-static int omap_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat,
- uint8_t *ecc_code)
-{
- struct nand_chip *chip = mtd->priv;
- struct nand_bch_priv *bch = chip->priv;
- uint8_t big_endian = 1;
- int8_t ret = 0;
-
- if (bch->type == ECC_BCH8)
- omap_read_bch8_result(mtd, big_endian, ecc_code);
- else /* BCH4 and BCH16 currently not supported */
- ret = -1;
-
- /*
- * Stop reading anymore ECC vals and clear old results
- * enable will be called if more reads are required
- */
- omap_ecc_disable(mtd);
-
- return ret;
-}
-
-/*
- * omap_fix_errors_bch - Correct bch error in the data
- *
- * @mtd: MTD device structure
- * @data: Data read from flash
- * @error_count:Number of errors in data
- * @error_loc: Locations of errors in the data
- *
- */
-static void omap_fix_errors_bch(struct mtd_info *mtd, uint8_t *data,
- uint32_t error_count, uint32_t *error_loc)
-{
- struct nand_chip *chip = mtd->priv;
- struct nand_bch_priv *bch = chip->priv;
- uint8_t count = 0;
- uint32_t error_byte_pos;
- uint32_t error_bit_mask;
- uint32_t last_bit = (bch->nibbles * 4) - 1;
-
- /* Flip all bits as specified by the error location array. */
- /* FOR( each found error location flip the bit ) */
- for (count = 0; count < error_count; count++) {
- if (error_loc[count] > last_bit) {
- /* Remove the ECC spare bits from correction. */
- error_loc[count] -= (last_bit + 1);
- /* Offset bit in data region */
- error_byte_pos = ((512 * 8) -
- (error_loc[count]) - 1) / 8;
- /* Error Bit mask */
- error_bit_mask = 0x1 << (error_loc[count] % 8);
- /* Toggle the error bit to make the correction. */
- data[error_byte_pos] ^= error_bit_mask;
- }
- }
+ return 0;
}
+#ifdef CONFIG_NAND_OMAP_ELM
/*
* omap_correct_data_bch - Compares the ecc read from nand spare area
* with ECC registers values and corrects one bit error if it has occured
{
struct nand_chip *chip = mtd->priv;
struct nand_bch_priv *bch = chip->priv;
- uint8_t syndrome[28];
- uint32_t error_count = 0;
+ uint32_t eccbytes = chip->ecc.bytes;
+ uint32_t error_count = 0, error_max;
uint32_t error_loc[8];
- uint32_t i, ecc_flag;
+ uint32_t i, ecc_flag = 0;
+ uint8_t count, err = 0;
+ uint32_t byte_pos, bit_pos;
+
+ /* check calculated ecc */
+ for (i = 0; i < chip->ecc.bytes && !ecc_flag; i++) {
+ if (calc_ecc[i] != 0x00)
+ ecc_flag = 1;
+ }
+ if (!ecc_flag)
+ return 0;
+ /* check for whether its a erased-page */
ecc_flag = 0;
- for (i = 0; i < chip->ecc.bytes; i++)
+ for (i = 0; i < chip->ecc.bytes && !ecc_flag; i++) {
if (read_ecc[i] != 0xff)
ecc_flag = 1;
-
+ }
if (!ecc_flag)
return 0;
- elm_reset();
- elm_config((enum bch_level)(bch->type));
-
/*
* while reading ECC result we read it in big endian.
* Hence while loading to ELM we have rotate to get the right endian.
*/
- omap_rotate_ecc_bch(mtd, calc_ecc, syndrome);
-
+ switch (bch->ecc_scheme) {
+ case OMAP_ECC_BCH8_CODE_HW:
+ omap_reverse_list(calc_ecc, eccbytes - 1);
+ break;
+ default:
+ return -EINVAL;
+ }
/* use elm module to check for errors */
- if (elm_check_error(syndrome, bch->nibbles, &error_count,
- error_loc) != 0) {
- printf("ECC: uncorrectable.\n");
- return -1;
+ elm_config((enum bch_level)(bch->type));
+ if (elm_check_error(calc_ecc, bch->nibbles, &error_count, error_loc)) {
+ printf("nand: error: uncorrectable ECC errors\n");
+ return -EINVAL;
}
-
/* correct bch error */
- if (error_count > 0)
- omap_fix_errors_bch(mtd, dat, error_count, error_loc);
-
- return 0;
+ for (count = 0; count < error_count; count++) {
+ switch (bch->type) {
+ case ECC_BCH8:
+ /* 14th byte in ECC is reserved to match ROM layout */
+ error_max = SECTOR_BYTES + (eccbytes - 1);
+ break;
+ default:
+ return -EINVAL;
+ }
+ byte_pos = error_max - (error_loc[count] / 8) - 1;
+ bit_pos = error_loc[count] % 8;
+ if (byte_pos < SECTOR_BYTES) {
+ dat[byte_pos] ^= 1 << bit_pos;
+ printf("nand: bit-flip corrected @data=%d\n", byte_pos);
+ } else if (byte_pos < error_max) {
+ read_ecc[byte_pos - SECTOR_BYTES] = 1 << bit_pos;
+ printf("nand: bit-flip corrected @oob=%d\n", byte_pos -
+ SECTOR_BYTES);
+ } else {
+ err = -EBADMSG;
+ printf("nand: error: invalid bit-flip location\n");
+ }
+ }
+ return (err) ? err : error_count;
}
/**
* OMAP3 BCH8 support (with BCH library)
*/
#ifdef CONFIG_BCH
-/*
- * omap_calculate_ecc_bch_sw - Read BCH ECC result
- *
- * @mtd: MTD device structure
- * @dat: The pointer to data on which ecc is computed (unused here)
- * @ecc: The ECC output buffer
- */
-static int omap_calculate_ecc_bch_sw(struct mtd_info *mtd, const uint8_t *dat,
- uint8_t *ecc)
-{
- int ret = 0;
- size_t i;
- unsigned long nsectors, val1, val2, val3, val4;
-
- nsectors = ((readl(&gpmc_cfg->ecc_config) >> 4) & 0x7) + 1;
-
- for (i = 0; i < nsectors; i++) {
- /* Read hw-computed remainder */
- val1 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[0]);
- val2 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[1]);
- val3 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[2]);
- val4 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[3]);
-
- /*
- * Add constant polynomial to remainder, in order to get an ecc
- * sequence of 0xFFs for a buffer filled with 0xFFs.
- */
- *ecc++ = 0xef ^ (val4 & 0xFF);
- *ecc++ = 0x51 ^ ((val3 >> 24) & 0xFF);
- *ecc++ = 0x2e ^ ((val3 >> 16) & 0xFF);
- *ecc++ = 0x09 ^ ((val3 >> 8) & 0xFF);
- *ecc++ = 0xed ^ (val3 & 0xFF);
- *ecc++ = 0x93 ^ ((val2 >> 24) & 0xFF);
- *ecc++ = 0x9a ^ ((val2 >> 16) & 0xFF);
- *ecc++ = 0xc2 ^ ((val2 >> 8) & 0xFF);
- *ecc++ = 0x97 ^ (val2 & 0xFF);
- *ecc++ = 0x79 ^ ((val1 >> 24) & 0xFF);
- *ecc++ = 0xe5 ^ ((val1 >> 16) & 0xFF);
- *ecc++ = 0x24 ^ ((val1 >> 8) & 0xFF);
- *ecc++ = 0xb5 ^ (val1 & 0xFF);
- }
-
- /*
- * Stop reading anymore ECC vals and clear old results
- * enable will be called if more reads are required
- */
- omap_ecc_disable(mtd);
-
- return ret;
-}
-
/**
* omap_correct_data_bch_sw - Decode received data and correct errors
* @mtd: MTD device structure
nand->ecc.strength = 8;
nand->ecc.size = SECTOR_BYTES;
nand->ecc.bytes = 13;
- nand->ecc.hwctl = omap_enable_ecc_bch;
+ nand->ecc.hwctl = omap_enable_hwecc;
nand->ecc.correct = omap_correct_data_bch_sw;
- nand->ecc.calculate = omap_calculate_ecc_bch_sw;
+ nand->ecc.calculate = omap_calculate_ecc;
/* define ecc-layout */
ecclayout->eccbytes = nand->ecc.bytes * eccsteps;
ecclayout->eccpos[0] = BADBLOCK_MARKER_LENGTH;
ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
BADBLOCK_MARKER_LENGTH;
- omap_hwecc_init_bch(nand, NAND_ECC_READ);
bch->ecc_scheme = OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
break;
#else
nand->ecc.strength = 8;
nand->ecc.size = SECTOR_BYTES;
nand->ecc.bytes = 14;
- nand->ecc.hwctl = omap_enable_ecc_bch;
+ nand->ecc.hwctl = omap_enable_hwecc;
nand->ecc.correct = omap_correct_data_bch;
- nand->ecc.calculate = omap_calculate_ecc_bch;
+ nand->ecc.calculate = omap_calculate_ecc;
nand->ecc.read_page = omap_read_page_bch;
/* define ecc-layout */
ecclayout->eccbytes = nand->ecc.bytes * eccsteps;
*/
#include <common.h>
+#include <errno.h>
#include <malloc.h>
#include <spi.h>
#include <spi_flash.h>
}
cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
- cmd = malloc(cmdsz);
- memset(cmd, 0, cmdsz);
+ cmd = calloc(1, cmdsz);
+ if (!cmd) {
+ debug("SF: Failed to allocate cmd\n");
+ return -ENOMEM;
+ }
cmd[0] = flash->read_cmd;
while (len) {
{"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, RD_FULL, WR_QPP},
{"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, RD_FULL, WR_QPP},
{"S25FL064P", 0x010216, 0x4d00, 64 * 1024, 128, RD_FULL, WR_QPP},
+ {"S25FL128S_256K", 0x012018, 0x4d00, 256 * 1024, 64, RD_FULL, WR_QPP},
{"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, RD_FULL, WR_QPP},
- {"S25FL256S_256K", 0x010219, 0x4d00, 64 * 1024, 512, RD_FULL, WR_QPP},
+ {"S25FL256S_256K", 0x010219, 0x4d00, 256 * 1024, 128, RD_FULL, WR_QPP},
{"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL, WR_QPP},
- {"S25FL512S_256K", 0x010220, 0x4d00, 64 * 1024, 1024, RD_FULL, WR_QPP},
+ {"S25FL512S_256K", 0x010220, 0x4d00, 256 * 1024, 256, RD_FULL, WR_QPP},
{"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL, WR_QPP},
#endif
#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
return NULL;
}
- flash = malloc(sizeof(*flash));
+ flash = calloc(1, sizeof(*flash));
if (!flash) {
debug("SF: Failed to allocate spi_flash\n");
return NULL;
}
- memset(flash, '\0', sizeof(*flash));
/* Assign spi data */
flash->spi = spi;
/* Compute the flash size */
flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0;
- flash->page_size = ((ext_jedec == 0x4d00) ? 512 : 256) << flash->shift;
+ /*
+ * The Spansion S25FL032P and S25FL064P have 256b pages, yet use the
+ * 0x4d00 Extended JEDEC code. The rest of the Spansion flashes with
+ * the 0x4d00 Extended JEDEC code have 512b pages. All of the others
+ * have 256b pages.
+ */
+ if (ext_jedec == 0x4d00) {
+ if ((jedec == 0x0215) || (jedec == 0x216))
+ flash->page_size = 256;
+ else
+ flash->page_size = 512;
+ } else {
+ flash->page_size = 256;
+ }
+ flash->page_size <<= flash->shift;
flash->sector_size = params->sector_size << flash->shift;
flash->size = flash->sector_size * params->nr_sectors << flash->shift;
#ifdef CONFIG_SF_DUAL_FLASH
{
struct cpsw_priv *priv = (struct cpsw_priv *)dev->priv;
struct phy_device *phydev;
- u32 supported = (SUPPORTED_10baseT_Half |
- SUPPORTED_10baseT_Full |
- SUPPORTED_100baseT_Half |
- SUPPORTED_100baseT_Full |
- SUPPORTED_1000baseT_Full);
+ u32 supported = PHY_GBIT_FEATURES;
phydev = phy_connect(priv->bus,
slave->data->phy_addr,
static struct phy_driver AR8021_driver = {
.name = "AR8021",
.uid = 0x4dd040,
- .mask = 0x4fffff,
+ .mask = 0x4ffff0,
.features = PHY_GBIT_FEATURES,
.config = ar8021_config,
.startup = genphy_startup,
#include <asm/io.h>
#include <fdtdec.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#undef DEBUG
#define ENET_ADDR_LENGTH 6
}
#ifdef CONFIG_OF_CONTROL
-int xilinx_emaclite_init(bd_t *bis)
+int xilinx_emaclite_of_init(const void *blob)
{
int offset = 0;
u32 ret = 0;
u32 reg;
do {
- offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset,
+ offset = fdt_node_offset_by_compatible(blob, offset,
"xlnx,xps-ethernetlite-1.00.a");
if (offset != -1) {
- reg = fdtdec_get_addr(gd->fdt_blob, offset, "reg");
+ reg = fdtdec_get_addr(blob, offset, "reg");
if (reg != FDT_ADDR_T_NONE) {
- u32 rxpp = fdtdec_get_int(gd->fdt_blob, offset,
+ u32 rxpp = fdtdec_get_int(blob, offset,
"xlnx,rx-ping-pong", 0);
- u32 txpp = fdtdec_get_int(gd->fdt_blob, offset,
+ u32 txpp = fdtdec_get_int(blob, offset,
"xlnx,tx-ping-pong", 0);
- ret |= xilinx_emaclite_initialize(bis, reg,
+ ret |= xilinx_emaclite_initialize(NULL, reg,
txpp, rxpp);
+ } else {
+ debug("EMACLITE: Can't get base address\n");
+ return -1;
}
}
} while (offset != -1);
#include <common.h>
#include <net.h>
#include <config.h>
+#include <fdtdec.h>
+#include <libfdt.h>
#include <malloc.h>
#include <asm/io.h>
#include <phy.h>
return 1;
}
+
+#ifdef CONFIG_OF_CONTROL
+int zynq_gem_of_init(const void *blob)
+{
+ int offset = 0;
+ u32 ret = 0;
+ u32 reg, phy_reg;
+
+ debug("ZYNQ GEM: Initialization\n");
+
+ do {
+ offset = fdt_node_offset_by_compatible(blob, offset,
+ "xlnx,ps7-ethernet-1.00.a");
+ if (offset != -1) {
+ reg = fdtdec_get_addr(blob, offset, "reg");
+ if (reg != FDT_ADDR_T_NONE) {
+ offset = fdtdec_lookup_phandle(blob, offset,
+ "phy-handle");
+ if (offset != -1)
+ phy_reg = fdtdec_get_addr(blob, offset,
+ "reg");
+ else
+ phy_reg = 0;
+
+ debug("ZYNQ GEM: addr %x, phyaddr %x\n",
+ reg, phy_reg);
+
+ ret |= zynq_gem_initialize(NULL, reg,
+ phy_reg, 0);
+
+ } else {
+ debug("ZYNQ GEM: Can't get base address\n");
+ return -1;
+ }
+ }
+ } while (offset != -1);
+
+ return ret;
+}
+#endif
#include <asm/arch/crm_regs.h>
#include <asm/gpio.h>
#include <asm/io.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#include <errno.h>
#define PCI_ACCESS_READ 0
*/
#include <common.h>
+#include <lcd.h>
#include <os.h>
#include <serial.h>
#include <linux/compiler.h>
+#include <asm/state.h>
/*
*
static int sandbox_serial_init(void)
{
- os_tty_raw(0);
+ struct sandbox_state *state = state_get_current();
+
+ if (state->term_raw != STATE_TERM_COOKED)
+ os_tty_raw(0, state->term_raw == STATE_TERM_RAW_WITH_SIGS);
return 0;
}
ssize_t count;
os_usleep(100);
+#ifdef CONFIG_LCD
+ lcd_sync();
+#endif
if (next_index == serial_buf_read)
return 1; /* buffer full */
*/
#include <common.h>
+#include <fdtdec.h>
#include <watchdog.h>
#include <asm/io.h>
#include <linux/compiler.h>
#include <asm/arch/clk.h>
#include <asm/arch/hardware.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#define ZYNQ_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
#define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
struct serial_device uart_zynq_serial1_device =
INIT_PSSERIAL_STRUCTURE(1, "ttyPS1");
+#ifdef CONFIG_OF_CONTROL
+__weak struct serial_device *default_serial_console(void)
+{
+ const void *blob = gd->fdt_blob;
+ int node;
+ unsigned int base_addr;
+
+ node = fdt_path_offset(blob, "serial0");
+ if (node < 0)
+ return NULL;
+
+ base_addr = fdtdec_get_addr(blob, node, "reg");
+ if (base_addr == FDT_ADDR_T_NONE)
+ return NULL;
+
+ if (base_addr == ZYNQ_SERIAL_BASEADDR0)
+ return &uart_zynq_serial0_device;
+
+ if (base_addr == ZYNQ_SERIAL_BASEADDR1)
+ return &uart_zynq_serial1_device;
+
+ return NULL;
+}
+#else
__weak struct serial_device *default_serial_console(void)
{
#if defined(CONFIG_ZYNQ_SERIAL_UART0)
#endif
return NULL;
}
+#endif
void zynq_serial_initalize(void)
{
#
obj-$(CONFIG_SOUND) += sound.o
-obj-$(CONFIG_I2S) += samsung-i2s.o
+obj-$(CONFIG_I2S) += sound-i2s.o
+obj-$(CONFIG_I2S_SAMSUNG) += samsung-i2s.o
+obj-$(CONFIG_SOUND_SANDBOX) += sandbox.o
obj-$(CONFIG_SOUND_WM8994) += wm8994.o
obj-$(CONFIG_SOUND_MAX98095) += max98095.o
--- /dev/null
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sound.h>
+#include <asm/sdl.h>
+
+int sound_play(uint32_t msec, uint32_t frequency)
+{
+ sandbox_sdl_sound_start(frequency);
+ mdelay(msec);
+ sandbox_sdl_sound_stop();
+
+ return 0;
+}
+
+int sound_init(const void *blob)
+{
+ return sandbox_sdl_sound_init();
+}
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * R. Chandrasekar <rcsekar@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <malloc.h>
+#include <common.h>
+#include <asm/io.h>
+#include <libfdt.h>
+#include <fdtdec.h>
+#include <i2c.h>
+#include <i2s.h>
+#include <sound.h>
+#include <asm/arch/sound.h>
+#include "wm8994.h"
+#include "max98095.h"
+
+/* defines */
+#define SOUND_400_HZ 400
+#define SOUND_BITS_IN_BYTE 8
+
+static struct i2stx_info g_i2stx_pri;
+
+/*
+ * get_sound_i2s_values gets values for i2s parameters
+ *
+ * @param i2stx_info i2s transmitter transfer param structure
+ * @param blob FDT blob if enabled else NULL
+ */
+static int get_sound_i2s_values(struct i2stx_info *i2s, const void *blob)
+{
+ int node;
+ int error = 0;
+ int base;
+
+ node = fdt_path_offset(blob, "i2s");
+ if (node <= 0) {
+ debug("EXYNOS_SOUND: No node for sound in device tree\n");
+ return -1;
+ }
+
+ /*
+ * Get the pre-defined sound specific values from FDT.
+ * All of these are expected to be correct otherwise
+ * wrong register values in i2s setup parameters
+ * may result in no sound play.
+ */
+ base = fdtdec_get_addr(blob, node, "reg");
+ if (base == FDT_ADDR_T_NONE) {
+ debug("%s: Missing i2s base\n", __func__);
+ return -1;
+ }
+ i2s->base_address = base;
+
+ i2s->audio_pll_clk = fdtdec_get_int(blob,
+ node, "samsung,i2s-epll-clock-frequency", -1);
+ error |= i2s->audio_pll_clk;
+ debug("audio_pll_clk = %d\n", i2s->audio_pll_clk);
+ i2s->samplingrate = fdtdec_get_int(blob,
+ node, "samsung,i2s-sampling-rate", -1);
+ error |= i2s->samplingrate;
+ debug("samplingrate = %d\n", i2s->samplingrate);
+ i2s->bitspersample = fdtdec_get_int(blob,
+ node, "samsung,i2s-bits-per-sample", -1);
+ error |= i2s->bitspersample;
+ debug("bitspersample = %d\n", i2s->bitspersample);
+ i2s->channels = fdtdec_get_int(blob,
+ node, "samsung,i2s-channels", -1);
+ error |= i2s->channels;
+ debug("channels = %d\n", i2s->channels);
+ i2s->rfs = fdtdec_get_int(blob,
+ node, "samsung,i2s-lr-clk-framesize", -1);
+ error |= i2s->rfs;
+ debug("rfs = %d\n", i2s->rfs);
+ i2s->bfs = fdtdec_get_int(blob,
+ node, "samsung,i2s-bit-clk-framesize", -1);
+ error |= i2s->bfs;
+ debug("bfs = %d\n", i2s->bfs);
+
+ i2s->id = fdtdec_get_int(blob, node, "samsung,i2s-id", -1);
+ error |= i2s->id;
+ debug("id = %d\n", i2s->id);
+
+ if (error == -1) {
+ debug("fail to get sound i2s node properties\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+/*
+ * Init codec
+ *
+ * @param blob FDT blob
+ * @param pi2s_tx i2s parameters required by codec
+ * @return int value, 0 for success
+ */
+static int codec_init(const void *blob, struct i2stx_info *pi2s_tx)
+{
+ int ret;
+ const char *codectype;
+ int node;
+
+ /* Get the node from FDT for sound */
+ node = fdt_path_offset(blob, "i2s");
+ if (node <= 0) {
+ debug("EXYNOS_SOUND: No node for sound in device tree\n");
+ debug("node = %d\n", node);
+ return -1;
+ }
+
+ /*
+ * Get the pre-defined sound codec specific values from FDT.
+ * All of these are expected to be correct otherwise sound
+ * can not be played
+ */
+ codectype = fdt_getprop(blob, node, "samsung,codec-type", NULL);
+ debug("device = %s\n", codectype);
+ if (!strcmp(codectype, "wm8994")) {
+ /* Check the codec type and initialise the same */
+ ret = wm8994_init(blob, pi2s_tx->id + 1,
+ pi2s_tx->samplingrate,
+ (pi2s_tx->samplingrate * (pi2s_tx->rfs)),
+ pi2s_tx->bitspersample, pi2s_tx->channels);
+ } else if (!strcmp(codectype, "max98095")) {
+ ret = max98095_init(blob, pi2s_tx->id + 1,
+ pi2s_tx->samplingrate,
+ (pi2s_tx->samplingrate * (pi2s_tx->rfs)),
+ pi2s_tx->bitspersample);
+ } else {
+ debug("%s: Unknown codec type %s\n", __func__, codectype);
+ return -1;
+ }
+
+ if (ret) {
+ debug("%s: Codec init failed\n", __func__);
+ return -1;
+ }
+
+ return 0;
+}
+
+int sound_init(const void *blob)
+{
+ int ret;
+ struct i2stx_info *pi2s_tx = &g_i2stx_pri;
+
+ /* Get the I2S Values */
+ if (get_sound_i2s_values(pi2s_tx, blob) < 0) {
+ debug(" FDT I2S values failed\n");
+ return -1;
+ }
+
+ if (codec_init(blob, pi2s_tx) < 0) {
+ debug(" Codec init failed\n");
+ return -1;
+ }
+
+ ret = i2s_tx_init(pi2s_tx);
+ if (ret) {
+ debug("%s: Failed to init i2c transmit: ret=%d\n", __func__,
+ ret);
+ return ret;
+ }
+
+
+ return ret;
+}
+
+int sound_play(uint32_t msec, uint32_t frequency)
+{
+ unsigned int *data;
+ unsigned long data_size;
+ unsigned int ret = 0;
+
+ /*Buffer length computation */
+ data_size = g_i2stx_pri.samplingrate * g_i2stx_pri.channels;
+ data_size *= (g_i2stx_pri.bitspersample / SOUND_BITS_IN_BYTE);
+ data = malloc(data_size);
+
+ if (data == NULL) {
+ debug("%s: malloc failed\n", __func__);
+ return -1;
+ }
+
+ sound_create_square_wave((unsigned short *)data,
+ data_size / sizeof(unsigned short),
+ frequency);
+
+ while (msec >= 1000) {
+ ret = i2s_transfer_tx_data(&g_i2stx_pri, data,
+ (data_size / sizeof(int)));
+ msec -= 1000;
+ }
+ if (msec) {
+ unsigned long size =
+ (data_size * msec) / (sizeof(int) * 1000);
+
+ ret = i2s_transfer_tx_data(&g_i2stx_pri, data, size);
+ }
+
+ free(data);
+
+ return ret;
+}
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <malloc.h>
#include <common.h>
-#include <asm/io.h>
-#include <libfdt.h>
-#include <fdtdec.h>
-#include <i2c.h>
-#include <i2s.h>
#include <sound.h>
-#include <asm/arch/sound.h>
-#include "wm8994.h"
-#include "max98095.h"
-/* defines */
-#define SOUND_400_HZ 400
-#define SOUND_BITS_IN_BYTE 8
-
-static struct i2stx_info g_i2stx_pri;
-
-/*
- * get_sound_i2s_values gets values for i2s parameters
- *
- * @param i2stx_info i2s transmitter transfer param structure
- * @param blob FDT blob if enabled else NULL
- */
-static int get_sound_i2s_values(struct i2stx_info *i2s, const void *blob)
-{
-#ifdef CONFIG_OF_CONTROL
- int node;
- int error = 0;
- int base;
-
- node = fdt_path_offset(blob, "i2s");
- if (node <= 0) {
- debug("EXYNOS_SOUND: No node for sound in device tree\n");
- return -1;
- }
-
- /*
- * Get the pre-defined sound specific values from FDT.
- * All of these are expected to be correct otherwise
- * wrong register values in i2s setup parameters
- * may result in no sound play.
- */
- base = fdtdec_get_addr(blob, node, "reg");
- if (base == FDT_ADDR_T_NONE) {
- debug("%s: Missing i2s base\n", __func__);
- return -1;
- }
- i2s->base_address = base;
-
- i2s->audio_pll_clk = fdtdec_get_int(blob,
- node, "samsung,i2s-epll-clock-frequency", -1);
- error |= i2s->audio_pll_clk;
- debug("audio_pll_clk = %d\n", i2s->audio_pll_clk);
- i2s->samplingrate = fdtdec_get_int(blob,
- node, "samsung,i2s-sampling-rate", -1);
- error |= i2s->samplingrate;
- debug("samplingrate = %d\n", i2s->samplingrate);
- i2s->bitspersample = fdtdec_get_int(blob,
- node, "samsung,i2s-bits-per-sample", -1);
- error |= i2s->bitspersample;
- debug("bitspersample = %d\n", i2s->bitspersample);
- i2s->channels = fdtdec_get_int(blob,
- node, "samsung,i2s-channels", -1);
- error |= i2s->channels;
- debug("channels = %d\n", i2s->channels);
- i2s->rfs = fdtdec_get_int(blob,
- node, "samsung,i2s-lr-clk-framesize", -1);
- error |= i2s->rfs;
- debug("rfs = %d\n", i2s->rfs);
- i2s->bfs = fdtdec_get_int(blob,
- node, "samsung,i2s-bit-clk-framesize", -1);
- error |= i2s->bfs;
- debug("bfs = %d\n", i2s->bfs);
-
- i2s->id = fdtdec_get_int(blob, node, "samsung,i2s-id", -1);
- error |= i2s->id;
- debug("id = %d\n", i2s->id);
-
- if (error == -1) {
- debug("fail to get sound i2s node properties\n");
- return -1;
- }
-#else
- i2s->base_address = samsung_get_base_i2s();
- i2s->audio_pll_clk = I2S_PLL_CLK;
- i2s->samplingrate = I2S_SAMPLING_RATE;
- i2s->bitspersample = I2S_BITS_PER_SAMPLE;
- i2s->channels = I2S_CHANNELS;
- i2s->rfs = I2S_RFS;
- i2s->bfs = I2S_BFS;
- i2s->id = 0;
-#endif
- return 0;
-}
-
-/*
- * Init codec
- *
- * @param blob FDT blob
- * @param pi2s_tx i2s parameters required by codec
- * @return int value, 0 for success
- */
-static int codec_init(const void *blob, struct i2stx_info *pi2s_tx)
-{
- int ret;
- const char *codectype;
-#ifdef CONFIG_OF_CONTROL
- int node;
-
- /* Get the node from FDT for sound */
- node = fdt_path_offset(blob, "i2s");
- if (node <= 0) {
- debug("EXYNOS_SOUND: No node for sound in device tree\n");
- debug("node = %d\n", node);
- return -1;
- }
-
- /*
- * Get the pre-defined sound codec specific values from FDT.
- * All of these are expected to be correct otherwise sound
- * can not be played
- */
- codectype = fdt_getprop(blob, node, "samsung,codec-type", NULL);
- debug("device = %s\n", codectype);
-#else
- codectype = AUDIO_CODEC;
-#endif
- if (!strcmp(codectype, "wm8994")) {
- /* Check the codec type and initialise the same */
- ret = wm8994_init(blob, pi2s_tx->id + 1,
- pi2s_tx->samplingrate,
- (pi2s_tx->samplingrate * (pi2s_tx->rfs)),
- pi2s_tx->bitspersample, pi2s_tx->channels);
- } else if (!strcmp(codectype, "max98095")) {
- ret = max98095_init(blob, pi2s_tx->id + 1,
- pi2s_tx->samplingrate,
- (pi2s_tx->samplingrate * (pi2s_tx->rfs)),
- pi2s_tx->bitspersample);
- } else {
- debug("%s: Unknown codec type %s\n", __func__, codectype);
- return -1;
- }
-
- if (ret) {
- debug("%s: Codec init failed\n", __func__);
- return -1;
- }
-
- return 0;
-}
-
-int sound_init(const void *blob)
-{
- int ret;
- struct i2stx_info *pi2s_tx = &g_i2stx_pri;
-
- /* Get the I2S Values */
- if (get_sound_i2s_values(pi2s_tx, blob) < 0) {
- debug(" FDT I2S values failed\n");
- return -1;
- }
-
- if (codec_init(blob, pi2s_tx) < 0) {
- debug(" Codec init failed\n");
- return -1;
- }
-
- ret = i2s_tx_init(pi2s_tx);
- if (ret) {
- debug("%s: Failed to init i2c transmit: ret=%d\n", __func__,
- ret);
- return ret;
- }
-
-
- return ret;
-}
-
-/*
- * Generates square wave sound data for 1 second
- *
- * @param data data buffer pointer
- * @param size size of the buffer
- * @param freq frequency of the wave
- */
-static void sound_prepare_buffer(unsigned short *data, int size, uint32_t freq)
+void sound_create_square_wave(unsigned short *data, int size, uint32_t freq)
{
const int sample = 48000;
const unsigned short amplitude = 16000; /* between 1 and 32767 */
}
}
}
-
-int sound_play(uint32_t msec, uint32_t frequency)
-{
- unsigned int *data;
- unsigned long data_size;
- unsigned int ret = 0;
-
- /*Buffer length computation */
- data_size = g_i2stx_pri.samplingrate * g_i2stx_pri.channels;
- data_size *= (g_i2stx_pri.bitspersample / SOUND_BITS_IN_BYTE);
- data = malloc(data_size);
-
- if (data == NULL) {
- debug("%s: malloc failed\n", __func__);
- return -1;
- }
-
- sound_prepare_buffer((unsigned short *)data,
- data_size / sizeof(unsigned short), frequency);
-
- while (msec >= 1000) {
- ret = i2s_transfer_tx_data(&g_i2stx_pri, data,
- (data_size / sizeof(int)));
- msec -= 1000;
- }
- if (msec) {
- unsigned long size =
- (data_size * msec) / (sizeof(int) * 1000);
-
- ret = i2s_transfer_tx_data(&g_i2stx_pri, data, size);
- }
-
- free(data);
-
- return ret;
-}
{
unsigned long mode;
+ mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR);
+ mode &= ~AT91_SPI_PCS;
+
switch (cs) {
- case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */
- mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR);
- mode &= 0xFFF0FFFF;
- writel(mode | ((AT91_SPI_PCS0_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
- ATMEL_BASE_SPI0 + AT91_SPI_MR);
+ case 0:
+ mode |= AT91_SPI_PCS0_DATAFLASH_CARD << 16;
break;
- case 1: /* Configure SPI CS1 for Serial DataFlash AT45DBxx */
- mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR);
- mode &= 0xFFF0FFFF;
- writel(mode | ((AT91_SPI_PCS1_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
- ATMEL_BASE_SPI0 + AT91_SPI_MR);
+ case 1:
+ mode |= AT91_SPI_PCS1_DATAFLASH_CARD << 16;
break;
- case 2: /* Configure SPI CS2 for Serial DataFlash AT45DBxx */
- mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR);
- mode &= 0xFFF0FFFF;
- writel(mode | ((AT91_SPI_PCS2_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
- ATMEL_BASE_SPI0 + AT91_SPI_MR);
+ case 2:
+ mode |= AT91_SPI_PCS2_DATAFLASH_CARD << 16;
break;
case 3:
- mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR);
- mode &= 0xFFF0FFFF;
- writel(mode | ((AT91_SPI_PCS3_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
- ATMEL_BASE_SPI0 + AT91_SPI_MR);
+ mode |= AT91_SPI_PCS3_DATAFLASH_CARD << 16;
break;
}
+ writel(mode, ATMEL_BASE_SPI0 + AT91_SPI_MR);
+
/* SPI_Enable */
writel(AT91_SPI_SPIEN, ATMEL_BASE_SPI0 + AT91_SPI_CR);
}
}
/* wait to finish of transfer */
- while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) &
- OMAP3_MCSPI_CHSTAT_EOT));
+ while ((readl(&ds->regs->channel[ds->slave.cs].chstat) &
+ (OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS)) !=
+ (OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS));
/* Disable the channel otherwise the next immediate RX will get affected */
omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS);
return ret;
}
+
+/**
+ * Set up a new SPI slave for an fdt node
+ *
+ * @param blob Device tree blob
+ * @param node SPI peripheral node to use
+ * @return 0 if ok, -1 on error
+ */
+struct spi_slave *spi_setup_slave_fdt(const void *blob, int slave_node,
+ int spi_node)
+{
+ return NULL;
+}
ifdef CONFIG_USB_ETHER_ASIX
obj-y += asix.o
endif
+obj-$(CONFIG_USB_ETHER_MCS7830) += mcs7830.o
obj-$(CONFIG_USB_ETHER_SMSC95XX) += smsc95xx.o
memcpy(msg, &packet_len, sizeof(packet_len));
memcpy(msg + sizeof(packet_len), (void *)packet, length);
- if (length & 1)
- length++;
err = usb_bulk_msg(dev->pusb_dev,
usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
--- /dev/null
+/*
+ * Copyright (c) 2013 Gerhard Sittig <gsi@denx.de>
+ * based on the U-Boot Asix driver as well as information
+ * from the Linux Moschip driver
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * MOSCHIP MCS7830 based (7730/7830/7832) USB 2.0 Ethernet Devices
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <linux/mii.h>
+#include <malloc.h>
+#include <usb.h>
+
+#include "usb_ether.h"
+
+#define MCS7830_BASE_NAME "mcs"
+
+#define USBCALL_TIMEOUT 1000
+#define LINKSTATUS_TIMEOUT 5000 /* link status, connect timeout */
+#define LINKSTATUS_TIMEOUT_RES 50 /* link status, resolution in msec */
+
+#define MCS7830_RX_URB_SIZE 2048
+
+/* command opcodes */
+#define MCS7830_WR_BREQ 0x0d
+#define MCS7830_RD_BREQ 0x0e
+
+/* register layout, numerical offset specs for USB API calls */
+struct mcs7830_regs {
+ uint8_t multicast_hashes[8];
+ uint8_t packet_gap[2];
+ uint8_t phy_data[2];
+ uint8_t phy_command[2];
+ uint8_t configuration;
+ uint8_t ether_address[6];
+ uint8_t frame_drop_count;
+ uint8_t pause_threshold;
+};
+#define REG_MULTICAST_HASH offsetof(struct mcs7830_regs, multicast_hashes)
+#define REG_PHY_DATA offsetof(struct mcs7830_regs, phy_data)
+#define REG_PHY_CMD offsetof(struct mcs7830_regs, phy_command)
+#define REG_CONFIG offsetof(struct mcs7830_regs, configuration)
+#define REG_ETHER_ADDR offsetof(struct mcs7830_regs, ether_address)
+#define REG_FRAME_DROP_COUNTER offsetof(struct mcs7830_regs, frame_drop_count)
+#define REG_PAUSE_THRESHOLD offsetof(struct mcs7830_regs, pause_threshold)
+
+/* bit masks and default values for the above registers */
+#define PHY_CMD1_READ 0x40
+#define PHY_CMD1_WRITE 0x20
+#define PHY_CMD1_PHYADDR 0x01
+
+#define PHY_CMD2_PEND 0x80
+#define PHY_CMD2_READY 0x40
+
+#define CONF_CFG 0x80
+#define CONF_SPEED100 0x40
+#define CONF_FDX_ENABLE 0x20
+#define CONF_RXENABLE 0x10
+#define CONF_TXENABLE 0x08
+#define CONF_SLEEPMODE 0x04
+#define CONF_ALLMULTICAST 0x02
+#define CONF_PROMISCUOUS 0x01
+
+#define PAUSE_THRESHOLD_DEFAULT 0
+
+/* bit masks for the status byte which follows received ethernet frames */
+#define STAT_RX_FRAME_CORRECT 0x20
+#define STAT_RX_LARGE_FRAME 0x10
+#define STAT_RX_CRC_ERROR 0x08
+#define STAT_RX_ALIGNMENT_ERROR 0x04
+#define STAT_RX_LENGTH_ERROR 0x02
+#define STAT_RX_SHORT_FRAME 0x01
+
+/*
+ * struct mcs7830_private - private driver data for an individual adapter
+ * @config: shadow for the network adapter's configuration register
+ * @mchash: shadow for the network adapter's multicast hash registers
+ */
+struct mcs7830_private {
+ uint8_t config;
+ uint8_t mchash[8];
+};
+
+/*
+ * mcs7830_read_reg() - read a register of the network adapter
+ * @dev: network device to read from
+ * @idx: index of the register to start reading from
+ * @size: number of bytes to read
+ * @data: buffer to read into
+ * Return: zero upon success, negative upon error
+ */
+static int mcs7830_read_reg(struct ueth_data *dev, uint8_t idx,
+ uint16_t size, void *data)
+{
+ int len;
+ ALLOC_CACHE_ALIGN_BUFFER(uint8_t, buf, size);
+
+ debug("%s() idx=0x%04X sz=%d\n", __func__, idx, size);
+
+ len = usb_control_msg(dev->pusb_dev,
+ usb_rcvctrlpipe(dev->pusb_dev, 0),
+ MCS7830_RD_BREQ,
+ USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
+ 0, idx, buf, size,
+ USBCALL_TIMEOUT);
+ if (len != size) {
+ debug("%s() len=%d != sz=%d\n", __func__, len, size);
+ return -EIO;
+ }
+ memcpy(data, buf, size);
+ return 0;
+}
+
+/*
+ * mcs7830_write_reg() - write a register of the network adapter
+ * @dev: network device to write to
+ * @idx: index of the register to start writing to
+ * @size: number of bytes to write
+ * @data: buffer holding the data to write
+ * Return: zero upon success, negative upon error
+ */
+static int mcs7830_write_reg(struct ueth_data *dev, uint8_t idx,
+ uint16_t size, void *data)
+{
+ int len;
+ ALLOC_CACHE_ALIGN_BUFFER(uint8_t, buf, size);
+
+ debug("%s() idx=0x%04X sz=%d\n", __func__, idx, size);
+
+ memcpy(buf, data, size);
+ len = usb_control_msg(dev->pusb_dev,
+ usb_sndctrlpipe(dev->pusb_dev, 0),
+ MCS7830_WR_BREQ,
+ USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
+ 0, idx, buf, size,
+ USBCALL_TIMEOUT);
+ if (len != size) {
+ debug("%s() len=%d != sz=%d\n", __func__, len, size);
+ return -EIO;
+ }
+ return 0;
+}
+
+/*
+ * mcs7830_phy_emit_wait() - emit PHY read/write access, wait for its execution
+ * @dev: network device to talk to
+ * @rwflag: PHY_CMD1_READ or PHY_CMD1_WRITE opcode
+ * @index: number of the PHY register to read or write
+ * Return: zero upon success, negative upon error
+ */
+static int mcs7830_phy_emit_wait(struct ueth_data *dev,
+ uint8_t rwflag, uint8_t index)
+{
+ int rc;
+ int retry;
+ uint8_t cmd[2];
+
+ /* send the PHY read/write request */
+ cmd[0] = rwflag | PHY_CMD1_PHYADDR;
+ cmd[1] = PHY_CMD2_PEND | (index & 0x1f);
+ rc = mcs7830_write_reg(dev, REG_PHY_CMD, sizeof(cmd), cmd);
+ if (rc < 0)
+ return rc;
+
+ /* wait for the response to become available (usually < 1ms) */
+ retry = 10;
+ do {
+ rc = mcs7830_read_reg(dev, REG_PHY_CMD, sizeof(cmd), cmd);
+ if (rc < 0)
+ return rc;
+ if (cmd[1] & PHY_CMD2_READY)
+ return 0;
+ if (!retry--)
+ return -ETIMEDOUT;
+ mdelay(1);
+ } while (1);
+ /* UNREACH */
+}
+
+/*
+ * mcs7830_read_phy() - read a PHY register of the network adapter
+ * @dev: network device to read from
+ * @index: index of the PHY register to read from
+ * Return: non-negative 16bit register content, negative upon error
+ */
+static int mcs7830_read_phy(struct ueth_data *dev, uint8_t index)
+{
+ int rc;
+ uint16_t val;
+
+ /* issue the PHY read request and wait for its execution */
+ rc = mcs7830_phy_emit_wait(dev, PHY_CMD1_READ, index);
+ if (rc < 0)
+ return rc;
+
+ /* fetch the PHY data which was read */
+ rc = mcs7830_read_reg(dev, REG_PHY_DATA, sizeof(val), &val);
+ if (rc < 0)
+ return rc;
+ rc = le16_to_cpu(val);
+ debug("%s(%s, %d) => 0x%04X\n", __func__, dev->eth_dev.name, index, rc);
+ return rc;
+}
+
+/*
+ * mcs7830_write_phy() - write a PHY register of the network adapter
+ * @dev: network device to write to
+ * @index: index of the PHY register to write to
+ * @val: value to write to the PHY register
+ * Return: zero upon success, negative upon error
+ */
+static int mcs7830_write_phy(struct ueth_data *dev, uint8_t index, uint16_t val)
+{
+ int rc;
+
+ debug("%s(%s, %d, 0x%04X)\n", __func__, dev->eth_dev.name, index, val);
+
+ /* setup the PHY data which is to get written */
+ val = cpu_to_le16(val);
+ rc = mcs7830_write_reg(dev, REG_PHY_DATA, sizeof(val), &val);
+ if (rc < 0)
+ return rc;
+
+ /* issue the PHY write request and wait for its execution */
+ rc = mcs7830_phy_emit_wait(dev, PHY_CMD1_WRITE, index);
+ if (rc < 0)
+ return rc;
+
+ return 0;
+}
+
+/*
+ * mcs7830_write_config() - write to the network adapter's config register
+ * @eth: network device to write to
+ * Return: zero upon success, negative upon error
+ *
+ * the data which gets written is taken from the shadow config register
+ * within the device driver's private data
+ */
+static int mcs7830_write_config(struct ueth_data *dev)
+{
+ struct mcs7830_private *priv;
+ int rc;
+
+ debug("%s()\n", __func__);
+ priv = dev->dev_priv;
+
+ rc = mcs7830_write_reg(dev, REG_CONFIG,
+ sizeof(priv->config), &priv->config);
+ if (rc < 0) {
+ debug("writing config to adapter failed\n");
+ return rc;
+ }
+
+ return 0;
+}
+
+/*
+ * mcs7830_write_mchash() - write the network adapter's multicast filter
+ * @eth: network device to write to
+ * Return: zero upon success, negative upon error
+ *
+ * the data which gets written is taken from the shadow multicast hashes
+ * within the device driver's private data
+ */
+static int mcs7830_write_mchash(struct ueth_data *dev)
+{
+ struct mcs7830_private *priv;
+ int rc;
+
+ debug("%s()\n", __func__);
+ priv = dev->dev_priv;
+
+ rc = mcs7830_write_reg(dev, REG_MULTICAST_HASH,
+ sizeof(priv->mchash), &priv->mchash);
+ if (rc < 0) {
+ debug("writing multicast hash to adapter failed\n");
+ return rc;
+ }
+
+ return 0;
+}
+
+/*
+ * mcs7830_set_autoneg() - setup and trigger ethernet link autonegotiation
+ * @eth: network device to run link negotiation on
+ * Return: zero upon success, negative upon error
+ *
+ * the routine advertises available media and starts autonegotiation
+ */
+static int mcs7830_set_autoneg(struct ueth_data *dev)
+{
+ int adv, flg;
+ int rc;
+
+ debug("%s()\n", __func__);
+
+ /*
+ * algorithm taken from the Linux driver, which took it from
+ * "the original mcs7830 version 1.4 driver":
+ *
+ * enable all media, reset BMCR, enable auto neg, restart
+ * auto neg while keeping the enable auto neg flag set
+ */
+
+ adv = ADVERTISE_PAUSE_CAP | ADVERTISE_ALL | ADVERTISE_CSMA;
+ rc = mcs7830_write_phy(dev, MII_ADVERTISE, adv);
+
+ flg = 0;
+ if (!rc)
+ rc = mcs7830_write_phy(dev, MII_BMCR, flg);
+
+ flg |= BMCR_ANENABLE;
+ if (!rc)
+ rc = mcs7830_write_phy(dev, MII_BMCR, flg);
+
+ flg |= BMCR_ANRESTART;
+ if (!rc)
+ rc = mcs7830_write_phy(dev, MII_BMCR, flg);
+
+ return rc;
+}
+
+/*
+ * mcs7830_get_rev() - identify a network adapter's chip revision
+ * @eth: network device to identify
+ * Return: non-negative number, reflecting the revision number
+ *
+ * currently, only "rev C and higher" and "below rev C" are needed, so
+ * the return value is #1 for "below rev C", and #2 for "rev C and above"
+ */
+static int mcs7830_get_rev(struct ueth_data *dev)
+{
+ uint8_t buf[2];
+ int rc;
+ int rev;
+
+ /* register 22 is readable in rev C and higher */
+ rc = mcs7830_read_reg(dev, REG_FRAME_DROP_COUNTER, sizeof(buf), buf);
+ if (rc < 0)
+ rev = 1;
+ else
+ rev = 2;
+ debug("%s() rc=%d, rev=%d\n", __func__, rc, rev);
+ return rev;
+}
+
+/*
+ * mcs7830_apply_fixup() - identify an adapter and potentially apply fixups
+ * @eth: network device to identify and apply fixups to
+ * Return: zero upon success (no errors emitted from here)
+ *
+ * this routine identifies the network adapter's chip revision, and applies
+ * fixups for known issues
+ */
+static int mcs7830_apply_fixup(struct ueth_data *dev)
+{
+ int rev;
+ int i;
+ uint8_t thr;
+
+ rev = mcs7830_get_rev(dev);
+ debug("%s() rev=%d\n", __func__, rev);
+
+ /*
+ * rev C requires setting the pause threshold (the Linux driver
+ * is inconsistent, the implementation does it for "rev C
+ * exactly", the introductory comment says "rev C and above")
+ */
+ if (rev == 2) {
+ debug("%s: applying rev C fixup\n", dev->eth_dev.name);
+ thr = PAUSE_THRESHOLD_DEFAULT;
+ for (i = 0; i < 2; i++) {
+ (void)mcs7830_write_reg(dev, REG_PAUSE_THRESHOLD,
+ sizeof(thr), &thr);
+ mdelay(1);
+ }
+ }
+
+ return 0;
+}
+
+/*
+ * mcs7830_basic_reset() - bring the network adapter into a known first state
+ * @eth: network device to act upon
+ * Return: zero upon success, negative upon error
+ *
+ * this routine initializes the network adapter such that subsequent invocations
+ * of the interface callbacks can exchange ethernet frames; link negotiation is
+ * triggered from here already and continues in background
+ */
+static int mcs7830_basic_reset(struct ueth_data *dev)
+{
+ struct mcs7830_private *priv;
+ int rc;
+
+ debug("%s()\n", __func__);
+ priv = dev->dev_priv;
+
+ /*
+ * comment from the respective Linux driver, which
+ * unconditionally sets the ALLMULTICAST flag as well:
+ * should not be needed, but does not work otherwise
+ */
+ priv->config = CONF_TXENABLE;
+ priv->config |= CONF_ALLMULTICAST;
+
+ rc = mcs7830_set_autoneg(dev);
+ if (rc < 0) {
+ error("setting autoneg failed\n");
+ return rc;
+ }
+
+ rc = mcs7830_write_mchash(dev);
+ if (rc < 0) {
+ error("failed to set multicast hash\n");
+ return rc;
+ }
+
+ rc = mcs7830_write_config(dev);
+ if (rc < 0) {
+ error("failed to set configuration\n");
+ return rc;
+ }
+
+ rc = mcs7830_apply_fixup(dev);
+ if (rc < 0) {
+ error("fixup application failed\n");
+ return rc;
+ }
+
+ return 0;
+}
+
+/*
+ * mcs7830_read_mac() - read an ethernet adapter's MAC address
+ * @eth: network device to read from
+ * Return: zero upon success, negative upon error
+ *
+ * this routine fetches the MAC address stored within the ethernet adapter,
+ * and stores it in the ethernet interface's data structure
+ */
+static int mcs7830_read_mac(struct eth_device *eth)
+{
+ struct ueth_data *dev;
+ int rc;
+ uint8_t buf[ETH_ALEN];
+
+ debug("%s()\n", __func__);
+ dev = eth->priv;
+
+ rc = mcs7830_read_reg(dev, REG_ETHER_ADDR, ETH_ALEN, buf);
+ if (rc < 0) {
+ debug("reading MAC from adapter failed\n");
+ return rc;
+ }
+
+ memcpy(ð->enetaddr[0], buf, ETH_ALEN);
+ return 0;
+}
+
+/*
+ * mcs7830_write_mac() - write an ethernet adapter's MAC address
+ * @eth: network device to write to
+ * Return: zero upon success, negative upon error
+ *
+ * this routine takes the MAC address from the ethernet interface's data
+ * structure, and writes it into the ethernet adapter such that subsequent
+ * exchange of ethernet frames uses this address
+ */
+static int mcs7830_write_mac(struct eth_device *eth)
+{
+ struct ueth_data *dev;
+ int rc;
+
+ debug("%s()\n", __func__);
+ dev = eth->priv;
+
+ if (sizeof(eth->enetaddr) != ETH_ALEN)
+ return -EINVAL;
+ rc = mcs7830_write_reg(dev, REG_ETHER_ADDR, ETH_ALEN, eth->enetaddr);
+ if (rc < 0) {
+ debug("writing MAC to adapter failed\n");
+ return rc;
+ }
+ return 0;
+}
+
+/*
+ * mcs7830_init() - network interface's init callback
+ * @eth: network device to initialize
+ * @bd: board information
+ * Return: zero upon success, negative upon error
+ *
+ * after initial setup during probe() and get_info(), this init() callback
+ * ensures that the link is up and subsequent send() and recv() calls can
+ * exchange ethernet frames
+ */
+static int mcs7830_init(struct eth_device *eth, bd_t *bd)
+{
+ struct ueth_data *dev;
+ int timeout;
+ int have_link;
+
+ debug("%s()\n", __func__);
+ dev = eth->priv;
+
+ timeout = 0;
+ do {
+ have_link = mcs7830_read_phy(dev, MII_BMSR) & BMSR_LSTATUS;
+ if (have_link)
+ break;
+ udelay(LINKSTATUS_TIMEOUT_RES * 1000);
+ timeout += LINKSTATUS_TIMEOUT_RES;
+ } while (timeout < LINKSTATUS_TIMEOUT);
+ if (!have_link) {
+ debug("ethernet link is down\n");
+ return -ETIMEDOUT;
+ }
+ return 0;
+}
+
+/*
+ * mcs7830_send() - network interface's send callback
+ * @eth: network device to send the frame from
+ * @packet: ethernet frame content
+ * @length: ethernet frame length
+ * Return: zero upon success, negative upon error
+ *
+ * this routine send an ethernet frame out of the network interface
+ */
+static int mcs7830_send(struct eth_device *eth, void *packet, int length)
+{
+ struct ueth_data *dev;
+ int rc;
+ int gotlen;
+ /* there is a status byte after the ethernet frame */
+ ALLOC_CACHE_ALIGN_BUFFER(uint8_t, buf, PKTSIZE + sizeof(uint8_t));
+
+ dev = eth->priv;
+
+ memcpy(buf, packet, length);
+ rc = usb_bulk_msg(dev->pusb_dev,
+ usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
+ &buf[0], length, &gotlen,
+ USBCALL_TIMEOUT);
+ debug("%s() TX want len %d, got len %d, rc %d\n",
+ __func__, length, gotlen, rc);
+ return rc;
+}
+
+/*
+ * mcs7830_recv() - network interface's recv callback
+ * @eth: network device to receive frames from
+ * Return: zero upon success, negative upon error
+ *
+ * this routine checks for available ethernet frames that the network
+ * interface might have received, and notifies the network stack
+ */
+static int mcs7830_recv(struct eth_device *eth)
+{
+ struct ueth_data *dev;
+ ALLOC_CACHE_ALIGN_BUFFER(uint8_t, buf, MCS7830_RX_URB_SIZE);
+ int rc, wantlen, gotlen;
+ uint8_t sts;
+
+ debug("%s()\n", __func__);
+ dev = eth->priv;
+
+ /* fetch input data from the adapter */
+ wantlen = MCS7830_RX_URB_SIZE;
+ rc = usb_bulk_msg(dev->pusb_dev,
+ usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
+ &buf[0], wantlen, &gotlen,
+ USBCALL_TIMEOUT);
+ debug("%s() RX want len %d, got len %d, rc %d\n",
+ __func__, wantlen, gotlen, rc);
+ if (rc != 0) {
+ error("RX: failed to receive\n");
+ return rc;
+ }
+ if (gotlen > wantlen) {
+ error("RX: got too many bytes (%d)\n", gotlen);
+ return -EIO;
+ }
+
+ /*
+ * the bulk message that we received from USB contains exactly
+ * one ethernet frame and a trailing status byte
+ */
+ if (gotlen < sizeof(sts))
+ return -EIO;
+ gotlen -= sizeof(sts);
+ sts = buf[gotlen];
+
+ if (sts == STAT_RX_FRAME_CORRECT) {
+ debug("%s() got a frame, len=%d\n", __func__, gotlen);
+ NetReceive(buf, gotlen);
+ return 0;
+ }
+
+ debug("RX: frame error (sts 0x%02X, %s %s %s %s %s)\n",
+ sts,
+ (sts & STAT_RX_LARGE_FRAME) ? "large" : "-",
+ (sts & STAT_RX_LENGTH_ERROR) ? "length" : "-",
+ (sts & STAT_RX_SHORT_FRAME) ? "short" : "-",
+ (sts & STAT_RX_CRC_ERROR) ? "crc" : "-",
+ (sts & STAT_RX_ALIGNMENT_ERROR) ? "align" : "-");
+ return -EIO;
+}
+
+/*
+ * mcs7830_halt() - network interface's halt callback
+ * @eth: network device to cease operation of
+ * Return: none
+ *
+ * this routine is supposed to undo the effect of previous initialization and
+ * ethernet frames exchange; in this implementation it's a NOP
+ */
+static void mcs7830_halt(struct eth_device *eth)
+{
+ debug("%s()\n", __func__);
+}
+
+/*
+ * mcs7830_iface_idx - index of detected network interfaces
+ *
+ * this counter keeps track of identified supported interfaces,
+ * to assign unique names as more interfaces are found
+ */
+static int mcs7830_iface_idx;
+
+/*
+ * mcs7830_eth_before_probe() - network driver's before_probe callback
+ * Return: none
+ *
+ * this routine initializes driver's internal data in preparation of
+ * subsequent probe callbacks
+ */
+void mcs7830_eth_before_probe(void)
+{
+ mcs7830_iface_idx = 0;
+}
+
+/*
+ * struct mcs7830_dongle - description of a supported Moschip ethernet dongle
+ * @vendor: 16bit USB vendor identification
+ * @product: 16bit USB product identification
+ *
+ * this structure describes a supported USB ethernet dongle by means of the
+ * vendor and product codes found during USB enumeration; no flags are held
+ * here since all supported dongles have identical behaviour, and required
+ * fixups get determined at runtime, such that no manual configuration is
+ * needed
+ */
+struct mcs7830_dongle {
+ uint16_t vendor;
+ uint16_t product;
+};
+
+/*
+ * mcs7830_dongles - the list of supported Moschip based USB ethernet dongles
+ */
+static const struct mcs7830_dongle const mcs7830_dongles[] = {
+ { 0x9710, 0x7832, }, /* Moschip 7832 */
+ { 0x9710, 0x7830, }, /* Moschip 7830 */
+ { 0x9710, 0x7730, }, /* Moschip 7730 */
+ { 0x0df6, 0x0021, }, /* Sitecom LN 30 */
+};
+
+/*
+ * mcs7830_eth_probe() - network driver's probe callback
+ * @dev: detected USB device to check
+ * @ifnum: detected USB interface to check
+ * @ss: USB ethernet data structure to fill in upon match
+ * Return: #1 upon match, #0 upon mismatch or error
+ *
+ * this routine checks whether the found USB device is supported by
+ * this ethernet driver, and upon match fills in the USB ethernet
+ * data structure which later is passed to the get_info callback
+ */
+int mcs7830_eth_probe(struct usb_device *dev, unsigned int ifnum,
+ struct ueth_data *ss)
+{
+ struct usb_interface *iface;
+ struct usb_interface_descriptor *iface_desc;
+ int i;
+ struct mcs7830_private *priv;
+ int ep_in_found, ep_out_found, ep_intr_found;
+
+ debug("%s()\n", __func__);
+
+ /* iterate the list of supported dongles */
+ iface = &dev->config.if_desc[ifnum];
+ iface_desc = &iface->desc;
+ for (i = 0; i < ARRAY_SIZE(mcs7830_dongles); i++) {
+ if (dev->descriptor.idVendor == mcs7830_dongles[i].vendor &&
+ dev->descriptor.idProduct == mcs7830_dongles[i].product)
+ break;
+ }
+ if (i == ARRAY_SIZE(mcs7830_dongles))
+ return 0;
+ debug("detected USB ethernet device: %04X:%04X\n",
+ dev->descriptor.idVendor, dev->descriptor.idProduct);
+
+ /* fill in driver private data */
+ priv = calloc(1, sizeof(*priv));
+ if (!priv)
+ return 0;
+
+ /* fill in the ueth_data structure, attach private data */
+ memset(ss, 0, sizeof(*ss));
+ ss->ifnum = ifnum;
+ ss->pusb_dev = dev;
+ ss->subclass = iface_desc->bInterfaceSubClass;
+ ss->protocol = iface_desc->bInterfaceProtocol;
+ ss->dev_priv = priv;
+
+ /*
+ * a minimum of three endpoints is expected: in (bulk),
+ * out (bulk), and interrupt; ignore all others
+ */
+ ep_in_found = ep_out_found = ep_intr_found = 0;
+ for (i = 0; i < iface_desc->bNumEndpoints; i++) {
+ uint8_t eptype, epaddr;
+ bool is_input;
+
+ eptype = iface->ep_desc[i].bmAttributes;
+ eptype &= USB_ENDPOINT_XFERTYPE_MASK;
+
+ epaddr = iface->ep_desc[i].bEndpointAddress;
+ is_input = epaddr & USB_DIR_IN;
+ epaddr &= USB_ENDPOINT_NUMBER_MASK;
+
+ if (eptype == USB_ENDPOINT_XFER_BULK) {
+ if (is_input && !ep_in_found) {
+ ss->ep_in = epaddr;
+ ep_in_found++;
+ }
+ if (!is_input && !ep_out_found) {
+ ss->ep_out = epaddr;
+ ep_out_found++;
+ }
+ }
+
+ if (eptype == USB_ENDPOINT_XFER_INT) {
+ if (is_input && !ep_intr_found) {
+ ss->ep_int = epaddr;
+ ss->irqinterval = iface->ep_desc[i].bInterval;
+ ep_intr_found++;
+ }
+ }
+ }
+ debug("endpoints: in %d, out %d, intr %d\n",
+ ss->ep_in, ss->ep_out, ss->ep_int);
+
+ /* apply basic sanity checks */
+ if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
+ !ss->ep_in || !ss->ep_out || !ss->ep_int) {
+ debug("device probe incomplete\n");
+ return 0;
+ }
+
+ dev->privptr = ss;
+ return 1;
+}
+
+/*
+ * mcs7830_eth_get_info() - network driver's get_info callback
+ * @dev: detected USB device
+ * @ss: USB ethernet data structure filled in at probe()
+ * @eth: ethernet interface data structure to fill in
+ * Return: #1 upon success, #0 upon error
+ *
+ * this routine registers the mandatory init(), send(), recv(), and
+ * halt() callbacks with the ethernet interface, can register the
+ * optional write_hwaddr() callback with the ethernet interface,
+ * and initiates configuration of the interface such that subsequent
+ * calls to those callbacks results in network communication
+ */
+int mcs7830_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
+ struct eth_device *eth)
+{
+ debug("%s()\n", __func__);
+ if (!eth) {
+ debug("%s: missing parameter.\n", __func__);
+ return 0;
+ }
+
+ snprintf(eth->name, sizeof(eth->name), "%s%d",
+ MCS7830_BASE_NAME, mcs7830_iface_idx++);
+ eth->init = mcs7830_init;
+ eth->send = mcs7830_send;
+ eth->recv = mcs7830_recv;
+ eth->halt = mcs7830_halt;
+ eth->write_hwaddr = mcs7830_write_mac;
+ eth->priv = ss;
+
+ if (mcs7830_basic_reset(ss))
+ return 0;
+
+ if (mcs7830_read_mac(eth))
+ return 0;
+ debug("MAC %pM\n", eth->enetaddr);
+
+ return 1;
+}
.get_info = asix_eth_get_info,
},
#endif
+#ifdef CONFIG_USB_ETHER_MCS7830
+ {
+ .before_probe = mcs7830_eth_before_probe,
+ .probe = mcs7830_eth_probe,
+ .get_info = mcs7830_eth_get_info,
+ },
+#endif
#ifdef CONFIG_USB_ETHER_SMSC95XX
{
.before_probe = smsc95xx_eth_before_probe,
#define _USB_THOR_H_
#include <linux/compiler.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
/* THOR Composite Gadget */
#define STRING_MANUFACTURER_IDX 0
QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0);
qh->qh_endpt2 = cpu_to_hc32(endpt);
qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
+ qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
tdp = &qh->qh_overlay.qt_next;
debug("ehci intr queue: out of memory\n");
goto fail1;
}
- result->first = memalign(32, sizeof(struct QH) * queuesize);
+ result->first = memalign(USB_DMA_MINALIGN,
+ sizeof(struct QH) * queuesize);
if (!result->first) {
debug("ehci intr queue: out of memory\n");
goto fail2;
}
result->current = result->first;
result->last = result->first + queuesize - 1;
- result->tds = memalign(32, sizeof(struct qTD) * queuesize);
+ result->tds = memalign(USB_DMA_MINALIGN,
+ sizeof(struct qTD) * queuesize);
if (!result->tds) {
debug("ehci intr queue: out of memory\n");
goto fail3;
qh->qh_link = QH_LINK_TERMINATE;
qh->qh_overlay.qt_next = (uint32_t)td;
+ qh->qh_overlay.qt_altnext = QT_NEXT_TERMINATE;
qh->qh_endpt1 = (0 << 28) | /* No NAK reload (ehci 4.9) */
(usb_maxpacket(dev, pipe) << 16) | /* MPS */
(1 << 14) |
/* --- Virtual Root Hub ---------------------------------------------------- */
-/* Device descriptor */
-static __u8 root_hub_dev_des[] = {
- 0x12, /* __u8 bLength; */
- 0x01, /* __u8 bDescriptorType; Device */
- 0x10, /* __u16 bcdUSB; v1.1 */
- 0x01,
- 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
- 0x00, /* __u8 bDeviceSubClass; */
- 0x00, /* __u8 bDeviceProtocol; */
- 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
- 0x00, /* __u16 idVendor; */
- 0x00,
- 0x00, /* __u16 idProduct; */
- 0x00,
- 0x00, /* __u16 bcdDevice; */
- 0x00,
- 0x00, /* __u8 iManufacturer; */
- 0x01, /* __u8 iProduct; */
- 0x00, /* __u8 iSerialNumber; */
- 0x01 /* __u8 bNumConfigurations; */
-};
-
-/* Configuration descriptor */
-static __u8 root_hub_config_des[] = {
- 0x09, /* __u8 bLength; */
- 0x02, /* __u8 bDescriptorType; Configuration */
- 0x19, /* __u16 wTotalLength; */
- 0x00,
- 0x01, /* __u8 bNumInterfaces; */
- 0x01, /* __u8 bConfigurationValue; */
- 0x00, /* __u8 iConfiguration; */
- 0x40, /* __u8 bmAttributes;
- Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
- 0x00, /* __u8 MaxPower; */
-
- /* interface */
- 0x09, /* __u8 if_bLength; */
- 0x04, /* __u8 if_bDescriptorType; Interface */
- 0x00, /* __u8 if_bInterfaceNumber; */
- 0x00, /* __u8 if_bAlternateSetting; */
- 0x01, /* __u8 if_bNumEndpoints; */
- 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
- 0x00, /* __u8 if_bInterfaceSubClass; */
- 0x00, /* __u8 if_bInterfaceProtocol; */
- 0x00, /* __u8 if_iInterface; */
-
- /* endpoint */
- 0x07, /* __u8 ep_bLength; */
- 0x05, /* __u8 ep_bDescriptorType; Endpoint */
- 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
- 0x03, /* __u8 ep_bmAttributes; Interrupt */
- 0x00, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
- 0x02,
- 0xff /* __u8 ep_bInterval; 255 ms */
-};
-
-static unsigned char root_hub_str_index0[] = {
- 0x04, /* __u8 bLength; */
- 0x03, /* __u8 bDescriptorType; String-descriptor */
- 0x09, /* __u8 lang ID */
- 0x04, /* __u8 lang ID */
-};
-
-static unsigned char root_hub_str_index1[] = {
- 0x22, /* __u8 bLength; */
- 0x03, /* __u8 bDescriptorType; String-descriptor */
- 'I', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'S', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'P', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- '1', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- '1', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- '6', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'x', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- ' ', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'R', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'o', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'o', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 't', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- ' ', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'H', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'u', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'b', /* __u8 Unicode */
- 0, /* __u8 Unicode */
-};
+#include <usbroothubdes.h>
/*
* Hub class-specific descriptor is constructed dynamically
* Virtual Root Hub
*-------------------------------------------------------------------------*/
-/* Device descriptor */
-static __u8 root_hub_dev_des[] =
-{
- 0x12, /* __u8 bLength; */
- 0x01, /* __u8 bDescriptorType; Device */
- 0x10, /* __u16 bcdUSB; v1.1 */
- 0x01,
- 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
- 0x00, /* __u8 bDeviceSubClass; */
- 0x00, /* __u8 bDeviceProtocol; */
- 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
- 0x00, /* __u16 idVendor; */
- 0x00,
- 0x00, /* __u16 idProduct; */
- 0x00,
- 0x00, /* __u16 bcdDevice; */
- 0x00,
- 0x00, /* __u8 iManufacturer; */
- 0x01, /* __u8 iProduct; */
- 0x00, /* __u8 iSerialNumber; */
- 0x01 /* __u8 bNumConfigurations; */
-};
-
-/* Configuration descriptor */
-static __u8 root_hub_config_des[] =
-{
- 0x09, /* __u8 bLength; */
- 0x02, /* __u8 bDescriptorType; Configuration */
- 0x19, /* __u16 wTotalLength; */
- 0x00,
- 0x01, /* __u8 bNumInterfaces; */
- 0x01, /* __u8 bConfigurationValue; */
- 0x00, /* __u8 iConfiguration; */
- 0x40, /* __u8 bmAttributes;
- Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
- 0x00, /* __u8 MaxPower; */
-
- /* interface */
- 0x09, /* __u8 if_bLength; */
- 0x04, /* __u8 if_bDescriptorType; Interface */
- 0x00, /* __u8 if_bInterfaceNumber; */
- 0x00, /* __u8 if_bAlternateSetting; */
- 0x01, /* __u8 if_bNumEndpoints; */
- 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
- 0x00, /* __u8 if_bInterfaceSubClass; */
- 0x00, /* __u8 if_bInterfaceProtocol; */
- 0x00, /* __u8 if_iInterface; */
-
- /* endpoint */
- 0x07, /* __u8 ep_bLength; */
- 0x05, /* __u8 ep_bDescriptorType; Endpoint */
- 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
- 0x03, /* __u8 ep_bmAttributes; Interrupt */
- 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
- 0x00,
- 0xff /* __u8 ep_bInterval; 255 ms */
-};
-
-static unsigned char root_hub_str_index0[] =
-{
- 0x04, /* __u8 bLength; */
- 0x03, /* __u8 bDescriptorType; String-descriptor */
- 0x09, /* __u8 lang ID */
- 0x04, /* __u8 lang ID */
-};
-
-static unsigned char root_hub_str_index1[] =
-{
- 28, /* __u8 bLength; */
- 0x03, /* __u8 bDescriptorType; String-descriptor */
- 'O', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'H', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'C', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'I', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- ' ', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'R', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'o', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'o', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 't', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- ' ', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'H', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'u', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'b', /* __u8 Unicode */
- 0, /* __u8 Unicode */
-};
+#include <usbroothubdes.h>
/* Hub class-specific descriptor is constructed dynamically */
* Virtual Root Hub
*-------------------------------------------------------------------------*/
-/* Device descriptor */
-static __u8 root_hub_dev_des[] = {
- 0x12, /* __u8 bLength; */
- 0x01, /* __u8 bDescriptorType; Device */
- 0x10, /* __u16 bcdUSB; v1.1 */
- 0x01,
- 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
- 0x00, /* __u8 bDeviceSubClass; */
- 0x00, /* __u8 bDeviceProtocol; */
- 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
- 0x00, /* __u16 idVendor; */
- 0x00,
- 0x00, /* __u16 idProduct; */
- 0x00,
- 0x00, /* __u16 bcdDevice; */
- 0x00,
- 0x00, /* __u8 iManufacturer; */
- 0x01, /* __u8 iProduct; */
- 0x00, /* __u8 iSerialNumber; */
- 0x01 /* __u8 bNumConfigurations; */
-};
-
-/* Configuration descriptor */
-static __u8 root_hub_config_des[] = {
- 0x09, /* __u8 bLength; */
- 0x02, /* __u8 bDescriptorType; Configuration */
- 0x19, /* __u16 wTotalLength; */
- 0x00,
- 0x01, /* __u8 bNumInterfaces; */
- 0x01, /* __u8 bConfigurationValue; */
- 0x00, /* __u8 iConfiguration; */
- 0x40, /* __u8 bmAttributes;
- Bit 7: Bus-powered, 6: Self-powered,
- 5 Remote-wakwup, 4..0: resvd */
- 0x00, /* __u8 MaxPower; */
-
- /* interface */
- 0x09, /* __u8 if_bLength; */
- 0x04, /* __u8 if_bDescriptorType; Interface */
- 0x00, /* __u8 if_bInterfaceNumber; */
- 0x00, /* __u8 if_bAlternateSetting; */
- 0x01, /* __u8 if_bNumEndpoints; */
- 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
- 0x00, /* __u8 if_bInterfaceSubClass; */
- 0x00, /* __u8 if_bInterfaceProtocol; */
- 0x00, /* __u8 if_iInterface; */
-
- /* endpoint */
- 0x07, /* __u8 ep_bLength; */
- 0x05, /* __u8 ep_bDescriptorType; Endpoint */
- 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
- 0x03, /* __u8 ep_bmAttributes; Interrupt */
- 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
- 0x00,
- 0xff /* __u8 ep_bInterval; 255 ms */
-};
-
-static unsigned char root_hub_str_index0[] = {
- 0x04, /* __u8 bLength; */
- 0x03, /* __u8 bDescriptorType; String-descriptor */
- 0x09, /* __u8 lang ID */
- 0x04, /* __u8 lang ID */
-};
-
-static unsigned char root_hub_str_index1[] = {
- 28, /* __u8 bLength; */
- 0x03, /* __u8 bDescriptorType; String-descriptor */
- 'O', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'H', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'C', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'I', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- ' ', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'R', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'o', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'o', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 't', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- ' ', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'H', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'u', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'b', /* __u8 Unicode */
- 0, /* __u8 Unicode */
-};
+#include <usbroothubdes.h>
/* Hub class-specific descriptor is constructed dynamically */
* Virtual Root Hub
*-------------------------------------------------------------------------*/
-/* Device descriptor */
-static __u8 root_hub_dev_des[] =
-{
- 0x12, /* __u8 bLength; */
- 0x01, /* __u8 bDescriptorType; Device */
- 0x10, /* __u16 bcdUSB; v1.1 */
- 0x01,
- 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
- 0x00, /* __u8 bDeviceSubClass; */
- 0x00, /* __u8 bDeviceProtocol; */
- 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
- 0x00, /* __u16 idVendor; */
- 0x00,
- 0x00, /* __u16 idProduct; */
- 0x00,
- 0x00, /* __u16 bcdDevice; */
- 0x00,
- 0x00, /* __u8 iManufacturer; */
- 0x01, /* __u8 iProduct; */
- 0x00, /* __u8 iSerialNumber; */
- 0x01 /* __u8 bNumConfigurations; */
-};
-
-/* Configuration descriptor */
-static __u8 root_hub_config_des[] =
-{
- 0x09, /* __u8 bLength; */
- 0x02, /* __u8 bDescriptorType; Configuration */
- 0x19, /* __u16 wTotalLength; */
- 0x00,
- 0x01, /* __u8 bNumInterfaces; */
- 0x01, /* __u8 bConfigurationValue; */
- 0x00, /* __u8 iConfiguration; */
- 0x40, /* __u8 bmAttributes; */
-
- 0x00, /* __u8 MaxPower; */
-
- /* interface */
- 0x09, /* __u8 if_bLength; */
- 0x04, /* __u8 if_bDescriptorType; Interface */
- 0x00, /* __u8 if_bInterfaceNumber; */
- 0x00, /* __u8 if_bAlternateSetting; */
- 0x01, /* __u8 if_bNumEndpoints; */
- 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
- 0x00, /* __u8 if_bInterfaceSubClass; */
- 0x00, /* __u8 if_bInterfaceProtocol; */
- 0x00, /* __u8 if_iInterface; */
-
- /* endpoint */
- 0x07, /* __u8 ep_bLength; */
- 0x05, /* __u8 ep_bDescriptorType; Endpoint */
- 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
- 0x03, /* __u8 ep_bmAttributes; Interrupt */
- 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
- 0x00,
- 0xff /* __u8 ep_bInterval; 255 ms */
-};
-
-static unsigned char root_hub_str_index0[] =
-{
- 0x04, /* __u8 bLength; */
- 0x03, /* __u8 bDescriptorType; String-descriptor */
- 0x09, /* __u8 lang ID */
- 0x04, /* __u8 lang ID */
-};
-
-static unsigned char root_hub_str_index1[] =
-{
- 34, /* __u8 bLength; */
- 0x03, /* __u8 bDescriptorType; String-descriptor */
- 'R', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- '8', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'A', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- '6', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- '6', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- '5', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- '9', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- '7', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- ' ', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'R', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'o', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'o', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 't', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'H', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'u', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'b', /* __u8 Unicode */
- 0, /* __u8 Unicode */
-};
+#include <usbroothubdes.h>
static int r8a66597_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
void *buffer, int transfer_len, struct devrequest *cmd)
static int rh_devnum;
static u32 port_status;
-/* Device descriptor */
-static const u8 root_hub_dev_des[] = {
- 0x12, /* __u8 bLength; */
- 0x01, /* __u8 bDescriptorType; Device */
- 0x00, /* __u16 bcdUSB; v1.1 */
- 0x02,
- 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
- 0x00, /* __u8 bDeviceSubClass; */
- 0x00, /* __u8 bDeviceProtocol; */
- 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
- 0x00, /* __u16 idVendor; */
- 0x00,
- 0x00, /* __u16 idProduct; */
- 0x00,
- 0x00, /* __u16 bcdDevice; */
- 0x00,
- 0x00, /* __u8 iManufacturer; */
- 0x01, /* __u8 iProduct; */
- 0x00, /* __u8 iSerialNumber; */
- 0x01 /* __u8 bNumConfigurations; */
-};
-
-/* Configuration descriptor */
-static const u8 root_hub_config_des[] = {
- 0x09, /* __u8 bLength; */
- 0x02, /* __u8 bDescriptorType; Configuration */
- 0x19, /* __u16 wTotalLength; */
- 0x00,
- 0x01, /* __u8 bNumInterfaces; */
- 0x01, /* __u8 bConfigurationValue; */
- 0x00, /* __u8 iConfiguration; */
- 0x40, /* __u8 bmAttributes;
- Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
- 0x00, /* __u8 MaxPower; */
-
- /* interface */
- 0x09, /* __u8 if_bLength; */
- 0x04, /* __u8 if_bDescriptorType; Interface */
- 0x00, /* __u8 if_bInterfaceNumber; */
- 0x00, /* __u8 if_bAlternateSetting; */
- 0x01, /* __u8 if_bNumEndpoints; */
- 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
- 0x00, /* __u8 if_bInterfaceSubClass; */
- 0x00, /* __u8 if_bInterfaceProtocol; */
- 0x00, /* __u8 if_iInterface; */
-
- /* endpoint */
- 0x07, /* __u8 ep_bLength; */
- 0x05, /* __u8 ep_bDescriptorType; Endpoint */
- 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
- 0x03, /* __u8 ep_bmAttributes; Interrupt */
- 0x00, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
- 0x02,
- 0xff /* __u8 ep_bInterval; 255 ms */
-};
+#include <usbroothubdes.h>
-static const unsigned char root_hub_str_index0[] = {
- 0x04, /* __u8 bLength; */
- 0x03, /* __u8 bDescriptorType; String-descriptor */
- 0x09, /* __u8 lang ID */
- 0x04, /* __u8 lang ID */
-};
-
-static const unsigned char root_hub_str_index1[] = {
- 0x1c, /* __u8 bLength; */
- 0x03, /* __u8 bDescriptorType; String-descriptor */
- 'M', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'U', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'S', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'B', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- ' ', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'R', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'o', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'o', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 't', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- ' ', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'H', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'u', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'b', /* __u8 Unicode */
- 0, /* __u8 Unicode */
-};
#endif
/*
obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o
obj-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o
+obj-$(CONFIG_VIDEO_SANDBOX_SDL) += sandbox_sdl.o
obj-$(CONFIG_VIDEO_SED13806) += sed13806.o
obj-$(CONFIG_VIDEO_SM501) += sm501.o
obj-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o
printf("Error: malloc in gunzip failed!\n");
return 1;
}
- if (gunzip(dst, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE,
+ /*
+ * NB: we need to force offset of +2
+ * See doc/README.displaying-bmps
+ */
+ if (gunzip(dst+2, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE-2,
(uchar *) bmp_image,
&len) != 0) {
printf("Error: no valid bmp or bmp.gz image at %lx\n",
/*
* Set addr to decompressed image
*/
- bmp = (bmp_image_t *) dst;
+ bmp = (bmp_image_t *)(dst+2);
if (!((bmp->header.signature[0] == 'B') &&
(bmp->header.signature[1] == 'M'))) {
void exynos_backlight_reset(void)
__attribute__((weak, alias("__exynos_backlight_reset")));
+int __exynos_lcd_misc_init(vidinfo_t *vid)
+{
+ return 0;
+}
+int exynos_lcd_misc_init(vidinfo_t *vid)
+ __attribute__((weak, alias("__exynos_lcd_misc_init")));
+
static void lcd_panel_on(vidinfo_t *vid)
{
udelay(vid->init_delay);
#ifdef CONFIG_OF_CONTROL
if (exynos_fimd_parse_dt(gd->fdt_blob))
debug("Can't get proper panel info\n");
+#ifdef CONFIG_EXYNOS_MIPI_DSIM
+ exynos_init_dsim_platform_data(&panel_info);
+#endif
+ exynos_lcd_misc_init(&panel_info);
#else
/* initialize parameters which is specific to panel. */
init_panel_info(&panel_info);
#endif
+
panel_width = panel_info.vl_width;
panel_height = panel_info.vl_height;
#include <common.h>
#include <malloc.h>
+#include <fdtdec.h>
+#include <libfdt.h>
#include <linux/err.h>
#include <asm/arch/dsim.h>
#include <asm/arch/mipi_dsim.h>
#define master_to_driver(a) (a->dsim_lcd_drv)
#define master_to_device(a) (a->dsim_lcd_dev)
+DECLARE_GLOBAL_DATA_PTR;
+
static struct exynos_platform_mipi_dsim *dsim_pd;
+#ifdef CONFIG_OF_CONTROL
+static struct mipi_dsim_config dsim_config_dt;
+static struct exynos_platform_mipi_dsim dsim_platform_data_dt;
+static struct mipi_dsim_lcd_device mipi_lcd_device_dt;
+#endif
struct mipi_dsim_ddi {
int bus_id;
dsim_pd = pd;
}
+
+#ifdef CONFIG_OF_CONTROL
+int exynos_dsim_config_parse_dt(const void *blob)
+{
+ int node;
+
+ node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_MIPI_DSI);
+ if (node <= 0) {
+ printf("exynos_mipi_dsi: Can't get device node for mipi dsi\n");
+ return -ENODEV;
+ }
+
+ dsim_config_dt.e_interface = fdtdec_get_int(blob, node,
+ "samsung,dsim-config-e-interface", 0);
+
+ dsim_config_dt.e_virtual_ch = fdtdec_get_int(blob, node,
+ "samsung,dsim-config-e-virtual-ch", 0);
+
+ dsim_config_dt.e_pixel_format = fdtdec_get_int(blob, node,
+ "samsung,dsim-config-e-pixel-format", 0);
+
+ dsim_config_dt.e_burst_mode = fdtdec_get_int(blob, node,
+ "samsung,dsim-config-e-burst-mode", 0);
+
+ dsim_config_dt.e_no_data_lane = fdtdec_get_int(blob, node,
+ "samsung,dsim-config-e-no-data-lane", 0);
+
+ dsim_config_dt.e_byte_clk = fdtdec_get_int(blob, node,
+ "samsung,dsim-config-e-byte-clk", 0);
+
+ dsim_config_dt.hfp = fdtdec_get_int(blob, node,
+ "samsung,dsim-config-hfp", 0);
+
+ dsim_config_dt.p = fdtdec_get_int(blob, node,
+ "samsung,dsim-config-p", 0);
+ dsim_config_dt.m = fdtdec_get_int(blob, node,
+ "samsung,dsim-config-m", 0);
+ dsim_config_dt.s = fdtdec_get_int(blob, node,
+ "samsung,dsim-config-s", 0);
+
+ dsim_config_dt.pll_stable_time = fdtdec_get_int(blob, node,
+ "samsung,dsim-config-pll-stable-time", 0);
+
+ dsim_config_dt.esc_clk = fdtdec_get_int(blob, node,
+ "samsung,dsim-config-esc-clk", 0);
+
+ dsim_config_dt.stop_holding_cnt = fdtdec_get_int(blob, node,
+ "samsung,dsim-config-stop-holding-cnt", 0);
+
+ dsim_config_dt.bta_timeout = fdtdec_get_int(blob, node,
+ "samsung,dsim-config-bta-timeout", 0);
+
+ dsim_config_dt.rx_timeout = fdtdec_get_int(blob, node,
+ "samsung,dsim-config-rx-timeout", 0);
+
+ mipi_lcd_device_dt.name = fdtdec_get_config_string(blob,
+ "samsung,dsim-device-name");
+
+ mipi_lcd_device_dt.id = fdtdec_get_int(blob, node,
+ "samsung,dsim-device-id", 0);
+
+ mipi_lcd_device_dt.bus_id = fdtdec_get_int(blob, node,
+ "samsung,dsim-device-bus_id", 0);
+
+ mipi_lcd_device_dt.reverse_panel = fdtdec_get_int(blob, node,
+ "samsung,dsim-device-reverse-panel", 0);
+
+ return 0;
+}
+
+void exynos_init_dsim_platform_data(vidinfo_t *vid)
+{
+ if (exynos_dsim_config_parse_dt(gd->fdt_blob))
+ debug("Can't get proper dsim config.\n");
+
+ strcpy(dsim_platform_data_dt.lcd_panel_name, mipi_lcd_device_dt.name);
+ dsim_platform_data_dt.dsim_config = &dsim_config_dt;
+ dsim_platform_data_dt.mipi_power = mipi_power;
+ dsim_platform_data_dt.phy_enable = set_mipi_phy_ctrl;
+ dsim_platform_data_dt.lcd_panel_info = (void *)vid;
+
+ mipi_lcd_device_dt.platform_data = (void *)&dsim_platform_data_dt;
+ exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device_dt);
+
+ dsim_pd = &dsim_platform_data_dt;
+}
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <lcd.h>
+#include <malloc.h>
+#include <asm/sdl.h>
+#include <asm/u-boot-sandbox.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+ /* Maximum LCD size we support */
+ LCD_MAX_WIDTH = 1366,
+ LCD_MAX_HEIGHT = 768,
+ LCD_MAX_LOG2_BPP = 4, /* 2^4 = 16 bpp */
+};
+
+vidinfo_t panel_info;
+
+void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
+{
+}
+
+void lcd_ctrl_init(void *lcdbase)
+{
+ /*
+ * Allocate memory to keep BMP color conversion map. This is required
+ * for 8 bit BMPs only (hence 256 colors). If malloc fails - keep
+ * going, it is not even clear if displyaing the bitmap will be
+ * required on the way up.
+ */
+ panel_info.cmap = malloc(256 * NBITS(panel_info.vl_bpix) / 8);
+}
+
+void lcd_enable(void)
+{
+ if (sandbox_sdl_init_display(panel_info.vl_col, panel_info.vl_row,
+ panel_info.vl_bpix))
+ puts("LCD init failed\n");
+}
+
+int sandbox_lcd_sdl_early_init(void)
+{
+ const void *blob = gd->fdt_blob;
+ int xres = LCD_MAX_WIDTH, yres = LCD_MAX_HEIGHT;
+ int node;
+ int ret = 0;
+
+ /*
+ * The code in common/lcd.c does not cope with not being able to
+ * set up a frame buffer. It will just happily keep writing to
+ * invalid memory. So here we make sure that at least some buffer
+ * is available even if it actually won't be displayed.
+ */
+ node = fdtdec_next_compatible(blob, 0, COMPAT_SANDBOX_LCD_SDL);
+ if (node >= 0) {
+ xres = fdtdec_get_int(blob, node, "xres", LCD_MAX_WIDTH);
+ yres = fdtdec_get_int(blob, node, "yres", LCD_MAX_HEIGHT);
+ if (xres < 0 || xres > LCD_MAX_WIDTH) {
+ xres = LCD_MAX_WIDTH;
+ ret = -EINVAL;
+ }
+ if (yres < 0 || yres > LCD_MAX_HEIGHT) {
+ yres = LCD_MAX_HEIGHT;
+ ret = -EINVAL;
+ }
+ }
+
+ panel_info.vl_col = xres;
+ panel_info.vl_row = yres;
+ panel_info.vl_bpix = LCD_COLOR16;
+
+ return ret;
+}
extra-$(CONFIG_SPI_FLASH_ATMEL) += atmel_df_pow2
extra-$(CONFIG_MPC5xxx) += interrupt
extra-$(CONFIG_8xx) += test_burst timer
-extra-$(CONFIG_8260) += mem_to_mem_idma2intr
+extra-$(CONFIG_MPC8260) += mem_to_mem_idma2intr
extra-$(CONFIG_PPC) += sched
#
# relocatable executable. The relocation data is not needed, and
# also causes the entry point of the standalone application to be
# inconsistent.
-ifeq ($(ARCH),powerpc)
-# FIX ME
-CPPFLAGS := $(filter-out $(RELFLAGS), $(CPPFLAGS))
+ifeq ($(CONFIG_PPC),y)
+PLATFORM_CPPFLAGS := $(filter-out $(RELFLAGS),$(PLATFORM_CPPFLAGS))
endif
# We don't want gcc reordering functions if possible. This ensures that an
+++ /dev/null
-/*
- * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
- *
- * Copyright (C) 2002-2011 Aleph One Ltd.
- * for Toby Churchill Ltd and Brightstar Engineering
- *
- * Created by Charles Manning <charles@aleph1.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License version 2.1 as
- * published by the Free Software Foundation.
- *
- * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
- */
-
-/*
- * This file is just holds extra declarations of macros that would normally
- * be providesd in the Linux kernel. These macros have been written from
- * scratch but are functionally equivalent to the Linux ones.
- *
- */
-
-#ifndef __YAFFS_LIST_H__
-#define __YAFFS_LIST_H__
-
-
-/*
- * This is a simple doubly linked list implementation that matches the
- * way the Linux kernel doubly linked list implementation works.
- */
-
-struct list_head {
- struct list_head *next; /* next in chain */
- struct list_head *prev; /* previous in chain */
-};
-
-
-/* Initialise a static list */
-#define LIST_HEAD(name) \
-struct list_head name = { &(name), &(name)}
-
-
-
-/* Initialise a list head to an empty list */
-#define INIT_LIST_HEAD(p) \
-do { \
- (p)->next = (p);\
- (p)->prev = (p); \
-} while (0)
-
-
-/* Add an element to a list */
-static inline void list_add(struct list_head *new_entry,
- struct list_head *list)
-{
- struct list_head *list_next = list->next;
-
- list->next = new_entry;
- new_entry->prev = list;
- new_entry->next = list_next;
- list_next->prev = new_entry;
-
-}
-
-static inline void list_add_tail(struct list_head *new_entry,
- struct list_head *list)
-{
- struct list_head *list_prev = list->prev;
-
- list->prev = new_entry;
- new_entry->next = list;
- new_entry->prev = list_prev;
- list_prev->next = new_entry;
-
-}
-
-
-/* Take an element out of its current list, with or without
- * reinitialising the links.of the entry*/
-static inline void list_del(struct list_head *entry)
-{
- struct list_head *list_next = entry->next;
- struct list_head *list_prev = entry->prev;
-
- list_next->prev = list_prev;
- list_prev->next = list_next;
-
-}
-
-static inline void list_del_init(struct list_head *entry)
-{
- list_del(entry);
- entry->next = entry->prev = entry;
-}
-
-
-/* Test if the list is empty */
-static inline int list_empty(struct list_head *entry)
-{
- return (entry->next == entry);
-}
-
-
-/* list_entry takes a pointer to a list entry and offsets it to that
- * we can find a pointer to the object it is embedded in.
- */
-
-
-#define list_entry(entry, type, member) \
- ((type *)((char *)(entry)-(unsigned long)(&((type *)NULL)->member)))
-
-
-/* list_for_each and list_for_each_safe iterate over lists.
- * list_for_each_safe uses temporary storage to make the list delete safe
- */
-
-#define list_for_each(itervar, list) \
- for (itervar = (list)->next; itervar != (list); itervar = itervar->next)
-
-#define list_for_each_safe(itervar, save_var, list) \
- for (itervar = (list)->next, save_var = (list)->next->next; \
- itervar != (list); \
- itervar = save_var, save_var = save_var->next)
-
-
-#endif
#define YAFFS_ROOT_MODE 0666
#define YAFFS_LOSTNFOUND_MODE 0666
-#include "yaffs_list.h"
+#include "linux/list.h"
#include "yaffsfs.h"
*/
#ifndef __ASSEMBLY__
+#include <linux/list.h>
+
typedef struct global_data {
bd_t *bd;
unsigned long flags;
unsigned long start_addr_sp; /* start_addr_stackpointer */
unsigned long reloc_off;
struct global_data *new_gd; /* relocated global data */
+
+#ifdef CONFIG_DM
+ struct device *dm_root; /* Root instance for Driver Model */
+ struct list_head uclass_root; /* Head of core tree */
+#endif
+
const void *fdt_blob; /* Our device tree, NULL if none */
void *new_fdt; /* Relocated FDT */
unsigned long fdt_size; /* Space reserved for relocated FDT */
* @return 0 if ok, -1 on error
*/
int gpio_set_value(unsigned gpio, int value);
+
+/* State of a GPIO, as reported by get_state() */
+enum {
+ GPIOF_INPUT = 0,
+ GPIOF_OUTPUT,
+ GPIOF_UNKNOWN,
+};
+
+struct device;
+
+/**
+ * struct struct dm_gpio_ops - Driver model GPIO operations
+ *
+ * Refer to functions above for description. These function largely copy
+ * the old API.
+ *
+ * This is trying to be close to Linux GPIO API. Once the U-Boot uses the
+ * new DM GPIO API, this should be really easy to flip over to the Linux
+ * GPIO API-alike interface.
+ *
+ * Akso it would be useful to standardise additional functions like
+ * pullup, slew rate and drive strength.
+ *
+ * gpio_request)( and gpio_free() are optional - if NULL then they will
+ * not be called.
+ *
+ * Note that @offset is the offset from the base GPIO of the device. So
+ * offset 0 is the device's first GPIO and offset o-1 is the last GPIO,
+ * where o is the number of GPIO lines controlled by the device. A device
+ * is typically used to control a single bank of GPIOs. Within complex
+ * SoCs there may be many banks and therefore many devices all referring
+ * to the different IO addresses within the SoC.
+ *
+ * The uclass combines all GPIO devices togther to provide a consistent
+ * numbering from 0 to n-1, where n is the number of GPIOs in total across
+ * all devices. Be careful not to confuse offset with gpio in the parameters.
+ */
+struct dm_gpio_ops {
+ int (*request)(struct device *dev, unsigned offset, const char *label);
+ int (*free)(struct device *dev, unsigned offset);
+ int (*direction_input)(struct device *dev, unsigned offset);
+ int (*direction_output)(struct device *dev, unsigned offset,
+ int value);
+ int (*get_value)(struct device *dev, unsigned offset);
+ int (*set_value)(struct device *dev, unsigned offset, int value);
+ int (*get_function)(struct device *dev, unsigned offset);
+ int (*get_state)(struct device *dev, unsigned offset, char *state,
+ int maxlen);
+};
+
+/**
+ * struct gpio_dev_priv - information about a device used by the uclass
+ *
+ * The uclass combines all active GPIO devices into a unified numbering
+ * scheme. To do this it maintains some private information aobut each
+ * device.
+ *
+ * To implement driver model support in your GPIO driver, add a probe
+ * handler, and set @gpio_count and @bank_name correctly in that handler.
+ * This tells the uclass the name of the GPIO bank and the number of GPIOs
+ * it contains.
+ *
+ * @bank_name: Name of the GPIO device (e.g 'a' means GPIOs will be called
+ * 'A0', 'A1', etc.
+ * @gpio_count: Number of GPIOs in this device
+ * @gpio_base: Base GPIO number for this device. For the first active device
+ * this will be 0; the numbering for others will follow sequentially so that
+ * @gpio_base for device 1 will equal the number of GPIOs in device 0.
+ */
+struct gpio_dev_priv {
+ const char *bank_name;
+ unsigned gpio_count;
+ unsigned gpio_base;
+};
+
+/* Access the GPIO operations for a device */
+#define gpio_get_ops(dev) ((struct dm_gpio_ops *)(dev)->driver->ops)
+
+/**
+ * gpio_get_bank_info - Return information about a GPIO bank/device
+ *
+ * This looks up a device and returns both its GPIO base name and the number
+ * of GPIOs it controls.
+ *
+ * @dev: Device to look up
+ * @offset_count: Returns number of GPIOs within this bank
+ * @return bank name of this device
+ */
+const char *gpio_get_bank_info(struct device *dev, int *offset_count);
+
+/**
+ * gpio_lookup_name - Look up a GPIO name and return its details
+ *
+ * This is used to convert a named GPIO into a device, offset and GPIO
+ * number.
+ *
+ * @name: GPIO name to look up
+ * @devp: Returns pointer to device which contains this GPIO
+ * @offsetp: Returns the offset number within this device
+ * @gpiop: Returns the absolute GPIO number, numbered from 0
+ */
+int gpio_lookup_name(const char *name, struct device **devp,
+ unsigned int *offsetp, unsigned int *gpiop);
+
#endif /* _ASM_GENERIC_GPIO_H_ */
unsigned long bi_dsp_freq; /* dsp core frequency */
unsigned long bi_ddr_freq; /* ddr frequency */
#endif
-#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \
+#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_MPC8260) \
|| defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
unsigned long bi_immr_base; /* base of IMMR register */
#endif
extern int cmd_auto_complete(const char *const prompt, char *buf, int *np, int *colp);
#endif
+/**
+ * cmd_process_error() - report and process a possible error
+ *
+ * @cmdtp: Command which caused the error
+ * @err: Error code (0 if none, -ve for error, like -EIO)
+ * @return 0 if there is not error, 1 (CMD_RET_FAILURE) if an error is found
+ */
+int cmd_process_error(cmd_tbl_t *cmdtp, int err);
+
/*
* Monitor Command
*
#include <mpc5xxx.h>
#elif defined(CONFIG_MPC512X)
#include <asm/immap_512x.h>
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
#if defined(CONFIG_MPC8247) \
|| defined(CONFIG_MPC8248) \
|| defined(CONFIG_MPC8271) \
|| defined(CONFIG_MPC8272)
#define CONFIG_MPC8272_FAMILY 1
#endif
-#if defined(CONFIG_MPC8272_FAMILY)
-#define CONFIG_MPC8260 1
-#endif
#include <asm/immap_8260.h>
#endif
#ifdef CONFIG_MPC86xx
#include <flash.h>
#include <image.h>
+#ifdef __LP64__
+#define CONFIG_SYS_SUPPORT_64BIT_DATA
+#endif
+
#ifdef DEBUG
#define _DEBUG 1
#else
}
#endif
int update_flash_size(int flash_size);
+int arch_early_init_r(void);
/**
* Show the DRAM size in a board-specific way
int env_init (void);
void env_relocate (void);
int envmatch (uchar *, int);
+
+/* Avoid unfortunate conflict with libc's getenv() */
+#ifdef CONFIG_SANDBOX
+#define getenv uboot_getenv
+#endif
char *getenv (const char *);
int getenv_f (const char *name, char *buf, unsigned len);
ulong getenv_ulong(const char *name, int base, ulong default_val);
int get_clocks_866 (void);
int sdram_adjust_866 (void);
int adjust_sdram_tbs_8xx (void);
-#if defined(CONFIG_8260)
+#if defined(CONFIG_MPC8260)
int prt_8260_clks (void);
#elif defined(CONFIG_MPC5xxx)
int prt_mpc5xxx_clks (void);
#endif
/* $(CPU)/cpu_init.c */
-#if defined(CONFIG_8xx) || defined(CONFIG_8260)
+#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260)
void cpu_init_f (volatile immap_t *immr);
#endif
#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2) ||defined(CONFIG_MPC86xx)
#endif
int cpu_init_r (void);
-#if defined(CONFIG_8260)
+#if defined(CONFIG_MPC8260)
int prt_8260_rsr (void);
#elif defined(CONFIG_MPC83xx)
int prt_83xx_rsr (void);
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
-#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/b4860qds/b4_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/b4860qds/b4_rcw.cfg
#endif
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
* (easy to change)
*/
-#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_CPU86 1 /* ...on a CPU86 board */
#define CONFIG_CPM2 1 /* Has a CPM2 */
* (easy to change)
*/
-#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_CPU87 1 /* ...on a CPU87 board */
#define CONFIG_PCI
#define CONFIG_CPM2 1 /* Has a CPM2 */
* (easy to change)
*/
-#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
#define CONFIG_MPC8272_FAMILY 1
#define CONFIG_IDS8247 1
#define CPU_ID_STR "MPC8247"
* (easy to change)
*/
-#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_IPHASE4539 1 /* ...on a Interphase 4539 PMC */
#define CONFIG_SYS_TEXT_BASE 0xffb00000
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_MPC8260 /* This is an MPC8260 CPU */
#define CONFIG_ISPAN /* ...on one of Interphase iSPAN boards */
#define CONFIG_CPM2 1 /* Has a CPM2 */
+++ /dev/null
-/*
- * Configuation settings for the Freescale M5271EVB
- *
- * Based on MC5272C3 and r5200 board configs
- * (C) Copyright 2006 Lab X Technologies <zachary.landau@labxtechnologies.com>
- * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef _M5271EVB_H
-#define _M5271EVB_H
-
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_MCF52x2 /* define processor family */
-#define CONFIG_M5271 /* define processor type */
-#define CONFIG_M5271EVB /* define board type */
-
-#define CONFIG_MCFTMR
-
-#define CONFIG_MCFUART
-#define CONFIG_SYS_UART_PORT (0)
-#define CONFIG_BAUDRATE 115200
-
-#undef CONFIG_WATCHDOG /* disable watchdog */
-
-/* Configuration for environment
- * Environment is embedded in u-boot in the second sector of the flash
- */
-#ifndef CONFIG_MONITOR_IS_IN_RAM
-#define CONFIG_ENV_OFFSET 0x4000
-#else
-#define CONFIG_ENV_ADDR 0xffe04000
-#endif
-#define CONFIG_ENV_SECT_SIZE 0x2000
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_MISC
-
-#undef CONFIG_CMD_LOADS
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMDLINE_EDITING 1 /* enables command line history */
-#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
-
-#define CONFIG_MCFFEC
-#ifdef CONFIG_MCFFEC
-# define CONFIG_MII 1
-# define CONFIG_MII_INIT 1
-# define CONFIG_SYS_DISCOVER_PHY
-# define CONFIG_SYS_RX_ETH_BUFFER 8
-# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-
-# define CONFIG_SYS_FEC0_PINMUX 0
-# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
-# define MCFFEC_TOUT_LOOP 50000
-/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
-# ifndef CONFIG_SYS_DISCOVER_PHY
-# define FECDUPLEX FULL
-# define FECSPEED _100BASET
-# else
-# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-# endif
-# endif /* CONFIG_SYS_DISCOVER_PHY */
-#endif
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 80000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
-#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
-
-#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */
-#define CONFIG_BOOTFILE "u-boot.bin"
-#ifdef CONFIG_MCFFEC
-# define CONFIG_NET_RETRY_COUNT 5
-# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
-# define CONFIG_IPADDR 192.162.1.2
-# define CONFIG_NETMASK 255.255.255.0
-# define CONFIG_SERVERIP 192.162.1.1
-# define CONFIG_GATEWAYIP 192.162.1.1
-# define CONFIG_OVERWRITE_ETHADDR_ONCE
-#endif /* FEC_ENET */
-
-#define CONFIG_HOSTNAME M5271EVB
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "loadaddr=10000\0" \
- "uboot=u-boot.bin\0" \
- "load=tftp $loadaddr $uboot\0" \
- "upd=run load; run prog\0" \
- "prog=prot off ffe00000 ffe3ffff;" \
- "era ffe00000 ffe3ffff;" \
- "cp.b $loadaddr ffe00000 $filesize;" \
- "save\0" \
- ""
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00100000
-
-#define CONFIG_SYS_MEMTEST_START 0x400
-#define CONFIG_SYS_MEMTEST_END 0x380000
-
-#define CONFIG_SYS_HZ 1000000
-
-/* Clock configuration
- * The external oscillator is a 25.000 MHz
- * CONFIG_SYS_CLK for ColdFire V2 sets cpu_clk (not bus_clk)
- * bus_clk = (cpu_clk/2) (fixed ratio)
- *
- * If CONFIG_SYS_CLK is changed. the CONFIG_SYS_MCF_SYNCR must be updated to
- * match the new clock speed. Max cpu_clk is 150 MHz.
- */
-#define CONFIG_SYS_CLK 100000000
-#define CONFIG_SYS_MCF_SYNCR (MCF_SYNCR_MFD_4X | MCF_SYNCR_RFD_DIV1)
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-#define CONFIG_SYS_MBAR 0x40000000 /* Register Base Addrs */
-
-/*
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
-#define CONFIG_SYS_FLASH_BASE 0xffe00000
-
-#ifdef CONFIG_MONITOR_IS_IN_RAM
-#define CONFIG_SYS_MONITOR_BASE 0x20000
-#else
-#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN 0x40000
-#define CONFIG_SYS_MALLOC_LEN (256 << 10)
-#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization ??
- */
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
-
-/* FLASH organization */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
-
-#define CONFIG_SYS_FLASH_CFI 1
-#define CONFIG_FLASH_CFI_DRIVER 1
-#define CONFIG_SYS_FLASH_SIZE 0x200000
-
-/* Cache Configuration */
-#define CONFIG_SYS_CACHELINE_SIZE 16
-
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
-#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
- CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
- CF_CACR_DISD | CF_CACR_INVI | \
- CF_CACR_CEIB | CF_CACR_DCM | \
- CF_CACR_EUSP)
-
-/* Chip Select 0 : Boot Flash */
-#define CONFIG_SYS_CS0_BASE 0xFFE00000
-#define CONFIG_SYS_CS0_MASK 0x001F0001
-#define CONFIG_SYS_CS0_CTRL 0x00001980
-
-/* Chip Select 1 : External SRAM */
-#define CONFIG_SYS_CS1_BASE 0x30000000
-#define CONFIG_SYS_CS1_MASK 0x00070001
-#define CONFIG_SYS_CS1_CTRL 0x00001900
-
-#endif /* _M5271EVB_H */
* details. :-(
*/
#define CONFIG_MPC8272 1
-#else
-#define CONFIG_MPC8260 1
#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
* (easy to change)
*/
-#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_MPC8266ADS 1 /* ...on motorola ADS board */
#define CONFIG_CPM2 1 /* Has a CPM2 */
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg
-#define CONFIG_SYS_FSL_PBL_RCW \
- $(SRCTREE)/board/freescale/corenet_ds/rcw_p2041rdb.cfg
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg
#endif
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
* (easy to change)
*/
-#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
#define CONFIG_PM826 1 /* ...on a PM8260 module */
#define CONFIG_CPM2 1 /* Has a CPM2 */
* (easy to change)
*/
-#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
#define CONFIG_PM828 1 /* ...on a PM828 module */
#define CONFIG_CPM2 1 /* Has a CPM2 */
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_ENV_IS_IN_EEPROM 1 /* use FLASH for environment vars */
-#else
-#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
-#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */
-#endif
/*-----------------------------------------------------------------------
* RTC
#define CONFIG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env vars */
#endif
-/*
- * IPL (Initial Program Loader, integrated inside CPU)
- * Will load first 4k from NAND (SPL) into cache and execute it from there.
- *
- * SPL (Secondary Program Loader)
- * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
- * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
- * controller and the NAND controller so that the special U-Boot image can be
- * loaded from NAND to SDRAM.
- *
- * NUB (NAND U-Boot)
- * This NAND U-Boot (NUB) is a special U-Boot version which can be started
- * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
- *
- * On 440EPx the SPL is copied to SDRAM before the NAND controller is
- * set up. While still running from cache, I experienced problems accessing
- * the NAND controller. sr - 2006-08-25
- */
-#if defined (CONFIG_NAND_U_BOOT)
-#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
-#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
-#define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here */
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */
-#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
-
-/*
- * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
- */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
-
-/*
- * Now the NAND chip has to be defined (no autodetection used!)
- */
-#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
-#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
-#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
-#undef CONFIG_SYS_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
-
-#define CONFIG_SYS_NAND_ECCSIZE 256
-#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_SYS_NAND_OOBSIZE 16
-#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_NAND
-/*
- * For NAND booting the environment is embedded in the U-Boot image. Please take
- * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
- */
-#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#endif
-
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
-#endif
#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
/* 440EPx errata CHIP 11 */
/*
* On Sequoia CS0 and CS3 are switched when configuring for NAND booting
*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_NAND_CS 2 /* NAND chip connected to CSx */
/* Memory Bank 0 (NOR-FLASH) initialization */
/* Memory Bank 2 (NAND-FLASH) initialization */
#define CONFIG_SYS_EBC_PB2AP 0x018003c0
#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
-#else
-#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
-/* Memory Bank 2 (NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x03017200
-#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FLASH_BASE | 0xda000)
-
-/* Memory Bank 0 (NAND-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x018003c0
-#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
-#endif
/* Memory Bank 1 (RESET) initialization */
#define CONFIG_SYS_EBC_PB1AP 0x7f817200 /* 0x03017200 */
*
*****************************************************************************/
-#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_RPXSUPER 1 /* on an Embedded Planet RPX Super Board */
#define CONFIG_CPM2 1 /* Has a CPM2 */
#ifdef CONFIG_MPC8248
#define CPU_ID_STR "MPC8248"
#else
-#define CONFIG_MPC8260
#define CPU_ID_STR "MPC8250"
#endif /* CONFIG_MPC8248 */
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t1040qds/t1040_pbi.cfg
-#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t1040qds/t1040_rcw.cfg
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg
#endif
/* High Level Configuration Options */
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
/* Serial Port - controlled on board with jumper J8
* open - index 2
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+/* Video */
+#define CONFIG_FSL_DIU_FB
+#ifdef CONFIG_FSL_DIU_FB
+#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
+#define CONFIG_VIDEO
+#define CONFIG_CMD_BMP
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+/*
+ * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
+ * disable empty flash sector detection, which is I/O-intensive.
+ */
+#undef CONFIG_SYS_FLASH_EMPTY_INFO
+#endif
+
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
/* I2C bus multiplexer */
#define I2C_MUX_CH_DEFAULT 0x8
+#define I2C_MUX_CH_DIU 0xC
+
+/* LDI/DVI Encoder for display */
+#define CONFIG_SYS_I2C_LDI_ADDR 0x38
+#define CONFIG_SYS_I2C_DVI_ADDR 0x75
/*
* RTC configuration
"bank_intlv=cs0_cs1;" \
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
"netdev=eth0\0" \
+ "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
"tftpflash=tftpboot $loadaddr $uboot && " \
/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD
#define CONFIG_SYS_DDR_RAW_TIMING
/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD
#define CONFIG_SYS_DDR_RAW_TIMING
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t208xqds/t208x_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
#if defined(CONFIG_PPC_T2080)
-#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t208xqds/t2080_rcw.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_rcw.cfg
#elif defined(CONFIG_PPC_T2081)
-#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t208xqds/t2081_rcw.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_rcw.cfg
#endif
#endif
#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
FTIM1_GPCM_TRAD(0x3f))
#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
- FTIM2_GPCM_TCH(0x0) | \
+ FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
#define CONFIG_SYS_CS3_FTIM3 0x0
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * T2080 RDB/PCIe board configuration file
+ */
+
+#ifndef __T2080RDB_H
+#define __T2080RDB_H
+
+#define CONFIG_T2080RDB
+#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
+#define CONFIG_MMC
+#define CONFIG_SPI_FLASH
+#define CONFIG_USB_EHCI
+#define CONFIG_FSL_SATA_V2
+
+/* High Level Configuration Options */
+#define CONFIG_PHYS_64BIT
+#define CONFIG_BOOKE
+#define CONFIG_E500 /* BOOKE e500 family */
+#define CONFIG_E500MC /* BOOKE e500mc family */
+#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
+#define CONFIG_MP /* support multiple processors */
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP 1
+#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_FSL_IFC /* Enable IFC Support */
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+#define CONFIG_ENV_OVERWRITE
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_rcw.cfg
+#endif
+
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+/* Set 1M boot space */
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+ (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xeff40000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
+#endif
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+#endif
+
+#ifdef CONFIG_SYS_NO_FLASH
+#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+#else
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#endif
+
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 10000000
+#define CONFIG_ENV_SPI_MODE 0
+#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
+#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_OFFSET (512 * 1658)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+#define CONFIG_ENV_IS_IN_REMOTE
+#define CONFIG_ENV_ADDR 0xffe20000
+#define CONFIG_ENV_SIZE 0x2000
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE 0x2000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
+#endif
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ 66660000
+#define CONFIG_DDR_CLK_FREQ 133330000
+
+/*
+ * Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
+
+#define CONFIG_SYS_DCSRBAR 0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_FSL_DDR3
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SYS_SPD_BUS_NUM 0
+#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
+#define SPD_EEPROM_ADDRESS1 0x51
+#define SPD_EEPROM_ADDRESS2 0x52
+#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
+#define CTRL_INTLV_PREFERED cacheline
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE 0xe8000000
+#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
+#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
+
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
+
+#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
+ FTIM0_NOR_TEADC(0x5) | \
+ FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
+ FTIM1_NOR_TRAD_NOR(0x1A) |\
+ FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
+ FTIM2_NOR_TCH(0x4) | \
+ FTIM2_NOR_TWPH(0x0E) | \
+ FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3 0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS }
+
+/* CPLD on IFC */
+#define CONFIG_SYS_CPLD_BASE 0xffdf0000
+#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
+#define CONFIG_SYS_CSPR2_EXT (0xf)
+#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
+ | CSPR_PORT_SIZE_8 \
+ | CSPR_MSEL_GPCM \
+ | CSPR_V)
+#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
+#define CONFIG_SYS_CSOR2 0x0
+
+/* CPLD Timing parameters for IFC CS2 */
+#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
+ FTIM0_GPCM_TEADC(0x0e) | \
+ FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
+ FTIM1_GPCM_TRAD(0x1f))
+#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
+ FTIM2_GPCM_TCH(0x0) | \
+ FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS2_FTIM3 0x0
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE 0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
+
+#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
+#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+ | CSPR_MSEL_NAND /* MSEL = NAND */ \
+ | CSPR_V)
+#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
+ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
+ | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
+ | CSOR_NAND_PGS_2K /* Page Size = 2K */\
+ | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
+ | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
+ FTIM0_NAND_TWP(0x18) | \
+ FTIM0_NAND_TWCHT(0x07) | \
+ FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+ FTIM1_NAND_TWBE(0x39) | \
+ FTIM1_NAND_TRR(0x0e) | \
+ FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
+ FTIM2_NAND_TREH(0x0a) | \
+ FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3 0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW 11
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
+#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
+#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
+#define CONFIG_SYS_FSL_I2C_SPEED 100000
+#define CONFIG_SYS_FSL_I2C2_SPEED 100000
+#define CONFIG_SYS_FSL_I2C3_SPEED 100000
+#define CONFIG_SYS_FSL_I2C4_SPEED 100000
+#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
+#define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
+#define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
+#define I2C_MUX_CH_DEFAULT 0x8
+
+
+/*
+ * RapidIO
+ */
+#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
+#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
+#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
+#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
+/*
+ * for slave u-boot IMAGE instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+/*
+ * for slave UCODE and ENV instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
+
+/* slave core release by master*/
+#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
+
+/*
+ * SRIO_PCIE_BOOT - SLAVE
+ */
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+ (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+#endif
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#ifdef CONFIG_SPI_FLASH
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED 10000000
+#define CONFIG_SF_DEFAULT_MODE 0
+#endif
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_PCI /* Enable PCI/PCIE */
+#define CONFIG_PCIE1 /* PCIE controler 1 */
+#define CONFIG_PCIE2 /* PCIE controler 2 */
+#define CONFIG_PCIE3 /* PCIE controler 3 */
+#define CONFIG_PCIE4 /* PCIE controler 4 */
+#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
+#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
+#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
+#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 4, Base address 203000 */
+#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
+#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
+#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
+#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */
+#define CONFIG_NET_MULTI
+#define CONFIG_E1000
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS 18
+#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
+#define CONFIG_SYS_QMAN_NUM_PORTALS 18
+#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+#define CONFIG_SYS_PMAN
+#define CONFIG_SYS_DPAA_DCE
+#define CONFIG_SYS_DPAA_RMAN /* RMan */
+#define CONFIG_SYS_INTERLAKEN
+
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
+#define CONFIG_CORTINA_FW_ADDR 0x120000
+
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 825KB (1650 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680)
+#define CONFIG_CORTINA_FW_ADDR (512 * 1808)
+
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_CORTINA_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+/*
+ * Slave has no ucode locally, it can fetch this from remote. When implementing
+ * in two corenet boards, slave's ucode could be stored in master's memory
+ * space, the address can be mapped from slave TLB->slave LAW->
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
+#define CONFIG_CORTINA_FW_ADDR 0xFFE10000
+#else
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000
+#define CONFIG_CORTINA_FW_ADDR 0xEFE00000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
+#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_CORTINA
+#define CONFIG_PHY_AQ1202
+#define CONFIG_PHY_REALTEK
+#define CONFIG_CORTINA_FW_LENGTH 0x40000
+#define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */
+#define RGMII_PHY2_ADDR 0x02
+#define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */
+#define CORTINA_PHY_ADDR2 0x0d
+#define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */
+#define FM1_10GEC4_PHY_ADDR 0x01
+#endif
+
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_ETHPRIME "FM1@DTSEC3"
+#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * SATA
+ */
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+#define CONFIG_SYS_SATA_MAX_DEVICE 2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
+ * USB
+ */
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+#define CONFIG_HAS_FSL_DR_USB
+#endif
+
+/*
+ * SDHC
+ */
+#ifdef CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * Environment
+ */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_BDI
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH "/opt/nfsroot"
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 1000000
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
+#define __USB_PHY_TYPE utmi
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:" \
+ "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
+ "bank_intlv=auto;" \
+ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+ "netdev=eth0\0" \
+ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot && " \
+ "protect off $ubootaddr +$filesize && " \
+ "erase $ubootaddr +$filesize && " \
+ "cp.b $loadaddr $ubootaddr $filesize && " \
+ "protect on $ubootaddr +$filesize && " \
+ "cmp.b $loadaddr $ubootaddr $filesize\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=t2080rdb/ramdisk.uboot\0" \
+ "fdtaddr=c00000\0" \
+ "fdtfile=t2080rdb/t2080rdb.dtb\0" \
+ "bdev=sda3\0" \
+ "c=ffe\0"
+
+/*
+ * For emulation this causes u-boot to jump to the start of the
+ * proof point app code automatically
+ */
+#define CONFIG_PROOF_POINTS \
+ "setenv bootargs root=/dev/$bdev rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "cpu 1 release 0x29000000 - - -;" \
+ "cpu 2 release 0x29000000 - - -;" \
+ "cpu 3 release 0x29000000 - - -;" \
+ "cpu 4 release 0x29000000 - - -;" \
+ "cpu 5 release 0x29000000 - - -;" \
+ "cpu 6 release 0x29000000 - - -;" \
+ "cpu 7 release 0x29000000 - - -;" \
+ "go 0x29000000"
+
+#define CONFIG_HVBOOT \
+ "setenv bootargs config-addr=0x60000000; " \
+ "bootm 0x01000000 - 0x00f00000"
+
+#define CONFIG_ALU \
+ "setenv bootargs root=/dev/$bdev rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "cpu 1 release 0x01000000 - - -;" \
+ "cpu 2 release 0x01000000 - - -;" \
+ "cpu 3 release 0x01000000 - - -;" \
+ "cpu 4 release 0x01000000 - - -;" \
+ "cpu 5 release 0x01000000 - - -;" \
+ "cpu 6 release 0x01000000 - - -;" \
+ "cpu 7 release 0x01000000 - - -;" \
+ "go 0x01000000"
+
+#define CONFIG_LINUX \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "setenv ramdiskaddr 0x02000000;" \
+ "setenv fdtaddr 0x00c00000;" \
+ "setenv loadaddr 0x1000000;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_HDBOOT \
+ "setenv bootargs root=/dev/$bdev rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_LINUX
+
+#ifdef CONFIG_SECURE_BOOT
+#include <asm/fsl_secure_boot.h>
+#undef CONFIG_CMD_USB
+#endif
+
+#endif /* __T2080RDB_H */
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4qds/t4_pbi.cfg
-#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4qds/t4_rcw.cfg
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_rcw.cfg
#endif
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
#define CONFIG_SYS_TEXT_BASE 0x40000000
-#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
#if 0
#define CONFIG_TQM8260 100 /* ...on a TQM8260 module Rev.100 */
* (easy to change)
*/
-#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
#define CONFIG_MPC8272_FAMILY 1
#define CONFIG_TQM8272 1
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_ZPC1900 1 /* ...on Zephyr ZPC.1900 board */
#define CONFIG_SYS_TEXT_BASE 0xFE000000
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-#else
-#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
-#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */
-#endif
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#else
-/*
- * No NOR-flash on Acadia when NAND-booting. We need to undef the
- * NOR device-tree fixup code as well, since flash_info is not defined
- * in this case.
- */
-#define CONFIG_SYS_NO_FLASH 1
-#undef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
-#endif
-
#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#endif
-/*
- * IPL (Initial Program Loader, integrated inside CPU)
- * Will load first 4k from NAND (SPL) into cache and execute it from there.
- *
- * SPL (Secondary Program Loader)
- * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
- * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
- * controller and the NAND controller so that the special U-Boot image can be
- * loaded from NAND to SDRAM.
- *
- * NUB (NAND U-Boot)
- * This NAND U-Boot (NUB) is a special U-Boot version which can be started
- * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
- *
- * On 440EPx the SPL is copied to SDRAM before the NAND controller is
- * set up. While still running from cache, I experienced problems accessing
- * the NAND controller. sr - 2006-08-25
- */
-#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
-#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
-#define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_DATA_ADDR + (16 << 10)) /* Copy SPL here*/
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */
-#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
-
-/*
- * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
- */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
-
-/*
- * Now the NAND chip has to be defined (no autodetection used!)
- */
-#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
-#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
-#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
-#undef CONFIG_SYS_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
-
-#define CONFIG_SYS_NAND_ECCSIZE 256
-#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_SYS_NAND_OOBSIZE 16
-#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
-
-#ifdef CONFIG_ENV_IS_IN_NAND
-/*
- * For NAND booting the environment is embedded in the U-Boot image. Please take
- * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
- */
-#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#endif
-
/*-----------------------------------------------------------------------
* RAM (CRAM)
*----------------------------------------------------------------------*/
CONFIG_AMCC_DEF_ENV_POWERPC \
CONFIG_AMCC_DEF_ENV_PPC_OLD \
CONFIG_AMCC_DEF_ENV_NOR_UPD \
- CONFIG_AMCC_DEF_ENV_NAND_UPD \
"kernel_addr=fff10000\0" \
"ramdisk_addr=fff20000\0" \
"kozio=bootm ffc60000\0" \
#define CONFIG_CMD_NAND
#define CONFIG_CMD_USB
-/*
- * No NOR on Acadia when NAND-booting
- */
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_IMLS
-#endif
-
/*-----------------------------------------------------------------------
* NAND FLASH
*----------------------------------------------------------------------*/
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*----------------------------------------------------------------------*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_NAND_CS 3
/* Memory Bank 0 (Flash) initialization */
#define CONFIG_SYS_EBC_PB0AP 0x03337200
/* Memory Bank 2 (CRAM) initialization */
#define CONFIG_SYS_EBC_PB2AP 0x030400c0
#define CONFIG_SYS_EBC_PB2CR 0x020bc000
-#else
-#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
-/* Memory Bank 0 (NAND-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x018003c0
-#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
-
-/*
- * When NAND-booting the CRAM EBC setup must be done in sync mode, since the
- * NAND-SPL already initialized the CRAM and EBC to sync mode.
- */
-/* Memory Bank 1 (CRAM) initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x9C0201C0
-#define CONFIG_SYS_EBC_PB1CR 0x000bc000
-
-/* Memory Bank 2 (CRAM) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x9C0201C0
-#define CONFIG_SYS_EBC_PB2CR 0x020bc000
-#endif
/* Memory Bank 4 (CPLD) initialization */
#define CONFIG_SYS_EBC_PB4AP 0x04006000
/* NAND support */
#ifdef CONFIG_NAND
#define CONFIG_CMD_NAND
-#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
#if !defined(CONFIG_SPI_BOOT) && !defined(CONFIG_NOR_BOOT)
#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \
#define CONFIG_SYS_FLASH_BASE (0x08000000)
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+/* Reduce SPL size by removing unlikey targets */
+#undef CONFIG_SPL_SPI_SUPPORT
#ifdef CONFIG_NOR_BOOT
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_NAND
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_NAND_OMAP_ELM
-#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
#define CONFIG_SYS_NAND_BASE (0x08000000) /* phys address CS0 */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_ONFI_DETECTION 1
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_NAND_OMAP_GPMC
-#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
#define CONFIG_ENV_IS_IN_NAND 1
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_NAND_OMAP_GPMC
-#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
#define CONFIG_ENV_IS_IN_NAND 1
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
"cp.b ${fileaddr} " __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
"upd=run load update\0" \
-#define CONFIG_AMCC_DEF_ENV_NAND_UPD \
- "u-boot-nand=" __stringify(CONFIG_HOSTNAME) "/u-boot-nand.bin\0"\
- "nload=tftp 200000 ${u-boot-nand}\0" \
- "nupdate=nand erase 0 100000;nand write 200000 0 100000\0" \
- "nupd=run nload nupdate\0"
-
#endif /* __AMCC_COMMON_H */
#ifndef __AT91RM9200EK_CONFIG_H__
#define __AT91RM9200EK_CONFIG_H__
-#include <asm/sizes.h>
+#include <linux/sizes.h>
/*
* set some initial configurations depending on configure target
#define CONFIG_CMD_PING 1
#define CONFIG_CMD_DHCP 1
#define CONFIG_CMD_NAND 1
+#define CONFIG_CMD_MMC
#define CONFIG_CMD_USB 1
/* SDRAM */
#define DATAFLASH_TCSS (0x1a << 16)
#define DATAFLASH_TCHS (0x1 << 24)
+/* MMC */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#endif
+
+/* FAT */
+#ifdef CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
/* NOR flash, if populated */
#ifdef CONFIG_SYS_USE_NORFLASH
#define CONFIG_SYS_FLASH_CFI 1
* (easy to change)
*/
-#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_ATC 1 /* ...on a ATC board */
#define CONFIG_CPM2 1 /* Has a CPM2 */
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-#else
-#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
-#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */
-#endif
/*-----------------------------------------------------------------------
* FLASH related
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#endif /* CONFIG_ENV_IS_IN_FLASH */
-/*
- * IPL (Initial Program Loader, integrated inside CPU)
- * Will load first 4k from NAND (SPL) into cache and execute it from there.
- *
- * SPL (Secondary Program Loader)
- * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
- * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
- * controller and the NAND controller so that the special U-Boot image can be
- * loaded from NAND to SDRAM.
- *
- * NUB (NAND U-Boot)
- * This NAND U-Boot (NUB) is a special U-Boot version which can be started
- * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
- *
- * On 440EPx the SPL is copied to SDRAM before the NAND controller is
- * set up. While still running from cache, I experienced problems accessing
- * the NAND controller. sr - 2006-08-25
- */
-#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
-#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
-#define CONFIG_SYS_NAND_BOOT_SPL_DST 0x00800000 /* Copy SPL here */
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */
-#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
-
-/*
- * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
- */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
-
-/*
- * Now the NAND chip has to be defined (no autodetection used!)
- */
-#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
-#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
-#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
-#define CONFIG_SYS_NAND_4_ADDR_CYCLE 1 /* Fourth addr used (>32MB) */
-
-#define CONFIG_SYS_NAND_ECCSIZE 256
-#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_SYS_NAND_OOBSIZE 16
-#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
-
-#ifdef CONFIG_ENV_IS_IN_NAND
-/*
- * For NAND booting the environment is embedded in the U-Boot image. Please take
- * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
- */
-#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#endif
-
/*-----------------------------------------------------------------------
* NAND FLASH
*----------------------------------------------------------------------*/
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_ADDR + 2 }
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
-
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_NAND_CS 1
-#else
-#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
-/* Memory Bank 0 (NAND-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x018003c0
-#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
-#endif
/*-----------------------------------------------------------------------
* DDR SDRAM
CONFIG_AMCC_DEF_ENV_POWERPC \
CONFIG_AMCC_DEF_ENV_PPC_OLD \
CONFIG_AMCC_DEF_ENV_NOR_UPD \
- CONFIG_AMCC_DEF_ENV_NAND_UPD \
"kernel_addr=fff00000\0" \
"ramdisk_addr=fff10000\0" \
""
#ifndef __BCM28155_AP_H
#define __BCM28155_AP_H
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#include <asm/arch/sysmap.h>
/* Architecture, CPU, chip, mach, etc */
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_SYS_HUSH_PARSER
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#include "tegra30-common.h"
#define CONFIG_MISC_INIT_R
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 0
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
#define CONFIG_MISC_INIT_R
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 1
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/* define to enable run status via led */
/* #define CONFIG_STATUS_LED */
*/
#define CONFIG_MISC_INIT_R
#define CONFIG_UART_CONSOLE 0
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
#define CONFIG_MISC_INIT_R
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 1
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
*/
#define CONFIG_MISC_INIT_R
#define CONFIG_UART_CONSOLE 0
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
#define CONFIG_MISC_INIT_R
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 0
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
*/
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 0
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/* FLASH/ETHERNET uses the same async bank */
#define SHARED_RESOURCES 1
#define CONFIG_MISC_INIT_R
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 0
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/* Define if want to do post memory test */
#undef CONFIG_POST
*/
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 0
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 1
#define CONFIG_BFIN_SPI_IMG_SIZE 0x50000
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
#define CONFIG_ADI_GPIO2
#define CONFIG_UART_CONSOLE 0
#define CONFIG_BAUDRATE 57600
#define CONFIG_SYS_PROMPT "Acvilon> "
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
* Misc Settings
*/
#define CONFIG_UART_CONSOLE 0
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Run core 1 from L1 SRAM start address when init uboot on core 0
#define CONFIG_BOOTCOMMAND "run nandboot"
#define CONFIG_BOOTDELAY 2
#define CONFIG_LOADADDR 0x2000000
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
/* Timer information */
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
-
+#define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC /* enable 32kHz OSC at bootime */
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_POWER_TPS65217
/*
* Define here the location of the environment variables (FLASH).
*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
#define CONFIG_SYS_NOR_CS 0 /* NOR chip connected to CSx */
#define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */
-#else
-#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
-#define CONFIG_SYS_NOR_CS 3 /* NOR chip connected to CSx */
-#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
-#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */
-#endif
-
-/*
- * IPL (Initial Program Loader, integrated inside CPU)
- * Will load first 4k from NAND (SPL) into cache and execute it from there.
- *
- * SPL (Secondary Program Loader)
- * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
- * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
- * controller and the NAND controller so that the special U-Boot image can be
- * loaded from NAND to SDRAM.
- *
- * NUB (NAND U-Boot)
- * This NAND U-Boot (NUB) is a special U-Boot version which can be started
- * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
- *
- * On 440EPx the SPL is copied to SDRAM before the NAND controller is
- * set up. While still running from cache, I experienced problems accessing
- * the NAND controller. sr - 2006-08-25
- *
- * This is the first official implementation of booting from 2k page sized
- * NAND devices (e.g. Micron 29F2G08AA 256Mbit * 8)
- */
-#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
-#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
-#define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here */
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from */
- /* this addr */
-#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
-
-/*
- * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
- */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) /* Offset to RAM U-Boot image */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (1 << 20) /* Size of RAM U-Boot image */
-
-/*
- * Now the NAND chip has to be defined (no autodetection used!)
- */
-#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) /* NAND chip page size */
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) /* NAND chip block size */
-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE)
- /* NAND chip page count */
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 /* Location of bad block marker*/
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE /* Fifth addr used (<=128MB) */
-
-#define CONFIG_SYS_NAND_ECCSIZE 256
-#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47, \
- 48, 49, 50, 51, 52, 53, 54, 55, \
- 56, 57, 58, 59, 60, 61, 62, 63}
-
-#ifdef CONFIG_ENV_IS_IN_NAND
-/*
- * For NAND booting the environment is embedded in the U-Boot image. Please take
- * look at the file board/amcc/canyonlands/u-boot-nand.lds for details.
- */
-#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#endif
/*-----------------------------------------------------------------------
* FLASH related
/*------------------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------------*/
-#if !defined(CONFIG_NAND_U_BOOT)
#if !defined(CONFIG_ARCHES)
/*
* NAND booting U-Boot version uses a fixed initialization, since the whole
#define CONFIG_SYS_SDRAM0_MMODE 0x00000432
#define CONFIG_SYS_SDRAM0_MEMODE 0x00000004
#endif /* !defined(CONFIG_ARCHES) */
-#endif /* !defined(CONFIG_NAND_U_BOOT) */
#define CONFIG_SYS_MBYTES_SDRAM 512 /* 512MB */
CONFIG_AMCC_DEF_ENV \
CONFIG_AMCC_DEF_ENV_POWERPC \
CONFIG_AMCC_DEF_ENV_NOR_UPD \
- CONFIG_AMCC_DEF_ENV_NAND_UPD \
"kernel_addr=fc000000\0" \
"fdt_addr=fc1e0000\0" \
"ramdisk_addr=fc200000\0" \
* 0xfe00.0000 -> 4.ce00.0000
*/
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
-/* Memory Bank 3 (NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB3AP 0x10055e00
-#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
-
-/* Memory Bank 0 (NAND-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x018003c0
-#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
-#else
/* Memory Bank 0 (NOR-FLASH) initialization */
#define CONFIG_SYS_EBC_PB0AP 0x10055e00
#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
#define CONFIG_SYS_EBC_PB3AP 0x018003c0
#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
#endif
-#endif /*defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
#if !defined(CONFIG_ARCHES)
/* Memory Bank 2 (CPLD) initialization */
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#include "tegra30-common.h"
#define FLASHBOOT_ENV_SETTINGS \
"flashboot=flread 20040000 1000000 300000;" \
"bootm 0x1000000\0"
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
#define CONFIG_UART_CONSOLE 0
#define CONFIG_BOOTCOMMAND "run flashboot"
#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0"
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
"flashboot=flread 20040000 1000000 3c0000;" \
"bootm 0x1000000\0"
#define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024))
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
"flashboot=flread 20040000 1000000 300000;" \
"bootm 0x1000000\0"
#define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024))
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
#define CONFIG_UART_CONSOLE 1
#define CONFIG_BOOTCOMMAND "run flashboot"
#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0"
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
#define CONFIG_ADI_GPIO2
#define CONFIG_UART_CONSOLE 0
#define CONFIG_BOOTCOMMAND "run flashboot"
#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0"
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access nand at */
/* CS0 */
-#define GPMC_NAND_ECC_LP_x8_LAYOUT
-
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
+#define GPMC_NAND_ECC_LP_x8_LAYOUT
+
/* Environment information */
#define CONFIG_BOOTDELAY 3
#define CONFIG_ZERO_BOOTDELAY_CHECK
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
#if defined(CONFIG_P3041DS)
-#define CONFIG_SYS_FSL_PBL_RCW \
- $(SRCTREE)/board/freescale/corenet_ds/rcw_p3041ds.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg
#elif defined(CONFIG_P4080DS)
-#define CONFIG_SYS_FSL_PBL_RCW \
- $(SRCTREE)/board/freescale/corenet_ds/rcw_p4080ds.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg
#elif defined(CONFIG_P5020DS)
-#define CONFIG_SYS_FSL_PBL_RCW \
- $(SRCTREE)/board/freescale/corenet_ds/rcw_p5020ds.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg
#elif defined(CONFIG_P5040DS)
-#define CONFIG_SYS_FSL_PBL_RCW \
- $(SRCTREE)/board/freescale/corenet_ds/rcw_p5040ds.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg
#endif
#endif
#ifndef _CONFIG_CPUAT91_H
#define _CONFIG_CPUAT91_H
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#ifdef CONFIG_RAMBOOT
#define CONFIG_SKIP_LOWLEVEL_INIT
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#include "tegra114-common.h"
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
#define CONFIG_DBAU1X00 1
#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
#define __CONFIG_DEVKIT3250_H__
/* SoC and board defines */
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#include <asm/arch/cpu.h>
/*
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access nand at */
/* CS0 */
-#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
-
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
#define CONFIG_JFFS2_NAND
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access nand at */
/* CS0 */
-#define GPMC_NAND_ECC_LP_x16_LAYOUT
-
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
#if defined(CONFIG_CMD_NET)
*
*****************************************************************************/
-#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_EP8260 11 /* on an Embedded Planet EP8260 Board, Rev. 11 */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_MPC8260
#define CPU_ID_STR "MPC8270"
#define CONFIG_EP82XXM /* Embedded Planet EP82xxM H 1.0 board */
--- /dev/null
+/*
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG EXYNOS5 board.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_SAMSUNG /* in a SAMSUNG core */
+#define CONFIG_S5P /* S5P Family */
+#define CONFIG_EXYNOS4 /* which is in a Exynos4 Family */
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_COMMON
+
+/* Enable fdt support */
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
+/* input clock of PLL: EXYNOS4 boards have 24MHz input clock */
+#define CONFIG_SYS_CLK_FREQ 24000000
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_EDITING
+
+#include <linux/sizes.h>
+
+/* SD/MMC configuration */
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_S5P_SDHCI
+#define CONFIG_SDHCI
+#define CONFIG_MMC_SDMA
+#define CONFIG_MMC_DEFAULT_DEV 0
+
+/* PWM */
+#define CONFIG_PWM
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Command definition*/
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_MISC
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_XIMG
+#undef CONFIG_CMD_CACHE
+#undef CONFIG_CMD_ONENAND
+#undef CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_DFU
+#define CONFIG_CMD_GPT
+#define CONFIG_CMD_PMIC
+#define CONFIG_CMD_SETEXPR
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+/* FAT */
+#define CONFIG_CMD_FAT
+#define CONFIG_FAT_WRITE
+
+/* EXT4 */
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+
+/* USB Composite download gadget - g_dnl */
+#define CONFIG_USBDOWNLOAD_GADGET
+
+/* TIZEN THOR downloader support */
+#define CONFIG_CMD_THOR_DOWNLOAD
+#define CONFIG_THOR_FUNCTION
+
+#define CONFIG_DFU_FUNCTION
+#define CONFIG_DFU_MMC
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M
+#define DFU_DEFAULT_POLL_TIMEOUT 300
+
+/* USB Samsung's IDs */
+#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
+#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
+#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
+#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D
+#define CONFIG_G_DNL_MANUFACTURER "Samsung"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_CMD_PART
+#define CONFIG_PARTITION_UUIDS
+
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_S3C_UDC_OTG
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+#define CONFIG_USB_CABLE_CHECK
+
+#define CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_USB_GADGET_MASS_STORAGE
+
+/* Enable devicetree support */
+#define CONFIG_OF_LIBFDT
+
+#endif /* __CONFIG_H */
#define CONFIG_CMD_SOUND
#ifdef CONFIG_CMD_SOUND
#define CONFIG_SOUND
+#define CONFIG_I2S_SAMSUNG
#define CONFIG_I2S
#define CONFIG_SOUND_MAX98095
#define CONFIG_SOUND_WM8994
*
*****************************************************************************/
-#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_GW8260 1 /* on an GW8260 Board */
#define CONFIG_CPM2 1 /* Has a CPM2 */
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#include "tegra20-common.h"
/* Enable fdt support for Harmony. Flash the image in u-boot-dtb.bin */
/* USB networking support */
#define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_SMSC95XX
#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_MCS7830
+#define CONFIG_USB_ETHER_SMSC95XX
/* General networking support */
#define CONFIG_CMD_NET
#include "mx6_common.h"
#include <asm/arch/imx-regs.h>
#include <asm/imx-common/gpio.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#define CONFIG_MX6
#define CONFIG_DISPLAY_CPUINFO
* (easy to change)
*/
-#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_HYMOD 1 /* ...on a Hymod board */
#define CONFIG_CPM2 1 /* Has a CPM2 */
+++ /dev/null
-/*
- * Configuration settings for the iDMR board
- *
- * Based on MC5272C3, r5200 and M5271EVB board configs
- * (C) Copyright 2006 Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- * (C) Copyright 2006 Lab X Technologies <zachary.landau@labxtechnologies.com>
- * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _IDMR_H
-#define _IDMR_H
-
-
-/*
- * High Level Configuration Options (easy to change)
- */
-
-#define CONFIG_MCF52x2 /* define processor family */
-#define CONFIG_M5271 /* define processor type */
-#define CONFIG_IDMR /* define board type */
-
-#undef CONFIG_WATCHDOG /* disable watchdog */
-
-/*
- * Default environment settings
- */
-#define CONFIG_BOOTCOMMAND "run net_nfs"
-#define CONFIG_BOOTDELAY 5
-#define CONFIG_MCFUART
-#define CONFIG_SYS_UART_PORT (0)
-#define CONFIG_BAUDRATE 19200
-#define CONFIG_ETHADDR 00:06:3b:01:41:55
-#define CONFIG_ETHPRIME
-#define CONFIG_IPADDR 192.168.30.1
-#define CONFIG_SERVERIP 192.168.1.1
-#define CONFIG_ROOTPATH ""
-#define CONFIG_GATEWAYIP 192.168.1.1
-#define CONFIG_NETMASK 255.255.0.0
-#define CONFIG_HOSTNAME idmr
-#define CONFIG_BOOTFILE "/tftpboot/idmr/uImage"
-#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root " \
- "filesystem over NFS; echo"
-
-#define CONFIG_MCFTMR
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):" \
- "$(netmask):$(hostname):$(netdev):off panic=1\0" \
- "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \
- "flash_self=run ramargs addip;bootm $(kernel_addr) " \
- "$(ramdisk_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
- "ethact=FEC\0 " \
- "update=prot off ff800000 ff81ffff; era ff800000 ff81ffff; " \
- "cp.b 200000 ff800000 $(filesize);" \
- "prot on ff800000 ff81ffff\0" \
- "load=tftp 200000 $(u-boot)\0" \
- "u-boot=/tftpboot/idmr/u-boot.bin\0" \
- ""
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_NET
-
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_LOADB
-
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*
- * Configuration for environment, which occupies third sector in flash.
- */
-#ifndef CONFIG_MONITOR_IS_IN_RAM
-#define CONFIG_ENV_ADDR 0xff820000
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_IS_IN_FLASH
-#else /* CONFIG_MONITOR_IS_IN_RAM */
-#define CONFIG_ENV_OFFSET 0x4000
-#define CONFIG_ENV_SECT_SIZE 0x2000
-#define CONFIG_ENV_IS_IN_FLASH
-#endif /* !CONFIG_MONITOR_IS_IN_RAM */
-
-#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00100000
-
-#define CONFIG_SYS_MEMTEST_START 0x400
-#define CONFIG_SYS_MEMTEST_END 0x380000
-
-#define CONFIG_SYS_HZ (50000000 / 64)
-#define CONFIG_SYS_CLK 100000000
-
-#define CONFIG_SYS_MBAR 0x40000000 /* Register Base Addrs */
-
-/*
- * Ethernet
- */
-#define CONFIG_MCFFEC
-#ifdef CONFIG_MCFFEC
-# define CONFIG_MII 1
-# define CONFIG_MII_INIT 1
-# define CONFIG_SYS_DISCOVER_PHY
-# define CONFIG_SYS_RX_ETH_BUFFER 8
-# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-
-# define CONFIG_SYS_FEC0_PINMUX 0
-# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
-# define MCFFEC_TOUT_LOOP 50000
-/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
-# ifndef CONFIG_SYS_DISCOVER_PHY
-# define FECDUPLEX FULL
-# define FECSPEED _100BASET
-# else
-# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-# endif
-# endif /* CONFIG_SYS_DISCOVER_PHY */
-#endif
-
-/*
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
-#define CONFIG_SYS_FLASH_BASE 0xff800000
-
-#ifdef CONFIG_MONITOR_IS_IN_RAM
-#define CONFIG_SYS_MONITOR_BASE 0x20000
-#else /* !CONFIG_MONITOR_IS_IN_RAM */
-#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
-#endif /* CONFIG_MONITOR_IS_IN_RAM */
-
-#define CONFIG_SYS_MONITOR_LEN 0x20000
-#define CONFIG_SYS_MALLOC_LEN (256 << 10)
-#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization ??
- */
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
-
-/* FLASH organization */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
-
-#define CONFIG_SYS_FLASH_SIZE 0x800000
-/*
- * #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
- */
-
-/* Cache Configuration */
-#define CONFIG_SYS_CACHELINE_SIZE 16
-
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
-#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
- CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
- CF_CACR_DISD | CF_CACR_INVI | \
- CF_CACR_CEIB | CF_CACR_DCM | \
- CF_CACR_EUSP)
-
-/* Port configuration */
-#define CONFIG_SYS_FECI2C 0xF0
-
-
-/* Dynamic MTD partition support */
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
-#define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT "nor0=idmr-0"
-
-#define MTDPARTS_DEFAULT "mtdparts=idmr-0:128k(u-boot)," \
- "64k(env)," \
- "640k(kernel)," \
- "2m(rootfs)," \
- "-(user)";
-
-#if defined(CONFIG_CMD_MII)
-#error "MII commands don't work on iDMR board and should not be enabled."
-#endif
-
-#endif /* _IDMR_H */
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_MIPS32 1 /* MIPS 4Kc CPU core */
#define CONFIG_INCA_IP 1 /* on a INCA-IP Board */
#define CONFIG_XWAY_SWAP_BYTES
#define CONFIG_BAUDRATE 115200
#define CONFIG_MISC_INIT_R /* needed for MAC address */
#define CONFIG_UART_CONSOLE 0
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
#undef CONFIG_SHOW_BOOT_PROGRESS
/* Enable this if bootretry required; currently it's disabled */
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-#else
-#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
-#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */
-#endif
/*-----------------------------------------------------------------------
* FLASH related
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#endif /* CONFIG_ENV_IS_IN_FLASH */
-/*
- * IPL (Initial Program Loader, integrated inside CPU)
- * Will load first 4k from NAND (SPL) into cache and execute it from there.
- *
- * SPL (Secondary Program Loader)
- * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
- * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
- * controller and the NAND controller so that the special U-Boot image can be
- * loaded from NAND to SDRAM.
- *
- * NUB (NAND U-Boot)
- * This NAND U-Boot (NUB) is a special U-Boot version which can be started
- * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
- *
- * On 405EX the SPL is copied to SDRAM before the NAND controller is
- * set up. While still running from location 0xfffff000...0xffffffff the
- * NAND controller cannot be accessed since it is attached to CS0 too.
- */
-#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
-#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
-#define CONFIG_SYS_NAND_BOOT_SPL_DST 0x00800000 /* Copy SPL here */
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */
-#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
-
-/*
- * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
- */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
-
-/*
- * Now the NAND chip has to be defined (no autodetection used!)
- */
-#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
-#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
-#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
-#define CONFIG_SYS_NAND_4_ADDR_CYCLE 1 /* Fourth addr used (>32MB) */
-
-#define CONFIG_SYS_NAND_ECCSIZE 256
-#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_SYS_NAND_OOBSIZE 16
-#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
-
-#ifdef CONFIG_ENV_IS_IN_NAND
-/*
- * For NAND booting the environment is embedded in the U-Boot image. Please take
- * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
- */
-#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#endif
-
/*-----------------------------------------------------------------------
* NAND FLASH
*----------------------------------------------------------------------*/
*
* DDR Autocalibration Method_B is the default.
*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */
#undef CONFIG_PPC4xx_DDR_METHOD_A
-#endif
#define CONFIG_SYS_SDRAM0_MB0CF_BASE (( 0 << 20) + CONFIG_SYS_SDRAM_BASE)
CONFIG_AMCC_DEF_ENV_POWERPC \
CONFIG_AMCC_DEF_ENV_PPC_OLD \
CONFIG_AMCC_DEF_ENV_NOR_UPD \
- CONFIG_AMCC_DEF_ENV_NAND_UPD \
"logversion=2\0" \
"kernel_addr=fc000000\0" \
"fdt_addr=fc1e0000\0" \
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SNTP
-/*
- * Don't run the memory POST on the NAND-booting version. It will
- * overwrite part of the U-Boot image which is already loaded from NAND
- * to SDRAM.
- */
-#if defined(CONFIG_NAND_U_BOOT)
-#define CONFIG_SYS_POST_MEMORY_ON 0
-#else
#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY
-#endif
/* POST support */
#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*----------------------------------------------------------------------*/
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
-/* booting from NAND, so NAND chips select has to be on CS 0 */
-#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
-
-/* Memory Bank 1 (NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x05806500
-#define CONFIG_SYS_EBC_PB1CR 0xFC0DA000 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
-
-/* Memory Bank 0 (NAND-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x018003c0
-#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1e000)
-#else
#define CONFIG_SYS_NAND_CS 1 /* NAND chip connected to CSx */
/* Memory Bank 0 (NOR-FLASH) initialization */
/* Memory Bank 1 (NAND-FLASH) initialization */
#define CONFIG_SYS_EBC_PB1AP 0x018003c0
#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_NAND_ADDR | 0x1e000)
-#endif
/* Memory Bank 2 (FPGA) initialization */
#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_ENABLED | \
#define CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/keymile/kmp204x/pbi.cfg
-#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/keymile/kmp204x/rcw_kmp204x.cfg
+#define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg
/* High Level Configuration Options */
#define CONFIG_BOOKE
#define CONFIG_IDENT_STRING "\nKeymile Kirkwood 128M16"
#define CONFIG_HOSTNAME km_kirkwood_128m16
#undef CONFIG_SYS_KWD_CONFIG
-#define CONFIG_SYS_KWD_CONFIG \
- $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
#define CONFIG_KM_DISABLE_PCIE
#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
#endif
#undef CONFIG_SYS_KWD_CONFIG
-#define CONFIG_SYS_KWD_CONFIG \
- $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
#define CONFIG_KM_ENV_IS_IN_SPI_NOR
#define CONFIG_KM_FPGA_CONFIG
#define CONFIG_KM_PIGGY4_88E6352
#define CONFIG_HOSTNAME mgcoge3un
#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
#undef CONFIG_SYS_KWD_CONFIG
-#define CONFIG_SYS_KWD_CONFIG \
- $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-memphis.cfg
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-memphis.cfg
#define CONFIG_KM_BOARD_EXTRA_ENV "waitforne=true\0"
#define CONFIG_PIGGY_MAC_ADRESS_OFFSET 3
#define CONFIG_KM_DISABLE_PCIE
#define CONFIG_IDENT_STRING "\nKeymile COGE5UN"
#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
#undef CONFIG_SYS_KWD_CONFIG
-#define CONFIG_SYS_KWD_CONFIG \
- $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_256M8_1.cfg
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_256M8_1.cfg
#define CONFIG_KM_ENV_IS_IN_SPI_NOR
#define CONFIG_PIGGY_MAC_ADRESS_OFFSET 3
#define CONFIG_HOSTNAME kmcoge5un
#define CONFIG_IDENT_STRING "\nKeymile SUV31"
#define CONFIG_HOSTNAME kmsuv31
#undef CONFIG_SYS_KWD_CONFIG
-#define CONFIG_SYS_KWD_CONFIG \
- $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
#define CONFIG_KM_ENV_IS_IN_SPI_NOR
#define CONFIG_KM_FPGA_CONFIG
* from the Network Space v2
*/
#if defined(CONFIG_INETSPACE_V2)
-#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-is2.cfg
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-is2.cfg
#elif defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2)
-#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-ns2l.cfg
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-ns2l.cfg
#endif
/*
*/
#if defined(CONFIG_LSCHLV2)
#define CONFIG_IDENT_STRING " LS-CHLv2"
-#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-lschl.cfg
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lschl.cfg
#define CONFIG_MACH_TYPE 3006
#define CONFIG_SYS_TCLK 166666667 /* 166 MHz */
#elif defined(CONFIG_LSXHL)
#define CONFIG_IDENT_STRING " LS-XHL"
-#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-lsxhl.cfg
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lsxhl.cfg
#define CONFIG_MACH_TYPE 2663
/* CONFIG_SYS_TCLK is 200000000 by default */
#else
#define CONFIG_USB_STORAGE
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_MCS7830
#define CONFIG_USB_ETHER_SMSC95XX
#define CONFIG_MXC_USB_PORT 1
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
#define CONFIG_NAND_OMAP_GPMC
-#define GPMC_NAND_ECC_LP_x16_LAYOUT
#define CONFIG_ENV_IS_IN_NAND
#define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */
* (easy to change)
*/
-#define CONFIG_8260 1
-#define CONFIG_MPC8260 1
#define CONFIG_MUAS3001 1
#define CONFIG_SYS_TEXT_BASE 0xFF000000
#define CONFIG_USB_STORAGE
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_MCS7830
#define CONFIG_USB_ETHER_SMSC95XX
#define CONFIG_MXC_USB_PORT 1
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MX6
#include "mx6_common.h"
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define __CONFIG_H
#include <asm/arch/imx-regs.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#include "mx6_common.h"
#define CONFIG_MX6
#define CONFIG_USB_STORAGE
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_MCS7830
#define CONFIG_USB_ETHER_SMSC95XX
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <asm/sizes.h>
+#include <linux/sizes.h>
/*
There are 2 sets of general I/O -->
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_SMSC95XX
#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_MCS7830
+#define CONFIG_USB_ETHER_SMSC95XX
/* GPIO banks */
#define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access nand at */
/* CS0 */
-#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
-
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
#define CONFIG_NAND_OMAP_GPMC
-#define GPMC_NAND_ECC_LP_x16_LAYOUT
#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#elif defined(CONFIG_CMD_ONENAND)
#define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE
#define CONFIG_SHOW_BOOT_PROGRESS
#endif
+/* GPIO banks */
+#define CONFIG_OMAP3_GPIO_3 /* GPIO64 .. 95 is in GPIO bank 3 */
+#define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */
+#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */
+
/* USB */
#define CONFIG_MUSB_UDC 1
#define CONFIG_USB_OMAP3 1
#ifdef CONFIG_NAND
#define PISMO1_NAND_SIZE GPMC_SIZE_128M /* Configure the PISMO */
-#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */
#if defined(CONFIG_CMD_NAND)
#define CONFIG_NAND_OMAP_GPMC
-#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#endif
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access nand */
/* at CS0 */
-#define GPMC_NAND_ECC_LP_x16_LAYOUT
-
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
#define CONFIG_JFFS2_NAND
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access nand */
/* at CS0 */
-#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
-
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
/* TODO: REMOVE THE FOLLOWING
* Retained the following till size.h is removed in u-boot
*/
-#include <asm/sizes.h>
+#include <linux/sizes.h>
/*
* High Level Configuration Options
*/
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access nand at */
/* CS0 */
-#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
-
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
#define CONFIG_JFFS2_NAND
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_ORIGEN_H
+#define __CONFIG_ORIGEN_H
+
+#include <configs/exynos4-dt.h>
+
+#define CONFIG_SYS_PROMPT "ORIGEN # "
+
+#undef CONFIG_DEFAULT_DEVICE_TREE
+#define CONFIG_DEFAULT_DEVICE_TREE exynos4210-origen
/* High Level Configuration Options */
-#define CONFIG_SAMSUNG 1 /* SAMSUNG core */
-#define CONFIG_S5P 1 /* S5P Family */
#define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */
#define CONFIG_ORIGEN 1 /* working with ORIGEN*/
-#include <asm/arch/cpu.h> /* get chip and board defs */
-
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_BOARD_EARLY_INIT_F
-
#define CONFIG_SYS_DCACHE_OFF 1
+/* ORIGEN has 4 bank of DRAM */
+#define CONFIG_NR_DRAM_BANKS 4
#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define CONFIG_SYS_TEXT_BASE 0x43E00000
+#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
-/* input clock of PLL: ORIGEN has 24MHz input clock */
-#define CONFIG_SYS_CLK_FREQ 24000000
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_INITRD_TAG
-#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_TEXT_BASE 0x43E00000
#define CONFIG_MACH_TYPE MACH_TYPE_ORIGEN
-/* Power Down Modes */
-#define S5P_CHECK_SLEEP 0x00000BAD
-#define S5P_CHECK_DIDLE 0xBAD00000
-#define S5P_CHECK_LPA 0xABAD0000
-
/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M))
/* select serial console configuration */
-#define CONFIG_SERIAL2 1 /* use SERIAL 2 */
+#define CONFIG_SERIAL2
#define CONFIG_BAUDRATE 115200
-#define EXYNOS4_DEFAULT_UART_OFFSET 0x020000
-#define CONFIG_SKIP_LOWLEVEL_INIT
+/* Console configuration */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
-/* SD/MMC configuration */
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
-#define CONFIG_SDHCI
-#define CONFIG_S5P_SDHCI
+#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
-/* PWM */
-#define CONFIG_PWM 1
+#define CONFIG_SYS_MONITOR_BASE 0x00000000
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/* Command definition*/
-#include <config_cmd_default.h>
+/* Power Down Modes */
+#define S5P_CHECK_SLEEP 0x00000BAD
+#define S5P_CHECK_DIDLE 0xBAD00000
+#define S5P_CHECK_LPA 0xABAD0000
#undef CONFIG_CMD_PING
#define CONFIG_CMD_ELF
#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_FAT
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_ZERO_BOOTDELAY_CHECK
/* MMC SPL */
#define CONFIG_SPL
#define COPY_BL2_FNPTR_ADDR 0x02020030
-
#define CONFIG_SPL_TEXT_BASE 0x02021410
#define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000"
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT "ORIGEN # "
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size*/
-#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-/* memtest works on */
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
-
-/* ORIGEN has 4 bank of DRAM */
-#define CONFIG_NR_DRAM_BANKS 4
-#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
-#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
-#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
-
-/* FLASH and environment organization */
-#define CONFIG_SYS_NO_FLASH 1
-#undef CONFIG_CMD_IMLS
#define CONFIG_IDENT_STRING " for ORIGEN"
#define CONFIG_CLK_1000_400_200
/* MIU (Memory Interleaving Unit) */
#define CONFIG_MIU_2BIT_21_7_INTERLEAVED
-#define CONFIG_ENV_IS_IN_MMC 1
+#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
#define RESERVE_BLOCK_SIZE (512)
#define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
#define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE)
-#define CONFIG_DOS_PARTITION 1
#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"
#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)
#define BL2_START_OFFSET ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512)
#define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512)
-/* Enable devicetree support */
-#define CONFIG_OF_LIBFDT
-
#endif /* __CONFIG_H */
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#include "tegra20-common.h"
/* Enable fdt support for Paz00. Flash the image in u-boot-dtb.bin */
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
#define CONFIG_PB1X00 1
#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
*
*****************************************************************************/
-#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_PPMC8260 1 /* on an Wind River PPMC8260 Board */
#define CONFIG_CPM2 1 /* Has a CPM2 */
#define CONFIG_BOOTCOMMAND "run nandboot"
#define CONFIG_BOOTDELAY 2
#define CONFIG_LOADADDR 0x2000000
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_MIPS32 /* MIPS32 CPU core */
#define CONFIG_QEMU_MIPS
#define CONFIG_MISC_INIT_R
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_MIPS64 /* MIPS64 CPU core */
#define CONFIG_QEMU_MIPS
#define CONFIG_MISC_INIT_R
CONFIG_AMCC_DEF_ENV \
CONFIG_AMCC_DEF_ENV_POWERPC \
CONFIG_AMCC_DEF_ENV_NOR_UPD \
- CONFIG_AMCC_DEF_ENV_NAND_UPD \
"kernel_addr=fc000000\0" \
"fdt_addr=fc1e0000\0" \
"ramdisk_addr=fc200000\0" \
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/sizes.h>
+#include <linux/sizes.h>
/* Architecture, CPU, etc.*/
#define CONFIG_ARM1176
* (easy to change)
*/
-#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_RSD_PROTO 1 /* on a R&S Protocol Board */
#define CONFIG_CPM2 1 /* Has a CPM2 */
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_UNIVERSAL_H
+#define __CONFIG_UNIVERSAL_H
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */
-#define CONFIG_S5P 1 /* which is in a S5P Family */
-#define CONFIG_EXYNOS4210 1 /* which is in a EXYNOS4210 */
-#define CONFIG_UNIVERSAL 1 /* working with Universal */
-#define CONFIG_TIZEN 1 /* TIZEN lib */
+#include <configs/exynos4-dt.h>
+
+#define CONFIG_SYS_PROMPT "Universal # " /* Monitor Command Prompt */
-#include <asm/arch/cpu.h> /* get chip and board defs */
+#undef CONFIG_DEFAULT_DEVICE_TREE
+#define CONFIG_DEFAULT_DEVICE_TREE exynos4210-universal_c210
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_TIZEN /* TIZEN lib */
/* Keep L2 Cache Disabled */
#define CONFIG_SYS_L2CACHE_OFF 1
+/* Universal has 2 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS 2
#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define CONFIG_SYS_TEXT_BASE 0x44800000
-
-/* input clock of PLL: Universal has 24MHz input clock at EXYNOS4210 */
-#define CONFIG_SYS_CLK_FREQ_C210 24000000
-#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_CLK_FREQ_C210
+#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_BOARD_EARLY_INIT_F
+#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M))
/* select serial console configuration */
-#define CONFIG_SERIAL2 1 /* use SERIAL 2 */
-#define CONFIG_BAUDRATE 115200
-
-/* MMC */
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
-#define CONFIG_SDHCI
-#define CONFIG_S5P_SDHCI
-
-/* PWM */
-#define CONFIG_PWM 1
-
-/* It should define before config_cmd_default.h */
-#define CONFIG_SYS_NO_FLASH 1
-
-/* Command definition */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_MISC
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_XIMG
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_ONENAND
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_FAT
-
-#define CONFIG_BOOTDELAY 1
-#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_SERIAL2
+#define CONFIG_BAUDRATE 115200
+
+/* Console configuration */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+#define CONFIG_BOOTARGS "Please use defined boot"
+#define CONFIG_BOOTCOMMAND "run mmcboot"
+#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
+
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
+ - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
+
+#define CONFIG_SYS_MONITOR_BASE 0x00000000
+
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
+
+#define CONFIG_SYS_TEXT_BASE 0x44800000
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
",100M(swap)"\
",-(UMS)\0"
-#define CONFIG_BOOTARGS "Please use defined boot"
-#define CONFIG_BOOTCOMMAND "run mmcboot"
-#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
-
#define CONFIG_ENV_UBI_MTD " ubi.mtd=${ubiblock} ubi.mtd=4 ubi.mtd=7"
#define CONFIG_BOOTBLOCK "10"
#define CONFIG_UBIBLOCK "9"
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV
+#define CONFIG_ENV_SIZE 4096
+#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */
+
#define CONFIG_ENV_UBIFS_OPTION " rootflags=bulk_read,no_chk_data_crc "
#define CONFIG_ENV_FLASHBOOT CONFIG_ENV_UBI_MTD CONFIG_ENV_UBIFS_OPTION \
"${mtdparts}"
#define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}"
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-
#define CONFIG_ENV_VARS_UBOOT_CONFIG
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
"mmcrootpart=3\0" \
"opts=always_resume=1"
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT "Universal # "
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-/* memtest works on */
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
-
-/* Universal has 2 banks of DRAM */
-#define CONFIG_NR_DRAM_BANKS 2
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* LDDDR2 DMC 0 */
-#define PHYS_SDRAM_1_SIZE (256 << 20) /* 256 MB in CS 0 */
-#define PHYS_SDRAM_2 0x50000000 /* LPDDR2 DMC 1 */
-#define PHYS_SDRAM_2_SIZE (256 << 20) /* 256 MB in CS 0 */
-
-#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
-
-#define CONFIG_SYS_MONITOR_BASE 0x00000000
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-
#define CONFIG_USE_ONENAND_BOARD_INIT
#define CONFIG_SAMSUNG_ONENAND
#define CONFIG_SYS_ONENAND_BASE 0x0C000000
-#define CONFIG_ENV_IS_IN_MMC 1
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_ENV_SIZE 4096
-#define CONFIG_ENV_OFFSET ((32 - 4) << 10)/* 32KiB - 4KiB */
-
-#define CONFIG_DOS_PARTITION 1
-
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
#include <asm/arch/gpio.h>
/*
* I2C Settings
#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_get(1, b, 7)
#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_get(1, b, 6)
+#define CONFIG_CMD_I2C
+
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
#define CONFIG_SYS_I2C_SOFT_SPEED 50000
#define CONFIG_CMD_BMP
#define CONFIG_BMP_16BPP
#define CONFIG_LD9040
-#define CONFIG_EXYNOS_MIPI_DSIM
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
+#define LCD_XRES 480
+#define LCD_YRES 800
+
#endif /* __CONFIG_H */
*
*****************************************************************************/
-#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_SACSng 1 /* munged for the SACSng */
#define CONFIG_CPM2 1 /* Has a CPM2 */
--- /dev/null
+/*
+ * Configuration settings for the SAMA5D3 Xplained board.
+ *
+ * Copyright (C) 2014 Atmel Corporation
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/hardware.h>
+
+#define CONFIG_SYS_TEXT_BASE 0x26f00000
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
+#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_AT91FAMILY
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_OF_LIBFDT /* Device Tree support */
+
+/* general purpose I/O */
+#define CONFIG_AT91_GPIO
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE ATMEL_BASE_DBGU
+#define CONFIG_USART_ID ATMEL_ID_DBGU
+
+/*
+ * This needs to be defined for the OHCI code to work but it is defined as
+ * ATMEL_ID_UHPHS in the CPU specific header files.
+ */
+#define ATMEL_ID_UHP ATMEL_ID_UHPHS
+
+/*
+ * Specify the clock enable bit in the PMC_SCER register.
+ */
+#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
+
+#define CONFIG_BOOTDELAY 3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* No NOR flash */
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_LOADS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
+#define CONFIG_SYS_SDRAM_SIZE 0x10000000
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+
+/* NAND flash */
+#define CONFIG_CMD_NAND
+
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+/* PMECC & PMERRLOC */
+#define CONFIG_ATMEL_NAND_HWECC
+#define CONFIG_ATMEL_NAND_HW_PMECC
+#define CONFIG_PMECC_CAP 4
+#define CONFIG_PMECC_SECTOR_SIZE 512
+#define CONFIG_CMD_NAND_TRIMFFS
+#define CONFIG_CMD_MTDPARTS
+
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#endif
+
+/* Ethernet Hardware */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_MULTI
+#define CONFIG_NET_RETRY_COUNT 20
+#define CONFIG_MACB_SEARCH_PHY
+#define CONFIG_RGMII
+#define CONFIG_CMD_MII
+#define CONFIG_PHYLIB
+
+/* MMC */
+#define CONFIG_CMD_MMC
+
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#define CONFIG_ATMEL_MCI_8BIT
+#endif
+
+/* USB */
+#define CONFIG_CMD_USB
+
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "SAMA5D3 Xplained"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_DOS_PARTITION
+#define CONFIG_USB_STORAGE
+#endif
+
+#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
+#define CONFIG_CMD_FAT
+#define CONFIG_FAT_WRITE
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
+
+#if CONFIG_SYS_USE_NANDFLASH
+/* bootstrap + u-boot + env in nandflash */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET 0xc0000
+#define CONFIG_ENV_OFFSET_REDUND 0x100000
+#define CONFIG_ENV_SIZE 0x20000
+#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0x180000 0x80000;" \
+ "nand read 0x22000000 0x200000 0x600000;" \
+ "bootz 0x22000000 - 0x21000000"
+#elif CONFIG_SYS_USE_MMC
+/* bootstrap + u-boot + env in sd card */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET 0x2000
+#define CONFIG_ENV_SIZE 0x1000
+#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 at91-sama5d3_xplained.dtb; " \
+ "fatload mmc 0:1 0x22000000 zImage; " \
+ "bootz 0x22000000 - 0x21000000"
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#ifdef CONFIG_SYS_USE_MMC
+#define CONFIG_BOOTARGS \
+ "console=ttyS0,115200 earlyprintk " \
+ "root=/dev/mmcblk0p2 rw rootwait"
+#else
+#define CONFIG_BOOTARGS \
+ "console=ttyS0,115200 earlyprintk " \
+ "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \
+ "256K(env),256k(evn_redundent),256k(spare)," \
+ "512k(dtb),6M(kernel)ro,-(rootfs) " \
+ "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs"
+#endif
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_SYS_PROMPT "U-Boot> "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
+
+#endif
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SYS_MONITOR_LEN (512 << 10)
+
#ifdef CONFIG_SYS_USE_MMC
#define CONFIG_SPL_LDSCRIPT arch/arm/cpu/at91-common/u-boot-spl.lds
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
+
+#elif CONFIG_SYS_USE_NANDFLASH
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
+#define CONFIG_SYS_NAND_PAGE_COUNT 64
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
+
+#elif CONFIG_SYS_USE_SERIALFLASH
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS 0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400
+
#endif
#endif
#define CONFIG_BOOTSTAGE
#define CONFIG_BOOTSTAGE_REPORT
+#define CONFIG_DM
+#define CONFIG_CMD_DEMO
+#define CONFIG_CMD_DM
+#define CONFIG_DM_DEMO
+#define CONFIG_DM_DEMO_SIMPLE
+#define CONFIG_DM_DEMO_SHAPE
+#define CONFIG_DM_GPIO
+#define CONFIG_DM_TEST
/* Number of bits in a C 'long' on this architecture */
#define CONFIG_SANDBOX_BITS_PER_LONG 64
#define CONFIG_FIT_SIGNATURE
#define CONFIG_RSA
#define CONFIG_CMD_FDT
+#define CONFIG_DEFAULT_DEVICE_TREE sandbox
#define CONFIG_FS_FAT
#define CONFIG_FS_EXT4
#define CONFIG_CMD_GPIO
#define CONFIG_SANDBOX_GPIO
-#define CONFIG_SANDBOX_GPIO_COUNT 20
+#define CONFIG_SANDBOX_GPIO_COUNT 128
#define CONFIG_CMD_GPT
#define CONFIG_PARTITION_UUIDS
/*
* Size of malloc() pool, although we don't actually use this yet.
*/
-#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */
+#define CONFIG_SYS_MALLOC_LEN (32 << 20) /* 32MB */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_LONGHELP /* #undef to save memory */
#define CONFIG_CMDLINE_EDITING
#define CONFIG_COMMAND_HISTORY
#define CONFIG_AUTO_COMPLETE
+#define CONFIG_BOOTDELAY 3
#define CONFIG_ENV_SIZE 8192
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_CMD_SF_TEST
#define CONFIG_CMD_SPI
#define CONFIG_SPI_FLASH
+#define CONFIG_OF_SPI
+#define CONFIG_OF_SPI_FLASH
#define CONFIG_SPI_FLASH_SANDBOX
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SYS_LOAD_ADDR 0x00000000
#define CONFIG_SYS_MEMTEST_START 0x00100000
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1000)
-#define CONFIG_SYS_FDT_LOAD_ADDR 0x1000000
+#define CONFIG_SYS_FDT_LOAD_ADDR 0x100
+
+#define CONFIG_PHYSMEM
/* Size of our emulated memory */
#define CONFIG_SYS_SDRAM_BASE 0
#define CONFIG_SHA1
#define CONFIG_SHA256
+#define CONFIG_TPM_TIS_SANDBOX
+
#define CONFIG_CMD_SANDBOX
#define CONFIG_BOOTARGS ""
-#define CONFIG_EXTRA_ENV_SETTINGS "stdin=serial\0" \
- "stdout=serial\0" \
- "stderr=serial\0"
+#define CONFIG_CROS_EC
+#define CONFIG_CMD_CROS_EC
+#define CONFIG_CROS_EC_SANDBOX
+#define CONFIG_KEYBOARD
+#define CONFIG_CROS_EC_KEYB
+#define CONFIG_ARCH_EARLY_INIT_R
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SOUND
+#define CONFIG_SOUND_SANDBOX
+#define CONFIG_CMD_SOUND
+
+#define CONFIG_SANDBOX_SDL
+#define CONFIG_LCD
+#define CONFIG_VIDEO_SANDBOX_SDL
+#define CONFIG_CMD_BMP
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define LCD_BPP LCD_COLOR16
+
+#define CONFIG_EXTRA_ENV_SETTINGS "stdin=serial,cros-ec-keyb\0" \
+ "stdout=serial,lcd\0" \
+ "stderr=serial,lcd\0"
#define CONFIG_GZIP_COMPRESSED
#define CONFIG_BZIP2
/* SoC type is defined in boards.cfg */
#include <asm/hardware.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#if defined(CONFIG_SYS_USE_NANDFLASH)
#define CONFIG_ENV_IS_IN_NAND
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/sizes.h>
+#include <linux/sizes.h>
/* LP0 suspend / resume */
#define CONFIG_TEGRA_LP0
/*
* Environment
*/
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
-#define CONFIG_ENV_IS_IN_NAND /* use NAND for environ vars */
-#define CONFIG_ENV_IS_EMBEDDED /* use embedded environment */
-#elif defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_ENV_IS_NOWHERE /* Store env in memory only */
#define CONFIG_ENV_SIZE (8 << 10)
/*
#endif
#endif /* CONFIG_CMD_FLASH */
-/*
- * IPL (Initial Program Loader, integrated inside CPU)
- * Will load first 4k from NAND (SPL) into cache and execute it from there.
- *
- * SPL (Secondary Program Loader)
- * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
- * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
- * controller and the NAND controller so that the special U-Boot image can be
- * loaded from NAND to SDRAM.
- *
- * NUB (NAND U-Boot)
- * This NAND U-Boot (NUB) is a special U-Boot version which can be started
- * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
- *
- * On 440EPx the SPL is copied to SDRAM before the NAND controller is
- * set up. While still running from cache, I experienced problems accessing
- * the NAND controller. sr - 2006-08-25
- */
-#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
-#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
-#define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here */
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from */
- /* this addr */
-#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
-
-/*
- * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
- */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */
-
-/*
- * Now the NAND chip has to be defined (no autodetection used!)
- */
-#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
-#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
-#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
-#undef CONFIG_SYS_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
-
-#define CONFIG_SYS_NAND_ECCSIZE 256
-#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_SYS_NAND_OOBSIZE 16
-#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
-
-#ifdef CONFIG_ENV_IS_IN_NAND
-/*
- * For NAND booting the environment is embedded in the U-Boot image. Please take
- * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
- */
-#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#endif
-
/*
* DDR SDRAM
*/
#define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
- !defined(CONFIG_SYS_RAMBOOT)
+#if !defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
#endif
#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
CONFIG_AMCC_DEF_ENV_POWERPC \
CONFIG_AMCC_DEF_ENV_PPC_OLD \
CONFIG_AMCC_DEF_ENV_NOR_UPD \
- CONFIG_AMCC_DEF_ENV_NAND_UPD \
"kernel_addr=FC000000\0" \
"ramdisk_addr=FC180000\0" \
""
* overwrite part of the U-Boot image which is already loaded from NAND
* to SDRAM.
*/
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_SYS_POST_MEMORY_ON 0
#else
#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY
/*
* On Sequoia CS0 and CS3 are switched when configuring for NAND booting
*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
- !defined(CONFIG_SYS_RAMBOOT)
+#if !defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */
/* Memory Bank 0 (NOR-FLASH) initialization */
#define CONFIG_SYS_EBC_PB0AP 0x03017200
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_NAND_OMAP_ELM
-#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
#define CONFIG_SYS_NAND_BASE (0x08000000) /* physical address */
/* to access nand at */
/* CS0 */
/* SoC type is defined in boards.cfg */
#include <asm/hardware.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#define CONFIG_SYS_TEXT_BASE 0x20000000
* can enable it here if your baseboard features ethernet.
*/
-/* #define CONFIG_MACB */
+#define CONFIG_MACB
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_MCS7830
#ifdef CONFIG_MACB
# define CONFIG_RMII /* use reduced MII inteface */
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
#define CONFIG_NAND_OMAP_GPMC
-#define GPMC_NAND_ECC_LP_x16_LAYOUT
#define CONFIG_ENV_IS_IN_NAND
#define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */
#define CONFIG_UART_CONSOLE 0
#define CONFIG_BOOTCOMMAND "run flashboot"
#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0"
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
"flashboot=flread 20040000 1000000 300000;" \
"bootm 0x1000000\0"
#define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024))
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
#define BOOT_TARGETS_DHCP ""
#endif
+#if defined(CONFIG_CMD_DHCP) && defined(CONFIG_CMD_PXE)
+#define BOOTCMDS_PXE \
+ "bootcmd_pxe=" \
+ BOOTCMD_INIT_USB \
+ "dhcp; " \
+ "if pxe get; then " \
+ "pxe boot; " \
+ "fi\0"
+#define BOOT_TARGETS_PXE "pxe"
+#else
+#define BOOTCMDS_PXE ""
+#define BOOT_TARGETS_PXE ""
+#endif
+
#define BOOTCMDS_COMMON \
"rootpart=1\0" \
\
+ "do_script_boot=" \
+ "load ${devtype} ${devnum}:${rootpart} " \
+ "${scriptaddr} ${prefix}${script}; " \
+ "source ${scriptaddr}\0" \
+ \
"script_boot=" \
- "if load ${devtype} ${devnum}:${rootpart} " \
- "${scriptaddr} ${prefix}${script}; then " \
- "echo ${script} found! Executing ...;" \
- "source ${scriptaddr};" \
- "fi;\0" \
+ "for script in ${boot_scripts}; do " \
+ "if test -e ${devtype} ${devnum}:${rootpart} " \
+ "${prefix}${script}; then " \
+ "echo Found U-Boot script " \
+ "${prefix}${script}; " \
+ "run do_script_boot; " \
+ "echo SCRIPT FAILED: continuing...; " \
+ "fi; " \
+ "done\0" \
+ \
+ "do_sysboot_boot=" \
+ "sysboot ${devtype} ${devnum}:${rootpart} any " \
+ "${scriptaddr} ${prefix}extlinux.conf\0" \
+ \
+ "sysboot_boot=" \
+ "if test -e ${devtype} ${devnum}:${rootpart} " \
+ "${prefix}extlinux.conf; then " \
+ "echo Found extlinux config " \
+ "${prefix}extlinux.conf; " \
+ "run do_sysboot_boot; " \
+ "echo SCRIPT FAILED: continuing...; " \
+ "fi\0" \
\
"scan_boot=" \
"echo Scanning ${devtype} ${devnum}...; " \
"for prefix in ${boot_prefixes}; do " \
- "for script in ${boot_scripts}; do " \
- "run script_boot; " \
- "done; " \
- "done;\0" \
+ "run sysboot_boot; " \
+ "run script_boot; " \
+ "done\0" \
\
"boot_targets=" \
BOOT_TARGETS_MMC " " \
BOOT_TARGETS_USB " " \
+ BOOT_TARGETS_PXE " " \
BOOT_TARGETS_DHCP " " \
"\0" \
\
\
BOOTCMDS_MMC \
BOOTCMDS_USB \
- BOOTCMDS_DHCP
+ BOOTCMDS_DHCP \
+ BOOTCMDS_PXE
#define CONFIG_BOOTCOMMAND \
"set usb_need_init; " \
#ifndef _TEGRA_COMMON_H_
#define _TEGRA_COMMON_H_
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#include <linux/stringify.h>
/*
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_OF_LIBFDT /* enable passing of devicetree */
/* Environment */
#define CONFIG_ENV_VARS_UBOOT_CONFIG
#undef CONFIG_CMD_NET /* network support */
/* turn on command-line edit/hist/auto */
-#define CONFIG_CMDLINE_EDITING
#define CONFIG_COMMAND_HISTORY
-#define CONFIG_AUTO_COMPLETE
/* turn on commonly used storage-related commands */
-
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
#define CONFIG_PARTITION_UUIDS
-#define CONFIG_FS_EXT4
-#define CONFIG_FS_FAT
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
#define CONFIG_CMD_PART
#define CONFIG_SYS_NO_FLASH
#define CONFIG_CONSOLE_MUX
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT V_PROMPT
/*
* Increasing the size of the IO buffer as default nfsargs size is more
#define CONFIG_TEGRA_GPIO
#define CONFIG_CMD_GPIO
#define CONFIG_CMD_ENTERRCM
-#define CONFIG_CMD_BOOTZ
-#define CONFIG_SUPPORT_RAW_INITRD
/* Defines for SPL */
#define CONFIG_SPL
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
+#ifdef CONFIG_SPL_BUILD
+# define CONFIG_USE_PRIVATE_LIBGCC
+#endif
+
#define CONFIG_SYS_GENERIC_BOARD
/* Misc utility code */
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_CRC32_VERIFY
+#ifndef CONFIG_SPL_BUILD
+#include <config_distro_defaults.h>
+#endif
+
#endif /* _TEGRA_COMMON_H_ */
*/
#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
-/*
- * High Level Configuration Options
- */
-#define CONFIG_TEGRA114 /* in a NVidia Tegra114 core */
-
/* Environment information, boards can override if required */
#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */
* scriptaddr can be pretty much anywhere that doesn't conflict with something
* else. Put it above BOOTMAPSZ to eliminate conflicts.
*
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ * something else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
* kernel_addr_r must be within the first 128M of RAM in order for the
* kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
* decompress itself to 0x8000 after the start of RAM, kernel_addr_r
*/
#define MEM_LAYOUT_ENV_SETTINGS \
"scriptaddr=0x90000000\0" \
+ "pxefile_addr_r=0x90100000\0" \
"kernel_addr_r=0x81000000\0" \
"fdt_addr_r=0x82000000\0" \
"ramdisk_addr_r=0x82100000\0"
/* For USB EHCI controller */
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
#endif /* _TEGRA114_COMMON_H_ */
*/
#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
-/*
- * High Level Configuration Options
- */
-#define CONFIG_TEGRA124 /* is an NVIDIA Tegra124 core */
-
/* Environment information, boards can override if required */
#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */
/* For USB EHCI controller */
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
#endif /* _TEGRA124_COMMON_H_ */
*/
#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
-/*
- * High Level Configuration Options
- */
-#define CONFIG_TEGRA20 /* in a NVidia Tegra20 core */
-
/* Environment information, boards can override if required */
#define CONFIG_LOADADDR 0x00408000 /* def. location for kernel */
* scriptaddr can be pretty much anywhere that doesn't conflict with something
* else. Put it above BOOTMAPSZ to eliminate conflicts.
*
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ * something else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
* kernel_addr_r must be within the first 128M of RAM in order for the
* kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
* decompress itself to 0x8000 after the start of RAM, kernel_addr_r
*/
#define MEM_LAYOUT_ENV_SETTINGS \
"scriptaddr=0x10000000\0" \
+ "pxefile_addr_r=0x10100000\0" \
"kernel_addr_r=0x01000000\0" \
"fdt_addr_r=0x02000000\0" \
"ramdisk_addr_r=0x02100000\0"
*/
#define CONFIG_USB_EHCI_TXFIFO_THRESH 10
#define CONFIG_EHCI_IS_TDI
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
/* Total I2C ports on Tegra20 */
#define TEGRA_I2C_NUM_CONTROLLERS 4
*/
#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
-/*
- * High Level Configuration Options
- */
-#define CONFIG_TEGRA30 /* in a NVidia Tegra30 core */
-
/* Environment information, boards can override if required */
#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */
* scriptaddr can be pretty much anywhere that doesn't conflict with something
* else. Put it above BOOTMAPSZ to eliminate conflicts.
*
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ * something else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
* kernel_addr_r must be within the first 128M of RAM in order for the
* kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
* decompress itself to 0x8000 after the start of RAM, kernel_addr_r
*/
#define MEM_LAYOUT_ENV_SETTINGS \
"scriptaddr=0x90000000\0" \
+ "pxefile_addr_r=0x90100000\0" \
"kernel_addr_r=0x81000000\0" \
"fdt_addr_r=0x82000000\0" \
"ramdisk_addr_r=0x82100000\0"
/* For USB EHCI controller */
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
#endif /* _TEGRA30_COMMON_H_ */
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#include <asm/arch/hardware.h>
#include <asm/arch/clock.h>
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_TRATS_H
+#define __CONFIG_TRATS_H
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_SAMSUNG /* in a SAMSUNG core */
-#define CONFIG_S5P /* which is in a S5P Family */
-#define CONFIG_EXYNOS4 /* which is in a EXYNOS4XXX */
-#define CONFIG_EXYNOS4210 /* which is in a EXYNOS4210 */
-#define CONFIG_TRATS /* working with TRATS */
-#define CONFIG_TIZEN /* TIZEN lib */
+#include <configs/exynos4-dt.h>
+
+#define CONFIG_SYS_PROMPT "Trats # " /* Monitor Command Prompt */
+
+#define CONFIG_TRATS
-#include <asm/arch/cpu.h> /* get chip and board defs */
+#undef CONFIG_DEFAULT_DEVICE_TREE
+#define CONFIG_DEFAULT_DEVICE_TREE exynos4210-trats
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_TIZEN /* TIZEN lib */
#define CONFIG_SYS_L2CACHE_OFF
#ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_PL310_BASE 0x10502000
#endif
+/* TRATS has 4 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS 4
#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_TEXT_BASE 0x63300000
+#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
-/* input clock of PLL: TRATS has 24MHz input clock at EXYNOS4210 */
-#define CONFIG_SYS_CLK_FREQ_C210 24000000
-#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_CLK_FREQ_C210
-
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_REVISION_TAG
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_BOARD_EARLY_INIT_F
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
-/* MACH_TYPE_TRATS macro will be removed once added to mach-types */
-#define MACH_TYPE_TRATS 3928
-#define CONFIG_MACH_TYPE MACH_TYPE_TRATS
+#define CONFIG_SYS_TEXT_BASE 0x63300000
-#include <asm/sizes.h>
+#include <linux/sizes.h>
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M))
/* select serial console configuration */
-#define CONFIG_SERIAL2 /* use SERIAL 2 */
+#define CONFIG_SERIAL2
#define CONFIG_BAUDRATE 115200
-/* MMC */
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
-#define CONFIG_S5P_SDHCI
-#define CONFIG_SDHCI
-#define CONFIG_MMC_SDMA
-
-/* PWM */
-#define CONFIG_PWM
-
-/* It should define before config_cmd_default.h */
-#define CONFIG_SYS_NO_FLASH
-
-/* Command definition */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_MISC
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_XIMG
-#undef CONFIG_CMD_CACHE
-#undef CONFIG_CMD_ONENAND
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_DFU
-#define CONFIG_CMD_GPT
-#define CONFIG_CMD_SETEXPR
-
-/* FAT */
-#define CONFIG_CMD_FAT
-#define CONFIG_FAT_WRITE
-
-/* USB Composite download gadget - g_dnl */
-#define CONFIG_USBDOWNLOAD_GADGET
-
-/* TIZEN THOR downloader support */
-#define CONFIG_CMD_THOR_DOWNLOAD
-#define CONFIG_THOR_FUNCTION
-
-#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M
-#define DFU_DEFAULT_POLL_TIMEOUT 300
-#define CONFIG_DFU_FUNCTION
-#define CONFIG_DFU_MMC
-
-/* USB Samsung's IDs */
-#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
-#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
-#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
-#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D
-#define CONFIG_G_DNL_MANUFACTURER "Samsung"
-
-#define CONFIG_BOOTDELAY 1
-#define CONFIG_ZERO_BOOTDELAY_CHECK
+/* Console configuration */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/* MACH_TYPE_TRATS macro will be removed once added to mach-types */
+#define MACH_TYPE_TRATS 3928
+#define CONFIG_MACH_TYPE MACH_TYPE_TRATS
+
#define CONFIG_BOOTARGS "Please use defined boot"
#define CONFIG_BOOTCOMMAND "run mmcboot"
+#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
+
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
+ - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
+
+#define CONFIG_SYS_MONITOR_BASE 0x00000000
-#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
#define CONFIG_BOOTBLOCK "10"
#define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}"
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV
+#define CONFIG_ENV_SIZE 4096
+#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
/* Tizen - partitions definitions */
#define PARTS_CSA "csa-mmc"
-#define PARTS_BOOTLOADER "u-boot"
#define PARTS_BOOT "boot"
+#define PARTS_QBOOT "qboot"
+#define PARTS_CSC "csc"
#define PARTS_ROOT "platform"
#define PARTS_DATA "data"
-#define PARTS_CSC "csc"
#define PARTS_UMS "ums"
#define PARTS_DEFAULT \
"uuid_disk=${uuid_gpt_disk};" \
- "name="PARTS_CSA",size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
- "name="PARTS_BOOTLOADER",size=60MiB," \
- "uuid=${uuid_gpt_"PARTS_BOOTLOADER"};" \
- "name="PARTS_BOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
- "name="PARTS_ROOT",size=1GiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
- "name="PARTS_DATA",size=3GiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
+ "name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
+ "name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
+ "name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \
"name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
+ "name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
+ "name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
"name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
#define CONFIG_DFU_ALT \
"u-boot mmc 80 400;" \
"uImage ext4 0 2;" \
+ "modem.bin ext4 0 2;" \
"exynos4210-trats.dtb ext4 0 2;" \
+ ""PARTS_CSA" part 0 1;" \
""PARTS_BOOT" part 0 2;" \
+ ""PARTS_QBOOT" part 0 3;" \
+ ""PARTS_CSC" part 0 4;" \
""PARTS_ROOT" part 0 5;" \
""PARTS_DATA" part 0 6;" \
""PARTS_UMS" part 0 7;" \
"params.bin mmc 0x38 0x8\0"
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-
-#define CONFIG_ENV_VARS_UBOOT_CONFIG
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootk=" \
"run loaduimage;" \
"setenv spl_addr_tmp;\0" \
"fdtaddr=40800000\0" \
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT "TRATS # "
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-/* memtest works on */
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
-
-/* TRATS has 4 banks of DRAM */
-#define CONFIG_NR_DRAM_BANKS 4
-#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
-#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
-#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
-
-#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
-
-#define CONFIG_SYS_MONITOR_BASE 0x00000000
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-
-#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_ENV_SIZE 4096
-#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */
-
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-
-/* EXT4 */
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
/* Falcon mode definitions */
#define CONFIG_CMD_SPL
-#define CONFIG_SYS_SPL_ARGS_ADDR PHYS_SDRAM_1 + 0x100
+#define CONFIG_SYS_SPL_ARGS_ADDR CONFIG_SYS_SDRAM_BASE + 0x100
-/* GPT */
-#define CONFIG_EFI_PARTITION
-#define CONFIG_PARTITION_UUIDS
+/* I2C */
+#include <asm/arch/gpio.h>
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_CACHELINE_SIZE 32
+#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_S3C24X0
#define CONFIG_SOFT_I2C_READ_REPEATED_START
#define CONFIG_SYS_I2C_INIT_BOARD
-#include <asm/arch/gpio.h>
-
/* I2C FG */
#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_get(2, y4, 1)
#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_get(2, y4, 0)
+/* POWER */
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_MAX8997
#define CONFIG_POWER_MUIC_MAX8997
#define CONFIG_POWER_BATTERY
#define CONFIG_POWER_BATTERY_TRATS
-#define CONFIG_USB_GADGET
-#define CONFIG_USB_GADGET_S3C_UDC_OTG
-#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW 2
-#define CONFIG_USB_CABLE_CHECK
/* Common misc for Samsung */
#define CONFIG_MISC_COMMON
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
-#define CONFIG_CMD_USB_MASS_STORAGE
-#define CONFIG_USB_GADGET_MASS_STORAGE
-
-/* Pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
+#define LCD_XRES 720
+#define LCD_YRES 1280
#endif /* __CONFIG_H */
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_TRATS2_H
+#define __CONFIG_TRATS2_H
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_SAMSUNG /* in a SAMSUNG core */
-#define CONFIG_S5P /* which is in a S5P Family */
-#define CONFIG_EXYNOS4 /* which is in a EXYNOS4XXX */
-#define CONFIG_TIZEN /* TIZEN lib */
+#include <configs/exynos4-dt.h>
-#include <asm/arch/cpu.h> /* get chip and board defs */
-
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_PROMPT "Trats2 # " /* Monitor Command Prompt */
-#define CONFIG_SKIP_LOWLEVEL_INIT
+#undef CONFIG_DEFAULT_DEVICE_TREE
+#define CONFIG_DEFAULT_DEVICE_TREE exynos4412-trats2
-#define CONFIG_SYS_CACHELINE_SIZE 32
+#define CONFIG_TIZEN /* TIZEN lib */
#define CONFIG_SYS_L2CACHE_OFF
#ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_PL310_BASE 0x10502000
#endif
-#define CONFIG_NR_DRAM_BANKS 4
-#define PHYS_SDRAM_1 0x40000000 /* LDDDR2 DMC 0 */
-#define PHYS_SDRAM_1_SIZE (256 << 20) /* 256 MB in CS 0 */
-#define PHYS_SDRAM_2 0x50000000 /* LPDDR2 DMC 1 */
-#define PHYS_SDRAM_2_SIZE (256 << 20) /* 256 MB in CS 0 */
-#define PHYS_SDRAM_3 0x60000000 /* LPDDR2 DMC 1 */
-#define PHYS_SDRAM_3_SIZE (256 << 20) /* 256 MB in CS 0 */
-#define PHYS_SDRAM_4 0x70000000 /* LPDDR2 DMC 1 */
-#define PHYS_SDRAM_4_SIZE (256 << 20) /* 256 MB in CS 0 */
-#define PHYS_SDRAM_END 0x80000000
-
-#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
-
-#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
-#define CONFIG_SYS_TEXT_BASE 0x78100000
-
-#define CONFIG_SYS_CLK_FREQ 24000000
-
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_REVISION_TAG
-
-/* MACH_TYPE_TRATS2 */
-#define MACH_TYPE_TRATS2 3765
-#define CONFIG_MACH_TYPE MACH_TYPE_TRATS2
+/* TRATS2 has 4 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS 4
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
-#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_SYS_TEXT_BASE 0x43e00000
-#include <asm/sizes.h>
+#include <linux/sizes.h>
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M))
/* select serial console configuration */
#define CONFIG_SERIAL2
+#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+/* Console configuration */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_CMDLINE_EDITING
+#define CONFIG_BOOTARGS "Please use defined boot"
+#define CONFIG_BOOTCOMMAND "run mmcboot"
+#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
-#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
+ - GENERATED_GBL_DATA_SIZE)
-/* It should define before config_cmd_default.h */
-#define CONFIG_SYS_NO_FLASH
-
-/***********************************************************
- * Command definition
- ***********************************************************/
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_ECHO
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_NAND
-#undef CONFIG_CMD_MISC
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_SOURCE
-#undef CONFIG_CMD_XIMG
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_DFU
-#define CONFIG_CMD_GPT
-#define CONFIG_CMD_PMIC
-
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
-#define CONFIG_CMD_FAT
-#define CONFIG_FAT_WRITE
-
-/* EXT4 */
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
-
-/* USB Composite download gadget - g_dnl */
-#define CONFIG_USBDOWNLOAD_GADGET
-#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M
-#define DFU_DEFAULT_POLL_TIMEOUT 300
-#define CONFIG_DFU_FUNCTION
-#define CONFIG_DFU_MMC
-
-/* TIZEN THOR downloader support */
-#define CONFIG_CMD_THOR_DOWNLOAD
-#define CONFIG_THOR_FUNCTION
-
-/* USB Samsung's IDs */
-#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
-#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
-#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
-#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D
-#define CONFIG_G_DNL_MANUFACTURER "Samsung"
-
-/* To use the TFTPBOOT over USB, Please enable the CONFIG_CMD_NET */
-#undef CONFIG_CMD_NET
-
-/* MMC */
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
-#define CONFIG_S5P_SDHCI
-#define CONFIG_SDHCI
-#define CONFIG_MMC_SDMA
-#define CONFIG_MMC_DEFAULT_DEV 0
-
-/* PWM */
-#define CONFIG_PWM
-
-#define CONFIG_BOOTARGS "Please use defined boot"
-#define CONFIG_BOOTCOMMAND "run mmcboot"
-#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
+#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
+
+#define CONFIG_SYS_MONITOR_BASE 0x00000000
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV
+#define CONFIG_ENV_SIZE 4096
+#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_ENV_VARS_UBOOT_CONFIG
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
/* Tizen - partitions definitions */
-#define PARTS_CSA "csa"
+#define PARTS_CSA "csa-mmc"
#define PARTS_BOOT "boot"
-#define PARTS_MODEM "modem"
+#define PARTS_QBOOT "qboot"
#define PARTS_CSC "csc"
#define PARTS_ROOT "platform"
#define PARTS_DATA "data"
#define PARTS_DEFAULT \
"uuid_disk=${uuid_gpt_disk};" \
"name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
- "name="PARTS_BOOT",size=64MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
- "name="PARTS_MODEM",size=100MiB,uuid=${uuid_gpt_"PARTS_MODEM"};" \
+ "name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
+ "name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \
"name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
"name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
- "name="PARTS_DATA",size=512MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
+ "name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
"name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
#define CONFIG_DFU_ALT \
"u-boot mmc 80 800;" \
"uImage ext4 0 2;" \
+ "modem.bin ext4 0 2;" \
"exynos4412-trats2.dtb ext4 0 2;" \
+ ""PARTS_CSA" part 0 1;" \
""PARTS_BOOT" part 0 2;" \
+ ""PARTS_QBOOT" part 0 3;" \
+ ""PARTS_CSC" part 0 4;" \
""PARTS_ROOT" part 0 5;" \
""PARTS_DATA" part 0 6;" \
""PARTS_UMS" part 0 7;" \
"setenv spl_addr_tmp;\0" \
"fdtaddr=40800000\0" \
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "Trats2 # " /* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
-
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-/* memtest works on */
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
-
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
- - GENERATED_GBL_DATA_SIZE)
-
-/* valid baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
-#define CONFIG_SYS_MONITOR_BASE 0x00000000
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-
-#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV
-#define CONFIG_ENV_SIZE 4096
-#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */
-#define CONFIG_EFI_PARTITION
-#define CONFIG_PARTITION_UUIDS
-
-#define CONFIG_BOARD_EARLY_INIT_F
-
/* I2C */
#include <asm/arch/gpio.h>
+#define CONFIG_CMD_I2C
+
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_S3C24X0
#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000
#define CONFIG_POWER_MUIC_MAX77693
#define CONFIG_POWER_FG_MAX77693
#define CONFIG_POWER_BATTERY_TRATS2
-#define CONFIG_USB_GADGET
-#define CONFIG_USB_GADGET_S3C_UDC_OTG
-#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW 2
-#define CONFIG_USB_CABLE_CHECK
/* Common misc for Samsung */
#define CONFIG_MISC_COMMON
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
-#define CONFIG_CMD_USB_MASS_STORAGE
-#define CONFIG_USB_GADGET_MASS_STORAGE
-
-/* Pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
+#define LCD_XRES 720
+#define LCD_YRES 1280
#endif /* __CONFIG_H */
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access nand at */
/* CS0 */
-#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
-
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
#define CONFIG_BCH
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#include "tegra20-common.h"
/* Enable fdt support for TrimSlice. Flash the image in u-boot-dtb.bin */
#include "mx6_common.h"
#include <asm/arch/imx-regs.h>
#include <asm/imx-common/gpio.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#define CONFIG_MX6
#define CONFIG_DISPLAY_CPUINFO
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_MIPS32 /* MIPS 4Kc CPU core */
#define CPU_CLOCK_RATE 324000000 /* Clock for the MIPS core */
#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2)
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#include "tegra124-common.h"
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#include "tegra20-common.h"
/* Enable fdt support for Ventana. Flash the image in u-boot-dtb.bin */
#include "mx6_common.h"
#include <asm/arch/imx-regs.h>
#include <asm/imx-common/gpio.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#define CONFIG_MX6
#define CONFIG_DISPLAY_CPUINFO
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#include "tegra20-common.h"
/* Enable fdt support for Whistler. Flash the image in u-boot-dtb.bin */
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_DCACHE_OFF
#undef CONFIG_FPGA
+#undef CONFIG_OF_CONTROL
#endif
/* MMC support */
CROS_EC_IF_SPI,
CROS_EC_IF_I2C,
CROS_EC_IF_LPC, /* Intel Low Pin Count interface */
+ CROS_EC_IF_SANDBOX,
};
/* Our configuration information */
unsigned int bus_num; /* Bus number (for I2C) */
unsigned int max_frequency; /* Maximum interface frequency */
struct fdt_gpio_state ec_int; /* GPIO used as EC interrupt line */
- int cmd_version_is_supported; /* Device supports command versions */
+ int protocol_version; /* Protocol version to use */
int optimise_flash_write; /* Don't write erased flash blocks */
/*
uint8_t data[CROS_EC_KEYSCAN_COLS];
};
+/* Holds information about the Chrome EC */
+struct fdt_cros_ec {
+ struct fmap_entry flash; /* Address and size of EC flash */
+ /*
+ * Byte value of erased flash, or -1 if not known. It is normally
+ * 0xff but some flash devices use 0 (e.g. STM32Lxxx)
+ */
+ int flash_erase_value;
+ struct fmap_entry region[EC_FLASH_REGION_COUNT];
+};
+
/**
* Read the ID of the CROS-EC device
*
};
/**
- * Set up the Chromium OS matrix keyboard protocol
+ * Initialise the Chromium OS EC driver
*
* @param blob Device tree blob containing setup information
* @param cros_ecp Returns pointer to the cros_ec device, or NULL if none
* @param info Place to put the info structure
*/
int cros_ec_info(struct cros_ec_dev *dev,
- struct ec_response_cros_ec_info *info);
+ struct ec_response_mkbp_info *info);
/**
* Read the host event flags
int cros_ec_i2c_init(struct cros_ec_dev *dev, const void *blob);
int cros_ec_spi_init(struct cros_ec_dev *dev, const void *blob);
int cros_ec_lpc_init(struct cros_ec_dev *dev, const void *blob);
+int cros_ec_sandbox_init(struct cros_ec_dev *dev, const void *blob);
/**
* Read information from the fdt for the i2c cros_ec interface
*/
int cros_ec_spi_decode_fdt(struct cros_ec_dev *dev, const void *blob);
+/**
+ * Read information from the fdt for the sandbox cros_ec interface
+ *
+ * @param dev CROS-EC device
+ * @param blob Device tree blob
+ * @return 0 if ok, -1 if we failed to read all required information
+ */
+int cros_ec_sandbox_decode_fdt(struct cros_ec_dev *dev, const void *blob);
+
/**
* Check whether the LPC interface supports new-style commands.
*
* LPC has its own way of doing this, which involves checking LPC values
- * visible to the host. Do this, and update dev->cmd_version_is_supported
- * accordingly.
+ * visible to the host. Do this, and update dev->protocol_version accordingly.
*
* @param dev CROS-EC device to check
*/
const uint8_t *dout, int dout_len,
uint8_t **dinp, int din_len);
+/**
+ * Send a packet to a CROS-EC device and return the response packet.
+ *
+ * Expects the request packet to be stored in dev->dout. Stores the response
+ * packet in dev->din.
+ *
+ * @param dev CROS-EC device
+ * @param out_bytes Size of request packet to output
+ * @param in_bytes Maximum size of response packet to receive
+ * @return number of bytes in response packet, or <0 on error
+ */
+int cros_ec_spi_packet(struct cros_ec_dev *dev, int out_bytes, int in_bytes);
+int cros_ec_sandbox_packet(struct cros_ec_dev *dev, int out_bytes,
+ int in_bytes);
+
/**
* Dump a block of data for a command.
*
* @return 0 if ok, -1 on error
*/
int cros_ec_get_ldo(struct cros_ec_dev *dev, uint8_t index, uint8_t *state);
+
+/**
+ * Initialize the Chrome OS EC at board initialization time.
+ *
+ * @return 0 if ok, -ve on error
+ */
+int cros_ec_board_init(void);
+
+/**
+ * Get access to the error reported when cros_ec_board_init() was called
+ *
+ * This permits delayed reporting of the EC error if it failed during
+ * early init.
+ *
+ * @return error (0 if there was no error, -ve if there was an error)
+ */
+int cros_ec_get_error(void);
+
+/**
+ * Returns information from the FDT about the Chrome EC flash
+ *
+ * @param blob FDT blob to use
+ * @param config Structure to use to return information
+ */
+int cros_ec_decode_ec_flash(const void *blob, struct fdt_cros_ec *config);
+
+/**
+ * Check the current keyboard state, in case recovery mode is requested.
+ * This function is for sandbox only.
+ *
+ * @param ec CROS-EC device
+ */
+void cros_ec_check_keyboard(struct cros_ec_dev *dev);
+
+/*
+ * Tunnel an I2C transfer to the EC
+ *
+ * @param dev CROS-EC device
+ * @param chip Chip address (7-bit I2C address)
+ * @param addr Register address to read/write
+ * @param alen Length of register address in bytes
+ * @param buffer Buffer containing data to read/write
+ * @param len Length of buffer
+ * @param is_read 1 if this is a read, 0 if this is a write
+ */
+int cros_ec_i2c_xfer(struct cros_ec_dev *dev, uchar chip, uint addr,
+ int alen, uchar *buffer, int len, int is_read);
+
#endif
MSG_PROTO_BYTES = MSG_HEADER_BYTES + MSG_TRAILER_BYTES,
/* Max length of messages */
- MSG_BYTES = EC_HOST_PARAM_SIZE + MSG_PROTO_BYTES,
+ MSG_BYTES = EC_PROTO2_MAX_PARAM_SIZE + MSG_PROTO_BYTES,
};
#endif
--- /dev/null
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DM_DEMO_H
+#define __DM_DEMO_H
+
+#include <dm.h>
+
+/**
+ * struct dm_demo_pdata - configuration data for demo instance
+ *
+ * @colour: Color of the demo
+ * @sides: Numbers of sides
+ * @default_char: Default ASCII character to output (65 = 'A')
+ */
+struct dm_demo_pdata {
+ const char *colour;
+ int sides;
+ int default_char;
+};
+
+struct demo_ops {
+ int (*hello)(struct device *dev, int ch);
+ int (*status)(struct device *dev, int *status);
+};
+
+int demo_hello(struct device *dev, int ch);
+int demo_status(struct device *dev, int *status);
+int demo_list(void);
+
+int demo_parse_dt(struct device *dev);
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _DM_H_
+#define _DM_H
+
+#include <dm/device.h>
+#include <dm/platdata.h>
+#include <dm/uclass.h>
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ * Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _DM_DEVICE_INTERNAL_H
+#define _DM_DEVICE_INTERNAL_H
+
+struct device;
+
+/**
+ * device_bind() - Create a device and bind it to a driver
+ *
+ * Called to set up a new device attached to a driver. The device will either
+ * have platdata, or a device tree node which can be used to create the
+ * platdata.
+ *
+ * Once bound a device exists but is not yet active until device_probe() is
+ * called.
+ *
+ * @parent: Pointer to device's parent, under which this driver will exist
+ * @drv: Device's driver
+ * @name: Name of device (e.g. device tree node name)
+ * @platdata: Pointer to data for this device - the structure is device-
+ * specific but may include the device's I/O address, etc.. This is NULL for
+ * devices which use device tree.
+ * @of_offset: Offset of device tree node for this device. This is -1 for
+ * devices which don't use device tree.
+ * @devp: Returns a pointer to the bound device
+ * @return 0 if OK, -ve on error
+ */
+int device_bind(struct device *parent, struct driver *drv,
+ const char *name, void *platdata, int of_offset,
+ struct device **devp);
+
+/**
+ * device_bind_by_name: Create a device and bind it to a driver
+ *
+ * This is a helper function used to bind devices which do not use device
+ * tree.
+ *
+ * @parent: Pointer to device's parent
+ * @info: Name and platdata for this device
+ * @devp: Returns a pointer to the bound device
+ * @return 0 if OK, -ve on error
+ */
+int device_bind_by_name(struct device *parent, const struct driver_info *info,
+ struct device **devp);
+
+/**
+ * device_probe() - Probe a device, activating it
+ *
+ * Activate a device so that it is ready for use. All its parents are probed
+ * first.
+ *
+ * @dev: Pointer to device to probe
+ * @return 0 if OK, -ve on error
+ */
+int device_probe(struct device *dev);
+
+/**
+ * device_remove() - Remove a device, de-activating it
+ *
+ * De-activate a device so that it is no longer ready for use. All its
+ * children are deactivated first.
+ *
+ * @dev: Pointer to device to remove
+ * @return 0 if OK, -ve on error (an error here is normally a very bad thing)
+ */
+int device_remove(struct device *dev);
+
+/**
+ * device_unbind() - Unbind a device, destroying it
+ *
+ * Unbind a device and remove all memory used by it
+ *
+ * @dev: Pointer to device to unbind
+ * @return 0 if OK, -ve on error
+ */
+int device_unbind(struct device *dev);
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ * Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _DM_DEVICE_H
+#define _DM_DEVICE_H
+
+#include <dm/uclass-id.h>
+#include <linker_lists.h>
+#include <linux/list.h>
+
+struct driver_info;
+
+/* Driver is active (probed). Cleared when it is removed */
+#define DM_FLAG_ACTIVATED (1 << 0)
+
+/* DM is responsible for allocating and freeing platdata */
+#define DM_FLAG_ALLOC_PDATA (2 << 0)
+
+/**
+ * struct device - An instance of a driver
+ *
+ * This holds information about a device, which is a driver bound to a
+ * particular port or peripheral (essentially a driver instance).
+ *
+ * A device will come into existence through a 'bind' call, either due to
+ * a U_BOOT_DEVICE() macro (in which case platdata is non-NULL) or a node
+ * in the device tree (in which case of_offset is >= 0). In the latter case
+ * we translate the device tree information into platdata in a function
+ * implemented by the driver ofdata_to_platdata method (called just before the
+ * probe method if the device has a device tree node.
+ *
+ * All three of platdata, priv and uclass_priv can be allocated by the
+ * driver, or you can use the auto_alloc_size members of struct driver and
+ * struct uclass_driver to have driver model do this automatically.
+ *
+ * @driver: The driver used by this device
+ * @name: Name of device, typically the FDT node name
+ * @platdata: Configuration data for this device
+ * @of_offset: Device tree node offset for this device (- for none)
+ * @parent: Parent of this device, or NULL for the top level device
+ * @priv: Private data for this device
+ * @uclass: Pointer to uclass for this device
+ * @uclass_priv: The uclass's private data for this device
+ * @uclass_node: Used by uclass to link its devices
+ * @child_head: List of children of this device
+ * @sibling_node: Next device in list of all devices
+ * @flags: Flags for this device DM_FLAG_...
+ */
+struct device {
+ struct driver *driver;
+ const char *name;
+ void *platdata;
+ int of_offset;
+ struct device *parent;
+ void *priv;
+ struct uclass *uclass;
+ void *uclass_priv;
+ struct list_head uclass_node;
+ struct list_head child_head;
+ struct list_head sibling_node;
+ uint32_t flags;
+};
+
+/* Returns the operations for a device */
+#define device_get_ops(dev) (dev->driver->ops)
+
+/* Returns non-zero if the device is active (probed and not removed) */
+#define device_active(dev) ((dev)->flags & DM_FLAG_ACTIVATED)
+
+/**
+ * struct device_id - Lists the compatible strings supported by a driver
+ * @compatible: Compatible string
+ * @data: Data for this compatible string
+ */
+struct device_id {
+ const char *compatible;
+ ulong data;
+};
+
+/**
+ * struct driver - A driver for a feature or peripheral
+ *
+ * This holds methods for setting up a new device, and also removing it.
+ * The device needs information to set itself up - this is provided either
+ * by platdata or a device tree node (which we find by looking up
+ * matching compatible strings with of_match).
+ *
+ * Drivers all belong to a uclass, representing a class of devices of the
+ * same type. Common elements of the drivers can be implemented in the uclass,
+ * or the uclass can provide a consistent interface to the drivers within
+ * it.
+ *
+ * @name: Device name
+ * @id: Identiies the uclass we belong to
+ * @of_match: List of compatible strings to match, and any identifying data
+ * for each.
+ * @bind: Called to bind a device to its driver
+ * @probe: Called to probe a device, i.e. activate it
+ * @remove: Called to remove a device, i.e. de-activate it
+ * @unbind: Called to unbind a device from its driver
+ * @ofdata_to_platdata: Called before probe to decode device tree data
+ * @priv_auto_alloc_size: If non-zero this is the size of the private data
+ * to be allocated in the device's ->priv pointer. If zero, then the driver
+ * is responsible for allocating any data required.
+ * @platdata_auto_alloc_size: If non-zero this is the size of the
+ * platform data to be allocated in the device's ->platdata pointer.
+ * This is typically only useful for device-tree-aware drivers (those with
+ * an of_match), since drivers which use platdata will have the data
+ * provided in the U_BOOT_DEVICE() instantiation.
+ * ops: Driver-specific operations. This is typically a list of function
+ * pointers defined by the driver, to implement driver functions required by
+ * the uclass.
+ */
+struct driver {
+ char *name;
+ enum uclass_id id;
+ const struct device_id *of_match;
+ int (*bind)(struct device *dev);
+ int (*probe)(struct device *dev);
+ int (*remove)(struct device *dev);
+ int (*unbind)(struct device *dev);
+ int (*ofdata_to_platdata)(struct device *dev);
+ int priv_auto_alloc_size;
+ int platdata_auto_alloc_size;
+ const void *ops; /* driver-specific operations */
+};
+
+/* Declare a new U-Boot driver */
+#define U_BOOT_DRIVER(__name) \
+ ll_entry_declare(struct driver, __name, driver)
+
+/**
+ * dev_get_platdata() - Get the platform data for a device
+ *
+ * This checks that dev is not NULL, but no other checks for now
+ *
+ * @dev Device to check
+ * @return platform data, or NULL if none
+ */
+void *dev_get_platdata(struct device *dev);
+
+/**
+ * dev_get_priv() - Get the private data for a device
+ *
+ * This checks that dev is not NULL, but no other checks for now
+ *
+ * @dev Device to check
+ * @return private data, or NULL if none
+ */
+void *dev_get_priv(struct device *dev);
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _DM_LISTS_H_
+#define _DM_LISTS_H_
+
+#include <dm/uclass-id.h>
+
+/**
+ * lists_driver_lookup_name() - Return u_boot_driver corresponding to name
+ *
+ * This function returns a pointer to a driver given its name. This is used
+ * for binding a driver given its name and platdata.
+ *
+ * @name: Name of driver to look up
+ * @return pointer to driver, or NULL if not found
+ */
+struct driver *lists_driver_lookup_name(const char *name);
+
+/**
+ * lists_uclass_lookup() - Return uclass_driver based on ID of the class
+ * id: ID of the class
+ *
+ * This function returns the pointer to uclass_driver, which is the class's
+ * base structure based on the ID of the class. Returns NULL on error.
+ */
+struct uclass_driver *lists_uclass_lookup(enum uclass_id id);
+
+int lists_bind_drivers(struct device *parent);
+
+int lists_bind_fdt(struct device *parent, const void *blob, int offset);
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ * Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _DM_PLATDATA_H
+#define _DM_PLATDATA_H
+
+struct driver_info {
+ const char *name;
+ const void *platdata;
+};
+
+#define U_BOOT_DEVICE(__name) \
+ ll_entry_declare(struct driver_info, __name, driver_info)
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _DM_ROOT_H_
+#define _DM_ROOT_H_
+
+struct device;
+
+/**
+ * dm_root() - Return pointer to the top of the driver tree
+ *
+ * This function returns pointer to the root node of the driver tree,
+ *
+ * @return pointer to root device, or NULL if not inited yet
+ */
+struct device *dm_root(void);
+
+/**
+ * dm_scan_platdata() - Scan all platform data and bind drivers
+ *
+ * This scans all available platdata and creates drivers for each
+ *
+ * @return 0 if OK, -ve on error
+ */
+int dm_scan_platdata(void);
+
+/**
+ * dm_scan_fdt() - Scan the device tree and bind drivers
+ *
+ * This scans the device tree and creates a driver for each node
+ *
+ * @blob: Pointer to device tree blob
+ * @return 0 if OK, -ve on error
+ */
+int dm_scan_fdt(const void *blob);
+
+/**
+ * dm_init() - Initialize Driver Model structures
+ *
+ * This function will initialize roots of driver tree and class tree.
+ * This needs to be called before anything uses the DM
+ *
+ * @return 0 if OK, -ve on error
+ */
+int dm_init(void);
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2013 Google, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DM_TEST_H
+#define __DM_TEST_H
+
+#include <dm.h>
+
+/**
+ * struct dm_test_cdata - configuration data for test instance
+ *
+ * @ping_add: Amonut to add each time we get a ping
+ * @base: Base address of this device
+ */
+struct dm_test_pdata {
+ int ping_add;
+ uint32_t base;
+};
+
+/**
+ * struct test_ops - Operations supported by the test device
+ *
+ * @ping: Ping operation
+ * @dev: Device to operate on
+ * @pingval: Value to ping the device with
+ * @pingret: Returns resulting value from driver
+ * @return 0 if OK, -ve on error
+ */
+struct test_ops {
+ int (*ping)(struct device *dev, int pingval, int *pingret);
+};
+
+/* Operations that our test driver supports */
+enum {
+ DM_TEST_OP_BIND = 0,
+ DM_TEST_OP_UNBIND,
+ DM_TEST_OP_PROBE,
+ DM_TEST_OP_REMOVE,
+
+ /* For uclass */
+ DM_TEST_OP_POST_BIND,
+ DM_TEST_OP_PRE_UNBIND,
+ DM_TEST_OP_POST_PROBE,
+ DM_TEST_OP_PRE_REMOVE,
+ DM_TEST_OP_INIT,
+ DM_TEST_OP_DESTROY,
+
+ DM_TEST_OP_COUNT,
+};
+
+/* Test driver types */
+enum {
+ DM_TEST_TYPE_FIRST = 0,
+ DM_TEST_TYPE_SECOND,
+};
+
+/* The number added to the ping total on each probe */
+#define DM_TEST_START_TOTAL 5
+
+/**
+ * struct dm_test_priv - private data for the test devices
+ */
+struct dm_test_priv {
+ int ping_total;
+ int op_count[DM_TEST_OP_COUNT];
+};
+
+/**
+ * struct dm_test_perdev_class_priv - private per-device data for test uclass
+ */
+struct dm_test_uclass_perdev_priv {
+ int base_add;
+};
+
+/**
+ * struct dm_test_uclass_priv - private data for test uclass
+ */
+struct dm_test_uclass_priv {
+ int total_add;
+};
+
+/*
+ * Operation counts for the test driver, used to check that each method is
+ * called correctly
+ */
+extern int dm_testdrv_op_count[DM_TEST_OP_COUNT];
+
+extern struct dm_test_state global_test_state;
+
+/*
+ * struct dm_test_state - Entire state of dm test system
+ *
+ * This is often abreviated to dms.
+ *
+ * @root: Root device
+ * @testdev: Test device
+ * @fail_count: Number of tests that failed
+ * @force_fail_alloc: Force all memory allocs to fail
+ * @skip_post_probe: Skip uclass post-probe processing
+ */
+struct dm_test_state {
+ struct device *root;
+ struct device *testdev;
+ int fail_count;
+ int force_fail_alloc;
+ int skip_post_probe;
+};
+
+/* Test flags for each test */
+enum {
+ DM_TESTF_SCAN_PDATA = 1 << 0, /* test needs platform data */
+ DM_TESTF_PROBE_TEST = 1 << 1, /* probe test uclass */
+ DM_TESTF_SCAN_FDT = 1 << 2, /* scan device tree */
+};
+
+/**
+ * struct dm_test - Information about a driver model test
+ *
+ * @name: Name of test
+ * @func: Function to call to perform test
+ * @flags: Flags indicated pre-conditions for test
+ */
+struct dm_test {
+ const char *name;
+ int (*func)(struct dm_test_state *dms);
+ int flags;
+};
+
+/* Declare a new driver model test */
+#define DM_TEST(_name, _flags) \
+ ll_entry_declare(struct dm_test, _name, dm_test) = { \
+ .name = #_name, \
+ .flags = _flags, \
+ .func = _name, \
+ }
+
+/* Declare ping methods for the drivers */
+int test_ping(struct device *dev, int pingval, int *pingret);
+int testfdt_ping(struct device *dev, int pingval, int *pingret);
+
+/**
+ * dm_check_operations() - Check that we can perform ping operations
+ *
+ * This checks that the ping operations work as expected for a device
+ *
+ * @dms: Overall test state
+ * @dev: Device to test
+ * @base: Base address, used to check ping return value
+ * @priv: Pointer to private test information
+ * @return 0 if OK, -ve on error
+ */
+int dm_check_operations(struct dm_test_state *dms, struct device *dev,
+ uint32_t base, struct dm_test_priv *priv);
+
+/**
+ * dm_test_main() - Run all the tests
+ *
+ * This runs all available driver model tests
+ *
+ * @return 0 if OK, -ve on error
+ */
+int dm_test_main(void);
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _DM_UCLASS_ID_H
+#define _DM_UCLASS_ID_H
+
+/* TODO(sjg@chromium.org): this could be compile-time generated */
+enum uclass_id {
+ /* These are used internally by driver model */
+ UCLASS_ROOT = 0,
+ UCLASS_DEMO,
+ UCLASS_TEST,
+ UCLASS_TEST_FDT,
+
+ /* U-Boot uclasses start here */
+ UCLASS_GPIO,
+
+ UCLASS_COUNT,
+ UCLASS_INVALID = -1,
+};
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _DM_UCLASS_INTERNAL_H
+#define _DM_UCLASS_INTERNAL_H
+
+/**
+ * uclass_find_device() - Return n-th child of uclass
+ * @id: Id number of the uclass
+ * @index: Position of the child in uclass's list
+ * #devp: Returns pointer to device, or NULL on error
+ *
+ * The device is not prepared for use - this is an internal function
+ *
+ * @return the uclass pointer of a child at the given index or
+ * return NULL on error.
+ */
+int uclass_find_device(enum uclass_id id, int index, struct device **devp);
+
+/**
+ * uclass_bind_device() - Associate device with a uclass
+ *
+ * Connect the device into uclass's list of devices.
+ *
+ * @dev: Pointer to the device
+ * #return 0 on success, -ve on error
+ */
+int uclass_bind_device(struct device *dev);
+
+/**
+ * uclass_unbind_device() - Deassociate device with a uclass
+ *
+ * Disconnect the device from uclass's list of devices.
+ *
+ * @dev: Pointer to the device
+ * #return 0 on success, -ve on error
+ */
+int uclass_unbind_device(struct device *dev);
+
+/**
+ * uclass_post_probe_device() - Deal with a device that has just been probed
+ *
+ * Perform any post-processing of a probed device that is needed by the
+ * uclass.
+ *
+ * @dev: Pointer to the device
+ * #return 0 on success, -ve on error
+ */
+int uclass_post_probe_device(struct device *dev);
+
+/**
+ * uclass_pre_remove_device() - Handle a device which is about to be removed
+ *
+ * Perform any pre-processing of a device that is about to be removed.
+ *
+ * @dev: Pointer to the device
+ * #return 0 on success, -ve on error
+ */
+int uclass_pre_remove_device(struct device *dev);
+
+/**
+ * uclass_find() - Find uclass by its id
+ *
+ * @id: Id to serach for
+ * @return pointer to uclass, or NULL if not found
+ */
+struct uclass *uclass_find(enum uclass_id key);
+
+/**
+ * uclass_destroy() - Destroy a uclass
+ *
+ * Destroy a uclass and all its devices
+ *
+ * @uc: uclass to destroy
+ * @return 0 on success, -ve on error
+ */
+int uclass_destroy(struct uclass *uc);
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _DM_UCLASS_H
+#define _DM_UCLASS_H
+
+#include <dm/uclass-id.h>
+#include <linux/list.h>
+
+/**
+ * struct uclass - a U-Boot drive class, collecting together similar drivers
+ *
+ * A uclass provides an interface to a particular function, which is
+ * implemented by one or more drivers. Every driver belongs to a uclass even
+ * if it is the only driver in that uclass. An example uclass is GPIO, which
+ * provides the ability to change read inputs, set and clear outputs, etc.
+ * There may be drivers for on-chip SoC GPIO banks, I2C GPIO expanders and
+ * PMIC IO lines, all made available in a unified way through the uclass.
+ *
+ * @priv: Private data for this uclass
+ * @uc_drv: The driver for the uclass itself, not to be confused with a
+ * 'struct driver'
+ * dev_head: List of devices in this uclass (devices are attached to their
+ * uclass when their bind method is called)
+ * @sibling_node: Next uclass in the linked list of uclasses
+ */
+struct uclass {
+ void *priv;
+ struct uclass_driver *uc_drv;
+ struct list_head dev_head;
+ struct list_head sibling_node;
+};
+
+struct device;
+
+/**
+ * struct uclass_driver - Driver for the uclass
+ *
+ * A uclass_driver provides a consistent interface to a set of related
+ * drivers.
+ *
+ * @name: Name of uclass driver
+ * @id: ID number of this uclass
+ * @post_bind: Called after a new device is bound to this uclass
+ * @pre_unbind: Called before a device is unbound from this uclass
+ * @post_probe: Called after a new device is probed
+ * @pre_remove: Called before a device is removed
+ * @init: Called to set up the uclass
+ * @destroy: Called to destroy the uclass
+ * @priv_auto_alloc_size: If non-zero this is the size of the private data
+ * to be allocated in the uclass's ->priv pointer. If zero, then the uclass
+ * driver is responsible for allocating any data required.
+ * @per_device_auto_alloc_size: Each device can hold private data owned
+ * by the uclass. If required this will be automatically allocated if this
+ * value is non-zero.
+ * @ops: Uclass operations, providing the consistent interface to devices
+ * within the uclass.
+ */
+struct uclass_driver {
+ const char *name;
+ enum uclass_id id;
+ int (*post_bind)(struct device *dev);
+ int (*pre_unbind)(struct device *dev);
+ int (*post_probe)(struct device *dev);
+ int (*pre_remove)(struct device *dev);
+ int (*init)(struct uclass *class);
+ int (*destroy)(struct uclass *class);
+ int priv_auto_alloc_size;
+ int per_device_auto_alloc_size;
+ const void *ops;
+};
+
+/* Declare a new uclass_driver */
+#define UCLASS_DRIVER(__name) \
+ ll_entry_declare(struct uclass_driver, __name, uclass)
+
+/**
+ * uclass_get() - Get a uclass based on an ID, creating it if needed
+ *
+ * Every uclass is identified by an ID, a number from 0 to n-1 where n is
+ * the number of uclasses. This function allows looking up a uclass by its
+ * ID.
+ *
+ * @key: ID to look up
+ * @ucp: Returns pointer to uclass (there is only one per ID)
+ * @return 0 if OK, -ve on error
+ */
+int uclass_get(enum uclass_id key, struct uclass **ucp);
+
+/**
+ * uclass_get_device() - Get a uclass device based on an ID and index
+ *
+ * id: ID to look up
+ * @index: Device number within that uclass (0=first)
+ * @ucp: Returns pointer to uclass (there is only one per for each ID)
+ * @return 0 if OK, -ve on error
+ */
+int uclass_get_device(enum uclass_id id, int index, struct device **ucp);
+
+/**
+ * uclass_first_device() - Get the first device in a uclass
+ *
+ * @id: Uclass ID to look up
+ * @devp: Returns pointer to the first device in that uclass, or NULL if none
+ * @return 0 if OK (found or not found), -1 on error
+ */
+int uclass_first_device(enum uclass_id id, struct device **devp);
+
+/**
+ * uclass_next_device() - Get the next device in a uclass
+ *
+ * @devp: On entry, pointer to device to lookup. On exit, returns pointer
+ * to the next device in the same uclass, or NULL if none
+ * @return 0 if OK (found or not found), -1 on error
+ */
+int uclass_next_device(struct device **devp);
+
+/**
+ * uclass_foreach_dev() - Helper function to iteration through devices
+ *
+ * This creates a for() loop which works through the available devices in
+ * a uclass in order from start to end.
+ *
+ * @pos: struct device * to hold the current device. Set to NULL when there
+ * are no more devices.
+ * uc: uclass to scan
+ */
+#define uclass_foreach_dev(pos, uc) \
+ for (pos = list_entry((&(uc)->dev_head)->next, typeof(*pos), \
+ uclass_node); \
+ prefetch(pos->uclass_node.next), \
+ &pos->uclass_node != (&(uc)->dev_head); \
+ pos = list_entry(pos->uclass_node.next, typeof(*pos), \
+ uclass_node))
+
+#endif
--- /dev/null
+/*
+ * Simple unit test library for driver model
+ *
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DM_UT_H
+#define __DM_UT_H
+
+struct dm_test_state;
+
+/**
+ * ut_fail() - Record failure of a unit test
+ *
+ * @dms: Test state
+ * @fname: Filename where the error occured
+ * @line: Line number where the error occured
+ * @func: Function name where the error occured
+ * @cond: The condition that failed
+ */
+void ut_fail(struct dm_test_state *dms, const char *fname, int line,
+ const char *func, const char *cond);
+
+/**
+ * ut_failf() - Record failure of a unit test
+ *
+ * @dms: Test state
+ * @fname: Filename where the error occured
+ * @line: Line number where the error occured
+ * @func: Function name where the error occured
+ * @cond: The condition that failed
+ * @fmt: printf() format string for the error, followed by args
+ */
+void ut_failf(struct dm_test_state *dms, const char *fname, int line,
+ const char *func, const char *cond, const char *fmt, ...)
+ __attribute__ ((format (__printf__, 6, 7)));
+
+
+/* Assert that a condition is non-zero */
+#define ut_assert(cond) \
+ if (!(cond)) { \
+ ut_fail(dms, __FILE__, __LINE__, __func__, #cond); \
+ return -1; \
+ }
+
+/* Assert that a condition is non-zero, with printf() string */
+#define ut_assertf(cond, fmt, args...) \
+ if (!(cond)) { \
+ ut_failf(dms, __FILE__, __LINE__, __func__, #cond, \
+ fmt, ##args); \
+ return -1; \
+ }
+
+/* Assert that two int expressions are equal */
+#define ut_asserteq(expr1, expr2) { \
+ unsigned int val1 = (expr1), val2 = (expr2); \
+ \
+ if (val1 != val2) { \
+ ut_failf(dms, __FILE__, __LINE__, __func__, \
+ #expr1 " == " #expr2, \
+ "Expected %d, got %d", val1, val2); \
+ return -1; \
+ } \
+}
+
+/* Assert that two string expressions are equal */
+#define ut_asserteq_str(expr1, expr2) { \
+ const char *val1 = (expr1), *val2 = (expr2); \
+ \
+ if (strcmp(val1, val2)) { \
+ ut_failf(dms, __FILE__, __LINE__, __func__, \
+ #expr1 " = " #expr2, \
+ "Expected \"%s\", got \"%s\"", val1, val2); \
+ return -1; \
+ } \
+}
+
+/* Assert that two pointers are equal */
+#define ut_asserteq_ptr(expr1, expr2) { \
+ const void *val1 = (expr1), *val2 = (expr2); \
+ \
+ if (val1 != val2) { \
+ ut_failf(dms, __FILE__, __LINE__, __func__, \
+ #expr1 " = " #expr2, \
+ "Expected %p, got %p", val1, val2); \
+ return -1; \
+ } \
+}
+
+/* Assert that an operation succeeds (returns 0) */
+#define ut_assertok(cond) ut_asserteq(0, cond)
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DM_UTIL_H
+
+void dm_warn(const char *fmt, ...);
+
+#ifdef DEBUG
+void dm_dbg(const char *fmt, ...);
+#else
+static inline void dm_dbg(const char *fmt, ...)
+{
+}
+#endif
+
+struct list_head;
+
+/**
+ * list_count_items() - Count number of items in a list
+ *
+ * @param head: Head of list
+ * @return number of items, or 0 if empty
+ */
+int list_count_items(struct list_head *head);
+
+#endif
-/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
#define EC_LPC_ADDR_HOST_CMD 0x204
/* I/O addresses for host command args and params */
-#define EC_LPC_ADDR_HOST_ARGS 0x800
-#define EC_LPC_ADDR_HOST_PARAM 0x804
-#define EC_HOST_PARAM_SIZE 0x0fc /* Size of param area in bytes */
-
-/* I/O addresses for host command params, old interface */
-#define EC_LPC_ADDR_OLD_PARAM 0x880
-#define EC_OLD_PARAM_SIZE 0x080 /* Size of param area in bytes */
+/* Protocol version 2 */
+#define EC_LPC_ADDR_HOST_ARGS 0x800 /* And 0x801, 0x802, 0x803 */
+#define EC_LPC_ADDR_HOST_PARAM 0x804 /* For version 2 params; size is
+ * EC_PROTO2_MAX_PARAM_SIZE */
+/* Protocol version 3 */
+#define EC_LPC_ADDR_HOST_PACKET 0x800 /* Offset of version 3 packet */
+#define EC_LPC_HOST_PACKET_SIZE 0x100 /* Max size of version 3 packet */
+
+/* The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff
+ * and they tell the kernel that so we have to think of it as two parts. */
+#define EC_HOST_CMD_REGION0 0x800
+#define EC_HOST_CMD_REGION1 0x880
+#define EC_HOST_CMD_REGION_SIZE 0x80
/* EC command register bit functions */
#define EC_LPC_CMDR_DATA (1 << 0) /* Data ready for host to read */
#define EC_SWITCH_LID_OPEN 0x01
#define EC_SWITCH_POWER_BUTTON_PRESSED 0x02
#define EC_SWITCH_WRITE_PROTECT_DISABLED 0x04
-/* Recovery requested via keyboard */
-#define EC_SWITCH_KEYBOARD_RECOVERY 0x08
+/* Was recovery requested via keyboard; now unused. */
+#define EC_SWITCH_IGNORE1 0x08
/* Recovery requested via dedicated signal (from servo board) */
#define EC_SWITCH_DEDICATED_RECOVERY 0x10
/* Was fake developer mode switch; now unused. Remove in next refactor. */
/* Host command interface flags */
/* Host command interface supports LPC args (LPC interface only) */
#define EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED 0x01
+/* Host command interface supports version 3 protocol */
+#define EC_HOST_CMD_FLAG_VERSION_3 0x02
/* Wireless switch flags */
#define EC_WIRELESS_SWITCH_WLAN 0x01
#define EC_WIRELESS_SWITCH_BLUETOOTH 0x02
+#define EC_WIRELESS_SWITCH_WWAN 0x04
/*
* This header file is used in coreboot both in C and ACPI code. The ACPI code
EC_RES_UNAVAILABLE = 9, /* No response available */
EC_RES_TIMEOUT = 10, /* We got a timeout */
EC_RES_OVERFLOW = 11, /* Table / data overflow */
+ EC_RES_INVALID_HEADER = 12, /* Header contains invalid data */
+ EC_RES_REQUEST_TRUNCATED = 13, /* Didn't get the entire request */
+ EC_RES_RESPONSE_TOO_BIG = 14 /* Response was too big to handle */
};
/*
*/
#define EC_HOST_ARGS_FLAG_TO_HOST 0x02
+/*****************************************************************************/
+
+/*
+ * Protocol version 2 for I2C and SPI send a request this way:
+ *
+ * 0 EC_CMD_VERSION0 + (command version)
+ * 1 Command number
+ * 2 Length of params = N
+ * 3..N+2 Params, if any
+ * N+3 8-bit checksum of bytes 0..N+2
+ *
+ * The corresponding response is:
+ *
+ * 0 Result code (EC_RES_*)
+ * 1 Length of params = M
+ * 2..M+1 Params, if any
+ * M+2 8-bit checksum of bytes 0..M+1
+ */
+#define EC_PROTO2_REQUEST_HEADER_BYTES 3
+#define EC_PROTO2_REQUEST_TRAILER_BYTES 1
+#define EC_PROTO2_REQUEST_OVERHEAD (EC_PROTO2_REQUEST_HEADER_BYTES + \
+ EC_PROTO2_REQUEST_TRAILER_BYTES)
+
+#define EC_PROTO2_RESPONSE_HEADER_BYTES 2
+#define EC_PROTO2_RESPONSE_TRAILER_BYTES 1
+#define EC_PROTO2_RESPONSE_OVERHEAD (EC_PROTO2_RESPONSE_HEADER_BYTES + \
+ EC_PROTO2_RESPONSE_TRAILER_BYTES)
+
+/* Parameter length was limited by the LPC interface */
+#define EC_PROTO2_MAX_PARAM_SIZE 0xfc
+
+/* Maximum request and response packet sizes for protocol version 2 */
+#define EC_PROTO2_MAX_REQUEST_SIZE (EC_PROTO2_REQUEST_OVERHEAD + \
+ EC_PROTO2_MAX_PARAM_SIZE)
+#define EC_PROTO2_MAX_RESPONSE_SIZE (EC_PROTO2_RESPONSE_OVERHEAD + \
+ EC_PROTO2_MAX_PARAM_SIZE)
+
+/*****************************************************************************/
+
+/*
+ * Value written to legacy command port / prefix byte to indicate protocol
+ * 3+ structs are being used. Usage is bus-dependent.
+ */
+#define EC_COMMAND_PROTOCOL_3 0xda
+
+#define EC_HOST_REQUEST_VERSION 3
+
+/* Version 3 request from host */
+struct ec_host_request {
+ /* Struct version (=3)
+ *
+ * EC will return EC_RES_INVALID_HEADER if it receives a header with a
+ * version it doesn't know how to parse.
+ */
+ uint8_t struct_version;
+
+ /*
+ * Checksum of request and data; sum of all bytes including checksum
+ * should total to 0.
+ */
+ uint8_t checksum;
+
+ /* Command code */
+ uint16_t command;
+
+ /* Command version */
+ uint8_t command_version;
+
+ /* Unused byte in current protocol version; set to 0 */
+ uint8_t reserved;
+
+ /* Length of data which follows this header */
+ uint16_t data_len;
+} __packed;
+
+#define EC_HOST_RESPONSE_VERSION 3
+
+/* Version 3 response from EC */
+struct ec_host_response {
+ /* Struct version (=3) */
+ uint8_t struct_version;
+
+ /*
+ * Checksum of response and data; sum of all bytes including checksum
+ * should total to 0.
+ */
+ uint8_t checksum;
+
+ /* Result code (EC_RES_*) */
+ uint16_t result;
+
+ /* Length of data which follows this header */
+ uint16_t data_len;
+
+ /* Unused bytes in current protocol version; set to 0 */
+ uint16_t reserved;
+} __packed;
+
+/*****************************************************************************/
/*
* Notes on commands:
*
uint32_t flags; /* Mask of enum ec_comms_status */
} __packed;
+/*
+ * Fake a variety of responses, purely for testing purposes.
+ * FIXME: Would be nice to force checksum errors.
+ */
+#define EC_CMD_TEST_PROTOCOL 0x0a
+
+/* Tell the EC what to send back to us. */
+struct ec_params_test_protocol {
+ uint32_t ec_result;
+ uint32_t ret_len;
+ uint8_t buf[32];
+} __packed;
+
+/* Here it comes... */
+struct ec_response_test_protocol {
+ uint8_t buf[32];
+} __packed;
+
+/* Get prococol information */
+#define EC_CMD_GET_PROTOCOL_INFO 0x0b
+
+/* Flags for ec_response_get_protocol_info.flags */
+/* EC_RES_IN_PROGRESS may be returned if a command is slow */
+#define EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED (1 << 0)
+
+struct ec_response_get_protocol_info {
+ /* Fields which exist if at least protocol version 3 supported */
+
+ /* Bitmask of protocol versions supported (1 << n means version n)*/
+ uint32_t protocol_versions;
+
+ /* Maximum request packet size, in bytes */
+ uint16_t max_request_packet_size;
+
+ /* Maximum response packet size, in bytes */
+ uint16_t max_response_packet_size;
+
+ /* Flags; see EC_PROTOCOL_INFO_* */
+ uint32_t flags;
+} __packed;
/*****************************************************************************/
/* Flash commands */
/* Write flash */
#define EC_CMD_FLASH_WRITE 0x12
+#define EC_VER_FLASH_WRITE 1
+
+/* Version 0 of the flash command supported only 64 bytes of data */
+#define EC_FLASH_WRITE_VER0_SIZE 64
struct ec_params_flash_write {
uint32_t offset; /* Byte offset to write */
uint32_t size; /* Size to write in bytes */
- /*
- * Data to write. Could really use EC_PARAM_SIZE - 8, but tidiest to
- * use a power of 2 so writes stay aligned.
- */
- uint8_t data[64];
+ /* Followed by data to write */
} __packed;
/* Erase flash */
enum ec_flash_region {
/* Region which holds read-only EC image */
- EC_FLASH_REGION_RO,
+ EC_FLASH_REGION_RO = 0,
/* Region which holds rewritable EC image */
EC_FLASH_REGION_RW,
/*
* EC_FLASH_REGION_RO)
*/
EC_FLASH_REGION_WP_RO,
+ /* Number of regions */
+ EC_FLASH_REGION_COUNT,
};
struct ec_params_flash_region_info {
LIGHTBAR_NUM_CMDS
};
+/*****************************************************************************/
+/* LED control commands */
+
+#define EC_CMD_LED_CONTROL 0x29
+
+enum ec_led_id {
+ EC_LED_ID_BATTERY_LED = 0,
+ EC_LED_ID_POWER_BUTTON_LED,
+ EC_LED_ID_ADAPTER_LED,
+};
+
+/* LED control flags */
+#define EC_LED_FLAGS_QUERY (1 << 0) /* Query LED capability only */
+#define EC_LED_FLAGS_AUTO (1 << 1) /* Switch LED back to automatic control */
+
+enum ec_led_colors {
+ EC_LED_COLOR_RED = 0,
+ EC_LED_COLOR_GREEN,
+ EC_LED_COLOR_BLUE,
+ EC_LED_COLOR_YELLOW,
+ EC_LED_COLOR_WHITE,
+
+ EC_LED_COLOR_COUNT
+};
+
+struct ec_params_led_control {
+ uint8_t led_id; /* Which LED to control */
+ uint8_t flags; /* Control flags */
+
+ uint8_t brightness[EC_LED_COLOR_COUNT];
+} __packed;
+
+struct ec_response_led_control {
+ /*
+ * Available brightness value range.
+ *
+ * Range 0 means color channel not present.
+ * Range 1 means on/off control.
+ * Other values means the LED is control by PWM.
+ */
+ uint8_t brightness_range[EC_LED_COLOR_COUNT];
+} __packed;
+
/*****************************************************************************/
/* Verified boot commands */
} __packed;
/*****************************************************************************/
-/* CROS_EC - Matrix KeyBoard Protocol */
+/* MKBP - Matrix KeyBoard Protocol */
/*
* Read key state
*
- * Returns raw data for keyboard cols; see ec_response_cros_ec_info.cols for
+ * Returns raw data for keyboard cols; see ec_response_mkbp_info.cols for
* expected response size.
*/
-#define EC_CMD_CROS_EC_STATE 0x60
+#define EC_CMD_MKBP_STATE 0x60
/* Provide information about the matrix : number of rows and columns */
-#define EC_CMD_CROS_EC_INFO 0x61
+#define EC_CMD_MKBP_INFO 0x61
-struct ec_response_cros_ec_info {
+struct ec_response_mkbp_info {
uint32_t rows;
uint32_t cols;
uint8_t switches;
} __packed;
/* Simulate key press */
-#define EC_CMD_CROS_EC_SIMULATE_KEY 0x62
+#define EC_CMD_MKBP_SIMULATE_KEY 0x62
-struct ec_params_cros_ec_simulate_key {
+struct ec_params_mkbp_simulate_key {
uint8_t col;
uint8_t row;
uint8_t pressed;
} __packed;
/* Configure keyboard scanning */
-#define EC_CMD_CROS_EC_SET_CONFIG 0x64
-#define EC_CMD_CROS_EC_GET_CONFIG 0x65
+#define EC_CMD_MKBP_SET_CONFIG 0x64
+#define EC_CMD_MKBP_GET_CONFIG 0x65
/* flags */
-enum cros_ec_config_flags {
- EC_CROS_EC_FLAGS_ENABLE = 1, /* Enable keyboard scanning */
+enum mkbp_config_flags {
+ EC_MKBP_FLAGS_ENABLE = 1, /* Enable keyboard scanning */
};
-enum cros_ec_config_valid {
- EC_CROS_EC_VALID_SCAN_PERIOD = 1 << 0,
- EC_CROS_EC_VALID_POLL_TIMEOUT = 1 << 1,
- EC_CROS_EC_VALID_MIN_POST_SCAN_DELAY = 1 << 3,
- EC_CROS_EC_VALID_OUTPUT_SETTLE = 1 << 4,
- EC_CROS_EC_VALID_DEBOUNCE_DOWN = 1 << 5,
- EC_CROS_EC_VALID_DEBOUNCE_UP = 1 << 6,
- EC_CROS_EC_VALID_FIFO_MAX_DEPTH = 1 << 7,
+enum mkbp_config_valid {
+ EC_MKBP_VALID_SCAN_PERIOD = 1 << 0,
+ EC_MKBP_VALID_POLL_TIMEOUT = 1 << 1,
+ EC_MKBP_VALID_MIN_POST_SCAN_DELAY = 1 << 3,
+ EC_MKBP_VALID_OUTPUT_SETTLE = 1 << 4,
+ EC_MKBP_VALID_DEBOUNCE_DOWN = 1 << 5,
+ EC_MKBP_VALID_DEBOUNCE_UP = 1 << 6,
+ EC_MKBP_VALID_FIFO_MAX_DEPTH = 1 << 7,
};
/* Configuration for our key scanning algorithm */
-struct ec_cros_ec_config {
+struct ec_mkbp_config {
uint32_t valid_mask; /* valid fields */
- uint8_t flags; /* some flags (enum cros_ec_config_flags) */
+ uint8_t flags; /* some flags (enum mkbp_config_flags) */
uint8_t valid_flags; /* which flags are valid */
uint16_t scan_period_us; /* period between start of scans */
/* revert to interrupt mode after no activity for this long */
uint8_t fifo_max_depth;
} __packed;
-struct ec_params_cros_ec_set_config {
- struct ec_cros_ec_config config;
+struct ec_params_mkbp_set_config {
+ struct ec_mkbp_config config;
} __packed;
-struct ec_response_cros_ec_get_config {
- struct ec_cros_ec_config config;
+struct ec_response_mkbp_get_config {
+ struct ec_mkbp_config config;
} __packed;
/* Run the key scan emulation */
#define EC_CMD_I2C_READ 0x94
struct ec_params_i2c_read {
- uint16_t addr;
+ uint16_t addr; /* 8-bit address (7-bit shifted << 1) */
uint8_t read_size; /* Either 8 or 16. */
uint8_t port;
uint8_t offset;
struct ec_params_i2c_write {
uint16_t data;
- uint16_t addr;
+ uint16_t addr; /* 8-bit address (7-bit shifted << 1) */
uint8_t write_size; /* Either 8 or 16. */
uint8_t port;
uint8_t offset;
uint8_t state;
} __packed;
+/*****************************************************************************/
+/* Power info. */
+
+/*
+ * Get power info.
+ */
+#define EC_CMD_POWER_INFO 0x9d
+
+struct ec_response_power_info {
+ uint32_t usb_dev_type;
+ uint16_t voltage_ac;
+ uint16_t voltage_system;
+ uint16_t current_system;
+ uint16_t usb_current_limit;
+} __packed;
+
+/*****************************************************************************/
+/* I2C passthru command */
+
+#define EC_CMD_I2C_PASSTHRU 0x9e
+
+/* Slave address is 10 (not 7) bit */
+#define EC_I2C_FLAG_10BIT (1 << 16)
+
+/* Read data; if not present, message is a write */
+#define EC_I2C_FLAG_READ (1 << 15)
+
+/* Mask for address */
+#define EC_I2C_ADDR_MASK 0x3ff
+
+#define EC_I2C_STATUS_NAK (1 << 0) /* Transfer was not acknowledged */
+#define EC_I2C_STATUS_TIMEOUT (1 << 1) /* Timeout during transfer */
+
+/* Any error */
+#define EC_I2C_STATUS_ERROR (EC_I2C_STATUS_NAK | EC_I2C_STATUS_TIMEOUT)
+
+struct ec_params_i2c_passthru_msg {
+ uint16_t addr_flags; /* I2C slave address (7 or 10 bits) and flags */
+ uint16_t len; /* Number of bytes to read or write */
+} __packed;
+
+struct ec_params_i2c_passthru {
+ uint8_t port; /* I2C port number */
+ uint8_t num_msgs; /* Number of messages */
+ struct ec_params_i2c_passthru_msg msg[];
+ /* Data to write for all messages is concatenated here */
+} __packed;
+
+struct ec_response_i2c_passthru {
+ uint8_t i2c_status; /* Status flags (EC_I2C_STATUS_...) */
+ uint8_t num_msgs; /* Number of messages processed */
+ uint8_t data[]; /* Data read by messages concatenated here */
+} __packed;
+
+
/*****************************************************************************/
/* Temporary debug commands. TODO: remove this crosbug.com/p/13849 */
#define EC_CMD_CHARGE_CURRENT_LIMIT 0xa1
struct ec_params_current_limit {
- uint32_t limit;
+ uint32_t limit; /* in mA */
+} __packed;
+
+/*
+ * Set maximum external power current.
+ */
+#define EC_CMD_EXT_POWER_CURRENT_LIMIT 0xa2
+
+struct ec_params_ext_power_current_limit {
+ uint32_t limit; /* in mA */
} __packed;
/*****************************************************************************/
COMPAT_SAMSUNG_EXYNOS5_USB3_PHY,/* Exynos phy controller for usb3.0 */
COMPAT_SAMSUNG_EXYNOS_TMU, /* Exynos TMU */
COMPAT_SAMSUNG_EXYNOS_FIMD, /* Exynos Display controller */
+ COMPAT_SAMSUNG_EXYNOS_MIPI_DSI, /* Exynos mipi dsi */
COMPAT_SAMSUNG_EXYNOS5_DP, /* Exynos Display port controller */
COMPAT_SAMSUNG_EXYNOS5_DWMMC, /* Exynos5 DWMMC controller */
+ COMPAT_SAMSUNG_EXYNOS_MMC, /* Exynos MMC controller */
COMPAT_SAMSUNG_EXYNOS_SERIAL, /* Exynos UART */
COMPAT_MAXIM_MAX77686_PMIC, /* MAX77686 PMIC */
COMPAT_GENERIC_SPI_FLASH, /* Generic SPI Flash chip */
COMPAT_INFINEON_SLB9635_TPM, /* Infineon SLB9635 TPM */
COMPAT_INFINEON_SLB9645_TPM, /* Infineon SLB9645 TPM */
COMPAT_SAMSUNG_EXYNOS5_I2C, /* Exynos5 High Speed I2C Controller */
+ COMPAT_SANDBOX_HOST_EMULATION, /* Sandbox emulation of a function */
+ COMPAT_SANDBOX_LCD_SDL, /* Sandbox LCD emulation with SDL */
COMPAT_COUNT,
};
*/
int fdtdec_decode_region(const void *blob, int node,
const char *prop_name, void **ptrp, size_t *size);
+
+/* A flash map entry, containing an offset and length */
+struct fmap_entry {
+ uint32_t offset;
+ uint32_t length;
+};
+
+/**
+ * Read a flash entry from the fdt
+ *
+ * @param blob FDT blob
+ * @param node Offset of node to read
+ * @param name Name of node being read
+ * @param entry Place to put offset and size of this node
+ * @return 0 if ok, -ve on error
+ */
+int fdtdec_read_fmap_entry(const void *blob, int node, const char *name,
+ struct fmap_entry *entry);
#endif
#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16)
#define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21)
#define CONFIG_SYS_FSL_USB_SYS_CLK_VALID (1 << 0)
+#define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN (1 << 7)
+#define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK (3 << 4)
+
+#define INC_DCNT_THRESHOLD_25MV (0 << 4)
+#define INC_DCNT_THRESHOLD_50MV (1 << 4)
+#define DEC_DCNT_THRESHOLD_25MV (2 << 4)
+#define DEC_DCNT_THRESHOLD_50MV (3 << 4)
#else
struct ccsr_usb_phy {
- u8 res0[0x18];
+ u32 config1;
+ u32 config2;
+ u32 config3;
+ u32 config4;
+ u32 config5;
+ u32 status1;
u32 usb_enable_override;
u8 res[0xe4];
};
-#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
+#define CONFIG_SYS_FSL_USB_HS_DISCNCT_INC (3 << 22)
+#define CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL (1 << 20)
+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0 13
+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3 16
+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0 0
+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3 3
+#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK 0x07
#endif
#endif /*_ASM_FSL_USB_H_ */
int lcd_dt_simplefb_add_node(void *blob);
int lcd_dt_simplefb_enable_existing_node(void *blob);
+/* Update the LCD / flush the cache */
+void lcd_sync(void);
+
/************************************************************************/
/* ** BITMAP DISPLAY SUPPORT */
/************************************************************************/
--- /dev/null
+/*
+ * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
+ * Rohit Choraria <rohitkc@ti.com>
+ *
+ * (C) Copyright 2013 Andreas Bießmann <andreas.devel@googlemail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __ASM_OMAP_GPMC_H
+#define __ASM_OMAP_GPMC_H
+
+#define GPMC_BUF_EMPTY 0
+#define GPMC_BUF_FULL 1
+
+enum omap_ecc {
+ /* 1-bit ECC calculation by Software, Error detection by Software */
+ OMAP_ECC_HAM1_CODE_SW = 1, /* avoid un-initialized int can be 0x0 */
+ /* 1-bit ECC calculation by GPMC, Error detection by Software */
+ /* ECC layout compatible to legacy ROMCODE. */
+ OMAP_ECC_HAM1_CODE_HW,
+ /* 4-bit ECC calculation by GPMC, Error detection by Software */
+ OMAP_ECC_BCH4_CODE_HW_DETECTION_SW,
+ /* 4-bit ECC calculation by GPMC, Error detection by ELM */
+ OMAP_ECC_BCH4_CODE_HW,
+ /* 8-bit ECC calculation by GPMC, Error detection by Software */
+ OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
+ /* 8-bit ECC calculation by GPMC, Error detection by ELM */
+ OMAP_ECC_BCH8_CODE_HW,
+};
+
+struct gpmc_cs {
+ u32 config1; /* 0x00 */
+ u32 config2; /* 0x04 */
+ u32 config3; /* 0x08 */
+ u32 config4; /* 0x0C */
+ u32 config5; /* 0x10 */
+ u32 config6; /* 0x14 */
+ u32 config7; /* 0x18 */
+ u32 nand_cmd; /* 0x1C */
+ u32 nand_adr; /* 0x20 */
+ u32 nand_dat; /* 0x24 */
+ u8 res[8]; /* blow up to 0x30 byte */
+};
+
+struct bch_res_0_3 {
+ u32 bch_result_x[4];
+};
+
+struct gpmc {
+ u8 res1[0x10];
+ u32 sysconfig; /* 0x10 */
+ u8 res2[0x4];
+ u32 irqstatus; /* 0x18 */
+ u32 irqenable; /* 0x1C */
+ u8 res3[0x20];
+ u32 timeout_control; /* 0x40 */
+ u8 res4[0xC];
+ u32 config; /* 0x50 */
+ u32 status; /* 0x54 */
+ u8 res5[0x8]; /* 0x58 */
+ struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */
+ u8 res6[0x14]; /* 0x1E0 */
+ u32 ecc_config; /* 0x1F4 */
+ u32 ecc_control; /* 0x1F8 */
+ u32 ecc_size_config; /* 0x1FC */
+ u32 ecc1_result; /* 0x200 */
+ u32 ecc2_result; /* 0x204 */
+ u32 ecc3_result; /* 0x208 */
+ u32 ecc4_result; /* 0x20C */
+ u32 ecc5_result; /* 0x210 */
+ u32 ecc6_result; /* 0x214 */
+ u32 ecc7_result; /* 0x218 */
+ u32 ecc8_result; /* 0x21C */
+ u32 ecc9_result; /* 0x220 */
+ u8 res7[12]; /* 0x224 */
+ u32 testmomde_ctrl; /* 0x230 */
+ u8 res8[12]; /* 0x234 */
+ struct bch_res_0_3 bch_result_0_3[2]; /* 0x240 */
+};
+
+/* Used for board specific gpmc initialization */
+extern struct gpmc *gpmc_cfg;
+
+#endif /* __ASM_OMAP_GPMC_H */
--- /dev/null
+/*
+ * include/linux/sizes.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __LINUX_SIZES_H__
+#define __LINUX_SIZES_H__
+
+#define SZ_1 0x00000001
+#define SZ_2 0x00000002
+#define SZ_4 0x00000004
+#define SZ_8 0x00000008
+#define SZ_16 0x00000010
+#define SZ_32 0x00000020
+#define SZ_64 0x00000040
+#define SZ_128 0x00000080
+#define SZ_256 0x00000100
+#define SZ_512 0x00000200
+
+#define SZ_1K 0x00000400
+#define SZ_2K 0x00000800
+#define SZ_4K 0x00001000
+#define SZ_8K 0x00002000
+#define SZ_16K 0x00004000
+#define SZ_32K 0x00008000
+#define SZ_64K 0x00010000
+#define SZ_128K 0x00020000
+#define SZ_256K 0x00040000
+#define SZ_512K 0x00080000
+
+#define SZ_1M 0x00100000
+#define SZ_2M 0x00200000
+#define SZ_4M 0x00400000
+#define SZ_8M 0x00800000
+#define SZ_16M 0x01000000
+#define SZ_32M 0x02000000
+#define SZ_64M 0x04000000
+#define SZ_128M 0x08000000
+#define SZ_256M 0x10000000
+#define SZ_512M 0x20000000
+
+#define SZ_1G 0x40000000
+#define SZ_2G 0x80000000
+
+#endif /* __LINUX_SIZES_H__ */
* at the same time, so do it here. When all drivers are
* converted, this will go away.
*/
+#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_NAND_FSL_ELBC) || defined(CONFIG_NAND_FSL_IFC)
+#define CONFIG_SYS_NAND_SELF_INIT
+#endif
+#else
#if defined(CONFIG_NAND_FSL_ELBC) || defined(CONFIG_NAND_ATMEL)\
|| defined(CONFIG_NAND_FSL_IFC)
#define CONFIG_SYS_NAND_SELF_INIT
#endif
+#endif
extern void nand_init(void);
int armada100_fec_register(unsigned long base_addr);
int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr,
unsigned long dma_addr);
+int xilinx_emaclite_of_init(const void *blob);
int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
int txpp, int rxpp);
int xilinx_ll_temac_eth_init(bd_t *bis, unsigned long base_addr, int flags,
unsigned long ctrl_addr);
+int zynq_gem_of_init(const void *blob);
int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio);
/*
* As long as the Xilinx xps_ll_temac ethernet driver has not its own interface
*/
int os_close(int fd);
+/**
+ * Access to the OS unlink() system call
+ *
+ * \param pathname Path of file to delete
+ * \return 0 for success, other for error
+ */
+int os_unlink(const char *pathname);
+
/**
* Access to the OS exit() system call
*
/**
* Put tty into raw mode to mimic serial console better
+ *
+ * @param fd File descriptor of stdin (normally 0)
+ * @param allow_sigs Allow Ctrl-C, Ctrl-Z to generate signals rather than
+ * be handled by U-Boot
*/
-void os_tty_raw(int fd);
+void os_tty_raw(int fd, bool allow_sigs);
/**
* Acquires some memory from the underlying os.
*/
int os_read_ram_buf(const char *fname);
+/**
+ * Jump to a new executable image
+ *
+ * This uses exec() to run a new executable image, after putting it in a
+ * temporary file. The same arguments and environment are passed to this
+ * new image, with the addition of:
+ *
+ * -j <filename> Specifies the filename the image was written to. The
+ * calling image may want to delete this at some point.
+ * -m <filename> Specifies the file containing the sandbox memory
+ * (ram_buf) from this image, so that the new image can
+ * have access to this. It also means that the original
+ * memory filename passed to U-Boot will be left intact.
+ *
+ * @param dest Buffer containing executable image
+ * @param size Size of buffer
+ */
+int os_jump_to_image(const void *dest, int size);
+
#endif
#define PLPRCR 0x00000284
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
#define HID2 1011
#include <asm/io.h>
#include <mmc.h>
+#include <fdtdec.h>
/*
* Controller registers
const struct sdhci_ops *ops;
int index;
+ int bus_width;
+ struct fdt_gpio_state pwr_gpio; /* Power GPIO */
+ struct fdt_gpio_state cd_gpio; /* Card Detect GPIO */
+
void (*set_control_reg)(struct sdhci_host *host);
void (*set_clock)(int dev_index, unsigned int div);
uint voltages;
enum en_sound_codec codec_type;
};
+/*
+ * Generates square wave sound data for 1 second
+ *
+ * @param data data buffer pointer
+ * @param size size of the buffer
+ * @param freq frequency of the wave
+ */
+void sound_create_square_wave(unsigned short *data, int size, uint32_t freq);
+
/*
* Initialises audio sub system
* @param blob Pointer of device tree node or NULL if none.
* @sector_size: Sector size of this device
* @nr_sectors: No.of sectors on this device
* @e_rd_cmd: Enum list for read commands
- * @flags: Importent param, for flash specific behaviour
+ * @flags: Important param, for flash specific behaviour
*/
struct spi_flash_params {
const char *name;
* @memory_map: Address of read-only SPI flash access
* @read: Flash read ops: Read len bytes at offset into buf
* Supported cmds: Fast Array Read
- * @write: Flash write ops: Write len bytes from buf into offeset
+ * @write: Flash write ops: Write len bytes from buf into offset
* Supported cmds: Page Program
* @erase: Flash erase ops: Erase len bytes from offset
* Supported cmds: Sector erase 4K, 32K, 64K
- * return 0 - Sucess, 1 - Failure
+ * return 0 - Success, 1 - Failure
*/
struct spi_flash {
struct spi_slave *spi;
#define __S3C_USB_GADGET
#include <asm/errno.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <linux/list.h>
};
/*
- * Function definitions for each USB ethernet driver go here, bracketed by
- * #ifdef CONFIG_USB_ETHER_xxx...#endif
+ * Function definitions for each USB ethernet driver go here
+ * (declaration is unconditional, compilation is conditional)
*/
-#ifdef CONFIG_USB_ETHER_ASIX
void asix_eth_before_probe(void);
int asix_eth_probe(struct usb_device *dev, unsigned int ifnum,
struct ueth_data *ss);
int asix_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
struct eth_device *eth);
-#endif
-#ifdef CONFIG_USB_ETHER_SMSC95XX
+void mcs7830_eth_before_probe(void);
+int mcs7830_eth_probe(struct usb_device *dev, unsigned int ifnum,
+ struct ueth_data *ss);
+int mcs7830_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
+ struct eth_device *eth);
+
void smsc95xx_eth_before_probe(void);
int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum,
struct ueth_data *ss);
int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
struct eth_device *eth);
-#endif
#endif /* __USB_ETHER_H__ */
--- /dev/null
+/*
+ * USB virtual root hub descriptors
+ *
+ * (C) Copyright 2014
+ * Stephen Warren swarren@wwwdotorg.org
+ *
+ * Based on ohci-hcd.c
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __USBROOTHUBDES_H__
+#define __USBROOTHUBDES_H__
+
+/* Device descriptor */
+static __u8 root_hub_dev_des[] = {
+ 0x12, /* __u8 bLength; */
+ 0x01, /* __u8 bDescriptorType; Device */
+ 0x10, /* __u16 bcdUSB; v1.1 */
+ 0x01,
+ 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
+ 0x00, /* __u8 bDeviceSubClass; */
+ 0x00, /* __u8 bDeviceProtocol; */
+ 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
+ 0x00, /* __u16 idVendor; */
+ 0x00,
+ 0x00, /* __u16 idProduct; */
+ 0x00,
+ 0x00, /* __u16 bcdDevice; */
+ 0x00,
+ 0x00, /* __u8 iManufacturer; */
+ 0x01, /* __u8 iProduct; */
+ 0x00, /* __u8 iSerialNumber; */
+ 0x01, /* __u8 bNumConfigurations; */
+};
+
+/* Configuration descriptor */
+static __u8 root_hub_config_des[] = {
+ 0x09, /* __u8 bLength; */
+ 0x02, /* __u8 bDescriptorType; Configuration */
+ 0x19, /* __u16 wTotalLength; */
+ 0x00,
+ 0x01, /* __u8 bNumInterfaces; */
+ 0x01, /* __u8 bConfigurationValue; */
+ 0x00, /* __u8 iConfiguration; */
+ 0x40, /* __u8 bmAttributes;
+ * Bit 7: Bus-powered
+ * 6: Self-powered,
+ * 5 Remote-wakwup,
+ * 4..0: resvd
+ */
+ 0x00, /* __u8 MaxPower; */
+ /* interface */
+ 0x09, /* __u8 if_bLength; */
+ 0x04, /* __u8 if_bDescriptorType; Interface */
+ 0x00, /* __u8 if_bInterfaceNumber; */
+ 0x00, /* __u8 if_bAlternateSetting; */
+ 0x01, /* __u8 if_bNumEndpoints; */
+ 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
+ 0x00, /* __u8 if_bInterfaceSubClass; */
+ 0x00, /* __u8 if_bInterfaceProtocol; */
+ 0x00, /* __u8 if_iInterface; */
+ /* endpoint */
+ 0x07, /* __u8 ep_bLength; */
+ 0x05, /* __u8 ep_bDescriptorType; Endpoint */
+ 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
+ 0x03, /* __u8 ep_bmAttributes; Interrupt */
+ 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
+ 0x00,
+ 0xff, /* __u8 ep_bInterval; 255 ms */
+};
+
+#ifdef WANT_USB_ROOT_HUB_HUB_DES
+static unsigned char root_hub_hub_des[] = {
+ 0x09, /* __u8 bLength; */
+ 0x29, /* __u8 bDescriptorType; Hub-descriptor */
+ 0x02, /* __u8 bNbrPorts; */
+ 0x00, /* __u16 wHubCharacteristics; */
+ 0x00,
+ 0x01, /* __u8 bPwrOn2pwrGood; 2ms */
+ 0x00, /* __u8 bHubContrCurrent; 0 mA */
+ 0x00, /* __u8 DeviceRemovable; *** 7 Ports max *** */
+ 0xff, /* __u8 PortPwrCtrlMask; *** 7 ports max *** */
+};
+#endif
+
+static unsigned char root_hub_str_index0[] = {
+ 0x04, /* __u8 bLength; */
+ 0x03, /* __u8 bDescriptorType; String-descriptor */
+ 0x09, /* __u8 lang ID */
+ 0x04, /* __u8 lang ID */
+};
+
+static unsigned char root_hub_str_index1[] = {
+ 32, /* __u8 bLength; */
+ 0x03, /* __u8 bDescriptorType; String-descriptor */
+ 'U', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ '-', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'B', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'o', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'o', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 't', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ ' ', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'R', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'o', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'o', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 't', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ ' ', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'H', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'u', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'b', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+};
+
+#endif
obj-$(CONFIG_RANDOM_MACADDR) += rand.o
obj-$(CONFIG_BOOTP_RANDOM_DELAY) += rand.o
obj-$(CONFIG_CMD_LINK_LOCAL) += rand.o
+
+subdir-ccflags-$(CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED) += -O2
{
/* linebuf as a union causes proper alignment */
union linebuf {
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+ uint64_t uq[MAX_LINE_LENGTH_BYTES/sizeof(uint64_t) + 1];
+#endif
uint32_t ui[MAX_LINE_LENGTH_BYTES/sizeof(uint32_t) + 1];
uint16_t us[MAX_LINE_LENGTH_BYTES/sizeof(uint16_t) + 1];
uint8_t uc[MAX_LINE_LENGTH_BYTES/sizeof(uint8_t) + 1];
} lb;
int i;
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+ uint64_t x;
+#else
+ uint32_t x;
+#endif
if (linelen*width > MAX_LINE_LENGTH_BYTES)
linelen = MAX_LINE_LENGTH_BYTES / width;
/* Copy from memory into linebuf and print hex values */
for (i = 0; i < thislinelen; i++) {
- uint32_t x;
if (width == 4)
x = lb.ui[i] = *(volatile uint32_t *)data;
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+ else if (width == 8)
+ x = lb.uq[i] = *(volatile uint64_t *)data;
+#endif
else if (width == 2)
x = lb.us[i] = *(volatile uint16_t *)data;
else
x = lb.uc[i] = *(volatile uint8_t *)data;
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+ printf(" %0*llx", width * 2, x);
+#else
printf(" %0*x", width * 2, x);
+#endif
data += width;
}
COMPAT(SAMSUNG_EXYNOS5_USB3_PHY, "samsung,exynos5250-usb3-phy"),
COMPAT(SAMSUNG_EXYNOS_TMU, "samsung,exynos-tmu"),
COMPAT(SAMSUNG_EXYNOS_FIMD, "samsung,exynos-fimd"),
+ COMPAT(SAMSUNG_EXYNOS_MIPI_DSI, "samsung,exynos-mipi-dsi"),
COMPAT(SAMSUNG_EXYNOS5_DP, "samsung,exynos5-dp"),
COMPAT(SAMSUNG_EXYNOS5_DWMMC, "samsung,exynos5250-dwmmc"),
+ COMPAT(SAMSUNG_EXYNOS_MMC, "samsung,exynos-mmc"),
COMPAT(SAMSUNG_EXYNOS_SERIAL, "samsung,exynos4210-uart"),
COMPAT(MAXIM_MAX77686_PMIC, "maxim,max77686_pmic"),
COMPAT(GENERIC_SPI_FLASH, "spi-flash"),
COMPAT(INFINEON_SLB9635_TPM, "infineon,slb9635-tpm"),
COMPAT(INFINEON_SLB9645_TPM, "infineon,slb9645-tpm"),
COMPAT(SAMSUNG_EXYNOS5_I2C, "samsung,exynos5-hsi2c"),
+ COMPAT(SANDBOX_HOST_EMULATION, "sandbox,host-emulation"),
+ COMPAT(SANDBOX_LCD_SDL, "sandbox,lcd-sdl"),
};
const char *fdtdec_get_compatible(enum fdt_compat_id id)
debug("%s: size=%zx\n", __func__, *size);
return 0;
}
+
+/**
+ * Read a flash entry from the fdt
+ *
+ * @param blob FDT blob
+ * @param node Offset of node to read
+ * @param name Name of node being read
+ * @param entry Place to put offset and size of this node
+ * @return 0 if ok, -ve on error
+ */
+int fdtdec_read_fmap_entry(const void *blob, int node, const char *name,
+ struct fmap_entry *entry)
+{
+ u32 reg[2];
+
+ if (fdtdec_get_int_array(blob, node, "reg", reg, 2)) {
+ debug("Node '%s' has bad/missing 'reg' property\n", name);
+ return -FDT_ERR_NOTFOUND;
+ }
+ entry->offset = reg[0];
+ entry->length = reg[1];
+
+ return 0;
+}
arch="$2"
cpu=`echo $3 | awk 'BEGIN {FS = ":"} ; {print $1}'`
spl_cpu=`echo $3 | awk 'BEGIN {FS = ":"} ; {print $2}'`
-if [ "$6" = "-" ] ; then
+if [ "$6" = "<none>" ] ; then
+ board=
+elif [ "$6" = "-" ] ; then
board=${BOARD_NAME}
else
board="$6"
#
# Create link to architecture specific headers
#
-if [ "$SRCTREE" != "$OBJTREE" ] ; then
- mkdir -p ${OBJTREE}/include
- LNPREFIX=${SRCTREE}/arch/${arch}/include/asm/
- cd ${OBJTREE}/include
+if [ -n "$KBUILD_SRC" ] ; then
+ mkdir -p ${objtree}/include
+ LNPREFIX=${srctree}/arch/${arch}/include/asm/
+ cd ${objtree}/include
mkdir -p asm
else
cd arch/${arch}/include
ln -s ${LNPREFIX}proc-armv asm/proc
fi
-if [ "$SRCTREE" = "$OBJTREE" ] ; then
- cd ${SRCTREE}/include
+if [ -z "$KBUILD_SRC" ] ; then
+ cd ${srctree}/include
fi
#
[ "${soc}" ] && echo "#define CONFIG_SYS_SOC \"${soc}\"" >> config.h
+[ "${board}" ] && echo "#define CONFIG_BOARDDIR board/$BOARDDIR" >> config.h
cat << EOF >> config.h
-#define CONFIG_BOARDDIR board/$BOARDDIR
#include <config_cmd_defaults.h>
#include <config_defaults.h>
#include <configs/${CONFIG_NAME}.h>
+++ /dev/null
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
-
-nandobj := $(OBJTREE)/nand_spl/
-
-LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
- $(LDFLAGS_FINAL)
-asflags-y += -DCONFIG_NAND_SPL
-ccflags-y += -DCONFIG_NAND_SPL
-
-SOBJS = start.o resetvec.o cache.o
-COBJS = gpio.o nand_boot.o nand_ecc.o memory.o ndfc.o pll.o
-
-OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(nandobj)board/$(BOARDDIR)
-
-targets += $(__OBJS)
-
-all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin \
- $(nandobj)System.map
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
-
-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map -o $@
-
-$(nandobj)System.map: $(nandobj)u-boot-spl
- @$(NM) $< | \
- grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
- sort > $@
-
-$(nandobj)u-boot.lds: $(LDSCRIPT)
- $(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
-
-# create symbolic links for common files
-
-# from cpu directory
-$(obj)/cache.S:
- @rm -f $@
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/cache.S $@
-
-$(obj)/gpio.c:
- @rm -f $@
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/gpio.c $@
-
-$(obj)/ndfc.c:
- @rm -f $@
- ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@
-
-$(obj)/resetvec.S:
- @rm -f $@
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@
-
-$(obj)/start.S:
- @rm -f $@
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@
-
-# from board directory
-$(obj)/memory.c:
- @rm -f $@
- ln -s $(SRCTREE)/board/amcc/acadia/memory.c $@
-
-$(obj)/pll.c:
- @rm -f $@
- ln -s $(SRCTREE)/board/amcc/acadia/pll.c $@
-
-# from nand_spl directory
-$(obj)/nand_boot.c:
- @rm -f $@
- ln -s $(SRCTREE)/nand_spl/nand_boot.c $@
-
-# from drivers/mtd/nand directory
-$(obj)/nand_ecc.c:
- @rm -f $@
- ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@
+++ /dev/null
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-#
-# AMCC 405EZ Reference Platform (Acadia) board
-#
-
-#
-# CONFIG_SYS_TEXT_BASE for SPL:
-#
-# On 4xx platforms the SPL is located at 0xfffff000...0xffffffff,
-# in the last 4kBytes of memory space in cache.
-# We will copy this SPL into internal SRAM in start.S. So we set
-# CONFIG_SYS_TEXT_BASE to starting address in internal SRAM here.
-#
-CONFIG_SYS_TEXT_BASE = 0xf8004000
-
-# PAD_TO used to generate a 16kByte binary needed for the combined image
-# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000
-PAD_TO = 0xf8008000
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc:common)
-SECTIONS
-{
- .resetvec 0xf8004ffc :
- {
- KEEP(*(.resetvec))
- } = 0xffff
-
- .text :
- {
- start.o (.text)
- nand_boot.o (.text)
- ndfc.o (.text)
-
- *(.text)
- *(.fixup)
- }
- _etext = .;
-
- .data :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- *(.data*)
- *(.sdata*)
- __got2_start = .;
- *(.got2)
- __got2_end = .;
- }
-
- _edata = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss)
- *(.bss)
- . = ALIGN(4);
- }
-
- __bss_end = . ;
-}
+++ /dev/null
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
-
-nandobj := $(OBJTREE)/nand_spl/
-
-LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
- $(LDFLAGS_FINAL)
-asflags-y += -DCONFIG_NAND_SPL
-ccflags-y += -DCONFIG_NAND_SPL
-
-SOBJS = start.o init.o resetvec.o
-COBJS = nand_boot.o nand_ecc.o ndfc.o sdram.o
-
-OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(nandobj)board/$(BOARDDIR)
-
-targets += $(__OBJS)
-
-all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
-
-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map -o $@
-
-$(nandobj)u-boot.lds: $(LDSCRIPT)
- $(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
-
-# create symbolic links for common files
-
-# from cpu directory
-$(obj)/ndfc.c:
- @rm -f $@
- ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@
-
-$(obj)/resetvec.S:
- @rm -f $@
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@
-
-$(obj)/start.S:
- @rm -f $@
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@
-
-# from board directory
-$(obj)/init.S:
- @rm -f $@
- ln -s $(SRCTREE)/board/amcc/bamboo/init.S $@
-
-# from nand_spl directory
-$(obj)/nand_boot.c:
- @rm -f $@
- ln -s $(SRCTREE)/nand_spl/nand_boot.c $@
-
-# from drivers/mtd/nand directory
-$(obj)/nand_ecc.c:
- @rm -f $@
- ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@
+++ /dev/null
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-#
-# AMCC 440EP Reference Platform (Bamboo) board
-#
-
-#
-# CONFIG_SYS_TEXT_BASE for SPL:
-#
-# On 440EP(x) platforms the SPL is located at 0xfffff000...0xffffffff,
-# in the last 4kBytes of memory space in cache.
-# We will copy this SPL into instruction-cache in start.S. So we set
-# CONFIG_SYS_TEXT_BASE to starting address in i-cache here.
-#
-CONFIG_SYS_TEXT_BASE = 0x00800000
-
-# PAD_TO used to generate a 16kByte binary needed for the combined image
-# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000
-PAD_TO = 0x00804000
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-
-static void wait_init_complete(void)
-{
- u32 val;
-
- do {
- mfsdram(SDRAM0_MCSTS, val);
- } while (!(val & 0x80000000));
-}
-
-/*
- * phys_size_t initdram(int board_type)
- *
- * As the name already indicates, this function is called very early
- * from start.S and configures the SDRAM with fixed values. This is needed,
- * since the 440EP has no internal SRAM and the 4kB NAND_SPL loader has
- * not enough free space to implement the complete I2C SPD DDR autodetection
- * routines. Therefore the Bamboo only supports the onboard 64MBytes of SDRAM
- * when booting from NAND flash.
- *
- * Note:
- * As found out by Eugene O'Brien <eugene.obrien@advantechamt.com>, the fixed
- * DDR setup has problems (U-Boot crashes randomly upon TFTP), when the DIMM
- * modules are still plugged in. So it is recommended to remove the DIMM
- * modules while using the NAND booting code with the fixed SDRAM setup!
- */
-phys_size_t initdram(int board_type)
-{
- /*
- * Soft-reset SDRAM controller.
- */
- mtsdr(SDR0_SRST, SDR0_SRST_DMC);
- mtsdr(SDR0_SRST, 0x00000000);
-
- /*
- * Disable memory controller.
- */
- mtsdram(SDRAM0_CFG0, 0x00000000);
-
- /*
- * Setup some default
- */
- mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
- mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
- mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
- mtsdram(SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */
- mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
-
- /*
- * Following for CAS Latency = 2.5 @ 133 MHz PLB
- */
- mtsdram(SDRAM0_B0CR, 0x00082001);
- mtsdram(SDRAM0_TR0, 0x41094012);
- mtsdram(SDRAM0_TR1, 0x8080083d); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
- mtsdram(SDRAM0_RTR, 0x04100000); /* Interval 7.8µs @ 133MHz PLB */
- mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM*/
-
- /*
- * Enable the controller, then wait for DCEN to complete
- */
- mtsdram(SDRAM0_CFG0, 0x80000000); /* DCEN=1, PMUD=0*/
- wait_init_complete();
-
- return CONFIG_SYS_MBYTES_SDRAM << 20;
-}
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc:common)
-SECTIONS
-{
- .resetvec 0x00800FFC :
- {
- KEEP(*(.resetvec))
- } = 0xffff
-
- .text :
- {
- start.o (.text)
- init.o (.text)
- nand_boot.o (.text)
- sdram.o (.text)
- ndfc.o (.text)
-
- *(.text)
- *(.fixup)
- }
- _etext = .;
-
- .data :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- *(.data*)
- *(.sdata*)
- __got2_start = .;
- *(.got2)
- __got2_end = .;
- }
-
- _edata = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss)
- *(.bss)
- . = ALIGN(4);
- }
-
- __bss_end = . ;
-}
+++ /dev/null
-#
-# (C) Copyright 2008
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
-
-nandobj := $(OBJTREE)/nand_spl/
-
-LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
- $(LDFLAGS_FINAL)
-asflags-y += -DCONFIG_NAND_SPL
-ccflags-y += -DCONFIG_NAND_SPL
-
-SOBJS := start.o
-SOBJS += init.o
-SOBJS += resetvec.o
-COBJS := ddr2_fixed.o
-COBJS += nand_boot.o
-COBJS += nand_ecc.o
-COBJS += ndfc.o
-
-OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(nandobj)board/$(BOARDDIR)
-
-targets += $(__OBJS)
-
-all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
-
-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map -o $@
-
-$(nandobj)u-boot.lds: $(LDSCRIPT)
- $(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
-
-# create symbolic links for common files
-
-# from cpu directory
-$(obj)/ndfc.c:
- @rm -f $@
- ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@
-
-$(obj)/resetvec.S:
- @rm -f $@
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@
-
-$(obj)/start.S:
- @rm -f $@
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@
-
-# from board directory
-$(obj)/init.S:
- @rm -f $@
- ln -s $(SRCTREE)/board/amcc/canyonlands/init.S $@
-
-# from nand_spl directory
-$(obj)/nand_boot.c:
- @rm -f $@
- ln -s $(SRCTREE)/nand_spl/nand_boot.c $@
-
-# from drivers/mtd/nand directory
-$(obj)/nand_ecc.c:
- @rm -f $@
- ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@
+++ /dev/null
-#
-# (C) Copyright 2008
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-#
-# AMCC 460EX Reference Platform (Canyonlands) board
-#
-
-#
-# CONFIG_SYS_TEXT_BASE for SPL:
-#
-# On 460EX platforms the SPL is located at 0xfffff000...0xffffffff,
-# in the last 4kBytes of memory space in cache.
-# We will copy this SPL into internal SRAM in start.S. So we set
-# CONFIG_SYS_TEXT_BASE to starting address in internal SRAM here.
-#
-CONFIG_SYS_TEXT_BASE = 0xE3003000
-
-# PAD_TO used to generate a 128kByte binary needed for the combined image
-# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x20000
-PAD_TO = 0xE3023000
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
+++ /dev/null
-/*
- * (C) Copyright 2008-2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-
-/*
- * This code can configure those two Crucial SODIMM's:
- *
- * Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank)
- * Crucial CT6464AC667.8FB - 512MB SO-DIMM (dual rank)
- *
- */
-
-#define TEST_ADDR 0x10000000
-#define TEST_MAGIC 0x11223344
-
-static void wait_init_complete(void)
-{
- u32 val;
-
- do {
- mfsdram(SDRAM_MCSTAT, val);
- } while (!(val & 0x80000000));
-}
-
-static void ddr_start(void)
-{
- mtsdram(SDRAM_MCOPT2, 0x28000000);
- wait_init_complete();
-}
-
-static void ddr_init_common(void)
-{
- /*
- * Reset the DDR-SDRAM controller.
- */
- mtsdr(SDR0_SRST, SDR0_SRST0_DMC);
- mtsdr(SDR0_SRST, 0x00000000);
-
- /*
- * These values are cloned from a running NOR booting
- * Canyonlands with SPD-DDR2 detection and calibration
- * enabled. This will only work for the same memory
- * configuration as used here:
- *
- */
- mtsdram(SDRAM_MCOPT2, 0x00000000);
- mtsdram(SDRAM_MODT0, 0x01000000);
- mtsdram(SDRAM_WRDTR, 0x82000823);
- mtsdram(SDRAM_CLKTR, 0x40000000);
- mtsdram(SDRAM_MB0CF, 0x00000201);
- mtsdram(SDRAM_RTR, 0x06180000);
- mtsdram(SDRAM_SDTR1, 0x80201000);
- mtsdram(SDRAM_SDTR2, 0x42103243);
- mtsdram(SDRAM_SDTR3, 0x0A0D0D16);
- mtsdram(SDRAM_MMODE, 0x00000632);
- mtsdram(SDRAM_MEMODE, 0x00000040);
- mtsdram(SDRAM_INITPLR0, 0xB5380000);
- mtsdram(SDRAM_INITPLR1, 0x82100400);
- mtsdram(SDRAM_INITPLR2, 0x80820000);
- mtsdram(SDRAM_INITPLR3, 0x80830000);
- mtsdram(SDRAM_INITPLR4, 0x80810040);
- mtsdram(SDRAM_INITPLR5, 0x80800532);
- mtsdram(SDRAM_INITPLR6, 0x82100400);
- mtsdram(SDRAM_INITPLR7, 0x8A080000);
- mtsdram(SDRAM_INITPLR8, 0x8A080000);
- mtsdram(SDRAM_INITPLR9, 0x8A080000);
- mtsdram(SDRAM_INITPLR10, 0x8A080000);
- mtsdram(SDRAM_INITPLR11, 0x80000432);
- mtsdram(SDRAM_INITPLR12, 0x808103C0);
- mtsdram(SDRAM_INITPLR13, 0x80810040);
- mtsdram(SDRAM_RDCC, 0x40000000);
- mtsdram(SDRAM_RQDC, 0x80000038);
- mtsdram(SDRAM_RFDC, 0x00000257);
-
- mtdcr(SDRAM_R0BAS, 0x0000F800); /* MQ0_B0BAS */
-}
-
-phys_size_t initdram(int board_type)
-{
- /*
- * First try init for this module:
- *
- * Crucial CT6464AC667.8FB - 512MB SO-DIMM (dual rank)
- */
-
- ddr_init_common();
-
- /*
- * Crucial CT6464AC667.8FB - 512MB SO-DIMM
- */
- mtdcr(SDRAM_R0BAS, 0x0000F800);
- mtdcr(SDRAM_R1BAS, 0x0400F800);
- mtsdram(SDRAM_MCOPT1, 0x05122000);
- mtsdram(SDRAM_CODT, 0x02800021);
- mtsdram(SDRAM_MB1CF, 0x00000201);
-
- ddr_start();
-
- /*
- * Now test if the dual-ranked module is really installed
- * by checking an address in the upper 256MByte region
- */
- out_be32((void *)TEST_ADDR, TEST_MAGIC);
- if (in_be32((void *)TEST_ADDR) != TEST_MAGIC) {
- /*
- * The test failed, so we assume that the single
- * ranked module is installed:
- *
- * Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank)
- */
-
- ddr_init_common();
-
- mtdcr(SDRAM_R0BAS, 0x0000F000);
- mtsdram(SDRAM_MCOPT1, 0x05322000);
- mtsdram(SDRAM_CODT, 0x00800021);
-
- ddr_start();
- }
-
- return CONFIG_SYS_MBYTES_SDRAM << 20;
-}
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc:common)
-SECTIONS
-{
- .resetvec 0xE3003FFC :
- {
- KEEP(*(.resetvec))
- } = 0xffff
-
- .text :
- {
- start.o (.text)
- init.o (.text)
- nand_boot.o (.text)
- ddr2_fixed.o (.text)
- ndfc.o (.text)
-
- *(.text)
- *(.fixup)
- }
- _etext = .;
-
- .data :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- *(.data*)
- *(.sdata*)
- __got2_start = .;
- *(.got2)
- __got2_end = .;
- }
-
- _edata = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss)
- *(.bss)
- . = ALIGN(4);
- }
-
- __bss_end = . ;
-}
+++ /dev/null
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
-
-nandobj := $(OBJTREE)/nand_spl/
-
-LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
- $(LDFLAGS_FINAL)
-asflags-y += -DCONFIG_NAND_SPL
-ccflags-y += -DCONFIG_NAND_SPL
-
-SOBJS = start.o resetvec.o cache.o
-COBJS = 44x_spd_ddr2.o nand_boot.o nand_ecc.o ndfc.o
-
-OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(nandobj)board/$(BOARDDIR)
-
-targets += $(__OBJS)
-
-all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
-
-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map -o $@
-
-$(nandobj)u-boot.lds: $(LDSCRIPT)
- $(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
-
-# create symbolic links for common files
-
-# from cpu directory
-$(obj)/44x_spd_ddr2.c: $(obj)/ecc.h
- @rm -f $@
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c $@
-
-$(obj)/cache.S:
- @rm -f $@
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/cache.S $@
-
-$(obj)/ecc.h:
- @rm -f $@
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/ecc.h $@
-
-$(obj)/ndfc.c:
- @rm -f $@
- ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@
-
-$(obj)/resetvec.S:
- @rm -f $@
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@
-
-$(obj)/start.S:
- @rm -f $@
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@
-
-# from nand_spl directory
-$(obj)/nand_boot.c:
- @rm -f $@
- ln -s $(SRCTREE)/nand_spl/nand_boot.c $@
-
-# from drivers/nand directory
-$(obj)/nand_ecc.c:
- @rm -f $@
- ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@
+++ /dev/null
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-#
-# AMCC 405EX Reference Platform (Kilauea) board
-#
-
-#
-# CONFIG_SYS_TEXT_BASE for SPL:
-#
-# On 4xx platforms the SPL is located at 0xfffff000...0xffffffff,
-# in the last 4kBytes of memory space in cache.
-# We will copy this SPL into SDRAM since we can't access the NAND
-# controller at CS0 while running from this location. So we set
-# CONFIG_SYS_TEXT_BASE to starting address in SDRAM here.
-#
-CONFIG_SYS_TEXT_BASE = 0x00800000
-
-# PAD_TO used to generate a 16kByte binary needed for the combined image
-# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000
-PAD_TO = 0x00804000
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc:common)
-SECTIONS
-{
- .resetvec 0x00800FFC :
- {
- KEEP(*(.resetvec))
- } = 0xffff
-
- .text :
- {
- start.o (.text)
- nand_boot.o (.text)
- ndfc.o (.text)
-
- *(.text)
- *(.fixup)
- }
- _etext = .;
-
- .data :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- *(.data*)
- *(.sdata*)
- __got2_start = .;
- *(.got2)
- __got2_end = .;
- }
-
- _edata = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss)
- *(.bss)
- . = ALIGN(4);
- }
-
- __bss_end = . ;
-}
+++ /dev/null
-#
-# (C) Copyright 2006-2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
-
-nandobj := $(OBJTREE)/nand_spl/
-
-LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
- $(LDFLAGS_FINAL)
-asflags-y += -DCONFIG_NAND_SPL
-ccflags-y += -DCONFIG_NAND_SPL
-
-SOBJS = start.o init.o resetvec.o
-COBJS = denali_data_eye.o nand_boot.o nand_ecc.o ndfc.o sdram.o
-
-OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(nandobj)board/$(BOARDDIR)
-
-targets += $(__OBJS)
-
-all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
-
-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map -o $@
-
-$(nandobj)u-boot.lds: $(LDSCRIPT)
- $(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
-
-# create symbolic links for common files
-
-# from cpu directory
-$(obj)/denali_data_eye.c:
- @rm -f $@
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/denali_data_eye.c $@
-
-$(obj)/ndfc.c:
- @rm -f $@
- ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@
-
-$(obj)/resetvec.S:
- @rm -f $@
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@
-
-$(obj)/start.S:
- @rm -f $@
- ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@
-
-# from board directory
-$(obj)/init.S:
- @rm -f $@
- ln -s $(SRCTREE)/board/amcc/sequoia/init.S $@
-
-$(obj)/sdram.c:
- @rm -f $@
- @rm -f $(obj)/sdram.h
- ln -s $(SRCTREE)/board/amcc/sequoia/sdram.c $@
- ln -s $(SRCTREE)/board/amcc/sequoia/sdram.h $(obj)/sdram.h
-
-# from nand_spl directory
-$(obj)/nand_boot.c:
- @rm -f $@
- ln -s $(SRCTREE)/nand_spl/nand_boot.c $@
-
-# from drivers/mtd/nand directory
-$(obj)/nand_ecc.c:
- @rm -f $@
- ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@
+++ /dev/null
-#
-# (C) Copyright 2006
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-#
-# AMCC 440EPx Reference Platform (Sequoia) board
-#
-
-#
-# CONFIG_SYS_TEXT_BASE for SPL:
-#
-# On 440EP(x) platforms the SPL is located at 0xfffff000...0xffffffff,
-# in the last 4kBytes of memory space in cache.
-# We will copy this SPL into internal SRAM in start.S. So we set
-# CONFIG_SYS_TEXT_BASE to starting address in internal SRAM here.
-#
-CONFIG_SYS_TEXT_BASE = 0xE0013000
-
-# PAD_TO used to generate a 16kByte binary needed for the combined image
-# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000
-PAD_TO = 0xE0017000
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
+++ /dev/null
-/*
- * (C) Copyright 2006-2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc:common)
-SECTIONS
-{
- .resetvec 0xE0013FFC :
- {
- KEEP(*(.resetvec))
- } = 0xffff
-
- .text :
- {
- start.o (.text)
- init.o (.text)
- nand_boot.o (.text)
- sdram.o (.text)
- ndfc.o (.text)
-
- *(.text)
- *(.fixup)
- }
- _etext = .;
-
- .data :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- *(.data*)
- *(.sdata*)
- __got2_start = .;
- *(.got2)
- __got2_end = .;
- }
-
- _edata = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss)
- *(.bss)
- . = ALIGN(4);
- }
-
- __bss_end = . ;
-}
PAD_TO := 0xfff04000
-nandobj := $(OBJTREE)/nand_spl/
+nandobj := $(objtree)/nand_spl/
-LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
+LDSCRIPT= $(srctree)/nand_spl/board/$(BOARDDIR)/u-boot.lds
LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
$(LDFLAGS) $(LDFLAGS_FINAL)
asflags-y += -DCONFIG_NAND_SPL
# create symbolic links for common files
$(obj)/start.S:
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc83xx/start.S $@
+ ln -sf $(srctree)/arch/powerpc/cpu/mpc83xx/start.S $@
$(obj)/nand_boot_fsl_elbc.c:
- ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@
+ ln -sf $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@
$(obj)/sdram.c:
- ln -sf $(SRCTREE)/board/$(BOARDDIR)/sdram.c $@
+ ln -sf $(srctree)/board/$(BOARDDIR)/sdram.c $@
$(obj)/$(BOARD).c:
- ln -sf $(SRCTREE)/board/$(BOARDDIR)/$(BOARD).c $@
+ ln -sf $(srctree)/board/$(BOARDDIR)/$(BOARD).c $@
$(obj)/ns16550.c:
- ln -sf $(SRCTREE)/drivers/serial/ns16550.c $@
+ ln -sf $(srctree)/drivers/serial/ns16550.c $@
$(obj)/spl_minimal.c:
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc83xx/spl_minimal.c $@
+ ln -sf $(srctree)/arch/powerpc/cpu/mpc83xx/spl_minimal.c $@
$(obj)/cache.c:
- ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $@
+ ln -sf $(srctree)/arch/powerpc/lib/cache.c $@
$(obj)/time.c:
- ln -sf $(SRCTREE)/arch/powerpc/lib/time.c $@
+ ln -sf $(srctree)/arch/powerpc/lib/time.c $@
$(obj)/ticks.S:
- ln -sf $(SRCTREE)/arch/powerpc/lib/ticks.S $@
+ ln -sf $(srctree)/arch/powerpc/lib/ticks.S $@
CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000
PAD_TO := 0xfff01000
-nandobj := $(OBJTREE)/nand_spl/
+nandobj := $(objtree)/nand_spl/
-LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
+LDSCRIPT= $(srctree)/$(CPUDIR)/u-boot-nand_spl.lds
LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
$(LDFLAGS) $(LDFLAGS_FINAL)
asflags-y += -DCONFIG_NAND_SPL
$(obj)/cache.c:
@rm -f $@
- ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $@
+ ln -sf $(srctree)/arch/powerpc/lib/cache.c $@
$(obj)/cpu_init_early.c:
@rm -f $@
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@
+ ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@
$(obj)/spl_minimal.c:
@rm -f $@
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@
+ ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@
$(obj)/fsl_law.c:
@rm -f $@
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $@
+ ln -sf $(srctree)/arch/powerpc/cpu/mpc8xxx/law.c $@
$(obj)/law.c:
@rm -f $@
- ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $@
+ ln -sf $(srctree)/board/$(BOARDDIR)/law.c $@
$(obj)/nand_boot_fsl_elbc.c:
@rm -f $@
- ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@
+ ln -sf $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@
$(obj)/ns16550.c:
@rm -f $@
- ln -sf $(SRCTREE)/drivers/serial/ns16550.c $@
+ ln -sf $(srctree)/drivers/serial/ns16550.c $@
$(obj)/resetvec.S:
@rm -f $@
- ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $@
+ ln -s $(srctree)/$(CPUDIR)/resetvec.S $@
$(obj)/fixed_ivor.S:
@rm -f $@
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@
+ ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@
$(obj)/start.S: $(obj)/fixed_ivor.S
@rm -f $@
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $@
+ ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/start.S $@
$(obj)/tlb.c:
@rm -f $@
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $@
+ ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/tlb.c $@
$(obj)/tlb_table.c:
@rm -f $@
- ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $@
+ ln -sf $(srctree)/board/$(BOARDDIR)/tlb.c $@
CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000
PAD_TO := 0xfff01000
-nandobj := $(OBJTREE)/nand_spl/
+nandobj := $(objtree)/nand_spl/
-LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
+LDSCRIPT= $(srctree)/$(CPUDIR)/u-boot-nand_spl.lds
LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
$(LDFLAGS) $(LDFLAGS_FINAL)
asflags-y += -DCONFIG_NAND_SPL
$(obj)/cache.c:
@rm -f $@
- ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $@
+ ln -sf $(srctree)/arch/powerpc/lib/cache.c $@
$(obj)/cpu_init_early.c:
@rm -f $@
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@
+ ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@
$(obj)/spl_minimal.c:
@rm -f $@
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@
+ ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@
$(obj)/fsl_law.c:
@rm -f $@
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $@
+ ln -sf $(srctree)/arch/powerpc/cpu/mpc8xxx/law.c $@
$(obj)/law.c:
@rm -f $@
- ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $@
+ ln -sf $(srctree)/board/$(BOARDDIR)/law.c $@
$(obj)/nand_boot_fsl_elbc.c:
@rm -f $@
- ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@
+ ln -sf $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@
$(obj)/ns16550.c:
@rm -f $@
- ln -sf $(SRCTREE)/drivers/serial/ns16550.c $@
+ ln -sf $(srctree)/drivers/serial/ns16550.c $@
$(obj)/resetvec.S:
@rm -f $@
- ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $@
+ ln -s $(srctree)/$(CPUDIR)/resetvec.S $@
$(obj)/fixed_ivor.S:
@rm -f $@
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@
+ ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@
$(obj)/start.S: $(obj)/fixed_ivor.S
@rm -f $@
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $@
+ ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/start.S $@
$(obj)/tlb.c:
@rm -f $@
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $@
+ ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/tlb.c $@
$(obj)/tlb_table.c:
@rm -f $@
- ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $@
+ ln -sf $(srctree)/board/$(BOARDDIR)/tlb.c $@
CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000
PAD_TO := 0xfff01000
-nandobj := $(OBJTREE)/nand_spl/
+nandobj := $(objtree)/nand_spl/
-LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
+LDSCRIPT= $(srctree)/$(CPUDIR)/u-boot-nand_spl.lds
LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
$(LDFLAGS) $(LDFLAGS_FINAL)
asflags-y += -DCONFIG_NAND_SPL
$(obj)/cache.c:
@rm -f $@
- ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $@
+ ln -sf $(srctree)/arch/powerpc/lib/cache.c $@
$(obj)/cpu_init_early.c:
@rm -f $@
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@
+ ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@
$(obj)/spl_minimal.c:
@rm -f $@
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@
+ ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@
$(obj)/fsl_law.c:
@rm -f $@
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $@
+ ln -sf $(srctree)/arch/powerpc/cpu/mpc8xxx/law.c $@
$(obj)/law.c:
@rm -f $@
- ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $@
+ ln -sf $(srctree)/board/$(BOARDDIR)/law.c $@
$(obj)/nand_boot_fsl_elbc.c:
@rm -f $@
- ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@
+ ln -sf $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@
$(obj)/ns16550.c:
@rm -f $@
- ln -sf $(SRCTREE)/drivers/serial/ns16550.c $@
+ ln -sf $(srctree)/drivers/serial/ns16550.c $@
$(obj)/resetvec.S:
@rm -f $@
- ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $@
+ ln -s $(srctree)/$(CPUDIR)/resetvec.S $@
$(obj)/fixed_ivor.S:
@rm -f $@
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@
+ ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@
$(obj)/start.S: $(obj)/fixed_ivor.S
@rm -f $@
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $@
+ ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/start.S $@
$(obj)/tlb.c:
@rm -f $@
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $@
+ ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/tlb.c $@
$(obj)/tlb_table.c:
@rm -f $@
- ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $@
+ ln -sf $(srctree)/board/$(BOARDDIR)/tlb.c $@
PAD_TO := 0xfff01000
-nandobj := $(OBJTREE)/nand_spl/
+nandobj := $(objtree)/nand_spl/
-LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
+LDSCRIPT= $(srctree)/$(CPUDIR)/u-boot-nand_spl.lds
LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
$(LDFLAGS) $(LDFLAGS_FINAL)
asflags-y += -DCONFIG_NAND_SPL
$(obj)/cache.c:
@rm -f $@
- ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $@
+ ln -sf $(srctree)/arch/powerpc/lib/cache.c $@
$(obj)/cpu_init_early.c:
@rm -f $@
- ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $@
+ ln -sf $(srctree)/$(CPUDIR)/cpu_init_early.c $@
$(obj)/spl_minimal.c:
@rm -f $@
- ln -sf $(SRCTREE)/$(CPUDIR)/spl_minimal.c $@
+ ln -sf $(srctree)/$(CPUDIR)/spl_minimal.c $@
$(obj)/fsl_law.c:
@rm -f $@
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $@
+ ln -sf $(srctree)/arch/powerpc/cpu/mpc8xxx/law.c $@
$(obj)/law.c:
@rm -f $@
- ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $@
+ ln -sf $(srctree)/board/$(BOARDDIR)/law.c $@
$(obj)/nand_boot_fsl_elbc.c:
@rm -f $@
- ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@
+ ln -sf $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@
$(obj)/ns16550.c:
@rm -f $@
- ln -sf $(SRCTREE)/drivers/serial/ns16550.c $@
+ ln -sf $(srctree)/drivers/serial/ns16550.c $@
$(obj)/resetvec.S:
@rm -f $@
- ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $@
+ ln -s $(srctree)/$(CPUDIR)/resetvec.S $@
$(obj)/fixed_ivor.S:
@rm -f $@
- ln -sf $(SRCTREE)/$(CPUDIR)/fixed_ivor.S $@
+ ln -sf $(srctree)/$(CPUDIR)/fixed_ivor.S $@
$(obj)/start.S: $(obj)/fixed_ivor.S
@rm -f $@
- ln -sf $(SRCTREE)/$(CPUDIR)/start.S $@
+ ln -sf $(srctree)/$(CPUDIR)/start.S $@
$(obj)/tlb.c:
@rm -f $@
- ln -sf $(SRCTREE)/$(CPUDIR)/tlb.c $@
+ ln -sf $(srctree)/$(CPUDIR)/tlb.c $@
$(obj)/tlb_table.c:
@rm -f $@
- ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $@
+ ln -sf $(srctree)/board/$(BOARDDIR)/tlb.c $@
CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000
PAD_TO := 0xfff01000
-nandobj := $(OBJTREE)/nand_spl/
+nandobj := $(objtree)/nand_spl/
-LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
+LDSCRIPT= $(srctree)/$(CPUDIR)/u-boot-nand_spl.lds
LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
$(LDFLAGS) $(LDFLAGS_FINAL)
asflags-y += -DCONFIG_NAND_SPL
$(obj)/cache.c:
@rm -f $@
- ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $@
+ ln -sf $(srctree)/arch/powerpc/lib/cache.c $@
$(obj)/cpu_init_early.c:
@rm -f $@
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@
+ ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@
$(obj)/spl_minimal.c:
@rm -f $@
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@
+ ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@
$(obj)/fsl_law.c:
@rm -f $@
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $@
+ ln -sf $(srctree)/arch/powerpc/cpu/mpc8xxx/law.c $@
$(obj)/law.c:
@rm -f $@
- ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $@
+ ln -sf $(srctree)/board/$(BOARDDIR)/law.c $@
$(obj)/nand_boot_fsl_elbc.c:
@rm -f $@
- ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@
+ ln -sf $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@
$(obj)/ns16550.c:
@rm -f $@
- ln -sf $(SRCTREE)/drivers/serial/ns16550.c $@
+ ln -sf $(srctree)/drivers/serial/ns16550.c $@
$(obj)/resetvec.S:
@rm -f $@
- ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $@
+ ln -s $(srctree)/$(CPUDIR)/resetvec.S $@
$(obj)/fixed_ivor.S:
@rm -f $@
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@
+ ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@
$(obj)/start.S: $(obj)/fixed_ivor.S
@rm -f $@
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $@
+ ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/start.S $@
$(obj)/tlb.c:
@rm -f $@
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $@
+ ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/tlb.c $@
$(obj)/tlb_table.c:
@rm -f $@
- ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $@
+ ln -sf $(srctree)/board/$(BOARDDIR)/tlb.c $@
# SPDX-License-Identifier: GPL-2.0+
#
-nandobj := $(OBJTREE)/nand_spl/
+include $(srctree)/$(src)/config.mk
-LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
+nandobj := $(objtree)/nand_spl/
+
+LDSCRIPT= $(srctree)/nand_spl/board/$(BOARDDIR)/u-boot.lds
LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
$(LDFLAGS) $(LDFLAGS_FINAL)
asflags-y += -DCONFIG_NAND_SPL
$(obj)/start.S:
@rm -f $@
- ln -s $(SRCTREE)/arch/powerpc/cpu/mpc83xx/start.S $@
+ ln -s $(srctree)/arch/powerpc/cpu/mpc83xx/start.S $@
$(obj)/nand_boot_fsl_elbc.c:
@rm -f $@
- ln -s $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@
+ ln -s $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@
$(obj)/sdram.c:
@rm -f $@
- ln -s $(SRCTREE)/board/$(BOARDDIR)/sdram.c $@
+ ln -s $(srctree)/board/$(BOARDDIR)/sdram.c $@
$(obj)/$(BOARD).c:
@rm -f $@
- ln -s $(SRCTREE)/board/$(BOARDDIR)/$(BOARD).c $@
+ ln -s $(srctree)/board/$(BOARDDIR)/$(BOARD).c $@
$(obj)/ns16550.c:
@rm -f $@
- ln -s $(SRCTREE)/drivers/serial/ns16550.c $@
+ ln -s $(srctree)/drivers/serial/ns16550.c $@
$(obj)/spl_minimal.c:
@rm -f $@
- ln -s $(SRCTREE)/arch/powerpc/cpu/mpc83xx/spl_minimal.c $@
+ ln -s $(srctree)/arch/powerpc/cpu/mpc83xx/spl_minimal.c $@
$(obj)/cache.c:
@rm -f $@
- ln -s $(SRCTREE)/arch/powerpc/lib/cache.c $@
+ ln -s $(srctree)/arch/powerpc/lib/cache.c $@
$(obj)/time.c:
@rm -f $@
- ln -s $(SRCTREE)/arch/powerpc/lib/time.c $@
+ ln -s $(srctree)/arch/powerpc/lib/time.c $@
$(obj)/ticks.S:
@rm -f $@
- ln -s $(SRCTREE)/arch/powerpc/lib/ticks.S $@
+ ln -s $(srctree)/arch/powerpc/lib/ticks.S $@
obj-y := $(objs-before-objcopy:.o=_.o)
OBJCOPYFLAGS := -R .gnu.attributes
-$(obj)/%_.o: $(obj)/%.o
+$(obj)/%_.o: $(obj)/%.o FORCE
$(call if_changed,objcopy)
include scripts/Kbuild.include
-# Added for U-Boot
-# We must include config.mk after Kbuild.include
-# so that some config.mk can use cc-option.
-include config.mk
-
# For backward compatibility check that these variables do not change
save-cflags := $(CFLAGS)
kbuild-file := $(if $(wildcard $(kbuild-dir)/Kbuild),$(kbuild-dir)/Kbuild,$(kbuild-dir)/Makefile)
include $(kbuild-file)
+# Added for U-Boot
+asflags-y += $(PLATFORM_CPPFLAGS)
+ccflags-y += $(PLATFORM_CPPFLAGS)
+cppflags-y += $(PLATFORM_CPPFLAGS)
+
# If the save-* variables changed error out
ifeq ($(KBUILD_NOPEDANTIC),)
ifneq ("$(save-cflags)","$(CFLAGS)")
modname_flags = $(if $(filter 1,$(words $(modname))),\
-D"KBUILD_MODNAME=KBUILD_STR($(call name-fix,$(modname)))")
-# U-Boot also uses $(CPPFLAGS)
-orig_c_flags = $(KBUILD_CPPFLAGS) $(CPPFLAGS) $(KBUILD_CFLAGS) $(KBUILD_SUBDIR_CCFLAGS) \
+orig_c_flags = $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) $(KBUILD_SUBDIR_CCFLAGS) \
$(ccflags-y) $(CFLAGS_$(basetarget).o)
_c_flags = $(filter-out $(CFLAGS_REMOVE_$(basetarget).o), $(orig_c_flags))
-_a_flags = $(KBUILD_CPPFLAGS) $(CPPFLAGS) $(KBUILD_AFLAGS) $(KBUILD_SUBDIR_ASFLAGS) \
+_a_flags = $(KBUILD_CPPFLAGS) $(KBUILD_AFLAGS) $(KBUILD_SUBDIR_ASFLAGS) \
$(asflags-y) $(AFLAGS_$(basetarget).o)
-_cpp_flags = $(KBUILD_CPPFLAGS) $(CPPFLAGS) $(cppflags-y) $(CPPFLAGS_$(@F))
+_cpp_flags = $(KBUILD_CPPFLAGS) $(cppflags-y) $(CPPFLAGS_$(@F))
#
# Enable gcov profiling flags for a file, directory or for all files depending
# Licensed under the terms of the GNU GPL License version 2
use strict;
+use POSIX;
my $P = $0;
$P =~ s@.*/@@g;
my $mailback = 0;
my $summary_file = 0;
my $show_types = 0;
+my $fix = 0;
+my $fix_inplace = 0;
my $root;
my %debug;
+my %camelcase = ();
+my %use_type = ();
+my @use = ();
my %ignore_type = ();
my @ignore = ();
my $help = 0;
my $configuration_file = ".checkpatch.conf";
my $max_line_length = 80;
+my $ignore_perl_version = 0;
+my $minimum_perl_version = 5.10.0;
sub help {
my ($exitcode) = @_;
--terse one line per report
-f, --file treat FILE as regular source file
--subjective, --strict enable more subjective tests
+ --types TYPE(,TYPE2...) show only these comma separated message types
--ignore TYPE(,TYPE2...) ignore various comma separated message types
--max-line-length=n set the maximum line length, if exceeded, warn
--show-types show the message "types" in the output
is all off)
--test-only=WORD report only warnings/errors containing WORD
literally
+ --fix EXPERIMENTAL - may create horrible results
+ If correctable single-line errors exist, create
+ "<inputfile>.EXPERIMENTAL-checkpatch-fixes"
+ with potential errors corrected to the preferred
+ checkpatch style
+ --fix-inplace EXPERIMENTAL - may create horrible results
+ Is the same as --fix, but overwrites the input
+ file. It's your fault if there's no backup or git
+ --ignore-perl-version override checking of perl version. expect
+ runtime errors.
-h, --help, --version display this help and exit
When FILE is - read standard input.
'subjective!' => \$check,
'strict!' => \$check,
'ignore=s' => \@ignore,
+ 'types=s' => \@use,
'show-types!' => \$show_types,
'max-line-length=i' => \$max_line_length,
'root=s' => \$root,
'summary!' => \$summary,
'mailback!' => \$mailback,
'summary-file!' => \$summary_file,
-
+ 'fix!' => \$fix,
+ 'fix-inplace!' => \$fix_inplace,
+ 'ignore-perl-version!' => \$ignore_perl_version,
'debug=s' => \%debug,
'test-only=s' => \$tst_only,
'h|help' => \$help,
help(0) if ($help);
+$fix = 1 if ($fix_inplace);
+
my $exit = 0;
+if ($^V && $^V lt $minimum_perl_version) {
+ printf "$P: requires at least perl version %vd\n", $minimum_perl_version;
+ if (!$ignore_perl_version) {
+ exit(1);
+ }
+}
+
if ($#ARGV < 0) {
print "$P: no input files\n";
exit(1);
}
-@ignore = split(/,/, join(',',@ignore));
-foreach my $word (@ignore) {
- $word =~ s/\s*\n?$//g;
- $word =~ s/^\s*//g;
- $word =~ s/\s+/ /g;
- $word =~ tr/[a-z]/[A-Z]/;
+sub hash_save_array_words {
+ my ($hashRef, $arrayRef) = @_;
- next if ($word =~ m/^\s*#/);
- next if ($word =~ m/^\s*$/);
+ my @array = split(/,/, join(',', @$arrayRef));
+ foreach my $word (@array) {
+ $word =~ s/\s*\n?$//g;
+ $word =~ s/^\s*//g;
+ $word =~ s/\s+/ /g;
+ $word =~ tr/[a-z]/[A-Z]/;
- $ignore_type{$word}++;
+ next if ($word =~ m/^\s*#/);
+ next if ($word =~ m/^\s*$/);
+
+ $hashRef->{$word}++;
+ }
}
+sub hash_show_words {
+ my ($hashRef, $prefix) = @_;
+
+ if ($quiet == 0 && keys %$hashRef) {
+ print "NOTE: $prefix message types:";
+ foreach my $word (sort keys %$hashRef) {
+ print " $word";
+ }
+ print "\n\n";
+ }
+}
+
+hash_save_array_words(\%ignore_type, \@ignore);
+hash_save_array_words(\%use_type, \@use);
+
my $dbg_values = 0;
my $dbg_possible = 0;
my $dbg_type = 0;
__ref|
__rcu
}x;
+our $InitAttributePrefix = qr{__(?:mem|cpu|dev|net_|)};
+our $InitAttributeData = qr{$InitAttributePrefix(?:initdata\b)};
+our $InitAttributeConst = qr{$InitAttributePrefix(?:initconst\b)};
+our $InitAttributeInit = qr{$InitAttributePrefix(?:init\b)};
+our $InitAttribute = qr{$InitAttributeData|$InitAttributeConst|$InitAttributeInit};
# Notes to $Attribute:
# We need \b after 'init' otherwise 'initconst' will cause a false positive in a check
__deprecated|
__read_mostly|
__kprobes|
- __(?:mem|cpu|dev|)(?:initdata|initconst|init\b)|
+ $InitAttribute|
____cacheline_aligned|
____cacheline_aligned_in_smp|
____cacheline_internodealigned_in_smp|
our $Member = qr{->$Ident|\.$Ident|\[[^]]*\]};
our $Lval = qr{$Ident(?:$Member)*};
+our $Int_type = qr{(?i)llu|ull|ll|lu|ul|l|u};
+our $Binary = qr{(?i)0b[01]+$Int_type?};
+our $Hex = qr{(?i)0x[0-9a-f]+$Int_type?};
+our $Int = qr{[0-9]+$Int_type?};
our $Float_hex = qr{(?i)0x[0-9a-f]+p-?[0-9]+[fl]?};
our $Float_dec = qr{(?i)(?:[0-9]+\.[0-9]*|[0-9]*\.[0-9]+)(?:e-?[0-9]+)?[fl]?};
our $Float_int = qr{(?i)[0-9]+e-?[0-9]+[fl]?};
our $Float = qr{$Float_hex|$Float_dec|$Float_int};
-our $Constant = qr{$Float|(?i)(?:0x[0-9a-f]+|[0-9]+)[ul]*};
+our $Constant = qr{$Float|$Binary|$Hex|$Int};
our $Assignment = qr{\*\=|/=|%=|\+=|-=|<<=|>>=|&=|\^=|\|=|=};
our $Compare = qr{<=|>=|==|!=|<|>};
+our $Arithmetic = qr{\+|-|\*|\/|%};
our $Operators = qr{
<=|>=|==|!=|
=>|->|<<|>>|<|>|!|~|
- &&|\|\||,|\^|\+\+|--|&|\||\+|-|\*|\/|%
+ &&|\|\||,|\^|\+\+|--|&|\||$Arithmetic
}x;
our $NonptrType;
+our $NonptrTypeWithAttr;
our $Type;
our $Declare;
our $logFunctions = qr{(?x:
printk(?:_ratelimited|_once|)|
- [a-z0-9]+_(?:printk|emerg|alert|crit|err|warning|warn|notice|info|debug|dbg|vdbg|devel|cont|WARN)(?:_ratelimited|_once|)|
+ (?:[a-z0-9]+_){1,2}(?:printk|emerg|alert|crit|err|warning|warn|notice|info|debug|dbg|vdbg|devel|cont|WARN)(?:_ratelimited|_once|)|
WARN(?:_RATELIMIT|_ONCE|)|
panic|
debug|
printf|
- MODULE_[A-Z_]+
+ puts|
+ MODULE_[A-Z_]+|
+ seq_vprintf|seq_printf|seq_puts
)};
our $signature_tags = qr{(?xi:
Tested-by:|
Reviewed-by:|
Reported-by:|
+ Suggested-by:|
To:|
Cc:
)};
qr{${Ident}_handler},
qr{${Ident}_handler_fn},
);
+our @typeListWithAttr = (
+ @typeList,
+ qr{struct\s+$InitAttribute\s+$Ident},
+ qr{union\s+$InitAttribute\s+$Ident},
+);
+
our @modifierList = (
qr{fastcall},
);
sub build_types {
my $mods = "(?x: \n" . join("|\n ", @modifierList) . "\n)";
my $all = "(?x: \n" . join("|\n ", @typeList) . "\n)";
+ my $allWithAttr = "(?x: \n" . join("|\n ", @typeListWithAttr) . "\n)";
$Modifier = qr{(?:$Attribute|$Sparse|$mods)};
$NonptrType = qr{
(?:$Modifier\s+|const\s+)*
)
(?:\s+$Modifier|\s+const)*
}x;
+ $NonptrTypeWithAttr = qr{
+ (?:$Modifier\s+|const\s+)*
+ (?:
+ (?:typeof|__typeof__)\s*\([^\)]*\)|
+ (?:$typeTypedefs\b)|
+ (?:${allWithAttr}\b)
+ )
+ (?:\s+$Modifier|\s+const)*
+ }x;
$Type = qr{
$NonptrType
(?:(?:\s|\*|\[\])+\s*const|(?:\s|\*|\[\])+|(?:\s*\[\s*\])+)?
}
build_types();
-
our $Typecast = qr{\s*(\(\s*$NonptrType\s*\)){0,1}\s*};
# Using $balanced_parens, $LvalOrFunc, or $FuncArg
return $string;
}
+sub seed_camelcase_file {
+ my ($file) = @_;
+
+ return if (!(-f $file));
+
+ local $/;
+
+ open(my $include_file, '<', "$file")
+ or warn "$P: Can't read '$file' $!\n";
+ my $text = <$include_file>;
+ close($include_file);
+
+ my @lines = split('\n', $text);
+
+ foreach my $line (@lines) {
+ next if ($line !~ /(?:[A-Z][a-z]|[a-z][A-Z])/);
+ if ($line =~ /^[ \t]*(?:#[ \t]*define|typedef\s+$Type)\s+(\w*(?:[A-Z][a-z]|[a-z][A-Z])\w*)/) {
+ $camelcase{$1} = 1;
+ } elsif ($line =~ /^\s*$Declare\s+(\w*(?:[A-Z][a-z]|[a-z][A-Z])\w*)\s*[\(\[,;]/) {
+ $camelcase{$1} = 1;
+ } elsif ($line =~ /^\s*(?:union|struct|enum)\s+(\w*(?:[A-Z][a-z]|[a-z][A-Z])\w*)\s*[;\{]/) {
+ $camelcase{$1} = 1;
+ }
+ }
+}
+
+my $camelcase_seeded = 0;
+sub seed_camelcase_includes {
+ return if ($camelcase_seeded);
+
+ my $files;
+ my $camelcase_cache = "";
+ my @include_files = ();
+
+ $camelcase_seeded = 1;
+
+ if (-e ".git") {
+ my $git_last_include_commit = `git log --no-merges --pretty=format:"%h%n" -1 -- include`;
+ chomp $git_last_include_commit;
+ $camelcase_cache = ".checkpatch-camelcase.git.$git_last_include_commit";
+ } else {
+ my $last_mod_date = 0;
+ $files = `find $root/include -name "*.h"`;
+ @include_files = split('\n', $files);
+ foreach my $file (@include_files) {
+ my $date = POSIX::strftime("%Y%m%d%H%M",
+ localtime((stat $file)[9]));
+ $last_mod_date = $date if ($last_mod_date < $date);
+ }
+ $camelcase_cache = ".checkpatch-camelcase.date.$last_mod_date";
+ }
+
+ if ($camelcase_cache ne "" && -f $camelcase_cache) {
+ open(my $camelcase_file, '<', "$camelcase_cache")
+ or warn "$P: Can't read '$camelcase_cache' $!\n";
+ while (<$camelcase_file>) {
+ chomp;
+ $camelcase{$_} = 1;
+ }
+ close($camelcase_file);
+
+ return;
+ }
+
+ if (-e ".git") {
+ $files = `git ls-files "include/*.h"`;
+ @include_files = split('\n', $files);
+ }
+
+ foreach my $file (@include_files) {
+ seed_camelcase_file($file);
+ }
+
+ if ($camelcase_cache ne "") {
+ unlink glob ".checkpatch-camelcase.*";
+ open(my $camelcase_file, '>', "$camelcase_cache")
+ or warn "$P: Can't write '$camelcase_cache' $!\n";
+ foreach (sort { lc($a) cmp lc($b) } keys(%camelcase)) {
+ print $camelcase_file ("$_\n");
+ }
+ close($camelcase_file);
+ }
+}
+
$chk_signoff = 0 if ($file);
my @rawlines = ();
my @lines = ();
+my @fixed = ();
my $vname;
for my $filename (@ARGV) {
my $FILE;
}
@rawlines = ();
@lines = ();
+ @fixed = ();
}
exit($exit);
my ($root) = @_;
my @tree_check = (
- "COPYING", "CREDITS", "Kbuild", "Makefile",
+ "COPYING", "CREDITS", "Kbuild", "MAINTAINERS", "Makefile",
"README", "Documentation", "arch", "include", "drivers",
"fs", "init", "ipc", "kernel", "lib", "scripts",
);
$comment = $2 if defined $2;
$formatted_email =~ s/$address.*$//;
$name = $formatted_email;
- $name =~ s/^\s+|\s+$//g;
+ $name = trim($name);
$name =~ s/^\"|\"$//g;
# If there's a name left after stripping spaces and
# leading quotes, and the address doesn't have both
}
}
- $name =~ s/^\s+|\s+$//g;
+ $name = trim($name);
$name =~ s/^\"|\"$//g;
- $address =~ s/^\s+|\s+$//g;
+ $address = trim($address);
$address =~ s/^\<|\>$//g;
if ($name =~ /[^\w \-]/i) { ##has "must quote" chars
my $formatted_email;
- $name =~ s/^\s+|\s+$//g;
+ $name = trim($name);
$name =~ s/^\"|\"$//g;
- $address =~ s/^\s+|\s+$//g;
+ $address = trim($address);
if ($name =~ /[^\w \-]/i) { ##has "must quote" chars
$name =~ s/(?<!\\)"/\\"/g; ##escape quotes
return $res;
}
+sub get_quoted_string {
+ my ($line, $rawline) = @_;
+
+ return "" if ($line !~ m/(\"[X]+\")/g);
+ return substr($rawline, $-[0], $+[0] - $-[0]);
+}
+
sub ctx_statement_block {
my ($linenr, $remain, $off) = @_;
my $line = $linenr - 1;
my $prefix = '';
sub show_type {
- return !defined $ignore_type{$_[0]};
+ return defined $use_type{$_[0]} if (scalar keys %use_type > 0);
+
+ return !defined $ignore_type{$_[0]};
}
sub report {
if (report("ERROR", $_[0], $_[1])) {
our $clean = 0;
our $cnt_error++;
+ return 1;
}
+ return 0;
}
sub WARN {
if (report("WARNING", $_[0], $_[1])) {
our $clean = 0;
our $cnt_warn++;
+ return 1;
}
+ return 0;
}
sub CHK {
if ($check && report("CHECK", $_[0], $_[1])) {
our $clean = 0;
our $cnt_chk++;
+ return 1;
}
+ return 0;
}
sub check_absolute_file {
}
}
+sub trim {
+ my ($string) = @_;
+
+ $string =~ s/^\s+|\s+$//g;
+
+ return $string;
+}
+
+sub ltrim {
+ my ($string) = @_;
+
+ $string =~ s/^\s+//;
+
+ return $string;
+}
+
+sub rtrim {
+ my ($string) = @_;
+
+ $string =~ s/\s+$//;
+
+ return $string;
+}
+
+sub string_find_replace {
+ my ($string, $find, $replace) = @_;
+
+ $string =~ s/$find/$replace/g;
+
+ return $string;
+}
+
+sub tabify {
+ my ($leading) = @_;
+
+ my $source_indent = 8;
+ my $max_spaces_before_tab = $source_indent - 1;
+ my $spaces_to_tab = " " x $source_indent;
+
+ #convert leading spaces to tabs
+ 1 while $leading =~ s@^([\t]*)$spaces_to_tab@$1\t@g;
+ #Remove spaces before a tab
+ 1 while $leading =~ s@^([\t]*)( {1,$max_spaces_before_tab})\t@$1\t@g;
+
+ return "$leading";
+}
+
sub pos_last_openparen {
my ($line) = @_;
my %suppress_export;
my $suppress_statement = 0;
- my %camelcase = ();
+ my %signatures = ();
# Pre-scan the patch sanitizing the lines.
# Pre-scan the patch looking for any __setup documentation.
my @setup_docs = ();
my $setup_docs = 0;
+ my $camelcase_file_seeded = 0;
+
sanitise_line_reset();
my $line;
foreach my $rawline (@rawlines) {
$linenr++;
$line = $rawline;
+ push(@fixed, $rawline) if ($fix);
+
if ($rawline=~/^\+\+\+\s+(\S+)/) {
$setup_docs = 0;
if ($1 =~ m@Documentation/kernel-parameters.txt$@) {
$linenr = 0;
foreach my $line (@lines) {
$linenr++;
+ my $sline = $line; #copy of $line
+ $sline =~ s/$;/ /g; #with comments as spaces
my $rawline = $rawlines[$linenr - 1];
# extract the filename as it passes
if ($line =~ /^diff --git.*?(\S+)$/) {
$realfile = $1;
- $realfile =~ s@^([^/]*)/@@;
+ $realfile =~ s@^([^/]*)/@@ if (!$file);
$in_commit_log = 0;
} elsif ($line =~ /^\+\+\+\s+(\S+)/) {
$realfile = $1;
- $realfile =~ s@^([^/]*)/@@;
+ $realfile =~ s@^([^/]*)/@@ if (!$file);
$in_commit_log = 0;
$p1_prefix = $1;
# Check for incorrect file permissions
if ($line =~ /^new (file )?mode.*[7531]\d{0,2}$/) {
my $permhere = $here . "FILE: $realfile\n";
- if ($realfile =~ /(Makefile|Kconfig|\.c|\.h|\.S|\.tmpl)$/) {
+ if ($realfile !~ m@scripts/@ &&
+ $realfile !~ /\.(py|pl|awk|sh)$/) {
ERROR("EXECUTE_PERMISSIONS",
"do not set execute permissions for source files\n" . $permhere);
}
"Non-standard signature: $sign_off\n" . $herecurr);
}
if (defined $space_before && $space_before ne "") {
- WARN("BAD_SIGN_OFF",
- "Do not use whitespace before $ucfirst_sign_off\n" . $herecurr);
+ if (WARN("BAD_SIGN_OFF",
+ "Do not use whitespace before $ucfirst_sign_off\n" . $herecurr) &&
+ $fix) {
+ $fixed[$linenr - 1] =
+ "$ucfirst_sign_off $email";
+ }
}
if ($sign_off =~ /-by:$/i && $sign_off ne $ucfirst_sign_off) {
- WARN("BAD_SIGN_OFF",
- "'$ucfirst_sign_off' is the preferred signature form\n" . $herecurr);
+ if (WARN("BAD_SIGN_OFF",
+ "'$ucfirst_sign_off' is the preferred signature form\n" . $herecurr) &&
+ $fix) {
+ $fixed[$linenr - 1] =
+ "$ucfirst_sign_off $email";
+ }
+
}
if (!defined $space_after || $space_after ne " ") {
- WARN("BAD_SIGN_OFF",
- "Use a single space after $ucfirst_sign_off\n" . $herecurr);
+ if (WARN("BAD_SIGN_OFF",
+ "Use a single space after $ucfirst_sign_off\n" . $herecurr) &&
+ $fix) {
+ $fixed[$linenr - 1] =
+ "$ucfirst_sign_off $email";
+ }
}
my ($email_name, $email_address, $comment) = parse_email($email);
"email address '$email' might be better as '$suggested_email$comment'\n" . $herecurr);
}
}
+
+# Check for duplicate signatures
+ my $sig_nospace = $line;
+ $sig_nospace =~ s/\s//g;
+ $sig_nospace = lc($sig_nospace);
+ if (defined $signatures{$sig_nospace}) {
+ WARN("BAD_SIGN_OFF",
+ "Duplicate signature\n" . $herecurr);
+ } else {
+ $signatures{$sig_nospace} = 1;
+ }
}
# Check for wrappage within a valid hunk of the file
#trailing whitespace
if ($line =~ /^\+.*\015/) {
my $herevet = "$here\n" . cat_vet($rawline) . "\n";
- ERROR("DOS_LINE_ENDINGS",
- "DOS line endings\n" . $herevet);
-
+ if (ERROR("DOS_LINE_ENDINGS",
+ "DOS line endings\n" . $herevet) &&
+ $fix) {
+ $fixed[$linenr - 1] =~ s/[\s\015]+$//;
+ }
} elsif ($rawline =~ /^\+.*\S\s+$/ || $rawline =~ /^\+\s+$/) {
my $herevet = "$here\n" . cat_vet($rawline) . "\n";
- ERROR("TRAILING_WHITESPACE",
- "trailing whitespace\n" . $herevet);
+ if (ERROR("TRAILING_WHITESPACE",
+ "trailing whitespace\n" . $herevet) &&
+ $fix) {
+ $fixed[$linenr - 1] =~ s/\s+$//;
+ }
+
$rpt_cleaners = 1;
}
+# Check for FSF mailing addresses.
+ if ($rawline =~ /\bwrite to the Free/i ||
+ $rawline =~ /\b59\s+Temple\s+Pl/i ||
+ $rawline =~ /\b51\s+Franklin\s+St/i) {
+ my $herevet = "$here\n" . cat_vet($rawline) . "\n";
+ my $msg_type = \&ERROR;
+ $msg_type = \&CHK if ($file);
+ &{$msg_type}("FSF_MAILING_ADDRESS",
+ "Do not include the paragraph about writing to the Free Software Foundation's mailing address from the sample GPL notice. The FSF has changed addresses in the past, and may do so again. Linux already includes a copy of the GPL.\n" . $herevet)
+ }
+
# check for Kconfig help text having a real description
# Only applies when adding the entry originally, after that we do not have
# sufficient context to determine whether it is indeed long enough.
"Use of $flag is deprecated, please use \`$replacement->{$flag} instead.\n" . $herecurr) if ($replacement->{$flag});
}
+# check for DT compatible documentation
+ if (defined $root && $realfile =~ /\.dts/ &&
+ $rawline =~ /^\+\s*compatible\s*=/) {
+ my @compats = $rawline =~ /\"([a-zA-Z0-9\-\,\.\+_]+)\"/g;
+
+ foreach my $compat (@compats) {
+ my $compat2 = $compat;
+ my $dt_path = $root . "/Documentation/devicetree/bindings/";
+ $compat2 =~ s/\,[a-z]*\-/\,<\.\*>\-/;
+ `grep -Erq "$compat|$compat2" $dt_path`;
+ if ( $? >> 8 ) {
+ WARN("UNDOCUMENTED_DT_STRING",
+ "DT compatible string \"$compat\" appears un-documented -- check $dt_path\n" . $herecurr);
+ }
+
+ my $vendor = $compat;
+ my $vendor_path = $dt_path . "vendor-prefixes.txt";
+ next if (! -f $vendor_path);
+ $vendor =~ s/^([a-zA-Z0-9]+)\,.*/$1/;
+ `grep -Eq "$vendor" $vendor_path`;
+ if ( $? >> 8 ) {
+ WARN("UNDOCUMENTED_DT_STRING",
+ "DT compatible string vendor \"$vendor\" appears un-documented -- check $vendor_path\n" . $herecurr);
+ }
+ }
+ }
+
# check we are in a valid source file if not then ignore this hunk
next if ($realfile !~ /\.(h|c|s|S|pl|sh)$/);
}
# Check for user-visible strings broken across lines, which breaks the ability
-# to grep for the string. Limited to strings used as parameters (those
-# following an open parenthesis), which almost completely eliminates false
-# positives, as well as warning only once per parameter rather than once per
-# line of the string. Make an exception when the previous string ends in a
-# newline (multiple lines in one string constant) or \n\t (common in inline
-# assembly to indent the instruction on the following line).
+# to grep for the string. Make exceptions when the previous string ends in a
+# newline (multiple lines in one string constant) or '\t', '\r', ';', or '{'
+# (common in inline assembly) or is a octal \123 or hexadecimal \xaf value
if ($line =~ /^\+\s*"/ &&
$prevline =~ /"\s*$/ &&
- $prevline =~ /\(/ &&
- $prevrawline !~ /\\n(?:\\t)*"\s*$/) {
+ $prevrawline !~ /(?:\\(?:[ntr]|[0-7]{1,3}|x[0-9a-fA-F]{1,2})|;\s*|\{\s*)"\s*$/) {
WARN("SPLIT_STRING",
"quoted string split across lines\n" . $hereprev);
}
# check for spaces before a quoted newline
if ($rawline =~ /^.*\".*\s\\n/) {
- WARN("QUOTED_WHITESPACE_BEFORE_NEWLINE",
- "unnecessary whitespace before a quoted newline\n" . $herecurr);
+ if (WARN("QUOTED_WHITESPACE_BEFORE_NEWLINE",
+ "unnecessary whitespace before a quoted newline\n" . $herecurr) &&
+ $fix) {
+ $fixed[$linenr - 1] =~ s/^(\+.*\".*)\s+\\n/$1\\n/;
+ }
+
}
# check for adding lines without a newline.
if ($rawline =~ /^\+\s* \t\s*\S/ ||
$rawline =~ /^\+\s* \s*/) {
my $herevet = "$here\n" . cat_vet($rawline) . "\n";
- ERROR("CODE_INDENT",
- "code indent should use tabs where possible\n" . $herevet);
$rpt_cleaners = 1;
+ if (ERROR("CODE_INDENT",
+ "code indent should use tabs where possible\n" . $herevet) &&
+ $fix) {
+ $fixed[$linenr - 1] =~ s/^\+([ \t]+)/"\+" . tabify($1)/e;
+ }
}
# check for space before tabs.
if ($rawline =~ /^\+/ && $rawline =~ / \t/) {
my $herevet = "$here\n" . cat_vet($rawline) . "\n";
- WARN("SPACE_BEFORE_TAB",
- "please, no space before tabs\n" . $herevet);
+ if (WARN("SPACE_BEFORE_TAB",
+ "please, no space before tabs\n" . $herevet) &&
+ $fix) {
+ while ($fixed[$linenr - 1] =~
+ s/(^\+.*) {8,8}+\t/$1\t\t/) {}
+ while ($fixed[$linenr - 1] =~
+ s/(^\+.*) +\t/$1\t/) {}
+ }
}
# check for && or || at the start of a line
if ($newindent ne $goodtabindent &&
$newindent ne $goodspaceindent) {
- CHK("PARENTHESIS_ALIGNMENT",
- "Alignment should match open parenthesis\n" . $hereprev);
+
+ if (CHK("PARENTHESIS_ALIGNMENT",
+ "Alignment should match open parenthesis\n" . $hereprev) &&
+ $fix && $line =~ /^\+/) {
+ $fixed[$linenr - 1] =~
+ s/^\+[ \t]*/\+$goodtabindent/;
+ }
}
}
}
- if ($line =~ /^\+.*\*[ \t]*\)[ \t]+/) {
- CHK("SPACING",
- "No space is necessary after a cast\n" . $hereprev);
+ if ($line =~ /^\+.*\*[ \t]*\)[ \t]+(?!$Assignment|$Arithmetic)/) {
+ if (CHK("SPACING",
+ "No space is necessary after a cast\n" . $hereprev) &&
+ $fix) {
+ $fixed[$linenr - 1] =~
+ s/^(\+.*\*[ \t]*\))[ \t]+/$1/;
+ }
}
if ($realfile =~ m@^(drivers/net/|net/)@ &&
- $rawline =~ /^\+[ \t]*\/\*[ \t]*$/ &&
- $prevrawline =~ /^\+[ \t]*$/) {
+ $prevrawline =~ /^\+[ \t]*\/\*[ \t]*$/ &&
+ $rawline =~ /^\+[ \t]*\*/) {
WARN("NETWORKING_BLOCK_COMMENT_STYLE",
"networking block comments don't use an empty /* line, use /* Comment...\n" . $hereprev);
}
+ if ($realfile =~ m@^(drivers/net/|net/)@ &&
+ $prevrawline =~ /^\+[ \t]*\/\*/ && #starting /*
+ $prevrawline !~ /\*\/[ \t]*$/ && #no trailing */
+ $rawline =~ /^\+/ && #line is new
+ $rawline !~ /^\+[ \t]*\*/) { #no leading *
+ WARN("NETWORKING_BLOCK_COMMENT_STYLE",
+ "networking block comments start with * on subsequent lines\n" . $hereprev);
+ }
+
if ($realfile =~ m@^(drivers/net/|net/)@ &&
$rawline !~ m@^\+[ \t]*\*/[ \t]*$@ && #trailing */
$rawline !~ m@^\+.*/\*.*\*/[ \t]*$@ && #inline /*...*/
# 1) within comments
# 2) indented preprocessor commands
# 3) hanging labels
- if ($rawline =~ /^\+ / && $line !~ /\+ *(?:$;|#|$Ident:)/) {
+ if ($rawline =~ /^\+ / && $line !~ /^\+ *(?:$;|#|$Ident:)/) {
my $herevet = "$here\n" . cat_vet($rawline) . "\n";
- WARN("LEADING_SPACE",
- "please, no spaces at the start of a line\n" . $herevet);
+ if (WARN("LEADING_SPACE",
+ "please, no spaces at the start of a line\n" . $herevet) &&
+ $fix) {
+ $fixed[$linenr - 1] =~ s/^\+([ \t]+)/"\+" . tabify($1)/e;
+ }
}
# check we are in a valid C source file if not then ignore this hunk
$realline_next);
#print "LINE<$line>\n";
if ($linenr >= $suppress_statement &&
- $realcnt && $line =~ /.\s*\S/) {
+ $realcnt && $sline =~ /.\s*\S/) {
($stat, $cond, $line_nr_next, $remain_next, $off_next) =
ctx_statement_block($linenr, $realcnt, 0);
$stat =~ s/\n./\n /g;
$prev_values = substr($curr_values, -1);
#ignore lines not being added
- if ($line=~/^[^\+]/) {next;}
+ next if ($line =~ /^[^\+]/);
# TEST: allow direct testing of the type matcher.
if ($dbg_type) {
# no C99 // comments
if ($line =~ m{//}) {
- ERROR("C99_COMMENTS",
- "do not use C99 // comments\n" . $herecurr);
+ if (ERROR("C99_COMMENTS",
+ "do not use C99 // comments\n" . $herecurr) &&
+ $fix) {
+ my $line = $fixed[$linenr - 1];
+ if ($line =~ /\/\/(.*)$/) {
+ my $comment = trim($1);
+ $fixed[$linenr - 1] =~ s@\/\/(.*)$@/\* $comment \*/@;
+ }
+ }
}
# Remove C99 comments.
$line =~ s@//.*@@;
}
# check for global initialisers.
- if ($line =~ /^.$Type\s*$Ident\s*(?:\s+$Modifier)*\s*=\s*(0|NULL|false)\s*;/) {
- ERROR("GLOBAL_INITIALISERS",
- "do not initialise globals to 0 or NULL\n" .
- $herecurr);
+ if ($line =~ /^\+(\s*$Type\s*$Ident\s*(?:\s+$Modifier))*\s*=\s*(0|NULL|false)\s*;/) {
+ if (ERROR("GLOBAL_INITIALISERS",
+ "do not initialise globals to 0 or NULL\n" .
+ $herecurr) &&
+ $fix) {
+ $fixed[$linenr - 1] =~ s/($Type\s*$Ident\s*(?:\s+$Modifier))*\s*=\s*(0|NULL|false)\s*;/$1;/;
+ }
}
# check for static initialisers.
- if ($line =~ /\bstatic\s.*=\s*(0|NULL|false)\s*;/) {
- ERROR("INITIALISED_STATIC",
- "do not initialise statics to 0 or NULL\n" .
- $herecurr);
+ if ($line =~ /^\+.*\bstatic\s.*=\s*(0|NULL|false)\s*;/) {
+ if (ERROR("INITIALISED_STATIC",
+ "do not initialise statics to 0 or NULL\n" .
+ $herecurr) &&
+ $fix) {
+ $fixed[$linenr - 1] =~ s/(\bstatic\s.*?)\s*=\s*(0|NULL|false)\s*;/$1;/;
+ }
}
# check for static const char * arrays.
$herecurr);
}
-# check for declarations of struct pci_device_id
- if ($line =~ /\bstruct\s+pci_device_id\s+\w+\s*\[\s*\]\s*\=\s*\{/) {
- WARN("DEFINE_PCI_DEVICE_TABLE",
- "Use DEFINE_PCI_DEVICE_TABLE for struct pci_device_id\n" . $herecurr);
+# check for function declarations without arguments like "int foo()"
+ if ($line =~ /(\b$Type\s+$Ident)\s*\(\s*\)/) {
+ if (ERROR("FUNCTION_WITHOUT_ARGS",
+ "Bad function definition - $1() should probably be $1(void)\n" . $herecurr) &&
+ $fix) {
+ $fixed[$linenr - 1] =~ s/(\b($Type)\s+($Ident))\s*\(\s*\)/$2 $3(void)/;
+ }
+ }
+
+# check for uses of DEFINE_PCI_DEVICE_TABLE
+ if ($line =~ /\bDEFINE_PCI_DEVICE_TABLE\s*\(\s*(\w+)\s*\)\s*=/) {
+ if (WARN("DEFINE_PCI_DEVICE_TABLE",
+ "Prefer struct pci_device_id over deprecated DEFINE_PCI_DEVICE_TABLE\n" . $herecurr) &&
+ $fix) {
+ $fixed[$linenr - 1] =~ s/\b(?:static\s+|)DEFINE_PCI_DEVICE_TABLE\s*\(\s*(\w+)\s*\)\s*=\s*/static const struct pci_device_id $1\[\] = /;
+ }
}
# check for new typedefs, only function parameters and sparse annotations
# (char*[ const])
while ($line =~ m{(\($NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)\))}g) {
#print "AA<$1>\n";
- my ($from, $to) = ($2, $2);
+ my ($ident, $from, $to) = ($1, $2, $2);
# Should start with a space.
$to =~ s/^(\S)/ $1/;
while ($to =~ s/\*\s+\*/\*\*/) {
}
- #print "from<$from> to<$to>\n";
+## print "1: from<$from> to<$to> ident<$ident>\n";
if ($from ne $to) {
- ERROR("POINTER_LOCATION",
- "\"(foo$from)\" should be \"(foo$to)\"\n" . $herecurr);
+ if (ERROR("POINTER_LOCATION",
+ "\"(foo$from)\" should be \"(foo$to)\"\n" . $herecurr) &&
+ $fix) {
+ my $sub_from = $ident;
+ my $sub_to = $ident;
+ $sub_to =~ s/\Q$from\E/$to/;
+ $fixed[$linenr - 1] =~
+ s@\Q$sub_from\E@$sub_to@;
+ }
}
}
while ($line =~ m{(\b$NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)($Ident))}g) {
#print "BB<$1>\n";
- my ($from, $to, $ident) = ($2, $2, $3);
+ my ($match, $from, $to, $ident) = ($1, $2, $2, $3);
# Should start with a space.
$to =~ s/^(\S)/ $1/;
# Modifiers should have spaces.
$to =~ s/(\b$Modifier$)/$1 /;
- #print "from<$from> to<$to> ident<$ident>\n";
+## print "2: from<$from> to<$to> ident<$ident>\n";
if ($from ne $to && $ident !~ /^$Modifier$/) {
- ERROR("POINTER_LOCATION",
- "\"foo${from}bar\" should be \"foo${to}bar\"\n" . $herecurr);
+ if (ERROR("POINTER_LOCATION",
+ "\"foo${from}bar\" should be \"foo${to}bar\"\n" . $herecurr) &&
+ $fix) {
+
+ my $sub_from = $match;
+ my $sub_to = $match;
+ $sub_to =~ s/\Q$from\E/$to/;
+ $fixed[$linenr - 1] =~
+ s@\Q$sub_from\E@$sub_to@;
+ }
}
}
}
if ($line =~ /\bpr_warning\s*\(/) {
- WARN("PREFER_PR_LEVEL",
- "Prefer pr_warn(... to pr_warning(...\n" . $herecurr);
+ if (WARN("PREFER_PR_LEVEL",
+ "Prefer pr_warn(... to pr_warning(...\n" . $herecurr) &&
+ $fix) {
+ $fixed[$linenr - 1] =~
+ s/\bpr_warning\b/pr_warn/;
+ }
}
if ($line =~ /\bdev_printk\s*\(\s*KERN_([A-Z]+)/) {
}
# missing space after union, struct or enum definition
- if ($line =~ /^.\s*(?:typedef\s+)?(enum|union|struct)(?:\s+$Ident)?(?:\s+$Ident)?[=\{]/) {
- WARN("SPACING",
- "missing space after $1 definition\n" . $herecurr);
+ if ($line =~ /^.\s*(?:typedef\s+)?(enum|union|struct)(?:\s+$Ident){1,2}[=\{]/) {
+ if (WARN("SPACING",
+ "missing space after $1 definition\n" . $herecurr) &&
+ $fix) {
+ $fixed[$linenr - 1] =~
+ s/^(.\s*(?:typedef\s+)?(?:enum|union|struct)(?:\s+$Ident){1,2})([=\{])/$1 $2/;
+ }
+ }
+
+# Function pointer declarations
+# check spacing between type, funcptr, and args
+# canonical declaration is "type (*funcptr)(args...)"
+#
+# the $Declare variable will capture all spaces after the type
+# so check it for trailing missing spaces or multiple spaces
+ if ($line =~ /^.\s*($Declare)\((\s*)\*(\s*)$Ident(\s*)\)(\s*)\(/) {
+ my $declare = $1;
+ my $pre_pointer_space = $2;
+ my $post_pointer_space = $3;
+ my $funcname = $4;
+ my $post_funcname_space = $5;
+ my $pre_args_space = $6;
+
+ if ($declare !~ /\s$/) {
+ WARN("SPACING",
+ "missing space after return type\n" . $herecurr);
+ }
+
+# unnecessary space "type (*funcptr)(args...)"
+ elsif ($declare =~ /\s{2,}$/) {
+ WARN("SPACING",
+ "Multiple spaces after return type\n" . $herecurr);
+ }
+
+# unnecessary space "type ( *funcptr)(args...)"
+ if (defined $pre_pointer_space &&
+ $pre_pointer_space =~ /^\s/) {
+ WARN("SPACING",
+ "Unnecessary space after function pointer open parenthesis\n" . $herecurr);
+ }
+
+# unnecessary space "type (* funcptr)(args...)"
+ if (defined $post_pointer_space &&
+ $post_pointer_space =~ /^\s/) {
+ WARN("SPACING",
+ "Unnecessary space before function pointer name\n" . $herecurr);
+ }
+
+# unnecessary space "type (*funcptr )(args...)"
+ if (defined $post_funcname_space &&
+ $post_funcname_space =~ /^\s/) {
+ WARN("SPACING",
+ "Unnecessary space after function pointer name\n" . $herecurr);
+ }
+
+# unnecessary space "type (*funcptr) (args...)"
+ if (defined $pre_args_space &&
+ $pre_args_space =~ /^\s/) {
+ WARN("SPACING",
+ "Unnecessary space before function pointer arguments\n" . $herecurr);
+ }
+
+ if (show_type("SPACING") && $fix) {
+ $fixed[$linenr - 1] =~
+ s/^(.\s*$Declare)\(\s*\*\s*($Ident)\s*\)\s*\(/rtrim($1) . " " . "\(\*$2\)\("/ex;
+ }
}
# check for spacing round square brackets; allowed:
if ($prefix !~ /$Type\s+$/ &&
($where != 0 || $prefix !~ /^.\s+$/) &&
$prefix !~ /[{,]\s+$/) {
- ERROR("BRACKET_SPACE",
- "space prohibited before open square bracket '['\n" . $herecurr);
+ if (ERROR("BRACKET_SPACE",
+ "space prohibited before open square bracket '['\n" . $herecurr) &&
+ $fix) {
+ $fixed[$linenr - 1] =~
+ s/^(\+.*?)\s+\[/$1\[/;
+ }
}
}
__attribute__|format|__extension__|
asm|__asm__)$/x)
{
-
# cpp #define statements have non-optional spaces, ie
# if there is a space between the name and the open
# parenthesis it is simply not a parameter group.
} elsif ($ctx =~ /$Type$/) {
} else {
- WARN("SPACING",
- "space prohibited between function name and open parenthesis '('\n" . $herecurr);
+ if (WARN("SPACING",
+ "space prohibited between function name and open parenthesis '('\n" . $herecurr) &&
+ $fix) {
+ $fixed[$linenr - 1] =~
+ s/\b$name\s+\(/$name\(/;
+ }
}
}
-# check for whitespace before a non-naked semicolon
- if ($line =~ /^\+.*\S\s+;/) {
- CHK("SPACING",
- "space prohibited before semicolon\n" . $herecurr);
- }
-
# Check operator spacing.
if (!($line=~/\#\s*include/)) {
+ my $fixed_line = "";
+ my $line_fixed = 0;
+
my $ops = qr{
<<=|>>=|<=|>=|==|!=|
\+=|-=|\*=|\/=|%=|\^=|\|=|&=|
=>|->|<<|>>|<|>|=|!|~|
&&|\|\||,|\^|\+\+|--|&|\||\+|-|\*|\/|%|
- \?|:
+ \?:|\?|:
}x;
my @elements = split(/($ops|;)/, $opline);
+
+## print("element count: <" . $#elements . ">\n");
+## foreach my $el (@elements) {
+## print("el: <$el>\n");
+## }
+
+ my @fix_elements = ();
my $off = 0;
+ foreach my $el (@elements) {
+ push(@fix_elements, substr($rawline, $off, length($el)));
+ $off += length($el);
+ }
+
+ $off = 0;
+
my $blank = copy_spacing($opline);
+ my $last_after = -1;
for (my $n = 0; $n < $#elements; $n += 2) {
+
+ my $good = $fix_elements[$n] . $fix_elements[$n + 1];
+
+## print("n: <$n> good: <$good>\n");
+
$off += length($elements[$n]);
# Pick up the preceding and succeeding characters.
} elsif ($op eq ';') {
if ($ctx !~ /.x[WEBC]/ &&
$cc !~ /^\\/ && $cc !~ /^;/) {
- ERROR("SPACING",
- "space required after that '$op' $at\n" . $hereptr);
+ if (ERROR("SPACING",
+ "space required after that '$op' $at\n" . $hereptr)) {
+ $good = $fix_elements[$n] . trim($fix_elements[$n + 1]) . " ";
+ $line_fixed = 1;
+ }
}
# // is a comment
# : when part of a bitfield
} elsif ($op eq '->' || $opv eq ':B') {
if ($ctx =~ /Wx.|.xW/) {
- ERROR("SPACING",
- "spaces prohibited around that '$op' $at\n" . $hereptr);
+ if (ERROR("SPACING",
+ "spaces prohibited around that '$op' $at\n" . $hereptr)) {
+ $good = rtrim($fix_elements[$n]) . trim($fix_elements[$n + 1]);
+ if (defined $fix_elements[$n + 2]) {
+ $fix_elements[$n + 2] =~ s/^\s+//;
+ }
+ $line_fixed = 1;
+ }
}
# , must have a space on the right.
} elsif ($op eq ',') {
if ($ctx !~ /.x[WEC]/ && $cc !~ /^}/) {
- ERROR("SPACING",
- "space required after that '$op' $at\n" . $hereptr);
+ if (ERROR("SPACING",
+ "space required after that '$op' $at\n" . $hereptr)) {
+ $good = $fix_elements[$n] . trim($fix_elements[$n + 1]) . " ";
+ $line_fixed = 1;
+ $last_after = $n;
+ }
}
# '*' as part of a type definition -- reported already.
$opv eq '*U' || $opv eq '-U' ||
$opv eq '&U' || $opv eq '&&U') {
if ($ctx !~ /[WEBC]x./ && $ca !~ /(?:\)|!|~|\*|-|\&|\||\+\+|\-\-|\{)$/) {
- ERROR("SPACING",
- "space required before that '$op' $at\n" . $hereptr);
+ if (ERROR("SPACING",
+ "space required before that '$op' $at\n" . $hereptr)) {
+ if ($n != $last_after + 2) {
+ $good = $fix_elements[$n] . " " . ltrim($fix_elements[$n + 1]);
+ $line_fixed = 1;
+ }
+ }
}
if ($op eq '*' && $cc =~/\s*$Modifier\b/) {
# A unary '*' may be const
} elsif ($ctx =~ /.xW/) {
- ERROR("SPACING",
- "space prohibited after that '$op' $at\n" . $hereptr);
+ if (ERROR("SPACING",
+ "space prohibited after that '$op' $at\n" . $hereptr)) {
+ $good = $fix_elements[$n] . rtrim($fix_elements[$n + 1]);
+ if (defined $fix_elements[$n + 2]) {
+ $fix_elements[$n + 2] =~ s/^\s+//;
+ }
+ $line_fixed = 1;
+ }
}
# unary ++ and unary -- are allowed no space on one side.
} elsif ($op eq '++' or $op eq '--') {
if ($ctx !~ /[WEOBC]x[^W]/ && $ctx !~ /[^W]x[WOBEC]/) {
- ERROR("SPACING",
- "space required one side of that '$op' $at\n" . $hereptr);
+ if (ERROR("SPACING",
+ "space required one side of that '$op' $at\n" . $hereptr)) {
+ $good = $fix_elements[$n] . trim($fix_elements[$n + 1]) . " ";
+ $line_fixed = 1;
+ }
}
if ($ctx =~ /Wx[BE]/ ||
($ctx =~ /Wx./ && $cc =~ /^;/)) {
- ERROR("SPACING",
- "space prohibited before that '$op' $at\n" . $hereptr);
+ if (ERROR("SPACING",
+ "space prohibited before that '$op' $at\n" . $hereptr)) {
+ $good = rtrim($fix_elements[$n]) . trim($fix_elements[$n + 1]);
+ $line_fixed = 1;
+ }
}
if ($ctx =~ /ExW/) {
- ERROR("SPACING",
- "space prohibited after that '$op' $at\n" . $hereptr);
+ if (ERROR("SPACING",
+ "space prohibited after that '$op' $at\n" . $hereptr)) {
+ $good = $fix_elements[$n] . trim($fix_elements[$n + 1]);
+ if (defined $fix_elements[$n + 2]) {
+ $fix_elements[$n + 2] =~ s/^\s+//;
+ }
+ $line_fixed = 1;
+ }
}
-
# << and >> may either have or not have spaces both sides
} elsif ($op eq '<<' or $op eq '>>' or
$op eq '&' or $op eq '^' or $op eq '|' or
$op eq '%')
{
if ($ctx =~ /Wx[^WCE]|[^WCE]xW/) {
- ERROR("SPACING",
- "need consistent spacing around '$op' $at\n" .
- $hereptr);
+ if (ERROR("SPACING",
+ "need consistent spacing around '$op' $at\n" . $hereptr)) {
+ $good = rtrim($fix_elements[$n]) . " " . trim($fix_elements[$n + 1]) . " ";
+ if (defined $fix_elements[$n + 2]) {
+ $fix_elements[$n + 2] =~ s/^\s+//;
+ }
+ $line_fixed = 1;
+ }
}
# A colon needs no spaces before when it is
# terminating a case value or a label.
} elsif ($opv eq ':C' || $opv eq ':L') {
if ($ctx =~ /Wx./) {
- ERROR("SPACING",
- "space prohibited before that '$op' $at\n" . $hereptr);
+ if (ERROR("SPACING",
+ "space prohibited before that '$op' $at\n" . $hereptr)) {
+ $good = rtrim($fix_elements[$n]) . trim($fix_elements[$n + 1]);
+ $line_fixed = 1;
+ }
}
# All the others need spaces both sides.
($op eq '>' &&
$ca =~ /<\S+\@\S+$/))
{
- $ok = 1;
- }
-
- # Ignore ?:
- if (($opv eq ':O' && $ca =~ /\?$/) ||
- ($op eq '?' && $cc =~ /^:/)) {
- $ok = 1;
+ $ok = 1;
}
+ # messages are ERROR, but ?: are CHK
if ($ok == 0) {
- ERROR("SPACING",
- "spaces required around that '$op' $at\n" . $hereptr);
+ my $msg_type = \&ERROR;
+ $msg_type = \&CHK if (($op eq '?:' || $op eq '?' || $op eq ':') && $ctx =~ /VxV/);
+
+ if (&{$msg_type}("SPACING",
+ "spaces required around that '$op' $at\n" . $hereptr)) {
+ $good = rtrim($fix_elements[$n]) . " " . trim($fix_elements[$n + 1]) . " ";
+ if (defined $fix_elements[$n + 2]) {
+ $fix_elements[$n + 2] =~ s/^\s+//;
+ }
+ $line_fixed = 1;
+ }
}
}
$off += length($elements[$n + 1]);
+
+## print("n: <$n> GOOD: <$good>\n");
+
+ $fixed_line = $fixed_line . $good;
+ }
+
+ if (($#elements % 2) == 0) {
+ $fixed_line = $fixed_line . $fix_elements[$#elements];
+ }
+
+ if ($fix && $line_fixed && $fixed_line ne $fixed[$linenr - 1]) {
+ $fixed[$linenr - 1] = $fixed_line;
+ }
+
+
+ }
+
+# check for whitespace before a non-naked semicolon
+ if ($line =~ /^\+.*\S\s+;\s*$/) {
+ if (WARN("SPACING",
+ "space prohibited before semicolon\n" . $herecurr) &&
+ $fix) {
+ 1 while $fixed[$linenr - 1] =~
+ s/^(\+.*\S)\s+;/$1;/;
}
}
#need space before brace following if, while, etc
if (($line =~ /\(.*\){/ && $line !~ /\($Type\){/) ||
$line =~ /do{/) {
- ERROR("SPACING",
- "space required before the open brace '{'\n" . $herecurr);
+ if (ERROR("SPACING",
+ "space required before the open brace '{'\n" . $herecurr) &&
+ $fix) {
+ $fixed[$linenr - 1] =~ s/^(\+.*(?:do|\))){/$1 {/;
+ }
}
+## # check for blank lines before declarations
+## if ($line =~ /^.\t+$Type\s+$Ident(?:\s*=.*)?;/ &&
+## $prevrawline =~ /^.\s*$/) {
+## WARN("SPACING",
+## "No blank lines before declarations\n" . $hereprev);
+## }
+##
+
# closing brace should have a space following it when it has anything
# on the line
if ($line =~ /}(?!(?:,|;|\)))\S/) {
- ERROR("SPACING",
- "space required after that close brace '}'\n" . $herecurr);
+ if (ERROR("SPACING",
+ "space required after that close brace '}'\n" . $herecurr) &&
+ $fix) {
+ $fixed[$linenr - 1] =~
+ s/}((?!(?:,|;|\)))\S)/} $1/;
+ }
}
# check spacing on square brackets
if ($line =~ /\[\s/ && $line !~ /\[\s*$/) {
- ERROR("SPACING",
- "space prohibited after that open square bracket '['\n" . $herecurr);
+ if (ERROR("SPACING",
+ "space prohibited after that open square bracket '['\n" . $herecurr) &&
+ $fix) {
+ $fixed[$linenr - 1] =~
+ s/\[\s+/\[/;
+ }
}
if ($line =~ /\s\]/) {
- ERROR("SPACING",
- "space prohibited before that close square bracket ']'\n" . $herecurr);
+ if (ERROR("SPACING",
+ "space prohibited before that close square bracket ']'\n" . $herecurr) &&
+ $fix) {
+ $fixed[$linenr - 1] =~
+ s/\s+\]/\]/;
+ }
}
# check spacing on parentheses
if ($line =~ /\(\s/ && $line !~ /\(\s*(?:\\)?$/ &&
$line !~ /for\s*\(\s+;/) {
- ERROR("SPACING",
- "space prohibited after that open parenthesis '('\n" . $herecurr);
+ if (ERROR("SPACING",
+ "space prohibited after that open parenthesis '('\n" . $herecurr) &&
+ $fix) {
+ $fixed[$linenr - 1] =~
+ s/\(\s+/\(/;
+ }
}
if ($line =~ /(\s+)\)/ && $line !~ /^.\s*\)/ &&
$line !~ /for\s*\(.*;\s+\)/ &&
$line !~ /:\s+\)/) {
- ERROR("SPACING",
- "space prohibited before that close parenthesis ')'\n" . $herecurr);
+ if (ERROR("SPACING",
+ "space prohibited before that close parenthesis ')'\n" . $herecurr) &&
+ $fix) {
+ $fixed[$linenr - 1] =~
+ s/\s+\)/\)/;
+ }
}
#goto labels aren't indented, allow a single space however
if ($line=~/^.\s+[A-Za-z\d_]+:(?![0-9]+)/ and
!($line=~/^. [A-Za-z\d_]+:/) and !($line=~/^.\s+default:/)) {
- WARN("INDENTED_LABEL",
- "labels should not be indented\n" . $herecurr);
+ if (WARN("INDENTED_LABEL",
+ "labels should not be indented\n" . $herecurr) &&
+ $fix) {
+ $fixed[$linenr - 1] =~
+ s/^(.)\s+/$1/;
+ }
}
# Return is not a function.
- if (defined($stat) && $stat =~ /^.\s*return(\s*)(\(.*);/s) {
+ if (defined($stat) && $stat =~ /^.\s*return(\s*)\(/s) {
my $spacing = $1;
- my $value = $2;
-
- # Flatten any parentheses
- $value =~ s/\(/ \(/g;
- $value =~ s/\)/\) /g;
- while ($value =~ s/\[[^\[\]]*\]/1/ ||
- $value !~ /(?:$Ident|-?$Constant)\s*
- $Compare\s*
- (?:$Ident|-?$Constant)/x &&
- $value =~ s/\([^\(\)]*\)/1/) {
- }
-#print "value<$value>\n";
- if ($value =~ /^\s*(?:$Ident|-?$Constant)\s*$/) {
+ if ($^V && $^V ge 5.10.0 &&
+ $stat =~ /^.\s*return\s*$balanced_parens\s*;\s*$/) {
ERROR("RETURN_PARENTHESES",
"return is not a function, parentheses are not required\n" . $herecurr);
"space required before the open parenthesis '('\n" . $herecurr);
}
}
+
+# if statements using unnecessary parentheses - ie: if ((foo == bar))
+ if ($^V && $^V ge 5.10.0 &&
+ $line =~ /\bif\s*((?:\(\s*){2,})/) {
+ my $openparens = $1;
+ my $count = $openparens =~ tr@\(@\(@;
+ my $msg = "";
+ if ($line =~ /\bif\s*(?:\(\s*){$count,$count}$LvalOrFunc\s*($Compare)\s*$LvalOrFunc(?:\s*\)){$count,$count}/) {
+ my $comp = $4; #Not $1 because of $LvalOrFunc
+ $msg = " - maybe == should be = ?" if ($comp eq "==");
+ WARN("UNNECESSARY_PARENTHESES",
+ "Unnecessary parentheses$msg\n" . $herecurr);
+ }
+ }
+
# Return of what appears to be an errno should normally be -'ve
if ($line =~ /^.\s*return\s*(E[A-Z]*)\s*;/) {
my $name = $1;
}
# Need a space before open parenthesis after if, while etc
- if ($line=~/\b(if|while|for|switch)\(/) {
- ERROR("SPACING", "space required before the open parenthesis '('\n" . $herecurr);
+ if ($line =~ /\b(if|while|for|switch)\(/) {
+ if (ERROR("SPACING",
+ "space required before the open parenthesis '('\n" . $herecurr) &&
+ $fix) {
+ $fixed[$linenr - 1] =~
+ s/\b(if|while|for|switch)\(/$1 \(/;
+ }
}
# Check for illegal assignment in if conditional -- and check for trailing
}
}
if (!defined $suppress_whiletrailers{$linenr} &&
+ defined($stat) && defined($cond) &&
$line =~ /\b(?:if|while|for)\s*\(/ && $line !~ /^.\s*#/) {
my ($s, $c) = ($stat, $cond);
}
}
-#CamelCase
+#Specific variable tests
while ($line =~ m{($Constant|$Lval)}g) {
my $var = $1;
- if ($var !~ /$Constant/ &&
- $var =~ /[A-Z]\w*[a-z]|[a-z]\w*[A-Z]/ &&
- $var !~ /"^(?:Clear|Set|TestClear|TestSet|)Page[A-Z]/ &&
- !defined $camelcase{$var}) {
- $camelcase{$var} = 1;
- WARN("CAMELCASE",
- "Avoid CamelCase: <$var>\n" . $herecurr);
+
+#gcc binary extension
+ if ($var =~ /^$Binary$/) {
+ if (WARN("GCC_BINARY_CONSTANT",
+ "Avoid gcc v4.3+ binary constant extension: <$var>\n" . $herecurr) &&
+ $fix) {
+ my $hexval = sprintf("0x%x", oct($var));
+ $fixed[$linenr - 1] =~
+ s/\b$var\b/$hexval/;
+ }
+ }
+
+#CamelCase
+ if ($var !~ /^$Constant$/ &&
+ $var =~ /[A-Z][a-z]|[a-z][A-Z]/ &&
+#Ignore Page<foo> variants
+ $var !~ /^(?:Clear|Set|TestClear|TestSet|)Page[A-Z]/ &&
+#Ignore SI style variants like nS, mV and dB (ie: max_uV, regulator_min_uA_show)
+ $var !~ /^(?:[a-z_]*?)_?[a-z][A-Z](?:_[a-z_]+)?$/) {
+ while ($var =~ m{($Ident)}g) {
+ my $word = $1;
+ next if ($word !~ /[A-Z][a-z]|[a-z][A-Z]/);
+ if ($check) {
+ seed_camelcase_includes();
+ if (!$file && !$camelcase_file_seeded) {
+ seed_camelcase_file($realfile);
+ $camelcase_file_seeded = 1;
+ }
+ }
+ if (!defined $camelcase{$word}) {
+ $camelcase{$word} = 1;
+ CHK("CAMELCASE",
+ "Avoid CamelCase: <$word>\n" . $herecurr);
+ }
+ }
}
}
#no spaces allowed after \ in define
- if ($line=~/\#\s*define.*\\\s$/) {
- WARN("WHITESPACE_AFTER_LINE_CONTINUATION",
- "Whitepspace after \\ makes next lines useless\n" . $herecurr);
+ if ($line =~ /\#\s*define.*\\\s+$/) {
+ if (WARN("WHITESPACE_AFTER_LINE_CONTINUATION",
+ "Whitespace after \\ makes next lines useless\n" . $herecurr) &&
+ $fix) {
+ $fixed[$linenr - 1] =~ s/\s+$//;
+ }
}
#warn if <asm/foo.h> is #included and <linux/foo.h> is available (uses RAW line)
if ($dstat ne '' &&
$dstat !~ /^(?:$Ident|-?$Constant),$/ && # 10, // foo(),
$dstat !~ /^(?:$Ident|-?$Constant);$/ && # foo();
- $dstat !~ /^[!~-]?(?:$Ident|$Constant)$/ && # 10 // foo() // !foo // ~foo // -foo
+ $dstat !~ /^[!~-]?(?:$Lval|$Constant)$/ && # 10 // foo() // !foo // ~foo // -foo // foo->bar // foo.bar->baz
$dstat !~ /^'X'$/ && # character constants
$dstat !~ /$exceptions/ &&
$dstat !~ /^\.$Ident\s*=/ && # .foo =
+ $dstat !~ /^(?:\#\s*$Ident|\#\s*$Constant)\s*$/ && # stringification #foo
$dstat !~ /^do\s*$Constant\s*while\s*$Constant;?$/ && # do {...} while (...); // do {...} while (...)
$dstat !~ /^for\s*$Constant$/ && # for (...)
$dstat !~ /^for\s*$Constant\s+(?:$Ident|-?$Constant)$/ && # for (...) bar()
$dstat !~ /^do\s*{/ && # do {...
- $dstat !~ /^\({/) # ({...
+ $dstat !~ /^\({/ && # ({...
+ $ctx !~ /^.\s*#\s*define\s+TRACE_(?:SYSTEM|INCLUDE_FILE|INCLUDE_PATH)\b/)
{
$ctx =~ s/\n*$//;
my $herectx = $here . "\n";
}
# check for unnecessary blank lines around braces
- if (($line =~ /^..*}\s*$/ && $prevline =~ /^.\s*$/)) {
+ if (($line =~ /^.\s*}\s*$/ && $prevrawline =~ /^.\s*$/)) {
CHK("BRACES",
"Blank lines aren't necessary before a close brace '}'\n" . $hereprev);
}
- if (($line =~ /^.\s*$/ && $prevline =~ /^..*{\s*$/)) {
+ if (($rawline =~ /^.\s*$/ && $prevline =~ /^..*{\s*$/)) {
CHK("BRACES",
"Blank lines aren't necessary after an open brace '{'\n" . $hereprev);
}
}
}
+# check for bad placement of section $InitAttribute (e.g.: __initdata)
+ if ($line =~ /(\b$InitAttribute\b)/) {
+ my $attr = $1;
+ if ($line =~ /^\+\s*static\s+(?:const\s+)?(?:$attr\s+)?($NonptrTypeWithAttr)\s+(?:$attr\s+)?($Ident(?:\[[^]]*\])?)\s*[=;]/) {
+ my $ptr = $1;
+ my $var = $2;
+ if ((($ptr =~ /\b(union|struct)\s+$attr\b/ &&
+ ERROR("MISPLACED_INIT",
+ "$attr should be placed after $var\n" . $herecurr)) ||
+ ($ptr !~ /\b(union|struct)\s+$attr\b/ &&
+ WARN("MISPLACED_INIT",
+ "$attr should be placed after $var\n" . $herecurr))) &&
+ $fix) {
+ $fixed[$linenr - 1] =~ s/(\bstatic\s+(?:const\s+)?)(?:$attr\s+)?($NonptrTypeWithAttr)\s+(?:$attr\s+)?($Ident(?:\[[^]]*\])?)\s*([=;])\s*/"$1" . trim(string_find_replace($2, "\\s*$attr\\s*", " ")) . " " . trim(string_find_replace($3, "\\s*$attr\\s*", "")) . " $attr" . ("$4" eq ";" ? ";" : " = ")/e;
+ }
+ }
+ }
+
+# check for $InitAttributeData (ie: __initdata) with const
+ if ($line =~ /\bconst\b/ && $line =~ /($InitAttributeData)/) {
+ my $attr = $1;
+ $attr =~ /($InitAttributePrefix)(.*)/;
+ my $attr_prefix = $1;
+ my $attr_type = $2;
+ if (ERROR("INIT_ATTRIBUTE",
+ "Use of const init definition must use ${attr_prefix}initconst\n" . $herecurr) &&
+ $fix) {
+ $fixed[$linenr - 1] =~
+ s/$InitAttributeData/${attr_prefix}initconst/;
+ }
+ }
+
+# check for $InitAttributeConst (ie: __initconst) without const
+ if ($line !~ /\bconst\b/ && $line =~ /($InitAttributeConst)/) {
+ my $attr = $1;
+ if (ERROR("INIT_ATTRIBUTE",
+ "Use of $attr requires a separate use of const\n" . $herecurr) &&
+ $fix) {
+ my $lead = $fixed[$linenr - 1] =~
+ /(^\+\s*(?:static\s+))/;
+ $lead = rtrim($1);
+ $lead = "$lead " if ($lead !~ /^\+$/);
+ $lead = "${lead}const ";
+ $fixed[$linenr - 1] =~ s/(^\+\s*(?:static\s+))/$lead/;
+ }
+ }
+
# prefer usleep_range over udelay
if ($line =~ /\budelay\s*\(\s*(\d+)\s*\)/) {
# ignore udelay's < 10, however
}
}
+# check for comparisons of jiffies
+ if ($line =~ /\bjiffies\s*$Compare|$Compare\s*jiffies\b/) {
+ WARN("JIFFIES_COMPARISON",
+ "Comparing jiffies is almost always wrong; prefer time_after, time_before and friends\n" . $herecurr);
+ }
+
+# check for comparisons of get_jiffies_64()
+ if ($line =~ /\bget_jiffies_64\s*\(\s*\)\s*$Compare|$Compare\s*get_jiffies_64\s*\(\s*\)/) {
+ WARN("JIFFIES_COMPARISON",
+ "Comparing get_jiffies_64() is almost always wrong; prefer time_after64, time_before64 and friends\n" . $herecurr);
+ }
+
# warn about #ifdefs in C files
# if ($line =~ /^.\s*\#\s*if(|n)def/ && ($realfile =~ /\.c$/)) {
# print "#ifdef in C files should be avoided\n";
# warn about spacing in #ifdefs
if ($line =~ /^.\s*\#\s*(ifdef|ifndef|elif)\s\s+/) {
- ERROR("SPACING",
- "exactly one space required after that #$1\n" . $herecurr);
+ if (ERROR("SPACING",
+ "exactly one space required after that #$1\n" . $herecurr) &&
+ $fix) {
+ $fixed[$linenr - 1] =~
+ s/^(.\s*\#\s*(ifdef|ifndef|elif))\s{2,}/$1 /;
+ }
+
}
# check for spinlock_t definitions without a comment.
# check for memory barriers without a comment.
if ($line =~ /\b(mb|rmb|wmb|read_barrier_depends|smp_mb|smp_rmb|smp_wmb|smp_read_barrier_depends)\(/) {
if (!ctx_has_comment($first_line, $linenr)) {
- CHK("MEMORY_BARRIER",
- "memory barrier without comment\n" . $herecurr);
+ WARN("MEMORY_BARRIER",
+ "memory barrier without comment\n" . $herecurr);
}
}
# check of hardware specific defines
}
# Check for __inline__ and __inline, prefer inline
- if ($line =~ /\b(__inline__|__inline)\b/) {
- WARN("INLINE",
- "plain inline is preferred over $1\n" . $herecurr);
+ if ($realfile !~ m@\binclude/uapi/@ &&
+ $line =~ /\b(__inline__|__inline)\b/) {
+ if (WARN("INLINE",
+ "plain inline is preferred over $1\n" . $herecurr) &&
+ $fix) {
+ $fixed[$linenr - 1] =~ s/\b(__inline__|__inline)\b/inline/;
+
+ }
}
# Check for __attribute__ packed, prefer __packed
- if ($line =~ /\b__attribute__\s*\(\s*\(.*\bpacked\b/) {
+ if ($realfile !~ m@\binclude/uapi/@ &&
+ $line =~ /\b__attribute__\s*\(\s*\(.*\bpacked\b/) {
WARN("PREFER_PACKED",
"__packed is preferred over __attribute__((packed))\n" . $herecurr);
}
}
# Check for __attribute__ aligned, prefer __aligned
- if ($line =~ /\b__attribute__\s*\(\s*\(.*aligned/) {
+ if ($realfile !~ m@\binclude/uapi/@ &&
+ $line =~ /\b__attribute__\s*\(\s*\(.*aligned/) {
WARN("PREFER_ALIGNED",
"__aligned(size) is preferred over __attribute__((aligned(size)))\n" . $herecurr);
}
# Check for __attribute__ format(printf, prefer __printf
- if ($line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*printf/) {
- WARN("PREFER_PRINTF",
- "__printf(string-index, first-to-check) is preferred over __attribute__((format(printf, string-index, first-to-check)))\n" . $herecurr);
+ if ($realfile !~ m@\binclude/uapi/@ &&
+ $line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*printf/) {
+ if (WARN("PREFER_PRINTF",
+ "__printf(string-index, first-to-check) is preferred over __attribute__((format(printf, string-index, first-to-check)))\n" . $herecurr) &&
+ $fix) {
+ $fixed[$linenr - 1] =~ s/\b__attribute__\s*\(\s*\(\s*format\s*\(\s*printf\s*,\s*(.*)\)\s*\)\s*\)/"__printf(" . trim($1) . ")"/ex;
+
+ }
}
# Check for __attribute__ format(scanf, prefer __scanf
- if ($line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*scanf\b/) {
- WARN("PREFER_SCANF",
- "__scanf(string-index, first-to-check) is preferred over __attribute__((format(scanf, string-index, first-to-check)))\n" . $herecurr);
+ if ($realfile !~ m@\binclude/uapi/@ &&
+ $line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*scanf\b/) {
+ if (WARN("PREFER_SCANF",
+ "__scanf(string-index, first-to-check) is preferred over __attribute__((format(scanf, string-index, first-to-check)))\n" . $herecurr) &&
+ $fix) {
+ $fixed[$linenr - 1] =~ s/\b__attribute__\s*\(\s*\(\s*format\s*\(\s*scanf\s*,\s*(.*)\)\s*\)\s*\)/"__scanf(" . trim($1) . ")"/ex;
+ }
}
# check for sizeof(&)
# check for sizeof without parenthesis
if ($line =~ /\bsizeof\s+((?:\*\s*|)$Lval|$Type(?:\s+$Lval|))/) {
- WARN("SIZEOF_PARENTHESIS",
- "sizeof $1 should be sizeof($1)\n" . $herecurr);
+ if (WARN("SIZEOF_PARENTHESIS",
+ "sizeof $1 should be sizeof($1)\n" . $herecurr) &&
+ $fix) {
+ $fixed[$linenr - 1] =~ s/\bsizeof\s+((?:\*\s*|)$Lval|$Type(?:\s+$Lval|))/"sizeof(" . trim($1) . ")"/ex;
+ }
}
# check for line continuations in quoted strings with odd counts of "
"struct spinlock should be spinlock_t\n" . $herecurr);
}
+# check for seq_printf uses that could be seq_puts
+ if ($sline =~ /\bseq_printf\s*\(.*"\s*\)\s*;\s*$/) {
+ my $fmt = get_quoted_string($line, $rawline);
+ if ($fmt ne "" && $fmt !~ /[^\\]\%/) {
+ if (WARN("PREFER_SEQ_PUTS",
+ "Prefer seq_puts to seq_printf\n" . $herecurr) &&
+ $fix) {
+ $fixed[$linenr - 1] =~ s/\bseq_printf\b/seq_puts/;
+ }
+ }
+ }
+
# Check for misused memsets
if ($^V && $^V ge 5.10.0 &&
defined $stat &&
}
}
+# Check for memcpy(foo, bar, ETH_ALEN) that could be ether_addr_copy(foo, bar)
+ if ($^V && $^V ge 5.10.0 &&
+ $line =~ /^\+(?:.*?)\bmemcpy\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*ETH_ALEN\s*\)/s) {
+ if (WARN("PREFER_ETHER_ADDR_COPY",
+ "Prefer ether_addr_copy() over memcpy() if the Ethernet addresses are __aligned(2)\n" . $herecurr) &&
+ $fix) {
+ $fixed[$linenr - 1] =~ s/\bmemcpy\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*ETH_ALEN\s*\)/ether_addr_copy($2, $7)/;
+ }
+ }
+
# typecasts on min/max could be min_t/max_t
if ($^V && $^V ge 5.10.0 &&
defined $stat &&
}
}
+# check for naked sscanf
+ if ($^V && $^V ge 5.10.0 &&
+ defined $stat &&
+ $stat =~ /\bsscanf\b/ &&
+ ($stat !~ /$Ident\s*=\s*sscanf\s*$balanced_parens/ &&
+ $stat !~ /\bsscanf\s*$balanced_parens\s*(?:$Compare)/ &&
+ $stat !~ /(?:$Compare)\s*\bsscanf\s*$balanced_parens/)) {
+ my $lc = $stat =~ tr@\n@@;
+ $lc = $lc + $linenr;
+ my $stat_real = raw_line($linenr, 0);
+ for (my $count = $linenr + 1; $count <= $lc; $count++) {
+ $stat_real = $stat_real . "\n" . raw_line($count, 0);
+ }
+ WARN("NAKED_SSCANF",
+ "unchecked sscanf return value\n" . "$here\n$stat_real\n");
+ }
+
+# check for new externs in .h files.
+ if ($realfile =~ /\.h$/ &&
+ $line =~ /^\+\s*(extern\s+)$Type\s*$Ident\s*\(/s) {
+ if (CHK("AVOID_EXTERNS",
+ "extern prototypes should be avoided in .h files\n" . $herecurr) &&
+ $fix) {
+ $fixed[$linenr - 1] =~ s/(.*)\bextern\b\s*(.*)/$1$2/;
+ }
+ }
+
# check for new externs in .c files.
if ($realfile =~ /\.c$/ && defined $stat &&
$stat =~ /^.\s*(?:extern\s+)?$Type\s+($Ident)(\s*)\(/s)
"unnecessary cast may hide bugs, see http://c-faq.com/malloc/mallocnocast.html\n" . $herecurr);
}
+# alloc style
+# p = alloc(sizeof(struct foo), ...) should be p = alloc(sizeof(*p), ...)
+ if ($^V && $^V ge 5.10.0 &&
+ $line =~ /\b($Lval)\s*\=\s*(?:$balanced_parens)?\s*([kv][mz]alloc(?:_node)?)\s*\(\s*(sizeof\s*\(\s*struct\s+$Lval\s*\))/) {
+ CHK("ALLOC_SIZEOF_STRUCT",
+ "Prefer $3(sizeof(*$1)...) over $3($4...)\n" . $herecurr);
+ }
+
+# check for krealloc arg reuse
+ if ($^V && $^V ge 5.10.0 &&
+ $line =~ /\b($Lval)\s*\=\s*(?:$balanced_parens)?\s*krealloc\s*\(\s*\1\s*,/) {
+ WARN("KREALLOC_ARG_REUSE",
+ "Reusing the krealloc arg is almost always a bug\n" . $herecurr);
+ }
+
# check for alloc argument mismatch
if ($line =~ /\b(kcalloc|kmalloc_array)\s*\(\s*sizeof\b/) {
WARN("ALLOC_ARRAY_ARGS",
"$1 uses number as first arg, sizeof is generally wrong\n" . $herecurr);
}
+# check for GFP_NOWAIT use
+ if ($line =~ /\b__GFP_NOFAIL\b/) {
+ WARN("__GFP_NOFAIL",
+ "Use of __GFP_NOFAIL is deprecated, no new users should be added\n" . $herecurr);
+ }
+
# check for multiple semicolons
if ($line =~ /;\s*;\s*$/) {
- WARN("ONE_SEMICOLON",
- "Statements terminations use 1 semicolon\n" . $herecurr);
+ if (WARN("ONE_SEMICOLON",
+ "Statements terminations use 1 semicolon\n" . $herecurr) &&
+ $fix) {
+ $fixed[$linenr - 1] =~ s/(\s*;\s*){2,}$/;/g;
+ }
+ }
+
+# check for case / default statements not preceeded by break/fallthrough/switch
+ if ($line =~ /^.\s*(?:case\s+(?:$Ident|$Constant)\s*|default):/) {
+ my $has_break = 0;
+ my $has_statement = 0;
+ my $count = 0;
+ my $prevline = $linenr;
+ while ($prevline > 1 && $count < 3 && !$has_break) {
+ $prevline--;
+ my $rline = $rawlines[$prevline - 1];
+ my $fline = $lines[$prevline - 1];
+ last if ($fline =~ /^\@\@/);
+ next if ($fline =~ /^\-/);
+ next if ($fline =~ /^.(?:\s*(?:case\s+(?:$Ident|$Constant)[\s$;]*|default):[\s$;]*)*$/);
+ $has_break = 1 if ($rline =~ /fall[\s_-]*(through|thru)/i);
+ next if ($fline =~ /^.[\s$;]*$/);
+ $has_statement = 1;
+ $count++;
+ $has_break = 1 if ($fline =~ /\bswitch\b|\b(?:break\s*;[\s$;]*$|return\b|goto\b|continue\b)/);
+ }
+ if (!$has_break && $has_statement) {
+ WARN("MISSING_BREAK",
+ "Possible switch case/default not preceeded by break or fallthrough comment\n" . $herecurr);
+ }
}
# check for switch/default statements without a break;
}
# check for gcc specific __FUNCTION__
- if ($line =~ /__FUNCTION__/) {
- WARN("USE_FUNC",
- "__func__ should be used instead of gcc specific __FUNCTION__\n" . $herecurr);
+ if ($line =~ /\b__FUNCTION__\b/) {
+ if (WARN("USE_FUNC",
+ "__func__ should be used instead of gcc specific __FUNCTION__\n" . $herecurr) &&
+ $fix) {
+ $fixed[$linenr - 1] =~ s/\b__FUNCTION__\b/__func__/g;
+ }
}
# check for use of yield()
"Using yield() is generally wrong. See yield() kernel-doc (sched/core.c)\n" . $herecurr);
}
+# check for comparisons against true and false
+ if ($line =~ /\+\s*(.*?)\b(true|false|$Lval)\s*(==|\!=)\s*(true|false|$Lval)\b(.*)$/i) {
+ my $lead = $1;
+ my $arg = $2;
+ my $test = $3;
+ my $otype = $4;
+ my $trail = $5;
+ my $op = "!";
+
+ ($arg, $otype) = ($otype, $arg) if ($arg =~ /^(?:true|false)$/i);
+
+ my $type = lc($otype);
+ if ($type =~ /^(?:true|false)$/) {
+ if (("$test" eq "==" && "$type" eq "true") ||
+ ("$test" eq "!=" && "$type" eq "false")) {
+ $op = "";
+ }
+
+ CHK("BOOL_COMPARISON",
+ "Using comparison to $otype is error prone\n" . $herecurr);
+
+## maybe suggesting a correct construct would better
+## "Using comparison to $otype is error prone. Perhaps use '${lead}${op}${arg}${trail}'\n" . $herecurr);
+
+ }
+ }
+
# check for semaphores initialized locked
if ($line =~ /^.\s*sema_init.+,\W?0\W?\)/) {
WARN("CONSIDER_COMPLETION",
"usage of NR_CPUS is often wrong - consider using cpu_possible(), num_possible_cpus(), for_each_possible_cpu(), etc\n" . $herecurr);
}
+# Use of __ARCH_HAS_<FOO> or ARCH_HAVE_<BAR> is wrong.
+ if ($line =~ /\+\s*#\s*define\s+((?:__)?ARCH_(?:HAS|HAVE)\w*)\b/) {
+ ERROR("DEFINE_ARCH_HAS",
+ "#define of '$1' is wrong - use Kconfig variables or standard guards instead\n" . $herecurr);
+ }
+
# check for %L{u,d,i} in strings
my $string;
while ($line =~ /(?:^|")([X\t]*)(?:"|$)/g) {
}
}
- if ($quiet == 0 && keys %ignore_type) {
- print "NOTE: Ignored message types:";
- foreach my $ignore (sort keys %ignore_type) {
- print " $ignore";
- }
- print "\n\n";
+ hash_show_words(\%use_type, "Used");
+ hash_show_words(\%ignore_type, "Ignored");
+
+ if ($clean == 0 && $fix && "@rawlines" ne "@fixed") {
+ my $newfile = $filename;
+ $newfile .= ".EXPERIMENTAL-checkpatch-fixes" if (!$fix_inplace);
+ my $linecount = 0;
+ my $f;
+
+ open($f, '>', $newfile)
+ or die "$P: Can't open $newfile for write\n";
+ foreach my $fixed_line (@fixed) {
+ $linecount++;
+ if ($file) {
+ if ($linecount > 3) {
+ $fixed_line =~ s/^\+//;
+ print $f $fixed_line. "\n";
+ }
+ } else {
+ print $f $fixed_line . "\n";
+ }
+ }
+ close($f);
+
+ if (!$quiet) {
+ print << "EOM";
+Wrote EXPERIMENTAL --fix correction(s) to '$newfile'
+
+Do _NOT_ trust the results written to this file.
+Do _NOT_ submit these changes without inspecting them for correctness.
+
+This EXPERIMENTAL file is simply a convenience to help rewrite patches.
+No warranties, expressed or implied...
+
+EOM
+ }
}
if ($clean == 1 && $quiet == 0) {
$vname has style problems, please review.
If any of these errors are false positives, please report
-them to the maintainer, see boards.cfg.
+them to the maintainer, see CHECKPATCH in MAINTAINERS.
EOM
}
KBUILD_CPPFLAGS += -DCONFIG_TPL_BUILD
endif
-# Enable garbage collection of un-used sections for SPL
-KBUILD_CFLAGS += -ffunction-sections -fdata-sections
-LDFLAGS_FINAL += --gc-sections
-
ifeq ($(CONFIG_TPL_BUILD),y)
export CONFIG_TPL_BUILD
SPL_BIN := u-boot-tpl
-include include/spl-autoconf.mk
endif
-include $(TOPDIR)/config.mk
+include $(srctree)/config.mk
+
+# Enable garbage collection of un-used sections for SPL
+KBUILD_CFLAGS += -ffunction-sections -fdata-sections
+LDFLAGS_FINAL += --gc-sections
# FIX ME
-c_flags := $(KBUILD_CFLAGS) $(KBUILD_CPPFLAGS) $(CPPFLAGS) $(UBOOTINCLUDE) $(NOSTDINC_FLAGS)
+cpp_flags := $(KBUILD_CPPFLAGS) $(PLATFORM_CPPFLAGS) $(UBOOTINCLUDE) \
+ $(NOSTDINC_FLAGS)
+c_flags := $(KBUILD_CFLAGS) $(cpp_flags)
# Auto-generate the spl-autoconf.mk file (which is included by all makefiles for SPL)
quiet_cmd_autoconf = GEN $@
include/spl-autoconf.mk: include/config.h
$(call cmd,autoconf)
-HAVE_VENDOR_COMMON_LIB = $(if $(wildcard $(SRCTREE)/board/$(VENDOR)/common/Makefile),y,n)
+HAVE_VENDOR_COMMON_LIB = $(if $(wildcard $(srctree)/board/$(VENDOR)/common/Makefile),y,n)
ifdef CONFIG_SPL_START_S_PATH
START_PATH := $(CONFIG_SPL_START_S_PATH:"%"=%)
libs-y := $(patsubst %/, %/built-in.o, $(libs-y))
# Add GCC lib
-ifeq ("$(USE_PRIVATE_LIBGCC)", "yes")
-PLATFORM_LIBGCC = $(SPLTREE)/arch/$(ARCH)/lib/lib.a
+ifeq ($(CONFIG_USE_PRIVATE_LIBGCC),y)
+PLATFORM_LIBGCC = arch/$(ARCH)/lib/lib.a
PLATFORM_LIBS := $(filter-out %/lib.a, $(filter-out -lgcc, $(PLATFORM_LIBS))) $(PLATFORM_LIBGCC)
endif
# Linker Script
ifdef CONFIG_SPL_LDSCRIPT
# need to strip off double quotes
-LDSCRIPT := $(addprefix $(SRCTREE)/,$(CONFIG_SPL_LDSCRIPT:"%"=%))
+LDSCRIPT := $(addprefix $(srctree)/,$(CONFIG_SPL_LDSCRIPT:"%"=%))
endif
ifeq ($(wildcard $(LDSCRIPT)),)
- LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-spl.lds
+ LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot-spl.lds
endif
ifeq ($(wildcard $(LDSCRIPT)),)
- LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-spl.lds
+ LDSCRIPT := $(srctree)/$(CPUDIR)/u-boot-spl.lds
endif
ifeq ($(wildcard $(LDSCRIPT)),)
- LDSCRIPT := $(TOPDIR)/arch/$(ARCH)/cpu/u-boot-spl.lds
+ LDSCRIPT := $(srctree)/arch/$(ARCH)/cpu/u-boot-spl.lds
endif
ifeq ($(wildcard $(LDSCRIPT)),)
$(error could not find linker script)
# Pass the version down so we can handle backwards compatibility
# on the fly.
LDPPFLAGS += \
- -include $(TOPDIR)/include/u-boot/u-boot.lds.h \
- -include $(OBJTREE)/include/config.h \
+ -include $(srctree)/include/u-boot/u-boot.lds.h \
+ -include $(objtree)/include/config.h \
-DCPUDIR=$(CPUDIR) \
$(shell $(LD) --version | \
sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p')
VAR_SIZE_PARAM =
endif
$(obj)/$(BOARD)-spl.bin: $(obj)/u-boot-spl.bin
- $(if $(wildcard $(OBJTREE)/spl/board/samsung/$(BOARD)/tools/mk$(BOARD)spl),\
- $(OBJTREE)/spl/board/samsung/$(BOARD)/tools/mk$(BOARD)spl,\
- $(OBJTREE)/tools/mkexynosspl) $(VAR_SIZE_PARAM) $< $@
+ $(if $(wildcard $(objtree)/spl/board/samsung/$(BOARD)/tools/mk$(BOARD)spl),\
+ $(objtree)/spl/board/samsung/$(BOARD)/tools/mk$(BOARD)spl,\
+ $(objtree)/tools/mkexynosspl) $(VAR_SIZE_PARAM) $< $@
endif
quiet_cmd_objcopy = OBJCOPY $@
$(u-boot-spl-dirs):
$(Q)$(MAKE) $(build)=$@
-# FIX ME
-cpp_flags := $(KBUILD_CPPFLAGS) $(CPPFLAGS) $(UBOOTINCLUDE) $(NOSTDINC_FLAGS)
-
quiet_cmd_cpp_lds = LDS $@
cmd_cpp_lds = $(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ \
-x assembler-with-cpp -P -o $@ $<
#define DEBUG
#include <common.h>
+#ifdef CONFIG_SANDBOX
+#include <os.h>
+#endif
static const char test_cmd[] = "setenv list 1\n setenv list ${list}2; "
"setenv list ${list}3\0"
run_command("if test " expr " ; then " \
"setenv " #name "_" #expected_result " y; else " \
"setenv " #name "_" #expected_result " n; fi", 0); \
- assert(!strcmp(#expected_result, getenv(#name "_" #expected_result)));
+ assert(!strcmp(#expected_result, getenv(#name "_" #expected_result))); \
+ setenv(#name "_" #expected_result, NULL);
/* Basic operators */
HUSH_TEST(streq, "aaa = aaa", y);
HUSH_TEST(or_1_0_inv_inv, "! ! aaa = aaa -o ! ! bbb != bbb", y);
HUSH_TEST(or_1_1_inv_inv, "! ! aaa = aaa -o ! ! bbb = bbb", y);
+ setenv("ut_var_nonexistent", NULL);
+ setenv("ut_var_exists", "1");
+ HUSH_TEST(z_varexp_quoted, "-z \"$ut_var_nonexistent\"", y);
+ HUSH_TEST(z_varexp_quoted, "-z \"$ut_var_exists\"", n);
+ setenv("ut_var_exists", NULL);
+
+ run_command("setenv ut_var_space \" \"", 0);
+ assert(!strcmp(getenv("ut_var_space"), " "));
+ run_command("setenv ut_var_test $ut_var_space", 0);
+ assert(!getenv("ut_var_test"));
+ run_command("setenv ut_var_test \"$ut_var_space\"", 0);
+ assert(!strcmp(getenv("ut_var_test"), " "));
+ run_command("setenv ut_var_test \" 1${ut_var_space}${ut_var_space} 2 \"", 0);
+ assert(!strcmp(getenv("ut_var_test"), " 1 2 "));
+ setenv("ut_var_space", NULL);
+ setenv("ut_var_test", NULL);
+
#ifdef CONFIG_SANDBOX
- /*
- * File existence
- * This assume U-Boot sandbox is run from the U-Boot build directory
- */
- HUSH_TEST(e, "-e host - u-boot", y);
+ /* File existence */
+ HUSH_TEST(e, "-e host - creating_this_file_breaks_uboot_unit_test", n);
+ run_command("sb save host - creating_this_file_breaks_uboot_unit_test 0 1", 0);
+ HUSH_TEST(e, "-e host - creating_this_file_breaks_uboot_unit_test", y);
+ /* Perhaps this could be replaced by an "rm" shell command one day */
+ assert(!os_unlink("creating_this_file_breaks_uboot_unit_test"));
HUSH_TEST(e, "-e host - creating_this_file_breaks_uboot_unit_test", n);
#endif
#endif
--- /dev/null
+#
+# Copyright (c) 2013 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_CMD_DM) += cmd_dm.o
+obj-$(CONFIG_DM_TEST) += test-driver.o
+obj-$(CONFIG_DM_TEST) += test-fdt.o
+obj-$(CONFIG_DM_TEST) += test-main.o
+obj-$(CONFIG_DM_TEST) += test-uclass.o
+obj-$(CONFIG_DM_TEST) += ut.o
+
+# Tests for particular subsystems - when enabling driver model for a new
+# subsystem you must add sandbox tests here.
+obj-$(CONFIG_DM_TEST) += core.o
+obj-$(CONFIG_DM_TEST) += ut.o
+obj-$(CONFIG_DM_GPIO) += gpio.o
--- /dev/null
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <malloc.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <dm/root.h>
+#include <dm/test.h>
+#include <dm/uclass-internal.h>
+
+static int display_succ(struct device *in, char *buf)
+{
+ int len;
+ int ip = 0;
+ char local[16];
+ struct device *pos, *n, *prev = NULL;
+
+ printf("%s- %s @ %08x", buf, in->name, map_to_sysmem(in));
+ if (in->flags & DM_FLAG_ACTIVATED)
+ puts(" - activated");
+ puts("\n");
+
+ if (list_empty(&in->child_head))
+ return 0;
+
+ len = strlen(buf);
+ strncpy(local, buf, sizeof(local));
+ snprintf(local + len, 2, "|");
+ if (len && local[len - 1] == '`')
+ local[len - 1] = ' ';
+
+ list_for_each_entry_safe(pos, n, &in->child_head, sibling_node) {
+ if (ip++)
+ display_succ(prev, local);
+ prev = pos;
+ }
+
+ snprintf(local + len, 2, "`");
+ display_succ(prev, local);
+
+ return 0;
+}
+
+static int dm_dump(struct device *dev)
+{
+ if (!dev)
+ return -EINVAL;
+ return display_succ(dev, "");
+}
+
+static int do_dm_dump_all(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ struct device *root;
+
+ root = dm_root();
+ printf("ROOT %08x\n", map_to_sysmem(root));
+ return dm_dump(root);
+}
+
+static int do_dm_dump_uclass(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ struct uclass *uc;
+ int ret;
+ int id;
+
+ for (id = 0; id < UCLASS_COUNT; id++) {
+ struct device *dev;
+
+ ret = uclass_get(id, &uc);
+ if (ret)
+ continue;
+
+ printf("uclass %d: %s\n", id, uc->uc_drv->name);
+ for (ret = uclass_first_device(id, &dev);
+ dev;
+ ret = uclass_next_device(&dev)) {
+ printf(" %s @ %08x:\n", dev->name,
+ map_to_sysmem(dev));
+ }
+ puts("\n");
+ }
+
+ return 0;
+}
+
+static int do_dm_test(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ return dm_test_main();
+}
+
+static cmd_tbl_t test_commands[] = {
+ U_BOOT_CMD_MKENT(tree, 0, 1, do_dm_dump_all, "", ""),
+ U_BOOT_CMD_MKENT(uclass, 1, 1, do_dm_dump_uclass, "", ""),
+ U_BOOT_CMD_MKENT(test, 1, 1, do_dm_test, "", ""),
+};
+
+static int do_dm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ cmd_tbl_t *test_cmd;
+ int ret;
+
+ if (argc != 2)
+ return CMD_RET_USAGE;
+ test_cmd = find_cmd_tbl(argv[1], test_commands,
+ ARRAY_SIZE(test_commands));
+ argc -= 2;
+ argv += 2;
+ if (!test_cmd || argc > test_cmd->maxargs)
+ return CMD_RET_USAGE;
+
+ ret = test_cmd->cmd(test_cmd, flag, argc, argv);
+
+ return cmd_process_error(test_cmd, ret);
+}
+
+U_BOOT_CMD(
+ dm, 2, 1, do_dm,
+ "Driver model low level access",
+ "tree Dump driver model tree\n"
+ "dm uclass Dump list of instances for each uclass\n"
+ "dm test Run tests"
+);
--- /dev/null
+/*
+ * Tests for the core driver model code
+ *
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <dm/device-internal.h>
+#include <dm/root.h>
+#include <dm/ut.h>
+#include <dm/util.h>
+#include <dm/test.h>
+#include <dm/uclass-internal.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+ TEST_INTVAL1 = 0,
+ TEST_INTVAL2 = 3,
+ TEST_INTVAL3 = 6,
+ TEST_INTVAL_MANUAL = 101112,
+};
+
+static const struct dm_test_pdata test_pdata[] = {
+ { .ping_add = TEST_INTVAL1, },
+ { .ping_add = TEST_INTVAL2, },
+ { .ping_add = TEST_INTVAL3, },
+};
+
+static const struct dm_test_pdata test_pdata_manual = {
+ .ping_add = TEST_INTVAL_MANUAL,
+};
+
+U_BOOT_DEVICE(dm_test_info1) = {
+ .name = "test_drv",
+ .platdata = &test_pdata[0],
+};
+
+U_BOOT_DEVICE(dm_test_info2) = {
+ .name = "test_drv",
+ .platdata = &test_pdata[1],
+};
+
+U_BOOT_DEVICE(dm_test_info3) = {
+ .name = "test_drv",
+ .platdata = &test_pdata[2],
+};
+
+static struct driver_info driver_info_manual = {
+ .name = "test_manual_drv",
+ .platdata = &test_pdata_manual,
+};
+
+/* Test that binding with platdata occurs correctly */
+static int dm_test_autobind(struct dm_test_state *dms)
+{
+ struct device *dev;
+
+ /*
+ * We should have a single class (UCLASS_ROOT) and a single root
+ * device with no children.
+ */
+ ut_assert(dms->root);
+ ut_asserteq(1, list_count_items(&gd->uclass_root));
+ ut_asserteq(0, list_count_items(&gd->dm_root->child_head));
+ ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_POST_BIND]);
+
+ ut_assertok(dm_scan_platdata());
+
+ /* We should have our test class now at least, plus more children */
+ ut_assert(1 < list_count_items(&gd->uclass_root));
+ ut_assert(0 < list_count_items(&gd->dm_root->child_head));
+
+ /* Our 3 dm_test_infox children should be bound to the test uclass */
+ ut_asserteq(3, dm_testdrv_op_count[DM_TEST_OP_POST_BIND]);
+
+ /* No devices should be probed */
+ list_for_each_entry(dev, &gd->dm_root->child_head, sibling_node)
+ ut_assert(!(dev->flags & DM_FLAG_ACTIVATED));
+
+ /* Our test driver should have been bound 3 times */
+ ut_assert(dm_testdrv_op_count[DM_TEST_OP_BIND] == 3);
+
+ return 0;
+}
+DM_TEST(dm_test_autobind, 0);
+
+/* Test that autoprobe finds all the expected devices */
+static int dm_test_autoprobe(struct dm_test_state *dms)
+{
+ int expected_base_add;
+ struct device *dev;
+ struct uclass *uc;
+ int i;
+
+ ut_assertok(uclass_get(UCLASS_TEST, &uc));
+ ut_assert(uc);
+
+ ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_INIT]);
+ ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_POST_PROBE]);
+
+ /* The root device should not be activated until needed */
+ ut_assert(!(dms->root->flags & DM_FLAG_ACTIVATED));
+
+ /*
+ * We should be able to find the three test devices, and they should
+ * all be activated as they are used (lazy activation, required by
+ * U-Boot)
+ */
+ for (i = 0; i < 3; i++) {
+ ut_assertok(uclass_find_device(UCLASS_TEST, i, &dev));
+ ut_assert(dev);
+ ut_assertf(!(dev->flags & DM_FLAG_ACTIVATED),
+ "Driver %d/%s already activated", i, dev->name);
+
+ /* This should activate it */
+ ut_assertok(uclass_get_device(UCLASS_TEST, i, &dev));
+ ut_assert(dev);
+ ut_assert(dev->flags & DM_FLAG_ACTIVATED);
+
+ /* Activating a device should activate the root device */
+ if (!i)
+ ut_assert(dms->root->flags & DM_FLAG_ACTIVATED);
+ }
+
+ /* Our 3 dm_test_infox children should be passed to post_probe */
+ ut_asserteq(3, dm_testdrv_op_count[DM_TEST_OP_POST_PROBE]);
+
+ /* Also we can check the per-device data */
+ expected_base_add = 0;
+ for (i = 0; i < 3; i++) {
+ struct dm_test_uclass_perdev_priv *priv;
+ struct dm_test_pdata *pdata;
+
+ ut_assertok(uclass_find_device(UCLASS_TEST, i, &dev));
+ ut_assert(dev);
+
+ priv = dev->uclass_priv;
+ ut_assert(priv);
+ ut_asserteq(expected_base_add, priv->base_add);
+
+ pdata = dev->platdata;
+ expected_base_add += pdata->ping_add;
+ }
+
+ return 0;
+}
+DM_TEST(dm_test_autoprobe, DM_TESTF_SCAN_PDATA);
+
+/* Check that we see the correct platdata in each device */
+static int dm_test_platdata(struct dm_test_state *dms)
+{
+ const struct dm_test_pdata *pdata;
+ struct device *dev;
+ int i;
+
+ for (i = 0; i < 3; i++) {
+ ut_assertok(uclass_find_device(UCLASS_TEST, i, &dev));
+ ut_assert(dev);
+ pdata = dev->platdata;
+ ut_assert(pdata->ping_add == test_pdata[i].ping_add);
+ }
+
+ return 0;
+}
+DM_TEST(dm_test_platdata, DM_TESTF_SCAN_PDATA);
+
+/* Test that we can bind, probe, remove, unbind a driver */
+static int dm_test_lifecycle(struct dm_test_state *dms)
+{
+ int op_count[DM_TEST_OP_COUNT];
+ struct device *dev, *test_dev;
+ int pingret;
+ int ret;
+
+ memcpy(op_count, dm_testdrv_op_count, sizeof(op_count));
+
+ ut_assertok(device_bind_by_name(dms->root, &driver_info_manual,
+ &dev));
+ ut_assert(dev);
+ ut_assert(dm_testdrv_op_count[DM_TEST_OP_BIND]
+ == op_count[DM_TEST_OP_BIND] + 1);
+ ut_assert(!dev->priv);
+
+ /* Probe the device - it should fail allocating private data */
+ dms->force_fail_alloc = 1;
+ ret = device_probe(dev);
+ ut_assert(ret == -ENOMEM);
+ ut_assert(dm_testdrv_op_count[DM_TEST_OP_PROBE]
+ == op_count[DM_TEST_OP_PROBE] + 1);
+ ut_assert(!dev->priv);
+
+ /* Try again without the alloc failure */
+ dms->force_fail_alloc = 0;
+ ut_assertok(device_probe(dev));
+ ut_assert(dm_testdrv_op_count[DM_TEST_OP_PROBE]
+ == op_count[DM_TEST_OP_PROBE] + 2);
+ ut_assert(dev->priv);
+
+ /* This should be device 3 in the uclass */
+ ut_assertok(uclass_find_device(UCLASS_TEST, 3, &test_dev));
+ ut_assert(dev == test_dev);
+
+ /* Try ping */
+ ut_assertok(test_ping(dev, 100, &pingret));
+ ut_assert(pingret == 102);
+
+ /* Now remove device 3 */
+ ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_PRE_REMOVE]);
+ ut_assertok(device_remove(dev));
+ ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_PRE_REMOVE]);
+
+ ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_UNBIND]);
+ ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_PRE_UNBIND]);
+ ut_assertok(device_unbind(dev));
+ ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_UNBIND]);
+ ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_PRE_UNBIND]);
+
+ return 0;
+}
+DM_TEST(dm_test_lifecycle, DM_TESTF_SCAN_PDATA | DM_TESTF_PROBE_TEST);
+
+/* Test that we can bind/unbind and the lists update correctly */
+static int dm_test_ordering(struct dm_test_state *dms)
+{
+ struct device *dev, *dev_penultimate, *dev_last, *test_dev;
+ int pingret;
+
+ ut_assertok(device_bind_by_name(dms->root, &driver_info_manual,
+ &dev));
+ ut_assert(dev);
+
+ /* Bind two new devices (numbers 4 and 5) */
+ ut_assertok(device_bind_by_name(dms->root, &driver_info_manual,
+ &dev_penultimate));
+ ut_assert(dev_penultimate);
+ ut_assertok(device_bind_by_name(dms->root, &driver_info_manual,
+ &dev_last));
+ ut_assert(dev_last);
+
+ /* Now remove device 3 */
+ ut_assertok(device_remove(dev));
+ ut_assertok(device_unbind(dev));
+
+ /* The device numbering should have shifted down one */
+ ut_assertok(uclass_find_device(UCLASS_TEST, 3, &test_dev));
+ ut_assert(dev_penultimate == test_dev);
+ ut_assertok(uclass_find_device(UCLASS_TEST, 4, &test_dev));
+ ut_assert(dev_last == test_dev);
+
+ /* Add back the original device 3, now in position 5 */
+ ut_assertok(device_bind_by_name(dms->root, &driver_info_manual, &dev));
+ ut_assert(dev);
+
+ /* Try ping */
+ ut_assertok(test_ping(dev, 100, &pingret));
+ ut_assert(pingret == 102);
+
+ /* Remove 3 and 4 */
+ ut_assertok(device_remove(dev_penultimate));
+ ut_assertok(device_unbind(dev_penultimate));
+ ut_assertok(device_remove(dev_last));
+ ut_assertok(device_unbind(dev_last));
+
+ /* Our device should now be in position 3 */
+ ut_assertok(uclass_find_device(UCLASS_TEST, 3, &test_dev));
+ ut_assert(dev == test_dev);
+
+ /* Now remove device 3 */
+ ut_assertok(device_remove(dev));
+ ut_assertok(device_unbind(dev));
+
+ return 0;
+}
+DM_TEST(dm_test_ordering, DM_TESTF_SCAN_PDATA);
+
+/* Check that we can perform operations on a device (do a ping) */
+int dm_check_operations(struct dm_test_state *dms, struct device *dev,
+ uint32_t base, struct dm_test_priv *priv)
+{
+ int expected;
+ int pingret;
+
+ /* Getting the child device should allocate platdata / priv */
+ ut_assertok(testfdt_ping(dev, 10, &pingret));
+ ut_assert(dev->priv);
+ ut_assert(dev->platdata);
+
+ expected = 10 + base;
+ ut_asserteq(expected, pingret);
+
+ /* Do another ping */
+ ut_assertok(testfdt_ping(dev, 20, &pingret));
+ expected = 20 + base;
+ ut_asserteq(expected, pingret);
+
+ /* Now check the ping_total */
+ priv = dev->priv;
+ ut_asserteq(DM_TEST_START_TOTAL + 10 + 20 + base * 2,
+ priv->ping_total);
+
+ return 0;
+}
+
+/* Check that we can perform operations on devices */
+static int dm_test_operations(struct dm_test_state *dms)
+{
+ struct device *dev;
+ int i;
+
+ /*
+ * Now check that the ping adds are what we expect. This is using the
+ * ping-add property in each node.
+ */
+ for (i = 0; i < ARRAY_SIZE(test_pdata); i++) {
+ uint32_t base;
+
+ ut_assertok(uclass_get_device(UCLASS_TEST, i, &dev));
+
+ /*
+ * Get the 'reg' property, which tells us what the ping add
+ * should be. We don't use the platdata because we want
+ * to test the code that sets that up (testfdt_drv_probe()).
+ */
+ base = test_pdata[i].ping_add;
+ debug("dev=%d, base=%d\n", i, base);
+
+ ut_assert(!dm_check_operations(dms, dev, base, dev->priv));
+ }
+
+ return 0;
+}
+DM_TEST(dm_test_operations, DM_TESTF_SCAN_PDATA);
+
+/* Remove all drivers and check that things work */
+static int dm_test_remove(struct dm_test_state *dms)
+{
+ struct device *dev;
+ int i;
+
+ for (i = 0; i < 3; i++) {
+ ut_assertok(uclass_find_device(UCLASS_TEST, i, &dev));
+ ut_assert(dev);
+ ut_assertf(dev->flags & DM_FLAG_ACTIVATED,
+ "Driver %d/%s not activated", i, dev->name);
+ ut_assertok(device_remove(dev));
+ ut_assertf(!(dev->flags & DM_FLAG_ACTIVATED),
+ "Driver %d/%s should have deactivated", i,
+ dev->name);
+ ut_assert(!dev->priv);
+ }
+
+ return 0;
+}
+DM_TEST(dm_test_remove, DM_TESTF_SCAN_PDATA | DM_TESTF_PROBE_TEST);
+
+/* Remove and recreate everything, check for memory leaks */
+static int dm_test_leak(struct dm_test_state *dms)
+{
+ int i;
+
+ for (i = 0; i < 2; i++) {
+ struct mallinfo start, end;
+ struct device *dev;
+ int ret;
+ int id;
+
+ start = mallinfo();
+ if (!start.uordblks)
+ puts("Warning: Please add '#define DEBUG' to the top of common/dlmalloc.c\n");
+
+ ut_assertok(dm_scan_platdata());
+ ut_assertok(dm_scan_fdt(gd->fdt_blob));
+
+ /* Scanning the uclass is enough to probe all the devices */
+ for (id = UCLASS_ROOT; id < UCLASS_COUNT; id++) {
+ for (ret = uclass_first_device(UCLASS_TEST, &dev);
+ dev;
+ ret = uclass_next_device(&dev))
+ ;
+ ut_assertok(ret);
+ }
+
+ /* Don't delete the root class, since we started with that */
+ for (id = UCLASS_ROOT + 1; id < UCLASS_COUNT; id++) {
+ struct uclass *uc;
+
+ uc = uclass_find(id);
+ if (!uc)
+ continue;
+ ut_assertok(uclass_destroy(uc));
+ }
+
+ end = mallinfo();
+ ut_asserteq(start.uordblks, end.uordblks);
+ }
+
+ return 0;
+}
+DM_TEST(dm_test_leak, 0);
+
+/* Test uclass init/destroy methods */
+static int dm_test_uclass(struct dm_test_state *dms)
+{
+ struct uclass *uc;
+
+ ut_assertok(uclass_get(UCLASS_TEST, &uc));
+ ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_INIT]);
+ ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_DESTROY]);
+ ut_assert(uc->priv);
+
+ ut_assertok(uclass_destroy(uc));
+ ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_INIT]);
+ ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_DESTROY]);
+
+ return 0;
+}
+DM_TEST(dm_test_uclass, 0);
+
+/**
+ * create_children() - Create children of a parent node
+ *
+ * @dms: Test system state
+ * @parent: Parent device
+ * @count: Number of children to create
+ * @key: Key value to put in first child. Subsequence children
+ * receive an incrementing value
+ * @child: If not NULL, then the child device pointers are written into
+ * this array.
+ * @return 0 if OK, -ve on error
+ */
+static int create_children(struct dm_test_state *dms, struct device *parent,
+ int count, int key, struct device *child[])
+{
+ struct device *dev;
+ int i;
+
+ for (i = 0; i < count; i++) {
+ struct dm_test_pdata *pdata;
+
+ ut_assertok(device_bind_by_name(parent, &driver_info_manual,
+ &dev));
+ pdata = calloc(1, sizeof(*pdata));
+ pdata->ping_add = key + i;
+ dev->platdata = pdata;
+ if (child)
+ child[i] = dev;
+ }
+
+ return 0;
+}
+
+#define NODE_COUNT 10
+
+static int dm_test_children(struct dm_test_state *dms)
+{
+ struct device *top[NODE_COUNT];
+ struct device *child[NODE_COUNT];
+ struct device *grandchild[NODE_COUNT];
+ struct device *dev;
+ int total;
+ int ret;
+ int i;
+
+ /* We don't care about the numbering for this test */
+ dms->skip_post_probe = 1;
+
+ ut_assert(NODE_COUNT > 5);
+
+ /* First create 10 top-level children */
+ ut_assertok(create_children(dms, dms->root, NODE_COUNT, 0, top));
+
+ /* Now a few have their own children */
+ ut_assertok(create_children(dms, top[2], NODE_COUNT, 2, NULL));
+ ut_assertok(create_children(dms, top[5], NODE_COUNT, 5, child));
+
+ /* And grandchildren */
+ for (i = 0; i < NODE_COUNT; i++)
+ ut_assertok(create_children(dms, child[i], NODE_COUNT, 50 * i,
+ i == 2 ? grandchild : NULL));
+
+ /* Check total number of devices */
+ total = NODE_COUNT * (3 + NODE_COUNT);
+ ut_asserteq(total, dm_testdrv_op_count[DM_TEST_OP_BIND]);
+
+ /* Try probing one of the grandchildren */
+ ut_assertok(uclass_get_device(UCLASS_TEST,
+ NODE_COUNT * 3 + 2 * NODE_COUNT, &dev));
+ ut_asserteq_ptr(grandchild[0], dev);
+
+ /*
+ * This should have probed the child and top node also, for a total
+ * of 3 nodes.
+ */
+ ut_asserteq(3, dm_testdrv_op_count[DM_TEST_OP_PROBE]);
+
+ /* Probe the other grandchildren */
+ for (i = 1; i < NODE_COUNT; i++)
+ ut_assertok(device_probe(grandchild[i]));
+
+ ut_asserteq(2 + NODE_COUNT, dm_testdrv_op_count[DM_TEST_OP_PROBE]);
+
+ /* Probe everything */
+ for (ret = uclass_first_device(UCLASS_TEST, &dev);
+ dev;
+ ret = uclass_next_device(&dev))
+ ;
+ ut_assertok(ret);
+
+ ut_asserteq(total, dm_testdrv_op_count[DM_TEST_OP_PROBE]);
+
+ /* Remove a top-level child and check that the children are removed */
+ ut_assertok(device_remove(top[2]));
+ ut_asserteq(NODE_COUNT + 1, dm_testdrv_op_count[DM_TEST_OP_REMOVE]);
+ dm_testdrv_op_count[DM_TEST_OP_REMOVE] = 0;
+
+ /* Try one with grandchildren */
+ ut_assertok(uclass_get_device(UCLASS_TEST, 5, &dev));
+ ut_asserteq_ptr(dev, top[5]);
+ ut_assertok(device_remove(dev));
+ ut_asserteq(1 + NODE_COUNT * (1 + NODE_COUNT),
+ dm_testdrv_op_count[DM_TEST_OP_REMOVE]);
+
+ /* Try the same with unbind */
+ ut_assertok(device_unbind(top[2]));
+ ut_asserteq(NODE_COUNT + 1, dm_testdrv_op_count[DM_TEST_OP_UNBIND]);
+ dm_testdrv_op_count[DM_TEST_OP_UNBIND] = 0;
+
+ /* Try one with grandchildren */
+ ut_assertok(uclass_get_device(UCLASS_TEST, 5, &dev));
+ ut_asserteq_ptr(dev, top[6]);
+ ut_assertok(device_unbind(top[5]));
+ ut_asserteq(1 + NODE_COUNT * (1 + NODE_COUNT),
+ dm_testdrv_op_count[DM_TEST_OP_UNBIND]);
+
+ return 0;
+}
+DM_TEST(dm_test_children, 0);
--- /dev/null
+/*
+ * Copyright (C) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <dm.h>
+#include <dm/ut.h>
+#include <dm/test.h>
+#include <dm/util.h>
+#include <asm/gpio.h>
+
+/* Test that sandbox GPIOs work correctly */
+static int dm_test_gpio(struct dm_test_state *dms)
+{
+ unsigned int offset, gpio;
+ struct dm_gpio_ops *ops;
+ struct device *dev;
+ const char *name;
+ int offset_count;
+ char buf[80];
+
+ /*
+ * We expect to get 3 banks. One is anonymous (just numbered) and
+ * comes from platdata. The other two are named a (20 gpios)
+ * and b (10 gpios) and come from the device tree. See
+ * test/dm/test.dts.
+ */
+ ut_assertok(gpio_lookup_name("b4", &dev, &offset, &gpio));
+ ut_asserteq_str(dev->name, "extra-gpios");
+ ut_asserteq(4, offset);
+ ut_asserteq(CONFIG_SANDBOX_GPIO_COUNT + 20 + 4, gpio);
+
+ name = gpio_get_bank_info(dev, &offset_count);
+ ut_asserteq_str("b", name);
+ ut_asserteq(10, offset_count);
+
+ /* Get the operations for this device */
+ ops = gpio_get_ops(dev);
+ ut_assert(ops->get_state);
+
+ /* Cannot get a value until it is reserved */
+ ut_asserteq(-1, ops->get_value(dev, offset));
+
+ /*
+ * Now some tests that use the 'sandbox' back door. All GPIOs
+ * should default to input, include b4 that we are using here.
+ */
+ ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf)));
+ ut_asserteq_str("b4: in: 0 [ ]", buf);
+
+ /* Change it to an output */
+ sandbox_gpio_set_direction(dev, offset, 1);
+ ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf)));
+ ut_asserteq_str("b4: out: 0 [ ]", buf);
+
+ sandbox_gpio_set_value(dev, offset, 1);
+ ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf)));
+ ut_asserteq_str("b4: out: 1 [ ]", buf);
+
+ ut_assertok(ops->request(dev, offset, "testing"));
+ ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf)));
+ ut_asserteq_str("b4: out: 1 [x] testing", buf);
+
+ /* Change the value a bit */
+ ut_asserteq(1, ops->get_value(dev, offset));
+ ut_assertok(ops->set_value(dev, offset, 0));
+ ut_asserteq(0, ops->get_value(dev, offset));
+ ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf)));
+ ut_asserteq_str("b4: out: 0 [x] testing", buf);
+ ut_assertok(ops->set_value(dev, offset, 1));
+ ut_asserteq(1, ops->get_value(dev, offset));
+
+ /* Make it an input */
+ ut_assertok(ops->direction_input(dev, offset));
+ ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf)));
+ ut_asserteq_str("b4: in: 1 [x] testing", buf);
+ sandbox_gpio_set_value(dev, offset, 0);
+ ut_asserteq(0, sandbox_gpio_get_value(dev, offset));
+ ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf)));
+ ut_asserteq_str("b4: in: 0 [x] testing", buf);
+
+ ut_assertok(ops->free(dev, offset));
+ ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf)));
+ ut_asserteq_str("b4: in: 0 [ ]", buf);
+
+ /* Check the 'a' bank also */
+ ut_assertok(gpio_lookup_name("a15", &dev, &offset, &gpio));
+ ut_asserteq_str(dev->name, "base-gpios");
+ ut_asserteq(15, offset);
+ ut_asserteq(CONFIG_SANDBOX_GPIO_COUNT + 15, gpio);
+
+ name = gpio_get_bank_info(dev, &offset_count);
+ ut_asserteq_str("a", name);
+ ut_asserteq(20, offset_count);
+
+ /* And the anonymous bank */
+ ut_assertok(gpio_lookup_name("14", &dev, &offset, &gpio));
+ ut_asserteq_str(dev->name, "gpio_sandbox");
+ ut_asserteq(14, offset);
+ ut_asserteq(14, gpio);
+
+ name = gpio_get_bank_info(dev, &offset_count);
+ ut_asserteq_ptr(NULL, name);
+ ut_asserteq(CONFIG_SANDBOX_GPIO_COUNT, offset_count);
+
+ return 0;
+}
+DM_TEST(dm_test_gpio, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
--- /dev/null
+#!/bin/sh
+
+NUM_CPUS=$(cat /proc/cpuinfo |grep -c processor)
+dtc -I dts -O dtb test/dm/test.dts -o test/dm/test.dtb
+make O=sandbox sandbox_config
+make O=sandbox -s -j${NUM_CPUS}
+./sandbox/u-boot -d test/dm/test.dtb -c "dm test"
--- /dev/null
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <malloc.h>
+#include <dm/test.h>
+#include <dm/ut.h>
+#include <asm/io.h>
+
+int dm_testdrv_op_count[DM_TEST_OP_COUNT];
+static struct dm_test_state *dms = &global_test_state;
+
+static int testdrv_ping(struct device *dev, int pingval, int *pingret)
+{
+ const struct dm_test_pdata *pdata = dev_get_platdata(dev);
+ struct dm_test_priv *priv = dev_get_priv(dev);
+
+ *pingret = pingval + pdata->ping_add;
+ priv->ping_total += *pingret;
+
+ return 0;
+}
+
+static const struct test_ops test_ops = {
+ .ping = testdrv_ping,
+};
+
+static int test_bind(struct device *dev)
+{
+ /* Private data should not be allocated */
+ ut_assert(!dev_get_priv(dev));
+
+ dm_testdrv_op_count[DM_TEST_OP_BIND]++;
+ return 0;
+}
+
+static int test_probe(struct device *dev)
+{
+ struct dm_test_priv *priv = dev_get_priv(dev);
+
+ /* Private data should be allocated */
+ ut_assert(priv);
+
+ dm_testdrv_op_count[DM_TEST_OP_PROBE]++;
+ priv->ping_total += DM_TEST_START_TOTAL;
+ return 0;
+}
+
+static int test_remove(struct device *dev)
+{
+ /* Private data should still be allocated */
+ ut_assert(dev_get_priv(dev));
+
+ dm_testdrv_op_count[DM_TEST_OP_REMOVE]++;
+ return 0;
+}
+
+static int test_unbind(struct device *dev)
+{
+ /* Private data should not be allocated */
+ ut_assert(!dev->priv);
+
+ dm_testdrv_op_count[DM_TEST_OP_UNBIND]++;
+ return 0;
+}
+
+U_BOOT_DRIVER(test_drv) = {
+ .name = "test_drv",
+ .id = UCLASS_TEST,
+ .ops = &test_ops,
+ .bind = test_bind,
+ .probe = test_probe,
+ .remove = test_remove,
+ .unbind = test_unbind,
+ .priv_auto_alloc_size = sizeof(struct dm_test_priv),
+};
+
+U_BOOT_DRIVER(test2_drv) = {
+ .name = "test2_drv",
+ .id = UCLASS_TEST,
+ .ops = &test_ops,
+ .bind = test_bind,
+ .probe = test_probe,
+ .remove = test_remove,
+ .unbind = test_unbind,
+ .priv_auto_alloc_size = sizeof(struct dm_test_priv),
+};
+
+static int test_manual_drv_ping(struct device *dev, int pingval, int *pingret)
+{
+ *pingret = pingval + 2;
+
+ return 0;
+}
+
+static const struct test_ops test_manual_ops = {
+ .ping = test_manual_drv_ping,
+};
+
+static int test_manual_bind(struct device *dev)
+{
+ dm_testdrv_op_count[DM_TEST_OP_BIND]++;
+
+ return 0;
+}
+
+static int test_manual_probe(struct device *dev)
+{
+ dm_testdrv_op_count[DM_TEST_OP_PROBE]++;
+ if (!dms->force_fail_alloc)
+ dev->priv = calloc(1, sizeof(struct dm_test_priv));
+ if (!dev->priv)
+ return -ENOMEM;
+
+ return 0;
+}
+
+static int test_manual_remove(struct device *dev)
+{
+ dm_testdrv_op_count[DM_TEST_OP_REMOVE]++;
+ return 0;
+}
+
+static int test_manual_unbind(struct device *dev)
+{
+ dm_testdrv_op_count[DM_TEST_OP_UNBIND]++;
+ return 0;
+}
+
+U_BOOT_DRIVER(test_manual_drv) = {
+ .name = "test_manual_drv",
+ .id = UCLASS_TEST,
+ .ops = &test_manual_ops,
+ .bind = test_manual_bind,
+ .probe = test_manual_probe,
+ .remove = test_manual_remove,
+ .unbind = test_manual_unbind,
+};
--- /dev/null
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <dm/test.h>
+#include <dm/root.h>
+#include <dm/ut.h>
+#include <dm/uclass-internal.h>
+#include <dm/util.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int testfdt_drv_ping(struct device *dev, int pingval, int *pingret)
+{
+ const struct dm_test_pdata *pdata = dev->platdata;
+ struct dm_test_priv *priv = dev_get_priv(dev);
+
+ *pingret = pingval + pdata->ping_add;
+ priv->ping_total += *pingret;
+
+ return 0;
+}
+
+static const struct test_ops test_ops = {
+ .ping = testfdt_drv_ping,
+};
+
+static int testfdt_ofdata_to_platdata(struct device *dev)
+{
+ struct dm_test_pdata *pdata = dev_get_platdata(dev);
+
+ pdata->ping_add = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ "ping-add", -1);
+ pdata->base = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
+
+ return 0;
+}
+
+static int testfdt_drv_probe(struct device *dev)
+{
+ struct dm_test_priv *priv = dev_get_priv(dev);
+
+ priv->ping_total += DM_TEST_START_TOTAL;
+
+ return 0;
+}
+
+static const struct device_id testfdt_ids[] = {
+ {
+ .compatible = "denx,u-boot-fdt-test",
+ .data = DM_TEST_TYPE_FIRST },
+ {
+ .compatible = "google,another-fdt-test",
+ .data = DM_TEST_TYPE_SECOND },
+ { }
+};
+
+U_BOOT_DRIVER(testfdt_drv) = {
+ .name = "testfdt_drv",
+ .of_match = testfdt_ids,
+ .id = UCLASS_TEST_FDT,
+ .ofdata_to_platdata = testfdt_ofdata_to_platdata,
+ .probe = testfdt_drv_probe,
+ .ops = &test_ops,
+ .priv_auto_alloc_size = sizeof(struct dm_test_priv),
+ .platdata_auto_alloc_size = sizeof(struct dm_test_pdata),
+};
+
+/* From here is the testfdt uclass code */
+int testfdt_ping(struct device *dev, int pingval, int *pingret)
+{
+ const struct test_ops *ops = device_get_ops(dev);
+
+ if (!ops->ping)
+ return -ENOSYS;
+
+ return ops->ping(dev, pingval, pingret);
+}
+
+UCLASS_DRIVER(testfdt) = {
+ .name = "testfdt",
+ .id = UCLASS_TEST_FDT,
+};
+
+/* Test that FDT-based binding works correctly */
+static int dm_test_fdt(struct dm_test_state *dms)
+{
+ const int num_drivers = 3;
+ struct device *dev;
+ struct uclass *uc;
+ int ret;
+ int i;
+
+ ret = dm_scan_fdt(gd->fdt_blob);
+ ut_assert(!ret);
+
+ ret = uclass_get(UCLASS_TEST_FDT, &uc);
+ ut_assert(!ret);
+
+ /* These are num_drivers compatible root-level device tree nodes */
+ ut_asserteq(num_drivers, list_count_items(&uc->dev_head));
+
+ /* Each should have no platdata / priv */
+ for (i = 0; i < num_drivers; i++) {
+ ret = uclass_find_device(UCLASS_TEST_FDT, i, &dev);
+ ut_assert(!ret);
+ ut_assert(!dev_get_priv(dev));
+ ut_assert(!dev->platdata);
+ }
+
+ /*
+ * Now check that the ping adds are what we expect. This is using the
+ * ping-add property in each node.
+ */
+ for (i = 0; i < num_drivers; i++) {
+ uint32_t base;
+
+ ret = uclass_get_device(UCLASS_TEST_FDT, i, &dev);
+ ut_assert(!ret);
+
+ /*
+ * Get the 'reg' property, which tells us what the ping add
+ * should be. We don't use the platdata because we want
+ * to test the code that sets that up (testfdt_drv_probe()).
+ */
+ base = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
+ debug("dev=%d, base=%d: %s\n", i, base,
+ fdt_get_name(gd->fdt_blob, dev->of_offset, NULL));
+
+ ut_assert(!dm_check_operations(dms, dev, base,
+ dev_get_priv(dev)));
+ }
+
+ return 0;
+}
+DM_TEST(dm_test_fdt, 0);
--- /dev/null
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <dm/test.h>
+#include <dm/root.h>
+#include <dm/uclass-internal.h>
+#include <dm/ut.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct dm_test_state global_test_state;
+
+/* Get ready for testing */
+static int dm_test_init(struct dm_test_state *dms)
+{
+ memset(dms, '\0', sizeof(*dms));
+ gd->dm_root = NULL;
+ memset(dm_testdrv_op_count, '\0', sizeof(dm_testdrv_op_count));
+
+ ut_assertok(dm_init());
+ dms->root = dm_root();
+
+ return 0;
+}
+
+/* Ensure all the test devices are probed */
+static int do_autoprobe(struct dm_test_state *dms)
+{
+ struct device *dev;
+ int ret;
+
+ /* Scanning the uclass is enough to probe all the devices */
+ for (ret = uclass_first_device(UCLASS_TEST, &dev);
+ dev;
+ ret = uclass_next_device(&dev))
+ ;
+
+ return ret;
+}
+
+static int dm_test_destroy(struct dm_test_state *dms)
+{
+ int id;
+
+ for (id = 0; id < UCLASS_COUNT; id++) {
+ struct uclass *uc;
+
+ /*
+ * If the uclass doesn't exist we don't want to create it. So
+ * check that here before we call uclass_find_device()/
+ */
+ uc = uclass_find(id);
+ if (!uc)
+ continue;
+ ut_assertok(uclass_destroy(uc));
+ }
+
+ return 0;
+}
+
+int dm_test_main(void)
+{
+ struct dm_test *tests = ll_entry_start(struct dm_test, dm_test);
+ const int n_ents = ll_entry_count(struct dm_test, dm_test);
+ struct dm_test_state *dms = &global_test_state;
+ struct dm_test *test;
+
+ /*
+ * If we have no device tree, or it only has a root node, then these
+ * tests clearly aren't going to work...
+ */
+ if (!gd->fdt_blob || fdt_next_node(gd->fdt_blob, 0, NULL) < 0) {
+ puts("Please run with test device tree:\n"
+ " dtc -I dts -O dtb test/dm/test.dts -o test/dm/test.dtb\n"
+ " ./u-boot -d test/dm/test.dtb\n");
+ ut_assert(gd->fdt_blob);
+ }
+
+ printf("Running %d driver model tests\n", n_ents);
+
+ for (test = tests; test < tests + n_ents; test++) {
+ printf("Test: %s\n", test->name);
+ ut_assertok(dm_test_init(dms));
+
+ if (test->flags & DM_TESTF_SCAN_PDATA)
+ ut_assertok(dm_scan_platdata());
+ if (test->flags & DM_TESTF_PROBE_TEST)
+ ut_assertok(do_autoprobe(dms));
+ if (test->flags & DM_TESTF_SCAN_FDT)
+ ut_assertok(dm_scan_fdt(gd->fdt_blob));
+
+ if (test->func(dms))
+ break;
+
+ ut_assertok(dm_test_destroy(dms));
+ }
+
+ printf("Failures: %d\n", dms->fail_count);
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <dm.h>
+#include <errno.h>
+#include <dm/test.h>
+#include <dm/ut.h>
+#include <asm/io.h>
+#include <linux/list.h>
+
+static struct dm_test_state *dms = &global_test_state;
+
+int test_ping(struct device *dev, int pingval, int *pingret)
+{
+ const struct test_ops *ops = device_get_ops(dev);
+
+ if (!ops->ping)
+ return -ENOSYS;
+
+ return ops->ping(dev, pingval, pingret);
+}
+
+static int test_post_bind(struct device *dev)
+{
+ dm_testdrv_op_count[DM_TEST_OP_POST_BIND]++;
+
+ return 0;
+}
+
+static int test_pre_unbind(struct device *dev)
+{
+ dm_testdrv_op_count[DM_TEST_OP_PRE_UNBIND]++;
+
+ return 0;
+}
+
+static int test_post_probe(struct device *dev)
+{
+ struct device *prev = list_entry(dev->uclass_node.prev, struct device,
+ uclass_node);
+ struct dm_test_uclass_perdev_priv *priv = dev->uclass_priv;
+ struct uclass *uc = dev->uclass;
+
+ dm_testdrv_op_count[DM_TEST_OP_POST_PROBE]++;
+ ut_assert(priv);
+ ut_assert(device_active(dev));
+ priv->base_add = 0;
+ if (dms->skip_post_probe)
+ return 0;
+ if (&prev->uclass_node != &uc->dev_head) {
+ struct dm_test_uclass_perdev_priv *prev_uc_priv
+ = prev->uclass_priv;
+ struct dm_test_pdata *pdata = prev->platdata;
+
+ ut_assert(pdata);
+ ut_assert(prev_uc_priv);
+ priv->base_add = prev_uc_priv->base_add + pdata->ping_add;
+ }
+
+ return 0;
+}
+
+static int test_pre_remove(struct device *dev)
+{
+ dm_testdrv_op_count[DM_TEST_OP_PRE_REMOVE]++;
+
+ return 0;
+}
+
+static int test_init(struct uclass *uc)
+{
+ dm_testdrv_op_count[DM_TEST_OP_INIT]++;
+ ut_assert(uc->priv);
+
+ return 0;
+}
+
+static int test_destroy(struct uclass *uc)
+{
+ dm_testdrv_op_count[DM_TEST_OP_DESTROY]++;
+
+ return 0;
+}
+
+UCLASS_DRIVER(test) = {
+ .name = "test",
+ .id = UCLASS_TEST,
+ .post_bind = test_post_bind,
+ .pre_unbind = test_pre_unbind,
+ .post_probe = test_post_probe,
+ .pre_remove = test_pre_remove,
+ .init = test_init,
+ .destroy = test_destroy,
+ .priv_auto_alloc_size = sizeof(struct dm_test_uclass_priv),
+ .per_device_auto_alloc_size = sizeof(struct dm_test_uclass_perdev_priv),
+};
--- /dev/null
+/dts-v1/;
+
+/ {
+ model = "sandbox";
+ compatible = "sandbox";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ a-test {
+ reg = <0>;
+ compatible = "denx,u-boot-fdt-test";
+ ping-add = <0>;
+ };
+
+ junk {
+ reg = <1>;
+ compatible = "not,compatible";
+ };
+
+ no-compatible {
+ reg = <2>;
+ };
+
+ b-test {
+ reg = <3>;
+ compatible = "denx,u-boot-fdt-test";
+ ping-add = <3>;
+ };
+
+ some-bus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ ping-add = <4>;
+ c-test {
+ compatible = "denx,u-boot-fdt-test";
+ reg = <5>;
+ ping-add = <5>;
+ };
+ };
+
+ d-test {
+ reg = <6>;
+ ping-add = <6>;
+ compatible = "google,another-fdt-test";
+ };
+
+ base-gpios {
+ compatible = "sandbox,gpio";
+ gpio-bank-name = "a";
+ num-gpios = <20>;
+ };
+
+ extra-gpios {
+ compatible = "sandbox,gpio";
+ gpio-bank-name = "b";
+ num-gpios = <10>;
+ };
+};
--- /dev/null
+/*
+ * Simple unit test library for driver model
+ *
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm/test.h>
+#include <dm/ut.h>
+
+struct dm_test_state;
+
+void ut_fail(struct dm_test_state *dms, const char *fname, int line,
+ const char *func, const char *cond)
+{
+ printf("%s:%d, %s(): %s\n", fname, line, func, cond);
+ dms->fail_count++;
+}
+
+void ut_failf(struct dm_test_state *dms, const char *fname, int line,
+ const char *func, const char *cond, const char *fmt, ...)
+{
+ va_list args;
+
+ printf("%s:%d, %s(): %s: ", fname, line, func, cond);
+ va_start(args, fmt);
+ vprintf(fmt, args);
+ va_end(args);
+ putc('\n');
+ dms->fail_count++;
+}
LOGO_BMP= $(srctree)/$(src)/logos/denx.bmp
# Use board logo and fallback to vendor
-ifneq ($(wildcard logos/$(BOARD).bmp),)
+ifneq ($(wildcard $(srctree)/$(src)/logos/$(BOARD).bmp),)
LOGO_BMP= $(srctree)/$(src)/logos/$(BOARD).bmp
else
-ifneq ($(wildcard logos/$(VENDOR).bmp),)
+ifneq ($(wildcard $(srctree)/$(src)/logos/$(VENDOR).bmp),)
LOGO_BMP= $(srctree)/$(src)/logos/$(VENDOR).bmp
endif
endif
# Define __KERNEL_STRICT_NAMES to prevent typedef overlaps
# Define _GNU_SOURCE to obtain the getline prototype from stdio.h
#
-HOST_EXTRACFLAGS += -include $(SRCTREE)/include/libfdt_env.h \
+HOST_EXTRACFLAGS += -include $(srctree)/include/libfdt_env.h \
$(patsubst -I%,-idirafter%, $(UBOOTINCLUDE)) \
- -I$(SRCTREE)/lib/libfdt \
- -I$(SRCTREE)/tools \
+ -I$(srctree)/lib/libfdt \
+ -I$(srctree)/tools \
-DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \
-DUSE_HOSTCC \
-D__KERNEL_STRICT_NAMES \
# Let clean descend into subdirs
subdir- += env
+
+ifneq ($(CROSS_BUILD_TOOLS),)
+HOSTCC = $(CC)
+
+quiet_cmd_crosstools_strip = STRIP $^
+ cmd_crosstools_strip = $(STRIP) $^; touch $@
+$(obj)/.strip: $(call objectify,$(filter $(always),$(hostprogs-y)))
+ $(call cmd,crosstools_strip)
+
+always += .strip
+endif
+clean-files += .strip
# Compile for a hosted environment on the target
HOST_EXTRACFLAGS = $(patsubst -I%,-idirafter%, $(UBOOTINCLUDE)) \
- -idirafter $(SRCTREE)/tools/env \
+ -idirafter $(srctree)/tools/env \
-DUSE_HOSTCC \
-DTEXT_BASE=$(TEXT_BASE)
if (mtd_type != MTD_ABSENT)
ioctl(fd, MEMLOCK, &erase);
- processed += blocklen;
+ processed += erasesize;
block_seek = 0;
- blockstart += blocklen;
+ blockstart += erasesize;
}
if (write_total > count)
strcpy (DEVNAME (0), DEVICE1_NAME);
DEVOFFSET (0) = DEVICE1_OFFSET;
ENVSIZE (0) = ENV1_SIZE;
- /* Default values are: erase-size=env-size, #sectors=1 */
+ /* Default values are: erase-size=env-size */
DEVESIZE (0) = ENVSIZE (0);
- ENVSECTORS (0) = 1;
+ /* #sectors=env-size/erase-size (rounded up) */
+ ENVSECTORS (0) = (ENVSIZE(0) + DEVESIZE(0) - 1) / DEVESIZE(0);
#ifdef DEVICE1_ESIZE
DEVESIZE (0) = DEVICE1_ESIZE;
#endif
strcpy (DEVNAME (1), DEVICE2_NAME);
DEVOFFSET (1) = DEVICE2_OFFSET;
ENVSIZE (1) = ENV2_SIZE;
- /* Default values are: erase-size=env-size, #sectors=1 */
+ /* Default values are: erase-size=env-size */
DEVESIZE (1) = ENVSIZE (1);
- ENVSECTORS (1) = 1;
+ /* #sectors=env-size/erase-size (rounded up) */
+ ENVSECTORS (1) = (ENVSIZE(1) + DEVESIZE(1) - 1) / DEVESIZE(1);
#ifdef DEVICE2_ESIZE
DEVESIZE (1) = DEVICE2_ESIZE;
#endif
DEVESIZE(i) = ENVSIZE(i);
if (rc < 5)
- /* Default - 1 sector */
- ENVSECTORS (i) = 1;
+ /* Assume enough env sectors to cover the environment */
+ ENVSECTORS (i) = (ENVSIZE(i) + DEVESIZE(i) - 1) / DEVESIZE(i);
i++;
}
# Configuration file for fw_(printenv/setenv) utility.
# Up to two entries are valid, in this case the redundant
# environment sector is assumed present.
-# Notice, that the "Number of sectors" is ignored on NOR and SPI-dataflash.
+# Notice, that the "Number of sectors" is not required on NOR and SPI-dataflash.
# Futhermore, if the Flash sector size is ommitted, this value is assumed to
# be the same as the Environment size, which is valid for NOR and SPI-dataflash
projects / karo-tx-uboot.git / commitdiff