the hosted environment to call out to the emulator to
retrieve files from the host machine.
-config SOC_AM335X
- bool
- select CPU_V7
- select OMAP_COMMON
+config SYS_ICACHE_OFF
+ bool "Do not use Instruction Cache"
-config SOC_MXS
- bool
- select CPU_ARM926EJS
+config SYS_DCACHE_OFF
+ bool "Do not use Data Cache"
-config SOC_MX23
- bool
- select SOC_MXS
+config SYS_L2CACHE_OFF
+ bool "Do not use L2 cache"
-config SOC_MX28
- bool
- select SOC_MXS
+config ARCH_MXS
+ bool "Freescale i.MX23 & i.MX28"
+ select CPU_ARM926EJS
-config SOC_MX5
- bool
+config ARCH_MX6
+ bool "Freescale MX6"
select CPU_V7
-config SOC_MX53
- bool
- select SOC_MX5
-
-config SOC_MX51
- bool
- select SOC_MX5
-
-config SOC_MX53
- bool
- select SOC_MX5
-
-config SOC_MX6
- bool
+config ARCH_MX5
+ bool "Freescale MX5"
select CPU_V7
-config SOC_MX6Q
- bool
- select SOC_MX6
-
-config SOC_MX6DL
- bool
- select SOC_MX6
-
-config SOC_MX6S
- bool
- select SOC_MX6
-
-config SOC_MX6SX
+config SOC_AM335X
bool
- select SOC_MX6
+ select CPU_V7
+ select OMAP_COMMON
config SOC_SAMA5D4
bool
config TARGET_TX6
bool "Support tx6"
- select SOC_MX6
config TARGET_ZMX25
bool "Support zmx25"
select CPU_V7
select SUPPORT_SPL
-config ARCH_MX6
- bool "Freescale MX6"
- select CPU_V7
-
-config ARCH_MX5
- bool "Freescale MX5"
- select CPU_V7
-
config TARGET_M53EVK
bool "Support m53evk"
select CPU_V7
config TARGET_MX6UL_14X14_EVK
bool "Support mx6ul_14x14_evk"
- select CPU_V7
+ select SOC_MX6UL
select DM
select DM_THERMAL
select SUPPORT_SPL
source "arch/arm/mach-kirkwood/Kconfig"
+source "arch/arm/cpu/arm926ejs/mxs/Kconfig"
+
source "arch/arm/cpu/armv7/mx6/Kconfig"
source "arch/arm/cpu/armv7/mx5/Kconfig"
--- /dev/null
+if ARCH_MXS
+
+config SOC_MX23
+ bool
+
+config SOC_MX28
+ bool
+
+endif
obj-y += cpu.o cp15.o
obj-y += syslib.o
-ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_SOC_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_ARCH_SOCFPGA),)
+ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_ARCH_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_ARCH_SOCFPGA),)
ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
obj-y += lowlevel_init.o
endif
obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/
obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/
obj-$(if $(filter mx5,$(SOC)),y) += mx5/
-obj-$(CONFIG_SOC_MX6) += mx6/
+obj-$(CONFIG_ARCH_MX6) += mx6/
obj-$(CONFIG_OMAP34XX) += omap3/
obj-$(CONFIG_OMAP44XX) += omap4/
obj-$(CONFIG_OMAP54XX) += omap5/
if ARCH_MX5
-config SOC_MX5
- bool
- default y
-
config SOC_MX51
bool
if ARCH_MX6
-config SOC_MX6
- bool
- default y
-
config SOC_MX6D
bool
bool
config SOC_MX6UL
- select SYS_L2CACHE_OFF
bool
choice
}
}
-void ocotp_clk_enable(void)
-{
- u32 reg = readl(&imx_ccm->CCGR2);
- reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
- writel(reg, &imx_ccm->CCGR2);
-}
-
-void ocotp_clk_disable(void)
-{
- u32 reg = readl(&imx_ccm->CCGR2);
- reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
- writel(reg, &imx_ccm->CCGR2);
-}
-
unsigned int mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {
}
#endif
-#ifdef CONFIG_MX6UL
+#ifdef CONFIG_SOC_MX6UL
void mx6ul_dram_iocfg(unsigned width,
const struct mx6ul_iomux_ddr_regs *ddr,
const struct mx6ul_iomux_grp_regs *grp)
#include <common.h>
#include <div64.h>
#include <ipu.h>
+#include <fuse.h>
+#include <thermal.h>
#include <asm/armv7.h>
#include <asm/bootm.h>
#include <asm/pl310.h>
u32 get_cpu_speed_grade_hz(void)
{
- struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
- struct fuse_bank *bank = &ocotp->bank[0];
- struct fuse_bank0_regs *fuse =
- (struct fuse_bank0_regs *)bank->fuse_regs;
uint32_t val;
- val = readl(&fuse->cfg3);
+ if (fuse_read(0, 3, &val)) {
+ printf("Failed to read speed_grade fuse\n");
+ return 0;
+ }
val >>= OCOTP_CFG3_SPEED_SHIFT;
val &= 0x3;
u32 get_cpu_temp_grade(int *minc, int *maxc)
{
- struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
- struct fuse_bank *bank = &ocotp->bank[1];
- struct fuse_bank1_regs *fuse =
- (struct fuse_bank1_regs *)bank->fuse_regs;
uint32_t val;
- val = readl(&fuse->mem0);
+ if (fuse_read(1, 0, &val)) {
+ printf("Failed to read temp_grade fuse\n");
+ val = 0;
+ }
val >>= OCOTP_MEM0_TEMP_SHIFT;
val &= 0x3;
struct aipstz_regs *aips3;
#endif
- aips1 = (struct aipstz_regs *)AIPS1_ARB_BASE_ADDR;
- aips2 = (struct aipstz_regs *)AIPS2_ARB_BASE_ADDR;
+ aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
+ aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
#ifdef CONFIG_SOC_MX6SX
- aips3 = (struct aipstz_regs *)AIPS3_ARB_BASE_ADDR;
+ aips3 = (struct aipstz_regs *)AIPS3_CONFIG_BASE_ADDR;
#endif
/*
return 0;
}
-static u32 __data thermal_calib;
-
-#define FACTOR0 10000000
-#define FACTOR1 15976
-#define FACTOR2 4297157
-
-int raw_to_celsius(unsigned int raw, unsigned int raw_25c, unsigned int raw_hot,
- unsigned int hot_temp)
-{
- int temperature;
-
- if (raw_hot != 0 && hot_temp != 0) {
- unsigned int raw_n40c, ratio;
-
- ratio = ((raw_25c - raw_hot) * 100) / (hot_temp - 25);
- raw_n40c = raw_25c + (13 * ratio) / 20;
- if (raw <= raw_n40c)
- temperature = (raw_n40c - raw) * 100 / ratio - 40;
- else
- temperature = TEMPERATURE_MIN;
- } else {
- u64 temp64 = FACTOR0;
- unsigned int c1, c2;
- /*
- * Derived from linear interpolation:
- * slope = 0.4297157 - (0.0015976 * 25C fuse)
- * slope = (FACTOR2 - FACTOR1 * n1) / FACTOR0
- * (Nmeas - n1) / (Tmeas - t1) = slope
- * We want to reduce this down to the minimum computation necessary
- * for each temperature read. Also, we want Tmeas in millicelsius
- * and we don't want to lose precision from integer division. So...
- * Tmeas = (Nmeas - n1) / slope + t1
- * milli_Tmeas = 1000 * (Nmeas - n1) / slope + 1000 * t1
- * milli_Tmeas = -1000 * (n1 - Nmeas) / slope + 1000 * t1
- * Let constant c1 = (-1000 / slope)
- * milli_Tmeas = (n1 - Nmeas) * c1 + 1000 * t1
- * Let constant c2 = n1 *c1 + 1000 * t1
- * milli_Tmeas = c2 - Nmeas * c1
- */
- temp64 *= 1000;
- do_div(temp64, FACTOR1 * raw_25c - FACTOR2);
- c1 = temp64;
- c2 = raw_25c * c1 + 1000 * 25;
- temperature = (c2 - raw * c1) / 1000;
- }
- return temperature;
-}
-
-int read_cpu_temperature(void)
-{
- unsigned int reg, tmp, i;
- unsigned int raw_25c, raw_hot, hot_temp;
- int temperature;
- struct anatop_regs *const anatop = (void *)ANATOP_BASE_ADDR;
- struct mx6_ocotp_regs *const ocotp_regs = (void *)OCOTP_BASE_ADDR;
-
- if (!thermal_calib) {
- ocotp_clk_enable();
- writel(1, &ocotp_regs->hw_ocotp_read_ctrl);
- thermal_calib = readl(&ocotp_regs->hw_ocotp_ana1);
- writel(0, &ocotp_regs->hw_ocotp_read_ctrl);
- ocotp_clk_disable();
- }
-
- if (thermal_calib == 0 || thermal_calib == 0xffffffff)
- return TEMPERATURE_MIN;
-
- /* Fuse data layout:
- * [31:20] sensor value @ 25C
- * [19:8] sensor value of hot
- * [7:0] hot temperature value */
- raw_25c = thermal_calib >> 20;
- raw_hot = (thermal_calib & 0xfff00) >> 8;
- hot_temp = thermal_calib & 0xff;
-
- /* now we only using single measure, every time we measure
- * the temperature, we will power on/off the anadig module
- */
- writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_clr);
- writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
-
- /* write measure freq */
- writel(327, &anatop->tempsense1);
- writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_clr);
- writel(BM_ANADIG_TEMPSENSE0_FINISHED, &anatop->tempsense0_clr);
- writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_set);
-
- /* average the temperature value over multiple readings */
- for (i = 0; i < TEMP_AVG_COUNT; i++) {
- static int failed;
- int limit = 100;
-
- while ((readl(&anatop->tempsense0) &
- BM_ANADIG_TEMPSENSE0_FINISHED) == 0) {
- udelay(10000);
- if (--limit < 0)
- break;
- }
- if ((readl(&anatop->tempsense0) &
- BM_ANADIG_TEMPSENSE0_FINISHED) == 0) {
- if (!failed) {
- printf("Failed to read temp sensor\n");
- failed = 1;
- }
- return 0;
- }
- failed = 0;
- reg = (readl(&anatop->tempsense0) &
- BM_ANADIG_TEMPSENSE0_TEMP_VALUE) >>
- BP_ANADIG_TEMPSENSE0_TEMP_VALUE;
- if (i == 0)
- tmp = reg;
- else
- tmp = (tmp * i + reg) / (i + 1);
- writel(BM_ANADIG_TEMPSENSE0_FINISHED,
- &anatop->tempsense0_clr);
- }
-
- temperature = raw_to_celsius(tmp, raw_25c, raw_hot, hot_temp);
-
- /* power down anatop thermal sensor */
- writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_set);
- writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_clr);
-
- return temperature;
-}
-
int check_cpu_temperature(int boot)
{
+ int ret;
static int __data max_temp;
int boot_limit = getenv_ulong("max_boot_temp", 10, TEMPERATURE_HOT);
- int tmp = read_cpu_temperature();
+ int tmp;
+ struct udevice *dev;
bool first = true;
+ if (uclass_get_device_by_name(UCLASS_THERMAL, "imx_thermal", &dev)) {
+ if (first) {
+ printf("No thermal device found; cannot read CPU temperature\n");
+ first = false;
+ }
+ return 0;
+ }
+
+ ret = thermal_get_temp(dev, &tmp);
+ if (ret) {
+ printf("Failed to read temperature: %d\n", ret);
+ return TEMPERATURE_MAX;
+ }
if (tmp < TEMPERATURE_MIN || tmp > TEMPERATURE_MAX) {
printf("Temperature: can't get valid data!\n");
return tmp;
if (!boot) {
if (tmp > boot_limit) {
- printf("CPU is %d C, too hot, resetting...\n", tmp);
+ printf("CPU is %d C; too hot, resetting...\n", tmp);
udelay(100000);
reset_cpu(0);
}
max_temp = tmp;
}
} else {
- printf("Temperature: %d C, calibration data 0x%x\n",
- tmp, thermal_calib);
while (tmp >= boot_limit) {
if (first) {
- printf("CPU is %d C, too hot to boot, waiting...\n",
+ printf("CPU is %d C; too hot to boot, waiting...\n",
tmp);
first = false;
}
if (ctrlc())
break;
udelay(50000);
- tmp = read_cpu_temperature();
+ ret = thermal_get_temp(dev, &tmp);
+ if (ret < 0) {
+ printf("Failed to read temperature: %d\n", ret);
+ return TEMPERATURE_MAX;
+ }
if (tmp > boot_limit - TEMP_WARN_THRESHOLD && tmp != max_temp)
printf("WARNING: CPU temperature %d C\n", tmp);
max_temp = tmp;
#if defined(CONFIG_FEC_MXC)
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
- struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
- struct fuse_bank *bank = &ocotp->bank[4];
- struct fuse_bank4_regs *fuse =
- (struct fuse_bank4_regs *)bank->fuse_regs;
-
- u32 value = readl(&fuse->mac_addr_high);
- mac[0] = (value >> 8);
- mac[1] = value;
-
- value = readl(&fuse->mac_addr_low);
- mac[2] = value >> 24;
- mac[3] = value >> 16;
- mac[4] = value >> 8;
- mac[5] = value;
+ unsigned int mac0, mac1;
+
+ memset(mac, 0, 6);
+ if (dev_id < 0 || dev_id > 2)
+ return;
+
+ if (fuse_read(4, 2, &mac0)) {
+ printf("Failed to read MAC0 fuse\n");
+ return;
+ }
+ if (fuse_read(4, 3, &mac1)) {
+ printf("Failed to read MAC1 fuse\n");
+ return;
+ }
+ mac[0] = mac1 >> 8;
+ mac[1] = mac1;
+ mac[2] = mac0 >> 24;
+ mac[3] = mac0 >> 16;
+ if (dev_id == 0) {
+ mac[4] = mac0 >> 8;
+ mac[5] = mac0;
+ } else {
+ mac[4] = mac1 >> 24;
+ mac[5] = mac1 >> 16;
+ }
}
#endif
}
#endif
-#if defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_SOC_MX53) || defined(CONFIG_ARCH_MX6)
#if defined(CONFIG_SOC_MX53)
#define MEMCTL_BASE ESDCTL_BASE_ADDR
#else
u32 cpurev;
__maybe_unused u32 max_freq;
-#if defined(CONFIG_SOC_MX6) && defined(CONFIG_IMX6_THERMAL)
+#if defined(CONFIG_ARCH_MX6) && defined(CONFIG_IMX6_THERMAL)
struct udevice *thermal_dev;
int cpu_tmp, minc, maxc, ret;
#endif
cpurev = get_cpu_rev();
-#if defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_ARCH_MX6)
printf("CPU: Freescale i.MX%s rev%d.%d",
get_imx_type((cpurev & 0xFF000) >> 12),
(cpurev & 0x000F0) >> 4,
mxc_get_clock(MXC_ARM_CLK) / 1000000);
#endif
-#if defined(CONFIG_SOC_MX6) && defined(CONFIG_IMX6_THERMAL)
+#if defined(CONFIG_ARCH_MX6) && defined(CONFIG_IMX6_THERMAL)
puts("CPU: ");
switch (get_cpu_temp_grade(&minc, &maxc)) {
case TEMP_AUTOMOTIVE:
{
int rc = -ENODEV;
-#if defined(CONFIG_FEC_MXC)
+#if defined(CONFIG_FEC_MXC) && defined(CONFIG_FEC_MXC_PHYADDR)
rc = fecmxc_initialize(bis);
#endif
{
#if defined(CONFIG_CMD_SATA)
sata_stop();
-#if defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_ARCH_MX6)
disable_sata_clock();
#endif
#endif
#include <asm/spl.h>
#include <spl.h>
-#if defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_ARCH_MX6)
/* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 register */
u32 spl_boot_device(void)
{
static inline int gpt_has_clk_source_osc(void)
{
-#if defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_ARCH_MX6)
if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) &&
(soc_rev() > CHIP_REV_1_0)) || is_cpu_type(MXC_CPU_MX6DL) ||
is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX) ||
void set_chipselect_size(int const);
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-
-int fecmxc_initialize(bd_t *bis);
u32 get_ahb_clk(void);
u32 get_periph_clk(void);
void ipu_di_clk_disable(int di);
void ldb_clk_enable(int ldb);
void ldb_clk_disable(int ldb);
-void ocotp_clk_enable(void);
-void ocotp_clk_disable(void);
#endif /* __ASM_ARCH_CLOCK_H */
#define HAB_ENG_RTL 0x77 /* RTL simulation engine */
#define HAB_ENG_SW 0xff /* Software engine */
-#ifdef CONFIG_SOC_MX6SX
-#define HAB_RVT_BASE 0x00000100
-#else
-#define HAB_RVT_BASE 0x00000094
-#endif
-
static inline void **hab_rvt_base(void)
{
- uint32_t *base;
-
- if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) &&
- soc_rev() >= CHIP_REV_1_5) ||
- (is_cpu_type(MXC_CPU_MX6DL) && soc_rev() >= CHIP_REV_1_2) ||
- is_cpu_type(MXC_CPU_MX6SOLO))
- base = (void *)0x98;
- else
- base = (void *)0x94;
- if ((*base & 0xff0000ff) != cpu_to_be32(0xdd000041)) {
- printf("Invalid RVT @ %p\n", base);
+ unsigned long base;
+ int cpu_type = get_cpu_type();
+ int rev = soc_rev();
+ const uint32_t mask = 0xfc0000ff;
+
+ switch (cpu_type) {
+ case MXC_CPU_MX6Q:
+ case MXC_CPU_MX6D:
+ if (rev >= CHIP_REV_1_5)
+ base = 0x98UL;
+ else
+ base = 0x94UL;
+ break;
+ case MXC_CPU_MX6DL:
+ if (rev >= CHIP_REV_1_2)
+ base = 0x98UL;
+ else
+ base = 0x94UL;
+ break;
+ case MXC_CPU_MX6SOLO:
+ base = 0x98UL;
+ break;
+ case MXC_CPU_MX6SX:
+ case MXC_CPU_MX6UL:
+ base = 0x100UL;
+ break;
+ default:
+ printf("Unsupported CPU type: %02x\n", cpu_type);
+ return NULL;
+ }
+
+ if (((rev = readl(base)) & mask) != cpu_to_be32(0xdd000040)) {
+ printf("Invalid RVT @ %08lx: %08x:%08x\n",
+ base, rev, rev & mask);
return NULL;
}
return (void **)base;
#ifndef CONFIG_SPL_BUILD
#ifdef CONFIG_SOC_MX6Q
#include "mx6q-ddr.h"
-#else
-#if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
+#elif defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
#include "mx6dl-ddr.h"
-#else
-#ifdef CONFIG_SOC_MX6SX
+#elif defined(CONFIG_SOC_MX6SX)
#include "mx6sx-ddr.h"
-#else
-#ifdef CONFIG_SOC_MX6UL
+#elif defined(CONFIG_SOC_MX6UL)
#include "mx6ul-ddr.h"
#else
#error "Please select cpu"
-#endif /* CONFIG_SOC_MX6UL */
-#endif /* CONFIG_SOC_MX6SX */
-#endif /* CONFIG_SOC_MX6DL or CONFIG_SOC_MX6S */
-#endif /* CONFIG_SOC_MX6Q */
+#endif
#else
/* MMDC P0/P1 Registers */
#ifndef __ASM_ARCH_MX6UL_DDR_H__
#define __ASM_ARCH_MX6UL_DDR_H__
-#ifndef CONFIG_MX6UL
+#ifndef CONFIG_SOC_MX6UL
#error "wrong CPU"
#endif
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-
-int fecmxc_initialize(bd_t *bis);
u32 get_ahb_clk(void);
u32 get_periph_clk(void);
uint32_t mask,
unsigned int timeout);
-int read_cpu_temperature(void);
int check_cpu_temperature(int boot);
#endif
MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
MXS_MAX_DMA_CHANNELS,
};
-#elif defined(CONFIG_SOC_MX6)
+#elif defined(CONFIG_ARCH_MX6)
enum {
MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0,
MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
#define __PAD_CTRL_VALID (1 << 17)
#define PAD_CTRL_VALID ((iomux_v3_cfg_t)__PAD_CTRL_VALID << MUX_PAD_CTRL_SHIFT)
-#ifdef CONFIG_SOC_MX6
+#ifdef CONFIG_ARCH_MX6
#define PAD_CTL_HYS __MUX_PAD_CTRL(1 << 16)
mxs_reg_32(hw_apbh_version);
};
-#elif (defined(CONFIG_SOC_MX28) || defined(CONFIG_SOC_MX6))
+#elif (defined(CONFIG_SOC_MX28) || defined(CONFIG_ARCH_MX6))
struct mxs_apbh_regs {
mxs_reg_32(hw_apbh_ctrl0); /* 0x000 */
mxs_reg_32(hw_apbh_ctrl1); /* 0x010 */
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800
#define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000
#define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000
-#elif defined(CONFIG_SOC_MX6)
+#elif defined(CONFIG_ARCH_MX6)
#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0001
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0002
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000
#endif
-#if defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_ARCH_MX6)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16
#endif
#define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24
#define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << 16)
#define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16
-#if defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_ARCH_MX6)
#define BCH_FLASHLAYOUT0_ECC0_MASK (0x1f << 11)
#define BCH_FLASHLAYOUT0_ECC0_OFFSET 11
#else
#define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16)
#define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16
-#if defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_ARCH_MX6)
#define BCH_FLASHLAYOUT1_ECCN_MASK (0x1f << 11)
#define BCH_FLASHLAYOUT1_ECCN_OFFSET 11
#else
#include <linux/kbuild.h>
#if defined(CONFIG_SOC_MX25) || defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX35) \
- || defined(CONFIG_SOC_MX51) || defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)
+ || defined(CONFIG_SOC_MX51) || defined(CONFIG_SOC_MX53) || defined(CONFIG_ARCH_MX6)
#include <asm/arch/imx-regs.h>
#endif
-#if defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_ARCH_MX6)
#include <asm/arch/crm_regs.h>
#endif
DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd));
DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn));
#endif
-#if defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_ARCH_MX6)
DEFINE(CCM_CCR, offsetof(struct mxc_ccm_reg, ccr));
DEFINE(CCM_CCDR, offsetof(struct mxc_ccm_reg, ccdr));
DEFINE(CCM_CSR, offsetof(struct mxc_ccm_reg, csr));
karo_fdt_enable_node(blob, "stk5led", 0);
fdt_fixup_mtdparts(blob, tx28_nand_nodes, ARRAY_SIZE(tx28_nand_nodes));
- fdt_fixup_ethernet(blob);
karo_fdt_fixup_touchpanel(blob, tx28_touchpanels,
ARRAY_SIZE(tx28_touchpanels));
return ret;
}
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
- fdt_fixup_ethernet(blob);
karo_fdt_fixup_touchpanel(blob, tx48_touchpanels,
ARRAY_SIZE(tx48_touchpanels));
return ret;
}
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
- fdt_fixup_ethernet(blob);
karo_fdt_fixup_touchpanel(blob, tx51_touchpanels,
ARRAY_SIZE(tx51_touchpanels));
karo_fdt_enable_node(blob, "stk5led", 0);
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
- fdt_fixup_ethernet(blob);
karo_fdt_fixup_touchpanel(blob, tx53_touchpanels,
ARRAY_SIZE(tx53_touchpanels));
select DM_THERMAL
select FSL_ESDHC if MMC
select FSL_USDHC if MMC
+ select IMX6_THERMAL
select LIB_RAND
select PHYLIB
- select SYS_I2C
- select SYS_I2C_MXC
select GET_FEC_MAC_ADDR_FROM_IIM if FEC_MXC
select MXC_OCOTP if CMD_FUSE
select OF_BOARD_SETUP
select MMC
select SUPPORT_EMMC_BOOT
+config TX6UL
+ bool
+ select SOC_MX6UL
+ select SYS_SDRAM_BUS_WIDTH_16
+
#
# variables selected depending on module variant
#
config SYS_SDRAM_BUS_WIDTH_32
bool
-
choice
prompt "TX6 module variant"
config TARGET_TX6Q_1020
bool "TX6Q-1020"
select SOC_MX6Q
+ select SYS_I2C
+ select SYS_I2C_MXC
select TX6_EMMC
config TARGET_TX6Q_1033
bool "TX6Q-1033"
select SOC_MX6Q
+ select SYS_I2C
+ select SYS_I2C_MXC
select TX6_EMMC
config TARGET_TX6Q_10X0
bool "TX6Q-1010 and TX6Q-1030"
select SOC_MX6Q
+ select SYS_I2C
+ select SYS_I2C_MXC
config TARGET_TX6Q_11X0
bool "TX6Q-1110 and TX6Q-1130"
select SOC_MX6Q
+ select SYS_I2C
+ select SYS_I2C_MXC
select SYS_LVDS_IF
config TARGET_TX6S_8034
bool "TX6S-8034"
select SOC_MX6S
+ select SYS_I2C
+ select SYS_I2C_MXC
select SYS_SDRAM_BUS_WIDTH_16
config TARGET_TX6S_8035
bool "TX6S-8035"
select SOC_MX6S
- select TX6_EMMC
+ select SYS_I2C
+ select SYS_I2C_MXC
select SYS_SDRAM_BUS_WIDTH_32
+ select TX6_EMMC
config TARGET_TX6U_8011
bool "TX6U-8011"
select SOC_MX6DL
+ select SYS_I2C
+ select SYS_I2C_MXC
select SYS_SDRAM_BUS_WIDTH_32
config TARGET_TX6U_8012
bool "TX6U-8012"
select SOC_MX6DL
+ select SYS_I2C
+ select SYS_I2C_MXC
config TARGET_TX6U_8033
bool "TX6U-8033"
select SOC_MX6DL
+ select SYS_I2C
+ select SYS_I2C_MXC
select TX6_EMMC
config TARGET_TX6U_80X0
bool "TX6U-8010 and TX6U-8030"
select SOC_MX6DL
+ select SYS_I2C
+ select SYS_I2C_MXC
config TARGET_TX6U_8111
bool "TX6U-8111"
select SOC_MX6DL
- select SYS_SDRAM_BUS_WIDTH_32
+ select SYS_I2C
+ select SYS_I2C_MXC
select SYS_LVDS_IF
+ select SYS_SDRAM_BUS_WIDTH_32
config TARGET_TX6U_81X0
bool "TX6U-8110 and TX6U-8130"
select SOC_MX6DL
+ select SYS_I2C
+ select SYS_I2C_MXC
select SYS_LVDS_IF
+config TARGET_TX6UL_0010
+ bool "TX6U-0010"
+ select TX6UL
+
+config TARGET_TX6UL_0011
+ bool "TX6U-0011"
+ select TX6UL
+ select TX6_EMMC
+
endchoice
choice
LDSCRIPT := $(BOARDDIR)/u-boot.lds
-obj-y += lowlevel_init.o pmic.o tx6qdl.o
-obj-$(CONFIG_LTC3676) += ltc3676.o
+obj-y += pmic.o
+ifeq ($(CONFIG_SOC_MX6UL),y)
+ obj-y += tx6ul_ll_init.o tx6ul.o
+else
+ obj-y += lowlevel_init.o tx6qdl.o
+ obj-$(CONFIG_LTC3676) += ltc3676.o
+endif
obj-$(CONFIG_RN5T567) += rn5t567.o
obj-$(CONFIG_RN5T618) += rn5t618.o
PLATFORM_CPPFLAGS += -Werror
ifneq ($(CONFIG_SECURE_BOOT),)
+ # promote config variable to linker script
PLATFORM_CPPFLAGS += -DCONFIG_SECURE_BOOT
endif
-#PLATFORM_CPPFLAGS += -DDEBUG
ifeq ($(CONFIG_TX6_NAND),y)
-# calculate U_BOOT_IMG_SIZE to be at least 3 eraseblocks larger than the maximum expected image size
CONFIG_SYS_NAND_BLOCK_SIZE := 131072
ifeq ($(CONFIG_SYS_NAND_BLOCKS),)
CONFIG_SYS_NAND_BLOCKS := 1024
endif
ifneq ($(CONFIG_SYS_NAND_BLOCK_SIZE),)
+# calculate U_BOOT_IMG_SIZE to be at least 3 eraseblocks larger than the maximum expected image size
CONFIG_U_BOOT_IMG_SIZE := $(shell echo 'e=$(CONFIG_SYS_NAND_BLOCK_SIZE);s=640*1024;s + (e - s % e) % e + 3*e' | bc)
CONFIG_SYS_USERFS_SIZE := $(shell expr \( $(CONFIG_SYS_NAND_BLOCKS) - 12 \) \* $(CONFIG_SYS_NAND_BLOCK_SIZE) - $(CONFIG_U_BOOT_IMG_SIZE) - 38 \* 1048576)
CONFIG_SYS_USERFS_SIZE2 := $(shell expr \( $(CONFIG_SYS_NAND_BLOCKS) - 15 \) \* $(CONFIG_SYS_NAND_BLOCK_SIZE) - $(CONFIG_U_BOOT_IMG_SIZE) - 38 \* 1048576)
#include <asm/io.h>
#include <linux/sizes.h>
-#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
#include <asm/imx-common/regs-gpmi.h>
#include <asm/imx-common/regs-bch.h>
u32 disbb_search;
};
-struct mx6_dbbt_header {
- u32 checksum;
- u32 fingerprint;
- u32 version;
- u32 number_bb;
- u32 number_pages;
- u8 spare[492];
-};
-
-struct mx6_dbbt {
- u32 nand_number;
- u32 number_bb;
- u32 bb_num[2040 / 4];
-};
-
-struct mx6_ivt {
- u32 magic;
- u32 app_start_addr;
- u32 rsrvd1;
- void *dcd;
- void *boot_data;
- void *self;
- void *csf;
- u32 rsrvd2;
-};
-
-struct mx6_boot_data {
- void *start;
- u32 length;
- u32 plugin;
-};
-
#define BF_VAL(v, bf) (((v) & bf##_MASK) >> bf##_OFFSET)
+#define BF_SET_VAL(r, v, bf) r = ((r) & ~bf##_MASK) | (((v) << bf##_OFFSET) & bf##_MASK)
static nand_info_t *mtd = &nand_info[0];
static bool doit;
ecc[i] = calculate_parity_13_8(src[i]);
}
+static struct bch_regs bch_save;
+static struct bch_regs *bch_base = (void *)BCH_BASE_ADDRESS;
+
+/*
+ * Reprogram BCH engine for 40bit ECC on chunks of 128 byte
+ * and 32 byte of metadata as required by the i.MX6UL ROM code.
+ */
+static void tx6_init_bch(void)
+{
+ u32 fl0 = readl(&bch_base->hw_bch_flash0layout0);
+ u32 fl1 = readl(&bch_base->hw_bch_flash0layout1);
+
+ bch_save.hw_bch_flash0layout0 = fl0;
+ bch_save.hw_bch_flash0layout1 = fl1;
+
+ BF_SET_VAL(fl0, 32, BCH_FLASHLAYOUT0_META_SIZE);
+ BF_SET_VAL(fl0, 7, BCH_FLASHLAYOUT0_NBLOCKS);
+
+ BF_SET_VAL(fl0, 0x14, BCH_FLASHLAYOUT0_ECC0);
+ BF_SET_VAL(fl0, 128 / 4, BCH_FLASHLAYOUT0_DATA0_SIZE);
+
+ BF_SET_VAL(fl1, 0x14, BCH_FLASHLAYOUT1_ECCN);
+ BF_SET_VAL(fl1, 128 / 4, BCH_FLASHLAYOUT1_DATAN_SIZE);
+
+ writel(fl0, &bch_base->hw_bch_flash0layout0);
+ writel(fl1, &bch_base->hw_bch_flash0layout1);
+}
+
+static void tx6_restore_bch(void)
+{
+ writel(bch_save.hw_bch_flash0layout0, &bch_base->hw_bch_flash0layout0);
+ writel(bch_save.hw_bch_flash0layout1, &bch_base->hw_bch_flash0layout1);
+}
+
static u32 calc_chksum(void *buf, size_t size)
{
u32 chksum = 0;
return ~chksum;
}
-/*
- Physical organisation of data in NAND flash:
- metadata
- payload chunk 0 (may be empty)
- ecc for metadata + payload chunk 0
- payload chunk 1
- ecc for payload chunk 1
-...
- payload chunk n
- ecc for payload chunk n
- */
-
-static inline int calc_bb_offset(nand_info_t *mtd, struct mx6_fcb *fcb)
-{
- int bb_mark_offset;
- int chunk_data_size = fcb->ecc_blockn_size * 8;
- int chunk_ecc_size = (fcb->ecc_blockn_type << 1) * 13;
- int chunk_total_size = chunk_data_size + chunk_ecc_size;
- int bb_mark_chunk, bb_mark_chunk_offs;
-
- bb_mark_offset = (mtd->writesize - fcb->metadata_size) * 8;
- if (fcb->ecc_block0_size == 0)
- bb_mark_offset -= (fcb->ecc_block0_type << 1) * 13;
-
- bb_mark_chunk = bb_mark_offset / chunk_total_size;
- bb_mark_chunk_offs = bb_mark_offset - (bb_mark_chunk * chunk_total_size);
- if (bb_mark_chunk_offs > chunk_data_size) {
- printf("Unsupported ECC layout; BB mark resides in ECC data: %u\n",
- bb_mark_chunk_offs);
- return -EINVAL;
- }
- bb_mark_offset -= bb_mark_chunk * chunk_ecc_size;
- return bb_mark_offset;
-}
-
/*
* return number of blocks to skip for a contiguous partition
* of given # blocks
int fw2_start_block, int fw_num_blocks)
{
struct gpmi_regs *gpmi_base = (void *)GPMI_BASE_ADDRESS;
- struct bch_regs *bch_base = (void *)BCH_BASE_ADDRESS;
u32 fl0, fl1;
u32 t0;
- int metadata_size;
- int bb_mark_bit_offs;
struct mx6_fcb *fcb;
int fcb_offs;
fl1 = readl(&bch_base->hw_bch_flash0layout1);
t0 = readl(&gpmi_base->hw_gpmi_timing0);
- metadata_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_META_SIZE);
+ if (!is_cpu_type(MXC_CPU_MX6UL)) {
+ int metadata_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_META_SIZE);
+
+ fcb = buf + ALIGN(metadata_size, 4);
+ fcb_offs = (void *)fcb - buf;
- fcb = buf + ALIGN(metadata_size, 4);
- fcb_offs = (void *)fcb - buf;
+ memset(buf, 0xff, fcb_offs);
+ } else {
+ fcb = buf;
+ fcb_offs = 0;
+ }
- memset(buf, 0xff, fcb_offs);
- memset(fcb, 0x00, sizeof(*fcb));
- memset(fcb + 1, 0xff, mtd->erasesize - fcb_offs - sizeof(*fcb));
+ memset(fcb, 0, mtd->erasesize - fcb_offs);
strncpy((char *)&fcb->fingerprint, "FCB ", 4);
fcb->version = cpu_to_be32(1);
fcb->dbbt_search_area = 0;
- bb_mark_bit_offs = calc_bb_offset(mtd, fcb);
- if (bb_mark_bit_offs < 0)
- return ERR_PTR(bb_mark_bit_offs);
- fcb->bb_mark_byte = bb_mark_bit_offs / 8;
- fcb->bb_mark_startbit = bb_mark_bit_offs % 8;
- fcb->bb_mark_phys_offset = mtd->writesize;
-
- pr_fcb_val(fcb, bb_mark_byte);
- pr_fcb_val(fcb, bb_mark_startbit);
- pr_fcb_val(fcb, bb_mark_phys_offset);
-
fcb->checksum = calc_chksum(&fcb->fingerprint, 512 - 4);
return fcb;
}
printf("Writing FCB to block %d @ %08llx\n", block,
(u64)block * mtd->erasesize);
if (doit) {
- chip->select_chip(mtd, 0);
- ret = chip->write_page(mtd, chip, 0, mtd->writesize,
- buf, 1, page, 0, 1);
+ if (is_cpu_type(MXC_CPU_MX6UL)) {
+ size_t len = mtd->writesize;
+
+ tx6_init_bch();
+ printf("writing block %u from buffer %p\n", block, buf);
+ ret = nand_write(mtd, block * mtd->erasesize, &len, buf);
+ tx6_restore_bch();
+ } else {
+ chip->select_chip(mtd, 0);
+ ret = chip->write_page(mtd, chip, 0, mtd->writesize,
+ buf, 1, page, 0, 1);
+ }
if (ret) {
printf("Failed to write FCB to block %u: %d\n", block, ret);
}
ret = PTR_ERR(fcb);
goto out;
}
- encode_hamming_13_8(fcb, (void *)fcb + 512, 512);
+ if (!is_cpu_type(MXC_CPU_MX6UL))
+ encode_hamming_13_8(fcb, (void *)fcb + 512, 512);
ret = write_fcb(buf, fcb_start_block);
if (ret) {
(((l) >> 8) & 0x0000FF00) | \
(((l) >> 24) & 0x000000FF))
-#define CHECK_DCD_ADDR(a) ( \
+#define CHECK_DCD_ADDR(a) ( \
((a) >= 0x020E0000 && (a) <= 0x020E3FFF) /* IOMUXC */ || \
- ((a) >= 0x020C4000 && (a) <= 0x020C7FFF) /* CCM */ || \
+ ((a) >= 0x020C4000 && (a) <= 0x020C7FFF) /* CCM */ || \
((a) >= 0x020C8000 && (a) <= 0x020C8FFF) /* ANALOG */ || \
- ((a) >= 0x021B0000 && (a) <= 0x021B7FFF) /* MMDC */ || \
- ((a) >= 0x00907000 && (a) <= 0x00937FF0) /* OCRAM */ || \
+ ((a) >= 0x021B0000 && (a) <= 0x021B7FFF) /* MMDC */ || \
+ ((a) >= 0x00907000 && (a) <= 0x00937FF0) /* OCRAM */ || \
((a) >= 0x08000000 && (a) <= 0x0FFEFFFF) /* EIM (CS0) */ || \
+ ((a) >= 0x021B8000 && (a) <= 0x021BBFFF) /* EIM registers */ || \
((a) >= 0x10000000 && (a) <= 0xFFFFFFFF) /* SDRAM */)
.macro mxc_dcd_item addr, val
.endm
#define MXC_DCD_ITEM(addr, val) mxc_dcd_item (addr), (val)
-#if PHYS_SDRAM_1_WIDTH == 16
-#define MXC_DCD_ITEM_16(addr, val) mxc_dcd_item (addr), (val)
+#if CONFIG_SYS_SDRAM_BUS_WIDTH == 16
+#define MXC_DCD_ITEM_16(addr, val) mxc_dcd_item (addr), (val)
#define MXC_DCD_CMD_CHK_16(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
#else
#define MXC_DCD_ITEM_16(addr, val)
#define MXC_DCD_CMD_CHK_16(type, flags, addr, mask)
#endif
-#if PHYS_SDRAM_1_WIDTH > 16
-#define MXC_DCD_ITEM_32(addr, val) mxc_dcd_item (addr), (val)
+#if CONFIG_SYS_SDRAM_BUS_WIDTH > 16
+#define MXC_DCD_ITEM_32(addr, val) mxc_dcd_item (addr), (val)
#define MXC_DCD_CMD_CHK_32(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
#else
#define MXC_DCD_ITEM_32(addr, val)
#define MXC_DCD_CMD_CHK_32(type, flags, addr, mask)
#endif
-#if PHYS_SDRAM_1_WIDTH == 64
-#define MXC_DCD_ITEM_64(addr, val) mxc_dcd_item (addr), (val)
+#if CONFIG_SYS_SDRAM_BUS_WIDTH == 64
+#define MXC_DCD_ITEM_64(addr, val) mxc_dcd_item (addr), (val)
#define MXC_DCD_CMD_CHK_64(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
#else
#define MXC_DCD_ITEM_64(addr, val)
#define MDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \
((COL_ADDR_BITS - 9) << 20) | \
(BURST_LEN << 19) | \
- ((PHYS_SDRAM_1_WIDTH / 32) << 16) | \
+ ((CONFIG_SYS_SDRAM_BUS_WIDTH / 32) << 16) | \
((-1) << (32 - BANK_ADDR_BITS)))
#define MDMISC_WALAT(n) (((n) & 3) << 16)
#define DCD_VERSION 0x40
#define DDR_SEL_VAL 3 /* DDR3 */
-#if PHYS_SDRAM_1_WIDTH == 16
+#if CONFIG_SYS_SDRAM_BUS_WIDTH == 16
#define DSE1_VAL 6 /* Drive Strength for DATA lines */
#define DSE2_VAL 6 /* Drive Strength for ADDR/CMD lines */
#else
#define MMDC1_MPWRDLST 0x021b0854
#define MMDC1_MPRDDLHWCTL 0x021b0860
#define MMDC1_MPWRDLHWCTL 0x021b0864
+#define MMDC1_MPDGHWST0 0x021b087c
+#define MMDC1_MPDGHWST1 0x021b0880
#define MMDC1_MPPDCMPR2 0x021b0890
+#define MMDC1_MPDGHWST2 0x021b0884
+#define MMDC1_MPDGHWST3 0x021b0888
#define MMDC1_MPSWDRDR0 0x021b0898
#define MMDC1_MPSWDRDR1 0x021b089c
#define MMDC1_MPSWDRDR2 0x021b08a0
#define MMDC1_MPSWDRDR7 0x021b08b4
#define MMDC1_MPMUR0 0x021b08b8
-#if PHYS_SDRAM_1_WIDTH == 64
+#if CONFIG_SYS_SDRAM_BUS_WIDTH == 64
#define MMDC2_MPWLGCR 0x021b4808
#define MMDC2_MPWLDECTRL0 0x021b480c
#define MMDC2_MPWLDECTRL1 0x021b4810
#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21 0x020e0898
#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28 0x020e089c
#define TX6_I2C1_SEL_INP_VAL 0
-#endif
-
-#if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
+#elif defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
#define IOMUXC_GPR1 0x020e0004
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20 0x020e0154
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 0x020e0158
MXC_DCD_ITEM(ANATOP_BASE_ADDR + ANATOP_PLL_ENET, 0x00002001) /* ENET PLL */
/* enable all relevant clocks... */
- MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR0, 0xf0c03f3f) /* default: 0xf0c03f0f APBH-DMA */
- MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, 0xf0fc0c00) /* default: 0xf0fc0000 */
- MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, 0xfc3ff0cc) /* default: 0xfc3ff00c I2C1 */
- MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR3, 0x3ff00000) /* default: 0x3ff00000 */
- MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, 0xff00ff00) /* default: 0x0000ff00 GPMI BCH */
- MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR5, 0xff033f0f) /* default: 0xf0033f0f UART1 */
- MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, 0xffff03ff) /* default: 0xffff0003 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) */
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET)
+#define CCGR(m) (3 << ((m) * 2))
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR0, CCGR(2)) /* 0xf0c03f3f default: 0xf0c03f0f APBH-DMA */
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, CCGR(5)) /* 0xf0fc0c00 default: 0xf0fc0000 ENET */
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR(3)) /* 0xfc3fc0cc default: 0xfc3fc00c I2C1 */
+// MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR3, CCGR()) /* 0x3ff00000 default: 0x3ff0000f */
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, CCGR(15) | CCGR(14) | CCGR(13) | CCGR(12)) /* 0xff00ff00 default: 0x0000ff00 GPMI BCH */
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR5, CCGR(13) | CCGR(12)) /* 0xff033f3f default: 0xf0033f3f UART1 */
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, CCGR(4) | CCGR(3) | CCGR(2) | CCGR(1)) /* 0xffff03ff default: 0xffff0000 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) USDHC1 USDHC1 */
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
MXC_DCD_ITEM(0x020c80a0, 0x80082029) /* set video PLL to 984MHz */
MXC_DCD_ITEM(0x020c80b0, 0x00065b9a)
MXC_DCD_ITEM(0x020c80c0, 0x000f4240)
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6, ODT_MASK)
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7, ODT_MASK)
#endif
-#if PHYS_SDRAM_1_WIDTH > 16
+#if CONFIG_SYS_SDRAM_BUS_WIDTH > 16
#define DO_DDR_CALIB
#endif
/* SDRAM initialization */
MXC_DCD_ITEM_32(MMDC1_MPWLDECTRL1, (WL_DLY_DQS3 << 16) | (WL_DLY_DQS2 << 0))
MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL0, (WL_DLY_DQS5 << 16) | (WL_DLY_DQS4 << 0))
MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL1, (WL_DLY_DQS7 << 16) | (WL_DLY_DQS6 << 0))
-
- MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x43240334)
- MXC_DCD_ITEM(MMDC1_MPDGCTRL1, 0x0324031a)
- MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x43340344)
- MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x03280276)
-
+#if defined(CONFIG_SOC_MX6Q)
+ MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x43430349)
+ MXC_DCD_ITEM_32(MMDC1_MPDGCTRL1, 0x03330334)
+ MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x434b0351)
+ MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x033d030e)
+#elif defined(CONFIG_SOC_MX6DL)
+ MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x423a0236)
+ MXC_DCD_ITEM_32(MMDC1_MPDGCTRL1, 0x02210227)
+ MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x42240226)
+ MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x02120223)
+#elif defined(CONFIG_SOC_MX6S)
+ MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x42490244)
+ MXC_DCD_ITEM_32(MMDC1_MPDGCTRL1, 0x022f0238)
+#else
+#error No DGCTRL settings for selected SoC
+#endif
MXC_DCD_ITEM(MMDC1_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
MXC_DCD_ITEM_64(MMDC2_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
#if BANK_ADDR_BITS > 1
MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */
#endif
-
- MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL)
/* DRAM_SDQS[0..7] pad config */
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK)
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK)
MXC_DCD_ITEM(MMDC1_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */
MXC_DCD_CMD_CHK_16(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x00000013)
MXC_DCD_CMD_CHK_32(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x0000001f)
-#if PHYS_SDRAM_1_WIDTH == 64
+#if CONFIG_SYS_SDRAM_BUS_WIDTH == 64
MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
/*
* Copyright (C) 2012-2015 Lothar Waßmann <LW@KARO-electronics.de>
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
+ * SPDX-License-Identifier: GPL-2.0+
*
*/
#include <common.h>
#define MUX_CFG_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
-enum {
- MX6_PAD_DECL(GARBAGE, 0, 0, 0, 0, 0, 0)
-};
-
char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
#ifdef CONFIG_SECURE_BOOT
char __csf_data[0] __attribute__((section(".__csf_data")));
/* placed in section '.data' to prevent overwriting relocation info
* overlayed with bss
*/
-static u32 wrsr __attribute__((section(".data")));
+static u32 wrsr __data;
#define WRSR_POR (1 << 4)
#define WRSR_TOUT (1 << 1)
static const char __data *tx6_mod_suffix;
+#ifdef CONFIG_IMX6_THERMAL
+#include <thermal.h>
+#include <imx_thermal.h>
+#include <fuse.h>
+
+static void print_temperature(void)
+{
+ struct udevice *thermal_dev;
+ int cpu_tmp, minc, maxc, ret;
+ char const *grade_str;
+ static u32 __data thermal_calib;
+
+ puts("Temperature: ");
+ switch (get_cpu_temp_grade(&minc, &maxc)) {
+ case TEMP_AUTOMOTIVE:
+ grade_str = "Automotive";
+ break;
+ case TEMP_INDUSTRIAL:
+ grade_str = "Industrial";
+ break;
+ case TEMP_EXTCOMMERCIAL:
+ grade_str = "Extended Commercial";
+ break;
+ default:
+ grade_str = "Commercial";
+ }
+ printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
+ ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
+ if (ret == 0) {
+ ret = thermal_get_temp(thermal_dev, &cpu_tmp);
+
+ if (ret == 0)
+ printf(" at %dC", cpu_tmp);
+ else
+ puts(" - failed to read sensor data");
+ } else {
+ puts(" - no sensor device found");
+ }
+
+ if (fuse_read(1, 6, &thermal_calib) == 0) {
+ printf(" - calibration data 0x%08x\n", thermal_calib);
+ } else {
+ puts(" - Failed to read thermal calib fuse\n");
+ }
+}
+#else
+static inline void print_temperature(void)
+{
+}
+#endif
+
int checkboard(void)
{
u32 cpurev = get_cpu_rev();
break;
}
- printf("CPU: Freescale i.MX6%s rev%d.%d at %d MHz\n",
+ printf("CPU: Freescale i.MX6%s rev%d.%d at %d MHz\n",
cpu_str,
(cpurev & 0x000F0) >> 4,
(cpurev & 0x0000F) >> 0,
mxc_get_clock(MXC_ARM_CLK) / 1000000);
+ print_temperature();
print_reset_cause();
#ifdef CONFIG_MX6_TEMPERATURE_HOT
check_cpu_temperature(1);
return 0;
}
+/* serial port not initialized at this point */
int board_early_init_f(void)
{
- debug("%s@%d: \n", __func__, __LINE__);
-
return 0;
}
#endif
#endif /* CONFIG_TX6_NAND */
-#define TX6_DDR_SZ (ffs(PHYS_SDRAM_1_WIDTH / 16) - 1)
+#define TX6_DDR_SZ (ffs(CONFIG_SYS_SDRAM_BUS_WIDTH / 16) - 1)
static char tx6_mem_table[] = {
'4', /* 256MiB SDRAM 16bit; 128MiB NAND */
return -EINVAL;
}
-static inline int __checkboard(void)
-{
- u32 cpurev = get_cpu_rev();
- int cpu_variant = (cpurev >> 12) & 0xff;
- int pmic_id;
-
- debug("%s@%d: \n", __func__, __LINE__);
-
- pmic_id = tx6_pmic_probe();
- if (pmic_id >= 0)
- pmic_addr = tx6_mod_revs[pmic_id].addr;
-
- printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
- tx6_mod_suffix,
- cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
- is_lvds(), tx6_get_mod_rev(pmic_id),
- tx6_mem_suffix());
-
- get_hab_status();
-
- debug("%s@%d: done\n", __func__, __LINE__);
- return 0;
-}
-
int board_init(void)
{
int ret;
{
u8 mac[ETH_ALEN];
- imx_get_mac_from_fuse(-1, mac);
+ imx_get_mac_from_fuse(0, mac);
if (!is_valid_ethaddr(mac)) {
printf("No valid MAC address programmed\n");
return;
karo_fdt_enable_node(blob, "stk5led", 0);
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
- fdt_fixup_ethernet(blob);
karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
ARRAY_SIZE(tx6_touchpanels));
--- /dev/null
+/*
+ * Copyright (C) 2015 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+#include <common.h>
+#include <errno.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <lcd.h>
+#include <netdev.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <video_fb.h>
+#include <ipu.h>
+#include <mxcfb.h>
+#include <i2c.h>
+#include <linux/fb.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/hab.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/sys_proto.h>
+
+#include "../common/karo.h"
+#include "pmic.h"
+
+#define __data __attribute__((section(".data")))
+
+#define TX6UL_FEC_RST_GPIO IMX_GPIO_NR(5, 6)
+#define TX6UL_FEC_PWR_GPIO IMX_GPIO_NR(5, 7)
+#define TX6UL_FEC_INT_GPIO IMX_GPIO_NR(5, 5)
+#define TX6UL_LED_GPIO IMX_GPIO_NR(5, 9)
+
+#define TX6UL_LCD_PWR_GPIO IMX_GPIO_NR(5, 4)
+#define TX6UL_LCD_RST_GPIO IMX_GPIO_NR(3, 4)
+#define TX6UL_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(4, 16)
+
+#define TX6UL_I2C1_SCL_GPIO IMX_GPIO_NR(5, 0)
+#define TX6UL_I2C1_SDA_GPIO IMX_GPIO_NR(5, 1)
+
+#define TX6UL_SD1_CD_GPIO IMX_GPIO_NR(4, 14)
+
+#ifdef CONFIG_MX6_TEMPERATURE_MIN
+#define TEMPERATURE_MIN CONFIG_MX6_TEMPERATURE_MIN
+#else
+#define TEMPERATURE_MIN (-40)
+#endif
+#ifdef CONFIG_MX6_TEMPERATURE_HOT
+#define TEMPERATURE_HOT CONFIG_MX6_TEMPERATURE_HOT
+#else
+#define TEMPERATURE_HOT 80
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MUX_CFG_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
+
+char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
+#ifdef CONFIG_SECURE_BOOT
+char __csf_data[0] __attribute__((section(".__csf_data")));
+#endif
+
+static const iomux_v3_cfg_t const tx6ul_pads[] = {
+ /* UART pads */
+#if CONFIG_MXC_UART_BASE == UART1_BASE
+ MX6_PAD_UART1_TX_DATA__UART1_DCE_TX,
+ MX6_PAD_UART1_RX_DATA__UART1_DCE_RX,
+ MX6_PAD_UART1_RTS_B__UART1_DCE_RTS,
+ MX6_PAD_UART1_CTS_B__UART1_DCE_CTS,
+#endif
+#if CONFIG_MXC_UART_BASE == UART2_BASE
+ MX6_PAD_UART2_TX_DATA__UART2_DCE_TX,
+ MX6_PAD_UART2_RX_DATA__UART2_DCE_RX,
+ MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS,
+ MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS,
+#endif
+#if CONFIG_MXC_UART_BASE == UART5_BASE
+ MX6_PAD_GPIO1_IO04__UART5_DCE_TX,
+ MX6_PAD_GPIO1_IO05__UART5_DCE_RX,
+ MX6_PAD_GPIO1_IO08__UART5_DCE_RTS,
+ MX6_PAD_GPIO1_IO09__UART5_DCE_CTS,
+#endif
+ /* internal I2C */
+ MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION, /* I2C SCL */
+ MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION, /* I2C SDA */
+
+ /* FEC PHY GPIO functions */
+ MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_CFG_SION, /* PHY POWER */
+ MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 | MUX_CFG_SION, /* PHY RESET */
+ MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
+ PAD_CTL_DSE_40ohm), /* PHY INT */
+};
+
+#define TX6_ENET_PAD_CTRL (PAD_CTL_SPEED_HIGH | \
+ PAD_CTL_DSE_48ohm | \
+ PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SRE_FAST)
+#define TX6_GPIO_OUT_PAD_CTRL (PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_60ohm | \
+ PAD_CTL_SRE_SLOW)
+#define TX6_GPIO_IN_PAD_CTRL (PAD_CTL_SPEED_LOW | \
+ PAD_CTL_PUS_47K_UP)
+
+static const iomux_v3_cfg_t const tx6ul_enet1_pads[] = {
+ /* FEC functions */
+ MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(PAD_CTL_DSE_48ohm |
+ PAD_CTL_SPEED_MED),
+ MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |
+ PAD_CTL_DSE_48ohm |
+ PAD_CTL_SPEED_MED),
+ MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_CFG_SION |
+ MUX_PAD_CTRL(PAD_CTL_SPEED_MED |
+ PAD_CTL_DSE_40ohm |
+ PAD_CTL_SRE_FAST),
+ MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
+ MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
+ MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
+ MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
+ MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
+ MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
+ MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
+
+ MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_CFG_SION |
+ MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH |
+ PAD_CTL_DSE_48ohm |
+ PAD_CTL_SRE_FAST),
+ MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
+ MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
+ MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
+ MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
+ MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
+ MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
+ MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
+};
+
+#define TX6_I2C_PAD_CTRL (PAD_CTL_PUS_22K_UP | \
+ PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_34ohm | \
+ PAD_CTL_SRE_FAST)
+
+static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
+ /* internal I2C */
+ MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
+ MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
+};
+
+static const struct gpio const tx6ul_gpios[] = {
+ /* These two entries are used to forcefully reinitialize the I2C bus */
+ { TX6UL_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
+ { TX6UL_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
+
+ { TX6UL_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
+ { TX6UL_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
+ { TX6UL_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
+};
+
+static int pmic_addr __maybe_unused __data = 0x3c;
+
+#define GPIO_DR 0
+#define GPIO_DIR 4
+#define GPIO_PSR 8
+
+static void tx6_i2c_recover(void)
+{
+ int i;
+ int bad = 0;
+#define SCL_BIT (1 << (TX6UL_I2C1_SCL_GPIO % 32))
+#define SDA_BIT (1 << (TX6UL_I2C1_SDA_GPIO % 32))
+#define I2C_GPIO_BASE (GPIO1_BASE_ADDR + TX6UL_I2C1_SCL_GPIO / 32 * 0x4000)
+
+ if ((readl(I2C_GPIO_BASE + GPIO_PSR) &
+ (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT))
+ return;
+
+ debug("Clearing I2C bus\n");
+ if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SCL_BIT)) {
+ printf("I2C SCL stuck LOW\n");
+ bad++;
+
+ writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT,
+ I2C_GPIO_BASE + GPIO_DR);
+ writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT,
+ I2C_GPIO_BASE + GPIO_DIR);
+ }
+ if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)) {
+ printf("I2C SDA stuck LOW\n");
+ bad++;
+
+ writel(readl(I2C_GPIO_BASE + GPIO_DIR) & ~SDA_BIT,
+ I2C_GPIO_BASE + GPIO_DIR);
+ writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT,
+ I2C_GPIO_BASE + GPIO_DR);
+ writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT,
+ I2C_GPIO_BASE + GPIO_DIR);
+
+ imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
+ ARRAY_SIZE(tx6_i2c_gpio_pads));
+ udelay(10);
+
+ for (i = 0; i < 18; i++) {
+ u32 reg = readl(I2C_GPIO_BASE + GPIO_DR) ^ SCL_BIT;
+
+ debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
+ writel(reg, I2C_GPIO_BASE + GPIO_DR);
+ udelay(10);
+ if (reg & SCL_BIT &&
+ readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)
+ break;
+ }
+ }
+ if (bad) {
+ u32 reg = readl(I2C_GPIO_BASE + GPIO_PSR);
+
+ if ((reg & (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) {
+ printf("I2C bus recovery succeeded\n");
+ } else {
+ printf("I2C bus recovery FAILED: %08x:%08x\n", reg,
+ SCL_BIT | SDA_BIT);
+ }
+ }
+ debug("Setting up I2C Pads\n");
+}
+
+/* placed in section '.data' to prevent overwriting relocation info
+ * overlayed with bss
+ */
+static u32 wrsr __data;
+
+#define WRSR_POR (1 << 4)
+#define WRSR_TOUT (1 << 1)
+#define WRSR_SFTW (1 << 0)
+
+static void print_reset_cause(void)
+{
+ struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+ void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
+ u32 srsr;
+ char *dlm = "";
+
+ printf("Reset cause: ");
+
+ srsr = readl(&src_regs->srsr);
+ wrsr = readw(wdt_base + 4);
+
+ if (wrsr & WRSR_POR) {
+ printf("%sPOR", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x00004) {
+ printf("%sCSU", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x00008) {
+ printf("%sIPP USER", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x00010) {
+ if (wrsr & WRSR_SFTW) {
+ printf("%sSOFT", dlm);
+ dlm = " | ";
+ }
+ if (wrsr & WRSR_TOUT) {
+ printf("%sWDOG", dlm);
+ dlm = " | ";
+ }
+ }
+ if (srsr & 0x00020) {
+ printf("%sJTAG HIGH-Z", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x00040) {
+ printf("%sJTAG SW", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x10000) {
+ printf("%sWARM BOOT", dlm);
+ dlm = " | ";
+ }
+ if (dlm[0] == '\0')
+ printf("unknown");
+
+ printf("\n");
+}
+
+#ifdef CONFIG_IMX6_THERMAL
+#include <thermal.h>
+#include <imx_thermal.h>
+#include <fuse.h>
+
+static void print_temperature(void)
+{
+ struct udevice *thermal_dev;
+ int cpu_tmp, minc, maxc, ret;
+ char const *grade_str;
+ static u32 __data thermal_calib;
+
+ puts("Temperature: ");
+ switch (get_cpu_temp_grade(&minc, &maxc)) {
+ case TEMP_AUTOMOTIVE:
+ grade_str = "Automotive";
+ break;
+ case TEMP_INDUSTRIAL:
+ grade_str = "Industrial";
+ break;
+ case TEMP_EXTCOMMERCIAL:
+ grade_str = "Extended Commercial";
+ break;
+ default:
+ grade_str = "Commercial";
+ }
+ printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
+ ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
+ if (ret == 0) {
+ ret = thermal_get_temp(thermal_dev, &cpu_tmp);
+
+ if (ret == 0)
+ printf(" at %dC", cpu_tmp);
+ else
+ puts(" - failed to read sensor data");
+ } else {
+ puts(" - no sensor device found");
+ }
+
+ if (fuse_read(1, 6, &thermal_calib) == 0) {
+ printf(" - calibration data 0x%08x\n", thermal_calib);
+ } else {
+ puts(" - Failed to read thermal calib fuse\n");
+ }
+}
+#else
+static inline void print_temperature(void)
+{
+}
+#endif
+
+int checkboard(void)
+{
+ u32 cpurev = get_cpu_rev();
+ char *cpu_str = "?";
+
+ switch ((cpurev >> 12) & 0xff) {
+ case MXC_CPU_MX6SL:
+ cpu_str = "SL";
+ break;
+ case MXC_CPU_MX6DL:
+ cpu_str = "DL";
+ break;
+ case MXC_CPU_MX6SOLO:
+ cpu_str = "SOLO";
+ break;
+ case MXC_CPU_MX6Q:
+ cpu_str = "Q";
+ break;
+ case MXC_CPU_MX6UL:
+ cpu_str = "UL";
+ break;
+ }
+
+ printf("CPU: Freescale i.MX6%s rev%d.%d at %d MHz\n",
+ cpu_str,
+ (cpurev & 0x000F0) >> 4,
+ (cpurev & 0x0000F) >> 0,
+ mxc_get_clock(MXC_ARM_CLK) / 1000000);
+
+ print_temperature();
+ print_reset_cause();
+#ifdef CONFIG_MX6_TEMPERATURE_HOT
+ check_cpu_temperature(1);
+#endif
+ tx6_i2c_recover();
+ return 0;
+}
+
+/* serial port not initialized at this point */
+int board_early_init_f(void)
+{
+ return 0;
+}
+
+#ifndef CONFIG_MX6_TEMPERATURE_HOT
+static bool tx6_temp_check_enabled = true;
+#else
+#define tx6_temp_check_enabled 0
+#endif
+
+static inline u8 tx6ul_mem_suffix(void)
+{
+#ifdef CONFIG_TX6_NAND
+ return '0';
+#else
+ return '1';
+#endif
+}
+
+int board_init(void)
+{
+ int ret;
+
+ debug("%s@%d: \n", __func__, __LINE__);
+
+ printf("Board: Ka-Ro TXUL-001%c\n",
+ tx6ul_mem_suffix());
+
+ get_hab_status();
+
+ ret = gpio_request_array(tx6ul_gpios, ARRAY_SIZE(tx6ul_gpios));
+ if (ret < 0) {
+ printf("Failed to request tx6ul_gpios: %d\n", ret);
+ }
+ imx_iomux_v3_setup_multiple_pads(tx6ul_pads, ARRAY_SIZE(tx6ul_pads));
+
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
+ gd->bd->bi_arch_number = -1;
+
+ if (ctrlc() || (wrsr & WRSR_TOUT)) {
+ if (wrsr & WRSR_TOUT)
+ printf("WDOG RESET detected; Skipping PMIC setup\n");
+ else
+ printf("<CTRL-C> detected; safeboot enabled\n");
+#ifndef CONFIG_MX6_TEMPERATURE_HOT
+ tx6_temp_check_enabled = false;
+#endif
+ return 0;
+ }
+#if 0
+ ret = tx6_pmic_init(pmic_addr);
+ if (ret) {
+ printf("Failed to setup PMIC voltages: %d\n", ret);
+ hang();
+ }
+#endif
+ return 0;
+}
+
+int dram_init(void)
+{
+ debug("%s@%d: \n", __func__, __LINE__);
+
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ debug("%s@%d: \n", __func__, __LINE__);
+
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
+#if CONFIG_NR_DRAM_BANKS > 1
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
+ PHYS_SDRAM_2_SIZE);
+#endif
+}
+
+#ifdef CONFIG_FSL_ESDHC
+#define TX6_SD_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST)
+
+static const iomux_v3_cfg_t mmc0_pads[] = {
+ MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
+ MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
+ MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
+ MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
+ MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
+ MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
+ /* SD1 CD */
+ MX6_PAD_NAND_CE1_B__GPIO4_IO14 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
+};
+
+#ifdef CONFIG_TX6_EMMC
+static const iomux_v3_cfg_t mmc1_pads[] = {
+ MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
+ MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
+ MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
+ MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
+ MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
+ MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
+ /* eMMC RESET */
+ MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
+ PAD_CTL_DSE_40ohm),
+};
+#endif
+
+static struct tx6_esdhc_cfg {
+ const iomux_v3_cfg_t *pads;
+ int num_pads;
+ enum mxc_clock clkid;
+ struct fsl_esdhc_cfg cfg;
+ int cd_gpio;
+} tx6ul_esdhc_cfg[] = {
+#ifdef CONFIG_TX6_EMMC
+ {
+ .pads = mmc1_pads,
+ .num_pads = ARRAY_SIZE(mmc1_pads),
+ .clkid = MXC_ESDHC2_CLK,
+ .cfg = {
+ .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
+ .max_bus_width = 4,
+ },
+ .cd_gpio = -EINVAL,
+ },
+#endif
+ {
+ .pads = mmc0_pads,
+ .num_pads = ARRAY_SIZE(mmc0_pads),
+ .clkid = MXC_ESDHC_CLK,
+ .cfg = {
+ .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
+ .max_bus_width = 4,
+ },
+ .cd_gpio = TX6UL_SD1_CD_GPIO,
+ },
+};
+
+static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
+{
+ return container_of(cfg, struct tx6_esdhc_cfg, cfg);
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
+
+ if (cfg->cd_gpio < 0)
+ return 1;
+
+ debug("SD card %d is %spresent (GPIO %d)\n",
+ cfg - tx6ul_esdhc_cfg,
+ gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
+ cfg->cd_gpio);
+ return !gpio_get_value(cfg->cd_gpio);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int i;
+
+ debug("%s@%d: \n", __func__, __LINE__);
+
+ for (i = 0; i < ARRAY_SIZE(tx6ul_esdhc_cfg); i++) {
+ struct mmc *mmc;
+ struct tx6_esdhc_cfg *cfg = &tx6ul_esdhc_cfg[i];
+ int ret;
+
+ cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
+ imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
+
+ if (cfg->cd_gpio >= 0) {
+ ret = gpio_request_one(cfg->cd_gpio,
+ GPIOFLAG_INPUT, "MMC CD");
+ if (ret) {
+ printf("Error %d requesting GPIO%d_%d\n",
+ ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
+ continue;
+ }
+ }
+
+ debug("%s: Initializing MMC slot %d\n", __func__, i);
+ fsl_esdhc_initialize(bis, &cfg->cfg);
+
+ mmc = find_mmc_device(i);
+ if (mmc == NULL)
+ continue;
+ if (board_mmc_getcd(mmc))
+ mmc_init(mmc);
+ }
+ return 0;
+}
+#endif /* CONFIG_CMD_MMC */
+
+#ifdef CONFIG_FEC_MXC
+
+#ifndef ETH_ALEN
+#define ETH_ALEN 6
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int ret;
+
+ debug("%s@%d: \n", __func__, __LINE__);
+
+ /* delay at least 21ms for the PHY internal POR signal to deassert */
+ udelay(22000);
+
+ imx_iomux_v3_setup_multiple_pads(tx6ul_enet1_pads,
+ ARRAY_SIZE(tx6ul_enet1_pads));
+
+ /* Deassert RESET to the external phy */
+ gpio_set_value(TX6UL_FEC_RST_GPIO, 1);
+
+ if (getenv("ethaddr")) {
+ ret = fecmxc_initialize_multi(bis, 0, -1, ENET_BASE_ADDR);
+ if (ret) {
+ printf("failed to initialize FEC0: %d\n", ret);
+ return ret;
+ }
+ }
+ if (getenv("eth1addr")) {
+ ret = fecmxc_initialize_multi(bis, 1, -1, ENET2_BASE_ADDR);
+ if (ret) {
+ printf("failed to initialize FEC1: %d\n", ret);
+ return ret;
+ }
+ }
+ return 0;
+}
+
+static void tx6_init_mac(void)
+{
+ u8 mac[ETH_ALEN];
+
+ imx_get_mac_from_fuse(0, mac);
+ if (!is_valid_ethaddr(mac)) {
+ printf("No valid MAC address programmed\n");
+ return;
+ }
+
+ printf("MAC addr from fuse: %pM\n", mac);
+ eth_setenv_enetaddr("ethaddr", mac);
+
+ imx_get_mac_from_fuse(1, mac);
+ eth_setenv_enetaddr("eth1addr", mac);
+}
+#else
+static inline void tx6_init_mac(void)
+{
+}
+#endif /* CONFIG_FEC_MXC */
+
+enum {
+ LED_STATE_INIT = -1,
+ LED_STATE_OFF,
+ LED_STATE_ON,
+};
+
+static inline int calc_blink_rate(void)
+{
+ if (!tx6_temp_check_enabled)
+ return CONFIG_SYS_HZ;
+
+ return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
+ (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
+ (TEMPERATURE_HOT - TEMPERATURE_MIN);
+}
+
+void show_activity(int arg)
+{
+ static int led_state = LED_STATE_INIT;
+ static int blink_rate;
+ static ulong last;
+
+ if (led_state == LED_STATE_INIT) {
+ last = get_timer(0);
+ gpio_set_value(TX6UL_LED_GPIO, 1);
+ led_state = LED_STATE_ON;
+ blink_rate = calc_blink_rate();
+ } else {
+ if (get_timer(last) > blink_rate) {
+ blink_rate = calc_blink_rate();
+ last = get_timer_masked();
+ if (led_state == LED_STATE_ON) {
+ gpio_set_value(TX6UL_LED_GPIO, 0);
+ } else {
+ gpio_set_value(TX6UL_LED_GPIO, 1);
+ }
+ led_state = 1 - led_state;
+ }
+ }
+}
+
+static const iomux_v3_cfg_t stk5_pads[] = {
+ /* SW controlled LED on STK5 baseboard */
+ MX6_PAD_SNVS_TAMPER9__GPIO5_IO09,
+
+ /* I2C bus on DIMM pins 40/41 */
+ MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
+ MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
+
+ /* TSC200x PEN IRQ */
+ MX6_PAD_JTAG_TMS__GPIO1_IO11 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL),
+#if 0
+ /* EDT-FT5x06 Polytouch panel */
+ MX6_PAD_NAND_CS2__GPIO6_IO15 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* IRQ */
+ MX6_PAD_EIM_A16__GPIO2_IO22 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* RESET */
+ MX6_PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* WAKE */
+
+ /* USBH1 */
+ MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */
+ MX6_PAD_EIM_D30__GPIO3_IO30 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */
+ /* USBOTG */
+ MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* USBOTG ID */
+ MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */
+ MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */
+#endif
+};
+
+static const struct gpio stk5_gpios[] = {
+ { TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
+
+ { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", },
+ { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
+ { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
+ { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
+ { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
+};
+
+#ifdef CONFIG_LCD
+static u16 tx6_cmap[256];
+vidinfo_t panel_info = {
+ /* set to max. size supported by SoC */
+ .vl_col = 1920,
+ .vl_row = 1080,
+
+ .vl_bpix = LCD_COLOR32, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
+ .cmap = tx6_cmap,
+};
+
+static struct fb_videomode tx6_fb_modes[] = {
+#ifndef CONFIG_SYS_LVDS_IF
+ {
+ /* Standard VGA timing */
+ .name = "VGA",
+ .refresh = 60,
+ .xres = 640,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(25175),
+ .left_margin = 48,
+ .hsync_len = 96,
+ .right_margin = 16,
+ .upper_margin = 31,
+ .vsync_len = 2,
+ .lower_margin = 12,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ETV570 640 x 480 display. Syncs low active,
+ * DE high active, 115.2 mm x 86.4 mm display area
+ * VGA compatible timing
+ */
+ .name = "ETV570",
+ .refresh = 60,
+ .xres = 640,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(25175),
+ .left_margin = 114,
+ .hsync_len = 30,
+ .right_margin = 16,
+ .upper_margin = 32,
+ .vsync_len = 3,
+ .lower_margin = 10,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ET0350G0DH6 320 x 240 display.
+ * 70.08 mm x 52.56 mm display area.
+ */
+ .name = "ET0350",
+ .refresh = 60,
+ .xres = 320,
+ .yres = 240,
+ .pixclock = KHZ2PICOS(6500),
+ .left_margin = 68 - 34,
+ .hsync_len = 34,
+ .right_margin = 20,
+ .upper_margin = 18 - 3,
+ .vsync_len = 3,
+ .lower_margin = 4,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ET0430G0DH6 480 x 272 display.
+ * 95.04 mm x 53.856 mm display area.
+ */
+ .name = "ET0430",
+ .refresh = 60,
+ .xres = 480,
+ .yres = 272,
+ .pixclock = KHZ2PICOS(9000),
+ .left_margin = 2,
+ .hsync_len = 41,
+ .right_margin = 2,
+ .upper_margin = 2,
+ .vsync_len = 10,
+ .lower_margin = 2,
+ },
+ {
+ /* Emerging ET0500G0DH6 800 x 480 display.
+ * 109.6 mm x 66.4 mm display area.
+ */
+ .name = "ET0500",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(33260),
+ .left_margin = 216 - 128,
+ .hsync_len = 128,
+ .right_margin = 1056 - 800 - 216,
+ .upper_margin = 35 - 2,
+ .vsync_len = 2,
+ .lower_margin = 525 - 480 - 35,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ETQ570G0DH6 320 x 240 display.
+ * 115.2 mm x 86.4 mm display area.
+ */
+ .name = "ETQ570",
+ .refresh = 60,
+ .xres = 320,
+ .yres = 240,
+ .pixclock = KHZ2PICOS(6400),
+ .left_margin = 38,
+ .hsync_len = 30,
+ .right_margin = 30,
+ .upper_margin = 16, /* 15 according to datasheet */
+ .vsync_len = 3, /* TVP -> 1>x>5 */
+ .lower_margin = 4, /* 4.5 according to datasheet */
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ET0700G0DH6 800 x 480 display.
+ * 152.4 mm x 91.44 mm display area.
+ */
+ .name = "ET0700",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(33260),
+ .left_margin = 216 - 128,
+ .hsync_len = 128,
+ .right_margin = 1056 - 800 - 216,
+ .upper_margin = 35 - 2,
+ .vsync_len = 2,
+ .lower_margin = 525 - 480 - 35,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ET070001DM6 800 x 480 display.
+ * 152.4 mm x 91.44 mm display area.
+ */
+ .name = "ET070001DM6",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(33260),
+ .left_margin = 216 - 128,
+ .hsync_len = 128,
+ .right_margin = 1056 - 800 - 216,
+ .upper_margin = 35 - 2,
+ .vsync_len = 2,
+ .lower_margin = 525 - 480 - 35,
+ .sync = 0,
+ },
+#else
+ {
+ /* HannStar HSD100PXN1
+ * 202.7m mm x 152.06 mm display area.
+ */
+ .name = "HSD100PXN1",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = KHZ2PICOS(65000),
+ .left_margin = 0,
+ .hsync_len = 0,
+ .right_margin = 320,
+ .upper_margin = 0,
+ .vsync_len = 0,
+ .lower_margin = 38,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+#endif
+ {
+ /* unnamed entry for assigning parameters parsed from 'video_mode' string */
+ .refresh = 60,
+ .left_margin = 48,
+ .hsync_len = 96,
+ .right_margin = 16,
+ .upper_margin = 31,
+ .vsync_len = 2,
+ .lower_margin = 12,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+};
+
+static int lcd_enabled = 1;
+static int lcd_bl_polarity;
+
+static int lcd_backlight_polarity(void)
+{
+ return lcd_bl_polarity;
+}
+
+void lcd_enable(void)
+{
+ /* HACK ALERT:
+ * global variable from common/lcd.c
+ * Set to 0 here to prevent messages from going to LCD
+ * rather than serial console
+ */
+ lcd_is_enabled = 0;
+
+ if (lcd_enabled) {
+ karo_load_splashimage(1);
+
+ debug("Switching LCD on\n");
+ gpio_set_value(TX6UL_LCD_PWR_GPIO, 1);
+ udelay(100);
+ gpio_set_value(TX6UL_LCD_RST_GPIO, 1);
+ udelay(300000);
+ gpio_set_value(TX6UL_LCD_BACKLIGHT_GPIO,
+ lcd_backlight_polarity());
+ }
+}
+
+void lcd_disable(void)
+{
+ if (lcd_enabled) {
+ printf("Disabling LCD\n");
+// ipuv3_fb_shutdown();
+ }
+}
+
+void lcd_panel_disable(void)
+{
+ if (lcd_enabled) {
+ debug("Switching LCD off\n");
+ gpio_set_value(TX6UL_LCD_BACKLIGHT_GPIO,
+ !lcd_backlight_polarity());
+ gpio_set_value(TX6UL_LCD_RST_GPIO, 0);
+ gpio_set_value(TX6UL_LCD_PWR_GPIO, 0);
+ }
+}
+
+static const iomux_v3_cfg_t stk5_lcd_pads[] = {
+#if 1
+ /* LCD RESET */
+ MX6_PAD_LCD_RESET__LCDIF_RESET,
+ /* LCD POWER_ENABLE */
+ MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL),
+ /* LCD Backlight (PWM) */
+ MX6_PAD_NAND_DQS__GPIO4_IO16 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL),
+#endif
+#ifdef CONFIG_LCD
+ /* Display */
+ MX6_PAD_LCD_DATA00__LCDIF_DATA00,
+ MX6_PAD_LCD_DATA01__LCDIF_DATA01,
+ MX6_PAD_LCD_DATA02__LCDIF_DATA02,
+ MX6_PAD_LCD_DATA03__LCDIF_DATA03,
+ MX6_PAD_LCD_DATA04__LCDIF_DATA04,
+ MX6_PAD_LCD_DATA05__LCDIF_DATA05,
+ MX6_PAD_LCD_DATA06__LCDIF_DATA06,
+ MX6_PAD_LCD_DATA07__LCDIF_DATA07,
+ MX6_PAD_LCD_DATA08__LCDIF_DATA08,
+ MX6_PAD_LCD_DATA09__LCDIF_DATA09,
+ MX6_PAD_LCD_DATA10__LCDIF_DATA10,
+ MX6_PAD_LCD_DATA11__LCDIF_DATA11,
+ MX6_PAD_LCD_DATA12__LCDIF_DATA12,
+ MX6_PAD_LCD_DATA13__LCDIF_DATA13,
+ MX6_PAD_LCD_DATA14__LCDIF_DATA14,
+ MX6_PAD_LCD_DATA15__LCDIF_DATA15,
+ MX6_PAD_LCD_DATA16__LCDIF_DATA16,
+ MX6_PAD_LCD_DATA17__LCDIF_DATA17,
+ MX6_PAD_LCD_DATA18__LCDIF_DATA18,
+ MX6_PAD_LCD_DATA19__LCDIF_DATA19,
+ MX6_PAD_LCD_DATA20__LCDIF_DATA20,
+ MX6_PAD_LCD_DATA21__LCDIF_DATA21,
+ MX6_PAD_LCD_DATA22__LCDIF_DATA22,
+ MX6_PAD_LCD_DATA23__LCDIF_DATA23,
+ MX6_PAD_LCD_HSYNC__LCDIF_HSYNC, /* HSYNC */
+ MX6_PAD_LCD_VSYNC__LCDIF_VSYNC, /* VSYNC */
+ MX6_PAD_LCD_ENABLE__LCDIF_ENABLE, /* OE_ACD */
+ MX6_PAD_LCD_CLK__LCDIF_CLK, /* LSCLK */
+#endif
+};
+
+static const struct gpio stk5_lcd_gpios[] = {
+// { TX6UL_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
+ { TX6UL_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
+ { TX6UL_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
+};
+
+void lcd_ctrl_init(void *lcdbase)
+{
+ int color_depth = 24;
+ const char *video_mode = karo_get_vmode(getenv("video_mode"));
+ const char *vm;
+ unsigned long val;
+ int refresh = 60;
+ struct fb_videomode *p = &tx6_fb_modes[0];
+ struct fb_videomode fb_mode;
+ int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
+ int pix_fmt;
+ int lcd_bus_width;
+
+ if (!lcd_enabled) {
+ debug("LCD disabled\n");
+ return;
+ }
+
+ if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
+ debug("Disabling LCD\n");
+ lcd_enabled = 0;
+ setenv("splashimage", NULL);
+ return;
+ }
+
+ karo_fdt_move_fdt();
+ lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
+
+ if (video_mode == NULL) {
+ debug("Disabling LCD\n");
+ lcd_enabled = 0;
+ return;
+ }
+ vm = video_mode;
+ if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
+ p = &fb_mode;
+ debug("Using video mode from FDT\n");
+ vm += strlen(vm);
+ if (fb_mode.xres > panel_info.vl_col ||
+ fb_mode.yres > panel_info.vl_row) {
+ printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
+ fb_mode.xres, fb_mode.yres,
+ panel_info.vl_col, panel_info.vl_row);
+ lcd_enabled = 0;
+ return;
+ }
+ }
+ if (p->name != NULL)
+ debug("Trying compiled-in video modes\n");
+ while (p->name != NULL) {
+ if (strcmp(p->name, vm) == 0) {
+ debug("Using video mode: '%s'\n", p->name);
+ vm += strlen(vm);
+ break;
+ }
+ p++;
+ }
+ if (*vm != '\0')
+ debug("Trying to decode video_mode: '%s'\n", vm);
+ while (*vm != '\0') {
+ if (*vm >= '0' && *vm <= '9') {
+ char *end;
+
+ val = simple_strtoul(vm, &end, 0);
+ if (end > vm) {
+ if (!xres_set) {
+ if (val > panel_info.vl_col)
+ val = panel_info.vl_col;
+ p->xres = val;
+ panel_info.vl_col = val;
+ xres_set = 1;
+ } else if (!yres_set) {
+ if (val > panel_info.vl_row)
+ val = panel_info.vl_row;
+ p->yres = val;
+ panel_info.vl_row = val;
+ yres_set = 1;
+ } else if (!bpp_set) {
+ switch (val) {
+ case 32:
+ case 24:
+ if (is_lvds())
+ pix_fmt = IPU_PIX_FMT_LVDS888;
+ /* fallthru */
+ case 16:
+ case 8:
+ color_depth = val;
+ break;
+
+ case 18:
+ if (is_lvds()) {
+ color_depth = val;
+ break;
+ }
+ /* fallthru */
+ default:
+ printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
+ end - vm, vm, color_depth);
+ }
+ bpp_set = 1;
+ } else if (!refresh_set) {
+ refresh = val;
+ refresh_set = 1;
+ }
+ }
+ vm = end;
+ }
+ switch (*vm) {
+ case '@':
+ bpp_set = 1;
+ /* fallthru */
+ case '-':
+ yres_set = 1;
+ /* fallthru */
+ case 'x':
+ xres_set = 1;
+ /* fallthru */
+ case 'M':
+ case 'R':
+ vm++;
+ break;
+
+ default:
+ if (*vm != '\0')
+ vm++;
+ }
+ }
+ if (p->xres == 0 || p->yres == 0) {
+ printf("Invalid video mode: %s\n", getenv("video_mode"));
+ lcd_enabled = 0;
+ printf("Supported video modes are:");
+ for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
+ printf(" %s", p->name);
+ }
+ printf("\n");
+ return;
+ }
+ if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
+ printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
+ p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
+ lcd_enabled = 0;
+ return;
+ }
+ panel_info.vl_col = p->xres;
+ panel_info.vl_row = p->yres;
+
+ switch (color_depth) {
+ case 8:
+ panel_info.vl_bpix = LCD_COLOR8;
+ break;
+ case 16:
+ panel_info.vl_bpix = LCD_COLOR16;
+ break;
+ default:
+ panel_info.vl_bpix = LCD_COLOR32;
+ }
+
+ p->pixclock = KHZ2PICOS(refresh *
+ (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
+ (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
+ 1000);
+ debug("Pixel clock set to %lu.%03lu MHz\n",
+ PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
+
+ if (p != &fb_mode) {
+ int ret;
+
+ debug("Creating new display-timing node from '%s'\n",
+ video_mode);
+ ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
+ if (ret)
+ printf("Failed to create new display-timing node from '%s': %d\n",
+ video_mode, ret);
+ }
+
+ gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
+ imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
+ ARRAY_SIZE(stk5_lcd_pads));
+
+ lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
+ switch (lcd_bus_width) {
+ case 24:
+ pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
+ break;
+
+ case 18:
+ pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
+ break;
+
+ case 16:
+ if (!is_lvds()) {
+ pix_fmt = IPU_PIX_FMT_RGB565;
+ break;
+ }
+ /* fallthru */
+ default:
+ lcd_enabled = 0;
+ printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
+ lcd_bus_width);
+ return;
+ }
+ if (is_lvds()) {
+ int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
+ int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
+ uint32_t gpr2;
+ uint32_t gpr3;
+
+ if (lvds_chan_mask == 0) {
+ printf("No LVDS channel active\n");
+ lcd_enabled = 0;
+ return;
+ }
+
+ gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
+ if (lcd_bus_width == 24)
+ gpr2 |= (1 << 5) | (1 << 7);
+ gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
+ gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
+ debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
+ writel(gpr2, IOMUXC_BASE_ADDR + 8);
+
+ gpr3 = readl(IOMUXC_BASE_ADDR + 0xc);
+ gpr3 &= ~((3 << 8) | (3 << 6));
+ writel(gpr3, IOMUXC_BASE_ADDR + 0xc);
+ }
+ if (karo_load_splashimage(0) == 0) {
+#if 0
+ int ret;
+
+ debug("Initializing LCD controller\n");
+ ret = ipuv3_fb_init(p, 0, pix_fmt,
+ is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3,
+ di_clk_rate, -1);
+ if (ret) {
+ printf("Failed to initialize FB driver: %d\n", ret);
+ lcd_enabled = 0;
+ }
+#else
+ lcd_enabled = pix_fmt * 0;
+#endif
+ } else {
+ debug("Skipping initialization of LCD controller\n");
+ }
+}
+#else
+#define lcd_enabled 0
+#endif /* CONFIG_LCD */
+
+static void stk5_board_init(void)
+{
+ int ret;
+
+ ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
+ if (ret < 0) {
+ printf("Failed to request stk5_gpios: %d\n", ret);
+ return;
+ }
+ imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
+debug("%s@%d: \n", __func__, __LINE__);
+}
+
+static void stk5v3_board_init(void)
+{
+debug("%s@%d: \n", __func__, __LINE__);
+ stk5_board_init();
+debug("%s@%d: \n", __func__, __LINE__);
+}
+
+static void stk5v5_board_init(void)
+{
+ int ret;
+
+ stk5_board_init();
+
+ ret = gpio_request_one(IMX_GPIO_NR(3, 5), GPIOFLAG_OUTPUT_INIT_HIGH,
+ "Flexcan Transceiver");
+ if (ret) {
+ printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
+ return;
+ }
+
+ imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA00__GPIO3_IO05 |
+ MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL));
+}
+
+static void tx6ul_set_cpu_clock(void)
+{
+ unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
+
+ if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
+ return;
+
+ if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
+ printf("%s detected; skipping cpu clock change\n",
+ (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
+ return;
+ }
+ if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
+ cpu_clk = mxc_get_clock(MXC_ARM_CLK);
+ printf("CPU clock set to %lu.%03lu MHz\n",
+ cpu_clk / 1000000, cpu_clk / 1000 % 1000);
+ } else {
+ printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
+ }
+}
+
+int board_late_init(void)
+{
+ int ret = 0;
+ const char *baseboard;
+
+ debug("%s@%d: \n", __func__, __LINE__);
+
+ env_cleanup();
+
+ if (tx6_temp_check_enabled)
+ check_cpu_temperature(1);
+
+ tx6ul_set_cpu_clock();
+
+ if (had_ctrlc())
+ setenv_ulong("safeboot", 1);
+ else if (wrsr & WRSR_TOUT)
+ setenv_ulong("wdreset", 1);
+ else
+ karo_fdt_move_fdt();
+
+ baseboard = getenv("baseboard");
+ if (!baseboard)
+ goto exit;
+
+ printf("Baseboard: %s\n", baseboard);
+
+ if (strncmp(baseboard, "stk5", 4) == 0) {
+ if ((strlen(baseboard) == 4) ||
+ strcmp(baseboard, "stk5-v3") == 0) {
+ stk5v3_board_init();
+ } else if (strcmp(baseboard, "stk5-v5") == 0) {
+ const char *otg_mode = getenv("otg_mode");
+
+ if (otg_mode && strcmp(otg_mode, "host") == 0) {
+ printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
+ otg_mode, baseboard);
+ setenv("otg_mode", "none");
+ }
+ stk5v5_board_init();
+ } else {
+ printf("WARNING: Unsupported STK5 board rev.: %s\n",
+ baseboard + 4);
+ }
+ } else {
+ printf("WARNING: Unsupported baseboard: '%s'\n",
+ baseboard);
+ ret = -EINVAL;
+ }
+
+exit:
+debug("%s@%d: \n", __func__, __LINE__);
+ tx6_init_mac();
+debug("%s@%d: \n", __func__, __LINE__);
+
+ clear_ctrlc();
+ return ret;
+}
+
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
+
+ serialnr->low = readl(&fuse->cfg0);
+ serialnr->high = readl(&fuse->cfg1);
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+#include <jffs2/jffs2.h>
+#include <mtd_node.h>
+static struct node_info nodes[] = {
+ { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
+};
+#else
+#define fdt_fixup_mtdparts(b,n,c) do { } while (0)
+#endif
+
+static const char *tx6_touchpanels[] = {
+ "ti,tsc2007",
+ "edt,edt-ft5x06",
+ "eeti,egalax_ts",
+};
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ const char *baseboard = getenv("baseboard");
+ int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
+ const char *video_mode = karo_get_vmode(getenv("video_mode"));
+ int ret;
+
+ ret = fdt_increase_size(blob, 4096);
+ if (ret) {
+ printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
+ return ret;
+ }
+ if (stk5_v5)
+ karo_fdt_enable_node(blob, "stk5led", 0);
+
+ fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+
+ karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
+ ARRAY_SIZE(tx6_touchpanels));
+ karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
+ karo_fdt_fixup_flexcan(blob, stk5_v5);
+
+ karo_fdt_update_fb_mode(blob, video_mode);
+
+ return 0;
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
--- /dev/null
+#include <config.h>
+#include <asm-offsets.h>
+#include <configs/tx6.h>
+#include <linux/linkage.h>
+#include <asm/arch/imx-regs.h>
+#include <generated/asm-offsets.h>
+
+#ifndef CCM_CCR
+#error asm-offsets not included
+#endif
+
+#define DEBUG_LED_BIT 20
+#define LED_GPIO_BASE GPIO2_BASE_ADDR
+#define LED_MUX_OFFSET 0x0ec
+#define LED_MUX_MODE 0x15
+
+#define SDRAM_CLK CONFIG_SYS_SDRAM_CLK
+
+#ifdef PHYS_SDRAM_2_SIZE
+#define SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
+#else
+#define SDRAM_SIZE PHYS_SDRAM_1_SIZE
+#endif
+
+#define CPU_2_BE_32(l) \
+ ((((l) << 24) & 0xFF000000) | \
+ (((l) << 8) & 0x00FF0000) | \
+ (((l) >> 8) & 0x0000FF00) | \
+ (((l) >> 24) & 0x000000FF))
+
+#define CHECK_DCD_ADDR(a) ( \
+ ((a) >= 0x020E0000 && (a) <= 0x020E3FFF) /* IOMUXC */ || \
+ ((a) >= 0x020E4000 && (a) <= 0x020E7FFF) /* IOMUXC GPR */ || \
+ ((a) >= 0x020C4000 && (a) <= 0x020C7FFF) /* CCM */ || \
+ ((a) >= 0x020C8000 && (a) <= 0x020C8FFF) /* ANALOG */ || \
+ ((a) >= 0x021B0000 && (a) <= 0x021B3FFF) /* MMDC */ || \
+ ((a) >= 0x00907000 && (a) <= 0x00937FF0) /* OCRAM */ || \
+ ((a) >= 0x021B8000 && (a) <= 0x021BBFFF) /* EIM registers */ || \
+ ((a) >= 0x80000000 && (a) <= 0xFFFF7FFF) /* SDRAM */ || \
+ ((a) >= 0x020D0000 && (a) <= 0x020D3FFF) /* EPIT */)
+
+ .macro mxc_dcd_item addr, val
+ .ifne CHECK_DCD_ADDR(\addr)
+ .word CPU_2_BE_32(\addr), CPU_2_BE_32(\val)
+ .else
+ .error "Address \addr not accessible from DCD"
+ .endif
+ .endm
+
+#define MXC_DCD_ITEM(addr, val) mxc_dcd_item (addr), (val)
+
+#define MXC_DCD_CMD_SZ_BYTE 1
+#define MXC_DCD_CMD_SZ_SHORT 2
+#define MXC_DCD_CMD_SZ_WORD 4
+#define MXC_DCD_CMD_FLAG_WRITE 0x0
+#define MXC_DCD_CMD_FLAG_CLR 0x1
+#define MXC_DCD_CMD_FLAG_SET 0x3
+#define MXC_DCD_CMD_FLAG_CHK_CLR ((0 << 0) | (0 << 1))
+#define MXC_DCD_CMD_FLAG_CHK_SET ((0 << 0) | (1 << 1))
+#define MXC_DCD_CMD_FLAG_CHK_ANY_CLR ((1 << 0) | (0 << 1))
+#define MXC_DCD_CMD_FLAG_CHK_ANY_SET ((1 << 0) | (1 << 1))
+
+#define MXC_DCD_START \
+ .word CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION) ; \
+dcd_start:
+
+ .macro MXC_DCD_END
+1:
+ .ifgt . - dcd_start - 1768
+ .error "DCD too large!"
+ .endif
+dcd_end:
+ .section ".pad"
+ .section ".text"
+ .endm
+
+#define MXC_DCD_CMD_WRT(type, flags) \
+1: .word CPU_2_BE_32((0xcc << 24) | ((1f - .) << 8) | ((flags) << 3) | (type))
+
+#define MXC_DCD_CMD_CHK(type, flags, addr, mask) \
+1: .word CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)), \
+ CPU_2_BE_32(addr), CPU_2_BE_32(mask)
+
+#define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count) \
+1: .word CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)), \
+ CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count)
+
+#define MXC_DCD_CMD_NOP() \
+1: .word CPU_2_BE_32((0xc0 << 24) | (4 << 8))
+
+
+#define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
+#define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
+#define NS_TO_CK10(ns) DIV_ROUND_UP(NS_TO_CK(ns), 10)
+#define PS_TO_CK(ps) DIV_ROUND_UP(NS_TO_CK(ps), 1000)
+
+ .macro CK_VAL, name, clks, offs, max
+ .iflt \clks - \offs
+ .set \name, 0
+ .else
+ .ifle \clks - \offs - \max
+ .set \name, \clks - \offs
+ .else
+ .error "Value \clks out of range for parameter \name"
+ .endif
+ .endif
+ .endm
+
+ .macro NS_VAL, name, ns, offs, max
+ .iflt \ns - \offs
+ .set \name, 0
+ .else
+ CK_VAL \name, NS_TO_CK(\ns), \offs, \max
+ .endif
+ .endm
+
+ .macro CK_MAX, name, ck1, ck2, offs, max
+ .ifgt \ck1 - \ck2
+ CK_VAL \name, \ck1, \offs, \max
+ .else
+ CK_VAL \name, \ck2, \offs, \max
+ .endif
+ .endm
+
+#define MDMISC_DDR_TYPE_DDR3 0
+#define MDMISC_DDR_TYPE_LPDDR2 1
+#define MDMISC_DDR_TYPE_DDR2 2
+
+#define DIV_ROUND_UP(m,d) (((m) + (d) - 1) / (d))
+
+#define MDOR_CLK_PERIOD_ns 15258 /* base clock for MDOR values */
+
+/* DDR3 SDRAM */
+#if SDRAM_SIZE > PHYS_SDRAM_1_SIZE
+#define BANK_ADDR_BITS 2
+#else
+#define BANK_ADDR_BITS 1
+#endif
+#define SDRAM_BURST_LENGTH 8
+#define RALAT 5
+#define WALAT 1
+#define BI_ON 1
+#define ADDR_MIRROR 0
+#define DDR_TYPE MDMISC_DDR_TYPE_DDR3
+
+/* 512/1024MiB SDRAM: NT5CB128M16FP-DII or MT41K128M16JT-125 */
+#if SDRAM_CLK > 666 && SDRAM_CLK <= 800
+#define CL_VAL 11
+#define CWL_VAL 8
+#elif SDRAM_CLK > 533 && SDRAM_CLK <= 666
+#define CL_VAL 9 // or 10
+#define CWL_VAL 7
+#elif SDRAM_CLK > 400 && SDRAM_CLK <= 533
+#define CL_VAL 7 // or 8
+#define CWL_VAL 6
+#elif SDRAM_CLK > 333 && SDRAM_CLK <= 400
+#define CL_VAL 6
+#define CWL_VAL 5
+#elif SDRAM_CLK >= 303 && SDRAM_CLK <= 333
+#define CL_VAL 5
+#define CWL_VAL 5
+#else
+#error SDRAM clock out of range: 303 .. 800
+#endif
+
+/* MDCFG0 0x0c */
+NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */
+CK_MAX tXS, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
+CK_MAX tXP, NS_TO_CK10(75), 3, 1, 7 /* clks - 1 (0..7) */ /* max(3tCK, 7.5ns) (MT41K128M16JT: 6ns) */
+CK_MAX tXPDLL, NS_TO_CK(24), 10, 1, 15 /* clks - 1 (0..15) */
+NS_VAL tFAW, 50, 1, 31 /* clks - 1 (0..31) (MT41K128M16JT: 30ns) */
+CK_VAL tCL, CL_VAL, 3, 8 /* clks - 3 (0..8) CAS Latency */
+
+/* MDCFG1 0x10 */
+CK_VAL tRCD, PS_TO_CK(13750), 1, 7 /* clks - 1 (0..7) */ /* 13.75 (NT5CB128M16FP: 12.5ns) */
+CK_VAL tRP, PS_TO_CK(13750), 1, 7 /* clks - 1 (0..7) */ /* 13.75 (NT5CB128M16FP: 12.5ns) */
+NS_VAL tRC, 50, 1, 31 /* clks - 1 (0..31) (MT41K128M16JT: 49ns) */
+CK_VAL tRAS, NS_TO_CK10(375), 1, 31 /* clks - 1 (0..31) (MT41K128M16JT: 3.5ns) */
+CK_VAL tRPA, 1, 0, 1 /* clks (0..1) */
+NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tCWL, CWL_VAL, 2, 6 /* clks - 2 (0..6) */
+
+/* MDCFG2 0x14 */
+CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */ /* (Jedec Standard) */
+CK_MAX tRTP, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
+CK_MAX tWTR, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
+CK_MAX tRRD, NS_TO_CK(10), 4, 1, 7 /* clks - 1 (0..7) (MT41K128M16JT: 6ns) */
+
+/* MDOR 0x30 */
+CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
+#define tSDE_RST (DIV_ROUND_UP(200000, MDOR_CLK_PERIOD_ns) + 2)
+#define tRST_CKE (DIV_ROUND_UP(500000, MDOR_CLK_PERIOD_ns) + 2)
+
+/* MDOTC 0x08 */
+CK_VAL tAOFPD, NS_TO_CK10(85), 1, 7 /* clks - 1 (0..7) */ /* 2ns .. 8.5ns */
+CK_VAL tAONPD, NS_TO_CK10(85), 1, 7 /* clks - 1 (0..7) */ /* 2ns .. 8.5ns */
+CK_VAL tANPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tAXPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tODTLon tCWL, 0, 7 /* clks - 1 (0..7) */ /* CWL+AL-2 */
+CK_VAL tODTLoff tCWL, 0, 31 /* clks - 1 (0..31) */ /* CWL+AL-2 */
+
+/* MDPDC 0x04 */
+CK_MAX tCKE, NS_TO_CK(5), 3, 1, 7
+CK_MAX tCKSRX, NS_TO_CK(10), 5, 0, 7
+CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7
+
+#define PRCT 0
+#define PWDT 5
+#define SLOW_PD 0
+#define BOTH_CS_PD 1
+
+#define MDPDC_VAL_0 ( \
+ (PRCT << 28) | \
+ (PRCT << 24) | \
+ (tCKE << 16) | \
+ (SLOW_PD << 7) | \
+ (BOTH_CS_PD << 6) | \
+ (tCKSRX << 3) | \
+ (tCKSRE << 0) \
+ )
+
+#define MDPDC_VAL_1 (MDPDC_VAL_0 | \
+ (PWDT << 12) | \
+ (PWDT << 8) \
+ )
+
+#define ROW_ADDR_BITS 14
+#define COL_ADDR_BITS 10
+
+#define Rtt_Nom 1 /* ODT: 0: off 1: RZQ/4 2: RZQ/2 3: RZQ/6 4: RZQ/12 5: RZQ/8 */
+#define Rtt_WR 0 /* Dynamic ODT: 0: off 1: RZQ/4 2: RZQ/2 */
+#define DLL_DISABLE 0
+
+ .iflt tWR - 7
+ .set mr0_val, (((1 - DLL_DISABLE) << 8) /* DLL Reset */ | \
+ (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\
+ ((tWR + 1 - 4) << 9) | \
+ ((((tCL + 3) - 4) & 0x7) << 4) | \
+ ((((tCL + 3) - 4) & 0x8) >> 1))
+ .else
+ .set mr0_val, ((1 << 8) /* DLL Reset */ | \
+ (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\
+ (((tWR + 1) / 2) << 9) | \
+ ((((tCL + 3) - 4) & 0x7) << 4) | \
+ ((((tCL + 3) - 4) & 0x8) >> 1))
+ .endif
+
+#define mr1_val ( \
+ ((Rtt_Nom & 1) << 2) | \
+ (((Rtt_Nom >> 1) & 1) << 6) | \
+ (((Rtt_Nom >> 2) & 1) << 9) | \
+ (DLL_DISABLE << 0) | \
+ 0)
+#define mr2_val ( \
+ (Rtt_WR << 9) /* dynamic ODT */ | \
+ (0 << 7) /* SRT: Ext. temp. (mutually exclusive with ASR!) */ | \
+ (1 << 6) | /* ASR: Automatic Self Refresh */ \
+ (((tCWL + 2) - 5) << 3) | \
+ 0)
+#define mr3_val 0
+
+#define MDSCR_MRS_VAL(cs, mr, val) (((val) << 16) | \
+ (1 << 15) /* CON_REQ */ | \
+ (3 << 4) /* MRS command */ | \
+ ((cs) << 3) | \
+ ((mr) << 0) | \
+ 0)
+
+#define MDCFG0_VAL ( \
+ (tRFC << 24) | \
+ (tXS << 16) | \
+ (tXP << 13) | \
+ (tXPDLL << 9) | \
+ (tFAW << 4) | \
+ (tCL << 0)) \
+
+#define MDCFG1_VAL ( \
+ (tRCD << 29) | \
+ (tRP << 26) | \
+ (tRC << 21) | \
+ (tRAS << 16) | \
+ (tRPA << 15) | \
+ (tWR << 9) | \
+ (tMRD << 5) | \
+ (tCWL << 0)) \
+
+#define MDCFG2_VAL ( \
+ (tDLLK << 16) | \
+ (tRTP << 6) | \
+ (tWTR << 3) | \
+ (tRRD << 0))
+
+#define BURST_LEN (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */
+
+#define MDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \
+ ((COL_ADDR_BITS - 9) << 20) | \
+ (BURST_LEN << 19) | \
+ ((CONFIG_SYS_SDRAM_BUS_WIDTH / 32) << 16) | \
+ ((-1) << (32 - BANK_ADDR_BITS)))
+
+#define MDMISC_WALAT(n) (((n) & 3) << 16)
+#define MDMISC_RALAT(n) (((n) & 7) << 6)
+
+#define CK1_GATING (2 - BANK_ADDR_BITS)
+
+#define MDMISC_VAL ((CK1_GATING << 21) | \
+ (ADDR_MIRROR << 19) | \
+ MDMISC_WALAT(WALAT) | \
+ (BI_ON << 12) | \
+ (0x3 << 9) | \
+ MDMISC_RALAT(RALAT) | \
+ (DDR_TYPE << 3))
+
+#define MDOR_VAL ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0))
+
+#define MDOTC_VAL ((tAOFPD << 27) | \
+ (tAONPD << 24) | \
+ (tANPD << 20) | \
+ (tAXPD << 16) | \
+ (tODTLon << 12) | \
+ (tODTLoff << 4))
+
+ .section ".ivt"
+ivt_header:
+ .word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40)
+app_start_addr:
+ .long _start
+ .long 0x0
+dcd_ptr:
+ .long dcd_hdr
+boot_data_ptr:
+ .word boot_data
+self_ptr:
+ .word ivt_header
+app_code_csf:
+#ifdef CONFIG_SECURE_BOOT
+ .word __csf_data
+#else
+ .word 0x0
+#endif
+ .word 0x0
+boot_data:
+ .long CONFIG_SYS_TEXT_BASE
+image_len:
+ .long __uboot_img_len
+plugin:
+ .word 0
+ivt_end:
+#define DCD_VERSION 0x40
+
+#define DDR_SEL_VAL 3 /* DDR3 */
+#if CONFIG_SYS_SDRAM_BUS_WIDTH == 16
+#define DSE1_VAL 6 /* Drive Strength for DATA lines */
+#define DSE2_VAL 6 /* Drive Strength for ADDR/CMD lines */
+#else
+#define DSE1_VAL 6 /* Drive Strength for DATA lines */
+#define DSE2_VAL 6 /* Drive Strength for ADDR/CMD lines */
+#endif
+#define ODT_VAL 2
+#define DDR_PKE_VAL 0
+
+#define DDR_SEL_SHIFT 18
+#define DDR_MODE_SHIFT 17
+#define ODT_SHIFT 8
+#define DSE_SHIFT 3
+#define HYS_SHIFT 16
+#define PKE_SHIFT 12
+#define PUE_SHIFT 13
+#define PUS_SHIFT 14
+
+#define DDR_SEL_MASK (DDR_SEL_VAL << DDR_SEL_SHIFT)
+#define DDR_MODE_MASK (1 << DDR_MODE_SHIFT) /* differential input mode */
+#define DSE1_MASK (DSE1_VAL << DSE_SHIFT)
+#define DSE2_MASK (DSE2_VAL << DSE_SHIFT)
+#define ODT_MASK (ODT_VAL << ODT_SHIFT)
+#define DDR_PKE_MASK (DDR_PKE_VAL << PKE_SHIFT)
+
+#define DQM_MASK (DDR_MODE_MASK | DSE2_MASK)
+#define SDQS_MASK DSE2_MASK
+#define SDODT_MASK (DSE2_MASK | (1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
+#define SDCLK_MASK (DDR_MODE_MASK | DSE2_MASK)
+#define SDCKE_MASK ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
+#define DDR_ADDR_MASK (ODT_MASK | DDR_MODE_MASK)
+#define DDR_CTRL_MASK (DDR_MODE_MASK | DSE2_MASK)
+
+#define MMDC_MDCTL 0x021b0000
+#define MMDC_MDPDC 0x021b0004
+#define MMDC_MDOTC 0x021b0008
+#define MMDC_MDCFG0 0x021b000c
+#define MMDC_MDCFG1 0x021b0010
+#define MMDC_MDCFG2 0x021b0014
+#define MMDC_MDMISC 0x021b0018
+#define MMDC_MDSCR 0x021b001c
+#define MMDC_MDREF 0x021b0020
+#define MMDC_MDRWD 0x021b002c
+#define MMDC_MDOR 0x021b0030
+#define MMDC_MDASP 0x021b0040
+
+#define MMDC_MAPSR 0x021b0404
+
+#define MMDC_MPZQHWCTRL 0x021b0800
+#define MMDC_MPWLGCR 0x021b0808
+#define MMDC_MPWLDECTRL0 0x021b080c
+#define MMDC_MPWLDLST 0x021b0814
+#define MMDC_MPODTCTRL 0x021b0818
+#define MMDC_MPRDDQBY0DL 0x021b081c
+#define MMDC_MPRDDQBY1DL 0x021b0820
+#define MMDC_MPWRDQBY0DL 0x021b082c
+#define MMDC_MPWRDQBY1DL 0x021b0830
+#define MMDC_MPDGCTRL0 0x021b083c
+#define MMDC_MPDGDLST0 0x021b0844
+#define MMDC_MPRDDLCTL 0x021b0848
+#define MMDC_MPRDDLST 0x021b084c
+#define MMDC_MPWRDLCTL 0x021b0850
+#define MMDC_MPWRDLST 0x021b0854
+#define MMDC_MPSDCTRL 0x021b0858
+#define MMDC_MPRDDLHWCTL 0x021b0860
+#define MMDC_MPWRDLHWCTL 0x021b0864
+#define MMDC_MPDGHWST0 0x021b087c
+#define MMDC_MPDGHWST1 0x021b0880
+#define MMDC_MPPDCMPR2 0x021b0890
+#define MMDC_MPSWDRDR0 0x021b0898
+#define MMDC_MPSWDRDR1 0x021b089c
+#define MMDC_MPSWDRDR2 0x021b08a0
+#define MMDC_MPSWDRDR3 0x021b08a4
+#define MMDC_MPSWDRDR4 0x021b08a8
+#define MMDC_MPSWDRDR5 0x021b08ac
+#define MMDC_MPSWDRDR6 0x021b08b0
+#define MMDC_MPSWDRDR7 0x021b08b4
+#define MMDC_MPMUR0 0x021b08b8
+
+#define IOMUXC_GPR0 0x020e4000
+#define IOMUXC_GPR1 0x020e4004
+#define IOMUXC_GPR2 0x020e4008
+#define IOMUXC_GPR3 0x020e400c
+#define IOMUXC_GPR4 0x020e4010
+#define IOMUXC_GPR5 0x020e4014
+#define IOMUXC_GPR10 0x020e4028
+#define IOMUXC_GPR14 0x020e4048
+
+#define IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER0 0x020e001c
+#define IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER1 0x020e0020
+#define IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER5 0x020e0030
+#define IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER6 0x020e0034
+#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA 0x020e0084
+#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA 0x020e0088
+#define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK 0x020e00dc
+#define IOMUXC_SW_MUX_CTL_PAD_UART1_CTS_B 0x020e008c
+#define IOMUXC_SW_MUX_CTL_PAD_UART1_RTS_B 0x020e0090
+#define IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK 0x020e00fc
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B 0x020e0178
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B 0x020e017c
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 0x020e0180
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 0x020e0184
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 0x020e0188
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 0x020e018c
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 0x020e0190
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 0x020e0194
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 0x020e0198
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 0x020e019c
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE 0x020e01a0
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B 0x020e01a4
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_READY 0x020e01a8
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B 0x020e01ac
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE 0x020e01b4
+
+#define IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER0 0x020e02a8
+#define IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER1 0x020e02ac
+#define IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER5 0x020e02bc
+#define IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER6 0x020e02c0
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA 0x020e0310
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA 0x020e0314
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_CTS_B 0x020e0318
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_RTS_B 0x020e031c
+#define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE 0x020e042c
+#define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE 0x020e0440
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00 0x020e0204
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01 0x020e0208
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 0x020e020c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 0x020e0210
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 0x020e0214
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 0x020e0218
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 0x020e021c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 0x020e0220
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 0x020e0224
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 0x020e0228
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10 0x020e022c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11 0x020e0230
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12 0x020e0234
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13 0x020e0238
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14 0x020e023c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 0x020e0244
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 0x020e0248
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS 0x020e024c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS 0x020e0250
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B 0x020e0254
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B 0x020e0258
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B 0x020e025c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 0x020e0260
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 0x020e0264
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0 0x020e0268
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1 0x020e026c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 0x020e0270
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 0x020e0274
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 0x020e0278
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P 0x020e027c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P 0x020e0280
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P 0x020e0284
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET 0x020e0288
+
+#define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK 0x020e0368
+#define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK 0x020e037c
+#define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B 0x020e0404
+#define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B 0x020e0408
+#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00 0x020e040c
+#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01 0x020e0410
+#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02 0x020e0414
+#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03 0x020e0418
+#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04 0x020e041c
+#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05 0x020e0420
+#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06 0x020e0424
+#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07 0x020e0428
+#define IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x020e0490
+#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 0x020e0494
+#define IOMUXC_SW_PAD_CTL_GRP_B0DS 0x020e0498
+#define IOMUXC_SW_PAD_CTL_GRP_DDRPK 0x020e049c
+#define IOMUXC_SW_PAD_CTL_GRP_CTLDS 0x020e04a0
+#define IOMUXC_SW_PAD_CTL_GRP_B1DS 0x020e04a4
+#define IOMUXC_SW_PAD_CTL_GRP_DDRHYS 0x020e04a8
+#define IOMUXC_SW_PAD_CTL_GRP_DDRPKE 0x020e04ac
+#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE 0x020e04b0
+#define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE 0x020e04b4
+
+#define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT 0x020e0620
+#define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x020e0624
+
+#define IOMUXC_ENET1_REF_CLK1_SELECT_INPUT 0x020e0574
+#define IOMUXC_ENET2_REF_CLK2_SELECT_INPUT 0x020e057c
+
+dcd_hdr:
+ MXC_DCD_START
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
+ /* setup I2C pads for PMIC */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER0, 0x00000015)
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER1, 0x00000015)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER0, 0x0000f0b9)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER1, 0x0000f0b9)
+ /* ENET_REF_CLK */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK, 0x00000014)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK, 0x000010b0)
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK, 0x00000014)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK, 0x000010b0)
+ MXC_DCD_ITEM(IOMUXC_ENET1_REF_CLK1_SELECT_INPUT, 2)
+ MXC_DCD_ITEM(IOMUXC_ENET2_REF_CLK2_SELECT_INPUT, 2)
+ /* ETN PHY nRST */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER6, 0x00000015)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER6, 0x000010b0)
+ /* ETN PHY Power */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER5, 0x00000015)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER5, 0x000010b0)
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x006336c1) /* default: 0x000336c1 */
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CSCDR2, 0x00012090) /* default: 0x0002a150 */
+
+ MXC_DCD_ITEM(ANATOP_BASE_ADDR + ANATOP_PLL_ENET, 0x00002005) /* ENET PLL */
+#define CCGR(m) (3 << ((m) * 2))
+ /* enable all relevant clocks... */
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET)
+ /* enable UART clock depending on selected console port */
+#if CONFIG_MXC_UART_BASE == UART1_BASE
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR5, CCGR(12)) /* UART1 */
+#elif CONFIG_MXC_UART_BASE == UART2_BASE
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR0, CCGR(14)) /* UART2 */
+#elif CONFIG_MXC_UART_BASE == UART3_BASE
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, CCGR(5)) /* UART3 */
+#elif CONFIG_MXC_UART_BASE == UART4_BASE
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, CCGR(12)) /* UART4 */
+#elif CONFIG_MXC_UART_BASE == UART5_BASE
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR3, CCGR(1)) /* UART5 */
+#endif
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR0, CCGR(2)) /* default: 0xcfc03f0f APBH-DMA */
+// MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, CCGR()) /* default: 0xfcfc0000 */
+// MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR()) /* default: 0x0c3ff033 */
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR3, CCGR(2)) /* default: 0xffff3300 ENET */
+#ifdef CONFIG_TX6_NAND
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4,
+ CCGR(15) | CCGR(14) | CCGR(13) | CCGR(12)) /* default: 0x0000f3ff GPMI BCH */
+#endif
+// MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR5, CCGR()) /* default: 0x0c3f0c3f */
+#ifdef CONFIG_TX6_EMMC
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, CCGR(2) | CCGR(1)) /* default: 0x00fc3003 USDHC2 USDHC1 */
+#else
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, CCGR(1)) /* default: 0x00fc3003 USDHC1 */
+#endif
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
+
+ MXC_DCD_ITEM(0x020c80a0, 0x80082029) /* set video PLL to 984MHz */
+ MXC_DCD_ITEM(0x020c80b0, 0x00065b9a)
+ MXC_DCD_ITEM(0x020c80c0, 0x000f4240)
+
+ /* IOMUX: */
+ MXC_DCD_ITEM(IOMUXC_GPR0, 0x00000000)
+ MXC_DCD_ITEM(IOMUXC_GPR1, 0x0f460005) /* default: 0x0f400005 ENET1_TX_CLK output */
+ MXC_DCD_ITEM(IOMUXC_GPR2, 0x00000000)
+ MXC_DCD_ITEM(IOMUXC_GPR3, 0x00000fff)
+ MXC_DCD_ITEM(IOMUXC_GPR4, 0x00000100)
+ MXC_DCD_ITEM(IOMUXC_GPR5, 0x00000000)
+ MXC_DCD_ITEM(IOMUXC_GPR10, 0x00000003)
+ /* UART1 pad config */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA, 0x00000000) /* UART1 TXD */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA, 0x000010b0) /* UART1 TXD */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA, 0x00000000) /* UART1 RXD */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA, 0x000010b0) /* UART1 RXD */
+ MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000003) /* UART1 RXD INPUT_SEL */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_UART1_CTS_B, 0x00000000) /* UART1 CTS */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_UART1_CTS_B, 0x000010b0) /* UART1 CTS */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_UART1_RTS_B, 0x00000000) /* UART1 RTS */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_UART1_RTS_B, 0x000010b0) /* UART1 RTS */
+ MXC_DCD_ITEM(IOMUXC_UART1_UART_RTS_B_SELECT_INPUT, 0x00000003) /* UART1 RTS INPUT_SEL */
+
+#ifdef CONFIG_NAND_MXS
+ /* NAND */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CLE, 0x00000000) /* NANDF_CLE: NANDF_CLE */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_NAND_CLE, 0x000030b0) /* NANDF_CLE: NANDF_CLE */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_ALE, 0x00000000) /* NANDF_ALE: NANDF_ALE */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B, 0x00000000) /* NANDF_WP_B: NANDF_WPn */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_READY, 0x00000000) /* NANDF_RB0: NANDF_READY0 */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B, 0x00000000) /* NANDF_CS0: NANDF_CS0 */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B, 0x00000000) /* NAND_RE_B: NANDF_RDn */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B, 0x00000000) /* NAND_WE_B: NANDF_WRn */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00, 0x00000000) /* NANDF_D0: NANDF_D0 */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01, 0x00000000) /* NANDF_D1: NANDF_D1 */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02, 0x00000000) /* NANDF_D2: NANDF_D2 */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03, 0x00000000) /* NANDF_D3: NANDF_D3 */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04, 0x00000000) /* NANDF_D4: NANDF_D4 */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05, 0x00000000) /* NANDF_D5: NANDF_D5 */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06, 0x00000000) /* NANDF_D6: NANDF_D6 */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07, 0x00000000) /* NANDF_D7: NANDF_D7 */
+#endif
+ /* DRAM_DQM[0..1] */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, DQM_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, DQM_MASK)
+
+ /* DRAM_A[0..15] */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14, DDR_ADDR_MASK)
+ /* DRAM_CAS */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS, DDR_CTRL_MASK)
+ /* DRAM_RAS */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS, DDR_CTRL_MASK)
+ /* DRAM_SDCLK0 */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P, SDCLK_MASK)
+ /* DRAM_RESET */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET, DDR_CTRL_MASK)
+ /* DRAM_SDCKE[0..1] */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0, SDCKE_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1, SDCKE_MASK)
+ /* DRAM_SDBA[0..2] */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0, 0x00000000)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1, 0x00000000)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2, 0x00000000)
+ /* DRAM_SDODT[0..1] */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0, SDODT_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1, SDODT_MASK)
+ /* DRAM_B[0..1]DS */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B0DS, DSE1_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B1DS, DSE1_MASK)
+ /* ADDDS */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_ADDDS, DSE2_MASK)
+ /* DDRMODE_CTL */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL, DDR_MODE_MASK)
+ /* DDRPKE */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPKE, DDR_PKE_MASK)
+ /* DDRMODE */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE, DDR_MODE_MASK)
+ /* CTLDS */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_CTLDS, DSE2_MASK)
+ /* DDR_TYPE */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE, DDR_SEL_MASK)
+ /* DDRPK */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPK, 1 << PUE_SHIFT)
+ /* DDRHYS */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRHYS, 0x00000000)
+
+ /* SDRAM initialization */
+#define WL_DLY_DQS_VAL 7
+#define WL_DLY_DQS0 (WL_DLY_DQS_VAL + 0)
+#define WL_DLY_DQS1 (WL_DLY_DQS_VAL + 0)
+
+ /* MDMISC */
+ MXC_DCD_ITEM(MMDC_MDMISC, MDMISC_VAL | 2) /* reset MMDC FSM */
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC_MDMISC, 0x00000002)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
+
+ /* ZQ calibration */
+ MXC_DCD_ITEM(MMDC_MDSCR, 0x04008010) /* precharge all */
+ MXC_DCD_ITEM(MMDC_MDSCR, 0x04008040) /* MRS: ZQ calibration */
+ MXC_DCD_ITEM(MMDC_MPZQHWCTRL, 0xa1390001)
+
+ MXC_DCD_ITEM(MMDC_MPWLDECTRL0, (WL_DLY_DQS1 << 16) | (WL_DLY_DQS0 << 0))
+
+ MXC_DCD_ITEM(MMDC_MPDGCTRL0, 0x41ae012f)
+
+ MXC_DCD_ITEM(MMDC_MPRDDLCTL, 0x3f3f4d4c) /* DQ RD Delay default values */
+ MXC_DCD_ITEM(MMDC_MPWRDLCTL, 0x3f3f3f3f) /* DQ WR Delay default values */
+
+ /* MPRDDQBY[0..7]DL */
+ MXC_DCD_ITEM(MMDC_MPRDDQBY0DL, 0x33333333)
+ MXC_DCD_ITEM(MMDC_MPRDDQBY1DL, 0x33333333)
+ /* MPRDDQBY[0..7]DL */
+ MXC_DCD_ITEM(MMDC_MPWRDQBY0DL, 0x33333333)
+ MXC_DCD_ITEM(MMDC_MPWRDQBY1DL, 0x33333333)
+#define MPMUR_FRC_MSR (1 << 11)
+ MXC_DCD_ITEM(MMDC_MPMUR0, MPMUR_FRC_MSR)
+
+ /* MDCTL */
+ MXC_DCD_ITEM(MMDC_MDCTL, MDCTL_VAL)
+#if BANK_ADDR_BITS > 1
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC_MDMISC, (3 << 30))
+#else
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC_MDMISC, (1 << 30))
+#endif
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
+
+ /* MSDSCR Conf Req */
+ MXC_DCD_ITEM(MMDC_MDSCR, 0x00008000)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC_MDSCR, 0x00004000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
+
+ MXC_DCD_ITEM(MMDC_MDCFG0, MDCFG0_VAL)
+ MXC_DCD_ITEM(MMDC_MDCFG1, MDCFG1_VAL)
+ MXC_DCD_ITEM(MMDC_MDCFG2, MDCFG2_VAL)
+
+ MXC_DCD_ITEM(MMDC_MDRWD, 0x000026d2)
+ MXC_DCD_ITEM(MMDC_MDOR, MDOR_VAL)
+ MXC_DCD_ITEM(MMDC_MDOTC, MDOTC_VAL)
+ MXC_DCD_ITEM(MMDC_MDPDC, MDPDC_VAL_0)
+ MXC_DCD_ITEM(MMDC_MDASP, PHYS_SDRAM_1_SIZE / SZ_32M + 0x3f)
+
+ /* CS0 MRS: */
+ MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(0, 0, mr0_val))
+ MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(0, 1, mr1_val))
+ MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(0, 2, mr2_val))
+ MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(0, 3, 0))
+#if BANK_ADDR_BITS > 1
+ /* CS1 MRS: */
+ MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(1, 0, mr0_val))
+ MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(1, 1, mr1_val))
+ MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(1, 2, mr2_val))
+ MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(1, 3, 0))
+#endif
+ MXC_DCD_ITEM(MMDC_MDREF, 0x0000c000) /* disable refresh */
+ MXC_DCD_ITEM(MMDC_MDSCR, 0x00008020) /* issue one refresh cycle */
+
+ MXC_DCD_ITEM(MMDC_MPODTCTRL, 0x00022222)
+
+ /* DDR3 calibration */
+ MXC_DCD_ITEM(MMDC_MPPDCMPR2, 0x00000003) /* select default compare pattern for DQ calibration */
+ MXC_DCD_ITEM(MMDC_MAPSR, 1)
+
+ /* ZQ calibration */
+ MXC_DCD_ITEM(MMDC_MDSCR, 0x04008010) /* precharge all */
+ MXC_DCD_ITEM(MMDC_MDSCR, 0x04008040) /* MRS: ZQ calibration */
+ MXC_DCD_ITEM(MMDC_MPZQHWCTRL, 0xa1390001)
+
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC_MPZQHWCTRL, 0x00010000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
+ MXC_DCD_ITEM(MMDC_MPZQHWCTRL, 0xa1380000)
+ MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */
+#if BANK_ADDR_BITS > 1
+ MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */
+#endif
+ /* DRAM_SDQS[0..1] pad config */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK)
+ /* Read delay calibration */
+ MXC_DCD_ITEM(MMDC_MDSCR, 0x04008050) /* precharge all to bank 0 */
+ MXC_DCD_ITEM(MMDC_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC_MPRDDLHWCTL, 0x00000013)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
+
+ /* Write delay calibration */
+ MXC_DCD_ITEM(MMDC_MDSCR, 0x04008050) /* precharge all to bank 0 */
+ MXC_DCD_ITEM(MMDC_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC_MPWRDLHWCTL, 0x00000013)
+
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
+ MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
+#if BANK_ADDR_BITS > 1
+ MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(1, 3, 0)) /* MRS: select normal data path */
+#endif
+ MXC_DCD_ITEM(MMDC_MPZQHWCTRL, 0xa138002b)
+ MXC_DCD_ITEM(MMDC_MDREF, (3 << 11) | (0 << 14)) /* 4 cycles per 64kHz period (3.9us) */
+ MXC_DCD_ITEM(MMDC_MAPSR, (16 << 8) | (0 << 0))
+ MXC_DCD_ITEM(MMDC_MDPDC, MDPDC_VAL_1)
+
+ /* MDSCR: Normal operation */
+ MXC_DCD_ITEM(MMDC_MDSCR, 0x00000000)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC_MDSCR, 0x00004000)
+ MXC_DCD_END
karo_fdt_enable_node(blob, "stk5led", 0);
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
- fdt_fixup_ethernet(blob);
karo_fdt_fixup_touchpanel(blob, txa5_touchpanels,
ARRAY_SIZE(txa5_touchpanels));
config AUTOBOOT_KEYED
bool "Stop autobooting via specific input key / string"
- default n
help
This option enables stopping (aborting) of the automatic
boot feature only by issuing a specific input key or
config AUTOBOOT_ENCRYPTION
bool "Enable encryption in autoboot stopping"
depends on AUTOBOOT_KEYED
- default n
config AUTOBOOT_DELAY_STR
string "Delay autobooting via specific input key / string"
config AUTOBOOT_KEYED_CTRLC
bool "Enable Ctrl-C autoboot interruption"
depends on AUTOBOOT_KEYED && !AUTOBOOT_ENCRYPTION
- default n
help
This option allows for the boot sequence to be interrupted
by ctrl-c, in addition to the "bootdelaykey" and "bootstopkey".
ret = gpio_request(gpio, "cmd_gpio");
if (ret && ret != -EBUSY) {
printf("gpio: requesting pin %u failed\n", gpio);
- return -1;
+ return CMD_RET_FAILURE;
}
/* finally, let's do it: set direction and exec command */
if (ret != -EBUSY)
gpio_free(gpio);
- return value;
+ return (ret && ret != -EBUSY) ? CMD_RET_FAILURE : CMD_RET_SUCCESS;
}
U_BOOT_CMD(gpio, 4, 0, do_gpio,
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6UL_14X14_EVK=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6UL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SOC_MX6UL"
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=SZ_128M"
CONFIG_ARM=y
+CONFIG_ARCH_MXS=y
CONFIG_TARGET_TX28=y
CONFIG_TARGET_TX28_40X1=y
CONFIG_TX28_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=SZ_128M"
CONFIG_ARM=y
+CONFIG_ARCH_MXS=y
CONFIG_TARGET_TX28=y
CONFIG_TARGET_TX28_40X1=y
CONFIG_TX28_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=SZ_256M"
CONFIG_ARM=y
+CONFIG_ARCH_MXS=y
CONFIG_TARGET_TX28=y
CONFIG_TARGET_TX28_40X1=y
CONFIG_TX28_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=SZ_256M"
CONFIG_ARM=y
+CONFIG_ARCH_MXS=y
CONFIG_TARGET_TX28=y
CONFIG_TARGET_TX28_40X1=y
CONFIG_TX28_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=SZ_128M,SYS_NAND_BLOCKS=2048"
CONFIG_ARM=y
+CONFIG_ARCH_MXS=y
CONFIG_TARGET_TX28=y
CONFIG_TARGET_TX28_40X1=y
CONFIG_TX28_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=SZ_128M,SYS_NAND_BLOCKS=2048"
CONFIG_ARM=y
+CONFIG_ARCH_MXS=y
CONFIG_TARGET_TX28=y
CONFIG_TARGET_TX28_40X1=y
CONFIG_TX28_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="TX28_S,SYS_SDRAM_SIZE=SZ_64M"
CONFIG_ARM=y
+CONFIG_ARCH_MXS=y
CONFIG_TARGET_TX28=y
CONFIG_TARGET_TX28_41X0=y
CONFIG_TX28_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="TX28_S,SYS_SDRAM_SIZE=SZ_64M"
CONFIG_ARM=y
+CONFIG_ARCH_MXS=y
CONFIG_TARGET_TX28=y
CONFIG_TARGET_TX28_41X0=y
CONFIG_TX28_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_CPU_CLK=800"
CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
CONFIG_TARGET_TX51=y
CONFIG_TARGET_TX51_8XX0=y
CONFIG_TX51_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_CPU_CLK=800"
CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
CONFIG_TARGET_TX51=y
CONFIG_TARGET_TX51_8XX0=y
CONFIG_TX51_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_CPU_CLK=800"
CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
CONFIG_TARGET_TX51=y
CONFIG_TARGET_TX51_8XX1_2=y
CONFIG_TX51_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_CPU_CLK=800"
CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
CONFIG_TARGET_TX51=y
CONFIG_TARGET_TX51_8XX1_2=y
CONFIG_TX51_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=SZ_2G"
CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
CONFIG_TARGET_TX53=y
CONFIG_TARGET_TX53_1232=y
CONFIG_TX53_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=SZ_2G"
CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
CONFIG_TARGET_TX53=y
CONFIG_TARGET_TX53_1232=y
CONFIG_TX53_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT,SYS_SDRAM_SIZE=SZ_2G"
CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
CONFIG_TARGET_TX53=y
CONFIG_TARGET_TX53_1232=y
CONFIG_TX53_UBOOT=y
CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
CONFIG_TARGET_TX53=y
CONFIG_TARGET_TX53_X030=y
CONFIG_TX53_UBOOT=y
CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
CONFIG_TARGET_TX53=y
CONFIG_TARGET_TX53_X030=y
CONFIG_TX53_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
CONFIG_TARGET_TX53=y
CONFIG_TARGET_TX53_X030=y
CONFIG_TX53_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
CONFIG_TARGET_TX53=y
CONFIG_TARGET_TX53_X130=y
CONFIG_TX53_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
CONFIG_TARGET_TX53=y
CONFIG_TARGET_TX53_X130=y
CONFIG_TX53_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT,SYS_LVDS_IF"
CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
CONFIG_TARGET_TX53=y
CONFIG_TARGET_TX53_X130=y
CONFIG_TX53_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
CONFIG_TARGET_TX53=y
CONFIG_TARGET_TX53_X131=y
CONFIG_TX53_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
CONFIG_TARGET_TX53=y
CONFIG_TARGET_TX53_X131=y
CONFIG_TX53_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT,SYS_LVDS_IF"
CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
CONFIG_TARGET_TX53=y
CONFIG_TARGET_TX53_X131=y
CONFIG_TX53_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=4096,TX6_REV=0x2"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6Q_1020=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=4096,TX6_REV=0x2"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6Q_1020=y
CONFIG_TX6_UBOOT_MFG=y
CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=4096,TX6_REV=0x2"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6Q_1020=y
CONFIG_TX6_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=4096,SECURE_BOOT,TX6_REV=0x2"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6Q_1020=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6Q_1033=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6Q_1033=y
CONFIG_TX6_UBOOT_MFG=y
CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6Q_1033=y
CONFIG_TX6_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SECURE_BOOT"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6Q_1033=y
CONFIG_TX6_UBOOT=y
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6Q_10X0=y
CONFIG_TX6_UBOOT=y
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6Q_10X0=y
CONFIG_TX6_UBOOT_MFG=y
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6Q_10X0=y
CONFIG_TX6_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6Q_10X0=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6Q_11X0=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6Q_11X0=y
CONFIG_TX6_UBOOT_MFG=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6Q_11X0=y
CONFIG_TX6_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT,SYS_LVDS_IF"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6Q_11X0=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=16"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6S_8034=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=16"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6S_8034=y
CONFIG_TX6_UBOOT_MFG=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=16"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6S_8034=y
CONFIG_TX6_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT,SYS_SDRAM_BUS_WIDTH=16"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6S_8034=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SYS_SDRAM_BUS_WIDTH=32"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6S_8035=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SYS_SDRAM_BUS_WIDTH=32"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6S_8035=y
CONFIG_TX6_UBOOT_MFG=y
CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SYS_SDRAM_BUS_WIDTH=32"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6S_8035=y
CONFIG_TX6_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SECURE_BOOT,SYS_SDRAM_BUS_WIDTH=32"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6S_8035=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_8011=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_8011=y
CONFIG_TX6_UBOOT_MFG=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_8011=y
CONFIG_TX6_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT,SYS_SDRAM_BUS_WIDTH=32"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_8011=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BLOCKS=2048"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_8012=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BLOCKS=2048"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_8012=y
CONFIG_TX6_UBOOT_MFG=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BLOCKS=2048"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_8012=y
CONFIG_TX6_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT,SYS_NAND_BLOCKS=2048"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_8012=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_8033=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_8033=y
CONFIG_TX6_UBOOT_MFG=y
CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_8033=y
CONFIG_TX6_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SECURE_BOOT"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_8033=y
CONFIG_TX6_UBOOT=y
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_80X0=y
CONFIG_TX6_UBOOT=y
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_80X0=y
CONFIG_TX6_UBOOT_MFG=y
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_80X0=y
CONFIG_TX6_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_80X0=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32,SYS_LVDS_IF"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_8111=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32,SYS_LVDS_IF"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_8111=y
CONFIG_TX6_UBOOT_MFG=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32,SYS_LVDS_IF"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_8111=y
CONFIG_TX6_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT,SYS_LVDS_IF,SYS_SDRAM_BUS_WIDTH=32"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_8111=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_81X0=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_81X0=y
CONFIG_TX6_UBOOT_MFG=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_81X0=y
CONFIG_TX6_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT,SYS_LVDS_IF"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_81X0=y
CONFIG_TX6_UBOOT=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SOC_MX6UL=y
+CONFIG_TARGET_TX6=y
+CONFIG_TARGET_TX6UL_0010=y
+CONFIG_TX6_UBOOT=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_FEC_MXC=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_LCD=y
+CONFIG_MMC=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
+CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6UL U-Boot > "
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SOC_MX6UL=y
+CONFIG_TARGET_TX6=y
+CONFIG_TARGET_TX6UL_0010=y
+CONFIG_TX6_UBOOT_MFG=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_FEC_MXC=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_MMC=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
+CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6UL U-Boot > "
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SOC_MX6UL=y
+CONFIG_TARGET_TX6=y
+CONFIG_TARGET_TX6UL_0010=y
+CONFIG_TX6_UBOOT_NOENV=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_FEC_MXC=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_LCD=y
+CONFIG_MMC=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
+CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6UL U-Boot > "
--- /dev/null
+CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SOC_MX6UL=y
+CONFIG_TARGET_TX6=y
+CONFIG_TARGET_TX6UL_0010=y
+CONFIG_TX6_UBOOT=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_FEC_MXC=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_LCD=y
+CONFIG_MMC=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
+CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6UL U-Boot > "
--- /dev/null
+CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SOC_MX6UL=y
+CONFIG_TARGET_TX6=y
+CONFIG_TARGET_TX6UL_0011=y
+CONFIG_TX6_UBOOT=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FEC_MXC=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_LCD=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
+CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6UL U-Boot > "
--- /dev/null
+CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SOC_MX6UL=y
+CONFIG_TARGET_TX6=y
+CONFIG_TARGET_TX6UL_0011=y
+CONFIG_TX6_UBOOT_MFG=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FEC_MXC=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
+CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6UL U-Boot > "
--- /dev/null
+CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SOC_MX6UL=y
+CONFIG_TARGET_TX6=y
+CONFIG_TARGET_TX6UL_0011=y
+CONFIG_TX6_UBOOT_NOENV=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FEC_MXC=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_LCD=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
+CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6UL U-Boot > "
--- /dev/null
+CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SECURE_BOOT"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SOC_MX6UL=y
+CONFIG_TARGET_TX6=y
+CONFIG_TARGET_TX6UL_0011=y
+CONFIG_TX6_UBOOT=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FEC_MXC=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_LCD=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
+CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6UL U-Boot > "
u32 linkmap;
struct ahci_probe_ent *probe_ent = NULL;
-#if defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_ARCH_MX6)
if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
return 1;
#endif
config APBH_DMA
bool "Freescale MXS and i.MX6 APBH DMA support"
- default y
- depends on SOC_MX28 || SOC_MX6
+ depends on ARCH_MXS || ARCH_MX6
config APBH_DMA_BURST
bool "Enable DMA burst mode"
#if defined(CONFIG_SOC_MX23)
uint32_t *setreg = &apbh_regs->hw_apbh_ctrl0_set;
uint32_t offset = APBH_CTRL0_RESET_CHANNEL_OFFSET;
-#elif (defined(CONFIG_SOC_MX28) || defined(CONFIG_SOC_MX6))
+#elif (defined(CONFIG_SOC_MX28) || defined(CONFIG_ARCH_MX6))
uint32_t *setreg = &apbh_regs->hw_apbh_channel_ctrl_set;
uint32_t offset = APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET;
#endif
config DWAPB_GPIO
bool "DWAPB GPIO driver"
depends on DM && DM_GPIO
- default n
help
Support for the Designware APB GPIO driver.
config LPC32XX_GPIO
bool "LPC32XX GPIO driver"
depends on DM
- default n
help
Support for the LPC32XX GPIO driver.
config VYBRID_GPIO
bool "Vybrid GPIO driver"
depends on DM
- default n
help
Say yes here to support Vybrid vf610 GPIOs.
[1] = GPIO2_BASE_ADDR,
[2] = GPIO3_BASE_ADDR,
#if defined(CONFIG_SOC_MX25) || defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX51) || \
- defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)
+ defined(CONFIG_SOC_MX53) || defined(CONFIG_ARCH_MX6)
[3] = GPIO4_BASE_ADDR,
#endif
-#if defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX53) || defined(CONFIG_ARCH_MX6)
[4] = GPIO5_BASE_ADDR,
#ifndef CONFIG_SOX_MX6UL
[5] = GPIO6_BASE_ADDR,
#endif
#endif
-#if defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_SOC_MX53) || defined(CONFIG_ARCH_MX6)
#ifndef CONFIG_SOC_MX6UL
[6] = GPIO7_BASE_ADDR,
#endif
{ 1, (struct gpio_regs *)GPIO2_BASE_ADDR },
{ 2, (struct gpio_regs *)GPIO3_BASE_ADDR },
#if defined(CONFIG_SOC_MX25) || defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX51) || \
- defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)
+ defined(CONFIG_SOC_MX53) || defined(CONFIG_ARCH_MX6)
{ 3, (struct gpio_regs *)GPIO4_BASE_ADDR },
#endif
-#if defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX53) || defined(CONFIG_ARCH_MX6)
{ 4, (struct gpio_regs *)GPIO5_BASE_ADDR },
{ 5, (struct gpio_regs *)GPIO6_BASE_ADDR },
#endif
-#if defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_SOC_MX53) || defined(CONFIG_ARCH_MX6)
{ 6, (struct gpio_regs *)GPIO7_BASE_ADDR },
#endif
};
{ "gpio_mxc", &mxc_plat[1] },
{ "gpio_mxc", &mxc_plat[2] },
#if defined(CONFIG_SOC_MX25) || defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX51) || \
- defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)
+ defined(CONFIG_SOC_MX53) || defined(CONFIG_ARCH_MX6)
{ "gpio_mxc", &mxc_plat[3] },
#endif
-#if defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX53) || defined(CONFIG_ARCH_MX6)
{ "gpio_mxc", &mxc_plat[4] },
{ "gpio_mxc", &mxc_plat[5] },
#endif
-#if defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_SOC_MX53) || defined(CONFIG_ARCH_MX6)
{ "gpio_mxc", &mxc_plat[6] },
#endif
};
config MXC_OCOTP
bool "Freescale OCOTP support"
- depends on SOC_MX5 || SOC_MX6
+ depends on ARCH_MX5 || ARCH_MX6
config MXS_OCOTP
bool "Freescale OCOTP support"
- depends on SOC_MXS
+ depends on ARCH_MXS
config PCA9551_LED
bool "Enable PCA9551 LED driver"
err = !!(readl(®s->ctrl) & BM_CTRL_ERROR);
clear_error(regs);
+ enable_ocotp_clk(0);
if (err) {
printf("mxc_ocotp %s(): Access protect error\n", caller);
config FSL_USDHC
bool "Support USDHC"
- depends on FSL_ESDHC && SOC_MX6
+ depends on FSL_ESDHC && ARCH_MX6
config MXS_MMC
bool "i.MXS MMC/SDHC controller"
- depends on SOC_MXS || SOC_MX6
+ depends on ARCH_MXS || ARCH_MX6
select GENERIC_MMC
select BOUNCE_BUFFER
config NAND_MXS_NO_BBM_SWAP
bool "disable bad block mark swapping"
- depends on NAND_MXS && SOC_MX6
+ depends on NAND_MXS && ARCH_MX6
select SYS_NAND_USE_FLASH_BBT
endif
#define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512
-#if defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_ARCH_MX6)
#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2
#else
#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0
}
#endif
-struct nand_ecclayout fake_ecc_layout;
+static struct nand_ecclayout fake_ecc_layout;
static int chunk_data_size = MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
static int galois_field = 13;
mxs_dma_desc_append(channel, d);
-#ifndef CONFIG_SOC_MX6Q
+#ifndef CONFIG_ARCH_MX6
/*
* A DMA descriptor that waits for the command to end and the chip to
* become ready.
rtn:
mxs_nand_return_dma_descs(nand_info);
- return 0;
+ return ret;
}
/*
bool "Read FEC MAC address from fuses"
depends on FEC_MXC
-if FEC_MXC
-
-config FEC_MXC_PHYADDR
- int "FEC Ethernet PHY address"
- default 0
- depends on !FEC_MXC_MULTI
-
-endif
-
source "drivers/net/phy/Kconfig"
endif # NETDEVICES
if (readl(ð->ievent) & FEC_IEVENT_MII)
break;
printf("Read MDIO failed...\n");
- return -1;
+ return -ETIMEDOUT;
}
}
if (readl(ð->ievent) & FEC_IEVENT_MII)
break;
printf("Write MDIO failed...\n");
- return -1;
+ return -ETIMEDOUT;
}
}
static int miiphy_wait_aneg(struct eth_device *dev)
{
- uint32_t start;
+ ulong start;
int status;
struct fec_priv *fec = (struct fec_priv *)dev->priv;
struct ethernet_regs *eth = fec->bus->priv;
do {
if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
printf("%s: Autonegotiation timeout\n", dev->name);
- return -1;
+ return -ETIMEDOUT;
}
status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
if (status < 0) {
printf("%s: Autonegotiation failed. status: %d\n",
dev->name, status);
- return -1;
+ return status;
}
} while (!(status & BMSR_LSTATUS));
static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
{
uint32_t size;
- uint8_t *data;
+ void *data;
int i;
/*
*/
size = roundup(dsize, ARCH_DMA_MINALIGN);
for (i = 0; i < count; i++) {
- data = (uint8_t *)fec->rbd_base[i].data_pointer;
+ data = (void *)fec->rbd_base[i].data_pointer;
memset(data, 0, dsize);
- flush_dcache_range((uint32_t)data, (uint32_t)data + size);
+ flush_dcache_range((unsigned long)data,
+ (unsigned long)data + size);
fec->rbd_base[i].status = FEC_RBD_EMPTY;
fec->rbd_base[i].data_length = 0;
fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
fec->rbd_index = 0;
- flush_dcache_range((unsigned)fec->rbd_base,
- (unsigned)fec->rbd_base + size);
+ flush_dcache_range((unsigned long)fec->rbd_base,
+ (unsigned long)fec->rbd_base + size);
}
/**
*/
static void fec_tbd_init(struct fec_priv *fec)
{
- unsigned addr = (unsigned)fec->tbd_base;
+ unsigned long addr = (unsigned long)fec->tbd_base;
unsigned size = roundup(2 * sizeof(struct fec_bd),
ARCH_DMA_MINALIGN);
static int fec_set_hwaddr(struct eth_device *dev)
{
uchar *mac = dev->enetaddr;
- struct fec_priv *fec = (struct fec_priv *)dev->priv;
+ struct fec_priv *fec = dev->priv;
writel(0, &fec->eth->iaddr1);
writel(0, &fec->eth->iaddr2);
static int fec_init(struct eth_device *dev, bd_t* bd)
{
struct fec_priv *fec = dev->priv;
- uint32_t *mib_ptr = (uint32_t *)&fec->eth->rmon_t_drop;
- int i;
/* Initialize MAC address */
fec_set_hwaddr(dev);
writel(0x00000000, &fec->eth->gaddr1);
writel(0x00000000, &fec->eth->gaddr2);
-
- /* clear MIB RAM */
- for (i = 0; i <= 0xfc >> 2; i++)
- writel(0, &mib_ptr[i]);
-
+ /* Do not access reserved register for i.MX6UL */
+#ifndef CONFIG_SOC_MX6UL
/* FIFO receive start register */
writel(0x520, &fec->eth->r_fstart);
-
+#endif
/* size and address of each buffer */
writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);
*/
static void fec_halt(struct eth_device *dev)
{
- struct fec_priv *fec = (struct fec_priv *)dev->priv;
+ struct fec_priv *fec = dev->priv;
int counter = 1000;
/*
*/
if ((length > 1500) || (length <= 0)) {
printf("Payload (%d) too large\n", length);
- return -1;
+ return -EINVAL;
}
/*
* engine. We also flush the packet to RAM here to avoid cache trouble.
*/
#ifdef CONFIG_FEC_MXC_SWAP_PACKET
- swap_packet((uint32_t *)packet, length);
+ swap_packet(packet, length);
#endif
addr = (uint32_t)packet;
while (--timeout) {
if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))
break;
+ udelay(1);
}
if (!timeout) {
- ret = -EINVAL;
+ ret = -ETIMEDOUT;
goto out;
}
if (!(readw(&fec->tbd_base[fec->tbd_index].status) &
FEC_TBD_READY))
break;
+ udelay(1);
}
if (!timeout)
- ret = -EINVAL;
+ ret = -ETIMEDOUT;
out:
debug("fec_send: status 0x%x index %d ret %i\n",
*/
static int fec_recv(struct eth_device *dev)
{
- struct fec_priv *fec = (struct fec_priv *)dev->priv;
+ struct fec_priv *fec = dev->priv;
struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
unsigned long ievent;
int frame_length, len = 0;
{
unsigned int size;
int i;
- uint8_t *data;
+ void *data;
/* Allocate TX descriptors. */
size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
fec->rbd_base[i].status = FEC_RBD_EMPTY;
fec->rbd_base[i].data_length = 0;
/* Flush the buffer to memory. */
- flush_dcache_range((uint32_t)data, (uint32_t)data + size);
+ flush_dcache_range((unsigned long)data,
+ (unsigned long)data + size);
}
/* Mark the last RBD to close the ring. */
if (!bus)
return -ENOMEM;
#ifdef CONFIG_PHYLIB
- phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII);
+ phydev = phy_find_by_mask(bus, phy_id < 0 ? 0xff : (1 << phy_id),
+ PHY_INTERFACE_MODE_RGMII);
if (!phydev) {
free(bus);
return -ENOMEM;
#ifndef CONFIG_PHYLIB
int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
{
- struct fec_priv *fec = (struct fec_priv *)dev->priv;
+ struct fec_priv *fec = dev->priv;
fec->mii_postcall = cb;
return 0;
}
temperature sensors to permit warnings, speed throttling or even
automatic power-off when the temperature gets too high or low. Other
devices may be discrete but connected on a suitable bus.
+
+config IMX6_THERMAL
+ bool "Driver for i.MX6 thermal sensor"
+ depends on ARCH_MX6
+ help
+ Enable support for the thermal sensor inside the i.MX6 SoC.
+
int temperature;
unsigned int reg, n_meas;
const struct imx_thermal_plat *pdata = dev_get_platdata(dev);
- struct anatop_regs *anatop = (struct anatop_regs *)pdata->regs;
+ struct anatop_regs *anatop = pdata->regs;
struct thermal_data *priv = dev_get_priv(dev);
u32 fuse = priv->fuse;
int t1, n1;
writel(MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
/* setup measure freq */
- reg = readl(&anatop->tempsense1);
- reg &= ~TEMPSENSE1_MEASURE_FREQ;
- reg |= MEASURE_FREQ;
- writel(reg, &anatop->tempsense1);
+ writel(MEASURE_FREQ, &anatop->tempsense1);
/* start the measurement process */
writel(TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_clr);
writel(TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_set);
/* make sure that the latest temp is valid */
- while ((readl(&anatop->tempsense0) &
- TEMPSENSE0_FINISHED) == 0)
- udelay(10000);
+ const int max_loops = 30;
+ int loops = 0;
+
+ while (((reg = readl(&anatop->tempsense0)) & TEMPSENSE0_FINISHED) == 0) {
+ udelay(5);
+ if (++loops >= max_loops)
+ break;
+ }
+ if ((readl(&anatop->tempsense0) & TEMPSENSE0_FINISHED) == 0)
+ return 0;
/* read temperature count */
reg = readl(&anatop->tempsense0);
writel(TEMPSENSE0_FINISHED, &anatop->tempsense0_clr);
/* milli_Tmeas = c2 - Nmeas * c1 */
- temperature = (long)(c2 - n_meas * c1)/1000;
+ temperature = (long)(c2 - n_meas * c1) / 1000;
/* power down anatop thermal sensor */
writel(TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_set);
static int imx_thermal_probe(struct udevice *dev)
{
+ int ret;
unsigned int fuse = ~0;
-
const struct imx_thermal_plat *pdata = dev_get_platdata(dev);
struct thermal_data *priv = dev_get_priv(dev);
/* Read Temperature calibration data fuse */
- fuse_read(pdata->fuse_bank, pdata->fuse_word, &fuse);
+ if ((ret = fuse_read(pdata->fuse_bank, pdata->fuse_word, &fuse))) {
+ printf("Failed to read temp calib fuse: %d\n", ret);
+ return ret;
+ }
/* Check for valid fuse */
if (fuse == 0 || fuse == ~0) {
- printf("CPU: Thermal invalid data, fuse: 0x%x\n", fuse);
- return -EPERM;
+ static int first = 1;
+
+ if (first) {
+ printf("CPU: Thermal invalid data, fuse: %#10x\n", fuse);
+ first = 0;
+ }
+ return -EINVAL;
}
/* set critical cooling temp */
#define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
#define UCMD_RESET (1 << 1) /* controller reset */
-#if defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_ARCH_MX6)
static const unsigned phy_bases[] = {
USB_PHY0_BASE_ADDR,
USB_PHY1_BASE_ADDR,
static void usb_oc_config(int index)
{
-#if defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_ARCH_MX6)
struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
USB_OTHERREGS_OFFSET);
void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
#endif
-#if defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_ARCH_MX6)
setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
#elif defined(CONFIG_SOC_MX7)
setbits_le32(ctrl, UCTRL_OVER_CUR_DIS | UCTRL_PM);
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
enum usb_init_type type;
-#if defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_ARCH_MX6)
u32 controller_spacing = 0x200;
#elif defined(CONFIG_SOC_MX7)
u32 controller_spacing = 0x10000;
usb_power_config(index);
usb_oc_config(index);
-#if defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_ARCH_MX6)
usb_internal_phy_clock_gate(index, 1);
usb_phy_enable(index, ehci);
#endif
config VIDEO_VESA
bool "Enable VESA video driver support"
- default n
help
Turn on this option to enable a very simple driver which uses vesa
to discover the video mode and then provides a frame buffer for use
config VIDEO_LCD_ANX9804
bool "ANX9804 bridge chip"
- default n
---help---
Support for the ANX9804 bridge chip, which can take pixel data coming
from a parallel LCD interface and translate it on the fy into a DP
config VIDEO_LCD_SSD2828
bool "SSD2828 bridge chip"
- default n
---help---
Support for the SSD2828 bridge chip, which can take pixel data coming
from a parallel LCD interface and translate it on the fly into MIPI DSI
config VIDEO_LCD_HITACHI_TX18D42VM
bool "Hitachi tx18d42vm LVDS LCD panel support"
depends on VIDEO
- default n
---help---
Support for Hitachi tx18d42vm LVDS LCD panels, these panels have a
lcd controller which needs to be initialized over SPI, once that is
};
/* Globals */
-struct clk *g_ipu_clk;
-struct clk *g_ldb_clk;
+struct clk *g_ipu_clk = &ipu_clk;
+struct clk *g_ldb_clk = &ldb_clk;
struct clk *g_di_clk[2];
struct clk *g_pixel_clk[2];
unsigned char g_dc_di_assignment[10];
g_di_clk[1] = &di_clk[1];
g_di_clk[di]->rate = di_clk_val;
- g_ipu_clk = &ipu_clk;
debug("ipu_clk = %u\n", clk_get_rate(g_ipu_clk));
-
- g_ldb_clk = &ldb_clk;
debug("ldb_clk = %u\n", clk_get_rate(g_ldb_clk));
ret = clk_enable(g_ipu_clk);
if (sig.Vsync_pol)
di_gen |= DI_GEN_POLARITY_3;
- if (!sig.clk_pol)
+ if (sig.clk_pol)
di_gen |= DI_GEN_POL_CLK;
/* Set the clock to stop at counter 6. */
config HW_WATCHDOG
bool "Generic SoC specific watchdog support"
- depends on !SOC_MX6
+ depends on !ARCH_MX6
config IMX_WATCHDOG
bool "Freescale i.MX watchdog support"
- depends on SOC_MX31 || SOC_MX35 || SOC_MX5 || SOC_MX6 || SOC_VF610 || SOC_LS102XA
+ depends on SOC_MX31 || SOC_MX35 || ARCH_MX5 || ARCH_MX6 || SOC_VF610 || SOC_LS102XA
#ifndef __MX6_COMMON_H
#define __MX6_COMMON_H
-#ifndef CONFIG_MX6UL
+#ifndef CONFIG_SOC_MX6UL
#define CONFIG_ARM_ERRATA_743622
#define CONFIG_ARM_ERRATA_751472
#define CONFIG_ARM_ERRATA_794072
#define CONFIG_BOARD_POSTCLK_INIT
#define CONFIG_MXC_GPT_HCLK
-#define CONFIG_SYS_NO_FLASH
-
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
#include <asm/imx-common/gpio.h>
#define CONFIG_REVISION_TAG
/* Boot options */
-#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6UL))
+#if (defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6UL))
#define CONFIG_LOADADDR 0x82000000
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0x87800000
/* Filesystems and image support */
#define CONFIG_OF_LIBFDT
-#define CONFIG_CMD_BOOTZ
#define CONFIG_SUPPORT_RAW_INITRD
#define CONFIG_CMD_FS_GENERIC
#define CONFIG_DOS_PARTITION
#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
#define CONFIG_SYS_CACHELINE_SIZE 32
-#ifdef CONFIG_FEC_MXC_PHYADDR
+#ifdef CONFIG_TX28_S
+#define CONFIG_FEC_MXC_PHYADDR 0
#define IMX_FEC_BASE MXS_ENET0_BASE
#endif
"mtdids=" MTDIDS_DEFAULT "\0" \
"mtdparts=" MTDPARTS_DEFAULT "\0"
#else
-#define CONFIG_SYS_CPU_CLK_STR xstr(CONFIG_SYS_MPU_CLK)
+#define CONFIG_SYS_CPU_CLK_STR xstr(CONFIG_SYS_CPU_CLK)
#define CONFIG_EXTRA_ENV_SETTINGS \
"autostart=no\0" \
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_CMD_GPIO
#ifndef CONFIG_TX6_UBOOT_MFG
/* LCD Logo and Splash screen support */
#ifdef CONFIG_LCD
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
+#ifndef CONFIG_SOC_MX6UL
#define CONFIG_VIDEO_IPUV3
#define CONFIG_IPUV3_CLK (CONFIG_SYS_SDRAM_CLK * 1000000 / 2)
+#endif
#define CONFIG_LCD_LOGO
#define LCD_BPP LCD_COLOR32
#define CONFIG_CMD_BMP
* Memory configuration options
*/
#define CONFIG_NR_DRAM_BANKS 0x1 /* # of SDRAM banks */
+#ifndef CONFIG_SOC_MX6UL
#define PHYS_SDRAM_1 0x10000000 /* Base address of bank 1 */
-#ifdef CONFIG_SYS_SDRAM_BUS_WIDTH
-#define PHYS_SDRAM_1_WIDTH CONFIG_SYS_SDRAM_BUS_WIDTH
-#elif defined(CONFIG_SYS_SDRAM_BUS_WIDTH_32)
-#define PHYS_SDRAM_1_WIDTH 32
+#define CONFIG_SYS_MPU_CLK 792
+#else
+#define PHYS_SDRAM_1 0x80000000 /* Base address of bank 1 */
+#define CONFIG_SYS_MPU_CLK 528
+#endif
+#ifndef CONFIG_SYS_SDRAM_BUS_WIDTH
+#if defined(CONFIG_SYS_SDRAM_BUS_WIDTH_32)
+#define CONFIG_SYS_SDRAM_BUS_WIDTH 32
#elif defined(CONFIG_SYS_SDRAM_BUS_WIDTH_16)
-#define PHYS_SDRAM_1_WIDTH 16
+#define CONFIG_SYS_SDRAM_BUS_WIDTH 16
#else
-#define PHYS_SDRAM_1_WIDTH 64
+#define CONFIG_SYS_SDRAM_BUS_WIDTH 64
#endif
-#define PHYS_SDRAM_1_SIZE (SZ_512M / 32 * PHYS_SDRAM_1_WIDTH)
+#endif /* CONFIG_SYS_SDRAM_BUS_WIDTH */
+#define PHYS_SDRAM_1_SIZE (SZ_512M / 32 * CONFIG_SYS_SDRAM_BUS_WIDTH)
#ifdef CONFIG_SOC_MX6Q
#define CONFIG_SYS_SDRAM_CLK 528
#else
#if defined(CONFIG_SOC_MX6Q)
#elif defined(CONFIG_SOC_MX6DL)
#elif defined(CONFIG_SOC_MX6S)
+#elif defined(CONFIG_SOC_MX6UL)
#else
#error Unsupported i.MX6 processor variant
#endif
"mtdids=" MTDIDS_DEFAULT "\0" \
"mtdparts=" MTDPARTS_DEFAULT "\0"
#else
+#define CONFIG_SYS_CPU_CLK_STR xstr(CONFIG_SYS_MPU_CLK)
+
#define CONFIG_EXTRA_ENV_SETTINGS \
"autostart=no\0" \
"baseboard=stk5-v3\0" \
";dhcp\0" \
"bootm_cmd=bootm ${loadaddr} - ${fdtaddr}\0" \
"boot_mode=" CONFIG_SYS_DEFAULT_BOOT_MODE "\0" \
- "cpu_clk=800\0" \
+ "cpu_clk=" CONFIG_SYS_CPU_CLK_STR "\0" \
"default_bootargs=setenv bootargs " CONFIG_BOOTARGS \
" ${append_bootargs}\0" \
EMMC_BOOT_PART_STR \
/* This is required for the FEC driver to work with cache enabled */
#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
+#ifndef CONFIG_SOC_MX6UL
+#define CONFIG_FEC_MXC_PHYADDR 0
#define IMX_FEC_BASE ENET_BASE_ADDR
+#endif
#define CONFIG_FEC_XCV_TYPE RMII
#endif
#endif
#endif /* CONFIG_TX6_REV */
/* autodetect which PMIC is present to derive TX6_REV */
+#ifndef CONFIG_SOC_MX6UL
#define CONFIG_LTC3676 /* TX6_REV == 1 */
+#endif
#define CONFIG_RN5T567 /* TX6_REV == 3 */
-#endif /* CONFIG_CMD_I2C */
+#endif /* CONFIG_HARD_I2C */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_JRSTARTR_JR0 0x00000001
struct jr_regs {
-#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_ARCH_MX6)
u32 irba_l;
u32 irba_h;
#else
u32 irsa;
u32 rsvd3;
u32 irja;
-#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_ARCH_MX6)
u32 orba_l;
u32 orba_h;
#else
* related information
*/
struct sg_entry {
-#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_ARCH_MX6)
uint32_t addr_lo; /* Memory Address - lo */
uint16_t addr_hi; /* Memory Address of start of buffer - hi */
uint16_t reserved_zero;
#define SG_ENTRY_OFFSET_SHIFT 0
};
-#ifdef CONFIG_SOC_MX6
+#ifdef CONFIG_ARCH_MX6
/* CAAM Job Ring 0 Registers */
/* Secure Memory Partition Owner register */
#define SMCSJR_PO (3 << 6)
projects / karo-tx-uboot.git / commitdiff