]> git.kernelconcepts.de Git - karo-tx-uboot.git/commitdiff
arm: mvebu: drivers/ddr: Move Armada XP DDR init code into new directory
authorStefan Roese <sr@denx.de>
Wed, 25 Mar 2015 11:51:18 +0000 (12:51 +0100)
committerLothar Waßmann <LW@KARO-electronics.de>
Wed, 9 Sep 2015 11:49:03 +0000 (13:49 +0200)
With the upcoming addition of the Armada 38x DDR support, which is not
compatible to the Armada XP DDR init code, we need to introduce a new
directory infrastructure. To support multiple Marvell DDR controller.

This will be the new structure:

     drivers/ddr/marvell/axp
     Supporting Armada XP (AXP) devices (and perhaps Armada 370)

     drivers/ddr/marvell/a38x
     Supporting Armada 38x devices (and perhaps Armada 39x)

Signed-off-by: Stefan Roese <sr@denx.de>
26 files changed:
arch/arm/mach-mvebu/include/mach/cpu.h
arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h
drivers/ddr/marvell/axp/Makefile [moved from drivers/ddr/mvebu/Makefile with 100% similarity]
drivers/ddr/marvell/axp/ddr3_axp.h [moved from drivers/ddr/mvebu/ddr3_axp.h with 100% similarity]
drivers/ddr/marvell/axp/ddr3_axp_config.h [moved from drivers/ddr/mvebu/ddr3_axp_config.h with 100% similarity]
drivers/ddr/marvell/axp/ddr3_axp_mc_static.h [moved from drivers/ddr/mvebu/ddr3_axp_mc_static.h with 100% similarity]
drivers/ddr/marvell/axp/ddr3_axp_training_static.h [moved from drivers/ddr/mvebu/ddr3_axp_training_static.h with 100% similarity]
drivers/ddr/marvell/axp/ddr3_axp_vars.h [moved from drivers/ddr/mvebu/ddr3_axp_vars.h with 100% similarity]
drivers/ddr/marvell/axp/ddr3_dfs.c [moved from drivers/ddr/mvebu/ddr3_dfs.c with 100% similarity]
drivers/ddr/marvell/axp/ddr3_dqs.c [moved from drivers/ddr/mvebu/ddr3_dqs.c with 100% similarity]
drivers/ddr/marvell/axp/ddr3_hw_training.c [moved from drivers/ddr/mvebu/ddr3_hw_training.c with 100% similarity]
drivers/ddr/marvell/axp/ddr3_hw_training.h [moved from drivers/ddr/mvebu/ddr3_hw_training.h with 100% similarity]
drivers/ddr/marvell/axp/ddr3_init.c [moved from drivers/ddr/mvebu/ddr3_init.c with 100% similarity]
drivers/ddr/marvell/axp/ddr3_init.h [moved from drivers/ddr/mvebu/ddr3_init.h with 100% similarity]
drivers/ddr/marvell/axp/ddr3_patterns_64bit.h [moved from drivers/ddr/mvebu/ddr3_patterns_64bit.h with 100% similarity]
drivers/ddr/marvell/axp/ddr3_pbs.c [moved from drivers/ddr/mvebu/ddr3_pbs.c with 100% similarity]
drivers/ddr/marvell/axp/ddr3_read_leveling.c [moved from drivers/ddr/mvebu/ddr3_read_leveling.c with 100% similarity]
drivers/ddr/marvell/axp/ddr3_sdram.c [moved from drivers/ddr/mvebu/ddr3_sdram.c with 100% similarity]
drivers/ddr/marvell/axp/ddr3_spd.c [moved from drivers/ddr/mvebu/ddr3_spd.c with 100% similarity]
drivers/ddr/marvell/axp/ddr3_write_leveling.c [moved from drivers/ddr/mvebu/ddr3_write_leveling.c with 100% similarity]
drivers/ddr/marvell/axp/xor.c [moved from drivers/ddr/mvebu/xor.c with 100% similarity]
drivers/ddr/marvell/axp/xor.h [moved from drivers/ddr/mvebu/xor.h with 100% similarity]
drivers/ddr/marvell/axp/xor_regs.h [moved from drivers/ddr/mvebu/xor_regs.h with 100% similarity]
include/configs/db-mv784mp-gp.h
include/configs/maxbcm.h
scripts/Makefile.spl

index 4bdb6331e113a149fdc1241b843e5a9d838499b7..8bcdef689f5fcf2dbda583a618b56b2a1f2cbb30 100644 (file)
@@ -125,7 +125,7 @@ int serdes_phy_config(void);
 /*
  * DDR3 init / training code ported from Marvell bin_hdr. Now
  * available in mainline U-Boot in:
- * drivers/ddr/mvebu/
+ * drivers/ddr/marvell
  */
 int ddr3_init(void);
 #endif /* __ASSEMBLY__ */
index e5aa1b06edbf4f5c64b70f24048126c6da3a2d09..e10574eac64375d9ca3f5453481132163bfcf03d 100644 (file)
@@ -7,7 +7,7 @@
 #ifndef __HIGHSPEED_ENV_SPEC_H
 #define __HIGHSPEED_ENV_SPEC_H
 
-#include "../../../drivers/ddr/mvebu/ddr3_hw_training.h"
+#include "../../../drivers/ddr/marvell/axp/ddr3_hw_training.h"
 
 typedef enum {
        SERDES_UNIT_UNCONNECTED = 0x0,
index aeddbf93d6ece63d6f08a6732950d325f2333956..41e6fdcb526b01aea465c433490fa6e440e71f12 100644 (file)
 #define CONFIG_SYS_SPI_U_BOOT_OFFS     0x20000
 
 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
-#define CONFIG_SYS_MVEBU_DDR
+#define CONFIG_SYS_MVEBU_DDR_AXP
 #define CONFIG_SPD_EEPROM              0x4e
 
 #endif /* _CONFIG_DB_MV7846MP_GP_H */
index 4826044857d1529880dbb931fca832205c32f3a5..0fb117f9d3651a59af64c74366cfa94502566625 100644 (file)
 #define CONFIG_SYS_SPI_U_BOOT_OFFS     0x20000
 
 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
-#define CONFIG_SYS_MVEBU_DDR
+#define CONFIG_SYS_MVEBU_DDR_AXP
 #define CONFIG_DDR_FIXED_SIZE          (1 << 20)       /* 1GiB */
 
 #endif /* _CONFIG_DB_MV7846MP_GP_H */
index 525f9a238c64f49f3eb3c3a915749a5adf79f392..6ed9333c20c5c5af4acc5e2be3043a86f8b8c050 100644 (file)
@@ -60,7 +60,7 @@ libs-$(CONFIG_SPL_I2C_SUPPORT) += drivers/i2c/
 libs-$(CONFIG_SPL_GPIO_SUPPORT) += drivers/gpio/
 libs-$(CONFIG_SPL_MMC_SUPPORT) += drivers/mmc/
 libs-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += drivers/ddr/fsl/
-libs-$(CONFIG_SYS_MVEBU_DDR) += drivers/ddr/mvebu/
+libs-$(CONFIG_SYS_MVEBU_DDR_AXP) += drivers/ddr/marvell/axp/
 libs-$(CONFIG_SPL_SERIAL_SUPPORT) += drivers/serial/
 libs-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += drivers/mtd/spi/
 libs-$(CONFIG_SPL_SPI_SUPPORT) += drivers/spi/