Merge branch 'master' of git://git.denx.de/u-boot-arc
authorTom Rini <trini@ti.com>
Tue, 2 Sep 2014 20:37:17 +0000 (16:37 -0400)
committerTom Rini <trini@ti.com>
Tue, 2 Sep 2014 20:37:17 +0000 (16:37 -0400)
701 files changed:
Kconfig
MAKEALL
Makefile
README
arch/arm/Kconfig
arch/arm/cpu/arm1136/u-boot-spl.lds
arch/arm/cpu/arm920t/ep93xx/u-boot.lds [deleted file]
arch/arm/cpu/arm926ejs/davinci/Kconfig [new file with mode: 0644]
arch/arm/cpu/arm926ejs/kirkwood/Kconfig [new file with mode: 0644]
arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
arch/arm/cpu/arm926ejs/nomadik/Kconfig [new file with mode: 0644]
arch/arm/cpu/arm926ejs/orion5x/Kconfig [new file with mode: 0644]
arch/arm/cpu/arm926ejs/versatile/Kconfig [new file with mode: 0644]
arch/arm/cpu/armv7/Makefile
arch/arm/cpu/armv7/am33xx/u-boot-spl.lds
arch/arm/cpu/armv7/bcm281xx/Makefile
arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c
arch/arm/cpu/armv7/bcm281xx/clk-eth.c [new file with mode: 0644]
arch/arm/cpu/armv7/bcmcygnus/Makefile [new file with mode: 0644]
arch/arm/cpu/armv7/bcmcygnus/reset.c [new file with mode: 0644]
arch/arm/cpu/armv7/bcmnsp/Makefile [new file with mode: 0644]
arch/arm/cpu/armv7/bcmnsp/reset.c [new file with mode: 0644]
arch/arm/cpu/armv7/exynos/Kconfig [new file with mode: 0644]
arch/arm/cpu/armv7/highbank/Kconfig [moved from board/highbank/Kconfig with 90% similarity]
arch/arm/cpu/armv7/iproc-common/Makefile [new file with mode: 0644]
arch/arm/cpu/armv7/iproc-common/armpll.c [new file with mode: 0644]
arch/arm/cpu/armv7/iproc-common/hwinit-common.c [new file with mode: 0644]
arch/arm/cpu/armv7/iproc-common/timer.c [new file with mode: 0644]
arch/arm/cpu/armv7/keystone/Kconfig [new file with mode: 0644]
arch/arm/cpu/armv7/keystone/clock-k2e.c
arch/arm/cpu/armv7/keystone/clock-k2hk.c
arch/arm/cpu/armv7/keystone/clock.c
arch/arm/cpu/armv7/mx6/Makefile
arch/arm/cpu/armv7/mx6/clock.c
arch/arm/cpu/armv7/mx6/ddr.c
arch/arm/cpu/armv7/mx6/mp.c [new file with mode: 0644]
arch/arm/cpu/armv7/mx6/soc.c
arch/arm/cpu/armv7/omap-common/emif-common.c
arch/arm/cpu/armv7/omap-common/hwinit-common.c
arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
arch/arm/cpu/armv7/omap3/Kconfig [new file with mode: 0644]
arch/arm/cpu/armv7/omap4/Kconfig [new file with mode: 0644]
arch/arm/cpu/armv7/omap5/Kconfig [new file with mode: 0644]
arch/arm/cpu/armv7/omap5/hw_data.c
arch/arm/cpu/armv7/omap5/sdram.c
arch/arm/cpu/armv7/rmobile/Kconfig [new file with mode: 0644]
arch/arm/cpu/armv7/socfpga/clock_manager.c
arch/arm/cpu/armv7/socfpga/config.mk
arch/arm/cpu/armv7/socfpga/misc.c
arch/arm/cpu/armv7/socfpga/spl.c
arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
arch/arm/cpu/armv7/sunxi/Makefile
arch/arm/cpu/armv7/sunxi/board.c
arch/arm/cpu/armv7/sunxi/clock_sun4i.c
arch/arm/cpu/armv7/sunxi/dram.c
arch/arm/cpu/armv7/sunxi/psci.S [new file with mode: 0644]
arch/arm/cpu/armv7/tegra-common/Kconfig [new file with mode: 0644]
arch/arm/cpu/armv7/tegra114/Kconfig [new file with mode: 0644]
arch/arm/cpu/armv7/tegra124/Kconfig [new file with mode: 0644]
arch/arm/cpu/armv7/tegra20/Kconfig [new file with mode: 0644]
arch/arm/cpu/armv7/tegra30/Kconfig [new file with mode: 0644]
arch/arm/cpu/armv7/zynq/Kconfig [new file with mode: 0644]
arch/arm/cpu/armv7/zynq/spl.c
arch/arm/cpu/armv7/zynq/u-boot-spl.lds
arch/arm/cpu/at91-common/u-boot-spl.lds
arch/arm/cpu/tegra-common/Makefile
arch/arm/cpu/tegra-common/ap.c
arch/arm/cpu/tegra-common/board.c
arch/arm/cpu/tegra-common/vpr.c [new file with mode: 0644]
arch/arm/dts/Makefile
arch/arm/dts/tegra30-colibri.dts [new file with mode: 0644]
arch/arm/imx-common/cpu.c
arch/arm/imx-common/sata.c
arch/arm/include/asm/arch-bcm281xx/sysmap.h
arch/arm/include/asm/arch-bcmcygnus/configs.h [new file with mode: 0644]
arch/arm/include/asm/arch-bcmnsp/configs.h [new file with mode: 0644]
arch/arm/include/asm/arch-imx/cpu.h
arch/arm/include/asm/arch-keystone/clock-k2e.h
arch/arm/include/asm/arch-keystone/clock-k2hk.h
arch/arm/include/asm/arch-keystone/clock.h
arch/arm/include/asm/arch-keystone/hardware.h
arch/arm/include/asm/arch-mx5/crm_regs.h
arch/arm/include/asm/arch-mx6/clock.h
arch/arm/include/asm/arch-mx6/crm_regs.h
arch/arm/include/asm/arch-mx6/imx-regs.h
arch/arm/include/asm/arch-mx6/iomux.h
arch/arm/include/asm/arch-mx6/mx6-ddr.h
arch/arm/include/asm/arch-mx6/mx6-pins.h
arch/arm/include/asm/arch-mx6/mx6sx-ddr.h [new file with mode: 0644]
arch/arm/include/asm/arch-mx6/mx6sx_pins.h [new file with mode: 0644]
arch/arm/include/asm/arch-mx6/sys_proto.h
arch/arm/include/asm/arch-omap5/mem.h
arch/arm/include/asm/arch-socfpga/clock_manager.h
arch/arm/include/asm/arch-socfpga/scan_manager.h
arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
arch/arm/include/asm/arch-sunxi/clock_sun4i.h
arch/arm/include/asm/arch-sunxi/dram.h
arch/arm/include/asm/arch-tegra/ap.h
arch/arm/include/asm/arch-tegra114/tegra.h
arch/arm/include/asm/arch-tegra124/mc.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra124/tegra.h
arch/arm/include/asm/arch-tegra20/tegra.h
arch/arm/include/asm/arch-tegra30/tegra.h
arch/arm/include/asm/arch-vf610/crm_regs.h
arch/arm/include/asm/arch-vf610/imx-regs.h
arch/arm/include/asm/arch-vf610/iomux-vf610.h
arch/arm/include/asm/arch-zynq/spl.h [deleted file]
arch/arm/include/asm/arch-zynq/sys_proto.h
arch/arm/include/asm/imx-common/iomux-v3.h
arch/arm/include/asm/io.h
arch/arm/include/asm/iproc-common/armpll.h [new file with mode: 0644]
arch/arm/include/asm/iproc-common/configs.h [new file with mode: 0644]
arch/arm/include/asm/iproc-common/sysmap.h [new file with mode: 0644]
arch/arm/include/asm/iproc-common/timer.h [new file with mode: 0644]
arch/arm/include/asm/mach-types.h
arch/arm/include/asm/spl.h
arch/arm/lib/bootm.c
arch/arm/lib/cache-cp15.c
arch/arm/lib/vectors.S
arch/nios2/cpu/cpu.c
arch/nios2/cpu/interrupts.c
arch/nios2/cpu/sysid.c
arch/nios2/cpu/u-boot.lds
arch/nios2/include/asm/nios2.h [moved from include/nios2.h with 95% similarity]
arch/powerpc/cpu/mpc5xxx/Makefile
arch/powerpc/cpu/mpc5xxx/cache.c [new file with mode: 0644]
arch/sandbox/dts/sandbox.dts
board/8dtech/eco5pk/Kconfig
board/Barix/ipam390/Kconfig
board/Barix/ipam390/u-boot-spl-ipam390.lds
board/LaCie/edminiv2/Kconfig
board/LaCie/net2big_v2/Kconfig
board/LaCie/netspace_v2/Kconfig
board/LaCie/wireless_space/Kconfig
board/Marvell/dreamplug/Kconfig
board/Marvell/guruplug/Kconfig
board/Marvell/mv88f6281gtw_ge/Kconfig
board/Marvell/openrd/Kconfig
board/Marvell/rd6281a/Kconfig
board/Marvell/sheevaplug/Kconfig
board/Seagate/dockstar/Kconfig
board/Seagate/goflexhome/Kconfig
board/ait/cam_enc_4xx/Kconfig
board/ait/cam_enc_4xx/u-boot-spl.lds
board/altera/common/epled.c [deleted file]
board/altera/nios2-generic/Makefile
board/altera/nios2-generic/custom_fpga.h
board/altera/nios2-generic/nios2-generic.c
board/altera/nios2-generic/text_base.S [deleted file]
board/altera/nios2-generic/u-boot.lds [deleted file]
board/altera/socfpga/Makefile
board/altera/socfpga/socfpga_cyclone5.c
board/aristainetos/Kconfig [new file with mode: 0644]
board/aristainetos/MAINTAINERS [new file with mode: 0644]
board/aristainetos/Makefile [new file with mode: 0644]
board/aristainetos/aristainetos.c [new file with mode: 0644]
board/aristainetos/aristainetos.cfg [new file with mode: 0644]
board/aristainetos/clocks.cfg [new file with mode: 0644]
board/aristainetos/ddr-setup.cfg [new file with mode: 0644]
board/aristainetos/mt41j128M.cfg [new file with mode: 0644]
board/armltd/versatile/Kconfig [deleted file]
board/armltd/vexpress/MAINTAINERS
board/atmark-techno/armadillo-800eva/Kconfig
board/avionic-design/medcom-wide/Kconfig
board/avionic-design/plutux/Kconfig
board/avionic-design/tec-ng/Kconfig
board/avionic-design/tec/Kconfig
board/boundary/nitrogen6x/nitrogen6x.c
board/broadcom/bcm28155_w1d/MAINTAINERS [new file with mode: 0644]
board/broadcom/bcm958300k/Kconfig [new file with mode: 0644]
board/broadcom/bcm958300k/MAINTAINERS [new file with mode: 0644]
board/broadcom/bcm958622hr/Kconfig [new file with mode: 0644]
board/broadcom/bcm958622hr/MAINTAINERS [new file with mode: 0644]
board/broadcom/bcm_ep/Makefile [new file with mode: 0644]
board/broadcom/bcm_ep/board.c [new file with mode: 0644]
board/buffalo/lsxl/Kconfig
board/cirrus/edb93xx/u-boot.lds
board/cloudengines/pogo_e02/Kconfig
board/comelit/dig297/Kconfig
board/compal/paz00/Kconfig
board/compulab/cm_t35/Kconfig
board/compulab/cm_t54/Kconfig
board/compulab/cm_t54/cm_t54.c
board/compulab/trimslice/Kconfig
board/corscience/tricorder/Kconfig
board/d-link/dns325/Kconfig
board/davinci/da8xxevm/Kconfig
board/davinci/da8xxevm/u-boot-spl-da850evm.lds
board/davinci/da8xxevm/u-boot-spl-hawk.lds
board/davinci/dm355evm/Kconfig
board/davinci/dm355leopard/Kconfig
board/davinci/dm365evm/Kconfig
board/davinci/dm6467evm/Kconfig
board/davinci/dvevm/Kconfig
board/davinci/ea20/Kconfig
board/davinci/schmoogie/Kconfig
board/davinci/sffsdr/Kconfig
board/davinci/sonata/Kconfig
board/embest/mx6boards/mx6boards.c
board/enbw/enbw_cmc/Kconfig
board/freescale/mx31pdk/MAINTAINERS
board/freescale/mx6sabresd/mx6sabresd.c
board/freescale/mx6slevk/mx6slevk.c
board/freescale/mx6sxsabresd/Kconfig [new file with mode: 0644]
board/freescale/mx6sxsabresd/MAINTAINERS [new file with mode: 0644]
board/freescale/mx6sxsabresd/Makefile [new file with mode: 0644]
board/freescale/mx6sxsabresd/imximage.cfg [new file with mode: 0644]
board/freescale/mx6sxsabresd/mx6sxsabresd.c [new file with mode: 0644]
board/gateworks/gw_ventana/eeprom.c
board/gateworks/gw_ventana/gsc.c
board/gateworks/gw_ventana/gw_ventana.c
board/gateworks/gw_ventana/ventana_eeprom.h
board/gumstix/duovero/Kconfig
board/htkw/mcx/Kconfig
board/iomega/iconnect/Kconfig
board/isee/igep00x0/Kconfig
board/karo/tk71/Kconfig
board/keymile/km_arm/Kconfig
board/kmc/kzm9g/Kconfig
board/logicpd/am3517evm/Kconfig
board/logicpd/omap3som/Kconfig
board/logicpd/zoom1/Kconfig
board/matrix_vision/mvblx/Kconfig
board/nokia/rx51/Kconfig
board/nvidia/beaver/Kconfig
board/nvidia/cardhu/Kconfig
board/nvidia/dalmore/Kconfig
board/nvidia/harmony/Kconfig
board/nvidia/jetson-tk1/Kconfig
board/nvidia/seaboard/Kconfig
board/nvidia/venice2/Kconfig
board/nvidia/venice2/as3722_init.h
board/nvidia/ventana/Kconfig
board/nvidia/whistler/Kconfig
board/omicron/calimain/Kconfig
board/overo/Kconfig
board/pandora/Kconfig
board/prodrive/alpr/nand.c
board/raidsonic/ib62x0/Kconfig
board/renesas/alt/Kconfig
board/renesas/koelsch/Kconfig
board/renesas/lager/Kconfig
board/samsung/arndale/Kconfig
board/samsung/arndale/arndale.c
board/samsung/common/exynos-uboot-spl.lds
board/samsung/origen/Kconfig
board/samsung/smdk5250/Kconfig
board/samsung/smdk5420/Kconfig
board/samsung/smdkv310/Kconfig
board/samsung/trats/Kconfig
board/samsung/trats2/Kconfig
board/samsung/universal_c210/Kconfig
board/socrates/nand.c
board/solidrun/hummingboard/hummingboard.c
board/st/nhk8815/Kconfig
board/sunxi/Kconfig
board/sunxi/MAINTAINERS
board/sunxi/Makefile
board/sunxi/ahci.c [new file with mode: 0644]
board/sunxi/dram_a10_olinuxino_l.c [new file with mode: 0644]
board/sunxi/dram_a10s_olinuxino_m.c [new file with mode: 0644]
board/sunxi/dram_a13_olinuxino.c [new file with mode: 0644]
board/sunxi/dram_bananapi.c [new file with mode: 0644]
board/sunxi/dram_linksprite_pcduino3.c [new file with mode: 0644]
board/sunxi/dram_sun4i_360_1024_iow16.c [new file with mode: 0644]
board/sunxi/dram_sun4i_360_1024_iow8.c [new file with mode: 0644]
board/sunxi/dram_sun4i_360_512.c [new file with mode: 0644]
board/sunxi/dram_sun4i_384_1024_iow8.c [new file with mode: 0644]
board/sunxi/dram_sun7i_384_1024_iow16.c [new file with mode: 0644]
board/sunxi/dram_sun7i_384_512_busw16_iow16.c [new file with mode: 0644]
board/technexion/tao3530/Kconfig
board/technexion/twister/Kconfig
board/teejet/mt_ventoux/Kconfig
board/ti/am335x/Kconfig
board/ti/am335x/board.c
board/ti/am335x/mux.c
board/ti/am3517crane/Kconfig
board/ti/am43xx/board.c
board/ti/am43xx/mux.c
board/ti/beagle/Kconfig
board/ti/dra7xx/Kconfig
board/ti/dra7xx/evm.c
board/ti/dra7xx/mux_data.h
board/ti/evm/Kconfig
board/ti/ks2_evm/Kconfig
board/ti/ks2_evm/board_k2e.c
board/ti/ks2_evm/board_k2hk.c
board/ti/omap5_uevm/Kconfig
board/ti/panda/Kconfig
board/ti/sdp3430/Kconfig
board/ti/sdp4430/Kconfig
board/timll/devkit8000/Kconfig
board/toradex/colibri_t20_iris/Kconfig
board/toradex/colibri_t30/Kconfig [new file with mode: 0644]
board/toradex/colibri_t30/MAINTAINERS [new file with mode: 0644]
board/toradex/colibri_t30/Makefile [new file with mode: 0644]
board/toradex/colibri_t30/colibri_t30.c [new file with mode: 0644]
board/toradex/colibri_t30/pinmux-config-colibri_t30.h [new file with mode: 0644]
board/tqc/tqm8272/nand.c
board/tqc/tqma6/Kconfig [new file with mode: 0644]
board/tqc/tqma6/MAINTAINERS [new file with mode: 0644]
board/tqc/tqma6/Makefile [new file with mode: 0644]
board/tqc/tqma6/README [new file with mode: 0644]
board/tqc/tqma6/clocks.cfg [new file with mode: 0644]
board/tqc/tqma6/tqma6.c [new file with mode: 0644]
board/tqc/tqma6/tqma6_bb.h [new file with mode: 0644]
board/tqc/tqma6/tqma6_mba6.c [new file with mode: 0644]
board/tqc/tqma6/tqma6q.cfg [new file with mode: 0644]
board/tqc/tqma6/tqma6s.cfg [new file with mode: 0644]
board/vpac270/u-boot-spl.lds
board/xilinx/zynq/Kconfig [deleted file]
board/xilinx/zynq/MAINTAINERS
common/Makefile
common/board_f.c
common/cmd_bootm.c
common/cmd_gpio.c
common/cmd_ubi.c
common/cmd_ubifs.c
common/image-fit.c
common/image.c
common/usb.c
common/usb_hub.c
configs/A10-OLinuXino-Lime_defconfig [new file with mode: 0644]
configs/A10s-OLinuXino-M_defconfig [new file with mode: 0644]
configs/A13-OLinuXinoM_defconfig
configs/A13-OLinuXino_defconfig [new file with mode: 0644]
configs/A20-OLinuXino_MICRO_defconfig [new file with mode: 0644]
configs/Auxtek-T004_defconfig [new file with mode: 0644]
configs/Bananapi_defconfig [new file with mode: 0644]
configs/Cubieboard2_FEL_defconfig
configs/Cubieboard2_defconfig
configs/Cubieboard_defconfig
configs/Cubietruck_FEL_defconfig
configs/Cubietruck_defconfig
configs/Linksprite_pcDuino3_defconfig [new file with mode: 0644]
configs/Mele_A1000G_defconfig [new file with mode: 0644]
configs/Mele_A1000_defconfig [new file with mode: 0644]
configs/Mini-X-1Gb_defconfig [new file with mode: 0644]
configs/Mini-X_defconfig [new file with mode: 0644]
configs/alt_defconfig
configs/am335x_evm_defconfig
configs/am335x_evm_nor_defconfig
configs/am335x_evm_norboot_defconfig
configs/am335x_evm_spiboot_defconfig
configs/am335x_evm_uart1_defconfig [deleted file]
configs/am335x_evm_uart2_defconfig [deleted file]
configs/am335x_evm_uart3_defconfig [deleted file]
configs/am335x_evm_uart4_defconfig [deleted file]
configs/am335x_evm_uart5_defconfig [deleted file]
configs/am335x_evm_usbspl_defconfig
configs/am3517_crane_defconfig
configs/am3517_evm_defconfig
configs/aristainetos_defconfig [new file with mode: 0644]
configs/armadillo-800eva_defconfig
configs/arndale_defconfig
configs/ba10_tv_box_defconfig [new file with mode: 0644]
configs/bcm28155_w1d_defconfig [new file with mode: 0644]
configs/bcm958300k_defconfig [new file with mode: 0644]
configs/bcm958622hr_defconfig [new file with mode: 0644]
configs/beaver_defconfig
configs/calimain_defconfig
configs/cam_enc_4xx_defconfig
configs/cardhu_defconfig
configs/cm_t35_defconfig
configs/cm_t54_defconfig
configs/colibri_t20_iris_defconfig
configs/colibri_t30_defconfig [new file with mode: 0644]
configs/d2net_v2_defconfig
configs/da830evm_defconfig
configs/da850_am18xxevm_defconfig
configs/da850evm_defconfig
configs/da850evm_direct_nor_defconfig
configs/dalmore_defconfig
configs/davinci_dm355evm_defconfig
configs/davinci_dm355leopard_defconfig
configs/davinci_dm365evm_defconfig
configs/davinci_dm6467Tevm_defconfig
configs/davinci_dm6467evm_defconfig
configs/davinci_dvevm_defconfig
configs/davinci_schmoogie_defconfig
configs/davinci_sffsdr_defconfig
configs/davinci_sonata_defconfig
configs/devkit8000_defconfig
configs/dig297_defconfig
configs/dns325_defconfig
configs/dockstar_defconfig
configs/dra7xx_evm_defconfig
configs/dra7xx_evm_qspiboot_defconfig
configs/dra7xx_evm_uart3_defconfig
configs/dreamplug_defconfig
configs/duovero_defconfig
configs/ea20_defconfig
configs/eco5pk_defconfig
configs/edminiv2_defconfig
configs/enbw_cmc_defconfig
configs/goflexhome_defconfig
configs/guruplug_defconfig
configs/harmony_defconfig
configs/hawkboard_defconfig
configs/hawkboard_uart_defconfig
configs/highbank_defconfig
configs/i12-tvbox_defconfig [new file with mode: 0644]
configs/ib62x0_defconfig
configs/iconnect_defconfig
configs/igep0020_defconfig
configs/igep0020_nand_defconfig
configs/igep0030_defconfig
configs/igep0030_nand_defconfig
configs/igep0032_defconfig
configs/inetspace_v2_defconfig
configs/ipam390_defconfig
configs/jetson-tk1_defconfig
configs/k2e_evm_defconfig
configs/k2hk_evm_defconfig
configs/km_kirkwood_128m16_defconfig
configs/km_kirkwood_defconfig
configs/km_kirkwood_pci_defconfig
configs/kmcoge5un_defconfig
configs/kmnusa_defconfig
configs/kmsugp1_defconfig
configs/kmsuv31_defconfig
configs/koelsch_defconfig
configs/kzm9g_defconfig
configs/lager_defconfig
configs/lschlv2_defconfig
configs/lsxhl_defconfig
configs/mcx_defconfig
configs/medcom-wide_defconfig
configs/mgcoge3un_defconfig
configs/mt_ventoux_defconfig
configs/mv88f6281gtw_ge_defconfig
configs/mx6sxsabresd_defconfig [new file with mode: 0644]
configs/net2big_v2_defconfig
configs/netspace_lite_v2_defconfig
configs/netspace_max_v2_defconfig
configs/netspace_mini_v2_defconfig
configs/netspace_v2_defconfig
configs/nhk8815_defconfig
configs/nhk8815_onenand_defconfig
configs/nokia_rx51_defconfig
configs/omap3_beagle_defconfig
configs/omap3_evm_defconfig
configs/omap3_evm_quick_mmc_defconfig
configs/omap3_evm_quick_nand_defconfig
configs/omap3_ha_defconfig
configs/omap3_logic_defconfig
configs/omap3_mvblx_defconfig
configs/omap3_overo_defconfig
configs/omap3_pandora_defconfig
configs/omap3_sdp3430_defconfig
configs/omap3_zoom1_defconfig
configs/omap4_panda_defconfig
configs/omap4_sdp4430_defconfig
configs/omap5_uevm_defconfig
configs/openrd_base_defconfig
configs/openrd_client_defconfig
configs/openrd_ultimate_defconfig
configs/origen_defconfig
configs/paz00_defconfig
configs/peach-pit_defconfig
configs/plutux_defconfig
configs/pogo_e02_defconfig
configs/portl2_defconfig
configs/qt840a_defconfig [new file with mode: 0644]
configs/r7-tv-dongle_defconfig
configs/rd6281a_defconfig
configs/s5pc210_universal_defconfig
configs/seaboard_defconfig
configs/sheevaplug_defconfig
configs/smdk5250_defconfig
configs/smdk5420_defconfig
configs/smdkv310_defconfig
configs/snow_defconfig
configs/tao3530_defconfig
configs/tec-ng_defconfig
configs/tec_defconfig
configs/tk71_defconfig
configs/tqma6q_mba6_mmc_defconfig [new file with mode: 0644]
configs/tqma6q_mba6_spi_defconfig [new file with mode: 0644]
configs/tqma6s_mba6_mmc_defconfig [new file with mode: 0644]
configs/tqma6s_mba6_spi_defconfig [new file with mode: 0644]
configs/trats2_defconfig
configs/trats_defconfig
configs/tricorder_defconfig
configs/tricorder_flash_defconfig
configs/trimslice_defconfig
configs/twister_defconfig
configs/venice2_defconfig
configs/ventana_defconfig
configs/versatileab_defconfig
configs/versatilepb_defconfig
configs/versatileqemu_defconfig
configs/whistler_defconfig
configs/wireless_space_defconfig
configs/zynq_microzed_defconfig
configs/zynq_zc70x_defconfig
configs/zynq_zc770_xm010_defconfig
configs/zynq_zc770_xm012_defconfig
configs/zynq_zc770_xm013_defconfig
configs/zynq_zed_defconfig
doc/README.cfi
doc/README.kconfig
drivers/Makefile
drivers/block/ahci.c
drivers/mmc/socfpga_dw_mmc.c
drivers/mtd/mtdconcat.c
drivers/mtd/mtdcore.c
drivers/mtd/mtdcore.h [new file with mode: 0644]
drivers/mtd/mtdpart.c
drivers/mtd/nand/fsl_elbc_nand.c
drivers/mtd/nand/fsl_ifc_nand.c
drivers/mtd/nand/fsl_upm.c
drivers/mtd/nand/kirkwood_nand.c
drivers/mtd/nand/mpc5121_nfc.c
drivers/mtd/nand/mxc_nand.c
drivers/mtd/nand/nand_base.c
drivers/mtd/nand/nand_bbt.c
drivers/mtd/nand/nand_ids.c
drivers/mtd/nand/nand_util.c
drivers/mtd/nand/ndfc.c
drivers/mtd/onenand/onenand_base.c
drivers/mtd/onenand/onenand_bbt.c
drivers/mtd/onenand/samsung.c
drivers/mtd/spi/sf_internal.h
drivers/mtd/spi/sf_probe.c
drivers/mtd/ubi/Makefile
drivers/mtd/ubi/attach.c [new file with mode: 0644]
drivers/mtd/ubi/build.c
drivers/mtd/ubi/crc32.c
drivers/mtd/ubi/crc32table.h
drivers/mtd/ubi/debug.c
drivers/mtd/ubi/debug.h
drivers/mtd/ubi/eba.c
drivers/mtd/ubi/fastmap.c [new file with mode: 0644]
drivers/mtd/ubi/io.c
drivers/mtd/ubi/kapi.c
drivers/mtd/ubi/misc.c
drivers/mtd/ubi/scan.c [deleted file]
drivers/mtd/ubi/scan.h [deleted file]
drivers/mtd/ubi/ubi-media.h
drivers/mtd/ubi/ubi.h
drivers/mtd/ubi/upd.c
drivers/mtd/ubi/vmt.c
drivers/mtd/ubi/vtbl.c
drivers/mtd/ubi/wl.c
drivers/net/Makefile
drivers/net/bcm-sf2-eth-gmac.c [new file with mode: 0644]
drivers/net/bcm-sf2-eth-gmac.h [new file with mode: 0644]
drivers/net/bcm-sf2-eth.c [new file with mode: 0644]
drivers/net/bcm-sf2-eth.h [new file with mode: 0644]
drivers/net/cpsw.c
drivers/pci/pcie_imx.c
drivers/power/pmic/pmic_pfuze100.c
drivers/pwm/Makefile [new file with mode: 0644]
drivers/pwm/pwm-imx-util.c [new file with mode: 0644]
drivers/pwm/pwm-imx-util.h [new file with mode: 0644]
drivers/pwm/pwm-imx.c [new file with mode: 0644]
drivers/serial/altera_jtag_uart.c
drivers/serial/altera_uart.c
drivers/serial/opencores_yanu.c
drivers/usb/gadget/ether.c
drivers/usb/gadget/storage_common.c
drivers/usb/host/Makefile
drivers/usb/host/ehci-sunxi.c [new file with mode: 0644]
drivers/usb/musb-new/linux-compat.h
drivers/video/exynos_dp.c
drivers/video/exynos_mipi_dsi.c
fs/ubifs/budget.c
fs/ubifs/debug.c
fs/ubifs/debug.h
fs/ubifs/io.c
fs/ubifs/key.h
fs/ubifs/log.c
fs/ubifs/lprops.c
fs/ubifs/lpt.c
fs/ubifs/lpt_commit.c
fs/ubifs/master.c
fs/ubifs/misc.h
fs/ubifs/orphan.c
fs/ubifs/recovery.c
fs/ubifs/replay.c
fs/ubifs/sb.c
fs/ubifs/scan.c
fs/ubifs/super.c
fs/ubifs/tnc.c
fs/ubifs/tnc_misc.c
fs/ubifs/ubifs-media.h
fs/ubifs/ubifs.c
fs/ubifs/ubifs.h
fs/yaffs2/ydirectenv.h
include/ahci.h
include/asm-generic/gpio.h
include/bootm.h
include/configs/alt.h
include/configs/am335x_evm.h
include/configs/am3517_crane.h
include/configs/am3517_evm.h
include/configs/am43xx_evm.h
include/configs/aristainetos.h [new file with mode: 0644]
include/configs/armadillo-800eva.h
include/configs/arndale.h
include/configs/bcm_ep_board.h [new file with mode: 0644]
include/configs/beaver.h
include/configs/cm_t35.h
include/configs/cm_t54.h
include/configs/colibri_t30.h [new file with mode: 0644]
include/configs/devkit8000.h
include/configs/dig297.h
include/configs/dns325.h
include/configs/dockstar.h
include/configs/dra7xx_evm.h
include/configs/dreamplug.h
include/configs/edminiv2.h
include/configs/embestmx6boards.h
include/configs/goflexhome.h
include/configs/guruplug.h
include/configs/gw_ventana.h
include/configs/ib62x0.h
include/configs/iconnect.h
include/configs/imx6_spl.h
include/configs/jetson-tk1.h
include/configs/km/km_arm.h
include/configs/km_kirkwood.h
include/configs/koelsch.h
include/configs/kzm9g.h
include/configs/lacie_kw.h
include/configs/lager.h
include/configs/lsxl.h
include/configs/m53evk.h
include/configs/mcx.h
include/configs/mv88f6281gtw_ge.h
include/configs/mx31pdk.h
include/configs/mx6_common.h
include/configs/mx6sxsabresd.h [new file with mode: 0644]
include/configs/mxs.h
include/configs/nhk8815.h
include/configs/nios2-generic.h
include/configs/nokia_rx51.h
include/configs/omap3_evm_common.h
include/configs/omap3_logic.h
include/configs/omap3_mvblx.h
include/configs/omap3_pandora.h
include/configs/omap3_sdp3430.h
include/configs/openrd.h
include/configs/pcm051.h
include/configs/pogo_e02.h
include/configs/rd6281a.h
include/configs/s5p_goni.h
include/configs/sheevaplug.h
include/configs/socfpga_cyclone5.h
include/configs/sun4i.h
include/configs/sun5i.h
include/configs/sun7i.h
include/configs/sunxi-common.h
include/configs/tam3517-common.h
include/configs/tao3530.h
include/configs/tegra-common-usb-gadget.h [moved from include/configs/tegra-common-ums.h with 57% similarity]
include/configs/tegra-common.h
include/configs/ti_armv7_common.h
include/configs/ti_omap3_common.h
include/configs/ti_omap4_common.h
include/configs/ti_omap5_common.h
include/configs/tk71.h
include/configs/tqma6.h [new file with mode: 0644]
include/configs/tricorder.h
include/configs/tseries.h
include/configs/venice2.h
include/configs/vexpress_aemv8a.h
include/configs/wireless_space.h
include/configs/zynq-common.h
include/image.h
include/linux/compat.h
include/linux/err.h
include/linux/list_sort.h [new file with mode: 0644]
include/linux/mtd/bbm.h
include/linux/mtd/concat.h
include/linux/mtd/flashchip.h [new file with mode: 0644]
include/linux/mtd/mtd.h
include/linux/mtd/nand.h
include/linux/mtd/partitions.h
include/linux/mtd/ubi.h
include/linux/rbtree.h
include/linux/rbtree_augmented.h [new file with mode: 0644]
include/linux/usb/gadget.h
include/mtd/mtd-abi.h
include/mtd/ubi-user.h
include/netdev.h
include/nios2-io.h [deleted file]
include/nios2-yanu.h [deleted file]
include/ubi_uboot.h
include/usb/lin_gadget_compat.h
lib/Makefile
lib/linux_compat.c [new file with mode: 0644]
lib/list_sort.c [new file with mode: 0644]
lib/rbtree.c
scripts/multiconfig.sh
scripts/setlocalversion
test/image/test-fit.py
tools/buildman/control.py
tools/genboardscfg.py
tools/patman/gitutil.py

diff --git a/Kconfig b/Kconfig
index 1a38645..cbb691e 100644 (file)
--- a/Kconfig
+++ b/Kconfig
@@ -14,6 +14,52 @@ config KCONFIG_OBJDIR
 
 menu "General setup"
 
+config LOCALVERSION
+       string "Local version - append to U-Boot release"
+       depends on !SPL_BUILD
+       help
+         Append an extra string to the end of your U-Boot version.
+         This will show up on your boot log, for example.
+         The string you set here will be appended after the contents of
+         any files with a filename matching localversion* in your
+         object and source tree, in that order.  Your total string can
+         be a maximum of 64 characters.
+
+config LOCALVERSION_AUTO
+       bool "Automatically append version information to the version string"
+       depends on !SPL_BUILD
+       default y
+       help
+         This will try to automatically determine if the current tree is a
+         release tree by looking for git tags that belong to the current
+         top of tree revision.
+
+         A string of the format -gxxxxxxxx will be added to the localversion
+         if a git-based tree is found.  The string generated by this will be
+         appended after any matching localversion* files, and after the value
+         set in CONFIG_LOCALVERSION.
+
+         (The actual string used here is the first eight characters produced
+         by running the command:
+
+           $ git rev-parse --verify HEAD
+
+         which is done within the script "scripts/setlocalversion".)
+
+config CC_OPTIMIZE_FOR_SIZE
+       bool "Optimize for size"
+       depends on !SPL_BUILD
+       default y
+       help
+         Enabling this option will pass "-Os" instead of "-O2" to gcc
+         resulting in a smaller U-Boot image.
+
+         This option is enabled by default for U-Boot.
+
+endmenu                # General setup
+
+menu "Boot images"
+
 config SPL_BUILD
        bool
        depends on $KCONFIG_OBJDIR="spl" || $KCONFIG_OBJDIR="tpl"
@@ -54,6 +100,6 @@ config SYS_EXTRA_OPTIONS
          configuration to Kconfig. Since this option will be removed sometime,
          new boards should not use this option.
 
-endmenu                # General setup
+endmenu                # Boot images
 
 source "arch/Kconfig"
diff --git a/MAKEALL b/MAKEALL
index 392ea8d..7c16319 100755 (executable)
--- a/MAKEALL
+++ b/MAKEALL
@@ -171,13 +171,10 @@ GNU_MAKE=$(scripts/show-gnu-make) || {
 # echo "Remaining arguments:"
 # for arg do echo '--> '"\`$arg'" ; done
 
-if [ ! -r boards.cfg ]; then
-       echo "Could not find boards.cfg"
-       tools/genboardscfg.py || {
-               echo "Failed to generate boards.cfg" >&2
-               exit 1
-       }
-fi
+tools/genboardscfg.py || {
+       echo "Failed to generate boards.cfg" >&2
+       exit 1
+}
 
 FILTER="\$1 !~ /^#/"
 [ "$opt_a" ] && FILTER="${FILTER} && $opt_a"
index 0fea5c2..9646859 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -529,7 +529,11 @@ else
 include/config/auto.conf: ;
 endif # $(dot-config)
 
-KBUILD_CFLAGS += -Os #-fomit-frame-pointer
+ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE
+KBUILD_CFLAGS  += -Os
+else
+KBUILD_CFLAGS  += -O2
+endif
 
 ifdef BUILD_TAG
 KBUILD_CFLAGS += -DBUILD_TAG='"$(BUILD_TAG)"'
diff --git a/README b/README
index 14d6b22..0a0f528 100644 (file)
--- a/README
+++ b/README
@@ -959,6 +959,7 @@ The following options need to be configured:
                CONFIG_CMD_BMP          * BMP support
                CONFIG_CMD_BSP          * Board specific commands
                CONFIG_CMD_BOOTD          bootd
+               CONFIG_CMD_BOOTI        * ARM64 Linux kernel Image support
                CONFIG_CMD_CACHE        * icache, dcache
                CONFIG_CMD_CLK          * clock command support
                CONFIG_CMD_CONSOLE        coninfo
@@ -1378,6 +1379,10 @@ The following options need to be configured:
                        CONFIG_SH_ETHER_CACHE_WRITEBACK
                        If this option is set, the driver enables cache flush.
 
+- PWM Support:
+               CONFIG_PWM_IMX
+               Support for PWM modul on the imx6.
+
 - TPM Support:
                CONFIG_TPM
                Support TPM devices.
@@ -2949,6 +2954,17 @@ CBFS (Coreboot Filesystem) support
                memories can be connected with a given cs line.
                currently Xilinx Zynq qspi support these type of connections.
 
+               CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
+               enable the W#/Vpp signal to disable writing to the status
+               register on ST MICRON flashes like the N25Q128.
+               The status register write enable/disable bit, combined with
+               the W#/VPP signal provides hardware data protection for the
+               device as follows: When the enable/disable bit is set to 1,
+               and the W#/VPP signal is driven LOW, the status register
+               nonvolatile bits become read-only and the WRITE STATUS REGISTER
+               operation will not execute. The only way to exit this
+               hardware-protected mode is to drive W#/VPP HIGH.
+
 - SystemACE Support:
                CONFIG_SYSTEMACE
 
@@ -3338,6 +3354,9 @@ FIT uImage format:
                Adds the MTD partitioning infrastructure from the Linux
                kernel. Needed for UBI support.
 
+               CONFIG_MTD_NAND_VERIFY_WRITE
+               verify if the written data is correct reread.
+
 - UBI support
                CONFIG_CMD_UBI
 
@@ -3351,6 +3370,64 @@ FIT uImage format:
                Make the verbose messages from UBI stop printing.  This leaves
                warnings and errors enabled.
 
+
+               CONFIG_MTD_UBI_WL_THRESHOLD
+               This parameter defines the maximum difference between the highest
+               erase counter value and the lowest erase counter value of eraseblocks
+               of UBI devices. When this threshold is exceeded, UBI starts performing
+               wear leveling by means of moving data from eraseblock with low erase
+               counter to eraseblocks with high erase counter.
+
+               The default value should be OK for SLC NAND flashes, NOR flashes and
+               other flashes which have eraseblock life-cycle 100000 or more.
+               However, in case of MLC NAND flashes which typically have eraseblock
+               life-cycle less than 10000, the threshold should be lessened (e.g.,
+               to 128 or 256, although it does not have to be power of 2).
+
+               default: 4096
+               
+               CONFIG_MTD_UBI_BEB_LIMIT
+               This option specifies the maximum bad physical eraseblocks UBI
+               expects on the MTD device (per 1024 eraseblocks). If the
+               underlying flash does not admit of bad eraseblocks (e.g. NOR
+               flash), this value is ignored.
+
+               NAND datasheets often specify the minimum and maximum NVM
+               (Number of Valid Blocks) for the flashes' endurance lifetime.
+               The maximum expected bad eraseblocks per 1024 eraseblocks
+               then can be calculated as "1024 * (1 - MinNVB / MaxNVB)",
+               which gives 20 for most NANDs (MaxNVB is basically the total
+               count of eraseblocks on the chip).
+
+               To put it differently, if this value is 20, UBI will try to
+               reserve about 1.9% of physical eraseblocks for bad blocks
+               handling. And that will be 1.9% of eraseblocks on the entire
+               NAND chip, not just the MTD partition UBI attaches. This means
+               that if you have, say, a NAND flash chip admits maximum 40 bad
+               eraseblocks, and it is split on two MTD partitions of the same
+               size, UBI will reserve 40 eraseblocks when attaching a
+               partition.
+
+               default: 20
+
+               CONFIG_MTD_UBI_FASTMAP
+               Fastmap is a mechanism which allows attaching an UBI device
+               in nearly constant time. Instead of scanning the whole MTD device it
+               only has to locate a checkpoint (called fastmap) on the device.
+               The on-flash fastmap contains all information needed to attach
+               the device. Using fastmap makes only sense on large devices where
+               attaching by scanning takes long. UBI will not automatically install
+               a fastmap on old images, but you can set the UBI parameter
+               CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT to 1 if you want so. Please note
+               that fastmap-enabled images are still usable with UBI implementations
+               without fastmap support. On typical flash devices the whole fastmap
+               fits into one PEB. UBI will reserve PEBs to hold two fastmaps.
+
+               CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT
+               Set this parameter to enable fastmap automatically on images
+               without a fastmap.
+               default: 0
+
 - UBIFS support
                CONFIG_CMD_UBIFS
 
index e97f94d..22f0f09 100644 (file)
@@ -131,107 +131,13 @@ config TARGET_TAURUS
 config TARGET_STAMP9G20
        bool "Support stamp9g20"
 
-config TARGET_CAM_ENC_4XX
-       bool "Support cam_enc_4xx"
+config ARCH_DAVINCI
+       bool "TI DaVinci"
+       help
+         Support for TI's DaVinci platform.
 
-config TARGET_IPAM390
-       bool "Support ipam390"
-
-config TARGET_DA830EVM
-       bool "Support da830evm"
-
-config TARGET_DA850EVM
-       bool "Support da850evm"
-
-config TARGET_HAWKBOARD
-       bool "Support hawkboard"
-
-config TARGET_DAVINCI_DM355EVM
-       bool "Support davinci_dm355evm"
-
-config TARGET_DAVINCI_DM355LEOPARD
-       bool "Support davinci_dm355leopard"
-
-config TARGET_DAVINCI_DM365EVM
-       bool "Support davinci_dm365evm"
-
-config TARGET_DAVINCI_DM6467EVM
-       bool "Support davinci_dm6467evm"
-
-config TARGET_DAVINCI_DVEVM
-       bool "Support davinci_dvevm"
-
-config TARGET_EA20
-       bool "Support ea20"
-
-config TARGET_DAVINCI_SCHMOOGIE
-       bool "Support davinci_schmoogie"
-
-config TARGET_DAVINCI_SFFSDR
-       bool "Support davinci_sffsdr"
-
-config TARGET_DAVINCI_SONATA
-       bool "Support davinci_sonata"
-
-config TARGET_ENBW_CMC
-       bool "Support enbw_cmc"
-
-config TARGET_CALIMAIN
-       bool "Support calimain"
-
-config TARGET_LSXL
-       bool "Support lsxl"
-
-config TARGET_POGO_E02
-       bool "Support pogo_e02"
-
-config TARGET_DNS325
-       bool "Support dns325"
-
-config TARGET_ICONNECT
-       bool "Support iconnect"
-
-config TARGET_TK71
-       bool "Support tk71"
-
-config TARGET_KM_KIRKWOOD
-       bool "Support km_kirkwood"
-
-config TARGET_NET2BIG_V2
-       bool "Support net2big_v2"
-
-config TARGET_NETSPACE_V2
-       bool "Support netspace_v2"
-
-config TARGET_WIRELESS_SPACE
-       bool "Support wireless_space"
-
-config TARGET_DREAMPLUG
-       bool "Support dreamplug"
-
-config TARGET_GURUPLUG
-       bool "Support guruplug"
-
-config TARGET_MV88F6281GTW_GE
-       bool "Support mv88f6281gtw_ge"
-
-config TARGET_OPENRD
-       bool "Support openrd"
-
-config TARGET_RD6281A
-       bool "Support rd6281a"
-
-config TARGET_SHEEVAPLUG
-       bool "Support sheevaplug"
-
-config TARGET_IB62X0
-       bool "Support ib62x0"
-
-config TARGET_DOCKSTAR
-       bool "Support dockstar"
-
-config TARGET_GOFLEXHOME
-       bool "Support goflexhome"
+config KIRKWOOD
+       bool "Marvell Kirkwood"
 
 config TARGET_DEVKIT3250
        bool "Support devkit3250"
@@ -284,11 +190,11 @@ config TARGET_SANSA_FUZE_PLUS
 config TARGET_SC_SPS_1
        bool "Support sc_sps_1"
 
-config TARGET_NHK8815
-       bool "Support nhk8815"
+config ARCH_NOMADIK
+       bool "ST-Ericsson Nomadik"
 
-config TARGET_EDMINIV2
-       bool "Support edminiv2"
+config ORION5X
+       bool "Marvell Orion"
 
 config TARGET_DKB
        bool "Support dkb"
@@ -308,14 +214,8 @@ config TARGET_SPEAR600
 config TARGET_X600
        bool "Support x600"
 
-config TARGET_VERSATILEAB
-       bool "Support versatileab"
-
-config TARGET_VERSATILEPB
-       bool "Support versatilepb"
-
-config TARGET_VERSATILEQEMU
-       bool "Support versatileqemu"
+config ARCH_VERSATILE
+       bool "ARM Ltd. Versatile family"
 
 config TARGET_INTEGRATORCP_CM1136
        bool "Support integratorcp_cm1136"
@@ -425,44 +325,20 @@ config TARGET_SAMA5D3XEK
 config TARGET_BCM28155_AP
        bool "Support bcm28155_ap"
 
-config TARGET_ARNDALE
-       bool "Support arndale"
-
-config TARGET_ORIGEN
-       bool "Support origen"
-
-config TARGET_SMDK5250
-       bool "Support smdk5250"
-
-config TARGET_SNOW
-       bool "Support snow"
-
-config TARGET_PEACH_PIT
-       bool "Support peach-pit"
-
-config TARGET_SMDK5420
-       bool "Support smdk5420"
-
-config TARGET_SMDKV310
-       bool "Support smdkv310"
+config TARGET_BCM958300K
+       bool "Support bcm958300k"
 
-config TARGET_TRATS
-       bool "Support trats"
+config TARGET_BCM958622HR
+       bool "Support bcm958622hr"
 
-config TARGET_TRATS2
-       bool "Support trats2"
+config ARCH_EXYNOS
+       bool "Samsung EXYNOS"
 
-config TARGET_S5PC210_UNIVERSAL
-       bool "Support s5pc210_universal"
+config ARCH_HIGHBANK
+       bool "Calxeda Highbank"
 
-config TARGET_HIGHBANK
-       bool "Support highbank"
-
-config TARGET_K2E_EVM
-       bool "Support k2e_evm"
-
-config TARGET_K2HK_EVM
-       bool "Support k2hk_evm"
+config ARCH_KEYSTONE
+       bool "TI Keystone"
 
 config TARGET_M53EVK
        bool "Support m53evk"
@@ -509,6 +385,9 @@ config TARGET_CGTQMX6EVAL
 config TARGET_EMBESTMX6BOARDS
        bool "Support embestmx6boards"
 
+config TARGET_ARISTAINETOS
+       bool "Support aristainetos"
+
 config TARGET_MX6QARM2
        bool "Support mx6qarm2"
 
@@ -521,113 +400,29 @@ config TARGET_MX6SABRESD
 config TARGET_MX6SLEVK
        bool "Support mx6slevk"
 
+config TARGET_MX6SXSABRESD
+       bool "Support mx6sxsabresd"
+
 config TARGET_GW_VENTANA
        bool "Support gw_ventana"
 
 config TARGET_HUMMINGBOARD
        bool "Support hummingboard"
 
-config TARGET_OMAP3_OVERO
-       bool "Support omap3_overo"
-
-config TARGET_OMAP3_PANDORA
-       bool "Support omap3_pandora"
-
-config TARGET_ECO5PK
-       bool "Support eco5pk"
-
-config TARGET_DIG297
-       bool "Support dig297"
-
-config TARGET_CM_T35
-       bool "Support cm_t35"
-
-config TARGET_TRICORDER
-       bool "Support tricorder"
-
-config TARGET_MCX
-       bool "Support mcx"
-
-config TARGET_OMAP3_IGEP00X0
-       bool "Support omap3_igep00x0"
-
-config TARGET_AM3517_EVM
-       bool "Support am3517_evm"
-
-config TARGET_OMAP3_LOGIC
-       bool "Support omap3_logic"
+config TARGET_TQMA6
+       bool "TQ Systems TQMa6 board"
 
-config TARGET_OMAP3_ZOOM1
-       bool "Support omap3_zoom1"
+config OMAP34XX
+       bool "OMAP34XX SoC"
 
-config TARGET_OMAP3_MVBLX
-       bool "Support omap3_mvblx"
+config OMAP44XX
+       bool "OMAP44XX SoC"
 
-config TARGET_NOKIA_RX51
-       bool "Support nokia_rx51"
+config OMAP54XX
+       bool "OMAP54XX SoC"
 
-config TARGET_TAO3530
-       bool "Support tao3530"
-
-config TARGET_TWISTER
-       bool "Support twister"
-
-config TARGET_MT_VENTOUX
-       bool "Support mt_ventoux"
-
-config TARGET_AM3517_CRANE
-       bool "Support am3517_crane"
-
-config TARGET_OMAP3_BEAGLE
-       bool "Support omap3_beagle"
-
-config TARGET_OMAP3_EVM
-       bool "Support omap3_evm"
-
-config TARGET_OMAP3_EVM_QUICK_MMC
-       bool "Support omap3_evm_quick_mmc"
-
-config TARGET_OMAP3_EVM_QUICK_NAND
-       bool "Support omap3_evm_quick_nand"
-
-config TARGET_OMAP3_SDP3430
-       bool "Support omap3_sdp3430"
-
-config TARGET_DEVKIT8000
-       bool "Support devkit8000"
-
-config TARGET_DUOVERO
-       bool "Support duovero"
-
-config TARGET_OMAP4_PANDA
-       bool "Support omap4_panda"
-
-config TARGET_OMAP4_SDP4430
-       bool "Support omap4_sdp4430"
-
-config TARGET_CM_T54
-       bool "Support cm_t54"
-
-config TARGET_DRA7XX_EVM
-       bool "Support dra7xx_evm"
-
-config TARGET_OMAP5_UEVM
-       bool "Support omap5_uevm"
-
-config TARGET_ARMADILLO_800EVA
-       bool "Support armadillo-800eva"
-
-config TARGET_KZM9G
-       bool "Support kzm9g"
-
-config TARGET_ALT
-       bool "Support alt"
-
-config TARGET_KOELSCH
-       bool "Support koelsch"
-
-config TARGET_LAGER
-       bool "Support lager"
+config RMOBILE
+       bool "Renesas ARM SoCs"
 
 config TARGET_S5P_GONI
        bool "Support s5p_goni"
@@ -656,65 +451,12 @@ config TARGET_U8500_HREF
 config TARGET_VF610TWR
        bool "Support vf610twr"
 
-config TARGET_ZYNQ_MICROZED
-       bool "Support zynq_microzed"
-
-config TARGET_ZYNQ_ZC70X
-       bool "Support zynq_zc70x"
-
-config TARGET_ZYNQ_ZC770
-       bool "Support zynq_zc770"
-
-config TARGET_ZYNQ_ZED
-       bool "Support zynq_zed"
-
-config TARGET_MEDCOM_WIDE
-       bool "Support medcom-wide"
-
-config TARGET_PLUTUX
-       bool "Support plutux"
-
-config TARGET_TEC
-       bool "Support tec"
+config ZYNQ
+       bool "Xilinx Zynq Platform"
 
-config TARGET_PAZ00
-       bool "Support paz00"
-
-config TARGET_TRIMSLICE
-       bool "Support trimslice"
-
-config TARGET_HARMONY
-       bool "Support harmony"
-
-config TARGET_SEABOARD
-       bool "Support seaboard"
-
-config TARGET_VENTANA
-       bool "Support ventana"
-
-config TARGET_WHISTLER
-       bool "Support whistler"
-
-config TARGET_COLIBRI_T20_IRIS
-       bool "Support colibri_t20_iris"
-
-config TARGET_TEC_NG
-       bool "Support tec-ng"
-
-config TARGET_BEAVER
-       bool "Support beaver"
-
-config TARGET_CARDHU
-       bool "Support cardhu"
-
-config TARGET_DALMORE
-       bool "Support dalmore"
-
-config TARGET_JETSON_TK1
-       bool "Support jetson-tk1"
-
-config TARGET_VENICE2
-       bool "Support venice2"
+config TEGRA
+       bool "NVIDIA Tegra"
+       select SPL
 
 config TARGET_VEXPRESS_AEMV8A
        bool "Support vexpress_aemv8a"
@@ -769,37 +511,49 @@ config TARGET_JORNADA
 
 endchoice
 
-source "board/8dtech/eco5pk/Kconfig"
-source "board/Barix/ipam390/Kconfig"
+source "arch/arm/cpu/arm926ejs/davinci/Kconfig"
+
+source "arch/arm/cpu/armv7/exynos/Kconfig"
+
+source "arch/arm/cpu/armv7/highbank/Kconfig"
+
+source "arch/arm/cpu/armv7/keystone/Kconfig"
+
+source "arch/arm/cpu/arm926ejs/kirkwood/Kconfig"
+
+source "arch/arm/cpu/arm926ejs/nomadik/Kconfig"
+
+source "arch/arm/cpu/armv7/omap3/Kconfig"
+
+source "arch/arm/cpu/armv7/omap4/Kconfig"
+
+source "arch/arm/cpu/armv7/omap5/Kconfig"
+
+source "arch/arm/cpu/arm926ejs/orion5x/Kconfig"
+
+source "arch/arm/cpu/armv7/rmobile/Kconfig"
+
+source "arch/arm/cpu/armv7/tegra-common/Kconfig"
+
+source "arch/arm/cpu/arm926ejs/versatile/Kconfig"
+
+source "arch/arm/cpu/armv7/zynq/Kconfig"
+
+source "board/aristainetos/Kconfig"
 source "board/BuR/kwb/Kconfig"
 source "board/BuR/tseries/Kconfig"
 source "board/BuS/eb_cpux9k2/Kconfig"
 source "board/BuS/vl_ma2sc/Kconfig"
 source "board/CarMediaLab/flea3/Kconfig"
-source "board/LaCie/edminiv2/Kconfig"
-source "board/LaCie/net2big_v2/Kconfig"
-source "board/LaCie/netspace_v2/Kconfig"
-source "board/LaCie/wireless_space/Kconfig"
 source "board/Marvell/aspenite/Kconfig"
 source "board/Marvell/dkb/Kconfig"
-source "board/Marvell/dreamplug/Kconfig"
 source "board/Marvell/gplugd/Kconfig"
-source "board/Marvell/guruplug/Kconfig"
-source "board/Marvell/mv88f6281gtw_ge/Kconfig"
-source "board/Marvell/openrd/Kconfig"
-source "board/Marvell/rd6281a/Kconfig"
-source "board/Marvell/sheevaplug/Kconfig"
-source "board/Seagate/dockstar/Kconfig"
-source "board/Seagate/goflexhome/Kconfig"
 source "board/afeb9260/Kconfig"
-source "board/ait/cam_enc_4xx/Kconfig"
 source "board/altera/socfpga/Kconfig"
 source "board/armadeus/apf27/Kconfig"
 source "board/armltd/integrator/Kconfig"
-source "board/armltd/versatile/Kconfig"
 source "board/armltd/vexpress/Kconfig"
 source "board/armltd/vexpress64/Kconfig"
-source "board/atmark-techno/armadillo-800eva/Kconfig"
 source "board/atmel/at91rm9200ek/Kconfig"
 source "board/atmel/at91sam9260ek/Kconfig"
 source "board/atmel/at91sam9261ek/Kconfig"
@@ -810,51 +564,29 @@ source "board/atmel/at91sam9rlek/Kconfig"
 source "board/atmel/at91sam9x5ek/Kconfig"
 source "board/atmel/sama5d3_xplained/Kconfig"
 source "board/atmel/sama5d3xek/Kconfig"
-source "board/avionic-design/medcom-wide/Kconfig"
-source "board/avionic-design/plutux/Kconfig"
-source "board/avionic-design/tec-ng/Kconfig"
-source "board/avionic-design/tec/Kconfig"
 source "board/balloon3/Kconfig"
 source "board/barco/titanium/Kconfig"
 source "board/bluegiga/apx4devkit/Kconfig"
 source "board/bluewater/snapper9260/Kconfig"
 source "board/boundary/nitrogen6x/Kconfig"
 source "board/broadcom/bcm28155_ap/Kconfig"
-source "board/buffalo/lsxl/Kconfig"
+source "board/broadcom/bcm958300k/Kconfig"
+source "board/broadcom/bcm958622hr/Kconfig"
 source "board/calao/sbc35_a9g20/Kconfig"
 source "board/calao/tny_a9260/Kconfig"
 source "board/calao/usb_a9263/Kconfig"
 source "board/cirrus/edb93xx/Kconfig"
-source "board/cloudengines/pogo_e02/Kconfig"
 source "board/cm4008/Kconfig"
 source "board/cm41xx/Kconfig"
-source "board/comelit/dig297/Kconfig"
-source "board/compal/paz00/Kconfig"
 source "board/compulab/cm_t335/Kconfig"
-source "board/compulab/cm_t35/Kconfig"
-source "board/compulab/cm_t54/Kconfig"
-source "board/compulab/trimslice/Kconfig"
 source "board/congatec/cgtqmx6eval/Kconfig"
-source "board/corscience/tricorder/Kconfig"
 source "board/creative/xfi3/Kconfig"
-source "board/d-link/dns325/Kconfig"
 source "board/davedenx/qong/Kconfig"
-source "board/davinci/da8xxevm/Kconfig"
-source "board/davinci/dm355evm/Kconfig"
-source "board/davinci/dm355leopard/Kconfig"
-source "board/davinci/dm365evm/Kconfig"
-source "board/davinci/dm6467evm/Kconfig"
-source "board/davinci/dvevm/Kconfig"
-source "board/davinci/ea20/Kconfig"
-source "board/davinci/schmoogie/Kconfig"
-source "board/davinci/sffsdr/Kconfig"
-source "board/davinci/sonata/Kconfig"
 source "board/denx/m28evk/Kconfig"
 source "board/denx/m53evk/Kconfig"
 source "board/egnite/ethernut5/Kconfig"
 source "board/embest/mx6boards/Kconfig"
 source "board/emk/top9000/Kconfig"
-source "board/enbw/enbw_cmc/Kconfig"
 source "board/esd/meesc/Kconfig"
 source "board/esd/otc570/Kconfig"
 source "board/esg/ima3-mx53/Kconfig"
@@ -877,71 +609,35 @@ source "board/freescale/mx6qarm2/Kconfig"
 source "board/freescale/mx6qsabreauto/Kconfig"
 source "board/freescale/mx6sabresd/Kconfig"
 source "board/freescale/mx6slevk/Kconfig"
+source "board/freescale/mx6sxsabresd/Kconfig"
 source "board/freescale/vf610twr/Kconfig"
 source "board/gateworks/gw_ventana/Kconfig"
 source "board/genesi/mx51_efikamx/Kconfig"
-source "board/gumstix/duovero/Kconfig"
 source "board/gumstix/pepper/Kconfig"
 source "board/h2200/Kconfig"
 source "board/hale/tt01/Kconfig"
-source "board/highbank/Kconfig"
-source "board/htkw/mcx/Kconfig"
 source "board/icpdas/lp8x4x/Kconfig"
 source "board/imx31_phycore/Kconfig"
-source "board/iomega/iconnect/Kconfig"
 source "board/isee/igep0033/Kconfig"
-source "board/isee/igep00x0/Kconfig"
 source "board/jornada/Kconfig"
-source "board/karo/tk71/Kconfig"
 source "board/karo/tx25/Kconfig"
-source "board/keymile/km_arm/Kconfig"
-source "board/kmc/kzm9g/Kconfig"
-source "board/logicpd/am3517evm/Kconfig"
 source "board/logicpd/imx27lite/Kconfig"
 source "board/logicpd/imx31_litekit/Kconfig"
-source "board/logicpd/omap3som/Kconfig"
-source "board/logicpd/zoom1/Kconfig"
-source "board/matrix_vision/mvblx/Kconfig"
 source "board/mpl/vcma9/Kconfig"
-source "board/nokia/rx51/Kconfig"
-source "board/nvidia/beaver/Kconfig"
-source "board/nvidia/cardhu/Kconfig"
-source "board/nvidia/dalmore/Kconfig"
-source "board/nvidia/harmony/Kconfig"
-source "board/nvidia/jetson-tk1/Kconfig"
-source "board/nvidia/seaboard/Kconfig"
-source "board/nvidia/venice2/Kconfig"
-source "board/nvidia/ventana/Kconfig"
-source "board/nvidia/whistler/Kconfig"
 source "board/olimex/mx23_olinuxino/Kconfig"
-source "board/omicron/calimain/Kconfig"
-source "board/overo/Kconfig"
 source "board/palmld/Kconfig"
 source "board/palmtc/Kconfig"
 source "board/palmtreo680/Kconfig"
-source "board/pandora/Kconfig"
 source "board/phytec/pcm051/Kconfig"
 source "board/ppcag/bg0900/Kconfig"
 source "board/pxa255_idp/Kconfig"
-source "board/raidsonic/ib62x0/Kconfig"
 source "board/raspberrypi/rpi_b/Kconfig"
-source "board/renesas/alt/Kconfig"
-source "board/renesas/koelsch/Kconfig"
-source "board/renesas/lager/Kconfig"
 source "board/ronetix/pm9261/Kconfig"
 source "board/ronetix/pm9263/Kconfig"
 source "board/ronetix/pm9g45/Kconfig"
-source "board/samsung/arndale/Kconfig"
 source "board/samsung/goni/Kconfig"
-source "board/samsung/origen/Kconfig"
 source "board/samsung/smdk2410/Kconfig"
-source "board/samsung/smdk5250/Kconfig"
-source "board/samsung/smdk5420/Kconfig"
 source "board/samsung/smdkc100/Kconfig"
-source "board/samsung/smdkv310/Kconfig"
-source "board/samsung/trats/Kconfig"
-source "board/samsung/trats2/Kconfig"
-source "board/samsung/universal_c210/Kconfig"
 source "board/sandisk/sansa_fuze_plus/Kconfig"
 source "board/scb9328/Kconfig"
 source "board/schulercontrol/sc_sps_1/Kconfig"
@@ -959,32 +655,18 @@ source "board/spear/spear600/Kconfig"
 source "board/spear/x600/Kconfig"
 source "board/st-ericsson/snowball/Kconfig"
 source "board/st-ericsson/u8500/Kconfig"
-source "board/st/nhk8815/Kconfig"
 source "board/sunxi/Kconfig"
 source "board/syteco/jadecpu/Kconfig"
 source "board/syteco/zmx25/Kconfig"
 source "board/taskit/stamp9g20/Kconfig"
-source "board/technexion/tao3530/Kconfig"
-source "board/technexion/twister/Kconfig"
-source "board/teejet/mt_ventoux/Kconfig"
 source "board/ti/am335x/Kconfig"
-source "board/ti/am3517crane/Kconfig"
 source "board/ti/am43xx/Kconfig"
-source "board/ti/beagle/Kconfig"
-source "board/ti/dra7xx/Kconfig"
-source "board/ti/evm/Kconfig"
-source "board/ti/ks2_evm/Kconfig"
-source "board/ti/omap5_uevm/Kconfig"
-source "board/ti/panda/Kconfig"
-source "board/ti/sdp3430/Kconfig"
-source "board/ti/sdp4430/Kconfig"
 source "board/ti/ti814x/Kconfig"
 source "board/ti/ti816x/Kconfig"
 source "board/ti/tnetv107xevm/Kconfig"
 source "board/timll/devkit3250/Kconfig"
-source "board/timll/devkit8000/Kconfig"
 source "board/toradex/colibri_pxa270/Kconfig"
-source "board/toradex/colibri_t20_iris/Kconfig"
+source "board/tqc/tqma6/Kconfig"
 source "board/trizepsiv/Kconfig"
 source "board/ttcontrol/vision2/Kconfig"
 source "board/udoo/Kconfig"
@@ -992,7 +674,6 @@ source "board/vpac270/Kconfig"
 source "board/wandboard/Kconfig"
 source "board/woodburn/Kconfig"
 source "board/xaeniax/Kconfig"
-source "board/xilinx/zynq/Kconfig"
 source "board/zipitz2/Kconfig"
 
 endmenu
index 0299902..97e4a8b 100644 (file)
@@ -22,6 +22,7 @@ SECTIONS
        .text      :
        {
        __start = .;
+         *(.vectors)
          arch/arm/cpu/arm1136/start.o  (.text*)
          *(.text*)
        } >.sram
diff --git a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
deleted file mode 100644 (file)
index 623a635..0000000
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-       . = 0x00000000;
-
-       . = ALIGN(4);
-       .text      :
-       {
-               *(.__image_copy_start)
-               *(.vectors)
-               arch/arm/cpu/arm920t/start.o    (.text*)
-               /* the EP93xx expects to find the pattern 'CRUS' at 0x1000 */
-         . = 0x1000;
-         LONG(0x53555243)
-         *(.text*)
-       }
-
-       . = ALIGN(4);
-       .rodata : { *(.rodata*) }
-
-       . = ALIGN(4);
-       .data : { *(.data*) }
-
-       . = ALIGN(4);
-       .got : { *(.got) }
-
-       . = .;
-
-       . = ALIGN(4);
-       .u_boot_list : {
-               KEEP(*(SORT(.u_boot_list*)));
-       }
-
-       . = ALIGN(4);
-
-       .image_copy_end :
-       {
-               *(.__image_copy_end)
-       }
-
-       __bss_start = .;
-       .bss : { *(.bss*) }
-       __bss_end = .;
-
-       .end :
-       {
-               *(.__end)
-       }
-}
diff --git a/arch/arm/cpu/arm926ejs/davinci/Kconfig b/arch/arm/cpu/arm926ejs/davinci/Kconfig
new file mode 100644 (file)
index 0000000..be1b0f9
--- /dev/null
@@ -0,0 +1,79 @@
+if ARCH_DAVINCI
+
+choice
+       prompt "DaVinci board select"
+
+config TARGET_ENBW_CMC
+       bool "EnBW CMC board"
+
+config TARGET_IPAM390
+       bool "IPAM390 board"
+
+config TARGET_DA830EVM
+       bool "DA830 EVM board"
+
+config TARGET_DA850EVM
+       bool "DA850 EVM board"
+
+config TARGET_CAM_ENC_4XX
+       bool "CAM ENC 4xx board"
+
+config TARGET_HAWKBOARD
+       bool "Hawkboard"
+
+config TARGET_DAVINCI_DM355EVM
+       bool "DM355 EVM board"
+
+config TARGET_DAVINCI_DM355LEOPARD
+       bool "DM355 Leopard board"
+
+config TARGET_DAVINCI_DM365EVM
+       bool "DM365 EVM board"
+
+config TARGET_DAVINCI_DM6467EVM
+       bool "DM6467 EVM board"
+
+config TARGET_DAVINCI_DVEVM
+       bool "DVEVM board"
+
+config TARGET_EA20
+       bool "EA20 board"
+
+config TARGET_DAVINCI_SCHMOOGIE
+       bool "Schmoogie board"
+
+config TARGET_DAVINCI_SFFSDR
+       bool "SFFSDR board"
+
+config TARGET_DAVINCI_SONATA
+       bool "Sonata board"
+
+config TARGET_CALIMAIN
+       bool "Calimain board"
+
+endchoice
+
+config SYS_CPU
+       string
+       default "arm926ejs"
+
+config SYS_SOC
+       string
+       default "davinci"
+
+source "board/enbw/enbw_cmc/Kconfig"
+source "board/ait/cam_enc_4xx/Kconfig"
+source "board/Barix/ipam390/Kconfig"
+source "board/davinci/da8xxevm/Kconfig"
+source "board/davinci/dm355evm/Kconfig"
+source "board/davinci/dm355leopard/Kconfig"
+source "board/davinci/dm365evm/Kconfig"
+source "board/davinci/dm6467evm/Kconfig"
+source "board/davinci/dvevm/Kconfig"
+source "board/davinci/ea20/Kconfig"
+source "board/davinci/schmoogie/Kconfig"
+source "board/davinci/sffsdr/Kconfig"
+source "board/davinci/sonata/Kconfig"
+source "board/omicron/calimain/Kconfig"
+
+endif
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/Kconfig b/arch/arm/cpu/arm926ejs/kirkwood/Kconfig
new file mode 100644 (file)
index 0000000..58867f3
--- /dev/null
@@ -0,0 +1,89 @@
+if KIRKWOOD
+
+choice
+       prompt "Marvell Kirkwood board select"
+
+config TARGET_OPENRD
+       bool "Marvell OpenRD Board"
+
+config TARGET_MV88F6281GTW_GE
+       bool "MV88f6281GTW_GE Board"
+
+config TARGET_RD6281A
+       bool "RD6281A Board"
+
+config TARGET_DREAMPLUG
+       bool "DreamPlug Board"
+
+config TARGET_GURUPLUG
+       bool "GuruPlug Board"
+
+config TARGET_SHEEVAPLUG
+       bool "SheevaPlug Board"
+
+config TARGET_LSXL
+       bool "lsxl Board"
+
+config TARGET_POGO_E02
+       bool "pogo_e02 Board"
+
+config TARGET_DNS325
+       bool "dns325 Board"
+
+config TARGET_ICONNECT
+       bool "iconnect Board"
+
+config TARGET_TK71
+       bool "TK71 Board"
+
+config TARGET_KM_KIRKWOOD
+       bool "KM_KIRKWOOD Board"
+
+config TARGET_NET2BIG_V2
+       bool "LaCie 2Big Network v2 NAS Board"
+
+config TARGET_NETSPACE_V2
+       bool "LaCie netspace_v2 Board"
+
+config TARGET_WIRELESS_SPACE
+       bool "LaCie Wireless_space Board"
+
+config TARGET_IB62X0
+       bool "ib62x0 Board"
+
+config TARGET_DOCKSTAR
+       bool "Dockstar Board"
+
+config TARGET_GOFLEXHOME
+       bool "GoFlex Home Board"
+
+endchoice
+
+config SYS_CPU
+       string
+       default "arm926ejs"
+
+config SYS_SOC
+       string
+       default "kirkwood"
+
+source "board/Marvell/openrd/Kconfig"
+source "board/Marvell/mv88f6281gtw_ge/Kconfig"
+source "board/Marvell/rd6281a/Kconfig"
+source "board/Marvell/dreamplug/Kconfig"
+source "board/Marvell/guruplug/Kconfig"
+source "board/Marvell/sheevaplug/Kconfig"
+source "board/buffalo/lsxl/Kconfig"
+source "board/cloudengines/pogo_e02/Kconfig"
+source "board/d-link/dns325/Kconfig"
+source "board/iomega/iconnect/Kconfig"
+source "board/karo/tk71/Kconfig"
+source "board/keymile/km_arm/Kconfig"
+source "board/LaCie/net2big_v2/Kconfig"
+source "board/LaCie/netspace_v2/Kconfig"
+source "board/LaCie/wireless_space/Kconfig"
+source "board/raidsonic/ib62x0/Kconfig"
+source "board/Seagate/dockstar/Kconfig"
+source "board/Seagate/goflexhome/Kconfig"
+
+endif
index f4bf8ac..bf2ac13 100644 (file)
@@ -21,6 +21,7 @@ SECTIONS
        . = ALIGN(4);
        .text   :
        {
+               *(.vectors)
                arch/arm/cpu/arm926ejs/mxs/start.o      (.text*)
                *(.text*)
        }
diff --git a/arch/arm/cpu/arm926ejs/nomadik/Kconfig b/arch/arm/cpu/arm926ejs/nomadik/Kconfig
new file mode 100644 (file)
index 0000000..7177800
--- /dev/null
@@ -0,0 +1,21 @@
+if ARCH_NOMADIK
+
+choice
+       prompt "Nomadik board select"
+
+config NOMADIK_NHK8815
+       bool "ST 8815 Nomadik Hardware Kit"
+
+endchoice
+
+config SYS_CPU
+       string
+       default "arm926ejs"
+
+config SYS_SOC
+       string
+       default "nomadik"
+
+source "board/st/nhk8815/Kconfig"
+
+endif
diff --git a/arch/arm/cpu/arm926ejs/orion5x/Kconfig b/arch/arm/cpu/arm926ejs/orion5x/Kconfig
new file mode 100644 (file)
index 0000000..aa40099
--- /dev/null
@@ -0,0 +1,21 @@
+if ORION5X
+
+choice
+       prompt "Marvell Orion board select"
+
+config TARGET_EDMINIV2
+       bool "LaCie Ethernet Disk mini V2"
+
+endchoice
+
+config SYS_CPU
+       string
+       default "arm926ejs"
+
+config SYS_SOC
+       string
+       default "orion5x"
+
+source "board/LaCie/edminiv2/Kconfig"
+
+endif
diff --git a/arch/arm/cpu/arm926ejs/versatile/Kconfig b/arch/arm/cpu/arm926ejs/versatile/Kconfig
new file mode 100644 (file)
index 0000000..fc29c98
--- /dev/null
@@ -0,0 +1,23 @@
+if ARCH_VERSATILE
+
+config SYS_CPU
+       string
+       default "arm926ejs"
+
+config SYS_BOARD
+       string
+       default "versatile"
+
+config SYS_VENDOR
+       string
+       default "armltd"
+
+config SYS_SOC
+       string
+       default "versatile"
+
+config SYS_CONFIG_NAME
+       string
+       default "versatile"
+
+endif
index 703ce8c..afeed4d 100644 (file)
@@ -28,6 +28,7 @@ ifneq ($(CONFIG_ARMV7_PSCI),)
 obj-y  += psci.o
 endif
 
+obj-$(CONFIG_IPROC) += iproc-common/
 obj-$(CONFIG_KONA) += kona-common/
 obj-$(CONFIG_OMAP_COMMON) += omap-common/
 obj-$(CONFIG_SYS_ARCH_TIMER) += arch_timer.o
index b1c28c9..07cf267 100644 (file)
@@ -22,6 +22,7 @@ SECTIONS
        .text      :
        {
                __start = .;
+               *(.vectors)
                arch/arm/cpu/armv7/start.o      (.text)
                *(.text*)
        } >.sram
index 98f5aa5..bd867a2 100644 (file)
@@ -9,3 +9,4 @@ obj-y   += clk-core.o
 obj-y  += clk-bcm281xx.o
 obj-y  += clk-sdio.o
 obj-y  += clk-bsc.o
+obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o
index bc8a170..d16b99f 100644 (file)
@@ -118,6 +118,16 @@ unsigned long slave_apb_freq_tbl[8] = {
        78 * CLOCK_1M
 };
 
+unsigned long esub_freq_tbl[8] = {
+       78 * CLOCK_1M,
+       156 * CLOCK_1M,
+       156 * CLOCK_1M,
+       156 * CLOCK_1M,
+       208 * CLOCK_1M,
+       208 * CLOCK_1M,
+       208 * CLOCK_1M
+};
+
 static struct bus_clk_data bsc1_apb_data = {
        .gate = HW_SW_GATE_AUTO(0x0458, 16, 0, 1),
 };
@@ -295,6 +305,27 @@ static struct ccu_clock kps_ccu_clk = {
        .freq_tbl = slave_axi_freq_tbl,
 };
 
+#ifdef CONFIG_BCM_SF2_ETH
+static struct ccu_clock esub_ccu_clk = {
+       .clk = {
+               .name = "esub_ccu_clk",
+               .ops = &ccu_clk_ops,
+               .ccu_clk_mgr_base = ESUB_CLK_BASE_ADDR,
+       },
+       .num_policy_masks = 1,
+       .policy_freq_offset = 0x00000008,
+       .freq_bit_shift = 8,
+       .policy_ctl_offset = 0x0000000c,
+       .policy0_mask_offset = 0x00000010,
+       .policy1_mask_offset = 0x00000014,
+       .policy2_mask_offset = 0x00000018,
+       .policy3_mask_offset = 0x0000001c,
+       .lvm_en_offset = 0x00000034,
+       .freq_id = 2,
+       .freq_tbl = esub_freq_tbl,
+};
+#endif
+
 /*
  * Bus clocks
  */
@@ -517,6 +548,9 @@ struct clk_lookup arch_clk_tbl[] = {
        CLK_LK(bsc1_apb),
        CLK_LK(bsc2_apb),
        CLK_LK(bsc3_apb),
+#ifdef CONFIG_BCM_SF2_ETH
+       CLK_LK(esub_ccu),
+#endif
 };
 
 /* public array size */
diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-eth.c b/arch/arm/cpu/armv7/bcm281xx/clk-eth.c
new file mode 100644 (file)
index 0000000..b0b92b9
--- /dev/null
@@ -0,0 +1,143 @@
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+#define WR_ACCESS_ADDR                 ESUB_CLK_BASE_ADDR
+#define WR_ACCESS_PASSWORD                             0xA5A500
+
+#define PLLE_POST_RESETB_ADDR          (ESUB_CLK_BASE_ADDR + 0x00000C00)
+
+#define PLLE_RESETB_ADDR               (ESUB_CLK_BASE_ADDR + 0x00000C58)
+#define PLLE_RESETB_I_PLL_RESETB_PLLE_MASK             0x00010000
+#define PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK       0x00000001
+
+#define PLL_LOCK_ADDR                  (ESUB_CLK_BASE_ADDR + 0x00000C38)
+#define PLL_LOCK_PLL_LOCK_PLLE_MASK                    0x00000001
+
+#define ESW_SYS_DIV_ADDR               (ESUB_CLK_BASE_ADDR + 0x00000A04)
+#define ESW_SYS_DIV_PLL_SELECT_MASK                    0x00000300
+#define ESW_SYS_DIV_DIV_MASK                           0x0000001C
+#define ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT            0x00000100
+#define ESW_SYS_DIV_DIV_SELECT                         0x4
+#define ESW_SYS_DIV_TRIGGER_MASK                       0x00000001
+
+#define ESUB_AXI_DIV_DEBUG_ADDR                (ESUB_CLK_BASE_ADDR + 0x00000E04)
+#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK             0x0000001C
+#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK    0x00000040
+#define ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT     0x0
+#define ESUB_AXI_DIV_DEBUG_TRIGGER_MASK                        0x00000001
+
+#define PLL_MAX_RETRY  100
+
+/* Enable appropriate clocks for Ethernet */
+int clk_eth_enable(void)
+{
+       int rc = -1;
+       int retry_count = 0;
+       rc = clk_get_and_enable("esub_ccu_clk");
+
+       /* Enable Access to CCU registers */
+       writel((1 | WR_ACCESS_PASSWORD), WR_ACCESS_ADDR);
+
+       writel(readl(PLLE_POST_RESETB_ADDR) &
+              ~PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK,
+              PLLE_POST_RESETB_ADDR);
+
+       /* Take PLL out of reset and put into normal mode */
+       writel(readl(PLLE_RESETB_ADDR) | PLLE_RESETB_I_PLL_RESETB_PLLE_MASK,
+              PLLE_RESETB_ADDR);
+
+       /* Wait for PLL lock */
+       rc = -1;
+       while (retry_count < PLL_MAX_RETRY) {
+               udelay(100);
+               if (readl(PLL_LOCK_ADDR) & PLL_LOCK_PLL_LOCK_PLLE_MASK) {
+                       rc = 0;
+                       break;
+               }
+               retry_count++;
+       }
+
+       if (rc == -1) {
+               printf("%s: ETH-PLL lock timeout, Ethernet is not enabled!\n",
+                      __func__);
+               return -1;
+       }
+
+       writel(readl(PLLE_POST_RESETB_ADDR) |
+              PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK,
+              PLLE_POST_RESETB_ADDR);
+
+       /* Switch esw_sys_clk to use 104MHz(208MHz/2) clock */
+       writel((readl(ESW_SYS_DIV_ADDR) &
+               ~(ESW_SYS_DIV_PLL_SELECT_MASK | ESW_SYS_DIV_DIV_MASK)) |
+              ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT | ESW_SYS_DIV_DIV_SELECT,
+              ESW_SYS_DIV_ADDR);
+
+       writel(readl(ESW_SYS_DIV_ADDR) | ESW_SYS_DIV_TRIGGER_MASK,
+              ESW_SYS_DIV_ADDR);
+
+       /* Wait for trigger complete */
+       rc = -1;
+       retry_count = 0;
+       while (retry_count < PLL_MAX_RETRY) {
+               udelay(100);
+               if (!(readl(ESW_SYS_DIV_ADDR) & ESW_SYS_DIV_TRIGGER_MASK)) {
+                       rc = 0;
+                       break;
+               }
+               retry_count++;
+       }
+
+       if (rc == -1) {
+               printf("%s: SYS CLK Trigger timeout, Ethernet is not enabled!\n",
+                      __func__);
+               return -1;
+       }
+
+       /* switch Esub AXI clock to 208MHz */
+       writel((readl(ESUB_AXI_DIV_DEBUG_ADDR) &
+               ~(ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK |
+                 ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK |
+                 ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) |
+              ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT |
+              ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK,
+              ESUB_AXI_DIV_DEBUG_ADDR);
+
+       writel(readl(ESUB_AXI_DIV_DEBUG_ADDR) |
+              ESUB_AXI_DIV_DEBUG_TRIGGER_MASK,
+              ESUB_AXI_DIV_DEBUG_ADDR);
+
+       /* Wait for trigger complete */
+       rc = -1;
+       retry_count = 0;
+       while (retry_count < PLL_MAX_RETRY) {
+               udelay(100);
+               if (!(readl(ESUB_AXI_DIV_DEBUG_ADDR) &
+                     ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) {
+                       rc = 0;
+                       break;
+               }
+               retry_count++;
+       }
+
+       if (rc == -1) {
+               printf("%s: AXI CLK Trigger timeout, Ethernet is not enabled!\n",
+                      __func__);
+               return -1;
+       }
+
+       /* Disable Access to CCU registers */
+       writel(WR_ACCESS_PASSWORD, WR_ACCESS_ADDR);
+
+       return rc;
+}
diff --git a/arch/arm/cpu/armv7/bcmcygnus/Makefile b/arch/arm/cpu/armv7/bcmcygnus/Makefile
new file mode 100644 (file)
index 0000000..04afcf9
--- /dev/null
@@ -0,0 +1,7 @@
+#
+# Copyright 2014 Broadcom Corporation.
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y  += reset.o
diff --git a/arch/arm/cpu/armv7/bcmcygnus/reset.c b/arch/arm/cpu/armv7/bcmcygnus/reset.c
new file mode 100644 (file)
index 0000000..53ecc0c
--- /dev/null
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#define CRMU_MAIL_BOX1         0x03024028
+#define CRMU_SOFT_RESET_CMD    0xFFFFFFFF
+
+void reset_cpu(ulong ignored)
+{
+       /* Send soft reset command via Mailbox. */
+       writel(CRMU_SOFT_RESET_CMD, CRMU_MAIL_BOX1);
+
+       while (1)
+               ;       /* loop forever till reset */
+}
diff --git a/arch/arm/cpu/armv7/bcmnsp/Makefile b/arch/arm/cpu/armv7/bcmnsp/Makefile
new file mode 100644 (file)
index 0000000..04afcf9
--- /dev/null
@@ -0,0 +1,7 @@
+#
+# Copyright 2014 Broadcom Corporation.
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y  += reset.o
diff --git a/arch/arm/cpu/armv7/bcmnsp/reset.c b/arch/arm/cpu/armv7/bcmnsp/reset.c
new file mode 100644 (file)
index 0000000..d79d9aa
--- /dev/null
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#define CRU_RESET_OFFSET       0x1803F184
+
+void reset_cpu(ulong ignored)
+{
+       /* Reset the cpu by setting software reset request bit */
+       writel(0x1, CRU_RESET_OFFSET);
+
+       while (1)
+               ;       /* loop forever till reset */
+}
diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig
new file mode 100644 (file)
index 0000000..f1cacdc
--- /dev/null
@@ -0,0 +1,55 @@
+if ARCH_EXYNOS
+
+choice
+       prompt "EXYNOS board select"
+
+config TARGET_SMDKV310
+       bool "Exynos4210 SMDKV310 board"
+
+config TARGET_TRATS
+       bool "Exynos4210 Trats board"
+
+config TARGET_S5PC210_UNIVERSAL
+       bool "EXYNOS4210 Universal C210 board"
+
+config TARGET_ORIGEN
+       bool "Exynos4412 Origen board"
+
+config TARGET_TRATS2
+       bool "Exynos4412 Trat2 board"
+
+config TARGET_ARNDALE
+       bool "Exynos5250 Arndale board"
+
+config TARGET_SMDK5250
+       bool "SMDK5250 board"
+
+config TARGET_SNOW
+       bool "Snow board"
+
+config TARGET_SMDK5420
+       bool "SMDK5420 board"
+
+config TARGET_PEACH_PIT
+       bool "Peach Pi board"
+
+endchoice
+
+config SYS_CPU
+       string
+       default "armv7"
+
+config SYS_SOC
+       string
+       default "exynos"
+
+source "board/samsung/smdkv310/Kconfig"
+source "board/samsung/trats/Kconfig"
+source "board/samsung/universal_c210/Kconfig"
+source "board/samsung/origen/Kconfig"
+source "board/samsung/trats2/Kconfig"
+source "board/samsung/arndale/Kconfig"
+source "board/samsung/smdk5250/Kconfig"
+source "board/samsung/smdk5420/Kconfig"
+
+endif
similarity index 90%
rename from board/highbank/Kconfig
rename to arch/arm/cpu/armv7/highbank/Kconfig
index 1c32490..9527928 100644 (file)
@@ -1,4 +1,4 @@
-if TARGET_HIGHBANK
+if ARCH_HIGHBANK
 
 config SYS_CPU
        string
diff --git a/arch/arm/cpu/armv7/iproc-common/Makefile b/arch/arm/cpu/armv7/iproc-common/Makefile
new file mode 100644 (file)
index 0000000..c071a17
--- /dev/null
@@ -0,0 +1,9 @@
+#
+# Copyright 2014 Broadcom Corporation.
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y  += armpll.o
+obj-y  += hwinit-common.o
+obj-y  += timer.o
diff --git a/arch/arm/cpu/armv7/iproc-common/armpll.c b/arch/arm/cpu/armv7/iproc-common/armpll.c
new file mode 100644 (file)
index 0000000..49b61bf
--- /dev/null
@@ -0,0 +1,170 @@
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/iproc-common/armpll.h>
+#include <asm/iproc-common/sysmap.h>
+
+#define NELEMS(x)      (sizeof(x) / sizeof(x[0]))
+
+struct armpll_parameters {
+       unsigned int mode;
+       unsigned int ndiv_int;
+       unsigned int ndiv_frac;
+       unsigned int pdiv;
+       unsigned int freqid;
+};
+
+struct armpll_parameters armpll_clk_tab[] = {
+       {   25, 64,      1, 1, 0},
+       {  100, 64,      1, 1, 2},
+       {  400, 64,      1, 1, 6},
+       {  448, 71, 713050, 1, 6},
+       {  500, 80,      1, 1, 6},
+       {  560, 89, 629145, 1, 6},
+       {  600, 96,      1, 1, 6},
+       {  800, 64,      1, 1, 7},
+       {  896, 71, 713050, 1, 7},
+       { 1000, 80,      1, 1, 7},
+       { 1100, 88,      1, 1, 7},
+       { 1120, 89, 629145, 1, 7},
+       { 1200, 96,      1, 1, 7},
+};
+
+uint32_t armpll_config(uint32_t clkmhz)
+{
+       uint32_t freqid;
+       uint32_t ndiv_frac;
+       uint32_t pll;
+       uint32_t status = 1;
+       uint32_t timeout_countdown;
+       int i;
+
+       for (i = 0; i < NELEMS(armpll_clk_tab); i++) {
+               if (armpll_clk_tab[i].mode == clkmhz) {
+                       status = 0;
+                       break;
+               }
+       }
+
+       if (status) {
+               printf("Error: Clock configuration not supported\n");
+               goto armpll_config_done;
+       }
+
+       /* Enable write access */
+       writel(IPROC_REG_WRITE_ACCESS, IHOST_PROC_CLK_WR_ACCESS);
+
+       if (clkmhz == 25)
+               freqid = 0;
+       else
+               freqid = 2;
+
+       /* Bypass ARM clock and run on sysclk */
+       writel(1 << IHOST_PROC_CLK_POLICY_FREQ__PRIV_ACCESS_MODE |
+              freqid << IHOST_PROC_CLK_POLICY_FREQ__POLICY3_FREQ_R |
+              freqid << IHOST_PROC_CLK_POLICY_FREQ__POLICY2_FREQ_R |
+              freqid << IHOST_PROC_CLK_POLICY_FREQ__POLICY1_FREQ_R |
+              freqid << IHOST_PROC_CLK_POLICY_FREQ__POLICY0_FREQ_R,
+              IHOST_PROC_CLK_POLICY_FREQ);
+
+       writel(1 << IHOST_PROC_CLK_POLICY_CTL__GO |
+              1 << IHOST_PROC_CLK_POLICY_CTL__GO_AC,
+              IHOST_PROC_CLK_POLICY_CTL);
+
+       /* Poll CCU until operation complete */
+       timeout_countdown = 0x100000;
+       while (readl(IHOST_PROC_CLK_POLICY_CTL) &
+              (1 << IHOST_PROC_CLK_POLICY_CTL__GO)) {
+               timeout_countdown--;
+               if (timeout_countdown == 0) {
+                       printf("CCU polling timedout\n");
+                       status = 1;
+                       goto armpll_config_done;
+               }
+       }
+
+       if (clkmhz == 25 || clkmhz == 100) {
+               status = 0;
+               goto armpll_config_done;
+       }
+
+       /* Now it is safe to program the PLL */
+       pll = readl(IHOST_PROC_CLK_PLLARMB);
+       pll &= ~((1 << IHOST_PROC_CLK_PLLARMB__PLLARM_NDIV_FRAC_WIDTH) - 1);
+       ndiv_frac =
+               ((1 << IHOST_PROC_CLK_PLLARMB__PLLARM_NDIV_FRAC_WIDTH) - 1) &
+                (armpll_clk_tab[i].ndiv_frac <<
+                IHOST_PROC_CLK_PLLARMB__PLLARM_NDIV_FRAC_R);
+       pll |= ndiv_frac;
+       writel(pll, IHOST_PROC_CLK_PLLARMB);
+
+       writel(1 << IHOST_PROC_CLK_PLLARMA__PLLARM_LOCK |
+              armpll_clk_tab[i].ndiv_int <<
+                       IHOST_PROC_CLK_PLLARMA__PLLARM_NDIV_INT_R |
+              armpll_clk_tab[i].pdiv <<
+                       IHOST_PROC_CLK_PLLARMA__PLLARM_PDIV_R |
+              1 << IHOST_PROC_CLK_PLLARMA__PLLARM_SOFT_RESETB,
+              IHOST_PROC_CLK_PLLARMA);
+
+       /* Poll ARM PLL Lock until operation complete */
+       timeout_countdown = 0x100000;
+       while (readl(IHOST_PROC_CLK_PLLARMA) &
+              (1 << IHOST_PROC_CLK_PLLARMA__PLLARM_LOCK)) {
+               timeout_countdown--;
+               if (timeout_countdown == 0) {
+                       printf("ARM PLL lock failed\n");
+                       status = 1;
+                       goto armpll_config_done;
+               }
+       }
+
+       pll = readl(IHOST_PROC_CLK_PLLARMA);
+       pll |= (1 << IHOST_PROC_CLK_PLLARMA__PLLARM_SOFT_POST_RESETB);
+       writel(pll, IHOST_PROC_CLK_PLLARMA);
+
+       /* Set the policy */
+       writel(1 << IHOST_PROC_CLK_POLICY_FREQ__PRIV_ACCESS_MODE |
+              armpll_clk_tab[i].freqid <<
+                       IHOST_PROC_CLK_POLICY_FREQ__POLICY3_FREQ_R |
+              armpll_clk_tab[i].freqid <<
+                       IHOST_PROC_CLK_POLICY_FREQ__POLICY2_FREQ_R |
+              armpll_clk_tab[i].freqid <<
+                       IHOST_PROC_CLK_POLICY_FREQ__POLICY1_FREQ_R |
+              armpll_clk_tab[i+4].freqid <<
+                       IHOST_PROC_CLK_POLICY_FREQ__POLICY0_FREQ_R,
+              IHOST_PROC_CLK_POLICY_FREQ);
+
+       writel(IPROC_CLKCT_HDELAY_SW_EN, IHOST_PROC_CLK_CORE0_CLKGATE);
+       writel(IPROC_CLKCT_HDELAY_SW_EN, IHOST_PROC_CLK_CORE1_CLKGATE);
+       writel(IPROC_CLKCT_HDELAY_SW_EN, IHOST_PROC_CLK_ARM_SWITCH_CLKGATE);
+       writel(IPROC_CLKCT_HDELAY_SW_EN, IHOST_PROC_CLK_ARM_PERIPH_CLKGATE);
+       writel(IPROC_CLKCT_HDELAY_SW_EN, IHOST_PROC_CLK_APB0_CLKGATE);
+
+       writel(1 << IHOST_PROC_CLK_POLICY_CTL__GO |
+              1 << IHOST_PROC_CLK_POLICY_CTL__GO_AC,
+              IHOST_PROC_CLK_POLICY_CTL);
+
+       /* Poll CCU until operation complete */
+       timeout_countdown = 0x100000;
+       while (readl(IHOST_PROC_CLK_POLICY_CTL) &
+              (1 << IHOST_PROC_CLK_POLICY_CTL__GO)) {
+               timeout_countdown--;
+               if (timeout_countdown == 0) {
+                       printf("CCU polling failed\n");
+                       status = 1;
+                       goto armpll_config_done;
+               }
+       }
+
+       status = 0;
+armpll_config_done:
+       /* Disable access to PLL registers */
+       writel(0, IHOST_PROC_CLK_WR_ACCESS);
+
+       return status;
+}
diff --git a/arch/arm/cpu/armv7/iproc-common/hwinit-common.c b/arch/arm/cpu/armv7/iproc-common/hwinit-common.c
new file mode 100644 (file)
index 0000000..7131524
--- /dev/null
@@ -0,0 +1,15 @@
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+       /* Enable D-cache. I-cache is already enabled in start.S */
+       dcache_enable();
+}
+#endif
diff --git a/arch/arm/cpu/armv7/iproc-common/timer.c b/arch/arm/cpu/armv7/iproc-common/timer.c
new file mode 100644 (file)
index 0000000..373d8ec
--- /dev/null
@@ -0,0 +1,130 @@
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <asm/io.h>
+#include <asm/iproc-common/timer.h>
+#include <asm/iproc-common/sysmap.h>
+
+static inline uint64_t timer_global_read(void)
+{
+       uint64_t cur_tick;
+       uint32_t count_h;
+       uint32_t count_l;
+
+       do {
+               count_h = readl(IPROC_PERIPH_GLB_TIM_REG_BASE +
+                               TIMER_GLB_HI_OFFSET);
+               count_l = readl(IPROC_PERIPH_GLB_TIM_REG_BASE +
+                               TIMER_GLB_LOW_OFFSET);
+               cur_tick = readl(IPROC_PERIPH_GLB_TIM_REG_BASE +
+                                TIMER_GLB_HI_OFFSET);
+       } while (cur_tick != count_h);
+
+       return (cur_tick << 32) + count_l;
+}
+
+void timer_global_init(void)
+{
+       writel(0, IPROC_PERIPH_GLB_TIM_REG_BASE + TIMER_GLB_CTRL_OFFSET);
+       writel(0, IPROC_PERIPH_GLB_TIM_REG_BASE + TIMER_GLB_LOW_OFFSET);
+       writel(0, IPROC_PERIPH_GLB_TIM_REG_BASE + TIMER_GLB_HI_OFFSET);
+       writel(TIMER_GLB_TIM_CTRL_TIM_EN,
+              IPROC_PERIPH_GLB_TIM_REG_BASE + TIMER_GLB_CTRL_OFFSET);
+}
+
+int timer_init(void)
+{
+       timer_global_init();
+       return 0;
+}
+
+unsigned long get_timer(unsigned long base)
+{
+       uint64_t count;
+       uint64_t ret;
+       uint64_t tim_clk;
+       uint64_t periph_clk;
+
+       count = timer_global_read();
+
+       /* default arm clk is 1GHz, periph_clk=arm_clk/2, tick per msec */
+       periph_clk = 500000;
+       tim_clk = lldiv(periph_clk,
+                       (((readl(IPROC_PERIPH_GLB_TIM_REG_BASE +
+                                TIMER_GLB_CTRL_OFFSET) &
+                       TIMER_GLB_TIM_CTRL_PRESC_MASK) >> 8) + 1));
+
+       ret = lldiv(count, (uint32_t)tim_clk);
+
+       /* returns msec */
+       return ret - base;
+}
+
+void __udelay(unsigned long usec)
+{
+       uint64_t cur_tick, end_tick;
+       uint64_t tim_clk;
+       uint64_t periph_clk;
+
+       /* default arm clk is 1GHz, periph_clk=arm_clk/2, tick per usec */
+       periph_clk = 500;
+
+       tim_clk = lldiv(periph_clk,
+                       (((readl(IPROC_PERIPH_GLB_TIM_REG_BASE +
+                                TIMER_GLB_CTRL_OFFSET) &
+                       TIMER_GLB_TIM_CTRL_PRESC_MASK) >> 8) + 1));
+
+       cur_tick = timer_global_read();
+
+       end_tick = tim_clk;
+       end_tick *= usec;
+       end_tick += cur_tick;
+
+       do {
+               cur_tick = timer_global_read();
+
+       } while (cur_tick < end_tick);
+}
+
+void timer_systick_init(uint32_t tick_ms)
+{
+       /* Disable timer and clear interrupt status*/
+       writel(0, IPROC_PERIPH_PVT_TIM_REG_BASE + TIMER_PVT_CTRL_OFFSET);
+       writel(TIMER_PVT_TIM_INT_STATUS_SET,
+              IPROC_PERIPH_PVT_TIM_REG_BASE + TIMER_PVT_STATUS_OFFSET);
+       writel((PLL_AXI_CLK/1000) * tick_ms,
+              IPROC_PERIPH_PVT_TIM_REG_BASE + TIMER_PVT_LOAD_OFFSET);
+       writel(TIMER_PVT_TIM_CTRL_INT_EN |
+              TIMER_PVT_TIM_CTRL_AUTO_RELD |
+              TIMER_PVT_TIM_CTRL_TIM_EN,
+              IPROC_PERIPH_PVT_TIM_REG_BASE + TIMER_PVT_CTRL_OFFSET);
+}
+
+void timer_systick_isr(void *data)
+{
+       writel(TIMER_PVT_TIM_INT_STATUS_SET,
+              IPROC_PERIPH_PVT_TIM_REG_BASE + TIMER_PVT_STATUS_OFFSET);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value in msec.
+ */
+unsigned long long get_ticks(void)
+{
+       return get_timer(0);
+}
+
+/*
+ * This is used in conjuction with get_ticks, which returns msec as ticks.
+ * Here we just return ticks/sec = msec/sec = 1000
+ */
+ulong get_tbclk(void)
+{
+       return 1000;
+}
diff --git a/arch/arm/cpu/armv7/keystone/Kconfig b/arch/arm/cpu/armv7/keystone/Kconfig
new file mode 100644 (file)
index 0000000..24d0cbe
--- /dev/null
@@ -0,0 +1,24 @@
+if ARCH_KEYSTONE
+
+choice
+       prompt "TI Keystone board select"
+
+config TARGET_K2HK_EVM
+       bool "TI Keystone 2 Kepler/Hawking EVM"
+
+config TARGET_K2E_EVM
+       bool "TI Keystone 2 Edison EVM"
+
+endchoice
+
+config SYS_CPU
+       string
+       default "armv7"
+
+config SYS_SOC
+       string
+       default "keystone"
+
+source "board/ti/ks2_evm/Kconfig"
+
+endif
index 42092e1..31f6661 100644 (file)
@@ -17,6 +17,22 @@ const struct keystone_pll_regs keystone_pll_regs[] = {
        [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
 };
 
+int dev_speeds[] = {
+       SPD800,
+       SPD850,
+       SPD1000,
+       SPD1250,
+       SPD1350,
+       SPD1400,
+       SPD1500,
+       SPD1400,
+       SPD1350,
+       SPD1250,
+       SPD1000,
+       SPD850,
+       SPD800
+};
+
 /**
  * pll_freq_get - get pll frequency
  * Fout = Fref * NF(mult) / NR(prediv) / OD
index 96a9f72..1591960 100644 (file)
@@ -19,6 +19,38 @@ const struct keystone_pll_regs keystone_pll_regs[] = {
        [DDR3B_PLL]     = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
 };
 
+int dev_speeds[] = {
+       SPD800,
+       SPD1000,
+       SPD1200,
+       SPD800,
+       SPD800,
+       SPD800,
+       SPD800,
+       SPD800,
+       SPD1200,
+       SPD1000,
+       SPD800,
+       SPD800,
+       SPD800,
+};
+
+int arm_speeds[] = {
+       SPD800,
+       SPD1000,
+       SPD1200,
+       SPD1350,
+       SPD1400,
+       SPD800,
+       SPD1400,
+       SPD1350,
+       SPD1200,
+       SPD1000,
+       SPD800,
+       SPD800,
+       SPD800,
+};
+
 /**
  * pll_freq_get - get pll frequency
  * Fout = Fref * NF(mult) / NR(prediv) / OD
index 03c1d9f..30d76a6 100644 (file)
@@ -11,6 +11,8 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/clock_defs.h>
 
+#define MAX_SPEEDS             13
+
 static void wait_for_completion(const struct pll_init_data *data)
 {
        int i;
@@ -218,3 +220,44 @@ void init_plls(int num_pll, struct pll_init_data *config)
        for (i = 0; i < num_pll; i++)
                init_pll(&config[i]);
 }
+
+static int get_max_speed(u32 val, int *speeds)
+{
+       int j;
+
+       if (!val)
+               return speeds[0];
+
+       for (j = 1; j < MAX_SPEEDS; j++) {
+               if (val == 1)
+                       return speeds[j];
+               val >>= 1;
+       }
+
+       return SPD800;
+}
+
+#ifdef CONFIG_SOC_K2HK
+static u32 read_efuse_bootrom(void)
+{
+       return (cpu_revision() > 1) ? __raw_readl(KS2_EFUSE_BOOTROM) :
+               __raw_readl(KS2_REV1_DEVSPEED);
+}
+#else
+static inline u32 read_efuse_bootrom(void)
+{
+       return __raw_readl(KS2_EFUSE_BOOTROM);
+}
+#endif
+
+inline int get_max_dev_speed(void)
+{
+       return get_max_speed(read_efuse_bootrom() & 0xffff, dev_speeds);
+}
+
+#ifndef CONFIG_SOC_K2E
+inline int get_max_arm_speed(void)
+{
+       return get_max_speed((read_efuse_bootrom() >> 16) & 0xffff, arm_speeds);
+}
+#endif
index 6dc9f8e..bf6effc 100644 (file)
@@ -10,3 +10,4 @@
 obj-y  := soc.o clock.o
 obj-$(CONFIG_SPL_BUILD)             += ddr.o
 obj-$(CONFIG_SECURE_BOOT)    += hab.o
+obj-$(CONFIG_MP)             += mp.o
index 7dd83ec..820b8d5 100644 (file)
@@ -71,6 +71,24 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 }
 #endif
 
+/* spi_num can be from 0 - SPI_MAX_NUM */
+int enable_spi_clk(unsigned char enable, unsigned spi_num)
+{
+       u32 reg;
+       u32 mask;
+
+       if (spi_num > SPI_MAX_NUM)
+               return -EINVAL;
+
+       mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
+       reg = __raw_readl(&imx_ccm->CCGR1);
+       if (enable)
+               reg |= mask;
+       else
+               reg &= ~mask;
+       __raw_writel(reg, &imx_ccm->CCGR1);
+       return 0;
+}
 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
 {
        u32 div;
@@ -214,7 +232,7 @@ static u32 get_uart_clk(void)
        u32 reg, uart_podf;
        u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
        reg = __raw_readl(&imx_ccm->cscdr1);
-#ifdef CONFIG_MX6SL
+#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
        if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
                freq = MXC_HCLK;
 #endif
@@ -282,7 +300,7 @@ static u32 get_emi_slow_clk(void)
        return root_freq / (emi_slow_podf + 1);
 }
 
-#ifdef CONFIG_MX6SL
+#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
 static u32 get_mmdc_ch0_clk(void)
 {
        u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
@@ -355,6 +373,27 @@ int enable_fec_anatop_clock(enum enet_freq freq)
        reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
        writel(reg, &anatop->pll_enet);
 
+#ifdef CONFIG_MX6SX
+       /*
+        * Set enet ahb clock to 200MHz
+        * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
+        */
+       reg = readl(&imx_ccm->chsccdr);
+       reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
+                | MXC_CCM_CHSCCDR_ENET_PODF_MASK
+                | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
+       /* PLL2 PFD2 */
+       reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
+       /* Div = 2*/
+       reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
+       reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
+       writel(reg, &imx_ccm->chsccdr);
+
+       /* Enable enet system clock */
+       reg = readl(&imx_ccm->CCGR3);
+       reg |= MXC_CCM_CCGR3_ENET_MASK;
+       writel(reg, &imx_ccm->CCGR3);
+#endif
        return 0;
 }
 #endif
@@ -437,6 +476,7 @@ static int enable_enet_pll(uint32_t en)
        return 0;
 }
 
+#ifndef CONFIG_MX6SX
 static void ungate_sata_clock(void)
 {
        struct mxc_ccm_reg *const imx_ccm =
@@ -445,6 +485,7 @@ static void ungate_sata_clock(void)
        /* Enable SATA clock. */
        setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
 }
+#endif
 
 static void ungate_pcie_clock(void)
 {
@@ -455,11 +496,13 @@ static void ungate_pcie_clock(void)
        setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
 }
 
+#ifndef CONFIG_MX6SX
 int enable_sata_clock(void)
 {
        ungate_sata_clock();
        return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
 }
+#endif
 
 int enable_pcie_clock(void)
 {
@@ -491,7 +534,9 @@ int enable_pcie_clock(void)
        clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
 
        /* Party time! Ungate the clock to the PCIe. */
+#ifndef CONFIG_MX6SX
        ungate_sata_clock();
+#endif
        ungate_pcie_clock();
 
        return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
@@ -573,6 +618,7 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
        return 0;
 }
 
+#ifndef CONFIG_MX6SX
 void enable_ipu_clock(void)
 {
        struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -581,6 +627,7 @@ void enable_ipu_clock(void)
        reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
        writel(reg, &mxc_ccm->CCGR3);
 }
+#endif
 /***************************************************/
 
 U_BOOT_CMD(
index 0434211..1ab69f6 100644 (file)
@@ -197,6 +197,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
        u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
        u16 CS0_END;
        u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
+       u8 coladdr;
        int clkper; /* clock period in picoseconds */
        int clock; /* clock freq in mHz */
        int cs;
@@ -422,8 +423,13 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
        mmdc0->mdor = reg;
 
        /* Step 5: Configure DDR physical parameters (density and burst len) */
+       coladdr = m->coladdr;
+       if (m->coladdr == 8)            /* 8-bit COL is 0x3 */
+               coladdr += 4;
+       else if (m->coladdr == 12)      /* 12-bit COL is 0x4 */
+               coladdr += 1;
        reg = (m->rowaddr - 11) << 24 |         /* ROW */
-             (m->coladdr - 9) << 20 |          /* COL */
+             (coladdr - 9) << 20 |             /* COL */
              (1 << 19) |                       /* Burst Length = 8 for DDR3 */
              (i->dsize << 16);                 /* DDR data bus size */
        mmdc0->mdctl = reg;
diff --git a/arch/arm/cpu/armv7/mx6/mp.c b/arch/arm/cpu/armv7/mx6/mp.c
new file mode 100644 (file)
index 0000000..9f034d6
--- /dev/null
@@ -0,0 +1,87 @@
+/*
+ * (C) Copyright 2014
+ * Gabriel Huau <contact@huau-gabriel.fr>
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/imx-regs.h>
+
+#define MAX_CPUS 4
+static struct src *src = (struct src *)SRC_BASE_ADDR;
+
+static uint32_t cpu_reset_mask[MAX_CPUS] = {
+       0, /* We don't really want to modify the cpu0 */
+       SRC_SCR_CORE_1_RESET_MASK,
+       SRC_SCR_CORE_2_RESET_MASK,
+       SRC_SCR_CORE_3_RESET_MASK
+};
+
+static uint32_t cpu_ctrl_mask[MAX_CPUS] = {
+       0, /* We don't really want to modify the cpu0 */
+       SRC_SCR_CORE_1_ENABLE_MASK,
+       SRC_SCR_CORE_2_ENABLE_MASK,
+       SRC_SCR_CORE_3_ENABLE_MASK
+};
+
+int cpu_reset(int nr)
+{
+       /* Software reset of the CPU N */
+       src->scr |= cpu_reset_mask[nr];
+       return 0;
+}
+
+int cpu_status(int nr)
+{
+       printf("core %d => %d\n", nr, !!(src->scr & cpu_ctrl_mask[nr]));
+       return 0;
+}
+
+int cpu_release(int nr, int argc, char *const argv[])
+{
+       uint32_t boot_addr;
+
+       boot_addr = simple_strtoul(argv[0], NULL, 16);
+
+       switch (nr) {
+       case 1:
+               src->gpr3 = boot_addr;
+               break;
+       case 2:
+               src->gpr5 = boot_addr;
+               break;
+       case 3:
+               src->gpr7 = boot_addr;
+               break;
+       default:
+               return 1;
+       }
+
+       /* CPU N is ready to start */
+       src->scr |= cpu_ctrl_mask[nr];
+
+       return 0;
+}
+
+int is_core_valid(unsigned int core)
+{
+       uint32_t nr_cores = get_nr_cpus();
+
+       if (core > nr_cores)
+               return 0;
+
+       return 1;
+}
+
+int cpu_disable(int nr)
+{
+       /* Disable the CPU N */
+       src->scr &= ~cpu_ctrl_mask[nr];
+       return 0;
+}
index f20bdeb..ac84a1f 100644 (file)
@@ -35,6 +35,12 @@ struct scu_regs {
        u32     fpga_rev;
 };
 
+u32 get_nr_cpus(void)
+{
+       struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
+       return readl(&scu->config) & 3;
+}
+
 u32 get_cpu_rev(void)
 {
        struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
@@ -79,9 +85,15 @@ u32 __weak get_board_rev(void)
 void init_aips(void)
 {
        struct aipstz_regs *aips1, *aips2;
+#ifdef CONFIG_MX6SX
+       struct aipstz_regs *aips3;
+#endif
 
        aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
        aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
+#ifdef CONFIG_MX6SX
+       aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
+#endif
 
        /*
         * Set all MPROTx to be non-bufferable, trusted for R/W,
@@ -107,6 +119,26 @@ void init_aips(void)
        writel(0x00000000, &aips2->opacr2);
        writel(0x00000000, &aips2->opacr3);
        writel(0x00000000, &aips2->opacr4);
+
+#ifdef CONFIG_MX6SX
+       /*
+        * Set all MPROTx to be non-bufferable, trusted for R/W,
+        * not forced to user-mode.
+        */
+       writel(0x77777777, &aips3->mprot0);
+       writel(0x77777777, &aips3->mprot1);
+
+       /*
+        * Set all OPACRx to be non-bufferable, not require
+        * supervisor privilege level for access,allow for
+        * write access and untrusted master access.
+        */
+       writel(0x00000000, &aips3->opacr0);
+       writel(0x00000000, &aips3->opacr1);
+       writel(0x00000000, &aips3->opacr2);
+       writel(0x00000000, &aips3->opacr3);
+       writel(0x00000000, &aips3->opacr4);
+#endif
 }
 
 static void clear_ldo_ramp(void)
@@ -311,6 +343,10 @@ void s_init(void)
        u32 mask480;
        u32 mask528;
 
+
+       if (is_cpu_type(MXC_CPU_MX6SX))
+               return;
+
        /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
         * to make sure PFD is working right, otherwise, PFDs may
         * not output clock after reset, MX6DL and MX6SL have added 396M pfd
index 71c0cc8..c8e9bc8 100644 (file)
@@ -242,46 +242,10 @@ static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs)
               __udelay(130);
 }
 
-static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
-{
-       struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-
-       u32 fifo_reg;
-
-       fifo_reg = readl(&emif->emif_ddr_fifo_misaligned_clear_1);
-       writel(fifo_reg | 0x00000100,
-              &emif->emif_ddr_fifo_misaligned_clear_1);
-
-       fifo_reg = readl(&emif->emif_ddr_fifo_misaligned_clear_2);
-       writel(fifo_reg | 0x00000100,
-              &emif->emif_ddr_fifo_misaligned_clear_2);
-
-       /* Launch Full leveling */
-       writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
-
-       /* Wait till full leveling is complete */
-       readl(&emif->emif_rd_wr_lvl_ctl);
-             __udelay(130);
-
-       /* Read data eye leveling no of samples */
-       config_data_eye_leveling_samples(base);
-
-       /*
-        * Disable leveling. This is because if leveling is kept
-        * enabled, then PHY triggers a false leveling during
-        * EMIF-idle scenario which results in wrong delay
-        * values getting updated. After this the EMIF becomes
-        * unaccessible. So disable it after the first time
-        */
-       writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl);
-}
-
 static void ddr3_leveling(u32 base, const struct emif_regs *regs)
 {
        if (is_omap54xx())
                omap5_ddr3_leveling(base, regs);
-       else
-               dra7_ddr3_leveling(base, regs);
 }
 
 static void ddr3_init(u32 base, const struct emif_regs *regs)
@@ -1383,7 +1347,7 @@ void sdram_init(void)
        }
 
        if (sdram_type == EMIF_SDRAM_TYPE_DDR3 &&
-           (!in_sdram && !warm_reset())) {
+           (!in_sdram && !warm_reset()) && (!is_dra7xx())) {
                if (emif1_enabled)
                        do_bug0039_workaround(EMIF1_BASE);
                if (emif2_enabled)
index 1b4477f..dd52e93 100644 (file)
@@ -140,6 +140,9 @@ void s_init(void)
 #endif
        prcm_init();
 #ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+       board_early_init_f();
+#endif
        /* For regular u-boot sdram_init() is called from dram_init() */
        sdram_init();
 #endif
index 745603d..ccd0c83 100644 (file)
@@ -22,6 +22,7 @@ SECTIONS
        .text      :
        {
                __start = .;
+               *(.vectors)
                arch/arm/cpu/armv7/start.o      (.text*)
                *(.text*)
        } >.sram
diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig
new file mode 100644 (file)
index 0000000..6578f0c
--- /dev/null
@@ -0,0 +1,107 @@
+if OMAP34XX
+
+choice
+       prompt "OMAP3 board select"
+
+config TARGET_AM3517_EVM
+       bool "AM3517 EVM"
+
+config TARGET_MT_VENTOUX
+       bool "TeeJet Mt.Ventoux"
+
+config TARGET_OMAP3_SDP3430
+       bool "TI OMAP3430 SDP"
+
+config TARGET_OMAP3_BEAGLE
+       bool "TI OMAP3 BeagleBoard"
+
+config TARGET_CM_T35
+       bool "CompuLab CM-T35"
+
+config TARGET_DEVKIT8000
+       bool "TimLL OMAP3 Devkit8000"
+
+config TARGET_OMAP3_EVM
+       bool "TI OMAP3 EVM"
+
+config TARGET_OMAP3_EVM_QUICK_MMC
+       bool "TI OMAP3 EVM Quick MMC"
+
+config TARGET_OMAP3_EVM_QUICK_NAND
+       bool "TI OMAP3 EVM Quick NAND"
+
+config TARGET_OMAP3_IGEP00X0
+       bool "IGEP"
+
+config TARGET_OMAP3_OVERO
+       bool "OMAP35xx Gumstix Overo"
+
+config TARGET_OMAP3_ZOOM1
+       bool "TI Zoom1"
+
+config TARGET_AM3517_CRANE
+       bool "am3517_crane"
+
+config TARGET_OMAP3_PANDORA
+       bool "OMAP3 Pandora"
+
+config TARGET_ECO5PK
+       bool "ECO5PK"
+
+config TARGET_DIG297
+       bool "DIG297"
+
+config TARGET_TRICORDER
+       bool "Tricorder"
+
+config TARGET_MCX
+       bool "MCX"
+
+config TARGET_OMAP3_LOGIC
+       bool "OMAP3 Logic"
+
+config TARGET_OMAP3_MVBLX
+       bool "OMAP3 MVBLX"
+
+config TARGET_NOKIA_RX51
+       bool "Nokia RX51"
+
+config TARGET_TAO3530
+       bool "TAO3530"
+
+config TARGET_TWISTER
+       bool "Twister"
+
+endchoice
+
+config SYS_CPU
+       string
+       default "armv7"
+
+config SYS_SOC
+       string
+       default "omap3"
+
+source "board/logicpd/am3517evm/Kconfig"
+source "board/teejet/mt_ventoux/Kconfig"
+source "board/ti/sdp3430/Kconfig"
+source "board/ti/beagle/Kconfig"
+source "board/compulab/cm_t35/Kconfig"
+source "board/timll/devkit8000/Kconfig"
+source "board/ti/evm/Kconfig"
+source "board/isee/igep00x0/Kconfig"
+source "board/overo/Kconfig"
+source "board/logicpd/zoom1/Kconfig"
+source "board/ti/am3517crane/Kconfig"
+source "board/pandora/Kconfig"
+source "board/8dtech/eco5pk/Kconfig"
+source "board/comelit/dig297/Kconfig"
+source "board/corscience/tricorder/Kconfig"
+source "board/htkw/mcx/Kconfig"
+source "board/logicpd/omap3som/Kconfig"
+source "board/matrix_vision/mvblx/Kconfig"
+source "board/nokia/rx51/Kconfig"
+source "board/technexion/tao3530/Kconfig"
+source "board/technexion/twister/Kconfig"
+
+endif
diff --git a/arch/arm/cpu/armv7/omap4/Kconfig b/arch/arm/cpu/armv7/omap4/Kconfig
new file mode 100644 (file)
index 0000000..20d2c11
--- /dev/null
@@ -0,0 +1,29 @@
+if OMAP44XX
+
+choice
+       prompt "OMAP4 board select"
+
+config TARGET_DUOVERO
+       bool "OMAP4430 Gumstix Duovero"
+
+config TARGET_OMAP4_PANDA
+       bool "TI OMAP4 PandaBoard"
+
+config TARGET_OMAP4_SDP4430
+       bool "TI OMAP4 SDP4430"
+
+endchoice
+
+config SYS_CPU
+       string
+       default "armv7"
+
+config SYS_SOC
+       string
+       default "omap4"
+
+source "board/gumstix/duovero/Kconfig"
+source "board/ti/panda/Kconfig"
+source "board/ti/sdp4430/Kconfig"
+
+endif
diff --git a/arch/arm/cpu/armv7/omap5/Kconfig b/arch/arm/cpu/armv7/omap5/Kconfig
new file mode 100644 (file)
index 0000000..be80393
--- /dev/null
@@ -0,0 +1,29 @@
+if OMAP54XX
+
+choice
+       prompt "OMAP5 board select"
+
+config TARGET_CM_T54
+       bool "CompuLab CM-T54"
+
+config TARGET_OMAP5_UEVM
+       bool "TI OMAP5 uEVM board"
+
+config TARGET_DRA7XX_EVM
+       bool "TI DRA7XX"
+
+endchoice
+
+config SYS_CPU
+       string
+       default "armv7"
+
+config SYS_SOC
+       string
+       default "omap5"
+
+source "board/compulab/cm_t54/Kconfig"
+source "board/ti/omap5_uevm/Kconfig"
+source "board/ti/dra7xx/Kconfig"
+
+endif
index 4baca11..ed89f85 100644 (file)
@@ -556,7 +556,7 @@ const struct ctrl_ioregs ioregs_dra7xx_es1 = {
        .ctrl_ddrio_1 = 0x84210840,
        .ctrl_ddrio_2 = 0x84210000,
        .ctrl_emif_sdram_config_ext = 0x0001C1A7,
-       .ctrl_emif_sdram_config_ext_final = 0x000101A7,
+       .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
        .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
 };
 
index e2ebab8..9105121 100644 (file)
@@ -145,18 +145,18 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
        .sdram_tim1                     = 0xCCCF36B3,
        .sdram_tim2                     = 0x308F7FDA,
        .sdram_tim3                     = 0x027F88A8,
-       .read_idle_ctrl                 = 0x00050000,
+       .read_idle_ctrl                 = 0x00050001,
        .zq_config                      = 0x0007190B,
        .temp_alert_config              = 0x00000000,
-       .emif_ddr_phy_ctlr_1_init       = 0x0024400A,
-       .emif_ddr_phy_ctlr_1            = 0x0024400A,
+       .emif_ddr_phy_ctlr_1_init       = 0x0E24400A,
+       .emif_ddr_phy_ctlr_1            = 0x0E24400A,
        .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
-       .emif_ddr_ext_phy_ctrl_2        = 0x00B000B0,
-       .emif_ddr_ext_phy_ctrl_3        = 0x00B000B0,
-       .emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,
-       .emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,
+       .emif_ddr_ext_phy_ctrl_2        = 0x00BB00BB,
+       .emif_ddr_ext_phy_ctrl_3        = 0x00BB00BB,
+       .emif_ddr_ext_phy_ctrl_4        = 0x00BB00BB,
+       .emif_ddr_ext_phy_ctrl_5        = 0x00BB00BB,
        .emif_rd_wr_lvl_rmp_win         = 0x00000000,
-       .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
+       .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
        .emif_rd_wr_lvl_ctl             = 0x00000000,
        .emif_rd_wr_exec_thresh         = 0x00000305
 };
@@ -169,18 +169,18 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
        .sdram_tim1                     = 0xCCCF36B3,
        .sdram_tim2                     = 0x308F7FDA,
        .sdram_tim3                     = 0x027F88A8,
-       .read_idle_ctrl                 = 0x00050000,
+       .read_idle_ctrl                 = 0x00050001,
        .zq_config                      = 0x0007190B,
        .temp_alert_config              = 0x00000000,
-       .emif_ddr_phy_ctlr_1_init       = 0x0024400A,
-       .emif_ddr_phy_ctlr_1            = 0x0024400A,
+       .emif_ddr_phy_ctlr_1_init       = 0x0E24400A,
+       .emif_ddr_phy_ctlr_1            = 0x0E24400A,
        .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
-       .emif_ddr_ext_phy_ctrl_2        = 0x00B000B0,
-       .emif_ddr_ext_phy_ctrl_3        = 0x00B000B0,
-       .emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,
-       .emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,
+       .emif_ddr_ext_phy_ctrl_2        = 0x00BB00BB,
+       .emif_ddr_ext_phy_ctrl_3        = 0x00BB00BB,
+       .emif_ddr_ext_phy_ctrl_4        = 0x00BB00BB,
+       .emif_ddr_ext_phy_ctrl_5        = 0x00BB00BB,
        .emif_rd_wr_lvl_rmp_win         = 0x00000000,
-       .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
+       .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
        .emif_rd_wr_lvl_ctl             = 0x00000000,
        .emif_rd_wr_exec_thresh         = 0x00000305
 };
@@ -394,24 +394,24 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
 
 const u32
 dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
-       0x00B000B0,
-       0x00400040,
-       0x00400040,
-       0x00400040,
-       0x00400040,
-       0x00400040,
-       0x00800080,
-       0x00800080,
-       0x00800080,
-       0x00800080,
-       0x00800080,
+       0x00BB00BB,
+       0x00440044,
+       0x00440044,
+       0x00440044,
+       0x00440044,
+       0x00440044,
+       0x007F007F,
+       0x007F007F,
+       0x007F007F,
+       0x007F007F,
+       0x007F007F,
        0x00600060,
        0x00600060,
        0x00600060,
        0x00600060,
        0x00600060,
-       0x00800080,
-       0x00800080,
+       0x00000000,
+       0x00600020,
        0x40010080,
        0x08102040,
        0x0,
@@ -439,7 +439,7 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
        0x00600060,
        0x00600060,
        0x00600060,
-       0x0,
+       0x00000000,
        0x00600020,
        0x40010080,
        0x08102040,
diff --git a/arch/arm/cpu/armv7/rmobile/Kconfig b/arch/arm/cpu/armv7/rmobile/Kconfig
new file mode 100644 (file)
index 0000000..55c620a
--- /dev/null
@@ -0,0 +1,37 @@
+if RMOBILE
+
+choice
+       prompt "Renesus ARM SoCs board select"
+
+config TARGET_ARMADILLO_800EVA
+       bool "armadillo 800 eva board"
+
+config TARGET_KOELSCH
+       bool "Koelsch board"
+
+config TARGET_LAGER
+       bool "Lager board"
+
+config TARGET_KZM9G
+       bool "KZM9D board"
+
+config TARGET_ALT
+       bool "Alt board"
+
+endchoice
+
+config SYS_CPU
+       string
+       default "armv7"
+
+config SYS_SOC
+       string
+       default "rmobile"
+
+source "board/atmark-techno/armadillo-800eva/Kconfig"
+source "board/renesas/koelsch/Kconfig"
+source "board/renesas/lager/Kconfig"
+source "board/kmc/kzm9g/Kconfig"
+source "board/renesas/alt/Kconfig"
+
+endif
index 23d697d..158501a 100644 (file)
@@ -110,8 +110,8 @@ void cm_basic_init(const cm_config_t *cfg)
         * gatting off the rest of the periperal clocks.
         */
        writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
-               readl(&clock_manager_base->per_pll_en),
-               &clock_manager_base->per_pll_en);
+               readl(&clock_manager_base->per_pll.en),
+               &clock_manager_base->per_pll.en);
 
        /* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */
        writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK |
@@ -120,12 +120,12 @@ void cm_basic_init(const cm_config_t *cfg)
                CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK |
                CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK |
                CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK,
-               &clock_manager_base->main_pll_en);
+               &clock_manager_base->main_pll.en);
 
-       writel(0, &clock_manager_base->sdr_pll_en);
+       writel(0, &clock_manager_base->sdr_pll.en);
 
        /* now we can gate off the rest of the peripheral clocks */
-       writel(0, &clock_manager_base->per_pll_en);
+       writel(0, &clock_manager_base->per_pll.en);
 
        /* Put all plls in bypass */
        cm_write_bypass(
@@ -142,11 +142,11 @@ void cm_basic_init(const cm_config_t *cfg)
         * Some code might have messed with them.
         */
        writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE,
-              &clock_manager_base->main_pll_vco);
+              &clock_manager_base->main_pll.vco);
        writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE,
-              &clock_manager_base->per_pll_vco);
+              &clock_manager_base->per_pll.vco);
        writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE,
-              &clock_manager_base->sdr_pll_vco);
+              &clock_manager_base->sdr_pll.vco);
 
        /*
         * The clocks to the flash devices and the L4_MAIN clocks can
@@ -156,14 +156,14 @@ void cm_basic_init(const cm_config_t *cfg)
         * after exiting safe mode but before ungating the clocks.
         */
        writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE,
-              &clock_manager_base->per_pll_src);
+              &clock_manager_base->per_pll.src);
        writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE,
-              &clock_manager_base->main_pll_l4src);
+              &clock_manager_base->main_pll.l4src);
 
        /* read back for the required 5 us delay. */
-       readl(&clock_manager_base->main_pll_vco);
-       readl(&clock_manager_base->per_pll_vco);
-       readl(&clock_manager_base->sdr_pll_vco);
+       readl(&clock_manager_base->main_pll.vco);
+       readl(&clock_manager_base->per_pll.vco);
+       readl(&clock_manager_base->sdr_pll.vco);
 
 
        /*
@@ -172,60 +172,59 @@ void cm_basic_init(const cm_config_t *cfg)
         */
        writel(cfg->main_vco_base | CLEAR_BGP_EN_PWRDN |
                CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
-               &clock_manager_base->main_pll_vco);
+               &clock_manager_base->main_pll.vco);
 
        writel(cfg->peri_vco_base | CLEAR_BGP_EN_PWRDN |
                CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
-               &clock_manager_base->per_pll_vco);
+               &clock_manager_base->per_pll.vco);
 
        writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
                CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
                cfg->sdram_vco_base | CLEAR_BGP_EN_PWRDN |
                CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
-               &clock_manager_base->sdr_pll_vco);
+               &clock_manager_base->sdr_pll.vco);
 
        /*
         * Time starts here
         * must wait 7 us from BGPWRDN_SET(0) to VCO_ENABLE_SET(1)
         */
-       reset_timer();
        start = get_timer(0);
        /* timeout in unit of us as CONFIG_SYS_HZ = 1000*1000 */
        timeout = 7;
 
        /* main mpu */
-       writel(cfg->mpuclk, &clock_manager_base->main_pll_mpuclk);
+       writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);
 
        /* main main clock */
-       writel(cfg->mainclk, &clock_manager_base->main_pll_mainclk);
+       writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk);
 
        /* main for dbg */
-       writel(cfg->dbgatclk, &clock_manager_base->main_pll_dbgatclk);
+       writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk);
 
        /* main for cfgs2fuser0clk */
        writel(cfg->cfg2fuser0clk,
-              &clock_manager_base->main_pll_cfgs2fuser0clk);
+              &clock_manager_base->main_pll.cfgs2fuser0clk);
 
        /* Peri emac0 50 MHz default to RMII */
-       writel(cfg->emac0clk, &clock_manager_base->per_pll_emac0clk);
+       writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk);
 
        /* Peri emac1 50 MHz default to RMII */
-       writel(cfg->emac1clk, &clock_manager_base->per_pll_emac1clk);
+       writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk);
 
        /* Peri QSPI */
-       writel(cfg->mainqspiclk, &clock_manager_base->main_pll_mainqspiclk);
+       writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk);
 
-       writel(cfg->perqspiclk, &clock_manager_base->per_pll_perqspiclk);
+       writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk);
 
        /* Peri pernandsdmmcclk */
        writel(cfg->pernandsdmmcclk,
-              &clock_manager_base->per_pll_pernandsdmmcclk);
+              &clock_manager_base->per_pll.pernandsdmmcclk);
 
        /* Peri perbaseclk */
-       writel(cfg->perbaseclk, &clock_manager_base->per_pll_perbaseclk);
+       writel(cfg->perbaseclk, &clock_manager_base->per_pll.perbaseclk);
 
        /* Peri s2fuser1clk */
-       writel(cfg->s2fuser1clk, &clock_manager_base->per_pll_s2fuser1clk);
+       writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk);
 
        /* 7 us must have elapsed before we can enable the VCO */
        while (get_timer(start) < timeout)
@@ -234,29 +233,29 @@ void cm_basic_init(const cm_config_t *cfg)
        /* Enable vco */
        /* main pll vco */
        writel(cfg->main_vco_base | VCO_EN_BASE,
-              &clock_manager_base->main_pll_vco);
+              &clock_manager_base->main_pll.vco);
 
        /* periferal pll */
        writel(cfg->peri_vco_base | VCO_EN_BASE,
-              &clock_manager_base->per_pll_vco);
+              &clock_manager_base->per_pll.vco);
 
        /* sdram pll vco */
        writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
                CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
                cfg->sdram_vco_base | VCO_EN_BASE,
-               &clock_manager_base->sdr_pll_vco);
+               &clock_manager_base->sdr_pll.vco);
 
        /* L3 MP and L3 SP */
-       writel(cfg->maindiv, &clock_manager_base->main_pll_maindiv);
+       writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv);
 
-       writel(cfg->dbgdiv, &clock_manager_base->main_pll_dbgdiv);
+       writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv);
 
-       writel(cfg->tracediv, &clock_manager_base->main_pll_tracediv);
+       writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv);
 
        /* L4 MP, L4 SP, can0, and can1 */
-       writel(cfg->perdiv, &clock_manager_base->per_pll_div);
+       writel(cfg->perdiv, &clock_manager_base->per_pll.div);
 
-       writel(cfg->gpiodiv, &clock_manager_base->per_pll_gpiodiv);
+       writel(cfg->gpiodiv, &clock_manager_base->per_pll.gpiodiv);
 
 #define LOCKED_MASK \
        (CLKMGR_INTER_SDRPLLLOCKED_MASK  | \
@@ -267,70 +266,70 @@ void cm_basic_init(const cm_config_t *cfg)
 
        /* write the sdram clock counters before toggling outreset all */
        writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK,
-              &clock_manager_base->sdr_pll_ddrdqsclk);
+              &clock_manager_base->sdr_pll.ddrdqsclk);
 
        writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK,
-              &clock_manager_base->sdr_pll_ddr2xdqsclk);
+              &clock_manager_base->sdr_pll.ddr2xdqsclk);
 
        writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK,
-              &clock_manager_base->sdr_pll_ddrdqclk);
+              &clock_manager_base->sdr_pll.ddrdqclk);
 
        writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK,
-              &clock_manager_base->sdr_pll_s2fuser2clk);
+              &clock_manager_base->sdr_pll.s2fuser2clk);
 
        /*
         * after locking, but before taking out of bypass
         * assert/deassert outresetall
         */
-       uint32_t mainvco = readl(&clock_manager_base->main_pll_vco);
+       uint32_t mainvco = readl(&clock_manager_base->main_pll.vco);
 
        /* assert main outresetall */
        writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
-              &clock_manager_base->main_pll_vco);
+              &clock_manager_base->main_pll.vco);
 
-       uint32_t periphvco = readl(&clock_manager_base->per_pll_vco);
+       uint32_t periphvco = readl(&clock_manager_base->per_pll.vco);
 
        /* assert pheriph outresetall */
        writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
-              &clock_manager_base->per_pll_vco);
+              &clock_manager_base->per_pll.vco);
 
        /* assert sdram outresetall */
        writel(cfg->sdram_vco_base | VCO_EN_BASE|
                CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(1),
-               &clock_manager_base->sdr_pll_vco);
+               &clock_manager_base->sdr_pll.vco);
 
        /* deassert main outresetall */
        writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
-              &clock_manager_base->main_pll_vco);
+              &clock_manager_base->main_pll.vco);
 
        /* deassert pheriph outresetall */
        writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
-              &clock_manager_base->per_pll_vco);
+              &clock_manager_base->per_pll.vco);
 
        /* deassert sdram outresetall */
        writel(CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
                cfg->sdram_vco_base | VCO_EN_BASE,
-               &clock_manager_base->sdr_pll_vco);
+               &clock_manager_base->sdr_pll.vco);
 
        /*
         * now that we've toggled outreset all, all the clocks
         * are aligned nicely; so we can change any phase.
         */
        cm_write_with_phase(cfg->ddrdqsclk,
-                           (uint32_t)&clock_manager_base->sdr_pll_ddrdqsclk,
+                           (uint32_t)&clock_manager_base->sdr_pll.ddrdqsclk,
                            CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
 
        /* SDRAM DDR2XDQSCLK */
        cm_write_with_phase(cfg->ddr2xdqsclk,
-                           (uint32_t)&clock_manager_base->sdr_pll_ddr2xdqsclk,
+                           (uint32_t)&clock_manager_base->sdr_pll.ddr2xdqsclk,
                            CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
 
        cm_write_with_phase(cfg->ddrdqclk,
-                           (uint32_t)&clock_manager_base->sdr_pll_ddrdqclk,
+                           (uint32_t)&clock_manager_base->sdr_pll.ddrdqclk,
                            CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
 
        cm_write_with_phase(cfg->s2fuser2clk,
-                           (uint32_t)&clock_manager_base->sdr_pll_s2fuser2clk,
+                           (uint32_t)&clock_manager_base->sdr_pll.s2fuser2clk,
                            CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
 
        /* Take all three PLLs out of bypass when safe mode is cleared. */
@@ -351,11 +350,11 @@ void cm_basic_init(const cm_config_t *cfg)
         * now that safe mode is clear with clocks gated
         * it safe to change the source mux for the flashes the the L4_MAIN
         */
-       writel(cfg->persrc, &clock_manager_base->per_pll_src);
-       writel(cfg->l4src, &clock_manager_base->main_pll_l4src);
+       writel(cfg->persrc, &clock_manager_base->per_pll.src);
+       writel(cfg->l4src, &clock_manager_base->main_pll.l4src);
 
        /* Now ungate non-hw-managed clocks */
-       writel(~0, &clock_manager_base->main_pll_en);
-       writel(~0, &clock_manager_base->per_pll_en);
-       writel(~0, &clock_manager_base->sdr_pll_en);
+       writel(~0, &clock_manager_base->main_pll.en);
+       writel(~0, &clock_manager_base->per_pll.en);
+       writel(~0, &clock_manager_base->sdr_pll.en);
 }
index 3d18491..2a99c72 100644 (file)
@@ -6,3 +6,6 @@
 ifndef CONFIG_SPL_BUILD
 ALL-y  += u-boot.img
 endif
+
+# Added for handoff support
+PLATFORM_RELFLAGS += -Iboard/$(VENDOR)/$(BOARD)
index 5268f2c..ecae393 100644 (file)
@@ -6,6 +6,8 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <miiphy.h>
+#include <netdev.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -38,3 +40,18 @@ int misc_init_r(void)
 {
        return 0;
 }
+
+
+/*
+ * DesignWare Ethernet initialization
+ */
+int cpu_eth_init(bd_t *bis)
+{
+#if !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) && !defined(CONFIG_SPL_BUILD)
+       /* initialize and register the emac */
+       return designware_initialize(CONFIG_EMAC_BASE,
+                                    CONFIG_PHY_INTERFACE_MODE);
+#else
+       return 0;
+#endif
+}
index 4bed19d..27efde6 100644 (file)
@@ -14,6 +14,8 @@
 #include <spl.h>
 #include <asm/arch/system_manager.h>
 #include <asm/arch/freeze_controller.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/scan_manager.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
index 4282beb..db9bdad 100644 (file)
@@ -16,6 +16,7 @@ SECTIONS
        . = ALIGN(4);
        .text   :
        {
+               *(.vectors)
                arch/arm/cpu/armv7/start.o      (.text*)
                *(.text*)
        } >.sdram
index 6c70639..e9721b2 100644 (file)
@@ -17,6 +17,9 @@ obj-$(CONFIG_SUN7I)   += clock_sun4i.o
 
 ifndef CONFIG_SPL_BUILD
 obj-y  += cpu_info.o
+ifdef CONFIG_ARMV7_PSCI
+obj-y  += psci.o
+endif
 endif
 
 ifdef CONFIG_SPL_BUILD
index 8f2cef3..f2cedbb 100644 (file)
@@ -129,6 +129,11 @@ int cpu_eth_init(bd_t *bis)
 {
        __maybe_unused int rc;
 
+#ifdef CONFIG_MACPWR
+       gpio_direction_output(CONFIG_MACPWR, 1);
+       mdelay(200);
+#endif
+
 #ifdef CONFIG_SUNXI_EMAC
        rc = sunxi_emac_initialize(bis);
        if (rc < 0) {
index b8b16cf..ecbdb01 100644 (file)
@@ -39,6 +39,10 @@ void clock_init_safe(void)
        setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA);
 #endif
        writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
+#ifdef CONFIG_SUNXI_AHCI
+       setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA);
+       setbits_le32(&ccm->pll6_cfg, 0x1 << CCM_PLL6_CTRL_SATA_EN_SHIFT);
+#endif
 }
 #endif
 
index 0f1ceec..584f742 100644 (file)
 #define CPU_CFG_CHIP_REV_B 0x3
 
 /*
- * Wait up to 1s for mask to be clear in given reg.
+ * Wait up to 1s for value to be set in given part of reg.
  */
-static void await_completion(u32 *reg, u32 mask)
+static void await_completion(u32 *reg, u32 mask, u32 val)
 {
        unsigned long tmo = timer_get_us() + 1000000;
 
-       while (readl(reg) & mask) {
+       while ((readl(reg) & mask) != val) {
                if (timer_get_us() > tmo)
                        panic("Timeout initialising DRAM\n");
        }
 }
 
+/*
+ * Wait up to 1s for mask to be clear in given reg.
+ */
+static inline void await_bits_clear(u32 *reg, u32 mask)
+{
+       await_completion(reg, mask, 0);
+}
+
+/*
+ * Wait up to 1s for mask to be set in given reg.
+ */
+static inline void await_bits_set(u32 *reg, u32 mask)
+{
+       await_completion(reg, mask, mask);
+}
+
+/*
+ * This performs the external DRAM reset by driving the RESET pin low and
+ * then high again. According to the DDR3 spec, the RESET pin needs to be
+ * kept low for at least 200 us.
+ */
 static void mctl_ddr3_reset(void)
 {
        struct sunxi_dram_reg *dram =
@@ -64,15 +85,28 @@ static void mctl_ddr3_reset(void)
        if ((reg_val & CPU_CFG_CHIP_VER_MASK) !=
            CPU_CFG_CHIP_VER(CPU_CFG_CHIP_REV_A)) {
                setbits_le32(&dram->mcr, DRAM_MCR_RESET);
-               udelay(2);
+               udelay(200);
                clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
        } else
 #endif
        {
                clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
-               udelay(2);
+               udelay(200);
                setbits_le32(&dram->mcr, DRAM_MCR_RESET);
        }
+       /* After the RESET pin is de-asserted, the DDR3 spec requires to wait
+        * for additional 500 us before driving the CKE pin (Clock Enable)
+        * high. The duration of this delay can be configured in the SDR_IDCR
+        * (Initialization Delay Configuration Register) and applied
+        * automatically by the DRAM controller during the DDR3 initialization
+        * step. But SDR_IDCR has limited range on sun4i/sun5i hardware and
+        * can't provide sufficient delay at DRAM clock frequencies higher than
+        * 524 MHz (while Allwinner A13 supports DRAM clock frequency up to
+        * 533 MHz according to the datasheet). Additionally, there is no
+        * official documentation for the SDR_IDCR register anywhere, and
+        * there is always a chance that we are interpreting it wrong.
+        * Better be safe than sorry, so add an explicit delay here. */
+       udelay(500);
 }
 
 static void mctl_set_drive(void)
@@ -102,6 +136,14 @@ static void mctl_itm_enable(void)
        clrbits_le32(&dram->ccr, DRAM_CCR_ITM_OFF);
 }
 
+static void mctl_itm_reset(void)
+{
+       mctl_itm_disable();
+       udelay(1); /* ITM reset needs a bit of delay */
+       mctl_itm_enable();
+       udelay(1);
+}
+
 static void mctl_enable_dll0(u32 phase)
 {
        struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
@@ -118,23 +160,28 @@ static void mctl_enable_dll0(u32 phase)
        udelay(22);
 }
 
+/* Get the number of DDR byte lanes */
+static u32 mctl_get_number_of_lanes(void)
+{
+       struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+       if ((readl(&dram->dcr) & DRAM_DCR_BUS_WIDTH_MASK) ==
+                               DRAM_DCR_BUS_WIDTH(DRAM_DCR_BUS_WIDTH_32BIT))
+               return 4;
+       else
+               return 2;
+}
+
 /*
  * Note: This differs from pm/standby in that it checks the bus width
  */
 static void mctl_enable_dllx(u32 phase)
 {
        struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
-       u32 i, n, bus_width;
+       u32 i, number_of_lanes;
 
-       bus_width = readl(&dram->dcr);
+       number_of_lanes = mctl_get_number_of_lanes();
 
-       if ((bus_width & DRAM_DCR_BUS_WIDTH_MASK) ==
-           DRAM_DCR_BUS_WIDTH(DRAM_DCR_BUS_WIDTH_32BIT))
-               n = DRAM_DCR_NR_DLLCR_32BIT;
-       else
-               n = DRAM_DCR_NR_DLLCR_16BIT;
-
-       for (i = 1; i < n; i++) {
+       for (i = 1; i <= number_of_lanes; i++) {
                clrsetbits_le32(&dram->dllcr[i], 0xf << 14,
                                (phase & 0xf) << 14);
                clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET,
@@ -143,12 +190,12 @@ static void mctl_enable_dllx(u32 phase)
        }
        udelay(2);
 
-       for (i = 1; i < n; i++)
+       for (i = 1; i <= number_of_lanes; i++)
                clrbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET |
                             DRAM_DLLCR_DISABLE);
        udelay(22);
 
-       for (i = 1; i < n; i++)
+       for (i = 1; i <= number_of_lanes; i++)
                clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_DISABLE,
                                DRAM_DLLCR_NRESET);
        udelay(22);
@@ -201,11 +248,20 @@ static void mctl_configure_hostport(void)
                writel(hpcr_value[i], &dram->hpcr[i]);
 }
 
-static void mctl_setup_dram_clock(u32 clk)
+static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
 {
        u32 reg_val;
        struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
+       /* PLL5P and PLL6 are the potential clock sources for MBUS */
+       u32 pll6x_div, pll5p_div;
+       u32 pll6x_clk = clock_get_pll6() / 1000000;
+       u32 pll5p_clk = clk / 24 * 48;
+       u32 pll5p_rate, pll6x_rate;
+#ifdef CONFIG_SUN7I
+       pll6x_clk *= 2; /* sun7i uses PLL6*2, sun5i uses just PLL6 */
+#endif
+
        /* setup DRAM PLL */
        reg_val = readl(&ccm->pll5_cfg);
        reg_val &= ~CCM_PLL5_CTRL_M_MASK;               /* set M to 0 (x1) */
@@ -213,41 +269,40 @@ static void mctl_setup_dram_clock(u32 clk)
        reg_val &= ~CCM_PLL5_CTRL_N_MASK;               /* set N to 0 (x0) */
        reg_val &= ~CCM_PLL5_CTRL_P_MASK;               /* set P to 0 (x1) */
        if (clk >= 540 && clk < 552) {
-               /* dram = 540MHz, pll5p = 540MHz */
+               /* dram = 540MHz, pll5p = 1080MHz */
+               pll5p_clk = 1080;
                reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
                reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
                reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15));
-               reg_val |= CCM_PLL5_CTRL_P(1);
        } else if (clk >= 512 && clk < 528) {
-               /* dram = 512MHz, pll5p = 384MHz */
+               /* dram = 512MHz, pll5p = 1536MHz */
+               pll5p_clk = 1536;
                reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));
                reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(4));
                reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16));
-               reg_val |= CCM_PLL5_CTRL_P(2);
        } else if (clk >= 496 && clk < 504) {
-               /* dram = 496MHz, pll5p = 372MHz */
+               /* dram = 496MHz, pll5p = 1488MHz */
+               pll5p_clk = 1488;
                reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));
                reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));
                reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31));
-               reg_val |= CCM_PLL5_CTRL_P(2);
        } else if (clk >= 468 && clk < 480) {
-               /* dram = 468MHz, pll5p = 468MHz */
+               /* dram = 468MHz, pll5p = 936MHz */
+               pll5p_clk = 936;
                reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
                reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
                reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13));
-               reg_val |= CCM_PLL5_CTRL_P(1);
        } else if (clk >= 396 && clk < 408) {
-               /* dram = 396MHz, pll5p = 396MHz */
+               /* dram = 396MHz, pll5p = 792MHz */
+               pll5p_clk = 792;
                reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
                reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
                reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11));
-               reg_val |= CCM_PLL5_CTRL_P(1);
        } else  {
                /* any other frequency that is a multiple of 24 */
                reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
                reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));
                reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24));
-               reg_val |= CCM_PLL5_CTRL_P(CCM_PLL5_CTRL_P_X(2));
        }
        reg_val &= ~CCM_PLL5_CTRL_VCO_GAIN;             /* PLL VCO Gain off */
        reg_val |= CCM_PLL5_CTRL_EN;                    /* PLL On */
@@ -264,20 +319,30 @@ static void mctl_setup_dram_clock(u32 clk)
        clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
 #endif
 
-#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
        /* setup MBUS clock */
-       reg_val = CCM_MBUS_CTRL_GATE |
-#ifdef CONFIG_SUN7I
-                 CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL6) |
-                 CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(2)) |
-                 CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2));
-#else /* defined(CONFIG_SUN5I) */
-                 CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL5) |
-                 CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) |
-                 CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2));
-#endif
+       if (!mbus_clk)
+               mbus_clk = 300;
+       pll6x_div = DIV_ROUND_UP(pll6x_clk, mbus_clk);
+       pll5p_div = DIV_ROUND_UP(pll5p_clk, mbus_clk);
+       pll6x_rate = pll6x_clk / pll6x_div;
+       pll5p_rate = pll5p_clk / pll5p_div;
+
+       if (pll6x_div <= 16 && pll6x_rate > pll5p_rate) {
+               /* use PLL6 as the MBUS clock source */
+               reg_val = CCM_MBUS_CTRL_GATE |
+                         CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL6) |
+                         CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) |
+                         CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(pll6x_div));
+       } else if (pll5p_div <= 16) {
+               /* use PLL5P as the MBUS clock source */
+               reg_val = CCM_MBUS_CTRL_GATE |
+                         CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL5) |
+                         CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) |
+                         CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(pll5p_div));
+       } else {
+               panic("Bad mbus_clk\n");
+       }
        writel(reg_val, &ccm->mbus_clk_cfg);
-#endif
 
        /*
         * open DRAMC AHB & DLL register clock
@@ -299,19 +364,48 @@ static void mctl_setup_dram_clock(u32 clk)
        udelay(22);
 }
 
+/*
+ * The data from rslrX and rdgrX registers (X=rank) is stored
+ * in a single 32-bit value using the following format:
+ *   bits [31:26] - DQS gating system latency for byte lane 3
+ *   bits [25:24] - DQS gating phase select for byte lane 3
+ *   bits [23:18] - DQS gating system latency for byte lane 2
+ *   bits [17:16] - DQS gating phase select for byte lane 2
+ *   bits [15:10] - DQS gating system latency for byte lane 1
+ *   bits [ 9:8 ] - DQS gating phase select for byte lane 1
+ *   bits [ 7:2 ] - DQS gating system latency for byte lane 0
+ *   bits [ 1:0 ] - DQS gating phase select for byte lane 0
+ */
+static void mctl_set_dqs_gating_delay(int rank, u32 dqs_gating_delay)
+{
+       struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+       u32 lane, number_of_lanes = mctl_get_number_of_lanes();
+       /* rank0 gating system latency (3 bits per lane: cycles) */
+       u32 slr = readl(rank == 0 ? &dram->rslr0 : &dram->rslr1);
+       /* rank0 gating phase select (2 bits per lane: 90, 180, 270, 360) */
+       u32 dgr = readl(rank == 0 ? &dram->rdgr0 : &dram->rdgr1);
+       for (lane = 0; lane < number_of_lanes; lane++) {
+               u32 tmp = dqs_gating_delay >> (lane * 8);
+               slr &= ~(7 << (lane * 3));
+               slr |= ((tmp >> 2) & 7) << (lane * 3);
+               dgr &= ~(3 << (lane * 2));
+               dgr |= (tmp & 3) << (lane * 2);
+       }
+       writel(slr, rank == 0 ? &dram->rslr0 : &dram->rslr1);
+       writel(dgr, rank == 0 ? &dram->rdgr0 : &dram->rdgr1);
+}
+
 static int dramc_scan_readpipe(void)
 {
        struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
        u32 reg_val;
 
        /* data training trigger */
-#ifdef CONFIG_SUN7I
        clrbits_le32(&dram->csr, DRAM_CSR_FAILED);
-#endif
        setbits_le32(&dram->ccr, DRAM_CCR_DATA_TRAINING);
 
        /* check whether data training process has completed */
-       await_completion(&dram->ccr, DRAM_CCR_DATA_TRAINING);
+       await_bits_clear(&dram->ccr, DRAM_CCR_DATA_TRAINING);
 
        /* check data training result */
        reg_val = readl(&dram->csr);
@@ -321,117 +415,6 @@ static int dramc_scan_readpipe(void)
        return 0;
 }
 
-static int dramc_scan_dll_para(void)
-{
-       struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
-       const u32 dqs_dly[7] = {0x3, 0x2, 0x1, 0x0, 0xe, 0xd, 0xc};
-       const u32 clk_dly[15] = {0x07, 0x06, 0x05, 0x04, 0x03,
-                                0x02, 0x01, 0x00, 0x08, 0x10,
-                                0x18, 0x20, 0x28, 0x30, 0x38};
-       u32 clk_dqs_count[15];
-       u32 dqs_i, clk_i, cr_i;
-       u32 max_val, min_val;
-       u32 dqs_index, clk_index;
-
-       /* Find DQS_DLY Pass Count for every CLK_DLY */
-       for (clk_i = 0; clk_i < 15; clk_i++) {
-               clk_dqs_count[clk_i] = 0;
-               clrsetbits_le32(&dram->dllcr[0], 0x3f << 6,
-                               (clk_dly[clk_i] & 0x3f) << 6);
-               for (dqs_i = 0; dqs_i < 7; dqs_i++) {
-                       for (cr_i = 1; cr_i < 5; cr_i++) {
-                               clrsetbits_le32(&dram->dllcr[cr_i],
-                                               0x4f << 14,
-                                               (dqs_dly[dqs_i] & 0x4f) << 14);
-                       }
-                       udelay(2);
-                       if (dramc_scan_readpipe() == 0)
-                               clk_dqs_count[clk_i]++;
-               }
-       }
-       /* Test DQS_DLY Pass Count for every CLK_DLY from up to down */
-       for (dqs_i = 15; dqs_i > 0; dqs_i--) {
-               max_val = 15;
-               min_val = 15;
-               for (clk_i = 0; clk_i < 15; clk_i++) {
-                       if (clk_dqs_count[clk_i] == dqs_i) {
-                               max_val = clk_i;
-                               if (min_val == 15)
-                                       min_val = clk_i;
-                       }
-               }
-               if (max_val < 15)
-                       break;
-       }
-
-       /* Check if Find a CLK_DLY failed */
-       if (!dqs_i)
-               goto fail;
-
-       /* Find the middle index of CLK_DLY */
-       clk_index = (max_val + min_val) >> 1;
-       if ((max_val == (15 - 1)) && (min_val > 0))
-               /* if CLK_DLY[MCTL_CLK_DLY_COUNT] is very good, then the middle
-                * value can be more close to the max_val
-                */
-               clk_index = (15 + clk_index) >> 1;
-       else if ((max_val < (15 - 1)) && (min_val == 0))
-               /* if CLK_DLY[0] is very good, then the middle value can be more
-                * close to the min_val
-                */
-               clk_index >>= 1;
-       if (clk_dqs_count[clk_index] < dqs_i)
-               clk_index = min_val;
-
-       /* Find the middle index of DQS_DLY for the CLK_DLY got above, and Scan
-        * read pipe again
-        */
-       clrsetbits_le32(&dram->dllcr[0], 0x3f << 6,
-                       (clk_dly[clk_index] & 0x3f) << 6);
-       max_val = 7;
-       min_val = 7;
-       for (dqs_i = 0; dqs_i < 7; dqs_i++) {
-               clk_dqs_count[dqs_i] = 0;
-               for (cr_i = 1; cr_i < 5; cr_i++) {
-                       clrsetbits_le32(&dram->dllcr[cr_i],
-                                       0x4f << 14,
-                                       (dqs_dly[dqs_i] & 0x4f) << 14);
-               }
-               udelay(2);
-               if (dramc_scan_readpipe() == 0) {
-                       clk_dqs_count[dqs_i] = 1;
-                       max_val = dqs_i;
-                       if (min_val == 7)
-                               min_val = dqs_i;
-               }
-       }
-
-       if (max_val < 7) {
-               dqs_index = (max_val + min_val) >> 1;
-               if ((max_val == (7-1)) && (min_val > 0))
-                       dqs_index = (7 + dqs_index) >> 1;
-               else if ((max_val < (7-1)) && (min_val == 0))
-                       dqs_index >>= 1;
-               if (!clk_dqs_count[dqs_index])
-                       dqs_index = min_val;
-               for (cr_i = 1; cr_i < 5; cr_i++) {
-                       clrsetbits_le32(&dram->dllcr[cr_i],
-                                       0x4f << 14,
-                                       (dqs_dly[dqs_index] & 0x4f) << 14);
-               }
-               udelay(2);
-               return dramc_scan_readpipe();
-       }
-
-fail:
-       clrbits_le32(&dram->dllcr[0], 0x3f << 6);
-       for (cr_i = 1; cr_i < 5; cr_i++)
-               clrbits_le32(&dram->dllcr[cr_i], 0x4f << 14);
-       udelay(2);
-
-       return dramc_scan_readpipe();
-}
-
 static void dramc_clock_output_en(u32 on)
 {
 #if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
@@ -451,48 +434,164 @@ static void dramc_clock_output_en(u32 on)
 #endif
 }
 
-static const u16 tRFC_table[2][6] = {
-       /*       256Mb    512Mb    1Gb      2Gb      4Gb      8Gb      */
-       /* DDR2  75ns     105ns    127.5ns  195ns    327.5ns  invalid  */
-       {        77,      108,     131,     200,     336,     336 },
-       /* DDR3  invalid  90ns     110ns    160ns    300ns    350ns    */
-       {        93,      93,      113,     164,     308,     359 }
+/* tRFC in nanoseconds for different densities (from the DDR3 spec) */
+static const u16 tRFC_DDR3_table[6] = {
+       /* 256Mb    512Mb    1Gb      2Gb      4Gb      8Gb */
+          90,      90,      110,     160,     300,     350
 };
 
-static void dramc_set_autorefresh_cycle(u32 clk, u32 type, u32 density)
+static void dramc_set_autorefresh_cycle(u32 clk, u32 density)
 {
        struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
        u32 tRFC, tREFI;
 
-       tRFC = (tRFC_table[type][density] * clk + 1023) >> 10;
+       tRFC = (tRFC_DDR3_table[density] * clk + 999) / 1000;
        tREFI = (7987 * clk) >> 10;     /* <= 7.8us */
 
        writel(DRAM_DRR_TREFI(tREFI) | DRAM_DRR_TRFC(tRFC), &dram->drr);
 }
 
-unsigned long dramc_init(struct dram_para *para)
+/* Calculate the value for A11, A10, A9 bits in MR0 (write recovery) */
+static u32 ddr3_write_recovery(u32 clk)
+{
+       u32 twr_ns = 15; /* DDR3 spec says that it is 15ns for all speed bins */
+       u32 twr_ck = (twr_ns * clk + 999) / 1000;
+       if (twr_ck < 5)
+               return 1;
+       else if (twr_ck <= 8)
+               return twr_ck - 4;
+       else if (twr_ck <= 10)
+               return 5;
+       else
+               return 6;
+}
+
+/*
+ * If the dram->ppwrsctl (SDR_DPCR) register has the lowest bit set to 1, this
+ * means that DRAM is currently in self-refresh mode and retaining the old
+ * data. Since we have no idea what to do in this situation yet, just set this
+ * register to 0 and initialize DRAM in the same way as on any normal reboot
+ * (discarding whatever was stored there).
+ *
+ * Note: on sun7i hardware, the highest 16 bits need to be set to 0x1651 magic
+ * value for this write operation to have any effect. On sun5i hadware this
+ * magic value is not necessary. And on sun4i hardware the writes to this
+ * register seem to have no effect at all.
+ */
+static void mctl_disable_power_save(void)
+{
+       struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+       writel(0x16510000, &dram->ppwrsctl);
+}
+
+/*
+ * After the DRAM is powered up or reset, the DDR3 spec requires to wait at
+ * least 500 us before driving the CKE pin (Clock Enable) high. The dram->idct
+ * (SDR_IDCR) register appears to configure this delay, which gets applied
+ * right at the time when the DRAM initialization is activated in the
+ * 'mctl_ddr3_initialize' function.
+ */
+static void mctl_set_cke_delay(void)
+{
+       struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+
+       /* The CKE delay is represented in DRAM clock cycles, multiplied by N
+        * (where N=2 for sun4i/sun5i and N=3 for sun7i). Here it is set to
+        * the maximum possible value 0x1ffff, just like in the Allwinner's
+        * boot0 bootloader. The resulting delay value is somewhere between
+        * ~0.4 ms (sun5i with 648 MHz DRAM clock speed) and ~1.1 ms (sun7i
+        * with 360 MHz DRAM clock speed). */
+       setbits_le32(&dram->idcr, 0x1ffff);
+}
+
+/*
+ * This triggers the DRAM initialization. It performs sending the mode registers
+ * to the DRAM among other things. Very likely the ZQCL command is also getting
+ * executed (to do the initial impedance calibration on the DRAM side of the
+ * wire). The memory controller and the PHY must be already configured before
+ * calling this function.
+ */
+static void mctl_ddr3_initialize(void)
+{
+       struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+       setbits_le32(&dram->ccr, DRAM_CCR_INIT);
+       await_bits_clear(&dram->ccr, DRAM_CCR_INIT);
+}
+
+/*
+ * Perform impedance calibration on the DRAM controller side of the wire.
+ */
+static void mctl_set_impedance(u32 zq, u32 odt_en)
+{
+       struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+       u32 reg_val;
+       u32 zprog = zq & 0xFF, zdata = (zq >> 8) & 0xFFFFF;
+
+#ifndef CONFIG_SUN7I
+       /* Appears that some kind of automatically initiated default
+        * ZQ calibration is already in progress at this point on sun4i/sun5i
+        * hardware, but not on sun7i. So it is reasonable to wait for its
+        * completion before doing anything else. */
+       await_bits_set(&dram->zqsr, DRAM_ZQSR_ZDONE);
+#endif
+
+       /* ZQ calibration is not really useful unless ODT is enabled */
+       if (!odt_en)
+               return;
+
+#ifdef CONFIG_SUN7I
+       /* Enabling ODT in SDR_IOCR on sun7i hardware results in a deadlock
+        * unless bit 24 is set in SDR_ZQCR1. Not much is known about the
+        * SDR_ZQCR1 register, but there are hints indicating that it might
+        * be related to periodic impedance re-calibration. This particular
+        * magic value is borrowed from the Allwinner boot0 bootloader, and
+        * using it helps to avoid troubles */
+       writel((1 << 24) | (1 << 1), &dram->zqcr1);
+#endif
+
+       /* Needed at least for sun5i, because it does not self clear there */
+       clrbits_le32(&dram->zqcr0, DRAM_ZQCR0_ZCAL);
+
+       if (zdata) {
+               /* Set the user supplied impedance data */
+               reg_val = DRAM_ZQCR0_ZDEN | zdata;
+               writel(reg_val, &dram->zqcr0);
+               /* no need to wait, this takes effect immediately */
+       } else {
+               /* Do the calibration using the external resistor */
+               reg_val = DRAM_ZQCR0_ZCAL | DRAM_ZQCR0_IMP_DIV(zprog);
+               writel(reg_val, &dram->zqcr0);
+               /* Wait for the new impedance configuration to settle */
+               await_bits_set(&dram->zqsr, DRAM_ZQSR_ZDONE);
+       }
+
+       /* Needed at least for sun5i, because it does not self clear there */
+       clrbits_le32(&dram->zqcr0, DRAM_ZQCR0_ZCAL);
+
+       /* Set I/O configure register */
+       writel(DRAM_IOCR_ODT_EN(odt_en), &dram->iocr);
+}
+
+static unsigned long dramc_init_helper(struct dram_para *para)
 {
        struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
        u32 reg_val;
        u32 density;
        int ret_val;
 
-       /* check input dram parameter structure */
-       if (!para)
+       /*
+        * only single rank DDR3 is supported by this code even though the
+        * hardware can theoretically support DDR2 and up to two ranks
+        */
+       if (para->type != DRAM_MEMORY_TYPE_DDR3 || para->rank_num != 1)
                return 0;
 
        /* setup DRAM relative clock */
-       mctl_setup_dram_clock(para->clock);
+       mctl_setup_dram_clock(para->clock, para->mbus_clock);
 
-#ifdef CONFIG_SUN5I
        /* Disable any pad power save control */
-       writel(0, &dram->ppwrsctl);
-#endif
+       mctl_disable_power_save();
 
-       /* reset external DRAM */
-#ifndef CONFIG_SUN7I
-       mctl_ddr3_reset();
-#endif
        mctl_set_drive();
 
        /* dram clock off */
@@ -507,9 +606,7 @@ unsigned long dramc_init(struct dram_para *para)
        mctl_enable_dll0(para->tpr3);
 
        /* configure external DRAM */
-       reg_val = 0x0;
-       if (para->type == DRAM_MEMORY_TYPE_DDR3)
-               reg_val |= DRAM_DCR_TYPE_DDR3;
+       reg_val = DRAM_DCR_TYPE_DDR3;
        reg_val |= DRAM_DCR_IO_WIDTH(para->io_width >> 3);
 
        if (para->density == 256)
@@ -534,85 +631,41 @@ unsigned long dramc_init(struct dram_para *para)
        reg_val |= DRAM_DCR_MODE(DRAM_DCR_MODE_INTERLEAVE);
        writel(reg_val, &dram->dcr);
 
-#ifdef CONFIG_SUN7I
-       setbits_le32(&dram->zqcr1, (0x1 << 24) | (0x1 << 1));
-       if (para->tpr4 & 0x2)
-               clrsetbits_le32(&dram->zqcr1, (0x1 << 24), (0x1 << 1));
        dramc_clock_output_en(1);
-#endif
 
-#if (defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I))
-       /* set odt impendance divide ratio */
-       reg_val = ((para->zq) >> 8) & 0xfffff;
-       reg_val |= ((para->zq) & 0xff) << 20;
-       reg_val |= (para->zq) & 0xf0000000;
-       writel(reg_val, &dram->zqcr0);
-#endif
+       mctl_set_impedance(para->zq, para->odt_en);
 
-#ifdef CONFIG_SUN7I
-       /* Set CKE Delay to about 1ms */
-       setbits_le32(&dram->idcr, 0x1ffff);
-#endif
+       mctl_set_cke_delay();
 
-#ifdef CONFIG_SUN7I
-       if ((readl(&dram->ppwrsctl) & 0x1) != 0x1)
-               mctl_ddr3_reset();
-       else
-               setbits_le32(&dram->mcr, DRAM_MCR_RESET);
-#else
-       /* dram clock on */
-       dramc_clock_output_en(1);
-#endif
+       mctl_ddr3_reset();
 
        udelay(1);
 
-       await_completion(&dram->ccr, DRAM_CCR_INIT);
+       await_bits_clear(&dram->ccr, DRAM_CCR_INIT);
 
        mctl_enable_dllx(para->tpr3);
 
-#ifdef CONFIG_SUN4I
-       /* set odt impedance divide ratio */
-       reg_val = ((para->zq) >> 8) & 0xfffff;
-       reg_val |= ((para->zq) & 0xff) << 20;
-       reg_val |= (para->zq) & 0xf0000000;
-       writel(reg_val, &dram->zqcr0);
-#endif
-
-#ifdef CONFIG_SUN4I
-       /* set I/O configure register */
-       reg_val = 0x00cc0000;
-       reg_val |= (para->odt_en) & 0x3;
-       reg_val |= ((para->odt_en) & 0x3) << 30;
-       writel(reg_val, &dram->iocr);
-#endif
-
        /* set refresh period */
-       dramc_set_autorefresh_cycle(para->clock, para->type - 2, density);
+       dramc_set_autorefresh_cycle(para->clock, density);
 
        /* set timing parameters */
        writel(para->tpr0, &dram->tpr0);
        writel(para->tpr1, &dram->tpr1);
        writel(para->tpr2, &dram->tpr2);
 
-       if (para->type == DRAM_MEMORY_TYPE_DDR3) {
-               reg_val = DRAM_MR_BURST_LENGTH(0x0);
+       reg_val = DRAM_MR_BURST_LENGTH(0x0);
 #if (defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I))
-               reg_val |= DRAM_MR_POWER_DOWN;
+       reg_val |= DRAM_MR_POWER_DOWN;
 #endif
-               reg_val |= DRAM_MR_CAS_LAT(para->cas - 4);
-               reg_val |= DRAM_MR_WRITE_RECOVERY(0x5);
-       } else if (para->type == DRAM_MEMORY_TYPE_DDR2) {
-               reg_val = DRAM_MR_BURST_LENGTH(0x2);
-               reg_val |= DRAM_MR_CAS_LAT(para->cas);
-               reg_val |= DRAM_MR_WRITE_RECOVERY(0x5);
-       }
+       reg_val |= DRAM_MR_CAS_LAT(para->cas - 4);
+       reg_val |= DRAM_MR_WRITE_RECOVERY(ddr3_write_recovery(para->clock));
        writel(reg_val, &dram->mr);
 
        writel(para->emr1, &dram->emr);
        writel(para->emr2, &dram->emr2);
        writel(para->emr3, &dram->emr3);
 
-       /* set DQS window mode */
+       /* disable drift compensation and set passive DQS window mode */
        clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE);
 
 #ifdef CONFIG_SUN7I
@@ -620,70 +673,78 @@ unsigned long dramc_init(struct dram_para *para)
        if (para->tpr4 & 0x1)
                setbits_le32(&dram->ccr, DRAM_CCR_COMMAND_RATE_1T);
 #endif
-       /* reset external DRAM */
-       setbits_le32(&dram->ccr, DRAM_CCR_INIT);
-       await_completion(&dram->ccr, DRAM_CCR_INIT);
+       /* initialize external DRAM */
+       mctl_ddr3_initialize();
 
-#ifdef CONFIG_SUN7I
-       /* setup zq calibration manual */
-       reg_val = readl(&dram->ppwrsctl);
-       if ((reg_val & 0x1) == 1) {
-               /* super_standby_flag = 1 */
-
-               reg_val = readl(0x01c20c00 + 0x120); /* rtc */
-               reg_val &= 0x000fffff;
-               reg_val |= 0x17b00000;
-               writel(reg_val, &dram->zqcr0);
+       /* scan read pipe value */
+       mctl_itm_enable();
 
-               /* exit self-refresh state */
-               clrsetbits_le32(&dram->dcr, 0x1f << 27, 0x12 << 27);
-               /* check whether command has been executed */
-               await_completion(&dram->dcr, 0x1 << 31);
+       /* Hardware DQS gate training */
+       ret_val = dramc_scan_readpipe();
 
-               udelay(2);
+       if (ret_val < 0)
+               return 0;
 
-               /* dram pad hold off */
-               setbits_le32(&dram->ppwrsctl, 0x16510000);
+       /* allow to override the DQS training results with a custom delay */
+       if (para->dqs_gating_delay)
+               mctl_set_dqs_gating_delay(0, para->dqs_gating_delay);
 
-               await_completion(&dram->ppwrsctl, 0x1);
+       /* set the DQS gating window type */
+       if (para->active_windowing)
+               clrbits_le32(&dram->ccr, DRAM_CCR_DQS_GATE);
+       else
+               setbits_le32(&dram->ccr, DRAM_CCR_DQS_GATE);
 
-               /* exit self-refresh state */
-               clrsetbits_le32(&dram->dcr, 0x1f << 27, 0x12 << 27);
+       mctl_itm_reset();
 
-               /* check whether command has been executed */
-               await_completion(&dram->dcr, 0x1 << 31);
+       /* configure all host port */
+       mctl_configure_hostport();
 
-               udelay(2);
+       return get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
+}
 
-               /* issue a refresh command */
-               clrsetbits_le32(&dram->dcr, 0x1f << 27, 0x13 << 27);
-               await_completion(&dram->dcr, 0x1 << 31);
+unsigned long dramc_init(struct dram_para *para)
+{
+       unsigned long dram_size, actual_density;
 
-               udelay(2);
-       }
+       /* If the dram configuration is not provided, use a default */
+       if (!para)
+               return 0;
+
+       /* if everything is known, then autodetection is not necessary */
+       if (para->io_width && para->bus_width && para->density)
+               return dramc_init_helper(para);
+
+       /* try to autodetect the DRAM bus width and density */
+       para->io_width  = 16;
+       para->bus_width = 32;
+#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I)
+       /* only A0-A14 address lines on A10/A13, limiting max density to 4096 */
+       para->density = 4096;
+#else
+       /* all A0-A15 address lines on A20, which allow density 8192 */
+       para->density = 8192;
 #endif
 
-       /* scan read pipe value */
-       mctl_itm_enable();
-       if (para->tpr3 & (0x1 << 31)) {
-               ret_val = dramc_scan_dll_para();
-               if (ret_val == 0)
-                       para->tpr3 =
-                               (((readl(&dram->dllcr[0]) >> 6) & 0x3f) << 16) |
-                               (((readl(&dram->dllcr[1]) >> 14) & 0xf) << 0) |
-                               (((readl(&dram->dllcr[2]) >> 14) & 0xf) << 4) |
-                               (((readl(&dram->dllcr[3]) >> 14) & 0xf) << 8) |
-                               (((readl(&dram->dllcr[4]) >> 14) & 0xf) << 12
-                               );
-       } else {
-               ret_val = dramc_scan_readpipe();
+       dram_size = dramc_init_helper(para);
+       if (!dram_size) {
+               /* if 32-bit bus width failed, try 16-bit bus width instead */
+               para->bus_width = 16;
+               dram_size = dramc_init_helper(para);
+               if (!dram_size) {
+                       /* if 16-bit bus width also failed, then bail out */
+                       return dram_size;
+               }
        }
 
-       if (ret_val < 0)
-               return 0;
+       /* check if we need to adjust the density */
+       actual_density = (dram_size >> 17) * para->io_width / para->bus_width;
 
-       /* configure all host port */
-       mctl_configure_hostport();
+       if (actual_density != para->density) {
+               /* update the density and re-initialize DRAM again */
+               para->density = actual_density;
+               dram_size = dramc_init_helper(para);
+       }
 
-       return get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
+       return dram_size;
 }
diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S
new file mode 100644 (file)
index 0000000..0084c81
--- /dev/null
@@ -0,0 +1,162 @@
+/*
+ * Copyright (C) 2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * Based on code by Carl van Schaik <carl@ok-labs.com>.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <config.h>
+#include <asm/psci.h>
+#include <asm/arch/cpu.h>
+
+/*
+ * Memory layout:
+ *
+ * SECURE_RAM to text_end :
+ *     ._secure_text section
+ * text_end to ALIGN_PAGE(text_end):
+ *     nothing
+ * ALIGN_PAGE(text_end) to ALIGN_PAGE(text_end) + 0x1000)
+ *     1kB of stack per CPU (4 CPUs max).
+ */
+
+       .pushsection ._secure.text, "ax"
+
+       .arch_extension sec
+
+#define        ONE_MS                  (CONFIG_SYS_CLK_FREQ / 1000)
+#define        TEN_MS                  (10 * ONE_MS)
+
+.macro timer_wait      reg, ticks
+       @ Program CNTP_TVAL
+       movw    \reg, #(\ticks & 0xffff)
+       movt    \reg, #(\ticks >> 16)
+       mcr     p15, 0, \reg, c14, c2, 0
+       isb
+       @ Enable physical timer, mask interrupt
+       mov     \reg, #3
+       mcr     p15, 0, \reg, c14, c2, 1
+       @ Poll physical timer until ISTATUS is on
+1:     isb
+       mrc     p15, 0, \reg, c14, c2, 1
+       ands    \reg, \reg, #4
+       bne     1b
+       @ Disable timer
+       mov     \reg, #0
+       mcr     p15, 0, \reg, c14, c2, 1
+       isb
+.endm
+
+.globl psci_arch_init
+psci_arch_init:
+       mrc     p15, 0, r5, c1, c1, 0   @ Read SCR
+       bic     r5, r5, #1              @ Secure mode
+       mcr     p15, 0, r5, c1, c1, 0   @ Write SCR
+       isb
+
+       mrc     p15, 0, r4, c0, c0, 5   @ MPIDR
+       and     r4, r4, #3              @ cpu number in cluster
+       mov     r5, #400                @ 1kB of stack per CPU
+       mul     r4, r4, r5
+
+       adr     r5, text_end            @ end of text
+       add     r5, r5, #0x2000         @ Skip two pages
+       lsr     r5, r5, #12             @ Align to start of page
+       lsl     r5, r5, #12
+       sub     sp, r5, r4              @ here's our stack!
+
+       bx      lr
+
+       @ r1 = target CPU
+       @ r2 = target PC
+.globl psci_cpu_on
+psci_cpu_on:
+       adr     r0, _target_pc
+       str     r2, [r0]
+       dsb
+
+       movw    r0, #(SUNXI_CPUCFG_BASE & 0xffff)
+       movt    r0, #(SUNXI_CPUCFG_BASE >> 16)
+
+       @ CPU mask
+       and     r1, r1, #3      @ only care about first cluster
+       mov     r4, #1
+       lsl     r4, r4, r1
+
+       adr     r6, _sunxi_cpu_entry
+       str     r6, [r0, #0x1a4] @ PRIVATE_REG (boot vector)
+
+       @ Assert reset on target CPU
+       mov     r6, #0
+       lsl     r5, r1, #6      @ 64 bytes per CPU
+       add     r5, r5, #0x40   @ Offset from base
+       add     r5, r5, r0      @ CPU control block
+       str     r6, [r5]        @ Reset CPU
+
+       @ l1 invalidate
+       ldr     r6, [r0, #0x184]
+       bic     r6, r6, r4
+       str     r6, [r0, #0x184]
+
+       @ Lock CPU
+       ldr     r6, [r0, #0x1e4]
+       bic     r6, r6, r4
+       str     r6, [r0, #0x1e4]
+
+       @ Release power clamp
+       movw    r6, #0x1ff
+       movt    r6, #0
+1:     lsrs    r6, r6, #1
+       str     r6, [r0, #0x1b0]
+       bne     1b
+
+       timer_wait r1, TEN_MS
+
+       @ Clear power gating
+       ldr     r6, [r0, #0x1b4]
+       bic     r6, r6, #1
+       str     r6, [r0, #0x1b4]
+
+       @ Deassert reset on target CPU
+       mov     r6, #3
+       str     r6, [r5]
+
+       @ Unlock CPU
+       ldr     r6, [r0, #0x1e4]
+       orr     r6, r6, r4
+       str     r6, [r0, #0x1e4]
+
+       mov     r0, #ARM_PSCI_RET_SUCCESS       @ Return PSCI_RET_SUCCESS
+       mov     pc, lr
+
+_target_pc:
+       .word   0
+
+_sunxi_cpu_entry:
+       @ Set SMP bit
+       mrc     p15, 0, r0, c1, c0, 1
+       orr     r0, r0, #0x40
+       mcr     p15, 0, r0, c1, c0, 1
+       isb
+
+       bl      _nonsec_init
+       bl      psci_arch_init
+
+       adr     r0, _target_pc
+       ldr     r0, [r0]
+       b       _do_nonsec_entry
+
+text_end:
+       .popsection
diff --git a/arch/arm/cpu/armv7/tegra-common/Kconfig b/arch/arm/cpu/armv7/tegra-common/Kconfig
new file mode 100644 (file)
index 0000000..8e2153b
--- /dev/null
@@ -0,0 +1,30 @@
+if TEGRA
+
+choice
+       prompt "Tegra SoC select"
+
+config TEGRA20
+       bool "Tegra20 family"
+
+config TEGRA30
+       bool "Tegra30 family"
+
+config TEGRA114
+       bool "Tegra114 family"
+
+config TEGRA124
+       bool "Tegra124 family"
+
+endchoice
+
+config SYS_CPU
+       string
+       default "arm720t" if SPL_BUILD
+       default "armv7" if !SPL_BUILD
+
+source "arch/arm/cpu/armv7/tegra20/Kconfig"
+source "arch/arm/cpu/armv7/tegra30/Kconfig"
+source "arch/arm/cpu/armv7/tegra114/Kconfig"
+source "arch/arm/cpu/armv7/tegra124/Kconfig"
+
+endif
diff --git a/arch/arm/cpu/armv7/tegra114/Kconfig b/arch/arm/cpu/armv7/tegra114/Kconfig
new file mode 100644 (file)
index 0000000..33a22da
--- /dev/null
@@ -0,0 +1,17 @@
+if TEGRA114
+
+choice
+       prompt "Tegra114 board select"
+
+config TARGET_DALMORE
+       bool "NVIDIA Tegra114 Dalmore evaluation board"
+
+endchoice
+
+config SYS_SOC
+       string
+       default "tegra114"
+
+source "board/nvidia/dalmore/Kconfig"
+
+endif
diff --git a/arch/arm/cpu/armv7/tegra124/Kconfig b/arch/arm/cpu/armv7/tegra124/Kconfig
new file mode 100644 (file)
index 0000000..753f511
--- /dev/null
@@ -0,0 +1,21 @@
+if TEGRA124
+
+choice
+       prompt "Tegra124 board select"
+
+config TARGET_JETSON_TK1
+       bool "NVIDIA Tegra124 Jetson TK1 board"
+
+config TARGET_VENICE2
+       bool "NVIDIA Tegra124 Venice2"
+
+endchoice
+
+config SYS_SOC
+       string
+       default "tegra124"
+
+source "board/nvidia/jetson-tk1/Kconfig"
+source "board/nvidia/venice2/Kconfig"
+
+endif
diff --git a/arch/arm/cpu/armv7/tegra20/Kconfig b/arch/arm/cpu/armv7/tegra20/Kconfig
new file mode 100644 (file)
index 0000000..e2e0890
--- /dev/null
@@ -0,0 +1,53 @@
+if TEGRA20
+
+choice
+       prompt "Tegra20 board select"
+
+config TARGET_HARMONY
+       bool "NVIDIA Tegra20 Harmony evaluation board"
+
+config TARGET_MEDCOM_WIDE
+       bool "Avionic Design Medcom-Wide board"
+
+config TARGET_PAZ00
+       bool "Paz00 board"
+
+config TARGET_PLUTUX
+       bool "Avionic Design Plutux board"
+
+config TARGET_SEABOARD
+       bool "NVIDIA Seaboard"
+
+config TARGET_TEC
+       bool "Avionic Design Tamonten Evaluation Carrier"
+
+config TARGET_TRIMSLICE
+       bool "Compulab TrimSlice board"
+
+config TARGET_VENTANA
+       bool "NVIDIA Tegra20 Ventana evaluation board"
+
+config TARGET_WHISTLER
+       bool "NVIDIA Tegra20 Whistler evaluation board"
+
+config TARGET_COLIBRI_T20_IRIS
+       bool "Toradex Colibri T20 board"
+
+endchoice
+
+config SYS_SOC
+       string
+       default "tegra20"
+
+source "board/nvidia/harmony/Kconfig"
+source "board/avionic-design/medcom-wide/Kconfig"
+source "board/compal/paz00/Kconfig"
+source "board/avionic-design/plutux/Kconfig"
+source "board/nvidia/seaboard/Kconfig"
+source "board/avionic-design/tec/Kconfig"
+source "board/compulab/trimslice/Kconfig"
+source "board/nvidia/ventana/Kconfig"
+source "board/nvidia/whistler/Kconfig"
+source "board/toradex/colibri_t20_iris/Kconfig"
+
+endif
diff --git a/arch/arm/cpu/armv7/tegra30/Kconfig b/arch/arm/cpu/armv7/tegra30/Kconfig
new file mode 100644 (file)
index 0000000..694e1cd
--- /dev/null
@@ -0,0 +1,29 @@
+if TEGRA30
+
+choice
+       prompt "Tegra30 board select"
+
+config TARGET_BEAVER
+       bool "NVIDIA Tegra30 Beaver evaluation board"
+
+config TARGET_CARDHU
+       bool "NVIDIA Tegra30 Cardhu evaluation board"
+
+config TARGET_COLIBRI_T30
+       bool "Toradex Colibri T30 board"
+
+config TARGET_TEC_NG
+       bool "Avionic Design TEC-NG board"
+
+endchoice
+
+config SYS_SOC
+       string
+       default "tegra30"
+
+source "board/nvidia/beaver/Kconfig"
+source "board/nvidia/cardhu/Kconfig"
+source "board/toradex/colibri_t30/Kconfig"
+source "board/avionic-design/tec-ng/Kconfig"
+
+endif
diff --git a/arch/arm/cpu/armv7/zynq/Kconfig b/arch/arm/cpu/armv7/zynq/Kconfig
new file mode 100644 (file)
index 0000000..6b88f18
--- /dev/null
@@ -0,0 +1,43 @@
+if ZYNQ
+
+choice
+       prompt "Xilinx Zynq board select"
+
+config TARGET_ZYNQ_ZED
+       bool "Zynq ZedBoard"
+