Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
authorTom Rini <trini@ti.com>
Thu, 11 Dec 2014 23:28:09 +0000 (18:28 -0500)
committerTom Rini <trini@ti.com>
Thu, 11 Dec 2014 23:28:09 +0000 (18:28 -0500)
53 files changed:
Makefile
arch/arm/Kconfig
arch/arm/cpu/armv7/ls102xa/Makefile
arch/arm/cpu/armv7/ls102xa/cpu.c
arch/arm/cpu/armv7/ls102xa/fdt.c
arch/arm/cpu/armv7/ls102xa/fsl_epu.c [new file with mode: 0644]
arch/arm/cpu/armv7/ls102xa/fsl_epu.h [new file with mode: 0644]
arch/arm/cpu/armv7/ls102xa/spl.c [new file with mode: 0644]
arch/arm/cpu/armv7/nonsec_virt.S
arch/arm/cpu/u-boot-spl.lds
arch/arm/include/asm/arch-ls102xa/config.h
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h [new file with mode: 0644]
arch/arm/include/asm/arch-ls102xa/ns_access.h [new file with mode: 0644]
arch/arm/include/asm/arch-ls102xa/spl.h [new file with mode: 0644]
arch/arm/include/asm/pcie_layerscape.h [new file with mode: 0644]
arch/powerpc/cpu/mpc8xxx/fdt.c
board/freescale/common/Makefile
board/freescale/common/arm_sleep.c [new file with mode: 0644]
board/freescale/common/ls102xa_stream_id.c [new file with mode: 0644]
board/freescale/common/mpc85xx_sleep.c [new file with mode: 0644]
board/freescale/common/ns_access.c [new file with mode: 0644]
board/freescale/common/qixis.h
board/freescale/common/sleep.h [new file with mode: 0644]
board/freescale/ls1021aqds/MAINTAINERS
board/freescale/ls1021aqds/ddr.c
board/freescale/ls1021aqds/ls1021aqds.c
board/freescale/ls1021aqds/ls102xa_pbi.cfg [new file with mode: 0644]
board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg [new file with mode: 0644]
board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg [new file with mode: 0644]
board/freescale/ls1021atwr/MAINTAINERS
board/freescale/ls1021atwr/ls1021atwr.c
board/freescale/ls1021atwr/ls102xa_pbi.cfg [new file with mode: 0644]
board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg [new file with mode: 0644]
configs/ls1021aqds_nand_defconfig [new file with mode: 0644]
configs/ls1021aqds_qspi_defconfig [new file with mode: 0644]
configs/ls1021aqds_sdcard_defconfig [new file with mode: 0644]
configs/ls1021atwr_qspi_defconfig [new file with mode: 0644]
configs/ls1021atwr_sdcard_defconfig [new file with mode: 0644]
drivers/ddr/fsl/arm_ddr_gen3.c
drivers/ddr/fsl/fsl_ddr_gen4.c
drivers/ddr/fsl/mpc85xx_ddr_gen3.c
drivers/mtd/nand/fsl_ifc_nand.c
drivers/mtd/nand/fsl_ifc_spl.c
drivers/pci/Makefile
drivers/pci/pcie_layerscape.c [new file with mode: 0644]
drivers/usb/host/ehci-fsl.c
include/configs/ls1021aqds.h
include/configs/ls1021atwr.h
include/configs/sun7i.h
include/fsl_ddr_sdram.h
include/fsl_usb.h
tools/pblimage.c

index 2308828..63eccc2 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -999,15 +999,22 @@ u-boot-img.bin: spl/u-boot-spl.bin u-boot.img FORCE
 #concatenated with u-boot binary. It is need by PowerPC SoC having
 #internal SRAM <= 512KB.
 MKIMAGEFLAGS_u-boot-spl.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
-               -R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage
+               -R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage \
+               -A $(ARCH) -a $(CONFIG_SPL_TEXT_BASE)
 
 spl/u-boot-spl.pbl: spl/u-boot-spl.bin FORCE
        $(call if_changed,mkimage)
 
+ifeq ($(ARCH),arm)
+UBOOT_BINLOAD := u-boot.img
+else
+UBOOT_BINLOAD := u-boot.bin
+endif
+
 OBJCOPYFLAGS_u-boot-with-spl-pbl.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \
                          --gap-fill=0xff
 
-u-boot-with-spl-pbl.bin: spl/u-boot-spl.pbl u-boot.bin FORCE
+u-boot-with-spl-pbl.bin: spl/u-boot-spl.pbl $(UBOOT_BINLOAD) FORCE
        $(call if_changed,pad_cat)
 
 # PPC4xx needs the SPL at the end of the image, since the reset vector
index c0b68cb..2b0d2c9 100644 (file)
@@ -733,12 +733,14 @@ config TARGET_LS2085A_SIMU
        select ARM64
 
 config TARGET_LS1021AQDS
-       bool "Support ls1021aqds_nor"
+       bool "Support ls1021aqds"
        select CPU_V7
+       select SUPPORT_SPL
 
 config TARGET_LS1021ATWR
-       bool "Support ls1021atwr_nor"
+       bool "Support ls1021atwr"
        select CPU_V7
+       select SUPPORT_SPL
 
 config TARGET_BALLOON3
        bool "Support balloon3"
index d82ce8d..2e6a207 100644 (file)
@@ -7,6 +7,8 @@
 obj-y  += cpu.o
 obj-y  += clock.o
 obj-y  += timer.o
+obj-y  += fsl_epu.o
 
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
 obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
+obj-$(CONFIG_SPL) += spl.o
index b7dde45..ce2d92f 100644 (file)
@@ -12,6 +12,8 @@
 #include <netdev.h>
 #include <fsl_esdhc.h>
 
+#include "fsl_epu.h"
+
 DECLARE_GLOBAL_DATA_PTR;
 
 #if defined(CONFIG_DISPLAY_CPUINFO)
@@ -101,3 +103,35 @@ int cpu_eth_init(bd_t *bis)
 
        return 0;
 }
+
+int arch_cpu_init(void)
+{
+       void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+
+       /*
+        * After wakeup from deep sleep, Clear EPU registers
+        * as early as possible to prevent from possible issue.
+        * It's also safe to clear at normal boot.
+        */
+       fsl_epu_clean(epu_base);
+
+       return 0;
+}
+
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+/* Set the address at which the secondary core starts from.*/
+void smp_set_core_boot_addr(unsigned long addr, int corenr)
+{
+       struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+       out_be32(&gur->scratchrw[0], addr);
+}
+
+/* Release the secondary core from holdoff state and kick it */
+void smp_kick_all_cpus(void)
+{
+       struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+       out_be32(&gur->brrl, 0x2);
+}
+#endif
index 4ce3808..989780d 100644 (file)
@@ -91,7 +91,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
        }
 
        do_fixup_by_prop_u32(blob, "device_type", "soc",
-                            4, "bus-frequency", busclk / 2, 1);
+                            4, "bus-frequency", busclk, 1);
 
        ft_fixup_enet_phy_connect_type(blob);
 
diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_epu.c b/arch/arm/cpu/armv7/ls102xa/fsl_epu.c
new file mode 100644 (file)
index 0000000..6212640
--- /dev/null
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#include "fsl_epu.h"
+
+/**
+ * fsl_epu_clean - Clear EPU registers
+ */
+void fsl_epu_clean(void *epu_base)
+{
+       u32 offset;
+
+       /* follow the exact sequence to clear the registers */
+       /* Clear EPACRn */
+       for (offset = EPACR0; offset <= EPACR15; offset += EPACR_STRIDE)
+               out_be32(epu_base + offset, 0);
+
+       /* Clear EPEVTCRn */
+       for (offset = EPEVTCR0; offset <= EPEVTCR9; offset += EPEVTCR_STRIDE)
+               out_be32(epu_base + offset, 0);
+
+       /* Clear EPGCR */
+       out_be32(epu_base + EPGCR, 0);
+
+       /* Clear EPSMCRn */
+       for (offset = EPSMCR0; offset <= EPSMCR15; offset += EPSMCR_STRIDE)
+               out_be32(epu_base + offset, 0);
+
+       /* Clear EPCCRn */
+       for (offset = EPCCR0; offset <= EPCCR31; offset += EPCCR_STRIDE)
+               out_be32(epu_base + offset, 0);
+
+       /* Clear EPCMPRn */
+       for (offset = EPCMPR0; offset <= EPCMPR31; offset += EPCMPR_STRIDE)
+               out_be32(epu_base + offset, 0);
+
+       /* Clear EPCTRn */
+       for (offset = EPCTR0; offset <= EPCTR31; offset += EPCTR_STRIDE)
+               out_be32(epu_base + offset, 0);
+
+       /* Clear EPIMCRn */
+       for (offset = EPIMCR0; offset <= EPIMCR31; offset += EPIMCR_STRIDE)
+               out_be32(epu_base + offset, 0);
+
+       /* Clear EPXTRIGCRn */
+       out_be32(epu_base + EPXTRIGCR, 0);
+
+       /* Clear EPECRn */
+       for (offset = EPECR0; offset <= EPECR15; offset += EPECR_STRIDE)
+               out_be32(epu_base + offset, 0);
+}
diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_epu.h b/arch/arm/cpu/armv7/ls102xa/fsl_epu.h
new file mode 100644 (file)
index 0000000..d658aad
--- /dev/null
@@ -0,0 +1,68 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __FSL_EPU_H
+#define __FSL_EPU_H
+
+#include <asm/types.h>
+
+#define FSL_STRIDE_4B  4
+#define FSL_STRIDE_8B  8
+
+/* Block offsets */
+#define EPU_BLOCK_OFFSET       0x00000000
+
+/* EPGCR (Event Processor Global Control Register) */
+#define EPGCR          0x000
+
+/* EPEVTCR0-9 (Event Processor EVT Pin Control Registers) */
+#define EPEVTCR0       0x050
+#define EPEVTCR9       0x074
+#define EPEVTCR_STRIDE FSL_STRIDE_4B
+
+/* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
+#define EPXTRIGCR      0x090
+
+/* EPIMCR0-31 (Event Processor Input Mux Control Registers) */
+#define EPIMCR0                0x100
+#define EPIMCR31       0x17C
+#define EPIMCR_STRIDE  FSL_STRIDE_4B
+
+/* EPSMCR0-15 (Event Processor SCU Mux Control Registers) */
+#define EPSMCR0                0x200
+#define EPSMCR15       0x278
+#define EPSMCR_STRIDE  FSL_STRIDE_8B
+
+/* EPECR0-15 (Event Processor Event Control Registers) */
+#define EPECR0         0x300
+#define EPECR15                0x33C
+#define EPECR_STRIDE   FSL_STRIDE_4B
+
+/* EPACR0-15 (Event Processor Action Control Registers) */
+#define EPACR0         0x400
+#define EPACR15                0x43C
+#define EPACR_STRIDE   FSL_STRIDE_4B
+
+/* EPCCRi0-15 (Event Processor Counter Control Registers) */
+#define EPCCR0         0x800
+#define EPCCR15                0x83C
+#define EPCCR31                0x87C
+#define EPCCR_STRIDE   FSL_STRIDE_4B
+
+/* EPCMPR0-15 (Event Processor Counter Compare Registers) */
+#define EPCMPR0                0x900
+#define EPCMPR15       0x93C
+#define EPCMPR31       0x97C
+#define EPCMPR_STRIDE  FSL_STRIDE_4B
+
+/* EPCTR0-31 (Event Processor Counter Register) */
+#define EPCTR0         0xA00
+#define EPCTR31                0xA7C
+#define EPCTR_STRIDE   FSL_STRIDE_4B
+
+void fsl_epu_clean(void *epu_base);
+
+#endif
diff --git a/arch/arm/cpu/armv7/ls102xa/spl.c b/arch/arm/cpu/armv7/ls102xa/spl.c
new file mode 100644 (file)
index 0000000..1dfbf54
--- /dev/null
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+
+u32 spl_boot_device(void)
+{
+#ifdef CONFIG_SPL_MMC_SUPPORT
+       return BOOT_DEVICE_MMC1;
+#endif
+       return BOOT_DEVICE_NAND;
+}
+
+u32 spl_boot_mode(void)
+{
+       switch (spl_boot_device()) {
+       case BOOT_DEVICE_MMC1:
+#ifdef CONFIG_SPL_FAT_SUPPORT
+               return MMCSD_MODE_FAT;
+#else
+               return MMCSD_MODE_RAW;
+#endif
+       case BOOT_DEVICE_NAND:
+               return 0;
+       default:
+               puts("spl: error: unsupported device\n");
+               hang();
+       }
+}
index 745670e..30d81db 100644 (file)
@@ -169,11 +169,11 @@ ENTRY(_nonsec_init)
  * we do this here instead.
  * But first check if we have the generic timer.
  */
-#ifdef CONFIG_SYS_CLK_FREQ
+#ifdef CONFIG_TIMER_CLK_FREQ
        mrc     p15, 0, r0, c0, c1, 1           @ read ID_PFR1
        and     r0, r0, #CPUID_ARM_GENTIMER_MASK        @ mask arch timer bits
        cmp     r0, #(1 << CPUID_ARM_GENTIMER_SHIFT)
-       ldreq   r1, =CONFIG_SYS_CLK_FREQ
+       ldreq   r1, =CONFIG_TIMER_CLK_FREQ
        mcreq   p15, 0, r1, c14, c0, 0          @ write CNTFRQ
 #endif
 
@@ -191,6 +191,9 @@ ENTRY(smp_waitloop)
        wfi
        ldr     r1, =CONFIG_SMP_PEN_ADDR        @ load start address
        ldr     r1, [r1]
+#ifdef CONFIG_PEN_ADDR_BIG_ENDIAN
+       rev     r1, r1
+#endif
        cmp     r0, r1                  @ make sure we dont execute this code
        beq     smp_waitloop            @ again (due to a spurious wakeup)
        mov     r0, r1
index a69b006..a8be204 100644 (file)
@@ -32,6 +32,9 @@ SECTIONS
        }
 
        . = ALIGN(4);
+       .u_boot_list : {
+               KEEP(*(SORT(.u_boot_list*_i2c_*)));
+       }
 
        . = .;
 #ifdef CONFIG_SPL_DM
index ba86eea..5e934da 100644 (file)
 
 #define OCRAM_BASE_ADDR                                0x10000000
 #define OCRAM_SIZE                             0x00020000
+#define OCRAM_BASE_S_ADDR                      0x10010000
+#define OCRAM_S_SIZE                           0x00010000
 
 #define CONFIG_SYS_IMMR                                0x01000000
+#define CONFIG_SYS_DCSRBAR                     0x20000000
+
+#define CONFIG_SYS_DCSR_DCFG_ADDR      (CONFIG_SYS_DCSRBAR + 0x00220000)
 
 #define CONFIG_SYS_FSL_DDR_ADDR                        (CONFIG_SYS_IMMR + 0x00080000)
 #define CONFIG_SYS_CCI400_ADDR                 (CONFIG_SYS_IMMR + 0x00180000)
+#define CONFIG_SYS_FSL_CSU_ADDR                 (CONFIG_SYS_IMMR + 0x00510000)
 #define CONFIG_SYS_IFC_ADDR                    (CONFIG_SYS_IMMR + 0x00530000)
 #define CONFIG_SYS_FSL_ESDHC_ADDR              (CONFIG_SYS_IMMR + 0x00560000)
 #define CONFIG_SYS_FSL_SCFG_ADDR               (CONFIG_SYS_IMMR + 0x00570000)
@@ -52,6 +58,9 @@
 
 #define LPUART_BASE                            (CONFIG_SYS_IMMR + 0x01950000)
 
+#define CONFIG_SYS_PCIE1_ADDR                  (CONFIG_SYS_IMMR + 0x2400000)
+#define CONFIG_SYS_PCIE2_ADDR                  (CONFIG_SYS_IMMR + 0x2500000)
+
 #ifdef CONFIG_DDR_SPD
 #define CONFIG_SYS_FSL_DDR_BE
 #define CONFIG_VERY_BIG_RAM
index b0c267c..697d4ca 100644 (file)
@@ -17,6 +17,9 @@
 #define SOC_VER_LS1021         0x11
 #define SOC_VER_LS1022         0x12
 
+#define CCSR_BRR_OFFSET                0xe4
+#define CCSR_SCRATCHRW1_OFFSET 0x200
+
 #define RCWSR0_SYS_PLL_RAT_SHIFT       25
 #define RCWSR0_SYS_PLL_RAT_MASK                0x1f
 #define RCWSR0_MEM_PLL_RAT_SHIFT       16
 #define ARCH_TIMER_CTRL_ENABLE         (1 << 0)
 #define SYS_COUNTER_CTRL_ENABLE                (1 << 24)
 
+#define DCFG_CCSR_PORSR1_RCW_MASK      0xff800000
+#define DCFG_CCSR_PORSR1_RCW_SRC_I2C   0x24800000
+
+#define DCFG_DCSR_PORCR1               0
+
 struct sys_info {
        unsigned long freq_processor[CONFIG_MAX_CPUS];
        unsigned long freq_systembus;
@@ -98,6 +106,7 @@ struct ccsr_gur {
 #define SCFG_ETSECDMAMCR_LE_BD_FR      0xf8001a0f
 #define SCFG_ETSECCMCR_GE2_CLK125      0x04000000
 #define SCFG_PIXCLKCR_PXCKEN           0x80000000
+#define SCFG_QSPI_CLKSEL               0xc0100000
 
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
new file mode 100644 (file)
index 0000000..abd70fc
--- /dev/null
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __FSL_LS102XA_STREAM_ID_H_
+#define __FSL_LS102XA_STREAM_ID_H_
+
+struct smmu_stream_id {
+       uint16_t offset;
+       uint16_t stream_id;
+       char dev_name[32];
+};
+
+void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num);
+#endif
diff --git a/arch/arm/include/asm/arch-ls102xa/ns_access.h b/arch/arm/include/asm/arch-ls102xa/ns_access.h
new file mode 100644 (file)
index 0000000..b53f699
--- /dev/null
@@ -0,0 +1,118 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __FSL_NS_ACCESS_H_
+#define __FSL_NS_ACCESS_H_
+
+enum csu_cslx_access {
+       CSU_NS_SUP_R = 0x08,
+       CSU_NS_SUP_W = 0x80,
+       CSU_NS_SUP_RW = 0x88,
+       CSU_NS_USER_R = 0x04,
+       CSU_NS_USER_W = 0x40,
+       CSU_NS_USER_RW = 0x44,
+       CSU_S_SUP_R = 0x02,
+       CSU_S_SUP_W = 0x20,
+       CSU_S_SUP_RW = 0x22,
+       CSU_S_USER_R = 0x01,
+       CSU_S_USER_W = 0x10,
+       CSU_S_USER_RW = 0x11,
+       CSU_ALL_RW = 0xff,
+};
+
+enum csu_cslx_ind {
+       CSU_CSLX_PCIE2_IO = 0,
+       CSU_CSLX_PCIE1_IO,
+       CSU_CSLX_MG2TPR_IP,
+       CSU_CSLX_IFC_MEM,
+       CSU_CSLX_OCRAM,
+       CSU_CSLX_GIC,
+       CSU_CSLX_PCIE1,
+       CSU_CSLX_OCRAM2,
+       CSU_CSLX_QSPI_MEM,
+       CSU_CSLX_PCIE2,
+       CSU_CSLX_SATA,
+       CSU_CSLX_USB3,
+       CSU_CSLX_SERDES = 32,
+       CSU_CSLX_QDMA,
+       CSU_CSLX_LPUART2,
+       CSU_CSLX_LPUART1,
+       CSU_CSLX_LPUART4,
+       CSU_CSLX_LPUART3,
+       CSU_CSLX_LPUART6,
+       CSU_CSLX_LPUART5,
+       CSU_CSLX_DSPI2 = 40,
+       CSU_CSLX_DSPI1,
+       CSU_CSLX_QSPI,
+       CSU_CSLX_ESDHC,
+       CSU_CSLX_2D_ACE,
+       CSU_CSLX_IFC,
+       CSU_CSLX_I2C1,
+       CSU_CSLX_USB2,
+       CSU_CSLX_I2C3,
+       CSU_CSLX_I2C2,
+       CSU_CSLX_DUART2 = 50,
+       CSU_CSLX_DUART1,
+       CSU_CSLX_WDT2,
+       CSU_CSLX_WDT1,
+       CSU_CSLX_EDMA,
+       CSU_CSLX_SYS_CNT,
+       CSU_CSLX_DMA_MUX2,
+       CSU_CSLX_DMA_MUX1,
+       CSU_CSLX_DDR,
+       CSU_CSLX_QUICC,
+       CSU_CSLX_DCFG_CCU_RCPM = 60,
+       CSU_CSLX_SECURE_BOOTROM,
+       CSU_CSLX_SFP,
+       CSU_CSLX_TMU,
+       CSU_CSLX_SECURE_MONITOR,
+       CSU_CSLX_RESERVED0,
+       CSU_CSLX_ETSEC1,
+       CSU_CSLX_SEC5_5,
+       CSU_CSLX_ETSEC3,
+       CSU_CSLX_ETSEC2,
+       CSU_CSLX_GPIO2 = 70,
+       CSU_CSLX_GPIO1,
+       CSU_CSLX_GPIO4,
+       CSU_CSLX_GPIO3,
+       CSU_CSLX_PLATFORM_CONT,
+       CSU_CSLX_CSU,
+       CSU_CSLX_ASRC,
+       CSU_CSLX_SPDIF,
+       CSU_CSLX_FLEXCAN2,
+       CSU_CSLX_FLEXCAN1,
+       CSU_CSLX_FLEXCAN4 = 80,
+       CSU_CSLX_FLEXCAN3,
+       CSU_CSLX_SAI2,
+       CSU_CSLX_SAI1,
+       CSU_CSLX_SAI4,
+       CSU_CSLX_SAI3,
+       CSU_CSLX_FTM2,
+       CSU_CSLX_FTM1,
+       CSU_CSLX_FTM4,
+       CSU_CSLX_FTM3,
+       CSU_CSLX_FTM6 = 90,
+       CSU_CSLX_FTM5,
+       CSU_CSLX_FTM8,
+       CSU_CSLX_FTM7,
+       CSU_CSLX_COP_DCSR,
+       CSU_CSLX_EPU,
+       CSU_CSLX_GDI,
+       CSU_CSLX_DDI,
+       CSU_CSLX_RESERVED1,
+       CSU_CSLX_USB3_PHY = 117,
+       CSU_CSLX_RESERVED2,
+       CSU_CSLX_MAX,
+};
+
+struct csu_ns_dev {
+       unsigned long ind;
+       uint32_t val;
+};
+
+void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num);
+
+#endif
diff --git a/arch/arm/include/asm/arch-ls102xa/spl.h b/arch/arm/include/asm/arch-ls102xa/spl.h
new file mode 100644 (file)
index 0000000..26e4ea1
--- /dev/null
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_SPL_H__
+#define __ASM_ARCH_SPL_H__
+
+#define BOOT_DEVICE_NONE       0
+#define BOOT_DEVICE_XIP                1
+#define BOOT_DEVICE_XIPWAIT    2
+#define BOOT_DEVICE_NAND       3
+#define BOOT_DEVICE_ONENAND    4
+#define BOOT_DEVICE_MMC1       5
+#define BOOT_DEVICE_MMC2       6
+#define BOOT_DEVICE_MMC2_2     7
+#define BOOT_DEVICE_SPI                10
+
+#endif /* __ASM_ARCH_SPL_H__ */
diff --git a/arch/arm/include/asm/pcie_layerscape.h b/arch/arm/include/asm/pcie_layerscape.h
new file mode 100644 (file)
index 0000000..fb08578
--- /dev/null
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __PCIE_LAYERSCAPE_H_
+#define __PCIE_LAYERSCAPE_H_
+
+void pci_init_board(void);
+void ft_pcie_setup(void *blob, bd_t *bd);
+
+#endif
index c6b4d95..1c63f93 100644 (file)
@@ -73,110 +73,6 @@ void ft_fixup_num_cores(void *blob) {
 }
 #endif /* defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) */
 
-#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
-static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
-                               const char *phy_type, int start_offset)
-{
-       const char *compat_dr = "fsl-usb2-dr";
-       const char *compat_mph = "fsl-usb2-mph";
-       const char *prop_mode = "dr_mode";
-       const char *prop_type = "phy_type";
-       const char *node_type = NULL;
-       int node_offset;
-       int err;
-
-       node_offset = fdt_node_offset_by_compatible(blob,
-                       start_offset, compat_mph);
-       if (node_offset < 0) {
-               node_offset = fdt_node_offset_by_compatible(blob,
-                       start_offset, compat_dr);
-               if (node_offset < 0) {
-                       printf("WARNING: could not find compatible"
-                               " node %s or %s: %s.\n", compat_mph,
-                               compat_dr, fdt_strerror(node_offset));
-                       return -1;
-               } else
-                       node_type = compat_dr;
-       } else
-               node_type = compat_mph;
-
-       if (mode) {
-               err = fdt_setprop(blob, node_offset, prop_mode, mode,
-                                 strlen(mode) + 1);
-               if (err < 0)
-                       printf("WARNING: could not set %s for %s: %s.\n",
-                              prop_mode, node_type, fdt_strerror(err));
-       }
-
-       if (phy_type) {
-               err = fdt_setprop(blob, node_offset, prop_type, phy_type,
-                                 strlen(phy_type) + 1);
-               if (err < 0)
-                       printf("WARNING: could not set %s for %s: %s.\n",
-                              prop_type, node_type, fdt_strerror(err));
-       }
-
-       return node_offset;
-}
-
-void fdt_fixup_dr_usb(void *blob, bd_t *bd)
-{
-       const char *modes[] = { "host", "peripheral", "otg" };
-       const char *phys[] = { "ulpi", "utmi" };
-       int usb_mode_off = -1;
-       int usb_phy_off = -1;
-       char str[5];
-       int i, j;
-
-       for (i = 1; i <= CONFIG_USB_MAX_CONTROLLER_COUNT; i++) {
-               const char *dr_mode_type = NULL;
-               const char *dr_phy_type = NULL;
-               int mode_idx = -1, phy_idx = -1;
-               snprintf(str, 5, "%s%d", "usb", i);
-               if (hwconfig(str)) {
-                       for (j = 0; j < ARRAY_SIZE(modes); j++) {
-                               if (hwconfig_subarg_cmp(str, "dr_mode",
-                                               modes[j])) {
-                                       mode_idx = j;
-                                       break;
-                               }
-                       }
-
-                       for (j = 0; j < ARRAY_SIZE(phys); j++) {
-                               if (hwconfig_subarg_cmp(str, "phy_type",
-                                               phys[j])) {
-                                       phy_idx = j;
-                                       break;
-                               }
-                       }
-
-                       if (mode_idx < 0 && phy_idx < 0) {
-                               printf("WARNING: invalid phy or mode\n");
-                               return;
-                       }
-
-                       if (mode_idx > -1)
-                               dr_mode_type = modes[mode_idx];
-
-                       if (phy_idx > -1)
-                               dr_phy_type = phys[phy_idx];
-               }
-
-               usb_mode_off = fdt_fixup_usb_mode_phy_type(blob,
-                       dr_mode_type, NULL, usb_mode_off);
-
-               if (usb_mode_off < 0)
-                       return;
-
-               usb_phy_off = fdt_fixup_usb_mode_phy_type(blob,
-                       NULL, dr_phy_type, usb_phy_off);
-
-               if (usb_phy_off < 0)
-                       return;
-       }
-}
-#endif /* defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) */
-
 /*
  * update crypto node properties to a specified revision of the SEC
  * called with sec_rev == 0 if not on an E processor
index 59ddeef..14af660 100644 (file)
@@ -37,6 +37,12 @@ endif
 
 obj-$(CONFIG_FSL_DIU_CH7301)   += diu_ch7301.o
 
+ifdef CONFIG_ARM
+obj-$(CONFIG_DEEP_SLEEP)               += arm_sleep.o
+else
+obj-$(CONFIG_DEEP_SLEEP)               += mpc85xx_sleep.o
+endif
+
 obj-$(CONFIG_FSL_DCU_SII9022A)    += dcu_sii9022a.o
 
 obj-$(CONFIG_MPC8541CDS)       += cds_pci_ft.o
@@ -56,10 +62,14 @@ obj-$(CONFIG_IDT8T49N222A)  += idt8t49n222a_serdes_clk.o
 obj-$(CONFIG_ZM7300)           += zm7300.o
 obj-$(CONFIG_POWER_PFUZE100)   += pfuze.o
 
+obj-$(CONFIG_LS102XA_STREAM_ID)        += ls102xa_stream_id.o
+
 # deal with common files for P-series corenet based devices
 obj-$(CONFIG_P2041RDB) += p_corenet/
 obj-$(CONFIG_P3041DS)  += p_corenet/
 obj-$(CONFIG_P4080DS)  += p_corenet/
 obj-$(CONFIG_P5020DS)  += p_corenet/
 obj-$(CONFIG_P5040DS)  += p_corenet/
+
+obj-$(CONFIG_LS102XA_NS_ACCESS)        += ns_access.o
 endif
diff --git a/board/freescale/common/arm_sleep.c b/board/freescale/common/arm_sleep.c
new file mode 100644 (file)
index 0000000..8edf878
--- /dev/null
@@ -0,0 +1,95 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#if !defined(CONFIG_ARMV7_NONSEC) || !defined(CONFIG_ARMV7_VIRT)
+#error " Deep sleep needs non-secure mode support. "
+#else
+#include <asm/secure.h>
+#endif
+#include <asm/armv7.h>
+#include <asm/cache.h>
+
+#if defined(CONFIG_LS102XA)
+#include <asm/arch/immap_ls102xa.h>
+#endif
+
+#include "sleep.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void __weak board_mem_sleep_setup(void)
+{
+}
+
+void __weak board_sleep_prepare(void)
+{
+}
+
+bool is_warm_boot(void)
+{
+       struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+
+       if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
+               return 1;
+
+       return 0;
+}
+
+void fsl_dp_disable_console(void)
+{
+       gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
+}
+
+/*
+ * When wakeup from deep sleep, the first 128 bytes space
+ * will be used to do DDR training which corrupts the data
+ * in there. This function will restore them.
+ */
+static void dp_ddr_restore(void)
+{
+       u64 *src, *dst;
+       int i;
+       struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+       /* get the address of ddr date from SPARECR3 */
+       src = (u64 *)in_le32(&scfg->sparecr[2]);
+       dst = (u64 *)CONFIG_SYS_SDRAM_BASE;
+
+       for (i = 0; i < DDR_BUFF_LEN / 8; i++)
+               *dst++ = *src++;
+
+       flush_dcache_all();
+}
+
+static void dp_resume_prepare(void)
+{
+       dp_ddr_restore();
+       board_sleep_prepare();
+       armv7_init_nonsec();
+       cleanup_before_linux();
+}
+
+int fsl_dp_resume(void)
+{
+       u32 start_addr;
+       void (*kernel_resume)(void);
+       struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+       if (!is_warm_boot())
+               return 0;
+
+       dp_resume_prepare();
+
+       /* Get the entry address and jump to kernel */
+       start_addr = in_le32(&scfg->sparecr[1]);
+       debug("Entry address is 0x%08x\n", start_addr);
+       kernel_resume = (void (*)(void))start_addr;
+       secure_ram_addr(_do_nonsec_entry)(kernel_resume, 0, 0, 0);
+
+       return 0;
+}
diff --git a/board/freescale/common/ls102xa_stream_id.c b/board/freescale/common/ls102xa_stream_id.c
new file mode 100644 (file)
index 0000000..6154c9c
--- /dev/null
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/ls102xa_stream_id.h>
+
+void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num)
+{
+       uint32_t *scfg = (uint32_t *)CONFIG_SYS_FSL_SCFG_ADDR;
+       int i;
+
+       for (i = 0; i < num; i++)
+               out_be32(scfg + id[i].offset, id[i].stream_id);
+}
diff --git a/board/freescale/common/mpc85xx_sleep.c b/board/freescale/common/mpc85xx_sleep.c
new file mode 100644 (file)
index 0000000..f924e7f
--- /dev/null
@@ -0,0 +1,88 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/immap_85xx.h>
+#include "sleep.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void __weak board_mem_sleep_setup(void)
+{
+}
+
+void __weak board_sleep_prepare(void)
+{
+}
+
+bool is_warm_boot(void)
+{
+       struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+       if (in_be32(&gur->scrtsr[0]) & DCFG_CCSR_CRSTSR_WDRFR)
+               return 1;
+
+       return 0;
+}
+
+void fsl_dp_disable_console(void)
+{
+       gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
+}
+
+/*
+ * When wakeup from deep sleep, the first 128 bytes space
+ * will be used to do DDR training which corrupts the data
+ * in there. This function will restore them.
+ */
+static void dp_ddr_restore(void)
+{
+       volatile u64 *src, *dst;
+       int i;
+       struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
+
+       /* get the address of ddr date from SPARECR3 */
+       src = (u64 *)in_be32(&scfg->sparecr[2]);
+       dst = (u64 *)CONFIG_SYS_SDRAM_BASE;
+
+       for (i = 0; i < DDR_BUFF_LEN / 8; i++)
+               *dst++ = *src++;
+
+       flush_dcache();
+}
+
+static void dp_resume_prepare(void)
+{
+       dp_ddr_restore();
+
+       board_sleep_prepare();
+
+       l2cache_init();
+#if defined(CONFIG_RAMBOOT_PBL)
+       disable_cpc_sram();
+#endif
+       enable_cpc();
+}
+
+int fsl_dp_resume(void)
+{
+       u32 start_addr;
+       void (*kernel_resume)(void);
+       struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
+
+       if (!is_warm_boot())
+               return 0;
+
+       dp_resume_prepare();
+
+       /* Get the entry address and jump to kernel */
+       start_addr = in_be32(&scfg->sparecr[1]);
+       debug("Entry address is 0x%08x\n", start_addr);
+       kernel_resume = (void (*)(void))start_addr;
+       kernel_resume();
+
+       return 0;
+}
diff --git a/board/freescale/common/ns_access.c b/board/freescale/common/ns_access.c
new file mode 100644 (file)
index 0000000..d7de982
--- /dev/null
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/ns_access.h>
+
+void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num)
+{
+       u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR;
+       u32 *reg;
+       uint32_t val;
+       int i;
+
+       for (i = 0; i < num; i++) {
+               reg = base + ns_dev[i].ind / 2;
+               val = in_be32(reg);
+               if (ns_dev[i].ind % 2 == 0) {
+                       val &= 0x0000ffff;
+                       val |= ns_dev[i].val << 16;
+               } else {
+                       val &= 0xffff0000;
+                       val |= ns_dev[i].val;
+               }
+               out_be32(reg, val);
+       }
+}
index d8fed14..52d2021 100644 (file)
@@ -100,8 +100,15 @@ u8 qixis_read_i2c(unsigned int reg);
 void qixis_write_i2c(unsigned int reg, u8 value);
 #endif
 
+#if defined(CONFIG_QIXIS_I2C_ACCESS) && defined(CONFIG_SYS_I2C_FPGA_ADDR)
+#define QIXIS_READ(reg) qixis_read_i2c(offsetof(struct qixis, reg))
+#define QIXIS_WRITE(reg, value) \
+       qixis_write_i2c(offsetof(struct qixis, reg), value)
+#else
 #define QIXIS_READ(reg) qixis_read(offsetof(struct qixis, reg))
 #define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value)
+#endif
+
 #ifdef CONFIG_SYS_I2C_FPGA_ADDR
 #define QIXIS_READ_I2C(reg) qixis_read_i2c(offsetof(struct qixis, reg))
 #define QIXIS_WRITE_I2C(reg, value) \
diff --git a/board/freescale/common/sleep.h b/board/freescale/common/sleep.h
new file mode 100644 (file)
index 0000000..c26c542
--- /dev/null
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __SLEEP_H
+#define __SLEEP_H
+
+#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
+#define DDR_BUFF_LEN                   128
+
+/* determine if it is a wakeup from deep sleep */
+bool is_warm_boot(void);
+
+/* disable console output */
+void fsl_dp_disable_console(void);
+
+/* clean up everything and jump to kernel */
+int fsl_dp_resume(void);
+#endif
index e30e944..638833d 100644 (file)
@@ -6,3 +6,6 @@ F:      include/configs/ls1021aqds.h
 F:     configs/ls1021aqds_nor_defconfig
 F:     configs/ls1021aqds_ddr4_nor_defconfig
 F:     configs/ls1021aqds_nor_SECURE_BOOT_defconfig
+F:     configs/ls1021aqds_sdcard_defconfig
+F:     configs/ls1021aqds_qspi_defconfig
+F:     configs/ls1021aqds_nand_defconfig
index 5898e33..a539ff9 100644 (file)
@@ -153,9 +153,12 @@ phys_size_t initdram(int board_type)
 {
        phys_size_t dram_size;
 
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
        puts("Initializing DDR....using SPD\n");
        dram_size = fsl_ddr_sdram();
-
+#else
+       dram_size =  fsl_ddr_sdram_size();
+#endif
        return dram_size;
 }
 
index 0a7720a..f08e54f 100644 (file)
@@ -8,12 +8,17 @@
 #include <i2c.h>
 #include <asm/io.h>
 #include <asm/arch/immap_ls102xa.h>
+#include <asm/arch/ns_access.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/fsl_serdes.h>
+#include <asm/arch/ls102xa_stream_id.h>
+#include <asm/pcie_layerscape.h>
+#include <hwconfig.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <fsl_ifc.h>
 #include <fsl_sec.h>
+#include <spl.h>
 
 #include "../common/qixis.h"
 #include "ls1021aqds_qixis.h"
 #include "../../../drivers/qe/qe.h"
 #endif
 
+#define PIN_MUX_SEL_CAN                0x03
+#define PIN_MUX_SEL_IIC2       0xa0
+#define PIN_MUX_SEL_RGMII      0x00
+#define PIN_MUX_SEL_SAI                0x0c
+#define PIN_MUX_SEL_SDHC       0x00
+
+#define SET_SDHC_MUX_SEL(reg, value)   ((reg & 0x0f) | value)
+#define SET_EC_MUX_SEL(reg, value)     ((reg & 0xf0) | value)
 DECLARE_GLOBAL_DATA_PTR;
 
 enum {
+       MUX_TYPE_CAN,
+       MUX_TYPE_IIC2,
+       MUX_TYPE_RGMII,
+       MUX_TYPE_SAI,
+       MUX_TYPE_SDHC,
        MUX_TYPE_SD_PCI4,
        MUX_TYPE_SD_PC_SA_SG_SG,
        MUX_TYPE_SD_PC_SA_PC_SG,
@@ -32,11 +50,20 @@ enum {
 
 int checkboard(void)
 {
+#ifndef CONFIG_QSPI_BOOT
        char buf[64];
+#endif
+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
        u8 sw;
+#endif
 
        puts("Board: LS1021AQDS\n");
 
+#ifdef CONFIG_SD_BOOT
+       puts("SD\n");
+#elif CONFIG_QSPI_BOOT
+       puts("QSPI\n");
+#else
        sw = QIXIS_READ(brdcfg[0]);
        sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 
@@ -50,13 +77,16 @@ int checkboard(void)
                printf("IFCCard\n");
        else
                printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+#endif
 
+#ifndef CONFIG_QSPI_BOOT
        printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
               QIXIS_READ(id), QIXIS_READ(arch));
 
        printf("FPGA:  v%d (%s), build %d\n",
               (int)QIXIS_READ(scver), qixis_read_tag(buf),
               (int)qixis_read_minor());
+#endif
 
        return 0;
 }
@@ -101,8 +131,27 @@ unsigned long get_board_ddr_clk(void)
        return 66666666;
 }
 
+int select_i2c_ch_pca9547(u8 ch)
+{
+       int ret;
+
+       ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+       if (ret) {
+               puts("PCA: failed to select proper channel\n");
+               return ret;
+       }
+
+       return 0;
+}
+
 int dram_init(void)
 {
+       /*
+        * When resuming from deep sleep, the I2C channel may not be
+        * in the default channel. So, switch to the default channel
+        * before accessing DDR SPD.
+        */
+       select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
        gd->ram_size = initdram(0);
 
        return 0;
@@ -121,19 +170,6 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
-int select_i2c_ch_pca9547(u8 ch)
-{
-       int ret;
-
-       ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
-       if (ret) {
-               puts("PCA: failed to select proper channel\n");
-               return ret;
-       }
-
-       return 0;
-}
-
 int board_early_init_f(void)
 {
        struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
@@ -148,6 +184,10 @@ int board_early_init_f(void)
        init_early_memctl_regs();
 #endif
 
+#ifdef CONFIG_FSL_QSPI
+       out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
+#endif
+
        /* Workaround for the issue that DDR could not respond to
         * barrier transaction which is generated by executing DSB/ISB
         * instruction. Set CCI-400 control override register to
@@ -158,13 +198,75 @@ int board_early_init_f(void)
        return 0;
 }
 
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+       struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+
+#ifdef CONFIG_NAND_BOOT
+       struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+       u32 porsr1, pinctl;
+
+       /*
+        * There is LS1 SoC issue where NOR, FPGA are inaccessible during
+        * NAND boot because IFC signals > IFC_AD7 are not enabled.
+        * This workaround changes RCW source to make all signals enabled.
+        */
+       porsr1 = in_be32(&gur->porsr1);
+       pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
+                DCFG_CCSR_PORSR1_RCW_SRC_I2C);
+       out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
+                pinctl);
+#endif
+
+       /* Set global data pointer */
+       gd = &gdata;
+
+       /* Clear the BSS */
+       memset(__bss_start, 0, __bss_end - __bss_start);
+
+#ifdef CONFIG_FSL_IFC
+       init_early_memctl_regs();
+#endif
+
+       get_clocks();
+
+       preloader_console_init();
+
+#ifdef CONFIG_SPL_I2C_SUPPORT
+       i2c_init_all();
+#endif
+       out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
+
+       dram_init();
+
+       board_init_r(NULL, 0);
+}
+#endif
+
 int config_board_mux(int ctrl_type)
 {
-       u8 reg12;
+       u8 reg12, reg14;
 
        reg12 = QIXIS_READ(brdcfg[12]);
+       reg14 = QIXIS_READ(brdcfg[14]);
 
        switch (ctrl_type) {
+       case MUX_TYPE_CAN:
+               reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
+               break;
+       case MUX_TYPE_IIC2:
+               reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2);
+               break;
+       case MUX_TYPE_RGMII:
+               reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
+               break;
+       case MUX_TYPE_SAI:
+               reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
+               break;
+       case MUX_TYPE_SDHC:
+               reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC);
+               break;
        case MUX_TYPE_SD_PCI4:
                reg12 = 0x38;
                break;
@@ -183,6 +285,7 @@ int config_board_mux(int ctrl_type)
        }
 
        QIXIS_WRITE(brdcfg[12], reg12);
+       QIXIS_WRITE(brdcfg[14], reg14);
 
        return 0;
 }
@@ -216,15 +319,154 @@ int config_serdes_mux(void)
        return 0;
 }
 
-#if defined(CONFIG_MISC_INIT_R)
 int misc_init_r(void)
 {
+       int conflict_flag;
+
+       /* some signals can not enable simultaneous*/
+       conflict_flag = 0;
+       if (hwconfig("sdhc"))
+               conflict_flag++;
+       if (hwconfig("iic2"))
+               conflict_flag++;
+       if (conflict_flag > 1) {
+               printf("WARNING: pin conflict !\n");
+               return 0;
+       }
+
+       conflict_flag = 0;
+       if (hwconfig("rgmii"))
+               conflict_flag++;
+       if (hwconfig("can"))
+               conflict_flag++;
+       if (hwconfig("sai"))
+               conflict_flag++;
+       if (conflict_flag > 1) {
+               printf("WARNING: pin conflict !\n");
+               return 0;
+       }
+
+       if (hwconfig("can"))
+               config_board_mux(MUX_TYPE_CAN);
+       else if (hwconfig("rgmii"))
+               config_board_mux(MUX_TYPE_RGMII);
+       else if (hwconfig("sai"))
+               config_board_mux(MUX_TYPE_SAI);
+
+       if (hwconfig("iic2"))
+               config_board_mux(MUX_TYPE_IIC2);
+       else if (hwconfig("sdhc"))
+               config_board_mux(MUX_TYPE_SDHC);
+
 #ifdef CONFIG_FSL_CAAM
        return sec_init();
 #endif
+       return 0;
 }
+
+#ifdef CONFIG_LS102XA_NS_ACCESS
+static struct csu_ns_dev ns_dev[] = {
+       { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
+       { CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
+       { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
+       { CSU_CSLX_IFC_MEM, CSU_ALL_RW },
+       { CSU_CSLX_OCRAM, CSU_ALL_RW },
+       { CSU_CSLX_GIC, CSU_ALL_RW },
+       { CSU_CSLX_PCIE1, CSU_ALL_RW },
+       { CSU_CSLX_OCRAM2, CSU_ALL_RW },
+       { CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
+       { CSU_CSLX_PCIE2, CSU_ALL_RW },
+       { CSU_CSLX_SATA, CSU_ALL_RW },
+       { CSU_CSLX_USB3, CSU_ALL_RW },
+       { CSU_CSLX_SERDES, CSU_ALL_RW },
+       { CSU_CSLX_QDMA, CSU_ALL_RW },
+       { CSU_CSLX_LPUART2, CSU_ALL_RW },
+       { CSU_CSLX_LPUART1, CSU_ALL_RW },
+       { CSU_CSLX_LPUART4, CSU_ALL_RW },
+       { CSU_CSLX_LPUART3, CSU_ALL_RW },
+       { CSU_CSLX_LPUART6, CSU_ALL_RW },
+       { CSU_CSLX_LPUART5, CSU_ALL_RW },
+       { CSU_CSLX_DSPI2, CSU_ALL_RW },
+       { CSU_CSLX_DSPI1, CSU_ALL_RW },
+       { CSU_CSLX_QSPI, CSU_ALL_RW },
+       { CSU_CSLX_ESDHC, CSU_ALL_RW },
+       { CSU_CSLX_2D_ACE, CSU_ALL_RW },
+       { CSU_CSLX_IFC, CSU_ALL_RW },
+       { CSU_CSLX_I2C1, CSU_ALL_RW },
+       { CSU_CSLX_USB2, CSU_ALL_RW },
+       { CSU_CSLX_I2C3, CSU_ALL_RW },
+       { CSU_CSLX_I2C2, CSU_ALL_RW },
+       { CSU_CSLX_DUART2, CSU_ALL_RW },
+       { CSU_CSLX_DUART1, CSU_ALL_RW },
+       { CSU_CSLX_WDT2, CSU_ALL_RW },
+       { CSU_CSLX_WDT1, CSU_ALL_RW },
+       { CSU_CSLX_EDMA, CSU_ALL_RW },
+       { CSU_CSLX_SYS_CNT, CSU_ALL_RW },
+       { CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
+       { CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
+       { CSU_CSLX_DDR, CSU_ALL_RW },
+       { CSU_CSLX_QUICC, CSU_ALL_RW },
+       { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
+       { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
+       { CSU_CSLX_SFP, CSU_ALL_RW },
+       { CSU_CSLX_TMU, CSU_ALL_RW },
+       { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
+       { CSU_CSLX_RESERVED0, CSU_ALL_RW },
+       { CSU_CSLX_ETSEC1, CSU_ALL_RW },
+       { CSU_CSLX_SEC5_5, CSU_ALL_RW },
+       { CSU_CSLX_ETSEC3, CSU_ALL_RW },
+       { CSU_CSLX_ETSEC2, CSU_ALL_RW },
+       { CSU_CSLX_GPIO2, CSU_ALL_RW },
+       { CSU_CSLX_GPIO1, CSU_ALL_RW },
+       { CSU_CSLX_GPIO4, CSU_ALL_RW },
+       { CSU_CSLX_GPIO3, CSU_ALL_RW },
+       { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
+       { CSU_CSLX_CSU, CSU_ALL_RW },
+       { CSU_CSLX_ASRC, CSU_ALL_RW },
+       { CSU_CSLX_SPDIF, CSU_ALL_RW },
+       { CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
+       { CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
+       { CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
+       { CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
+       { CSU_CSLX_SAI2, CSU_ALL_RW },
+       { CSU_CSLX_SAI1, CSU_ALL_RW },
+       { CSU_CSLX_SAI4, CSU_ALL_RW },
+       { CSU_CSLX_SAI3, CSU_ALL_RW },
+       { CSU_CSLX_FTM2, CSU_ALL_RW },
+       { CSU_CSLX_FTM1, CSU_ALL_RW },
+       { CSU_CSLX_FTM4, CSU_ALL_RW },
+       { CSU_CSLX_FTM3, CSU_ALL_RW },
+       { CSU_CSLX_FTM6, CSU_ALL_RW },
+       { CSU_CSLX_FTM5, CSU_ALL_RW },
+       { CSU_CSLX_FTM8, CSU_ALL_RW },
+       { CSU_CSLX_FTM7, CSU_ALL_RW },
+       { CSU_CSLX_COP_DCSR, CSU_ALL_RW },
+       { CSU_CSLX_EPU, CSU_ALL_RW },
+       { CSU_CSLX_GDI, CSU_ALL_RW },
+       { CSU_CSLX_DDI, CSU_ALL_RW },
+       { CSU_CSLX_RESERVED1, CSU_ALL_RW },
+       { CSU_CSLX_USB3_PHY, CSU_ALL_RW },
+       { CSU_CSLX_RESERVED2, CSU_ALL_RW },
+};
 #endif
 
+struct smmu_stream_id dev_stream_id[] = {
+       { 0x100, 0x01, "ETSEC MAC1" },
+       { 0x104, 0x02, "ETSEC MAC2" },
+       { 0x108, 0x03, "ETSEC MAC3" },
+       { 0x10c, 0x04, "PEX1" },
+       { 0x110, 0x05, "PEX2" },
+       { 0x114, 0x06, "qDMA" },
+       { 0x118, 0x07, "SATA" },
+       { 0x11c, 0x08, "USB3" },
+       { 0x120, 0x09, "QE" },
+       { 0x124, 0x0a, "eSDHC" },
+       { 0x128, 0x0b, "eMA" },
+       { 0x14c, 0x0c, "2D-ACE" },
+       { 0x150, 0x0d, "USB2" },
+       { 0x18c, 0x0e, "DEBUG" },
+};
+
 int board_init(void)
 {
        struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
@@ -247,6 +489,13 @@ int board_init(void)
        config_serdes_mux();
 #endif
 
+       ls102xa_config_smmu_stream_id(dev_stream_id,
+                                     ARRAY_SIZE(dev_stream_id));
+
+#ifdef CONFIG_LS102XA_NS_ACCESS
+       enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
+#endif
+
 #ifdef CONFIG_U_QE
        u_qe_init();
 #endif
@@ -258,6 +507,10 @@ int ft_board_setup(void *blob, bd_t *bd)
 {
        ft_cpu_setup(blob, bd);
 
+#ifdef CONFIG_PCIE_LAYERSCAPE
+       ft_pcie_setup(blob, bd);
+#endif
+
        return 0;
 }
 
diff --git a/board/freescale/ls1021aqds/ls102xa_pbi.cfg b/board/freescale/ls1021aqds/ls102xa_pbi.cfg
new file mode 100644 (file)
index 0000000..f1a1b63
--- /dev/null
@@ -0,0 +1,12 @@
+#PBI commands
+
+09570200 ffffffff
+09570158 00000300
+8940007c 21f47300
+
+#Configure Scratch register
+09ee0200 10000000
+#Configure alternate space
+09570158 00001000
+#Flush PBL data
+096100c0 000FFFFF
diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
new file mode 100644 (file)
index 0000000..222c71d
--- /dev/null
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# serdes protocol
+0608000a 00000000 00000000 00000000
+60000000 00407900 e0106a00 21046000
+00000000 00000000 00000000 00038000
+00000000 001b7200 00000000 00000000
diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg
new file mode 100644 (file)
index 0000000..9d99bd8
--- /dev/null
@@ -0,0 +1,14 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+
+#enable IFC, disable QSPI and DSPI
+0608000a 00000000 00000000 00000000
+60000000 00407900 60040a00 21046000
+00000000 00000000 00000000 00038000
+00000000 001b7200 00000000 00000000
+
+#disable IFC, enable QSPI and DSPI
+#0608000a 00000000 00000000 00000000
+#60000000 00407900 60040a00 21046000
+#00000000 00000000 00000000 00038000
+#20024800 001b7200 00000000 00000000
index 8def0e5..9176706 100644 (file)
@@ -5,3 +5,5 @@ F:      board/freescale/ls1021atwr/
 F:     include/configs/ls1021atwr.h
 F:     configs/ls1021atwr_nor_defconfig
 F:     configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+F:     configs/ls1021atwr_sdcard_defconfig
+F:     configs/ls1021atwr_qspi_defconfig
index 3e8c37b..8ab229d 100644 (file)
@@ -8,8 +8,11 @@
 #include <i2c.h>
 #include <asm/io.h>
 #include <asm/arch/immap_ls102xa.h>
+#include <asm/arch/ns_access.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/fsl_serdes.h>
+#include <asm/arch/ls102xa_stream_id.h>
+#include <asm/pcie_layerscape.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <fsl_ifc.h>
@@ -17,6 +20,7 @@
 #include <fsl_mdio.h>
 #include <tsec.h>
 #include <fsl_sec.h>
+#include <spl.h>
 #ifdef CONFIG_U_QE
 #include "../../../drivers/qe/qe.h"
 #endif
@@ -70,6 +74,7 @@ struct cpld_data {
        u8 rev2;                /* Reserved */
 };
 
+#ifndef CONFIG_QSPI_BOOT
 static void convert_serdes_mux(int type, int need_reset);
 
 void cpld_show(void)
@@ -105,11 +110,14 @@ void cpld_show(void)
               in_8(&cpld_data->serdes_mux));
 #endif
 }
+#endif
 
 int checkboard(void)
 {
        puts("Board: LS1021ATWR\n");
+#ifndef CONFIG_QSPI_BOOT
        cpld_show();
+#endif
 
        return 0;
 }
@@ -218,6 +226,7 @@ int board_eth_init(bd_t *bis)
 }
 #endif
 
+#ifndef CONFIG_QSPI_BOOT
 int config_serdes_mux(void)
 {
        struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -249,6 +258,7 @@ int config_serdes_mux(void)
 
        return 0;
 }
+#endif
 
 int board_early_init_f(void)
 {
@@ -267,9 +277,135 @@ int board_early_init_f(void)
        out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
 #endif
 
+#ifdef CONFIG_FSL_QSPI
+       out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
+#endif
+
        return 0;
 }
 
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+       /* Set global data pointer */
+       gd = &gdata;
+
+       /* Clear the BSS */
+       memset(__bss_start, 0, __bss_end - __bss_start);
+
+       get_clocks();
+
+       preloader_console_init();
+
+       dram_init();
+
+       board_init_r(NULL, 0);
+}
+#endif
+
+#ifdef CONFIG_LS102XA_NS_ACCESS
+static struct csu_ns_dev ns_dev[] = {
+       { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
+       { CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
+       { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
+       { CSU_CSLX_IFC_MEM, CSU_ALL_RW },
+       { CSU_CSLX_OCRAM, CSU_ALL_RW },
+       { CSU_CSLX_GIC, CSU_ALL_RW },
+       { CSU_CSLX_PCIE1, CSU_ALL_RW },
+       { CSU_CSLX_OCRAM2, CSU_ALL_RW },
+       { CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
+       { CSU_CSLX_PCIE2, CSU_ALL_RW },
+       { CSU_CSLX_SATA, CSU_ALL_RW },
+       { CSU_CSLX_USB3, CSU_ALL_RW },
+       { CSU_CSLX_SERDES, CSU_ALL_RW },
+       { CSU_CSLX_QDMA, CSU_ALL_RW },
+       { CSU_CSLX_LPUART2, CSU_ALL_RW },
+       { CSU_CSLX_LPUART1, CSU_ALL_RW },
+       { CSU_CSLX_LPUART4, CSU_ALL_RW },
+       { CSU_CSLX_LPUART3, CSU_ALL_RW },
+       { CSU_CSLX_LPUART6, CSU_ALL_RW },
+       { CSU_CSLX_LPUART5, CSU_ALL_RW },
+       { CSU_CSLX_DSPI2, CSU_ALL_RW },
+       { CSU_CSLX_DSPI1, CSU_ALL_RW },
+       { CSU_CSLX_QSPI, CSU_ALL_RW },
+       { CSU_CSLX_ESDHC, CSU_ALL_RW },
+       { CSU_CSLX_2D_ACE, CSU_ALL_RW },
+       { CSU_CSLX_IFC, CSU_ALL_RW },
+       { CSU_CSLX_I2C1, CSU_ALL_RW },
+       { CSU_CSLX_USB2, CSU_ALL_RW },
+       { CSU_CSLX_I2C3, CSU_ALL_RW },
+       { CSU_CSLX_I2C2, CSU_ALL_RW },
+       { CSU_CSLX_DUART2, CSU_ALL_RW },
+       { CSU_CSLX_DUART1, CSU_ALL_RW },
+       { CSU_CSLX_WDT2, CSU_ALL_RW },
+       { CSU_CSLX_WDT1, CSU_ALL_RW },
+       { CSU_CSLX_EDMA, CSU_ALL_RW },
+       { CSU_CSLX_SYS_CNT, CSU_ALL_RW },
+       { CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
+       { CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
+       { CSU_CSLX_DDR, CSU_ALL_RW },
+       { CSU_CSLX_QUICC, CSU_ALL_RW },
+       { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
+       { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
+       { CSU_CSLX_SFP, CSU_ALL_RW },
+       { CSU_CSLX_TMU, CSU_ALL_RW },
+       { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
+       { CSU_CSLX_RESERVED0, CSU_ALL_RW },
+       { CSU_CSLX_ETSEC1, CSU_ALL_RW },
+       { CSU_CSLX_SEC5_5, CSU_ALL_RW },
+       { CSU_CSLX_ETSEC3, CSU_ALL_RW },
+       { CSU_CSLX_ETSEC2, CSU_ALL_RW },
+       { CSU_CSLX_GPIO2, CSU_ALL_RW },
+       { CSU_CSLX_GPIO1, CSU_ALL_RW },
+       { CSU_CSLX_GPIO4, CSU_ALL_RW },
+       { CSU_CSLX_GPIO3, CSU_ALL_RW },
+       { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
+       { CSU_CSLX_CSU, CSU_ALL_RW },
+       { CSU_CSLX_ASRC, CSU_ALL_RW },
+       { CSU_CSLX_SPDIF, CSU_ALL_RW },
+       { CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
+       { CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
+       { CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
+       { CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
+       { CSU_CSLX_SAI2, CSU_ALL_RW },
+       { CSU_CSLX_SAI1, CSU_ALL_RW },
+       { CSU_CSLX_SAI4, CSU_ALL_RW },
+       { CSU_CSLX_SAI3, CSU_ALL_RW },
+       { CSU_CSLX_FTM2, CSU_ALL_RW },
+       { CSU_CSLX_FTM1, CSU_ALL_RW },
+       { CSU_CSLX_FTM4, CSU_ALL_RW },
+       { CSU_CSLX_FTM3, CSU_ALL_RW },
+       { CSU_CSLX_FTM6, CSU_ALL_RW },
+       { CSU_CSLX_FTM5, CSU_ALL_RW },
+       { CSU_CSLX_FTM8, CSU_ALL_RW },
+       { CSU_CSLX_FTM7, CSU_ALL_RW },
+       { CSU_CSLX_COP_DCSR, CSU_ALL_RW },
+       { CSU_CSLX_EPU, CSU_ALL_RW },
+       { CSU_CSLX_GDI, CSU_ALL_RW },
+       { CSU_CSLX_DDI, CSU_ALL_RW },
+       { CSU_CSLX_RESERVED1, CSU_ALL_RW },
+       { CSU_CSLX_USB3_PHY, CSU_ALL_RW },
+       { CSU_CSLX_RESERVED2, CSU_ALL_RW },
+};
+#endif
+
+struct smmu_stream_id dev_stream_id[] = {
+       { 0x100, 0x01, "ETSEC MAC1" },
+       { 0x104, 0x02, "ETSEC MAC2" },
+       { 0x108, 0x03, "ETSEC MAC3" },
+       { 0x10c, 0x04, "PEX1" },
+       { 0x110, 0x05, "PEX2" },
+       { 0x114, 0x06, "qDMA" },
+       { 0x118, 0x07, "SATA" },
+       { 0x11c, 0x08, "USB3" },
+       { 0x120, 0x09, "QE" },
+       { 0x124, 0x0a, "eSDHC" },
+       { 0x128, 0x0b, "eMA" },
+       { 0x14c, 0x0c, "2D-ACE" },
+       { 0x150, 0x0d, "USB2" },
+       { 0x18c, 0x0e, "DEBUG" },
+};
+
 int board_init(void)
 {
        struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
@@ -284,8 +420,17 @@ int board_init(void)
 
 #ifndef CONFIG_SYS_FSL_NO_SERDES
        fsl_serdes_init();
+#ifndef CONFIG_QSPI_BOOT
        config_serdes_mux();
 #endif
+#endif
+
+       ls102xa_config_smmu_stream_id(dev_stream_id,
+                                     ARRAY_SIZE(dev_stream_id));
+
+#ifdef CONFIG_LS102XA_NS_ACCESS
+       enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
+#endif
 
 #ifdef CONFIG_U_QE
        u_qe_init();
@@ -307,6 +452,10 @@ int ft_board_setup(void *blob, bd_t *bd)
 {
        ft_cpu_setup(blob, bd);
 
+#ifdef CONFIG_PCIE_LAYERSCAPE
+       ft_pcie_setup(blob, bd);
+#endif
+
        return 0;
 }
 
@@ -329,6 +478,7 @@ u16 flash_read16(void *addr)
        return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 }
 
+#ifndef CONFIG_QSPI_BOOT
 static void convert_flash_bank(char bank)
 {
        struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
@@ -511,3 +661,4 @@ U_BOOT_CMD(
        "       -change lane C & lane D to PCIeX2\n"
        "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"
 );
+#endif
diff --git a/board/freescale/ls1021atwr/ls102xa_pbi.cfg b/board/freescale/ls1021atwr/ls102xa_pbi.cfg
new file mode 100644 (file)
index 0000000..f1a1b63
--- /dev/null
@@ -0,0 +1,12 @@
+#PBI commands
+
+09570200 ffffffff
+09570158 00000300
+8940007c 21f47300
+
+#Configure Scratch register
+09ee0200 10000000
+#Configure alternate space
+09570158 00001000
+#Flush PBL data
+096100c0 000FFFFF
diff --git a/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg b/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg
new file mode 100644 (file)
index 0000000..9c3e3b0
--- /dev/null
@@ -0,0 +1,14 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+
+#enable IFC, disable QSPI and DSPI
+0608000a 00000000 00000000 00000000
+20000000 00407900 60040a00 21046000
+00000000 00000000 00000000 00038000
+00080000 881b7340 00000000 00000000
+
+#disable IFC, enable QSPI and DSPI
+#0608000a 00000000 00000000 00000000
+#20000000 00407900 60040a00 21046000
+#00000000 00000000 00000000 00038000
+#20084800 881b7340 00000000 00000000
diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig
new file mode 100644 (file)
index 0000000..dad5274
--- /dev/null
@@ -0,0 +1,4 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_LS1021AQDS=y
diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig
new file mode 100644 (file)
index 0000000..05ec8e6
--- /dev/null
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_LS1021AQDS=y
diff --git a/configs/ls1021aqds_sdcard_defconfig b/configs/ls1021aqds_sdcard_defconfig
new file mode 100644 (file)
index 0000000..e03c3b4
--- /dev/null
@@ -0,0 +1,4 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_LS1021AQDS=y
diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig
new file mode 100644 (file)
index 0000000..611f6e8
--- /dev/null
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_LS1021ATWR=y
diff --git a/configs/ls1021atwr_sdcard_defconfig b/configs/ls1021atwr_sdcard_defconfig
new file mode 100644 (file)
index 0000000..0eb556a
--- /dev/null
@@ -0,0 +1,4 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_LS1021ATWR=y
index 59f2fd6..c139da6 100644 (file)
@@ -92,7 +92,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0);
        ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1);
        ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2);
-       ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
        ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode);
        ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
        ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
@@ -105,9 +104,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
        ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init);
        ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
-       ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
-       ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
-
        ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4);
        ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5);
        ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
@@ -128,7 +124,24 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
        ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
        ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
-       ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
+#ifdef CONFIG_DEEP_SLEEP
+       if (is_warm_boot()) {
+               ddr_out32(&ddr->sdram_cfg_2,
+                         regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
+               ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
+               ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
+
+               /* DRAM VRef will not be trained */
+               ddr_out32(&ddr->ddr_cdr2,
+                         regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
+       } else
+#endif
+       {
+               ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
+               ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
+               ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
+               ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
+       }
        ddr_out32(&ddr->err_disable, regs->err_disable);
        ddr_out32(&ddr->err_int_en, regs->err_int_en);
        for (i = 0; i < 32; i++) {
@@ -167,8 +180,20 @@ step2:
        udelay(500);
        asm volatile("dsb sy;isb");
 
+#ifdef CONFIG_DEEP_SLEEP
+       if (is_warm_boot()) {
+               /* enter self-refresh */
+               temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
+               temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
+               ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
+               /* do board specific memory setup */
+               board_mem_sleep_setup();
+
+               temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
+       } else
+#endif
+               temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
        /* Let the controller go */
-       temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
        ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
        asm volatile("dsb sy;isb");
 
@@ -211,4 +236,12 @@ step2:
 
        if (timeout <= 0)
                printf("Waiting for D_INIT timeout. Memory may not work.\n");
+#ifdef CONFIG_DEEP_SLEEP
+       if (is_warm_boot()) {
+               /* exit self-refresh */
+               temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
+               temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
+               ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
+       }
+#endif
 }
index e024db9..a3c01e7 100644 (file)
@@ -103,7 +103,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        ddr_out32(&ddr->dq_map_1, regs->dq_map_1);
        ddr_out32(&ddr->dq_map_2, regs->dq_map_2);
        ddr_out32(&ddr->dq_map_3, regs->dq_map_3);
-       ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
        ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3);
        ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode);
        ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
@@ -124,8 +123,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
        ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
        ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init);
-       ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
-       ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
        ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
 #ifndef CONFIG_SYS_FSL_DDR_EMU
        /*
@@ -147,7 +144,24 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5);
        ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6);
        ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
-       ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
+#ifdef CONFIG_DEEP_SLEEP
+       if (is_warm_boot()) {
+               ddr_out32(&ddr->sdram_cfg_2,
+                         regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
+               ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
+               ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
+
+               /* DRAM VRef will not be trained */
+               ddr_out32(&ddr->ddr_cdr2,
+                         regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
+       } else
+#endif
+       {
+               ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
+               ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
+               ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
+               ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
+       }
        ddr_out32(&ddr->err_disable, regs->err_disable);
        ddr_out32(&ddr->err_int_en, regs->err_int_en);
        for (i = 0; i < 32; i++) {
@@ -187,8 +201,20 @@ step2:
        mb();
        isb();
 
+#ifdef CONFIG_DEEP_SLEEP
+       if (is_warm_boot()) {
+               /* enter self-refresh */
+               temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
+               temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
+               ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
+               /* do board specific memory setup */
+               board_mem_sleep_setup();
+
+               temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
+       } else
+#endif
+               temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
        /* Let the controller go */
-       temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
        ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
        mb();
        isb();
@@ -233,4 +259,12 @@ step2:
 
        if (timeout <= 0)
                printf("Waiting for D_INIT timeout. Memory may not work.\n");
+#ifdef CONFIG_DEEP_SLEEP
+       if (is_warm_boot()) {
+               /* exit self-refresh */
+               temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
+               temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
+               ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
+       }
+#endif
 }
index 4d5572e..8f4d01a 100644 (file)
@@ -15,8 +15,6 @@
 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
 #endif
 
-DECLARE_GLOBAL_DATA_PTR;
-
 /*
  * regs has the to-be-set values for DDR controller registers
  * ctrl_num is the DDR controller number
@@ -44,16 +42,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        u32 save1, save2;
 #endif
 
-#ifdef CONFIG_DEEP_SLEEP
-       const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-       bool sleep_flag = 0;
-#endif
-
-#ifdef CONFIG_DEEP_SLEEP
-       if (in_be32(&gur->scrtsr[0]) & (1 << 3))
-               sleep_flag = 1;
-#endif
-
        switch (ctrl_num) {
        case 0:
                ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
@@ -130,13 +118,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
        out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
        out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
-#ifdef CONFIG_DEEP_SLEEP
-       if (sleep_flag)
-               out_be32(&ddr->sdram_cfg_2,
-                        regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
-       else
-#endif
-               out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
        out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
        out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
        out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
@@ -149,17 +130,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
        out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
        out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
-#ifdef CONFIG_DEEP_SLEEP
-       if (sleep_flag) {
-               out_be32(&ddr->init_addr, 0);
-               out_be32(&ddr->init_ext_addr, (1 << 31));
-       } else
-#endif
-       {
-               out_be32(&ddr->init_addr, regs->ddr_init_addr);
-               out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
-       }
-
        out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
        out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
        out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
@@ -180,7 +150,24 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
        out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
        out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1);
-       out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
+#ifdef CONFIG_DEEP_SLEEP
+       if (is_warm_boot()) {
+               out_be32(&ddr->sdram_cfg_2,
+                        regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
+               out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
+               out_be32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
+
+               /* DRAM VRef will not be trained */
+               out_be32(&ddr->ddr_cdr2,
+                        regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
+       } else
+#endif
+       {
+               out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
+               out_be32(&ddr->init_addr, regs->ddr_init_addr);
+               out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
+               out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
+       }
        out_be32(&ddr->err_disable, regs->err_disable);
        out_be32(&ddr->err_int_en, regs->err_int_en);
        for (i = 0; i < 32; i++) {
@@ -400,21 +387,17 @@ step2:
        asm volatile("sync;isync");
 
 #ifdef CONFIG_DEEP_SLEEP
-       if (sleep_flag) {
+       if (is_warm_boot()) {
                /* enter self-refresh */
-               setbits_be32(&ddr->sdram_cfg_2, (1 << 31));
+               setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR);
                /* do board specific memory setup */
                board_mem_sleep_setup();
-       }
-#endif
-
-       /* Let the controller go */
-#ifdef CONFIG_DEEP_SLEEP
-       if (sleep_flag)
                temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
-       else
+       else
 #endif
                temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI);
+
+       /* Let the controller go */
        out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
        asm volatile("sync;isync");
 
@@ -566,8 +549,8 @@ step2:
        }
 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */
 #ifdef CONFIG_DEEP_SLEEP
-       if (sleep_flag)
+       if (is_warm_boot())
                /* exit self-refresh */
-               clrbits_be32(&ddr->sdram_cfg_2, (1 << 31));
+               clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR);
 #endif
 }
index 81b5070..b283eae 100644 (file)
@@ -292,7 +292,7 @@ static int fsl_ifc_run_command(struct mtd_info *mtd)
        struct fsl_ifc *ifc = ctrl->regs;
        u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
        u32 time_start;
-       u32 eccstat[4];
+       u32 eccstat[4] = {0};
        int i;
 
        /* set the chip select for NAND Transaction */
index e336cb1..fb827c5 100644 (file)
@@ -254,3 +254,13 @@ void nand_boot(void)
        uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
        uboot();
 }
+
+#ifndef CONFIG_SPL_NAND_INIT
+void nand_init(void)
+{
+}
+
+void nand_deselect(void)
+{
+}
+#endif
index 55d6a9b..85e82bd 100644 (file)
@@ -17,3 +17,4 @@ obj-$(CONFIG_SH7751_PCI) +=pci_sh7751.o
 obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o
 obj-$(CONFIG_TSI108_PCI) += tsi108_pci.o
 obj-$(CONFIG_WINBOND_83C553) += w83c553f.o
+obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
new file mode 100644 (file)
index 0000000..291c249
--- /dev/null
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Layerscape PCIe driver
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/fsl_serdes.h>
+#include <pci.h>
+#include <asm/io.h>
+#include <asm/pcie_layerscape.h>
+
+#ifdef CONFIG_OF_BOARD_SETUP
+#include <libfdt.h>
+#include <fdt_support.h>
+
+static void ft_pcie_ls_setup(void *blob, const char *pci_compat,
+                            unsigned long ctrl_addr, enum srds_prtcl dev)
+{
+       int off;
+
+       off = fdt_node_offset_by_compat_reg(blob, pci_compat,
+                                           (phys_addr_t)ctrl_addr);
+       if (off < 0)
+               return;
+
+       if (!is_serdes_configured(dev))
+               fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
+}
+
+void ft_pcie_setup(void *blob, bd_t *bd)
+{
+       #ifdef CONFIG_PCIE1
+       ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE1_ADDR, PCIE1);
+       #endif
+
+       #ifdef CONFIG_PCIE2
+       ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE2_ADDR, PCIE2);
+       #endif
+}
+
+#else
+void ft_pcie_setup(void *blob, bd_t *bd)
+{
+}
+#endif
+
+void pci_init_board(void)
+{
+}
index 8f55464..5d4288d 100644 (file)
 #include <usb/ehci-fsl.h>
 #include <hwconfig.h>
 #include <fsl_usb.h>
+#include <fdt_support.h>
 
 #include "ehci.h"
 
+#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#endif
+
 static void set_txfifothresh(struct usb_ehci *, u32);
 
 /* Check USB PHY clock valid */
@@ -158,3 +163,184 @@ static void set_txfifothresh(struct usb_ehci *ehci, u32 txfifo_thresh)
        cmd |= TXFIFO_THRESH(txfifo_thresh);
        ehci_writel(&ehci->txfilltuning, cmd);
 }
+
+#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
+static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
+                                      const char *phy_type, int start_offset)
+{
+       const char *compat_dr = "fsl-usb2-dr";
+       const char *compat_mph = "fsl-usb2-mph";
+       const char *prop_mode = "dr_mode";
+       const char *prop_type = "phy_type";
+       const char *node_type = NULL;
+       int node_offset;
+       int err;
+
+       node_offset = fdt_node_offset_by_compatible(blob,
+                                                   start_offset, compat_mph);
+       if (node_offset < 0) {
+               node_offset = fdt_node_offset_by_compatible(blob,
+                                                           start_offset,
+                                                           compat_dr);
+               if (node_offset < 0) {
+                       printf("WARNING: could not find compatible node: %s",
+                              fdt_strerror(node_offset));
+                       return -1;
+               }
+               node_type = compat_dr;
+       } else {
+               node_type = compat_mph;
+       }
+
+       if (mode) {
+               err = fdt_setprop(blob, node_offset, prop_mode, mode,
+                                 strlen(mode) + 1);
+               if (err < 0)
+                       printf("WARNING: could not set %s for %s: %s.\n",
+                              prop_mode, node_type, fdt_strerror(err));
+       }
+
+       if (phy_type) {
+               err = fdt_setprop(blob, node_offset, prop_type, phy_type,
+                                 strlen(phy_type) + 1);
+               if (err < 0)
+                       printf("WARNING: could not set %s for %s: %s.\n",
+                              prop_type, node_type, fdt_strerror(err));
+       }
+
+       return node_offset;
+}
+
+static const char *fdt_usb_get_node_type(void *blob, int start_offset,
+                                        int *node_offset)
+{
+       const char *compat_dr = "fsl-usb2-dr";
+       const char *compat_mph = "fsl-usb2-mph";
+       const char *node_type = NULL;
+
+       *node_offset = fdt_node_offset_by_compatible(blob, start_offset,
+                                                    compat_mph);
+       if (*node_offset < 0) {
+               *node_offset = fdt_node_offset_by_compatible(blob,
+                                                            start_offset,
+                                                            compat_dr);
+               if (*node_offset < 0) {
+                       printf("ERROR: could not find compatible node: %s\n",
+                              fdt_strerror(*node_offset));
+               } else {
+                       node_type = compat_dr;
+               }
+       } else {
+               node_type = compat_mph;
+       }
+
+       return node_type;
+}
+
+static int fdt_fixup_usb_erratum(void *blob, const char *prop_erratum,
+                                int start_offset)
+{
+       int node_offset, err;
+       const char *node_type = NULL;
+
+       node_type = fdt_usb_get_node_type(blob, start_offset, &node_offset);
+       if (!node_type)
+               return -1;
+
+       err = fdt_setprop(blob, node_offset, prop_erratum, NULL, 0);
+       if (err < 0) {
+               printf("ERROR: could not set %s for %s: %s.\n",
+                      prop_erratum, node_type, fdt_strerror(err));
+       }
+
+       return node_offset;
+}
+
+void fdt_fixup_dr_usb(void *blob, bd_t *bd)
+{
+       static const char * const modes[] = { "host", "peripheral", "otg" };
+       static const char * const phys[] = { "ulpi", "utmi" };
+       int usb_erratum_a006261_off = -1;
+       int usb_erratum_a007075_off = -1;
+       int usb_erratum_a007792_off = -1;
+       int usb_mode_off = -1;
+       int usb_phy_off = -1;
+       char str[5];
+       int i, j;
+
+       for (i = 1; i <= CONFIG_USB_MAX_CONTROLLER_COUNT; i++) {
+               const char *dr_mode_type = NULL;
+               const char *dr_phy_type = NULL;
+               int mode_idx = -1, phy_idx = -1;
+
+               snprintf(str, 5, "%s%d", "usb", i);
+               if (hwconfig(str)) {
+                       for (j = 0; j < ARRAY_SIZE(modes); j++) {
+                               if (hwconfig_subarg_cmp(str, "dr_mode",
+                                                       modes[j])) {
+                                       mode_idx = j;
+                                       break;
+                               }
+                       }
+
+                       for (j = 0; j < ARRAY_SIZE(phys); j++) {
+                               if (hwconfig_subarg_cmp(str, "phy_type",
+                                                       phys[j])) {
+                                       phy_idx = j;
+                                       break;
+                               }
+                       }
+
+                       if (mode_idx < 0 && phy_idx < 0) {
+                               printf("WARNING: invalid phy or mode\n");
+                               return;
+                       }
+
+                       if (mode_idx > -1)
+                               dr_mode_type = modes[mode_idx];
+
+                       if (phy_idx > -1)
+                               dr_phy_type = phys[phy_idx];
+               }
+
+               usb_mode_off = fdt_fixup_usb_mode_phy_type(blob,
+                                                          dr_mode_type, NULL,
+                                                          usb_mode_off);
+
+               if (usb_mode_off < 0)
+                       return;
+
+               usb_phy_off = fdt_fixup_usb_mode_phy_type(blob,
+                                                         NULL, dr_phy_type,
+                                                         usb_phy_off);
+
+               if (usb_phy_off < 0)
+                       return;
+
+               if (has_erratum_a006261()) {
+                       usb_erratum_a006261_off =  fdt_fixup_usb_erratum
+                                                  (blob,
+                                                   "fsl,usb-erratum-a006261",
+                                                   usb_erratum_a006261_off);
+                       if (usb_erratum_a006261_off < 0)
+                               return;
+               }
+               if (has_erratum_a007075()) {
+                       usb_erratum_a007075_off =  fdt_fixup_usb_erratum
+                                                  (blob,
+                                                   "fsl,usb-erratum-a007075",
+                                                   usb_erratum_a007075_off);
+                       if (usb_erratum_a007075_off < 0)
+                               return;
+               }
+               if (has_erratum_a007792()) {
+                       usb_erratum_a007792_off =  fdt_fixup_usb_erratum
+                                                  (blob,
+                                                   "fsl,usb-erratum-a007792",
+                                                   usb_erratum_a007792_off);
+                       if (usb_erratum_a007792_off < 0)
+                               return;
+               }
+       }
+}
+#endif
index 48e10ec..8dc04f2 100644 (file)
@@ -37,8 +37,85 @@ unsigned long get_board_sys_clk(void);
 unsigned long get_board_ddr_clk(void);
 #endif
 
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_SYS_CLK_FREQ            100000000
+#define CONFIG_DDR_CLK_FREQ            100000000
+#define CONFIG_QIXIS_I2C_ACCESS
+#else
 #define CONFIG_SYS_CLK_FREQ            get_board_sys_clk()
 #define CONFIG_DDR_CLK_FREQ            get_board_ddr_clk()
+#endif
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg
+#endif
+
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LDSCRIPT    "arch/$(ARCH)/cpu/u-boot-spl.lds"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR                0xe8
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS             0x400
+
+#define CONFIG_SPL_TEXT_BASE           0x10000000
+#define CONFIG_SPL_MAX_SIZE            0x1a000
+#define CONFIG_SPL_STACK               0x1001d000
+#define CONFIG_SPL_PAD_TO              0x1c000
+#define CONFIG_SYS_TEXT_BASE           0x82000000
+
+#define CONFIG_SYS_SPL_MALLOC_START    0x80200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE     0x100000
+#define CONFIG_SPL_BSS_START_ADDR      0x80100000
+#define CONFIG_SPL_BSS_MAX_SIZE                0x80000
+#define CONFIG_SYS_MONITOR_LEN         0x80000
+#endif
+
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_SYS_TEXT_BASE           0x40010000
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LDSCRIPT    "arch/$(ARCH)/cpu/u-boot-spl.lds"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+
+#define CONFIG_SPL_TEXT_BASE           0x10000000
+#define CONFIG_SPL_MAX_SIZE            0x1a000
+#define CONFIG_SPL_STACK               0x1001d000
+#define CONFIG_SPL_PAD_TO              0x1c000
+#define CONFIG_SYS_TEXT_BASE           0x82000000
+
+#define CONFIG_SYS_NAND_U_BOOT_SIZE    (400 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS    CONFIG_SPL_PAD_TO
+#define CONFIG_SYS_NAND_PAGE_SIZE      2048
+#define CONFIG_SYS_NAND_U_BOOT_DST     CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_SPL_MALLOC_START    0x80200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE     0x100000
+#define CONFIG_SPL_BSS_START_ADDR      0x80100000
+#define CONFIG_SPL_BSS_MAX_SIZE                0x80000
+#define CONFIG_SYS_MONITOR_LEN         0x80000
+#endif
 
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE           0x67f80000
@@ -71,13 +148,15 @@ unsigned long get_board_ddr_clk(void);
 
 #define CONFIG_FSL_CAAM                        /* Enable CAAM */
 
-#if !defined(CONFIG_SDCARD) && !defined(CONFIG_NAND) && !defined(CONFIG_SPI)
+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
+       !defined(CONFIG_QSPI_BOOT)
 #define CONFIG_U_QE
 #endif
 
 /*
  * IFC Definitions
  */
+#ifndef CONFIG_QSPI_BOOT
 #define CONFIG_FSL_IFC
 #define CONFIG_SYS_FLASH_BASE          0x60000000
 #define CONFIG_SYS_FLASH_BASE_PHYS     CONFIG_SYS_FLASH_BASE
@@ -170,6 +249,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_CMD_NAND
 
 #define CONFIG_SYS_NAND_BLOCK_SIZE     (128 * 1024)
+#endif
 
 /*
  * QIXIS Definitions
@@ -214,6 +294,40 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_FPGA_FTIM3          0x0
 #endif
 
+#if defined(CONFIG_NAND_BOOT)
+#define CONFIG_SYS_CSPR0_EXT           CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0               CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0              CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0               CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0           CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1           CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2           CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3           CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT           CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1               CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK1              CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1               CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0           CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1           CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2           CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3           CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT           CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR2               CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK2              CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2               CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0           CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1           CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2           CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3           CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR3_EXT           CONFIG_SYS_FPGA_CSPR_EXT
+#define CONFIG_SYS_CSPR3               CONFIG_SYS_FPGA_CSPR
+#define CONFIG_SYS_AMASK3              CONFIG_SYS_FPGA_AMASK
+#define CONFIG_SYS_CSOR3               CONFIG_SYS_FPGA_CSOR
+#define CONFIG_SYS_CS3_FTIM0           CONFIG_SYS_FPGA_FTIM0
+#define CONFIG_SYS_CS3_FTIM1           CONFIG_SYS_FPGA_FTIM1
+#define CONFIG_SYS_CS3_FTIM2           CONFIG_SYS_FPGA_FTIM2
+#define CONFIG_SYS_CS3_FTIM3           CONFIG_SYS_FPGA_FTIM3
+#else
 #define CONFIG_SYS_CSPR0_EXT           CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR0               CONFIG_SYS_NOR0_CSPR
 #define CONFIG_SYS_AMASK0              CONFIG_SYS_NOR_AMASK
@@ -246,6 +360,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CS3_FTIM1           CONFIG_SYS_FPGA_FTIM1
 #define CONFIG_SYS_CS3_FTIM2           CONFIG_SYS_FPGA_FTIM2
 #define CONFIG_SYS_CS3_FTIM3           CONFIG_SYS_FPGA_FTIM3
+#endif
 
 /*
  * Serial Port
@@ -279,6 +394,21 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_FSL_ESDHC
 #define CONFIG_GENERIC_MMC
 
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+/* QSPI */
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_FSL_QSPI
+#define QSPI0_AMBA_BASE                        0x40000000
+#define FSL_QSPI_FLASH_SIZE            (1 << 24)
+#define FSL_QSPI_FLASH_NUM             2
+
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#endif
+
 /*
  * USB
  */
@@ -341,6 +471,14 @@ unsigned long get_board_ddr_clk(void);
 #endif
 
 #endif
+
+/* PCIe */
+#define CONFIG_PCI             /* Enable PCI/PCIE */
+#define CONFIG_PCIE1           /* PCIE controler 1 */
+#define CONFIG_PCIE2           /* PCIE controler 2 */
+#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
+#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
+
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
@@ -348,7 +486,20 @@ unsigned long get_board_ddr_clk(void);
 
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_CMDLINE_EDITING
+
+#ifdef CONFIG_QSPI_BOOT
+#undef CONFIG_CMD_IMLS
+#else
 #define CONFIG_CMD_IMLS
+#endif
+
+#define CONFIG_ARMV7_NONSEC
+#define CONFIG_ARMV7_VIRT
+#define CONFIG_PEN_ADDR_BIG_ENDIAN
+#define CONFIG_LS102XA_NS_ACCESS
+#define CONFIG_SMP_PEN_ADDR            0x01ee0200
+#define CONFIG_TIMER_CLK_FREQ          12500000
+#define CONFIG_ARMV7_SECURE_BASE       OCRAM_BASE_S_ADDR
 
 #define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE           128
@@ -385,6 +536,8 @@ unsigned long get_board_ddr_clk(void);
 
 #define CONFIG_SYS_LOAD_ADDR           0x82000000
 
+#define CONFIG_LS102XA_STREAM_ID
+
 /*
  * Stack sizes
  * The stack sizes are set up in start.S using the settings below
@@ -396,17 +549,37 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_INIT_SP_ADDR \
        (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
+#endif
 
 /*
  * Environment
  */
 #define CONFIG_ENV_OVERWRITE
 
+#if defined(CONFIG_SD_BOOT)
+#define CONFIG_ENV_OFFSET              0x100000
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV         0
+#define CONFIG_ENV_SIZE                        0x2000
+#elif defined(CONFIG_QSPI_BOOT)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE                        0x2000          /* 8KB */
+#define CONFIG_ENV_OFFSET              0x100000        /* 1MB */
+#define CONFIG_ENV_SECT_SIZE           0x10000
+#elif defined(CONFIG_NAND_BOOT)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE                        0x2000
+#define CONFIG_ENV_OFFSET              (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_ADDR                (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE                        0x2000
 #define CONFIG_ENV_SECT_SIZE           0x20000 /* 128K (one sector) */
+#endif
 
 #define CONFIG_OF_LIBFDT
 #define CONFIG_OF_BOARD_SETUP
index 3eac7ee..66954d0 100644 (file)
 #define CONFIG_SYS_CLK_FREQ            100000000
 #define CONFIG_DDR_CLK_FREQ            100000000
 
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg
+#endif
+
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LDSCRIPT    "arch/$(ARCH)/cpu/u-boot-spl.lds"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR                0xe8
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS             0x400
+
+#define CONFIG_SPL_TEXT_BASE           0x10000000
+#define CONFIG_SPL_MAX_SIZE            0x1a000
+#define CONFIG_SPL_STACK               0x1001d000
+#define CONFIG_SPL_PAD_TO              0x1c000
+#define CONFIG_SYS_TEXT_BASE           0x82000000
+
+#define CONFIG_SYS_SPL_MALLOC_START    0x80200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE     0x100000
+#define CONFIG_SPL_BSS_START_ADDR      0x80100000
+#define CONFIG_SPL_BSS_MAX_SIZE                0x80000
+#define CONFIG_SYS_MONITOR_LEN         0x80000
+#endif
+
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_SYS_TEXT_BASE           0x40010000
+#define CONFIG_SYS_NO_FLASH
+#endif
+
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE           0x67f80000
 #endif
 
 #define CONFIG_FSL_CAAM                        /* Enable CAAM */
 
-#if !defined(CONFIG_SDCARD) && !defined(CONFIG_NAND) && !defined(CONFIG_SPI)
+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
+       !defined(CONFIG_QSPI_BOOT)
 #define CONFIG_U_QE
 #endif
 
 /*
  * IFC Definitions
  */
+#ifndef CONFIG_QSPI_BOOT
 #define CONFIG_FSL_IFC
 #define CONFIG_SYS_FLASH_BASE          0x60000000
 #define CONFIG_SYS_FLASH_BASE_PHYS     CONFIG_SYS_FLASH_BASE
 
 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 #define CONFIG_SYS_WRITE_SWAPPED_DATA
+#endif
 
 /* CPLD */
 
 #define CONFIG_FSL_ESDHC
 #define CONFIG_GENERIC_MMC
 
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+/* QSPI */
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_FSL_QSPI
+#define QSPI0_AMBA_BASE                        0x40000000
+#define FSL_QSPI_FLASH_SIZE            (1 << 24)
+#define FSL_QSPI_FLASH_NUM             2
+
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#endif
+
 /*
  * Video
  */
 #define CONFIG_HAS_ETH2
 #endif
 
+/* PCIe */
+#define CONFIG_PCI             /* Enable PCI/PCIE */
+#define CONFIG_PCIE1           /* PCIE controler 1 */
+#define CONFIG_PCIE2           /* PCIE controler 2 */
+#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
+#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
+
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
 
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_CMDLINE_EDITING
+
+#ifdef CONFIG_QSPI_BOOT
+#undef CONFIG_CMD_IMLS
+#else
 #define CONFIG_CMD_IMLS
+#endif
+
+#define CONFIG_ARMV7_NONSEC
+#define CONFIG_ARMV7_VIRT
+#define CONFIG_PEN_ADDR_BIG_ENDIAN
+#define CONFIG_LS102XA_NS_ACCESS
+#define CONFIG_SMP_PEN_ADDR            0x01ee0200
+#define CONFIG_TIMER_CLK_FREQ          12500000
+#define CONFIG_ARMV7_SECURE_BASE       OCRAM_BASE_S_ADDR
 
 #define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE           128
 
 #define CONFIG_SYS_LOAD_ADDR           0x82000000
 
+#define CONFIG_LS102XA_STREAM_ID
+
 /*
  * Stack sizes
  * The stack sizes are set up in start.S using the settings below
 #define CONFIG_SYS_INIT_SP_ADDR \
        (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
+#endif
 
 #define CONFIG_SYS_QE_FW_ADDR     0x67f40000
 
  */
 #define CONFIG_ENV_OVERWRITE
 
+#if defined(CONFIG_SD_BOOT)
+#define CONFIG_ENV_OFFSET              0x100000
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV         0
+#define CONFIG_ENV_SIZE                        0x20000
+#elif defined(CONFIG_QSPI_BOOT)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE                        0x2000
+#define CONFIG_ENV_OFFSET              0x100000
+#define CONFIG_ENV_SECT_SIZE           0x10000
+#else
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_ADDR                (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE                        0x20000
 #define CONFIG_ENV_SECT_SIZE           0x20000 /* 128K (one sector) */
+#endif
 
 #define CONFIG_OF_LIBFDT
 #define CONFIG_OF_BOARD_SETUP
index f6b1b3e..ccec50c 100644 (file)
@@ -25,6 +25,7 @@
 #define CONFIG_ARMV7_PSCI              1
 #define CONFIG_ARMV7_SECURE_BASE       SUNXI_SRAM_B_BASE
 #define CONFIG_SYS_CLK_FREQ            24000000
+#define CONFIG_TIMER_CLK_FREQ          CONFIG_SYS_CLK_FREQ
 
 /*
  * Include common sunxi configuration where most the settings are
index 5b03c14..095b33e 100644 (file)
@@ -114,6 +114,7 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
 #define SDRAM_CFG_2T_EN                        0x00008000
 #define SDRAM_CFG_BI                   0x00000001
 
+#define SDRAM_CFG2_FRC_SR              0x80000000
 #define SDRAM_CFG2_D_INIT              0x00000010
 #define SDRAM_CFG2_ODT_CFG_MASK                0x00600000
 #define SDRAM_CFG2_ODT_NEVER           0
@@ -163,6 +164,7 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
 #define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT)
 #define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)
 #define DDR_CDR2_VREF_OVRD(x)  (0x00008080 | ((((x) - 37) & 0x3F) << 8))
+#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
 
 #if (defined(CONFIG_SYS_FSL_DDR_VER) && \
        (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
@@ -202,6 +204,8 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
 #define DDR_CDR_ODT_120ohm     0x6
 #endif
 
+#define DDR_INIT_ADDR_EXT_UIA  (1 << 31)
+
 /* Record of register values computed */
 typedef struct fsl_ddr_cfg_regs_s {
        struct {
@@ -414,9 +418,11 @@ static int __board_need_mem_reset(void)
 int board_need_mem_reset(void)
        __attribute__((weak, alias("__board_need_mem_reset")));
 
-void __weak board_mem_sleep_setup(void)
-{
-}
+#if defined(CONFIG_DEEP_SLEEP)
+void board_mem_sleep_setup(void);
+bool is_warm_boot(void);
+int fsl_dp_resume(void);
+#endif
 
 /*
  * The 85xx boards have a common prototype for fixed_sdram so put the
index e4902aa..d251f5d 100644 (file)
@@ -145,6 +145,25 @@ static inline bool has_erratum_a007798(void)
        return SVR_SOC_VER(get_svr()) == SVR_T4240 &&
                IS_SVR_REV(get_svr(), 2, 0);
 }
+
+static inline bool has_erratum_a007792(void)
+{
+       u32 svr = get_svr();
+       u32 soc = SVR_SOC_VER(svr);
+
+       switch (soc) {
+       case SVR_T4240:
+       case SVR_T4160:
+               return IS_SVR_REV(svr, 2, 0);
+       case SVR_T1040:
+               return IS_SVR_REV(svr, 1, 0);
+       case SVR_T2080:
+       case SVR_T2081:
+               return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
+       }
+       return false;
+}
+
 #else
 static inline bool has_erratum_a006261(void)
 {
@@ -161,5 +180,9 @@ static inline bool has_erratum_a007798(void)
        return false;
 }
 
+static inline bool has_erratum_a007792(void)
+{
+       return false;
+}
 #endif
 #endif /*_ASM_FSL_USB_H_ */
index 6e6e801..2a799ab 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2012-2014 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
@@ -8,6 +8,10 @@
 #include "pblimage.h"
 #include "pbl_crc32.h"
 
+#define roundup(x, y)          ((((x) + ((y) - 1)) / (y)) * (y))
+#define PBL_ACS_CONT_CMD       0x81000000
+#define PBL_ADDR_24BIT_MASK    0x00ffffff
+
 /*
  * Initialize to an invalid value.
  */
@@ -22,6 +26,13 @@ static int pbl_size;
 static char *fname = "Unknown";
 static int lineno = -1;
 static struct pbl_header pblimage_header;
+static int uboot_size;
+static int arch_flag;
+
+static uint32_t pbl_cmd_initaddr;
+static uint32_t pbi_crc_cmd1;
+static uint32_t pbi_crc_cmd2;
+static uint32_t pbl_end_cmd[4];
 
 static union
 {
@@ -38,20 +49,6 @@ static union
  * start offset by subtracting the size of the u-boot image from the
  * top of the allowable 24-bit range.
  */
-static void init_next_pbl_cmd(FILE *fp_uboot)
-{
-       struct stat st;
-       int fd = fileno(fp_uboot);
-
-       if (fstat(fd, &st) == -1) {
-               printf("Error: Could not determine u-boot image size. %s\n",
-                       strerror(errno));
-               exit(EXIT_FAILURE);
-       }
-
-       next_pbl_cmd = 0x82000000 - st.st_size;
-}
-
 static void generate_pbl_cmd(void)
 {
        uint32_t val = next_pbl_cmd;
@@ -66,11 +63,15 @@ static void generate_pbl_cmd(void)
 
 static void pbl_fget(size_t size, FILE *stream)
 {
-       unsigned char c;
+       unsigned char c = 0xff;
        int c_temp;
 
-       while (size && (c_temp = fgetc(stream)) != EOF) {
-               c = (unsigned char)c_temp;
+       while (size) {
+               c_temp = fgetc(stream);
+               if (c_temp != EOF)
+                       c = (unsigned char)c_temp;
+               else if ((c_temp == EOF) && (arch_flag == IH_ARCH_ARM))
+                       c = 0xff;
                *pmem_buf++ = c;
                pbl_size++;
                size--;
@@ -80,8 +81,8 @@ static void pbl_fget(size_t size, FILE *stream)
 /* load split u-boot with PBI command 81xxxxxx. */
 static void load_uboot(FILE *fp_uboot)
 {
-       init_next_pbl_cmd(fp_uboot);
-       while (next_pbl_cmd < 0x82000000) {
+       next_pbl_cmd = pbl_cmd_initaddr - uboot_size;
+       while (next_pbl_cmd < pbl_cmd_initaddr) {
                generate_pbl_cmd();
                pbl_fget(64, fp_uboot);
        }
@@ -154,8 +155,6 @@ static uint32_t reverse_byte(uint32_t val)
 /* write end command and crc command to memory. */
 static void add_end_cmd(void)
 {
-       uint32_t pbl_end_cmd[4] = {0x09138000, 0x00000000,
-               0x091380c0, 0x00000000};
        uint32_t crc32_pbl;
        int i;
        unsigned char *p = (unsigned char *)&pbl_end_cmd;
@@ -172,8 +171,8 @@ static void add_end_cmd(void)
 
        /* Add PBI CRC command. */
        *pmem_buf++ = 0x08;
-       *pmem_buf++ = 0x13;
-       *pmem_buf++ = 0x80;
+       *pmem_buf++ = pbi_crc_cmd1;
+       *pmem_buf++ = pbi_crc_cmd2;
        *pmem_buf++ = 0x40;
        pbl_size += 4;
 
@@ -184,17 +183,6 @@ static void add_end_cmd(void)
        *pmem_buf++ = (crc32_pbl >> 8) & 0xff;
        *pmem_buf++ = (crc32_pbl) & 0xff;
        pbl_size += 4;
-
-       if ((pbl_size % 16) != 0) {
-               for (i = 0; i < 8; i++) {
-                       *pmem_buf++ = 0x0;
-                       pbl_size++;
-               }
-       }
-       if ((pbl_size % 16 != 0)) {
-               printf("Error: Bad size of image file\n");
-               exit(EXIT_FAILURE);
-       }
 }
 
 void pbl_load_uboot(int ifd, struct image_tool_params *params)
@@ -268,12 +256,64 @@ static void pblimage_set_header(void *ptr, struct stat *sbuf, int ifd,
        /*nothing need to do, pbl_load_uboot takes care of whole file. */
 }
 
+int pblimage_check_params(struct image_tool_params *params)
+{
+       FILE *fp_uboot;
+       int fd;
+       struct stat st;
+
+       if (!params)
+               return EXIT_FAILURE;
+
+       fp_uboot = fopen(params->datafile, "r");
+       if (fp_uboot == NULL) {
+               printf("Error: %s open failed\n", params->datafile);
+               exit(EXIT_FAILURE);
+       }
+       fd = fileno(fp_uboot);
+
+       if (fstat(fd, &st) == -1) {
+               printf("Error: Could not determine u-boot image size. %s\n",
+                      strerror(errno));
+               exit(EXIT_FAILURE);
+       }
+
+       /* For the variable size, we need to pad it to 64 byte boundary */
+       uboot_size = roundup(st.st_size, 64);
+
+       if (params->arch == IH_ARCH_ARM) {
+               arch_flag = IH_ARCH_ARM;
+               pbi_crc_cmd1 = 0x61;
+               pbi_crc_cmd2 = 0;
+               pbl_cmd_initaddr = params->addr & PBL_ADDR_24BIT_MASK;
+               pbl_cmd_initaddr |= PBL_ACS_CONT_CMD;
+               pbl_cmd_initaddr |= uboot_size;
+               pbl_end_cmd[0] = 0x09610000;
+               pbl_end_cmd[1] = 0x00000000;
+               pbl_end_cmd[2] = 0x096100c0;
+               pbl_end_cmd[3] = 0x00000000;
+       } else if (params->arch == IH_ARCH_PPC) {
+               arch_flag = IH_ARCH_PPC;
+               pbi_crc_cmd1 = 0x13;
+               pbi_crc_cmd2 = 0x80;
+               pbl_cmd_initaddr = 0x82000000;
+               pbl_end_cmd[0] = 0x09138000;
+               pbl_end_cmd[1] = 0x00000000;
+               pbl_end_cmd[2] = 0x091380c0;
+               pbl_end_cmd[3] = 0x00000000;
+       }
+
+       next_pbl_cmd = pbl_cmd_initaddr;
+       return 0;
+};
+
 /* pblimage parameters */
 static struct image_type_params pblimage_params = {
        .name           = "Freescale PBL Boot Image support",
        .header_size    = sizeof(struct pbl_header),
        .hdr            = (void *)&pblimage_header,
        .check_image_type = pblimage_check_image_types,
+       .check_params   = pblimage_check_params,
        .verify_header  = pblimage_verify_header,
        .print_header   = pblimage_print_header,
        .set_header     = pblimage_set_header,