Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
authorTom Rini <trini@ti.com>
Thu, 11 Dec 2014 23:28:09 +0000 (18:28 -0500)
committerTom Rini <trini@ti.com>
Thu, 11 Dec 2014 23:28:09 +0000 (18:28 -0500)
63 files changed:
MAINTAINERS
arch/arm/Kconfig
arch/arm/cpu/armv7/Makefile
arch/arm/cpu/armv7/mx6/clock.c
arch/arm/cpu/armv7/stv0991/Makefile [new file with mode: 0644]
arch/arm/cpu/armv7/stv0991/clock.c [new file with mode: 0644]
arch/arm/cpu/armv7/stv0991/lowlevel.S [new file with mode: 0644]
arch/arm/cpu/armv7/stv0991/pinmux.c [new file with mode: 0644]
arch/arm/cpu/armv7/stv0991/reset.c [new file with mode: 0644]
arch/arm/cpu/armv7/stv0991/timer.c [new file with mode: 0644]
arch/arm/cpu/armv7/vf610/generic.c
arch/arm/imx-common/cpu.c
arch/arm/include/asm/arch-mx6/clock.h
arch/arm/include/asm/arch-rmobile/mmc.h [new file with mode: 0644]
arch/arm/include/asm/arch-rmobile/r8a7790.h
arch/arm/include/asm/arch-rmobile/r8a7791.h
arch/arm/include/asm/arch-rmobile/r8a7793.h
arch/arm/include/asm/arch-rmobile/r8a7794.h
arch/arm/include/asm/arch-rmobile/rcar-base.h
arch/arm/include/asm/arch-rmobile/rcar-mstp.h [new file with mode: 0644]
arch/arm/include/asm/arch-stv0991/gpio.h [new file with mode: 0644]
arch/arm/include/asm/arch-stv0991/hardware.h [new file with mode: 0644]
arch/arm/include/asm/arch-stv0991/stv0991_cgu.h [new file with mode: 0644]
arch/arm/include/asm/arch-stv0991/stv0991_creg.h [new file with mode: 0644]
arch/arm/include/asm/arch-stv0991/stv0991_defs.h [new file with mode: 0644]
arch/arm/include/asm/arch-stv0991/stv0991_gpt.h [new file with mode: 0644]
arch/arm/include/asm/arch-stv0991/stv0991_periph.h [new file with mode: 0644]
arch/arm/include/asm/arch-stv0991/stv0991_wdru.h [new file with mode: 0644]
arch/arm/include/asm/arch-vf610/imx-regs.h
board/aristainetos/aristainetos.c
board/freescale/mx6slevk/mx6slevk.c
board/freescale/mx6sxsabresd/mx6sxsabresd.c
board/renesas/alt/Makefile
board/renesas/alt/alt.c
board/renesas/gose/Makefile
board/renesas/gose/gose.c
board/renesas/koelsch/Makefile
board/renesas/koelsch/koelsch.c
board/renesas/lager/Makefile
board/renesas/lager/lager.c
board/renesas/rcar-gen2-common/common.c [new file with mode: 0644]
board/solidrun/hummingboard/hummingboard.c
board/st/stv0991/Kconfig [new file with mode: 0644]
board/st/stv0991/MAINTAINERS [new file with mode: 0644]
board/st/stv0991/Makefile [new file with mode: 0644]
board/st/stv0991/stv0991.c [new file with mode: 0644]
board/tbs/tbs2910/Kconfig
configs/stv0991_defconfig [new file with mode: 0644]
drivers/block/dwc_ahsata.c
drivers/misc/mxc_ocotp.c
drivers/misc/mxs_ocotp.c
drivers/thermal/imx_thermal.c
include/config_fallbacks.h
include/configs/alt.h
include/configs/gose.h
include/configs/koelsch.h
include/configs/lager.h
include/configs/mx53loco.h
include/configs/mx6sabre_common.h
include/configs/mx6sxsabresd.h
include/configs/rcar-gen2-common.h
include/configs/stv0991.h [new file with mode: 0644]
include/configs/tbs2910.h

index 0cf2602..6041936 100644 (file)
@@ -128,6 +128,12 @@ T: git git://git.denx.de/u-boot-stm.git
 F:     arch/arm/cpu/arm926ejs/spear/
 F:     arch/arm/include/asm/arch-spear/
 
+ARM STM STV0991
+M:     Vikas Manocha <vikas.manocha@st.com>
+S:     Maintained
+F:     arch/arm/cpu/armv7/stv0991/
+F:     arch/arm/include/asm/arch-stv0991/
+
 ARM SUNXI
 M:     Ian Campbell <ijc@hellion.org.uk>
 M:     Hans De Goede <hdegoede@redhat.com>
index c026dec..2b0d2c9 100644 (file)
@@ -341,6 +341,10 @@ config TARGET_SPEAR600
        bool "Support spear600"
        select CPU_ARM926EJS
 
+config TARGET_STV0991
+       bool "Support stv0991"
+       select CPU_V7
+
 config TARGET_X600
        bool "Support x600"
        select CPU_ARM926EJS
@@ -650,6 +654,7 @@ config TARGET_KOSAGI_NOVENA
 
 config TARGET_TBS2910
        bool "Support tbs2910"
+       select CPU_V7
 
 config TARGET_TQMA6
        bool "TQ Systems TQMa6 board"
@@ -955,6 +960,7 @@ source "board/spear/spear600/Kconfig"
 source "board/spear/x600/Kconfig"
 source "board/st-ericsson/snowball/Kconfig"
 source "board/st-ericsson/u8500/Kconfig"
+source "board/st/stv0991/Kconfig"
 source "board/sunxi/Kconfig"
 source "board/syteco/jadecpu/Kconfig"
 source "board/syteco/zmx25/Kconfig"
index e419716..409e6f5 100644 (file)
@@ -56,6 +56,7 @@ obj-$(CONFIG_OMAP54XX) += omap5/
 obj-$(CONFIG_RMOBILE) += rmobile/
 obj-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx/
 obj-$(CONFIG_SOCFPGA) += socfpga/
+obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
 obj-$(CONFIG_ARCH_SUNXI) += sunxi/
 obj-$(CONFIG_TEGRA20) += tegra20/
 obj-$(CONFIG_U8500) += u8500/
index ab7ac3d..93a02ad 100644 (file)
@@ -443,7 +443,7 @@ int enable_fec_anatop_clock(enum enet_freq freq)
        struct anatop_regs __iomem *anatop =
                (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
 
-       if (freq < ENET_25MHz || freq > ENET_125MHz)
+       if (freq < ENET_25MHZ || freq > ENET_125MHZ)
                return -EINVAL;
 
        reg = readl(&anatop->pll_enet);
diff --git a/arch/arm/cpu/armv7/stv0991/Makefile b/arch/arm/cpu/armv7/stv0991/Makefile
new file mode 100644 (file)
index 0000000..95641d3
--- /dev/null
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2014
+# Vikas Manocha, ST Microelectronics, vikas.manocha@stcom
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y  := timer.o clock.o pinmux.o reset.o
+obj-y  += lowlevel.o
diff --git a/arch/arm/cpu/armv7/stv0991/clock.c b/arch/arm/cpu/armv7/stv0991/clock.c
new file mode 100644 (file)
index 0000000..70b8a8d
--- /dev/null
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2014
+ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/stv0991_cgu.h>
+#include<asm/arch/stv0991_periph.h>
+
+static struct stv0991_cgu_regs *const stv0991_cgu_regs = \
+                               (struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
+
+void enable_pll1(void)
+{
+       /* pll1 already configured for 1000Mhz, just need to enable it */
+       writel(readl(&stv0991_cgu_regs->pll1_ctrl) & ~(0x01),
+                       &stv0991_cgu_regs->pll1_ctrl);
+}
+
+void clock_setup(int peripheral)
+{
+       switch (peripheral) {
+       case UART_CLOCK_CFG:
+               writel(UART_CLK_CFG, &stv0991_cgu_regs->uart_freq);
+               break;
+       case ETH_CLOCK_CFG:
+               enable_pll1();
+               writel(ETH_CLK_CFG, &stv0991_cgu_regs->eth_freq);
+
+               /* Clock selection for ethernet tx_clk & rx_clk*/
+               writel((readl(&stv0991_cgu_regs->eth_ctrl) & ETH_CLK_MASK)
+                               | ETH_CLK_CTRL, &stv0991_cgu_regs->eth_ctrl);
+
+               break;
+       default:
+               break;
+       }
+}
diff --git a/arch/arm/cpu/armv7/stv0991/lowlevel.S b/arch/arm/cpu/armv7/stv0991/lowlevel.S
new file mode 100644 (file)
index 0000000..6dafba3
--- /dev/null
@@ -0,0 +1,12 @@
+/*
+ * (C) Copyright 2014 stmicroelectronics
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+ENTRY(lowlevel_init)
+       mov     pc, lr
+ENDPROC(lowlevel_init)
diff --git a/arch/arm/cpu/armv7/stv0991/pinmux.c b/arch/arm/cpu/armv7/stv0991/pinmux.c
new file mode 100644 (file)
index 0000000..1d086a2
--- /dev/null
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2014
+ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <asm/arch/stv0991_creg.h>
+#include <asm/arch/stv0991_periph.h>
+#include <asm/arch/hardware.h>
+
+static struct stv0991_creg *const stv0991_creg = \
+                       (struct stv0991_creg *)CREG_BASE_ADDR;
+
+int stv0991_pinmux_config(int peripheral)
+{
+       switch (peripheral) {
+       case UART_GPIOC_30_31:
+               /* SSDA/SSCL pad muxing to UART Rx/Dx */
+               writel((readl(&stv0991_creg->mux12) & GPIOC_31_MUX_MASK) |
+                               CFG_GPIOC_31_UART_RX,
+                               &stv0991_creg->mux12);
+               writel((readl(&stv0991_creg->mux12) & GPIOC_30_MUX_MASK) |
+                               CFG_GPIOC_30_UART_TX,
+                               &stv0991_creg->mux12);
+               /* SSDA/SSCL pad config to push pull*/
+               writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_31_MODE_MASK) |
+                               CFG_GPIOC_31_MODE_PP,
+                               &stv0991_creg->cfg_pad6);
+               writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_30_MODE_MASK) |
+                               CFG_GPIOC_30_MODE_HIGH,
+                               &stv0991_creg->cfg_pad6);
+               break;
+       case UART_GPIOB_16_17:
+               /* ethernet rx_6/7 to UART Rx/Dx */
+               writel((readl(&stv0991_creg->mux7) & GPIOB_17_MUX_MASK) |
+                               CFG_GPIOB_17_UART_RX,
+                               &stv0991_creg->mux7);
+               writel((readl(&stv0991_creg->mux7) & GPIOB_16_MUX_MASK) |
+                               CFG_GPIOB_16_UART_TX,
+                               &stv0991_creg->mux7);
+               break;
+       case ETH_GPIOB_10_31_C_0_4:
+               writel(readl(&stv0991_creg->mux6) & 0x000000FF,
+                               &stv0991_creg->mux6);
+               writel(0x00000000, &stv0991_creg->mux7);
+               writel(0x00000000, &stv0991_creg->mux8);
+               writel(readl(&stv0991_creg->mux9) & 0xFFF00000,
+                               &stv0991_creg->mux9);
+               /* Ethernet Voltage configuration to 1.8V*/
+               writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) |
+                               ETH_VDD_CFG, &stv0991_creg->vdd_pad1);
+               writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) |
+                               ETH_M_VDD_CFG, &stv0991_creg->vdd_pad1);
+
+               break;
+       default:
+               break;
+       }
+       return 0;
+}
diff --git a/arch/arm/cpu/armv7/stv0991/reset.c b/arch/arm/cpu/armv7/stv0991/reset.c
new file mode 100644 (file)
index 0000000..3384b32
--- /dev/null
@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2014
+ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/stv0991_wdru.h>
+void reset_cpu(ulong ignored)
+{
+       puts("System is going to reboot ...\n");
+       /*
+        * This 1 second delay will allow the above message
+        * to be printed before reset
+        */
+       udelay((1000 * 1000));
+
+       /* Setting bit 1 of the WDRU unit will reset the SoC */
+       writel(WDRU_RST_SYS, &stv0991_wd_ru_ptr->wdru_ctrl1);
+
+       /* system will restart */
+       while (1)
+               ;
+}
diff --git a/arch/arm/cpu/armv7/stv0991/timer.c b/arch/arm/cpu/armv7/stv0991/timer.c
new file mode 100644 (file)
index 0000000..8654b8b
--- /dev/null
@@ -0,0 +1,114 @@
+/*
+ * (C) Copyright 2014
+ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch-stv0991/hardware.h>
+#include <asm/arch-stv0991/stv0991_cgu.h>
+#include <asm/arch-stv0991/stv0991_gpt.h>
+
+static struct stv0991_cgu_regs *const stv0991_cgu_regs = \
+                               (struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
+
+#define READ_TIMER()   (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING)
+#define GPT_RESOLUTION (CONFIG_STV0991_HZ_CLOCK / CONFIG_STV0991_HZ)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd->arch.tbl
+#define lastdec gd->arch.lastinc
+
+int timer_init(void)
+{
+       /* Timer1 clock configuration */
+       writel(TIMER1_CLK_CFG, &stv0991_cgu_regs->tim_freq);
+       writel(readl(&stv0991_cgu_regs->cgu_enable_2) |
+                       TIMER1_CLK_EN, &stv0991_cgu_regs->cgu_enable_2);
+
+       /* Stop the timer */
+       writel(readl(&gpt1_regs_ptr->cr1) & ~GPT_CR1_CEN, &gpt1_regs_ptr->cr1);
+       writel(GPT_PRESCALER_128, &gpt1_regs_ptr->psc);
+       /* Configure timer for auto-reload */
+       writel(readl(&gpt1_regs_ptr->cr1) | GPT_MODE_AUTO_RELOAD,
+                       &gpt1_regs_ptr->cr1);
+
+       /* load value for free running */
+       writel(GPT_FREE_RUNNING, &gpt1_regs_ptr->arr);
+
+       /* start timer */
+       writel(readl(&gpt1_regs_ptr->cr1) | GPT_CR1_CEN,
+                       &gpt1_regs_ptr->cr1);
+
+       /* Reset the timer */
+       lastdec = READ_TIMER();
+       timestamp = 0;
+
+       return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+ulong get_timer(ulong base)
+{
+       return (get_timer_masked() / GPT_RESOLUTION) - base;
+}
+
+void __udelay(unsigned long usec)
+{
+       ulong tmo;
+       ulong start = get_timer_masked();
+       ulong tenudelcnt = CONFIG_STV0991_HZ_CLOCK / (1000 * 100);
+       ulong rndoff;
+
+       rndoff = (usec % 10) ? 1 : 0;
+
+       /* tenudelcnt timer tick gives 10 microsecconds delay */
+       tmo = ((usec / 10) + rndoff) * tenudelcnt;
+
+       while ((ulong) (get_timer_masked() - start) < tmo)
+               ;
+}
+
+ulong get_timer_masked(void)
+{
+       ulong now = READ_TIMER();
+
+       if (now >= lastdec) {
+               /* normal mode */
+               timestamp += now - lastdec;
+       } else {
+               /* we have an overflow ... */
+               timestamp += now + GPT_FREE_RUNNING - lastdec;
+       }
+       lastdec = now;
+
+       return timestamp;
+}
+
+void udelay_masked(unsigned long usec)
+{
+       return udelay(usec);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+       return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+       return CONFIG_STV0991_HZ;
+}
index a26d63e..92aaad9 100644 (file)
@@ -265,20 +265,21 @@ static char *get_reset_cause(void)
 
        cause = readl(&src_regs->srsr);
        writel(cause, &src_regs->srsr);
-       cause &= 0xff;
 
-       switch (cause) {
-       case 0x08:
-               return "WDOG";
-       case 0x20:
+       if (cause & SRC_SRSR_POR_RST)
+               return "POWER ON RESET";
+       else if (cause & SRC_SRSR_WDOG_A5)
+               return "WDOG A5";
+       else if (cause & SRC_SRSR_WDOG_M4)
+               return "WDOG M4";
+       else if (cause & SRC_SRSR_JTAG_RST)
                return "JTAG HIGH-Z";
-       case 0x80:
+       else if (cause & SRC_SRSR_SW_RST)
+               return "SW RESET";
+       else if (cause & SRC_SRSR_RESETB)
                return "EXTERNAL RESET";
-       case 0xfd:
-               return "POR";
-       default:
+       else
                return "unknown reset";
-       }
 }
 
 int print_cpuinfo(void)
index b58df7d..28ccd29 100644 (file)
@@ -206,6 +206,9 @@ void arch_preboot_os(void)
 {
 #if defined(CONFIG_CMD_SATA)
        sata_stop();
+#if defined(CONFIG_MX6)
+       disable_sata_clock();
+#endif
 #endif
 #if defined(CONFIG_VIDEO_IPUV3)
        /* disable video before launching O/S */
index 323805c..226a4cd 100644 (file)
@@ -43,10 +43,10 @@ enum mxc_clock {
 };
 
 enum enet_freq {
-       ENET_25MHz,
-       ENET_50MHz,
-       ENET_100MHz,
-       ENET_125MHz,
+       ENET_25MHZ,
+       ENET_50MHZ,
+       ENET_100MHZ,
+       ENET_125MHZ,
 };
 
 u32 imx_get_uartclk(void);
diff --git a/arch/arm/include/asm/arch-rmobile/mmc.h b/arch/arm/include/asm/arch-rmobile/mmc.h
new file mode 100644 (file)
index 0000000..4e0fef1
--- /dev/null
@@ -0,0 +1,14 @@
+/*
+ * Renesas SuperH MMCIF driver.
+ *
+ * Copyright (C)  2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * Copyright (C)  2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#ifndef _RMOBILE_MMC_H_
+#define _RMOBILE_MMC_H_
+
+int mmcif_mmc_init(void);
+
+#endif /* _RMOBILE_MMC_H_ */
index de14869..132d58c 100644 (file)
 #define CONFIG_SYS_I2C_SH_BASE2        0xE6520000
 #define CONFIG_SYS_I2C_SH_BASE3        0xE60B0000
 
+/* Module stop control/status register bits */
+#define MSTP0_BITS     0x00640801
+#define MSTP1_BITS     0xDB6E9BDF
+#define MSTP2_BITS     0x300DA1FC
+#define MSTP3_BITS     0xF08CF831
+#define MSTP4_BITS     0x80000184
+#define MSTP5_BITS     0x44C00046
+#define MSTP7_BITS     0x07F30718
+#define MSTP8_BITS     0x01F0FF84
+#define MSTP9_BITS     0xF5979FCF
+#define MSTP10_BITS    0xFFFEFFE0
+#define MSTP11_BITS    0x00000000
+
 #define R8A7790_CUT_ES2X       2
 #define IS_R8A7790_ES2()       \
        (rmobile_get_cpu_rev_integer() == R8A7790_CUT_ES2X)
index 26a0bd5..d2cbcd7 100644 (file)
 #define DBSC3_1_QOS_W15_BASE   0xE67A2F00
 #define DBSC3_1_DBADJ2         0xE67A00C8
 
+/* Module stop control/status register bits */
+#define MSTP0_BITS     0x00640801
+#define MSTP1_BITS     0x9B6C9B5A
+#define MSTP2_BITS     0x100D21FC
+#define MSTP3_BITS     0xF08CD810
+#define MSTP4_BITS     0x800001C4
+#define MSTP5_BITS     0x44C00046
+#define MSTP7_BITS     0x05BFE618
+#define MSTP8_BITS     0x40C0FE85
+#define MSTP9_BITS     0xFF979FFF
+#define MSTP10_BITS    0xFFFEFFE0
+#define MSTP11_BITS    0x000001C0
+
 #define R8A7791_CUT_ES2X       2
 #define IS_R8A7791_ES2()       \
        (rmobile_get_cpu_rev_integer() == R8A7791_CUT_ES2X)
index 778812e..1abdeb7 100644 (file)
 /*
  * R8A7793 I/O Product Information
  */
+
+/* Module stop control/status register bits */
+#define MSTP0_BITS     0x00640801
+#define MSTP1_BITS     0x9B6C9B5A
+#define MSTP2_BITS     0x100D21FC
+#define MSTP3_BITS     0xF08CD810
+#define MSTP4_BITS     0x800001C4
+#define MSTP5_BITS     0x44C00046
+#define MSTP7_BITS     0x05BFE618
+#define MSTP8_BITS     0x40C0FE85
+#define MSTP9_BITS     0xFF979FFF
+#define MSTP10_BITS    0xFFFEFFE0
+#define MSTP11_BITS    0x000001C0
+
 #define R8A7793_CUT_ES2X       2
 #define IS_R8A7793_ES2() \
        (rmobile_get_cpu_rev_integer() == R8A7793_CUT_ES2X)
index 66d5a29..d7c9004 100644 (file)
 /* SH-I2C */
 #define CONFIG_SYS_I2C_SH_BASE2        0xE60B0000
 
+/* Module stop control/status register bits */
+#define MSTP0_BITS     0x00440801
+#define MSTP1_BITS     0x936899DA
+#define MSTP2_BITS     0x100D21FC
+#define MSTP3_BITS     0xE084D810
+#define MSTP4_BITS     0x800001C4
+#define MSTP5_BITS     0x40C00044
+#define MSTP7_BITS     0x013FE618
+#define MSTP8_BITS     0x40803C05
+#define MSTP9_BITS     0xFB879FEE
+#define MSTP10_BITS    0xFFFEFFE0
+#define MSTP11_BITS    0x000001C0
+
 #endif /* __ASM_ARCH_R8A7794_H */
index dbbebcf..23c4bba 100644 (file)
 #define SCIF4_BASE             0xE6EE0000
 #define SCIF5_BASE             0xE6EE8000
 
+/* Module stop status register */
+#define MSTPSR0                        0xE6150030
+#define MSTPSR1                        0xE6150038
+#define MSTPSR2                        0xE6150040
+#define MSTPSR3                        0xE6150048
+#define MSTPSR4                        0xE615004C
+#define MSTPSR5                        0xE615003C
+#define MSTPSR7                        0xE61501C4
+#define MSTPSR8                        0xE61509A0
+#define MSTPSR9                        0xE61509A4
+#define MSTPSR10               0xE61509A8
+#define MSTPSR11               0xE61509AC
+
+/* Realtime module stop control register */
+#define RMSTPCR0               0xE6150110
+#define RMSTPCR1               0xE6150114
+#define RMSTPCR2               0xE6150118
+#define RMSTPCR3               0xE615011C
+#define RMSTPCR4               0xE6150120
+#define RMSTPCR5               0xE6150124
+#define RMSTPCR7               0xE615012C
+#define RMSTPCR8               0xE6150980
+#define RMSTPCR9               0xE6150984
+#define RMSTPCR10              0xE6150988
+#define RMSTPCR11              0xE615098C
+
+/* System module stop control register */
+#define SMSTPCR0               0xE6150130
+#define SMSTPCR1               0xE6150134
+#define SMSTPCR2               0xE6150138
+#define SMSTPCR3               0xE615013C
+#define SMSTPCR4               0xE6150140
+#define SMSTPCR5               0xE6150144
+#define SMSTPCR7               0xE615014C
+#define SMSTPCR8               0xE6150990
+#define SMSTPCR9               0xE6150994
+#define SMSTPCR10              0xE6150998
+#define SMSTPCR11              0xE615099C
+
 /*
  * SH-I2C
  * Ch2 and ch3 are different address. These are defined
diff --git a/arch/arm/include/asm/arch-rmobile/rcar-mstp.h b/arch/arm/include/asm/arch-rmobile/rcar-mstp.h
new file mode 100644 (file)
index 0000000..9a564f8
--- /dev/null
@@ -0,0 +1,109 @@
+/*
+ * arch/arm/include/asm/arch-rmobile/rcar-mstp.h
+ *
+ * Copyright (C) 2013, 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * Copyright (C) 2013, 2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#ifndef __ASM_ARCH_RCAR_MSTP_H
+#define __ASM_ARCH_RCAR_MSTP_H
+
+#define mstp_setbits(type, addr, saddr, set) \
+               out_##type((saddr), in_##type(addr) | (set))
+#define mstp_clrbits(type, addr, saddr, clear) \
+               out_##type((saddr), in_##type(addr) & ~(clear))
+#define mstp_setclrbits(type, addr, set, clear) \
+               out_##type((addr), (in_##type(addr) | (set)) & ~(clear))
+#define mstp_setbits_le32(addr, saddr, set) \
+               mstp_setbits(le32, addr, saddr, set)
+#define mstp_clrbits_le32(addr, saddr, clear) \
+               mstp_clrbits(le32, addr, saddr, clear)
+#define mstp_setclrbits_le32(addr, set, clear) \
+               mstp_setclrbits(le32, addr, set, clear)
+
+#ifndef CONFIG_SMSTP0_ENA
+#define CONFIG_SMSTP0_ENA      0x00
+#endif
+#ifndef CONFIG_SMSTP1_ENA
+#define CONFIG_SMSTP1_ENA      0x00
+#endif
+#ifndef CONFIG_SMSTP2_ENA
+#define CONFIG_SMSTP2_ENA      0x00
+#endif
+#ifndef CONFIG_SMSTP3_ENA
+#define CONFIG_SMSTP3_ENA      0x00
+#endif
+#ifndef CONFIG_SMSTP4_ENA
+#define CONFIG_SMSTP4_ENA      0x00
+#endif
+#ifndef CONFIG_SMSTP5_ENA
+#define CONFIG_SMSTP5_ENA      0x00
+#endif
+#ifndef CONFIG_SMSTP6_ENA
+#define CONFIG_SMSTP6_ENA      0x00
+#endif
+#ifndef CONFIG_SMSTP7_ENA
+#define CONFIG_SMSTP7_ENA      0x00
+#endif
+#ifndef CONFIG_SMSTP8_ENA
+#define CONFIG_SMSTP8_ENA      0x00
+#endif
+#ifndef CONFIG_SMSTP9_ENA
+#define CONFIG_SMSTP9_ENA      0x00
+#endif
+#ifndef CONFIG_SMSTP10_ENA
+#define CONFIG_SMSTP10_ENA     0x00
+#endif
+#ifndef CONFIG_SMSTP11_ENA
+#define CONFIG_SMSTP11_ENA     0x00
+#endif
+
+#ifndef CONFIG_RMSTP0_ENA
+#define CONFIG_RMSTP0_ENA      0x00
+#endif
+#ifndef CONFIG_RMSTP1_ENA
+#define CONFIG_RMSTP1_ENA      0x00
+#endif
+#ifndef CONFIG_RMSTP2_ENA
+#define CONFIG_RMSTP2_ENA      0x00
+#endif
+#ifndef CONFIG_RMSTP3_ENA
+#define CONFIG_RMSTP3_ENA      0x00
+#endif
+#ifndef CONFIG_RMSTP4_ENA
+#define CONFIG_RMSTP4_ENA      0x00
+#endif
+#ifndef CONFIG_RMSTP5_ENA
+#define CONFIG_RMSTP5_ENA      0x00
+#endif
+#ifndef CONFIG_RMSTP6_ENA
+#define CONFIG_RMSTP6_ENA      0x00
+#endif
+#ifndef CONFIG_RMSTP7_ENA
+#define CONFIG_RMSTP7_ENA      0x00
+#endif
+#ifndef CONFIG_RMSTP8_ENA
+#define CONFIG_RMSTP8_ENA      0x00
+#endif
+#ifndef CONFIG_RMSTP9_ENA
+#define CONFIG_RMSTP9_ENA      0x00
+#endif
+#ifndef CONFIG_RMSTP10_ENA
+#define CONFIG_RMSTP10_ENA     0x00
+#endif
+#ifndef CONFIG_RMSTP11_ENA
+#define CONFIG_RMSTP11_ENA     0x00
+#endif
+
+struct mstp_ctl {
+       u32 s_addr;
+       u32 s_dis;
+       u32 s_ena;
+       u32 r_addr;
+       u32 r_dis;
+       u32 r_ena;
+};
+
+#endif /* __ASM_ARCH_RCAR_MSTP_H */
diff --git a/arch/arm/include/asm/arch-stv0991/gpio.h b/arch/arm/include/asm/arch-stv0991/gpio.h
new file mode 100644 (file)
index 0000000..9131ded
--- /dev/null
@@ -0,0 +1,22 @@
+/*
+ * (C) Copyright 2014
+ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_STV0991_GPIO_H
+#define __ASM_ARCH_STV0991_GPIO_H
+
+enum gpio_direction {
+       GPIO_DIRECTION_IN,
+       GPIO_DIRECTION_OUT,
+};
+
+struct gpio_regs {
+       u32 data;               /* offset 0x0 */
+       u32 reserved[0xff];     /* 0x4--0x3fc */
+       u32 dir;                /* offset 0x400 */
+};
+
+#endif /* __ASM_ARCH_STV0991_GPIO_H */
diff --git a/arch/arm/include/asm/arch-stv0991/hardware.h b/arch/arm/include/asm/arch-stv0991/hardware.h
new file mode 100644 (file)
index 0000000..3f6bcaf
--- /dev/null
@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2014
+ * Vikas Manocha, STMicroelectronics, <vikas.manocha@st.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_HARDWARE_H
+#define _ASM_ARCH_HARDWARE_H
+
+/* STV0991 */
+#define SRAM0_BASE_ADDR                          0x00000000UL
+#define SRAM1_BASE_ADDR                          0x00068000UL
+#define SRAM2_BASE_ADDR                          0x000D0000UL
+#define SRAM3_BASE_ADDR                          0x00138000UL
+#define CFS_SRAM0_BASE_ADDR                      0x00198000UL
+#define CFS_SRAM1_BASE_ADDR                      0x001B8000UL
+#define FAST_SRAM_BASE_ADDR                      0x001D8000UL
+#define FLASH_BASE_ADDR                          0x40000000UL
+#define PL310_BASE_ADDR                          0x70000000UL
+#define HSAXIM_BASE_ADDR                         0x70100000UL
+#define IMGSS_BASE_ADDR                          0x70200000UL
+#define ADC_BASE_ADDR                            0x80000000UL
+#define GPIOA_BASE_ADDR                          0x80001000UL
+#define GPIOB_BASE_ADDR                          0x80002000UL
+#define GPIOC_BASE_ADDR                          0x80003000UL
+#define HDM_BASE_ADDR                            0x80004000UL
+#define THSENS_BASE_ADDR                         0x80200000UL
+#define GPTIMER2_BASE_ADDR                       0x80201000UL
+#define GPTIMER1_BASE_ADDR                       0x80202000UL
+#define QSPI_BASE_ADDR                           0x80203000UL
+#define CGU_BASE_ADDR                            0x80204000UL
+#define CREG_BASE_ADDR                           0x80205000UL
+#define PEC_BASE_ADDR                            0x80206000UL
+#define WDRU_BASE_ADDR                           0x80207000UL
+#define BSEC_BASE_ADDR                           0x80208000UL
+#define DAP_ROM_BASE_ADDR                        0x80210000UL
+#define SOC_CTI_BASE_ADDR                        0x80211000UL
+#define TPIU_BASE_ADDR                           0x80212000UL
+#define TMC_ETF_BASE_ADDR                        0x80213000UL
+#define R4_ETM_BASE_ADDR                         0x80214000UL
+#define R4_CTI_BASE_ADDR                         0x80215000UL
+#define R4_DBG_BASE_ADDR                         0x80216000UL
+#define GMAC_BASE_ADDR                           0x80300000UL
+#define RNSS_BASE_ADDR                           0x80302000UL
+#define CRYP_BASE_ADDR                           0x80303000UL
+#define HASH_BASE_ADDR                           0x80304000UL
+#define GPDMA_BASE_ADDR                          0x80305000UL
+#define ISA_BASE_ADDR                            0x8032A000UL
+#define HCI_BASE_ADDR                            0x80400000UL
+#define I2C1_BASE_ADDR                           0x80401000UL
+#define I2C2_BASE_ADDR                           0x80402000UL
+#define SAI_BASE_ADDR                            0x80403000UL
+#define USI_BASE_ADDR                            0x80404000UL
+#define SPI1_BASE_ADDR                           0x80405000UL
+#define UART_BASE_ADDR                           0x80406000UL
+#define SPI2_BASE_ADDR                           0x80500000UL
+#define CAN_BASE_ADDR                            0x80501000UL
+#define USART1_BASE_ADDR                         0x80502000UL
+#define USART2_BASE_ADDR                         0x80503000UL
+#define USART3_BASE_ADDR                         0x80504000UL
+#define USART4_BASE_ADDR                         0x80505000UL
+#define USART5_BASE_ADDR                         0x80506000UL
+#define USART6_BASE_ADDR                         0x80507000UL
+#define SDI2_BASE_ADDR                           0x80600000UL
+#define SDI1_BASE_ADDR                           0x80601000UL
+#define VICA_BASE_ADDR                           0x81000000UL
+#define VICB_BASE_ADDR                           0x81001000UL
+#define STM_CHANNELS_BASE_ADDR                   0x81100000UL
+#define STM_BASE_ADDR                            0x81110000UL
+#define SROM_BASE_ADDR                           0xFFFF0000UL
+
+#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h b/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h
new file mode 100644 (file)
index 0000000..ddcbb57
--- /dev/null
@@ -0,0 +1,116 @@
+/*
+ * (C) Copyright 2014
+ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _STV0991_CGU_H
+#define _STV0991_CGU_H
+
+struct stv0991_cgu_regs {
+       u32 cpu_freq;           /* offset 0x0 */
+       u32 icn2_freq;          /* offset 0x4 */
+       u32 dma_freq;           /* offset 0x8 */
+       u32 isp_freq;           /* offset 0xc */
+       u32 h264_freq;          /* offset 0x10 */
+       u32 osif_freq;          /* offset 0x14 */
+       u32 ren_freq;           /* offset 0x18 */
+       u32 tim_freq;           /* offset 0x1c */
+       u32 sai_freq;           /* offset 0x20 */
+       u32 eth_freq;           /* offset 0x24 */
+       u32 i2c_freq;           /* offset 0x28 */
+       u32 spi_freq;           /* offset 0x2c */
+       u32 uart_freq;          /* offset 0x30 */
+       u32 qspi_freq;          /* offset 0x34 */
+       u32 sdio_freq;          /* offset 0x38 */
+       u32 usi_freq;           /* offset 0x3c */
+       u32 can_line_freq;      /* offset 0x40 */
+       u32 debug_freq;         /* offset 0x44 */
+       u32 trace_freq;         /* offset 0x48 */
+       u32 stm_freq;           /* offset 0x4c */
+       u32 eth_ctrl;           /* offset 0x50 */
+       u32 reserved[3];        /* offset 0x54 */
+       u32 osc_ctrl;           /* offset 0x60 */
+       u32 pll1_ctrl;          /* offset 0x64 */
+       u32 pll1_freq;          /* offset 0x68 */
+       u32 pll1_fract;         /* offset 0x6c */
+       u32 pll1_spread;        /* offset 0x70 */
+       u32 pll1_status;        /* offset 0x74 */
+       u32 pll2_ctrl;          /* offset 0x78 */
+       u32 pll2_freq;          /* offset 0x7c */
+       u32 pll2_fract;         /* offset 0x80 */
+       u32 pll2_spread;        /* offset 0x84 */
+       u32 pll2_status;        /* offset 0x88 */
+       u32 cgu_enable_1;       /* offset 0x8c */
+       u32 cgu_enable_2;       /* offset 0x90 */
+       u32 cgu_isp_pulse;      /* offset 0x94 */
+       u32 cgu_h264_pulse;     /* offset 0x98 */
+       u32 cgu_osif_pulse;     /* offset 0x9c */
+       u32 cgu_ren_pulse;      /* offset 0xa0 */
+
+};
+
+/* CGU Timer */
+#define CLK_TMR_OSC                    0
+#define CLK_TMR_MCLK                   1
+#define CLK_TMR_PLL1                   2
+#define CLK_TMR_PLL2                   3
+#define MDIV_SHIFT_TMR                 3
+#define DIV_SHIFT_TMR                  6
+
+#define TIMER1_CLK_CFG                 (0 << DIV_SHIFT_TMR \
+                                       | 0 << MDIV_SHIFT_TMR | CLK_TMR_MCLK)
+
+/* Clock Enable/Disable */
+
+#define TIMER1_CLK_EN                  (1 << 15)
+
+/* CGU Uart config */
+#define CLK_UART_MCLK                  0
+#define CLK_UART_PLL1                  1
+#define CLK_UART_PLL2                  2
+
+#define MDIV_SHIFT_UART                        3
+#define DIV_SHIFT_UART                 6
+
+#define UART_CLK_CFG                   (4 << DIV_SHIFT_UART \
+                                       | 1 << MDIV_SHIFT_UART | CLK_UART_MCLK)
+
+/* CGU Ethernet clock config */
+#define CLK_ETH_MCLK                   0
+#define CLK_ETH_PLL1                   1
+#define CLK_ETH_PLL2                   2
+
+#define MDIV_SHIFT_ETH                 3
+#define DIV_SHIFT_ETH                  6
+#define DIV_ETH_125                    9
+#define DIV_ETH_50                     12
+#define DIV_ETH_P2P                    15
+
+#define ETH_CLK_CFG                    (4 << DIV_ETH_P2P | 4 << DIV_ETH_50 \
+                                       | 1 << DIV_ETH_125 \
+                                       | 0 << DIV_SHIFT_ETH \
+                                       | 3 << MDIV_SHIFT_ETH | CLK_ETH_PLL1)
+ /* CGU Ethernet control */
+
+#define ETH_CLK_TX_EXT_PHY             0
+#define ETH_CLK_TX_125M                        1
+#define ETH_CLK_TX_25M                 2
+#define ETH_CLK_TX_2M5                 3
+#define ETH_CLK_TX_DIS                 7
+
+#define ETH_CLK_RX_EXT_PHY             0
+#define ETH_CLK_RX_25M                 1
+#define ETH_CLK_RX_2M5                 2
+#define ETH_CLK_RX_DIS                 3
+#define RX_CLK_SHIFT                   3
+#define ETH_CLK_MASK                   ~(0x1F)
+
+#define ETH_PHY_MODE_GMII              0
+#define ETH_PHY_MODE_RMII              1
+#define ETH_PHY_CLK_DIS                        1
+
+#define ETH_CLK_CTRL                   (ETH_CLK_RX_EXT_PHY << RX_CLK_SHIFT \
+                                       | ETH_CLK_TX_EXT_PHY)
+#endif
diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_creg.h b/arch/arm/include/asm/arch-stv0991/stv0991_creg.h
new file mode 100644 (file)
index 0000000..c804eb5
--- /dev/null
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2014
+ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _STV0991_CREG_H
+#define _STV0991_CREG_H
+
+struct stv0991_creg {
+       u32 version;            /* offset 0x0 */
+       u32 hdpctl;             /* offset 0x4 */
+       u32 hdpval;             /* offset 0x8 */
+       u32 hdpgposet;          /* offset 0xc */
+       u32 hdpgpoclr;          /* offset 0x10 */
+       u32 hdpgpoval;          /* offset 0x14 */
+       u32 stm_mux;            /* offset 0x18 */
+       u32 sysctrl_1;          /* offset 0x1c */
+       u32 sysctrl_2;          /* offset 0x20 */
+       u32 sysctrl_3;          /* offset 0x24 */
+       u32 sysctrl_4;          /* offset 0x28 */
+       u32 reserved_1[0x35];   /* offset 0x2C-0xFC */
+       u32 mux1;               /* offset 0x100 */
+       u32 mux2;               /* offset 0x104 */
+       u32 mux3;               /* offset 0x108 */
+       u32 mux4;               /* offset 0x10c */
+       u32 mux5;               /* offset 0x110 */
+       u32 mux6;               /* offset 0x114 */
+       u32 mux7;               /* offset 0x118 */
+       u32 mux8;               /* offset 0x11c */
+       u32 mux9;               /* offset 0x120 */
+       u32 mux10;              /* offset 0x124 */
+       u32 mux11;              /* offset 0x128 */
+       u32 mux12;              /* offset 0x12c */
+       u32 mux13;              /* offset 0x130 */
+       u32 reserved_2[0x33];   /* offset 0x134-0x1FC */
+       u32 cfg_pad1;           /* offset 0x200 */
+       u32 cfg_pad2;           /* offset 0x204 */
+       u32 cfg_pad3;           /* offset 0x208 */
+       u32 cfg_pad4;           /* offset 0x20c */
+       u32 cfg_pad5;           /* offset 0x210 */
+       u32 cfg_pad6;           /* offset 0x214 */
+       u32 cfg_pad7;           /* offset 0x218 */
+       u32 reserved_3[0x39];   /* offset 0x21C-0x2FC */
+       u32 vdd_pad1;           /* offset 0x300 */
+       u32 vdd_pad2;           /* offset 0x304 */
+       u32 reserved_4[0x3e];   /* offset 0x308-0x3FC */
+       u32 vdd_comp1;          /* offset 0x400 */
+};
+
+/* CREG MUX 12 register */
+#define GPIOC_30_MUX_SHIFT     24
+#define GPIOC_30_MUX_MASK      ~(1 << GPIOC_30_MUX_SHIFT)
+#define CFG_GPIOC_30_UART_TX   (1 << GPIOC_30_MUX_SHIFT)
+
+#define GPIOC_31_MUX_SHIFT     28
+#define GPIOC_31_MUX_MASK      ~(1 << GPIOC_31_MUX_SHIFT)
+#define CFG_GPIOC_31_UART_RX   (1 << GPIOC_31_MUX_SHIFT)
+
+/* CREG MUX 7 register */
+#define GPIOB_16_MUX_SHIFT     0
+#define GPIOB_16_MUX_MASK      ~(1 << GPIOB_16_MUX_SHIFT)
+#define CFG_GPIOB_16_UART_TX   (1 << GPIOB_16_MUX_SHIFT)
+
+#define GPIOB_17_MUX_SHIFT     4
+#define GPIOB_17_MUX_MASK      ~(1 << GPIOB_17_MUX_SHIFT)
+#define CFG_GPIOB_17_UART_RX   (1 << GPIOB_17_MUX_SHIFT)
+
+/* CREG CFG_PAD6 register */
+
+#define GPIOC_31_MODE_SHIFT    30
+#define GPIOC_31_MODE_MASK     ~(1 << GPIOC_31_MODE_SHIFT)
+#define CFG_GPIOC_31_MODE_OD   (0 << GPIOC_31_MODE_SHIFT)
+#define CFG_GPIOC_31_MODE_PP   (1 << GPIOC_31_MODE_SHIFT)
+
+#define GPIOC_30_MODE_SHIFT    28
+#define GPIOC_30_MODE_MASK     ~(1 << GPIOC_30_MODE_SHIFT)
+#define CFG_GPIOC_30_MODE_LOW  (0 << GPIOC_30_MODE_SHIFT)
+#define CFG_GPIOC_30_MODE_HIGH (1 << GPIOC_30_MODE_SHIFT)
+
+/* CREG Ethernet pad config */
+
+#define VDD_ETH_PS_1V8         0
+#define VDD_ETH_PS_2V5         2
+#define VDD_ETH_PS_3V3         3
+#define VDD_ETH_PS_MASK                0x3
+
+#define VDD_ETH_PS_SHIFT       12
+#define ETH_VDD_CFG            (VDD_ETH_PS_1V8 << VDD_ETH_PS_SHIFT)
+
+#define VDD_ETH_M_PS_SHIFT     28
+#define ETH_M_VDD_CFG          (VDD_ETH_PS_1V8 << VDD_ETH_M_PS_SHIFT)
+
+#endif
diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_defs.h b/arch/arm/include/asm/arch-stv0991/stv0991_defs.h
new file mode 100644 (file)
index 0000000..1151378
--- /dev/null
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2014
+ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __STV0991_DEFS_H__
+#define __STV0991_DEFS_H__
+#include <asm/arch/stv0991_periph.h>
+
+extern int stv0991_pinmux_config(enum periph_id);
+extern int clock_setup(enum periph_clock);
+
+#endif
+
diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h
new file mode 100644 (file)
index 0000000..abd7257
--- /dev/null
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2014
+ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _STV0991_GPT_H
+#define _STV0991_GPT_H
+
+#include <asm/arch-stv0991/hardware.h>
+
+struct gpt_regs {
+       u32 cr1;
+       u32 cr2;
+       u32 reserved_1;
+       u32 dier;       /* dma_int_en */
+       u32 sr;         /* status reg */
+       u32 egr;        /* event gen */
+       u32 reserved_2[3];      /* offset 0x18--0x20*/
+       u32 cnt;
+       u32 psc;
+       u32 arr;
+};
+
+struct gpt_regs *const gpt1_regs_ptr =
+       (struct gpt_regs *) GPTIMER1_BASE_ADDR;
+
+/* Timer control1 register  */
+#define GPT_CR1_CEN                    0x0001
+#define GPT_MODE_AUTO_RELOAD           (1 << 7)
+
+/* Timer prescalar reg */
+#define GPT_PRESCALER_128              0x128
+
+/* Auto reload register for free running config */
+#define GPT_FREE_RUNNING               0xFFFF
+
+/* Timer, HZ specific defines */
+#define CONFIG_STV0991_HZ              1000
+#define CONFIG_STV0991_HZ_CLOCK                (27*1000*1000)/GPT_PRESCALER_128
+
+#endif
diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_periph.h b/arch/arm/include/asm/arch-stv0991/stv0991_periph.h
new file mode 100644 (file)
index 0000000..f728c83
--- /dev/null
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2014
+ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_PERIPH_H
+#define __ASM_ARM_ARCH_PERIPH_H
+
+/*
+ * Peripherals required for pinmux configuration. List will
+ * grow with support for more devices getting added.
+ * Numbering based on interrupt table.
+ *
+ */
+enum periph_id {
+       UART_GPIOC_30_31 = 0,
+       UART_GPIOB_16_17,
+       ETH_GPIOB_10_31_C_0_4,
+       PERIPH_ID_I2C0,
+       PERIPH_ID_I2C1,
+       PERIPH_ID_I2C2,
+       PERIPH_ID_I2C3,
+       PERIPH_ID_I2C4,
+       PERIPH_ID_I2C5,
+       PERIPH_ID_I2C6,
+       PERIPH_ID_I2C7,
+       PERIPH_ID_SPI0,
+       PERIPH_ID_SPI1,
+       PERIPH_ID_SPI2,
+       PERIPH_ID_SDMMC0,
+       PERIPH_ID_SDMMC1,
+       PERIPH_ID_SDMMC2,
+       PERIPH_ID_SDMMC3,
+       PERIPH_ID_I2S1,
+};
+
+enum periph_clock {
+       UART_CLOCK_CFG = 0,
+       ETH_CLOCK_CFG,
+};
+
+#endif /* __ASM_ARM_ARCH_PERIPH_H */
diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h b/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h
new file mode 100644 (file)
index 0000000..7e555a2
--- /dev/null
@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 2014
+ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _STV0991_WD_RST_H
+#define _STV0991_WD_RST_H
+#include <asm/arch-stv0991/hardware.h>
+
+struct stv0991_wd_ru {
+       u32 wdru_config;
+       u32 wdru_ctrl1;
+       u32 wdru_ctrl2;
+       u32 wdru_tim;
+       u32 wdru_count;
+       u32 wdru_stat;
+       u32 wdru_wrlock;
+};
+
+struct stv0991_wd_ru *const stv0991_wd_ru_ptr = \
+               (struct stv0991_wd_ru *)WDRU_BASE_ADDR;
+
+/* Watchdog control register */
+#define WDRU_RST_SYS           0x1
+
+#endif
index 9d797db..6b10bdf 100644 (file)
 #define DDRMC_CR161_TODTH_RD(v)                                (((v) & 0xf) << 8)
 #define DDRMC_CR161_TODTH_WR(v)                                ((v) & 0xf)
 
+/* System Reset Controller (SRC) */
+#define SRC_SRSR_SW_RST                                        (0x1 << 18)
+#define SRC_SRSR_RESETB                                        (0x1 << 7)
+#define SRC_SRSR_JTAG_RST                              (0x1 << 5)
+#define SRC_SRSR_WDOG_M4                               (0x1 << 4)
+#define SRC_SRSR_WDOG_A5                               (0x1 << 3)
+#define SRC_SRSR_POR_RST                               (0x1 << 0)
+
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 #include <asm/types.h>
 
index 06922c0..67ac260 100644 (file)
@@ -301,7 +301,7 @@ int board_eth_init(bd_t *bis)
        /* clear gpr1[14], gpr1[18:17] to select anatop clock */
        clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
 
-       ret = enable_fec_anatop_clock(ENET_50MHz);
+       ret = enable_fec_anatop_clock(ENET_50MHZ);
        if (ret)
                return ret;
 
index 8111edf..cac6d73 100644 (file)
@@ -234,7 +234,7 @@ static int setup_fec(void)
        /* clear gpr1[14], gpr1[18:17] to select anatop clock */
        clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
 
-       return enable_fec_anatop_clock(ENET_50MHz);
+       return enable_fec_anatop_clock(ENET_50MHZ);
 }
 #endif
 
index 7aee074..8b959b9 100644 (file)
@@ -168,7 +168,7 @@ static int setup_fec(void)
        reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
        writel(reg, &anatop->pll_enet);
 
-       return enable_fec_anatop_clock(ENET_125MHz);
+       return enable_fec_anatop_clock(ENET_125MHZ);
 }
 
 int board_eth_init(bd_t *bis)
index 9ed12bd..6904e39 100644 (file)
@@ -6,4 +6,4 @@
 # SPDX-License-Identifier: GPL-2.0
 #
 
-obj-y  := alt.o qos.o
+obj-y  := alt.o qos.o ../rcar-gen2-common/common.o
index 523c5f1..8cc17e9 100644 (file)
@@ -15,6 +15,8 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
 #include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/mmc.h>
 #include <netdev.h>
 #include <miiphy.h>
 #include <i2c.h>
@@ -37,30 +39,11 @@ void s_init(void)
        qos_init();
 }
 
-#define MSTPSR1                0xE6150038
-#define SMSTPCR1       0xE6150134
 #define TMU0_MSTP125   (1 << 25)
-
-#define MSTPSR7                0xE61501C4
-#define SMSTPCR7       0xE615014C
 #define SCIF2_MSTP719  (1 << 19)
-
-#define MSTPSR8                0xE61509A0
-#define SMSTPCR8       0xE6150990
 #define ETHER_MSTP813  (1 << 13)
-
-#define MSTPSR3                0xE6150048
-#define SMSTPCR3       0xE615013C
 #define IIC1_MSTP323   (1 << 23)
-
-#define mstp_setbits(type, addr, saddr, set) \
-       out_##type((saddr), in_##type(addr) | (set))
-#define mstp_clrbits(type, addr, saddr, clear) \
-       out_##type((saddr), in_##type(addr) & ~(clear))
-#define mstp_setbits_le32(addr, saddr, set) \
-       mstp_setbits(le32, addr, saddr, set)
-#define mstp_clrbits_le32(addr, saddr, clear)   \
-       mstp_clrbits(le32, addr, saddr, clear)
+#define MMC0_MSTP315   (1 << 15)
 
 int board_early_init_f(void)
 {
@@ -76,15 +59,13 @@ int board_early_init_f(void)
        /* IIC1 / sh-i2c ch1 */
        mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323);
 
+#ifdef CONFIG_SH_MMCIF
+       /* MMC */
+       mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315);
+#endif
        return 0;
 }
 
-void arch_preboot_os(void)
-{
-       /* Disable TMU0 */
-       mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
-}
-
 int board_init(void)
 {
        /* adress of boot parameters */
@@ -145,6 +126,19 @@ int board_eth_init(bd_t *bis)
 #endif
 }
 
+int board_mmc_init(bd_t *bis)
+{
+       int ret = 0;
+
+#ifdef CONFIG_SH_MMCIF
+       gpio_request(GPIO_GP_4_31, NULL);
+       gpio_set_value(GPIO_GP_4_31, 1);
+
+       ret = mmcif_mmc_init();
+#endif
+       return ret;
+}
+
 int dram_init(void)
 {
        gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
index a4fb6cc..2dac748 100644 (file)
@@ -6,4 +6,4 @@
 # SPDX-License-Identifier: GPL-2.0
 #
 
-obj-y  := gose.o qos.o
+obj-y  := gose.o qos.o ../rcar-gen2-common/common.o
index 715fba0..677b976 100644 (file)
@@ -15,6 +15,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
 #include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
 #include <netdev.h>
 #include <miiphy.h>
 #include <i2c.h>
@@ -41,27 +42,10 @@ void s_init(void)
        qos_init();
 }
 
-#define MSTPSR1                0xE6150038
-#define SMSTPCR1       0xE6150134
 #define TMU0_MSTP125   (1 << 25)
-
-#define MSTPSR7                0xE61501C4
-#define SMSTPCR7       0xE615014C
 #define SCIF0_MSTP721  (1 << 21)
-
-#define MSTPSR8                0xE61509A0
-#define SMSTPCR8       0xE6150990
 #define ETHER_MSTP813  (1 << 13)
 
-#define mstp_setbits(type, addr, saddr, set) \
-       out_##type((saddr), in_##type(addr) | (set))
-#define mstp_clrbits(type, addr, saddr, clear) \
-       out_##type((saddr), in_##type(addr) & ~(clear))
-#define mstp_setbits_le32(addr, saddr, set) \
-       mstp_setbits(le32, addr, saddr, set)
-#define mstp_clrbits_le32(addr, saddr, clear) \
-       mstp_clrbits(le32, addr, saddr, clear)
-
 int board_early_init_f(void)
 {
        /* TMU0 */
@@ -76,16 +60,6 @@ int board_early_init_f(void)
        return 0;
 }
 
-#define TSTR0          0x04
-#define TSTR0_STR0     0x01
-void arch_preboot_os(void)
-{
-       /* stop TMU0 */
-       mstp_clrbits_le32(TMU_BASE + TSTR0, TMU_BASE + TSTR0, TSTR0_STR0);
-       /* Disable TMU0 */
-       mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
-}
-
 #define PUPR5          0xE6060114
 #define PUPR5_ETH      0x3FFC0000
 #define PUPR5_ETH_MAGIC        (1 << 27)
index b4d0183..c10bba5 100644 (file)
@@ -6,4 +6,4 @@
 # SPDX-License-Identifier: GPL-2.0
 #
 
-obj-y  := koelsch.o qos.o
+obj-y  := koelsch.o qos.o ../rcar-gen2-common/common.o
index 244bc58..10fa571 100644 (file)
@@ -16,6 +16,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
 #include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
 #include <netdev.h>
 #include <miiphy.h>
 #include <i2c.h>
@@ -43,27 +44,10 @@ void s_init(void)
        qos_init();
 }
 
-#define MSTPSR1                0xE6150038
-#define SMSTPCR1       0xE6150134
 #define TMU0_MSTP125   (1 << 25)
-
-#define MSTPSR7                0xE61501C4
-#define SMSTPCR7       0xE615014C
 #define SCIF0_MSTP721  (1 << 21)
-
-#define MSTPSR8                0xE61509A0
-#define SMSTPCR8       0xE6150990
 #define ETHER_MSTP813  (1 << 13)
 
-#define mstp_setbits(type, addr, saddr, set) \
-       out_##type((saddr), in_##type(addr) | (set))
-#define mstp_clrbits(type, addr, saddr, clear) \
-       out_##type((saddr), in_##type(addr) & ~(clear))
-#define mstp_setbits_le32(addr, saddr, set) \
-       mstp_setbits(le32, addr, saddr, set)
-#define mstp_clrbits_le32(addr, saddr, clear)   \
-       mstp_clrbits(le32, addr, saddr, clear)
-
 int board_early_init_f(void)
 {
        mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
@@ -77,12 +61,6 @@ int board_early_init_f(void)
        return 0;
 }
 
-void arch_preboot_os(void)
-{
-       /* Disable TMU0 */
-       mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
-}
-
 /* LSI pin pull-up control */
 #define PUPR5 0xe6060114
 #define PUPR5_ETH 0x3FFC0000
index 034c6f8..8d03461 100644 (file)
@@ -6,4 +6,4 @@
 # SPDX-License-Identifier: GPL-2.0
 #
 
-obj-y  := lager.o qos.o
+obj-y  := lager.o qos.o ../rcar-gen2-common/common.o
index 93273b2..d1e29d2 100644 (file)
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
 #include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/mmc.h>
 #include <miiphy.h>
 #include <i2c.h>
+#include <mmc.h>
 #include "qos.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -50,26 +53,10 @@ void s_init(void)
        qos_init();
 }
 
-#define MSTPSR1        0xE6150038
-#define SMSTPCR1       0xE6150134
 #define TMU0_MSTP125   (1 << 25)
-
-#define MSTPSR7        0xE61501C4
-#define SMSTPCR7       0xE615014C
 #define SCIF0_MSTP721  (1 << 21)
-
-#define MSTPSR8        0xE61509A0
-#define SMSTPCR8       0xE6150990
 #define ETHER_MSTP813  (1 << 13)
-
-#define mstp_setbits(type, addr, saddr, set) \
-       out_##type((saddr), in_##type(addr) | (set))
-#define mstp_clrbits(type, addr, saddr, clear) \
-       out_##type((saddr), in_##type(addr) & ~(clear))
-#define mstp_setbits_le32(addr, saddr, set)    \
-               mstp_setbits(le32, addr, saddr, set)
-#define mstp_clrbits_le32(addr, saddr, clear)  \
-               mstp_clrbits(le32, addr, saddr, clear)
+#define MMC1_MSTP305    (1 << 5)
 
 int board_early_init_f(void)
 {
@@ -79,16 +66,12 @@ int board_early_init_f(void)
        mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
        /* ETHER */
        mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
+       /* eMMC */
+       mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC1_MSTP305);
 
        return 0;
 }
 
-void arch_preboot_os(void)
-{
-       /* Disable TMU0 */
-       mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
-}
-
 DECLARE_GLOBAL_DATA_PTR;
 int board_init(void)
 {
@@ -163,6 +146,28 @@ int board_phy_config(struct phy_device *phydev)
        return 0;
 }
 
+int board_mmc_init(bd_t *bis)
+{
+       int ret = 0;
+
+#ifdef CONFIG_SH_MMCIF
+       gpio_request(GPIO_FN_MMC1_D0, NULL);
+       gpio_request(GPIO_FN_MMC1_D1, NULL);
+       gpio_request(GPIO_FN_MMC1_D2, NULL);
+       gpio_request(GPIO_FN_MMC1_D3, NULL);
+       gpio_request(GPIO_FN_MMC1_D4, NULL);
+       gpio_request(GPIO_FN_MMC1_D5, NULL);
+       gpio_request(GPIO_FN_MMC1_D6, NULL);
+       gpio_request(GPIO_FN_MMC1_D7, NULL);
+       gpio_request(GPIO_FN_MMC1_CLK, NULL);
+       gpio_request(GPIO_FN_MMC1_CMD, NULL);
+
+       ret = mmcif_mmc_init();
+#endif
+       return ret;
+}
+
+
 int dram_init(void)
 {
        gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
diff --git a/board/renesas/rcar-gen2-common/common.c b/board/renesas/rcar-gen2-common/common.c
new file mode 100644 (file)
index 0000000..0103f42
--- /dev/null
@@ -0,0 +1,59 @@
+/*
+ * board/renesas/rcar-gen2-common/common.c
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+
+#define TSTR0          0x04
+#define TSTR0_STR0     0x01
+
+static struct mstp_ctl mstptbl[] = {
+       { SMSTPCR0, MSTP0_BITS, CONFIG_SMSTP0_ENA,
+               RMSTPCR0, MSTP0_BITS, CONFIG_RMSTP0_ENA },
+       { SMSTPCR1, MSTP1_BITS, CONFIG_SMSTP1_ENA,
+               RMSTPCR1, MSTP1_BITS, CONFIG_RMSTP1_ENA },
+       { SMSTPCR2, MSTP2_BITS, CONFIG_SMSTP2_ENA,
+               RMSTPCR2, MSTP2_BITS, CONFIG_RMSTP2_ENA },
+       { SMSTPCR3, MSTP3_BITS, CONFIG_SMSTP3_ENA,
+               RMSTPCR3, MSTP3_BITS, CONFIG_RMSTP3_ENA },
+       { SMSTPCR4, MSTP4_BITS, CONFIG_SMSTP4_ENA,
+               RMSTPCR4, MSTP4_BITS, CONFIG_RMSTP4_ENA },
+       { SMSTPCR5, MSTP5_BITS, CONFIG_SMSTP5_ENA,
+               RMSTPCR5, MSTP5_BITS, CONFIG_RMSTP5_ENA },
+       /* No MSTP6 */
+       { SMSTPCR7, MSTP7_BITS, CONFIG_SMSTP7_ENA,
+               RMSTPCR7, MSTP7_BITS, CONFIG_RMSTP7_ENA },
+       { SMSTPCR8, MSTP8_BITS, CONFIG_SMSTP8_ENA,
+               RMSTPCR8, MSTP8_BITS, CONFIG_RMSTP8_ENA },
+       { SMSTPCR9, MSTP9_BITS, CONFIG_SMSTP9_ENA,
+               RMSTPCR9, MSTP9_BITS, CONFIG_RMSTP9_ENA },
+       { SMSTPCR10, MSTP10_BITS, CONFIG_SMSTP10_ENA,
+                RMSTPCR10, MSTP10_BITS, CONFIG_RMSTP10_ENA },
+       { SMSTPCR11, MSTP11_BITS, CONFIG_SMSTP1_ENA,
+                RMSTPCR11, MSTP11_BITS, CONFIG_RMSTP11_ENA },
+};
+
+void arch_preboot_os(void)
+{
+       int i;
+
+       /* stop TMU0 */
+       mstp_clrbits_le32(TMU_BASE + TSTR0, TMU_BASE + TSTR0, TSTR0_STR0);
+
+       /* Stop module clock */
+       for (i = 0; i < ARRAY_SIZE(mstptbl); i++) {
+               mstp_setclrbits_le32(mstptbl[i].s_addr, mstptbl[i].s_dis,
+                                    mstptbl[i].s_ena);
+               mstp_setclrbits_le32(mstptbl[i].r_addr, mstptbl[i].r_dis,
+                                    mstptbl[i].r_ena);
+       }
+}
index 6d204b3..52c384b 100644 (file)
@@ -146,7 +146,7 @@ int board_eth_init(bd_t *bis)
 {
        struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 
-       int ret = enable_fec_anatop_clock(ENET_25MHz);
+       int ret = enable_fec_anatop_clock(ENET_25MHZ);
        if (ret)
                return ret;
 
diff --git a/board/st/stv0991/Kconfig b/board/st/stv0991/Kconfig
new file mode 100644 (file)
index 0000000..8bda349
--- /dev/null
@@ -0,0 +1,23 @@
+if TARGET_STV0991
+
+config SYS_CPU
+       string
+       default "armv7"
+
+config SYS_BOARD
+       string
+       default "stv0991"
+
+config SYS_VENDOR
+       string
+       default "st"
+
+config SYS_SOC
+       string
+       default "stv0991"
+
+config SYS_CONFIG_NAME
+       string
+       default "stv0991"
+
+endif
diff --git a/board/st/stv0991/MAINTAINERS b/board/st/stv0991/MAINTAINERS
new file mode 100644 (file)
index 0000000..87221e9
--- /dev/null
@@ -0,0 +1,5 @@
+STV0991 APPLICATION BOARD
+M:     Vikas Manocha <vikas.manocha@st.com>
+S:     Maintained
+F:     board/st/stv0991/
+F:     include/configs/stv0991.h
diff --git a/board/st/stv0991/Makefile b/board/st/stv0991/Makefile
new file mode 100644 (file)
index 0000000..fb5169a
--- /dev/null
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2014
+# Vikas Manocha, ST Microelectronics, vikas.manocha@stcom
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y  := stv0991.o
diff --git a/board/st/stv0991/stv0991.c b/board/st/stv0991/stv0991.c
new file mode 100644 (file)
index 0000000..f465699
--- /dev/null
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2014
+ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/stv0991_periph.h>
+#include <asm/arch/stv0991_defs.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/gpio.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <dm/platdata.h>
+#include <dm/platform_data/serial_pl01x.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct gpio_regs *const gpioa_regs =
+               (struct gpio_regs *) GPIOA_BASE_ADDR;
+
+static const struct pl01x_serial_platdata serial_platdata = {
+       .base = 0x80406000,
+       .type = TYPE_PL011,
+       .clock = 2700 * 1000,
+};
+
+U_BOOT_DEVICE(stv09911_serials) = {
+       .name = "serial_pl01x",
+       .platdata = &serial_platdata,
+};
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+void show_boot_progress(int progress)
+{
+       printf("%i\n", progress);
+}
+#endif
+
+void enable_eth_phy(void)
+{
+       /* Set GPIOA_06 pad HIGH (Appli board)*/
+       writel(readl(&gpioa_regs->dir) | 0x40, &gpioa_regs->dir);
+       writel(readl(&gpioa_regs->data) | 0x40, &gpioa_regs->data);
+}
+int board_eth_enable(void)
+{
+       stv0991_pinmux_config(ETH_GPIOB_10_31_C_0_4);
+       clock_setup(ETH_CLOCK_CFG);
+       enable_eth_phy();
+       return 0;
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+       board_eth_enable();
+       return 0;
+}
+
+int board_uart_init(void)
+{
+       stv0991_pinmux_config(UART_GPIOC_30_31);
+       clock_setup(UART_CLOCK_CFG);
+       return 0;
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+       board_uart_init();
+       return 0;
+}
+#endif
+
+int dram_init(void)
+{
+       gd->ram_size = PHYS_SDRAM_1_SIZE;
+       return 0;
+}
+
+void dram_init_banksize(void)
+{
+       gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+       gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+       int ret = 0;
+
+#if defined(CONFIG_DESIGNWARE_ETH)
+       u32 interface = PHY_INTERFACE_MODE_MII;
+       if (designware_initialize(GMAC_BASE_ADDR, interface) >= 0)
+               ret++;
+#endif
+       return ret;
+}
+#endif
index c514e24..84b243e 100644 (file)
@@ -1,23 +1,15 @@
 if TARGET_TBS2910
 
-config SYS_CPU
-       string
-       default "armv7"
-
 config SYS_BOARD
-       string
        default "tbs2910"
 
 config SYS_VENDOR
-       string
        default "tbs"
 
 config SYS_SOC
-       string
        default "mx6"
 
 config SYS_CONFIG_NAME
-       string
        default "tbs2910"
 
 endif
diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig
new file mode 100644 (file)
index 0000000..a05e991
--- /dev/null
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS="stv0991"
+CONFIG_ARM=y
+CONFIG_TARGET_STV0991=y
index 9a2b547..01a4148 100644 (file)
@@ -594,22 +594,24 @@ int init_sata(int dev)
 
 int reset_sata(int dev)
 {
-       struct ahci_probe_ent *probe_ent =
-                       (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
-       struct sata_host_regs *host_mmio =
-                       (struct sata_host_regs *)probe_ent->mmio_base;
+       struct ahci_probe_ent *probe_ent;
+       struct sata_host_regs *host_mmio;
 
        if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
                printf("The sata index %d is out of ranges\n\r", dev);
                return -1;
        }
 
+       probe_ent = (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
+       if (NULL == probe_ent)
+               /* not initialized, so nothing to reset */
+               return 0;
+
+       host_mmio = (struct sata_host_regs *)probe_ent->mmio_base;
        setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR);
        while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR)
                udelay(100);
 
-       disable_sata_clock();
-
        return 0;
 }
 
index 89737af..d92044e 100644 (file)
@@ -81,8 +81,6 @@ static int finish_access(struct ocotp_regs *regs, const char *caller)
        err = !!(readl(&regs->ctrl) & BM_CTRL_ERROR);
        clear_error(regs);
 
-       enable_ocotp_clk(0);
-
        if (err) {
                printf("mxc_ocotp %s(): Access protect error\n", caller);
                return -EIO;
index 545d3eb..6f0a1d3 100644 (file)
@@ -187,6 +187,8 @@ static int mxs_ocotp_write_fuse(uint32_t addr, uint32_t mask)
        uint32_t hclk_val, vddio_val;
        int ret;
 
+       mxs_ocotp_clear_error();
+
        /* Make sure the banks are closed for reading. */
        ret = mxs_ocotp_read_bank_open(0);
        if (ret) {
@@ -221,13 +223,17 @@ static int mxs_ocotp_write_fuse(uint32_t addr, uint32_t mask)
                goto fail;
        }
 
+       /* Check for errors */
+       if (readl(&ocotp_regs->hw_ocotp_ctrl) & OCOTP_CTRL_ERROR) {
+               puts("Failed writing fuses!\n");
+               ret = -EPERM;
+               goto fail;
+       }
+
 fail:
        mxs_ocotp_scale_vddio(0, &vddio_val);
-       ret = mxs_ocotp_scale_hclk(0, &hclk_val);
-       if (ret) {
+       if (mxs_ocotp_scale_hclk(0, &hclk_val))
                puts("Failed scaling up the HCLK!\n");
-               return ret;
-       }
 
        return ret;
 }
index 1161585..0bd9cfd 100644 (file)
@@ -156,8 +156,6 @@ static int imx_thermal_probe(struct udevice *dev)
        if (fuse == 0 || fuse == ~0) {
                printf("CPU:   Thermal invalid data, fuse: 0x%x\n", fuse);
                return -EPERM;
-       } else {
-               printf("CPU:   Thermal calibration data: 0x%x\n", fuse);
        }
 
        *priv = fuse;
index 7d8daa2..508db56 100644 (file)
 #define CONFIG_SYS_PROMPT      "=> "
 #endif
 
+#ifndef CONFIG_SYS_PBSIZE
+#define CONFIG_SYS_PBSIZE      (CONFIG_SYS_CBSIZE + 128)
+#endif
+
 #ifndef CONFIG_FIT_SIGNATURE
 #define CONFIG_IMAGE_FORMAT_LEGACY
 #endif
index 5c8223c..58eac31 100644 (file)
 #define CONFIG_USB_EHCI_RMOBILE
 #define CONFIG_USB_MAX_CONTROLLER_COUNT        2
 
+/* MMCIF */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_MMC
+
+#define CONFIG_SH_MMCIF
+#define CONFIG_SH_MMCIF_ADDR           0xee200000
+#define CONFIG_SH_MMCIF_CLK            48000000
+
+/* Module stop status bits */
+/* INTC-RT */
+#define CONFIG_SMSTP0_ENA      0x00400000
+/* MSIF */
+#define CONFIG_SMSTP2_ENA      0x00002000
+/* INTC-SYS, IRQC */
+#define CONFIG_SMSTP4_ENA      0x00000180
+/* SCIF2 */
+#define CONFIG_SMSTP7_ENA      0x00080000
+
 #endif /* __ALT_H */
index c347e45..44c8a30 100644 (file)
 #define CONFIG_USB_EHCI_RMOBILE
 #define CONFIG_USB_MAX_CONTROLLER_COUNT        2
 
+/* Module stop status bits */
+/* INTC-RT */
+#define CONFIG_SMSTP0_ENA      0x00400000
+/* MSIF */
+#define CONFIG_SMSTP2_ENA      0x00002000
+/* INTC-SYS, IRQC */
+#define CONFIG_SMSTP4_ENA      0x00000180
+/* SCIF0 */
+#define CONFIG_SMSTP7_ENA      0x00200000
+
 #endif /* __GOSE_H */
index bb98302..c14889c 100644 (file)
 #define CONFIG_USB_MAX_CONTROLLER_COUNT        2
 #define CONFIG_USB_STORAGE
 
+
+/* Module stop status bits */
+/* INTC-RT */
+#define CONFIG_SMSTP0_ENA      0x00400000
+/* MSIF*/
+#define CONFIG_SMSTP2_ENA      0x00002000
+/* INTC-SYS, IRQC */
+#define CONFIG_SMSTP4_ENA      0x00000180
+/* SCIF0 */
+#define CONFIG_SMSTP7_ENA      0x00200000
+
 #endif /* __KOELSCH_H */
index 37be38f..291267f 100644 (file)
 #define CONFIG_USB_MAX_CONTROLLER_COUNT        3
 #define CONFIG_USB_STORAGE
 
+/* MMC */
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+
+#define CONFIG_SH_MMCIF
+#define CONFIG_SH_MMCIF_ADDR           0xEE220000
+#define CONFIG_SH_MMCIF_CLK            97500000
+
+/* Module stop status bits */
+/* INTC-RT */
+#define CONFIG_SMSTP0_ENA      0x00400000
+/* MSIF */
+#define CONFIG_SMSTP2_ENA      0x00002000
+/* INTC-SYS, IRQC */
+#define CONFIG_SMSTP4_ENA      0x00000180
+/* SCIF0 */
+#define CONFIG_SMSTP7_ENA      0x00200000
+
 #endif /* __LAGER_H */
index 10fb1f4..42bc3c8 100644 (file)
@@ -94,6 +94,7 @@
 /* Command definition */
 #include <config_cmd_default.h>
 #define CONFIG_CMD_BOOTZ
+#define CONFIG_SUPPORT_RAW_INITRD
 
 #undef CONFIG_CMD_IMLS
 
index 9fdd841..f0f721e 100644 (file)
 #define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_CBSIZE              256
-
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 #define CONFIG_SYS_MAXARGS             16
 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
 
index d8ab291..5e0edab 100644 (file)
 #define CONFIG_PCIE_IMX_POWER_GPIO     IMX_GPIO_NR(2, 1)
 #endif
 
+#define CONFIG_DM
+#define CONFIG_DM_THERMAL
+#define CONFIG_SYS_MALLOC_F_LEN        (1 << 10)
+#define CONFIG_IMX6_THERMAL
+
+#define CONFIG_CMD_FUSE
+#if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX6_THERMAL)
+#define CONFIG_MXC_OCOTP
+#endif
+
 /* FLASH and environment organization */
 #define CONFIG_SYS_NO_FLASH
 
index 46c7526..c33f1cb 100644 (file)
@@ -28,6 +28,9 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_SF
 #define CONFIG_CMD_SPI
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
 
 #define CONFIG_SYS_THUMB_BUILD
 #define CONFIG_SYS_GENERIC_BOARD
@@ -36,6 +39,7 @@
 #define CONFIG_FAT_WRITE
 #define CONFIG_DOS_PARTITION
 #define CONFIG_SUPPORT_VFAT
+#define CONFIG_FS_EXT4
 #define CONFIG_EXT4_WRITE
 
 #define CONFIG_CMDLINE_TAG
diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h
new file mode 100644 (file)
index 0000000..fd9bd63
--- /dev/null
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2014
+ * Vikas Manocha, STMicroelectronics, <vikas.manocha@st.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __CONFIG_STV0991_H
+#define __CONFIG_STV0991_H
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_SYS_CORTEX_R4
+
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_SYS_NO_FLASH
+
+/* ram memory-related information */
+#define CONFIG_NR_DRAM_BANKS                   1
+#define PHYS_SDRAM_1                           0x00000000
+#define CONFIG_SYS_SDRAM_BASE                  PHYS_SDRAM_1
+#define PHYS_SDRAM_1_SIZE                      0x00198000
+
+#define CONFIG_ENV_SIZE                                0x10000
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR                                \
+       (PHYS_SDRAM_1_SIZE - CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MAXARGS                     16
+#define CONFIG_SYS_MALLOC_LEN                  (CONFIG_ENV_SIZE + 16 * 1024)
+#define CONFIG_SYS_MALLOC_F_LEN                        0x2000
+
+#define CONFIG_DM
+/* serial port (PL011) configuration */
+#define CONFIG_BAUDRATE                                115200
+#ifdef CONFIG_DM
+#define CONFIG_DM_SERIAL
+#define CONFIG_PL01X_SERIAL
+#else
+#define CONFIG_SYS_SERIAL0                     0x80406000
+#define CONFIG_CONS_INDEX                      0
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL01x_PORTS                     {(void *)CONFIG_SYS_SERIAL0}
+#define CONFIG_PL011_CLOCK                     (2700 * 1000)
+#endif
+
+/* user interface */
+#define CONFIG_SYS_PROMPT                      "STV0991> "
+#define CONFIG_SYS_CBSIZE                      1024
+#define CONFIG_SYS_PBSIZE                      (CONFIG_SYS_CBSIZE \
+                                               +sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* MISC */
+#define CONFIG_SYS_LOAD_ADDR                   0x00000000
+#define CONFIG_SYS_INIT_RAM_SIZE               0x8000
+#define CONFIG_SYS_INIT_RAM_ADDR               0x00190000
+#define CONFIG_SYS_INIT_SP_OFFSET              \
+       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+/* U-boot Load Address */
+#define CONFIG_SYS_TEXT_BASE                   0x00010000
+#define CONFIG_SYS_INIT_SP_ADDR                        \
+       (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* GMAC related configs */
+
+#define CONFIG_MII
+#define CONFIG_PHYLIB
+#define CONFIG_CMD_NET
+#define CONFIG_DESIGNWARE_ETH
+#define CONFIG_DW_ALTDESCRIPTOR
+#define CONFIG_PHY_MICREL
+
+/* Command support defines */
+#define CONFIG_CMD_PING
+#define CONFIG_PHY_RESET_DELAY                 10000           /* in usec */
+
+#include "config_cmd_default.h"
+#undef CONFIG_CMD_SAVEENV
+
+#define CONFIG_SYS_MEMTEST_START               0x0000
+#define CONFIG_SYS_MEMTEST_END                 1024*1024
+#define CONFIG_CMD_MEMTEST
+
+/* Misc configuration */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_BOOTDELAY                       3
+#define CONFIG_BOOTCOMMAND                     "go 0x40040000"
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_STOP_STR               " "
+#define CONFIG_AUTOBOOT_PROMPT                 \
+       "Hit SPACE in %d seconds to stop autoboot.\n", bootdelay
+
+#endif /* __CONFIG_H */
index 6ab2184..c097b98 100644 (file)
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_KEYBOARD
 #ifdef CONFIG_USB_KEYBOARD
-#define CONFIG_SYS_USB_EVENT_POLL
+#define CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
 #define CONFIG_SYS_STDIO_DEREGISTER
 #define CONFIG_PREBOOT "if hdmidet; then usb start; fi"
 #endif /* CONFIG_USB_KEYBOARD */