adsvix cerf250 cradle csb226 \
delta innokom lubbock pleb2 \
pxa255_idp wepep250 xaeniax xm250 \
- xsengine zylonite \
+ xsengine zylonite triton320 \
"
LIST_ixp="ixdp425 ixdpg425 pdnb3"
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
-
+CROSS_COMPILE = arm-linux-
VERSION = 1
PATCHLEVEL = 1
SUBLEVEL = 6
$(obj)u-boot.bin: $(obj)u-boot
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+ $(OBJCOPY) ${OBJCFLAGS} -O elf32-littlearm $< $(obj)u-boot.elf
$(obj)u-boot.img: $(obj)u-boot.bin
./tools/mkimage -A $(ARCH) -T firmware -C none \
zylonite_config :
@$(MKCONFIG) $(@:_config=) arm pxa zylonite
+triton320_config :
+ @$(MKCONFIG) $(@:_config=) arm pxa triton320
+
+
#########################################################################
## ARM1136 Systems
#########################################################################
*
* Last ChangeLog Entry
* $Log$
- * Revision 1.1 2007-03-09 09:43:18 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 16:58:58 lothar
+ * imported KARO specific modifications
*
* Revision 1.4 2005/03/02 16:40:20 mleeman
* remove empty labels (3.4 complains)
*
* Last ChangeLog Entry
* $Log$
- * Revision 1.1 2007-03-09 09:43:18 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 16:58:58 lothar
+ * imported KARO specific modifications
*
* Revision 1.2 2005/02/21 12:48:58 mleeman
* update of copyright years (feedback wd)
*
* Last ChangeLog Entry
* $Log$
- * Revision 1.1 2007-03-09 09:43:18 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 16:58:58 lothar
+ * imported KARO specific modifications
*
* Revision 1.3 2005/02/21 12:48:58 mleeman
* update of copyright years (feedback wd)
*
* Last ChangeLog Entry
* $Log$
- * Revision 1.1 2007-03-09 09:43:18 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 16:58:59 lothar
+ * imported KARO specific modifications
*
* Revision 1.2 2005/02/21 12:48:58 mleeman
* update of copyright years (feedback wd)
--- /dev/null
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := triton320.o nand.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+####PLATFORM_CPPFLAGS+= -Wa,-mfpu=softvfp
+#PLATFORM_CPPFLAGS+= -DDEBUG
+TEXT_BASE = 0x800c0000
+#####TEXT_BASE = 0x007c0000
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/* Board support for 1 or 2 flash devices */
+#define FLASH_PORT_WIDTH32
+#undef FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH ushort
+#define FLASH_PORT_WIDTHV vu_short
+#define SWAP(x) __swab16(x)
+#else
+#define FLASH_PORT_WIDTH ulong
+#define FLASH_PORT_WIDTHV vu_long
+#define SWAP(x) __swab32(x)
+#endif
+
+#define FPW FLASH_PORT_WIDTH
+#define FPWV FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info);
+static int write_data (flash_info_t *info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+#if 0
+ int i;
+ ulong size = 0;
+
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+ switch (i) {
+ case 0:
+ flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+ flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+ break;
+ case 1:
+ flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]);
+ flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
+ break;
+ default:
+ panic ("configured too many flash banks!\n");
+ break;
+ }
+ size += flash_info[i].size;
+ }
+
+ /* Protect monitor and environment sectors
+ */
+ flash_protect ( FLAG_PROTECT_SET,
+ CFG_FLASH_BASE,
+ CFG_FLASH_BASE + monitor_flash_len - 1,
+ &flash_info[0] );
+
+ flash_protect ( FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] );
+
+ return size;
+#endif
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ return;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+ for (i = 0; i < info->sector_count; i++) {
+ info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+ info->protect[i] = 0;
+ }
+ }
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_INTEL:
+ printf ("INTEL ");
+ break;
+ default:
+ printf ("Unknown Vendor ");
+ break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_28F128J3A:
+ printf ("28F128J3A\n");
+ break;
+ default:
+ printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " ");
+ }
+ printf ("\n");
+ return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info)
+{
+ volatile FPW value;
+
+ /* Write auto select command: read Manufacturer ID */
+ addr[0x5555] = (FPW) 0x00AA00AA;
+ addr[0x2AAA] = (FPW) 0x00550055;
+ addr[0x5555] = (FPW) 0x00900090;
+
+ mb ();
+ value = addr[0];
+
+ switch (value) {
+
+ case (FPW) INTEL_MANUFACT:
+ info->flash_id = FLASH_MAN_INTEL;
+ break;
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
+ return (0); /* no or unknown flash */
+ }
+
+ mb ();
+ value = addr[1]; /* device ID */
+
+ switch (value) {
+
+ case (FPW) INTEL_ID_28F128J3A:
+ info->flash_id += FLASH_28F128J3A;
+ info->sector_count = 128;
+ info->size = 0x02000000;
+ break; /* => 16 MB */
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ break;
+ }
+
+ if (info->sector_count > CFG_MAX_FLASH_SECT) {
+ printf ("** ERROR: sector count %d > max (%d) **\n",
+ info->sector_count, CFG_MAX_FLASH_SECT);
+ info->sector_count = CFG_MAX_FLASH_SECT;
+ }
+
+ addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
+
+ return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ int flag, prot, sect;
+ ulong type, start, last;
+ int rcode = 0;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ type = (info->flash_id & FLASH_VENDMASK);
+ if ((type != FLASH_MAN_INTEL)) {
+ printf ("Can't erase unknown flash type %08lx - aborted\n",
+ info->flash_id);
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ start = get_timer (0);
+ last = start;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts ();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ FPWV *addr = (FPWV *) (info->start[sect]);
+ FPW status;
+
+ printf ("Erasing sector %2d ... ", sect);
+
+ /* arm simple, non interrupt dependent timer */
+ reset_timer_masked ();
+
+ *addr = (FPW) 0x00500050; /* clear status register */
+ *addr = (FPW) 0x00200020; /* erase setup */
+ *addr = (FPW) 0x00D000D0; /* erase confirm */
+
+ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+ if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ *addr = (FPW) 0x00B000B0; /* suspend erase */
+ *addr = (FPW) 0x00FF00FF; /* reset to read mode */
+ rcode = 1;
+ break;
+ }
+ }
+
+ *addr = 0x00500050; /* clear status register cmd. */
+ *addr = 0x00FF00FF; /* resest to read mode */
+
+ printf (" done\n");
+ }
+ }
+ return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong cp, wp;
+ FPW data;
+ int count, i, l, rc, port_width;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ return 4;
+ }
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+ wp = (addr & ~1);
+ port_width = 2;
+#else
+ wp = (addr & ~3);
+ port_width = 4;
+#endif
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i = 0, cp = wp; i < l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+ for (; i < port_width && cnt > 0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt == 0 && i < port_width; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+ return (rc);
+ }
+ wp += port_width;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ count = 0;
+ while (cnt >= port_width) {
+ data = 0;
+ for (i = 0; i < port_width; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+ return (rc);
+ }
+ wp += port_width;
+ cnt -= port_width;
+ if (count++ > 0x800) {
+ spin_wheel ();
+ count = 0;
+ }
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i < port_width; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, FPW data)
+{
+ FPWV *addr = (FPWV *) dest;
+ ulong status;
+ int flag;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*addr & data) != data) {
+ printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
+ return (2);
+ }
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts ();
+
+ *addr = (FPW) 0x00400040; /* write setup */
+ *addr = data;
+
+ /* arm simple, non interrupt dependent timer */
+ reset_timer_masked ();
+
+ /* wait while polling the status register */
+ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+ if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+ *addr = (FPW) 0x00FF00FF; /* restore read mode */
+ return (1);
+ }
+ }
+
+ *addr = (FPW) 0x00FF00FF; /* restore read mode */
+
+ return (0);
+}
+
+void inline spin_wheel (void)
+{
+ static int p = 0;
+ static char w[] = "\\/-";
+
+ printf ("\010%c", w[p]);
+ (++p == 3) ? (p = 0) : 0;
+}
--- /dev/null
+\r
+#include <config.h>\r
+#include <version.h>\r
+#include <asm/arch/pxa-regs.h>\r
+\r
+\r
+#define DAVICOM_RDF 4\r
+#define DAVICOM_RDN 2\r
+#define DAVICOM_RT 4 /* VLIO */\r
+\r
+#define DEFAULT_RDF 15\r
+#define DEFAULT_RDN 15\r
+#define DEFAULT_RT 0\r
+\r
+\r
+\r
+\r
+DRAM_SIZE: .long CFG_DRAM_SIZE\r
+\r
+/* wait for coprocessor write complete */\r
+.macro CPWAIT reg\r
+ mrc p15,0,\reg,c2,c0,0\r
+ mov \reg,\reg\r
+ sub pc,pc,#4\r
+.endm\r
+\r
+\r
+.macro wait time\r
+ ldr r2, =OSCR\r
+ mov r3, #0\r
+ str r3, [r2]\r
+0:\r
+ ldr r3, [r2]\r
+ cmp r3, \time\r
+ bls 0b\r
+.endm\r
+\r
+\r
+ // macro to print a string\r
+ // modifies r9-r12\r
+.macro PRINT_STRING_FF address\r
+ ldr r9, =\address \r
+ ldr r10, =FFLSR\r
+ ldr r11, =FFTHR\r
+ \r
+ \r
+12:\r
+ ldr r12, [r10] // LSR\r
+ and r12, r12, #32\r
+ cmp r12, #32\r
+ bne 12b\r
+ \r
+ ldrb r12, [r9], #1\r
+ str r12, [r11]\r
+ cmp r12, #0\r
+ bne 12b\r
+.endm\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+/*\r
+ * Memory setup is already done by system boot loader\r
+ */\r
+\r
+.globl lowlevel_init\r
+lowlevel_init:\r
+\r
+ mov r8, lr @ save link register contents\r
+\r
+#if 0\r
+ b 930f\r
+__string_good_1:\r
+\r
+ .ascii "\r\nup to now, it is ok \r\n\0" \r
+ .balign 4\r
+\r
+930:\r
+ PRINT_STRING_FF __string_good_1\r
+\r
+#endif \r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+ \r
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
+@ @\r
+@ @\r
+@ first enable the clocks we need for the board @\r
+@ @\r
+@ @\r
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
+ \r
+\r
+ ldr r0, =CKENA\r
+ ldr r2, [r0]\r
+ ldr r3, =(CKENA_4_NAND | CKENA_10_SRAM | CKENA_9_SMC | CKENA_8_DMC | CKENA_22_FFUART)\r
+ orr r2, r2, r3\r
+ str r2, [r0]\r
+\r
+\r
+\r
+\r
+ ldr r0, =CKENB\r
+ ldr r2, [r0]\r
+ ldr r3, =CKENB_7_GPIO\r
+ orr r2, r2, r3\r
+ str r2, [r0]\r
+ \r
+\r
+\r
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
+@ @\r
+@ @\r
+@ init GPIO pins now @\r
+@ @\r
+@ @\r
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
+\r
+ \r
+\r
+\r
+__init_GPIO_pins_start:\r
+\r
+ \r
+ \r
+ \r
+ @ must set the GPIOs up before any chip selects will work\r
+ @ first, clear all values\r
+ ldr r1, =0xffffffff\r
+ @ reset all output registers\r
+ ldr r0, =GPCR0\r
+ str r1, [r0], #4\r
+ str r1, [r0], #4\r
+ str r1, [r0]\r
+ ldr r0, =GPCR3\r
+ str r1, [r0]\r
+\r
+\r
+\r
+ add r1, pc, #(__hal_gpio_init_table_0 - (.+8)) @ load table base \r
+ mov r3, #GPIO_HIGH @ feature mask of output = high/low\r
+ \r
+ \r
+ ldr r2, =GPSR0 \r
+ bl hal_init_gpio_register @ Output Set Register for GPIO [31..0]\r
+ bl hal_init_gpio_register @ Output Set Register for GPIO [63..32]\r
+ bl hal_init_gpio_register @ Output Set Register for GPIO [95..64]\r
+ ldr r2, =GPSR3 \r
+ bl hal_init_gpio_register @ Output Set Register for GPIO [127..96]\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+ add r1, pc, #(__hal_gpio_init_table_0 - (.+8)) @ load table base \r
+ mov r3, #GPIO_DIR_OUTPUT @ feature mask of output direction\r
+ \r
+ \r
+ ldr r2, =GPDR0 \r
+ bl hal_init_gpio_register @ Output Direction Register for GPIO [31..0]\r
+ bl hal_init_gpio_register @ Output Direction Register for GPIO [63..32]\r
+ bl hal_init_gpio_register @ Output Direction Register for GPIO [95..64]\r
+ ldr r2, =GPDR3 \r
+ bl hal_init_gpio_register @ Output Direction Register for GPIO [127..96]\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+ add r1, pc, #(__hal_gpio_init_table_0 - (.+8)) @ load table base \r
+ mov r3, #GPIO_REDGE @ feature mask of rising edge\r
+ \r
+ \r
+ ldr r2, =GRER0 \r
+ bl hal_init_gpio_register @ Output Rising Edge Register for GPIO [31..0]\r
+ bl hal_init_gpio_register @ Output Rising Edge Register for GPIO [63..32]\r
+ bl hal_init_gpio_register @ Output Rising Edge Register for GPIO [95..64]\r
+ ldr r2, =GRER3 \r
+ bl hal_init_gpio_register @ Output Rising Edge Register for GPIO [127..96]\r
+\r
+\r
+\r
+\r
+ add r1, pc, #(__hal_gpio_init_table_0 - (.+8)) @ load table base \r
+ mov r3, #GPIO_FEDGE @ feature mask of rising edge\r
+ \r
+ \r
+ ldr r2, =GFER0 \r
+ bl hal_init_gpio_register @ Output Falling Edge Register for GPIO [31..0]\r
+ bl hal_init_gpio_register @ Output Falling Edge Register for GPIO [63..32]\r
+ bl hal_init_gpio_register @ Output Falling Edge Register for GPIO [95..64]\r
+ ldr r2, =GFER3 \r
+ bl hal_init_gpio_register @ Output Falling Edge Register for GPIO [127..96]\r
+\r
+\r
+\r
+\r
+\r
+ @ reset all edge detect registers\r
+ ldr r1, =0xffffffff\r
+ @ reset all output registers\r
+ ldr r0, =GEDR0\r
+ str r1, [r0], #4\r
+ str r1, [r0], #4\r
+ str r1, [r0]\r
+ ldr r0, =GEDR3\r
+ str r1, [r0]\r
+ \r
+__init_GPIO_pins_end: \r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
+@ @\r
+@ @\r
+@ init MPFR now @\r
+@ @\r
+@ @\r
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
+\r
+ \r
+\r
+\r
+__init_MPFR_start:\r
+ \r
+\r
+ ldr r2, =0x40e10000 @ physical base address of MFPRs\r
+ add r1, pc, #(__hal_MFPR_init_table - (.+8)) @ Address of data for MFPR settings \r
+\r
+\r
+1:\r
+ ldrh r3, [r1], #2 @ load offset of MFPR\r
+ cmp r3, #0\r
+ beq __init_MFPR_end @ if offset = 0 -> end of table\r
+ add r3, r3, r2 @ r3 = MFPR address now\r
+\r
+ ldrh r4, [r1], #2 @ load bits [31..16]\r
+ mov r4, r4, lsl #16 @ shift it up 16 bits\r
+ ldrh r5, [r1], #2 @ load bits [15..0]\r
+ add r4, r4, r5\r
+\r
+ str r4, [r3] @ store data\r
+ ldr r4, [r3] @ dummy read to be sure that the value is stored\r
+ b 1b\r
+\r
+\r
+\r
+ \r
+ \r
+ \r
+__init_MFPR_end: \r
+\r
+\r
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
+@ @\r
+@ @\r
+@ Initialize static Memory Controller @\r
+@ @\r
+@ @\r
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
+\r
+ \r
+\r
+\r
+__init_Static_Mem_Contr_start:\r
+\r
+\r
+ ldr r0, =CSMSADRCFG @ Clock Configuration Register\r
+ mov r1, #2 \r
+ str r1, [r0]\r
+\r
+\r
+\r
+ @ initialise the CS Address Configuration Register\r
+ \r
+ ldr r0, =CSADRCFG0 @ only synchronus flash is allowed\r
+ ldr r1, =CSADRCFG_ALW1 @ not used in the moment\r
+ str r1, [r0]\r
+\r
+ ldr r0, =CSADRCFG1 @ only synchronus flash is allowed\r
+ ldr r1, =CSADRCFG_ALW1 @ not used in the moment\r
+ str r1, [r0]\r
+\r
+ ldr r0, =CSADRCFG2 @ only synchronus flash is allowed\r
+ ldr r1, =(CSADRCFG_INFTYPE_VLIO | CSADRCFG_INFTYPE_BASE0 | CSADRCFG_AdrCfg_FullLatch | CSADRCFG_Split16 | CSADRCFG_ALW7 | CSADRCFG_ALT_1S1H) @ used for Davicom Ethernet\r
+ str r1, [r0]\r
+\r
+ ldr r0, =CSADRCFG3 @ only synchronus flash is allowed\r
+ ldr r1, =CSADRCFG_ALW1 @ not used in the moment\r
+ str r1, [r0]\r
+\r
+\r
+\r
+\r
+\r
+\r
+ ldr r0, =MSC0 \r
+ ldr r1, = (DEFAULT_RDN<<24) | (DEFAULT_RDF<<20) | (1<<19) | (DEFAULT_RT<<16) | (DEFAULT_RDN<<8) | (DEFAULT_RDF<<4) | (1<<3) | DEFAULT_RT\r
+ str r1, [r0]\r
+ ldr r0, =MSC1\r
+ ldr r1, =(DEFAULT_RDN<<24) | (DEFAULT_RDF<<20) | (1<<19) | (DEFAULT_RT<<16) | (DAVICOM_RDN<<8) | (DAVICOM_RDF<<4) | (1<<3) | DAVICOM_RT\r
+ str r1, [r0]\r
+\r
+\r
+ @@@ Compact Flash Setup @@@\r
+ ldr r0, =MCMEM0\r
+ ldr r1, =0x0003c80f @ 4081\r
+ str r1, [r0]\r
+ \r
+ ldr r0, =MCATT0 \r
+ ldr r1, =0x0003c80f\r
+ str r1, [r0]\r
+\r
+ ldr r0, =MCIO0\r
+ ldr r1, =0x0003c80f\r
+ str r1, [r0]\r
+ \r
+ ldr r0, =CSADRCFG_P\r
+ ldr r1, =0x003e080C\r
+ str r1, [r0]\r
+\r
+ ldr r0, =MECR\r
+ mov r1, #2 @Set the CIT (Card Is There) bit\r
+ str r1, [r0]\r
+\r
+\r
+\r
+\r
+__init_Static_Mem_Contr_end:\r
+\r
+\r
+\r
+\r
+\r
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
+@ @\r
+@ @\r
+@ clear the RDH bit in the ASCR register @\r
+@ @\r
+@ @\r
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
+\r
+\r
+\r
+ ldr r0, =ASCR\r
+ ldr r1, [r0]\r
+ ldr r2, =0x80000000\r
+ bic r1, r1, r2\r
+ str r1, [r0]\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
+@ @\r
+@ @\r
+@ undo Reset for DAVICOM @\r
+@ @\r
+@ @\r
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
+\r
+\r
+\r
+ ldr r0, =GPCR3\r
+ ldr r1, =0x00000080\r
+ str r1, [r0]\r
+\r
+\r
+\r
+\r
+\r
+ /* ---------------------------------------------------------------- */\r
+ /* End lowlevel_init */\r
+ /* ---------------------------------------------------------------- */\r
+\r
+endlowlevel_init:\r
+\r
+ mov pc, r8\r
+\r
+\r
+\r
+hal_init_gpio_register:\r
+ @ r1 = table address\r
+ @ r2 = register address\r
+ @ r3 = feature mask\r
+\r
+ mov r4, #1 @ mask register\r
+ mov r5, #0 @ this is the register where the value is composed\r
+\r
+1:\r
+ ldrb r6, [r1], #1 @ load table entry, increase pointer\r
+ tst r6, r3 @ test the table entry with feature mask\r
+ orrne r5, r5, r4 @ OR mask bit to value if Z=0, means bit was 1\r
+\r
+ movs r4, r4, lsl #1 @ shift mask bit\r
+ bne 1b\r
+\r
+ str r5, [r2], #4 @ store register and increase address\r
+ mov pc, lr @ jump back to calling function\r
+\r
+\r
+\r
+\r
+\r
+\r
+ \r
+\r
+ .balign 32\r
+\r
+\r
+\r
+__hal_MFPR_init_table: \r
+ .short 0x0124, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO0 -> GPIO Input (GPIO0 key)\r
+ .short 0x0128, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO1 -> GPIO Input (unused) \r
+ .short 0x012C, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO2 -> RDY \r
+ .short 0x0130, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ MFPR GPIO3 -> nCS2 (Ethernet) \r
+ .short 0x0134, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO4 -> GPIO Input (unused) \r
+ .short 0x028C, 0x0000, AF_SEL_3 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ MFPR GPIO5 -> nPIOR \r
+ .short 0x0290, 0x0000, AF_SEL_3 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ MFPR GPIO6 -> nPIOW \r
+ .short 0x0294, 0x0000, AF_SEL_3 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ MFPR GPIO7 -> nIOS16\r
+ .short 0x0298, 0x0000, AF_SEL_3 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ MFPR GPIO8 -> nPWAIT \r
+ .short 0x029C, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO9 -> GPIO Input (USB Power Detect) \r
+ .short 0x0458, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO10 -> GPIO Input (USB Cable Detect) \r
+ .short 0x02A0, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO11 -> GPIO Input (unused) \r
+ .short 0x02A4, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO12 -> GPIO Input (unused) \r
+ .short 0x02A8, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO13 -> GPIO Input (unused) \r
+ .short 0x02AC, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO14 -> GPIO Output (Backlight Enable) \r
+ .short 0x02B0, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ MFPR GPIO15 -> GPIO Output (nMIC_PWR) \r
+ .short 0x02B4, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ MFPR GPIO16 -> GPIO Input (CF-Card BVD1) \r
+ .short 0x02B8, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ MFPR GPIO17 -> GPIO Input (CF-Card BVD2)\r
+ .short 0x02BC, 0x0000, AF_SEL_4 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ MFPR GPIO18 -> MM1_DAT0\r
+ .short 0x02C0, 0x0000, AF_SEL_4 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ MFPR GPIO19 -> MM1_DAT1\r
+ .short 0x02C4, 0x0000, AF_SEL_4 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ MFPR GPIO20 -> MM1_DAT2\r
+ .short 0x02C8, 0x0000, AF_SEL_4 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ MFPR GPIO21 -> MM1_DAT3\r
+ .short 0x02CC, 0x0000, AF_SEL_4 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ MFPR GPIO22 -> MM1_MMCLK\r
+ .short 0x02D0, 0x0000, AF_SEL_4 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ MFPR GPIO23 -> MM1_MMCMD\r
+ .short 0x02D4, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO24 -> GPIO Input (unused)\r
+ .short 0x02D8, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO25 -> GPIO Input (unused)\r
+ .short 0x02DC, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO26 -> GPIO Input (unused)\r
+ .short 0x0400, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO27 -> GPIO Input (unused)\r
+ .short 0x0404, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO28 -> GPIO Input (unused)\r
+ .short 0x0408, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO29 -> GPIO Input (unused)\r
+ .short 0x040C, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO30 -> GPIO Input (ETN Wakeup)\r
+ .short 0x0410, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO31 -> GPIO Input (ETN Interrupt)\r
+ .short 0x0414, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ MFPR GPIO32 -> SCL\r
+ .short 0x0418, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ MFPR GPIO33 -> SDA\r
+ .short 0x041C, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO34 -> GPIO Input (AC97 IRQ)\r
+ .short 0x0420, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO35 -> AC97_SDATAIN0\r
+ .short 0x0424, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO36 -> GPIO Input (unused)\r
+ .short 0x0428, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO37 -> AC97_SDATAOUT\r
+ .short 0x042C, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO38 -> AC97_SYNC\r
+ .short 0x0430, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO39 -> AC97_BITCLK\r
+ .short 0x0434, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ MFPR GPIO40 -> nAC97_Reset\r
+ .short 0x0438, 0x0000, AF_SEL_2 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ MFPR GPIO41 -> FF_RxD\r
+ .short 0x043C, 0x0000, AF_SEL_2 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ MFPR GPIO42 -> FF_TxD\r
+ .short 0x0440, 0x0000, AF_SEL_2 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ MFPR GPIO43 -> FF_CTS \r
+ .short 0x0444, 0x0000, AF_SEL_2 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ MFPR GPIO44 -> FF_DCD\r
+ .short 0x0448, 0x0000, AF_SEL_2 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ MFPR GPIO45 -> FF_DSR\r
+ .short 0x044C, 0x0000, AF_SEL_2 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ MFPR GPIO46 -> FF_RI\r
+ .short 0x0450, 0x0000, AF_SEL_2 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ MFPR GPIO47 -> FF_DTR\r
+ .short 0x0454, 0x0000, AF_SEL_2 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ MFPR GPIO48 -> FF_RTS \r
+ .short 0x045C, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO49 -> GPIO Input (unused) \r
+ .short 0x0460, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO50 -> GPIO Input (unused) \r
+ .short 0x0464, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO51 -> GPIO Input (unused) \r
+ .short 0x0468, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO52 -> GPIO Input (unused) \r
+ .short 0x046C, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO53 -> GPIO Input (unused) \r
+ .short 0x0470, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO54 -> GPIO Input (unused) \r
+ .short 0x0474, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO55 -> GPIO Input (unused) \r
+ .short 0x0478, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO56 -> GPIO Input (unused)\r
+ .short 0x047C, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO57 -> GPIO Input (unused) \r
+ .short 0x0480, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO58 -> GPIO Input (unused) \r
+ .short 0x0484, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO59 -> GPIO Input (unused)\r
+ .short 0x0488, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO60 -> GPIO Input (unused)\r
+ .short 0x048C, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO61 -> GPIO Input (unused)\r
+ .short 0x0490, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO62 -> GPIO Input (unused)\r
+ .short 0x04B4, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO63 -> LDD[8] \r
+ .short 0x04B8, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO64 -> LDD[9] \r
+ .short 0x04BC, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO65 -> LDD[10] \r
+ .short 0x04C0, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO66 -> LDD[11] \r
+ .short 0x04C4, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO67 -> LDD[12] \r
+ .short 0x04C8, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO68 -> LDD[13] \r
+ .short 0x04CC, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO69 -> LDD[14] \r
+ .short 0x04D0, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO70 -> LDD[15] \r
+ .short 0x04D4, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO71 -> LDD[16] \r
+ .short 0x04D8, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO72 -> LDD[17] \r
+ .short 0x04DC, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO73 -> GPIO Input (LCD Header) \r
+ .short 0x04F0, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO74 -> GPIO Input (LCD Header) \r
+ .short 0x04F4, 0x0000, AF_SEL_0 | DRIVE_SLOW_10mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO75 -> GPIO Output (userLED red) \r
+ .short 0x04F8, 0x0000, AF_SEL_0 | DRIVE_SLOW_10mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO76 -> GPIO Output (userLED green) \r
+ .short 0x04FC, 0x0000, AF_SEL_0 | DRIVE_SLOW_10mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO77 -> GPIO Output (userLED red) \r
+ .short 0x0500, 0x0000, AF_SEL_0 | DRIVE_SLOW_10mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO78 -> GPIO Output (userLED green) \r
+ .short 0x0504, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO79 -> GPIO Input (unused) \r
+ .short 0x0508, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO80 -> GPIO Input (unused) \r
+ .short 0x050C, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO81 -> GPIO Input (unused) \r
+ .short 0X0510, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO82 -> GPIO Input (unused) \r
+ .short 0X0514, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO83 -> GPIO Input (unused) \r
+ .short 0x0518, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO84 -> GPIO Input (unused) \r
+ .short 0x051C, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO85 -> GPIO Input (unused) \r
+ .short 0x0520, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO86 -> GPIO Input (unused) \r
+ .short 0x0524, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO87 -> GPIO Input (unused) \r
+ .short 0x0528, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO88 -> GPIO Input (unused) \r
+ .short 0x052C, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO89 -> GPIO Input (unused) \r
+ .short 0x0530, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO90 -> GPIO Input (unused) \r
+ .short 0x0534, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO91 -> GPIO Input (unused) \r
+ .short 0x0538, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO92 -> GPIO Input (unused) \r
+ .short 0x053C, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO93 -> GPIO Input (unused) \r
+ .short 0x0540, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO94 -> GPIO Input (unused) \r
+ .short 0x0544, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO95 -> GPIO Input (unused) \r
+ .short 0x0548, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO96 -> GPIO Input (unused) \r
+ .short 0x054C, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO97 -> CF_IREQ_RDY\r
+ .short 0x0550, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO98 -> CF_CD \r
+ .short 0x0600, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ MFPR GPIO99 -> CF_RESET \r
+ .short 0x0604, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | | PULL_SEL @ MFPR GPIO100 -> GPIO Input (Boot option) \r
+ .short 0x0608, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | | PULL_SEL @ MFPR GPIO101 -> GPIO Input (Boot option) \r
+ .short 0x060C, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | | PULL_SEL @ MFPR GPIO102 -> GPIO Input (Boot option) \r
+ .short 0x0610, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ MFPR GPIO103 -> GPIO Output (ETN_RST)\r
+ .short 0x0614, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ MFPR GPIO104 -> GPIO Output (nSD_PWR)\r
+ .short 0x0618, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ MFPR GPIO105 -> GPIO Input (nSD_CD) \r
+ .short 0x061C, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ MFPR GPIO106 -> GPIO Input (nSD_WP) \r
+ .short 0x0620, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ MFPR GPIO107 -> ICP_TxD \r
+ .short 0x0624, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ MFPR GPIO108 -> ICP_RxD \r
+ .short 0x0628, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ MFPR GPIO109 -> BT_RTS \r
+ .short 0x062C, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ MFPR GPIO110 -> BT_RxD \r
+ .short 0x0630, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ MFPR GPIO111 -> BT_TxD \r
+ .short 0x0634, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ MFPR GPIO112 -> BT_CTS \r
+ .short 0x0638, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO113 -> GPIO Input (unused) \r
+ .short 0x063C, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO114 -> GPIO Input (unused) \r
+ .short 0x0640, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO115 -> GPIO Input (unused) \r
+ .short 0x0644, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO116 -> GPIO Input (unused) \r
+ .short 0x0648, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO117 -> GPIO Input (unused) \r
+ .short 0x064C, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO118 -> GPIO Input (unused) \r
+ .short 0x0650, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO119 -> GPIO Input (unused) \r
+ .short 0x0654, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO120 -> GPIO Input (unused) \r
+ .short 0x0658, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO121 -> GPIO Input (unused) \r
+ .short 0x065C, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO122 -> GPIO Input (unused) \r
+ .short 0x0660, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO123 -> GPIO Input (unused) \r
+ .short 0x0664, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO124 -> GPIO Input (unused) \r
+ .short 0x0668, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO125 -> GPIO Input (unused) \r
+ .short 0x066C, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO126 -> GPIO Input (unused) \r
+ .short 0x0670, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO127 -> GPIO Input (User Key) \r
+ \r
+ .short 0x0674, 0x0000, AF_SEL_2 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ MFPR GPIO0_2 -> 1Wire \r
+ .short 0x0678, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO1_2 -> unused \r
+ .short 0x067C, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ MFPR GPIO2_2 -> GPIO Output (USBHPEN1 USB Host Power Enable)\r
+ .short 0x0680, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ MFPR GPIO3_2 -> GPIO Input (USBHPWR1 USB Host Power Fault)\r
+ .short 0x0684, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO4_2 -> GPIO Input (unused) \r
+ .short 0x0688, 0x0000, AF_SEL_0 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO5_2 -> GPIO Input (unused) \r
+ .short 0x0494, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO6_2 -> LDD[0] \r
+ .short 0x0498, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO7_2 -> LDD[1] \r
+ .short 0x049C, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO9_2 -> LDD[2] \r
+ .short 0x04A0, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO9_2 -> LDD[3] \r
+ .short 0x04A4, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO10_2 -> LDD[4] \r
+ .short 0x04A8, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO11_2 -> LDD[5] \r
+ .short 0x04AC, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO12_2 -> LDD[6] \r
+ .short 0x04B0, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO13_2 -> LDD[7] \r
+ .short 0x04E0, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO14_2 -> FCLK \r
+ .short 0x04E4, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO15_2 -> LCLK \r
+ .short 0x04E8, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO16_2 -> PCLK \r
+ .short 0x04EC, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ MFPR GPIO17_2 -> BIAS \r
+\r
+\r
+\r
+\r
+\r
+\r
+@@ .short 0x23C, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ DF_ADDR0\r
+@@ .short 0x240, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ DF_ADDR1\r
+@@ .short 0x244, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ DF_ADDR2\r
+@@ .short 0x248, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ DF_ADDR3 \r
+@@ .short 0x238, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ nLLA\r
+@@ .short 0x204, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ DF_CLE_NOE\r
+@@ .short 0x208, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ DF_ALE_WE1\r
+@@ .short 0x20C, 0x0000, AF_SEL_1 | EDGE_CLEAR @ Reserved (INTEL BBU writes this value)\r
+@@ .short 0x210, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ DF_SCLK_E\r
+@@ .short 0x214, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ nBE0\r
+@@ .short 0x218, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ nBE1\r
+@@ .short 0x21C, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ DF_ALE_WE2 \r
+@@ .short 0x220, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLDOWN_EN | PULL_SEL @ DF_INT_RnB\r
+@@ .short 0x224, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ DF_nCS0\r
+@@ .short 0x228, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ DF_nCS1\r
+@@ .short 0x22C, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ DF_nWE\r
+@@ .short 0x230, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ DF_nRE\r
+@@ .short 0x234, 0x0000, AF_SEL_1 | DRIVE_FAST_4mA | EDGE_CLEAR | PULLUP_EN | PULL_SEL @ nLUA\r
+ .short 0x0000, 0x0000, 0x0000 @ table end \r
+ \r
+ \r
+\r
+\r
+\r
+ .equ GPIO_DIR_INPUT, 0\r
+ .equ GPIO_DIR_OUTPUT, 1\r
+ .equ GPIO_LOW, 0\r
+ .equ GPIO_HIGH, 2\r
+ .equ GPIO_REDGE, 0x80\r
+ .equ GPIO_FEDGE, 0x40\r
+ .equ GPIO_NOEDGE, 0\r
+ \r
+\r
+\r
+\r
+\r
+ .balign 4\r
+__hal_gpio_init_table_0: \r
+/*GPIO 0 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO0 -> GPIO Input (user key) \r
+/*GPIO 1 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO1 -> unused \r
+/*GPIO 2 */ .byte GPIO_DIR_OUTPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO2 -> GPIO Output (USBHPEN1 USB Host Power Enable) \r
+/*GPIO 3 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO3 -> GPIO Input (USBHPWR1 USB Host Power Fault) \r
+/*GPIO 4 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO4 -> unused \r
+/*GPIO 5 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO5 -> unused \r
+/*GPIO 6 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO6 -> unused \r
+/*GPIO 7 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO7 -> unused \r
+/*GPIO 8 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO8 -> unused \r
+/*GPIO 9 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO9 -> GPIO Input (USB Power Detect) \r
+/*GPIO 10 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO10 -> GPIO Input (USB Cable Detect) \r
+/*GPIO 11 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO11 -> input \r
+/*GPIO 12 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO12 -> input \r
+/*GPIO 13 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO13 -> input \r
+/*GPIO 14 */ .byte GPIO_DIR_OUTPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO14 -> GPIO Output (Backlight Enable) \r
+/*GPIO 15 */ .byte GPIO_DIR_OUTPUT | GPIO_NOEDGE | GPIO_HIGH @ GPIO15 -> GPIO Output (nMIC_PWR) \r
+/*GPIO 16 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO16 -> GPIO Input (CF-Card BVD1) \r
+/*GPIO 17 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO17 -> GPIO Input (CF-Card BVD2) \r
+/*GPIO 18 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO18 -> unused \r
+/*GPIO 19 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO19 -> unused \r
+/*GPIO 20 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO20 -> unused \r
+/*GPIO 21 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO21 -> unused \r
+/*GPIO 22 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO22 -> unused \r
+/*GPIO 23 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO23 -> unused \r
+/*GPIO 24 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO24 -> unused \r
+/*GPIO 25 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO25 -> unused \r
+/*GPIO 26 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO26 -> unused \r
+/*GPIO 27 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO27 -> unused \r
+/*GPIO 28 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO28 -> unused \r
+/*GPIO 29 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO29 -> unused \r
+/*GPIO 30 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO30 -> GPIO Input (ETN Wakeup) \r
+/*GPIO 31 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO31 -> GPIO Input (ETN Interrupt) \r
+\r
+__hal_gpio_init_table_32: \r
+/*GPIO 32 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO32 -> unused \r
+/*GPIO 33 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO33 -> unused \r
+/*GPIO 34 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO34 -> unused \r
+/*GPIO 35 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO35 -> unused \r
+/*GPIO 36 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO36 -> unused \r
+/*GPIO 37 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO37 -> unused \r
+/*GPIO 38 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO38 -> unused \r
+/*GPIO 39 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO39 -> unused \r
+/*GPIO 40 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO40 -> unused \r
+/*GPIO 41 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO41 -> unused \r
+/*GPIO 42 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO42 -> unused \r
+/*GPIO 43 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO43 -> unused \r
+/*GPIO 44 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO44 -> unused \r
+/*GPIO 45 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO45 -> unused \r
+/*GPIO 46 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO46 -> unused \r
+/*GPIO 47 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO47 -> unused \r
+/*GPIO 48 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO48 -> unused \r
+/*GPIO 49 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO49 -> unused \r
+/*GPIO 50 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO50 -> unused \r
+/*GPIO 51 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO51 -> unused \r
+/*GPIO 52 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO52 -> unused \r
+/*GPIO 53 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO53 -> unused \r
+/*GPIO 54 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO54 -> unused \r
+/*GPIO 55 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO55 -> unused \r
+/*GPIO 56 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO56 -> unused \r
+/*GPIO 57 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO57 -> unused \r
+/*GPIO 58 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO58 -> unused \r
+/*GPIO 59 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO59 -> unused \r
+/*GPIO 60 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO60 -> unused \r
+/*GPIO 61 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO61 -> unused \r
+/*GPIO 62 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO62 -> unused \r
+/*GPIO 63 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO63 -> unused \r
+\r
+__hal_gpio_init_table_64: \r
+/*GPIO 64 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO64 -> unused \r
+/*GPIO 65 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO65 -> unused \r
+/*GPIO 66 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO66 -> unused \r
+/*GPIO 67 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO67 -> unused \r
+/*GPIO 68 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO68 -> unused \r
+/*GPIO 69 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO69 -> unused \r
+/*GPIO 70 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO70 -> unused \r
+/*GPIO 71 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO71 -> unused \r
+/*GPIO 72 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO72 -> unused \r
+/*GPIO 73 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO73 -> GPIO Input (LCD Header) \r
+/*GPIO 74 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO74 -> GPIO Input (LCD Header) \r
+/*GPIO 75 */ .byte GPIO_DIR_OUTPUT | GPIO_NOEDGE | GPIO_HIGH @ GPIO75 -> GPIO Output (userLED red) \r
+/*GPIO 76 */ .byte GPIO_DIR_OUTPUT | GPIO_NOEDGE | GPIO_HIGH @ GPIO76 -> GPIO Output (userLED green) \r
+/*GPIO 77 */ .byte GPIO_DIR_OUTPUT | GPIO_NOEDGE | GPIO_HIGH @ GPIO77 -> GPIO Output (userLED red) \r
+/*GPIO 78 */ .byte GPIO_DIR_OUTPUT | GPIO_NOEDGE | GPIO_HIGH @ GPIO78 -> GPIO Output (userLED green) \r
+/*GPIO 79 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO79 -> unused \r
+/*GPIO 80 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO80 -> unused \r
+/*GPIO 81 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO81 -> unused \r
+/*GPIO 82 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO82 -> unused \r
+/*GPIO 83 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO83 -> unused \r
+/*GPIO 84 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO84 -> unused \r
+/*GPIO 85 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO85 -> unused \r
+/*GPIO 86 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO86 -> unused \r
+/*GPIO 87 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO87 -> unused \r
+/*GPIO 88 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO88 -> unused \r
+/*GPIO 89 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO89 -> unused \r
+/*GPIO 90 */ .byte GPIO_DIR_OUTPUT | GPIO_NOEDGE | GPIO_HIGH @ GPIO90 -> unused Test Test Test Test Test Test Test Test Test \r
+/*GPIO 91 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO91 -> unused \r
+/*GPIO 92 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO92 -> unused \r
+/*GPIO 93 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO93 -> unused \r
+/*GPIO 94 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO94 -> unused \r
+/*GPIO 95 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO95 -> unused \r
+\r
+__hal_gpio_init_table_96: \r
+/*GPIO 96 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO96 -> unused \r
+/*GPIO 97 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO97 -> GPIO Input (CF_IREQ_RDY) \r
+/*GPIO 98 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO98 -> GPIO Input (CF_CD) \r
+/*GPIO 99 */ .byte GPIO_DIR_OUTPUT | GPIO_NOEDGE | GPIO_HIGH @ GPIO99 -> GPIO Output (CF_RESET) \r
+/*GPIO 100 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO100 -> GPIO Input (Boot option) \r
+/*GPIO 101 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO101 -> GPIO Input (Boot option) \r
+/*GPIO 102 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO102 -> GPIO Input (Boot option) \r
+/*GPIO 103 */ .byte GPIO_DIR_OUTPUT | GPIO_NOEDGE | GPIO_HIGH @ GPIO103 -> GPIO Output (ETN_RST) \r
+/*GPIO 104 */ .byte GPIO_DIR_OUTPUT | GPIO_NOEDGE | GPIO_HIGH @ GPIO104 -> GPIO Output (nSD_PWR) \r
+/*GPIO 105 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO105 -> GPIO Input (nSD_CD) \r
+/*GPIO 106 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO106 -> GPIO Input (nSD_WP) \r
+/*GPIO 107 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO107 -> unused \r
+/*GPIO 108 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO108 -> unused \r
+/*GPIO 109 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO109 -> unused \r
+/*GPIO 110 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO110 -> unused \r
+/*GPIO 111 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO111 -> unused \r
+/*GPIO 112 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO112 -> unused \r
+/*GPIO 113 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO113 -> unused \r
+/*GPIO 114 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO114 -> unused \r
+/*GPIO 115 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO115 -> unused \r
+/*GPIO 116 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO116 -> unused \r
+/*GPIO 117 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO117 -> unused \r
+/*GPIO 118 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO118 -> unused \r
+/*GPIO 119 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO119 -> unused \r
+/*GPIO 120 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO120 -> unused \r
+/*GPIO 121 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO121 -> unused \r
+/*GPIO 122 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO122 -> unused \r
+/*GPIO 123 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO123 -> unused \r
+/*GPIO 124 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO124 -> unused \r
+/*GPIO 125 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO125 -> unused \r
+/*GPIO 126 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO126 -> unused \r
+/*GPIO 127 */ .byte GPIO_DIR_INPUT | GPIO_NOEDGE | GPIO_LOW @ GPIO127 -> GPIO Input (User Key) \r
+ \r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*
+ * (C) Copyright 2006 DENX Software Engineering
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#define NAND_RESET_COMMAND 0x80000000
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#ifdef CONFIG_NEW_NAND_CODE
+
+#include <nand.h>
+#include <asm/arch/pxa-regs.h>
+
+#ifdef CFG_DFC_DEBUG1
+# define DFC_DEBUG1(fmt, args...) printf(fmt, ##args)
+#else
+# define DFC_DEBUG1(fmt, args...)
+#endif
+
+#ifdef CFG_DFC_DEBUG2
+# define DFC_DEBUG2(fmt, args...) printf(fmt, ##args)
+#else
+# define DFC_DEBUG2(fmt, args...)
+#endif
+
+#ifdef CFG_DFC_DEBUG3
+# define DFC_DEBUG3(fmt, args...) printf(fmt, ##args)
+#else
+# define DFC_DEBUG3(fmt, args...)
+#endif
+
+#define MIN(x, y) ((x < y) ? x : y)
+
+/* These really don't belong here, as they are specific to the NAND Model */
+static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
+
+uint8_t partial_buffer[2048+64]; /* used to handle partial writes in case of nand erase clean */
+int partial_page;
+int partial_pointer;
+
+
+
+
+static struct nand_bbt_descr delta_bbt_descr = {
+ .options = 0,
+ .offs = 0,
+ .len = 2,
+ .pattern = scan_ff_pattern
+};
+
+static struct nand_oobinfo delta_oob = {
+ .useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */
+ .eccbytes = 24,
+ .eccpos = {0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37},
+ .oobfree = { {0x20, 32}, {0, 0} }
+};
+
+
+/*
+ * not required for Monahans DFC
+ */
+static void dfc_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+{
+ return;
+}
+
+
+
+
+#if 0
+/* read device ready pin */
+static int dfc_device_ready(struct mtd_info *mtdinfo)
+{
+ if(NDSR & NDSR_RDY)
+ return 1;
+ else
+ return 0;
+ return 0;
+}
+#endif
+
+
+
+
+
+/*
+ * Write buf to the DFC Controller Data Buffer
+ */
+static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+ unsigned long bytes_multi = len & 0xfffffffc;
+ unsigned long rest = len & 0x3;
+ unsigned long *long_buf;
+ int i;
+
+ if(!partial_page) {
+ DFC_DEBUG2("dfc_write_buf: writing %d bytes starting with 0x%x .\n", len, *((unsigned long*) buf));
+ if(bytes_multi) {
+ for(i=0; i<bytes_multi; i+=4) {
+ long_buf = (unsigned long*) &buf[i];
+ NDDB = *long_buf;
+ }
+ }
+
+ if(rest) {
+ printf("dfc_write_buf: ERROR, writing non 4-byte aligned data.\n");
+ }
+ return;
+ } else {
+ DFC_DEBUG2("dfc_write_buf: writing %d bytes starting with 0x%x to local buffer.\n", len, *((unsigned long*) buf));
+ for(i=0; i<len; i++) {
+ partial_buffer[partial_pointer+i]=buf[i];
+ }
+ }
+}
+
+
+/*
+ * These functions are quite problematic for the DFC. Luckily they are
+ * not used in the current nand code, except for nand_command, which
+ * we've defined our own anyway. The problem is, that we always need
+ * to write 4 bytes to the DFC Data Buffer, but in these functions we
+ * don't know if to buffer the bytes/half words until we've gathered 4
+ * bytes or if to send them straight away.
+ *
+ * Solution: Don't use these with Mona's DFC and complain loudly.
+ */
+static void dfc_write_word(struct mtd_info *mtd, u16 word)
+{
+ printf("dfc_write_word: WARNING, this function does not work with the Monahans DFC!\n");
+}
+static void dfc_write_byte(struct mtd_info *mtd, u_char byte)
+{
+ printf("dfc_write_byte: WARNING, this function does not work with the Monahans DFC!\n");
+}
+
+/* The original:
+ * static void dfc_read_buf(struct mtd_info *mtd, const u_char *buf, int len)
+ *
+ * Shouldn't this be "u_char * const buf" ?
+ */
+static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
+{
+ int i=0, j;
+
+ /* we have to be carefull not to overflow the buffer if len is
+ * not a multiple of 4 */
+ unsigned long bytes_multi = len & 0xfffffffc;
+ unsigned long rest = len & 0x3;
+ unsigned long *long_buf;
+
+ DFC_DEBUG3("dfc_read_buf: reading %d bytes.\n", len);
+ /* if there are any, first copy multiple of 4 bytes */
+ if(bytes_multi) {
+ for(i=0; i<bytes_multi; i+=4) {
+ long_buf = (unsigned long*) &buf[i];
+ *long_buf = NDDB;
+ }
+ }
+
+ /* ...then the rest */
+ if(rest) {
+ unsigned long rest_data = NDDB;
+ for(j=0;j<rest; j++)
+ buf[i+j] = (u_char) ((rest_data>>j) & 0xff);
+ }
+
+ return;
+}
+
+/*
+ * read a word. Not implemented as not used in NAND code.
+ */
+static u16 dfc_read_word(struct mtd_info *mtd)
+{
+ printf("dfc_write_byte: UNIMPLEMENTED.\n");
+ return 0;
+}
+
+/* global var, too bad: mk@tbd: move to ->priv pointer */
+static unsigned long read_buf = 0;
+static int bytes_read = -1;
+
+/*
+ * read a byte from NDDB Because we can only read 4 bytes from NDDB at
+ * a time, we buffer the remaining bytes. The buffer is reset when a
+ * new command is sent to the chip.
+ *
+ * WARNING:
+ * This function is currently only used to read status and id
+ * bytes. For these commands always 8 bytes need to be read from
+ * NDDB. So we read and discard these bytes right now. In case this
+ * function is used for anything else in the future, we must check
+ * what was the last command issued and read the appropriate amount of
+ * bytes respectively.
+ */
+static u_char dfc_read_byte(struct mtd_info *mtd)
+{
+ unsigned char byte;
+ unsigned long dummy;
+
+ if(bytes_read < 0) {
+ read_buf = NDDB;
+ dummy = NDDB;
+ bytes_read = 0;
+ }
+ byte = (unsigned char) (read_buf>>(8 * bytes_read++));
+ DFC_DEBUG2("dfc_read_byte: byte %u: 0x%x of (0x%x).\n", bytes_read - 1, byte, read_buf);
+
+ if(bytes_read >= 4)
+ bytes_read = -1;
+
+ return byte;
+}
+
+/* calculate delta between OSCR values start and now */
+static unsigned long get_delta(unsigned long start)
+{
+ unsigned long cur = OSCR;
+
+ if(cur < start) /* OSCR overflowed */
+ return (cur + (start^0xffffffff));
+ else
+ return (cur - start);
+}
+
+/* delay function, this doesn't belong here */
+static void wait_us(unsigned long us)
+{
+ unsigned long start = OSCR;
+ us *= OSCR_CLK_FREQ;
+
+ while (get_delta(start) < us) {
+ /* do nothing */
+ }
+}
+
+static void dfc_clear_nddb(void)
+{
+ NDCR &= ~NDCR_ND_RUN;
+ wait_us(CFG_NAND_OTHER_TO);
+}
+
+/* wait_event with timeout */
+static unsigned long dfc_wait_event(unsigned long event)
+{
+ unsigned long ndsr, timeout, start = OSCR;
+
+ if(!event)
+ return 0xff000000;
+ else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD))
+ timeout = CFG_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ;
+ else
+ timeout = CFG_NAND_OTHER_TO * OSCR_CLK_FREQ;
+
+ while(1) {
+ ndsr = NDSR;
+ if(ndsr & event) {
+ NDSR |= event;
+ break;
+ }
+ if(get_delta(start) > timeout) {
+ DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%x timeout: %d ticks status register: 0x%08X control register: 0x%08X.\n", event, timeout, ndsr, NDCR);
+ return 0xff000000;
+ }
+
+ }
+ return ndsr;
+}
+
+/* we don't always wan't to do this */
+static void dfc_new_cmd(void)
+{
+ int retry = 0;
+ unsigned long status;
+
+ while(retry++ <= CFG_NAND_SENDCMD_RETRY) {
+ /* Clear NDSR */
+ NDSR = 0xFFF;
+
+ /* set NDCR[NDRUN] */
+ if(!(NDCR & NDCR_ND_RUN))
+ NDCR |= NDCR_ND_RUN;
+
+ status = dfc_wait_event(NDSR_WRCMDREQ);
+
+ if(status & NDSR_WRCMDREQ)
+ return;
+
+ DFC_DEBUG2("dfc_new_cmd: FAILED to get WRITECMDREQ, retry: %d.\n", retry);
+ dfc_clear_nddb();
+ }
+ DFC_DEBUG1("dfc_new_cmd: giving up after %d retries.\n", retry);
+}
+
+/* this function is called after Programm and Erase Operations to
+ * check for success or failure */
+static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
+{
+ unsigned long ndsr=0, event=0;
+
+ if(state == FL_WRITING) {
+ event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
+ } else if(state == FL_ERASING) {
+ event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
+ }
+
+ ndsr = dfc_wait_event(event);
+
+ if((ndsr & NDSR_CS0_BBD) || (ndsr & 0xff000000))
+ return(0x1); /* Status Read error */
+ return 0;
+}
+
+
+/* cmdfunc send commands to the DFC */
+static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command,
+ int column, int page_addr)
+{
+ /* register struct nand_chip *this = mtd->priv; */
+ unsigned long ndcb0=0, ndcb1=0, ndcb2=0, event=0;
+
+ /* clear the ugly byte read buffer */
+ bytes_read = -1;
+ read_buf = 0;
+
+ switch (command) {
+ case NAND_CMD_READ0:
+ DFC_DEBUG3("dfc_cmdfunc: NAND_CMD_READ0, page_addr: 0x%x, column: 0x%x.\n", page_addr, column);
+ dfc_new_cmd();
+ ndcb0 = (NAND_CMD_READ0 | (NAND_CMD_READSTART<<8) | (4<<16) | (1<<19));
+ ndcb1 = (column & 0xfff) | ((page_addr & 0xffff)<<16);
+ ndcb2 = 0;
+ event = NDSR_RDDREQ;
+ goto write_cmd;
+ case NAND_CMD_READ1:
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READ1 unimplemented!\n");
+ goto end;
+ case NAND_CMD_READOOB:
+ DFC_DEBUG1("dfc_cmdfunc: NAND_CMD_READOOB unimplemented!\n");
+ goto end;
+ case NAND_CMD_READID:
+ dfc_new_cmd();
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READID.\n");
+ ndcb0 = (NAND_CMD_READID | (3 << 21) | (1 << 16)); /* addr cycles*/
+ ndcb1 = 0;
+ ndcb2 = 0;
+ event = NDSR_RDDREQ;
+ goto write_cmd;
+ case NAND_CMD_PAGEPROG:
+ /* sent as a multicommand in NAND_CMD_SEQIN */
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_PAGEPROG empty due to multicmd.\n");
+ if(partial_page) {
+ partial_page=0;
+ dfc_write_buf(mtd, partial_buffer, 2048+64); /* write back the partial buffer */
+ }
+ goto end;
+ case NAND_CMD_ERASE1:
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE1, page_addr: 0x%x, column: 0x%x.\n", page_addr, column);
+ dfc_new_cmd();
+ ndcb0 = (0xd060 | (1<<25) | (2<<21) | (1<<19) | (2<<16));
+ ndcb1 = (page_addr & 0x0000ffff);
+ ndcb2 = 0;
+ goto write_cmd;
+ case NAND_CMD_SEQIN:
+ /* send PAGE_PROG command(0x1080) */
+ if(column) {
+ partial_page = 1;
+ partial_pointer = column;
+ /* read whole page into local buffer first */
+ DFC_DEBUG3("dfc_cmdfunc: NAND_CMD_READ0, page_addr: 0x%x, column: 0x%x.\n", page_addr, column);
+ dfc_new_cmd();
+ NDCB0 = (NAND_CMD_READ0 | (NAND_CMD_READSTART<<8) | (4<<16) | (1<<19));
+ NDCB0 = (column & 0xfff) | ((page_addr & 0xffff)<<16);
+ NDCB0 = 0;
+ event = NDSR_RDDREQ;
+ dfc_wait_event(event);
+ dfc_read_buf(mtd, partial_buffer, 2048+64); /* this works in that way only for large page */
+ } else {
+ partial_page = 0;
+ }
+
+ dfc_new_cmd();
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, page_addr: 0x%x, column: 0x%x.\n", page_addr, column);
+ ndcb0 = (0x1080 | (1<<25) | (1<<21) | (1<<19) | (4<<16));
+ ndcb1 = (column & 0xfff) | ((page_addr & 0xffff)<<16);
+ ndcb2 = 0;
+ event = NDSR_WRDREQ;
+ goto write_cmd;
+ case NAND_CMD_ERASE2:
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE2 empty due to multicmd.\n");
+ goto end;
+ case NAND_CMD_STATUS:
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_STATUS.\n");
+ dfc_new_cmd();
+ ndcb0 = NAND_CMD_STATUS | (4<<21);
+ ndcb1 = 0;
+ ndcb2 = 0;
+ event = NDSR_RDDREQ;
+ goto write_cmd;
+ case NAND_CMD_RESET:
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_RESET.\n");
+ return; /* DFC or NAND hangs after Reset, but we do not need the command */
+ ndcb0 = NAND_CMD_RESET | (5<<21);
+ ndcb1 = 0;
+ ndcb2 = 0;
+ event = NDSR_CS0_CMDD;
+ goto write_cmd;
+ default:
+ printk("dfc_cmdfunc: error, unsupported command.\n");
+ goto end;
+ }
+
+ write_cmd:
+ DFC_DEBUG3("dfc_cmdfunc: writing NDCB0 = 0x%08X NDCB1 = 0x%08X NDCB2 = 0x%08X\n", ndcb0, ndcb1, ndcb2);
+ NDCB0 = ndcb0;
+ NDCB0 = ndcb1;
+ NDCB0 = ndcb2;
+
+ /* wait_event: */
+ dfc_wait_event(event);
+ end:
+ return;
+}
+
+static void dfc_gpio_init(void)
+{
+ DFC_DEBUG2("Setting up DFC GPIO's.\n");
+
+ /* no idea what is done here, see triton320.c */
+ GPIO4 = 0x1;
+
+ DF_ALE_WE1 = 0x00000001;
+ DF_ALE_WE2 = 0x00000001;
+ DF_nCS0 = 0x00000001;
+ DF_nCS1 = 0x00000001;
+ DF_nWE = 0x00000001;
+ DF_nRE = 0x00000001;
+ DF_IO0 = 0x00000001;
+ DF_IO8 = 0x00000001;
+ DF_IO1 = 0x00000001;
+ DF_IO9 = 0x00000001;
+ DF_IO2 = 0x00000001;
+ DF_IO10 = 0x00000001;
+ DF_IO3 = 0x00000001;
+ DF_IO11 = 0x00000001;
+ DF_IO4 = 0x00000001;
+ DF_IO12 = 0x00000001;
+ DF_IO5 = 0x00000001;
+ DF_IO13 = 0x00000001;
+ DF_IO6 = 0x00000001;
+ DF_IO14 = 0x00000001;
+ DF_IO7 = 0x00000001;
+ DF_IO15 = 0x00000001;
+
+ DF_nWE = 0x1901;
+ DF_nRE = 0x1901;
+ DF_CLE_NOE = 0x1900;
+ DF_ALE_WE1 = 0x1901;
+ DF_INT_RnB = 0x1900;
+}
+
+/*
+ * Board-specific NAND initialization. The following members of the
+ * argument are board-specific (per include/linux/mtd/nand_new.h):
+ * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
+ * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
+ * - hwcontrol: hardwarespecific function for accesing control-lines
+ * - dev_ready: hardwarespecific function for accesing device ready/busy line
+ * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
+ * only be provided if a hardware ECC is available
+ * - eccmode: mode of ecc, see defines
+ * - chip_delay: chip dependent delay for transfering data from array to
+ * read regs (tR)
+ * - options: various chip options. They can partly be set to inform
+ * nand_scan about special functionality. See the defines for further
+ * explanation
+ * Members with a "?" were not set in the merged testing-NAND branch,
+ * so they are not set here either.
+ */
+void board_nand_init(struct nand_chip *nand)
+{
+ unsigned long value;
+#if 0 /* this is already done by low level board initialisation */
+ unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR;
+
+ /* set up GPIO Control Registers */
+ /*dfc_gpio_init(); */ /* should be done by the low level board initialisation */
+
+ /* turn on the NAND Controller Clock (104 MHz @ D0) */
+ CKENA |= (CKENA_4_NAND | CKENA_9_SMC);
+
+#undef CFG_TIMING_TIGHT
+#ifndef CFG_TIMING_TIGHT
+ tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tCH);
+ tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tCS);
+ tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tWH);
+ tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tWP);
+ tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tRH);
+ tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tRP);
+ tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tR);
+ tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tWHR);
+ tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tAR);
+#else /* this is the tight timing */
+
+ tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US)),
+ DFC_MAX_tCH);
+ tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US)),
+ DFC_MAX_tCS);
+ tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US)),
+ DFC_MAX_tWH);
+ tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US)),
+ DFC_MAX_tWP);
+ tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US)),
+ DFC_MAX_tRH);
+ tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US)),
+ DFC_MAX_tRP);
+ tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) - tCH - 2),
+ DFC_MAX_tR);
+ tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) - tCH - 2),
+ DFC_MAX_tWHR);
+ tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) - 2),
+ DFC_MAX_tAR);
+#endif /* CFG_TIMING_TIGHT */
+
+
+ DFC_DEBUG2("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR);
+
+ /* tRP value is split in the register */
+ if(tRP & (1 << 4)) {
+ tRP_high = 1;
+ tRP &= ~(1 << 4);
+ } else {
+ tRP_high = 0;
+ }
+
+ NDTR0CS0 = (tCH << 19) |
+ (tCS << 16) |
+ (tWH << 11) |
+ (tWP << 8) |
+ (tRP_high << 6) |
+ (tRH << 3) |
+ (tRP << 0);
+
+ NDTR1CS0 = (tR << 16) |
+ (tWHR << 4) |
+ (tAR << 0);
+
+ /* If it doesn't work (unlikely) think about:
+ * - ecc enable
+ * - chip select don't care
+ * - read id byte count
+ *
+ * Intentionally enabled by not setting bits:
+ * - dma (DMA_EN)
+ * - page size = 512
+ * - cs don't care, see if we can enable later!
+ * - row address start position (after second cycle)
+ * - pages per block = 32
+ * - ND_RDY : clears command buffer
+ */
+ /* NDCR_NCSX | /\* Chip select busy don't care *\/ */
+
+ NDCR = (NDCR_SPARE_EN | /* use the spare area */
+ NDCR_DWIDTH_C | /* 16bit DFC data bus width */
+ NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */
+ (2 << 16) | /* read id count = 7 ???? mk@tbd */
+ NDCR_ND_ARB_EN | /* enable bus arbiter */
+ NDCR_RDYM | /* flash device ready ir masked */
+ NDCR_CS0_PAGEDM | /* ND_nCSx page done ir masked */
+ NDCR_CS1_PAGEDM |
+ NDCR_CS0_CMDDM | /* ND_CSx command done ir masked */
+ NDCR_CS1_CMDDM |
+ NDCR_CS0_BBDM | /* ND_CSx bad block detect ir masked */
+ NDCR_CS1_BBDM |
+ NDCR_DBERRM | /* double bit error ir masked */
+ NDCR_SBERRM | /* single bit error ir masked */
+ NDCR_WRDREQM | /* write data request ir masked */
+ NDCR_RDDREQM | /* read data request ir masked */
+ NDCR_WRCMDREQM); /* write command request ir masked */
+
+
+ /* wait 10 us due to cmd buffer clear reset */
+ /* wait(10); */
+
+#endif
+
+
+ value = NDCR & ~(NDCR_ECC_EN); /* clear hardware ECC */
+ NDCR = value;
+
+ nand->hwcontrol = dfc_hwcontrol;
+/* nand->dev_ready = dfc_device_ready; */
+ nand->eccmode = NAND_ECC_SOFT;
+ nand->options = NAND_SAMSUNG_LP_OPTIONS;
+ nand->waitfunc = dfc_wait;
+ nand->read_byte = dfc_read_byte;
+ nand->write_byte = dfc_write_byte;
+ nand->read_word = dfc_read_word;
+ nand->write_word = dfc_write_word;
+ nand->read_buf = dfc_read_buf;
+ nand->write_buf = dfc_write_buf;
+
+ nand->cmdfunc = dfc_cmdfunc;
+ nand->autooob = &delta_oob;
+ nand->badblock_pattern = &delta_bbt_descr;
+}
+
+#else
+ #error "U-Boot legacy NAND support not available for Monahans DFC."
+#endif
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+ /* memory and cpu-speed are setup before relocation */
+ /* so we do _nothing_ here */
+
+ /* arch number of Lubbock-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_KARO;
+
+ /* adress of boot parameters */
+
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ setenv("stdout", "serial");
+ setenv("stderr", "serial");
+ return 0;
+}
+
+
+int dram_init (void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
+
+
+
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/pxa/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
--- /dev/null
+#!/bin/sh
+set -e
+
+export BUILD_DIR=../.build-uboot-1.1.6
+export MAKEALL_LOGDIR=../.uboot-1.1.6.log
+export CROSS_COMPILE=arm-softfloat-linux-gnu-
+
+[ -d "${BUILD_DIR}" ] || mkdir -p "${BUILD_DIR}"
+[ -d "${MAKEALL_LOGDIR}" ] || mkdir -p "${MAKEALL_LOGDIR}"
+
+BUILD_DIR=$(cd "${BUILD_DIR}" && pwd)
+MAKEALL_LOGDIR=$(cd "${MAKEALL_LOGDIR}" && pwd)
+
+sh MAKEALL triton320
memsize.o miiphybb.o miiphyutil.o \
s_record.o serial.o soft_i2c.o soft_spi.o spartan2.o spartan3.o \
usb.o usb_kbd.o usb_storage.o \
- virtex2.o xilinx.o crc16.o xyzModem.o cmd_mac.o
+ virtex2.o xilinx.o crc16.o xyzModem.o cmd_mac.o cmd_bootce.o
SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS))
--- /dev/null
+#include <common.h>\r
+#include <command.h>
+#include <net.h>\r
+#include <wince.h>\r
+\r
+DECLARE_GLOBAL_DATA_PTR; /* defines global data structure pointer */
+\r
+\r
+/*/////////////////////////////////////////////////////////////////////////////////////////////*/\r
+/* Local macro */\r
+\r
+/* Memory macro */\r
+\r
+/* #define CE_RAM_BASE 0x80100000 */\r
+/* #define CE_WINCE_VRAM_BASE 0x80000000 */\r
+/* #define CE_FIX_ADDRESS(a) (((a) - CE_WINCE_VRAM_BASE) + CE_RAM_BASE) */\r
+#define CE_FIX_ADDRESS(a) (a)\r
+\r
+/* Bin image parse states */\r
+\r
+#define CE_PS_RTI_ADDR 0\r
+#define CE_PS_RTI_LEN 1\r
+#define CE_PS_E_ADDR 2\r
+#define CE_PS_E_LEN 3\r
+#define CE_PS_E_CHKSUM 4\r
+#define CE_PS_E_DATA 5\r
+\r
+/* Min/max */\r
+\r
+#define CE_MIN(a, b) (((a) < (b)) ? (a) : (b))\r
+#define CE_MAX(a, b) (((a) > (b)) ? (a) : (b))\r
+\r
+// Macro string\r
+\r
+#define _STRMAC(s) #s\r
+#define STRMAC(s) _STRMAC(s)\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+///////////////////////////////////////////////////////////////////////////////////////////////\r
+// Global data\r
+\r
+static ce_bin __attribute__ ((aligned (32))) g_bin;\r
+static ce_net __attribute__ ((aligned (32))) g_net;\r
+\r
+\r
+///////////////////////////////////////////////////////////////////////////////////////////////\r
+// Local proto\r
+\r
+\r
+\r
+\r
+///////////////////////////////////////////////////////////////////////////////////////////////\r
+// Implementation\r
+\r
+int ce_bin_load(void* image, int imglen)\r
+{\r
+ ce_init_bin(&g_bin, image);\r
+\r
+ g_bin.dataLen = imglen;\r
+\r
+ if (ce_parse_bin(&g_bin) == CE_PR_EOF)\r
+ {\r
+ ce_prepare_run_bin(&g_bin); \r
+ return 1;\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+int ce_is_bin_image(void* image, int imglen)\r
+{\r
+ if (imglen < CE_BIN_SIGN_LEN)\r
+ {\r
+ return 0;\r
+ }\r
+\r
+ return (memcmp(image, CE_BIN_SIGN, CE_BIN_SIGN_LEN) == 0);\r
+}\r
+\r
+void ce_bin_init_parser(void)\r
+{\r
+ // No buffer address by now, will be specified \r
+ // latter by the ce_bin_parse_next routine\r
+\r
+ ce_init_bin(&g_bin, NULL); \r
+}\r
+\r
+int ce_bin_parse_next(void* parseBuffer, int len)\r
+{\r
+ int rc;\r
+\r
+ g_bin.data = (unsigned char*)parseBuffer;\r
+ g_bin.dataLen = len;\r
+ rc = ce_parse_bin(&g_bin);\r
+ \r
+ if (rc == CE_PR_EOF)\r
+ {\r
+ ce_prepare_run_bin(&g_bin); \r
+ }\r
+\r
+ return rc;\r
+}\r
+\r
+void ce_init_bin(ce_bin* bin, unsigned char* dataBuffer)\r
+{\r
+ memset(bin, 0, sizeof(ce_bin));\r
+\r
+ bin->data = dataBuffer;\r
+ bin->parseState = CE_PS_RTI_ADDR;\r
+ bin->parsePtr = (unsigned char*)&bin->rtiPhysAddr;\r
+}\r
+\r
+int ce_parse_bin(ce_bin* bin)\r
+{\r
+ unsigned char* pbData = bin->data;\r
+ int pbLen = bin->dataLen;\r
+ int copyLen;\r
+ \r
+ #ifdef DEBUG\r
+ printf("starting ce image parsing:\n\tbin->binLen: 0x%08X\n", bin->binLen);\r
+ printf("\tpbData: 0x%08X pbLEN: 0x%08X\n", pbData, pbLen);\r
+ #endif\r
+ \r
+ if (pbLen)\r
+ {\r
+ if (bin->binLen == 0)\r
+ {\r
+ // Check for the .BIN signature first\r
+ \r
+ if (!ce_is_bin_image(pbData, pbLen))\r
+ {\r
+ printf("Error: Invalid or corrupted .BIN image!\n");\r
+\r
+ return CE_PR_ERROR;\r
+ }\r
+\r
+ printf("Loading Windows CE .BIN image ...\n");\r
+\r
+ // Skip signature\r
+\r
+ pbLen -= CE_BIN_SIGN_LEN;\r
+ pbData += CE_BIN_SIGN_LEN; \r
+ }\r
+\r
+ while (pbLen)\r
+ {\r
+ switch (bin->parseState)\r
+ {\r
+ case CE_PS_RTI_ADDR:\r
+ case CE_PS_RTI_LEN:\r
+ case CE_PS_E_ADDR:\r
+ case CE_PS_E_LEN:\r
+ case CE_PS_E_CHKSUM:\r
+\r
+ copyLen = CE_MIN(sizeof(unsigned int) - bin->parseLen, pbLen);\r
+ \r
+ memcpy(&bin->parsePtr[ bin->parseLen ], pbData, copyLen);\r
+\r
+ bin->parseLen += copyLen;\r
+ pbLen -= copyLen;\r
+ pbData += copyLen;\r
+\r
+ if (bin->parseLen == sizeof(unsigned int))\r
+ {\r
+ if (bin->parseState == CE_PS_RTI_ADDR)\r
+ {\r
+ bin->rtiPhysAddr = CE_FIX_ADDRESS(bin->rtiPhysAddr); \r
+ }\r
+ else if (bin->parseState == CE_PS_E_ADDR)\r
+ {\r
+ if (bin->ePhysAddr)\r
+ {\r
+ bin->ePhysAddr = CE_FIX_ADDRESS(bin->ePhysAddr);\r
+ }\r
+ }\r
+ \r
+ bin->parseState ++;\r
+ bin->parseLen = 0;\r
+ bin->parsePtr += sizeof(unsigned int);\r
+\r
+ if (bin->parseState == CE_PS_E_DATA)\r
+ {\r
+ if (bin->ePhysAddr)\r
+ {\r
+ bin->parsePtr = (unsigned char*)(bin->ePhysAddr);\r
+ bin->parseChkSum = 0;\r
+ }\r
+ else \r
+ {\r
+ // EOF\r
+\r
+ pbLen = 0;\r
+ bin->endOfBin = 1; \r
+ }\r
+ }\r
+ } \r
+ \r
+ break;\r
+\r
+ case CE_PS_E_DATA:\r
+\r
+ if (bin->ePhysAddr)\r
+ {\r
+ copyLen = CE_MIN(bin->ePhysLen - bin->parseLen, pbLen);\r
+ bin->parseLen += copyLen;\r
+ pbLen -= copyLen;\r
+ \r
+ #ifdef DEBUG\r
+ printf("copy %d bytes from: 0x%08X to: 0x%08X\n", copyLen, pbData, bin->parsePtr);\r
+ #endif\r
+ while (copyLen --)\r
+ {\r
+ bin->parseChkSum += *pbData;\r
+ *bin->parsePtr ++ = *pbData ++; \r
+ }\r
+ \r
+ if (bin->parseLen == bin->ePhysLen)\r
+ {\r
+ printf("Section [%02d]: address 0x%08X, size 0x%08X, checksum %s\n",\r
+ bin->secion,\r
+ bin->ePhysAddr, \r
+ bin->ePhysLen, \r
+ (bin->eChkSum == bin->parseChkSum) ? "ok" : "fail");\r
+\r
+ if (bin->eChkSum != bin->parseChkSum)\r
+ {\r
+ // Checksum error!\r
+ \r
+ printf("Error: Checksum error, corrupted .BIN file!\n");\r
+\r
+ bin->binLen = 0;\r
+\r
+ return CE_PR_ERROR;\r
+ }\r
+\r
+ bin->secion ++;\r
+ bin->parseState = CE_PS_E_ADDR;\r
+ bin->parseLen = 0;\r
+ bin->parsePtr = (unsigned char*)(&bin->ePhysAddr);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ bin->parseLen = 0;\r
+ bin->endOfBin = 1;\r
+ pbLen = 0; \r
+ }\r
+\r
+ break;\r
+ }\r
+ }\r
+ }\r
+\r
+ if (bin->endOfBin)\r
+ {\r
+ // Find entry point\r
+\r
+ if (!ce_lookup_ep_bin(bin))\r
+ {\r
+ printf("Error: entry point not found!\n");\r
+\r
+ bin->binLen = 0;\r
+\r
+ return CE_PR_ERROR;\r
+ }\r
+\r
+ printf("Entry point: 0x%08X, address range: 0x%08X-0x%08X\n",\r
+ bin->eEntryPoint,\r
+ bin->rtiPhysAddr,\r
+ bin->rtiPhysAddr + bin->rtiPhysLen);\r
+\r
+ return CE_PR_EOF;\r
+ }\r
+ \r
+ // Need more data\r
+\r
+ bin->binLen += bin->dataLen;\r
+ \r
+ return CE_PR_MORE;\r
+}\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+void ce_prepare_run_bin(ce_bin* bin)\r
+{\r
+ ce_driver_globals* drv_glb;\r
+ char *e, *s;\r
+ char tmp[64];\r
+ int i;\r
+\r
+ \r
+ // Clear os RAM area (if needed)\r
+ \r
+ //if (bin->edbgConfig.flags & EDBG_FL_CLEANBOOT)\r
+ {\r
+ #ifdef DEBUG\r
+ printf("cleaning memory from 0x%08X to 0x%08X\n", bin->eRamStart, bin->eRamStart + bin->eRamLen);\r
+ #endif\r
+ printf("Preparing clean boot ... ");\r
+ memset((void*)bin->eRamStart, 0, bin->eRamLen);\r
+ printf("ok\n");\r
+ }\r
+\r
+ // Prepare driver globals (if needed)\r
+\r
+ if (bin->eDrvGlb)\r
+ {\r
+ drv_glb = (ce_driver_globals*)bin->eDrvGlb;\r
+\r
+ // Fill out driver globals\r
+\r
+ memset(drv_glb, 0, sizeof(ce_driver_globals));\r
+\r
+ // Signature\r
+\r
+ drv_glb->signature = DRV_GLB_SIGNATURE; \r
+ \r
+ // No flags by now\r
+\r
+ drv_glb->flags = 0; \r
+\r
+ /* Local ethernet MAC address */\r
+ i = getenv_r ("ethaddr", tmp, sizeof (tmp));
+ s = (i > 0) ? tmp : 0;
+\r
+ for (i = 0; i < 6; ++i) {
+ drv_glb->macAddr[i] = s ? simple_strtoul (s, &e, 16) : 0;
+ if (s)
+ s = (*e) ? e + 1 : e;
+ }\r
+\r
+\r
+ #ifdef DEBUG\r
+ printf("got MAC address %02X:%02X:%02X:%02X:%02X:%02X from environment\n", drv_glb->macAddr[0],drv_glb->macAddr[1],drv_glb->macAddr[2],drv_glb->macAddr[3],drv_glb->macAddr[4],drv_glb->macAddr[5]);\r
+ #endif\r
+\r
+ /* Local IP address */\r
+ drv_glb->ipAddr=(unsigned int)getenv_IPaddr("ipaddr");\r
+ #ifdef DEBUG\r
+ printf("got IP address ");\r
+ print_IPaddr((IPaddr_t)drv_glb->ipAddr);\r
+ printf(" from environment\n");\r
+ #endif\r
+\r
+ /* Subnet mask */\r
+ drv_glb->ipMask=(unsigned long)getenv_IPaddr("netmask");\r
+ #ifdef DEBUG\r
+ printf("got IP mask ");\r
+ print_IPaddr((IPaddr_t)drv_glb->ipMask);\r
+ printf(" from environment\n");\r
+ #endif\r
+\r
+ /* Gateway config */\r
+ drv_glb->ipGate=(unsigned long)getenv_IPaddr("gatewayip");\r
+ #ifdef DEBUG\r
+ printf("got gateway address ");\r
+ print_IPaddr((IPaddr_t)drv_glb->ipGate);\r
+ printf(" from environment\n");\r
+ #endif\r
+ \r
+\r
+\r
+\r
+\r
+ // EDBG services config\r
+\r
+ memcpy(&drv_glb->edbgConfig, &bin->edbgConfig, sizeof(bin->edbgConfig));\r
+\r
+ \r
+\r
+\r
+ }\r
+ \r
+}\r
+\r
+\r
+int ce_lookup_ep_bin(ce_bin* bin)\r
+{\r
+ ce_rom_hdr* header;\r
+ ce_toc_entry* tentry;\r
+ e32_rom* e32;\r
+ unsigned int i;\r
+ \r
+ // Check image Table Of Contents (TOC) signature\r
+\r
+ if (*(unsigned int*)(bin->rtiPhysAddr + ROM_SIGNATURE_OFFSET) != ROM_SIGNATURE)\r
+ {\r
+ // Error: Did not find image TOC signature!\r
+\r
+ return 0;\r
+ }\r
+\r
+\r
+ // Lookup entry point\r
+\r
+ header = (ce_rom_hdr*)CE_FIX_ADDRESS(*(unsigned int*)(bin->rtiPhysAddr + ROM_SIGNATURE_OFFSET + sizeof(unsigned int)));\r
+ tentry = (ce_toc_entry*)(header + 1);\r
+\r
+ for (i = 0; i < header->nummods; i ++)\r
+ {\r
+ // Look for 'nk.exe' module\r
+\r
+ if (strcmp((char*)CE_FIX_ADDRESS(tentry[ i ].fileName), "nk.exe") == 0)\r
+ {\r
+ // Save entry point and RAM addresses\r
+\r
+ e32 = (e32_rom*)CE_FIX_ADDRESS(tentry[ i ].e32Offset);\r
+\r
+ bin->eEntryPoint = CE_FIX_ADDRESS(tentry[ i ].loadOffset) + e32->e32_entryrva;\r
+ bin->eRamStart = CE_FIX_ADDRESS(header->ramStart);\r
+ bin->eRamLen = header->ramEnd - header->ramStart;\r
+ \r
+ // Save driver_globals address\r
+ // Must follow RAM section in CE config.bib file\r
+ //\r
+ // eg.\r
+ //\r
+ // RAM 80900000 03200000 RAM\r
+ // DRV_GLB 83B00000 00001000 RESERVED\r
+ //\r
+ \r
+ bin->eDrvGlb = CE_FIX_ADDRESS(header->ramEnd);\r
+\r
+ return 1;\r
+ } \r
+ }\r
+\r
+ // Error: Did not find 'nk.exe' module\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+\r
+\r
+typedef void (*CeEntryPointPtr)(void);\r
+\r
+\r
+\r
+void ce_run_bin(ce_bin* bin)\r
+{\r
+ CeEntryPointPtr EnrtryPoint;\r
+ \r
+ printf("Launching Windows CE ...\n");\r
+ \r
+ \r
+ EnrtryPoint = (CeEntryPointPtr)bin->eEntryPoint;\r
+\r
+ EnrtryPoint();\r
+ \r
+}\r
+\r
+int ce_boot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned long addr;\r
+ unsigned long image_size;\r
+ unsigned char *s;\r
+ \r
+
+ if (argc < 2) {
+ printf ("myUsage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+
+ addr = simple_strtoul(argv[1], NULL, 16);\r
+ image_size = 0x7fffffff; /* actually we do not know the image size */
+
+ printf ("## Booting Windows CE Image from address 0x%08lX ...\n", addr);
+
+\r
+ /* check if there is a valid windows CE image */\r
+ if (ce_is_bin_image((void *)addr, image_size))
+ {
+ if (!ce_bin_load((void*)addr, image_size))
+ {
+ /* Ops! Corrupted .BIN image! */
+ /* Handle error here ... */\r
+ printf("corrupted .BIN image !!!\n");\r
+ return 1;
+
+ }\r
+ if ((s = getenv("autostart")) != NULL) {
+ if (*s == 'n') {
+ /*
+ * just use bootce to load the image to SDRAM;
+ * Do not start it automatically.
+ */\r
+ return 0;\r
+ } \r
+ }\r
+ ce_run_bin(&g_bin); /* start the image */\r
+
+ } else {\r
+ printf("Image seems to be no valid Windows CE image !\n");\r
+ return 1;\r
+ \r
+ }
+ return 1; /* never reached - just to keep compiler happy */\r
+\r
+\r
+}
+\r
+\r
+\r
+U_BOOT_CMD(
+ bootce, 2, 0, ce_boot,
+ "bootce\t- Boot a Windows CE image from memory \n",\r
+ "[args..]\n"
+ "\taddr\t\t-boot image from address addr\n"
+);
+\r
+\r
+\r
+#if 1\r
+static void wince_handler (uchar * pkt, unsigned dest, unsigned src, unsigned len)
+{\r
+ \r
+
+ NetState = NETLOOP_SUCCESS; /* got input - quit net loop */\r
+ if(!memcmp(g_net.data + g_net.align_offset, gd->bd->bi_enetaddr, 6)) {\r
+ g_net.got_packet_4me=1;\r
+ g_net.dataLen=len;\r
+ } else {\r
+ g_net.got_packet_4me=0;\r
+ return;\r
+ }\r
+ \r
+ if(1) {\r
+ g_net.srvAddrRecv.sin_port = ntohs(*((unsigned short *)(g_net.data + ETHER_HDR_SIZE + IP_HDR_SIZE_NO_UDP + g_net.align_offset)));\r
+ NetCopyIP(&g_net.srvAddrRecv.sin_addr, g_net.data + ETHER_HDR_SIZE + g_net.align_offset + 12);\r
+ memcpy(NetServerEther, g_net.data + g_net.align_offset +6, 6); \r
+\r
+ #if 0\r
+ printf("received packet: buffer 0x%08X Laenge %d \n", (unsigned long) pkt, len);\r
+ printf("from ");\r
+ print_IPaddr(g_net.srvAddrRecv.sin_addr);\r
+ printf(", port: %d\n", g_net.srvAddrRecv.sin_port); \r
+ \r
+ \r
+ \r
+ ce_dump_block(pkt, len);\r
+ \r
+ printf("Headers:\n");\r
+ ce_dump_block(pkt - ETHER_HDR_SIZE - IP_HDR_SIZE, ETHER_HDR_SIZE + IP_HDR_SIZE);\r
+ printf("\n\nmy port should be: %d\n", ntohs(*((unsigned short *)(g_net.data + ETHER_HDR_SIZE + IP_HDR_SIZE_NO_UDP + g_net.align_offset +2))));\r
+ #endif\r
+ }\r
+\r
+}
+\r
+\r
+\r
+/* returns packet lengt if successfull */\r
+int ce_recv_packet(char *buf, int len, struct sockaddr_in *from, struct sockaddr_in *local, struct timeval *timeout){\r
+\r
+ int rxlength;\r
+ ulong time_started;\r
+ \r
+
+
+ g_net.got_packet_4me=0;
+ time_started = get_timer(0);
+
+ \r
+ NetRxPackets[0] = (uchar *)buf;\r
+ NetSetHandler(wince_handler);\r
+ \r
+ while(1) {\r
+ rxlength=eth_rx();\r
+ if(g_net.got_packet_4me)\r
+ return g_net.dataLen;\r
+ /* check for timeout */
+ if (get_timer(time_started) > timeout->tv_sec * CFG_HZ) {
+ return -1;
+ }
+ }\r
+}\r
+\r
+\r
+\r
+int ce_recv_frame(ce_net* net, int timeout)\r
+{\r
+ struct timeval timeo;\r
+\r
+ // Setup timeout\r
+\r
+ timeo.tv_sec = timeout;\r
+ timeo.tv_usec = 0;\r
+\r
+ /* Receive UDP packet */\r
+ \r
+ net->dataLen = ce_recv_packet(net->data+net->align_offset, sizeof(net->data)-net->align_offset, &net->srvAddrRecv, &net->locAddr, &timeo);\r
+ \r
+ if (net->dataLen < 0)\r
+ {\r
+ /* Error! No data available */\r
+ \r
+ net->dataLen = 0;\r
+ }\r
+ \r
+ return net->dataLen;\r
+}\r
+\r
+int ce_process_download(ce_net* net, ce_bin* bin)\r
+{\r
+ int ret = CE_PR_MORE;\r
+ \r
+ if (net->dataLen >= 2)\r
+ {\r
+ unsigned short command;\r
+ \r
+ command = ntohs(*(unsigned short*)(net->data+CE_DOFFSET));\r
+ \r
+ #ifdef DEBUG\r
+ printf("command found: 0x%04X\n", command);\r
+ #endif\r
+ \r
+ switch (command)\r
+ {\r
+ case EDBG_CMD_WRITE_REQ:\r
+ \r
+ if (!net->link)\r
+ {\r
+ // Check file name for WRITE request\r
+ // CE EShell uses "boot.bin" file name\r
+\r
+ /*printf(">>>>>>>> First Frame, IP: %s, port: %d\n",\r
+ inet_ntoa((in_addr_t *)&net->srvAddrRecv),\r
+ net->srvAddrRecv.sin_port);*/\r
+\r
+ if (strncmp((char*)(net->data +CE_DOFFSET + 2), "boot.bin", 8) == 0)\r
+ {\r
+ // Some diag output\r
+\r
+ if (net->verbose)\r
+ {\r
+ printf("Locked Down download link, IP: ");\r
+ print_IPaddr(net->srvAddrRecv.sin_addr);\r
+ printf(", port: %d\n", net->srvAddrRecv.sin_port); \r
+ }\r
+\r
+\r
+\r
+\r
+ if (net->verbose)\r
+ {\r
+ printf("Sending BOOTME request [%d] to ", (int)net->secNum);\r
+ print_IPaddr(net->srvAddrSend.sin_addr);\r
+ printf("\n");\r
+ }\r
+\r
+\r
+\r
+\r
+ // Lock down EShell download link\r
+\r
+ net->locAddr.sin_port = (EDBG_DOWNLOAD_PORT + 1);\r
+ net->srvAddrSend.sin_port = net->srvAddrRecv.sin_port;\r
+ net->srvAddrSend.sin_addr = net->srvAddrRecv.sin_addr;\r
+ net->link = 1; \r
+ }\r
+ else\r
+ {\r
+ // Unknown link\r
+\r
+ net->srvAddrRecv.sin_port = 0;\r
+ } \r
+\r
+ // Return write ack\r
+\r
+ if (net->link)\r
+ {\r
+ ce_send_write_ack(net);\r
+ }\r
+\r
+ break;\r
+ }\r
+\r
+ case EDBG_CMD_WRITE:\r
+\r
+ /* Fix data len */\r
+ bin->dataLen = net->dataLen - 4;\r
+\r
+ // Parse next block of .bin file\r
+\r
+ ret = ce_parse_bin(bin);\r
+\r
+ // Request next block\r
+\r
+ if (ret != CE_PR_ERROR)\r
+ {\r
+ net->blockNum ++;\r
+\r
+ ce_send_write_ack(net);\r
+ }\r
+\r
+ break;\r
+\r
+ case EDBG_CMD_READ_REQ:\r
+\r
+ // Read requests are not supported\r
+ // Do nothing ...\r
+ \r
+ break;\r
+\r
+ case EDBG_CMD_ERROR:\r
+\r
+ // Error condition on the host side\r
+\r
+ printf("Error: unknown error on the host side\n");\r
+\r
+ bin->binLen = 0;\r
+ ret = CE_PR_ERROR;\r
+\r
+ break;\r
+ default:\r
+ printf("unknown command 0x%04X ????\n", command);\r
+ while(1);\r
+ }\r
+ \r
+ \r
+ }\r
+\r
+ return ret;\r
+}\r
+\r
+\r
+\r
+void ce_init_edbg_link(ce_net* net)\r
+{\r
+ /* Initialize EDBG link for commands */\r
+ \r
+ net->locAddr.sin_port = EDBG_DOWNLOAD_PORT;\r
+ net->srvAddrSend.sin_port = EDBG_DOWNLOAD_PORT;\r
+ net->srvAddrRecv.sin_port = 0;\r
+ net->link = 0;\r
+}\r
+\r
+void ce_process_edbg(ce_net* net, ce_bin* bin)\r
+{\r
+ eth_dbg_hdr* header;\r
+\r
+\r
+\r
+ if (net->dataLen < sizeof(eth_dbg_hdr))\r
+ {\r
+ /* Bad packet */\r
+ \r
+ net->srvAddrRecv.sin_port = 0;\r
+ return;\r
+ }\r
+ \r
+ header = (eth_dbg_hdr*)(net->data + net->align_offset + ETHER_HDR_SIZE + IP_HDR_SIZE);\r
+\r
+ if (header->id != EDBG_ID)\r
+ {\r
+ /* Bad packet */\r
+\r
+ net->srvAddrRecv.sin_port = 0;\r
+ return;\r
+ }\r
+\r
+ if (header->service != EDBG_SVC_ADMIN)\r
+ {\r
+ /* Unknown service */\r
+ \r
+ return;\r
+ }\r
+\r
+ if (!net->link)\r
+ {\r
+ /* Some diag output */\r
+ \r
+ if (net->verbose)\r
+ {\r
+ printf("Locked Down EDBG service link, IP: ");\r
+ print_IPaddr(net->srvAddrRecv.sin_addr);\r
+ printf(", port: %d\n", net->srvAddrRecv.sin_port);\r
+ }\r
+ \r
+ /* Lock down EDBG link */\r
+\r
+ net->srvAddrSend.sin_port = net->srvAddrRecv.sin_port;\r
+ net->link = 1; \r
+ }\r
+\r
+ switch (header->cmd)\r
+ {\r
+ case EDBG_CMD_JUMPIMG:\r
+\r
+ net->gotJumpingRequest = 1;\r
+\r
+ if (net->verbose)\r
+ {\r
+ printf("Received JUMPING command\n");\r
+ }\r
+ \r
+ /* Just pass through and copy CONFIG structure */ \r
+\r
+ case EDBG_CMD_OS_CONFIG:\r
+\r
+ /* Copy config structure */\r
+\r
+ memcpy(&bin->edbgConfig, header->data, sizeof(edbg_os_config_data));\r
+\r
+ if (net->verbose)\r
+ {\r
+ printf("Received CONFIG command\n");\r
+\r
+ if (bin->edbgConfig.flags & EDBG_FL_DBGMSG)\r
+ {\r
+ printf("--> Enabling DBGMSG service, IP: %d.%d.%d.%d, port: %d\n",\r
+ (bin->edbgConfig.dbgMsgIPAddr >> 0) & 0xFF,\r
+ (bin->edbgConfig.dbgMsgIPAddr >> 8) & 0xFF,\r
+ (bin->edbgConfig.dbgMsgIPAddr >> 16) & 0xFF,\r
+ (bin->edbgConfig.dbgMsgIPAddr >> 24) & 0xFF,\r
+ (int)bin->edbgConfig.dbgMsgPort);\r
+ }\r
+\r
+ if (bin->edbgConfig.flags & EDBG_FL_PPSH)\r
+ {\r
+ printf("--> Enabling PPSH service, IP: %d.%d.%d.%d, port: %d\n",\r
+ (bin->edbgConfig.ppshIPAddr >> 0) & 0xFF,\r
+ (bin->edbgConfig.ppshIPAddr >> 8) & 0xFF,\r
+ (bin->edbgConfig.ppshIPAddr >> 16) & 0xFF,\r
+ (bin->edbgConfig.ppshIPAddr >> 24) & 0xFF,\r
+ (int)bin->edbgConfig.ppshPort);\r
+ }\r
+\r
+ if (bin->edbgConfig.flags & EDBG_FL_KDBG)\r
+ {\r
+ printf("--> Enabling KDBG service, IP: %d.%d.%d.%d, port: %d\n",\r
+ (bin->edbgConfig.kdbgIPAddr >> 0) & 0xFF,\r
+ (bin->edbgConfig.kdbgIPAddr >> 8) & 0xFF,\r
+ (bin->edbgConfig.kdbgIPAddr >> 16) & 0xFF,\r
+ (bin->edbgConfig.kdbgIPAddr >> 24) & 0xFF,\r
+ (int)bin->edbgConfig.kdbgPort);\r
+ }\r
+\r
+ if (bin->edbgConfig.flags & EDBG_FL_CLEANBOOT)\r
+ {\r
+ printf("--> Force clean boot\n");\r
+ }\r
+ }\r
+\r
+ break;\r
+\r
+ default:\r
+ if (net->verbose) {\r
+ printf("Received unknown command: %08X\n", header->cmd);\r
+ }\r
+ return;\r
+ }\r
+\r
+ /* Respond with ack */\r
+ header->flags = EDBG_FL_FROM_DEV | EDBG_FL_ACK;\r
+ net->dataLen = EDBG_DATA_OFFSET;\r
+ ce_send_frame(net); \r
+}\r
+\r
+int ce_send_write_ack(ce_net* net)\r
+{\r
+ unsigned short* wdata;\r
+ unsigned long aligned_address; \r
+\r
+ aligned_address=(unsigned long)net->data+ETHER_HDR_SIZE+IP_HDR_SIZE+net->align_offset;\r
+\r
+ wdata = (unsigned short*)aligned_address;\r
+ wdata[ 0 ] = htons(EDBG_CMD_WRITE_ACK);\r
+ wdata[ 1 ] = htons(net->blockNum);\r
+\r
+ net->dataLen = 4;\r
+ \r
+ return ce_send_frame(net);\r
+}\r
+\r
+\r
+\r
+int ce_send_frame(ce_net* net)\r
+{\r
+ /* Send UDP packet */\r
+ NetTxPacket = (uchar *)net->data + net->align_offset;\r
+ return NetSendUDPPacket(NetServerEther, net->srvAddrSend.sin_addr, (int)net->srvAddrSend.sin_port, (int)net->locAddr.sin_port, net->dataLen);\r
+}\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+int ce_send_bootme(ce_net* net)\r
+{\r
+ eth_dbg_hdr* header;\r
+ edbg_bootme_data* data;\r
+\r
+ char *e, *s;\r
+ int i;\r
+ unsigned char tmp[64];\r
+ unsigned char *macp;\r
+\r
+ #ifdef DEBUG\r
+ char *pkt;\r
+ #endif\r
+\r
+\r
+ /* Fill out BOOTME packet */\r
+ memset(net->data, 0, PKTSIZE);\r
+ header = (eth_dbg_hdr*)(net->data +CE_DOFFSET); \r
+ data = (edbg_bootme_data*)header->data;\r
+\r
+ header->id=EDBG_ID;\r
+ header->service = EDBG_SVC_ADMIN;\r
+ header->flags = EDBG_FL_FROM_DEV;\r
+ header->seqNum = net->secNum ++;\r
+ header->cmd = EDBG_CMD_BOOTME;\r
+\r
+ data->versionMajor = 0; \r
+ data->versionMinor = 0; \r
+ data->cpuId = EDBG_CPU_TYPE_ARM;\r
+ data->bootmeVer = EDBG_CURRENT_BOOTME_VERSION;\r
+ data->bootFlags = 0;\r
+ data->downloadPort = 0;\r
+ data->svcPort = 0;\r
+\r
+ macp=(unsigned char *)data->macAddr;\r
+ /* MAC address from environment*/\r
+ i = getenv_r ("ethaddr", tmp, sizeof (tmp));
+ s = (i > 0) ? tmp : 0;
+ for (i = 0; i < 6; ++i) {
+ macp[i] = s ? simple_strtoul (s, &e, 16) : 0;
+ if (s)
+ s = (*e) ? e + 1 : e;
+ }\r
+\r
+ /* IP address from environment */ \r
+ data->ipAddr = (unsigned int)getenv_IPaddr("ipaddr");\r
+\r
+ // Device name string (NULL terminated). Should include\r
+ // platform and number based on Ether address (e.g. Odo42, CEPCLS2346, etc)\r
+\r
+ // We will use lower MAC address segment to create device name\r
+ // eg. MAC '00-0C-C6-69-09-05', device name 'Triton05'\r
+\r
+ strcpy(data->platformId, "Triton");\r
+ sprintf(data->deviceName, "%s%02X", data->platformId, macp[5]);\r
+\r
+\r
+#ifdef DEBUG\r
+\r
+ printf("header->id: %08X\r\n", header->id);\r
+ printf("header->service: %08X\r\n", header->service);\r
+ printf("header->flags: %08X\r\n", header->flags);\r
+ printf("header->seqNum: %08X\r\n", header->seqNum);\r
+ printf("header->cmd: %08X\r\n\r\n", header->cmd);\r
+ \r
+ printf("data->versionMajor: %08X\r\n", data->versionMajor);\r
+ printf("data->versionMinor: %08X\r\n", data->versionMinor);\r
+ printf("data->cpuId: %08X\r\n", data->cpuId);\r
+ printf("data->bootmeVer: %08X\r\n", data->bootmeVer);\r
+ printf("data->bootFlags: %08X\r\n", data->bootFlags);\r
+ printf("data->svcPort: %08X\r\n\r\n", data->svcPort);\r
+\r
+ printf("data->macAddr: %02X-%02X-%02X-%02X-%02X-%02X\r\n",\r
+ (data->macAddr[0] >> 0) & 0xFF,\r
+ (data->macAddr[0] >> 8) & 0xFF,\r
+ (data->macAddr[1] >> 0) & 0xFF,\r
+ (data->macAddr[1] >> 8) & 0xFF,\r
+ (data->macAddr[2] >> 0) & 0xFF,\r
+ (data->macAddr[2] >> 8) & 0xFF);\r
+\r
+ printf("data->ipAddr: %d.%d.%d.%d\r\n",\r
+ (data->ipAddr >> 0) & 0xFF,\r
+ (data->ipAddr >> 8) & 0xFF,\r
+ (data->ipAddr >> 16) & 0xFF,\r
+ (data->ipAddr >> 24) & 0xFF);\r
+\r
+ printf("data->platformId: %s\r\n", data->platformId);\r
+\r
+ printf("data->deviceName: %s\r\n", data->deviceName);\r
+\r
+#endif\r
+ \r
+\r
+ // Some diag output ...\r
+\r
+ if (net->verbose)\r
+ {\r
+ printf("Sending BOOTME request [%d] to ", (int)net->secNum);\r
+ print_IPaddr(net->srvAddrSend.sin_addr);\r
+ printf("\n");\r
+ }\r
+ \r
+ // Send packet\r
+\r
+ net->dataLen = BOOTME_PKT_SIZE;\r
+\r
+\r
+ #ifdef DEBUG\r
+ printf("\n\n\nStart of buffer: 0x%08X\n", (unsigned long)net->data);\r
+ printf("Start of ethernet buffer: 0x%08X\n", (unsigned long)net->data+net->align_offset);\r
+ printf("Start of CE header: 0x%08X\n", (unsigned long)header);\r
+ printf("Start of CE data: 0x%08X\n", (unsigned long)data);\r
+ \r
+ pkt = (uchar *)net->data+net->align_offset;
+ printf("\n\npacket to send (ceconnect): \n");
+ for(i=0; i<(net->dataLen+ETHER_HDR_SIZE+IP_HDR_SIZE); i++) {
+ printf("0x%02X ", pkt[i]);
+ if(!((i+1)%16))
+ printf("\n");
+ }
+ printf("\n\n");
+ #endif\r
+\r
+ memcpy(NetServerEther, NetBcastAddr, 6);\r
+\r
+ return ce_send_frame(net); \r
+}\r
+\r
+\r
+\r
+void ce_dump_block(unsigned char *ptr, int length) {\r
+ \r
+ int i;\r
+ int j;\r
+ \r
+ for(i=0; i<length; i++) {\r
+ if(!(i%16)) {\r
+ printf("\n0x%08X: ", (unsigned long)ptr + i);\r
+ }\r
+\r
+ printf("0x%02X ", ptr[i]);\r
+ \r
+ if(!((i+1)%16)){\r
+ printf(" ");\r
+ for(j=i-15; j<i; j++){\r
+ if((ptr[j]>0x1f) && (ptr[j]<0x7f)) {\r
+ printf("%c", ptr[j]);\r
+ } else {\r
+ printf(".");\r
+ }\r
+ }\r
+ } \r
+ \r
+ }\r
+ \r
+ printf("\n\n");\r
+}\r
+ \r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+void ce_init_download_link(ce_net* net, ce_bin* bin, struct sockaddr_in* host_addr, int verbose)\r
+{\r
+ unsigned long aligned_address;\r
+ /* Initialize EDBG link for download */\r
+\r
+\r
+ memset(net, 0, sizeof(ce_net));\r
+\r
+ /* our buffer contains space for ethernet- ip- and udp- headers */\r
+ /* calucalate an offset that our ce field is aligned to 4 bytes */\r
+ aligned_address=(unsigned long)net->data; /* this is the start of our physical buffer */\r
+ aligned_address += (ETHER_HDR_SIZE+IP_HDR_SIZE); /* we need 42 bytes room for headers (14 Ethernet , 20 IPv4, 8 UDP) */\r
+ net->align_offset = 4-(aligned_address%4); /* want CE header aligned to 4 Byte boundary */ \r
+ if(net->align_offset == 4) {\r
+ net->align_offset=0;\r
+ }\r
+ \r
+ net->locAddr.sin_family = AF_INET;\r
+ net->locAddr.sin_addr = getenv_IPaddr("ipaddr");\r
+ net->locAddr.sin_port = EDBG_DOWNLOAD_PORT;\r
+\r
+ net->srvAddrSend.sin_family = AF_INET;\r
+ net->srvAddrSend.sin_port = EDBG_DOWNLOAD_PORT;\r
+\r
+ net->srvAddrRecv.sin_family = AF_INET;\r
+ net->srvAddrRecv.sin_port = 0; \r
+\r
+ if (host_addr->sin_addr)\r
+ {\r
+ /* Use specified host address ... */\r
+\r
+ net->srvAddrSend.sin_addr = host_addr->sin_addr;\r
+ net->srvAddrRecv.sin_addr = host_addr->sin_addr; \r
+ }\r
+ else\r
+ {\r
+ /* ... or use default server address */\r
+ \r
+ net->srvAddrSend.sin_addr = getenv_IPaddr("serverip");\r
+ net->srvAddrRecv.sin_addr = getenv_IPaddr("serverip");\r
+ }\r
+\r
+ net->verbose = verbose;\r
+ /* Initialize .BIN parser */\r
+ ce_init_bin(bin, net->data + CE_DOFFSET + 4);\r
+ \r
+
+ \r
+ eth_halt();\r
+
+#ifdef CONFIG_NET_MULTI
+ eth_set_current();
+#endif
+ if (eth_init(gd->bd) < 0) {\r
+ #ifdef ET_DEBUG\r
+ puts("ceconnect: failed to init ethernet !\n");\r
+ #endif
+ eth_halt();
+ return;
+ }
+ #ifdef ET_DEBUG\r
+ puts("ceconnect: init ethernet done!\n");\r
+ #endif
+\r
+\r
+ memcpy (NetOurEther, gd->bd->bi_enetaddr, 6); \r
+ NetCopyIP(&NetOurIP, &gd->bd->bi_ip_addr);
+ NetOurGatewayIP = getenv_IPaddr ("gatewayip");
+ NetOurSubnetMask= getenv_IPaddr ("netmask");
+ NetServerIP = getenv_IPaddr ("serverip");\r
+\r
+}\r
+\r
+\r
+int ce_load(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])\r
+{\r
+ int i;\r
+ int verbose, use_timeout;\r
+ int timeout, recv_timeout, ret;\r
+ struct sockaddr_in host_ip_addr;\r
+\r
+ // -v verbose\r
+\r
+ verbose = 0;\r
+ use_timeout = 0;\r
+ timeout = 0;\r
+ \r
+\r
+ for(i=0;i<argc;i++){\r
+ if (strcmp(argv[i+1], "-v") == 0){ \r
+ verbose = 1;\r
+ }\r
+ }\r
+\r
+\r
+ for(i=0;i<(argc-1);i++){\r
+ if (strcmp(argv[i+1], "-t") == 0){ \r
+ use_timeout = 1;\r
+ timeout = simple_strtoul(argv[i+2], NULL, 10);\r
+ }\r
+ }\r
+\r
+ #ifdef DEBUG\r
+ printf("verbose=%d, use_timeout=%d, timeout=%d\n", verbose, use_timeout, timeout);\r
+ #endif\r
+\r
+ // Check host IP address (if specified)\r
+\r
+ *((unsigned int *)&host_ip_addr) = 0xFFFFFFFF;\r
+ \r
+\r
+ // Initialize download link\r
+\r
+ ce_init_download_link(&g_net, &g_bin, &host_ip_addr, verbose);\r
+\r
+ // Download loop\r
+\r
+ while (1)\r
+ {\r
+ if (g_net.link)\r
+ {\r
+ recv_timeout = 3; \r
+ }\r
+ else\r
+ {\r
+ recv_timeout = 1; \r
+ \r
+ if (use_timeout)\r
+ {\r
+ if (timeout <= 0)\r
+ {\r
+ printf("CELOAD - Canceled, timeout\n");\r
+ eth_halt();\r
+ return 1;\r
+ }\r
+ } else {\r
+ /* Try to catch ^C */\r
+ #ifdef DEBUG\r
+ puts("try to catch ^C\n");\r
+ #endif \r
+ if (ctrlc())\r
+ {\r
+ printf("CELOAD - canceled by user\n");\r
+ eth_halt();\r
+ return 1;\r
+ }\r
+ }\r
+ #ifdef DEBUG\r
+ puts("sending broadcast frame bootme\n");\r
+ #endif \r
+\r
+ if (ce_send_bootme(&g_net))\r
+ {\r
+ printf("CELOAD - error while sending BOOTME request\n");\r
+ eth_halt();\r
+ return 1;\r
+ }\r
+ printf("net state is: %d\n", NetState);\r
+ if (verbose)\r
+ {\r
+ if (use_timeout)\r
+ {\r
+ printf("Waiting for connection, timeout %d sec\n", timeout);\r
+ }\r
+ else\r
+ {\r
+ printf("Waiting for connection, enter ^C to abort\n");\r
+ }\r
+ }\r
+ }\r
+\r
+ // Try to receive frame\r
+\r
+ if (ce_recv_frame(&g_net, recv_timeout))\r
+ {\r
+ // Process received data\r
+ \r
+ ret = ce_process_download(&g_net, &g_bin);\r
+\r
+ if (ret != CE_PR_MORE)\r
+ {\r
+ break;\r
+ } \r
+ }\r
+ else if (use_timeout)\r
+ {\r
+ timeout -= recv_timeout;\r
+ }\r
+ }\r
+\r
+ if (g_bin.binLen)\r
+ {\r
+ // Try to receive edbg commands from host\r
+\r
+ ce_init_edbg_link(&g_net);\r
+\r
+ if (verbose)\r
+ {\r
+ printf("Waiting for EDBG commands ...\n");\r
+ }\r
+ \r
+ while (ce_recv_frame(&g_net, 3))\r
+ {\r
+ ce_process_edbg(&g_net, &g_bin);\r
+ }\r
+\r
+ // Prepare WinCE image for execution\r
+\r
+ ce_prepare_run_bin(&g_bin);\r
+\r
+ // Launch WinCE, if necessary\r
+ \r
+ if (g_net.gotJumpingRequest)\r
+ {\r
+ ce_run_bin(&g_bin);\r
+ } \r
+ }\r
+ eth_halt();\r
+ return 0;\r
+}\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+U_BOOT_CMD(
+ ceconnect, 2, 1, ce_load,
+ "ceconnect - Set up a connection to the CE host PC over TCP/IP and download the run-time image\n",
+ "ceconnect [-v] [-t <timeout>]\n"
+ " -v verbose operation\n"
+ " -t <timeout> - max wait time (#sec) for the connection\n"
+);
+\r
+#endif\r
+\r
+/* CFG_CMD_WINCE */\r
if ((part = jffs2_part_info(current_dev, current_partnum))){
/* check partition type for cramfs */
+#ifdef CFG_FS_CRAMFS
fsname = (cramfs_check(part) ? "CRAMFS" : "JFFS2");
printf("### %s loading '%s' to 0x%lx\n", fsname, filename, offset);
-
if (cramfs_check(part)) {
size = cramfs_load ((char *) offset, part, filename);
} else {
/* if this is not cramfs assume jffs2 */
size = jffs2_1pass_load((char *)offset, part, filename);
}
+#else
+ fsname = "JFFS2";
+ printf("### %s loading '%s' to 0x%lx\n", fsname, filename, offset);
+ size = jffs2_1pass_load((char *)offset, part, filename);
+#endif
if (size > 0) {
char buf[10];
if ((part = jffs2_part_info(current_dev, current_partnum))){
/* check partition type for cramfs */
+#ifdef CFG_FS_CRAMFS
if (cramfs_check(part)) {
ret = cramfs_ls (part, filename);
} else {
/* if this is not cramfs assume jffs2 */
ret = jffs2_1pass_ls(part, filename);
}
+#else
+ ret = jffs2_1pass_ls(part, filename);
+#endif
return ret ? 0 : 1;
}
if ((part = jffs2_part_info(current_dev, current_partnum))){
/* check partition type for cramfs */
+#ifdef CFG_FS_CRAMFS
fsname = (cramfs_check(part) ? "CRAMFS" : "JFFS2");
printf("### filesystem type is %s\n", fsname);
/* if this is not cramfs assume jffs2 */
ret = jffs2_1pass_info(part);
}
-
+#else
+ fsname = "JFFS2";
+ printf("### filesystem type is %s\n", fsname);
+ ret = jffs2_1pass_info(part);
+#endif
return ret ? 0 : 1;
}
return 1;
/* set clock speed */
#ifdef CONFIG_CPU_MONAHANS
ldr r0, =ACCR
+ /* KaRo: do not clear other clock fields, otherwise boards still running in SDRAM will crash here */
+ ldr r2, =~(ACCR_XN_MASK | ACCR_XL_MASK)
+ ldr r1, [r0]
+ and r2, r2, r1
ldr r1, =(((CFG_MONAHANS_TURBO_RUN_MODE_RATIO<<8) & ACCR_XN_MASK) | (CFG_MONAHANS_RUN_MODE_OSC_RATIO & ACCR_XL_MASK))
- str r1, [r0]
+ orr r2, r2, r1
+ str r2, [r0]
#else /* ! CONFIG_CPU_MONAHANS */
#ifdef CFG_CPUSPEED
ldr r0, CC_BASE
DM9000_iow(DM9000_ISR, 0x0f); /* Clear interrupt status */
/* Set Node address */
+#ifndef CONFIG_USE_MAC_FROM_ENV
for (i = 0; i < 6; i++)
((u16 *) bd->bi_enetaddr)[i] = read_srom_word(i);
+#endif
printf("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", bd->bi_enetaddr[0],
bd->bi_enetaddr[1], bd->bi_enetaddr[2], bd->bi_enetaddr[3],
bd->bi_enetaddr[4], bd->bi_enetaddr[5]);
*
* History:
* $Log$
- * Revision 1.1 2007-03-09 09:43:58 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:01:39 lothar
+ * imported KARO specific modifications
*
* Revision 1.4 2002/04/25 11:04:10 rschmidt
* Editorial changes
* History:
*
* $Log$
- * Revision 1.1 2007-03-09 09:43:58 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:01:39 lothar
+ * imported KARO specific modifications
*
* Revision 1.26 2002/11/15 07:24:42 tschilli
* SK_ADDR_EQUAL macro fixed.
* History:
*
* $Log$
- * Revision 1.1 2007-03-09 09:43:58 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:01:39 lothar
+ * imported KARO specific modifications
*
* Revision 1.9 2001/02/06 11:21:39 rassmann
* Editorial changes.
*
* History:
* $Log$
- * Revision 1.1 2007-03-09 09:43:58 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:01:39 lothar
+ * imported KARO specific modifications
*
* Revision 1.12 2002/07/15 15:37:13 rschmidt
* Power Management support
* History:
*
* $Log$
- * Revision 1.1 2007-03-09 09:43:58 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:01:40 lothar
+ * imported KARO specific modifications
*
* Revision 1.11 2003/02/25 14:16:40 mlindner
* Fix: Copyright statement
* History:
*
* $Log$
- * Revision 1.1 2007-03-09 09:43:58 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:01:40 lothar
+ * imported KARO specific modifications
*
* Revision 1.15 2003/02/25 14:16:40 mlindner
* Fix: Copyright statement
*
* History:
* $Log$
- * Revision 1.1 2007-03-09 09:43:58 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:01:40 lothar
+ * imported KARO specific modifications
*
* Revision 1.5 2002/04/25 11:05:10 rschmidt
* Editorial changes
* History:
*
* $Log$
- * Revision 1.1 2007-03-09 09:43:58 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:01:40 lothar
+ * imported KARO specific modifications
*
* Revision 1.6 2002/07/15 15:38:01 rschmidt
* Power Management support
*
* History:
* $Log$
- * Revision 1.1 2007-03-09 09:43:58 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:01:40 lothar
+ * imported KARO specific modifications
*
* Revision 1.49 2003/01/28 09:43:49 rschmidt
* Added defines for PCI-Spec. 2.3 IRQ
* History:
*
* $Log$
- * Revision 1.1 2007-03-09 09:43:58 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:01:40 lothar
+ * imported KARO specific modifications
*
* Revision 1.5 1999/11/22 13:54:24 cgoos
* Changed license header to GPL.
* History:
*
* $Log$
- * Revision 1.1 2007-03-09 09:43:58 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:01:40 lothar
+ * imported KARO specific modifications
*
* Revision 1.23 2002/12/19 14:34:27 rschmidt
* Added cast in macros SK_I2C_SET_BIT() and SK_I2C_CLR_BIT()
* History:
*
* $Log$
- * Revision 1.1 2007-03-09 09:43:58 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:01:40 lothar
+ * imported KARO specific modifications
*
* Revision 1.75 2003/02/05 13:36:39 rschmidt
* Added define SK_FACT_78 for YUKON's Host Clock of 78.12 MHz
* History:
*
* $Log$
- * Revision 1.1 2007-03-09 09:43:58 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:01:40 lothar
+ * imported KARO specific modifications
*
* Revision 1.34 2002/12/16 09:05:18 tschilli
* Code for VCT handling added.
* History:
*
* $Log$
- * Revision 1.1 2007-03-09 09:43:58 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:01:40 lothar
+ * imported KARO specific modifications
*
* Revision 1.59 2002/12/16 14:03:50 tschilli
* New defines for VCT added.
*
* History:
* $Log$
- * Revision 1.1 2007-03-09 09:43:59 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:01:40 lothar
+ * imported KARO specific modifications
*
* Revision 1.26 2002/10/14 09:52:36 rschmidt
* Added SKERR_SIRQ_E023 and SKERR_SIRQ_E023 for GPHY (Yukon)
* History:
*
* $Log$
- * Revision 1.1 2007-03-09 09:43:59 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:01:40 lothar
+ * imported KARO specific modifications
*
* Revision 1.34 2003/01/28 09:11:21 rschmidt
* Editorial changes
* History:
*
* $Log$
- * Revision 1.1 2007-03-09 09:43:59 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:01:40 lothar
+ * imported KARO specific modifications
*
* Revision 1.14 2002/03/15 10:52:13 mkunz
* Added event classes for link aggregation
* History:
*
* $Log$
- * Revision 1.1 2007-03-09 09:43:59 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:01:41 lothar
+ * imported KARO specific modifications
*
* Revision 1.35 2003/01/31 14:12:41 mkunz
* single port adapter runs now with two identical MAC addresses
* History:
*
* $Log$
- * Revision 1.1 2007-03-09 09:43:59 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:01:41 lothar
+ * imported KARO specific modifications
*
* Revision 1.9 1999/11/22 14:00:29 cgoos
* Changed license header to GPL.
* History:
*
* $Log$
- * Revision 1.1 2007-03-09 09:43:59 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:01:41 lothar
+ * imported KARO specific modifications
*
* Revision 1.3 2003/02/25 14:16:40 mlindner
* Fix: Copyright statement
*
* History:
* $Log$
- * Revision 1.1 2007-03-09 09:43:59 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:01:41 lothar
+ * imported KARO specific modifications
*
* Revision 1.4 2003/02/25 14:16:40 mlindner
* Fix: Copyright statement
* History:
*
* $Log$
- * Revision 1.1 2007-03-09 09:43:59 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:01:41 lothar
+ * imported KARO specific modifications
*
* Revision 1.15 2003/01/13 10:39:38 rschmidt
* Replaced define for PCI device Id for YUKON with GENESIS
* History:
*
* $Log$
- * Revision 1.1 2007-03-09 09:43:59 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:01:41 lothar
+ * imported KARO specific modifications
*
* Revision 1.46 2003/01/28 09:47:45 rschmidt
* Added defines for copper MDI/MDIX configuration
* History:
*
* $Log$
- * Revision 1.1 2007-03-09 09:43:58 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:01:37 lothar
+ * imported KARO specific modifications
*
* Revision 1.48 2003/02/12 17:09:37 tschilli
* Fix in SkAddrOverride() to set both (physical and logical) MAC addresses
* History:
*
* $Log$
- * Revision 1.1 2007-03-09 09:43:58 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:01:37 lothar
+ * imported KARO specific modifications
*
* Revision 1.10 2002/04/11 10:02:04 rwahl
* Fix in SkCsGetSendInfo():
* History:
*
* $Log$
- * Revision 1.1 2007-03-09 09:43:58 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:01:37 lothar
+ * imported KARO specific modifications
*
* Revision 1.46 2003/02/25 14:16:36 mlindner
* Fix: Copyright statement
* History:
*
* $Log$
- * Revision 1.1 2007-03-09 09:43:58 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:01:37 lothar
+ * imported KARO specific modifications
*
* Revision 1.13 1999/11/22 13:31:12 cgoos
* Changed license header to GPL.
* History:
*
* $Log$
- * Revision 1.1 2007-03-09 09:43:58 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:01:37 lothar
+ * imported KARO specific modifications
*
* Revision 1.85 2003/02/05 15:30:33 rschmidt
* Corrected setting of GIHstClkFact (Host Clock Factor) and
* History:
*
* $Log$
- * Revision 1.1 2007-03-09 09:43:58 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:01:37 lothar
+ * imported KARO specific modifications
*
* Revision 1.7 2002/12/16 09:04:34 tschilli
* Code for VCT handling added.
* History:
*
* $Log$
- * Revision 1.1 2007-03-09 09:43:58 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:01:37 lothar
+ * imported KARO specific modifications
*
* Revision 1.102 2002/12/16 14:03:24 tschilli
* VCT code in Vct() changed.
* History:
*
* $Log$
- * Revision 1.1 2007-03-09 09:43:58 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:01:38 lothar
+ * imported KARO specific modifications
*
* Revision 1.83 2003/02/05 15:10:59 rschmidt
* Fixed setting of PLinkSpeedUsed in SkHWLinkUp() when
* History:
*
* $Log$
- * Revision 1.1 2007-03-09 09:43:58 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:01:38 lothar
+ * imported KARO specific modifications
*
* Revision 1.57 2003/01/28 09:17:38 rschmidt
* Fixed handling for sensors on YUKON Fiber.
* History:
*
* $Log$
- * Revision 1.1 2007-03-09 09:43:58 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:01:38 lothar
+ * imported KARO specific modifications
*
* Revision 1.20 2002/08/13 09:16:27 rschmidt
* Changed return value for SkLm80ReadSensor() back to 'int'
* History:
*
* $Log$
- * Revision 1.1 2007-03-09 09:43:58 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:01:38 lothar
+ * imported KARO specific modifications
*
* Revision 1.4 2003/02/25 14:16:37 mlindner
* Fix: Copyright statement
* History:
*
* $Log$
- * Revision 1.1 2007-03-09 09:43:58 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:01:38 lothar
+ * imported KARO specific modifications
*
* Revision 1.18 2002/05/07 14:11:11 rwahl
* Fixed Watcom Precompiler error.
* History:
*
* $Log$
- * Revision 1.1 2007-03-09 09:43:58 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:01:38 lothar
+ * imported KARO specific modifications
*
* Revision 1.68 2003/01/31 15:26:56 rschmidt
* Added init for local variables in RlmtInit().
* History:
*
* $Log$
- * Revision 1.1 2007-03-09 09:43:58 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:01:38 lothar
+ * imported KARO specific modifications
*
* Revision 1.12 1999/11/22 13:38:51 cgoos
* Changed license header to GPL.
* History:
*
* $Log$
- * Revision 1.1 2007-03-09 09:43:58 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:01:38 lothar
+ * imported KARO specific modifications
*
* Revision 1.37 2003/01/13 10:42:45 rschmidt
* Replaced check for PCI device Id from YUKON with GENESIS
* History:
*
* $Log$
- * Revision 1.1 2007-03-09 09:43:58 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:01:38 lothar
+ * imported KARO specific modifications
*
* Revision 1.91 2003/02/05 15:09:34 rschmidt
* Removed setting of 'Collision Test'-bit in SkGmInitPhyMarv().
endif
ifeq ($(ARCH),arm)
-LOAD_ADDR = 0xc100000
+LOAD_ADDR = 0x100000
endif
ifeq ($(ARCH),mips)
printf ("Example expects ABI version %d\n", XF_VERSION);
printf ("Actual U-Boot ABI version %d\n", (int)get_version());
- printf ("Hello World\n");
+ printf ("Hello World here is KaRo\n");
printf ("argc = %d\n", argc);
#include <common.h>
#include <malloc.h>
-#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+#if (CFG_FS_CRAMFS)
#include <asm/byteorder.h>
#include <linux/stat.h>
#include <watchdog.h>
#include <zlib.h>
-#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+#if (CFG_FS_CRAMFS)
static z_stream stream;
#define PAD_SCLK __REG_2(0x4810012C)
#define TAI __REG_2(0x48100F00) /* TAI Tavor Address Isolation Register */
+/* some CSADRCFG bits */
+#define CSADRCFG_INFTYPE_SyncDevice (0xe)
+#define CSADRCFG_INFTYPE_SyncFlash (0xd)
+#define CSADRCFG_INFTYPE_VLIO (0xb)
+#define CSADRCFG_INFTYPE_SRAM (0x9)
+
+#define CSADRCFG_INFTYPE_BASE0 (0<<4)
+#define CSADRCFG_INFTYPE_BASE1 (1<<4)
+#define CSADRCFG_INFTYPE_BASE2 (2<<4)
+#define CSADRCFG_INFTYPE_BASE3 (3<<4)
+
+#define CSADRCFG_Split16 (8<<8)
+#define CSADRCFG_Split17 (9<<8)
+
+#define CSADRCFG_AdrCfg_FullLatch (0<<14)
+#define CSADRCFG_AdrCfg_LowOrder (3<<14)
+
+#define CSADRCFG_ALW1 (1<<17)
+#define CSADRCFG_ALW2 (2<<17)
+#define CSADRCFG_ALW3 (3<<17)
+#define CSADRCFG_ALW4 (4<<17)
+#define CSADRCFG_ALW5 (5<<17)
+#define CSADRCFG_ALW6 (6<<17)
+#define CSADRCFG_ALW7 (7<<17)
+
+#define CSADRCFG_ALT_0S0H (0<<20)
+#define CSADRCFG_ALT_0S1H (1<<20)
+#define CSADRCFG_ALT_1S0H (2<<20)
+#define CSADRCFG_ALT_1S1H (3<<20)
+
/* Some frequently used bits */
#define MDCNFG_DMAP 0x80000000 /* SDRAM 1GB Memory Map Enable */
#define MDCNFG_DMCEN 0x40000000 /* Enable Dynamic Memory Controller */
* History:
*
* $Log$
- * Revision 1.1 2007-03-09 09:44:04 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:02:15 lothar
+ * imported KARO specific modifications
*
* Revision 1.3 2003/04/26 04:58:13 brad
* Cosmetic changes and compiler warning cleanups
*
*
* $Log$
- * Revision 1.1 2007-03-09 09:44:05 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:02:18 lothar
+ * imported KARO specific modifications
*
* Revision 1.21 2005/06/03 15:05:25 tsawyer
* MB rev 2.0.3 KA rev 0.0.7. Add CONFIG_VERSION_VARIABLE, Add fakeled to MB
*
* Last ChangeLog Entry
* $Log$
- * Revision 1.1 2007-03-09 09:44:07 lothar
- * Initial revision
+ * Revision 1.1.3.1 2007-05-22 17:02:25 lothar
+ * imported KARO specific modifications
*
* Revision 1.2 2005/02/21 12:48:58 mleeman
* update of copyright years (feedback wd)
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Configuation settings for the TRITON320 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */
+#define CONFIG_TRITON320 1 /* Zylonite board */
+
+/* #define CONFIG_LCD 1 */
+#ifdef CONFIG_LCD
+#define CONFIG_SHARP_LM8V31
+#endif
+/* #define CONFIG_MMC 1 */
+#define BOARD_LATE_INIT 1
+
+#define CONFIG_SKIP_RELOCATE_UBOOT 1
+#undef CONFIG_SKIP_LOWLEVEL_INIT
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 256*1024)
+#define CFG_GBL_DATA_SIZE 512 /* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+
+#define CONFIG_DRIVER_DM9000 1
+#define CONFIG_DM9000_BASE 0x10000300
+#define DM9000_IO CONFIG_DM9000_BASE
+#define DM9000_DATA (CONFIG_DM9000_BASE+0x8000)
+#define CONFIG_DM9000_USE_16BIT
+
+
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_FFUART 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE 38400
+
+#if 0
+# define CONFIG_COMMANDS CFG_CMD_AUTOSCRIPT \
+ | CFG_CMD_BDI \
+ | CFG_CMD_BOOTD \
+ | CFG_CMD_CONSOLE \
+ | CFG_CMD_ECHO \
+ | CFG_CMD_ENV \
+ | CFG_CMD_IMI \
+ | CFG_CMD_ITEST \
+ | CFG_CMD_LOADB \
+ | CFG_CMD_LOADS \
+ | CFG_CMD_MEMORY \
+ | CFG_CMD_NAND \
+ | CFG_CMD_REGINFO \
+ | CFG_CMD_RUN \
+ & ~(CFG_CMD_JFFS2 | CFG_CMD_FLASH | CFG_CMD_IMLS)
+#endif
+
+#define CONFIG_COMMANDS ((CONFIG_CMD_DFL| \
+ CFG_CMD_NAND | \
+ CFG_CMD_JFFS2 | \
+ CFG_CMD_PING | \
+ CFG_CMD_DHCP) & \
+ ~(CFG_CMD_FLASH | \
+ CFG_CMD_IMLS))
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTCOMMAND "bootm 80000"
+#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rootfstype=jffs2 console=ttyS0,38400"
+#define CONFIG_BOOT_RETRY_TIME -1
+#define CONFIG_BOOT_RETRY_MIN 60
+#define CONFIG_RESET_TO_RETRY
+#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
+#define CONFIG_AUTOBOOT_DELAY_STR " "
+#define CONFIG_AUTOBOOT_STOP_STR "system"
+
+#define CONFIG_ETHADDR ff:ff:ff:ff:ff:ff
+#define CONFIG_NETMASK 255.255.255.255
+#define CONFIG_IPADDR 0.0.0.0
+#define CONFIG_SERVERIP 0.0.0.0
+#define CONFIG_CMDLINE_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_TIMESTAMP
+#define CONFIG_USE_MAC_FROM_ENV
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_HUSH_PARSER 1
+#define CFG_PROMPT_HUSH_PS2 "> "
+
+#define CFG_LONGHELP /* undef to save memory */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT "$ " /* Monitor Command Prompt */
+#else
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#endif
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_DEVICE_NULLDEV 1
+
+#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CFG_HZ 3250000 /* incrementer freq: 3.25 MHz */
+
+/* Monahans Core Frequency */
+#define CFG_MONAHANS_RUN_MODE_OSC_RATIO 31 /* valid values: 8, 16, 24, 31 */
+#define CFG_MONAHANS_TURBO_RUN_MODE_RATIO 2 /* valid values: 1, 2 */
+
+ /* valid baudrates */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/* #define CFG_MMC_BASE 0xF0000000 */
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks of DRAM */
+#define PHYS_SDRAM_1 0x80000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
+
+#define CFG_DRAM_BASE PHYS_SDRAM_1
+#define CFG_DRAM_SIZE PHYS_SDRAM_1_SIZE
+
+
+#define CFG_LOAD_ADDR (PHYS_SDRAM_1 + 0x100000) /* default load address */
+
+#define CFG_SKIP_DRAM_SCRUB
+
+/*
+ * NAND Flash
+ */
+/* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */
+#define CONFIG_NEW_NAND_CODE
+#define CFG_NAND0_BASE 0x0
+#undef CFG_NAND1_BASE
+
+#define CONFIG_MTD_NAND_ECC_JFFS2 1
+
+#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE }
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+
+/* nand timeout values */
+#define CFG_NAND_PROG_ERASE_TO 9000
+#define CFG_NAND_OTHER_TO 2000
+#define CFG_NAND_SENDCMD_RETRY 3
+#undef NAND_ALLOW_ERASE_ALL /* Allow erasing bad blocks - don't use */
+
+/* NAND Timing Parameters (in ns) */
+#define NAND_TIMING_tCH 10
+#define NAND_TIMING_tCS 0
+#define NAND_TIMING_tWH 20
+#define NAND_TIMING_tWP 40
+
+#define NAND_TIMING_tRH 20
+#define NAND_TIMING_tRP 40
+
+#define NAND_TIMING_tR 11123
+#define NAND_TIMING_tWHR 100
+#define NAND_TIMING_tAR 10
+
+/* NAND debugging */
+#if 0
+#define CFG_DFC_DEBUG1 /* useful */
+#define CFG_DFC_DEBUG2 /* noisy */
+#define CFG_DFC_DEBUG3 /* extremly noisy */
+#else
+#undef CFG_DFC_DEBUG1 /* useful */
+#undef CFG_DFC_DEBUG2 /* noisy */
+#undef CFG_DFC_DEBUG3 /* extremly noisy */
+#endif
+
+#define CONFIG_MTD_DEBUG 0
+#define CONFIG_MTD_DEBUG_VERBOSE 0
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN 0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+#define CFG_NO_FLASH 1
+
+#define CFG_ENV_IS_IN_NAND 1
+#define CFG_ENV_OFFSET 0x60000
+#undef CFG_ENV_OFFSET_REDUND
+#define CFG_ENV_SIZE 0x20000
+
+#define CONFIG_JFFS2_NAND 1
+#define CONFIG_JFFS2_NAND_DEV "nand0" /* nand device jffs2 lives on */
+#define CONFIG_JFFS2_NAND_OFF 0x80000 /* start of jffs2 partition */
+#define CONFIG_JFFS2_NAND_SIZE 64*1024*1024 /* size of jffs2 partition */
+
+
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nand0=triton320-nand"
+#define MTDPARTS_DEFAULT "mtdparts=triton320-nand:128k(sbootl),256k(u-boot),128k(env),2m(linux_kernel),83456k(userfs),32m(wince);"
+
+#endif /* __CONFIG_H */
--- /dev/null
+#ifndef __WINCE_H__\r
+#define __WINCE_H__\r
+\r
+#define CE_DOFFSET (net->align_offset + ETHER_HDR_SIZE + IP_HDR_SIZE)\r
+\r
+/* Bin image parse results */\r
+\r
+#define CE_PR_EOF 0\r
+#define CE_PR_MORE 1\r
+#define CE_PR_ERROR 2\r
+\r
+\r
+\r
+\r
+#pragma pack(1)\r
+\r
+/* Edbg BOOTME packet structures */\r
+\r
+typedef struct \r
+{\r
+ unsigned int id; /* Protocol identifier ("EDBG" on the wire) */\r
+ unsigned char service; /* Service identifier */\r
+ unsigned char flags; /* Flags (see defs below) */\r
+ unsigned char seqNum; /* For detection of dropped packets */\r
+ unsigned char cmd; /* For administrative messages */\r
+ unsigned char data[1]; /* Cmd specific data starts here (format is determined by */ \r
+ /* Cmd, len is determined by UDP packet size) */\r
+} \r
+eth_dbg_hdr;\r
+\r
+#define OFFSETOF(s,m) ((unsigned int)&(((s*)0)->m))\r
+#define EDBG_DATA_OFFSET (OFFSETOF(eth_dbg_hdr, data))\r
+\r
+typedef struct \r
+{\r
+ unsigned char versionMajor; // Bootloader version\r
+ unsigned char versionMinor; // Bootloader version\r
+ unsigned char macAddr[6]; // Ether address of device (net byte order)\r
+ unsigned int ipAddr; // IP address of device (net byte order)\r
+ char platformId[17]; // Platform Id string (NULL terminated)\r
+ char deviceName[17]; // Device name string (NULL terminated). Should include\r
+ // platform and number based on Ether address (e.g. Odo42, CEPCLS2346, etc)\r
+ unsigned char cpuId; // CPU identifier (upper nibble = type)\r
+ // The following fields were added in CE 3.0 Platform Builder release\r
+ unsigned char bootmeVer; // BOOTME Version. Must be in the range 2 -> EDBG_CURRENT_BOOTME_VERSION, or\r
+ // remaining fields will be ignored by Eshell and defaults will be used.\r
+ unsigned int bootFlags; // Boot Flags\r
+ unsigned short downloadPort; // Download Port (net byte order) (0 -> EDBG_DOWNLOAD_PORT) \r
+ unsigned short svcPort; // Service Port (net byte order) (0 -> EDBG_SVC_PORT)\r
+\r
+} edbg_bootme_data;\r
+\r
+// Packet size\r
+\r
+#define BOOTME_PKT_SIZE (EDBG_DATA_OFFSET + sizeof(edbg_bootme_data))\r
+\r
+// WinCE .BIN file format signature\r
+\r
+#define CE_BIN_SIGN "B000FF\x0A"\r
+#define CE_BIN_SIGN_LEN 7\r
+\r
+\r
+typedef struct\r
+{\r
+ unsigned char sign[ CE_BIN_SIGN_LEN ];\r
+ unsigned int rtiPhysAddr;\r
+ unsigned int rtiPhysLen;\r
+}\r
+ce_bin_hdr;\r
+\r
+typedef struct\r
+{\r
+ unsigned int physAddr;\r
+ unsigned int physLen;\r
+ unsigned int chkSum;\r
+ unsigned char data[ 1 ];\r
+}\r
+ce_bin_entry;\r
+\r
+// CE ROM image structures\r
+\r
+#define ROM_SIGNATURE_OFFSET 0x40 // Offset from the image's physfirst address to the ROM signature.\r
+#define ROM_SIGNATURE 0x43454345 // Signature\r
+#define ROM_TOC_POINTER_OFFSET 0x44 // Offset from the image's physfirst address to the TOC pointer.\r
+#define ROM_TOC_OFFSET_OFFSET 0x48 // Offset from the image's physfirst address to the TOC offset (from physfirst).\r
+\r
+typedef struct\r
+{\r
+ unsigned int dllfirst; // first DLL address\r
+ unsigned int dlllast; // last DLL address\r
+ unsigned int physfirst; // first physical address\r
+ unsigned int physlast; // highest physical address\r
+ unsigned int nummods; // number of TOCentry's\r
+ unsigned int ramStart; // start of RAM\r
+ unsigned int ramFree; // start of RAM free space\r
+ unsigned int ramEnd; // end of RAM\r
+ unsigned int copyEntries; // number of copy section entries\r
+ unsigned int copyOffset; // offset to copy section\r
+ unsigned int profileLen; // length of PROFentries RAM \r
+ unsigned int profileOffset; // offset to PROFentries\r
+ unsigned int numfiles; // number of FILES\r
+ unsigned int kernelFlags; // optional kernel flags from ROMFLAGS .bib config option\r
+ unsigned int fsRamPercent; // Percentage of RAM used for filesystem \r
+ // from FSRAMPERCENT .bib config option\r
+ // byte 0 = #4K chunks/Mbyte of RAM for filesystem 0-2Mbytes 0-255\r
+ // byte 1 = #4K chunks/Mbyte of RAM for filesystem 2-4Mbytes 0-255\r
+ // byte 2 = #4K chunks/Mbyte of RAM for filesystem 4-6Mbytes 0-255\r
+ // byte 3 = #4K chunks/Mbyte of RAM for filesystem > 6Mbytes 0-255\r
+\r
+ unsigned int drivglobStart; // device driver global starting address\r
+ unsigned int drivglobLen; // device driver global length\r
+ unsigned short cpuType; // CPU (machine) Type\r
+ unsigned short miscFlags; // Miscellaneous flags\r
+ void* extensions; // pointer to ROM Header extensions\r
+ unsigned int trackingStart; // tracking memory starting address\r
+ unsigned int trackingLen; // tracking memory ending address\r
+} \r
+ce_rom_hdr;\r
+\r
+// Win32 FILETIME strcuture\r
+\r
+typedef struct\r
+{\r
+ unsigned int loDateTime;\r
+ unsigned int hiDateTime;\r
+} \r
+ce_file_time;\r
+\r
+// Table Of Contents entry structure\r
+\r
+typedef struct\r
+{ \r
+ unsigned int fileAttributes;\r
+ ce_file_time fileTime;\r
+ unsigned int fileSize;\r
+ char* fileName;\r
+ unsigned int e32Offset; // Offset to E32 structure\r
+ unsigned int o32Offset; // Offset to O32 structure\r
+ unsigned int loadOffset; // MODULE load buffer offset\r
+} \r
+ce_toc_entry;\r
+\r
+typedef struct \r
+{ /* Extra information header block */\r
+ unsigned int rva; /* Virtual relative address of info */\r
+ unsigned int size; /* Size of information block */\r
+}\r
+e32_info;\r
+\r
+#define ROM_EXTRA 9\r
+\r
+typedef struct\r
+{\r
+ unsigned short e32_objcnt; /* Number of memory objects */\r
+ unsigned short e32_imageflags; /* Image flags */\r
+ unsigned int e32_entryrva; /* Relative virt. addr. of entry point */\r
+ unsigned int e32_vbase; /* Virtual base address of module */\r
+ unsigned short e32_subsysmajor;/* The subsystem major version number */\r
+ unsigned short e32_subsysminor;/* The subsystem minor version number */\r
+ unsigned int e32_stackmax; /* Maximum stack size */\r
+ unsigned int e32_vsize; /* Virtual size of the entire image */\r
+ unsigned int e32_sect14rva; /* section 14 rva */\r
+ unsigned int e32_sect14size; /* section 14 size */\r
+ unsigned int e32_timestamp; /* Time EXE/DLL was created/modified */\r
+ e32_info e32_unit[ ROM_EXTRA ]; /* Array of extra info units */\r
+ unsigned short e32_subsys; /* The subsystem type */\r
+} \r
+e32_rom;\r
+\r
+\r
+\r
+// OS config msg \r
+\r
+#define EDBG_FL_DBGMSG 0x01 // Debug messages\r
+#define EDBG_FL_PPSH 0x02 // Text shell\r
+#define EDBG_FL_KDBG 0x04 // Kernel debugger\r
+#define EDBG_FL_CLEANBOOT 0x08 // Force a clean boot\r
+\r
+typedef struct\r
+{\r
+ unsigned char flags; // Flags that will be used to determine what features are\r
+ // enabled over ethernet (saved in driver globals by bootloader)\r
+ unsigned char kitlTransport; // Tells KITL which transport to start\r
+\r
+ // The following specify addressing info, only valid if the corresponding\r
+ // flag is set in the Flags field.\r
+ \r
+ unsigned int dbgMsgIPAddr;\r
+ unsigned short dbgMsgPort;\r
+ unsigned int ppshIPAddr;\r
+ unsigned short ppshPort;\r
+ unsigned int kdbgIPAddr;\r
+ unsigned short kdbgPort;\r
+ \r
+} edbg_os_config_data;\r
+\r
+\r
+\r
+// Driver globals structure\r
+// Used to pass driver globals info from RedBoot to WinCE core\r
+\r
+#define DRV_GLB_SIGNATURE 0x424C4744 // "DGLB"\r
+\r
+typedef struct\r
+{\r
+ unsigned int signature; // Signature\r
+ unsigned int flags; // Misc flags\r
+ unsigned int ipAddr; // IP address of device (net byte order)\r
+ unsigned int ipGate; // IP address of gateway (net byte order)\r
+ unsigned int ipMask; // Subnet mask\r
+ unsigned char macAddr[6]; // Ether address of device (net byte order)\r
+ edbg_os_config_data edbgConfig; // EDBG services info\r
+}\r
+ce_driver_globals;\r
+\r
+\r
+#pragma pack()\r
+\r
+\r
+\r
+typedef struct\r
+{\r
+ unsigned int rtiPhysAddr;\r
+ unsigned int rtiPhysLen;\r
+ unsigned int ePhysAddr;\r
+ unsigned int ePhysLen;\r
+ unsigned int eChkSum;\r
+\r
+ unsigned int eEntryPoint;\r
+ unsigned int eRamStart;\r
+ unsigned int eRamLen;\r
+ unsigned int eDrvGlb;\r
+ \r
+ unsigned char parseState;\r
+ unsigned int parseChkSum;\r
+ int parseLen;\r
+ unsigned char* parsePtr;\r
+ int secion;\r
+ \r
+ int dataLen;\r
+ unsigned char* data;\r
+ \r
+ int binLen;\r
+ int endOfBin;\r
+\r
+ edbg_os_config_data edbgConfig;\r
+}\r
+ce_bin;\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+// IPv4 support
+
+// Socket/connection information
+struct sockaddr_in {
+ IPaddr_t sin_addr;
+ unsigned short sin_port;
+ unsigned short sin_family;
+ short sin_len;
+};
+#define AF_INET 1
+#define INADDR_ANY 0
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+typedef struct\r
+{\r
+ int verbose;\r
+ int link;\r
+ struct sockaddr_in locAddr;\r
+ struct sockaddr_in srvAddrSend;\r
+ struct sockaddr_in srvAddrRecv;\r
+ int gotJumpingRequest;\r
+ unsigned char secNum;\r
+ unsigned short blockNum;\r
+ int dataLen;\r
+ int align_offset;\r
+ int got_packet_4me;\r
+ unsigned char data[PKTSIZE_ALIGN];\r
+}\r
+ce_net;\r
+\r
+\r
+struct timeval {
+ long tv_sec; /* seconds */
+ long tv_usec; /* and microseconds */
+};
+\r
+\r
+\r
+// Default UDP ports used for Ethernet download and EDBG messages. May be overriden\r
+// by device in BOOTME message.\r
+\r
+#define EDBG_DOWNLOAD_PORT 980 // For downloading images to bootloader via TFTP\r
+#define EDBG_SVC_PORT 981 // Other types of transfers\r
+\r
+// Byte string for Id field (note - must not conflict with valid TFTP\r
+// opcodes (0-5), as we share the download port with TFTP)\r
+\r
+#define EDBG_ID 0x47424445 // "EDBG"\r
+\r
+// Defs for reserved values of the Service field\r
+\r
+#define EDBG_SVC_DBGMSG 0 // Debug messages\r
+#define EDBG_SVC_PPSH 1 // Text shell and PPFS file system\r
+#define EDBG_SVC_KDBG 2 // Kernel debugger\r
+#define EDBG_SVC_ADMIN 0xFF // Administrative messages \r
+\r
+// Commands\r
+\r
+#define EDBG_CMD_READ_REQ 1 // Read request\r
+#define EDBG_CMD_WRITE_REQ 2 // Write request\r
+#define EDBG_CMD_WRITE 3 // Host ack\r
+#define EDBG_CMD_WRITE_ACK 4 // Target ack\r
+#define EDBG_CMD_ERROR 5 // Error\r
+\r
+// Service Ids from 3-FE are used for user apps\r
+\r
+#define NUM_DFLT_EDBG_SERVICES 3 \r
+\r
+// Size of send and receive windows (except for stop and wait mode)\r
+\r
+#define EDBG_WINDOW_SIZE 8\r
+\r
+// The window size can be negotiated up to this amount if a client provides\r
+// enough memory.\r
+#define EDBG_MAX_WINDOW_SIZE 16\r
+\r
+// Max size for an EDBG frame. Based on ethernet MTU - protocol overhead.\r
+// Limited to one MTU because we don't do IP fragmentation on device.\r
+\r
+#define EDBG_MAX_DATA_SIZE 1446\r
+\r
+// Defs for Flags field.\r
+#define EDBG_FL_FROM_DEV 0x01 // Set if message is from the device\r
+#define EDBG_FL_NACK 0x02 // Set if frame is a nack\r
+#define EDBG_FL_ACK 0x04 // Set if frame is an ack\r
+#define EDBG_FL_SYNC 0x08 // Can be used to reset sequence # to 0\r
+#define EDBG_FL_ADMIN_RESP 0x10 // For admin messages, indicate whether this is a response\r
+\r
+// Definitions for Cmd field (used for administrative messages)\r
+// Msgs from device\r
+\r
+#define EDBG_CMD_BOOTME 0 // Initial bootup message from device\r
+\r
+// Msgs from PC\r
+\r
+#define EDBG_CMD_SETDEBUG 1 // Used to set debug zones on device (TBD)\r
+#define EDBG_CMD_JUMPIMG 2 // Command to tell bootloader to jump to existing\r
+ // flash or RAM image. Data is same as CMD_OS_CONFIG.\r
+#define EDBG_CMD_OS_CONFIG 3 // Configure OS for debug ethernet services\r
+#define EDBG_CMD_QUERYINFO 4 // "Ping" device, and return information (same fmt as bootme)\r
+#define EDBG_CMD_RESET 5 // Command to have platform perform SW reset (e.g. so it\r
+ // can be reprogrammed). Support for this command is\r
+ // processor dependant, and may not be implemented\r
+ // on all platforms (requires HW mods for Odo).\r
+\r
+// Msgs from device or PC \r
+\r
+#define EDBG_CMD_SVC_CONFIG 6\r
+#define EDBG_CMD_SVC_DATA 7\r
+\r
+#define EDBG_CMD_DEBUGBREAK 8 // Break into debugger\r
+\r
+// Structures for Data portion of EDBG packets\r
+\r
+#define EDBG_MAX_DEV_NAMELEN 16\r
+\r
+// BOOTME message - Devices broadcast this message when booted to request configuration\r
+\r
+#define EDBG_CURRENT_BOOTME_VERSION 2\r
+\r
+//\r
+// Capability and boot Flags for dwBootFlags in EDBG_BOOTME_DATA\r
+// LOWORD for boot flags, HIWORD for capability flags\r
+//\r
+\r
+// Always download image\r
+\r
+#define EDBG_BOOTFLAG_FORCE_DOWNLOAD 0x00000001 \r
+\r
+// Support passive-kitl\r
+\r
+#define EDBG_CAPS_PASSIVEKITL 0x00010000 \r
+\r
+// Defs for CPUId\r
+\r
+#define EDBG_CPU_TYPE_SHX 0x10\r
+#define EDBG_CPU_TYPE_MIPS 0x20\r
+#define EDBG_CPU_TYPE_X86 0x30\r
+#define EDBG_CPU_TYPE_ARM 0x40\r
+#define EDBG_CPU_TYPE_PPC 0x50\r
+#define EDBG_CPU_TYPE_THUMB 0x60\r
+ \r
+#define EDBG_CPU_SH3 (EDBG_CPU_TYPE_SHX | 0)\r
+#define EDBG_CPU_SH4 (EDBG_CPU_TYPE_SHX | 1)\r
+#define EDBG_CPU_R3000 (EDBG_CPU_TYPE_MIPS | 0)\r
+#define EDBG_CPU_R4101 (EDBG_CPU_TYPE_MIPS | 1)\r
+#define EDBG_CPU_R4102 (EDBG_CPU_TYPE_MIPS | 2)\r
+#define EDBG_CPU_R4111 (EDBG_CPU_TYPE_MIPS | 3)\r
+#define EDBG_CPU_R4200 (EDBG_CPU_TYPE_MIPS | 4)\r
+#define EDBG_CPU_R4300 (EDBG_CPU_TYPE_MIPS | 5)\r
+#define EDBG_CPU_R5230 (EDBG_CPU_TYPE_MIPS | 6)\r
+#define EDBG_CPU_R5432 (EDBG_CPU_TYPE_MIPS | 7)\r
+#define EDBG_CPU_i486 (EDBG_CPU_TYPE_X86 | 0)\r
+#define EDBG_CPU_SA1100 (EDBG_CPU_TYPE_ARM | 0)\r
+#define EDBG_CPU_ARM720 (EDBG_CPU_TYPE_ARM | 1)\r
+#define EDBG_CPU_PPC821 (EDBG_CPU_TYPE_PPC | 0)\r
+#define EDBG_CPU_PPC403 (EDBG_CPU_TYPE_PPC | 1)\r
+#define EDBG_CPU_THUMB720 (EDBG_CPU_TYPE_THUMB | 0)\r
+\r
+\r
+\r
+#endif\r
+\r
+\r
+int ce_bin_load(void* image, int imglen);\r
+int ce_is_bin_image(void* image, int imglen);\r
+void ce_bin_init_parser(void);\r
+int ce_bin_parse_next(void* parseBuffer, int len);\r
+void ce_init_bin(ce_bin* bin, unsigned char* dataBuffer);\r
+int ce_parse_bin(ce_bin* bin);\r
+int ce_lookup_ep_bin(ce_bin* bin);\r
+void ce_prepare_run_bin(ce_bin* bin);\r
+void ce_run_bin(ce_bin* bin);\r
+\r
+int ce_recv_frame(ce_net* net, int timeout);\r
+int ce_process_download(ce_net* net, ce_bin* bin);\r
+void ce_init_edbg_link(ce_net* net);\r
+void ce_process_edbg(ce_net* net, ce_bin* bin);\r
+\r
+int ce_recv_frame(ce_net* net, int timeout);\r
+int ce_process_download(ce_net* net, ce_bin* bin);\r
+void ce_init_edbg_link(ce_net* net);\r
+void ce_process_edbg(ce_net* net, ce_bin* bin);\r
+int ce_send_write_ack(ce_net* net);\r
+int ce_send_frame(ce_net* net);\r
+int ce_recv_packet(char *buf, int len, struct sockaddr_in *from, struct sockaddr_in *local, struct timeval *timeout);\r
+void ce_dump_block(unsigned char *ptr, int length);\r
projects / karo-tx-uboot.git / commitdiff