imx: mx6: ccm: Change the clock settings for i.MX6QP

Since i.MX6QP changes some CCM registers, so modify the clocks settings to
follow the hardware changes.

In c files, use runtime check and discard #ifdef.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 980a6eb6dc7bbb076186e9daf8e313f287c3fa0b..836fe8f52a46cb95c59b88a893cb86f4ac96149f 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -435,10 +435,12 @@ static u32 get_ipg_per_clk(void)
        u32 reg, perclk_podf;
 
        reg = __raw_readl(&imx_ccm->cscmr1);
        u32 reg, perclk_podf;
 
        reg = __raw_readl(&imx_ccm->cscmr1);

-#if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))
-       if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
-               return MXC_HCLK; /* OSC 24Mhz */
-#endif
+       if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
+           is_mx6dqp()) {
+               if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
+                       return MXC_HCLK; /* OSC 24Mhz */
+       }
+

        perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
 
        return get_ipg_clk() / (perclk_podf + 1);
        perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
 
        return get_ipg_clk() / (perclk_podf + 1);


@@ -449,10 +451,13 @@ static u32 get_uart_clk(void)
        u32 reg, uart_podf;
        u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
        reg = __raw_readl(&imx_ccm->cscdr1);
        u32 reg, uart_podf;
        u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
        reg = __raw_readl(&imx_ccm->cscdr1);

-#if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))
-       if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
-               freq = MXC_HCLK;
-#endif
+
+       if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
+           is_mx6dqp()) {
+               if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
+                       freq = MXC_HCLK;
+       }
+

        reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
        uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
 
        reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
        uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
 


@@ -464,8 +469,13 @@ static u32 get_cspi_clk(void)
        u32 reg, cspi_podf;
 
        reg = __raw_readl(&imx_ccm->cscdr2);
        u32 reg, cspi_podf;
 
        reg = __raw_readl(&imx_ccm->cscdr2);

-       reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
-       cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
+       cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
+                    MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
+
+       if (is_mx6dqp()) {
+               if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
+                       return MXC_HCLK / (cspi_podf + 1);
+       }

 
        return  decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
 }
 
        return  decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
 }

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 5cd712f1777470f69ca94da47ecefea620664689..546a275c01683f6142e291f30ea5e85a0efc06ec 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -538,9 +538,12 @@ static void set_ahb_rate(u32 val)
 static void clear_mmdc_ch_mask(void)
 {
        struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 static void clear_mmdc_ch_mask(void)
 {
        struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

+       u32 reg;
+       reg = readl(&mxc_ccm->ccdr);

 
        /* Clear MMDC channel mask */
 
        /* Clear MMDC channel mask */

-       writel(0, &mxc_ccm->ccdr);
+       reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
+       writel(reg, &mxc_ccm->ccdr);

 }
 
 static void init_bandgap(void)
 }
 
 static void init_bandgap(void)

diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index 08f54646c6a8cdac337252e9235a1bda45cc50aa..aeb2e5ea2d4871ffe5de60ffcb17d7994ab474d0 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -75,6 +75,8 @@ struct mxc_ccm_reg {
 /* Define the bits in register CCDR */
 #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK                  (1 << 16)
 #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK                  (1 << 17)
 /* Define the bits in register CCDR */
 #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK                  (1 << 16)
 #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK                  (1 << 17)

+/* Exists on i.MX6QP */
+#define MXC_CCM_CCDR_MMDC_CH1_AXI_ROOT_CG              (1 << 18)

 
 /* Define the bits in register CSR */
 #define MXC_CCM_CSR_COSC_READY                         (1 << 5)
 
 /* Define the bits in register CSR */
 #define MXC_CCM_CSR_COSC_READY                         (1 << 5)


@@ -147,10 +149,8 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET      8
 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK          (0x3 << MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET)
 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET                4
 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET      8
 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK          (0x3 << MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET)
 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET                4

-#ifndef CONFIG_SOC_MX6SX
-#define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL                        (1 << 1)
-#define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL                        (1 << 0)
-#endif
+/* Exists on i.MX6QP */
+#define MXC_CCM_CBCMR_PRE_CLK_SEL                      (1 << 1)

 
 /* Define the bits in register CSCMR1 */
 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK              (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET)
 
 /* Define the bits in register CSCMR1 */
 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK              (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET)


@@ -181,12 +181,11 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK              (0x7 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET)
 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET            7
 #endif
 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK              (0x7 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET)
 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET            7
 #endif

-#if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))
-#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK                        (1 << MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET)
+/* CSCMR1_PER_CLK exists on i.MX6SX/SL/QP */
+#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6)

 #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET              6
 #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET              6

-#endif
-#define MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET              0
-#define MXC_CCM_CSCMR1_PERCLK_PODF_MASK                        (0x3F << MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET)
+
+#define MXC_CCM_CSCMR1_PERCLK_PODF_MASK                        0x3F

 
 /* Define the bits in register CSCMR2 */
 #ifdef CONFIG_SOC_MX6SX
 
 /* Define the bits in register CSCMR2 */
 #ifdef CONFIG_SOC_MX6SX


@@ -197,15 +196,12 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET             19
 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV                 (1 << 11)
 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV                 (1 << 10)
 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET             19
 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV                 (1 << 11)
 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV                 (1 << 10)

-#ifdef CONFIG_SOC_MX6SX
-#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK                        (0x3 << MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET)
+/* CSCMR1_CAN_CLK exists on i.MX6SX/QP */
+#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK                        (0x3 << 8)

 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET              8
 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET              8

-#define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK               (0x3F << MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET)
+
+#define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK               (0x3F << 2)

 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET             2
 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET             2

-#else
-#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK                        (0x3F << MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET)
-#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET              2
-#endif

 
 /* Define the bits in register CSCDR1 */
 #ifndef CONFIG_SOC_MX6SX
 
 /* Define the bits in register CSCDR1 */
 #ifndef CONFIG_SOC_MX6SX


@@ -226,17 +222,10 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET          6
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK            (0x3 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET)
 #endif
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET          6
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK            (0x3 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET)
 #endif

-#ifdef CONFIG_SOC_MX6SL
-#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK              (0x1F << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET)
-#define MXC_CCM_CSCDR1_UART_CLK_SEL                    (1 << MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET)
-#else
-#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK              (0x3F << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET)
-#ifdef CONFIG_SOC_MX6SX
-#define MXC_CCM_CSCDR1_UART_CLK_SEL                    (1 << MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET)
-#endif
-#endif
-#define MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET             6
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK              0x3F

 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET            0
 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET            0

+/* UART_CLK_SEL exists on i.MX6SL/SX/QP */
+#define MXC_CCM_CSCDR1_UART_CLK_SEL                    (1 << 6)

 
 /* Define the bits in register CS1CDR */
 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK              (0x3F << MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET)
 
 /* Define the bits in register CS1CDR */
 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK              (0x3F << MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET)


@@ -269,10 +258,15 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v)                        (((v) & 0x3f) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET)
 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK              (0x7 << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET)
 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET            18
 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v)                        (((v) & 0x3f) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET)
 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK              (0x7 << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET)
 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET            18

-#define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v)                        (((v) & 0x7) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET)
-#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK               (0x3 << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET)
-#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET             16
-#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v)                 (((v) & 0x3) << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET)
+#define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v)                        (((v) & 0x7) << 18)
+
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK       \
+       (is_mx6dqp() ? (0x7 << 15) : (0x3 << 16))
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET     \
+       (is_mx6dqp() ? 15 : 16)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v)         \
+       (is_mx6dqp() ? (((v) & 0x7) << 15) : (((v) & 0x3) << 16))
+

 #endif
 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK            (0x7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET          12
 #endif
 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK            (0x7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET          12


@@ -339,6 +333,9 @@ struct mxc_ccm_reg {
 /* Define the bits in register CSCDR2 */
 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK             (0x3F << MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET)
 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET           19
 /* Define the bits in register CSCDR2 */
 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK             (0x3F << MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET)
 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET           19

+/* ECSPI_CLK_SEL exists on i.MX6SX/SL/QP */
+#define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK              (0x1 << 18)
+

 /* All IPU2_DI1 are LCDIF1 on MX6SX */
 #define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK       (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET)
 #define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET     15
 /* All IPU2_DI1 are LCDIF1 on MX6SX */
 #define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK       (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET)
 #define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET     15