Merge branch 'master' of git://git.denx.de/u-boot-arm
authorTom Rini <trini@ti.com>
Thu, 13 Nov 2014 14:32:45 +0000 (09:32 -0500)
committerTom Rini <trini@ti.com>
Thu, 13 Nov 2014 14:32:45 +0000 (09:32 -0500)
79 files changed:
arch/arm/Kconfig
arch/arm/cpu/armv7/socfpga/clock_manager.c
arch/arm/cpu/armv7/socfpga/misc.c
arch/arm/cpu/armv7/socfpga/reset_manager.c
arch/arm/cpu/armv7/tegra-common/Kconfig
arch/arm/cpu/armv7/zynq/Kconfig
arch/arm/cpu/armv8/Kconfig [deleted file]
arch/arm/dts/Makefile
arch/arm/dts/socfpga.dtsi [new file with mode: 0644]
arch/arm/dts/socfpga_cyclone5.dtsi [new file with mode: 0644]
arch/arm/dts/socfpga_cyclone5_socrates.dts [new file with mode: 0644]
arch/arm/dts/zynq-zybo.dts [new file with mode: 0644]
arch/arm/include/asm/arch-socfpga/gpio.h [new file with mode: 0644]
arch/arm/include/asm/arch-socfpga/reset_manager.h
arch/powerpc/cpu/mpc5xxx/Kconfig
board/Marvell/db-mv784mp-gp/Kconfig
board/altera/socfpga/socfpga_cyclone5.c
board/kosagi/novena/Kconfig
board/maxbcm/Kconfig
board/mcc200/Kconfig [deleted file]
board/mcc200/MAINTAINERS [deleted file]
board/mcc200/Makefile [deleted file]
board/mcc200/auto_update.c [deleted file]
board/mcc200/lcd.c [deleted file]
board/mcc200/mcc200.c [deleted file]
board/mcc200/mt46v16m16-75.h [deleted file]
board/mcc200/mt48lc16m16a2-75.h [deleted file]
board/mcc200/mt48lc16m32s2-75.h [deleted file]
board/mcc200/mt48lc8m32b2-6-7.h [deleted file]
board/ti/ks2_evm/Kconfig
board/xilinx/zynq/.gitignore
board/xilinx/zynq/Makefile
board/xilinx/zynq/legacy.c [new file with mode: 0644]
board/xilinx/zynq/xil_io.h
common/lcd.c
common/usb_storage.c
configs/mcc200_COM12_SDRAM_defconfig [deleted file]
configs/mcc200_COM12_defconfig [deleted file]
configs/mcc200_COM12_highboot_SDRAM_defconfig [deleted file]
configs/mcc200_COM12_highboot_defconfig [deleted file]
configs/mcc200_SDRAM_defconfig [deleted file]
configs/mcc200_defconfig [deleted file]
configs/mcc200_highboot_SDRAM_defconfig [deleted file]
configs/mcc200_highboot_defconfig [deleted file]
configs/novena_defconfig
configs/prs200_DDR_defconfig [deleted file]
configs/prs200_defconfig [deleted file]
configs/prs200_highboot_DDR_defconfig [deleted file]
configs/prs200_highboot_defconfig [deleted file]
configs/socfpga_socrates_defconfig [new file with mode: 0644]
configs/zynq_zybo_defconfig [new file with mode: 0644]
doc/README.scrapyard
drivers/usb/eth/Makefile
drivers/usb/gadget/Makefile
drivers/usb/gadget/s3c_udc_otg.c
drivers/usb/gadget/s3c_udc_otg_phy.c [new file with mode: 0644]
drivers/usb/gadget/s3c_udc_otg_xfer_dma.c
drivers/usb/host/ehci-rmobile.c
drivers/usb/host/ehci.h
include/configs/exynos4-common.h
include/configs/mcc200.h [deleted file]
include/configs/s5p_goni.h
include/configs/s5pc210_universal.h
include/configs/smdkv310.h
include/configs/socfpga_common.h
include/configs/socfpga_cyclone5.h
include/configs/zynq_zybo.h [new file with mode: 0644]
include/dt-bindings/reset/altr,rst-mgr.h [new file with mode: 0644]
include/lcd.h
include/usb.h
include/usb/s3c_udc.h
scripts/binutils-version.sh [changed mode: 0644->0755]
scripts/dtc-version.sh [changed mode: 0644->0755]
scripts/gcc-stack-usage.sh [changed mode: 0644->0755]
scripts/gcc-version.sh [changed mode: 0644->0755]
scripts/kconfig/lxdialog/check-lxdialog.sh [changed mode: 0644->0755]
scripts/kconfig/streamline_config.pl [changed mode: 0644->0755]
scripts/mkmakefile [changed mode: 0644->0755]
scripts/multiconfig.sh [changed mode: 0644->0755]

index 79ccc06..3955978 100644 (file)
@@ -49,6 +49,7 @@ config SYS_CPU
         default "armv7" if CPU_V7
         default "pxa" if CPU_PXA
         default "sa1100" if CPU_SA1100
+       default "armv8" if ARM64
 
 choice
        prompt "Target select"
@@ -225,9 +226,11 @@ config KIRKWOOD
 
 config TARGET_DB_MV784MP_GP
        bool "Support db-mv784mp-gp"
+       select CPU_V7
 
 config TARGET_MAXBCM
        bool "Support maxbcm"
+       select CPU_V7
 
 config TARGET_DEVKIT3250
        bool "Support devkit3250"
@@ -629,6 +632,8 @@ config TARGET_HUMMINGBOARD
 
 config TARGET_KOSAGI_NOVENA
        bool "Support Kosagi Novena"
+       select CPU_V7
+       select SUPPORT_SPL
 
 config TARGET_TQMA6
        bool "TQ Systems TQMa6 board"
@@ -775,8 +780,6 @@ config ARCH_UNIPHIER
 
 endchoice
 
-source "arch/arm/cpu/armv8/Kconfig"
-
 source "arch/arm/cpu/arm926ejs/davinci/Kconfig"
 
 source "arch/arm/cpu/armv7/exynos/Kconfig"
index d869f47..fa3b93a 100644 (file)
@@ -507,6 +507,19 @@ unsigned int cm_get_qspi_controller_clk_hz(void)
        return clock;
 }
 
+unsigned int cm_get_spi_controller_clk_hz(void)
+{
+       uint32_t reg, clock = 0;
+
+       clock = cm_get_per_vco_clk_hz();
+
+       /* get the clock prior L4 SP divider (periph_base_clk) */
+       reg = readl(&clock_manager_base->per_pll.perbaseclk);
+       clock /= (reg + 1);
+
+       return clock;
+}
+
 static void cm_print_clock_quick_summary(void)
 {
        printf("MPU       %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
@@ -518,6 +531,7 @@ static void cm_print_clock_quick_summary(void)
        printf("MMC         %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
        printf("QSPI        %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000);
        printf("UART        %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
+       printf("SPI         %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000);
 }
 
 int set_cpu_clk_info(void)
index 8c3e5f7..73cffd3 100644 (file)
@@ -202,6 +202,12 @@ int arch_early_init_r(void)
 
        /* Add device descriptor to FPGA device table */
        socfpga_fpga_add();
+
+#ifdef CONFIG_DESIGNWARE_SPI
+       /* Get Designware SPI controller out of reset */
+       socfpga_spim_enable();
+#endif
+
        return 0;
 }
 
index 1d3a95d..af9db85 100644 (file)
@@ -104,3 +104,12 @@ void socfpga_emac_reset(int enable)
 #endif
        }
 }
+
+/* SPI Master enable (its held in reset by the preloader) */
+void socfpga_spim_enable(void)
+{
+       const void *reset = &reset_manager_base->per_mod_reset;
+
+       clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM0_LSB);
+       clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM1_LSB);
+}
index 3ea6d76..1446452 100644 (file)
@@ -20,10 +20,6 @@ endchoice
 config USE_PRIVATE_LIBGCC
        default y if SPL_BUILD
 
-config SYS_CPU
-       default "arm720t" if SPL_BUILD
-       default "armv7" if !SPL_BUILD
-
 source "arch/arm/cpu/armv7/tegra20/Kconfig"
 source "arch/arm/cpu/armv7/tegra30/Kconfig"
 source "arch/arm/cpu/armv7/tegra114/Kconfig"
index f418cd6..3a52535 100644 (file)
@@ -15,6 +15,9 @@ config TARGET_ZYNQ_ZC70X
 config TARGET_ZYNQ_ZC770
        bool "Zynq ZC770 Board"
 
+config TARGET_ZYNQ_ZYBO
+       bool "Zynq Zybo Board"
+
 endchoice
 
 config SYS_BOARD
@@ -31,5 +34,6 @@ config SYS_CONFIG_NAME
        default "zynq_microzed" if TARGET_ZYNQ_MICROZED
        default "zynq_zc70x" if TARGET_ZYNQ_ZC70X
        default "zynq_zc770" if TARGET_ZYNQ_ZC770
+       default "zynq_zybo" if TARGET_ZYNQ_ZYBO
 
 endif
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
deleted file mode 100644 (file)
index 3d1655b..0000000
+++ /dev/null
@@ -1,6 +0,0 @@
-if ARM64
-
-config SYS_CPU
-       default "armv8"
-
-endif
index 52f8926..ba6dec9 100644 (file)
@@ -34,12 +34,15 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
 dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
        zynq-zc706.dtb \
        zynq-zed.dtb \
+       zynq-zybo.dtb \
        zynq-microzed.dtb \
        zynq-zc770-xm010.dtb \
        zynq-zc770-xm012.dtb \
        zynq-zc770-xm013.dtb
 dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb
 
+dtb-$(CONFIG_SOCFPGA) += socfpga_cyclone5_socrates.dtb
+
 targets += $(dtb-y)
 
 DTC_FLAGS += -R 4 -p 0x1000
diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
new file mode 100644 (file)
index 0000000..4472fd9
--- /dev/null
@@ -0,0 +1,755 @@
+/*
+ *  Copyright (C) 2012 Altera <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/reset/altr,rst-mgr.h>
+
+/ {
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       aliases {
+               ethernet0 = &gmac0;
+               ethernet1 = &gmac1;
+               serial0 = &uart0;
+               serial1 = &uart1;
+               timer0 = &timer0;
+               timer1 = &timer1;
+               timer2 = &timer2;
+               timer3 = &timer3;
+       };
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu@0 {
+                       compatible = "arm,cortex-a9";
+                       device_type = "cpu";
+                       reg = <0>;
+                       next-level-cache = <&L2>;
+               };
+               cpu@1 {
+                       compatible = "arm,cortex-a9";
+                       device_type = "cpu";
+                       reg = <1>;
+                       next-level-cache = <&L2>;
+               };
+       };
+
+       intc: intc@fffed000 {
+               compatible = "arm,cortex-a9-gic";
+               #interrupt-cells = <3>;
+               interrupt-controller;
+               reg = <0xfffed000 0x1000>,
+                     <0xfffec100 0x100>;
+       };
+
+       soc {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "simple-bus";
+               device_type = "soc";
+               interrupt-parent = <&intc>;
+               ranges;
+
+               amba {
+                       compatible = "arm,amba-bus";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
+
+                       pdma: pdma@ffe01000 {
+                               compatible = "arm,pl330", "arm,primecell";
+                               reg = <0xffe01000 0x1000>;
+                               interrupts = <0 104 4>,
+                                            <0 105 4>,
+                                            <0 106 4>,
+                                            <0 107 4>,
+                                            <0 108 4>,
+                                            <0 109 4>,
+                                            <0 110 4>,
+                                            <0 111 4>;
+                               #dma-cells = <1>;
+                               #dma-channels = <8>;
+                               #dma-requests = <32>;
+                               clocks = <&l4_main_clk>;
+                               clock-names = "apb_pclk";
+                       };
+               };
+
+               can0: can@ffc00000 {
+                       compatible = "bosch,d_can";
+                       reg = <0xffc00000 0x1000>;
+                       interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
+                       clocks = <&can0_clk>;
+                       status = "disabled";
+               };
+
+               can1: can@ffc01000 {
+                       compatible = "bosch,d_can";
+                       reg = <0xffc01000 0x1000>;
+                       interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
+                       clocks = <&can1_clk>;
+                       status = "disabled";
+               };
+
+               clkmgr@ffd04000 {
+                               compatible = "altr,clk-mgr";
+                               reg = <0xffd04000 0x1000>;
+
+                               clocks {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       osc1: osc1 {
+                                               #clock-cells = <0>;
+                                               compatible = "fixed-clock";
+                                       };
+
+                                       osc2: osc2 {
+                                               #clock-cells = <0>;
+                                               compatible = "fixed-clock";
+                                       };
+
+                                       f2s_periph_ref_clk: f2s_periph_ref_clk {
+                                               #clock-cells = <0>;
+                                               compatible = "fixed-clock";
+                                       };
+
+                                       f2s_sdram_ref_clk: f2s_sdram_ref_clk {
+                                               #clock-cells = <0>;
+                                               compatible = "fixed-clock";
+                                       };
+
+                                       main_pll: main_pll {
+                                               #address-cells = <1>;
+                                               #size-cells = <0>;
+                                               #clock-cells = <0>;
+                                               compatible = "altr,socfpga-pll-clock";
+                                               clocks = <&osc1>;
+                                               reg = <0x40>;
+
+                                               mpuclk: mpuclk {
+                                                       #clock-cells = <0>;
+                                                       compatible = "altr,socfpga-perip-clk";
+                                                       clocks = <&main_pll>;
+                                                       div-reg = <0xe0 0 9>;
+                                                       reg = <0x48>;
+                                               };
+
+                                               mainclk: mainclk {
+                                                       #clock-cells = <0>;
+                                                       compatible = "altr,socfpga-perip-clk";
+                                                       clocks = <&main_pll>;
+                                                       div-reg = <0xe4 0 9>;
+                                                       reg = <0x4C>;
+                                               };
+
+                                               dbg_base_clk: dbg_base_clk {
+                                                       #clock-cells = <0>;
+                                                       compatible = "altr,socfpga-perip-clk";
+                                                       clocks = <&main_pll>;
+                                                       div-reg = <0xe8 0 9>;
+                                                       reg = <0x50>;
+                                               };
+
+                                               main_qspi_clk: main_qspi_clk {
+                                                       #clock-cells = <0>;
+                                                       compatible = "altr,socfpga-perip-clk";
+                                                       clocks = <&main_pll>;
+                                                       reg = <0x54>;
+                                               };
+
+                                               main_nand_sdmmc_clk: main_nand_sdmmc_clk {
+                                                       #clock-cells = <0>;
+                                                       compatible = "altr,socfpga-perip-clk";
+                                                       clocks = <&main_pll>;
+                                                       reg = <0x58>;
+                                               };
+
+                                               cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
+                                                       #clock-cells = <0>;
+                                                       compatible = "altr,socfpga-perip-clk";
+                                                       clocks = <&main_pll>;
+                                                       reg = <0x5C>;
+                                               };
+                                       };
+
+                                       periph_pll: periph_pll {
+                                               #address-cells = <1>;
+                                               #size-cells = <0>;
+                                               #clock-cells = <0>;
+                                               compatible = "altr,socfpga-pll-clock";
+                                               clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
+                                               reg = <0x80>;
+
+                                               emac0_clk: emac0_clk {
+                                                       #clock-cells = <0>;
+                                                       compatible = "altr,socfpga-perip-clk";
+                                                       clocks = <&periph_pll>;
+                                                       reg = <0x88>;
+                                               };
+
+                                               emac1_clk: emac1_clk {
+                                                       #clock-cells = <0>;
+                                                       compatible = "altr,socfpga-perip-clk";
+                                                       clocks = <&periph_pll>;
+                                                       reg = <0x8C>;
+                                               };
+
+                                               per_qspi_clk: per_qsi_clk {
+                                                       #clock-cells = <0>;
+                                                       compatible = "altr,socfpga-perip-clk";
+                                                       clocks = <&periph_pll>;
+                                                       reg = <0x90>;
+                                               };
+
+                                               per_nand_mmc_clk: per_nand_mmc_clk {
+                                                       #clock-cells = <0>;
+                                                       compatible = "altr,socfpga-perip-clk";
+                                                       clocks = <&periph_pll>;
+                                                       reg = <0x94>;
+                                               };
+
+                                               per_base_clk: per_base_clk {
+                                                       #clock-cells = <0>;
+                                                       compatible = "altr,socfpga-perip-clk";
+                                                       clocks = <&periph_pll>;
+                                                       reg = <0x98>;
+                                               };
+
+                                               h2f_usr1_clk: h2f_usr1_clk {
+                                                       #clock-cells = <0>;
+                                                       compatible = "altr,socfpga-perip-clk";
+                                                       clocks = <&periph_pll>;
+                                                       reg = <0x9C>;
+                                               };
+                                       };
+
+                                       sdram_pll: sdram_pll {
+                                               #address-cells = <1>;
+                                               #size-cells = <0>;
+                                               #clock-cells = <0>;
+                                               compatible = "altr,socfpga-pll-clock";
+                                               clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
+                                               reg = <0xC0>;
+
+                                               ddr_dqs_clk: ddr_dqs_clk {
+                                                       #clock-cells = <0>;
+                                                       compatible = "altr,socfpga-perip-clk";
+                                                       clocks = <&sdram_pll>;
+                                                       reg = <0xC8>;
+                                               };
+
+                                               ddr_2x_dqs_clk: ddr_2x_dqs_clk {
+                                                       #clock-cells = <0>;
+                                                       compatible = "altr,socfpga-perip-clk";
+                                                       clocks = <&sdram_pll>;
+                                                       reg = <0xCC>;
+                                               };
+
+                                               ddr_dq_clk: ddr_dq_clk {
+                                                       #clock-cells = <0>;
+                                                       compatible = "altr,socfpga-perip-clk";
+                                                       clocks = <&sdram_pll>;
+                                                       reg = <0xD0>;
+                                               };
+
+                                               h2f_usr2_clk: h2f_usr2_clk {
+                                                       #clock-cells = <0>;
+                                                       compatible = "altr,socfpga-perip-clk";
+                                                       clocks = <&sdram_pll>;
+                                                       reg = <0xD4>;
+                                               };
+                                       };
+
+                                       mpu_periph_clk: mpu_periph_clk {
+                                               #clock-cells = <0>;
+                                               compatible = "altr,socfpga-perip-clk";
+                                               clocks = <&mpuclk>;
+                                               fixed-divider = <4>;
+                                       };
+
+                                       mpu_l2_ram_clk: mpu_l2_ram_clk {
+                                               #clock-cells = <0>;
+                                               compatible = "altr,socfpga-perip-clk";
+                                               clocks = <&mpuclk>;
+                                               fixed-divider = <2>;
+                                       };
+
+                                       l4_main_clk: l4_main_clk {
+                                               #clock-cells = <0>;
+                                               compatible = "altr,socfpga-gate-clk";
+                                               clocks = <&mainclk>;
+                                               clk-gate = <0x60 0>;
+                                       };
+
+                                       l3_main_clk: l3_main_clk {
+                                               #clock-cells = <0>;
+                                               compatible = "altr,socfpga-perip-clk";
+                                               clocks = <&mainclk>;
+                                               fixed-divider = <1>;
+                                       };
+
+                                       l3_mp_clk: l3_mp_clk {
+                                               #clock-cells = <0>;
+                                               compatible = "altr,socfpga-gate-clk";
+                                               clocks = <&mainclk>;
+                                               div-reg = <0x64 0 2>;
+                                               clk-gate = <0x60 1>;
+                                       };
+
+                                       l3_sp_clk: l3_sp_clk {
+                                               #clock-cells = <0>;
+                                               compatible = "altr,socfpga-gate-clk";
+                                               clocks = <&mainclk>;
+                                               div-reg = <0x64 2 2>;
+                                       };
+
+                                       l4_mp_clk: l4_mp_clk {
+                                               #clock-cells = <0>;
+                                               compatible = "altr,socfpga-gate-clk";
+                                               clocks = <&mainclk>, <&per_base_clk>;
+                                               div-reg = <0x64 4 3>;
+                                               clk-gate = <0x60 2>;
+                                       };
+
+                                       l4_sp_clk: l4_sp_clk {
+                                               #clock-cells = <0>;
+                                               compatible = "altr,socfpga-gate-clk";
+                                               clocks = <&mainclk>, <&per_base_clk>;
+                                               div-reg = <0x64 7 3>;
+                                               clk-gate = <0x60 3>;
+                                       };
+
+                                       dbg_at_clk: dbg_at_clk {
+                                               #clock-cells = <0>;
+                                               compatible = "altr,socfpga-gate-clk";
+                                               clocks = <&dbg_base_clk>;
+                                               div-reg = <0x68 0 2>;
+                                               clk-gate = <0x60 4>;
+                                       };
+
+                                       dbg_clk: dbg_clk {
+                                               #clock-cells = <0>;
+                                               compatible = "altr,socfpga-gate-clk";
+                                               clocks = <&dbg_base_clk>;
+                                               div-reg = <0x68 2 2>;
+                                               clk-gate = <0x60 5>;
+                                       };
+
+                                       dbg_trace_clk: dbg_trace_clk {
+                                               #clock-cells = <0>;
+                                               compatible = "altr,socfpga-gate-clk";
+                                               clocks = <&dbg_base_clk>;
+                                               div-reg = <0x6C 0 3>;
+                                               clk-gate = <0x60 6>;
+                                       };
+
+                                       dbg_timer_clk: dbg_timer_clk {
+                                               #clock-cells = <0>;
+                                               compatible = "altr,socfpga-gate-clk";
+                                               clocks = <&dbg_base_clk>;
+                                               clk-gate = <0x60 7>;
+                                       };
+
+                                       cfg_clk: cfg_clk {
+                                               #clock-cells = <0>;
+                                               compatible = "altr,socfpga-gate-clk";
+                                               clocks = <&cfg_h2f_usr0_clk>;
+                                               clk-gate = <0x60 8>;
+                                       };
+
+                                       h2f_user0_clk: h2f_user0_clk {
+                                               #clock-cells = <0>;
+                                               compatible = "altr,socfpga-gate-clk";
+                                               clocks = <&cfg_h2f_usr0_clk>;
+                                               clk-gate = <0x60 9>;
+                                       };
+
+                                       emac_0_clk: emac_0_clk {
+                                               #clock-cells = <0>;
+                                               compatible = "altr,socfpga-gate-clk";
+                                               clocks = <&emac0_clk>;
+                                               clk-gate = <0xa0 0>;
+                                       };
+
+                                       emac_1_clk: emac_1_clk {
+                                               #clock-cells = <0>;
+                                               compatible = "altr,socfpga-gate-clk";
+                                               clocks = <&emac1_clk>;
+                                               clk-gate = <0xa0 1>;
+                                       };
+
+                                       usb_mp_clk: usb_mp_clk {
+                                               #clock-cells = <0>;
+                                               compatible = "altr,socfpga-gate-clk";
+                                               clocks = <&per_base_clk>;
+                                               clk-gate = <0xa0 2>;
+                                               div-reg = <0xa4 0 3>;
+                                       };
+
+                                       spi_m_clk: spi_m_clk {
+                                               #clock-cells = <0>;
+                                               compatible = "altr,socfpga-gate-clk";
+                                               clocks = <&per_base_clk>;
+                                               clk-gate = <0xa0 3>;
+                                               div-reg = <0xa4 3 3>;
+                                       };
+
+                                       can0_clk: can0_clk {
+                                               #clock-cells = <0>;
+                                               compatible = "altr,socfpga-gate-clk";
+                                               clocks = <&per_base_clk>;
+                                               clk-gate = <0xa0 4>;
+                                               div-reg = <0xa4 6 3>;
+                                       };
+
+                                       can1_clk: can1_clk {
+                                               #clock-cells = <0>;
+                                               compatible = "altr,socfpga-gate-clk";
+                                               clocks = <&per_base_clk>;
+                                               clk-gate = <0xa0 5>;
+                                               div-reg = <0xa4 9 3>;
+                                       };
+
+                                       gpio_db_clk: gpio_db_clk {
+                                               #clock-cells = <0>;
+                                               compatible = "altr,socfpga-gate-clk";
+                                               clocks = <&per_base_clk>;
+                                               clk-gate = <0xa0 6>;
+                                               div-reg = <0xa8 0 24>;
+                                       };
+
+                                       h2f_user1_clk: h2f_user1_clk {
+                                               #clock-cells = <0>;
+                                               compatible = "altr,socfpga-gate-clk";
+                                               clocks = <&h2f_usr1_clk>;
+                                               clk-gate = <0xa0 7>;
+                                       };
+
+                                       sdmmc_clk: sdmmc_clk {
+                                               #clock-cells = <0>;
+                                               compatible = "altr,socfpga-gate-clk";
+                                               clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+                                               clk-gate = <0xa0 8>;
+                                               clk-phase = <0 135>;
+                                       };
+
+                                       nand_x_clk: nand_x_clk {
+                                               #clock-cells = <0>;
+                                               compatible = "altr,socfpga-gate-clk";
+                                               clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+                                               clk-gate = <0xa0 9>;
+                                       };
+
+                                       nand_clk: nand_clk {
+                                               #clock-cells = <0>;
+                                               compatible = "altr,socfpga-gate-clk";
+                                               clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+                                               clk-gate = <0xa0 10>;
+                                               fixed-divider = <4>;
+                                       };
+
+                                       qspi_clk: qspi_clk {
+                                               #clock-cells = <0>;
+                                               compatible = "altr,socfpga-gate-clk";
+                                               clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
+                                               clk-gate = <0xa0 11>;
+                                       };
+                               };
+                       };
+
+               gmac0: ethernet@ff700000 {
+                       compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
+                       altr,sysmgr-syscon = <&sysmgr 0x60 0>;
+                       reg = <0xff700000 0x2000>;
+                       interrupts = <0 115 4>;
+                       interrupt-names = "macirq";
+                       mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
+                       clocks = <&emac0_clk>;
+                       clock-names = "stmmaceth";
+                       resets = <&rst EMAC0_RESET>;
+                       reset-names = "stmmaceth";
+                       snps,multicast-filter-bins = <256>;
+                       snps,perfect-filter-entries = <128>;
+                       status = "disabled";
+               };
+
+               gmac1: ethernet@ff702000 {
+                       compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
+                       altr,sysmgr-syscon = <&sysmgr 0x60 2>;
+                       reg = <0xff702000 0x2000>;
+                       interrupts = <0 120 4>;
+                       interrupt-names = "macirq";
+                       mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
+                       clocks = <&emac1_clk>;
+                       clock-names = "stmmaceth";
+                       resets = <&rst EMAC1_RESET>;
+                       reset-names = "stmmaceth";
+                       snps,multicast-filter-bins = <256>;
+                       snps,perfect-filter-entries = <128>;
+                       status = "disabled";
+               };
+
+               i2c0: i2c@ffc04000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "snps,designware-i2c";
+                       reg = <0xffc04000 0x1000>;
+                       clocks = <&l4_sp_clk>;
+                       interrupts = <0 158 0x4>;
+                       status = "disabled";
+               };
+
+               i2c1: i2c@ffc05000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "snps,designware-i2c";
+                       reg = <0xffc05000 0x1000>;
+                       clocks = <&l4_sp_clk>;
+                       interrupts = <0 159 0x4>;
+                       status = "disabled";
+               };
+
+               i2c2: i2c@ffc06000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "snps,designware-i2c";
+                       reg = <0xffc06000 0x1000>;
+                       clocks = <&l4_sp_clk>;
+                       interrupts = <0 160 0x4>;
+                       status = "disabled";
+               };
+
+               i2c3: i2c@ffc07000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "snps,designware-i2c";
+                       reg = <0xffc07000 0x1000>;
+                       clocks = <&l4_sp_clk>;
+                       interrupts = <0 161 0x4>;
+                       status = "disabled";
+               };
+
+               gpio0: gpio@ff708000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "snps,dw-apb-gpio";
+                       reg = <0xff708000 0x1000>;
+                       clocks = <&per_base_clk>;
+                       status = "disabled";
+
+                       porta: gpio-controller@0 {
+                               compatible = "snps,dw-apb-gpio-port";
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               snps,nr-gpios = <29>;
+                               reg = <0>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               interrupts = <0 164 4>;
+                       };
+               };
+
+               gpio1: gpio@ff709000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "snps,dw-apb-gpio";
+                       reg = <0xff709000 0x1000>;
+                       clocks = <&per_base_clk>;
+                       status = "disabled";
+
+                       portb: gpio-controller@0 {
+                               compatible = "snps,dw-apb-gpio-port";
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               snps,nr-gpios = <29>;
+                               reg = <0>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               interrupts = <0 165 4>;
+                       };
+               };
+
+               gpio2: gpio@ff70a000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "snps,dw-apb-gpio";
+                       reg = <0xff70a000 0x1000>;
+                       clocks = <&per_base_clk>;
+                       status = "disabled";
+
+                       portc: gpio-controller@0 {
+                               compatible = "snps,dw-apb-gpio-port";
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               snps,nr-gpios = <27>;
+                               reg = <0>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               interrupts = <0 166 4>;
+                       };
+               };
+
+               sdr: sdr@ffc25000 {
+                       compatible = "syscon";
+                       reg = <0xffc25000 0x1000>;
+               };
+
+               sdramedac {
+                       compatible = "altr,sdram-edac";
+                       altr,sdr-syscon = <&sdr>;
+                       interrupts = <0 39 4>;
+               };
+
+               L2: l2-cache@fffef000 {
+                       compatible = "arm,pl310-cache";
+                       reg = <0xfffef000 0x1000>;
+                       interrupts = <0 38 0x04>;
+                       cache-unified;
+                       cache-level = <2>;
+                       arm,tag-latency = <1 1 1>;
+                       arm,data-latency = <2 1 1>;
+               };
+
+               mmc: dwmmc0@ff704000 {
+                       compatible = "altr,socfpga-dw-mshc";
+                       reg = <0xff704000 0x1000>;
+                       interrupts = <0 139 4>;
+                       fifo-depth = <0x400>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       clocks = <&l4_mp_clk>, <&sdmmc_clk>;
+                       clock-names = "biu", "ciu";
+               };
+
+               /* Local timer */
+               timer@fffec600 {
+                       compatible = "arm,cortex-a9-twd-timer";
+                       reg = <0xfffec600 0x100>;
+                       interrupts = <1 13 0xf04>;
+                       clocks = <&mpu_periph_clk>;
+               };
+
+               timer0: timer0@ffc08000 {
+                       compatible = "snps,dw-apb-timer";
+                       interrupts = <0 167 4>;
+                       reg = <0xffc08000 0x1000>;
+                       clocks = <&l4_sp_clk>;
+                       clock-names = "timer";
+               };
+
+               timer1: timer1@ffc09000 {
+                       compatible = "snps,dw-apb-timer";
+                       interrupts = <0 168 4>;
+                       reg = <0xffc09000 0x1000>;
+                       clocks = <&l4_sp_clk>;
+                       clock-names = "timer";
+               };
+
+               timer2: timer2@ffd00000 {
+                       compatible = "snps,dw-apb-timer";
+                       interrupts = <0 169 4>;
+                       reg = <0xffd00000 0x1000>;
+                       clocks = <&osc1>;
+                       clock-names = "timer";
+               };
+
+               timer3: timer3@ffd01000 {
+                       compatible = "snps,dw-apb-timer";
+                       interrupts = <0 170 4>;
+                       reg = <0xffd01000 0x1000>;
+                       clocks = <&osc1>;
+                       clock-names = "timer";
+               };
+
+               uart0: serial0@ffc02000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0xffc02000 0x1000>;
+                       interrupts = <0 162 4>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       clocks = <&l4_sp_clk>;
+               };
+
+               uart1: serial1@ffc03000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0xffc03000 0x1000>;
+                       interrupts = <0 163 4>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       clocks = <&l4_sp_clk>;
+               };
+
+               rst: rstmgr@ffd05000 {
+                       #reset-cells = <1>;
+                       compatible = "altr,rst-mgr";
+                       reg = <0xffd05000 0x1000>;
+               };
+
+               usbphy0: usbphy@0 {
+                       #phy-cells = <0>;
+                       compatible = "usb-nop-xceiv";
+                       status = "okay";
+               };
+
+               usb0: usb@ffb00000 {
+                       compatible = "snps,dwc2";
+                       reg = <0xffb00000 0xffff>;
+                       interrupts = <0 125 4>;
+                       clocks = <&usb_mp_clk>;
+                       clock-names = "otg";
+                       phys = <&usbphy0>;
+                       phy-names = "usb2-phy";
+                       status = "disabled";
+               };
+
+               usb1: usb@ffb40000 {
+                       compatible = "snps,dwc2";
+                       reg = <0xffb40000 0xffff>;
+                       interrupts = <0 128 4>;
+                       clocks = <&usb_mp_clk>;
+                       clock-names = "otg";
+                       phys = <&usbphy0>;
+                       phy-names = "usb2-phy";
+                       status = "disabled";
+               };
+
+               watchdog0: watchdog@ffd02000 {
+                       compatible = "snps,dw-wdt";
+                       reg = <0xffd02000 0x1000>;
+                       interrupts = <0 171 4>;
+                       clocks = <&osc1>;
+                       status = "disabled";
+               };
+
+               watchdog1: watchdog@ffd03000 {
+                       compatible = "snps,dw-wdt";
+                       reg = <0xffd03000 0x1000>;
+                       interrupts = <0 172 4>;
+                       clocks = <&osc1>;
+                       status = "disabled";
+               };
+
+               sysmgr: sysmgr@ffd08000 {
+                       compatible = "altr,sys-mgr", "syscon";
+                       reg = <0xffd08000 0x4000>;
+               };
+       };
+};
diff --git a/arch/arm/dts/socfpga_cyclone5.dtsi b/arch/arm/dts/socfpga_cyclone5.dtsi
new file mode 100644 (file)
index 0000000..28c05e7
--- /dev/null
@@ -0,0 +1,51 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/dts-v1/;
+/* First 4KB has trampoline code for secondary cores. */
+/memreserve/ 0x00000000 0x0001000;
+#include "socfpga.dtsi"
+
+/ {
+       soc {
+               clkmgr@ffd04000 {
+                       clocks {
+                               osc1 {
+                                       clock-frequency = <25000000>;
+                               };
+                       };
+               };
+
+               mmc0: dwmmc0@ff704000 {
+                       num-slots = <1>;
+                       broken-cd;
+                       bus-width = <4>;
+                       cap-mmc-highspeed;
+                       cap-sd-highspeed;
+               };
+
+               ethernet@ff702000 {
+                       phy-mode = "rgmii";
+                       phy-addr = <0xffffffff>; /* probe for phy addr */
+                       status = "okay";
+               };
+
+               sysmgr@ffd08000 {
+                       cpu1-start-addr = <0xffd080c4>;
+               };
+       };
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts
new file mode 100644 (file)
index 0000000..a1814b4
--- /dev/null
@@ -0,0 +1,50 @@
+/*
+ *  Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+       model = "EBV SOCrates";
+       compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga";
+
+       chosen {
+               bootargs = "console=ttyS0,115200";
+       };
+
+       memory {
+               name = "memory";
+               device_type = "memory";
+               reg = <0x0 0x40000000>; /* 1GB */
+       };
+};
+
+&gmac1 {
+       status = "okay";
+};
+
+&i2c0 {
+       status = "okay";
+
+       rtc: rtc@68 {
+               compatible = "stm,m41t82";
+               reg = <0x68>;
+       };
+};
+
+&mmc {
+       status = "okay";
+};
diff --git a/arch/arm/dts/zynq-zybo.dts b/arch/arm/dts/zynq-zybo.dts
new file mode 100644 (file)
index 0000000..20e0386
--- /dev/null
@@ -0,0 +1,23 @@
+/*
+ * Digilent ZYBO board DTS
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+       model = "Zynq ZYBO Board";
+       compatible = "xlnx,zynq-zybo", "xlnx,zynq-7000";
+
+       aliases {
+               serial0 = &uart1;
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0 0x20000000>;
+       };
+};
diff --git a/arch/arm/include/asm/arch-socfpga/gpio.h b/arch/arm/include/asm/arch-socfpga/gpio.h
new file mode 100644 (file)
index 0000000..6c61f18
--- /dev/null
@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _SOCFPGA_GPIO_H
+#define _SOCFPGA_GPIO_H
+
+#endif /* _SOCFPGA_GPIO_H */
index 1857b80..034135b 100644 (file)
@@ -14,6 +14,7 @@ void socfpga_bridges_reset(int enable);
 
 void socfpga_emac_reset(int enable);
 void socfpga_watchdog_reset(void);
+void socfpga_spim_enable(void);
 
 struct socfpga_reset_manager {
        u32     status;
@@ -35,5 +36,7 @@ struct socfpga_reset_manager {
 #define RSTMGR_PERMODRST_EMAC0_LSB     0
 #define RSTMGR_PERMODRST_EMAC1_LSB     1
 #define RSTMGR_PERMODRST_L4WD0_LSB     6
+#define RSTMGR_PERMODRST_SPIM0_LSB     18
+#define RSTMGR_PERMODRST_SPIM1_LSB     19
 
 #endif /* _RESET_MANAGER_H_ */
index c1fb92a..bd64ea6 100644 (file)
@@ -38,9 +38,6 @@ config TARGET_IPEK01
 config TARGET_JUPITER
        bool "Support jupiter"
 
-config TARGET_MCC200
-       bool "Support mcc200"
-
 config TARGET_MOTIONPRO
        bool "Support motionpro"
 
@@ -130,7 +127,6 @@ source "board/jupiter/Kconfig"
 source "board/manroland/hmi1001/Kconfig"
 source "board/manroland/mucmc52/Kconfig"
 source "board/manroland/uc101/Kconfig"
-source "board/mcc200/Kconfig"
 source "board/motionpro/Kconfig"
 source "board/munices/Kconfig"
 source "board/phytec/pcm030/Kconfig"
index f94a444..98aa10a 100644 (file)
@@ -1,23 +1,15 @@
 if TARGET_DB_MV784MP_GP
 
-config SYS_CPU
-       string
-       default "armv7"
-
 config SYS_BOARD
-       string
        default "db-mv784mp-gp"
 
 config SYS_VENDOR
-       string
        default "Marvell"
 
 config SYS_SOC
-       string
        default "armada-xp"
 
 config SYS_CONFIG_NAME
-       string
        default "db-mv784mp-gp"
 
 endif
index 0f81d89..ce625e5 100644 (file)
@@ -8,6 +8,10 @@
 #include <asm/arch/reset_manager.h>
 #include <asm/io.h>
 
+#include <usb.h>
+#include <usb/s3c_udc.h>
+#include <usb_mass_storage.h>
+
 #include <netdev.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -39,3 +43,20 @@ int board_init(void)
 
        return 0;
 }
+
+#ifdef CONFIG_USB_GADGET
+struct s3c_plat_otg_data socfpga_otg_data = {
+       .regs_otg       = CONFIG_USB_DWC2_REG_ADDR,
+       .usb_gusbcfg    = 0x1417,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+       return s3c_udc_probe(&socfpga_otg_data);
+}
+
+int g_dnl_board_usb_cable_connected(void)
+{
+       return 1;
+}
+#endif
index 4ba6399..94f1754 100644 (file)
@@ -1,8 +1,5 @@
 if TARGET_KOSAGI_NOVENA
 
-config SYS_CPU
-       default "armv7"
-
 config SYS_BOARD
        default "novena"
 
index d34e2ab..d833ca0 100644 (file)
@@ -1,19 +1,12 @@
 if TARGET_MAXBCM
 
-config SYS_CPU
-       string
-       default "armv7"
-
 config SYS_BOARD
-       string
        default "maxbcm"
 
 config SYS_SOC
-       string
        default "armada-xp"
 
 config SYS_CONFIG_NAME
-       string
        default "maxbcm"
 
 endif
diff --git a/board/mcc200/Kconfig b/board/mcc200/Kconfig
deleted file mode 100644 (file)
index 3b27eeb..0000000
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_MCC200
-
-config SYS_BOARD
-       default "mcc200"
-
-config SYS_CONFIG_NAME
-       default "mcc200"
-
-endif
diff --git a/board/mcc200/MAINTAINERS b/board/mcc200/MAINTAINERS
deleted file mode 100644 (file)
index a59a498..0000000
+++ /dev/null
@@ -1,17 +0,0 @@
-MCC200 BOARD
-#M:    -
-S:     Maintained
-F:     board/mcc200/
-F:     include/configs/mcc200.h
-F:     configs/mcc200_defconfig
-F:     configs/mcc200_COM12_defconfig
-F:     configs/mcc200_COM12_highboot_defconfig
-F:     configs/mcc200_COM12_highboot_SDRAM_defconfig
-F:     configs/mcc200_COM12_SDRAM_defconfig
-F:     configs/mcc200_highboot_defconfig
-F:     configs/mcc200_highboot_SDRAM_defconfig
-F:     configs/mcc200_SDRAM_defconfig
-F:     configs/prs200_defconfig
-F:     configs/prs200_DDR_defconfig
-F:     configs/prs200_highboot_defconfig
-F:     configs/prs200_highboot_DDR_defconfig
diff --git a/board/mcc200/Makefile b/board/mcc200/Makefile
deleted file mode 100644 (file)
index db3b396..0000000
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y  := mcc200.o lcd.o auto_update.o
diff --git a/board/mcc200/auto_update.c b/board/mcc200/auto_update.c
deleted file mode 100644 (file)
index 43173ce..0000000
+++ /dev/null
@@ -1,521 +0,0 @@
-/*
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-#include <common.h>
-#include <command.h>
-#include <malloc.h>
-#include <image.h>
-#include <asm/byteorder.h>
-#include <usb.h>
-#include <part.h>
-
-#ifdef CONFIG_AUTO_UPDATE
-
-#ifndef CONFIG_USB_OHCI
-#error "must define CONFIG_USB_OHCI"
-#endif
-
-#ifndef CONFIG_USB_STORAGE
-#error "must define CONFIG_USB_STORAGE"
-#endif
-
-#ifndef CONFIG_SYS_HUSH_PARSER
-#error "must define CONFIG_SYS_HUSH_PARSER"
-#endif
-
-#if !defined(CONFIG_CMD_FAT)
-#error "must define CONFIG_CMD_FAT"
-#endif
-
-#undef AU_DEBUG
-
-#undef debug
-#ifdef AU_DEBUG
-#define debug(fmt,args...)     printf (fmt ,##args)
-#else
-#define debug(fmt,args...)
-#endif /* AU_DEBUG */
-
-/* possible names of files on the USB stick. */
-#define AU_FIRMWARE    "u-boot.img"
-#define AU_KERNEL      "kernel.img"
-#define AU_ROOTFS      "rootfs.img"
-
-struct flash_layout {
-       long start;
-       long end;
-};
-
-/* layout of the FLASH. ST = start address, ND = end address. */
-#define AU_FL_FIRMWARE_ST      0xfC000000
-#define AU_FL_FIRMWARE_ND      0xfC03FFFF
-#define AU_FL_KERNEL_ST                0xfC0C0000
-#define AU_FL_KERNEL_ND                0xfC1BFFFF
-#define AU_FL_ROOTFS_ST                0xFC1C0000
-#define AU_FL_ROOTFS_ND                0xFCFBFFFF
-
-static int au_usb_stor_curr_dev; /* current device */
-
-/* index of each file in the following arrays */
-#define IDX_FIRMWARE   0
-#define IDX_KERNEL     1
-#define IDX_ROOTFS     2
-
-/* max. number of files which could interest us */
-#define AU_MAXFILES 3
-
-/* pointers to file names */
-char *aufile[AU_MAXFILES] = {
-       AU_FIRMWARE,
-       AU_KERNEL,
-       AU_ROOTFS
-};
-
-/* sizes of flash areas for each file */
-long ausize[AU_MAXFILES] = {
-       (AU_FL_FIRMWARE_ND + 1) - AU_FL_FIRMWARE_ST,
-       (AU_FL_KERNEL_ND   + 1) - AU_FL_KERNEL_ST,
-       (AU_FL_ROOTFS_ND   + 1) - AU_FL_ROOTFS_ST,
-};
-
-/* array of flash areas start and end addresses */
-struct flash_layout aufl_layout[AU_MAXFILES] = {
-       { AU_FL_FIRMWARE_ST,    AU_FL_FIRMWARE_ND, },
-       { AU_FL_KERNEL_ST,      AU_FL_KERNEL_ND,   },
-       { AU_FL_ROOTFS_ST,      AU_FL_ROOTFS_ND,   },
-};
-
-ulong totsize;
-
-/* where to load files into memory */
-#define LOAD_ADDR ((unsigned char *)0x00200000)
-
-/* the root file system is the largest image */
-#define MAX_LOADSZ ausize[IDX_ROOTFS]
-
-/*i2c address of the keypad status*/
-#define I2C_PSOC_KEYPAD_ADDR   0x53
-
-/* keypad mask */
-#define KEYPAD_ROW     2
-#define KEYPAD_COL     2
-#define KEYPAD_MASK_LO ((1<<(KEYPAD_COL-1+(KEYPAD_ROW*3-3)))&0xFF)
-#define KEYPAD_MASK_HI ((1<<(KEYPAD_COL-1+(KEYPAD_ROW*3-3)))>>8)
-
-/* externals */
-extern int fat_register_device(block_dev_desc_t *, int);
-extern int file_fat_detectfs(void);
-extern long file_fat_read(const char *, void *, unsigned long);
-extern int i2c_read (unsigned char, unsigned int, int , unsigned char* , int);
-extern int flash_sect_erase(ulong, ulong);
-extern int flash_sect_protect (int, ulong, ulong);
-extern int flash_write (char *, ulong, ulong);
-extern int u_boot_hush_start(void);
-#ifdef CONFIG_PROGRESSBAR
-extern void show_progress(int, int);
-extern void lcd_puts (char *);
-extern void lcd_enable(void);
-#endif
-
-int au_check_cksum_valid(int idx, long nbytes)
-{
-       image_header_t *hdr;
-
-       hdr = (image_header_t *)LOAD_ADDR;
-#if defined(CONFIG_FIT)
-       if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
-               puts ("Non legacy image format not supported\n");
-               return -1;
-       }
-#endif
-
-       if (nbytes != image_get_image_size (hdr)) {
-               printf ("Image %s bad total SIZE\n", aufile[idx]);
-               return -1;
-       }
-       /* check the data CRC */
-       if (!image_check_dcrc (hdr)) {
-               printf ("Image %s bad data checksum\n", aufile[idx]);
-               return -1;
-       }
-       return 0;
-}
-
-int au_check_header_valid(int idx, long nbytes)
-{
-       image_header_t *hdr;
-       unsigned long checksum, fsize;
-
-       hdr = (image_header_t *)LOAD_ADDR;
-#if defined(CONFIG_FIT)
-       if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
-               puts ("Non legacy image format not supported\n");
-               return -1;
-       }
-#endif
-
-       /* check the easy ones first */
-#undef CHECK_VALID_DEBUG
-#ifdef CHECK_VALID_DEBUG
-       printf("magic %#x %#x ", image_get_magic (hdr), IH_MAGIC);
-       printf("arch %#x %#x ", image_get_arch (hdr), IH_ARCH_ARM);
-       printf("size %#x %#lx ", image_get_data_size (hdr), nbytes);
-       printf("type %#x %#x ", image_get_type (hdr), IH_TYPE_KERNEL);
-#endif
-       if (nbytes < image_get_header_size ()) {
-               printf ("Image %s bad header SIZE\n", aufile[idx]);
-               ausize[idx] = 0;
-               return -1;
-       }
-       if (!image_check_magic (hdr) || !image_check_arch (hdr, IH_ARCH_PPC)) {
-               printf ("Image %s bad MAGIC or ARCH\n", aufile[idx]);
-               ausize[idx] = 0;
-               return -1;
-       }
-       /* check the hdr CRC */
-       if (!image_check_hcrc (hdr)) {
-               printf ("Image %s bad header checksum\n", aufile[idx]);
-               ausize[idx] = 0;
-               return -1;
-       }
-       /* check the type - could do this all in one gigantic if() */
-       if ((idx == IDX_FIRMWARE) && !image_check_type (hdr, IH_TYPE_FIRMWARE)) {
-               printf ("Image %s wrong type\n", aufile[idx]);
-               ausize[idx] = 0;
-               return -1;
-       }
-       if ((idx == IDX_KERNEL) && !image_check_type (hdr, IH_TYPE_KERNEL)) {
-               printf ("Image %s wrong type\n", aufile[idx]);
-               ausize[idx] = 0;
-               return -1;
-       }
-       if ((idx == IDX_ROOTFS) &&
-                       (!image_check_type (hdr, IH_TYPE_RAMDISK) &&
-                       !image_check_type (hdr, IH_TYPE_FILESYSTEM))) {
-               printf ("Image %s wrong type\n", aufile[idx]);
-               ausize[idx] = 0;
-               return -1;
-       }
-       /* recycle checksum */
-       checksum = image_get_data_size (hdr);
-
-       fsize = checksum + image_get_header_size ();
-       /* for kernel and ramdisk the image header must also fit into flash */
-       if (idx == IDX_KERNEL || image_check_type (hdr, IH_TYPE_RAMDISK))
-               checksum += image_get_header_size ();
-
-       /* check the size does not exceed space in flash. HUSH scripts */
-       if ((ausize[idx] != 0) && (ausize[idx] < checksum)) {
-               printf ("Image %s is bigger than FLASH\n", aufile[idx]);
-               ausize[idx] = 0;
-               return -1;
-       }
-       /* Update with the real filesize */
-       ausize[idx] = fsize;
-
-       return checksum; /* return size to be written to flash */
-}
-
-int au_do_update(int idx, long sz)
-{
-       image_header_t *hdr;
-       char *addr;
-       long start, end;
-       int off, rc;
-       uint nbytes;
-
-       hdr = (image_header_t *)LOAD_ADDR;
-#if defined(CONFIG_FIT)
-       if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
-               puts ("Non legacy image format not supported\n");
-               return -1;
-       }
-#endif
-
-       /* execute a script */
-       if (image_check_type (hdr, IH_TYPE_SCRIPT)) {
-               addr = (char *)((char *)hdr + image_get_header_size ());
-               /* stick a NULL at the end of the script, otherwise */
-               /* parse_string_outer() runs off the end. */
-               addr[image_get_data_size (hdr)] = 0;
-               addr += 8;
-               run_command_list(addr, -1, 0);
-               return 0;
-       }
-
-       start = aufl_layout[idx].start;
-       end = aufl_layout[idx].end;
-
-       /* unprotect the address range */
-       /* this assumes that ONLY the firmware is protected! */
-       if (idx == IDX_FIRMWARE) {
-#undef AU_UPDATE_TEST
-#ifdef AU_UPDATE_TEST
-               /* erase it where Linux goes */
-               start = aufl_layout[1].start;
-               end = aufl_layout[1].end;
-#endif
-               flash_sect_protect(0, start, end);
-       }
-
-       /*
-        * erase the address range.
-        */
-       debug ("flash_sect_erase(%lx, %lx);\n", start, end);
-       flash_sect_erase(start, end);
-       mdelay(100);
-#ifdef CONFIG_PROGRESSBAR
-       show_progress(end - start, totsize);
-#endif
-
-       /* strip the header - except for the kernel and ramdisk */
-       if (image_check_type (hdr, IH_TYPE_KERNEL) ||
-                       image_check_type (hdr, IH_TYPE_RAMDISK)) {
-               addr = (char *)hdr;
-               off = image_get_header_size ();
-               nbytes = image_get_image_size (hdr);
-       } else {
-               addr = (char *)((char *)hdr + image_get_header_size ());
-#ifdef AU_UPDATE_TEST
-               /* copy it to where Linux goes */
-               if (idx == IDX_FIRMWARE)
-                       start = aufl_layout[1].start;
-#endif
-               off = 0;
-               nbytes = image_get_data_size (hdr);
-       }
-
-       /* copy the data from RAM to FLASH */
-       debug ("flash_write(%p, %lx %x)\n", addr, start, nbytes);
-       rc = flash_write(addr, start, nbytes);
-       if (rc != 0) {
-               printf("Flashing failed due to error %d\n", rc);
-               return -1;
-       }
-
-#ifdef CONFIG_PROGRESSBAR
-       show_progress(nbytes, totsize);
-#endif
-
-       /* check the data CRC of the copy */
-       if (crc32 (0, (uchar *)(start + off), image_get_data_size (hdr)) !=
-           image_get_dcrc (hdr)) {
-               printf ("Image %s Bad Data Checksum after COPY\n", aufile[idx]);
-               return -1;
-       }
-
-       /* protect the address range */
-       /* this assumes that ONLY the firmware is protected! */
-       if (idx == IDX_FIRMWARE)
-               flash_sect_protect(1, start, end);
-       return 0;
-}
-
-/*
- * this is called from board_init() after the hardware has been set up
- * and is usable. That seems like a good time to do this.
- * Right now the return value is ignored.
- */
-int do_auto_update(void)
-{
-       block_dev_desc_t *stor_dev;
-       long sz;
-       int i, res = 0, cnt, old_ctrlc;
-       char *env;
-       long start, end;
-
-#if 0 /* disable key-press detection to speed up boot-up time */
-       uchar keypad_status1[2] = {0,0}, keypad_status2[2] = {0,0};
-
-       /*
-        * Read keypad status
-        */
-       i2c_read(I2C_PSOC_KEYPAD_ADDR, 0, 0, keypad_status1, 2);
-       mdelay(500);
-       i2c_read(I2C_PSOC_KEYPAD_ADDR, 0, 0, keypad_status2, 2);
-
-       /*
-        * Check keypad
-        */
-       if ( !(keypad_status1[1] & KEYPAD_MASK_LO) ||
-             (keypad_status1[1] != keypad_status2[1])) {
-               return 0;
-       }
-
-#endif
-       au_usb_stor_curr_dev = -1;
-       /* start USB */
-       if (usb_stop() < 0) {
-               debug ("usb_stop failed\n");
-               return -1;
-       }
-       if (usb_init() < 0) {
-               debug ("usb_init failed\n");
-               return -1;
-       }
-       /*
-        * check whether a storage device is attached (assume that it's
-        * a USB memory stick, since nothing else should be attached).
-        */
-       au_usb_stor_curr_dev = usb_stor_scan(0);
-       if (au_usb_stor_curr_dev == -1) {
-               debug ("No device found. Not initialized?\n");
-               res = -1;
-               goto xit;
-       }
-       /* check whether it has a partition table */
-       stor_dev = get_dev("usb", 0);
-       if (stor_dev == NULL) {
-               debug ("uknown device type\n");
-               res = -1;
-               goto xit;
-       }
-       if (fat_register_device(stor_dev, 1) != 0) {
-               debug ("Unable to use USB %d:%d for fatls\n",
-                       au_usb_stor_curr_dev, 1);
-               res = -1;
-               goto xit;
-       }
-       if (file_fat_detectfs() != 0) {
-               debug ("file_fat_detectfs failed\n");
-       }
-
-       /*
-        * now check whether start and end are defined using environment
-        * variables.
-        */
-       start = -1;
-       end = 0;
-       env = getenv("firmware_st");
-       if (env != NULL)
-               start = simple_strtoul(env, NULL, 16);
-       env = getenv("firmware_nd");
-       if (env != NULL)
-               end = simple_strtoul(env, NULL, 16);
-       if (start >= 0 && end && end > start) {
-               ausize[IDX_FIRMWARE] = (end + 1) - start;
-               aufl_layout[IDX_FIRMWARE].start = start;
-               aufl_layout[IDX_FIRMWARE].end = end;
-       }
-       start = -1;
-       end = 0;
-       env = getenv("kernel_st");
-       if (env != NULL)
-               start = simple_strtoul(env, NULL, 16);
-       env = getenv("kernel_nd");
-       if (env != NULL)
-               end = simple_strtoul(env, NULL, 16);
-       if (start >= 0 && end && end > start) {
-               ausize[IDX_KERNEL] = (end + 1) - start;
-               aufl_layout[IDX_KERNEL].start = start;
-               aufl_layout[IDX_KERNEL].end = end;
-       }
-       start = -1;
-       end = 0;
-       env = getenv("rootfs_st");
-       if (env != NULL)
-               start = simple_strtoul(env, NULL, 16);
-       env = getenv("rootfs_nd");
-       if (env != NULL)
-               end = simple_strtoul(env, NULL, 16);
-       if (start >= 0 && end && end > start) {
-               ausize[IDX_ROOTFS] = (end + 1) - start;
-               aufl_layout[IDX_ROOTFS].start = start;
-               aufl_layout[IDX_ROOTFS].end = end;
-       }
-
-       /* make certain that HUSH is runnable */
-       u_boot_hush_start();
-       /* make sure that we see CTRL-C and save the old state */
-       old_ctrlc = disable_ctrlc(0);
-
-       /* validate the images first */
-       for (i = 0; i < AU_MAXFILES; i++) {
-               ulong imsize;
-               /* just read the header */
-               sz = file_fat_read(aufile[i], LOAD_ADDR, image_get_header_size ());
-               debug ("read %s sz %ld hdr %d\n",
-                       aufile[i], sz, image_get_header_size ());
-               if (sz <= 0 || sz < image_get_header_size ()) {
-                       debug ("%s not found\n", aufile[i]);
-                       ausize[i] = 0;
-                       continue;
-               }
-               /* au_check_header_valid() updates ausize[] */
-               if ((imsize = au_check_header_valid(i, sz)) < 0) {
-                       debug ("%s header not valid\n", aufile[i]);
-                       continue;
-               }
-               /* totsize accounts for image size and flash erase size */
-               totsize += (imsize + (aufl_layout[i].end - aufl_layout[i].start));
-       }
-
-#ifdef CONFIG_PROGRESSBAR
-       if (totsize) {
-               lcd_puts(" Update in progress\n");
-               lcd_enable();
-       }
-#endif
-
-       /* just loop thru all the possible files */
-       for (i = 0; i < AU_MAXFILES && totsize; i++) {
-               if (!ausize[i]) {
-                       continue;
-               }
-               sz = file_fat_read(aufile[i], LOAD_ADDR, ausize[i]);
-
-               debug ("read %s sz %ld hdr %d\n",
-                       aufile[i], sz, image_get_header_size ());
-
-               if (sz != ausize[i]) {
-                       printf ("%s: size %ld read %ld?\n", aufile[i], ausize[i], sz);
-                       continue;
-               }
-
-               if (sz <= 0 || sz <= image_get_header_size ()) {
-                       debug ("%s not found\n", aufile[i]);
-                       continue;
-               }
-               if (au_check_cksum_valid(i, sz) < 0) {
-                       debug ("%s checksum not valid\n", aufile[i]);
-                       continue;
-               }
-               /* this is really not a good idea, but it's what the */
-               /* customer wants. */
-               cnt = 0;
-               do {
-                       res = au_do_update(i, sz);
-                       /* let the user break out of the loop */
-                       if (ctrlc() || had_ctrlc()) {
-                               clear_ctrlc();
-                               break;
-                       }
-                       cnt++;
-#ifdef AU_TEST_ONLY
-               } while (res < 0 && cnt < (AU_MAXFILES + 1));
-               if (cnt < (AU_MAXFILES + 1))
-#else
-               } while (res < 0);
-#endif
-       }
-
-       /* restore the old state */
-       disable_ctrlc(old_ctrlc);
-#ifdef CONFIG_PROGRESSBAR
-       if (totsize) {
-               if (!res) {
-                       lcd_puts("\n  Update completed\n");
-               } else {
-                       lcd_puts("\n   Update error\n");
-               }
-               lcd_enable();
-       }
-#endif
- xit:
-       usb_stop();
-       return res;
-}
-#endif /* CONFIG_AUTO_UPDATE */
diff --git a/board/mcc200/lcd.c b/board/mcc200/lcd.c
deleted file mode 100644 (file)
index c911445..0000000
+++ /dev/null
@@ -1,200 +0,0 @@
-/*
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <lcd.h>
-#include <mpc5xxx.h>
-#include <malloc.h>
-
-#ifdef CONFIG_LCD
-
-#undef SWAPPED_LCD /* For the previous h/w version */
-/*
- *  The name of the device used for communication
- * with the PSoC.
- */
-#define PSOC_PSC       MPC5XXX_PSC2
-#define PSOC_BAUD      230400UL
-
-#define RTS_ASSERT     1
-#define RTS_NEGATE     0
-#define CTS_ASSERT     1
-#define CTS_NEGATE     0
-
-/*
- * Dimensions in pixels
- */
-#define LCD_WIDTH      160
-#define LCD_HEIGHT     100
-
-/*
- * Dimensions in bytes
- */
-#define LCD_BUF_SIZE   ((LCD_WIDTH*LCD_HEIGHT)>>3)
-
-#if LCD_BPP != LCD_MONOCHROME
-#error "MCC200 support only monochrome displays (1 bpp)!"
-#endif
-
-#define PSOC_RETRIES   10      /* each of PSOC_WAIT_TIME */
-#define PSOC_WAIT_TIME 10      /* usec */
-
-#include <video_font.h>
-#define FONT_WIDTH     VIDEO_FONT_WIDTH
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * LCD information
- */
-vidinfo_t panel_info = {
-       LCD_WIDTH, LCD_HEIGHT, LCD_BPP
-};
-
-
-/*
- *  The device we use to communicate with PSoC
- */
-int serial_inited = 0;
-
-/*
- *  Imported functions to support the PSoC protocol
- */
-extern int serial_init_dev (unsigned long dev_base);
-extern void serial_setrts_dev (unsigned long dev_base, int s);
-extern int serial_getcts_dev (unsigned long dev_base);
-extern void serial_putc_raw_dev(unsigned long dev_base, const char c);
-
-/*
- *  Just stubs for our driver, needed for compiling compabilty with
- * the common LCD driver code.
- */
-void lcd_initcolregs (void)
-{
-}
-
-void lcd_ctrl_init (void *lcdbase)
-{
-}
-
-/*
- * Function sends the contents of the frame-buffer to the LCD
- */
-void lcd_enable (void)
-{
-       int i, retries, fb_size;
-
-       if (!serial_inited) {
-               unsigned long baud;
-
-               baud = gd->baudrate;
-               gd->baudrate = PSOC_BAUD;
-               serial_init_dev(PSOC_PSC);
-               gd->baudrate = baud;
-               serial_setrts_dev (PSOC_PSC, RTS_ASSERT);
-               serial_inited = 1;
-       }
-
-       /*
-        *  Implement PSoC communication protocol:
-        * 1. Assert RTS, wait CTS assertion
-        * 2. Transmit data
-        * 3. Negate RTS, wait CTS negation
-        */
-
-       /* 1 */
-       serial_setrts_dev (PSOC_PSC, RTS_ASSERT);
-       for (retries = PSOC_RETRIES; retries; retries--) {
-               if (serial_getcts_dev(PSOC_PSC) == CTS_ASSERT)
-                       break;
-               udelay (PSOC_WAIT_TIME);
-       }
-       if (!retries) {
-               printf ("%s Error: PSoC doesn't respond on "
-                       "RTS ASSERT\n", __FUNCTION__);
-       }
-
-       /* 2 */
-       fb_size = panel_info.vl_row * (panel_info.vl_col >> 3);
-
-#if !defined(SWAPPED_LCD)
-       for (i=0; i<fb_size; i++) {
-               serial_putc_raw_dev(PSOC_PSC, ((char *)gd->fb_base)[i]);
-       }
-#else
-    {
-       int x, y, pwidth;
-       char *p = (char *)gd->fb_base;
-
-       pwidth = ((panel_info.vl_col+7) >> 3);
-       for (y=0; y<panel_info.vl_row; y++) {
-               i = y * pwidth;
-               for (x=0; x<pwidth; x+=5) {
-                       serial_putc_raw_dev (PSOC_PSC, (p[i+x+2]<<4 & 0xF0) | (p[i+x+3]>>4 & 0x0F));
-                       serial_putc_raw_dev (PSOC_PSC, (p[i+x+3]<<4 & 0xF0) | (p[i+x+4]>>4 & 0x0F));
-                       serial_putc_raw_dev (PSOC_PSC, (p[i+x+4]<<4 & 0xF0) | (p[i+x]>>4 & 0x0F));
-                       serial_putc_raw_dev (PSOC_PSC, (p[i+x]<<4 & 0xF0) | (p[i+x+1]>>4 & 0x0F));
-                       serial_putc_raw_dev (PSOC_PSC, (p[i+x+1]<<4 & 0xF0) | (p[i+x+2]>>4 & 0x0F));
-               }
-       }
-    }
-#endif
-
-       /* 3 */
-       serial_setrts_dev (PSOC_PSC, RTS_NEGATE);
-       for (retries = PSOC_RETRIES; retries; retries--) {
-               if (serial_getcts_dev(PSOC_PSC) == CTS_NEGATE)
-                       break;
-               udelay (PSOC_WAIT_TIME);
-       }
-
-       return;
-}
-#ifdef CONFIG_PROGRESSBAR
-
-void show_progress (int size, int tot)
-{
-       int cnt;
-       int i;
-       static int rc = 0;
-
-       rc += size;
-
-       cnt = ((LCD_WIDTH/FONT_WIDTH) * rc) / tot;
-
-       rc -= (cnt * tot) / (LCD_WIDTH/FONT_WIDTH);
-
-       for (i = 0; i < cnt; i++) {
-               lcd_putc(0xdc);
-       }
-
-       if (cnt) {
-               lcd_enable(); /* MCC200-specific - send the framebuffer to PSoC */
-       }
-}
-
-#endif
-
-int bmp_display(ulong addr, int x, int y)
-{
-       int ret;
-       bmp_image_t *bmp = (bmp_image_t *)addr;
-
-       if (!bmp) {
-               printf("There is no valid bmp file at the given address\n");
-               return 1;
-       }
-
-       ret = lcd_display_bitmap((ulong)bmp, x, y);
-
-       if ((unsigned long)bmp != addr)
-               free(bmp);
-
-       return ret;
-}
-
-#endif /* CONFIG_LCD */
diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c
deleted file mode 100644 (file)
index 706886b..0000000
+++ /dev/null
@@ -1,314 +0,0 @@
-/*
- * (C) Copyright 2003-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <asm/processor.h>
-
-/* Two MT48LC8M32B2 for 32 MB */
-/* #include "mt48lc8m32b2-6-7.h" */
-
-/* One MT48LC16M32S2 for 64 MB */
-/* #include "mt48lc16m32s2-75.h" */
-#if defined (CONFIG_MCC200_SDRAM)
-#include "mt48lc16m16a2-75.h"
-#else
-#include "mt46v16m16-75.h"
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern flash_info_t flash_info[];      /* FLASH chips info */
-
-extern int do_auto_update(void);
-ulong flash_get_size (ulong base, int banknum);
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start (int hi_addr)
-{
-       long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
-       /* unlock mode register */
-       *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
-       __asm__ volatile ("sync");
-
-       /* precharge all banks */
-       *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
-       __asm__ volatile ("sync");
-
-#if SDRAM_DDR
-       /* set mode register: extended mode */
-       *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
-       __asm__ volatile ("sync");
-
-       /* set mode register: reset DLL */
-       *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
-       __asm__ volatile ("sync");
-#endif
-
-       /* precharge all banks */
-       *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
-       __asm__ volatile ("sync");
-
-       /* auto refresh */
-       *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
-       __asm__ volatile ("sync");
-
-       /* set mode register */
-       *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
-       __asm__ volatile ("sync");
-
-       /* normal operation */
-       *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
-       __asm__ volatile ("sync");
-
-       udelay(10);
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
- *           use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- *           is something else than 0x00000000.
- */
-
-phys_size_t initdram (int board_type)
-{
-       ulong dramsize = 0;
-       ulong dramsize2 = 0;
-       uint svr, pvr;
-#ifndef CONFIG_SYS_RAMBOOT
-       ulong test1, test2;
-
-       /* setup SDRAM chip selects */
-       *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
-       *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
-       __asm__ volatile ("sync");
-
-       /* setup config registers */
-       *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
-       *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-       __asm__ volatile ("sync");
-
-#if SDRAM_DDR
-       /* set tap delay */
-       *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
-       __asm__ volatile ("sync");
-#endif
-
-       /* find RAM size using SDRAM CS0 only */
-       sdram_start(0);
-       test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-       sdram_start(1);
-       test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-       if (test1 > test2) {
-               sdram_start(0);
-               dramsize = test1;
-       } else {
-               dramsize = test2;
-       }
-
-       /* memory smaller than 1MB is impossible */
-       if (dramsize < (1 << 20)) {
-               dramsize = 0;
-       }
-
-       /* set SDRAM CS0 size according to the amount of RAM found */
-       if (dramsize > 0) {
-               *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
-       } else {
-               *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
-       }
-
-       /* let SDRAM CS1 start right after CS0 */
-       *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
-
-       /* find RAM size using SDRAM CS1 only */
-       if (!dramsize)
-               sdram_start(0);
-       test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
-       if (!dramsize) {
-               sdram_start(1);
-               test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
-       }
-       if (test1 > test2) {
-               sdram_start(0);
-               dramsize2 = test1;
-       } else {
-               dramsize2 = test2;
-       }
-
-       /* memory smaller than 1MB is impossible */
-       if (dramsize2 < (1 << 20)) {
-               dramsize2 = 0;
-       }
-
-       /* set SDRAM CS1 size according to the amount of RAM found */
-       if (dramsize2 > 0) {
-               *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
-                       | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
-       } else {
-               *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
-       }
-
-#else /* CONFIG_SYS_RAMBOOT */
-
-       /* retrieve size of memory connected to SDRAM CS0 */
-       dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
-       if (dramsize >= 0x13) {
-               dramsize = (1 << (dramsize - 0x13)) << 20;
-       } else {
-               dramsize = 0;
-       }
-
-       /* retrieve size of memory connected to SDRAM CS1 */
-       dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
-       if (dramsize2 >= 0x13) {
-               dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
-       } else {
-               dramsize2 = 0;
-       }
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-       /*
-        * On MPC5200B we need to set the special configuration delay in the
-        * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
-        * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
-        *
-        * "The SDelay should be written to a value of 0x00000004. It is
-        * required to account for changes caused by normal wafer processing
-        * parameters."
-        */
-       svr = get_svr();
-       pvr = get_pvr();
-       if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
-               *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
-               __asm__ volatile ("sync");
-       }
-
-       return dramsize + dramsize2;
-}
-
-int checkboard (void)
-{
-#if defined(CONFIG_PRS200)
-       puts ("Board: PRS200\n");
-#else
-       puts ("Board: MCC200\n");
-#endif
-       return 0;
-}
-
-int misc_init_r (void)
-{
-       ulong flash_sup_end, snum;
-
-       /*
-        * Adjust flash start and offset to detected values
-        */
-       gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
-       gd->bd->bi_flashoffset = 0;
-
-       /*
-        * Check if boot FLASH isn't max size
-        */
-       if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH_BASE)) {
-               /* adjust mapping */
-               *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
-                       START_REG(gd->bd->bi_flashstart);
-               *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
-                       STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize);
-
-               /*
-                * Re-check to get correct base address
-                */
-               flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);
-
-               /*
-                * Re-do flash protection upon new addresses
-                */
-               flash_protect (FLAG_PROTECT_CLEAR,
-                              gd->bd->bi_flashstart, 0xffffffff,
-                              &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
-
-               /* Monitor protection ON by default */
-               flash_protect (FLAG_PROTECT_SET,
-                              CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
-                              &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
-
-               /* Environment protection ON by default */
-               flash_protect (FLAG_PROTECT_SET,
-                              CONFIG_ENV_ADDR,
-                              CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
-                              &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
-
-               /* Redundant environment protection ON by default */
-               flash_protect (FLAG_PROTECT_SET,
-                              CONFIG_ENV_ADDR_REDUND,
-                              CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
-                              &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
-       }
-
-       if (gd->bd->bi_flashsize > (32 << 20)) {
-               /* Unprotect the upper bank of the Flash */
-               *(volatile int*)MPC5XXX_CS0_CFG |= (1 << 6);
-               flash_protect (FLAG_PROTECT_CLEAR,
-                              flash_info[0].start[0] + flash_info[0].size / 2,
-                              (flash_info[0].start[0] - 1) + flash_info[0].size,
-                              &flash_info[0]);
-               *(volatile int*)MPC5XXX_CS0_CFG &= ~(1 << 6);
-               printf ("Warning: Only 32 of 64 MB of Flash are accessible from U-Boot\n");
-               flash_info[0].size = 32 << 20;
-               for (snum = 0, flash_sup_end = gd->bd->bi_flashstart + (32<<20);
-                       flash_info[0].start[snum] < flash_sup_end;
-                       snum++);
-               flash_info[0].sector_count = snum;
-       }
-
-#ifdef CONFIG_AUTO_UPDATE
-       do_auto_update();
-#endif
-       return (0);
-}
-
-#ifdef CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
-       pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
-
-void init_ide_reset (void)
-{
-       debug ("init_ide_reset\n");
-
-}
-
-void ide_set_reset (int idereset)
-{
-       debug ("ide_reset(%d)\n", idereset);
-
-}
-#endif
-
-#if defined(CONFIG_CMD_DOC)
-void doc_init (void)
-{
-       doc_probe (CONFIG_SYS_DOC_BASE);
-}
-#endif
diff --git a/board/mcc200/mt46v16m16-75.h b/board/mcc200/mt46v16m16-75.h
deleted file mode 100644 (file)
index 9068fbf..0000000
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#define SDRAM_DDR      1               /* is DDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE     0x018D0000
-#define SDRAM_EMODE    0x40090000
-#define SDRAM_CONTROL  0x714f0f00
-#define SDRAM_CONFIG1  0x73722930
-#define SDRAM_CONFIG2  0x47770000
-#define SDRAM_TAPDELAY 0x10000000
diff --git a/board/mcc200/mt48lc16m16a2-75.h b/board/mcc200/mt48lc16m16a2-75.h
deleted file mode 100644 (file)
index 0133eaa..0000000
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#define SDRAM_DDR      0               /* is SDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE     0x00CD0000
-#define SDRAM_CONTROL  0x504F0000
-#define SDRAM_CONFIG1  0xD2322800
-#define SDRAM_CONFIG2  0x8AD70000
diff --git a/board/mcc200/mt48lc16m32s2-75.h b/board/mcc200/mt48lc16m32s2-75.h
deleted file mode 100644 (file)
index 0133eaa..0000000
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#define SDRAM_DDR      0               /* is SDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE     0x00CD0000
-#define SDRAM_CONTROL  0x504F0000
-#define SDRAM_CONFIG1  0xD2322800
-#define SDRAM_CONFIG2  0x8AD70000
diff --git a/board/mcc200/mt48lc8m32b2-6-7.h b/board/mcc200/mt48lc8m32b2-6-7.h
deleted file mode 100644 (file)
index 13aebbd..0000000
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * Configuration Registers for the MT48LC8M32B2 SDRAM on the MPC5200 platform
- */
-
-#define SDRAM_DDR      0               /* is SDR */
-
-/* Settings for XLB = 132 MHz */
-
-#define SDRAM_MODE     0x008d0000 /* CL-3 BURST-8 -> Mode Register MBAR + 0x0100 */
-#define SDRAM_CONTROL  0x504f0000 /* Control Register MBAR + 0x0104 */
-#define SDRAM_CONFIG1  0xc2222900 /* Delays between commands -> Configuration Register 1 MBAR + 0x0108 */
-#define SDRAM_CONFIG2  0x88c70000 /* Delays between commands -> Configuration Register 2 MBAR + 0x010C */
index 96c5f22..384b175 100644 (file)
@@ -27,15 +27,12 @@ endif
 if TARGET_K2L_EVM
 
 config SYS_BOARD
-       string
        default "ks2_evm"
 
 config SYS_VENDOR
-       string
        default "ti"
 
 config SYS_CONFIG_NAME
-       string
        default "k2l_evm"
 
 endif
index 68b8edd..7c36bc9 100644 (file)
@@ -1 +1,2 @@
 ps7_init.[ch]
+ps7_init_gpl.[ch]
index 71c0c35..3b1eb4f 100644 (file)
@@ -7,9 +7,11 @@
 
 obj-y  := board.o
 
-# Please copy ps7_init.c/h from hw project to this directory
+# Please copy ps7_init_gpl.c/h from hw project to this directory
 obj-$(CONFIG_SPL_BUILD) += \
-               $(if $(wildcard $(srctree)/$(src)/ps7_init.c), ps7_init.o)
+               $(if $(wildcard $(srctree)/$(src)/ps7_init_gpl.c), ps7_init_gpl.o, \
+                       $(if $(wildcard $(srctree)/$(src)/ps7_init.c), ps7_init.o legacy.o))
 
 # Suppress "warning: function declaration isn't a prototype"
+CFLAGS_REMOVE_ps7_init_gpl.o := -Wstrict-prototypes
 CFLAGS_REMOVE_ps7_init.o := -Wstrict-prototypes
diff --git a/board/xilinx/zynq/legacy.c b/board/xilinx/zynq/legacy.c
new file mode 100644 (file)
index 0000000..4ae913e
--- /dev/null
@@ -0,0 +1,2 @@
+
+#warning usage of ps7_init files is deprecated please use ps7_init_gpl
index e59a977..1eccf8d 100644 (file)
@@ -6,7 +6,7 @@
 #define XIL_IO_H
 
 /*
- * This empty file is here because ps7_init.c exported by hw project
+ * This empty file is here because ps7_init_gpl.c exported by hw project
  * has #include "xil_io.h" line.
  */
 
index 787d80e..37147af 100644 (file)
@@ -881,7 +881,7 @@ static void lcd_display_rle8_bitmap(bmp_image_t *bmp, ushort *cmap, uchar *fb,
 }
 #endif
 
-#if defined(CONFIG_MPC823) || defined(CONFIG_MCC200)
+#if defined(CONFIG_MPC823)
 #define FB_PUT_BYTE(fb, from) *(fb)++ = (255 - *(from)++)
 #else
 #define FB_PUT_BYTE(fb, from) *(fb)++ = *(from)++
@@ -906,9 +906,7 @@ static inline void fb_put_word(uchar **fb, uchar **from)
 
 int lcd_display_bitmap(ulong bmp_image, int x, int y)
 {
-#if !defined(CONFIG_MCC200)
        ushort *cmap = NULL;
-#endif
        ushort *cmap_base = NULL;
        ushort i, j;
        uchar *fb;
@@ -956,8 +954,6 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
        debug("Display-bmp: %d x %d  with %d colors\n",
                (int)width, (int)height, (int)colors);
 
-#if !defined(CONFIG_MCC200)
-       /* MCC200 LCD doesn't need CMAP, supports 1bpp b&w only */
        if (bmp_bpix == 8) {
                cmap = configuration_get_cmap();
                cmap_base = cmap;
@@ -985,24 +981,6 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 #endif
                }
        }
-#endif
-       /*
-        *  BMP format for Monochrome assumes that the state of a
-        * pixel is described on a per Bit basis, not per Byte.
-        *  So, in case of Monochrome BMP we should align widths
-        * on a byte boundary and convert them from Bit to Byte
-        * units.
-        *  Probably, PXA250 and MPC823 process 1bpp BMP images in
-        * their own ways, so make the converting to be MCC200
-        * specific.
-        */
-#if defined(CONFIG_MCC200)
-       if (bpix == 1) {
-               width = ((width + 7) & ~7) >> 3;
-               x     = ((x + 7) & ~7) >> 3;
-               pwidth= ((pwidth + 7) & ~7) >> 3;
-       }
-#endif
 
        padded_width = (width & 0x3 ? (width & ~0x3) + 4 : width);
 
index eb7706c..1411737 100644 (file)
@@ -1351,8 +1351,11 @@ int usb_stor_get_info(struct usb_device *dev, struct us_data *ss,
        perq = usb_stor_buf[0];
        modi = usb_stor_buf[1];
 
-       if ((perq & 0x1f) == 0x1f) {
-               /* skip unknown devices */
+       /*
+        * Skip unknown devices (0x1f) and enclosure service devices (0x0d),
+        * they would not respond to test_unit_ready .
+        */
+       if (((perq & 0x1f) == 0x1f) || ((perq & 0x1f) == 0x0d)) {
                return 0;
        }
        if ((modi&0x80) == 0x80) {
diff --git a/configs/mcc200_COM12_SDRAM_defconfig b/configs/mcc200_COM12_SDRAM_defconfig
deleted file mode 100644 (file)
index be6dbd7..0000000
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="CONSOLE_COM12,MCC200_SDRAM"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_MCC200=y
diff --git a/configs/mcc200_COM12_defconfig b/configs/mcc200_COM12_defconfig
deleted file mode 100644 (file)
index 6ed8635..0000000
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="CONSOLE_COM12"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_MCC200=y
diff --git a/configs/mcc200_COM12_highboot_SDRAM_defconfig b/configs/mcc200_COM12_highboot_SDRAM_defconfig
deleted file mode 100644 (file)
index 5f93702..0000000
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_MCC200=y
diff --git a/configs/mcc200_COM12_highboot_defconfig b/configs/mcc200_COM12_highboot_defconfig
deleted file mode 100644 (file)
index 7abb0a4..0000000
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_MCC200=y
diff --git a/configs/mcc200_SDRAM_defconfig b/configs/mcc200_SDRAM_defconfig
deleted file mode 100644 (file)
index 37761b5..0000000
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="MCC200_SDRAM"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_MCC200=y
diff --git a/configs/mcc200_defconfig b/configs/mcc200_defconfig
deleted file mode 100644 (file)
index b6aafec..0000000
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_MCC200=y
diff --git a/configs/mcc200_highboot_SDRAM_defconfig b/configs/mcc200_highboot_SDRAM_defconfig
deleted file mode 100644 (file)
index 94d33e5..0000000
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_MCC200=y
diff --git a/configs/mcc200_highboot_defconfig b/configs/mcc200_highboot_defconfig
deleted file mode 100644 (file)
index f863dd9..0000000
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFFF00000"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_MCC200=y
index a560afb..cadf461 100644 (file)
@@ -1,4 +1,4 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/kosagi/novena/setup.cfg,MX6Q,SPL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/kosagi/novena/setup.cfg,MX6Q"
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_KOSAGI_NOVENA=y
diff --git a/configs/prs200_DDR_defconfig b/configs/prs200_DDR_defconfig
deleted file mode 100644 (file)
index 541fb99..0000000
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PRS200"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_MCC200=y
diff --git a/configs/prs200_defconfig b/configs/prs200_defconfig
deleted file mode 100644 (file)
index a094a08..0000000
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PRS200,MCC200_SDRAM"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_MCC200=y
diff --git a/configs/prs200_highboot_DDR_defconfig b/configs/prs200_highboot_DDR_defconfig
deleted file mode 100644 (file)
index b8eb8d4..0000000
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PRS200,SYS_TEXT_BASE=0xFFF00000"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_MCC200=y
diff --git a/configs/prs200_highboot_defconfig b/configs/prs200_highboot_defconfig
deleted file mode 100644 (file)
index 8d68cc0..0000000
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PRS200,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_MCC200=y
diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
new file mode 100644 (file)
index 0000000..0f3896d
--- /dev/null
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_SOCFPGA_CYCLONE5=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig
new file mode 100644 (file)
index 0000000..12311cd
--- /dev/null
@@ -0,0 +1,6 @@
+CONFIG_SPL=y
++S:CONFIG_ARM=y
++S:CONFIG_ZYNQ=y
++S:CONFIG_TARGET_ZYNQ_ZYBO=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="zynq-zybo"
index bd4dd3c..8ba6e0a 100644 (file)
@@ -12,9 +12,11 @@ The list should be sorted in reverse chronological order.
 
 Board            Arch        CPU            Commit      Removed     Last known maintainer/contact
 =================================================================================================
-TOP5200                 powerpc     mpc5200        -           -           Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
-TOP860          powerpc     mpc860         -           -           Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
-TOP9000                 arm         at91sam9xeXXX  -           -           Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
+PRS200          powerpc     mpc5200        -           -
+MCC200          powerpc     mpc5200        -           -
+TOP5200                 powerpc     mpc5200        d58a945     2014-10-28  Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
+TOP860          powerpc     mpc860         d58a945     2014-10-28  Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
+TOP9000                 arm         at91sam9xeXXX  d58a945     2014-10-28  Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
 TQM8272          powerpc     mpc8260        f06f9a1     2014-10-27  Wolfgang Denk <wd@denx.de>
 TQM8260          powerpc     mpc8260        ccc1950     2014-10-27  Wolfgang Denk <wd@denx.de>
 IDS8247          powerpc     mpc8260        6afb357     2014-10-27  Heiko Schocher <hs@denx.de>
index 94551c4..e6ae9f1 100644 (file)
@@ -5,8 +5,6 @@
 
 # new USB host ethernet layer dependencies
 obj-$(CONFIG_USB_HOST_ETHER) += usb_ether.o
-ifdef CONFIG_USB_ETHER_ASIX
-obj-y += asix.o
-endif
+obj-$(CONFIG_USB_ETHER_ASIX) += asix.o
 obj-$(CONFIG_USB_ETHER_MCS7830) += mcs7830.o
 obj-$(CONFIG_USB_ETHER_SMSC95XX) += smsc95xx.o
index 2efd5a4..70bb550 100644 (file)
@@ -12,6 +12,7 @@ obj-$(CONFIG_USB_ETHER) += epautoconf.o config.o usbstring.o
 ifdef CONFIG_USB_GADGET
 obj-$(CONFIG_USB_GADGET_ATMEL_USBA) += atmel_usba_udc.o
 obj-$(CONFIG_USB_GADGET_S3C_UDC_OTG) += s3c_udc_otg.o
+obj-$(CONFIG_USB_GADGET_S3C_UDC_OTG_PHY) += s3c_udc_otg_phy.o
 obj-$(CONFIG_USB_GADGET_FOTG210) += fotg210.o
 obj-$(CONFIG_CI_UDC)   += ci_udc.o
 obj-$(CONFIG_THOR_FUNCTION) += f_thor.o
index b9816df..7653f03 100644 (file)
@@ -31,7 +31,6 @@
 #include <asm/io.h>
 
 #include <asm/mach-types.h>
-#include <asm/arch/gpio.h>
 
 #include "regs-otg.h"
 #include <usb/lin_gadget_compat.h>
@@ -105,7 +104,7 @@ static void stop_activity(struct s3c_udc *dev,
                          struct usb_gadget_driver *driver);
 static int udc_enable(struct s3c_udc *dev);
 static void udc_set_address(struct s3c_udc *dev, unsigned char address);
-static void reconfig_usbd(void);
+static void reconfig_usbd(struct s3c_udc *dev);
 static void set_max_pktsize(struct s3c_udc *dev, enum usb_device_speed speed);
 static void nuke(struct s3c_ep *ep, int status);
 static int s3c_udc_set_halt(struct usb_ep *_ep, int value);
@@ -146,68 +145,14 @@ static struct usb_ep_ops s3c_ep_ops = {
 
 void __iomem           *regs_otg;
 struct s3c_usbotg_reg *reg;
-struct s3c_usbotg_phy *phy;
-static unsigned int usb_phy_ctrl;
 
 bool dfu_usb_get_reset(void)
 {
        return !!(readl(&reg->gintsts) & INT_RESET);
 }
 
-void otg_phy_init(struct s3c_udc *dev)
-{
-       dev->pdata->phy_control(1);
-
-       /*USB PHY0 Enable */
-       printf("USB PHY0 Enable\n");
-
-       /* Enable PHY */
-       writel(readl(usb_phy_ctrl) | USB_PHY_CTRL_EN0, usb_phy_ctrl);
-
-       if (dev->pdata->usb_flags == PHY0_SLEEP) /* C210 Universal */
-               writel((readl(&phy->phypwr)
-                       &~(PHY_0_SLEEP | OTG_DISABLE_0 | ANALOG_PWRDOWN)
-                       &~FORCE_SUSPEND_0), &phy->phypwr);
-       else /* C110 GONI */
-               writel((readl(&phy->phypwr) &~(OTG_DISABLE_0 | ANALOG_PWRDOWN)
-                       &~FORCE_SUSPEND_0), &phy->phypwr);
-
-       if (s5p_cpu_id == 0x4412)
-               writel((readl(&phy->phyclk) & ~(EXYNOS4X12_ID_PULLUP0 |
-                       EXYNOS4X12_COMMON_ON_N0)) | EXYNOS4X12_CLK_SEL_24MHZ,
-                      &phy->phyclk); /* PLL 24Mhz */
-       else
-               writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)) |
-                      CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */
-
-       writel((readl(&phy->rstcon) &~(LINK_SW_RST | PHYLNK_SW_RST))
-              | PHY_SW_RST0, &phy->rstcon);
-       udelay(10);
-       writel(readl(&phy->rstcon)
-              &~(PHY_SW_RST0 | LINK_SW_RST | PHYLNK_SW_RST), &phy->rstcon);
-       udelay(10);
-}
-
-void otg_phy_off(struct s3c_udc *dev)
-{
-       /* reset controller just in case */
-       writel(PHY_SW_RST0, &phy->rstcon);
-       udelay(20);
-       writel(readl(&phy->phypwr) &~PHY_SW_RST0, &phy->rstcon);
-       udelay(20);
-
-       writel(readl(&phy->phypwr) | OTG_DISABLE_0 | ANALOG_PWRDOWN
-              | FORCE_SUSPEND_0, &phy->phypwr);
-
-       writel(readl(usb_phy_ctrl) &~USB_PHY_CTRL_EN0, usb_phy_ctrl);
-
-       writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)),
-             &phy->phyclk);
-
-       udelay(10000);
-
-       dev->pdata->phy_control(0);
-}
+__weak void otg_phy_init(struct s3c_udc *dev) {}
+__weak void otg_phy_off(struct s3c_udc *dev) {}
 
 /***********************************************************/
 
@@ -270,7 +215,7 @@ static int udc_enable(struct s3c_udc *dev)
        debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev);
 
        otg_phy_init(dev);
-       reconfig_usbd();
+       reconfig_usbd(dev);
 
        debug_cond(DEBUG_SETUP != 0,
                   "S3C USB 2.0 OTG Controller Core Initialized : 0x%x\n",
@@ -451,15 +396,17 @@ static void stop_activity(struct s3c_udc *dev,
        udc_reinit(dev);
 }
 
-static void reconfig_usbd(void)
+static void reconfig_usbd(struct s3c_udc *dev)
 {
        /* 2. Soft-reset OTG Core and then unreset again. */
        int i;
        unsigned int uTemp = writel(CORE_SOFT_RESET, &reg->grstctl);
+       uint32_t dflt_gusbcfg;
 
        debug("Reseting OTG controller\n");
 
-       writel(0<<15            /* PHY Low Power Clock sel*/
+       dflt_gusbcfg =
+               0<<15           /* PHY Low Power Clock sel*/
                |1<<14          /* Non-Periodic TxFIFO Rewind Enable*/
                |0x5<<10        /* Turnaround time*/
                |0<<9 | 0<<8    /* [0:HNP disable,1:HNP enable][ 0:SRP disable*/
@@ -468,8 +415,12 @@ static void reconfig_usbd(void)
                |0<<6           /* 0: high speed utmi+, 1: full speed serial*/
                |0<<4           /* 0: utmi+, 1:ulpi*/
                |1<<3           /* phy i/f  0:8bit, 1:16bit*/
-               |0x7<<0,        /* HS/FS Timeout**/
-               &reg->gusbcfg);
+               |0x7<<0;        /* HS/FS Timeout**/
+
+       if (dev->pdata->usb_gusbcfg)
+               dflt_gusbcfg = dev->pdata->usb_gusbcfg;
+
+       writel(dflt_gusbcfg, &reg->gusbcfg);
 
        /* 3. Put the OTG device core in the disconnected state.*/
        uTemp = readl(&reg->dctl);
@@ -854,9 +805,7 @@ int s3c_udc_probe(struct s3c_plat_otg_data *pdata)
 
        dev->pdata = pdata;
 
-       phy = (struct s3c_usbotg_phy *)pdata->regs_phy;
        reg = (struct s3c_usbotg_reg *)pdata->regs_otg;
-       usb_phy_ctrl = pdata->usb_phy_ctrl;
 
        /* regs_otg = (void *)pdata->regs_otg; */
 
diff --git a/drivers/usb/gadget/s3c_udc_otg_phy.c b/drivers/usb/gadget/s3c_udc_otg_phy.c
new file mode 100644 (file)
index 0000000..f13cb89
--- /dev/null
@@ -0,0 +1,101 @@
+/*
+ * drivers/usb/gadget/s3c_udc_otg.c
+ * Samsung S3C on-chip full/high speed USB OTG 2.0 device controllers
+ *
+ * Copyright (C) 2008 for Samsung Electronics
+ *
+ * BSP Support for Samsung's UDC driver
+ * available at:
+ * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
+ *
+ * State machine bugfixes:
+ * Marek Szyprowski <m.szyprowski@samsung.com>
+ *
+ * Ported to u-boot:
+ * Marek Szyprowski <m.szyprowski@samsung.com>
+ * Lukasz Majewski <l.majewski@samsumg.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <linux/list.h>
+#include <malloc.h>
+
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+
+#include <asm/byteorder.h>
+#include <asm/unaligned.h>
+#include <asm/io.h>
+
+#include <asm/mach-types.h>
+
+#include "regs-otg.h"
+#include <usb/lin_gadget_compat.h>
+
+#include <usb/s3c_udc.h>
+
+void otg_phy_init(struct s3c_udc *dev)
+{
+       unsigned int usb_phy_ctrl = dev->pdata->usb_phy_ctrl;
+       struct s3c_usbotg_phy *phy =
+               (struct s3c_usbotg_phy *)dev->pdata->regs_phy;
+
+       dev->pdata->phy_control(1);
+
+       /* USB PHY0 Enable */
+       printf("USB PHY0 Enable\n");
+
+       /* Enable PHY */
+       writel(readl(usb_phy_ctrl) | USB_PHY_CTRL_EN0, usb_phy_ctrl);
+
+       if (dev->pdata->usb_flags == PHY0_SLEEP) /* C210 Universal */
+               writel((readl(&phy->phypwr)
+                       &~(PHY_0_SLEEP | OTG_DISABLE_0 | ANALOG_PWRDOWN)
+                       &~FORCE_SUSPEND_0), &phy->phypwr);
+       else /* C110 GONI */
+               writel((readl(&phy->phypwr) &~(OTG_DISABLE_0 | ANALOG_PWRDOWN)
+                       &~FORCE_SUSPEND_0), &phy->phypwr);
+
+       if (s5p_cpu_id == 0x4412)
+               writel((readl(&phy->phyclk) & ~(EXYNOS4X12_ID_PULLUP0 |
+                       EXYNOS4X12_COMMON_ON_N0)) | EXYNOS4X12_CLK_SEL_24MHZ,
+                      &phy->phyclk); /* PLL 24Mhz */
+       else
+               writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)) |
+                      CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */
+
+       writel((readl(&phy->rstcon) &~(LINK_SW_RST | PHYLNK_SW_RST))
+              | PHY_SW_RST0, &phy->rstcon);
+       udelay(10);
+       writel(readl(&phy->rstcon)
+              &~(PHY_SW_RST0 | LINK_SW_RST | PHYLNK_SW_RST), &phy->rstcon);
+       udelay(10);
+}
+
+void otg_phy_off(struct s3c_udc *dev)
+{
+       unsigned int usb_phy_ctrl = dev->pdata->usb_phy_ctrl;
+       struct s3c_usbotg_phy *phy =
+               (struct s3c_usbotg_phy *)dev->pdata->regs_phy;
+
+       /* reset controller just in case */
+       writel(PHY_SW_RST0, &phy->rstcon);
+       udelay(20);
+       writel(readl(&phy->phypwr) &~PHY_SW_RST0, &phy->rstcon);
+       udelay(20);
+
+       writel(readl(&phy->phypwr) | OTG_DISABLE_0 | ANALOG_PWRDOWN
+              | FORCE_SUSPEND_0, &phy->phypwr);
+
+       writel(readl(usb_phy_ctrl) &~USB_PHY_CTRL_EN0, usb_phy_ctrl);
+
+       writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)),
+             &phy->phyclk);
+
+       udelay(10000);
+
+       dev->pdata->phy_control(0);
+}
index 4f69b22..9c54b46 100644 (file)
@@ -551,7 +551,7 @@ static int s3c_udc_irq(int irq, void *_dev)
                                debug_cond(DEBUG_ISR,
                                        "\t\tOTG core got reset (%d)!!\n",
                                        reset_available);
-                               reconfig_usbd();
+                               reconfig_usbd(dev);
                                dev->ep0state = WAIT_FOR_SETUP;
                                reset_available = 0;
                                s3c_udc_pre_setup();
index b433087..7fe79ef 100644 (file)
 #include "ehci.h"
 
 #if defined(CONFIG_R8A7740)
-static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = {
+static u32 usb_base_address[] = {
        0xC6700000
 };
 #elif defined(CONFIG_R8A7790)
-static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = {
+static u32 usb_base_address[] = {
        0xEE080000,     /* USB0 (EHCI) */
        0xEE0A0000,     /* USB1 */
        0xEE0C0000,     /* USB2 */
 };
 #elif defined(CONFIG_R8A7791) || defined(CONFIG_R8A7793) || \
        defined(CONFIG_R8A7794)
-static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = {
+static u32 usb_base_address[] = {
        0xEE080000,     /* USB0 (EHCI) */
        0xEE0C0000,     /* USB1 */
 };
@@ -53,7 +53,7 @@ int ehci_hcd_stop(int index)
        if (!i)
                printf("error : ehci(%d) reset failed.\n", index);
 
-       if (index == (CONFIG_USB_MAX_CONTROLLER_COUNT - 1))
+       if (index == (ARRAY_SIZE(usb_base_address) - 1))
                setbits_le32(SMSTPCR7, SMSTPCR703);
 
        return 0;
index 433e703..79aecd4 100644 (file)
@@ -47,9 +47,9 @@ struct ehci_hcor {
        uint32_t or_usbcmd;
 #define CMD_PARK       (1 << 11)               /* enable "park" */
 #define CMD_PARK_CNT(c)        (((c) >> 8) & 3)        /* how many transfers to park */
-#define CMD_ASE                (1 << 5)                /* async schedule enable */
 #define CMD_LRESET     (1 << 7)                /* partial reset */
-#define CMD_IAAD       (1 << 5)                /* "doorbell" interrupt */
+#define CMD_IAAD       (1 << 6)                /* "doorbell" interrupt */
+#define CMD_ASE                (1 << 5)                /* async schedule enable */
 #define CMD_PSE                (1 << 4)                /* periodic schedule enable */
 #define CMD_RESET      (1 << 1)                /* reset HC not bus */
 #define CMD_RUN                (1 << 0)                /* start/stop HC */
index 89ba14e..41631c7 100644 (file)
@@ -59,6 +59,7 @@
 
 #define CONFIG_USB_GADGET
 #define CONFIG_USB_GADGET_S3C_UDC_OTG
+#define CONFIG_USB_GADGET_S3C_UDC_OTG_PHY
 #define CONFIG_USB_GADGET_DUALSPEED
 #define CONFIG_USB_GADGET_VBUS_DRAW    2
 
diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h
deleted file mode 100644 (file)
index a317782..0000000
+++ /dev/null
@@ -1,397 +0,0 @@
-/*
- * (C) Copyright 2006-2008
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5200
-#define CONFIG_MCC200          1       /* MCC200 board */
-
-/*
- * Valid values for CONFIG_SYS_TEXT_BASE are:
- * 0xFC000000  boot low (standard configuration)
- * 0xFFF00000  boot high
- * 0x00100000  boot from RAM (for testing only)
- */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE   0xFC000000
-#endif
-
-#define CONFIG_SYS_MPC5XXX_CLKIN       33000000 /* ... running at 33MHz                */
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_HIGH_BATS       1       /* High BATs supported                  */
-
-/*
- * Serial console configuration
- *
- *  To select console on the one of 8 external UARTs,
- * define CONFIG_QUART_CONSOLE as 1, 2, 3, or 4 for the first Quad UART,
- * or as 5, 6, 7, or 8 for the second Quad UART.
- * COM11, COM12, COM13, COM14 are located on the second Quad UART.
- *
- *  CONFIG_PSC_CONSOLE must be undefined in this case.
- */
-#if !defined(CONFIG_PRS200)
-/* MCC200 configuration: */
-#ifdef CONFIG_CONSOLE_COM12
-#define CONFIG_QUART_CONSOLE   6       /* console is on UARTF of QUART2        */
-#else
-#define CONFIG_QUART_CONSOLE   8       /* console is on UARTH of QUART2        */
-#endif
-#else
-/* PRS200 configuration: */
-#undef CONFIG_QUART_CONSOLE
-#endif /* CONFIG_PRS200 */
-/*
- *  To select console on PSC1, define CONFIG_PSC_CONSOLE as 1
- * and undefine CONFIG_QUART_CONSOLE.
- */
-#if !defined(CONFIG_PRS200)
-/* MCC200 configuration: */
-#define CONFIG_PSC_CONSOLE     1       /* PSC1 may be COM */
-#define CONFIG_PSC_CONSOLE2    2       /* PSC2 is PSoC */
-#else
-/* PRS200 configuration: */
-#define CONFIG_PSC_CONSOLE     1       /* console is on PSC1           */
-#endif
-#define CONFIG_BAUDRATE                115200
-#define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CONFIG_MII             1
-
-#define CONFIG_DOS_PARTITION
-
-/* USB */
-#define CONFIG_USB_OHCI
-#define CONFIG_USB_STORAGE
-/* automatic software updates (see board/mcc200/auto_update.c) */
-#define CONFIG_AUTO_UPDATE 1
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_USB
-
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY       1       /* autoboot after 1 second */
-
-#define CONFIG_PREBOOT "echo;" \
-       "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-       "echo"
-
-#undef CONFIG_BOOTARGS
-
-#ifdef CONFIG_PRS200
-# define CONFIG_SYS__BOARDNAME         "prs200"
-# define CONFIG_SYS__LINUX_CONSOLE     "ttyS0"
-#else
-# define CONFIG_SYS__BOARDNAME         "mcc200"
-# define CONFIG_SYS__LINUX_CONSOLE     "ttyEU5"
-#endif
-
-/* Network */
-#define CONFIG_ETHADDR 00:17:17:ff:00:00
-#define CONFIG_IPADDR  10.76.9.29
-#define CONFIG_SERVERIP        10.76.9.1
-
-#include <version.h> /* For U-Boot version */
-
-#define CONFIG_EXTRA_ENV_SETTINGS                                      \
-       "ubootver=" U_BOOT_VERSION "\0"                                 \
-       "netdev=eth0\0"                                                 \
-       "hostname=" CONFIG_SYS__BOARDNAME "\0"                          \
-       "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
-               "nfsroot=${serverip}:${rootpath}\0"                     \
-       "ramargs=setenv bootargs root=/dev/mtdblock2 "                  \
-               "rootfstype=cramfs\0"                                   \
-       "addip=setenv bootargs ${bootargs} "                            \
-               "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
-               ":${hostname}:${netdev}:off panic=1\0"                  \
-       "addcons=setenv bootargs ${bootargs} "                          \
-               "console=${console},${baudrate} "                       \
-               "ubootver=${ubootver} board=${board}\0"                 \
-       "flash_nfs=run nfsargs addip addcons;"                          \
-               "bootm ${kernel_addr}\0"                                \
-       "flash_self=run ramargs addip addcons;"                         \
-               "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
-       "net_nfs=tftp 200000 ${bootfile};"                              \
-               "run nfsargs addip addcons;bootm\0"                     \
-       "console=" CONFIG_SYS__LINUX_CONSOLE "\0"                               \
-       "rootpath=/opt/eldk/ppc_6xx\0"                                  \
-       "bootfile=/tftpboot/" CONFIG_SYS__BOARDNAME "/uImage\0"         \
-       "load=tftp 200000 /tftpboot/" CONFIG_SYS__BOARDNAME "/u-boot.bin\0"     \
-       "text_base=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"             \
-       "kernel_addr=0xFC0C0000\0"                                      \
-       "update=protect off ${text_base} +${filesize};"                 \
-               "era ${text_base} +${filesize};"                        \
-               "cp.b 200000 ${text_base} ${filesize}\0"                \
-       "unlock=yes\0"                                                  \
-       ""
-
-#define CONFIG_BOOTCOMMAND     "run flash_self"
-
-#define CONFIG_SYS_HUSH_PARSER         1       /* use "hush" command parser    */
-
-/*
- * IPB Bus clocking configuration.
- */
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK                /* define for 133MHz speed */
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C                1       /* I2C with hardware support */
-#define CONFIG_SYS_I2C_MODULE          2       /* Select I2C module #1 or #2 */
-
-#define CONFIG_SYS_I2C_SPEED           100000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE           0x7F
-
-/*
- * Flash configuration (8,16 or 32 MB)
- * TEXT base always at 0xFFF00000
- * ENV_ADDR always at  0xFFF40000
- * FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!)
- *              0xFE000000 for 32 MB
- *              0xFF000000 for 16 MB
- *              0xFF800000 for  8 MB
- */
-#define CONFIG_SYS_FLASH_BASE          0xfc000000
-#define CONFIG_SYS_FLASH_SIZE          0x04000000
-
-#define CONFIG_SYS_FLASH_CFI                           /* The flash is CFI compatible  */
-#define CONFIG_FLASH_CFI_DRIVER                        /* Use common CFI driver        */
-
-#define CONFIG_SYS_FLASH_BANKS_LIST    { CONFIG_SYS_FLASH_BASE }
-
-#define CONFIG_SYS_MAX_FLASH_BANKS     1       /* max number of memory banks           */
-#define CONFIG_SYS_MAX_FLASH_SECT      512     /* max number of sectors on one chip    */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)     */
-#define CONFIG_SYS_FLASH_PROTECTION    1       /* hardware flash protection            */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_QUIET_TEST    1       /* don't warn upon unknown flash        */
-
-#define CONFIG_ENV_IS_IN_FLASH 1       /* use FLASH for environment vars       */
-
-#define CONFIG_ENV_SECT_SIZE   0x40000 /* size of one complete sector  */
-#define CONFIG_ENV_ADDR                (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define        CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector     */
-
-/* Address and size of Redundant Environment Sector    */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
-#define CONFIG_ENV_OVERWRITE   1       /* allow modification of vendor params */
-
-#if CONFIG_SYS_TEXT_BASE == CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LOWBOOT     1
-#endif
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR                0xf0000000
-#define CONFIG_SYS_SDRAM_BASE          0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR        0x80000000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR       MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE       MPC5XXX_SRAM_SIZE       /* Size of used area in DPRAM */
-
-
-#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#   define CONFIG_SYS_RAMBOOT          1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
-#define CONFIG_SYS_MALLOC_LEN          (512 << 10)     /* Reserve 512 kB for malloc()  */
-#define CONFIG_SYS_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-/* #define CONFIG_MPC5xxx_FEC  1 */
-/* #define CONFIG_MPC5xxx_FEC_MII100 */
-/*
- * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
- */
-/* #define CONFIG_MPC5xxx_FEC_MII10 */
-#define CONFIG_PHY_ADDR                1
-
-/*
- * LCD Splash Screen
- */
-#if !defined(CONFIG_PRS200)
-#define CONFIG_LCD             1
-#define CONFIG_PROGRESSBAR 1
-#endif
-
-#if defined(CONFIG_LCD)
-#define CONFIG_SPLASH_SCREEN   1
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV   1
-#define LCD_BPP                        LCD_MONOCHROME
-#endif
-
-/*
- * GPIO configuration
- */
-/* 0x10000004 = 32MB SDRAM */
-/* 0x90000004 = 64MB SDRAM */
-#if defined(CONFIG_LCD)
-/* set PSC2 in UART mode */
-#define CONFIG_SYS_GPS_PORT_CONFIG     0x00000044
-#else
-#define CONFIG_SYS_GPS_PORT_CONFIG     0x00000004
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP                    /* undef to save memory         */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE              1024    /* Console I/O Buffer Size      */
-#else
-#define CONFIG_SYS_CBSIZE              256     /* Console I/O Buffer Size      */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)     /* Print Buffer Size    */
-#define CONFIG_SYS_MAXARGS             16              /* max number of command args   */
-#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
-
-#define CONFIG_SYS_MEMTEST_START       0x00100000      /* memtest works on     */
-#define CONFIG_SYS_MEMTEST_END         0x00f00000      /* 1 ... 15 MB in DRAM  */
-
-#define CONFIG_SYS_LOAD_ADDR           0x100000        /* default load address */
-
-#define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC5xxx CPUs                     */
-#if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CACHELINE_SHIFT   5       /* log base 2 of the above value        */
-#endif
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT           HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL          HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START        CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE         CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG          0x0004fb00
-#define CONFIG_SYS_CS0_START           CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE            CONFIG_SYS_FLASH_SIZE
-
-/* Quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
-#define CONFIG_SYS_CS2_START           0x80000000
-#define CONFIG_SYS_CS2_SIZE            0x00001000
-#define CONFIG_SYS_CS2_CFG             0x1d300
-
-/* Second Quad UART @0x80010000 */
-#define CONFIG_SYS_CS1_START           0x80010000
-#define CONFIG_SYS_CS1_SIZE            0x00001000
-#define CONFIG_SYS_CS1_CFG             0x1d300
-
-/* Leica - build revision resistors */
-/*
-#define CONFIG_SYS_CS3_START           0x80020000
-#define CONFIG_SYS_CS3_SIZE            0x00000004
-#define CONFIG_SYS_CS3_CFG             0x1d300
-*/
-
-/*
- *  Select one of quarts as a default
- * console. If undefined - PSC console
- * wil be default
- */
-#define CONFIG_SYS_CS_BURST            0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE        0x33333333
-
-#define CONFIG_SYS_RESET_ADDRESS       0xff000000
-
-/*
- * QUART Expanders support
- */
-#if defined(CONFIG_QUART_CONSOLE)
-/*
- * We'll use NS16550 chip routines,
- */
-#define CONFIG_SYS_NS16550             1
-#define CONFIG_SYS_NS16550_SERIAL      1
-#define CONFIG_CONS_INDEX      1
-/*
- *  To achieve necessary offset on SC16C554
- * A0-A2 (register select) pins with NS16550
- * functions (in struct NS16550), REG_SIZE
- * should be 4, because A0-A2 pins are connected
- * to DA2-DA4 address bus lines.
- */
-#define CONFIG_SYS_NS16550_REG_SIZE    4
-/*
- * LocalPlus Bus already inited in cpu_init_f(),
- * so can work with QUART's chip selects.
- * One of four SC16C554 UARTs is selected with
- * A3-A4 (DA5-DA6) lines.
- */
-#if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5) && !defined(CONFIG_PRS200)
-#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5)
-#elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9)
-#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5)
-#else
-#error "Wrong QUART expander number."
-#endif
-
-/*
- * SC16C554 chip's external crystal oscillator frequency
- * is 7.3728 MHz
- */
-#define CONFIG_SYS_NS16550_CLK         7372800
-#endif /* CONFIG_QUART_CONSOLE */
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_CLOCK       0x0001BBBB
-#define CONFIG_USB_CONFIG      0x00005000
-
-#define CONFIG_AUTOBOOT_KEYED          /* use key strings to stop autoboot     */
-#define CONFIG_AUTOBOOT_STOP_STR       "432"
-#define CONFIG_SILENT_CONSOLE  1
-
-#endif /* __CONFIG_H */
index 3633a35..dfa2e07 100644 (file)
 #define CONFIG_SYS_MAX_I2C_BUS 7
 #define CONFIG_USB_GADGET
 #define CONFIG_USB_GADGET_S3C_UDC_OTG
+#define CONFIG_USB_GADGET_S3C_UDC_OTG_PHY
 #define CONFIG_USB_GADGET_DUALSPEED
 #define CONFIG_USB_GADGET_VBUS_DRAW 2
 #define CONFIG_CMD_USB_MASS_STORAGE
index 4b30d14..e7bace4 100644 (file)
 
 #define CONFIG_USB_GADGET
 #define CONFIG_USB_GADGET_S3C_UDC_OTG
+#define CONFIG_USB_GADGET_S3C_UDC_OTG_PHY
 #define CONFIG_USB_GADGET_DUALSPEED
 
 /*
index a2469eb..655025c 100644 (file)
@@ -14,6 +14,7 @@
 #undef CONFIG_BOARD_COMMON
 #undef CONFIG_USB_GADGET
 #undef CONFIG_USB_GADGET_S3C_UDC_OTG
+#undef CONFIG_USB_GADGET_S3C_UDC_OTG_PHY
 #undef CONFIG_CMD_USB_MASS_STORAGE
 #undef CONFIG_REVISION_TAG
 #undef CONFIG_CMD_THOR_DOWNLOAD
index 83a1bcd..c436fda 100644 (file)
@@ -37,7 +37,7 @@
  */
 #define CONFIG_NR_DRAM_BANKS           1
 #define PHYS_SDRAM_1                   0x0
-#define CONFIG_SYS_MALLOC_LEN          (10 * 1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN          (64 * 1024 * 1024)
 #define CONFIG_SYS_MEMTEST_START       PHYS_SDRAM_1
 #define CONFIG_SYS_MEMTEST_END         PHYS_SDRAM_1_SIZE
 
 #define CONFIG_SYS_PL310_BASE          SOCFPGA_MPUL2_ADDRESS
 
 /*
+ * EPCS/EPCQx1 Serial Flash Controller
+ */
+#ifdef CONFIG_ALTERA_SPI
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED                30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_BAR
+/*
+ * The base address is configurable in QSys, each board must specify the
+ * base address based on it's particular FPGA configuration. Please note
+ * that the address here is incremented by  0x400  from the Base address
+ * selected in QSys, since the SPI registers are at offset +0x400.
+ * #define CONFIG_SYS_SPI_BASE         0xff240400
+ */
+#endif
+
+/*
  * Ethernet on SoC (EMAC)
  */
 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
 #define CONFIG_SYS_MMC_MAX_BLK_COUNT   256     /* FIXME -- SPL only? */
 #endif
 
+ /*
+ * I2C support
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DW
+#define CONFIG_SYS_I2C_BUS_MAX         4
+#define CONFIG_SYS_I2C_BASE            SOCFPGA_I2C0_ADDRESS
+#define CONFIG_SYS_I2C_BASE1           SOCFPGA_I2C1_ADDRESS
+#define CONFIG_SYS_I2C_BASE2           SOCFPGA_I2C2_ADDRESS
+#define CONFIG_SYS_I2C_BASE3           SOCFPGA_I2C3_ADDRESS
+/* Using standard mode which the speed up to 100Kb/s */
+#define CONFIG_SYS_I2C_SPEED           100000
+#define CONFIG_SYS_I2C_SPEED1          100000
+#define CONFIG_SYS_I2C_SPEED2          100000
+#define CONFIG_SYS_I2C_SPEED3          100000
+/* Address of device when used as slave */
+#define CONFIG_SYS_I2C_SLAVE           0x02
+#define CONFIG_SYS_I2C_SLAVE1          0x02
+#define CONFIG_SYS_I2C_SLAVE2          0x02
+#define CONFIG_SYS_I2C_SLAVE3          0x02
+#ifndef __ASSEMBLY__
+/* Clock supplied to I2C controller in unit of MHz */
+unsigned int cm_get_l4_sp_clk_hz(void);
+#define IC_CLK                         (cm_get_l4_sp_clk_hz() / 1000000)
+#endif
+#define CONFIG_CMD_I2C
+
 /*
  * Serial Driver
  */
 #endif
 
 /*
+ * USB Gadget (DFU, UMS)
+ */
+#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_S3C_UDC_OTG
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_VBUS_DRAW    2
+
+/* USB Composite download gadget - g_dnl */
+#define CONFIG_USBDOWNLOAD_GADGET
+#define CONFIG_USB_GADGET_MASS_STORAGE
+
+#define CONFIG_DFU_FUNCTION
+#define CONFIG_DFU_MMC
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE   (32 * 1024 * 1024)
+#define DFU_DEFAULT_POLL_TIMEOUT       300
+
+/* USB IDs */
+#define CONFIG_G_DNL_VENDOR_NUM                0x0525  /* NetChip */
+#define CONFIG_G_DNL_PRODUCT_NUM       0xA4A5  /* Linux-USB File-backed Storage Gadget */
+#define CONFIG_G_DNL_UMS_VENDOR_NUM    CONFIG_G_DNL_VENDOR_NUM
+#define CONFIG_G_DNL_UMS_PRODUCT_NUM   CONFIG_G_DNL_PRODUCT_NUM
+#ifndef CONFIG_G_DNL_MANUFACTURER
+#define CONFIG_G_DNL_MANUFACTURER      "Altera"
+#endif
+#endif
+
+/*
  * U-Boot environment
  */
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
index 942738c..c3d958c 100644 (file)
@@ -42,7 +42,7 @@
 /* Booting Linux */
 #define CONFIG_BOOTDELAY       3
 #define CONFIG_BOOTFILE                "zImage"
-#define CONFIG_BOOTARGS                "console=ttyS0" __stringify(CONFIG_BAUDRATE)
+#define CONFIG_BOOTARGS                "console=ttyS0," __stringify(CONFIG_BAUDRATE)
 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 #define CONFIG_BOOTCOMMAND     "run ramboot"
 #else
diff --git a/include/configs/zynq_zybo.h b/include/configs/zynq_zybo.h
new file mode 100644 (file)
index 0000000..191f2a5
--- /dev/null
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright 2012 Xilinx
+ * (C) Copyright 2014 Digilent Inc.
+ *
+ * Configuration for Zynq Development Board - ZYBO
+ * See zynq-common.h for Zynq common configs
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQ_ZYBO_H
+#define __CONFIG_ZYNQ_ZYBO_H
+
+#define CONFIG_SYS_SDRAM_SIZE (512 * 1024 * 1024)
+
+#define CONFIG_ZYNQ_SERIAL_UART1
+#define CONFIG_ZYNQ_GEM0
+#define CONFIG_ZYNQ_GEM_PHY_ADDR0      0
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ZYNQ_SDHCI0
+#define CONFIG_ZYNQ_BOOT_FREEBSD
+
+/* Define ZYBO PS Clock Frequency to 50MHz */
+#define CONFIG_ZYNQ_PS_CLK_FREQ        50000000UL
+
+#include <configs/zynq-common.h>
+
+#endif /* __CONFIG_ZYNQ_ZYBO_H */
diff --git a/include/dt-bindings/reset/altr,rst-mgr.h b/include/dt-bindings/reset/altr,rst-mgr.h
new file mode 100644 (file)
index 0000000..3f04908
--- /dev/null
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H
+#define _DT_BINDINGS_RESET_ALTR_RST_MGR_H
+
+/* MPUMODRST */
+#define CPU0_RESET             0
+#define CPU1_RESET             1
+#define WDS_RESET              2
+#define SCUPER_RESET           3
+#define L2_RESET               4
+
+/* PERMODRST */
+#define EMAC0_RESET            32
+#define EMAC1_RESET            33
+#define USB0_RESET             34
+#define USB1_RESET             35
+#define NAND_RESET             36
+#define QSPI_RESET             37
+#define L4WD0_RESET            38
+#define L4WD1_RESET            39
+#define OSC1TIMER0_RESET       40
+#define OSC1TIMER1_RESET       41
+#define SPTIMER0_RESET         42
+#define SPTIMER1_RESET         43
+#define I2C0_RESET             44
+#define I2C1_RESET             45
+#define I2C2_RESET             46
+#define I2C3_RESET             47
+#define UART0_RESET            48
+#define UART1_RESET            49
+#define SPIM0_RESET            50
+#define SPIM1_RESET            51
+#define SPIS0_RESET            52
+#define SPIS1_RESET            53
+#define SDMMC_RESET            54
+#define CAN0_RESET             55
+#define CAN1_RESET             56
+#define GPIO0_RESET            57
+#define GPIO1_RESET            58
+#define GPIO2_RESET            59
+#define DMA_RESET              60
+#define SDR_RESET              61
+
+/* PER2MODRST */
+#define DMAIF0_RESET           64
+#define DMAIF1_RESET           65
+#define DMAIF2_RESET           66
+#define DMAIF3_RESET           67
+#define DMAIF4_RESET           68
+#define DMAIF5_RESET           69
+#define DMAIF6_RESET           70
+#define DMAIF7_RESET           71
+
+/* BRGMODRST */
+#define HPS2FPGA_RESET         96
+#define LWHPS2FPGA_RESET       97
+#define FPGA2HPS_RESET         98
+
+/* MISCMODRST*/
+#define ROM_RESET              128
+#define OCRAM_RESET            129
+#define SYSMGR_RESET           130
+#define SYSMGRCOLD_RESET       131
+#define FPGAMGR_RESET          132
+#define ACPIDMAP_RESET         133
+#define S2F_RESET              134
+#define S2FCOLD_RESET          135
+#define NRSTPIN_RESET          136
+#define TIMESTAMPCOLD_RESET    137
+#define CLKMGRCOLD_RESET       138
+#define SCANMGR_RESET          139
+#define FRZCTRLCOLD_RESET      140
+#define SYSDBG_RESET           141
+#define DBG_RESET              142
+#define TAPCOLD_RESET          143
+#define SDRCOLD_RESET          144
+
+#endif
index ea5860c..020d880 100644 (file)
@@ -250,7 +250,7 @@ typedef struct vidinfo {
        void    *priv;          /* Pointer to driver-specific data */
 } vidinfo_t;
 
-#endif /* CONFIG_MPC823, CONFIG_CPU_PXA25X, CONFIG_MCC200, CONFIG_ATMEL_LCD */
+#endif /* CONFIG_MPC823, CONFIG_CPU_PXA25X, CONFIG_ATMEL_LCD */
 
 extern vidinfo_t panel_info;
 
index 9d0d04d..d3c7415 100644 (file)
@@ -11,6 +11,8 @@
 
 #include <usb_defs.h>
 #include <linux/usb/ch9.h>
+#include <asm/cache.h>
+#include <part.h>
 
 /*
  * The EHCI spec says that we must align to at least 32 bytes.  However,
index 70e48f8..7f49a4e 100644 (file)
@@ -108,5 +108,6 @@ struct s3c_plat_otg_data {
        unsigned int    regs_otg;
        unsigned int    usb_phy_ctrl;
        unsigned int    usb_flags;
+       unsigned int    usb_gusbcfg;
 };
 #endif
old mode 100644 (file)
new mode 100755 (executable)
old mode 100644 (file)
new mode 100755 (executable)
old mode 100644 (file)
new mode 100755 (executable)
old mode 100644 (file)
new mode 100755 (executable)
old mode 100644 (file)
new mode 100755 (executable)
old mode 100644 (file)
new mode 100755 (executable)
old mode 100644 (file)
new mode 100755 (executable)
old mode 100644 (file)
new mode 100755 (executable)