{
writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_ENABLE,
&vtpreg->vtp0ctrlreg);
- writel(readl(&vtpreg->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
+ writel(readl(&vtpreg->vtp0ctrlreg) & ~(VTP_CTRL_START_EN |
+ VTP_CTRL_FILTER_MASK),
&vtpreg->vtp0ctrlreg);
- writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_START_EN,
+ writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_START_EN |
+ VTP_CTRL_FILTER(3),
&vtpreg->vtp0ctrlreg);
/* Poll for READY */
- while ((readl(&vtpreg->vtp0ctrlreg) & VTP_CTRL_READY) !=
- VTP_CTRL_READY)
+ while (!(readl(&vtpreg->vtp0ctrlreg) & VTP_CTRL_READY))
;
}
/* AM335X EMIF Register values */
#define VTP_CTRL_READY (0x1 << 5)
#define VTP_CTRL_ENABLE (0x1 << 6)
-#define VTP_CTRL_START_EN (0x1)
+#define VTP_CTRL_FILTER_SHIFT 1
+#define VTP_CTRL_FILTER_MASK (0x7 << VTP_CTRL_FILTER_SHIFT)
+#define VTP_CTRL_FILTER(n) (((n) << VTP_CTRL_FILTER_SHIFT) & VTP_CTRL_FILTER_MASK)
+#define VTP_CTRL_START_EN (0x1 << 0)
#define PHY_DLL_LOCK_DIFF 0x0
#define DDR_CKE_CTRL_NORMAL 0x1