Merge branch 'master' of git://git.denx.de/u-boot-video
authorTom Rini <trini@ti.com>
Fri, 7 Jun 2013 12:35:36 +0000 (08:35 -0400)
committerTom Rini <trini@ti.com>
Fri, 7 Jun 2013 12:35:36 +0000 (08:35 -0400)
710 files changed:
.gitignore
MAINTAINERS
MAKEALL
Makefile
README
api/api_platform-powerpc.c
arch/arm/config.mk
arch/arm/cpu/arm1136/mx35/Makefile
arch/arm/cpu/arm1136/mx35/iomux.c [deleted file]
arch/arm/cpu/arm1136/start.S
arch/arm/cpu/arm1176/start.S
arch/arm/cpu/arm720t/start.S
arch/arm/cpu/arm920t/start.S
arch/arm/cpu/arm925t/start.S
arch/arm/cpu/arm926ejs/at91/Makefile
arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c
arch/arm/cpu/arm926ejs/at91/at91sam9n12_devices.c [new file with mode: 0644]
arch/arm/cpu/arm926ejs/at91/clock.c
arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
arch/arm/cpu/arm926ejs/mx25/generic.c
arch/arm/cpu/arm926ejs/mxs/Makefile
arch/arm/cpu/arm926ejs/mxs/clock.c
arch/arm/cpu/arm926ejs/mxs/mxs.c
arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd
arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd
arch/arm/cpu/arm926ejs/start.S
arch/arm/cpu/arm946es/start.S
arch/arm/cpu/arm_intcm/start.S
arch/arm/cpu/armv7/am33xx/clock_ti814x.c
arch/arm/cpu/armv7/am33xx/sys_info.c
arch/arm/cpu/armv7/at91/Makefile [moved from board/alaska/Makefile with 72% similarity]
arch/arm/cpu/armv7/at91/clock.c [new file with mode: 0644]
arch/arm/cpu/armv7/at91/cpu.c [new file with mode: 0644]
arch/arm/cpu/armv7/at91/reset.c [new file with mode: 0644]
arch/arm/cpu/armv7/at91/sama5d3_devices.c [new file with mode: 0644]
arch/arm/cpu/armv7/at91/timer.c [new file with mode: 0644]
arch/arm/cpu/armv7/lowlevel_init.S
arch/arm/cpu/armv7/mx5/Makefile
arch/arm/cpu/armv7/mx5/clock.c
arch/arm/cpu/armv7/mx5/iomux.c [deleted file]
arch/arm/cpu/armv7/mx5/soc.c
arch/arm/cpu/armv7/mx6/clock.c
arch/arm/cpu/armv7/mx6/soc.c
arch/arm/cpu/armv7/omap-common/boot-common.c
arch/arm/cpu/armv7/omap-common/clocks-common.c
arch/arm/cpu/armv7/omap-common/emif-common.c
arch/arm/cpu/armv7/omap-common/hwinit-common.c
arch/arm/cpu/armv7/omap-common/lowlevel_init.S
arch/arm/cpu/armv7/omap-common/reset.c
arch/arm/cpu/armv7/omap4/emif.c
arch/arm/cpu/armv7/omap4/hw_data.c
arch/arm/cpu/armv7/omap4/hwinit.c
arch/arm/cpu/armv7/omap5/emif.c
arch/arm/cpu/armv7/omap5/hw_data.c
arch/arm/cpu/armv7/omap5/hwinit.c
arch/arm/cpu/armv7/omap5/prcm-regs.c
arch/arm/cpu/armv7/start.S
arch/arm/cpu/armv7/zynq/slcr.c
arch/arm/cpu/armv7/zynq/timer.c
arch/arm/cpu/ixp/config.mk
arch/arm/cpu/ixp/start.S
arch/arm/cpu/pxa/pxa2xx.c
arch/arm/cpu/pxa/start.S
arch/arm/cpu/s3c44b0/start.S
arch/arm/cpu/sa1100/start.S
arch/arm/cpu/tegra-common/ap.c
arch/arm/cpu/tegra-common/clock.c
arch/arm/imx-common/Makefile
arch/arm/imx-common/iomux-v3.c
arch/arm/imx-common/misc.c [new file with mode: 0644]
arch/arm/include/asm/arch-am33xx/ddr_defs.h
arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
arch/arm/include/asm/arch-am33xx/omap.h
arch/arm/include/asm/arch-am33xx/sys_proto.h
arch/arm/include/asm/arch-at91/at91_common.h
arch/arm/include/asm/arch-at91/at91_dbu.h
arch/arm/include/asm/arch-at91/at91_pmc.h
arch/arm/include/asm/arch-at91/at91sam9_matrix.h
arch/arm/include/asm/arch-at91/at91sam9x5.h
arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h
arch/arm/include/asm/arch-at91/clk.h
arch/arm/include/asm/arch-at91/hardware.h
arch/arm/include/asm/arch-at91/sama5d3.h [new file with mode: 0644]
arch/arm/include/asm/arch-at91/sama5d3_smc.h [new file with mode: 0644]
arch/arm/include/asm/arch-davinci/hardware.h
arch/arm/include/asm/arch-davinci/nand_defs.h
arch/arm/include/asm/arch-mx25/imx-regs.h
arch/arm/include/asm/arch-mx25/imx25-pinmux.h [deleted file]
arch/arm/include/asm/arch-mx25/iomux-mx25.h [new file with mode: 0644]
arch/arm/include/asm/arch-mx27/imx-regs.h
arch/arm/include/asm/arch-mx31/imx-regs.h
arch/arm/include/asm/arch-mx35/imx-regs.h
arch/arm/include/asm/arch-mx35/iomux-mx35.h [new file with mode: 0644]
arch/arm/include/asm/arch-mx35/iomux.h [deleted file]
arch/arm/include/asm/arch-mx35/mx35_pins.h [deleted file]
arch/arm/include/asm/arch-mx5/clock.h
arch/arm/include/asm/arch-mx5/imx-regs.h
arch/arm/include/asm/arch-mx5/iomux-mx51.h
arch/arm/include/asm/arch-mx5/iomux-mx53.h [new file with mode: 0644]
arch/arm/include/asm/arch-mx5/iomux.h [deleted file]
arch/arm/include/asm/arch-mx5/mx5x_pins.h [deleted file]
arch/arm/include/asm/arch-mx5/spl.h [new file with mode: 0644]
arch/arm/include/asm/arch-mx6/clock.h
arch/arm/include/asm/arch-mx6/crm_regs.h
arch/arm/include/asm/arch-mx6/imx-regs.h
arch/arm/include/asm/arch-mx6/mx6-pins.h
arch/arm/include/asm/arch-mx6/mx6dl_pins.h
arch/arm/include/asm/arch-mx6/mx6q_pins.h
arch/arm/include/asm/arch-mx6/mx6sl_pins.h [new file with mode: 0644]
arch/arm/include/asm/arch-mx6/sys_proto.h
arch/arm/include/asm/arch-mxs/clock.h
arch/arm/include/asm/arch-mxs/imx-regs.h
arch/arm/include/asm/arch-mxs/iomux.h
arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h
arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h
arch/arm/include/asm/arch-mxs/regs-digctl.h
arch/arm/include/asm/arch-mxs/regs-i2c.h
arch/arm/include/asm/arch-mxs/regs-lcdif.h
arch/arm/include/asm/arch-mxs/regs-lradc.h
arch/arm/include/asm/arch-mxs/regs-ocotp.h
arch/arm/include/asm/arch-mxs/regs-pinctrl.h
arch/arm/include/asm/arch-mxs/regs-power-mx23.h
arch/arm/include/asm/arch-mxs/regs-power-mx28.h
arch/arm/include/asm/arch-mxs/regs-rtc.h
arch/arm/include/asm/arch-mxs/regs-ssp.h
arch/arm/include/asm/arch-mxs/regs-timrot.h
arch/arm/include/asm/arch-omap4/omap.h
arch/arm/include/asm/arch-omap4/sys_proto.h
arch/arm/include/asm/arch-omap5/clocks.h
arch/arm/include/asm/arch-omap5/cpu.h
arch/arm/include/asm/arch-omap5/i2c.h
arch/arm/include/asm/arch-omap5/omap.h
arch/arm/include/asm/arch-omap5/sys_proto.h
arch/arm/include/asm/arch-pxa/hardware.h
arch/arm/include/asm/arch-tegra/tegra.h
arch/arm/include/asm/arch-zynq/hardware.h
arch/arm/include/asm/arch-zynq/sys_proto.h
arch/arm/include/asm/bootm.h
arch/arm/include/asm/global_data.h
arch/arm/include/asm/imx-common/dma.h [moved from arch/arm/include/asm/arch-mxs/dma.h with 93% similarity]
arch/arm/include/asm/imx-common/imximage.cfg [new file with mode: 0644]
arch/arm/include/asm/imx-common/iomux-v3.h
arch/arm/include/asm/imx-common/regs-apbh.h [moved from arch/arm/include/asm/arch-mxs/regs-apbh.h with 97% similarity]
arch/arm/include/asm/imx-common/regs-bch.h [moved from arch/arm/include/asm/arch-mxs/regs-bch.h with 96% similarity]
arch/arm/include/asm/imx-common/regs-common.h [moved from arch/arm/include/asm/arch-mxs/regs-common.h with 100% similarity]
arch/arm/include/asm/imx-common/regs-gpmi.h [moved from arch/arm/include/asm/arch-mxs/regs-gpmi.h with 99% similarity]
arch/arm/include/asm/omap_boot.h [new file with mode: 0644]
arch/arm/include/asm/omap_common.h
arch/arm/include/asm/u-boot-arm.h
arch/arm/lib/Makefile
arch/arm/lib/bootm-fdt.c [moved from drivers/tpm/slb9635_i2c/compatibility.h with 51% similarity]
arch/arm/lib/bootm.c
arch/arm/lib/relocate.S [new file with mode: 0644]
arch/avr32/lib/board.c
arch/blackfin/cpu/Makefile
arch/blackfin/cpu/cpu.c
arch/blackfin/cpu/gpio.c
arch/blackfin/cpu/initcode.c
arch/blackfin/cpu/start.S
arch/blackfin/include/asm/clock.h [new file with mode: 0644]
arch/blackfin/include/asm/dma.h
arch/blackfin/include/asm/gpio.h
arch/blackfin/include/asm/mach-bf561/BF561_def.h
arch/blackfin/include/asm/mach-bf609/BF609_def.h
arch/blackfin/include/asm/portmux.h
arch/blackfin/include/asm/serial.h [moved from arch/blackfin/cpu/serial.h with 82% similarity]
arch/blackfin/include/asm/serial1.h [moved from arch/blackfin/cpu/serial1.h with 94% similarity]
arch/blackfin/include/asm/serial4.h [moved from arch/blackfin/cpu/serial4.h with 86% similarity]
arch/blackfin/include/asm/soft_switch.h [new file with mode: 0644]
arch/blackfin/lib/board.c
arch/blackfin/lib/clocks.c
arch/blackfin/lib/string.c
arch/m68k/lib/bootm.c
arch/microblaze/include/asm/gpio.h
arch/microblaze/lib/bootm.c
arch/nds32/include/asm/u-boot-nds32.h
arch/nds32/lib/board.c
arch/openrisc/config.mk
arch/openrisc/cpu/u-boot.lds [moved from board/openrisc/openrisc-generic/u-boot.lds with 98% similarity]
arch/powerpc/cpu/mpc512x/Makefile
arch/powerpc/cpu/mpc512x/cpu_init.c
arch/powerpc/cpu/mpc512x/iim.c [deleted file]
arch/powerpc/cpu/mpc8220/config.mk [deleted file]
arch/powerpc/cpu/mpc8220/cpu.c [deleted file]
arch/powerpc/cpu/mpc8220/cpu_init.c [deleted file]
arch/powerpc/cpu/mpc8220/dma.h [deleted file]
arch/powerpc/cpu/mpc8220/dramSetup.c [deleted file]
arch/powerpc/cpu/mpc8220/dramSetup.h [deleted file]
arch/powerpc/cpu/mpc8220/fec.c [deleted file]
arch/powerpc/cpu/mpc8220/fec.h [deleted file]
arch/powerpc/cpu/mpc8220/fec_dma_tasks.S [deleted file]
arch/powerpc/cpu/mpc8220/i2c.c [deleted file]
arch/powerpc/cpu/mpc8220/i2cCore.c [deleted file]
arch/powerpc/cpu/mpc8220/i2cCore.h [deleted file]
arch/powerpc/cpu/mpc8220/interrupts.c [deleted file]
arch/powerpc/cpu/mpc8220/io.S [deleted file]
arch/powerpc/cpu/mpc8220/loadtask.c [deleted file]
arch/powerpc/cpu/mpc8220/pci.c [deleted file]
arch/powerpc/cpu/mpc8220/speed.c [deleted file]
arch/powerpc/cpu/mpc8220/start.S [deleted file]
arch/powerpc/cpu/mpc8220/traps.c [deleted file]
arch/powerpc/cpu/mpc8220/u-boot.lds [deleted file]
arch/powerpc/cpu/mpc8220/uart.c [deleted file]
arch/powerpc/cpu/mpc85xx/Makefile
arch/powerpc/cpu/mpc85xx/cpu_init.c
arch/powerpc/cpu/mpc85xx/cpu_init_early.c
arch/powerpc/cpu/mpc85xx/ddr-gen3.c
arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
arch/powerpc/cpu/mpc85xx/mp.c
arch/powerpc/cpu/mpc85xx/portals.c
arch/powerpc/cpu/mpc85xx/release.S
arch/powerpc/cpu/mpc85xx/speed.c
arch/powerpc/cpu/mpc85xx/start.S
arch/powerpc/cpu/mpc85xx/t1040_ids.c [new file with mode: 0644]
arch/powerpc/cpu/mpc85xx/t1040_serdes.c [new file with mode: 0644]
arch/powerpc/cpu/mpc85xx/t4240_serdes.c
arch/powerpc/cpu/mpc8xxx/cpu.c
arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
arch/powerpc/cpu/mpc8xxx/ddr/main.c
arch/powerpc/include/asm/config_mpc85xx.h
arch/powerpc/include/asm/fsl_law.h
arch/powerpc/include/asm/fsl_secure_boot.h
arch/powerpc/include/asm/fsl_serdes.h
arch/powerpc/include/asm/global_data.h
arch/powerpc/include/asm/immap_512x.h
arch/powerpc/include/asm/immap_8220.h [deleted file]
arch/powerpc/include/asm/immap_85xx.h
arch/powerpc/include/asm/processor.h
arch/powerpc/include/asm/u-boot.h
arch/powerpc/lib/board.c
arch/powerpc/lib/bootm.c
arch/sparc/lib/bootm.c
arch/x86/cpu/Makefile
arch/x86/cpu/coreboot/coreboot.c
arch/x86/cpu/coreboot/timestamp.c
arch/x86/cpu/cpu.c
arch/x86/cpu/interrupts.c
arch/x86/cpu/timer.c [deleted file]
arch/x86/cpu/u-boot.lds
arch/x86/include/asm/arch-coreboot/timestamp.h
arch/x86/include/asm/init_helpers.h
arch/x86/include/asm/pci.h
arch/x86/include/asm/u-boot-x86.h
arch/x86/include/asm/u-boot.h
arch/x86/lib/Makefile
arch/x86/lib/bios.h [deleted file]
arch/x86/lib/board.c [deleted file]
arch/x86/lib/bootm.c
arch/x86/lib/cmd_boot.c
arch/x86/lib/init_helpers.c
arch/x86/lib/init_wrappers.c [deleted file]
arch/x86/lib/pcat_timer.c
arch/x86/lib/pci.c [deleted file]
arch/x86/lib/physmem.c
arch/x86/lib/relocate.c
arch/x86/lib/timer.c [deleted file]
arch/x86/lib/tsc_timer.c [new file with mode: 0644]
arch/x86/lib/zimage.c
board/CarMediaLab/flea3/flea3.c
board/LaCie/net2big_v2/kwbimage.cfg
board/LaCie/netspace_v2/kwbimage-is2.cfg
board/LaCie/netspace_v2/kwbimage-ns2l.cfg
board/LaCie/netspace_v2/kwbimage.cfg
board/LaCie/wireless_space/kwbimage.cfg
board/Marvell/dreamplug/kwbimage.cfg
board/Marvell/guruplug/kwbimage.cfg
board/Marvell/mv88f6281gtw_ge/kwbimage.cfg
board/Marvell/openrd/kwbimage.cfg
board/Marvell/rd6281a/kwbimage.cfg
board/Seagate/dockstar/kwbimage.cfg
board/Seagate/goflexhome/Makefile [new file with mode: 0644]
board/Seagate/goflexhome/goflexhome.c [new file with mode: 0644]
board/Seagate/goflexhome/kwbimage.cfg [new file with mode: 0644]
board/ait/cam_enc_4xx/cam_enc_4xx.c
board/alaska/README [deleted file]
board/alaska/alaska.c [deleted file]
board/alaska/flash.c [deleted file]
board/armltd/vexpress/Makefile
board/armltd/vexpress/vexpress_common.c [moved from board/armltd/vexpress/ca9x4_ct_vxp.c with 89% similarity]
board/atmel/at91sam9260ek/at91sam9260ek.c
board/atmel/at91sam9n12ek/Makefile [new file with mode: 0644]
board/atmel/at91sam9n12ek/at91sam9n12ek.c [new file with mode: 0644]
board/atmel/sama5d3xek/Makefile [moved from arch/powerpc/cpu/mpc8220/Makefile with 67% similarity]
board/atmel/sama5d3xek/sama5d3xek.c [new file with mode: 0644]
board/bf609-ezkit/soft_switch.c [new file with mode: 0644]
board/bf609-ezkit/soft_switch.h [new file with mode: 0644]
board/boundary/nitrogen6x/clocks.cfg
board/boundary/nitrogen6x/nitrogen6dl.cfg
board/boundary/nitrogen6x/nitrogen6dl2g.cfg
board/boundary/nitrogen6x/nitrogen6q.cfg
board/boundary/nitrogen6x/nitrogen6q2g.cfg
board/boundary/nitrogen6x/nitrogen6s.cfg
board/boundary/nitrogen6x/nitrogen6s1g.cfg
board/boundary/nitrogen6x/nitrogen6x.c
board/buffalo/lsxl/kwbimage-lschl.cfg
board/buffalo/lsxl/kwbimage-lsxhl.cfg
board/cloudengines/pogo_e02/kwbimage.cfg
board/compulab/cm_t35/Makefile [moved from board/cm_t35/Makefile with 82% similarity]
board/compulab/cm_t35/cm_t35.c [moved from board/cm_t35/cm_t35.c with 96% similarity]
board/compulab/cm_t35/display.c [moved from board/cm_t35/display.c with 99% similarity]
board/compulab/cm_t35/eeprom.c [moved from board/cm_t35/eeprom.c with 100% similarity]
board/compulab/cm_t35/eeprom.h [moved from board/cm_t35/eeprom.h with 100% similarity]
board/compulab/cm_t35/leds.c [moved from board/cm_t35/leds.c with 95% similarity]
board/d-link/dns325/kwbimage.cfg
board/denx/m53evk/Makefile [moved from board/sorcery/Makefile with 79% similarity]
board/denx/m53evk/imximage.cfg [new file with mode: 0644]
board/denx/m53evk/m53evk.c [new file with mode: 0644]
board/esg/ima3-mx53/ima3-mx53.c
board/esg/ima3-mx53/imximage.cfg
board/freescale/b4860qds/b4860qds.c
board/freescale/b4860qds/b4860qds_crossbar_con.h
board/freescale/b4860qds/ddr.c
board/freescale/b4860qds/eth_b4860qds.c
board/freescale/b4860qds/law.c
board/freescale/b4860qds/tlb.c
board/freescale/common/qixis.h
board/freescale/corenet_ds/eth_superhydra.c
board/freescale/corenet_ds/pbi.cfg
board/freescale/corenet_ds/rcw_p5040ds.cfg [new file with mode: 0644]
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
board/freescale/mx23evk/spl_boot.c
board/freescale/mx25pdk/imximage.cfg
board/freescale/mx25pdk/mx25pdk.c
board/freescale/mx31pdk/mx31pdk.c
board/freescale/mx35pdk/mx35pdk.c
board/freescale/mx51evk/imximage.cfg
board/freescale/mx51evk/mx51evk.c
board/freescale/mx51evk/mx51evk_video.c
board/freescale/mx53ard/imximage_dd3.cfg
board/freescale/mx53ard/mx53ard.c
board/freescale/mx53evk/imximage.cfg
board/freescale/mx53evk/mx53evk.c
board/freescale/mx53loco/imximage.cfg
board/freescale/mx53loco/mx53loco.c
board/freescale/mx53loco/mx53loco_video.c
board/freescale/mx53smd/imximage.cfg
board/freescale/mx53smd/mx53smd.c
board/freescale/mx6qarm2/imximage.cfg
board/freescale/mx6qarm2/mx6qarm2.c
board/freescale/mx6qsabreauto/imximage.cfg
board/freescale/mx6qsabreauto/mx6qsabreauto.c
board/freescale/mx6qsabrelite/mx6qsabrelite.c
board/freescale/mx6qsabresd/mx6qsabresd.c
board/freescale/mx6slevk/Makefile [new file with mode: 0644]
board/freescale/mx6slevk/imximage.cfg [new file with mode: 0644]
board/freescale/mx6slevk/mx6slevk.c [new file with mode: 0644]
board/freescale/p2041rdb/p2041rdb.c
board/freescale/t4qds/ddr.c
board/freescale/t4qds/eth.c
board/freescale/t4qds/law.c
board/freescale/t4qds/t4240qds_qixis.h
board/freescale/t4qds/t4_pbi.cfg [new file with mode: 0644]
board/freescale/t4qds/t4_rcw.cfg [new file with mode: 0644]
board/freescale/t4qds/t4qds.c
board/freescale/t4qds/tlb.c
board/freescale/titanium/Makefile [new file with mode: 0644]
board/freescale/titanium/imximage.cfg [new file with mode: 0644]
board/freescale/titanium/titanium.c [new file with mode: 0644]
board/genesi/mx51_efikamx/efikamx-usb.c
board/genesi/mx51_efikamx/efikamx.c
board/genesi/mx51_efikamx/imximage_mx.cfg
board/genesi/mx51_efikamx/imximage_sb.cfg
board/h2200/h2200.c
board/iomega/iconnect/kwbimage.cfg
board/isee/igep0033/Makefile [new file with mode: 0644]
board/isee/igep0033/board.c [new file with mode: 0644]
board/isee/igep0033/board.h [new file with mode: 0644]
board/isee/igep0033/mux.c [new file with mode: 0644]
board/karo/tk71/kwbimage.cfg
board/karo/tx25/tx25.c
board/keymile/km_arm/kwbimage-memphis.cfg
board/keymile/km_arm/kwbimage.cfg
board/keymile/km_arm/kwbimage_128M16_1.cfg
board/keymile/km_arm/kwbimage_256M8_1.cfg
board/nokia/rx51/rx51.c
board/nvidia/beaver/Makefile [new file with mode: 0644]
board/olimex/mx23_olinuxino/spl_boot.c
board/pandora/pandora.c
board/phytec/pcm051/board.c
board/raidsonic/ib62x0/kwbimage.cfg
board/sorcery/sorcery.c [deleted file]
board/syteco/zmx25/zmx25.c
board/ti/am335x/board.c
board/ti/beagle/beagle.c
board/ti/dra7xx/evm.c
board/ti/omap5_uevm/evm.c
board/ti/panda/panda.c
board/ti/ti814x/evm.c
board/ti/ti814x/evm.h
board/ti/ti814x/mux.c
board/ttcontrol/vision2/imximage_hynix.cfg
board/ttcontrol/vision2/vision2.c
board/wandboard/wandboard.c
board/woodburn/woodburn.c
board/xilinx/microblaze-generic/microblaze-generic.c
board/xilinx/zynq/board.c
boards.cfg
common/Makefile
common/board_f.c
common/board_r.c
common/bootstage.c
common/cmd_bdinfo.c
common/cmd_bootm.c
common/cmd_fitupd.c
common/cmd_fpga.c
common/cmd_fuse.c [new file with mode: 0644]
common/cmd_mem.c
common/cmd_nand.c
common/cmd_nvedit.c
common/cmd_onenand.c
common/cmd_softswitch.c [new file with mode: 0644]
common/cmd_source.c
common/cmd_usb.c
common/cmd_ximg.c
common/env_onenand.c
common/fdt_support.c
common/hash.c
common/image-fdt.c [new file with mode: 0644]
common/image-fit.c [new file with mode: 0644]
common/image.c
common/main.c
common/spl/Makefile
common/spl/spl.c
common/spl/spl_mmc.c [moved from drivers/mmc/spl_mmc.c with 100% similarity]
common/update.c
common/usb.c
common/usb_hub.c
common/usb_kbd.c
common/usb_storage.c
config.mk
disk/part_efi.c
doc/README.at91
doc/README.b4860qds
doc/README.fdt-control
doc/README.fsl_iim [new file with mode: 0644]
doc/README.fuse [new file with mode: 0644]
doc/README.imx25 [new file with mode: 0644]
doc/README.imx27 [new file with mode: 0644]
doc/README.imx5
doc/README.imx6 [new file with mode: 0644]
doc/README.imximage
doc/README.mxc_ocotp [new file with mode: 0644]
doc/README.omap-reset-time [new file with mode: 0644]
doc/README.scrapyard
doc/README.t4240qds
doc/README.ubi
doc/README.watchdog
doc/SPL/README.am335x-network
doc/driver-model/UDM-pci.txt
drivers/dma/apbh_dma.c
drivers/fpga/Makefile
drivers/fpga/fpga.c
drivers/fpga/xilinx.c
drivers/fpga/zynqpl.c [new file with mode: 0644]
drivers/gpio/Makefile
drivers/gpio/adi_gpio2.c [new file with mode: 0644]
drivers/gpio/xilinx_gpio.c [new file with mode: 0644]
drivers/i2c/Makefile
drivers/i2c/zynq_i2c.c [new file with mode: 0644]
drivers/input/key_matrix.c
drivers/misc/Makefile
drivers/misc/fsl_iim.c [new file with mode: 0644]
drivers/misc/mxc_ocotp.c [new file with mode: 0644]
drivers/misc/twl4030_led.c
drivers/mmc/Makefile
drivers/mmc/davinci_mmc.c
drivers/mmc/fsl_esdhc.c
drivers/mmc/ftsdc010_esdhc.c [deleted file]
drivers/mmc/ftsdc010_mci.c [new file with mode: 0644]
drivers/mmc/gen_atmel_mci.c
drivers/mmc/mmc.c
drivers/mmc/mv_sdhci.c
drivers/mmc/mxsmmc.c
drivers/mmc/omap_hsmmc.c
drivers/mmc/s5p_sdhci.c
drivers/mmc/spear_sdhci.c [new file with mode: 0644]
drivers/mmc/zynq_sdhci.c [new file with mode: 0644]
drivers/mtd/Makefile
drivers/mtd/cfi_flash.c
drivers/mtd/cfi_mtd.c
drivers/mtd/mtdconcat.c
drivers/mtd/mtdcore.c
drivers/mtd/mtdpart.c
drivers/mtd/nand/Makefile
drivers/mtd/nand/atmel_nand.c
drivers/mtd/nand/bfin_nand.c
drivers/mtd/nand/davinci_nand.c
drivers/mtd/nand/diskonchip.c
drivers/mtd/nand/docg4.c [new file with mode: 0644]
drivers/mtd/nand/docg4_spl.c [new file with mode: 0644]
drivers/mtd/nand/fsl_elbc_nand.c
drivers/mtd/nand/fsl_ifc_nand.c
drivers/mtd/nand/fsmc_nand.c
drivers/mtd/nand/jz4740_nand.c
drivers/mtd/nand/mpc5121_nfc.c
drivers/mtd/nand/mxc_nand.c
drivers/mtd/nand/mxc_nand_spl.c
drivers/mtd/nand/mxs_nand.c
drivers/mtd/nand/nand_base.c
drivers/mtd/nand/nand_bbt.c
drivers/mtd/nand/nand_ids.c
drivers/mtd/nand/nand_util.c
drivers/mtd/nand/ndfc.c
drivers/mtd/nand/nomadik.c
drivers/mtd/nand/omap_gpmc.c
drivers/mtd/nand/s3c2410_nand.c
drivers/mtd/nand/tegra_nand.c
drivers/mtd/nand/tegra_nand.h
drivers/mtd/onenand/onenand_base.c
drivers/mtd/onenand/onenand_bbt.c
drivers/mtd/spi/spansion.c
drivers/mtd/ubi/build.c
drivers/mtd/ubi/eba.c
drivers/mtd/ubi/io.c
drivers/mtd/ubi/kapi.c
drivers/mtd/ubi/misc.c
drivers/mtd/ubi/vtbl.c
drivers/net/bfin_mac.c
drivers/net/cpsw.c
drivers/net/fm/Makefile
drivers/net/fm/b4860.c
drivers/net/fm/eth.c
drivers/net/fm/fm.h
drivers/net/fm/init.c
drivers/net/fm/t4240.c
drivers/net/phy/Makefile
drivers/net/phy/et1011c.c [new file with mode: 0644]
drivers/net/phy/marvell.c
drivers/net/phy/phy.c
drivers/net/phy/teranetics.c
drivers/net/phy/vitesse.c
drivers/net/smc911x.h
drivers/net/zynq_gem.c
drivers/power/Makefile
drivers/power/palmas.c [moved from drivers/power/twl6035.c with 61% similarity]
drivers/power/twl4030.c
drivers/power/twl6030.c
drivers/serial/Makefile
drivers/serial/serial.c
drivers/serial/serial_bfin.c [moved from arch/blackfin/cpu/serial.c with 79% similarity]
drivers/spi/atmel_spi.c
drivers/spi/atmel_spi.h
drivers/spi/bfin_spi.c
drivers/spi/mxs_spi.c
drivers/tpm/Makefile
drivers/tpm/tis_i2c.c
drivers/tpm/tpm.c [moved from drivers/tpm/slb9635_i2c/tpm.c with 63% similarity]
drivers/tpm/tpm_private.h [moved from drivers/tpm/slb9635_i2c/tpm.h with 71% similarity]
drivers/tpm/tpm_tis_i2c.c [moved from drivers/tpm/slb9635_i2c/tpm_tis_i2c.c with 59% similarity]
drivers/tpm/tpm_tis_lpc.c [moved from drivers/tpm/generic_lpc_tpm.c with 100% similarity]
drivers/usb/eth/smsc95xx.c
drivers/usb/gadget/pxa27x_udc.c
drivers/usb/host/ehci-hcd.c
drivers/usb/host/ehci-mx5.c
drivers/usb/host/ohci-at91.c
drivers/usb/phy/twl4030.c
drivers/video/Makefile
drivers/video/cfb_console.c
drivers/video/mxsfb.c [new file with mode: 0644]
drivers/video/pxa_lcd.c
drivers/watchdog/Makefile
drivers/watchdog/bfin_wdt.c [moved from arch/blackfin/cpu/watchdog.c with 64% similarity]
fs/ext4/dev.c
fs/ext4/ext4_common.c
fs/ext4/ext4_common.h
fs/ext4/ext4_journal.c
fs/ext4/ext4_write.c
fs/ext4/ext4fs.c
fs/yaffs2/yaffs_mtdif.c
fs/yaffs2/yaffs_mtdif2.c
include/altera.h
include/asm-generic/u-boot.h
include/atmel_mci.h
include/bootstage.h
include/common.h
include/config_cmd_all.h
include/configs/Alaska8220.h [deleted file]
include/configs/B4860QDS.h
include/configs/M54455EVB.h
include/configs/MERGERBOX.h
include/configs/MVBC_P.h
include/configs/MVBLM7.h
include/configs/MVSMR.h
include/configs/P1022DS.h
include/configs/T4240QDS.h
include/configs/Yukon8220.h [deleted file]
include/configs/ac14xx.h
include/configs/am335x_evm.h
include/configs/aria.h
include/configs/at91sam9260ek.h
include/configs/at91sam9n12ek.h [new file with mode: 0644]
include/configs/bf527-ezkit.h
include/configs/bf537-stamp.h
include/configs/bf548-ezkit.h
include/configs/bf561-ezkit.h
include/configs/bf609-ezkit.h
include/configs/bfin_adi_common.h
include/configs/cm_t35.h
include/configs/coreboot.h
include/configs/corenet_ds.h
include/configs/da830evm.h
include/configs/da850evm.h
include/configs/enbw_cmc.h
include/configs/exynos5250-dt.h
include/configs/goflexhome.h [new file with mode: 0644]
include/configs/igep0033.h [new file with mode: 0644]
include/configs/ima3-mx53.h
include/configs/m28evk.h
include/configs/m53evk.h [new file with mode: 0644]
include/configs/mecp5123.h
include/configs/microblaze-generic.h
include/configs/mpc5121ads.h
include/configs/mx28evk.h
include/configs/mx51evk.h
include/configs/mx53ard.h
include/configs/mx53evk.h
include/configs/mx53smd.h
include/configs/mx6_common.h
include/configs/mx6qsabre_common.h
include/configs/mx6qsabrelite.h
include/configs/mx6slevk.h [new file with mode: 0644]
include/configs/nitrogen6x.h
include/configs/omap3_mvblx.h
include/configs/omap4_common.h
include/configs/omap4_panda.h
include/configs/omap5_common.h
include/configs/omap5_uevm.h
include/configs/pcm051.h
include/configs/pdm360ng.h
include/configs/pm9263.h
include/configs/sama5d3xek.h [new file with mode: 0644]
include/configs/sorcery.h [deleted file]
include/configs/t4qds.h
include/configs/tegra-common-post.h
include/configs/tegra114-common.h
include/configs/tegra20-common.h
include/configs/tegra30-common.h
include/configs/ti814x_evm.h
include/configs/titanium.h [new file with mode: 0644]
include/configs/tnetv107x_evm.h
include/configs/vexpress_ca15_tc2.h [moved from arch/x86/include/asm/init_wrappers.h with 56% similarity]
include/configs/vexpress_ca5x2.h [new file with mode: 0644]
include/configs/vexpress_ca9x4.h [moved from arch/arm/include/asm/arch-mx25/sys_proto.h with 61% similarity]
include/configs/vexpress_common.h [moved from include/configs/ca9x4_ct_vxp.h with 56% similarity]
include/configs/wandboard.h
include/configs/zynq.h
include/ext4fs.h
include/ext_common.h
include/faraday/ftsdc010.h
include/fdt.h
include/fdt_support.h
include/fdtdec.h
include/fm_eth.h
include/fpga.h
include/fuse.h [new file with mode: 0644]
include/hash.h
include/image.h
include/lattice.h
include/libfdt.h
include/libfdt_env.h
include/linux/bitrev.h [new file with mode: 0644]
include/linux/mtd/bbm.h
include/linux/mtd/docg4.h [new file with mode: 0644]
include/linux/mtd/mtd.h
include/linux/mtd/nand.h
include/linux/string.h
include/lmb.h
include/mmc.h
include/mpc8220.h [deleted file]
include/mtd/cfi_flash.h
include/mtd/mtd-abi.h [moved from include/linux/mtd/mtd-abi.h with 65% similarity]
include/nand.h
include/net.h
include/netdev.h
include/palmas.h [moved from include/twl6035.h with 68% similarity]
include/phy.h
include/ppc_asm.tmpl
include/spl.h
include/twl4030.h
include/twl6030.h
include/usb.h
include/usb/ehci-fsl.h
include/usb_defs.h
include/watchdog.h
include/xilinx.h
include/zynqpl.h [new file with mode: 0644]
lib/Makefile
lib/bitrev.c [new file with mode: 0644]
lib/fdtdec.c
lib/hashtable.c
lib/libfdt/fdt.c
lib/libfdt/fdt_ro.c
lib/string.c
spl/Makefile
test/image/test-fit.py [new file with mode: 0755]
tools/Makefile
tools/aisimage.c
tools/buildman/control.py
tools/checkpatch.pl
tools/fit_image.c
tools/image-host.c [new file with mode: 0644]
tools/imximage.c
tools/imximage.h
tools/mkimage.h
tools/mxsboot.c
tools/patman/gitutil.py
tools/patman/patman.py
tools/patman/series.py

index ed21203..771b860 100644 (file)
@@ -46,6 +46,7 @@
 /u-boot.ais
 /u-boot.dtb
 /u-boot.sb
+/u-boot.bd
 /u-boot.geany
 
 #
@@ -79,5 +80,11 @@ cscope.*
 /ctags
 /etags
 
+# gnu global files
+GPATH
+GRTAGS
+GSYMS
+GTAGS
+
 # spl ais files
 /spl/*.ais
index 643a5ac..14075af 100644 (file)
@@ -607,6 +607,7 @@ Enric Balletbo i Serra <eballetbo@iseebcn.com>
        igep0020        ARM ARMV7 (OMAP3xx SoC)
        igep0030        ARM ARMV7 (OMAP3xx SoC)
        igep0032        ARM ARMV7 (OMAP3xx SoC)
+       igep0033        ARM ARMV7 (AM33xx Soc)
 
 Eric Benard <eric@eukrea.com>
 
@@ -664,6 +665,7 @@ Fabio Estevam <fabio.estevam@freescale.com>
        mx6qsabresd     i.MX6Q
        mx6qsabreauto   i.MX6Q
        wandboard       i.MX6DL/S
+       mx6slevk        i.MX6SL
 
 Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
 
@@ -683,7 +685,7 @@ Simon Guinot <simon.guinot@sequanux.org>
 
 Igor Grinberg <grinberg@compulab.co.il>
 
-       cm-t35          ARM ARMV7 (OMAP3xx Soc)
+       cm_t35          ARM ARMV7 (OMAP3xx Soc)
 
 Stefan Herbrechtsmeier <stefan@code.herbrechtsmeier.net>
 
@@ -848,6 +850,10 @@ Sricharan R <r.sricharan@ti.com>
        omap4_sdp4430   ARM ARMV7 (OMAP4xx SoC)
        omap5_evm       ARM ARMV7 (OMAP5xx Soc)
 
+Suriyan Ramasami <suriyan.r@gmail.com>
+
+       goflexhome      ARM926EJS (Kirkwood SoC)
+
 Thierry Reding <thierry.reding@avionic-design.de>
 
        plutux          Tegra20 (ARM7 & A9 Dual Core)
@@ -877,6 +883,8 @@ Stefan Roese <sr@denx.de>
 
        x600            ARM926EJS (spear600 Soc)
 
+       titanium        i.MX6Q
+
        pdnb3           xscale/ixp
        scpu            xscale/ixp
 
@@ -914,6 +922,7 @@ Matt Sealey <matt@genesi-usa.com>
 
 Bo Shen <voice.shen@atmel.com>
        at91sam9x5ek            ARM926EJS (AT91SAM9G15,G25,G35,X25,X35 SoC)
+       sama5d3xek              ARMV7 (SAMA5D31, D33, D34, D35 SoC)
 
 Rajeshwari Shinde <rajeshwari.s@samsung.com>
 
@@ -954,6 +963,7 @@ Marek Vasut <marek.vasut@gmail.com>
        mx23_olinuxino  i.MX23
        m28evk          i.MX28
        sc_sps_1        i.MX28
+       m53evk          i.MX53
 
 Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
 
@@ -961,7 +971,8 @@ Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
 
 Matt Waddel <matt.waddel@linaro.org>
 
-       ca9x4_ct_vxp    ARM ARMV7 (Quad Core)
+       vexpress_ca9x4  ARM ARMV7 (Quad Core)
+       vexpress_ca5x2  ARM ARMV7 (Dual Core)
 
 Otavio Salvador <otavio@ossystems.com.br>
 
@@ -1018,6 +1029,9 @@ Richard Woodruff <r-woodruff2@ti.com>
 
        omap2420h4      ARM1136EJS
 
+Josh Wu <josh.wu@atmel.com>
+       at91sam9n12ek   ARM926EJS (AT91SAM9N12 SoC)
+
 Ilya Yanok <yanok@emcraft.com>
 
        mcx             ARM ARMV7 (AM35x SoC)
@@ -1072,9 +1086,19 @@ Unknown / orphaned boards:
 #      Board           CPU                                             #
 #########################################################################
 
-Graeme Russ <graeme.russ@gmail.com>
+Simon Glass <sjg@chromium.org>
 
-       eNET            AMD SC520
+       chromebook-x86  Coreboot runs first, then U-Boot
+                       Supports Intel Sandy Bridge / Ivy Bridge so far
+
+                       Chromebooks for x86, including:
+                               Samsung Series 5 Chromebook
+                               Acer AC700 Chromebook
+                               Acer C7 Chromebook
+                               Samsung Chromebook 550
+                               HP Pavillion Chromebook
+                               Acer C710 Chromebook
+                               Chromebook Pixel
 
 #########################################################################
 # MIPS Systems:                                                                #
@@ -1339,6 +1363,17 @@ Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
 
        openrisc-generic        OpenRISC
 
+#########################################################################
+# Sandbox:                                                             #
+#                                                                      #
+# Maintainer Name, Email Address                                       #
+#      Board           CPU                                             #
+#########################################################################
+
+Simon Glass <sjg@chromium.org>
+
+       sandbox         sandbox
+
 #########################################################################
 # End of MAINTAINERS list                                              #
 #########################################################################
diff --git a/MAKEALL b/MAKEALL
index 2737eab..2e16e0d 100755 (executable)
--- a/MAKEALL
+++ b/MAKEALL
@@ -267,12 +267,6 @@ LIST_8xx="$(boards_by_cpu mpc8xx)"
 
 LIST_4xx="$(boards_by_cpu ppc4xx)"
 
-#########################################################################
-## MPC8220 Systems
-#########################################################################
-
-LIST_8220="$(boards_by_cpu mpc8220)"
-
 #########################################################################
 ## MPC824x Systems
 #########################################################################
@@ -324,7 +318,6 @@ LIST_powerpc="              \
        ${LIST_512x}    \
        ${LIST_5xxx}    \
        ${LIST_8xx}     \
-       ${LIST_8220}    \
        ${LIST_824x}    \
        ${LIST_8260}    \
        ${LIST_83xx}    \
index dbc4b70..ef154aa 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -341,7 +341,7 @@ ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(C
 LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
 endif
 
-ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs))
 LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
 endif
 
@@ -522,13 +522,9 @@ $(obj)u-boot.ais:       $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
                cat $(obj)spl/u-boot-spl-pad.ais $(obj)u-boot.img > \
                        $(obj)u-boot.ais
 
-# Specify the target for use in elftosb call
-ELFTOSB_TARGET-$(CONFIG_MX23) = imx23
-ELFTOSB_TARGET-$(CONFIG_MX28) = imx28
 
 $(obj)u-boot.sb:       $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin
-               elftosb -zf $(ELFTOSB_TARGET-y) -c $(TOPDIR)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd \
-                       -o $(obj)u-boot.sb
+               $(MAKE) -C $(SRCTREE)/$(CPUDIR)/$(SOC)/ $(OBJTREE)/u-boot.sb
 
 # On x600 (SPEAr600) U-Boot is appended to U-Boot SPL.
 # Both images are created using mkimage (crc etc), so that the ROM
@@ -547,18 +543,15 @@ $(obj)u-boot.spr: $(obj)u-boot.img $(obj)spl/u-boot-spl.bin
                cat $(obj)spl/u-boot-spl-pad.img $(obj)u-boot.img > $@
 
 ifneq ($(CONFIG_TEGRA),)
-ifeq ($(CONFIG_OF_SEPARATE),y)
-nodtb=dtb
-dtbfile=$(obj)u-boot.dtb
-else
-nodtb=nodtb
-dtbfile=
-endif
-
-$(obj)u-boot-$(nodtb)-tegra.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin $(dtbfile)
+$(obj)u-boot-nodtb-tegra.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
                $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SYS_TEXT_BASE) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
-               cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin $(dtbfile) > $@
+               cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@
                rm $(obj)spl/u-boot-spl-pad.bin
+
+ifeq ($(CONFIG_OF_SEPARATE),y)
+$(obj)u-boot-dtb-tegra.bin: $(obj)u-boot-nodtb-tegra.bin $(obj)u-boot.dtb
+               cat $(obj)u-boot-nodtb-tegra.bin $(obj)u-boot.dtb > $@
+endif
 endif
 
 $(obj)u-boot-img.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
@@ -871,6 +864,7 @@ clobber:    tidy
        @rm -f $(obj)u-boot.ais
        @rm -f $(obj)u-boot.dtb
        @rm -f $(obj)u-boot.sb
+       @rm -f $(obj)u-boot.bd
        @rm -f $(obj)u-boot.spr
        @rm -f $(obj)nand_spl/{u-boot.{lds,lst},System.map}
        @rm -f $(obj)nand_spl/{u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map}
diff --git a/README b/README
index 0d37d56..3780564 100644 (file)
--- a/README
+++ b/README
@@ -201,7 +201,6 @@ Directory Hierarchy:
       /mpc5xx          Files specific to Freescale MPC5xx CPUs
       /mpc5xxx         Files specific to Freescale MPC5xxx CPUs
       /mpc8xx          Files specific to Freescale MPC8xx CPUs
-      /mpc8220         Files specific to Freescale MPC8220 CPUs
       /mpc824x         Files specific to Freescale MPC824x CPUs
       /mpc8260         Files specific to Freescale MPC8260 CPUs
       /mpc85xx         Files specific to Freescale MPC85xx CPUs
@@ -844,6 +843,7 @@ The following options need to be configured:
                CONFIG_CMD_FDOS         * Dos diskette Support
                CONFIG_CMD_FLASH          flinfo, erase, protect
                CONFIG_CMD_FPGA           FPGA device initialization support
+               CONFIG_CMD_FUSE           Device fuse support
                CONFIG_CMD_GETTIME      * Get time since boot
                CONFIG_CMD_GO           * the 'go' command (exec code)
                CONFIG_CMD_GREPENV      * search environment
@@ -898,6 +898,7 @@ The following options need to be configured:
                CONFIG_CMD_SF           * Read/write/erase SPI NOR flash
                CONFIG_CMD_SHA1SUM        print sha1 memory digest
                                          (requires CONFIG_CMD_MEMORY)
+               CONFIG_CMD_SOFTSWITCH   * Soft switch setting command for BF60x
                CONFIG_CMD_SOURCE         "source" command Support
                CONFIG_CMD_SPI          * SPI serial bus support
                CONFIG_CMD_TFTPSRV      * TFTP transfer in server mode
@@ -1208,7 +1209,23 @@ The following options need to be configured:
                        If this option is set, the driver enables cache flush.
 
 - TPM Support:
-               CONFIG_GENERIC_LPC_TPM
+               CONFIG_TPM
+               Support TPM devices.
+
+               CONFIG_TPM_TIS_I2C
+               Support for i2c bus TPM devices. Only one device
+               per system is supported at this time.
+
+                       CONFIG_TPM_TIS_I2C_BUS_NUMBER
+                       Define the the i2c bus number for the TPM device
+
+                       CONFIG_TPM_TIS_I2C_SLAVE_ADDRESS
+                       Define the TPM's address on the i2c bus
+
+                       CONFIG_TPM_TIS_I2C_BURST_LIMITATION
+                       Define the burst count bytes upper limit
+
+               CONFIG_TPM_TIS_LPC
                Support for generic parallel port TPM devices. Only one device
                per system is supported at this time.
 
@@ -2996,6 +3013,12 @@ FIT uImage format:
                use an arch-specific makefile fragment instead, for
                example if more than one image needs to be produced.
 
+               CONFIG_FIT_SPL_PRINT
+               Printing information about a FIT image adds quite a bit of
+               code to SPL. So this is normally disabled in SPL. Use this
+               option to re-enable it. This will affect the output of the
+               bootm command when booting a FIT image.
+
 Modem Support:
 --------------
 
@@ -3339,6 +3362,10 @@ Configuration Settings:
        offset _bss_start_ofs from CONFIG_SYS_TEXT_BASE, rather than
        directly. You should not need to touch this setting.
 
+- CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC (OMAP only)
+       This is set by OMAP boards for the max time that reset should
+       be asserted. See doc/README.omap-reset-time for details on how
+       the value can be calulated on a given board.
 
 The following definitions that deal with the placement and management
 of environment data (variable area); in general, we support the
@@ -5057,7 +5084,7 @@ On some platforms, it's possible to boot Linux zImage. This is done
 using the "bootz" command. The syntax of "bootz" command is the same
 as the syntax of "bootm" command.
 
-Note, defining the CONFIG_SUPPORT_INITRD_RAW allows user to supply
+Note, defining the CONFIG_SUPPORT_RAW_INITRD allows user to supply
 kernel with raw initrd images. The syntax is slightly different, the
 address of the initrd must be augmented by it's size, in the following
 format: "<initrd addres>:<initrd size>".
index a3d981f..ceb1271 100644 (file)
@@ -55,8 +55,6 @@ int platform_sys_info(struct sys_info *si)
 #define bi_bar bi_mbar_base
 #elif defined(CONFIG_MPC83xx)
 #define bi_bar bi_immrbar
-#elif defined(CONFIG_MPC8220)
-#define bi_bar bi_mbar_base
 #endif
 
 #if defined(bi_bar)
index 461899e..dc64160 100644 (file)
@@ -31,6 +31,9 @@ CONFIG_STANDALONE_LOAD_ADDR = 0xc100000
 endif
 endif
 
+LDFLAGS_FINAL += --gc-sections
+PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
+
 # Support generic board on ARM
 __HAVE_ARCH_GENERIC_BOARD := y
 
index f4ababb..23adac0 100644 (file)
@@ -29,7 +29,6 @@ LIB   = $(obj)lib$(SOC).o
 
 COBJS  += generic.o
 COBJS  += timer.o
-COBJS  += iomux.o
 COBJS  += mx35_sdram.o
 
 SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/arch/arm/cpu/arm1136/mx35/iomux.c b/arch/arm/cpu/arm1136/mx35/iomux.c
deleted file mode 100644 (file)
index a302575..0000000
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx35_pins.h>
-#include <asm/arch/iomux.h>
-
-/*
- * IOMUX register (base) addresses
- */
-enum iomux_reg_addr {
-       IOMUXGPR = IOMUXC_BASE_ADDR,                    /* General purpose */
-       IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR + 4,         /* MUX control */
-       IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + 0x324,     /* last MUX control */
-       IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + 0x328,     /* Pad control */
-       IOMUXSW_PAD_END = IOMUXC_BASE_ADDR + 0x794,     /* last Pad control */
-       IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + 0x7AC,   /* input select */
-       IOMUXSW_INPUT_END = IOMUXC_BASE_ADDR + 0x9F4,   /* last input select */
-};
-
-#define MUX_PIN_NUM_MAX                \
-               (((IOMUXSW_PAD_END - IOMUXSW_PAD_CTL) >> 2) + 1)
-#define MUX_INPUT_NUM_MUX      \
-               (((IOMUXSW_INPUT_END - IOMUXSW_INPUT_CTL) >> 2) + 1)
-
-/*
- * Request ownership for an IO pin. This function has to be the first one
- * being called before that pin is used.
- */
-void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
-       u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
-
-       if (mux_reg != NON_MUX_I) {
-               mux_reg += IOMUXGPR;
-               writel(cfg, mux_reg);
-       }
-}
-
-/*
- * Release ownership for an IO pin
- */
-void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
-}
-
-/*
- * This function configures the pad value for a IOMUX pin.
- *
- * @param  pin     a pin number as defined in iomux_pin_name_t
- * @param  config  the ORed value of elements defined in iomux_pad_config_t
- */
-void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config)
-{
-       u32 pad_reg = IOMUXGPR + PIN_TO_IOMUX_PAD(pin);
-
-       writel(config, pad_reg);
-}
-
-/*
- * This function enables/disables the general purpose function for a particular
- * signal.
- *
- * @param  gp   one signal as defined in iomux_gp_func_t
- * @param  en   enable/disable
- */
-void mxc_iomux_set_gpr(iomux_gp_func_t gp, int en)
-{
-       u32 l;
-
-       l = readl(IOMUXGPR);
-       if (en)
-               l |= gp;
-       else
-               l &= ~gp;
-
-       writel(l, IOMUXGPR);
-}
-
-/*
- * This function configures input path.
- *
- * @param input index of input select register as defined in
- *                     iomux_input_select_t
- * @param config the binary value of elements defined in
- *                     iomux_input_config_t
- */
-void mxc_iomux_set_input(iomux_input_select_t input, u32 config)
-{
-       u32 reg = IOMUXSW_INPUT_CTL + (input << 2);
-
-       writel(config, reg);
-}
index ccea2d5..edf249d 100644 (file)
@@ -104,10 +104,6 @@ _TEXT_BASE:
 _bss_start_ofs:
        .word __bss_start - _start
 
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
-       .word __image_copy_end - _start
-
 .globl _bss_end_ofs
 _bss_end_ofs:
        .word __bss_end - _start
@@ -173,83 +169,6 @@ next:
 
 /*------------------------------------------------------------------------------*/
 
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
-       .globl  relocate_code
-relocate_code:
-       mov     r6, r0  /* save addr of destination */
-
-       adr     r0, _start
-       subs    r9, r6, r0              /* r9 <- relocation offset */
-       beq     relocate_done           /* skip relocation */
-       mov     r1, r6                  /* r1 <- scratch for copy_loop */
-       ldr     r3, _image_copy_end_ofs
-       add     r2, r0, r3              /* r2 <- source end address         */
-
-copy_loop:
-       ldmia   r0!, {r10-r11}          /* copy from source address [r0]    */
-       stmia   r1!, {r10-r11}          /* copy to   target address [r1]    */
-       cmp     r0, r2                  /* until source end address [r2]    */
-       blo     copy_loop
-
-#ifndef CONFIG_SPL_BUILD
-       /*
-        * fix .rel.dyn relocations
-        */
-       ldr     r0, _TEXT_BASE          /* r0 <- Text base */
-       ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
-       add     r10, r10, r0            /* r10 <- sym table in FLASH */
-       ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
-       add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
-       ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
-       add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
-fixloop:
-       ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
-       add     r0, r0, r9              /* r0 <- location to fix up in RAM */
-       ldr     r1, [r2, #4]
-       and     r7, r1, #0xff
-       cmp     r7, #23                 /* relative fixup? */
-       beq     fixrel
-       cmp     r7, #2                  /* absolute fixup? */
-       beq     fixabs
-       /* ignore unknown type of fixup */
-       b       fixnext
-fixabs:
-       /* absolute fix: set location to (offset) symbol value */
-       mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
-       add     r1, r10, r1             /* r1 <- address of symbol in table */
-       ldr     r1, [r1, #4]            /* r1 <- symbol value */
-       add     r1, r1, r9              /* r1 <- relocated sym addr */
-       b       fixnext
-fixrel:
-       /* relative fix: increase location by offset */
-       ldr     r1, [r0]
-       add     r1, r1, r9
-fixnext:
-       str     r1, [r0]
-       add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
-       cmp     r2, r3
-       blo     fixloop
-#endif
-
-relocate_done:
-
-       bx      lr
-
-#ifndef CONFIG_SPL_BUILD
-
-_rel_dyn_start_ofs:
-       .word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-       .word __rel_dyn_end - _start
-_dynsym_start_ofs:
-       .word __dynsym_start - _start
-
-#endif
-
        .globl  c_runtime_cpu_setup
 c_runtime_cpu_setup:
 
index f20da8e..65292bc 100644 (file)
@@ -112,10 +112,6 @@ _TEXT_BASE:
 _bss_start_ofs:
        .word __bss_start - _start
 
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
-       .word __image_copy_end - _start
-
 .globl _bss_end_ofs
 _bss_end_ofs:
        .word __bss_end - _start
@@ -225,79 +221,6 @@ skip_tcmdisable:
 
 /*------------------------------------------------------------------------------*/
 
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
-       .globl  relocate_code
-relocate_code:
-       mov     r6, r0  /* save addr of destination */
-
-       adr     r0, _start
-       subs    r9, r6, r0              /* r9 <- relocation offset */
-       beq     relocate_done           /* skip relocation */
-       mov     r1, r6                  /* r1 <- scratch for copy_loop */
-       ldr     r3, _image_copy_end_ofs
-       add     r2, r0, r3              /* r2 <- source end address         */
-
-copy_loop:
-       ldmia   r0!, {r10-r11}          /* copy from source address [r0]    */
-       stmia   r1!, {r10-r11}          /* copy to   target address [r1]    */
-       cmp     r0, r2                  /* until source end address [r2]    */
-       blo     copy_loop
-
-#ifndef CONFIG_SPL_BUILD
-       /*
-        * fix .rel.dyn relocations
-        */
-       ldr     r0, _TEXT_BASE          /* r0 <- Text base */
-       ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
-       add     r10, r10, r0            /* r10 <- sym table in FLASH */
-       ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
-       add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
-       ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
-       add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
-fixloop:
-       ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
-       add     r0, r0, r9              /* r0 <- location to fix up in RAM */
-       ldr     r1, [r2, #4]
-       and     r7, r1, #0xff
-       cmp     r7, #23                 /* relative fixup? */
-       beq     fixrel
-       cmp     r7, #2                  /* absolute fixup? */
-       beq     fixabs
-       /* ignore unknown type of fixup */
-       b       fixnext
-fixabs:
-       /* absolute fix: set location to (offset) symbol value */
-       mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
-       add     r1, r10, r1             /* r1 <- address of symbol in table */
-       ldr     r1, [r1, #4]            /* r1 <- symbol value */
-       add     r1, r1, r9              /* r1 <- relocated sym addr */
-       b       fixnext
-fixrel:
-       /* relative fix: increase location by offset */
-       ldr     r1, [r0]
-       add     r1, r1, r9
-fixnext:
-       str     r1, [r0]
-       add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
-       cmp     r2, r3
-       blo     fixloop
-#endif
-
-relocate_done:
-
-       bx      lr
-
-_rel_dyn_start_ofs:
-       .word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-       .word __rel_dyn_end - _start
-_dynsym_start_ofs:
-       .word __dynsym_start - _start
-
        .globl  c_runtime_cpu_setup
 c_runtime_cpu_setup:
 
index 9facc7e..a396ebc 100644 (file)
@@ -101,10 +101,6 @@ _TEXT_BASE:
 _bss_start_ofs:
        .word __bss_start - _start
 
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
-       .word __image_copy_end - _start
-
 .globl _bss_end_ofs
 _bss_end_ofs:
        .word __bss_end - _start
@@ -155,79 +151,6 @@ reset:
 
 /*------------------------------------------------------------------------------*/
 
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
-       .globl  relocate_code
-relocate_code:
-       mov     r6, r0  /* save addr of destination */
-
-       adr     r0, _start
-       subs    r9, r6, r0              /* r9 <- relocation offset */
-       beq     relocate_done           /* skip relocation */
-       mov     r1, r6                  /* r1 <- scratch for copy_loop */
-       ldr     r3, _image_copy_end_ofs
-       add     r2, r0, r3              /* r2 <- source end address         */
-
-copy_loop:
-       ldmia   r0!, {r10-r11}          /* copy from source address [r0]    */
-       stmia   r1!, {r10-r11}          /* copy to   target address [r1]    */
-       cmp     r0, r2                  /* until source end address [r2]    */
-       blo     copy_loop
-
-#ifndef CONFIG_SPL_BUILD
-       /*
-        * fix .rel.dyn relocations
-        */
-       ldr     r0, _TEXT_BASE          /* r0 <- Text base */
-       ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
-       add     r10, r10, r0            /* r10 <- sym table in FLASH */
-       ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
-       add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
-       ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
-       add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
-fixloop:
-       ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
-       add     r0, r0, r9              /* r0 <- location to fix up in RAM */
-       ldr     r1, [r2, #4]
-       and     r7, r1, #0xff
-       cmp     r7, #23                 /* relative fixup? */
-       beq     fixrel
-       cmp     r7, #2                  /* absolute fixup? */
-       beq     fixabs
-       /* ignore unknown type of fixup */
-       b       fixnext
-fixabs:
-       /* absolute fix: set location to (offset) symbol value */
-       mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
-       add     r1, r10, r1             /* r1 <- address of symbol in table */
-       ldr     r1, [r1, #4]            /* r1 <- symbol value */
-       add     r1, r1, r9              /* r1 <- relocated sym addr */
-       b       fixnext
-fixrel:
-       /* relative fix: increase location by offset */
-       ldr     r1, [r0]
-       add     r1, r1, r9
-fixnext:
-       str     r1, [r0]
-       add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
-       cmp     r2, r3
-       blo     fixloop
-#endif
-
-relocate_done:
-
-       mov     pc, lr
-
-_rel_dyn_start_ofs:
-       .word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-       .word __rel_dyn_end - _start
-_dynsym_start_ofs:
-       .word __dynsym_start - _start
-
        .globl  c_runtime_cpu_setup
 c_runtime_cpu_setup:
 
@@ -244,9 +167,9 @@ c_runtime_cpu_setup:
  *************************************************************************
  */
 
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 cpu_init_crit:
 
-#if !defined(CONFIG_TEGRA)
        mov     ip, lr
        /*
         * before relocating, we have to setup RAM timing
@@ -255,9 +178,9 @@ cpu_init_crit:
         */
        bl      lowlevel_init
        mov     lr, ip
-#endif
 
        mov     pc, lr
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
 
 
 #ifndef CONFIG_SPL_BUILD
index 6250025..3232065 100644 (file)
@@ -89,10 +89,6 @@ _TEXT_BASE:
 _bss_start_ofs:
        .word __bss_start - _start
 
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
-       .word __image_copy_end - _start
-
 .globl _bss_end_ofs
 _bss_end_ofs:
        .word __bss_end - _start
@@ -194,79 +190,6 @@ copyex:
 
 /*------------------------------------------------------------------------------*/
 
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
-       .globl  relocate_code
-relocate_code:
-       mov     r6, r0  /* save addr of destination */
-
-       adr     r0, _start
-       subs    r9, r6, r0              /* r9 <- relocation offset */
-       beq     relocate_done           /* skip relocation */
-       mov     r1, r6                  /* r1 <- scratch for copy_loop */
-       ldr     r3, _image_copy_end_ofs
-       add     r2, r0, r3              /* r2 <- source end address         */
-
-copy_loop:
-       ldmia   r0!, {r10-r11}          /* copy from source address [r0]    */
-       stmia   r1!, {r10-r11}          /* copy to   target address [r1]    */
-       cmp     r0, r2                  /* until source end address [r2]    */
-       blo     copy_loop
-
-#ifndef CONFIG_SPL_BUILD
-       /*
-        * fix .rel.dyn relocations
-        */
-       ldr     r0, _TEXT_BASE          /* r0 <- Text base */
-       ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
-       add     r10, r10, r0            /* r10 <- sym table in FLASH */
-       ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
-       add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
-       ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
-       add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
-fixloop:
-       ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
-       add     r0, r0, r9              /* r0 <- location to fix up in RAM */
-       ldr     r1, [r2, #4]
-       and     r7, r1, #0xff
-       cmp     r7, #23                 /* relative fixup? */
-       beq     fixrel
-       cmp     r7, #2                  /* absolute fixup? */
-       beq     fixabs
-       /* ignore unknown type of fixup */
-       b       fixnext
-fixabs:
-       /* absolute fix: set location to (offset) symbol value */
-       mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
-       add     r1, r10, r1             /* r1 <- address of symbol in table */
-       ldr     r1, [r1, #4]            /* r1 <- symbol value */
-       add     r1, r1, r9              /* r1 <- relocated sym addr */
-       b       fixnext
-fixrel:
-       /* relative fix: increase location by offset */
-       ldr     r1, [r0]
-       add     r1, r1, r9
-fixnext:
-       str     r1, [r0]
-       add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
-       cmp     r2, r3
-       blo     fixloop
-#endif
-
-relocate_done:
-
-       mov     pc, lr
-
-_rel_dyn_start_ofs:
-       .word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-       .word __rel_dyn_end - _start
-_dynsym_start_ofs:
-       .word __dynsym_start - _start
-
        .globl  c_runtime_cpu_setup
 c_runtime_cpu_setup:
 
index 021e241..97eb276 100644 (file)
@@ -95,10 +95,6 @@ _TEXT_BASE:
 _bss_start_ofs:
        .word __bss_start - _start
 
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
-       .word __image_copy_end - _start
-
 .globl _bss_end_ofs
 _bss_end_ofs:
        .word __bss_end - _start
@@ -184,79 +180,6 @@ poll1:
 
 /*------------------------------------------------------------------------------*/
 
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
-       .globl  relocate_code
-relocate_code:
-       mov     r6, r0  /* save addr of destination */
-
-       adr     r0, _start
-       subs    r9, r6, r0              /* r9 <- relocation offset */
-       beq     relocate_done           /* skip relocation */
-       mov     r1, r6                  /* r1 <- scratch for copy_loop */
-       ldr     r3, _image_copy_end_ofs
-       add     r2, r0, r3              /* r2 <- source end address         */
-
-copy_loop:
-       ldmia   r0!, {r10-r11}          /* copy from source address [r0]    */
-       stmia   r1!, {r10-r11}          /* copy to   target address [r1]    */
-       cmp     r0, r2                  /* until source end address [r2]    */
-       blo     copy_loop
-
-#ifndef CONFIG_SPL_BUILD
-       /*
-        * fix .rel.dyn relocations
-        */
-       ldr     r0, _TEXT_BASE          /* r0 <- Text base */
-       ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
-       add     r10, r10, r0            /* r10 <- sym table in FLASH */
-       ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
-       add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
-       ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
-       add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
-fixloop:
-       ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
-       add     r0, r0, r9              /* r0 <- location to fix up in RAM */
-       ldr     r1, [r2, #4]
-       and     r7, r1, #0xff
-       cmp     r7, #23                 /* relative fixup? */
-       beq     fixrel
-       cmp     r7, #2                  /* absolute fixup? */
-       beq     fixabs
-       /* ignore unknown type of fixup */
-       b       fixnext
-fixabs:
-       /* absolute fix: set location to (offset) symbol value */
-       mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
-       add     r1, r10, r1             /* r1 <- address of symbol in table */
-       ldr     r1, [r1, #4]            /* r1 <- symbol value */
-       add     r1, r1, r9              /* r1 <- relocated sym addr */
-       b       fixnext
-fixrel:
-       /* relative fix: increase location by offset */
-       ldr     r1, [r0]
-       add     r1, r1, r9
-fixnext:
-       str     r1, [r0]
-       add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
-       cmp     r2, r3
-       blo     fixloop
-#endif
-
-relocate_done:
-
-       mov     pc, lr
-
-_rel_dyn_start_ofs:
-       .word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-       .word __rel_dyn_end - _start
-_dynsym_start_ofs:
-       .word __dynsym_start - _start
-
        .globl  c_runtime_cpu_setup
 c_runtime_cpu_setup:
 
index 346e58f..c4408f6 100644 (file)
@@ -35,6 +35,7 @@ COBJS-$(CONFIG_AT91SAM9263)   += at91sam9263_devices.o
 COBJS-$(CONFIG_AT91SAM9RL)     += at91sam9rl_devices.o
 COBJS-$(CONFIG_AT91SAM9M10G45) += at91sam9m10g45_devices.o
 COBJS-$(CONFIG_AT91SAM9G45)    += at91sam9m10g45_devices.o
+COBJS-$(CONFIG_AT91SAM9N12)    += at91sam9n12_devices.o
 COBJS-$(CONFIG_AT91SAM9X5)     += at91sam9x5_devices.o
 COBJS-$(CONFIG_AT91_EFLASH)    += eflash.o
 COBJS-$(CONFIG_AT91_LED)       += led.o
index 19ec615..5e995e1 100644 (file)
@@ -203,6 +203,10 @@ void at91_macb_hw_init(void)
 #if defined(CONFIG_GENERIC_ATMEL_MCI)
 void at91_mci_hw_init(void)
 {
+       /* Enable mci clock */
+       struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+       writel(1 << ATMEL_ID_MCI, &pmc->pcer);
+
        at91_set_a_periph(AT91_PIO_PORTA, 8, 1);        /* MCCK */
 #if defined(CONFIG_ATMEL_MCI_PORTB)
        at91_set_b_periph(AT91_PIO_PORTA, 1, 1);        /* MCCDB */
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9n12_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9n12_devices.c
new file mode 100644 (file)
index 0000000..6eaeac0
--- /dev/null
@@ -0,0 +1,177 @@
+/*
+ * (C) Copyright 2013 Atmel Corporation
+ * Josh Wu <josh.wu@atmel.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_pio.h>
+
+unsigned int has_lcdc()
+{
+       return 1;
+}
+
+void at91_serial0_hw_init(void)
+{
+       struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+       at91_set_a_periph(AT91_PIO_PORTA, 0, 1);                /* TXD0 */
+       at91_set_a_periph(AT91_PIO_PORTA, 1, 0);                /* RXD0 */
+       writel(1 << ATMEL_ID_USART0, &pmc->pcer);
+}
+
+void at91_serial1_hw_init(void)
+{
+       struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+       at91_set_a_periph(AT91_PIO_PORTA, 5, 1);                /* TXD1 */
+       at91_set_a_periph(AT91_PIO_PORTA, 6, 0);                /* RXD1 */
+       writel(1 << ATMEL_ID_USART1, &pmc->pcer);
+}
+
+void at91_serial2_hw_init(void)
+{
+       struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+       at91_set_a_periph(AT91_PIO_PORTA, 7, 1);                /* TXD2 */
+       at91_set_a_periph(AT91_PIO_PORTA, 8, 0);                /* RXD2 */
+       writel(1 << ATMEL_ID_USART2, &pmc->pcer);
+}
+
+void at91_serial3_hw_init(void)
+{
+       struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+       at91_set_b_periph(AT91_PIO_PORTC, 22, 1);               /* TXD3 */
+       at91_set_b_periph(AT91_PIO_PORTC, 23, 0);               /* RXD3 */
+       writel(1 << ATMEL_ID_USART3, &pmc->pcer);
+}
+
+void at91_seriald_hw_init(void)
+{
+       struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+       at91_set_a_periph(AT91_PIO_PORTA, 10, 1);               /* DTXD */
+       at91_set_a_periph(AT91_PIO_PORTA, 9, 0);                /* DRXD */
+       writel(1 << ATMEL_ID_SYS, &pmc->pcer);
+}
+
+#ifdef CONFIG_ATMEL_SPI
+void at91_spi0_hw_init(unsigned long cs_mask)
+{
+       struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+       at91_set_a_periph(AT91_PIO_PORTA, 11, 0);       /* SPI0_MISO */
+       at91_set_a_periph(AT91_PIO_PORTA, 12, 0);       /* SPI0_MOSI */
+       at91_set_a_periph(AT91_PIO_PORTA, 13, 0);       /* SPI0_SPCK */
+
+       /* Enable clock */
+       writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
+
+       if (cs_mask & (1 << 0))
+               at91_set_pio_output(AT91_PIO_PORTA, 14, 1);
+       if (cs_mask & (1 << 1))
+               at91_set_pio_output(AT91_PIO_PORTA, 7, 1);
+       if (cs_mask & (1 << 2))
+               at91_set_pio_output(AT91_PIO_PORTA, 1, 1);
+       if (cs_mask & (1 << 3))
+               at91_set_pio_output(AT91_PIO_PORTB, 3, 1);
+}
+
+void at91_spi1_hw_init(unsigned long cs_mask)
+{
+       struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+       at91_set_b_periph(AT91_PIO_PORTA, 21, 0);       /* SPI1_MISO */
+       at91_set_b_periph(AT91_PIO_PORTA, 22, 0);       /* SPI1_MOSI */
+       at91_set_b_periph(AT91_PIO_PORTA, 23, 0);       /* SPI1_SPCK */
+
+       /* Enable clock */
+       writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
+
+       if (cs_mask & (1 << 0))
+               at91_set_pio_output(AT91_PIO_PORTA, 8, 1);
+       if (cs_mask & (1 << 1))
+               at91_set_pio_output(AT91_PIO_PORTA, 0, 1);
+       if (cs_mask & (1 << 2))
+               at91_set_pio_output(AT91_PIO_PORTA, 31, 1);
+       if (cs_mask & (1 << 3))
+               at91_set_pio_output(AT91_PIO_PORTA, 30, 1);
+}
+#endif
+
+void at91_mci_hw_init(void)
+{
+       struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+       at91_set_a_periph(AT91_PIO_PORTA, 17, 0);       /* MCCK */
+       at91_set_a_periph(AT91_PIO_PORTA, 16, 0);       /* MCCDA */
+       at91_set_a_periph(AT91_PIO_PORTA, 15, 0);       /* MCDA0 */
+       at91_set_a_periph(AT91_PIO_PORTA, 18, 0);       /* MCDA1 */
+       at91_set_a_periph(AT91_PIO_PORTA, 19, 0);       /* MCDA2 */
+       at91_set_a_periph(AT91_PIO_PORTA, 20, 0);       /* MCDA3 */
+
+       writel(1 << ATMEL_ID_HSMCI0, &pmc->pcer);
+}
+
+#ifdef CONFIG_LCD
+void at91_lcd_hw_init(void)
+{
+       struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+       at91_set_a_periph(AT91_PIO_PORTC, 24, 0);       /* LCDDPWR */
+       at91_set_a_periph(AT91_PIO_PORTC, 26, 0);       /* LCDVSYNC */
+       at91_set_a_periph(AT91_PIO_PORTC, 27, 0);       /* LCDHSYNC */
+       at91_set_a_periph(AT91_PIO_PORTC, 28, 0);       /* LCDDOTCK */
+       at91_set_a_periph(AT91_PIO_PORTC, 29, 0);       /* LCDDEN */
+       at91_set_a_periph(AT91_PIO_PORTC, 30, 0);       /* LCDDOTCK */
+
+       at91_set_a_periph(AT91_PIO_PORTC, 0, 0);        /* LCDD0 */
+       at91_set_a_periph(AT91_PIO_PORTC, 1, 0);        /* LCDD1 */
+       at91_set_a_periph(AT91_PIO_PORTC, 2, 0);        /* LCDD2 */
+       at91_set_a_periph(AT91_PIO_PORTC, 3, 0);        /* LCDD3 */
+       at91_set_a_periph(AT91_PIO_PORTC, 4, 0);        /* LCDD4 */
+       at91_set_a_periph(AT91_PIO_PORTC, 5, 0);        /* LCDD5 */
+       at91_set_a_periph(AT91_PIO_PORTC, 6, 0);        /* LCDD6 */
+       at91_set_a_periph(AT91_PIO_PORTC, 7, 0);        /* LCDD7 */
+       at91_set_a_periph(AT91_PIO_PORTC, 8, 0);        /* LCDD8 */
+       at91_set_a_periph(AT91_PIO_PORTC, 9, 0);        /* LCDD9 */
+       at91_set_a_periph(AT91_PIO_PORTC, 10, 0);       /* LCDD10 */
+       at91_set_a_periph(AT91_PIO_PORTC, 11, 0);       /* LCDD11 */
+       at91_set_a_periph(AT91_PIO_PORTC, 12, 0);       /* LCDD12 */
+       at91_set_a_periph(AT91_PIO_PORTC, 13, 0);       /* LCDD13 */
+       at91_set_a_periph(AT91_PIO_PORTC, 14, 0);       /* LCDD14 */
+       at91_set_a_periph(AT91_PIO_PORTC, 15, 0);       /* LCDD15 */
+       at91_set_a_periph(AT91_PIO_PORTC, 16, 0);       /* LCDD16 */
+       at91_set_a_periph(AT91_PIO_PORTC, 17, 0);       /* LCDD17 */
+       at91_set_a_periph(AT91_PIO_PORTC, 18, 0);       /* LCDD18 */
+       at91_set_a_periph(AT91_PIO_PORTC, 19, 0);       /* LCDD19 */
+       at91_set_a_periph(AT91_PIO_PORTC, 20, 0);       /* LCDD20 */
+       at91_set_a_periph(AT91_PIO_PORTC, 21, 0);       /* LCDD21 */
+       at91_set_a_periph(AT91_PIO_PORTC, 22, 0);       /* LCDD22 */
+       at91_set_a_periph(AT91_PIO_PORTC, 23, 0);       /* LCDD23 */
+
+       writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
+}
+#endif
index f825388..5b4923f 100644 (file)
@@ -156,7 +156,7 @@ int at91_clock_init(unsigned long main_clock)
         */
        mckr = readl(&pmc->mckr);
 #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
-               || defined(CONFIG_AT91SAM9X5)
+               || defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
        /* plla divisor by 2 */
        gd->arch.plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
 #endif
@@ -171,7 +171,7 @@ int at91_clock_init(unsigned long main_clock)
        if (mckr & AT91_PMC_MCKR_MDIV_MASK)
                freq /= 2;                      /* processor clock division */
 #elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
-               || defined(CONFIG_AT91SAM9X5)
+               || defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
        /* mdiv <==> divisor
         *  0   <==>   1
         *  1   <==>   2
index ff2e2e3..127beb8 100644 (file)
 #include <asm/arch/emif_defs.h>
 #include <asm/arch/pll_defs.h>
 
+void davinci_enable_uart0(void)
+{
+       lpsc_on(DAVINCI_LPSC_UART0);
+
+       /* Bringup UART0 out of reset */
+       REG(UART0_PWREMU_MGMT) = 0x00006001;
+}
+
 #if defined(CONFIG_SYS_DA850_PLL_INIT)
 void da850_waitloop(unsigned long loopcnt)
 {
index 679273b..7cbbe65 100644 (file)
@@ -27,7 +27,6 @@
 #include <netdev.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/imx25-pinmux.h>
 #include <asm/arch/clock.h>
 
 #ifdef CONFIG_FSL_ESDHC
@@ -248,123 +247,7 @@ int cpu_mmc_init(bd_t *bis)
 }
 #endif
 
-#ifdef CONFIG_MXC_UART
-void mx25_uart1_init_pins(void)
-{
-       struct iomuxc_mux_ctl *muxctl;
-       struct iomuxc_pad_ctl *padctl;
-       u32 inpadctl;
-       u32 outpadctl;
-       u32 muxmode0;
-
-       muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
-       padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
-       muxmode0 = MX25_PIN_MUX_MODE(0);
-       /*
-        * set up input pins with hysteresis and 100K pull-ups
-        */
-       inpadctl = MX25_PIN_PAD_CTL_HYS
-           | MX25_PIN_PAD_CTL_PKE
-           | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PU;
-
-       /*
-        * set up output pins with 100K pull-downs
-        * FIXME: need to revisit this
-        *      PUE is ignored if PKE is not set
-        *      so the right value here is likely
-        *        0x0 for no pull up/down
-        *      or
-        *        0xc0 for 100k pull down
-        */
-       outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
-
-       /* UART1 */
-       /* rxd */
-       writel(muxmode0, &muxctl->pad_uart1_rxd);
-       writel(inpadctl, &padctl->pad_uart1_rxd);
-
-       /* txd */
-       writel(muxmode0, &muxctl->pad_uart1_txd);
-       writel(outpadctl, &padctl->pad_uart1_txd);
-
-       /* rts */
-       writel(muxmode0, &muxctl->pad_uart1_rts);
-       writel(outpadctl, &padctl->pad_uart1_rts);
-
-       /* cts */
-       writel(muxmode0, &muxctl->pad_uart1_cts);
-       writel(inpadctl, &padctl->pad_uart1_cts);
-}
-#endif /* CONFIG_MXC_UART */
-
 #ifdef CONFIG_FEC_MXC
-void mx25_fec_init_pins(void)
-{
-       struct iomuxc_mux_ctl *muxctl;
-       struct iomuxc_pad_ctl *padctl;
-       u32 inpadctl_100kpd;
-       u32 inpadctl_22kpu;
-       u32 outpadctl;
-       u32 muxmode0;
-
-       muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
-       padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
-       muxmode0 = MX25_PIN_MUX_MODE(0);
-       inpadctl_100kpd = MX25_PIN_PAD_CTL_HYS
-           | MX25_PIN_PAD_CTL_PKE
-           | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
-       inpadctl_22kpu = MX25_PIN_PAD_CTL_HYS
-           | MX25_PIN_PAD_CTL_PKE
-           | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_22K_PU;
-       /*
-        * set up output pins with 100K pull-downs
-        * FIXME: need to revisit this
-        *      PUE is ignored if PKE is not set
-        *      so the right value here is likely
-        *        0x0 for no pull
-        *      or
-        *        0xc0 for 100k pull down
-        */
-       outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
-
-       /* FEC_TX_CLK */
-       writel(muxmode0, &muxctl->pad_fec_tx_clk);
-       writel(inpadctl_100kpd, &padctl->pad_fec_tx_clk);
-
-       /* FEC_RX_DV */
-       writel(muxmode0, &muxctl->pad_fec_rx_dv);
-       writel(inpadctl_100kpd, &padctl->pad_fec_rx_dv);
-
-       /* FEC_RDATA0 */
-       writel(muxmode0, &muxctl->pad_fec_rdata0);
-       writel(inpadctl_100kpd, &padctl->pad_fec_rdata0);
-
-       /* FEC_TDATA0 */
-       writel(muxmode0, &muxctl->pad_fec_tdata0);
-       writel(outpadctl, &padctl->pad_fec_tdata0);
-
-       /* FEC_TX_EN */
-       writel(muxmode0, &muxctl->pad_fec_tx_en);
-       writel(outpadctl, &padctl->pad_fec_tx_en);
-
-       /* FEC_MDC */
-       writel(muxmode0, &muxctl->pad_fec_mdc);
-       writel(outpadctl, &padctl->pad_fec_mdc);
-
-       /* FEC_MDIO */
-       writel(muxmode0, &muxctl->pad_fec_mdio);
-       writel(inpadctl_22kpu, &padctl->pad_fec_mdio);
-
-       /* FEC_RDATA1 */
-       writel(muxmode0, &muxctl->pad_fec_rdata1);
-       writel(inpadctl_100kpd, &padctl->pad_fec_rdata1);
-
-       /* FEC_TDATA1 */
-       writel(muxmode0, &muxctl->pad_fec_tdata1);
-       writel(outpadctl, &padctl->pad_fec_tdata1);
-
-}
-
 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 {
        int i;
index eeecf89..038c1c1 100644 (file)
@@ -40,6 +40,16 @@ all: $(obj).depend $(LIB)
 $(LIB):        $(OBJS)
        $(call cmd_link_o_target, $(OBJS))
 
+# Specify the target for use in elftosb call
+ELFTOSB_TARGET-$(CONFIG_MX23) = imx23
+ELFTOSB_TARGET-$(CONFIG_MX28) = imx28
+
+$(OBJTREE)/u-boot.bd: $(SRCTREE)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd
+       sed "s@OBJTREE@$(OBJTREE)@g" $^ > $@
+
+$(OBJTREE)/u-boot.sb: $(OBJTREE)/u-boot.bin $(OBJTREE)/spl/u-boot-spl.bin $(OBJTREE)/u-boot.bd
+               elftosb -zf $(ELFTOSB_TARGET-y) -c $(OBJTREE)/u-boot.bd -o $(OBJTREE)/u-boot.sb
+
 #########################################################################
 
 # defines $(obj).depend target
index 43e7663..f94107f 100644 (file)
@@ -325,6 +325,99 @@ void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq)
                bus, tgtclk, freq);
 }
 
+void mxs_set_lcdclk(uint32_t freq)
+{
+       struct mxs_clkctrl_regs *clkctrl_regs =
+               (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       uint32_t fp, x, k_rest, k_best, x_best, tk;
+       int32_t k_best_l = 999, k_best_t = 0, x_best_l = 0xff, x_best_t = 0xff;
+
+       if (freq == 0)
+               return;
+
+#if defined(CONFIG_MX23)
+       writel(CLKCTRL_CLKSEQ_BYPASS_PIX, &clkctrl_regs->hw_clkctrl_clkseq_clr);
+#elif defined(CONFIG_MX28)
+       writel(CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF, &clkctrl_regs->hw_clkctrl_clkseq_clr);
+#endif
+
+       /*
+        *             /               18 \     1       1
+        * freq kHz = | 480000000 Hz * --  | * --- * ------
+        *             \                x /     k     1000
+        *
+        *      480000000 Hz   18
+        *      ------------ * --
+        *        freq kHz      x
+        * k = -------------------
+        *             1000
+        */
+
+       fp = ((PLL_FREQ_KHZ * 1000) / freq) * 18;
+
+       for (x = 18; x <= 35; x++) {
+               tk = fp / x;
+               if ((tk / 1000 == 0) || (tk / 1000 > 255))
+                       continue;
+
+               k_rest = tk % 1000;
+
+               if (k_rest < (k_best_l % 1000)) {
+                       k_best_l = tk;
+                       x_best_l = x;
+               }
+
+               if (k_rest > (k_best_t % 1000)) {
+                       k_best_t = tk;
+                       x_best_t = x;
+               }
+       }
+
+       if (1000 - (k_best_t % 1000) > (k_best_l % 1000)) {
+               k_best = k_best_l;
+               x_best = x_best_l;
+       } else {
+               k_best = k_best_t;
+               x_best = x_best_t;
+       }
+
+       k_best /= 1000;
+
+#if defined(CONFIG_MX23)
+       writeb(CLKCTRL_FRAC_CLKGATE,
+               &clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_PIX]);
+       writeb(CLKCTRL_FRAC_CLKGATE | (x_best & CLKCTRL_FRAC_FRAC_MASK),
+               &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_PIX]);
+       writeb(CLKCTRL_FRAC_CLKGATE,
+               &clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_PIX]);
+
+       writel(CLKCTRL_PIX_CLKGATE,
+               &clkctrl_regs->hw_clkctrl_pix_set);
+       clrsetbits_le32(&clkctrl_regs->hw_clkctrl_pix,
+                       CLKCTRL_PIX_DIV_MASK | CLKCTRL_PIX_CLKGATE,
+                       k_best << CLKCTRL_PIX_DIV_OFFSET);
+
+       while (readl(&clkctrl_regs->hw_clkctrl_pix) & CLKCTRL_PIX_BUSY)
+               ;
+#elif defined(CONFIG_MX28)
+       writeb(CLKCTRL_FRAC_CLKGATE,
+               &clkctrl_regs->hw_clkctrl_frac1_set[CLKCTRL_FRAC1_PIX]);
+       writeb(CLKCTRL_FRAC_CLKGATE | (x_best & CLKCTRL_FRAC_FRAC_MASK),
+               &clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_PIX]);
+       writeb(CLKCTRL_FRAC_CLKGATE,
+               &clkctrl_regs->hw_clkctrl_frac1_clr[CLKCTRL_FRAC1_PIX]);
+
+       writel(CLKCTRL_DIS_LCDIF_CLKGATE,
+               &clkctrl_regs->hw_clkctrl_lcdif_set);
+       clrsetbits_le32(&clkctrl_regs->hw_clkctrl_lcdif,
+                       CLKCTRL_DIS_LCDIF_DIV_MASK | CLKCTRL_DIS_LCDIF_CLKGATE,
+                       k_best << CLKCTRL_DIS_LCDIF_DIV_OFFSET);
+
+       while (readl(&clkctrl_regs->hw_clkctrl_lcdif) & CLKCTRL_DIS_LCDIF_BUSY)
+               ;
+#endif
+}
+
 uint32_t mxc_get_clock(enum mxc_clock clk)
 {
        switch (clk) {
index e2b4196..a5e388b 100644 (file)
@@ -30,7 +30,7 @@
 #include <asm/errno.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
-#include <asm/arch/dma.h>
+#include <asm/imx-common/dma.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/imx-regs.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/* 1 second delay should be plenty of time for block reset. */
-#define        RESET_MAX_TIMEOUT       1000000
-
-#define        MXS_BLOCK_SFTRST        (1 << 31)
-#define        MXS_BLOCK_CLKGATE       (1 << 30)
-
 /* Lowlevel init isn't used on i.MX28, so just have a dummy here */
 inline void lowlevel_init(void) {}
 
@@ -82,63 +76,6 @@ void enable_caches(void)
 #endif
 }
 
-int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned
-                                                               int timeout)
-{
-       while (--timeout) {
-               if ((readl(&reg->reg) & mask) == mask)
-                       break;
-               udelay(1);
-       }
-
-       return !timeout;
-}
-
-int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned
-                                                               int timeout)
-{
-       while (--timeout) {
-               if ((readl(&reg->reg) & mask) == 0)
-                       break;
-               udelay(1);
-       }
-
-       return !timeout;
-}
-
-int mxs_reset_block(struct mxs_register_32 *reg)
-{
-       /* Clear SFTRST */
-       writel(MXS_BLOCK_SFTRST, &reg->reg_clr);
-
-       if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
-               return 1;
-
-       /* Clear CLKGATE */
-       writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);
-
-       /* Set SFTRST */
-       writel(MXS_BLOCK_SFTRST, &reg->reg_set);
-
-       /* Wait for CLKGATE being set */
-       if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
-               return 1;
-
-       /* Clear SFTRST */
-       writel(MXS_BLOCK_SFTRST, &reg->reg_clr);
-
-       if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
-               return 1;
-
-       /* Clear CLKGATE */
-       writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);
-
-       if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
-               return 1;
-
-       return 0;
-}
-
 void mx28_fixup_vt(uint32_t start_addr)
 {
        uint32_t *vt = (uint32_t *)0x20;
index bc2d69c..07db279 100644 (file)
@@ -110,6 +110,7 @@ __weak void mxs_adjust_memory_params(uint32_t *dram_vals)
 {
 }
 
+#ifdef CONFIG_MX28
 static void initialize_dram_values(void)
 {
        int i;
@@ -118,15 +119,36 @@ static void initialize_dram_values(void)
 
        for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
                writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
+}
+#else
+static void initialize_dram_values(void)
+{
+       int i;
+
+       mxs_adjust_memory_params(dram_vals);
+
+       /*
+        * HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as
+        * per FSL bootlets code.
+        *
+        * mx23 Reference Manual marks HW_DRAM_CTL27 and HW_DRAM_CTL28 as
+        * "reserved".
+        * HW_DRAM_CTL8 is setup as the last element.
+        * So skip the initialization of these HW_DRAM_CTL registers.
+        */
+       for (i = 0; i < ARRAY_SIZE(dram_vals); i++) {
+               if (i == 8 || i == 27 || i == 28 || i == 35)
+                       continue;
+               writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
+       }
 
-#ifdef CONFIG_MX23
        /*
         * Enable tRAS lockout in HW_DRAM_CTL08 ; it must be the last
         * element to be set
         */
        writel((1 << 24), MXS_DRAM_BASE + (4 * 8));
-#endif
 }
+#endif
 
 static void mxs_mem_init_clock(void)
 {
@@ -234,17 +256,9 @@ static void mx23_mem_setup_vddmem(void)
        struct mxs_power_regs *power_regs =
                (struct mxs_power_regs *)MXS_POWER_BASE;
 
-       writel((0x10 << POWER_VDDMEMCTRL_TRG_OFFSET) |
-               POWER_VDDMEMCTRL_ENABLE_ILIMIT |
-               POWER_VDDMEMCTRL_ENABLE_LINREG |
-               POWER_VDDMEMCTRL_PULLDOWN_ACTIVE,
-               &power_regs->hw_power_vddmemctrl);
+       clrbits_le32(&power_regs->hw_power_vddmemctrl,
+               POWER_VDDMEMCTRL_ENABLE_ILIMIT);
 
-       early_delay(10000);
-
-       writel((0x10 << POWER_VDDMEMCTRL_TRG_OFFSET) |
-               POWER_VDDMEMCTRL_ENABLE_LINREG,
-               &power_regs->hw_power_vddmemctrl);
 }
 
 static void mx23_mem_init(void)
@@ -267,22 +281,18 @@ static void mx23_mem_init(void)
 
        initialize_dram_values();
 
-       /* Set START bit in DRAM_CTL16 */
+       /* Set START bit in DRAM_CTL8 */
        setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16);
 
        clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17);
        early_delay(20000);
 
        /* Adjust EMI port priority. */
-       clrsetbits_le32(0x80020000, 0x1f << 16, 0x8);
+       clrsetbits_le32(0x80020000, 0x1f << 16, 0x2);
        early_delay(20000);
 
        setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19);
        setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11);
-
-       /* Wait for bit 10 (DRAM init complete) in DRAM_CTL18 */
-       while (!(readl(MXS_DRAM_BASE + 0x48) & (1 << 10)))
-               ;
 }
 #endif
 
index 287c698..21cac7b 100644 (file)
@@ -687,6 +687,12 @@ static void mxs_power_configure_power_source(void)
        mxs_init_batt_bo();
 
        mxs_switch_vddd_to_dcdc_source();
+
+#ifdef CONFIG_MX23
+       /* Fire up the VDDMEM LinReg now that we're all set. */
+       writel(POWER_VDDMEMCTRL_ENABLE_LINREG | POWER_VDDMEMCTRL_ENABLE_ILIMIT,
+               &power_regs->hw_power_vddmemctrl);
+#endif
 }
 
 static void mxs_enable_output_rail_protection(void)
@@ -781,7 +787,11 @@ struct mxs_vddx_cfg {
 static const struct mxs_vddx_cfg mxs_vddio_cfg = {
        .reg                    = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
                                        hw_power_vddioctrl),
+#if defined(CONFIG_MX23)
+       .step_mV                = 25,
+#else
        .step_mV                = 50,
+#endif
        .lowest_mV              = 2800,
        .powered_by_linreg      = mxs_get_vddio_power_source_off,
        .trg_mask               = POWER_VDDIOCTRL_TRG_MASK,
@@ -804,6 +814,21 @@ static const struct mxs_vddx_cfg mxs_vddd_cfg = {
        .bo_offset_offset       = POWER_VDDDCTRL_BO_OFFSET_OFFSET,
 };
 
+#ifdef CONFIG_MX23
+static const struct mxs_vddx_cfg mxs_vddmem_cfg = {
+       .reg                    = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
+                                       hw_power_vddmemctrl),
+       .step_mV                = 50,
+       .lowest_mV              = 1700,
+       .powered_by_linreg      = NULL,
+       .trg_mask               = POWER_VDDMEMCTRL_TRG_MASK,
+       .bo_irq                 = 0,
+       .bo_enirq               = 0,
+       .bo_offset_mask         = 0,
+       .bo_offset_offset       = 0,
+};
+#endif
+
 static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
                                uint32_t new_target, uint32_t new_brownout)
 {
@@ -821,9 +846,10 @@ static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
        cur_target += cfg->lowest_mV;
 
        adjust_up = new_target > cur_target;
-       powered_by_linreg = cfg->powered_by_linreg();
+       if (cfg->powered_by_linreg)
+               powered_by_linreg = cfg->powered_by_linreg();
 
-       if (adjust_up) {
+       if (adjust_up && cfg->bo_irq) {
                if (powered_by_linreg) {
                        bo_int = readl(cfg->reg);
                        clrbits_le32(cfg->reg, cfg->bo_enirq);
@@ -864,14 +890,16 @@ static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
                cur_target += cfg->lowest_mV;
        } while (new_target > cur_target);
 
-       if (adjust_up && powered_by_linreg) {
-               writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
-               if (bo_int & cfg->bo_enirq)
-                       setbits_le32(cfg->reg, cfg->bo_enirq);
-       }
+       if (cfg->bo_irq) {
+               if (adjust_up && powered_by_linreg) {
+                       writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
+                       if (bo_int & cfg->bo_enirq)
+                               setbits_le32(cfg->reg, cfg->bo_enirq);
+               }
 
-       clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
-                       new_brownout << cfg->bo_offset_offset);
+               clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
+                               new_brownout << cfg->bo_offset_offset);
+       }
 }
 
 static void mxs_setup_batt_detect(void)
@@ -910,7 +938,9 @@ void mxs_power_init(void)
 
        mxs_power_set_vddx(&mxs_vddio_cfg, 3300, 3150);
        mxs_power_set_vddx(&mxs_vddd_cfg, 1500, 1000);
-
+#ifdef CONFIG_MX23
+       mxs_power_set_vddx(&mxs_vddmem_cfg, 2500, 1700);
+#endif
        writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
                POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
                POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
index 3a51879..8b6c30e 100644 (file)
@@ -4,8 +4,8 @@ options {
 }
 
 sources {
-       u_boot_spl="spl/u-boot-spl.bin";
-       u_boot="u-boot.bin";
+       u_boot_spl="OBJTREE/spl/u-boot-spl.bin";
+       u_boot="OBJTREE/u-boot.bin";
 }
 
 section (0) {
index c60615a..a5fa648 100644 (file)
@@ -1,6 +1,6 @@
 sources {
-       u_boot_spl="spl/u-boot-spl.bin";
-       u_boot="u-boot.bin";
+       u_boot_spl="OBJTREE/spl/u-boot-spl.bin";
+       u_boot="OBJTREE/u-boot.bin";
 }
 
 section (0) {
index 4c56711..5fc8e04 100644 (file)
@@ -136,10 +136,6 @@ _TEXT_BASE:
 _bss_start_ofs:
        .word __bss_start - _start
 
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
-       .word __image_copy_end - _start
-
 .globl _bss_end_ofs
 _bss_end_ofs:
        .word __bss_end - _start
@@ -190,83 +186,6 @@ reset:
 
 /*------------------------------------------------------------------------------*/
 
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
-       .globl  relocate_code
-relocate_code:
-       mov     r6, r0  /* save addr of destination */
-
-       adr     r0, _start
-       subs    r9, r6, r0              /* r9 <- relocation offset */
-       beq     relocate_done           /* skip relocation */
-       mov     r1, r6                  /* r1 <- scratch for copy loop */
-       ldr     r3, _image_copy_end_ofs
-       add     r2, r0, r3              /* r2 <- source end address         */
-
-copy_loop:
-       ldmia   r0!, {r10-r11}          /* copy from source address [r0]    */
-       stmia   r1!, {r10-r11}          /* copy to   target address [r1]    */
-       cmp     r0, r2                  /* until source end address [r2]    */
-       blo     copy_loop
-
-#ifndef CONFIG_SPL_BUILD
-       /*
-        * fix .rel.dyn relocations
-        */
-       ldr     r0, _TEXT_BASE          /* r0 <- Text base */
-       ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
-       add     r10, r10, r0            /* r10 <- sym table in FLASH */
-       ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
-       add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
-       ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
-       add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
-fixloop:
-       ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
-       add     r0, r0, r9              /* r0 <- location to fix up in RAM */
-       ldr     r1, [r2, #4]
-       and     r7, r1, #0xff
-       cmp     r7, #23                 /* relative fixup? */
-       beq     fixrel
-       cmp     r7, #2                  /* absolute fixup? */
-       beq     fixabs
-       /* ignore unknown type of fixup */
-       b       fixnext
-fixabs:
-       /* absolute fix: set location to (offset) symbol value */
-       mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
-       add     r1, r10, r1             /* r1 <- address of symbol in table */
-       ldr     r1, [r1, #4]            /* r1 <- symbol value */
-       add     r1, r1, r9              /* r1 <- relocated sym addr */
-       b       fixnext
-fixrel:
-       /* relative fix: increase location by offset */
-       ldr     r1, [r0]
-       add     r1, r1, r9
-fixnext:
-       str     r1, [r0]
-       add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
-       cmp     r2, r3
-       blo     fixloop
-#endif
-
-relocate_done:
-
-       bx      lr
-
-#ifndef CONFIG_SPL_BUILD
-
-_rel_dyn_start_ofs:
-       .word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-       .word __rel_dyn_end - _start
-_dynsym_start_ofs:
-       .word __dynsym_start - _start
-
-#endif
-
        .globl  c_runtime_cpu_setup
 c_runtime_cpu_setup:
 
index 9c2b70d..e9d0c34 100644 (file)
@@ -105,10 +105,6 @@ _TEXT_BASE:
 _bss_start_ofs:
        .word __bss_start - _start
 
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
-       .word __image_copy_end - _start
-
 .globl _bss_end_ofs
 _bss_end_ofs:
        .word __bss_end - _start
@@ -159,79 +155,6 @@ reset:
 
 /*------------------------------------------------------------------------------*/
 
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
-       .globl  relocate_code
-relocate_code:
-       mov     r6, r0  /* save addr of destination */
-
-       adr     r0, _start
-       subs    r9, r6, r0              /* r9 <- relocation offset */
-       beq     relocate_done           /* skip relocation */
-       mov     r1, r6                  /* r1 <- scratch for copy_loop */
-       ldr     r3, _image_copy_end_ofs
-       add     r2, r0, r3              /* r2 <- source end address         */
-
-copy_loop:
-       ldmia   r0!, {r10-r11}          /* copy from source address [r0]    */
-       stmia   r1!, {r10-r11}          /* copy to   target address [r1]    */
-       cmp     r0, r2                  /* until source end address [r2]    */
-       blo     copy_loop
-
-#ifndef CONFIG_SPL_BUILD
-       /*
-        * fix .rel.dyn relocations
-        */
-       ldr     r0, _TEXT_BASE          /* r0 <- Text base */
-       ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
-       add     r10, r10, r0            /* r10 <- sym table in FLASH */
-       ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
-       add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
-       ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
-       add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
-fixloop:
-       ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
-       add     r0, r0, r9              /* r0 <- location to fix up in RAM */
-       ldr     r1, [r2, #4]
-       and     r7, r1, #0xff
-       cmp     r7, #23                 /* relative fixup? */
-       beq     fixrel
-       cmp     r7, #2                  /* absolute fixup? */
-       beq     fixabs
-       /* ignore unknown type of fixup */
-       b       fixnext
-fixabs:
-       /* absolute fix: set location to (offset) symbol value */
-       mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
-       add     r1, r10, r1             /* r1 <- address of symbol in table */
-       ldr     r1, [r1, #4]            /* r1 <- symbol value */
-       add     r1, r1, r9              /* r1 <- relocated sym addr */
-       b       fixnext
-fixrel:
-       /* relative fix: increase location by offset */
-       ldr     r1, [r0]
-       add     r1, r1, r9
-fixnext:
-       str     r1, [r0]
-       add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
-       cmp     r2, r3
-       blo     fixloop
-#endif
-
-relocate_done:
-
-       mov     pc, lr
-
-_rel_dyn_start_ofs:
-       .word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-       .word __rel_dyn_end - _start
-_dynsym_start_ofs:
-       .word __dynsym_start - _start
-
        .globl  c_runtime_cpu_setup
 c_runtime_cpu_setup:
 
index 5e8c528..8dfd919 100644 (file)
@@ -101,10 +101,6 @@ _TEXT_BASE:
 _bss_start_ofs:
        .word __bss_start - _start
 
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
-       .word __image_copy_end - _start
-
 .globl _bss_end_ofs
 _bss_end_ofs:
        .word __bss_end - _start
@@ -155,79 +151,6 @@ reset:
 
 /*------------------------------------------------------------------------------*/
 
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
-       .globl  relocate_code
-relocate_code:
-       mov     r6, r0  /* save addr of destination */
-
-       adr     r0, _start
-       subs    r9, r6, r0              /* r9 <- relocation offset */
-       beq     relocate_done           /* skip relocation */
-       mov     r1, r6                  /* r1 <- scratch for copy_loop */
-       ldr     r3, _image_copy_end_ofs
-       add     r2, r0, r3              /* r2 <- source end address         */
-
-copy_loop:
-       ldmia   r0!, {r10-r11}          /* copy from source address [r0]    */
-       stmia   r1!, {r10-r11}          /* copy to   target address [r1]    */
-       cmp     r0, r2                  /* until source end address [r2]    */
-       blo     copy_loop
-
-#ifndef CONFIG_SPL_BUILD
-       /*
-        * fix .rel.dyn relocations
-        */
-       ldr     r0, _TEXT_BASE          /* r0 <- Text base */
-       ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
-       add     r10, r10, r0            /* r10 <- sym table in FLASH */
-       ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
-       add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
-       ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
-       add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
-fixloop:
-       ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
-       add     r0, r0, r9              /* r0 <- location to fix up in RAM */
-       ldr     r1, [r2, #4]
-       and     r7, r1, #0xff
-       cmp     r7, #23                 /* relative fixup? */
-       beq     fixrel
-       cmp     r7, #2                  /* absolute fixup? */
-       beq     fixabs
-       /* ignore unknown type of fixup */
-       b       fixnext
-fixabs:
-       /* absolute fix: set location to (offset) symbol value */
-       mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
-       add     r1, r10, r1             /* r1 <- address of symbol in table */
-       ldr     r1, [r1, #4]            /* r1 <- symbol value */
-       add     r1, r1, r9              /* r1 <- relocated sym addr */
-       b       fixnext
-fixrel:
-       /* relative fix: increase location by offset */
-       ldr     r1, [r0]
-       add     r1, r1, r9
-fixnext:
-       str     r1, [r0]
-       add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
-       cmp     r2, r3
-       blo     fixloop
-#endif
-
-relocate_done:
-
-       bx      lr
-
-_rel_dyn_start_ofs:
-       .word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-       .word __rel_dyn_end - _start
-_dynsym_start_ofs:
-       .word __dynsym_start - _start
-
        .globl  c_runtime_cpu_setup
 c_runtime_cpu_setup:
 
index cb4210f..8b2878d 100644 (file)
@@ -109,6 +109,8 @@ struct ad_pll {
 #define OSC_SRC_CTRL                   (PLL_SUBSYS_BASE + 0x2C0)
 
 /* PRCM */
+#define ENET_CLKCTRL_CMPL              0x30000
+
 #define CM_DEFAULT_BASE                        (PRCM_BASE + 0x0500)
 
 struct cm_def {
@@ -183,7 +185,7 @@ struct cm_alwon {
        unsigned int resv5[2];
        unsigned int gpmcclkctrl;
        unsigned int ethernet0clkctrl;
-       unsigned int resv6[1];
+       unsigned int ethernet1clkctrl;
        unsigned int mpuclkctrl;
        unsigned int debugssclkctrl;
        unsigned int l3clkctrl;
@@ -203,9 +205,67 @@ struct cm_alwon {
        unsigned int custefuseclkctrl;
 };
 
+#define SATA_PLL_BASE                  (CTRL_BASE + 0x0720)
+
+struct sata_pll {
+       unsigned int pllcfg0;
+       unsigned int pllcfg1;
+       unsigned int pllcfg2;
+       unsigned int pllcfg3;
+       unsigned int pllcfg4;
+       unsigned int pllstatus;
+       unsigned int rxstatus;
+       unsigned int txstatus;
+       unsigned int testcfg;
+};
+
+#define SEL_IN_FREQ            (0x1 << 31)
+#define DIGCLRZ                        (0x1 << 30)
+#define ENDIGLDO               (0x1 << 4)
+#define APLL_CP_CURR           (0x1 << 3)
+#define ENBGSC_REF             (0x1 << 2)
+#define ENPLLLDO               (0x1 << 1)
+#define ENPLL                  (0x1 << 0)
+
+#define SATA_PLLCFG0_1 (SEL_IN_FREQ | ENBGSC_REF)
+#define SATA_PLLCFG0_2 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF)
+#define SATA_PLLCFG0_3 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF | ENPLLLDO)
+#define SATA_PLLCFG0_4 (SEL_IN_FREQ | DIGCLRZ | ENDIGLDO | ENBGSC_REF | \
+                       ENPLLLDO | ENPLL)
+
+#define PLL_LOCK               (0x1 << 0)
+
+#define ENSATAMODE             (0x1 << 31)
+#define PLLREFSEL              (0x1 << 30)
+#define MDIVINT                        (0x4b << 18)
+#define EN_CLKAUX              (0x1 << 5)
+#define EN_CLK125M             (0x1 << 4)
+#define EN_CLK100M             (0x1 << 3)
+#define EN_CLK50M              (0x1 << 2)
+
+#define SATA_PLLCFG1 (ENSATAMODE |     \
+                     PLLREFSEL |       \
+                     MDIVINT |         \
+                     EN_CLKAUX |       \
+                     EN_CLK125M |      \
+                     EN_CLK100M |      \
+                     EN_CLK50M)
+
+#define DIGLDO_EN_CAPLESSMODE  (0x1 << 22)
+#define PLLDO_EN_LDO_STABLE    (0x1 << 11)
+#define PLLDO_EN_BUF_CUR       (0x1 << 7)
+#define PLLDO_EN_LP            (0x1 << 6)
+#define PLLDO_CTRL_TRIM_1_4V   (0x10 << 1)
+
+#define SATA_PLLCFG3 (DIGLDO_EN_CAPLESSMODE |  \
+                     PLLDO_EN_LDO_STABLE |     \
+                     PLLDO_EN_BUF_CUR |        \
+                     PLLDO_EN_LP |             \
+                     PLLDO_CTRL_TRIM_1_4V)
 
 const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE;
 const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE;
+const struct sata_pll *spll = (struct sata_pll *)SATA_PLL_BASE;
 
 /*
  * Enable the peripheral clock for required peripherals
@@ -221,6 +281,15 @@ static void enable_per_clocks(void)
        writel(PRCM_MOD_EN, &cmalwon->mmchs1clkctrl);
        while (readl(&cmalwon->mmchs1clkctrl) != PRCM_MOD_EN)
                ;
+
+       /* Ethernet */
+       writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl);
+       writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl);
+       while ((readl(&cmalwon->ethernet0clkctrl) & ENET_CLKCTRL_CMPL) != 0)
+               ;
+       writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl);
+       while ((readl(&cmalwon->ethernet1clkctrl) & ENET_CLKCTRL_CMPL) != 0)
+               ;
 }
 
 /*
@@ -365,6 +434,35 @@ void ddr_pll_config(unsigned int ddrpll_m)
        pll_config(DDR_PLL_BASE, DDR_N, DDR_M, DDR_M2, DDR_CLKCTRL, 1);
 }
 
+void sata_pll_config(void)
+{
+       /*
+        * This sequence for configuring the SATA PLL
+        * resident in the control module is documented
+        * in TI8148 TRM section 21.3.1
+        */
+       writel(SATA_PLLCFG1, &spll->pllcfg1);
+       udelay(50);
+
+       writel(SATA_PLLCFG3, &spll->pllcfg3);
+       udelay(50);
+
+       writel(SATA_PLLCFG0_1, &spll->pllcfg0);
+       udelay(50);
+
+       writel(SATA_PLLCFG0_2, &spll->pllcfg0);
+       udelay(50);
+
+       writel(SATA_PLLCFG0_3, &spll->pllcfg0);
+       udelay(50);
+
+       writel(SATA_PLLCFG0_4, &spll->pllcfg0);
+       udelay(50);
+
+       while (((readl(&spll->pllstatus) & PLL_LOCK) == 0))
+               ;
+}
+
 void enable_emif_clocks(void) {};
 
 void enable_dmm_clocks(void)
@@ -397,9 +495,10 @@ void pll_init()
        /* Enable the control module */
        writel(PRCM_MOD_EN, &cmalwon->controlclkctrl);
 
+       /* Configure PLLs */
        mpu_pll_config();
-
        l3_pll_config();
+       sata_pll_config();
 
        /* Enable the required peripherals */
        enable_per_clocks();
index 5fd8b47..ac049ac 100644 (file)
@@ -92,7 +92,6 @@ u32 get_sysboot_value(void)
 int print_cpuinfo(void)
 {
        char *cpu_s, *sec_s;
-       int arm_freq, ddr_freq;
 
        switch (get_cpu_type()) {
        case AM335X:
@@ -123,10 +122,7 @@ int print_cpuinfo(void)
                sec_s = "?";
        }
 
-       printf("%s-%s rev %d\n",
-                       cpu_s, sec_s, get_cpu_rev());
-
-       /* TODO: Print ARM and DDR frequencies  */
+       printf("%s-%s rev %d\n", cpu_s, sec_s, get_cpu_rev());
 
        return 0;
 }
similarity index 72%
rename from board/alaska/Makefile
rename to arch/arm/cpu/armv7/at91/Makefile
index a21f851..040c67d 100644 (file)
@@ -1,7 +1,10 @@
 #
-# (C) Copyright 2003-2006
+# (C) Copyright 2000-2008
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
+# (C) Copyright 2013
+# Bo Shen <voice.shen@atmel.com>
+#
 # See file CREDITS for list of people who contributed to this
 # project.
 #
@@ -12,7 +15,7 @@
 #
 # This program is distributed in the hope that it will be useful,
 # but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 # GNU General Public License for more details.
 #
 # You should have received a copy of the GNU General Public License
 
 include $(TOPDIR)/config.mk
 
-LIB    = $(obj)lib$(BOARD).o
+LIB    = $(obj)lib$(SOC).o
+
+COBJS-$(CONFIG_SAMA5D3)        += sama5d3_devices.o
+COBJS-y += clock.o
+COBJS-y += cpu.o
+COBJS-y += reset.o
+COBJS-y += timer.o
 
-COBJS  := $(BOARD).o flash.o
+SRCS    := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS    := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
 
-SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS   := $(addprefix $(obj),$(COBJS))
-SOBJS  := $(addprefix $(obj),$(SOBJS))
+all:   $(obj).depend $(LIB)
 
 $(LIB):        $(OBJS)
        $(call cmd_link_o_target, $(OBJS))
diff --git a/arch/arm/cpu/armv7/at91/clock.c b/arch/arm/cpu/armv7/at91/clock.c
new file mode 100644 (file)
index 0000000..624b52c
--- /dev/null
@@ -0,0 +1,125 @@
+/*
+ * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
+ *
+ * Copyright (C) 2005 David Brownell
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ * Copyright (C) 2013 Bo Shen <voice.shen@atmel.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
+
+#if !defined(CONFIG_AT91FAMILY)
+# error You need to define CONFIG_AT91FAMILY in your board config!
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static unsigned long at91_css_to_rate(unsigned long css)
+{
+       switch (css) {
+       case AT91_PMC_MCKR_CSS_SLOW:
+               return CONFIG_SYS_AT91_SLOW_CLOCK;
+       case AT91_PMC_MCKR_CSS_MAIN:
+               return gd->arch.main_clk_rate_hz;
+       case AT91_PMC_MCKR_CSS_PLLA:
+               return gd->arch.plla_rate_hz;
+       }
+
+       return 0;
+}
+
+static u32 at91_pll_rate(u32 freq, u32 reg)
+{
+       unsigned mul, div;
+
+       div = reg & 0xff;
+       mul = (reg >> 18) & 0x7f;
+       if (div && mul) {
+               freq /= div;
+               freq *= mul + 1;
+       } else {
+               freq = 0;
+       }
+
+       return freq;
+}
+
+int at91_clock_init(unsigned long main_clock)
+{
+       unsigned freq, mckr;
+       struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
+       unsigned tmp;
+       /*
+        * When the bootloader initialized the main oscillator correctly,
+        * there's no problem using the cycle counter.  But if it didn't,
+        * or when using oscillator bypass mode, we must be told the speed
+        * of the main clock.
+        */
+       if (!main_clock) {
+               do {
+                       tmp = readl(&pmc->mcfr);
+               } while (!(tmp & AT91_PMC_MCFR_MAINRDY));
+               tmp &= AT91_PMC_MCFR_MAINF_MASK;
+               main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
+       }
+#endif
+       gd->arch.main_clk_rate_hz = main_clock;
+
+       /* report if PLLA is more than mildly overclocked */
+       gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
+
+       /*
+        * MCK and CPU derive from one of those primary clocks.
+        * For now, assume this parentage won't change.
+        */
+       mckr = readl(&pmc->mckr);
+
+       /* plla divisor by 2 */
+       if (mckr & (1 << 12))
+               gd->arch.plla_rate_hz >>= 1;
+
+       gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
+       freq = gd->arch.mck_rate_hz;
+
+       /* prescale */
+       freq >>= mckr & AT91_PMC_MCKR_PRES_MASK;
+
+       switch (mckr & AT91_PMC_MCKR_MDIV_MASK) {
+       case AT91_PMC_MCKR_MDIV_2:
+               gd->arch.mck_rate_hz = freq / 2;
+               break;
+       case AT91_PMC_MCKR_MDIV_3:
+               gd->arch.mck_rate_hz = freq / 3;
+               break;
+       case AT91_PMC_MCKR_MDIV_4:
+               gd->arch.mck_rate_hz = freq / 4;
+               break;
+       default:
+               break;
+       }
+
+       gd->arch.cpu_clk_rate_hz = freq;
+
+       return 0;
+}
+
+void at91_periph_clk_enable(int id)
+{
+       struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+       if (id > 31)
+               writel(1 << (id - 32), &pmc->pcer1);
+       else
+               writel(1 << id, &pmc->pcer);
+}
diff --git a/arch/arm/cpu/armv7/at91/cpu.c b/arch/arm/cpu/armv7/at91/cpu.c
new file mode 100644 (file)
index 0000000..3df6143
--- /dev/null
@@ -0,0 +1,90 @@
+/*
+ * (C) Copyright 2010
+ * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
+ * (C) Copyright 2009
+ * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ * (C) Copyright 2013
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_dbu.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_pit.h>
+#include <asm/arch/at91_gpbr.h>
+#include <asm/arch/clk.h>
+
+#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
+#define CONFIG_SYS_AT91_MAIN_CLOCK 0
+#endif
+
+int arch_cpu_init(void)
+{
+       return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
+}
+
+void arch_preboot_os(void)
+{
+       ulong cpiv;
+       at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
+
+       cpiv = AT91_PIT_MR_PIV_MASK(readl(&pit->piir));
+
+       /*
+        * Disable PITC
+        * Add 0x1000 to current counter to stop it faster
+        * without waiting for wrapping back to 0
+        */
+       writel(cpiv + 0x1000, &pit->mr);
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+       char buf[32];
+
+       printf("CPU: %s\n", get_cpu_name());
+       printf("Crystal frequency: %8s MHz\n",
+              strmhz(buf, get_main_clk_rate()));
+       printf("CPU clock        : %8s MHz\n",
+              strmhz(buf, get_cpu_clk_rate()));
+       printf("Master clock     : %8s MHz\n",
+              strmhz(buf, get_mck_clk_rate()));
+
+       return 0;
+}
+#endif
+
+void enable_caches(void)
+{
+}
+
+unsigned int get_chip_id(void)
+{
+       return readl(ATMEL_BASE_DBGU + AT91_DBU_CIDR) & ~AT91_DBU_CIDR_MASK;
+}
+
+unsigned int get_extension_chip_id(void)
+{
+       return readl(ATMEL_BASE_DBGU + AT91_DBU_EXID);
+}
diff --git a/arch/arm/cpu/armv7/at91/reset.c b/arch/arm/cpu/armv7/at91/reset.c
new file mode 100644 (file)
index 0000000..b9f83d9
--- /dev/null
@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2013
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_rstc.h>
+
+/* Reset the cpu by telling the reset controller to do so */
+void reset_cpu(ulong ignored)
+{
+       at91_rstc_t *rstc = (at91_rstc_t *)ATMEL_BASE_RSTC;
+
+       writel(AT91_RSTC_KEY
+               | AT91_RSTC_CR_PROCRST  /* Processor Reset */
+               | AT91_RSTC_CR_PERRST   /* Peripheral Reset */
+#ifdef CONFIG_AT91RESET_EXTRST
+               | AT91_RSTC_CR_EXTRST   /* External Reset (assert nRST pin) */
+#endif
+               , &rstc->cr);
+       /* never reached */
+       do { } while (1);
+}
diff --git a/arch/arm/cpu/armv7/at91/sama5d3_devices.c b/arch/arm/cpu/armv7/at91/sama5d3_devices.c
new file mode 100644 (file)
index 0000000..acf8b43
--- /dev/null
@@ -0,0 +1,196 @@
+/*
+ * Copyright (C) 2012-2013 Atmel Corporation
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/sama5d3.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/io.h>
+
+unsigned int has_emac()
+{
+       return cpu_is_sama5d31() || cpu_is_sama5d35();
+}
+
+unsigned int has_gmac()
+{
+       return !cpu_is_sama5d31();
+}
+
+unsigned int has_lcdc()
+{
+       return !cpu_is_sama5d35();
+}
+
+char *get_cpu_name()
+{
+       unsigned int extension_id = get_extension_chip_id();
+
+       if (cpu_is_sama5d3())
+               switch (extension_id) {
+               case ARCH_EXID_SAMA5D31:
+                       return "SAMA5D31";
+               case ARCH_EXID_SAMA5D33:
+                       return "SAMA5D33";
+               case ARCH_EXID_SAMA5D34:
+                       return "SAMA5D34";
+               case ARCH_EXID_SAMA5D35:
+                       return "SAMA5D35";
+               default:
+                       return "Unknown CPU type";
+               }
+       else
+               return "Unknown CPU type";
+}
+
+void at91_serial0_hw_init(void)
+{
+       at91_set_a_periph(AT91_PIO_PORTD, 18, 1);       /* TXD0 */
+       at91_set_a_periph(AT91_PIO_PORTD, 17, 0);       /* RXD0 */
+
+       /* Enable clock */
+       at91_periph_clk_enable(ATMEL_ID_USART0);
+}
+
+void at91_serial1_hw_init(void)
+{
+       at91_set_a_periph(AT91_PIO_PORTB, 29, 1);       /* TXD1 */
+       at91_set_a_periph(AT91_PIO_PORTB, 28, 0);       /* RXD1 */
+
+       /* Enable clock */
+       at91_periph_clk_enable(ATMEL_ID_USART1);
+}
+
+void at91_serial2_hw_init(void)
+{
+       at91_set_b_periph(AT91_PIO_PORTE, 26, 1);       /* TXD2 */
+       at91_set_b_periph(AT91_PIO_PORTE, 25, 0);       /* RXD2 */
+
+       /* Enable clock */
+       at91_periph_clk_enable(ATMEL_ID_USART2);
+}
+
+void at91_seriald_hw_init(void)
+{
+       at91_set_a_periph(AT91_PIO_PORTB, 31, 1);       /* DTXD */
+       at91_set_a_periph(AT91_PIO_PORTB, 30, 0);       /* DRXD */
+
+       /* Enable clock */
+       at91_periph_clk_enable(ATMEL_ID_SYS);
+}
+
+#if defined(CONFIG_ATMEL_SPI)
+void at91_spi0_hw_init(unsigned long cs_mask)
+{
+       at91_set_a_periph(AT91_PIO_PORTD, 10, 0);       /* SPI0_MISO */
+       at91_set_a_periph(AT91_PIO_PORTD, 11, 0);       /* SPI0_MOSI */
+       at91_set_a_periph(AT91_PIO_PORTD, 12, 0);       /* SPI0_SPCK */
+
+       if (cs_mask & (1 << 0))
+               at91_set_pio_output(AT91_PIO_PORTD, 13, 1);
+       if (cs_mask & (1 << 1))
+               at91_set_pio_output(AT91_PIO_PORTD, 14, 1);
+       if (cs_mask & (1 << 2))
+               at91_set_pio_output(AT91_PIO_PORTD, 15, 1);
+       if (cs_mask & (1 << 3))
+               at91_set_pio_output(AT91_PIO_PORTD, 16, 1);
+
+       /* Enable clock */
+       at91_periph_clk_enable(ATMEL_ID_SPI0);
+}
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+void at91_mci_hw_init(void)
+{
+       at91_set_a_periph(AT91_PIO_PORTD, 0, 0);        /* MCI0 CMD */
+       at91_set_a_periph(AT91_PIO_PORTD, 1, 0);        /* MCI0 DA0 */
+       at91_set_a_periph(AT91_PIO_PORTD, 2, 0);        /* MCI0 DA1 */
+       at91_set_a_periph(AT91_PIO_PORTD, 3, 0);        /* MCI0 DA2 */
+       at91_set_a_periph(AT91_PIO_PORTD, 4, 0);        /* MCI0 DA3 */
+#ifdef CONFIG_ATMEL_MCI_8BIT
+       at91_set_a_periph(AT91_PIO_PORTD, 5, 0);        /* MCI0 DA4 */
+       at91_set_a_periph(AT91_PIO_PORTD, 6, 0);        /* MCI0 DA5 */
+       at91_set_a_periph(AT91_PIO_PORTD, 7, 0);        /* MCI0 DA6 */
+       at91_set_a_periph(AT91_PIO_PORTD, 8, 0);        /* MCI0 DA7 */
+#endif
+       at91_set_a_periph(AT91_PIO_PORTD, 9, 0);        /* MCI0 CLK */
+
+       /* Enable clock */
+       at91_periph_clk_enable(ATMEL_ID_MCI0);
+}
+#endif
+
+#ifdef CONFIG_MACB
+void at91_macb_hw_init(void)
+{
+       at91_set_a_periph(AT91_PIO_PORTC, 7, 0);        /* ETXCK_EREFCK */
+       at91_set_a_periph(AT91_PIO_PORTC, 5, 0);        /* ERXDV */
+       at91_set_a_periph(AT91_PIO_PORTC, 2, 0);        /* ERX0 */
+       at91_set_a_periph(AT91_PIO_PORTC, 3, 0);        /* ERX1 */
+       at91_set_a_periph(AT91_PIO_PORTC, 6, 0);        /* ERXER */
+       at91_set_a_periph(AT91_PIO_PORTC, 4, 0);        /* ETXEN */
+       at91_set_a_periph(AT91_PIO_PORTC, 0, 0);        /* ETX0 */
+       at91_set_a_periph(AT91_PIO_PORTC, 1, 0);        /* ETX1 */
+       at91_set_a_periph(AT91_PIO_PORTC, 9, 0);        /* EMDIO */
+       at91_set_a_periph(AT91_PIO_PORTC, 8, 0);        /* EMDC */
+
+       /* Enable clock */
+       at91_periph_clk_enable(ATMEL_ID_EMAC);
+}
+#endif
+
+#ifdef CONFIG_LCD
+void at91_lcd_hw_init(void)
+{
+       at91_set_a_periph(AT91_PIO_PORTA, 24, 0);       /* LCDPWM */
+       at91_set_a_periph(AT91_PIO_PORTA, 25, 0);       /* LCDDISP */
+       at91_set_a_periph(AT91_PIO_PORTA, 26, 0);       /* LCDVSYNC */
+       at91_set_a_periph(AT91_PIO_PORTA, 27, 0);       /* LCDHSYNC */
+       at91_set_a_periph(AT91_PIO_PORTA, 28, 0);       /* LCDDOTCK */
+       at91_set_a_periph(AT91_PIO_PORTA, 29, 0);       /* LCDDEN */
+
+       /* The lower 16-bit of LCD only available on Port A */
+       at91_set_a_periph(AT91_PIO_PORTA,  0, 0);       /* LCDD0 */
+       at91_set_a_periph(AT91_PIO_PORTA,  1, 0);       /* LCDD1 */
+       at91_set_a_periph(AT91_PIO_PORTA,  2, 0);       /* LCDD2 */
+       at91_set_a_periph(AT91_PIO_PORTA,  3, 0);       /* LCDD3 */
+       at91_set_a_periph(AT91_PIO_PORTA,  4, 0);       /* LCDD4 */
+       at91_set_a_periph(AT91_PIO_PORTA,  5, 0);       /* LCDD5 */
+       at91_set_a_periph(AT91_PIO_PORTA,  6, 0);       /* LCDD6 */
+       at91_set_a_periph(AT91_PIO_PORTA,  7, 0);       /* LCDD7 */
+       at91_set_a_periph(AT91_PIO_PORTA,  8, 0);       /* LCDD8 */
+       at91_set_a_periph(AT91_PIO_PORTA,  9, 0);       /* LCDD9 */
+       at91_set_a_periph(AT91_PIO_PORTA, 10, 0);       /* LCDD10 */
+       at91_set_a_periph(AT91_PIO_PORTA, 11, 0);       /* LCDD11 */
+       at91_set_a_periph(AT91_PIO_PORTA, 12, 0);       /* LCDD12 */
+       at91_set_a_periph(AT91_PIO_PORTA, 13, 0);       /* LCDD13 */
+       at91_set_a_periph(AT91_PIO_PORTA, 14, 0);       /* LCDD14 */
+       at91_set_a_periph(AT91_PIO_PORTA, 15, 0);       /* LCDD15 */
+
+       /* Enable clock */
+       at91_periph_clk_enable(ATMEL_ID_LCDC);
+}
+#endif
diff --git a/arch/arm/cpu/armv7/at91/timer.c b/arch/arm/cpu/armv7/at91/timer.c
new file mode 100644 (file)
index 0000000..b3a450f
--- /dev/null
@@ -0,0 +1,139 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2013
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_pit.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
+#include <div64.h>
+
+#if !defined(CONFIG_AT91FAMILY)
+# error You need to define CONFIG_AT91FAMILY in your board config!
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * We're using the SAMA5D3x PITC in 32 bit mode, by
+ * setting the 20 bit counter period to its maximum (0xfffff).
+ * (See the relevant data sheets to understand that this really works)
+ *
+ * We do also mimic the typical powerpc way of incrementing
+ * two 32 bit registers called tbl and tbu.
+ *
+ * Those registers increment at 1/16 the main clock rate.
+ */
+
+#define TIMER_LOAD_VAL 0xfffff
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+       tick *= CONFIG_SYS_HZ;
+       do_div(tick, gd->arch.timer_rate_hz);
+
+       return tick;
+}
+
+static inline unsigned long long usec_to_tick(unsigned long long usec)
+{
+       usec *= gd->arch.timer_rate_hz;
+       do_div(usec, 1000000);
+
+       return usec;
+}
+
+/*
+ * Use the PITC in full 32 bit incrementing mode
+ */
+int timer_init(void)
+{
+       at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
+
+       /* Enable PITC Clock */
+       at91_periph_clk_enable(ATMEL_ID_SYS);
+
+       /* Enable PITC */
+       writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
+
+       gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16;
+       gd->arch.tbu = 0;
+       gd->arch.tbl = 0;
+
+       return 0;
+}
+
+/*
+ * Get the current 64 bit timer tick count
+ */
+unsigned long long get_ticks(void)
+{
+       at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
+
+       ulong now = readl(&pit->piir);
+
+       /* increment tbu if tbl has rolled over */
+       if (now < gd->arch.tbl)
+               gd->arch.tbu++;
+       gd->arch.tbl = now;
+       return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
+}
+
+void __udelay(unsigned long usec)
+{
+       unsigned long long start;
+       ulong tmo;
+
+       start = get_ticks();            /* get current timestamp */
+       tmo = usec_to_tick(usec);       /* convert usecs to ticks */
+       while ((get_ticks() - start) < tmo)
+               ;                       /* loop till time has passed */
+}
+
+/*
+ * get_timer(base) can be used to check for timeouts or
+ * to measure elasped time relative to an event:
+ *
+ * ulong start_time = get_timer(0) sets start_time to the current
+ * time value.
+ * get_timer(start_time) returns the time elapsed since then.
+ *
+ * The time is used in CONFIG_SYS_HZ units!
+ */
+ulong get_timer(ulong base)
+{
+       return tick_to_time(get_ticks()) - base;
+}
+
+/*
+ * Return the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+       return gd->arch.timer_rate_hz;
+}
index 0d45528..0a15aa4 100644 (file)
@@ -37,7 +37,13 @@ ENTRY(lowlevel_init)
         */
        ldr     sp, =CONFIG_SYS_INIT_SP_ADDR
        bic     sp, sp, #7 /* 8-byte alignment for ABI compliance */
-
+#ifdef CONFIG_SPL_BUILD
+       ldr     r8, =gdata
+#else
+       sub     sp, #GD_SIZE
+       bic     sp, sp, #7
+       mov     r8, sp
+#endif
        /*
         * Save the old lr(passed in ip) and the current lr to stack
         */
index ecd1184..e05fae9 100644 (file)
@@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
 
 LIB    = $(obj)lib$(SOC).o
 
-COBJS  = soc.o clock.o iomux.o
+COBJS  = soc.o clock.o
 SOBJS = lowlevel_init.o
 
 SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
index 76c2c52..431756e 100644 (file)
@@ -739,10 +739,11 @@ static int config_core_clk(u32 ref, u32 freq)
 static int config_nfc_clk(u32 nfc_clk)
 {
        u32 parent_rate = get_emi_slow_clk();
-       u32 div = parent_rate / nfc_clk;
+       u32 div;
 
-       if (nfc_clk <= 0)
+       if (nfc_clk == 0)
                return -EINVAL;
+       div = parent_rate / nfc_clk;
        if (div == 0)
                div++;
        if (parent_rate / div > NFC_CLK_MAX)
@@ -755,6 +756,15 @@ static int config_nfc_clk(u32 nfc_clk)
        return 0;
 }
 
+void enable_nfc_clk(unsigned char enable)
+{
+       unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
+
+       clrsetbits_le32(&mxc_ccm->CCGR5,
+               MXC_CCM_CCGR5_EMI_ENFC(MXC_CCM_CCGR_CG_MASK),
+               MXC_CCM_CCGR5_EMI_ENFC(cg));
+}
+
 /* Config main_bus_clock for periphs */
 static int config_periph_clk(u32 ref, u32 freq)
 {
diff --git a/arch/arm/cpu/armv7/mx5/iomux.c b/arch/arm/cpu/armv7/mx5/iomux.c
deleted file mode 100644 (file)
index d4e3bbb..0000000
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/sys_proto.h>
-
-/* IOMUX register (base) addresses */
-enum iomux_reg_addr {
-       IOMUXGPR0 = IOMUXC_BASE_ADDR,
-       IOMUXGPR1 = IOMUXC_BASE_ADDR + 0x004,
-       IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR,
-       IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + MUX_I_END,
-       IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + PAD_I_START,
-       IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + INPUT_CTL_START,
-};
-
-#define MUX_PIN_NUM_MAX (((MUX_I_END - MUX_I_START) >> 2) + 1)
-
-/* Get the iomux register address of this pin */
-static inline u32 get_mux_reg(iomux_pin_name_t pin)
-{
-       u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
-
-#if defined(CONFIG_MX51)
-       if (is_soc_rev(CHIP_REV_2_0) < 0) {
-               /*
-                * Fixup register address:
-                * i.MX51 TO1 has offset with the register
-                * which is define as TO2.
-                */
-               if ((pin == MX51_PIN_NANDF_RB5) ||
-                       (pin == MX51_PIN_NANDF_RB6) ||
-                       (pin == MX51_PIN_NANDF_RB7))
-                       ; /* Do nothing */
-               else if (mux_reg >= 0x2FC)
-                       mux_reg += 8;
-               else if (mux_reg >= 0x130)
-                       mux_reg += 0xC;
-       }
-#endif
-       mux_reg += IOMUXSW_MUX_CTL;
-       return mux_reg;
-}
-
-/* Get the pad register address of this pin */
-static inline u32 get_pad_reg(iomux_pin_name_t pin)
-{
-       u32 pad_reg = PIN_TO_IOMUX_PAD(pin);
-
-#if defined(CONFIG_MX51)
-       if (is_soc_rev(CHIP_REV_2_0) < 0) {
-               /*
-                * Fixup register address:
-                * i.MX51 TO1 has offset with the register
-                * which is define as TO2.
-                */
-               if ((pin == MX51_PIN_NANDF_RB5) ||
-                       (pin == MX51_PIN_NANDF_RB6) ||
-                       (pin == MX51_PIN_NANDF_RB7))
-                       ; /* Do nothing */
-               else if (pad_reg == 0x4D0 - PAD_I_START)
-                       pad_reg += 0x4C;
-               else if (pad_reg == 0x860 - PAD_I_START)
-                       pad_reg += 0x9C;
-               else if (pad_reg >= 0x804 - PAD_I_START)
-                       pad_reg += 0xB0;
-               else if (pad_reg >= 0x7FC - PAD_I_START)
-                       pad_reg += 0xB4;
-               else if (pad_reg >= 0x4E4 - PAD_I_START)
-                       pad_reg += 0xCC;
-               else
-                       pad_reg += 8;
-       }
-#endif
-       pad_reg += IOMUXSW_PAD_CTL;
-       return pad_reg;
-}
-
-/* Get the last iomux register address */
-static inline u32 get_mux_end(void)
-{
-#if defined(CONFIG_MX51)
-       if (is_soc_rev(CHIP_REV_2_0) < 0)
-               return IOMUXC_BASE_ADDR + (0x3F8 - 4);
-       else
-               return IOMUXC_BASE_ADDR + (0x3F0 - 4);
-#endif
-       return IOMUXSW_MUX_END;
-}
-
-/*
- * This function is used to configure a pin through the IOMUX module.
- * @param  pin         a pin number as defined in iomux_pin_name_t
- * @param  cfg         an output function as defined in iomux_pin_cfg_t
- *
- * @return             0 if successful; Non-zero otherwise
- */
-static void iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
-       u32 mux_reg = get_mux_reg(pin);
-
-       if ((mux_reg > get_mux_end()) || (mux_reg < IOMUXSW_MUX_CTL))
-               return ;
-       if (cfg == IOMUX_CONFIG_GPIO)
-               writel(PIN_TO_ALT_GPIO(pin), mux_reg);
-       else
-               writel(cfg, mux_reg);
-}
-
-/*
- * Request ownership for an IO pin. This function has to be the first one
- * being called before that pin is used. The caller has to check the
- * return value to make sure it returns 0.
- *
- * @param  pin         a name defined by iomux_pin_name_t
- * @param  cfg         an input function as defined in iomux_pin_cfg_t
- *
- */
-void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
-       iomux_config_mux(pin, cfg);
-}
-
-/*
- * Release ownership for an IO pin
- *
- * @param  pin         a name defined by iomux_pin_name_t
- * @param  cfg         an input function as defined in iomux_pin_cfg_t
- */
-void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
-}
-
-/*
- * This function configures the pad value for a IOMUX pin.
- *
- * @param  pin     a pin number as defined in iomux_pin_name_t
- * @param  config  the ORed value of elements defined in iomux_pad_config_t
- */
-void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config)
-{
-       u32 pad_reg = get_pad_reg(pin);
-       writel(config, pad_reg);
-}
-
-unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin)
-{
-       u32 pad_reg = get_pad_reg(pin);
-       return readl(pad_reg);
-}
-
-/*
- * This function configures daisy-chain
- *
- * @param input    index of input select register
- * @param config   the binary value of elements
- */
-void mxc_iomux_set_input(iomux_input_select_t input, u32 config)
-{
-       u32 reg = IOMUXSW_INPUT_CTL + (input << 2);
-
-       writel(config, reg);
-}
index 263658a..3d50a5d 100644 (file)
@@ -72,6 +72,13 @@ u32 get_cpu_rev(void)
        return system_rev;
 }
 
+#ifdef CONFIG_REVISION_TAG
+u32 __weak get_board_rev(void)
+{
+       return get_cpu_rev();
+}
+#endif
+
 #ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)
 {
index a50db70..3c0d908 100644 (file)
@@ -37,6 +37,20 @@ enum pll_clocks {
 
 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 
+#ifdef CONFIG_MXC_OCOTP
+void enable_ocotp_clk(unsigned char enable)
+{
+       u32 reg;
+
+       reg = __raw_readl(&imx_ccm->CCGR2);
+       if (enable)
+               reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
+       else
+               reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
+       __raw_writel(reg, &imx_ccm->CCGR2);
+}
+#endif
+
 void enable_usboh3_clk(unsigned char enable)
 {
        u32 reg;
@@ -186,12 +200,16 @@ static u32 get_ipg_per_clk(void)
 static u32 get_uart_clk(void)
 {
        u32 reg, uart_podf;
-
+       u32 freq = PLL3_80M;
        reg = __raw_readl(&imx_ccm->cscdr1);
+#ifdef CONFIG_MX6SL
+       if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
+               freq = MXC_HCLK;
+#endif
        reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
        uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
 
-       return PLL3_80M / (uart_podf + 1);
+       return freq / (uart_podf + 1);
 }
 
 static u32 get_cspi_clk(void)
@@ -252,6 +270,35 @@ static u32 get_emi_slow_clk(void)
        return root_freq / (emi_slow_pof + 1);
 }
 
+#ifdef CONFIG_MX6SL
+static u32 get_mmdc_ch0_clk(void)
+{
+       u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
+       u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
+       u32 freq, podf;
+
+       podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
+                       >> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
+
+       switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
+               MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
+       case 0:
+               freq = decode_pll(PLL_BUS, MXC_HCLK);
+               break;
+       case 1:
+               freq = PLL2_PFD2_FREQ;
+               break;
+       case 2:
+               freq = PLL2_PFD0_FREQ;
+               break;
+       case 3:
+               freq = PLL2_PFD2_DIV_FREQ;
+       }
+
+       return freq / (podf + 1);
+
+}
+#else
 static u32 get_mmdc_ch0_clk(void)
 {
        u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
@@ -260,6 +307,7 @@ static u32 get_mmdc_ch0_clk(void)
 
        return get_periph_clk() / (mmdc_ch0_podf + 1);
 }
+#endif
 
 static u32 get_usdhc_clk(u32 port)
 {
index 2ea8ca3..fc436fb 100644 (file)
@@ -30,6 +30,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/dma.h>
 #include <stdbool.h>
 
 struct scu_regs {
@@ -151,6 +152,12 @@ int arch_cpu_init(void)
        set_vddsoc(1200);       /* Set VDDSOC to 1.2V */
 
        imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
+
+#ifdef CONFIG_APBH_DMA
+       /* Start APBH DMA */
+       mxs_dma_init();
+#endif
+
        return 0;
 }
 
@@ -165,8 +172,8 @@ void enable_caches(void)
 #if defined(CONFIG_FEC_MXC)
 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 {
-       struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
-       struct fuse_bank *bank = &iim->bank[4];
+       struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+       struct fuse_bank *bank = &ocotp->bank[4];
        struct fuse_bank4_regs *fuse =
                        (struct fuse_bank4_regs *)bank->fuse_regs;
 
index 24cbe2d..76ae1b6 100644 (file)
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/sys_proto.h>
 
-/*
- * This is used to verify if the configuration header
- * was executed by rom code prior to control of transfer
- * to the bootloader. SPL is responsible for saving and
- * passing the boot_params pointer to the u-boot.
- */
-struct omap_boot_parameters boot_params __attribute__ ((section(".data")));
+DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_SPL_BUILD
-/*
- * We use static variables because global data is not ready yet.
- * Initialized data is available in SPL right from the beginning.
- * We would not typically need to save these parameters in regular
- * U-Boot. This is needed only in SPL at the moment.
- */
-u32 omap_bootmode = MMCSD_MODE_FAT;
+void save_omap_boot_params(void)
+{
+       u32 rom_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS);
+       u8 boot_device;
+       u32 dev_desc, dev_data;
+
+       if ((rom_params <  NON_SECURE_SRAM_START) ||
+           (rom_params > NON_SECURE_SRAM_END))
+               return;
+
+       /*
+        * rom_params can be type casted to omap_boot_parameters and
+        * used. But it not correct to assume that romcode structure
+        * encoding would be same as u-boot. So use the defined offsets.
+        */
+       gd->arch.omap_boot_params.omap_bootdevice = boot_device =
+                                  *((u8 *)(rom_params + BOOT_DEVICE_OFFSET));
+
+       gd->arch.omap_boot_params.ch_flags =
+                               *((u8 *)(rom_params + CH_FLAGS_OFFSET));
 
+       if ((boot_device >= MMC_BOOT_DEVICES_START) &&
+           (boot_device <= MMC_BOOT_DEVICES_END)) {
+#if !defined(CONFIG_AM33XX) && !defined(CONFIG_TI81XX)
+               if ((omap_hw_init_context() ==
+                                     OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)) {
+                       gd->arch.omap_boot_params.omap_bootmode =
+                       *((u8 *)(rom_params + BOOT_MODE_OFFSET));
+               } else
+#endif
+               {
+                       dev_desc = *((u32 *)(rom_params + DEV_DESC_PTR_OFFSET));
+                       dev_data = *((u32 *)(dev_desc + DEV_DATA_PTR_OFFSET));
+                       gd->arch.omap_boot_params.omap_bootmode =
+                                       *((u32 *)(dev_data + BOOT_MODE_OFFSET));
+               }
+       }
+}
+
+#ifdef CONFIG_SPL_BUILD
 u32 spl_boot_device(void)
 {
-       return (u32) (boot_params.omap_bootdevice);
+       return (u32) (gd->arch.omap_boot_params.omap_bootdevice);
 }
 
 u32 spl_boot_mode(void)
 {
-       return omap_bootmode;
+       return gd->arch.omap_boot_params.omap_bootmode;
 }
 
 void spl_board_init(void)
@@ -73,4 +98,15 @@ int board_mmc_init(bd_t *bis)
        }
        return 0;
 }
+
+void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+{
+       typedef void __noreturn (*image_entry_noargs_t)(u32 *);
+       image_entry_noargs_t image_entry =
+                       (image_entry_noargs_t) spl_image->entry_point;
+
+       debug("image entry point: 0x%X\n", spl_image->entry_point);
+       /* Pass the saved boot_params from rom code */
+       image_entry((u32 *)&gd->arch.omap_boot_params);
+}
 #endif
index 2b955c7..99910cd 100644 (file)
@@ -716,6 +716,7 @@ void prcm_init(void)
                setup_non_essential_dplls();
                enable_non_essential_clocks();
 #endif
+               setup_warmreset_time();
                break;
        default:
                break;
index cdb4439..11e830a 100644 (file)
@@ -1075,6 +1075,11 @@ static void do_sdram_init(u32 base)
                else
                        ddr3_init(base, regs);
        }
+       if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) {
+               set_lpmode_selfrefresh(base);
+               emif_reset_phy(base);
+               ddr3_leveling(base, regs);
+       }
 
        /* Write to the shadow registers */
        emif_update_timings(base, regs);
@@ -1262,10 +1267,10 @@ void sdram_init(void)
        in_sdram = running_from_sdram();
        debug("in_sdram = %d\n", in_sdram);
 
-       if (!(in_sdram || warm_reset())) {
-               if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
+       if (!in_sdram) {
+               if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset())
                        bypass_dpll((*prcm)->cm_clkmode_dpll_core);
-               else
+               else if (sdram_type == EMIF_SDRAM_TYPE_DDR3)
                        writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl);
        }
 
index 70d16a8..0776d5c 100644 (file)
@@ -84,7 +84,7 @@ u32 cortex_rev(void)
        return rev;
 }
 
-void omap_rev_string(void)
+static void omap_rev_string(void)
 {
        u32 omap_rev = omap_revision();
        u32 soc_variant = (omap_rev & 0xF0000000) >> 28;
@@ -101,11 +101,6 @@ void omap_rev_string(void)
 }
 
 #ifdef CONFIG_SPL_BUILD
-static void init_boot_params(void)
-{
-       boot_params_ptr = (u32 *) &boot_params;
-}
-
 void spl_display_print(void)
 {
        omap_rev_string();
@@ -116,6 +111,17 @@ void __weak srcomp_enable(void)
 {
 }
 
+#ifdef CONFIG_ARCH_CPU_INIT
+/*
+ * SOC specific cpu init
+ */
+int arch_cpu_init(void)
+{
+       save_omap_boot_params();
+       return 0;
+}
+#endif /* CONFIG_ARCH_CPU_INIT */
+
 /*
  * Routine: s_init
  * Description: Does early system init of watchdog, muxing,  andclocks
@@ -132,6 +138,14 @@ void __weak srcomp_enable(void)
  */
 void s_init(void)
 {
+       /*
+        * Save the boot parameters passed from romcode.
+        * We cannot delay the saving further than this,
+        * to prevent overwrites.
+        */
+#ifdef CONFIG_SPL_BUILD
+       save_omap_boot_params();
+#endif
        init_omap_revision();
        hw_data_init();
 
@@ -156,7 +170,6 @@ void s_init(void)
 
        /* For regular u-boot sdram_init() is called from dram_init() */
        sdram_init();
-       init_boot_params();
 #endif
 }
 
index 90b3c8a..c489536 100644 (file)
 
 #include <config.h>
 #include <asm/arch/omap.h>
+#include <asm/omap_common.h>
 #include <asm/arch/spl.h>
 #include <linux/linkage.h>
 
 ENTRY(save_boot_params)
-       /*
-        * See if the rom code passed pointer is valid:
-        * It is not valid if it is not in non-secure SRAM
-        * This may happen if you are booting with the help of
-        * debugger
-        */
-       ldr     r2, =NON_SECURE_SRAM_START
-       cmp     r2, r0
-       bgt     1f
-       ldr     r2, =NON_SECURE_SRAM_END
-       cmp     r2, r0
-       blt     1f
-
-       /*
-        * store the boot params passed from rom code or saved
-        * and passed by SPL
-        */
-       cmp     r0, #0
-       beq     1f
-       ldr     r1, =boot_params
+       ldr     r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS
        str     r0, [r1]
-#ifdef CONFIG_SPL_BUILD
-       /* Store the boot device in spl_boot_device */
-       ldrb    r2, [r0, #BOOT_DEVICE_OFFSET]   @ r1 <- value of boot device
-       and     r2, #BOOT_DEVICE_MASK
-       ldr     r3, =boot_params
-       strb    r2, [r3, #BOOT_DEVICE_OFFSET]   @ spl_boot_device <- r1
-
-       /*
-        * boot mode is only valid for device that can be raw or FAT booted.
-        * in other cases it may be fatal to look.  While platforms differ
-        * in the values used for each MMC slot, they are contiguous.
-        */
-       cmp     r2, #MMC_BOOT_DEVICES_START
-       blt     2f
-       cmp     r2, #MMC_BOOT_DEVICES_END
-       bgt     2f
-       /* Store the boot mode (raw/FAT) in omap_bootmode */
-       ldr     r2, [r0, #DEV_DESC_PTR_OFFSET]  @ get the device descriptor ptr
-       ldr     r2, [r2, #DEV_DATA_PTR_OFFSET]  @ get the pDeviceData ptr
-       ldr     r2, [r2, #BOOT_MODE_OFFSET]     @ get the boot mode
-       ldr     r3, =omap_bootmode
-       str     r2, [r3]
-#endif
-2:
-       ldrb    r2, [r0, #CH_FLAGS_OFFSET]
-       ldr     r3, =boot_params
-       strb    r2, [r3, #CH_FLAGS_OFFSET]
-1:
        bx      lr
 ENDPROC(save_boot_params)
 
index 587bb47..57ea9d9 100644 (file)
@@ -39,3 +39,7 @@ u32 __weak warm_reset(void)
 {
        return (readl(PRM_RSTST) & PRM_RSTST_WARM_RESET_MASK);
 }
+
+void __weak setup_warmreset_time(void)
+{
+}
index 53f6063..0ddf35f 100644 (file)
@@ -31,8 +31,8 @@
 #include <asm/utils.h>
 
 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
-u32 *const T_num = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_NUM;
-u32 *const T_den = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_DEN;
+u32 *const T_num = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_NUM;
+u32 *const T_den = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_DEN;
 #endif
 
 #ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
index 04977b4..06a2fc8 100644 (file)
@@ -40,7 +40,7 @@ struct dplls const **dplls_data =
 struct vcores_data const **omap_vcores =
                (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
 struct omap_sys_ctrl_regs const **ctrl =
-       (struct omap_sys_ctrl_regs const **)OMAP4_SRAM_SCRATCH_SYS_CTRL;
+       (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
 
 /*
  * The M & N values in the following tables are created using the
index 2db517b..81f5a48 100644 (file)
 #include <asm/sizes.h>
 #include <asm/emif.h>
 #include <asm/arch/gpio.h>
+#include <asm/omap_common.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-u32 *const omap_si_rev = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV;
+u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
 
 static const struct gpio_bank gpio_bank_44xx[6] = {
        { (void *)OMAP44XX_GPIO1_BASE, METHOD_GPIO_24XX },
index 3f37abd..b4c1319 100644 (file)
@@ -32,8 +32,8 @@
 
 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
-static u32 *const T_num = (u32 *)OMAP5_SRAM_SCRATCH_EMIF_T_NUM;
-static u32 *const T_den = (u32 *)OMAP5_SRAM_SCRATCH_EMIF_T_DEN;
+static u32 *const T_num = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_NUM;
+static u32 *const T_den = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_DEN;
 #endif
 
 #ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
index ced274e..604fa42 100644 (file)
@@ -41,7 +41,7 @@ struct dplls const **dplls_data =
 struct vcores_data const **omap_vcores =
                (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
 struct omap_sys_ctrl_regs const **ctrl =
-       (struct omap_sys_ctrl_regs const **)OMAP5_SRAM_SCRATCH_SYS_CTRL;
+       (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
 
 /* OPP HIGH FREQUENCY for ES2.0 */
 static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
@@ -403,6 +403,7 @@ void enable_basic_uboot_clocks(void)
        };
 
        u32 const clk_modules_hw_auto_essential[] = {
+               (*prcm)->cm_l3init_hsusbtll_clkctrl,
                0
        };
 
@@ -411,7 +412,7 @@ void enable_basic_uboot_clocks(void)
                (*prcm)->cm_l4per_i2c2_clkctrl,
                (*prcm)->cm_l4per_i2c3_clkctrl,
                (*prcm)->cm_l4per_i2c4_clkctrl,
-               (*prcm)->cm_l3init_hsusbtll_clkctrl,
+               (*prcm)->cm_l4per_i2c5_clkctrl,
                (*prcm)->cm_l3init_hsusbhost_clkctrl,
                (*prcm)->cm_l3init_fsusb_clkctrl,
                0
index 2f4b247..e192fea 100644 (file)
 #include <asm/utils.h>
 #include <asm/arch/gpio.h>
 #include <asm/emif.h>
+#include <asm/omap_common.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-u32 *const omap_si_rev = (u32 *)OMAP5_SRAM_SCRATCH_OMAP5_REV;
+u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
 
 static struct gpio_bank gpio_bank_54xx[6] = {
        { (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX },
@@ -363,3 +364,22 @@ u32 warm_reset(void)
 {
        return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
 }
+
+void setup_warmreset_time(void)
+{
+       u32 rst_time, rst_val;
+
+#ifndef CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
+       rst_time = CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC;
+#else
+       rst_time = CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC;
+#endif
+       rst_time = usec_to_32k(rst_time) << RSTTIME1_SHIFT;
+
+       if (rst_time > RSTTIME1_MASK)
+               rst_time = RSTTIME1_MASK;
+
+       rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK;
+       rst_val |= rst_time;
+       writel(rst_val, (*prcm)->prm_rsttime);
+}
index b8a61fe..e9f6a32 100644 (file)
@@ -729,6 +729,7 @@ struct prcm_regs const omap5_es2_prcm = {
        .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07998,
        .prm_rstctrl = 0x4ae07c00,
        .prm_rstst = 0x4ae07c04,
+       .prm_rsttime = 0x4ae07c08,
        .prm_vc_val_bypass = 0x4ae07ca0,
        .prm_vc_cfg_i2c_mode = 0x4ae07cb4,
        .prm_vc_cfg_i2c_clk = 0x4ae07cb8,
@@ -952,6 +953,7 @@ struct prcm_regs const dra7xx_prcm = {
        .cm_wkupaon_scrm_clkctrl                = 0x4ae07890,
        .prm_rstctrl                            = 0x4ae07d00,
        .prm_rstst                              = 0x4ae07d04,
+       .prm_rsttime                            = 0x4ae07d08,
        .prm_vc_val_bypass                      = 0x4ae07da0,
        .prm_vc_cfg_i2c_mode                    = 0x4ae07db4,
        .prm_vc_cfg_i2c_clk                     = 0x4ae07db8,
index e9e57e6..8e9cb19 100644 (file)
@@ -94,10 +94,6 @@ _TEXT_BASE:
 _bss_start_ofs:
        .word __bss_start - _start
 
-.globl _image_copy_end_ofs
-_image_copy_end_ofs:
-       .word __image_copy_end - _start
-
 .globl _bss_end_ofs
 _bss_end_ofs:
        .word __bss_end - _start
@@ -167,80 +163,6 @@ reset:
 
 /*------------------------------------------------------------------------------*/
 
-#ifndef CONFIG_SPL_BUILD
-/*
- * void relocate_code(addr_moni)
- *
- * This function relocates the monitor code.
- */
-ENTRY(relocate_code)
-       mov     r6, r0  /* save addr of destination */
-
-       adr     r0, _start
-       subs    r9, r6, r0              /* r9 <- relocation offset */
-       beq     relocate_done           /* skip relocation */
-       mov     r1, r6                  /* r1 <- scratch for copy_loop */
-       ldr     r3, _image_copy_end_ofs
-       add     r2, r0, r3              /* r2 <- source end address         */
-
-copy_loop:
-       ldmia   r0!, {r10-r11}          /* copy from source address [r0]    */
-       stmia   r1!, {r10-r11}          /* copy to   target address [r1]    */
-       cmp     r0, r2                  /* until source end address [r2]    */
-       blo     copy_loop
-
-       /*
-        * fix .rel.dyn relocations
-        */
-       ldr     r0, _TEXT_BASE          /* r0 <- Text base */
-       ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
-       add     r10, r10, r0            /* r10 <- sym table in FLASH */
-       ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
-       add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
-       ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
-       add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
-fixloop:
-       ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
-       add     r0, r0, r9              /* r0 <- location to fix up in RAM */
-       ldr     r1, [r2, #4]
-       and     r7, r1, #0xff
-       cmp     r7, #23                 /* relative fixup? */
-       beq     fixrel
-       cmp     r7, #2                  /* absolute fixup? */
-       beq     fixabs
-       /* ignore unknown type of fixup */
-       b       fixnext
-fixabs:
-       /* absolute fix: set location to (offset) symbol value */
-       mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
-       add     r1, r10, r1             /* r1 <- address of symbol in table */
- &nb