DCDGEN(4, ESDCTL_BASE_ADDR + REG_ESDMISC, ESDMISC_VAL)
DCDGEN(4, ESDCTL_BASE_ADDR + REG_ESDSCR, 0x00000000)
- /* UART1_RXD */
- DCDGEN(4, IOMUXC_BASE_ADDR + 0x228, 0x00000000)
- DCDGEN(4, IOMUXC_BASE_ADDR + 0x618, 0x000001c1)
- DCDGEN(4, IOMUXC_BASE_ADDR + 0x9e4, 0x00000000)
-
- /* UART1_TXD */
- DCDGEN(4, IOMUXC_BASE_ADDR + 0x22c, 0x00000000)
- DCDGEN(4, IOMUXC_BASE_ADDR + 0x61c, 0x000000c5)
-
- /* UART1_RTS */
- DCDGEN(4, IOMUXC_BASE_ADDR + 0x230, 0x00000000)
- DCDGEN(4, IOMUXC_BASE_ADDR + 0x620, 0x000001c1)
- DCDGEN(4, IOMUXC_BASE_ADDR + 0x9e0, 0x00000000)
-
- /* UART1_CTS */
- DCDGEN(4, IOMUXC_BASE_ADDR + 0x234, 0x00000000)
- DCDGEN(4, IOMUXC_BASE_ADDR + 0x624, 0x000000c5)
-
- /* STK5 board LED */
- DCDGEN(4, IOMUXC_BASE_ADDR + 0x1d0, 0x00000013)
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x508, 0x000020e0) @ EIM_SDBA2
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x50c, 0x000020e1) @ EIM_SDODT1
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x510, 0x000020e1) @ EIM_SDODT0
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x820, 0x00000040) @ (Bit6 PUE) GRP_DDRPKS
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x82c, 0x00000000) @ (Bit[1..2] DSE D[24..31]) GRP_DRAM_B4 DFT: 0x4
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x830, 0x00000000) @ (Bit9 DDR_INPUT A[0..14] CAS CS[0..1] RAS SDCKE[0..1]
+ @ SDWE SDBA[0..1]) GRP_INDDR
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x838, 0x00000080) @ (Bit7 PKE D[0..31]) GRP_PKEDDR
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x83c, 0x00000000) @ (Bit[1..2] DSE A[0..7]) GRP_DDR_A0 DFT: 0x4
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x848, 0x00000000) @ (Bit[1..2] DSE A[8..14] SDBA[0..2]) GRP_DDR_A1
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x84c, 0x00000020) @ (Bit[4..5] PUS A[0..14] CAS RAS SDBA[0..1]) GRP_DDRAPUS
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x85c, 0x00000000) @ (Bit8 HYS D[0..7]) GRP_HYSDDR0
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x864, 0x00000000) @ (Bit8 HYS D[8..15]) GRP_HYSDDR1
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x86c, 0x00000000) @ (Bit8 HYS D[16..23]) GRP_HYSDDR2
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x870, 0x00002000) @ (Bit13 A[0..14] CAS CS[0..1] D[0..31] DQM[0..3] RAS
+ @ SDCKE[0..1] SDCLK SDQS[0..3] SDWE SDBA[0..2]
+ @ SDODT[0..1]) GRP_HVDDR
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x874, 0x00000000) @ (Bit8 HYS D[24..31]) GRP_HYSDDR3
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x878, 0x00000001) @ (Bit0 SRE D[0..7]) GRP_SR_B0
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x87c, 0x00000040) @ (Bit6 PUE A[0..14] CAS RAS SDBA[0..1]) GRP_DDRAPKS
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x880, 0x00000001) @ (Bit0 SRE D[8..15]) GRP_SR_B1
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x884, 0x00000020) @ (Bit[4..5] PUS D[0..31]) GRP_DDRPUS
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x88c, 0x00000001) @ (Bit0 SRE D[16..23]) GRP_SR_B2
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x890, 0x00000080) @ (Bit7 PKE A[0..14] CAS RAS SDBA[0..1]) GRP_PKEADDR
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x89c, 0x00000001) @ (Bit0 SRE D[24..31]) GRP_SR_B4
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x8a0, 0x00000000) @ (Bit9 DDR_INPUT D[0..31] DQM[0..3]) GRP_INMODE1
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x8a4, 0x00000000) @ (Bit[1..2] DSE D[0..7]) GRP_DRAM_B0 DFT: 0x4
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x8ac, 0x00000000) @ (Bit[1..2] DSE D[8..15]) GRP_DRAM_B1 DFT: 0x4
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x8b0, 0x00000001) @ (Bit0 SRE A[0..7]) GRP_SR_A0
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x8b8, 0x00000000) @ (Bit[1..2] DSE D[16..23]) GRP_DRAM_B2 DFT: 0x4
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x8bc, 0x00000001) @ (Bit0 SRE A[8..14] SDBA[0..2]) GRP_SR_A1
+
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x4e4, 0x2000) @ NANDF_WE_B
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x4e8, 0x2000) @ NANDF_RE_B
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x4ec, 0x2000) @ NANDF_ALE
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x4f0, 0x2000) @ NANDF_CLE
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x4f4, 0x2000) @ NANDF_WP_B
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x4f8, 0x2000) @ NANDF_RB0
+
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x518, 0x0084) @ NANDF_CS0
+
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x538, 0x20e0) @ NANDF_RDY_INT
+
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x55c, 0x20a4) @ NANDF_D7
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x560, 0x20a4) @ NANDF_D6
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x564, 0x20a4) @ NANDF_D5
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x568, 0x20a4) @ NANDF_D4
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x56c, 0x20a4) @ NANDF_D3
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x570, 0x20a4) @ NANDF_D2
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x574, 0x20a4) @ NANDF_D1
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x578, 0x20a4) @ NANDF_D0
dcd_end:
.ifgt dcd_end - dcd_start - 720
DCD too large!