/ctags
/etags
-# OneNAND IPL files
-/onenand_ipl/onenand-ipl*
-/onenand_ipl/board/*/onenand*
-/onenand_ipl/board/*/*.S
-
# spl ais files
/spl/*.ais
am3517_crane ARM ARMV7 (AM35x SoC)
-Kyungmin Park <kyungmin.park@samsung.com>
-
- apollon ARM1136EJS
-
Sandeep Paulraj <s-paulraj@ti.com>
davinci_dm355evm ARM926EJS
Andreas Bießmann <andreas.devel@googlemail.com>
grasshopper AT32AP7000
+ atngw100mkii AT32AP7000
Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
endif
LIBS-$(CONFIG_OF_EMBED) += dts/libdts.o
LIBS-y += arch/$(ARCH)/lib/lib$(ARCH).o
-LIBS-y += fs/cramfs/libcramfs.o fs/fat/libfat.o fs/fdos/libfdos.o fs/jffs2/libjffs2.o \
- fs/reiserfs/libreiserfs.o fs/ext2/libext2fs.o fs/yaffs2/libyaffs2.o \
- fs/ubifs/libubifs.o fs/zfs/libzfs.o
+LIBS-y += fs/cramfs/libcramfs.o \
+ fs/ext4/libext4fs.o \
+ fs/fat/libfat.o \
+ fs/fdos/libfdos.o \
+ fs/jffs2/libjffs2.o \
+ fs/reiserfs/libreiserfs.o \
+ fs/ubifs/libubifs.o \
+ fs/yaffs2/libyaffs2.o \
+ fs/zfs/libzfs.o
LIBS-y += net/libnet.o
LIBS-y += disk/libdisk.o
LIBS-y += drivers/bios_emulator/libatibiosemu.o
LIBS-y += drivers/pcmcia/libpcmcia.o
LIBS-y += drivers/power/libpower.o
LIBS-y += drivers/spi/libspi.o
+LIBS-y += drivers/dfu/libdfu.o
ifeq ($(CPU),mpc83xx)
LIBS-y += drivers/qe/libqe.o
LIBS-y += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
ALL-$(CONFIG_NAND_U_BOOT) += $(obj)u-boot-nand.bin
ALL-$(CONFIG_ONENAND_U_BOOT) += $(obj)u-boot-onenand.bin
-ONENAND_BIN ?= $(obj)onenand_ipl/onenand-ipl-2k.bin
ALL-$(CONFIG_SPL) += $(obj)spl/u-boot-spl.bin
ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin
$(SUBDIR_TOOLS) $(OBJS) $(LIBBOARD) $(LIBS) $(LDSCRIPT) $(obj)u-boot.lds
$(GEN_UBOOT)
ifeq ($(CONFIG_KALLSYMS),y)
- smap=`$(call SYSTEM_MAP,u-boot) | \
+ smap=`$(call SYSTEM_MAP,$(obj)u-boot) | \
awk '$$2 ~ /[tTwW]/ {printf $$1 $$3 "\\\\000"}'` ; \
$(CC) $(CFLAGS) -DSYSTEM_MAP="\"$${smap}\"" \
-c common/system_map.c -o $(obj)common/system_map.o
$(obj)u-boot-nand.bin: nand_spl $(obj)u-boot.bin
cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin
-onenand_ipl: $(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk
- $(MAKE) -C onenand_ipl/board/$(BOARDDIR) all
-
-$(obj)u-boot-onenand.bin: onenand_ipl $(obj)u-boot.bin
- cat $(ONENAND_BIN) $(obj)u-boot.bin > $(obj)u-boot-onenand.bin
-
$(obj)spl/u-boot-spl.bin: $(SUBDIR_TOOLS) depend
$(MAKE) -C spl all
@rm -f $(obj)include/generated/asm-offsets.h
@rm -f $(obj)$(CPUDIR)/$(SOC)/asm-offsets.s
@rm -f $(obj)nand_spl/{u-boot.lds,u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map,System.map}
- @rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl.map}
@rm -f $(ONENAND_BIN)
- @rm -f $(obj)onenand_ipl/u-boot.lds
@rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.lds,u-boot-spl.map}
@rm -f $(obj)MLO
@rm -f $(TIMESTAMP_FILE) $(VERSION_FILE)
@rm -fr $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
@rm -fr $(obj)include/generated
@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f
- @[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -name "*" -type l -print | xargs rm -f
@rm -f $(obj)dts/*.tmp
@rm -f $(obj)spl/u-boot-spl{,-pad}.ais
If this variable is defined, an environment variable
named "ver" is created by U-Boot showing the U-Boot
version as printed by the "version" command.
- This variable is readonly.
+ Any change to this variable will be reverted at the
+ next reset.
- Real-Time Clock:
commands like bootm or iminfo. This option is
automatically enabled when you select CONFIG_CMD_DATE .
-- Partition Support:
- CONFIG_MAC_PARTITION and/or CONFIG_DOS_PARTITION
- and/or CONFIG_ISO_PARTITION and/or CONFIG_EFI_PARTITION
+- Partition Labels (disklabels) Supported:
+ Zero or more of the following:
+ CONFIG_MAC_PARTITION Apple's MacOS partition table.
+ CONFIG_DOS_PARTITION MS Dos partition table, traditional on the
+ Intel architecture, USB sticks, etc.
+ CONFIG_ISO_PARTITION ISO partition table, used on CDROM etc.
+ CONFIG_EFI_PARTITION GPT partition table, common when EFI is the
+ bootloader. Note 2TB partition limit; see
+ disk/part_efi.c
+ CONFIG_MTD_PARTITIONS Memory Technology Device partition table.
If IDE or SCSI support is enabled (CONFIG_CMD_IDE or
CONFIG_CMD_SCSI) you must configure support for at
- least one partition type as well.
+ least one non-MTD partition type as well.
- IDE Reset method:
CONFIG_IDE_RESET_ROUTINE - this is defined in several
Disable PCI-Express on systems where it is supported but not
required.
+- CONFIG_PCI_ENUM_ONLY
+ Only scan through and get the devices on the busses.
+ Don't do any setup work, presumably because someone or
+ something has already done it, and we don't need to do it
+ a second time. Useful for platforms that are pre-booted
+ by coreboot or similar.
+
- CONFIG_SYS_SRIO:
Chip has SRIO or not
#define SDHCI_CTRL4_DRIVE_MASK(_x) ((_x) << 16)
#define SDHCI_CTRL4_DRIVE_SHIFT (16)
-int s5p_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks);
+int s5p_sdhci_init(u32 regbase, int index, int bus_width);
static inline unsigned int s5p_mmc_init(int index, int bus_width)
{
unsigned int base = samsung_get_base_mmc() + (0x10000 * index);
- return s5p_sdhci_init(base, 52000000, 400000, index);
+ return s5p_sdhci_init(base, index, bus_width);
}
#endif
#define LAN_RESET_REGISTER (H4_CS1_BASE+0x1c)
#endif /* endif CONFIG_2420H4 */
-#if defined(CONFIG_APOLLON)
-#define APOLLON_CS0_BASE 0x00000000 /* OneNAND */
-#define APOLLON_CS1_BASE 0x08000000 /* ethernet */
-#define APOLLON_CS2_BASE 0x10000000 /* OneNAND */
-#define APOLLON_CS3_BASE 0x18000000 /* NOR */
-
-#define ETH_CONTROL_REG (APOLLON_CS1_BASE + 0x30b)
-#define LAN_RESET_REGISTER (APOLLON_CS1_BASE + 0x1c)
-#endif /* endif CONFIG_APOLLON */
-
/* Common */
#define LOW_LEVEL_SRAM_STACK 0x4020FFFC
#define I2C_BASE1 (OMAP44XX_L4_PER_BASE + 0x70000)
#define I2C_BASE2 (OMAP44XX_L4_PER_BASE + 0x72000)
#define I2C_BASE3 (OMAP44XX_L4_PER_BASE + 0x60000)
+#define I2C_BASE4 (OMAP44XX_L4_PER_BASE + 0x350000)
/* MUSB base */
#define MUSB_BASE (OMAP44XX_L4_CORE_BASE + 0xAB000)
#ifndef _OMAP4_I2C_H_
#define _OMAP4_I2C_H_
-#define I2C_BUS_MAX 3
+#define I2C_BUS_MAX 4
#define I2C_DEFAULT_BASE I2C_BASE1
struct i2c {
--- /dev/null
+/*
+ * PXA25x UDC definitions
+ *
+ * Copyright (C) 2012 Łukasz Dałek <luk0104@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __REGS_USB_H__
+#define __REGS_USB_H__
+
+struct pxa25x_udc_regs {
+ /* UDC Control Register */
+ uint32_t udccr; /* 0x000 */
+ uint32_t reserved1;
+
+ /* UDC Control Function Register */
+ uint32_t udccfr; /* 0x008 */
+ uint32_t reserved2;
+
+ /* UDC Endpoint Control/Status Registers */
+ uint32_t udccs[16]; /* 0x010 - 0x04c */
+
+ /* UDC Interrupt Control/Status Registers */
+ uint32_t uicr0; /* 0x050 */
+ uint32_t uicr1; /* 0x054 */
+ uint32_t usir0; /* 0x058 */
+ uint32_t usir1; /* 0x05c */
+
+ /* UDC Frame Number/Byte Count Registers */
+ uint32_t ufnrh; /* 0x060 */
+ uint32_t ufnrl; /* 0x064 */
+ uint32_t ubcr2; /* 0x068 */
+ uint32_t ubcr4; /* 0x06c */
+ uint32_t ubcr7; /* 0x070 */
+ uint32_t ubcr9; /* 0x074 */
+ uint32_t ubcr12; /* 0x078 */
+ uint32_t ubcr14; /* 0x07c */
+
+ /* UDC Endpoint Data Registers */
+ uint32_t uddr0; /* 0x080 */
+ uint32_t reserved3[7];
+ uint32_t uddr5; /* 0x0a0 */
+ uint32_t reserved4[7];
+ uint32_t uddr10; /* 0x0c0 */
+ uint32_t reserved5[7];
+ uint32_t uddr15; /* 0x0e0 */
+ uint32_t reserved6[7];
+ uint32_t uddr1; /* 0x100 */
+ uint32_t reserved7[31];
+ uint32_t uddr2; /* 0x180 */
+ uint32_t reserved8[31];
+ uint32_t uddr3; /* 0x200 */
+ uint32_t reserved9[127];
+ uint32_t uddr4; /* 0x400 */
+ uint32_t reserved10[127];
+ uint32_t uddr6; /* 0x600 */
+ uint32_t reserved11[31];
+ uint32_t uddr7; /* 0x680 */
+ uint32_t reserved12[31];
+ uint32_t uddr8; /* 0x700 */
+ uint32_t reserved13[127];
+ uint32_t uddr9; /* 0x900 */
+ uint32_t reserved14[127];
+ uint32_t uddr11; /* 0xb00 */
+ uint32_t reserved15[31];
+ uint32_t uddr12; /* 0xb80 */
+ uint32_t reserved16[31];
+ uint32_t uddr13; /* 0xc00 */
+ uint32_t reserved17[127];
+ uint32_t uddr14; /* 0xe00 */
+
+};
+
+#define PXA25X_UDC_BASE 0x40600000
+
+#define UDCCR_UDE (1 << 0)
+#define UDCCR_UDA (1 << 1)
+#define UDCCR_RSM (1 << 2)
+#define UDCCR_RESIR (1 << 3)
+#define UDCCR_SUSIR (1 << 4)
+#define UDCCR_SRM (1 << 5)
+#define UDCCR_RSTIR (1 << 6)
+#define UDCCR_REM (1 << 7)
+
+/* Bulk IN endpoint 1/6/11 */
+#define UDCCS_BI_TSP (1 << 7)
+#define UDCCS_BI_FST (1 << 5)
+#define UDCCS_BI_SST (1 << 4)
+#define UDCCS_BI_TUR (1 << 3)
+#define UDCCS_BI_FTF (1 << 2)
+#define UDCCS_BI_TPC (1 << 1)
+#define UDCCS_BI_TFS (1 << 0)
+
+/* Bulk OUT endpoint 2/7/12 */
+#define UDCCS_BO_RSP (1 << 7)
+#define UDCCS_BO_RNE (1 << 6)
+#define UDCCS_BO_FST (1 << 5)
+#define UDCCS_BO_SST (1 << 4)
+#define UDCCS_BO_DME (1 << 3)
+#define UDCCS_BO_RPC (1 << 1)
+#define UDCCS_BO_RFS (1 << 0)
+
+/* Isochronous OUT endpoint 4/9/14 */
+#define UDCCS_IO_RSP (1 << 7)
+#define UDCCS_IO_RNE (1 << 6)
+#define UDCCS_IO_DME (1 << 3)
+#define UDCCS_IO_ROF (1 << 2)
+#define UDCCS_IO_RPC (1 << 1)
+#define UDCCS_IO_RFS (1 << 0)
+
+/* Control endpoint 0 */
+#define UDCCS0_OPR (1 << 0)
+#define UDCCS0_IPR (1 << 1)
+#define UDCCS0_FTF (1 << 2)
+#define UDCCS0_DRWF (1 << 3)
+#define UDCCS0_SST (1 << 4)
+#define UDCCS0_FST (1 << 5)
+#define UDCCS0_RNE (1 << 6)
+#define UDCCS0_SA (1 << 7)
+
+#define UICR0_IM0 (1 << 0)
+
+#define USIR0_IR0 (1 << 0)
+#define USIR0_IR1 (1 << 1)
+#define USIR0_IR2 (1 << 2)
+#define USIR0_IR3 (1 << 3)
+#define USIR0_IR4 (1 << 4)
+#define USIR0_IR5 (1 << 5)
+#define USIR0_IR6 (1 << 6)
+#define USIR0_IR7 (1 << 7)
+
+#define UDCCFR_AREN (1 << 7) /* ACK response enable (now) */
+#define UDCCFR_ACM (1 << 2) /* ACK control mode (wait for AREN) */
+/*
+ * Intel(R) PXA255 Processor Specification, September 2003 (page 31)
+ * define new "must be one" bits in UDCCFR (see Table 12-13.)
+ */
+#define UDCCFR_MB1 (0xff & ~(UDCCFR_AREN | UDCCFR_ACM))
+
+#define UFNRH_SIR (1 << 7) /* SOF interrupt request */
+#define UFNRH_SIM (1 << 6) /* SOF interrupt mask */
+#define UFNRH_IPE14 (1 << 5) /* ISO packet error, ep14 */
+#define UFNRH_IPE9 (1 << 4) /* ISO packet error, ep9 */
+#define UFNRH_IPE4 (1 << 3) /* ISO packet error, ep4 */
+
+#endif /* __REGS_USB_H__ */
#define SDHCI_CTRL4_DRIVE_MASK(_x) ((_x) << 16)
#define SDHCI_CTRL4_DRIVE_SHIFT (16)
-int s5p_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks);
+int s5p_sdhci_init(u32 regbase, int index, int bus_width);
static inline unsigned int s5p_mmc_init(int index, int bus_width)
{
unsigned int base = samsung_get_base_mmc() + (0x10000 * index);
- return s5p_sdhci_init(base, 52000000, 400000, index);
+ return s5p_sdhci_init(base, index, bus_width);
}
#endif
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
LDFLAGS_u-boot = --gc-sections --relax
-
-LDSCRIPT = $(SRCTREE)/$(CPUDIR)/u-boot.lds
portd_mask |= (1 << 15);/* SPD */
/* REVISIT: Some pins are probably pure outputs */
- portmux_select_peripheral(PORTMUX_PORT_D, portc_mask,
+ portmux_select_peripheral(PORTMUX_PORT_D, portd_mask,
PORTMUX_FUNC_B, PORTMUX_BUSKEEPER);
portmux_select_peripheral(PORTMUX_PORT_C, portc_mask,
PORTMUX_FUNC_B, PORTMUX_BUSKEEPER);
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
#include <command.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);
+ rcm_t *rcm = (rcm_t *) (MMAP_RCM);
udelay(1000);
- rcm->rcr |= RCM_RCR_SOFTRST;
+ setbits_8(&rcm->rcr, RCM_RCR_SOFTRST);
/* we don't return! */
return 0;
int checkcpu(void)
{
- volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
+ ccm_t *ccm = (ccm_t *) MMAP_CCM;
u16 msk;
u16 id = 0;
u8 ver;
puts("CPU: ");
- msk = (ccm->cir >> 6);
- ver = (ccm->cir & 0x003f);
+ msk = (in_be16(&ccm->cir) >> 6);
+ ver = (in_be16(&ccm->cir) & 0x003f);
switch (msk) {
case 0x6c:
id = 52277;
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
+ * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
#include <watchdog.h>
#include <asm/immap.h>
+#include <asm/io.h>
#include <asm/rtc.h>
/*
*/
void cpu_init_f(void)
{
- volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
- volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
+ scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+ pll_t *pll = (pll_t *)MMAP_PLL;
#if !defined(CONFIG_CF_SBF)
/* Workaround, must place before fbcs */
- pll->psr = 0x12;
-
- scm1->mpr = 0x77777777;
- scm1->pacra = 0;
- scm1->pacrb = 0;
- scm1->pacrc = 0;
- scm1->pacrd = 0;
- scm1->pacre = 0;
- scm1->pacrf = 0;
- scm1->pacrg = 0;
- scm1->pacri = 0;
+ out_be32(&pll->psr, 0x12);
+
+ out_be32(&scm1->mpr, 0x77777777);
+ out_be32(&scm1->pacra, 0);
+ out_be32(&scm1->pacrb, 0);
+ out_be32(&scm1->pacrc, 0);
+ out_be32(&scm1->pacrd, 0);
+ out_be32(&scm1->pacre, 0);
+ out_be32(&scm1->pacrf, 0);
+ out_be32(&scm1->pacrg, 0);
+ out_be32(&scm1->pacri, 0);
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
&& defined(CONFIG_SYS_CS0_CTRL))
- fbcs->csar0 = CONFIG_SYS_CS0_BASE;
- fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
- fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
+ out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
+ out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
+ out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
#endif
#endif /* CONFIG_CF_SBF */
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
&& defined(CONFIG_SYS_CS1_CTRL))
- fbcs->csar1 = CONFIG_SYS_CS1_BASE;
- fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
- fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
+ out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
+ out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
+ out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
#endif
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
&& defined(CONFIG_SYS_CS2_CTRL))
- fbcs->csar2 = CONFIG_SYS_CS2_BASE;
- fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
- fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
+ out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
+ out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
+ out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
#endif
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
&& defined(CONFIG_SYS_CS3_CTRL))
- fbcs->csar3 = CONFIG_SYS_CS3_BASE;
- fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
- fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
+ out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
+ out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
+ out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
&& defined(CONFIG_SYS_CS4_CTRL))
- fbcs->csar4 = CONFIG_SYS_CS4_BASE;
- fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
- fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
+ out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
+ out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
+ out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
#endif
#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
&& defined(CONFIG_SYS_CS5_CTRL))
- fbcs->csar5 = CONFIG_SYS_CS5_BASE;
- fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
- fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
+ out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
+ out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
+ out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
#endif
#ifdef CONFIG_FSL_I2C
- gpio->par_i2c = GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA;
+ out_8(&gpio->par_i2c, GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA);
#endif
icache_enable();
int cpu_init_r(void)
{
#ifdef CONFIG_MCFRTC
- volatile rtc_t *rtc = (volatile rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
- volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended;
+ rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
+ rtcex_t *rtcex = (rtcex_t *)&rtc->extended;
- rtcex->gocu = (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xFFFF;
- rtcex->gocl = CONFIG_SYS_RTC_OSCILLATOR & 0xFFFF;
+ out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff);
+ out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff);
#endif
return (0);
void uart_port_conf(int port)
{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
switch (port) {
case 0:
- gpio->par_uart &=
- (GPIO_PAR_UART_U0TXD_UNMASK & GPIO_PAR_UART_U0RXD_UNMASK);
- gpio->par_uart |=
- (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
+ clrbits_be16(&gpio->par_uart,
+ ~(GPIO_PAR_UART_U0TXD_UNMASK & GPIO_PAR_UART_U0RXD_UNMASK));
+ setbits_be16(&gpio->par_uart,
+ GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
break;
case 1:
- gpio->par_uart &=
- (GPIO_PAR_UART_U1TXD_UNMASK & GPIO_PAR_UART_U1RXD_UNMASK);
- gpio->par_uart |=
- (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
+ clrbits_be16(&gpio->par_uart,
+ ~(GPIO_PAR_UART_U1TXD_UNMASK & GPIO_PAR_UART_U1RXD_UNMASK));
+ setbits_be16(&gpio->par_uart,
+ GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
break;
case 2:
- gpio->par_dspi &=
- (GPIO_PAR_DSPI_SIN_UNMASK & GPIO_PAR_DSPI_SOUT_UNMASK);
- gpio->par_dspi =
- (GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD);
+ clrbits_8(&gpio->par_dspi,
+ ~(GPIO_PAR_DSPI_SIN_UNMASK & GPIO_PAR_DSPI_SOUT_UNMASK));
+ out_8(&gpio->par_dspi,
+ GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD);
break;
}
}
#ifdef CONFIG_CF_DSPI
void cfspi_port_conf(void)
{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- gpio->par_dspi =
- GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
- GPIO_PAR_DSPI_SCK_SCK;
+ out_8(&gpio->par_dspi,
+ GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
+ GPIO_PAR_DSPI_SCK_SCK);
}
int cfspi_claim_bus(uint bus, uint cs)
{
- volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- if ((dspi->sr & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
+ if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
return -1;
/* Clear FIFO and resume transfer */
- dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF);
+ clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
switch (cs) {
case 0:
- gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_UNMASK;
- gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0;
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_UNMASK);
+ setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
break;
case 2:
- gpio->par_timer &= GPIO_PAR_TIMER_T2IN_UNMASK;
- gpio->par_timer |= GPIO_PAR_TIMER_T2IN_DSPIPCS2;
+ clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
+ setbits_8(&gpio->par_timer, GPIO_PAR_TIMER_T2IN_DSPIPCS2);
break;
}
void cfspi_release_bus(uint bus, uint cs)
{
- volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF); /* Clear FIFO */
+ /* Clear FIFO */
+ clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
switch (cs) {
case 0:
- gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
break;
case 2:
- gpio->par_timer &= GPIO_PAR_TIMER_T2IN_UNMASK;
+ clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
break;
}
}
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
/* CPU specific interrupt routine */
#include <common.h>
#include <asm/immap.h>
+#include <asm/io.h>
int interrupt_init(void)
{
- volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+ int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
/* Make sure all interrupts are disabled */
- intp->imrh0 |= 0xFFFFFFFF;
- intp->imrl0 |= 0xFFFFFFFF;
+ setbits_be32(&intp->imrh0, 0xffffffff);
+ setbits_be32(&intp->imrl0, 0xffffffff);
enable_interrupts();
return 0;
#if defined(CONFIG_MCFTMR)
void dtimer_intr_setup(void)
{
- volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+ int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
- intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
- intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK;
+ out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
+ clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK);
}
#endif
/*
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
#include <asm/processor.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
void clock_enter_limp(int lpdiv)
{
- volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
+ ccm_t *ccm = (ccm_t *)MMAP_CCM;
int i, j;
/* Check bounds of divider */
for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
/* Apply the divider to the system clock */
- ccm->cdr = (ccm->cdr & 0xF0FF) | CCM_CDR_LPDIV(i);
+ clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
/* Enable Limp Mode */
- ccm->misccr |= CCM_MISCCR_LIMP;
+ setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
}
/*
*/
void clock_exit_limp(void)
{
- volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
- volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
+ ccm_t *ccm = (ccm_t *)MMAP_CCM;
+ pll_t *pll = (pll_t *)MMAP_PLL;
/* Exit Limp mode */
- ccm->misccr &= ~CCM_MISCCR_LIMP;
+ clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
/* Wait for the PLL to lock */
- while (!(pll->psr & PLL_PSR_LOCK)) ;
+ while (!(in_be32(&pll->psr) & PLL_PSR_LOCK))
+ ;
}
/*
int get_clocks(void)
{
- volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
- volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
+ ccm_t *ccm = (ccm_t *)MMAP_CCM;
+ pll_t *pll = (pll_t *)MMAP_PLL;
int vco, temp, pcrvalue, pfdr;
u8 bootmode;
- pcrvalue = pll->pcr & 0xFF0F0FFF;
+ pcrvalue = in_be32(&pll->pcr) & 0xFF0F0FFF;
pfdr = pcrvalue >> 24;
if (pfdr == 0x1E)
if (bootmode == 0) {
/* Normal mode */
- vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
+ vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
/* Default value */
- pcrvalue = (pll->pcr & 0x00FFFFFF);
+ pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF);
pcrvalue |= 0x1E << 24;
- pll->pcr = pcrvalue;
+ out_be32(&pll->pcr, pcrvalue);
vco =
- ((pll->pcr & 0xFF000000) >> 24) *
+ ((in_be32(&pll->pcr) & 0xFF000000) >> 24) *
CONFIG_SYS_INPUT_CLKSRC;
}
gd->vco_clk = vco; /* Vco clock */
} else if (bootmode == 3) {
/* serial mode */
- vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
+ vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
gd->vco_clk = vco; /* Vco clock */
}
- if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
+ if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
/* Limp mode */
} else {
gd->inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
- temp = (pll->pcr & PLL_PCR_OUTDIV1_MASK) + 1;
+ temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
gd->cpu_clk = vco / temp; /* cpu clock */
- temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
+ temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
gd->flb_clk = vco / temp; /* flexbus clock */
gd->bus_clk = gd->flb_clk;
}
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
#include <netdev.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
+ ccm_t *ccm = (ccm_t *) MMAP_CCM;
- ccm->rcr = CCM_RCR_SOFTRST;
+ out_8(&ccm->rcr, CCM_RCR_SOFTRST);
/* we don't return! */
return 0;
-};
+}
int checkcpu(void)
{
- volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
+ ccm_t *ccm = (ccm_t *) MMAP_CCM;
u16 msk;
u16 id = 0;
u8 ver;
puts("CPU: ");
- msk = (ccm->cir >> 6);
- ver = (ccm->cir & 0x003f);
+ msk = (in_be16(&ccm->cir) >> 6);
+ ver = (in_be16(&ccm->cir) & 0x003f);
switch (msk) {
case 0x31:
id = 5235;
/* Called by macro WATCHDOG_RESET */
void watchdog_reset(void)
{
- volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+ wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
- wdp->sr = 0x5555; /* Count register */
+ /* Count register */
+ out_be16(&wdp->sr, 0x5555);
asm("nop");
- wdp->sr = 0xAAAA; /* Count register */
+ out_be16(&wdp->sr, 0xaaaa);
}
int watchdog_disable(void)
{
- volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+ wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
/* UserManual, once the wdog is disabled, wdog cannot be re-enabled */
- wdp->cr |= WTM_WCR_HALTED; /* halted watchdog timer */
+ /* halted watchdog timer */
+ setbits_be16(&wdp->cr, WTM_WCR_HALTED);
puts("WATCHDOG:disabled\n");
return (0);
int watchdog_init(void)
{
- volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+ wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
u32 wdog_module = 0;
/* set timeout and enable watchdog */
wdog_module = ((CONFIG_SYS_CLK / CONFIG_SYS_HZ) * CONFIG_WATCHDOG_TIMEOUT);
wdog_module |= (wdog_module / 8192);
- wdp->mr = wdog_module;
+ out_be16(&wdp->mr, wdog_module);
- wdp->cr = WTM_WCR_EN;
+ out_be16(&wdp->cr, WTM_WCR_EN);
puts("WATCHDOG:enabled\n");
return (0);
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * (C) Copyright 2007 Freescale Semiconductor, Inc.
+ * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
#include <common.h>
#include <watchdog.h>
#include <asm/immap.h>
+#include <asm/io.h>
#if defined(CONFIG_CMD_NET)
#include <config.h>
*/
void cpu_init_f(void)
{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
- volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG;
- volatile scm_t *scm = (scm_t *) MMAP_SCM;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+ wdog_t *wdog = (wdog_t *) MMAP_WDOG;
+ scm_t *scm = (scm_t *) MMAP_SCM;
/* watchdog is enabled by default - disable the watchdog */
#ifndef CONFIG_WATCHDOG
- wdog->cr = 0;
+ out_be16(&wdog->cr, 0);
#endif
- scm->rambar = (CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
+ out_be32(&scm->rambar, CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
/* Port configuration */
- gpio->par_cs = 0;
+ out_8(&gpio->par_cs, 0);
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
- fbcs->csar0 = CONFIG_SYS_CS0_BASE;
- fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
- fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
+ out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
+ out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
+ out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
#endif
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
- gpio->par_cs |= GPIO_PAR_CS_CS1;
- fbcs->csar1 = CONFIG_SYS_CS1_BASE;
- fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
- fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
+ setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS1);
+ out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
+ out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
+ out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
#endif
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
- gpio->par_cs |= GPIO_PAR_CS_CS2;
- fbcs->csar2 = CONFIG_SYS_CS2_BASE;
- fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
- fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
+ setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS2);
+ out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
+ out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
+ out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
#endif
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
- gpio->par_cs |= GPIO_PAR_CS_CS3;
- fbcs->csar3 = CONFIG_SYS_CS3_BASE;
- fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
- fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
+ setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS3);
+ out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
+ out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
+ out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
- gpio->par_cs |= GPIO_PAR_CS_CS4;
- fbcs->csar4 = CONFIG_SYS_CS4_BASE;
- fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
- fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
+ setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS4);
+ out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
+ out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
+ out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
#endif
#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
- gpio->par_cs |= GPIO_PAR_CS_CS5;
- fbcs->csar5 = CONFIG_SYS_CS5_BASE;
- fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
- fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
+ setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS5);
+ out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
+ out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
+ out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
#endif
#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && defined(CONFIG_SYS_CS6_CTRL))
- gpio->par_cs |= GPIO_PAR_CS_CS6;
- fbcs->csar6 = CONFIG_SYS_CS6_BASE;
- fbcs->cscr6 = CONFIG_SYS_CS6_CTRL;
- fbcs->csmr6 = CONFIG_SYS_CS6_MASK;
+ setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS6);
+ out_be32(&fbcs->csar6, CONFIG_SYS_CS6_BASE);
+ out_be32(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL);
+ out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK);
#endif
#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && defined(CONFIG_SYS_CS7_CTRL))
- gpio->par_cs |= GPIO_PAR_CS_CS7;
- fbcs->csar7 = CONFIG_SYS_CS7_BASE;
- fbcs->cscr7 = CONFIG_SYS_CS7_CTRL;
- fbcs->csmr7 = CONFIG_SYS_CS7_MASK;
+ setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS7);
+ out_be32(&fbcs->csar7, CONFIG_SYS_CS7_BASE);
+ out_be32(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL);
+ out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK);
#endif
#ifdef CONFIG_FSL_I2C
void uart_port_conf(int port)
{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
switch (port) {
case 0:
- gpio->par_uart &= ~(GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
- gpio->par_uart |= (GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
+ clrbits_be16(&gpio->par_uart,
+ GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
+ setbits_be16(&gpio->par_uart,
+ GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
break;
case 1:
- gpio->par_uart &=
- ~(GPIO_PAR_UART_U1RXD_MASK | GPIO_PAR_UART_U1TXD_MASK);
- gpio->par_uart |=
- (GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD);
+ clrbits_be16(&gpio->par_uart,
+ GPIO_PAR_UART_U1RXD_MASK | GPIO_PAR_UART_U1TXD_MASK);
+ setbits_be16(&gpio->par_uart,
+ GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD);
break;
case 2:
#ifdef CONFIG_SYS_UART2_PRI_GPIO
- gpio->par_uart &= ~(GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
- gpio->par_uart |= (GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
+ clrbits_be16(&gpio->par_uart,
+ GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
+ setbits_be16(&gpio->par_uart,
+ GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
#elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
- gpio->feci2c &=
- ~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
- gpio->feci2c |=
- (GPIO_PAR_FECI2C_EMDC_U2TXD | GPIO_PAR_FECI2C_EMDIO_U2RXD);
+ clrbits_8(&gpio->par_feci2c,
+ GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
+ setbits_8(&gpio->par_feci2c,
+ GPIO_PAR_FECI2C_EMDC_U2TXD | GPIO_PAR_FECI2C_EMDIO_U2RXD);
#endif
break;
}
#if defined(CONFIG_CMD_NET)
int fecpin_setclear(struct eth_device *dev, int setclear)
{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
if (setclear) {
- gpio->par_feci2c |=
- (GPIO_PAR_FECI2C_EMDC_FECEMDC |
- GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
+ setbits_8(&gpio->par_feci2c,
+ GPIO_PAR_FECI2C_EMDC_FECEMDC |
+ GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
} else {
- gpio->par_feci2c &=
- ~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
+ clrbits_8(&gpio->par_feci2c,
+ GPIO_PAR_FECI2C_EMDC_MASK |
+ GPIO_PAR_FECI2C_EMDIO_MASK);
}
return 0;
/*
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
/* CPU specific interrupt routine */
#include <common.h>
#include <asm/immap.h>
+#include <asm/io.h>
int interrupt_init(void)
{
- volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+ int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
/* Make sure all interrupts are disabled */
- intp->imrl0 |= 0x1;
+ setbits_be32(&intp->imrl0, 0x1);
enable_interrupts();
return 0;
#if defined(CONFIG_MCFTMR)
void dtimer_intr_setup(void)
{
- volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+ int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
- intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
- intp->imrl0 &= ~INTC_IPRL_INT0;
- intp->imrl0 &= ~CONFIG_SYS_TMRINTR_MASK;
+ out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
+ clrbits_be32(&intp->imrl0, INTC_IPRL_INT0);
+ clrbits_be32(&intp->imrl0, CONFIG_SYS_TMRINTR_MASK);
}
#endif
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
#include <asm/processor.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
/*
*/
int get_clocks(void)
{
- volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
+ pll_t *pll = (pll_t *)(MMAP_PLL);
- pll->syncr = PLL_SYNCR_MFD(1);
+ out_be32(&pll->syncr, PLL_SYNCR_MFD(1));
- while (!(pll->synsr & PLL_SYNSR_LOCK));
+ while (!(in_be32(&pll->synsr) & PLL_SYNSR_LOCK))
+ ;
gd->bus_clk = CONFIG_SYS_CLK;
gd->cpu_clk = (gd->bus_clk * 2);
* MCF5275 additions
* Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
#include <watchdog.h>
#include <command.h>
#include <asm/immap.h>
+#include <asm/io.h>
#include <netdev.h>
#include "cpu.h"
#ifdef CONFIG_M5208
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
+ rcm_t *rcm = (rcm_t *)(MMAP_RCM);
udelay(1000);
- rcm->rcr = RCM_RCR_SOFTRST;
+ out_8(&rcm->rcr, RCM_RCR_SOFTRST);
/* we don't return! */
return 0;
/* Called by macro WATCHDOG_RESET */
void watchdog_reset(void)
{
- volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
- wdt->sr = 0x5555;
- wdt->sr = 0xAAAA;
+ wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
+
+ out_be16(&wdt->sr, 0x5555);
+ out_be16(&wdt->sr, 0xaaaa);
}
int watchdog_disable(void)
{
- volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+ wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
- wdt->sr = 0x5555; /* reset watchdog counter */
- wdt->sr = 0xAAAA;
- wdt->cr = 0; /* disable watchdog timer */
+ /* reset watchdog counter */
+ out_be16(&wdt->sr, 0x5555);
+ out_be16(&wdt->sr, 0xaaaa);
+ /* disable watchdog timer */
+ out_be16(&wdt->cr, 0);
puts("WATCHDOG:disabled\n");
return (0);
int watchdog_init(void)
{
- volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+ wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
- wdt->cr = 0; /* disable watchdog */
+ /* disable watchdog */
+ out_be16(&wdt->cr, 0);
/* set timeout and enable watchdog */
- wdt->mr =
- ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
- wdt->sr = 0x5555; /* reset watchdog counter */
- wdt->sr = 0xAAAA;
+ out_be16(&wdt->mr,
+ (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
+
+ /* reset watchdog counter */
+ out_be16(&wdt->sr, 0x5555);
+ out_be16(&wdt->sr, 0xaaaa);
puts("WATCHDOG:enabled\n");
return (0);
#ifdef CONFIG_M5272
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+ wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
- wdp->wdog_wrrr = 0;
+ out_be16(&wdp->wdog_wrrr, 0);
udelay(1000);
/* enable watchdog, set timeout to 0 and wait */
- wdp->wdog_wrrr = 1;
+ out_be16(&wdp->wdog_wrrr, 1);
while (1) ;
/* we don't return! */
int checkcpu(void)
{
- volatile sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
+ sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
uchar msk;
char *suf;
puts("CPU: ");
- msk = (sysctrl->sc_dir > 28) & 0xf;
+ msk = (in_be32(&sysctrl->sc_dir) > 28) & 0xf;
switch (msk) {
case 0x2:
suf = "1K75N";
/* Called by macro WATCHDOG_RESET */
void watchdog_reset(void)
{
- volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
- wdt->wdog_wcr = 0;
+ wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
+
+ out_be16(&wdt->wdog_wcr, 0);
}
int watchdog_disable(void)
{
- volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+ wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
- wdt->wdog_wcr = 0; /* reset watchdog counter */
- wdt->wdog_wirr = 0; /* disable watchdog interrupt */
- wdt->wdog_wrrr = 0; /* disable watchdog timer */
+ /* reset watchdog counter */
+ out_be16(&wdt->wdog_wcr, 0);
+ /* disable watchdog interrupt */
+ out_be16(&wdt->wdog_wirr, 0);
+ /* disable watchdog timer */
+ out_be16(&wdt->wdog_wrrr, 0);
puts("WATCHDOG:disabled\n");
return (0);
int watchdog_init(void)
{
- volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+ wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
- wdt->wdog_wirr = 0; /* disable watchdog interrupt */
+ /* disable watchdog interrupt */
+ out_be16(&wdt->wdog_wirr, 0);
/* set timeout and enable watchdog */
- wdt->wdog_wrrr =
- ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
- wdt->wdog_wcr = 0; /* reset watchdog counter */
+ out_be16(&wdt->wdog_wrrr,
+ (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
+
+ /* reset watchdog counter */
+ out_be16(&wdt->wdog_wcr, 0);
puts("WATCHDOG:enabled\n");
return (0);
#ifdef CONFIG_M5275
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
+ rcm_t *rcm = (rcm_t *)(MMAP_RCM);
udelay(1000);
- rcm->rcr = RCM_RCR_SOFTRST;
+ out_8(&rcm->rcr, RCM_RCR_SOFTRST);
/* we don't return! */
return 0;
/* Called by macro WATCHDOG_RESET */
void watchdog_reset(void)
{
- volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
- wdt->wsr = 0x5555;
- wdt->wsr = 0xAAAA;
+ wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
+
+ out_be16(&wdt->wsr, 0x5555);
+ out_be16(&wdt->wsr, 0xaaaa);
}
int watchdog_disable(void)
{
- volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+ wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
- wdt->wsr = 0x5555; /* reset watchdog counter */
- wdt->wsr = 0xAAAA;
- wdt->wcr = 0; /* disable watchdog timer */
+ /* reset watchdog counter */
+ out_be16(&wdt->wsr, 0x5555);
+ out_be16(&wdt->wsr, 0xaaaa);
+
+ /* disable watchdog timer */
+ out_be16(&wdt->wcr, 0);
puts("WATCHDOG:disabled\n");
return (0);
int watchdog_init(void)
{
- volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+ wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
- wdt->wcr = 0; /* disable watchdog */
+ /* disable watchdog */
+ out_be16(&wdt->wcr, 0);
/* set timeout and enable watchdog */
- wdt->wmr =
- ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
- wdt->wsr = 0x5555; /* reset watchdog counter */
- wdt->wsr = 0xAAAA;
+ out_be16(&wdt->wmr,
+ (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
+
+ /* reset watchdog counter */
+ out_be16(&wdt->wsr, 0x5555);
+ out_be16(&wdt->wsr, 0xaaaa);
puts("WATCHDOG:enabled\n");
return (0);
* (c) Copyright 2010
* Arcturus Networks Inc. <www.arcturusnetworks.com>
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
* Hayden Fraser (Hayden.Fraser@freescale.com)
*
#include <common.h>
#include <watchdog.h>
#include <asm/immap.h>
+#include <asm/io.h>
#if defined(CONFIG_CMD_NET)
#include <config.h>
/* Only 5272 Flexbus chipselect is different from the rest */
void init_fbcs(void)
{
- volatile fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
+ fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
&& defined(CONFIG_SYS_CS0_CTRL))
- fbcs->csar0 = CONFIG_SYS_CS0_BASE;
- fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
- fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
+ out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
+ out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
+ out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
#else
#warning "Chip Select 0 are not initialized/used"
#endif
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
&& defined(CONFIG_SYS_CS1_CTRL))
- fbcs->csar1 = CONFIG_SYS_CS1_BASE;
- fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
- fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
+ out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
+ out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
+ out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
#endif
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
&& defined(CONFIG_SYS_CS2_CTRL))
- fbcs->csar2 = CONFIG_SYS_CS2_BASE;
- fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
- fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
+ out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
+ out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
+ out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
#endif
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
&& defined(CONFIG_SYS_CS3_CTRL))
- fbcs->csar3 = CONFIG_SYS_CS3_BASE;
- fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
- fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
+ out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
+ out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
+ out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
&& defined(CONFIG_SYS_CS4_CTRL))
- fbcs->csar4 = CONFIG_SYS_CS4_BASE;
- fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
- fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
+ out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
+ out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
+ out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
#endif
#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
&& defined(CONFIG_SYS_CS5_CTRL))
- fbcs->csar5 = CONFIG_SYS_CS5_BASE;
- fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
- fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
+ out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
+ out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
+ out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
#endif
#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \
&& defined(CONFIG_SYS_CS6_CTRL))
- fbcs->csar6 = CONFIG_SYS_CS6_BASE;
- fbcs->cscr6 = CONFIG_SYS_CS6_CTRL;
- fbcs->csmr6 = CONFIG_SYS_CS6_MASK;
+ out_be32(&fbcs->csar6, CONFIG_SYS_CS6_BASE);
+ out_be32(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL);
+ out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK);
#endif
#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \
&& defined(CONFIG_SYS_CS7_CTRL))
- fbcs->csar7 = CONFIG_SYS_CS7_BASE;
- fbcs->cscr7 = CONFIG_SYS_CS7_CTRL;
- fbcs->csmr7 = CONFIG_SYS_CS7_MASK;
+ out_be32(&fbcs->csar7, CONFIG_SYS_CS7_BASE);
+ out_be32(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL);
+ out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK);
#endif
}
#endif
#if defined(CONFIG_M5208)
void cpu_init_f(void)
{
- volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+ scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
#ifndef CONFIG_WATCHDOG
- volatile wdog_t *wdg = (wdog_t *) MMAP_WDOG;
+ wdog_t *wdg = (wdog_t *) MMAP_WDOG;
/* Disable the watchdog if we aren't using it */
- wdg->cr = 0;
+ out_be16(&wdg->cr, 0);
#endif
- scm1->mpr = 0x77777777;
- scm1->pacra = 0;
- scm1->pacrb = 0;
- scm1->pacrc = 0;
- scm1->pacrd = 0;
- scm1->pacre = 0;
- scm1->pacrf = 0;
+ out_be32(&scm1->mpr, 0x77777777);
+ out_be32(&scm1->pacra, 0);
+ out_be32(&scm1->pacrb, 0);
+ out_be32(&scm1->pacrc, 0);
+ out_be32(&scm1->pacrd, 0);
+ out_be32(&scm1->pacre, 0);
+ out_be32(&scm1->pacrf, 0);
/* FlexBus Chipselect */
init_fbcs();
void uart_port_conf(int port)
{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
switch (port) {
case 0:
- gpio->par_uart &= GPIO_PAR_UART0_UNMASK;
- gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
+ clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK);
+ setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
break;
case 1:
- gpio->par_uart &= GPIO_PAR_UART0_UNMASK;
- gpio->par_uart |= (GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD);
+ clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK);
+ setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD);
break;
case 2:
#ifdef CONFIG_SYS_UART2_PRI_GPIO
- gpio->par_timer &=
- (GPIO_PAR_TMR_TIN0_UNMASK | GPIO_PAR_TMR_TIN1_UNMASK);
- gpio->par_timer |=
- (GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD);
+ clrbits_8(&gpio->par_timer,
+ ~(GPIO_PAR_TMR_TIN0_UNMASK | GPIO_PAR_TMR_TIN1_UNMASK));
+ setbits_8(&gpio->par_timer,
+ GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD);
#endif
#ifdef CONFIG_SYS_UART2_ALT1_GPIO
- gpio->par_feci2c &=
- (GPIO_PAR_FECI2C_MDC_UNMASK | GPIO_PAR_FECI2C_MDIO_UNMASK);
- gpio->par_feci2c |=
- (GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD);
+ clrbits_8(&gpio->par_feci2c,
+ ~(GPIO_PAR_FECI2C_MDC_UNMASK | GPIO_PAR_FECI2C_MDIO_UNMASK));
+ setbits_8(&gpio->par_feci2c,
+ GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD);
#endif
#ifdef CONFIG_SYS_UART2_ALT1_GPIO
- gpio->par_feci2c &=
- (GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK);
- gpio->par_feci2c |=
- (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
+ clrbits_8(&gpio->par_feci2c,
+ ~(GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK));
+ setbits_8(&gpio->par_feci2c,
+ GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
#endif
break;
}
#if defined(CONFIG_CMD_NET)
int fecpin_setclear(struct eth_device *dev, int setclear)
{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
if (setclear) {
- gpio->par_fec |=
- GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
- gpio->par_feci2c |=
- GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO;
+ setbits_8(&gpio->par_fec,
+ GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
+ setbits_8(&gpio->par_feci2c,
+ GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO);
} else {
- gpio->par_fec &=
- (GPIO_PAR_FEC_7W_UNMASK & GPIO_PAR_FEC_MII_UNMASK);
- gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII_UNMASK;
+ clrbits_8(&gpio->par_fec,
+ ~(GPIO_PAR_FEC_7W_UNMASK & GPIO_PAR_FEC_MII_UNMASK));
+ clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII_UNMASK);
}
return 0;
}
void uart_port_conf(int port)
{
- volatile u32 *par = (u32 *) MMAP_PAR;
+ u32 *par = (u32 *) MMAP_PAR;
/* Setup Ports: */
switch (port) {
case 1:
- *par &= 0xFFE7FFFF;
- *par |= 0x00180000;
+ clrbits_be32(par, 0x00180000);
+ setbits_be32(par, 0x00180000);
break;
case 2:
- *par &= 0xFFFFFFFC;
- *par &= 0x00000003;
+ clrbits_be32(par, 0x00000003);
+ clrbits_be32(par, 0xFFFFFFFC);
break;
}
}
return 0;
}
#endif /* CONFIG_CMD_NET */
-#endif
+
+#if defined(CONFIG_CF_QSPI)
+
+/* Configure PIOs for SIN, SOUT, and SCK */
+void cfspi_port_conf(void)
+{
+ mbar_writeByte(MCF_GPIO_PAR_QSPI,
+ MCF_GPIO_PAR_QSPI_SIN_SIN |
+ MCF_GPIO_PAR_QSPI_SOUT_SOUT |
+ MCF_GPIO_PAR_QSPI_SCK_SCK);
+}
+#endif /* CONFIG_CF_QSPI */
+
+#endif /* CONFIG_M5271 */
#if defined(CONFIG_M5272)
/*
* already initialized.
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
- volatile sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR);
- volatile gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
- volatile csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
+ sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR);
+ gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
+ csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
- sysctrl->sc_scr = CONFIG_SYS_SCR;
- sysctrl->sc_spr = CONFIG_SYS_SPR;
+ out_be16(&sysctrl->sc_scr, CONFIG_SYS_SCR);
+ out_be16(&sysctrl->sc_spr, CONFIG_SYS_SPR);
/* Setup Ports: */
- gpio->gpio_pacnt = CONFIG_SYS_PACNT;
- gpio->gpio_paddr = CONFIG_SYS_PADDR;
- gpio->gpio_padat = CONFIG_SYS_PADAT;
- gpio->gpio_pbcnt = CONFIG_SYS_PBCNT;
- gpio->gpio_pbddr = CONFIG_SYS_PBDDR;
- gpio->gpio_pbdat = CONFIG_SYS_PBDAT;
- gpio->gpio_pdcnt = CONFIG_SYS_PDCNT;
+ out_be32(&gpio->gpio_pacnt, CONFIG_SYS_PACNT);
+ out_be16(&gpio->gpio_paddr, CONFIG_SYS_PADDR);
+ out_be16(&gpio->gpio_padat, CONFIG_SYS_PADAT);
+ out_be32(&gpio->gpio_pbcnt, CONFIG_SYS_PBCNT);
+ out_be16(&gpio->gpio_pbddr, CONFIG_SYS_PBDDR);
+ out_be16(&gpio->gpio_pbdat, CONFIG_SYS_PBDAT);
+ out_be32(&gpio->gpio_pdcnt, CONFIG_SYS_PDCNT);
/* Memory Controller: */
- csctrl->cs_br0 = CONFIG_SYS_BR0_PRELIM;
- csctrl->cs_or0 = CONFIG_SYS_OR0_PRELIM;
+ out_be32(&csctrl->cs_br0, CONFIG_SYS_BR0_PRELIM);
+ out_be32(&csctrl->cs_or0, CONFIG_SYS_OR0_PRELIM);
#if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
- csctrl->cs_br1 = CONFIG_SYS_BR1_PRELIM;
- csctrl->cs_or1 = CONFIG_SYS_OR1_PRELIM;
+ out_be32(&csctrl->cs_br1, CONFIG_SYS_BR1_PRELIM);
+ out_be32(&csctrl->cs_or1, CONFIG_SYS_OR1_PRELIM);
#endif
#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
- csctrl->cs_br2 = CONFIG_SYS_BR2_PRELIM;
- csctrl->cs_or2 = CONFIG_SYS_OR2_PRELIM;
+ out_be32(&csctrl->cs_br2, CONFIG_SYS_BR2_PRELIM);
+ out_be32(&csctrl->cs_or2, CONFIG_SYS_OR2_PRELIM);
#endif
#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
- csctrl->cs_br3 = CONFIG_SYS_BR3_PRELIM;
- csctrl->cs_or3 = CONFIG_SYS_OR3_PRELIM;
+ out_be32(&csctrl->cs_br3, CONFIG_SYS_BR3_PRELIM);
+ out_be32(&csctrl->cs_or3, CONFIG_SYS_OR3_PRELIM);
#endif
#if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
- csctrl->cs_br4 = CONFIG_SYS_BR4_PRELIM;
- csctrl->cs_or4 = CONFIG_SYS_OR4_PRELIM;
+ out_be32(&csctrl->cs_br4, CONFIG_SYS_BR4_PRELIM);
+ out_be32(&csctrl->cs_or4, CONFIG_SYS_OR4_PRELIM);
#endif
#if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
- csctrl->cs_br5 = CONFIG_SYS_BR5_PRELIM;
- csctrl->cs_or5 = CONFIG_SYS_OR5_PRELIM;
+ out_be32(&csctrl->cs_br5, CONFIG_SYS_BR5_PRELIM);
+ out_be32(&csctrl->cs_or5, CONFIG_SYS_OR5_PRELIM);
#endif
#if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
- csctrl->cs_br6 = CONFIG_SYS_BR6_PRELIM;
- csctrl->cs_or6 = CONFIG_SYS_OR6_PRELIM;
+ out_be32(&csctrl->cs_br6, CONFIG_SYS_BR6_PRELIM);
+ out_be32(&csctrl->cs_or6, CONFIG_SYS_OR6_PRELIM);
#endif
#if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
- csctrl->cs_br7 = CONFIG_SYS_BR7_PRELIM;
- csctrl->cs_or7 = CONFIG_SYS_OR7_PRELIM;
+ out_be32(&csctrl->cs_br7, CONFIG_SYS_BR7_PRELIM);
+ out_be32(&csctrl->cs_or7, CONFIG_SYS_OR7_PRELIM);
#endif
#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
void uart_port_conf(int port)
{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
switch (port) {
case 0:
- gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
- gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
+ clrbits_be32(&gpio->gpio_pbcnt,
+ GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
+ setbits_be32(&gpio->gpio_pbcnt,
+ GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
break;
case 1:
- gpio->gpio_pdcnt &= ~(GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK);
- gpio->gpio_pdcnt |= (GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD);
+ clrbits_be32(&gpio->gpio_pdcnt,
+ GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK);
+ setbits_be32(&gpio->gpio_pdcnt,
+ GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD);
break;
}
}
#if defined(CONFIG_CMD_NET)
int fecpin_setclear(struct eth_device *dev, int setclear)
{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
if (setclear) {
- gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER |
- GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 |
- GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 |
- GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3;
+ setbits_be32(&gpio->gpio_pbcnt,
+ GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER |
+ GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 |
+ GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 |
+ GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3);
} else {
}
return 0;
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
- volatile wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG);
- volatile gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO);
+ wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG);
+ gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO);
/* Kill watchdog so we can initialize the PLL */
- wdog_reg->wcr = 0;
+ out_be16(&wdog_reg->wcr, 0);
/* FlexBus Chipselect */
init_fbcs();
void uart_port_conf(int port)
{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
switch (port) {
case 0:
- gpio->par_uart &= ~UART0_ENABLE_MASK;
- gpio->par_uart |= UART0_ENABLE_MASK;
+ clrbits_be16(&gpio->par_uart, UART0_ENABLE_MASK);
+ setbits_be16(&gpio->par_uart, UART0_ENABLE_MASK);
break;
case 1:
- gpio->par_uart &= ~UART1_ENABLE_MASK;
- gpio->par_uart |= UART1_ENABLE_MASK;
+ clrbits_be16(&gpio->par_uart, UART1_ENABLE_MASK);
+ setbits_be16(&gpio->par_uart, UART1_ENABLE_MASK);
break;
case 2:
- gpio->par_uart &= ~UART2_ENABLE_MASK;
- gpio->par_uart |= UART2_ENABLE_MASK;
+ clrbits_be16(&gpio->par_uart, UART2_ENABLE_MASK);
+ setbits_be16(&gpio->par_uart, UART2_ENABLE_MASK);
break;
}
}
int fecpin_setclear(struct eth_device *dev, int setclear)
{
struct fec_info_s *info = (struct fec_info_s *) dev->priv;
- volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
+ gpio_t *gpio = (gpio_t *)MMAP_GPIO;
if (setclear) {
/* Enable Ethernet pins */
if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
- gpio->par_feci2c |= 0x0F00;
- gpio->par_fec0hl |= 0xC0;
+ setbits_be16(&gpio->par_feci2c, 0x0f00);
+ setbits_8(&gpio->par_fec0hl, 0xc0);
} else {
- gpio->par_feci2c |= 0x00A0;
- gpio->par_fec1hl |= 0xC0;
+ setbits_be16(&gpio->par_feci2c, 0x00a0);
+ setbits_8(&gpio->par_fec1hl, 0xc0);
}
} else {
if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
- gpio->par_feci2c &= ~0x0F00;
- gpio->par_fec0hl &= ~0xC0;
+ clrbits_be16(&gpio->par_feci2c, 0x0f00);
+ clrbits_8(&gpio->par_fec0hl, 0xc0);
} else {
- gpio->par_feci2c &= ~0x00A0;
- gpio->par_fec1hl &= ~0xC0;
+ clrbits_be16(&gpio->par_feci2c, 0x00a0);
+ clrbits_8(&gpio->par_fec1hl, 0xc0);
}
}
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
#include <watchdog.h>
#include <asm/processor.h>
#include <asm/immap.h>
+#include <asm/io.h>
#ifdef CONFIG_M5272
int interrupt_init(void)
{
- volatile intctrl_t *intp = (intctrl_t *) (MMAP_INTC);
+ intctrl_t *intp = (intctrl_t *) (MMAP_INTC);
/* disable all external interrupts */
- intp->int_icr1 = 0x88888888;
- intp->int_icr2 = 0x88888888;
- intp->int_icr3 = 0x88888888;
- intp->int_icr4 = 0x88888888;
- intp->int_pitr = 0x00000000;
+ out_be32(&intp->int_icr1, 0x88888888);
+ out_be32(&intp->int_icr2, 0x88888888);
+ out_be32(&intp->int_icr3, 0x88888888);
+ out_be32(&intp->int_icr4, 0x88888888);
+ out_be32(&intp->int_pitr, 0x00000000);
+
/* initialize vector register */
- intp->int_pivr = 0x40;
+ out_8(&intp->int_pivr, 0x40);
enable_interrupts();
#if defined(CONFIG_MCFTMR)
void dtimer_intr_setup(void)
{
- volatile intctrl_t *intp = (intctrl_t *) (CONFIG_SYS_INTR_BASE);
+ intctrl_t *intp = (intctrl_t *) (CONFIG_SYS_INTR_BASE);
- intp->int_icr1 &= ~INT_ICR1_TMR3MASK;
- intp->int_icr1 |= CONFIG_SYS_TMRINTR_PRI;
+ clrbits_be32(&intp->int_icr1, INT_ICR1_TMR3MASK);
+ setbits_be32(&intp->int_icr1, CONFIG_SYS_TMRINTR_PRI);
}
#endif /* CONFIG_MCFTMR */
#endif /* CONFIG_M5272 */
defined(CONFIG_M5271) || defined(CONFIG_M5275)
int interrupt_init(void)
{
- volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+ int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
/* Make sure all interrupts are disabled */
#if defined(CONFIG_M5208)
- intp->imrl0 = 0xFFFFFFFF;
- intp->imrh0 = 0xFFFFFFFF;
+ out_be32(&intp->imrl0, 0xffffffff);
+ out_be32(&intp->imrh0, 0xffffffff);
#else
- intp->imrl0 |= 0x1;
+ setbits_be32(&intp->imrl0, 0x1);
#endif
enable_interrupts();
#if defined(CONFIG_MCFTMR)
void dtimer_intr_setup(void)
{
- volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+ int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
- intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
- intp->imrl0 &= 0xFFFFFFFE;
- intp->imrl0 &= ~CONFIG_SYS_TMRINTR_MASK;
+ out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
+ clrbits_be32(&intp->imrl0, 0x00000001);
+ clrbits_be32(&intp->imrl0, CONFIG_SYS_TMRINTR_MASK);
}
#endif /* CONFIG_MCFTMR */
#endif /* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */
* (C) Copyright 2003
* Josef Baumgartner <josef.baumgartner@telex.de>
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* Hayden Fraser (Hayden.Fraser@freescale.com)
*
* See file CREDITS for list of people who contributed to this
#include <common.h>
#include <asm/processor.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
int get_clocks (void)
{
#if defined(CONFIG_M5208)
- volatile pll_t *pll = (pll_t *) MMAP_PLL;
+ pll_t *pll = (pll_t *) MMAP_PLL;
- pll->odr = CONFIG_SYS_PLL_ODR;
- pll->fdr = CONFIG_SYS_PLL_FDR;
+ out_8(&pll->odr, CONFIG_SYS_PLL_ODR);
+ out_8(&pll->fdr, CONFIG_SYS_PLL_FDR);
#endif
#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
#endif /* CONFIG_M5249 || CONFIG_M5253 */
#if defined(CONFIG_M5275)
- volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
+ pll_t *pll = (pll_t *)(MMAP_PLL);
/* Setup PLL */
- pll->syncr = 0x01080000;
- while (!(pll->synsr & FMPLL_SYNSR_LOCK))
+ out_be32(&pll->syncr, 0x01080000);
+ while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK))
;
- pll->syncr = 0x01000000;
- while (!(pll->synsr & FMPLL_SYNSR_LOCK))
+ out_be32(&pll->syncr, 0x01000000);
+ while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK))
;
#endif
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
#include <netdev.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);
+ rcm_t *rcm = (rcm_t *) (MMAP_RCM);
udelay(1000);
- rcm->rcr |= RCM_RCR_SOFTRST;
+ setbits_8(&rcm->rcr, RCM_RCR_SOFTRST);
/* we don't return! */
return 0;
int checkcpu(void)
{
- volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
+ ccm_t *ccm = (ccm_t *) MMAP_CCM;
u16 msk;
u16 id = 0;
u8 ver;
puts("CPU: ");
- msk = (ccm->cir >> 6);
- ver = (ccm->cir & 0x003f);
+ msk = (in_be16(&ccm->cir) >> 6);
+ ver = (in_be16(&ccm->cir) & 0x003f);
switch (msk) {
#ifdef CONFIG_MCF5301x
case 0x78:
/* Called by macro WATCHDOG_RESET */
void watchdog_reset(void)
{
- volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+ wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
- wdp->sr = 0x5555; /* Count register */
- wdp->sr = 0xAAAA; /* Count register */
+ /* Count register */
+ out_be16(&wdp->sr, 0x5555);
+ out_be16(&wdp->sr, 0xaaaa);
}
int watchdog_disable(void)
{
- volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+ wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
/* UserManual, once the wdog is disabled, wdog cannot be re-enabled */
- wdp->cr |= WTM_WCR_HALTED; /* halted watchdog timer */
+ /* halted watchdog timer */
+ setbits_be16(&wdp->cr, WTM_WCR_HALTED);
puts("WATCHDOG:disabled\n");
return (0);
int watchdog_init(void)
{
- volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+ wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
u32 wdog_module = 0;
/* set timeout and enable watchdog */
wdog_module = ((CONFIG_SYS_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT);
#ifdef CONFIG_M5329
- wdp->mr = (wdog_module / 8192);
+ out_be16(&wdp->mr, wdog_module / 8192);
#else
- wdp->mr = (wdog_module / 4096);
+ out_be16(&wdp->mr, wdog_module / 4096);
#endif
- wdp->cr = WTM_WCR_EN;
+ out_be16(&wdp->cr, WTM_WCR_EN);
puts("WATCHDOG:enabled\n");
return (0);
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * (C) Copyright 2004-2008 Freescale Semiconductor, Inc.
+ * (C) Copyright 2004-2008, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
#include <common.h>
#include <watchdog.h>
#include <asm/immap.h>
+#include <asm/io.h>
#if defined(CONFIG_CMD_NET)
#include <config.h>
#ifdef CONFIG_MCF5301x
void cpu_init_f(void)
{
- volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
-
- /* watchdog is enabled by default - disable the watchdog */
-#ifndef CONFIG_WATCHDOG
- /*wdog->cr = 0; */
-#endif
-
- scm1->mpr = 0x77777777;
- scm1->pacra = 0;
- scm1->pacrb = 0;
- scm1->pacrc = 0;
- scm1->pacrd = 0;
- scm1->pacre = 0;
- scm1->pacrf = 0;
- scm1->pacrg = 0;
+ scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+
+ out_be32(&scm1->mpr, 0x77777777);
+ out_be32(&scm1->pacra, 0);
+ out_be32(&scm1->pacrb, 0);
+ out_be32(&scm1->pacrc, 0);
+ out_be32(&scm1->pacrd, 0);
+ out_be32(&scm1->pacre, 0);
+ out_be32(&scm1->pacrf, 0);
+ out_be32(&scm1->pacrg, 0);
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
&& defined(CONFIG_SYS_CS0_CTRL))
- gpio->par_cs |= GPIO_PAR_CS0_CS0;
- fbcs->csar0 = CONFIG_SYS_CS0_BASE;
- fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
- fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
+ setbits_8(&gpio->par_cs, GPIO_PAR_CS0_CS0);
+ out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
+ out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
+ out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
#endif
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
&& defined(CONFIG_SYS_CS1_CTRL))
- gpio->par_cs |= GPIO_PAR_CS1_CS1;
- fbcs->csar1 = CONFIG_SYS_CS1_BASE;
- fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
- fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
+ setbits_8(&gpio->par_cs, GPIO_PAR_CS1_CS1);
+ out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
+ out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
+ out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
#endif
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
&& defined(CONFIG_SYS_CS2_CTRL))
- fbcs->csar2 = CONFIG_SYS_CS2_BASE;
- fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
- fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
+ out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
+ out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
+ out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
#endif
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
&& defined(CONFIG_SYS_CS3_CTRL))
- fbcs->csar3 = CONFIG_SYS_CS3_BASE;
- fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
- fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
+ out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
+ out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
+ out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
&& defined(CONFIG_SYS_CS4_CTRL))
- gpio->par_cs |= GPIO_PAR_CS4;
- fbcs->csar4 = CONFIG_SYS_CS4_BASE;
- fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
- fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
+ setbits_8(&gpio->par_cs, GPIO_PAR_CS4);
+ out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
+ out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
+ out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
#endif
#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
&& defined(CONFIG_SYS_CS5_CTRL))
- gpio->par_cs |= GPIO_PAR_CS5;
- fbcs->csar5 = CONFIG_SYS_CS5_BASE;
- fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
- fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
+ setbits_8(&gpio->par_cs, GPIO_PAR_CS5);
+ out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
+ out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
+ out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
#endif
#ifdef CONFIG_FSL_I2C
- gpio->par_feci2c = GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL;
+ out_8(&gpio->par_feci2c,
+ GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL);
#endif
icache_enable();
int cpu_init_r(void)
{
#ifdef CONFIG_MCFFEC
- volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
+ ccm_t *ccm = (ccm_t *) MMAP_CCM;
#endif
#ifdef CONFIG_MCFRTC
- volatile rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE);
- volatile rtcex_t *rtcex = (rtcex_t *) & rtc->extended;
+ rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE);
+ rtcex_t *rtcex = (rtcex_t *) &rtc->extended;
- rtcex->gocu = CONFIG_SYS_RTC_CNT;
- rtcex->gocl = CONFIG_SYS_RTC_SETUP;
+ out_be32(&rtcex->gocu, CONFIG_SYS_RTC_CNT);
+ out_be32(&rtcex->gocl, CONFIG_SYS_RTC_SETUP);
#endif
#ifdef CONFIG_MCFFEC
if (CONFIG_SYS_FEC0_MIIBASE != CONFIG_SYS_FEC1_MIIBASE)
- ccm->misccr |= CCM_MISCCR_FECM;
+ setbits_be16(&ccm->misccr, CCM_MISCCR_FECM);
else
- ccm->misccr &= ~CCM_MISCCR_FECM;
+ clrbits_be16(&ccm->misccr, CCM_MISCCR_FECM);
#endif
return (0);
void uart_port_conf(int port)
{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
switch (port) {
case 0:
- gpio->par_uart &= ~(GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
- gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
+ clrbits_8(&gpio->par_uart,
+ GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
+ setbits_8(&gpio->par_uart,
+ GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
break;
case 1:
#ifdef CONFIG_SYS_UART1_ALT1_GPIO
- gpio->par_simp1h &=
- ~(GPIO_PAR_SIMP1H_DATA1_UNMASK |
- GPIO_PAR_SIMP1H_VEN1_UNMASK);
- gpio->par_simp1h |=
- (GPIO_PAR_SIMP1H_DATA1_U1TXD | GPIO_PAR_SIMP1H_VEN1_U1RXD);
+ clrbits_8(&gpio->par_simp1h,
+ GPIO_PAR_SIMP1H_DATA1_UNMASK |
+ GPIO_PAR_SIMP1H_VEN1_UNMASK);
+ setbits_8(&gpio->par_simp1h,
+ GPIO_PAR_SIMP1H_DATA1_U1TXD |
+ GPIO_PAR_SIMP1H_VEN1_U1RXD);
#elif defined(CONFIG_SYS_UART1_ALT2_GPIO)
- gpio->par_ssih &=
- ~(GPIO_PAR_SSIH_RXD_UNMASK | GPIO_PAR_SSIH_TXD_UNMASK);
- gpio->par_ssih |=
- (GPIO_PAR_SSIH_RXD_U1RXD | GPIO_PAR_SSIH_TXD_U1TXD);
+ clrbits_8(&gpio->par_ssih,
+ GPIO_PAR_SSIH_RXD_UNMASK |
+ GPIO_PAR_SSIH_TXD_UNMASK);
+ setbits_8(&gpio->par_ssih,
+ GPIO_PAR_SSIH_RXD_U1RXD |
+ GPIO_PAR_SSIH_TXD_U1TXD);
#endif
break;
case 2:
#ifdef CONFIG_SYS_UART2_PRI_GPIO
- gpio->par_uart |= (GPIO_PAR_UART_U2TXD | GPIO_PAR_UART_U2RXD);
+ setbits_8(&gpio->par_uart,
+ GPIO_PAR_UART_U2TXD |
+ GPIO_PAR_UART_U2RXD);
#elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
- gpio->par_dspih &=
- ~(GPIO_PAR_DSPIH_SIN_UNMASK | GPIO_PAR_DSPIH_SOUT_UNMASK);
- gpio->par_dspih |=
- (GPIO_PAR_DSPIH_SIN_U2RXD | GPIO_PAR_DSPIH_SOUT_U2TXD);
+ clrbits_8(&gpio->par_dspih,
+ GPIO_PAR_DSPIH_SIN_UNMASK |
+ GPIO_PAR_DSPIH_SOUT_UNMASK);
+ setbits_8(&gpio->par_dspih,
+ GPIO_PAR_DSPIH_SIN_U2RXD |
+ GPIO_PAR_DSPIH_SOUT_U2TXD);
#elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
- gpio->par_feci2c &=
- ~(GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK);
- gpio->par_feci2c |=
- (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
+ clrbits_8(&gpio->par_feci2c,
+ GPIO_PAR_FECI2C_SDA_UNMASK |
+ GPIO_PAR_FECI2C_SCL_UNMASK);
+ setbits_8(&gpio->par_feci2c,
+ GPIO_PAR_FECI2C_SDA_U2TXD |
+ GPIO_PAR_FECI2C_SCL_U2RXD);
#endif
break;
}
#if defined(CONFIG_CMD_NET)
int fecpin_setclear(struct eth_device *dev, int setclear)
{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
struct fec_info_s *info = (struct fec_info_s *)dev->priv;
if (setclear) {
if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
- gpio->par_fec |=
- GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC;
- gpio->par_feci2c |=
- GPIO_PAR_FECI2C_MDC0 | GPIO_PAR_FECI2C_MDIO0;
+ setbits_8(&gpio->par_fec,
+ GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC);
+ setbits_8(&gpio->par_feci2c,
+ GPIO_PAR_FECI2C_MDC0 | GPIO_PAR_FECI2C_MDIO0);
} else {
- gpio->par_fec |=
- GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC;
- gpio->par_feci2c |=
- GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1;
+ setbits_8(&gpio->par_fec,
+ GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC);
+ setbits_8(&gpio->par_feci2c,
+ GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1);
}
} else {
if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
- gpio->par_fec &=
- ~(GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC);
- gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII0_UNMASK;
+ clrbits_8(&gpio->par_fec,
+ GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC);
+ clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII0_UNMASK);
} else {
- gpio->par_fec &=
- ~(GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC);
- gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII1_UNMASK;
+ clrbits_8(&gpio->par_fec,
+ GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC);
+ clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII1_UNMASK);
}
}
return 0;
#ifdef CONFIG_MCF532x
void cpu_init_f(void)
{
- volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
- volatile scm2_t *scm2 = (scm2_t *) MMAP_SCM2;
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
- volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG;
+ scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+ scm2_t *scm2 = (scm2_t *) MMAP_SCM2;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+ wdog_t *wdog = (wdog_t *) MMAP_WDOG;
/* watchdog is enabled by default - disable the watchdog */
#ifndef CONFIG_WATCHDOG
- wdog->cr = 0;
+ out_be16(&wdog->cr, 0);
#endif
- scm1->mpr0 = 0x77777777;
- scm2->pacra = 0;
- scm2->pacrb = 0;
- scm2->pacrc = 0;
- scm2->pacrd = 0;
- scm2->pacre = 0;
- scm2->pacrf = 0;
- scm2->pacrg = 0;
- scm1->pacrh = 0;
+ out_be32(&scm1->mpr0, 0x77777777);
+ out_be32(&scm2->pacra, 0);
+ out_be32(&scm2->pacrb, 0);
+ out_be32(&scm2->pacrc, 0);
+ out_be32(&scm2->pacrd, 0);
+ out_be32(&scm2->pacre, 0);
+ out_be32(&scm2->pacrf, 0);
+ out_be32(&scm2->pacrg, 0);
+ out_be32(&scm1->pacrh, 0);
/* Port configuration */
- gpio->par_cs = 0;
+ out_8(&gpio->par_cs, 0);
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
&& defined(CONFIG_SYS_CS0_CTRL))
- fbcs->csar0 = CONFIG_SYS_CS0_BASE;
- fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
- fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
+ out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
+ out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
+ out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
#endif
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
&& defined(CONFIG_SYS_CS1_CTRL))
/* Latch chipselect */
- gpio->par_cs |= GPIO_PAR_CS1;
- fbcs->csar1 = CONFIG_SYS_CS1_BASE;
- fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
- fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
+ setbits_8(&gpio->par_cs, GPIO_PAR_CS1);
+ out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
+ out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
+ out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
#endif
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
&& defined(CONFIG_SYS_CS2_CTRL))
- gpio->par_cs |= GPIO_PAR_CS2;
- fbcs->csar2 = CONFIG_SYS_CS2_BASE;
- fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
- fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
+ setbits_8(&gpio->par_cs, GPIO_PAR_CS2);
+ out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
+ out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
+ out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
#endif
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
&& defined(CONFIG_SYS_CS3_CTRL))
- gpio->par_cs |= GPIO_PAR_CS3;
- fbcs->csar3 = CONFIG_SYS_CS3_BASE;
- fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
- fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
+ setbits_8(&gpio->par_cs, GPIO_PAR_CS3);
+ out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
+ out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
+ out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
&& defined(CONFIG_SYS_CS4_CTRL))
- gpio->par_cs |= GPIO_PAR_CS4;
- fbcs->csar4 = CONFIG_SYS_CS4_BASE;
- fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
- fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
+ setbits_8(&gpio->par_cs, GPIO_PAR_CS4);
+ out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
+ out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
+ out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
#endif
#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
&& defined(CONFIG_SYS_CS5_CTRL))
- gpio->par_cs |= GPIO_PAR_CS5;
- fbcs->csar5 = CONFIG_SYS_CS5_BASE;
- fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
- fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
+ setbits_8(&gpio->par_cs, GPIO_PAR_CS5);
+ out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
+ out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
+ out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
#endif
#ifdef CONFIG_FSL_I2C
- gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA;
+ out_8(&gpio->par_feci2c,
+ GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
#endif
icache_enable();
void uart_port_conf(int port)
{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
switch (port) {
case 0:
- gpio->par_uart &= ~(GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
- gpio->par_uart |= (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
+ clrbits_be16(&gpio->par_uart,
+ GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
+ setbits_be16(&gpio->par_uart,
+ GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
break;
case 1:
- gpio->par_uart &=
- ~(GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
- gpio->par_uart |=
- (GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
+ clrbits_be16(&gpio->par_uart,
+ GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
+ setbits_be16(&gpio->par_uart,
+ GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
break;
case 2:
#ifdef CONFIG_SYS_UART2_ALT1_GPIO
- gpio->par_timer &= 0x0F;
- gpio->par_timer |= (GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2);
+ clrbits_8(&gpio->par_timer, 0xf0);
+ setbits_8(&gpio->par_timer,
+ GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2);
#elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
- gpio->par_feci2c &= 0xFF00;
- gpio->par_feci2c |= (GPIO_PAR_FECI2C_SCL_UTXD2 | GPIO_PAR_FECI2C_SDA_URXD2);
+ clrbits_8(&gpio->par_feci2c, 0x00ff);
+ setbits_8(&gpio->par_feci2c,
+ GPIO_PAR_FECI2C_SCL_UTXD2 | GPIO_PAR_FECI2C_SDA_URXD2);
#elif defined(CONFIG_SYS_UART2_ALT3_GPIO)
- gpio->par_ssi &= 0xF0FF;
- gpio->par_ssi |= (GPIO_PAR_SSI_RXD(2) | GPIO_PAR_SSI_TXD(2));
+ clrbits_be16(&gpio->par_ssi, 0x0f00);
+ setbits_be16(&gpio->par_ssi,
+ GPIO_PAR_SSI_RXD(2) | GPIO_PAR_SSI_TXD(2));
#endif
break;
}
#if defined(CONFIG_CMD_NET)
int fecpin_setclear(struct eth_device *dev, int setclear)
{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
if (setclear) {
- gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
- gpio->par_feci2c |=
- GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO;
+ setbits_8(&gpio->par_fec,
+ GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
+ setbits_8(&gpio->par_feci2c,
+ GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
} else {
- gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
- gpio->par_feci2c &=
- ~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
+ clrbits_8(&gpio->par_fec,
+ GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
+ clrbits_8(&gpio->par_feci2c,
+ GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
}
return 0;
}
/*
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
/* CPU specific interrupt routine */
#include <common.h>
#include <asm/immap.h>
+#include <asm/io.h>
int interrupt_init(void)
{
- volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+ int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
/* Make sure all interrupts are disabled */
- intp->imrh0 |= 0xFFFFFFFF;
- intp->imrl0 |= 0xFFFFFFFF;
+ setbits_be32(&intp->imrh0, 0xffffffff);
+ setbits_be32(&intp->imrl0, 0xffffffff);
enable_interrupts();
return 0;
#if defined(CONFIG_MCFTMR)
void dtimer_intr_setup(void)
{
- volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+ int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
- intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
- intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK;
+ out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
+ clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK);
}
#endif
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
#include <asm/processor.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
/* Get the value of the current system clock */
int get_sys_clock(void)
{
- volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
- volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
+ ccm_t *ccm = (ccm_t *)(MMAP_CCM);
+ pll_t *pll = (pll_t *)(MMAP_PLL);
int divider;
/* Test to see if device is in LIMP mode */
- if (ccm->misccr & CCM_MISCCR_LIMP) {
- divider = ccm->cdr & CCM_CDR_LPDIV(0xF);
+ if (in_be16(&ccm->misccr) & CCM_MISCCR_LIMP) {
+ divider = in_be16(&ccm->cdr) & CCM_CDR_LPDIV(0xF);
#ifdef CONFIG_MCF5301x
return (FREF / (3 * (1 << divider)));
#endif
#endif
} else {
#ifdef CONFIG_MCF5301x
- u32 pfdr = (pll->pcr & 0x3F) + 1;
- u32 refdiv = (1 << ((pll->pcr & PLL_PCR_REFDIV(7)) >> 8));
- u32 busdiv = ((pll->pdr & 0x00F0) >> 4) + 1;
+ u32 pfdr = (in_be32(&pll->pcr) & 0x3F) + 1;
+ u32 refdiv = (1 << ((in_be32(&pll->pcr) & PLL_PCR_REFDIV(7)) >> 8));
+ u32 busdiv = ((in_be32(&pll->pdr) & 0x00F0) >> 4) + 1;
return (((FREF * pfdr) / refdiv) / busdiv);
#endif
#ifdef CONFIG_MCF532x
- return ((FREF * pll->pfdr) / (BUSDIV * 4));
+ return (FREF * in_8(&pll->pfdr)) / (BUSDIV * 4);
#endif
}
}
*/
int clock_limp(int div)
{
- volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
+ ccm_t *ccm = (ccm_t *)(MMAP_CCM);
u32 temp;
/* Check bounds of divider */
div = MAX_LPD;
/* Save of the current value of the SSIDIV so we don't overwrite the value */
- temp = (ccm->cdr & CCM_CDR_SSIDIV(0xFF));
+ temp = (in_be16(&ccm->cdr) & CCM_CDR_SSIDIV(0xFF));
/* Apply the divider to the system clock */
- ccm->cdr = (CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp));
+ out_be16(&ccm->cdr, CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp));
- ccm->misccr |= CCM_MISCCR_LIMP;
+ setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
return (FREF / (3 * (1 << div)));
}
/* Exit low power LIMP mode */
int clock_exit_limp(void)
{
- volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
+ ccm_t *ccm = (ccm_t *)(MMAP_CCM);
int fout;
/* Exit LIMP mode */
- ccm->misccr &= (~CCM_MISCCR_LIMP);
+ clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
/* Wait for PLL to lock */
- while (!(ccm->misccr & CCM_MISCCR_PLL_LOCK)) ;
+ while (!(in_be16(&ccm->misccr) & CCM_MISCCR_PLL_LOCK))
+ ;
fout = get_sys_clock();
int clock_pll(int fsys, int flags)
{
#ifdef CONFIG_MCF532x
- volatile u32 *sdram_workaround = (volatile u32 *)(MMAP_SDRAM + 0x80);
+ u32 *sdram_workaround = (u32 *)(MMAP_SDRAM + 0x80);
#endif
- volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
- volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
+ sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
+ pll_t *pll = (pll_t *)(MMAP_PLL);
int fref, temp, fout, mfd;
u32 i;
if (fsys == 0) {
/* Return current PLL output */
#ifdef CONFIG_MCF5301x
- u32 busdiv = ((pll->pdr >> 4) & 0x0F) + 1;
- mfd = (pll->pcr & 0x3F) + 1;
+ u32 busdiv = ((in_be32(&pll->pdr) >> 4) & 0x0F) + 1;
+ mfd = (in_be32(&pll->pcr) & 0x3F) + 1;
return (fref * mfd) / busdiv;
#endif
#ifdef CONFIG_MCF532x
- mfd = pll->pfdr;
+ mfd = in_8(&pll->pfdr);
return (fref * mfd / (BUSDIV * 4));
#endif
* If it has then the SDRAM needs to be put into self refresh
* mode before reprogramming the PLL.
*/
- if (sdram->ctrl & SDRAMC_SDCR_REF)
- sdram->ctrl &= ~SDRAMC_SDCR_CKE;
+ if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF)
+ clrbits_be32(&sdram->ctrl, SDRAMC_SDCR_CKE);
/*
* Initialize the PLL to generate the new system clock frequency.
clock_limp(DEFAULT_LPD);
#ifdef CONFIG_MCF5301x
- pll->pdr =
- PLL_PDR_OUTDIV1((BUSDIV / 3) - 1) |
- PLL_PDR_OUTDIV2(BUSDIV - 1) |
- PLL_PDR_OUTDIV3((BUSDIV / 2) - 1) |
- PLL_PDR_OUTDIV4(USBDIV - 1);
-
- pll->pcr &= PLL_PCR_FBDIV_UNMASK;
- pll->pcr |= PLL_PCR_FBDIV(mfd - 1);
+ out_be32(&pll->pdr,
+ PLL_PDR_OUTDIV1((BUSDIV / 3) - 1) |
+ PLL_PDR_OUTDIV2(BUSDIV - 1) |
+ PLL_PDR_OUTDIV3((BUSDIV / 2) - 1) |
+ PLL_PDR_OUTDIV4(USBDIV - 1));
+
+ clrbits_be32(&pll->pcr, ~PLL_PCR_FBDIV_UNMASK);
+ setbits_be32(&pll->pcr, PLL_PCR_FBDIV(mfd - 1));
#endif
#ifdef CONFIG_MCF532x
/* Reprogram PLL for desired fsys */
- pll->podr = (PLL_PODR_CPUDIV(BUSDIV / 3) | PLL_PODR_BUSDIV(BUSDIV));
+ out_8(&pll->podr,
+ PLL_PODR_CPUDIV(BUSDIV / 3) | PLL_PODR_BUSDIV(BUSDIV));
- pll->pfdr = mfd;
+ out_8(&pll->pfdr, mfd);
#endif
/* Exit LIMP mode */
clock_exit_limp();
/* Return the SDRAM to normal operation if it is in use. */
- if (sdram->ctrl & SDRAMC_SDCR_REF)
- sdram->ctrl |= SDRAMC_SDCR_CKE;
+ if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF)
+ setbits_be32(&sdram->ctrl, SDRAMC_SDCR_CKE);
#ifdef CONFIG_MCF532x
/*
* software workaround for SDRAM opeartion after exiting LIMP
* mode errata
*/
- *sdram_workaround = CONFIG_SYS_SDRAM_BASE;
+ out_be32(sdram_workaround, CONFIG_SYS_SDRAM_BASE);
#endif
/* wait for DQS logic to relock */
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
#include <netdev.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);
+ rcm_t *rcm = (rcm_t *) (MMAP_RCM);
udelay(1000);
- rcm->rcr |= RCM_RCR_SOFTRST;
+ setbits_8(&rcm->rcr, RCM_RCR_SOFTRST);
/* we don't return! */
return 0;
int checkcpu(void)
{
- volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
+ ccm_t *ccm = (ccm_t *) MMAP_CCM;
u16 msk;
u16 id = 0;
u8 ver;
puts("CPU: ");
- msk = (ccm->cir >> 6);
- ver = (ccm->cir & 0x003f);
+ msk = (in_be16(&ccm->cir) >> 6);
+ ver = (in_be16(&ccm->cir) & 0x003f);
switch (msk) {
case 0x48:
id = 54455;
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
+ * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
#include <asm/immap.h>
#include <asm/processor.h>
#include <asm/rtc.h>
+#include <asm/io.h>
#if defined(CONFIG_CMD_NET)
#include <config.h>
*/
void cpu_init_f(void)
{
- volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
-
- scm1->mpr = 0x77777777;
- scm1->pacra = 0;
- scm1->pacrb = 0;
- scm1->pacrc = 0;
- scm1->pacrd = 0;
- scm1->pacre = 0;
- scm1->pacrf = 0;
- scm1->pacrg = 0;
+ scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+
+ out_be32(&scm1->mpr, 0x77777777);
+ out_be32(&scm1->pacra, 0);
+ out_be32(&scm1->pacrb, 0);
+ out_be32(&scm1->pacrc, 0);
+ out_be32(&scm1->pacrd, 0);
+ out_be32(&scm1->pacre, 0);
+ out_be32(&scm1->pacrf, 0);
+ out_be32(&scm1->pacrg, 0);
/* FlexBus */
- gpio->par_be =
- GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 | GPIO_PAR_BE_BE1_BE1 |
- GPIO_PAR_BE_BE0_BE0;
- gpio->par_fbctl =
- GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA | GPIO_PAR_FBCTL_RW_RW |
- GPIO_PAR_FBCTL_TS_TS;
+ out_8(&gpio->par_be,
+ GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
+ GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
+ out_8(&gpio->par_fbctl,
+ GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
+ GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
#if !defined(CONFIG_CF_SBF)
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
- fbcs->csar0 = CONFIG_SYS_CS0_BASE;
- fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
- fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
+ out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
+ out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
+ out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
#endif
#endif
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
/* Latch chipselect */
- fbcs->csar1 = CONFIG_SYS_CS1_BASE;
- fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
- fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
+ out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
+ out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
+ out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
#endif
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
- fbcs->csar2 = CONFIG_SYS_CS2_BASE;
- fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
- fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
+ out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
+ out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
+ out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
#endif
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
- fbcs->csar3 = CONFIG_SYS_CS3_BASE;
- fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
- fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
+ out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
+ out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
+ out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
- fbcs->csar4 = CONFIG_SYS_CS4_BASE;
- fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
- fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
+ out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
+ out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
+ out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
#endif
#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
- fbcs->csar5 = CONFIG_SYS_CS5_BASE;
- fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
- fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
+ out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
+ out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
+ out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
#endif
/*
setvbr(CONFIG_SYS_CS0_BASE);
#ifdef CONFIG_FSL_I2C
- gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA;
+ out_be16(&gpio->par_feci2c,
+ GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
#endif
icache_enable();
int cpu_init_r(void)
{
#ifdef CONFIG_MCFRTC
- volatile rtc_t *rtc = (volatile rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
- volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended;
+ rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
+ rtcex_t *rtcex = (rtcex_t *)&rtc->extended;
- rtcex->gocu = (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xFFFF;
- rtcex->gocl = CONFIG_SYS_RTC_OSCILLATOR & 0xFFFF;
+ out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff);
+ out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff);
#endif
return (0);
void uart_port_conf(int port)
{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
switch (port) {
case 0:
- gpio->par_uart &=
- ~(GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
- gpio->par_uart |=
- (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
+ clrbits_8(&gpio->par_uart,
+ GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
+ setbits_8(&gpio->par_uart,
+ GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
break;
case 1:
#ifdef CONFIG_SYS_UART1_PRI_GPIO
- gpio->par_uart &=
- ~(GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
- gpio->par_uart |=
- (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
+ clrbits_8(&gpio->par_uart,
+ GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
+ setbits_8(&gpio->par_uart,
+ GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
#elif defined(CONFIG_SYS_UART1_ALT1_GPIO)
- gpio->par_ssi &=
- (GPIO_PAR_SSI_SRXD_UNMASK | GPIO_PAR_SSI_STXD_UNMASK);
- gpio->par_ssi |=
- (GPIO_PAR_SSI_SRXD_U1RXD | GPIO_PAR_SSI_STXD_U1TXD);
+ clrbits_be16(&gpio->par_ssi,
+ ~(GPIO_PAR_SSI_SRXD_UNMASK | GPIO_PAR_SSI_STXD_UNMASK));
+ setbits_be16(&gpio->par_ssi,
+ GPIO_PAR_SSI_SRXD_U1RXD | GPIO_PAR_SSI_STXD_U1TXD);
#endif
break;
case 2:
#if defined(CONFIG_SYS_UART2_ALT1_GPIO)
- gpio->par_timer &=
- (GPIO_PAR_TIMER_T3IN_UNMASK | GPIO_PAR_TIMER_T2IN_UNMASK);
- gpio->par_timer |=
- (GPIO_PAR_TIMER_T3IN_U2RXD | GPIO_PAR_TIMER_T2IN_U2TXD);
+ clrbits_8(&gpio->par_timer,
+ ~(GPIO_PAR_TIMER_T3IN_UNMASK | GPIO_PAR_TIMER_T2IN_UNMASK));
+ setbits_8(&gpio->par_timer,
+ GPIO_PAR_TIMER_T3IN_U2RXD | GPIO_PAR_TIMER_T2IN_U2TXD);
#elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
- gpio->par_timer &=
- (GPIO_PAR_FECI2C_SCL_UNMASK | GPIO_PAR_FECI2C_SDA_UNMASK);
- gpio->par_timer |=
- (GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD);
+ clrbits_8(&gpio->par_timer,
+ ~(GPIO_PAR_FECI2C_SCL_UNMASK | GPIO_PAR_FECI2C_SDA_UNMASK));
+ setbits_8(&gpio->par_timer,
+ GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD);
#endif
break;
}
#if defined(CONFIG_CMD_NET)
int fecpin_setclear(struct eth_device *dev, int setclear)
{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
struct fec_info_s *info = (struct fec_info_s *)dev->priv;
if (setclear) {
#ifdef CONFIG_SYS_FEC_NO_SHARED_PHY
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
- gpio->par_feci2c |=
- (GPIO_PAR_FECI2C_MDC0_MDC0 |
- GPIO_PAR_FECI2C_MDIO0_MDIO0);
+ setbits_be16(&gpio->par_feci2c,
+ GPIO_PAR_FECI2C_MDC0_MDC0 |
+ GPIO_PAR_FECI2C_MDIO0_MDIO0);
else
- gpio->par_feci2c |=
- (GPIO_PAR_FECI2C_MDC1_MDC1 |
- GPIO_PAR_FECI2C_MDIO1_MDIO1);
+ setbits_be16(&gpio->par_feci2c,
+ GPIO_PAR_FECI2C_MDC1_MDC1 |
+ GPIO_PAR_FECI2C_MDIO1_MDIO1);
#else
- gpio->par_feci2c |=
- (GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
+ setbits_be16(&gpio->par_feci2c,
+ GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
#endif
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
- gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO;
+ setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_RMII_GPIO);
else
- gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA;
+ setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_RMII_ATA);
} else {
- gpio->par_feci2c &=
- ~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
+ clrbits_be16(&gpio->par_feci2c,
+ GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
#ifdef CONFIG_SYS_FEC_FULL_MII
- gpio->par_fec |= GPIO_PAR_FEC_FEC0_MII;
+ setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_MII);
#else
- gpio->par_fec &= GPIO_PAR_FEC_FEC0_UNMASK;
+ clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC0_UNMASK);
#endif
} else {
#ifdef CONFIG_SYS_FEC_FULL_MII
- gpio->par_fec |= GPIO_PAR_FEC_FEC1_MII;
+ setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_MII);
#else
- gpio->par_fec &= GPIO_PAR_FEC_FEC1_UNMASK;
+ clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC1_UNMASK);
#endif
}
}
#ifdef CONFIG_CF_DSPI
void cfspi_port_conf(void)
{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- gpio->par_dspi = GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
- GPIO_PAR_DSPI_SCK_SCK;
+ out_8(&gpio->par_dspi,
+ GPIO_PAR_DSPI_SIN_SIN |
+ GPIO_PAR_DSPI_SOUT_SOUT |
+ GPIO_PAR_DSPI_SCK_SCK);
}
int cfspi_claim_bus(uint bus, uint cs)
{
- volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- if ((dspi->sr & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
+ if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
return -1;
/* Clear FIFO and resume transfer */
- dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF);
+ clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
switch (cs) {
case 0:
- gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
- gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0;
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
+ setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
break;
case 1:
- gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS1_PCS1;
- gpio->par_dspi |= GPIO_PAR_DSPI_PCS1_PCS1;
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
+ setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
break;
case 2:
- gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS2_PCS2;
- gpio->par_dspi |= GPIO_PAR_DSPI_PCS2_PCS2;
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
+ setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
break;
case 3:
- gpio->par_dma &= GPIO_PAR_DMA_DACK0_UNMASK;
- gpio->par_dma |= GPIO_PAR_DMA_DACK0_PCS3;
+ clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
+ setbits_8(&gpio->par_dma, GPIO_PAR_DMA_DACK0_PCS3);
break;
case 5:
- gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS5_PCS5;
- gpio->par_dspi |= GPIO_PAR_DSPI_PCS5_PCS5;
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
+ setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
break;
}
void cfspi_release_bus(uint bus, uint cs)
{
- volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF); /* Clear FIFO */
+ /* Clear FIFO */
+ clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
switch (cs) {
case 0:
- gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
break;
case 1:
- gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS1_PCS1;
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
break;
case 2:
- gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS2_PCS2;
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
break;
case 3:
- gpio->par_dma &= GPIO_PAR_DMA_DACK0_UNMASK;
+ clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
break;
case 5:
- gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS5_PCS5;
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
break;
}
}
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
/* CPU specific interrupt routine */
#include <common.h>
#include <asm/immap.h>
+#include <asm/io.h>
int interrupt_init(void)
{
- volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+ int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
/* Make sure all interrupts are disabled */
- intp->imrh0 |= 0xFFFFFFFF;
- intp->imrl0 |= 0xFFFFFFFF;
+ setbits_be32(&intp->imrh0, 0xffffffff);
+ setbits_be32(&intp->imrl0, 0xffffffff);
enable_interrupts();
return 0;
#if defined(CONFIG_MCFTMR)
void dtimer_intr_setup(void)
{
- volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+ int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
- intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
- intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK;
+ out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
+ clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK);
}
#endif
/*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
void pci_mcf5445x_init(struct pci_controller *hose)
{
- volatile pci_t *pci = (volatile pci_t *)MMAP_PCI;
- volatile pciarb_t *pciarb = (volatile pciarb_t *)MMAP_PCIARB;
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ pci_t *pci = (pci_t *)MMAP_PCI;
+ pciarb_t *pciarb = (pciarb_t *)MMAP_PCIARB;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
u32 barEn = 0;
- pciarb->acr = 0x001F001F;
+ out_be32(&pciarb->acr, 0x001f001f);
/* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT,
PCIREQ2, PCIGNT2 */
- gpio->par_pci =
- GPIO_PAR_PCI_GNT3_GNT3 | GPIO_PAR_PCI_GNT2 | GPIO_PAR_PCI_GNT1 |
- GPIO_PAR_PCI_GNT0 | GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 |
- GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0;
+ out_be16(&gpio->par_pci,
+ GPIO_PAR_PCI_GNT3_GNT3 | GPIO_PAR_PCI_GNT2 |
+ GPIO_PAR_PCI_GNT1 | GPIO_PAR_PCI_GNT0 |
+ GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 |
+ GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0);
/* Assert reset bit */
- pci->gscr |= PCI_GSCR_PR;
+ setbits_be32(&pci->gscr, PCI_GSCR_PR);
- pci->tcr1 |= PCI_TCR1_P;
+ setbits_be32(&pci->tcr1, PCI_TCR1_P);
/* Initiator windows */
- pci->iw0btar = CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16);
- pci->iw1btar = CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16);
- pci->iw2btar = CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16);
+ out_be32(&pci->iw0btar,
+ CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16));
+ out_be32(&pci->iw1btar,
+ CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16));
+ out_be32(&pci->iw2btar,
+ CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16));
- pci->iwcr =
- PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
- PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO;
+ out_be32(&pci->iwcr,
+ PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
+ PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO);
- pci->icr = 0;
+ out_be32(&pci->icr, 0);
/* Enable bus master and mem access */
- pci->scr = PCI_SCR_B | PCI_SCR_M;
+ out_be32(&pci->scr, PCI_SCR_B | PCI_SCR_M);
/* Cache line size and master latency */
- pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8);
- pci->cr2 = 0;
+ out_be32(&pci->cr1, PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8));
+ out_be32(&pci->cr2, 0);
#ifdef CONFIG_SYS_PCI_BAR0
- pci->bar0 = PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0);
- pci->tbatr0 = CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN;
+ out_be32(&pci->bar0, PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0));
+ out_be32(&pci->tbatr0, CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN);
barEn |= PCI_TCR2_B0E;
#endif
#ifdef CONFIG_SYS_PCI_BAR1
- pci->bar1 = PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1);
- pci->tbatr1 = CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN;
+ out_be32(&pci->bar1, PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1));
+ out_be32(&pci->tbatr1, CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN);
barEn |= PCI_TCR2_B1E;
#endif
#ifdef CONFIG_SYS_PCI_BAR2
- pci->bar2 = PCI_BAR_BAR2(CONFIG_SYS_PCI_BAR2);
- pci->tbatr2 = CONFIG_SYS_PCI_TBATR2 | PCI_TBATR_EN;
+ out_be32(&pci->bar2, PCI_BAR_BAR2(CONFIG_SYS_PCI_BAR2));
+ out_be32(&pci->tbatr2, CONFIG_SYS_PCI_TBATR2 | PCI_TBATR_EN);
barEn |= PCI_TCR2_B2E;
#endif
#ifdef CONFIG_SYS_PCI_BAR3
- pci->bar3 = PCI_BAR_BAR3(CONFIG_SYS_PCI_BAR3);
- pci->tbatr3 = CONFIG_SYS_PCI_TBATR3 | PCI_TBATR_EN;
+ out_be32(&pci->bar3, PCI_BAR_BAR3(CONFIG_SYS_PCI_BAR3));
+ out_be32(&pci->tbatr3, CONFIG_SYS_PCI_TBATR3 | PCI_TBATR_EN);
barEn |= PCI_TCR2_B3E;
#endif
#ifdef CONFIG_SYS_PCI_BAR4
- pci->bar4 = PCI_BAR_BAR4(CONFIG_SYS_PCI_BAR4);
- pci->tbatr4 = CONFIG_SYS_PCI_TBATR4 | PCI_TBATR_EN;
+ out_be32(&pci->bar4, PCI_BAR_BAR4(CONFIG_SYS_PCI_BAR4));
+ out_be32(&pci->tbatr4, CONFIG_SYS_PCI_TBATR4 | PCI_TBATR_EN);
barEn |= PCI_TCR2_B4E;
#endif
#ifdef CONFIG_SYS_PCI_BAR5
- pci->bar5 = PCI_BAR_BAR5(CONFIG_SYS_PCI_BAR5);
- pci->tbatr5 = CONFIG_SYS_PCI_TBATR5 | PCI_TBATR_EN;
+ out_be32(&pci->bar5, PCI_BAR_BAR5(CONFIG_SYS_PCI_BAR5));
+ out_be32(&pci->tbatr5, CONFIG_SYS_PCI_TBATR5 | PCI_TBATR_EN);
barEn |= PCI_TCR2_B5E;
#endif
- pci->tcr2 = barEn;
+ out_be32(&pci->tcr2, barEn);
/* Deassert reset bit */
- pci->gscr &= ~PCI_GSCR_PR;
+ clrbits_be32(&pci->gscr, PCI_GSCR_PR);
udelay(1000);
/* Enable PCI bus master support */
/*
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
#include <asm/processor.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
void clock_enter_limp(int lpdiv)
{
- volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
+ ccm_t *ccm = (ccm_t *)MMAP_CCM;
int i, j;
/* Check bounds of divider */
for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
/* Apply the divider to the system clock */
- ccm->cdr = (ccm->cdr & 0xF0FF) | CCM_CDR_LPDIV(i);
+ clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
/* Enable Limp Mode */
- ccm->misccr |= CCM_MISCCR_LIMP;
+ setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
}
/*
*/
void clock_exit_limp(void)
{
- volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
- volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
+ ccm_t *ccm = (ccm_t *)MMAP_CCM;
+ pll_t *pll = (pll_t *)MMAP_PLL;
/* Exit Limp mode */
- ccm->misccr &= ~CCM_MISCCR_LIMP;
+ clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
/* Wait for the PLL to lock */
- while (!(pll->psr & PLL_PSR_LOCK)) ;
+ while (!(in_be32(&pll->psr) & PLL_PSR_LOCK))
+ ;
}
/*
int get_clocks(void)
{
- volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
- volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
+ ccm_t *ccm = (ccm_t *)MMAP_CCM;
+ pll_t *pll = (pll_t *)MMAP_PLL;
int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 };
int pllmult_pci[] = { 12, 6, 16, 8 };
int vco = 0, bPci, temp, fbtemp, pcrvalue;
u16 fbpll_mask;
#ifdef CONFIG_M54455EVB
- volatile u8 *cpld = (volatile u8 *)(CONFIG_SYS_CS2_BASE + 3);
+ u8 *cpld = (u8 *)(CONFIG_SYS_CS2_BASE + 3);
#endif
u8 bootmode;
/* To determine PCI is present or not */
- if (((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) ||
- ((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) {
+ if (((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) ||
+ ((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) {
pPllmult = &pllmult_pci[0];
fbpll_mask = 3; /* 11b */
bPci = 1;
}
#ifdef CONFIG_M54455EVB
- bootmode = (*cpld & 0x03);
+ bootmode = (in_8(cpld) & 0x03);
if (bootmode != 3) {
/* Temporary read from CCR- fixed fb issue, must be the same clock
fbtemp = pPllmult[ccm->ccr & fbpll_mask];
/* Break down into small pieces, code still in flex bus */
- pcrvalue = pll->pcr & 0xFFFFF0FF;
+ pcrvalue = in_be32(&pll->pcr) & 0xFFFFF0FF;
temp = fbtemp - 1;
pcrvalue |= PLL_PCR_OUTDIV3(temp);
- pll->pcr = pcrvalue;
+ out_be32(&pll->pcr, pcrvalue);
}
#endif
#ifdef CONFIG_M54451EVB
bootmode = 2;
/* default value is 16 mul, set to 20 mul */
- pcrvalue = (pll->pcr & 0x00FFFFFF) | 0x14000000;
- pll->pcr = pcrvalue;
- while ((pll->psr & PLL_PSR_LOCK) != PLL_PSR_LOCK);
+ pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF) | 0x14000000;
+ out_be32(&pll->pcr, pcrvalue);
+ while ((in_be32(&pll->psr) & PLL_PSR_LOCK) != PLL_PSR_LOCK)
+ ;
#endif
#endif
if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
/* invaild range, re-set in PCR */
- int temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
+ int temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
int i, j, bus;
- j = (pll->pcr & 0xFF000000) >> 24;
+ j = (in_be32(&pll->pcr) & 0xFF000000) >> 24;
for (i = j; i < 0xFF; i++) {
vco = i * CONFIG_SYS_INPUT_CLKSRC;
if (vco >= CLOCK_PLL_FVCO_MIN) {
break;
}
}
- pcrvalue = pll->pcr & 0x00FF00FF;
+ pcrvalue = in_be32(&pll->pcr) & 0x00FF00FF;
fbtemp = ((i - 1) << 8) | ((i - 1) << 12);
pcrvalue |= ((i << 24) | fbtemp);
- pll->pcr = pcrvalue;
+ out_be32(&pll->pcr, pcrvalue);
}
gd->vco_clk = vco; /* Vco clock */
} else if (bootmode == 2) {
/* Normal mode */
- vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
+ vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
/* Default value */
- pcrvalue = (pll->pcr & 0x00FFFFFF);
- pcrvalue |= pPllmult[ccm->ccr & fbpll_mask] << 24;
- pll->pcr = pcrvalue;
- vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
+ pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF);
+ pcrvalue |= pPllmult[in_be16(&ccm->ccr) & fbpll_mask] << 24;
+ out_be32(&pll->pcr, pcrvalue);
+ vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
}
gd->vco_clk = vco; /* Vco clock */
} else if (bootmode == 3) {
/* serial mode */
- vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
+ vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
gd->vco_clk = vco; /* Vco clock */
}
- if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
+ if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
/* Limp mode */
} else {
gd->inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
- temp = (pll->pcr & PLL_PCR_OUTDIV1_MASK) + 1;
+ temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
gd->cpu_clk = vco / temp; /* cpu clock */
- temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
+ temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
gd->bus_clk = vco / temp; /* bus clock */
- temp = ((pll->pcr & PLL_PCR_OUTDIV3_MASK) >> 8) + 1;
+ temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV3_MASK) >> 8) + 1;
gd->flb_clk = vco / temp; /* FlexBus clock */
#ifdef CONFIG_PCI
if (bPci) {
- temp = ((pll->pcr & PLL_PCR_OUTDIV4_MASK) >> 12) + 1;
+ temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV4_MASK) >> 12) + 1;
gd->pci_clk = vco / temp; /* PCI clock */
}
#endif
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
#include <netdev.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
+ gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
- gptmr->pre = 10;
- gptmr->cnt = 1;
+ out_be16(&gptmr->pre, 10);
+ out_be16(&gptmr->cnt, 1);
/* enable watchdog, set timeout to 0 and wait */
- gptmr->mode = GPT_TMS_SGPIO;
- gptmr->ctrl = GPT_CTRL_WDEN | GPT_CTRL_CE;
+ out_8(&gptmr->mode, GPT_TMS_SGPIO);
+ out_8(&gptmr->ctrl, GPT_CTRL_WDEN | GPT_CTRL_CE);
/* we don't return! */
return 1;
int checkcpu(void)
{
- volatile siu_t *siu = (siu_t *) MMAP_SIU;
+ siu_t *siu = (siu_t *) MMAP_SIU;
u16 id = 0;
puts("CPU: ");
- switch ((siu->jtagid & 0x000FF000) >> 12) {
+ switch ((in_be32(&siu->jtagid) & 0x000FF000) >> 12) {
case 0x0C:
id = 5485;
break;
/* Called by macro WATCHDOG_RESET */
void hw_watchdog_reset(void)
{
- volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
+ gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
- gptmr->ocpw = 0xa5;
+ out_8(&gptmr->ocpw, 0xa5);
}
int watchdog_disable(void)
{
- volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
+ gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
/* UserManual, once the wdog is disabled, wdog cannot be re-enabled */
- gptmr->mode = 0;
- gptmr->ctrl = 0;
+ out_8(&gptmr->mode, 0);
+ out_8(&gptmr->ctrl, 0);
puts("WATCHDOG:disabled\n");
int watchdog_init(void)
{
+ gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
- volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
+ out_be16(&gptmr->pre, CONFIG_WATCHDOG_TIMEOUT);
+ out_be16(&gptmr->cnt, CONFIG_SYS_TIMER_PRESCALER * 1000);
- gptmr->pre = CONFIG_WATCHDOG_TIMEOUT;
- gptmr->cnt = CONFIG_SYS_TIMER_PRESCALER * 1000;
-
- gptmr->mode = GPT_TMS_SGPIO;
- gptmr->ctrl = GPT_CTRL_CE | GPT_CTRL_WDEN;
+ out_8(&gptmr->mode, GPT_TMS_SGPIO);
+ out_8(&gptmr->ctrl, GPT_CTRL_CE | GPT_CTRL_WDEN);
puts("WATCHDOG:enabled\n");
return (0);
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * (C) Copyright 2007 Freescale Semiconductor, Inc.
+ * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
#include <common.h>
#include <MCD_dma.h>
#include <asm/immap.h>
+#include <asm/io.h>
#if defined(CONFIG_CMD_NET)
#include <config.h>
*/
void cpu_init_f(void)
{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
- volatile xlbarb_t *xlbarb = (volatile xlbarb_t *) MMAP_XARB;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+ xlbarb_t *xlbarb = (xlbarb_t *) MMAP_XARB;
- xlbarb->adrto = 0x2000;
- xlbarb->datto = 0x2500;
- xlbarb->busto = 0x3000;
+ out_be32(&xlbarb->adrto, 0x2000);
+ out_be32(&xlbarb->datto, 0x2500);
+ out_be32(&xlbarb->busto, 0x3000);
- xlbarb->cfg = XARB_CFG_AT | XARB_CFG_DT;
+ out_be32(&xlbarb->cfg, XARB_CFG_AT | XARB_CFG_DT);
/* Master Priority Enable */
- xlbarb->prien = 0xff;
- xlbarb->pri = 0;
+ out_be32(&xlbarb->prien, 0xff);
+ out_be32(&xlbarb->pri, 0);
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
- fbcs->csar0 = CONFIG_SYS_CS0_BASE;
- fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
- fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
+ out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
+ out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
+ out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
#endif
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
- fbcs->csar1 = CONFIG_SYS_CS1_BASE;
- fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
- fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
+ out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
+ out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
+ out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
#endif
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
- fbcs->csar2 = CONFIG_SYS_CS2_BASE;
- fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
- fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
+ out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
+ out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
+ out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
#endif
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
- fbcs->csar3 = CONFIG_SYS_CS3_BASE;
- fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
- fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
+ out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
+ out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
+ out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
- fbcs->csar4 = CONFIG_SYS_CS4_BASE;
- fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
- fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
+ out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
+ out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
+ out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
#endif
#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
- fbcs->csar5 = CONFIG_SYS_CS5_BASE;
- fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
- fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
+ out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
+ out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
+ out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
#endif
#ifdef CONFIG_FSL_I2C
- gpio->par_feci2cirq = GPIO_PAR_FECI2CIRQ_SCL | GPIO_PAR_FECI2CIRQ_SDA;
+ out_be16(&gpio->par_feci2cirq,
+ GPIO_PAR_FECI2CIRQ_SCL | GPIO_PAR_FECI2CIRQ_SDA);
#endif
icache_enable();
void uart_port_conf(int port)
{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- volatile u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40);
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40);
/* Setup Ports: */
switch (port) {
case 0:
- gpio->par_psc0 = (GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0);
+ out_8(&gpio->par_psc0, GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0);
break;
case 1:
- gpio->par_psc1 = (GPIO_PAR_PSC1_TXD1 | GPIO_PAR_PSC1_RXD1);
+ out_8(&gpio->par_psc1, GPIO_PAR_PSC1_TXD1 | GPIO_PAR_PSC1_RXD1);
break;
case 2:
- gpio->par_psc2 = (GPIO_PAR_PSC2_TXD2 | GPIO_PAR_PSC2_RXD2);
+ out_8(&gpio->par_psc2, GPIO_PAR_PSC2_TXD2 | GPIO_PAR_PSC2_RXD2);
break;
case 3:
- gpio->par_psc3 = (GPIO_PAR_PSC3_TXD3 | GPIO_PAR_PSC3_RXD3);
+ out_8(&gpio->par_psc3, GPIO_PAR_PSC3_TXD3 | GPIO_PAR_PSC3_RXD3);
break;
}
- *pscsicr &= 0xF8;
+ clrbits_8(pscsicr, 0x07);
}
#if defined(CONFIG_CMD_NET)
int fecpin_setclear(struct eth_device *dev, int setclear)
{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
struct fec_info_dma *info = (struct fec_info_dma *)dev->priv;
if (setclear) {
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
- gpio->par_feci2cirq |= 0xF000;
+ setbits_be16(&gpio->par_feci2cirq, 0xf000);
else
- gpio->par_feci2cirq |= 0x0FC0;
+ setbits_be16(&gpio->par_feci2cirq, 0x0fc0);
} else {
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
- gpio->par_feci2cirq &= 0x0FFF;
+ clrbits_be16(&gpio->par_feci2cirq, 0xf000);
else
- gpio->par_feci2cirq &= 0xF03F;
+ clrbits_be16(&gpio->par_feci2cirq, 0x0fc0);
}
return 0;
}
/*
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
/* CPU specific interrupt routine */
#include <common.h>
#include <asm/immap.h>
+#include <asm/io.h>
int interrupt_init(void)
{
- volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+ int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
/* Make sure all interrupts are disabled */
- intp->imrh0 |= 0xFFFFFFFF;
- intp->imrl0 |= 0xFFFFFFFF;
+ setbits_be32(&intp->imrh0, 0xffffffff);
+ setbits_be32(&intp->imrl0, 0xffffffff);
enable_interrupts();
#if defined(CONFIG_SLTTMR)
void dtimer_intr_setup(void)
{
- volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+ int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
- intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
- intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK;
+ out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
+ clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK);
}
#endif
/*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
void pci_mcf547x_8x_init(struct pci_controller *hose)
{
- volatile pci_t *pci = (volatile pci_t *) MMAP_PCI;
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ pci_t *pci = (pci_t *) MMAP_PCI;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Port configuration */
- gpio->par_pcibg =
- GPIO_PAR_PCIBG_PCIBG0(3) | GPIO_PAR_PCIBG_PCIBG1(3) |
- GPIO_PAR_PCIBG_PCIBG2(3) | GPIO_PAR_PCIBG_PCIBG3(3) |
- GPIO_PAR_PCIBG_PCIBG4(3);
- gpio->par_pcibr =
- GPIO_PAR_PCIBR_PCIBR0(3) | GPIO_PAR_PCIBR_PCIBR1(3) |
- GPIO_PAR_PCIBR_PCIBR2(3) | GPIO_PAR_PCIBR_PCIBR3(3) |
- GPIO_PAR_PCIBR_PCIBR4(3);
+ out_be16(&gpio->par_pcibg,
+ GPIO_PAR_PCIBG_PCIBG0(3) | GPIO_PAR_PCIBG_PCIBG1(3) |
+ GPIO_PAR_PCIBG_PCIBG2(3) | GPIO_PAR_PCIBG_PCIBG3(3) |
+ GPIO_PAR_PCIBG_PCIBG4(3));
+ out_be16(&gpio->par_pcibr,
+ GPIO_PAR_PCIBR_PCIBR0(3) | GPIO_PAR_PCIBR_PCIBR1(3) |
+ GPIO_PAR_PCIBR_PCIBR2(3) | GPIO_PAR_PCIBR_PCIBR3(3) |
+ GPIO_PAR_PCIBR_PCIBR4(3));
/* Assert reset bit */
- pci->gscr |= PCI_GSCR_PR;
+ setbits_be32(&pci->gscr, PCI_GSCR_PR);
- pci->tcr1 = PCI_TCR1_P;
+ out_be32(&pci->tcr1, PCI_TCR1_P);
/* Initiator windows */
- pci->iw0btar = CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16);
- pci->iw1btar = CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16);
- pci->iw2btar = CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16);
+ out_be32(&pci->iw0btar,
+ CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16));
+ out_be32(&pci->iw1btar,
+ CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16));
+ out_be32(&pci->iw2btar,
+ CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16));
- pci->iwcr =
- PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
- PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO;
+ out_be32(&pci->iwcr,
+ PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
+ PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO);
- pci->icr = 0;
+ out_be32(&pci->icr, 0);
/* Enable bus master and mem access */
- pci->scr = PCI_SCR_B | PCI_SCR_M;
+ out_be32(&pci->scr, PCI_SCR_B | PCI_SCR_M);
/* Cache line size and master latency */
- pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8);
- pci->cr2 = 0;
+ out_be32(&pci->cr1, PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xf8));
+ out_be32(&pci->cr2, 0);
#ifdef CONFIG_SYS_PCI_BAR0
- pci->bar0 = PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0);
- pci->tbatr0a = CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN;
+ out_be32(&pci->bar0, PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0));
+ out_be32(&pci->tbatr0a, CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN);
#endif
#ifdef CONFIG_SYS_PCI_BAR1
- pci->bar1 = PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1);
- pci->tbatr1a = CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN;
+ out_be32(&pci->bar1, PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1));
+ out_be32(&pci->tbatr1a, CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN);
#endif
/* Deassert reset bit */
- pci->gscr &= ~PCI_GSCR_PR;
+ clrbits_be32(&pci->gscr, PCI_GSCR_PR);
udelay(1000);
/* Enable PCI bus master support */
/*
- * (C) Copyright 2007 Freescale Semiconductor, Inc.
+ * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
#include <asm/timer.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
void __udelay(unsigned long usec)
{
- volatile slt_t *timerp = (slt_t *) (CONFIG_SYS_UDELAY_BASE);
+ slt_t *timerp = (slt_t *) (CONFIG_SYS_UDELAY_BASE);
u32 now, freq;
/* 1 us period */
freq = CONFIG_SYS_TIMER_PRESCALER;
- timerp->cr = 0; /* Disable */
- timerp->tcnt = usec * freq;
- timerp->cr = SLT_CR_TEN;
+ /* Disable */
+ out_be32(&timerp->cr, 0);
+ out_be32(&timerp->tcnt, usec * freq);
+ out_be32(&timerp->cr, SLT_CR_TEN);
- now = timerp->cnt;
+ now = in_be32(&timerp->cnt);
while (now != 0)
- now = timerp->cnt;
+ now = in_be32(&timerp->cnt);
- timerp->sr |= SLT_SR_ST;
- timerp->cr = 0;
+ setbits_be32(&timerp->sr, SLT_SR_ST);
+ out_be32(&timerp->cr, 0);
}
void dtimer_interrupt(void *not_used)
{
- volatile slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
+ slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
/* check for timer interrupt asserted */
if ((CONFIG_SYS_TMRPND_REG & CONFIG_SYS_TMRINTR_MASK) == CONFIG_SYS_TMRINTR_PEND) {
- timerp->sr |= SLT_SR_ST;
+ setbits_be32(&timerp->sr, SLT_SR_ST);
timestamp++;
return;
}
int timer_init(void)
{
- volatile slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
+ slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
timestamp = 0;
- timerp->cr = 0; /* disable timer */
- timerp->tcnt = 0;
- timerp->sr = SLT_SR_BE | SLT_SR_ST; /* clear status */
+ /* disable timer */
+ out_be32(&timerp->cr, 0);
+ out_be32(&timerp->tcnt, 0);
+ /* clear status */
+ out_be32(&timerp->sr, SLT_SR_BE | SLT_SR_ST);
/* initialize and enable timer interrupt */
irq_install_handler(CONFIG_SYS_TMRINTR_NO, dtimer_interrupt, 0);
/* Interrupt every ms */
- timerp->tcnt = 1000 * CONFIG_SYS_TIMER_PRESCALER;
+ out_be32(&timerp->tcnt, 1000 * CONFIG_SYS_TIMER_PRESCALER);
dtimer_intr_setup();
/* set a period of 1us, set timer mode to restart and
enable timer and interrupt */
- timerp->cr = SLT_CR_RUN | SLT_CR_IEN | SLT_CR_TEN;
+ out_be32(&timerp->cr, SLT_CR_RUN | SLT_CR_IEN | SLT_CR_TEN);
return 0;
}
#ifdef __KERNEL__
-/*
- * ffs: find first bit set. This is defined the same way as
- * the libc and compiler builtin ffs routines, therefore
- * differs in spirit from the above ffz (man ffs).
- */
-extern __inline__ int ffs(int x)
+
+extern inline int test_bit(int nr, __const__ volatile void *addr)
{
- int r = 1;
-
- if (!x)
- return 0;
- if (!(x & 0xffff)) {
- x >>= 16;
- r += 16;
- }
- if (!(x & 0xff)) {
- x >>= 8;
- r += 8;
- }
- if (!(x & 0xf)) {
- x >>= 4;
- r += 4;
- }
- if (!(x & 3)) {
- x >>= 2;
- r += 2;
- }
- if (!(x & 1)) {
- x >>= 1;
- r += 1;
- }
- return r;
+ __const__ unsigned int *p = (__const__ unsigned int *) addr;
+
+ return (p[nr >> 5] & (1UL << (nr & 31))) != 0;
}
+
+extern inline int test_and_set_bit(int nr, volatile void *vaddr)
+{
+ char retval;
+
+ volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3];
+ __asm__ __volatile__ ("bset %2,(%4); sne %0"
+ : "=d" (retval), "=m" (*p)
+ : "di" (nr & 7), "m" (*p), "a" (p));
+
+ return retval;
+}
+
#define __ffs(x) (ffs(x) - 1)
-#define PLATFORM_FFS
+
+/*
+ * * hweightN: returns the hamming weight (i.e. the number
+ * * of bits set) of a N-bit word
+ * */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
#endif /* __KERNEL__ */
/*********************************************************************
* FlexBus Chip Selects (FBCS)
*********************************************************************/
+#ifdef CONFIG_M5235
+typedef struct fbcs {
+ u16 csar0; /* Chip-select Address */
+ u16 res1;
+ u32 csmr0; /* Chip-select Mask */
+ u16 res2;
+ u16 cscr0; /* Chip-select Control */
+
+ u16 csar1;
+ u16 res3;
+ u32 csmr1;
+ u16 res4;
+ u16 cscr1;
+
+ u16 csar2;
+ u16 res5;
+ u32 csmr2;
+ u16 res6;
+ u16 cscr2;
+
+ u16 csar3;
+ u16 res7;
+ u32 csmr3;
+ u16 res8;
+ u16 cscr3;
+
+ u16 csar4;
+ u16 res9;
+ u32 csmr4;
+ u16 res10;
+ u16 cscr4;
+
+ u16 csar5;
+ u16 res11;
+ u32 csmr5;
+ u16 res12;
+ u16 cscr5;
+ u16 csar6;
+ u16 res13;
+ u32 csmr6;
+ u16 res14;
+ u16 cscr6;
+
+ u16 csar7;
+ u16 res15;
+ u32 csmr7;
+ u16 res16;
+ u16 cscr7;
+} fbcs_t;
+#else
typedef struct fbcs {
u32 csar0; /* Chip-select Address */
u32 csmr0; /* Chip-select Mask */
u32 csmr7;
u32 cscr7;
} fbcs_t;
+#endif
#define FBCS_CSAR_BA(x) ((x) & 0xFFFF0000)
#endif
#define FBCS_CSMR_V (0x00000001) /* Valid bit */
+#ifdef CONFIG_M5235
+#define FBCS_CSCR_SRWS(x) (((x) & 0x3) << 14)
+#define FBCS_CSCR_IWS(x) (((x) & 0xF) << 10)
+#define FBCS_CSCR_AA_ON (1 << 8)
+#define FBCS_CSCR_AA_OFF (0 << 8)
+#define FBCS_CSCR_PS_32 (0 << 6)
+#define FBCS_CSCR_PS_16 (2 << 6)
+#define FBCS_CSCR_PS_8 (1 << 6)
+#define FBCS_CSCR_BEM_ON (1 << 5)
+#define FBCS_CSCR_BEM_OFF (0 << 5)
+#define FBCS_CSCR_BSTR_ON (1 << 4)
+#define FBCS_CSCR_BSTR_OFF (0 << 4)
+#define FBCS_CSCR_BSTW_ON (1 << 3)
+#define FBCS_CSCR_BSTW_OFF (0 << 3)
+#define FBCS_CSCR_SWWS(x) (((x) & 0x7) << 0)
+#else
#define FBCS_CSCR_SWS(x) (((x) & 0x3F) << 26)
#define FBCS_CSCR_SWS_MASK (0x03FFFFFF)
#define FBCS_CSCR_SWSEN (0x00800000)
#define FBCS_CSCR_PS_16 (0x00000080)
#define FBCS_CSCR_PS_8 (0x00000040)
#define FBCS_CSCR_PS_32 (0x00000000)
+#endif
#endif /* __FLEXBUS_H */
#define QSPI_QAR_RECV (0x0010)
#define QSPI_QAR_CMD (0x0020)
-/* DR */
+/* DR with RAM command word definitions */
#define QSPI_QDR_CONT (0x8000)
#define QSPI_QDR_BITSE (0x4000)
#define QSPI_QDR_DT (0x2000)
/*
* IO header file
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
*addr = val;
}
+/* Clear and set bits in one shot. These macros can be used to clear and
+ * set multiple bits in a register using a single call. These macros can
+ * also be used to set a multiple-bit bit pattern using a mask, by
+ * specifying the mask in the 'clear' parameter and the new bit pattern
+ * in the 'set' parameter.
+ */
+
+#define clrbits(type, addr, clear) \
+ out_##type((addr), in_##type(addr) & ~(clear))
+
+#define setbits(type, addr, set) \
+ out_##type((addr), in_##type(addr) | (set))
+
+#define clrsetbits(type, addr, clear, set) \
+ out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
+
+#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
+#define setbits_be32(addr, set) setbits(be32, addr, set)
+#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
+
+#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
+#define setbits_le32(addr, set) setbits(le32, addr, set)
+#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
+
+#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
+#define setbits_be16(addr, set) setbits(be16, addr, set)
+#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
+
+#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
+#define setbits_le16(addr, set) setbits(le16, addr, set)
+#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
+
+#define clrbits_8(addr, clear) clrbits(8, addr, clear)
+#define setbits_8(addr, set) setbits(8, addr, set)
+#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
+
static inline void sync(void)
{
/* This sync function is for PowerPC or other architecture instruction
#define MCF_GPIO_PAR_UART_U1RXD_UART1 0x0C00
#define MCF_GPIO_PAR_UART_U1TXD_UART1 0x0300
+/* Bit definitions and macros for PAR_QSPI */
+#define MCF_GPIO_PAR_QSPI_PCS1_UNMASK 0x3F
+#define MCF_GPIO_PAR_QSPI_PCS1_PCS1 0xC0
+#define MCF_GPIO_PAR_QSPI_PCS1_SDRAM_SCKE 0x80
+#define MCF_GPIO_PAR_QSPI_PCS1_GPIO 0x00
+#define MCF_GPIO_PAR_QSPI_PCS0_UNMASK 0xDF
+#define MCF_GPIO_PAR_QSPI_PCS0_PCS0 0x20
+#define MCF_GPIO_PAR_QSPI_PCS0_GPIO 0x00
+#define MCF_GPIO_PAR_QSPI_SIN_UNMASK 0xE7
+#define MCF_GPIO_PAR_QSPI_SIN_SIN 0x18
+#define MCF_GPIO_PAR_QSPI_SIN_I2C_SDA 0x10
+#define MCF_GPIO_PAR_QSPI_SIN_GPIO 0x00
+#define MCF_GPIO_PAR_QSPI_SOUT_UNMASK 0xFB
+#define MCF_GPIO_PAR_QSPI_SOUT_SOUT 0x04
+#define MCF_GPIO_PAR_QSPI_SOUT_GPIO 0x00
+#define MCF_GPIO_PAR_QSPI_SCK_UNMASK 0xFC
+#define MCF_GPIO_PAR_QSPI_SCK_SCK 0x03
+#define MCF_GPIO_PAR_QSPI_SCK_I2C_SCL 0x02
+#define MCF_GPIO_PAR_QSPI_SCK_GPIO 0x00
+
+/* Bit definitions and macros for PAR_TIMER for QSPI */
+#define MCF_GPIO_PAR_TIMER_T3IN_UNMASK 0x3FFF
+#define MCF_GPIO_PAR_TIMER_T3IN_QSPI_PCS2 0x4000
+#define MCF_GPIO_PAR_TIMER_T3OUT_UNMASK 0xFF3F
+#define MCF_GPIO_PAR_TIMER_T3OUT_QSPI_PCS3 0x0040
+
#define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6)
#define MCF_SDRAMC_DCR 0x000040
PLATFORM_CPPFLAGS += -ffixed-r31 -D__microblaze__
LDSCRIPT ?= $(SRCTREE)/$(CPUDIR)/u-boot.lds
+
+CONFIG_ARCH_DEVICE_TREE := microblaze
#undef DEBUG_INT
-extern void microblaze_disable_interrupts (void);
-extern void microblaze_enable_interrupts (void);
-
-void enable_interrupts (void)
+void enable_interrupts(void)
{
MSRSET(0x2);
}
-int disable_interrupts (void)
+int disable_interrupts(void)
{
unsigned int msr;
/* default handler */
static void def_hdlr(void)
{
- puts ("def_hdlr\n");
+ puts("def_hdlr\n");
}
static void enable_one_interrupt(int irq)
{
int mask;
int offset = 1;
+
offset <<= irq;
mask = intc->ier;
intc->ier = (mask | offset);
#ifdef DEBUG_INT
- printf ("Enable one interrupt irq %x - mask %x,ier %x\n", offset, mask,
+ printf("Enable one interrupt irq %x - mask %x,ier %x\n", offset, mask,
intc->ier);
- printf ("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
+ printf("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
intc->iar, intc->mer);
#endif
}
{
int mask;
int offset = 1;
+
offset <<= irq;
mask = intc->ier;
intc->ier = (mask & ~offset);
#ifdef DEBUG_INT
- printf ("Disable one interrupt irq %x - mask %x,ier %x\n", irq, mask,
+ printf("Disable one interrupt irq %x - mask %x,ier %x\n", irq, mask,
intc->ier);
- printf ("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
+ printf("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
intc->iar, intc->mer);
#endif
}
-/* adding new handler for interrupt */
-void install_interrupt_handler (int irq, interrupt_handler_t * hdlr, void *arg)
+int install_interrupt_handler(int irq, interrupt_handler_t *hdlr, void *arg)
{
struct irq_action *act;
+
/* irq out of range */
if ((irq < 0) || (irq > irq_no)) {
- puts ("IRQ out of range\n");
- return;
+ puts("IRQ out of range\n");
+ return -1;
}
act = &vecs[irq];
if (hdlr) { /* enable */
act->arg = arg;
act->count = 0;
enable_one_interrupt (irq);
- } else { /* disable */
- act->handler = (interrupt_handler_t *) def_hdlr;
- act->arg = (void *)irq;
- disable_one_interrupt (irq);
+ return 0;
}
+
+ /* Disable */
+ act->handler = (interrupt_handler_t *) def_hdlr;
+ act->arg = (void *)irq;
+ disable_one_interrupt(irq);
+ return 1;
}
/* initialization interrupt controller - hardware */
/* XIntc_Start - hw_interrupt enable and all interrupt enable */
intc->mer = 0x3;
#ifdef DEBUG_INT
- printf ("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
+ printf("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
intc->iar, intc->mer);
#endif
}
return 0;
}
-void interrupt_handler (void)
+void interrupt_handler(void)
{
int irqs = intc->ivr; /* find active interrupt */
int mask = 1;
cmp r6, r5, r4 /* check if we have reach the end */
bnei r6, 2b
3: /* jumping to board_init */
- brai board_init
+ brai board_init_f
1: bri 1b
/*
#include <asm/microblaze_intc.h>
volatile int timestamp = 0;
+microblaze_timer_t *tmr;
-#ifdef CONFIG_SYS_TIMER_0
ulong get_timer (ulong base)
{
- return (timestamp - base);
+ if (tmr)
+ return timestamp - base;
+ return timestamp++ - base;
}
-#else
-ulong get_timer (ulong base)
-{
- return (timestamp++ - base);
-}
-#endif
-#ifdef CONFIG_SYS_TIMER_0
void __udelay(unsigned long usec)
{
- int i;
+ u32 i;
- i = get_timer(0);
- while ((get_timer(0) - i) < (usec / 1000))
- ;
+ if (tmr) {
+ i = get_timer(0);
+ while ((get_timer(0) - i) < (usec / 1000))
+ ;
+ } else {
+ for (i = 0; i < (usec * XILINX_CLOCK_FREQ / 10000000); i++)
+ ;
+ }
}
-#else
-void __udelay(unsigned long usec)
-{
- unsigned int i;
- for (i = 0; i < (usec * CONFIG_XILINX_CLOCK_FREQ / 10000000); i++)
- ;
-}
-#endif
-
-#ifdef CONFIG_SYS_TIMER_0
-microblaze_timer_t *tmr = (microblaze_timer_t *) (CONFIG_SYS_TIMER_0_ADDR);
-
-void timer_isr (void *arg)
+static void timer_isr(void *arg)
{
timestamp++;
tmr->control = tmr->control | TIMER_INTERRUPT;
int timer_init (void)
{
- tmr->loadreg = CONFIG_SYS_TIMER_0_PRELOAD;
- tmr->control = TIMER_INTERRUPT | TIMER_RESET;
- tmr->control =
- TIMER_ENABLE | TIMER_ENABLE_INTR | TIMER_RELOAD | TIMER_DOWN_COUNT;
- timestamp = 0;
- install_interrupt_handler (CONFIG_SYS_TIMER_0_IRQ, timer_isr, (void *)tmr);
+ int irq = -1;
+ u32 preload = 0;
+ u32 ret = 0;
+
+#if defined(CONFIG_SYS_TIMER_0_ADDR) && defined(CONFIG_SYS_INTC_0_NUM)
+ preload = XILINX_CLOCK_FREQ / CONFIG_SYS_HZ;
+ irq = CONFIG_SYS_TIMER_0_IRQ;
+ tmr = (microblaze_timer_t *) (CONFIG_SYS_TIMER_0_ADDR);
+#endif
+
+ if (tmr && preload && irq >= 0) {
+ tmr->loadreg = preload;
+ tmr->control = TIMER_INTERRUPT | TIMER_RESET;
+ tmr->control = TIMER_ENABLE | TIMER_ENABLE_INTR |\
+ TIMER_RELOAD | TIMER_DOWN_COUNT;
+ timestamp = 0;
+ ret = install_interrupt_handler (irq, timer_isr, (void *)tmr);
+ if (ret)
+ tmr = NULL;
+ }
+
+ /* No problem if timer is not found/initialized */
return 0;
}
-#endif
/*
* This function is derived from PowerPC code (read timebase as long long).
.data ALIGN(0x4):
{
__data_start = .;
+ dts/libdts.o (.data)
*(.data)
__data_end = .;
}
unsigned long precon_buf_idx; /* Pre-Console buffer index */
#endif
unsigned long env_addr; /* Address of Environment struct */
+ const void *fdt_blob; /* Our device tree, NULL if none */
unsigned long env_valid; /* Checksum of Environment valid? */
unsigned long fb_base; /* base address of frame buffer */
void **jt; /* jump table */
int count; /* number of interrupt */
};
-void install_interrupt_handler (int irq, interrupt_handler_t * hdlr,
+/**
+ * Register and unregister interrupt handler rutines
+ *
+ * @param irq IRQ number
+ * @param hdlr Interrupt handler rutine
+ * @param arg Pointer to argument which is passed to int. handler rutine
+ * @return 0 if registration pass, 1 if unregistration pass,
+ * or an error code < 0 otherwise
+ */
+int install_interrupt_handler(int irq, interrupt_handler_t *hdlr,
void *arg);
int interrupts_init(void);
int loadreg; /* load register TLR */
int counter; /* timer/counter register */
} microblaze_timer_t;
+
+int timer_init(void);
+
extern char __end[];
extern char __text_start[];
+/* Microblaze board initialization function */
+void board_init(void);
+
#endif /* __ASM_MICROBLAZE_PROCESSOR_H */
#include <stdio_dev.h>
#include <serial.h>
#include <net.h>
+#include <linux/compiler.h>
#include <asm/processor.h>
#include <asm/microblaze_intc.h>
+#include <fdtdec.h>
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_SYS_GPIO_0
-extern int gpio_init (void);
-#endif
-#ifdef CONFIG_SYS_TIMER_0
-extern int timer_init (void);
-#endif
-#ifdef CONFIG_SYS_FSL_2
-extern void fsl_init2 (void);
-#endif
-
/*
* All attempts to come up with a "common" initialization sequence
* that works for all boards and architectures failed: some of the
init_fnc_t *init_sequence[] = {
env_init,
+#ifdef CONFIG_OF_CONTROL
+ fdtdec_check_fdt,
+#endif
serial_init,
console_init_f,
-#ifdef CONFIG_SYS_GPIO_0
- gpio_init,
-#endif
interrupts_init,
-#ifdef CONFIG_SYS_TIMER_0
timer_init,
-#endif
-#ifdef CONFIG_SYS_FSL_2
- fsl_init2,
-#endif
NULL,
};
unsigned long monitor_flash_len;
-void board_init (void)
+void board_init_f(ulong not_used)
{
bd_t *bd;
init_fnc_t **init_fnc_ptr;
gd = (gd_t *) (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET);
bd = (bd_t *) (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET \
- GENERATED_BD_INFO_SIZE);
- char *s;
+ __maybe_unused char *s;
#if defined(CONFIG_CMD_FLASH)
ulong flash_size = 0;
#endif
monitor_flash_len = __end - __text_start;
+#ifdef CONFIG_OF_EMBED
+ /* Get a pointer to the FDT */
+ gd->fdt_blob = _binary_dt_dtb_start;
+#elif defined CONFIG_OF_SEPARATE
+ /* FDT is at end of image */
+ gd->fdt_blob = (void *)__end;
+#endif
+ /* Allow the early environment to override the fdt address */
+ gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16,
+ (uintptr_t)gd->fdt_blob);
+
/*
* The Malloc area is immediately below the monitor copy in DRAM
* aka CONFIG_SYS_MONITOR_BASE - Note there is no need for reloc_off
}
}
+#ifdef CONFIG_OF_CONTROL
+ /* For now, put this check after the console is ready */
+ if (fdtdec_prepare_fdt()) {
+ panic("** CONFIG_OF_CONTROL defined but no FDT - please see "
+ "doc/README.fdt-control");
+ } else
+ printf("DTB: 0x%x\n", (u32)gd->fdt_blob);
+#endif
+
puts ("SDRAM :\n");
printf ("\t\tIcache:%s\n", icache_status() ? "ON" : "OFF");
printf ("\t\tDcache:%s\n", dcache_status() ? "ON" : "OFF");
#if defined(CONFIG_CMD_FLASH)
puts ("Flash: ");
bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
- if (0 < (flash_size = flash_init ())) {
- bd->bi_flashsize = flash_size;
- bd->bi_flashoffset = CONFIG_SYS_FLASH_BASE + flash_size;
+ flash_size = flash_init();
+ if (bd->bi_flashstart && flash_size > 0) {
# ifdef CONFIG_SYS_FLASH_CHECKSUM
print_size (flash_size, "");
/*
s = getenv ("flashchecksum");
if (s && (*s == 'y')) {
printf (" CRC: %08X",
- crc32 (0, (const unsigned char *) CONFIG_SYS_FLASH_BASE, flash_size)
+ crc32(0, (const u8 *)bd->bi_flashstart,
+ flash_size)
);
}
putc ('\n');
# else /* !CONFIG_SYS_FLASH_CHECKSUM */
print_size (flash_size, "\n");
# endif /* CONFIG_SYS_FLASH_CHECKSUM */
+ bd->bi_flashsize = flash_size;
+ bd->bi_flashoffset = bd->bi_flashstart + flash_size;
} else {
puts ("Flash init FAILED");
bd->bi_flashstart = 0;
/* Initialize the console (after the relocation and devices init) */
console_init_r();
+ board_init();
+
/* Initialize from environment */
load_addr = getenv_ulong("loadaddr", 16, load_addr);
CROSS_COMPILE ?= mips_4KC-
-CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds
+# Handle special prefix in ELDK 4.0 toolchain
+ifneq (,$(findstring 4KCle,$(CROSS_COMPILE)))
+ENDIANNESS := -EL
+endif
+
+ifdef CONFIG_SYS_LITTLE_ENDIAN
+ENDIANNESS := -EL
+endif
+
+ifdef CONFIG_SYS_BIG_ENDIAN
+ENDIANNESS := -EB
+endif
+
+# Default to EB if no endianess is configured
+ENDIANNESS ?= -EB
PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__
# On the other hand, we want PIC in the U-Boot code to relocate it from ROM
# to RAM. $28 is always used as gp.
#
-PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic
+PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic $(ENDIANNESS)
PLATFORM_CPPFLAGS += -msoft-float
-PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib
+PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib $(ENDIANNESS)
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
LDFLAGS_FINAL += --gc-sections
#
MIPSFLAGS := -march=mips32r2
-# Handle special prefix in ELDK 4.0 toolchain
-ifneq (,$(findstring 4KCle,$(CROSS_COMPILE)))
-ENDIANNESS := -EL
-endif
+PLATFORM_CPPFLAGS += $(MIPSFLAGS)
-ifdef CONFIG_SYS_LITTLE_ENDIAN
-ENDIANNESS := -EL
-endif
-
-ifdef CONFIG_SYS_BIG_ENDIAN
-ENDIANNESS := -EB
-endif
-
-# Default to EB if no endianess is configured
-ENDIANNESS ?= -EB
-
-PLATFORM_CPPFLAGS += $(MIPSFLAGS) $(ENDIANNESS)
-PLATFORM_LDFLAGS += $(ENDIANNESS)
+CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds
# MA 02111-1307 USA
#
-PLATFORM_CPPFLAGS += -march=mips32 -EL
-PLATFORM_LDFLAGS += -EL
+PLATFORM_CPPFLAGS += -march=mips32
+
+CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds
writew(100, &wdt->tdr); /* wdt_set_data(100) */
writew(0, &wdt->tcnt); /* wdt_set_count(0); */
- writew(TCU_TSSR_WDTSC, &tcu->tscr); /* tcu_start_wdt_clock */
+ writel(TCU_TSSR_WDTSC, &tcu->tscr); /* tcu_start_wdt_clock */
writeb(readb(&wdt->tcer) | WDT_TCER_TCEN, &wdt->tcer); /* wdt start */
while (1)
void reset_timer_masked(void)
{
/* reset time */
- gd->lastinc = readw(&tcu->tcnt0);
+ gd->lastinc = readl(&tcu->tcnt0);
gd->tbl = 0;
}
ulong get_timer_masked(void)
{
- ulong now = readw(&tcu->tcnt0);
+ ulong now = readl(&tcu->tcnt0);
if (gd->lastinc <= now)
gd->tbl += now - gd->lastinc; /* normal mode */
int timer_init(void)
{
- writew(TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN, &tcu->tcsr0);
+ writel(TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN, &tcu->tcsr0);
- writew(0, &tcu->tcnt0);
- writew(0, &tcu->tdhr0);
- writew(TIMER_FDATA, &tcu->tdfr0);
+ writel(0, &tcu->tcnt0);
+ writel(0, &tcu->tdhr0);
+ writel(TIMER_FDATA, &tcu->tdfr0);
/* mask irqs */
writel((1 << TIMER_CHAN) | (1 << (TIMER_CHAN + 16)), &tcu->tmsr);
LIB = $(obj)lib$(ARCH).o
+## Build a couple of necessary functions into a private libgcc
+LIBGCC = $(obj)libgcc.o
+GLSOBJS += ashldi3.o
+GLSOBJS += ashrdi3.o
+GLSOBJS += lshrdi3.o
+LGOBJS := $(addprefix $(obj),$(GLSOBJS))
+
SOBJS-y +=
COBJS-y += board.o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
+# Always build libmips.o
+TARGETS := $(LIB)
+
+# Build private libgcc only when asked for
+ifdef USE_PRIVATE_LIBGCC
+TARGETS += $(LIBGCC)
+endif
+
+all: $(TARGETS)
+
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
+$(LIBGCC): $(obj).depend $(LGOBJS)
+ $(call cmd_link_o_target, $(LGOBJS))
+
#########################################################################
# defines $(obj).depend target
--- /dev/null
+#include "libgcc.h"
+
+long long __ashldi3(long long u, word_type b)
+{
+ DWunion uu, w;
+ word_type bm;
+
+ if (b == 0)
+ return u;
+
+ uu.ll = u;
+ bm = 32 - b;
+
+ if (bm <= 0) {
+ w.s.low = 0;
+ w.s.high = (unsigned int) uu.s.low << -bm;
+ } else {
+ const unsigned int carries = (unsigned int) uu.s.low >> bm;
+
+ w.s.low = (unsigned int) uu.s.low << b;
+ w.s.high = ((unsigned int) uu.s.high << b) | carries;
+ }
+
+ return w.ll;
+}
--- /dev/null
+#include "libgcc.h"
+
+long long __ashrdi3(long long u, word_type b)
+{
+ DWunion uu, w;
+ word_type bm;
+
+ if (b == 0)
+ return u;
+
+ uu.ll = u;
+ bm = 32 - b;
+
+ if (bm <= 0) {
+ /* w.s.high = 1..1 or 0..0 */
+ w.s.high =
+ uu.s.high >> 31;
+ w.s.low = uu.s.high >> -bm;
+ } else {
+ const unsigned int carries = (unsigned int) uu.s.high << bm;
+
+ w.s.high = uu.s.high >> b;
+ w.s.low = ((unsigned int) uu.s.low >> b) | carries;
+ }
+
+ return w.ll;
+}
--- /dev/null
+#ifndef __ASM_LIBGCC_H
+#define __ASM_LIBGCC_H
+
+#include <asm/byteorder.h>
+
+typedef int word_type __attribute__ ((mode (__word__)));
+
+#ifdef __BIG_ENDIAN
+struct DWstruct {
+ int high, low;
+};
+#elif defined(__LITTLE_ENDIAN)
+struct DWstruct {
+ int low, high;
+};
+#else
+#error I feel sick.
+#endif
+
+typedef union {
+ struct DWstruct s;
+ long long ll;
+} DWunion;
+
+#endif /* __ASM_LIBGCC_H */
--- /dev/null
+#include "libgcc.h"
+
+long long __lshrdi3(long long u, word_type b)
+{
+ DWunion uu, w;
+ word_type bm;
+
+ if (b == 0)
+ return u;
+
+ uu.ll = u;
+ bm = 32 - b;
+
+ if (bm <= 0) {
+ w.s.high = 0;
+ w.s.low = (unsigned int) uu.s.high >> -bm;
+ } else {
+ const unsigned int carries = (unsigned int) uu.s.high << bm;
+
+ w.s.high = (unsigned int) uu.s.high >> b;
+ w.s.low = ((unsigned int) uu.s.low >> b) | carries;
+ }
+
+ return w.ll;
+}
unsigned long bi_vcofreq; /* VCO Freq, in MHz */
#endif
unsigned long bi_bootflags; /* boot / reboot flag (Unused) */
+ unsigned long bi_ip_addr; /* IP Address */
unsigned char bi_enetaddr[6]; /* OLD: see README.enetaddr */
unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
unsigned long bi_intfreq; /* Internal Freq, in MHz */
*/
.globl wait_ticks
wait_ticks:
- mflr r8 /* save link register */
+ stwu r1, -16(r1)
+ mflr r0 /* save link register */
+ stw r0, 20(r1) /* Use r0 or GDB will be unhappy */
mr r7, r3 /* save tick count */
bl get_ticks /* Get start time */
subfe. r3, r3, r6
bge 1b /* Loop until time expired */
- mtlr r8 /* restore link register */
+ mtlr r0 /* restore link register */
+ addi r1,r1,16
blr
for (irq = 0; irq < NR_IRQS; irq++) {
if (irq_handlers[irq].handler != NULL) {
- printf("%02d %08lx %08lx %ld\n", irq,
- (unsigned int)irq_handlers[irq].handler,
- (unsigned int)irq_handlers[irq].arg,
+ printf("%02d %p %p %d\n", irq,
+ irq_handlers[irq].handler,
+ irq_handlers[irq].arg,
irq_handlers[irq].count);
}
}
for (irq = 0; irq < NR_IRQS; irq++) {
if (irq_handlers[irq].handler != NULL) {
- printf("%02d %08lx %08lx %ld\n", irq,
- (unsigned int)irq_handlers[irq].handler,
- (unsigned int)irq_handlers[irq].arg,
+ printf("%02d %p %p %d\n", irq,
+ irq_handlers[irq].handler,
+ irq_handlers[irq].arg,
irq_handlers[irq].count);
}
}
void board_init_f(ulong bootflag)
{
bd_t *bd;
- unsigned char *s;
init_fnc_t **init_fnc_ptr;
int j;
+++ /dev/null
-/*
- * (C) Copyright 2005-2007
- * Samsung Electronics.
- * Kyungmin Park <kyungmin.park@samsung.com>
- *
- * Derived from omap2420
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <netdev.h>
-#include <asm/arch/omap2420.h>
-#include <asm/io.h>
-#include <asm/arch/bits.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/sys_info.h>
-#include <asm/arch/mem.h>
-#include <asm/mach-types.h>
-
-void wait_for_command_complete(unsigned int wd_base);
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define write_config_reg(reg, value) \
-do { \
- writeb(value, reg); \
-} while (0)
-
-#define mask_config_reg(reg, mask) \
-do { \
- char value = readb(reg) & ~(mask); \
- writeb(value, reg); \
-} while (0)
-
-/*******************************************************
- * Routine: delay
- * Description: spinning delay to use before udelay works
- ******************************************************/
-static inline void delay(unsigned long loops)
-{
- __asm__("1:\n" "subs %0, %1, #1\n"
- "bne 1b":"=r" (loops):"0"(loops));
-}
-
-/*****************************************
- * Routine: board_init
- * Description: Early hardware init.
- *****************************************/
-int board_init(void)
-{
- gpmc_init(); /* in SRAM or SDRM, finish GPMC */
-
- gd->bd->bi_arch_number = 919;
- /* adress of boot parameters */
- gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0 + 0x100);
-
- return 0;
-}
-
-/**********************************************************
- * Routine: s_init
- * Description: Does early system init of muxing and clocks.
- * - Called path is with sram stack.
- **********************************************************/
-void s_init(void)
-{
- watchdog_init();
- set_muxconf_regs();
- delay(100);
-
- peripheral_enable();
- icache_enable();
-}
-
-/*******************************************************
- * Routine: misc_init_r
- * Description: Init ethernet (done here so udelay works)
- ********************************************************/
-int misc_init_r(void)
-{
- return (0);
-}
-
-/****************************************
- * Routine: watchdog_init
- * Description: Shut down watch dogs
- *****************************************/
-void watchdog_init(void)
-{
- /* There are 4 watch dogs. 1 secure, and 3 general purpose.
- * The ROM takes care of the secure one. Of the 3 GP ones,
- * 1 can reset us directly, the other 2 only generate MPU interrupts.
- */
- __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
- wait_for_command_complete(WD2_BASE);
- __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
-
-#define MPU_WD_CLOCKED 1
-#if MPU_WD_CLOCKED
- /* value 0x10 stick on aptix, BIT4 polarity seems oppsite */
- __raw_writel(WD_UNLOCK1, WD3_BASE + WSPR);
- wait_for_command_complete(WD3_BASE);
- __raw_writel(WD_UNLOCK2, WD3_BASE + WSPR);
-
- __raw_writel(WD_UNLOCK1, WD4_BASE + WSPR);
- wait_for_command_complete(WD4_BASE);
- __raw_writel(WD_UNLOCK2, WD4_BASE + WSPR);
-#endif
-}
-
-/******************************************************
- * Routine: wait_for_command_complete
- * Description: Wait for posting to finish on watchdog
- ******************************************************/
-void wait_for_command_complete(unsigned int wd_base)
-{
- int pending = 1;
- do {
- pending = __raw_readl(wd_base + WWPS);
- } while (pending);
-}
-
-/*******************************************************************
- * Routine:board_eth_init
- * Description: take the Ethernet controller out of reset and wait
- * for the EEPROM load to complete.
- ******************************************************************/
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_LAN91C96
- int cnt = 20;
-
- __raw_writeb(0x03, OMAP2420_CTRL_BASE + 0x0f2); /*protect->gpio74 */
-
- __raw_writew(0x0, LAN_RESET_REGISTER);
- do {
- __raw_writew(0x1, LAN_RESET_REGISTER);
- udelay(100);
- if (cnt == 0)
- goto eth_reset_err_out;
- --cnt;
- } while (__raw_readw(LAN_RESET_REGISTER) != 0x1);
-
- cnt = 20;
-
- do {
- __raw_writew(0x0, LAN_RESET_REGISTER);
- udelay(100);
- if (cnt == 0)
- goto eth_reset_err_out;
- --cnt;
- } while (__raw_readw(LAN_RESET_REGISTER) != 0x0000);
- udelay(1000);
-
- mask_config_reg(ETH_CONTROL_REG, 0x01);
- udelay(1000);
- rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
-eth_reset_err_out:
-#endif
- return rc;
-}
-
-/**********************************************
- * Routine: dram_init
- * Description: sets uboots idea of sdram size
- **********************************************/
-int dram_init(void)
-{
- unsigned int size;
- u32 mtype, btype;
-#define NOT_EARLY 0
-
- btype = get_board_type();
- mtype = get_mem_type();
-
- display_board_info(btype);
-
- if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
- /* init other chip select */
- do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY);
- }
-
- size = get_sdr_cs_size(SDRC_CS0_OSET);
-
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = size;
-#if CONFIG_NR_DRAM_BANKS > 1
- size = get_sdr_cs_size(SDRC_CS1_OSET);
-
- gd->bd->bi_dram[1].start = gd->bd->bi_dram[0].start +
- gd->bd->bi_dram[0].size;
- gd->bd->bi_dram[1].size = size;
-#endif
-
- return 0;
-}
-
-/**********************************************************
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers
- * specific to the hardware
- *********************************************************/
-void set_muxconf_regs(void)
-{
- muxSetupSDRC();
- muxSetupGPMC();
- muxSetupUsb0(); /* USB Device */
- muxSetupUsbHost(); /* USB Host */
- muxSetupUART1();
- muxSetupLCD();
- muxSetupMMCSD();
- muxSetupTouchScreen();
-}
-
-/*****************************************************************
- * Routine: peripheral_enable
- * Description: Enable the clks & power for perifs (GPT2, UART1,...)
- ******************************************************************/
-void peripheral_enable(void)
-{
- unsigned int v, if_clks = 0, func_clks = 0;
-
- /* Enable GP2 timer. */
- if_clks |= BIT4 | BIT3;
- func_clks |= BIT4 | BIT3;
- /* Sys_clk input OMAP2420_GPT2 */
- v = __raw_readl(CM_CLKSEL2_CORE) | 0x4 | 0x2;
- __raw_writel(v, CM_CLKSEL2_CORE);
- __raw_writel(0x1, CM_CLKSEL_WKUP);
-
-#ifdef CONFIG_SYS_NS16550
- /* Enable UART1 clock */
- func_clks |= BIT21;
- if_clks |= BIT21;
-#endif
- /* Interface clocks on */
- v = __raw_readl(CM_ICLKEN1_CORE) | if_clks;
- __raw_writel(v, CM_ICLKEN1_CORE);
- /* Functional Clocks on */
- v = __raw_readl(CM_FCLKEN1_CORE) | func_clks;
- __raw_writel(v, CM_FCLKEN1_CORE);
- delay(1000);
-
-#ifndef KERNEL_UPDATED
- {
-#define V1 0xffffffff
-#define V2 0x00000007
-
- __raw_writel(V1, CM_FCLKEN1_CORE);
- __raw_writel(V2, CM_FCLKEN2_CORE);
- __raw_writel(V1, CM_ICLKEN1_CORE);
- __raw_writel(V1, CM_ICLKEN2_CORE);
- }
-#endif
-}
-
-/****************************************
- * Routine: muxSetupUsb0 (ostboot)
- * Description: Setup usb muxing
- *****************************************/
-void muxSetupUsb0(void)
-{
- mask_config_reg(CONTROL_PADCONF_USB0_PUEN, 0x1f);
- mask_config_reg(CONTROL_PADCONF_USB0_VP, 0x1f);
- mask_config_reg(CONTROL_PADCONF_USB0_VM, 0x1f);
- mask_config_reg(CONTROL_PADCONF_USB0_RCV, 0x1f);
- mask_config_reg(CONTROL_PADCONF_USB0_TXEN, 0x1f);
- mask_config_reg(CONTROL_PADCONF_USB0_SE0, 0x1f);
- mask_config_reg(CONTROL_PADCONF_USB0_DAT, 0x1f);
-}
-
-/****************************************
- * Routine: muxSetupUSBHost (ostboot)
- * Description: Setup USB Host muxing
- *****************************************/
-void muxSetupUsbHost(void)
-{
- /* V19 */
- write_config_reg(CONTROL_PADCONF_USB1_RCV, 1);
- /* W20 */
- write_config_reg(CONTROL_PADCONF_USB1_TXEN, 1);
- /* N14 */
- write_config_reg(CONTROL_PADCONF_GPIO69, 3);
- /* P15 */
- write_config_reg(CONTROL_PADCONF_GPIO70, 3);
- /* L18 */
- write_config_reg(CONTROL_PADCONF_GPIO102, 3);
- /* L19 */
- write_config_reg(CONTROL_PADCONF_GPIO103, 3);
- /* K15 */
- write_config_reg(CONTROL_PADCONF_GPIO104, 3);
- /* K14 */
- write_config_reg(CONTROL_PADCONF_GPIO105, 3);
-}
-
-/****************************************
- * Routine: muxSetupUART1 (ostboot)
- * Description: Set up uart1 muxing
- *****************************************/
-void muxSetupUART1(void)
-{
- /* UART1_CTS pin configuration, PIN = D21, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_UART1_CTS, 0);
- /* UART1_RTS pin configuration, PIN = H21, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_UART1_RTS, 0);
- /* UART1_TX pin configuration, PIN = L20, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_UART1_TX, 0);
- /* UART1_RX pin configuration, PIN = T21, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_UART1_RX, 0);
-}
-
-/****************************************
- * Routine: muxSetupLCD (ostboot)
- * Description: Setup lcd muxing
- *****************************************/
-void muxSetupLCD(void)
-{
- /* LCD_D0 pin configuration, PIN = Y7, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_D0, 0);
- /* LCD_D1 pin configuration, PIN = P10 , Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_D1, 0);
- /* LCD_D2 pin configuration, PIN = V8, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_D2, 0);
- /* LCD_D3 pin configuration, PIN = Y8, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_D3, 0);
- /* LCD_D4 pin configuration, PIN = W8, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_D4, 0);
- /* LCD_D5 pin configuration, PIN = R10, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_D5, 0);
- /* LCD_D6 pin configuration, PIN = Y9, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_D6, 0);
- /* LCD_D7 pin configuration, PIN = V9, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_D7, 0);
- /* LCD_D8 pin configuration, PIN = W9, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_D8, 0);
- /* LCD_D9 pin configuration, PIN = P11, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_D9, 0);
- /* LCD_D10 pin configuration, PIN = V10, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_D10, 0);
- /* LCD_D11 pin configuration, PIN = Y10, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_D11, 0);
- /* LCD_D12 pin configuration, PIN = W10, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_D12, 0);
- /* LCD_D13 pin configuration, PIN = R11, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_D13, 0);
- /* LCD_D14 pin configuration, PIN = V11, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_D14, 0);
- /* LCD_D15 pin configuration, PIN = W11, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_D15, 0);
- /* LCD_D16 pin configuration, PIN = P12, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_D16, 0);
- /* LCD_D17 pin configuration, PIN = R12, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_D17, 0);
- /* LCD_PCLK pin configuration, PIN = W6, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_PCLK, 0);
- /* LCD_VSYNC pin configuration, PIN = V7, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_VSYNC, 0);
- /* LCD_HSYNC pin configuration, PIN = Y6, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_HSYNC, 0);
- /* LCD_ACBIAS pin configuration, PIN = W7, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_DSS_ACBIAS, 0);
-}
-
-/****************************************
- * Routine: muxSetupMMCSD (ostboot)
- * Description: set up MMC muxing
- *****************************************/
-void muxSetupMMCSD(void)
-{
- /* SDMMC_CLKI pin configuration, PIN = H15, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_MMC_CLKI, 0);
- /* SDMMC_CLKO pin configuration, PIN = G19, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_MMC_CLKO, 0);
- /* SDMMC_CMD pin configuration, PIN = H18, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_MMC_CMD, 0);
- /* SDMMC_DAT0 pin configuration, PIN = F20, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_MMC_DAT0, 0);
- /* SDMMC_DAT1 pin configuration, PIN = H14, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_MMC_DAT1, 0);
- /* SDMMC_DAT2 pin configuration, PIN = E19, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_MMC_DAT2, 0);
- /* SDMMC_DAT3 pin configuration, PIN = D19, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_MMC_DAT3, 0);
- /* SDMMC_DDIR0 pin configuration, PIN = F19, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR0, 0);
- /* SDMMC_DDIR1 pin configuration, PIN = E20, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR1, 0);
- /* SDMMC_DDIR2 pin configuration, PIN = F18, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR2, 0);
- /* SDMMC_DDIR3 pin configuration, PIN = E18, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR3, 0);
- /* SDMMC_CDIR pin configuration, PIN = G18, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_MMC_CMD_DIR, 0);
-}
-
-/******************************************
- * Routine: muxSetupTouchScreen (ostboot)
- * Description: Set up touch screen muxing
- *******************************************/
-void muxSetupTouchScreen(void)
-{
- /* SPI1_CLK pin configuration, PIN = U18, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_SPI1_CLK, 0);
- /* SPI1_MOSI pin configuration, PIN = V20, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_SPI1_SIMO, 0);
- /* SPI1_MISO pin configuration, PIN = T18, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_SPI1_SOMI, 0);
- /* SPI1_nCS0 pin configuration, PIN = U19, Mode = 0, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_SPI1_NCS0, 0);
-#define CONTROL_PADCONF_GPIO85 CONTROL_PADCONF_SPI1_NCS1
- /* PEN_IRQ pin configuration, PIN = N15, Mode = 3, PUPD=Disabled */
- write_config_reg(CONTROL_PADCONF_GPIO85, 3);
-}
-
-/***************************************************************
- * Routine: muxSetupGPMC (ostboot)
- * Description: Configures balls which cam up in protected mode
- ***************************************************************/
-void muxSetupGPMC(void)
-{
- /* gpmc_io_dir, MCR */
- volatile unsigned int *MCR = (unsigned int *) 0x4800008C;
- *MCR = 0x19000000;
-
- /* NOR FLASH CS0 */
- /* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode 0; Byte-3 */
- write_config_reg(CONTROL_PADCONF_GPMC_D2_BYTE3, 0);
- /* MPDB(Multi Port Debug Port) CS1 */
- /* signal - gpmc_ncs1; pin - N8; offset - 0x008D; mode 0; Byte-1 */
- write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE1, 0);
- /* signal - Gpmc_ncs2; pin - E2; offset - 0x008E; mode 0; Byte-2 */
- write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE2, 0);
- /* signal - Gpmc_ncs3; pin - N2; offset - 0x008F; mode 0; Byte-3 */
- write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE3, 0);
- /* signal - Gpmc_ncs4; pin - ??; offset - 0x0090; mode 0; Byte-4 */
- write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE4, 0);
- /* signal - Gpmc_ncs5; pin - ??; offset - 0x0091; mode 0; Byte-5 */
- write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE5, 0);
- /* signal - Gpmc_ncs6; pin - ??; offset - 0x0092; mode 0; Byte-6 */
- write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE6, 0);
- /* signal - Gpmc_ncs7; pin - ??; offset - 0x0093; mode 0; Byte-7 */
- write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE7, 0);
-}
-
-/****************************************************************
- * Routine: muxSetupSDRC (ostboot)
- * Description: Configures balls which come up in protected mode
- ****************************************************************/
-void muxSetupSDRC(void)
-{
- /* It's set by IPL */
-}
+++ /dev/null
-#
-# (C) Copyright 2005-2007
-# Samsung Electronics
-#
-# Samsung December board with OMAP2420 (ARM1136) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# December has 1 bank of 128MB mDDR-SDRAM on CS0
-# December has 1 bank of 00MB mDDR-SDRAM on CS1
-# Physical Address:
-# 8000'0000 (bank0)
-# A000/0000 (bank1) ES2 will be configurable
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-# For use with external or internal boots.
-CONFIG_SYS_TEXT_BASE = 0x83e80000
-
-# Used with full SRAM boot.
-# This is either with a GP system or a signed boot image.
-# easiest, and safest way to go if you can.
-#CONFIG_SYS_TEXT_BASE = 0x40270000
-
-# Handy to get symbols to debug ROM version.
-#CONFIG_SYS_TEXT_BASE = 0x0
-#CONFIG_SYS_TEXT_BASE = 0x08000000
+++ /dev/null
-/*
- * Board specific setup info
- *
- * (C) Copyright 2005-2007
- * Samsung Electronics,
- * Kyungmin Park <kyungmin.park@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/omap2420.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/clocks.h>
-#include "mem.h"
-
-#define APOLLON_CS0_BASE 0x00000000
-
-#ifdef PRCM_CONFIG_I
-#define SDRC_ACTIM_CTRLA_0_VAL 0x7BA35907
-#define SDRC_ACTIM_CTRLB_0_VAL 0x00000013
-#define SDRC_RFR_CTRL_0_VAL 0x00044C01
-#elif defined(PRCM_CONFIG_II)
-#define SDRC_ACTIM_CTRLA_0_VAL 0x4A59B485
-#define SDRC_ACTIM_CTRLB_0_VAL 0x0000000C
-#define SDRC_RFR_CTRL_0_VAL 0x00030001
-#endif
-
-#define SDRAM_BASE_ADDRESS 0x80008000
-
-_TEXT_BASE:
- .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
-
-.globl lowlevel_init
-lowlevel_init:
-
-#ifdef CONFIG_SYS_NOR_BOOT
- /* Check running in SDRAM */
- mov r0, pc, lsr #28
- cmp r0, #8
- beq prcm_setup
-
-flash_setup:
- /* In Flash */
- ldr r0, =WD2_BASE
- ldr r1, =WD_UNLOCK1
- str r1, [r0, #WSPR]
-
- ldr r1, =WD_UNLOCK2
- str r1, [r0, #WSPR]
-
- /* Pin muxing for SDRC */
- mov r1, #0x00
- ldr r0, =0x480000A1 /* ball C12, mode 0 */
- strb r1, [r0]
-
- ldr r0, =0x48000032 /* ball D11, mode 0 */
- strb r1, [r0]
-
- ldr r0, =0x480000A3 /* ball B13, mode 0 */
- strb r1, [r0]
-
- /* SDRC setting */
- ldr r0, =OMAP2420_SDRC_BASE
- ldr r1, =0x00000010
- str r1, [r0, #0x10]
-
- ldr r1, =0x00000100
- str r1, [r0, #0x44]
-
- /* SDRC CS0 configuration */
- ldr r1, =0x00d04011
- str r1, [r0, #0x80]
-
- ldr r1, =SDRC_ACTIM_CTRLA_0_VAL
- str r1, [r0, #0x9C]
-
- ldr r1, =SDRC_ACTIM_CTRLB_0_VAL
- str r1, [r0, #0xA0]
-
- ldr r1, =SDRC_RFR_CTRL_0_VAL
- str r1, [r0, #0xA4]
-
- ldr r1, =0x00000041
- str r1, [r0, #0x70]
-
- /* Manual command sequence */
- ldr r1, =0x00000007
- str r1, [r0, #0xA8]
-
- ldr r1, =0x00000000
- str r1, [r0, #0xA8]
-
- ldr r1, =0x00000001
- str r1, [r0, #0xA8]
-
- ldr r1, =0x00000002
- str r1, [r0, #0xA8]
- str r1, [r0, #0xA8]
-
- /*
- * CS0 SDRC Mode register
- * Burst length = 4 - DDR memory
- * Serial mode
- * CAS latency = 3
- */
- ldr r1, =0x00000032
- str r1, [r0, #0x84]
-
- /* Note: You MUST set EMR values */
- /* EMR1 & EMR2 */
- ldr r1, =0x00000000
- str r1, [r0, #0x88]
- str r1, [r0, #0x8C]
-
-#ifdef OLD_SDRC_DLLA_CTRL
- /* SDRC_DLLA_CTRL */
- ldr r1, =0x00007306
- str r1, [r0, #0x60]
-
- ldr r1, =0x00007303
- str r1, [r0, #0x60]
-#else
- /* SDRC_DLLA_CTRL */
- ldr r1, =0x00000506
- str r1, [r0, #0x60]
-
- ldr r1, =0x00000503
- str r1, [r0, #0x60]
-#endif
-
-#ifdef __BROKEN_FEATURE__
- /* SDRC_DLLB_CTRL */
- ldr r1, =0x00000506
- str r1, [r0, #0x68]
-
- ldr r1, =0x00000503
- str r1, [r0, #0x68]
-#endif
-
- /* little delay after init */
- mov r2, #0x1800
-1:
- subs r2, r2, #0x1
- bne 1b
-
- /* Setup base address */
- ldr r0, =0x00000000 /* NOR address */
- ldr r1, =SDRAM_BASE_ADDRESS /* SDRAM address */
- ldr r2, =0x20000 /* Size: 128KB */
-
-copy_loop:
- ldmia r0!, {r3-r10}
- stmia r1!, {r3-r10}
- cmp r0, r2
- ble copy_loop
-
- ldr r1, =SDRAM_BASE_ADDRESS
- mov lr, pc
- mov pc, r1
-#endif
-
-prcm_setup:
- ldr r0, =OMAP2420_CM_BASE
- ldr r1, [r0, #0x544] /* CLKSEL2_PLL */
- bic r1, r1, #0x03
- orr r1, r1, #0x02
- str r1, [r0, #0x544]
-
- ldr r1, [r0, #0x500]
- bic r1, r1, #0x03
- orr r1, r1, #0x01
- str r1, [r0, #0x500]
-
- ldr r1, [r0, #0x140]
- bic r1, r1, #0x1f
- orr r1, r1, #0x02
- str r1, [r0, #0x140]
-
-#ifdef PRCM_CONFIG_I
- ldr r1, =0x000003C3
-#else
- ldr r1, =0x00000343
-#endif
- str r1, [r0, #0x840]
-
- ldr r1, =0x00000002
- str r1, [r0, #0x340]
-
- ldr r1, =CM_CLKSEL1_CORE
-#ifdef PRCM_CONFIG_I
- ldr r2, =0x08300C44
-#else
- ldr r2, =0x04600C26
-#endif
- str r2, [r1]
-
- ldr r0, =OMAP2420_CM_BASE
- ldr r1, [r0, #0x084]
- and r1, r1, #0x01
- cmp r1, #0x01
- bne clkvalid
-
- b .
-
-clkvalid:
- mov r1, #0x01
- str r1, [r0, #0x080]
-
-waitvalid:
- ldr r1, [r0, #0x084]
- and r1, r1, #0x01
- cmp r1, #0x00
- bne waitvalid
-
- ldr r0, =CM_CLKSEL1_PLL
-#ifdef PRCM_CONFIG_I
- ldr r1, =0x01837100
-#else
- ldr r1, =0x01832100
-#endif
- str r1, [r0]
-
- ldr r0, =PRCM_CLKCFG_CTRL
- mov r1, #0x01
- str r1, [r0]
- mov r6, #0x50
-loop1:
- subs r6, r6, #0x01
- cmp r6, #0x01
- bne loop1
-
- ldr r0, =CM_CLKEN_PLL
- mov r1, #0x0f
- str r1, [r0]
-
- mov r6, #0x100
-loop2:
- subs r6, r6, #0x01
- cmp r6, #0x01
- bne loop2
-
- ldr r0, =0x48008200
- ldr r1, =0xbfffffff
- str r1, [r0]
-
- ldr r0, =0x48008210
- ldr r1, =0xfffffff9
- str r1, [r0]
-
- ldr r0, =0x4806a004
- ldr r1, =0x00
- strb r1, [r0]
-
- ldr r0, =0x4806a020
- ldr r1, =0x07
- strb r1, [r0]
-
- ldr r0, =0x4806a00c
- ldr r1, =0x83
- strb r1, [r0]
-
- ldr r0, =0x4806a000
- ldr r1, =0x1a
- strb r1, [r0]
-
- ldr r0, =0x4806a004
- ldr r1, =0x00
- strb r1, [r0]
-
- ldr r0, =0x4806a00c
- ldr r1, =0x03
- strb r1, [r0]
-
- ldr r0, =0x4806a010
- ldr r1, =0x03
- strb r1, [r0]
-
- ldr r0, =0x4806a008
- ldr r1, =0x04
- strb r1, [r0]
-
- ldr r0, =0x4806a020
- ldr r1, =0x00
- strb r1, [r0]
-
-#if 0
- ldr r0, =0x4806a000
- mov r1, #'u'
- strb r1, [r0]
-#endif
-
-#if 0
- /* LED0 OFF */
- ldr r3, =0x480000E5
- mov r4, #0x0b
- strb r4, [r3]
-#endif
-
- ldr sp, SRAM_STACK
- str ip, [sp] /* stash old link register */
- mov ip, lr /* save link reg across call */
- bl s_init /* go setup pll,mux,memory */
- ldr ip, [sp] /* restore save ip */
- mov lr, ip /* restore link reg */
-
- /* map interrupt controller */
- ldr r0, VAL_INTH_SETUP
- mcr p15, 0, r0, c15, c2, 4
-
- /* back to arch calling code */
- mov pc, lr
-
- /* the literal pools origin */
- .ltorg
-
-VAL_INTH_SETUP:
- .word PERIFERAL_PORT_BASE
-SRAM_STACK:
- .word LOW_LEVEL_SRAM_STACK
+++ /dev/null
-/*
- * (C) Copyright 2005-2007
- * Samsung Electronics,
- * Kyungmin Park <kyungmin.park@samsung.com>
- *
- * Derived from omap2420
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/omap2420.h>
-#include <asm/io.h>
-#include <asm/arch/bits.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/clocks.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/sys_info.h>
-
-#include "mem.h"
-
-/************************************************************
- * sdelay() - simple spin loop. Will be constant time as
- * its generally used in 12MHz bypass conditions only. This
- * is necessary until timers are accessible.
- *
- * not inline to increase chances its in cache when called
- *************************************************************/
-void sdelay(unsigned long loops)
-{
- __asm__("1:\n" "subs %0, %1, #1\n"
- "bne 1b":"=r" (loops):"0"(loops));
-}
-
-/********************************************************************
- * prcm_init() - inits clocks for PRCM as defined in clocks.h
- * (config II default).
- * -- called from SRAM, or Flash (using temp SRAM stack).
- ********************************************************************/
-void prcm_init(void) { }
-
-/**************************************************************************
- * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
- * command line mem=xyz use all memory with out discontigious support
- * compiled in. Could do it at the ATAG, but there really is two banks...
- * Called as part of 2nd phase DDR init.
- **************************************************************************/
-void make_cs1_contiguous(void)
-{
- u32 size, a_add_low, a_add_high;
-
- size = get_sdr_cs_size(SDRC_CS0_OSET);
- size /= SZ_32M; /* find size to offset CS1 */
- a_add_high = (size & 3) << 8; /* set up low field */
- a_add_low = (size & 0x3C) >> 2; /* set up high field */
- __raw_writel((a_add_high | a_add_low), SDRC_CS_CFG);
-
-}
-
-/********************************************************
- * mem_ok() - test used to see if timings are correct
- * for a part. Helps in gussing which part
- * we are currently using.
- *******************************************************/
-u32 mem_ok(void)
-{
- u32 val1, val2;
- u32 pattern = 0x12345678;
-
- /* clear pos A */
- __raw_writel(0x0, OMAP2420_SDRC_CS0 + 0x400);
- /* pattern to pos B */
- __raw_writel(pattern, OMAP2420_SDRC_CS0);
- /* remove pattern off the bus */
- __raw_writel(0x0, OMAP2420_SDRC_CS0 + 4);
- /* get pos A value */
- val1 = __raw_readl(OMAP2420_SDRC_CS0 + 0x400);
- val2 = __raw_readl(OMAP2420_SDRC_CS0); /* get val2 */
-
- /* see if pos A value changed */
- if ((val1 != 0) || (val2 != pattern))
- return (0);
- else
- return (1);
-}
-
-/********************************************************
- * sdrc_init() - init the sdrc chip selects CS0 and CS1
- * - early init routines, called from flash or
- * SRAM.
- *******************************************************/
-void sdrc_init(void)
-{
-#define EARLY_INIT 1
- /* only init up first bank here */
- do_sdrc_init(SDRC_CS0_OSET, EARLY_INIT);
-}
-
-/*************************************************************************
- * do_sdrc_init(): initialize the SDRAM for use.
- * -called from low level code with stack only.
- * -code sets up SDRAM timing and muxing for 2422 or 2420.
- * -optimal settings can be placed here, or redone after i2c
- * inspection of board info
- *
- * This is a bit ugly, but should handle all memory moduels
- * used with the APOLLON. The first time though this code from s_init()
- * we configure the first chip select. Later on we come back and
- * will configure the 2nd chip select if it exists.
- *
- **************************************************************************/
-void do_sdrc_init(u32 offset, u32 early)
-{
-}
-
-/*****************************************************
- * gpmc_init(): init gpmc bus
- * Init GPMC for x16, MuxMode (SDRAM in x32).
- * This code can only be executed from SRAM or SDRAM.
- *****************************************************/
-void gpmc_init(void)
-{
- u32 mux = 0, mtype, mwidth, rev, tval;
-
- rev = get_cpu_rev();
- if (rev == CPU_2420_2422_ES1)
- tval = 1;
- else
- tval = 0; /* disable bit switched meaning */
-
- /* global settings */
- __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */
- __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
- __raw_writel(tval, GPMC_TIMEOUT_CONTROL); /* timeout disable */
-#ifdef CONFIG_SYS_NAND_BOOT
- /* set nWP, disable limited addr */
- __raw_writel(0x001, GPMC_CONFIG);
-#else
- /* set nWP, disable limited addr */
- __raw_writel(0x111, GPMC_CONFIG);
-#endif
-
- /* discover bus connection from sysboot */
- if (is_gpmc_muxed() == GPMC_MUXED)
- mux = BIT9;
- mtype = get_gpmc0_type();
- mwidth = get_gpmc0_width();
-
- /* setup cs0 */
- __raw_writel(0x0, GPMC_CONFIG7_0); /* disable current map */
- sdelay(1000);
-
-#ifdef CONFIG_SYS_NOR_BOOT
- __raw_writel(APOLLON_24XX_GPMC_CONFIG1_3, GPMC_CONFIG1_0);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG2_3, GPMC_CONFIG2_0);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG3_3, GPMC_CONFIG3_0);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG4_3, GPMC_CONFIG4_0);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG5_3, GPMC_CONFIG5_0);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG6_3, GPMC_CONFIG6_0);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG7_3, GPMC_CONFIG7_0);
-#else
- __raw_writel(APOLLON_24XX_GPMC_CONFIG1_0 | mux | mtype | mwidth,
- GPMC_CONFIG1_0);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_0);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_0);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_0);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_0);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_0);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_0);
-#endif
- sdelay(2000);
-
- /* setup cs1 */
- __raw_writel(0, GPMC_CONFIG7_1); /* disable any mapping */
- sdelay(1000);
-
- __raw_writel(APOLLON_24XX_GPMC_CONFIG1_1, GPMC_CONFIG1_1);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG2_1, GPMC_CONFIG2_1);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG3_1, GPMC_CONFIG3_1);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG4_1, GPMC_CONFIG4_1);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG5_1, GPMC_CONFIG5_1);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG6_1, GPMC_CONFIG6_1);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG7_1, GPMC_CONFIG7_1);
- sdelay(2000);
-
- /* setup cs2 */
- __raw_writel(0x0, GPMC_CONFIG7_2); /* disable current map */
- sdelay(1000);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG1_0 | mux | mtype | mwidth,
- GPMC_CONFIG1_2);
- /* It's same as cs 0 */
- __raw_writel(APOLLON_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_2);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_2);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_2);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_2);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_2);
-#ifdef CONFIG_SYS_NOR_BOOT
- __raw_writel(APOLLON_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_2);
-#else
- __raw_writel(APOLLON_24XX_GPMC_CONFIG7_2, GPMC_CONFIG7_2);
-#endif
-
-#ifndef CONFIG_SYS_NOR_BOOT
- /* setup cs3 */
- __raw_writel(0, GPMC_CONFIG7_3); /* disable any mapping */
- sdelay(1000);
-
- __raw_writel(APOLLON_24XX_GPMC_CONFIG1_3, GPMC_CONFIG1_3);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG2_3, GPMC_CONFIG2_3);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG3_3, GPMC_CONFIG3_3);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG4_3, GPMC_CONFIG4_3);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG5_3, GPMC_CONFIG5_3);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG6_3, GPMC_CONFIG6_3);
- __raw_writel(APOLLON_24XX_GPMC_CONFIG7_3, GPMC_CONFIG7_3);
-#endif
-
-#ifndef ASYNC_NOR
- __raw_writew(0xaa, (APOLLON_CS3_BASE + 0xaaa));
- __raw_writew(0x55, (APOLLON_CS3_BASE + 0x554));
- __raw_writew(0xc0, (APOLLON_CS3_BASE | SYNC_NOR_VALUE));
-#endif
- sdelay(2000);
-}
+++ /dev/null
-/*
- * (C) Copyright 2005-2007
- * Samsung Electronics,
- * Kyungmin Park <kyungmin.park@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _APOLLON_OMAP24XX_MEM_H_
-#define _APOLLON_OMAP24XX_MEM_H_
-
-/* Slower full frequency range default timings for x32 operation*/
-#define APOLLON_2420_SDRC_SHARING 0x00000100
-#define APOLLON_2420_SDRC_MDCFG_0_DDR 0x00d04011
-#define APOLLON_2420_SDRC_MR_0_DDR 0x00000032
-
-/* optimized timings good for current shipping parts */
-#define APOLLON_242X_SDRC_ACTIM_CTRLA_0_100MHz 0x4A59B485
-#define APOLLON_242X_SDRC_ACTIM_CTRLB_0_100MHz 0x0000000C
-
-#define APOLLON_242X_SDRC_ACTIM_CTRLA_0_166MHz 0x7BA35907
-#define APOLLON_242X_SDRC_ACTIM_CTRLB_0_166MHz 0x00000013
-
-#define APOLLON_242X_SDRC_RFR_CTRL_100MHz 0x00030001
-#define APOLLON_242X_SDRC_RFR_CTRL_166MHz 0x00044C01
-
-#define APOLLON_242x_SDRC_DLLAB_CTRL_100MHz 0x00007306
-#define APOLLON_242x_SDRC_DLLAB_CTRL_166MHz 0x00000506
-
-#ifdef PRCM_CONFIG_I
-#define APOLLON_2420_SDRC_ACTIM_CTRLA_0 APOLLON_242X_SDRC_ACTIM_CTRLA_0_166MHz
-#define APOLLON_2420_SDRC_ACTIM_CTRLB_0 APOLLON_242X_SDRC_ACTIM_CTRLB_0_166MHz
-#define APOLLON_2420_SDRC_RFR_CTRL APOLLON_242X_SDRC_RFR_CTRL_166MHz
-#define APOLLON_2420_SDRC_DLLAB_CTRL APOLLON_242x_SDRC_DLLAB_CTRL_166MHz
-#elif PRCM_CONFIG_II
-#define APOLLON_2420_SDRC_ACTIM_CTRLA_0 APOLLON_242X_SDRC_ACTIM_CTRLA_0_100MHz
-#define APOLLON_2420_SDRC_ACTIM_CTRLB_0 APOLLON_242X_SDRC_ACTIM_CTRLB_0_100MHz
-#define APOLLON_2420_SDRC_RFR_CTRL APOLLON_242X_SDRC_RFR_CTRL_100MHz
-#define APOLLON_2420_SDRC_DLLAB_CTRL APOLLON_242x_SDRC_DLLAB_CTRL_100MHz
-#endif
-
-/* GPMC settings */
-#ifdef PRCM_CONFIG_I /* L3 at 165MHz */
-/* CS0: OneNAND */
-# define APOLLON_24XX_GPMC_CONFIG1_0 0x00000001
-# define APOLLON_24XX_GPMC_CONFIG2_0 0x000c1000
-# define APOLLON_24XX_GPMC_CONFIG3_0 0x00030400
-# define APOLLON_24XX_GPMC_CONFIG4_0 0x0b841006
-# define APOLLON_24XX_GPMC_CONFIG5_0 0x020f0c11
-# define APOLLON_24XX_GPMC_CONFIG6_0 0x00000000
-# define APOLLON_24XX_GPMC_CONFIG7_0 (0x00000e40|(APOLLON_CS0_BASE >> 24))
-
-/* CS1: Ethernet */
-# define APOLLON_24XX_GPMC_CONFIG1_1 0x00011203
-# define APOLLON_24XX_GPMC_CONFIG2_1 0x001F1F01
-# define APOLLON_24XX_GPMC_CONFIG3_1 0x00080803
-# define APOLLON_24XX_GPMC_CONFIG4_1 0x1C0b1C0a
-# define APOLLON_24XX_GPMC_CONFIG5_1 0x041F1F1F
-# define APOLLON_24XX_GPMC_CONFIG6_1 0x000004C4
-# define APOLLON_24XX_GPMC_CONFIG7_1 (0x00000F40|(APOLLON_CS1_BASE >> 24))
-
-/* CS2: OneNAND */
-/* It's same as CS0 */
-# define APOLLON_24XX_GPMC_CONFIG7_2 (0x00000e40|(APOLLON_CS2_BASE >> 24))
-
-/* CS3: NOR */
-#ifdef ASYNC_NOR
-# define APOLLON_24XX_GPMC_CONFIG1_3 0x00021201
-# define APOLLON_24XX_GPMC_CONFIG2_3 0x00121601
-# define APOLLON_24XX_GPMC_CONFIG3_3 0x00040401
-# define APOLLON_24XX_GPMC_CONFIG4_3 0x12061605
-# define APOLLON_24XX_GPMC_CONFIG5_3 0x01151317
-#else
-# define SYNC_NOR_VALUE 0x24aaa
-# define APOLLON_24XX_GPMC_CONFIG1_3 0xe5011211
-# define APOLLON_24XX_GPMC_CONFIG2_3 0x00090b01
-# define APOLLON_24XX_GPMC_CONFIG3_3 0x00020201
-# define APOLLON_24XX_GPMC_CONFIG4_3 0x09030b03
-# define APOLLON_24XX_GPMC_CONFIG5_3 0x010a0a0c
-#endif /* ASYNC_NOR */
-# define APOLLON_24XX_GPMC_CONFIG6_3 0x00000000
-# define APOLLON_24XX_GPMC_CONFIG7_3 (0x00000e40|(APOLLON_CS3_BASE >> 24))
-#endif /* endif PRCM_CONFIG_I */
-
-#ifdef PRCM_CONFIG_II /* L3 at 100MHz */
-/* CS0: OneNAND */
-# define APOLLON_24XX_GPMC_CONFIG1_0 0x00000001
-# define APOLLON_24XX_GPMC_CONFIG2_0 0x00081080
-# define APOLLON_24XX_GPMC_CONFIG3_0 0x00030300
-# define APOLLON_24XX_GPMC_CONFIG4_0 0x08041004
-# define APOLLON_24XX_GPMC_CONFIG5_0 0x020b0910
-# define APOLLON_24XX_GPMC_CONFIG6_0 0x00000000
-# define APOLLON_24XX_GPMC_CONFIG7_0 (0x00000C40|(APOLLON_CS0_BASE >> 24))
-
-/* CS1: ethernet */
-# define APOLLON_24XX_GPMC_CONFIG1_1 0x00401203
-# define APOLLON_24XX_GPMC_CONFIG2_1 0x001F1F01
-# define APOLLON_24XX_GPMC_CONFIG3_1 0x00080803
-# define APOLLON_24XX_GPMC_CONFIG4_1 0x1C091C09
-# define APOLLON_24XX_GPMC_CONFIG5_1 0x041F1F1F
-# define APOLLON_24XX_GPMC_CONFIG6_1 0x000004C4
-# define APOLLON_24XX_GPMC_CONFIG7_1 (0x00000F40|(APOLLON_CS1_BASE >> 24))
-
-/* CS2: OneNAND */
-/* It's same as CS0 */
-# define APOLLON_24XX_GPMC_CONFIG7_2 (0x00000e40|(APOLLON_CS2_BASE >> 24))
-
-/* CS3: NOR */
-#define ASYNC_NOR
-#ifdef ASYNC_NOR
-# define APOLLON_24XX_GPMC_CONFIG1_3 0x00021201
-# define APOLLON_24XX_GPMC_CONFIG2_3 0x00121601
-# define APOLLON_24XX_GPMC_CONFIG3_3 0x00040401
-# define APOLLON_24XX_GPMC_CONFIG4_3 0x12061605
-# define APOLLON_24XX_GPMC_CONFIG5_3 0x01151317
-#else
-# define SYNC_NOR_VALUE 0x24aaa
-# define APOLLON_24XX_GPMC_CONFIG1_3 0xe1001202
-# define APOLLON_24XX_GPMC_CONFIG2_3 0x00151501
-# define APOLLON_24XX_GPMC_CONFIG3_3 0x00050501
-# define APOLLON_24XX_GPMC_CONFIG4_3 0x0e070e07
-# define APOLLON_24XX_GPMC_CONFIG5_3 0x01131F1F
-#endif /* ASYNC_NOR */
-# define APOLLON_24XX_GPMC_CONFIG6_3 0x00000000
-# define APOLLON_24XX_GPMC_CONFIG7_3 (0x00000C40|(APOLLON_CS3_BASE >> 24))
-#endif /* endif PRCM_CONFIG_II */
-
-#ifdef PRCM_CONFIG_III /* L3 at 133MHz */
-# ifdef CONFIG_SYS_NAND_BOOT
-# define APOLLON_24XX_GPMC_CONFIG1_0 0x0
-# define APOLLON_24XX_GPMC_CONFIG2_0 0x00141400
-# define APOLLON_24XX_GPMC_CONFIG3_0 0x00141400
-# define APOLLON_24XX_GPMC_CONFIG4_0 0x0F010F01
-# define APOLLON_24XX_GPMC_CONFIG5_0 0x010C1414
-# define APOLLON_24XX_GPMC_CONFIG6_0 0x00000A80
-# else /* NOR boot */
-# define APOLLON_24XX_GPMC_CONFIG1_0 0x3
-# define APOLLON_24XX_GPMC_CONFIG2_0 0x00151501
-# define APOLLON_24XX_GPMC_CONFIG3_0 0x00060602
-# define APOLLON_24XX_GPMC_CONFIG4_0 0x10081008
-# define APOLLON_24XX_GPMC_CONFIG5_0 0x01131F1F
-# define APOLLON_24XX_GPMC_CONFIG6_0 0x000004c4
-# endif /* endif CONFIG_SYS_NAND_BOOT */
-# define APOLLON_24XX_GPMC_CONFIG7_0 (0x00000C40|(APOLLON_CS0_BASE >> 24))
-# define APOLLON_24XX_GPMC_CONFIG1_1 0x00011000
-# define APOLLON_24XX_GPMC_CONFIG2_1 0x001f1f01
-# define APOLLON_24XX_GPMC_CONFIG3_1 0x00080803
-# define APOLLON_24XX_GPMC_CONFIG4_1 0x1C091C09
-# define APOLLON_24XX_GPMC_CONFIG5_1 0x041f1F1F
-# define APOLLON_24XX_GPMC_CONFIG6_1 0x000004C4
-# define APOLLON_24XX_GPMC_CONFIG7_1 (0x00000F40|(APOLLON_CS1_BASE >> 24))
-#endif /* endif CONFIG_SYS_PRCM_III */
-
-#endif /* endif _APOLLON_OMAP24XX_MEM_H_ */
+++ /dev/null
-/*
- * (C) Copyright 2005-2007
- * Samsung Electronics,
- * Kyungmin Park <kyungmin.park@samsung.com>
- *
- * Derived from omap2420
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/omap2420.h>
-#include <asm/io.h>
-#include <asm/arch/bits.h>
-#include <asm/arch/mem.h> /* get mem tables */
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/sys_info.h>
-#include <i2c.h>
-
-/**************************************************************************
- * get_prod_id() - get id info from chips
- ***************************************************************************/
-static u32 get_prod_id(void)
-{
- u32 p;
- p = __raw_readl(PRODUCTION_ID); /* get production ID */
- return ((p & CPU_242X_PID_MASK) >> 16);
-}
-
-/**************************************************************************
- * get_cpu_type() - low level get cpu type
- * - no C globals yet.
- * - just looking to say if this is a 2422 or 2420 or ...
- * - to start with we will look at switch settings..
- * - 2422 id's same as 2420 for ES1 will rely on H4 board characteristics
- * (mux for 2420, non-mux for 2422).
- ***************************************************************************/
-u32 get_cpu_type(void)
-{
- u32 v;
-
- switch (get_prod_id()) {
- case 1:; /* 2420 */
- case 2:
- return (CPU_2420);
- break; /* 2420 pop */
- case 4:
- return (CPU_2422);
- break;
- case 8:
- return (CPU_2423);
- break;
- default:
- break; /* early 2420/2422's unmarked */
- }
-
- v = __raw_readl(TAP_IDCODE_REG);
- v &= CPU_24XX_ID_MASK;
- /* currently 2420 and 2422 have same id */
- if (v == CPU_2420_CHIPID) {
- if (is_gpmc_muxed() == GPMC_MUXED) /* if mux'ed */
- return (CPU_2420);
- else
- return (CPU_2422);
- } else
- return (CPU_2420); /* don't know, say 2420 */
-}
-
-/******************************************
- * get_cpu_rev(void) - extract version info
- ******************************************/
-u32 get_cpu_rev(void)
-{
- u32 v;
- v = __raw_readl(TAP_IDCODE_REG);
- v = v >> 28;
- return (v + 1); /* currently 2422 and 2420 match up */
-}
-
-/****************************************************
- * is_mem_sdr() - return 1 if mem type in use is SDR
- ****************************************************/
-u32 is_mem_sdr(void)
-{
- volatile u32 *burst = (volatile u32 *)(SDRC_MR_0 + SDRC_CS0_OSET);
- if (*burst == H4_2420_SDRC_MR_0_SDR)
- return (1);
- return (0);
-}
-
-/***********************************************************
- * get_mem_type() - identify type of mDDR part used.
- * 2422 uses stacked DDR, 2 parts CS0/CS1.
- * 2420 may have 1 or 2, no good way to know...only init 1...
- * when eeprom data is up we can select 1 more.
- *************************************************************/
-u32 get_mem_type(void)
-{
- u32 cpu, sdr = is_mem_sdr();
-
- cpu = get_cpu_type();
- if (cpu == CPU_2422 || cpu == CPU_2423)
- return (DDR_STACKED);
-
- if (get_prod_id() == 0x2)
- return (XDR_POP);
-
- if (get_board_type() == BOARD_H4_MENELAUS)
- if (sdr)
- return (SDR_DISCRETE);
- else
- return (DDR_COMBO);
- else if (sdr) /* SDP + SDR kit */
- return (SDR_DISCRETE);
- else
- return (DDR_DISCRETE); /* origional SDP */
-}
-
-/***********************************************************************
- * get_cs0_size() - get size of chip select 0/1
- ************************************************************************/
-u32 get_sdr_cs_size(u32 offset)
-{
- u32 size;
- size = __raw_readl(SDRC_MCFG_0 + offset) >> 8; /* get ram size field */
- size &= 0x2FF; /* remove unwanted bits */
- size *= SZ_2M; /* find size in MB */
- return (size);
-}
-
-/***********************************************************************
- * get_board_type() - get board type based on current production stats.
- * --- NOTE: 2 I2C EEPROMs will someday be populated with proper info.
- * when they are available we can get info from there. This should
- * be correct of all known boards up until today.
- ************************************************************************/
-u32 get_board_type(void)
-{
- return (BOARD_H4_SDP);
-}
-
-/******************************************************************
- * get_sysboot_value() - get init word settings (dip switch on h4)
- ******************************************************************/
-inline u32 get_sysboot_value(void)
-{
- return (0x00000FFF & __raw_readl(CONTROL_STATUS));
-}
-
-/***************************************************************************
- * get_gpmc0_base() - Return current address hardware will be
- * fetching from. The below effectively gives what is correct, its a bit
- * mis-leading compared to the TRM. For the most general case the mask
- * needs to be also taken into account this does work in practice.
- * - for u-boot we currently map:
- * -- 0 to nothing,
- * -- 4 to flash
- * -- 8 to enent
- * -- c to wifi
- ****************************************************************************/
-u32 get_gpmc0_base(void)
-{
- u32 b;
-
- b = __raw_readl(GPMC_CONFIG7_0);
- b &= 0x1F; /* keep base [5:0] */
- b = b << 24; /* ret 0x0b000000 */
- return (b);
-}
-
-/*****************************************************************
- * is_gpmc_muxed() - tells if address/data lines are multiplexed
- *****************************************************************/
-u32 is_gpmc_muxed(void)
-{
- u32 mux;
- mux = get_sysboot_value();
- if ((mux & (BIT0 | BIT1 | BIT2 | BIT3)) == (BIT0 | BIT2 | BIT3))
- return (GPMC_MUXED); /* NAND Boot mode */
- if (mux & BIT1) /* if mux'ed */
- return (GPMC_MUXED);
- else
- return (GPMC_NONMUXED);
-}
-
-/************************************************************************
- * get_gpmc0_type() - read sysboot lines to see type of memory attached
- ************************************************************************/
-u32 get_gpmc0_type(void)
-{
- u32 type;
- type = get_sysboot_value();
- if ((type & (BIT3 | BIT2)) == (BIT3 | BIT2))
- return (TYPE_NAND);
- else
- return (TYPE_NOR);
-}
-
-/*******************************************************************
- * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
- *******************************************************************/
-u32 get_gpmc0_width(void)
-{
- u32 width;
- width = get_sysboot_value();
- if ((width & 0xF) == (BIT3 | BIT2))
- return (WIDTH_8BIT);
- else
- return (WIDTH_16BIT);
-}
-
-/*********************************************************************
- * wait_on_value() - common routine to allow waiting for changes in
- * volatile regs.
- *********************************************************************/
-u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
-{
- u32 i = 0, val;
- do {
- ++i;
- val = __raw_readl(read_addr) & read_bit_mask;
- if (val == match_value)
- return (1);
- if (i == bound)
- return (0);
- } while (1);
-}
-
-/*********************************************************************
- * display_board_info() - print banner with board info.
- *********************************************************************/
-void display_board_info(u32 btype)
-{
- char cpu_2420[] = "2420"; /* cpu type */
- char cpu_2422[] = "2422";
- char cpu_2423[] = "2423";
- char mem_sdr[] = "mSDR"; /* memory type */
- char mem_ddr[] = "mDDR";
- char t_tst[] = "TST"; /* security level */
- char t_emu[] = "EMU";
- char t_hs[] = "HS";
- char t_gp[] = "GP";
- char unk[] = "?";
-
- char *cpu_s, *mem_s, *sec_s;
- u32 cpu, rev, sec;
-
- rev = get_cpu_rev();
- cpu = get_cpu_type();
- sec = get_device_type();
-
- if (is_mem_sdr())
- mem_s = mem_sdr;
- else
- mem_s = mem_ddr;
-
- if (cpu == CPU_2423)
- cpu_s = cpu_2423;
- else if (cpu == CPU_2422)
- cpu_s = cpu_2422;
- else
- cpu_s = cpu_2420;
-
- switch (sec) {
- case TST_DEVICE:
- sec_s = t_tst;
- break;
- case EMU_DEVICE:
- sec_s = t_emu;
- break;
- case HS_DEVICE:
- sec_s = t_hs;
- break;
- case GP_DEVICE:
- sec_s = t_gp;
- break;
- default:
- sec_s = unk;
- }
-
- printf("OMAP%s-%s revision %d\n", cpu_s, sec_s, rev - 1);
- printf("Samsung Apollon SDP Base Board + %s \n", mem_s);
-}
-
-/*************************************************************************
- * get_board_rev() - setup to pass kernel board revision information
- * 0 = 242x IP platform (first 2xx boards)
- * 1 = 242x Menelaus platfrom.
- *************************************************************************/
-u32 get_board_rev(void)
-{
- u32 rev = 0;
- u32 btype = get_board_type();
-
- if (btype == BOARD_H4_MENELAUS)
- rev = 1;
- return (rev);
-}
-
-/********************************************************
- * get_base(); get upper addr of current execution
- *******************************************************/
-u32 get_base(void)
-{
- u32 val;
- __asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
- val &= 0xF0000000;
- val >>= 28;
- return (val);
-}
-
-/********************************************************
- * get_base2(); get 2upper addr of current execution
- *******************************************************/
-u32 get_base2(void)
-{
- u32 val;
- __asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
- val &= 0xFF000000;
- val >>= 24;
- return (val);
-}
-
-/********************************************************
- * running_in_flash() - tell if currently running in
- * flash.
- *******************************************************/
-u32 running_in_flash(void)
-{
- if (get_base() < 4)
- return (1); /* in flash */
- return (0); /* running in SRAM or SDRAM */
-}
-
-/********************************************************
- * running_in_sram() - tell if currently running in
- * sram.
- *******************************************************/
-u32 running_in_sram(void)
-{
- if (get_base() == 4)
- return (1); /* in SRAM */
- return (0); /* running in FLASH or SDRAM */
-}
-
-/********************************************************
- * running_in_sdram() - tell if currently running in
- * flash.
- *******************************************************/
-u32 running_in_sdram(void)
-{
- if (get_base() > 4)
- return (1); /* in sdram */
- return (0); /* running in SRAM or FLASH */
-}
-
-/*************************************************************
- * running_from_internal_boot() - am I a signed NOR image.
- *************************************************************/
-u32 running_from_internal_boot(void)
-{
- u32 v, base;
-
- v = get_sysboot_value() & BIT3;
- base = get_base2();
- /* if running at mask rom flash address and
- * sysboot3 says this was an internal boot
- */
- if ((base == 0x08) && v)
- return (1);
- else
- return (0);
-}
-
-/*************************************************************
- * get_device_type(): tell if GP/HS/EMU/TST
- *************************************************************/
-u32 get_device_type(void)
-{
- int mode;
- mode = __raw_readl(CONTROL_STATUS) & (BIT10 | BIT9 | BIT8);
- return (mode >>= 8);
-}
--- /dev/null
+#
+# Copyright (C) 2005-2006 Atmel Corporation
+#
+# See file CREDITS for list of people who contributed to this project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB := $(obj)lib$(BOARD).o
+
+COBJS := $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright (C) 2010 Atmel Corporation
+ *
+ * Copyright (C) 2012 Andreas Bießmann <andreas.devel@googlemail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <spi.h>
+#include <netdev.h>
+
+#include <asm/io.h>
+#include <asm/sdram.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/hmatrix.h>
+#include <asm/arch/mmu.h>
+#include <asm/arch/portmux.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
+ {
+ /* Atmel AT49BV640D 8 MiB x16 NOR flash on NCS0 */
+ .virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
+ .nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
+ .phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_NONE,
+ }, {
+ /* Micron MT29F2G16AAD 256 MiB x16 NAND flash on NCS3 */
+ .virt_pgno = EBI_SRAM_CS3_BASE >> PAGE_SHIFT,
+ .nr_pages = EBI_SRAM_CS3_SIZE >> PAGE_SHIFT,
+ .phys = (EBI_SRAM_CS3_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_NONE,
+ }, {
+ /* 2x16-bit ISSI IS42S16320B 64 MiB SDRAM (128 MiB total) */
+ .virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
+ .nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT,
+ .phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_WRBACK,
+ },
+};
+
+static const struct sdram_config sdram_config = {
+ .data_bits = SDRAM_DATA_32BIT,
+ .row_bits = 13,
+ .col_bits = 10,
+ .bank_bits = 2,
+ .cas = 3,
+ .twr = 2,
+ .trc = 7,
+ .trp = 2,
+ .trcd = 2,
+ .tras = 5,
+ .txsr = 6,
+ /* 7.81 us */
+ .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
+};
+
+int board_early_init_f(void)
+{
+ /* Enable SDRAM in the EBI mux */
+ hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)
+ | HMATRIX_BIT(EBI_NAND_ENABLE));
+
+ portmux_enable_ebi(32, 23, PORTMUX_EBI_NAND,
+ PORTMUX_DRIVE_HIGH);
+ portmux_select_gpio(PORTMUX_PORT_E, 1 << 23,
+ PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH
+ | PORTMUX_DRIVE_MIN);
+ portmux_enable_usart1(PORTMUX_DRIVE_MIN);
+
+#if defined(CONFIG_MACB)
+ portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
+ portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
+#endif
+#if defined(CONFIG_MMC)
+ portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
+#endif
+#if defined(CONFIG_ATMEL_SPI)
+ portmux_enable_spi0(1 << 0, PORTMUX_DRIVE_LOW);
+#endif
+
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ unsigned long expected_size;
+ unsigned long actual_size;
+ void *sdram_base;
+
+ sdram_base = uncached(EBI_SDRAM_BASE);
+
+ expected_size = sdram_init(sdram_base, &sdram_config);
+ actual_size = get_ram_size(sdram_base, expected_size);
+
+ if (expected_size != actual_size)
+ printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+ actual_size >> 20, expected_size >> 20);
+
+ return actual_size;
+}
+
+int board_early_init_r(void)
+{
+ gd->bd->bi_phy_id[0] = 0x01;
+ gd->bd->bi_phy_id[1] = 0x03;
+ return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bi)
+{
+ macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
+ macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
+ return 0;
+}
+#endif
+
+/* SPI chip select control */
+#ifdef CONFIG_ATMEL_SPI
+#define ATNGW100_DATAFLASH_CS_PIN GPIO_PIN_PA(3)
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 1);
+}
+#endif /* CONFIG_ATMEL_SPI */
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
#include <config.h>
#include <common.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
phys_size_t initdram(int board_type)
{
- volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+ sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
}
i--;
- sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
#ifdef CONFIG_SYS_SDRAM_BASE1
- sdram->cs1 = (CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i);
#endif
- sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
- sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+ out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
udelay(500);
/* Issue PALL */
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
asm("nop");
/* Perform two refresh cycles */
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
asm("nop");
/* Issue LEMR */
- sdram->mode = CONFIG_SYS_SDRAM_MODE;
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
asm("nop");
- sdram->mode = CONFIG_SYS_SDRAM_EMOD;
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
asm("nop");
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
asm("nop");
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
+ out_be32(&sdram->ctrl,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
asm("nop");
udelay(100);
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
#include <common.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
*/
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
#else
- volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
- volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
+ sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
+ gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
u32 i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
}
i--;
- gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH;
+ out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
- sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
- sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
- sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2;
+ out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
/* Issue PALL */
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
__asm__("nop");
/* Issue LEMR */
- sdram->sdmr = CONFIG_SYS_SDRAM_MODE;
+ out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
__asm__("nop");
- sdram->sdmr = CONFIG_SYS_SDRAM_EMOD;
+ out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD);
__asm__("nop");
udelay(1000);
/* Issue PALL */
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
__asm__("nop");
/* Perform two refresh cycles */
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
__asm__("nop");
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
__asm__("nop");
- sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000C00;
+ out_be32(&sdram->sdcr,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
udelay(100);
#endif
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
#include <config.h>
#include <common.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
phys_size_t initdram(int board_type)
{
- volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
- volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
+ sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
+ gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
u32 dramsize, i, dramclk;
/*
* the port-size of SDRAM. In this case it is necessary to enable
* Data[15:0] on Port Address/Data.
*/
- gpio->par_ad =
- GPIO_PAR_AD_ADDR23 | GPIO_PAR_AD_ADDR22 | GPIO_PAR_AD_ADDR21 |
- GPIO_PAR_AD_DATAL;
+ out_8(&gpio->par_ad,
+ GPIO_PAR_AD_ADDR23 | GPIO_PAR_AD_ADDR22 | GPIO_PAR_AD_ADDR21 |
+ GPIO_PAR_AD_DATAL);
/* Initialize PAR to enable SDRAM signals */
- gpio->par_sdram =
- GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS | GPIO_PAR_SDRAM_SRAS |
- GPIO_PAR_SDRAM_SCKE | GPIO_PAR_SDRAM_SDCS(3);
+ out_8(&gpio->par_sdram,
+ GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS |
+ GPIO_PAR_SDRAM_SRAS | GPIO_PAR_SDRAM_SCKE |
+ GPIO_PAR_SDRAM_SDCS(3));
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
}
i--;
- if (!(sdram->dacr0 & SDRAMC_DARCn_RE)) {
+ if (!(in_be32(&sdram->dacr0) & SDRAMC_DARCn_RE)) {
dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ);
/* Initialize DRAM Control Register: DCR */
- sdram->dcr = SDRAMC_DCR_RTIM_9CLKS |
- SDRAMC_DCR_RTIM_6CLKS | SDRAMC_DCR_RC((15 * dramclk) >> 4);
+ out_be16(&sdram->dcr, SDRAMC_DCR_RTIM_9CLKS |
+ SDRAMC_DCR_RTIM_6CLKS |
+ SDRAMC_DCR_RC((15 * dramclk) >> 4));
/* Initialize DACR0 */
- sdram->dacr0 =
- SDRAMC_DARCn_BA(CONFIG_SYS_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 |
- SDRAMC_DARCn_CBM_CMD20 | SDRAMC_DARCn_PS_32;
+ out_be32(&sdram->dacr0,
+ SDRAMC_DARCn_BA(CONFIG_SYS_SDRAM_BASE) |
+ SDRAMC_DARCn_CASL_C1 | SDRAMC_DARCn_CBM_CMD20 |
+ SDRAMC_DARCn_PS_32);
asm("nop");
/* Initialize DMR0 */
- sdram->dmr0 = ((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V;
+ out_be32(&sdram->dmr0,
+ ((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V);
asm("nop");
/* Set IP (bit 3) in DACR */
- sdram->dacr0 |= SDRAMC_DARCn_IP;
+ setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IP);
/* Wait 30ns to allow banks to precharge */
for (i = 0; i < 5; i++) {
*(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
/* Set RE (bit 15) in DACR */
- sdram->dacr0 |= SDRAMC_DARCn_RE;
+ setbits_be32(&sdram->dacr0, SDRAMC_DARCn_RE);
/* Wait for at least 8 auto refresh cycles to occur */
for (i = 0; i < 0x2000; i++) {
}
/* Finish the configuration by issuing the MRS. */
- sdram->dacr0 |= SDRAMC_DARCn_IMRS;
+ setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IMRS);
asm("nop");
/* Write to the SDRAM Mode Register */
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* Hayden Fraser (Hayden.Fraser@freescale.com)
*
* See file CREDITS for list of people who contributed to this
void ide_set_reset(int idereset)
{
- volatile atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
+ atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
long period;
/* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
};
if (idereset) {
- ata->cr = 0; /* control reset */
+ /* control reset */
+ out_8(&ata->cr, 0);
udelay(100);
} else {
mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */
/*ata->ton = CALC_TIMING (180); */
- ata->t1 = CALC_TIMING(piotms[2][0]);
- ata->t2w = CALC_TIMING(piotms[2][1]);
- ata->t2r = CALC_TIMING(piotms[2][1]);
- ata->ta = CALC_TIMING(piotms[2][8]);
- ata->trd = CALC_TIMING(piotms[2][7]);
- ata->t4 = CALC_TIMING(piotms[2][3]);
- ata->t9 = CALC_TIMING(piotms[2][6]);
-
- ata->cr = 0x40; /* IORDY enable */
+ out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
+ out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
+ out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
+ out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
+ out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
+ out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
+ out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
+
+ /* IORDY enable */
+ out_8(&ata->cr, 0x40);
udelay(2000);
- ata->cr |= 0x01; /* IORDY enable */
+ /* IORDY enable */
+ setbits_8(&ata->cr, 0x01);
}
}
#endif /* CONFIG_CMD_IDE */
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* Hayden Fraser (Hayden.Fraser@freescale.com)
*
* See file CREDITS for list of people who contributed to this
#include <common.h>
#include <asm/immap.h>
+#include <asm/io.h>
int checkboard(void)
{
void ide_set_reset(int idereset)
{
- volatile atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
+ atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
long period;
/* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
};
if (idereset) {
- ata->cr = 0; /* control reset */
+ /* control reset */
+ out_8(&ata->cr, 0);
udelay(100);
} else {
mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */
/*ata->ton = CALC_TIMING (180); */
- ata->t1 = CALC_TIMING(piotms[2][0]);
- ata->t2w = CALC_TIMING(piotms[2][1]);
- ata->t2r = CALC_TIMING(piotms[2][1]);
- ata->ta = CALC_TIMING(piotms[2][8]);
- ata->trd = CALC_TIMING(piotms[2][7]);
- ata->t4 = CALC_TIMING(piotms[2][3]);
- ata->t9 = CALC_TIMING(piotms[2][6]);
-
- ata->cr = 0x40; /* IORDY enable */
+ out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
+ out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
+ out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
+ out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
+ out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
+ out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
+ out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
+
+ /* IORDY enable */
+ out_8(&ata->cr, 0x40);
udelay(2000);
- ata->cr |= 0x01; /* IORDY enable */
+ /* IORDY enable */
+ setbits_8(&ata->cr, 0x01);
}
}
#endif /* CONFIG_CMD_IDE */
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
#include <common.h>
#include <asm/immap.h>
+#include <asm/io.h>
int checkboard (void) {
};
phys_size_t initdram (int board_type) {
- volatile sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM);
+ sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM);
- sdp->sdram_sdtr = 0xf539;
- sdp->sdram_sdcr = 0x4211;
+ out_be16(&sdp->sdram_sdtr, 0xf539);
+ out_be16(&sdp->sdram_sdcr, 0x4211);
/* Dummy write to start SDRAM */
*((volatile unsigned long *)0) = 0;
*
* Copyright (C) 2005-2008 Arthur Shipkowski (art@videon-central.com)
*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
#include <common.h>
#include <asm/immap.h>
+#include <asm/io.h>
#define PERIOD 13 /* system bus period in ns */
#define SDRAM_TREFI 7800 /* in ns */
phys_size_t initdram(int board_type)
{
- volatile sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM);
- volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
+ sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM);
+ gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
- gpio_reg->par_sdram = 0x3FF; /* Enable SDRAM */
+ /* Enable SDRAM */
+ out_be16(&gpio_reg->par_sdram, 0x3FF);
/* Set up chip select */
- sdp->sdbar0 = CONFIG_SYS_SDRAM_BASE;
- sdp->sdbmr0 = MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V;
+ out_be32(&sdp->sdbar0, CONFIG_SYS_SDRAM_BASE);
+ out_be32(&sdp->sdbmr0, MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V);
/* Set up timing */
- sdp->sdcfg1 = 0x83711630;
- sdp->sdcfg2 = 0x46770000;
+ out_be32(&sdp->sdcfg1, 0x83711630);
+ out_be32(&sdp->sdcfg2, 0x46770000);
/* Enable clock */
- sdp->sdcr = MCF_SDRAMC_SDCR_MODE_EN | MCF_SDRAMC_SDCR_CKE;
+ out_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN | MCF_SDRAMC_SDCR_CKE);
/* Set precharge */
- sdp->sdcr |= MCF_SDRAMC_SDCR_IPALL;
+ setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
/* Dummy write to start SDRAM */
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Send LEMR */
- sdp->sdmr = MCF_SDRAMC_SDMR_BNKAD_LEMR
- | MCF_SDRAMC_SDMR_AD(0x0)
- | MCF_SDRAMC_SDMR_CMD;
+ setbits_be32(&sdp->sdmr,
+ MCF_SDRAMC_SDMR_BNKAD_LEMR | MCF_SDRAMC_SDMR_AD(0x0) |
+ MCF_SDRAMC_SDMR_CMD);
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Send LMR */
- sdp->sdmr = 0x058d0000;
+ out_be32(&sdp->sdmr, 0x058d0000);
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Stop sending commands */
- sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD);
+ clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
/* Set precharge */
- sdp->sdcr |= MCF_SDRAMC_SDCR_IPALL;
+ setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Stop manual precharge, send 2 IREF */
- sdp->sdcr &= ~(MCF_SDRAMC_SDCR_IPALL);
- sdp->sdcr |= MCF_SDRAMC_SDCR_IREF;
+ clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
+ setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IREF);
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
- /* Write mode register, clear reset DLL */
- sdp->sdmr = 0x018d0000;
+
+ out_be32(&sdp->sdmr, 0x018d0000);
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Stop sending commands */
- sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD);
- sdp->sdcr &= ~(MCF_SDRAMC_SDCR_MODE_EN);
+ clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
+ clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN);
/* Turn on auto refresh, lock SDMR */
- sdp->sdcr =
+ out_be32(&sdp->sdcr,
MCF_SDRAMC_SDCR_CKE
| MCF_SDRAMC_SDCR_REF
| MCF_SDRAMC_SDCR_MUX(1)
/* 1 added to round up */
| MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1)
- | MCF_SDRAMC_SDCR_DQS_OE(0x3);
+ | MCF_SDRAMC_SDCR_DQS_OE(0x3));
return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
};
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
#include <config.h>
#include <common.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
phys_size_t initdram(int board_type)
{
- volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+ sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
}
i--;
- sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
#ifdef CONFIG_SYS_SDRAM_BASE1
- sdram->cs1 = (CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i);
#endif
- sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
- sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+ out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
udelay(500);
/* Issue PALL */
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
asm("nop");
/* Perform two refresh cycles */
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
asm("nop");
/* Issue LEMR */
- sdram->mode = CONFIG_SYS_SDRAM_MODE;
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
asm("nop");
- sdram->mode = CONFIG_SYS_SDRAM_EMOD;
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
asm("nop");
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
asm("nop");
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
+ out_be32(&sdram->ctrl,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
asm("nop");
udelay(100);
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
#include <config.h>
#include <common.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
phys_size_t initdram(int board_type)
{
- volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+ sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
}
i--;
- sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
- sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
- sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+ out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
/* Issue PALL */
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Issue LEMR */
- sdram->mode = CONFIG_SYS_SDRAM_EMOD;
- sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
udelay(500);
/* Issue PALL */
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
- sdram->mode = CONFIG_SYS_SDRAM_MODE;
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
+ out_be32(&sdram->ctrl,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
udelay(100);
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
int board_nand_init(struct nand_chip *nand)
{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/*
* set up pin configuration - enabled 2nd output buffer's signals
* (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
* to use nCE signal
*/
- gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
- gpio->pddr_timer |= 0x08;
- gpio->ppd_timer |= 0x08;
- gpio->pclrr_timer = 0;
- gpio->podr_timer = 0;
+ clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3);
+ setbits_8(&gpio->pddr_timer, 0x08);
+ setbits_8(&gpio->ppd_timer, 0x08);
+ out_8(&gpio->pclrr_timer, 0);
+ out_8(&gpio->podr_timer, 0);
nand->chip_delay = 60;
nand->ecc.mode = NAND_ECC_SOFT;
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
#include <config.h>
#include <common.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
phys_size_t initdram(int board_type)
{
- volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+ sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
}
i--;
- sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
- sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
- sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+ out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
/* Issue PALL */
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Issue LEMR */
- sdram->mode = CONFIG_SYS_SDRAM_EMOD;
- sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
udelay(500);
/* Issue PALL */
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
- sdram->mode = CONFIG_SYS_SDRAM_MODE;
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
+ out_be32(&sdram->ctrl,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
udelay(100);
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
int board_nand_init(struct nand_chip *nand)
{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
- fbcs->csmr2 &= ~FBCS_CSMR_WP;
+ clrbits_be32(&fbcs->csmr2, FBCS_CSMR_WP);
/*
* set up pin configuration - enabled 2nd output buffer's signals
* (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
* to use nCE signal
*/
- gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
- gpio->pddr_timer |= 0x08;
- gpio->ppd_timer |= 0x08;
- gpio->pclrr_timer = 0;
- gpio->podr_timer = 0;
+ clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3);
+ setbits_8(&gpio->pddr_timer, 0x08);
+ setbits_8(&gpio->ppd_timer, 0x08);
+ out_8(&gpio->pclrr_timer, 0);
+ out_8(&gpio->podr_timer, 0);
nand->chip_delay = 60;
nand->ecc.mode = NAND_ECC_SOFT;
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
#include <common.h>
#include <spi.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
*/
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
#else
- volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
- volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
+ sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
+ gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
u32 i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
- if ((sdram->sdcfg1 == CONFIG_SYS_SDRAM_CFG1) &&
- (sdram->sdcfg2 == CONFIG_SYS_SDRAM_CFG2))
+ if ((in_be32(&sdram->sdcfg1) == CONFIG_SYS_SDRAM_CFG1) &&
+ (in_be32(&sdram->sdcfg2) == CONFIG_SYS_SDRAM_CFG2))
return dramsize;
for (i = 0x13; i < 0x20; i++) {
}
i--;
- gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH;
+ out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
- sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
- sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
- sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2;
+ out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
udelay(200);
/* Issue PALL */
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
__asm__("nop");
/* Perform two refresh cycles */
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
__asm__("nop");
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
__asm__("nop");
/* Issue LEMR */
- sdram->sdmr = CONFIG_SYS_SDRAM_MODE;
+ out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
__asm__("nop");
- sdram->sdmr = CONFIG_SYS_SDRAM_EMOD;
+ out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
__asm__("nop");
- sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000000;
+ out_be32(&sdram->sdcr,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000000);
udelay(100);
#endif
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
#include <common.h>
#include <pci.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
*/
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
#else
- volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
- volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
+ sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
+ gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
u32 i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
}
i--;
- gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH;
+ out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
- sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
- sdram->sdcs1 = (CONFIG_SYS_SDRAM_BASE1 | i);
+ out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->sdcs1, CONFIG_SYS_SDRAM_BASE1 | i);
- sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
- sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2;
+ out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
/* Issue PALL */
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
/* Issue LEMR */
- sdram->sdmr = CONFIG_SYS_SDRAM_EMOD | 0x408;
- sdram->sdmr = CONFIG_SYS_SDRAM_MODE | 0x300;
+ out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD | 0x408);
+ out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x300);
udelay(500);
/* Issue PALL */
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
- sdram->sdmr = CONFIG_SYS_SDRAM_MODE | 0x200;
+ out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x200);
- sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
+ out_be32(&sdram->sdcr,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
udelay(100);
#endif
int ide_preinit(void)
{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
- gpio->par_fec |= (gpio->par_fec & GPIO_PAR_FEC_FEC1_UNMASK) | 0x10;
- gpio->par_feci2c |=
- (gpio->par_feci2c & 0xF0FF) | (GPIO_PAR_FECI2C_MDC1_ATA_DIOR |
- GPIO_PAR_FECI2C_MDIO1_ATA_DIOW);
- gpio->par_ata |=
- (GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 |
- GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0
- | GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ |
- GPIO_PAR_ATA_IORDY_IORDY);
- gpio->par_pci |=
- (GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ);
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ u32 tmp;
+
+ tmp = (in_8(&gpio->par_fec) & GPIO_PAR_FEC_FEC1_UNMASK) | 0x10;
+ setbits_8(&gpio->par_fec, tmp);
+ tmp = ((in_be16(&gpio->par_feci2c) & 0xf0ff) |
+ (GPIO_PAR_FECI2C_MDC1_ATA_DIOR | GPIO_PAR_FECI2C_MDIO1_ATA_DIOW));
+ setbits_be16(&gpio->par_feci2c, tmp);
+
+ setbits_be16(&gpio->par_ata,
+ GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 |
+ GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0 |
+ GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ |
+ GPIO_PAR_ATA_IORDY_IORDY);
+ setbits_be16(&gpio->par_pci,
+ GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ);
return (0);
}
void ide_set_reset(int idereset)
{
- volatile atac_t *ata = (atac_t *) MMAP_ATA;
+ atac_t *ata = (atac_t *) MMAP_ATA;
long period;
/* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
int piotms[5][9] = {
}; /* PIO 4 */
if (idereset) {
- ata->cr = 0; /* control reset */
+ /* control reset */
+ out_8(&ata->cr, 0);
udelay(10000);
} else {
#define CALC_TIMING(t) (t + period - 1) / period
period = 1000000000 / gd->bus_clk; /* period in ns */
/*ata->ton = CALC_TIMING (180); */
- ata->t1 = CALC_TIMING(piotms[2][0]);
- ata->t2w = CALC_TIMING(piotms[2][1]);
- ata->t2r = CALC_TIMING(piotms[2][1]);
- ata->ta = CALC_TIMING(piotms[2][8]);
- ata->trd = CALC_TIMING(piotms[2][7]);
- ata->t4 = CALC_TIMING(piotms[2][3]);
- ata->t9 = CALC_TIMING(piotms[2][6]);
-
- ata->cr = 0x40; /* IORDY enable */
+ out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
+ out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
+ out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
+ out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
+ out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
+ out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
+ out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
+
+ /* IORDY enable */
+ out_8(&ata->cr, 0x40);
udelay(200000);
- ata->cr |= 0x01; /* IORDY enable */
+ /* IORDY enable */
+ setbits_8(&ata->cr, 0x01);
}
}
#endif
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
#include <common.h>
#include <pci.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
phys_size_t initdram(int board_type)
{
- volatile siu_t *siu = (siu_t *) (MMAP_SIU);
- volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+ siu_t *siu = (siu_t *) (MMAP_SIU);
+ sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
#ifdef CONFIG_SYS_DRAMSZ1
u32 temp;
#endif
- siu->drv = CONFIG_SYS_SDRAM_DRVSTRENGTH;
+ out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH);
dramsize = CONFIG_SYS_DRAMSZ * 0x100000;
for (i = 0x13; i < 0x20; i++) {
break;
}
i--;
- siu->cs0cfg = (CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&siu->cs0cfg, CONFIG_SYS_SDRAM_BASE | i);
#ifdef CONFIG_SYS_DRAMSZ1
temp = CONFIG_SYS_DRAMSZ1 * 0x100000;
}
i--;
dramsize += temp;
- siu->cs1cfg = ((CONFIG_SYS_SDRAM_BASE + temp) | i);
+ out_be32(&siu->cs1cfg, (CONFIG_SYS_SDRAM_BASE + temp) | i);
#endif
- sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
- sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+ out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
/* Issue PALL */
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Issue LEMR */
- sdram->mode = CONFIG_SYS_SDRAM_EMOD;
- sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
udelay(500);
/* Issue PALL */
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
- sdram->mode = CONFIG_SYS_SDRAM_MODE;
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
+ out_be32(&sdram->ctrl,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
udelay(100);
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
#include <common.h>
#include <pci.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
phys_size_t initdram(int board_type)
{
- volatile siu_t *siu = (siu_t *) (MMAP_SIU);
- volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+ siu_t *siu = (siu_t *) (MMAP_SIU);
+ sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
#ifdef CONFIG_SYS_DRAMSZ1
u32 temp;
#endif
- siu->drv = CONFIG_SYS_SDRAM_DRVSTRENGTH;
+ out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH);
dramsize = CONFIG_SYS_DRAMSZ * 0x100000;
for (i = 0x13; i < 0x20; i++) {
break;
}
i--;
- siu->cs0cfg = (CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&siu->cs0cfg, CONFIG_SYS_SDRAM_BASE | i);
#ifdef CONFIG_SYS_DRAMSZ1
temp = CONFIG_SYS_DRAMSZ1 * 0x100000;
}
i--;
dramsize += temp;
- siu->cs1cfg = ((CONFIG_SYS_SDRAM_BASE + temp) | i);
+ out_be32(&siu->cs1cfg, (CONFIG_SYS_SDRAM_BASE + temp) | i);
#endif
- sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
- sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+ out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
/* Issue PALL */
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Issue LEMR */
- sdram->mode = CONFIG_SYS_SDRAM_EMOD;
- sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
udelay(500);
/* Issue PALL */
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
- sdram->mode = CONFIG_SYS_SDRAM_MODE;
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
+ out_be32(&sdram->ctrl,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
udelay(100);
#include <common.h>
#include <hwconfig.h>
#include <i2c.h>
+#include <spi.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <pci.h>
#include <mpc83xx.h>
#include <vsc7385.h>
#include <netdev.h>
+#include <fsl_esdhc.h>
#include <asm/io.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_mpc83xx_serdes.h>
DECLARE_GLOBAL_DATA_PTR;
+/*
+ * The following are used to control the SPI chip selects for the SPI command.
+ */
+#ifdef CONFIG_MPC8XXX_SPI
+
+#define SPI_CS_MASK 0x00400000
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+ /* active low */
+ clrbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+ /* inactive high */
+ setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
+}
+#endif /* CONFIG_MPC8XXX_SPI */
+
+#ifdef CONFIG_FSL_ESDHC
+int board_mmc_init(bd_t *bd)
+{
+ return fsl_esdhc_mmc_init(bd);
+}
+#endif
+
static u8 read_board_info(void)
{
u8 val8;
*/
int misc_init_r(void)
{
+#ifdef CONFIG_MPC8XXX_SPI
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+ sysconf83xx_t *sysconf = &immr->sysconf;
+
+ /*
+ * Set proper bits in SICRH to allow SPI on header J8
+ *
+ * NOTE: this breaks the TSEC2 interface, attached to the Vitesse
+ * switch. The pinmux configuration does not have a fine enough
+ * granularity to support both simultaneously.
+ */
+ clrsetbits_be32(&sysconf->sicrh, SICRH_GPIO_A_TSEC2, SICRH_GPIO_A_GPIO);
+ puts("WARNING: SPI enabled, TSEC2 support is broken\n");
+
+ /* Set header J8 SPI chip select output, disabled */
+ setbits_be32(&immr->gpio[0].dir, SPI_CS_MASK);
+ setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
+#endif
+
#ifdef CONFIG_VSC7385_IMAGE
if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
CONFIG_VSC7385_IMAGE_SIZE)) {
{
ft_cpu_setup(blob, bd);
fdt_fixup_dr_usb(blob, bd);
+ fdt_fixup_esdhc(blob, bd);
}
#endif
static void cpm_init(void)
{
struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE;
- uint32_t reg = readw(&cpm->clkgr);
+ uint32_t reg = readl(&cpm->clkgr);
reg |= CPM_CLKGR_IPU |
CPM_CLKGR_CIM |
CPM_CLKGR_UDC |
CPM_CLKGR_AIC1;
- writew(reg, &cpm->clkgr);
+ writel(reg, &cpm->clkgr);
}
int board_early_init_f(void)
#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Copyright (C) 2012 Samsung Electronics
+# Lukasz Majewski <l.majewski@samsung.com>
#
# See file CREDITS for list of people who contributed to this
# project.
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).o
+LIB = $(obj)libsamsung.o
-COBJS-y := apollon.o mem.o sys_info.o
-SOBJS := lowlevel_init.o
+COBJS-$(CONFIG_SOFT_I2C_MULTI_BUS) += multi_i2c.o
-COBJS := $(COBJS-y)
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
+SRCS := $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * Lukasz Majewski <l.majewski@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+/* Handle multiple I2C buses instances */
+int get_multi_scl_pin(void)
+{
+ unsigned int bus = I2C_GET_BUS();
+
+ switch (bus) {
+ case I2C_0: /* I2C_0 definition - compatibility layer */
+ case I2C_5:
+ return CONFIG_SOFT_I2C_I2C5_SCL;
+ case I2C_9:
+ return CONFIG_SOFT_I2C_I2C9_SCL;
+ default:
+ printf("I2C_%d not supported!\n", bus);
+ };
+
+ return 0;
+}
+
+int get_multi_sda_pin(void)
+{
+ unsigned int bus = I2C_GET_BUS();
+
+ switch (bus) {
+ case I2C_0: /* I2C_0 definition - compatibility layer */
+ case I2C_5:
+ return CONFIG_SOFT_I2C_I2C5_SDA;
+ case I2C_9:
+ return CONFIG_SOFT_I2C_I2C9_SDA;
+ default:
+ printf("I2C_%d not supported!\n", bus);
+ };
+
+ return 0;
+}
+
+int multi_i2c_init(void)
+{
+ return 0;
+}
str r1, [r0, #0x0] @ GPIO_CON_OFFSET
ldr r1, [r0, #0x4] @ GPIO_DAT_OFFSET
-#ifdef CONFIG_ONENAND_IPL
- orr r1, r1, #(1 << 1) @ 1 * 1-bit
-#else
bic r1, r1, #(1 << 1)
-#endif
str r1, [r0, #0x4] @ GPIO_DAT_OFFSET
/* Don't setup at s5pc100 */
/* Do not release retention here for S5PC110 */
streq r1, [r0]
-#ifndef CONFIG_ONENAND_IPL
/* Disable Watchdog */
ldreq r0, =S5PC100_WATCHDOG_BASE @ 0xEA200000
ldrne r0, =S5PC110_WATCHDOG_BASE @ 0xE2700000
ldrne r0, =S5PC110_SROMC_BASE
ldr r1, =0x9
str r1, [r0]
-#endif
/* S5PC100 has 3 groups of interrupt sources */
ldreq r0, =S5PC100_VIC0_BASE @ 0xE4000000
str r3, [r1, #0x14] @ INTENCLEAR
str r3, [r2, #0x14] @ INTENCLEAR
-#ifndef CONFIG_ONENAND_IPL
/* Set all interrupts as IRQ */
str r5, [r0, #0xc] @ INTSELECT
str r5, [r1, #0xc] @ INTSELECT
str r5, [r0, #0xf00] @ INTADDRESS
str r5, [r1, #0xf00] @ INTADDRESS
str r5, [r2, #0xf00] @ INTADDRESS
-#endif
-#ifndef CONFIG_ONENAND_IPL
/* for UART */
bl uart_asm_init
bl internal_ram_init
-#endif
-
-#ifdef CONFIG_ONENAND_IPL
- /* init system clock */
- bl system_clock_init
-
- /* OneNAND Sync Read Support at S5PC110 only
- * RM[15] : Sync Read
- * BRWL[14:12] : 7 CLK
- * BL[11:9] : Continuous
- * VHF[3] : Very High Frequency Enable (Over 83MHz)
- * HF[2] : High Frequency Enable (Over 66MHz)
- * WM[1] : Sync Write
- */
- cmp r7, r8
- ldrne r1, =0xE006
- ldrne r0, =0xB001E442
- strneh r1, [r0]
-
- /*
- * GCE[26] : Gated Clock Enable
- * RPE[17] : Enables Read Prefetch
- */
- ldrne r1, =((1 << 26) | (1 << 17) | 0xE006)
- ldrne r0, =0xB0600000
- strne r1, [r0, #0x100] @ ONENAND_IF_CTRL
- ldrne r1, =0x1212
- strne r1, [r0, #0x108]
-
- /* Board detection to set proper memory configuration */
- cmp r7, r8
- moveq r9, #1 /* r9 has 1Gib default at s5pc100 */
- movne r9, #2 /* r9 has 2Gib default at s5pc110 */
-
- ldr r2, =0xE0200200
- ldr r4, [r2, #0x48]
-
- bic r1, r4, #(0x3F << 4) /* PULLUP_DISABLE: 3 * 2-bit */
- bic r1, r1, #(0x3 << 2) /* PULLUP_DISABLE: 2 * 2-bit */
- bic r1, r1, #(0x3 << 14) /* PULLUP_DISABLE: 2 * 2-bit */
- str r1, [r2, #0x48]
- /* For write completion */
- nop
- nop
-
- ldr r3, [r2, #0x44]
- and r1, r3, #(0x7 << 2)
- mov r1, r1, lsr #2
- cmp r1, #0x5
- moveq r9, #3
- cmp r1, #0x6
- moveq r9, #1
- cmp r1, #0x7
- moveq r9, #2
- and r0, r3, #(0x1 << 1)
- mov r0, r0, lsr #1
- orr r1, r1, r0, lsl #3
- cmp r1, #0x8
- moveq r9, #3
- and r1, r3, #(0x7 << 2)
- mov r1, r1, lsr #2
- and r0, r3, #(0x1 << 7)
- mov r0, r0, lsr #7
- orr r1, r1, r0, lsl #3
- cmp r1, #0x9
- moveq r9, #3
- str r4, [r2, #0x48] /* Restore PULLUP configuration */
-
- bl mem_ctrl_asm_init
-
- /* Wakeup support. Don't know if it's going to be used, untested. */
- ldreq r0, =S5PC100_RST_STAT
- ldrne r0, =S5PC110_RST_STAT
- ldr r1, [r0]
- biceq r1, r1, #0xfffffff7
- moveq r2, #(1 << 3)
- bicne r1, r1, #0xfffeffff
- movne r2, #(1 << 16)
- cmp r1, r2
- bne 1f
-wakeup:
- /* turn off L2 cache */
- bl l2_cache_disable
-
- cmp r7, r8
- ldreq r0, =0xC100
- ldrne r0, =0xC110
-
- /* invalidate L2 cache also */
- bl invalidate_dcache
-
- /* turn on L2 cache */
- bl l2_cache_enable
-
- cmp r7, r8
- /* Load return address and jump to kernel */
- ldreq r0, =S5PC100_INFORM0
- ldrne r0, =S5PC110_INFORM0
-
- /* r1 = physical address of s5pc1xx_cpu_resume function */
- ldr r1, [r0]
- /* Jump to kernel (sleep-s5pc1xx.S) */
- mov pc, r1
- nop
- nop
-#else
cmp r7, r8
/* Clear wakeup status register */
ldreq r0, =S5PC100_WAKEUP_STAT
orr r1, r1, r2
str r1, [r0]
-#endif
b 1f
didle_wakeup:
mov pc, lr
-#ifndef CONFIG_ONENAND_IPL
internal_ram_init:
ldreq r0, =0xE3800000
ldrne r0, =0xF1500000
str r1, [r0]
mov pc, lr
-#endif
-#ifndef CONFIG_ONENAND_IPL
/*
* uart_asm_init: Initialize UART's pins
*/
str r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET
200:
mov pc, lr
-#endif
orr r0, r0, #0x0
str r5, [r0]
-#ifndef CONFIG_ONENAND_IPL
/* setting SRAM */
ldr r0, =S5PC100_SROMC_BASE
ldr r1, =0x9
str r1, [r0]
-#endif
/* S5PC100 has 3 groups of interrupt sources */
ldr r0, =S5PC100_VIC0_BASE @0xE4000000
str r3, [r1, #0x14] @INTENCLEAR
str r3, [r2, #0x14] @INTENCLEAR
-#ifndef CONFIG_ONENAND_IPL
/* Set all interrupts as IRQ */
str r5, [r0, #0xc] @INTSELECT
str r5, [r1, #0xc] @INTSELECT
str r5, [r0, #0xf00] @INTADDRESS
str r5, [r1, #0xf00] @INTADDRESS
str r5, [r2, #0xf00] @INTADDRESS
-#endif
-#ifndef CONFIG_ONENAND_IPL
/* for UART */
bl uart_asm_init
/* for TZPC */
bl tzpc_asm_init
-#endif
-
-#ifdef CONFIG_ONENAND_IPL
- /* init system clock */
- bl system_clock_init
-
- bl mem_ctrl_asm_init
-
- /* Wakeup support. Don't know if it's going to be used, untested. */
- ldr r0, =S5PC100_RST_STAT
- ldr r1, [r0]
- bic r1, r1, #0xfffffff7
- cmp r1, #0x8
- beq wakeup_reset
-#endif
1:
mov lr, r9
mov pc, lr
-#ifdef CONFIG_ONENAND_IPL
-wakeup_reset:
-
- /* Clear wakeup status register */
- ldr r0, =S5PC100_WAKEUP_STAT
- ldr r1, [r0]
- str r1, [r0]
-
- /* Load return address and jump to kernel */
- ldr r0, =S5PC100_INFORM0
-
- /* r1 = physical address of s5pc100_cpu_resume function */
- ldr r1, [r0]
-
- /* Jump to kernel (sleep.S) */
- mov pc, r1
- nop
- nop
-#endif
-
/*
* system_clock_init: Initialize core clock and bus clock.
* void system_clock_init(void)
mov pc, lr
-#ifndef CONFIG_ONENAND_IPL
/*
* uart_asm_init: Initialize UART's pins
*/
str r1, [r0, #0x810]
mov pc, lr
-#endif
return (board_rev & 0xf) == rev;
}
+struct s3c_plat_otg_data s5pc210_otg_data;
+
int board_init(void)
{
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
return 0;
}
+void i2c_init_board(void)
+{
+ struct exynos4_gpio_part1 *gpio1 =
+ (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
+ struct exynos4_gpio_part2 *gpio2 =
+ (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
+
+ /* I2C_5 -> PMIC */
+ s5p_gpio_direction_output(&gpio1->b, 7, 1);
+ s5p_gpio_direction_output(&gpio1->b, 6, 1);
+ /* I2C_9 -> FG */
+ s5p_gpio_direction_output(&gpio2->y4, 0, 1);
+ s5p_gpio_direction_output(&gpio2->y4, 1, 1);
+}
+
int dram_init(void)
{
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
.usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL,
.usb_flags = PHY0_SLEEP,
};
+
+void board_usb_init(void)
+{
+ debug("USB_udc_probe\n");
+ s3c_udc_probe(&s5pc210_otg_data);
+}
#endif
static void pmic_reset(void)
#include <common.h>
#include <config.h>
#include <netdev.h>
+#include <asm/processor.h>
#include <asm/microblaze_intc.h>
#include <asm/asm.h>
}
#endif
+void board_init(void)
+{
+ gpio_init();
+#ifdef CONFIG_SYS_FSL_2
+ fsl_init2();
+#endif
+}
+
int board_eth_init(bd_t *bis)
{
int ret = 0;
imx31_litekit arm arm1136 - logicpd mx31
flea3 arm arm1136 - CarMediaLab mx35
mx35pdk arm arm1136 - freescale mx35
-apollon arm arm1136 apollon - omap24xx
omap2420h4 arm arm1136 - ti omap24xx
tnetv107x_evm arm arm1176 tnetv107xevm ti tnetv107x
rpi_b arm arm1176 rpi_b raspberrypi bcm2835
paz00 arm armv7:arm720t paz00 compal tegra20
trimslice arm armv7:arm720t trimslice compulab tegra20
atngw100 avr32 at32ap - atmel at32ap700x
+atngw100mkii avr32 at32ap - atmel at32ap700x
atstk1002 avr32 at32ap atstk1000 atmel at32ap700x
atstk1003 avr32 at32ap atstk1000 atmel at32ap700x
atstk1004 avr32 at32ap atstk1000 atmel at32ap700x
M5485GFE m68k mcf547x_8x m548xevb freescale - M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=4,SYS_DRAMSZ=64
M5485HFE m68k mcf547x_8x m548xevb freescale - M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO
microblaze-generic microblaze microblaze microblaze-generic xilinx
-qemu_mips mips mips32 qemu-mips - - qemu-mips
+qemu_mips mips mips32 qemu-mips - - qemu-mips:SYS_BIG_ENDIAN
+qemu_mipsel mips mips32 qemu-mips - - qemu-mips:SYS_LITTLE_ENDIAN
vct_platinum mips mips32 vct micronas - vct:VCT_PLATINUM
vct_platinumavc mips mips32 vct micronas - vct:VCT_PLATINUMAVC
vct_platinumavc_onenand mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND
COBJS-$(CONFIG_CMD_EEPROM) += cmd_eeprom.o
COBJS-$(CONFIG_CMD_ELF) += cmd_elf.o
COBJS-$(CONFIG_SYS_HUSH_PARSER) += cmd_exit.o
+COBJS-$(CONFIG_CMD_EXT4) += cmd_ext4.o
COBJS-$(CONFIG_CMD_EXT2) += cmd_ext2.o
+ifdef CONFIG_CMD_EXT4
+COBJS-y += cmd_ext_common.o
+else
+COBJS-$(CONFIG_CMD_EXT2) += cmd_ext_common.o
+endif
COBJS-$(CONFIG_CMD_FAT) += cmd_fat.o
COBJS-$(CONFIG_CMD_FDC)$(CONFIG_CMD_FDOS) += cmd_fdc.o
COBJS-$(CONFIG_OF_LIBFDT) += cmd_fdt.o fdt_support.o
COBJS-$(CONFIG_MODEM_SUPPORT) += modem.o
COBJS-$(CONFIG_UPDATE_TFTP) += update.o
COBJS-$(CONFIG_USB_KEYBOARD) += usb_kbd.o
+COBJS-$(CONFIG_CMD_DFU) += cmd_dfu.o
endif
ifdef CONFIG_SPL_BUILD
print_num("flashstart ", bd->bi_flashstart);
print_num("CONFIG_SYS_MONITOR_BASE ", CONFIG_SYS_MONITOR_BASE);
print_num("CONFIG_ENV_ADDR ", CONFIG_ENV_ADDR);
- printf("CONFIG_SYS_RELOC_MONITOR_BASE = 0x%lx (%d)\n", CONFIG_SYS_RELOC_MONITOR_BASE,
+ printf("CONFIG_SYS_RELOC_MONITOR_BASE = 0x%x (%d)\n", CONFIG_SYS_RELOC_MONITOR_BASE,
CONFIG_SYS_MONITOR_LEN);
- printf("CONFIG_SYS_MALLOC_BASE = 0x%lx (%d)\n", CONFIG_SYS_MALLOC_BASE,
+ printf("CONFIG_SYS_MALLOC_BASE = 0x%x (%d)\n", CONFIG_SYS_MALLOC_BASE,
CONFIG_SYS_MALLOC_LEN);
- printf("CONFIG_SYS_INIT_SP_OFFSET = 0x%lx (%d)\n", CONFIG_SYS_INIT_SP_OFFSET,
+ printf("CONFIG_SYS_INIT_SP_OFFSET = 0x%x (%d)\n", CONFIG_SYS_INIT_SP_OFFSET,
CONFIG_SYS_STACK_SIZE);
- printf("CONFIG_SYS_PROM_OFFSET = 0x%lx (%d)\n", CONFIG_SYS_PROM_OFFSET,
+ printf("CONFIG_SYS_PROM_OFFSET = 0x%x (%d)\n", CONFIG_SYS_PROM_OFFSET,
CONFIG_SYS_PROM_SIZE);
- printf("CONFIG_SYS_GBL_DATA_OFFSET = 0x%lx (%d)\n", CONFIG_SYS_GBL_DATA_OFFSET,
+ printf("CONFIG_SYS_GBL_DATA_OFFSET = 0x%x (%d)\n", CONFIG_SYS_GBL_DATA_OFFSET,
GENERATED_GBL_DATA_SIZE);
#if defined(CONFIG_CMD_NET)
--- /dev/null
+/*
+ * cmd_dfu.c -- dfu command
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ * authors: Andrzej Pietrasiewicz <andrzej.p@samsung.com>
+ * Lukasz Majewski <l.majewski@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <dfu.h>
+#include <asm/errno.h>
+#include <g_dnl.h>
+
+static int do_dfu(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ const char *str_env;
+ char s[] = "dfu";
+ char *env_bkp;
+ int ret;
+
+ if (argc < 3)
+ return CMD_RET_USAGE;
+
+ str_env = getenv("dfu_alt_info");
+ if (str_env == NULL) {
+ printf("%s: \"dfu_alt_info\" env variable not defined!\n",
+ __func__);
+ return CMD_RET_FAILURE;
+ }
+
+ env_bkp = strdup(str_env);
+ ret = dfu_config_entities(env_bkp, argv[1],
+ (int)simple_strtoul(argv[2], NULL, 10));
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ if (strcmp(argv[3], "list") == 0) {
+ dfu_show_entities();
+ goto done;
+ }
+
+ board_usb_init();
+ g_dnl_register(s);
+ while (1) {
+ if (ctrlc())
+ goto exit;
+
+ usb_gadget_handle_interrupts();
+ }
+exit:
+ g_dnl_unregister();
+done:
+ dfu_free_entities();
+ free(env_bkp);
+
+ return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(dfu, CONFIG_SYS_MAXARGS, 1, do_dfu,
+ "Device Firmware Upgrade",
+ "<interface> <dev> [list]\n"
+ " - device firmware upgrade on a device <dev>\n"
+ " attached to interface <interface>\n"
+ " [list] - list available alt settings"
+);
/*
+ * (C) Copyright 2011 - 2012 Samsung Electronics
+ * EXT4 filesystem implementation in Uboot by
+ * Uma Shankar <uma.shankar@samsung.com>
+ * Manjunatha C Achar <a.manjunatha@samsung.com>
+
* (C) Copyright 2004
* esd gmbh <www.esd-electronics.com>
* Reinhard Arlt <reinhard.arlt@esd-electronics.com>
* Ext2fs support
*/
#include <common.h>
-#include <part.h>
-#include <config.h>
-#include <command.h>
-#include <image.h>
-#include <linux/ctype.h>
-#include <asm/byteorder.h>
-#include <ext2fs.h>
-#if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE)
-#include <usb.h>
-#endif
-
-#if !defined(CONFIG_DOS_PARTITION) && !defined(CONFIG_EFI_PARTITION)
-#error DOS or EFI partition support must be selected
-#endif
-
-/* #define EXT2_DEBUG */
-
-#ifdef EXT2_DEBUG
-#define PRINTF(fmt,args...) printf (fmt ,##args)
-#else
-#define PRINTF(fmt,args...)
-#endif
+#include <ext_common.h>
int do_ext2ls (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- char *filename = "/";
- int dev=0;
- int part=1;
- char *ep;
- block_dev_desc_t *dev_desc=NULL;
- int part_length;
-
- if (argc < 3)
- return CMD_RET_USAGE;
-
- dev = (int)simple_strtoul (argv[2], &ep, 16);
- dev_desc = get_dev(argv[1],dev);
-
- if (dev_desc == NULL) {
- printf ("\n** Block device %s %d not supported\n", argv[1], dev);
- return 1;
- }
-
- if (*ep) {
- if (*ep != ':') {
- puts ("\n** Invalid boot device, use `dev[:part]' **\n");
- return 1;
- }
- part = (int)simple_strtoul(++ep, NULL, 16);
- }
-
- if (argc == 4)
- filename = argv[3];
-
- PRINTF("Using device %s %d:%d, directory: %s\n", argv[1], dev, part, filename);
-
- if ((part_length = ext2fs_set_blk_dev(dev_desc, part)) == 0) {
- printf ("** Bad partition - %s %d:%d **\n", argv[1], dev, part);
- ext2fs_close();
- return 1;
- }
-
- if (!ext2fs_mount(part_length)) {
- printf ("** Bad ext2 partition or disk - %s %d:%d **\n", argv[1], dev, part);
- ext2fs_close();
- return 1;
- }
-
- if (ext2fs_ls (filename)) {
- printf ("** Error ext2fs_ls() **\n");
- ext2fs_close();
- return 1;
- };
-
- ext2fs_close();
+ if (do_ext_ls(cmdtp, flag, argc, argv))
+ return -1;
return 0;
}
-U_BOOT_CMD(
- ext2ls, 4, 1, do_ext2ls,
- "list files in a directory (default /)",
- "<interface> <dev[:part]> [directory]\n"
- " - list files from 'dev' on 'interface' in a 'directory'"
-);
-
/******************************************************************************
* Ext2fs boot command intepreter. Derived from diskboot
*/
int do_ext2load (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- char *filename = NULL;
- char *ep;
- int dev, part = 1;
- ulong addr = 0, part_length;
- int filelen;
- disk_partition_t info;
- block_dev_desc_t *dev_desc = NULL;
- char buf [12];
- unsigned long count;
- char *addr_str;
-
- switch (argc) {
- case 3:
- addr_str = getenv("loadaddr");
- if (addr_str != NULL)
- addr = simple_strtoul (addr_str, NULL, 16);
- else
- addr = CONFIG_SYS_LOAD_ADDR;
-
- filename = getenv ("bootfile");
- count = 0;
- break;
- case 4:
- addr = simple_strtoul (argv[3], NULL, 16);
- filename = getenv ("bootfile");
- count = 0;
- break;
- case 5:
- addr = simple_strtoul (argv[3], NULL, 16);
- filename = argv[4];
- count = 0;
- break;
- case 6:
- addr = simple_strtoul (argv[3], NULL, 16);
- filename = argv[4];
- count = simple_strtoul (argv[5], NULL, 16);
- break;
-
- default:
- return CMD_RET_USAGE;
- }
-
- if (!filename) {
- puts ("** No boot file defined **\n");
- return 1;
- }
-
- dev = (int)simple_strtoul (argv[2], &ep, 16);
- dev_desc = get_dev(argv[1],dev);
- if (dev_desc==NULL) {
- printf ("** Block device %s %d not supported\n", argv[1], dev);
- return 1;
- }
- if (*ep) {
- if (*ep != ':') {
- puts ("** Invalid boot device, use `dev[:part]' **\n");
- return 1;
- }
- part = (int)simple_strtoul(++ep, NULL, 16);
- }
-
- PRINTF("Using device %s%d, partition %d\n", argv[1], dev, part);
-
- if (part != 0) {
- if (get_partition_info (dev_desc, part, &info)) {
- printf ("** Bad partition %d **\n", part);
- return 1;
- }
-
- if (strncmp((char *)info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) {
- printf ("** Invalid partition type \"%.32s\""
- " (expect \"" BOOT_PART_TYPE "\")\n",
- info.type);
- return 1;
- }
- printf ("Loading file \"%s\" "
- "from %s device %d:%d (%.32s)\n",
- filename,
- argv[1], dev, part, info.name);
- } else {
- printf ("Loading file \"%s\" from %s device %d\n",
- filename, argv[1], dev);
- }
-
-
- if ((part_length = ext2fs_set_blk_dev(dev_desc, part)) == 0) {
- printf ("** Bad partition - %s %d:%d **\n", argv[1], dev, part);
- ext2fs_close();
- return 1;
- }
-
- if (!ext2fs_mount(part_length)) {
- printf ("** Bad ext2 partition or disk - %s %d:%d **\n",
- argv[1], dev, part);
- ext2fs_close();
- return 1;
- }
-
- filelen = ext2fs_open(filename);
- if (filelen < 0) {
- printf("** File not found %s\n", filename);
- ext2fs_close();
- return 1;
- }
- if ((count < filelen) && (count != 0)) {
- filelen = count;
- }
-
- if (ext2fs_read((char *)addr, filelen) != filelen) {
- printf("** Unable to read \"%s\" from %s %d:%d **\n",
- filename, argv[1], dev, part);
- ext2fs_close();
- return 1;
- }
-
- ext2fs_close();
-
- /* Loading ok, update default load address */
- load_addr = addr;
-
- printf ("%d bytes read\n", filelen);
- sprintf(buf, "%X", filelen);
- setenv("filesize", buf);
+ if (do_ext_load(cmdtp, flag, argc, argv))
+ return -1;
return 0;
}
+U_BOOT_CMD(
+ ext2ls, 4, 1, do_ext2ls,
+ "list files in a directory (default /)",
+ "<interface> <dev[:part]> [directory]\n"
+ " - list files from 'dev' on 'interface' in a 'directory'"
+);
+
U_BOOT_CMD(
ext2load, 6, 0, do_ext2load,
"load binary file from a Ext2 filesystem",
--- /dev/null
+/*
+ * (C) Copyright 2011 - 2012 Samsung Electronics
+ * EXT4 filesystem implementation in Uboot by
+ * Uma Shankar <uma.shankar@samsung.com>
+ * Manjunatha C Achar <a.manjunatha@samsung.com>
+ *
+ * Ext4fs support
+ * made from existing cmd_ext2.c file of Uboot
+ *
+ * (C) Copyright 2004
+ * esd gmbh <www.esd-electronics.com>
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * made from cmd_reiserfs by
+ *
+ * (C) Copyright 2003 - 2004
+ * Sysgo Real-Time Solutions, AG <www.elinos.com>
+ * Pavel Bartusek <pba@sysgo.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/*
+ * Changelog:
+ * 0.1 - Newly created file for ext4fs support. Taken from cmd_ext2.c
+ * file in uboot. Added ext4fs ls load and write support.
+ */
+
+#include <common.h>
+#include <part.h>
+#include <config.h>
+#include <command.h>
+#include <image.h>
+#include <linux/ctype.h>
+#include <asm/byteorder.h>
+#include <ext_common.h>
+#include <ext4fs.h>
+#include <linux/stat.h>
+#include <malloc.h>
+
+#if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE)
+#include <usb.h>
+#endif
+
+#if !defined(CONFIG_DOS_PARTITION) && !defined(CONFIG_EFI_PARTITION)
+#error DOS or EFI partition support must be selected
+#endif
+
+uint64_t total_sector;
+uint64_t part_offset;
+#if defined(CONFIG_CMD_EXT4_WRITE)
+static uint64_t part_size;
+static uint16_t cur_part = 1;
+#endif
+
+#define DOS_PART_MAGIC_OFFSET 0x1fe
+#define DOS_FS_TYPE_OFFSET 0x36
+#define DOS_FS32_TYPE_OFFSET 0x52
+
+int do_ext4_load(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ if (do_ext_load(cmdtp, flag, argc, argv))
+ return -1;
+
+ return 0;
+}
+
+int do_ext4_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ if (do_ext_ls(cmdtp, flag, argc, argv))
+ return -1;
+
+ return 0;
+}
+
+#if defined(CONFIG_CMD_EXT4_WRITE)
+static int ext4_register_device(block_dev_desc_t *dev_desc, int part_no)
+{
+ unsigned char buffer[SECTOR_SIZE];
+ disk_partition_t info;
+
+ if (!dev_desc->block_read)
+ return -1;
+
+ /* check if we have a MBR (on floppies we have only a PBR) */
+ if (dev_desc->block_read(dev_desc->dev, 0, 1, (ulong *) buffer) != 1) {
+ printf("** Can't read from device %d **\n", dev_desc->dev);
+ return -1;
+ }
+ if (buffer[DOS_PART_MAGIC_OFFSET] != 0x55 ||
+ buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa) {
+ /* no signature found */
+ return -1;
+ }
+
+ /* First we assume there is a MBR */
+ if (!get_partition_info(dev_desc, part_no, &info)) {
+ part_offset = info.start;
+ cur_part = part_no;
+ part_size = info.size;
+ } else if ((strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET],
+ "FAT", 3) == 0) || (strncmp((char *)&buffer
+ [DOS_FS32_TYPE_OFFSET],
+ "FAT32", 5) == 0)) {
+ /* ok, we assume we are on a PBR only */
+ cur_part = 1;
+ part_offset = 0;
+ } else {
+ printf("** Partition %d not valid on device %d **\n",
+ part_no, dev_desc->dev);
+ return -1;
+ }
+
+ return 0;
+}
+
+int do_ext4_write(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ const char *filename = "/";
+ int part_length;
+ unsigned long part = 1;
+ int dev;
+ char *ep;
+ unsigned long ram_address;
+ unsigned long file_size;
+ disk_partition_t info;
+ struct ext_filesystem *fs;
+
+ if (argc < 6)
+ return cmd_usage(cmdtp);
+
+ dev = (int)simple_strtoul(argv[2], &ep, 16);
+ ext4_dev_desc = get_dev(argv[1], dev);
+ if (ext4_dev_desc == NULL) {
+ printf("Block device %s %d not supported\n", argv[1], dev);
+ return 1;
+ }
+ if (init_fs(ext4_dev_desc))
+ return 1;
+
+ fs = get_fs();
+ if (*ep) {
+ if (*ep != ':') {
+ puts("Invalid boot device, use `dev[:part]'\n");
+ goto fail;
+ }
+ part = simple_strtoul(++ep, NULL, 16);
+ }
+
+ /* get the filename */
+ filename = argv[3];
+
+ /* get the address in hexadecimal format (string to int) */
+ ram_address = simple_strtoul(argv[4], NULL, 16);
+
+ /* get the filesize in base 10 format */
+ file_size = simple_strtoul(argv[5], NULL, 10);
+
+ /* set the device as block device */
+ part_length = ext4fs_set_blk_dev(fs->dev_desc, part);
+ if (part_length == 0) {
+ printf("Bad partition - %s %d:%lu\n", argv[1], dev, part);
+ goto fail;
+ }
+
+ /* register the device and partition */
+ if (ext4_register_device(fs->dev_desc, part) != 0) {
+ printf("Unable to use %s %d:%lu for fattable\n",
+ argv[1], dev, part);
+ goto fail;
+ }
+
+ /* get the partition information */
+ if (!get_partition_info(fs->dev_desc, part, &info)) {
+ total_sector = (info.size * info.blksz) / SECTOR_SIZE;
+ fs->total_sect = total_sector;
+ } else {
+ printf("error : get partition info\n");
+ goto fail;
+ }
+
+ /* mount the filesystem */
+ if (!ext4fs_mount(part_length)) {
+ printf("Bad ext4 partition %s %d:%lu\n", argv[1], dev, part);
+ goto fail;
+ }
+
+ /* start write */
+ if (ext4fs_write(filename, (unsigned char *)ram_address, file_size)) {
+ printf("** Error ext4fs_write() **\n");
+ goto fail;
+ }
+ ext4fs_close();
+ deinit_fs(fs->dev_desc);
+
+ return 0;
+
+fail:
+ ext4fs_close();
+ deinit_fs(fs->dev_desc);
+
+ return 1;
+}
+
+U_BOOT_CMD(ext4write, 6, 1, do_ext4_write,
+ "create a file in the root directory",
+ "<interface> <dev[:part]> [Absolute filename path] [Address] [sizebytes]\n"
+ " - create a file in / directory");
+
+#endif
+
+U_BOOT_CMD(ext4ls, 4, 1, do_ext4_ls,
+ "list files in a directory (default /)",
+ "<interface> <dev[:part]> [directory]\n"
+ " - list files from 'dev' on 'interface' in a 'directory'");
+
+U_BOOT_CMD(ext4load, 6, 0, do_ext4_load,
+ "load binary file from a Ext4 filesystem",
+ "<interface> <dev[:part]> [addr] [filename] [bytes]\n"
+ " - load binary file 'filename' from 'dev' on 'interface'\n"
+ " to address 'addr' from ext4 filesystem");
--- /dev/null
+/*
+ * (C) Copyright 2011 - 2012 Samsung Electronics
+ * EXT2/4 filesystem implementation in Uboot by
+ * Uma Shankar <uma.shankar@samsung.com>
+ * Manjunatha C Achar <a.manjunatha@samsung.com>
+ *
+ * Ext4fs support
+ * made from existing cmd_ext2.c file of Uboot
+ *
+ * (C) Copyright 2004
+ * esd gmbh <www.esd-electronics.com>
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * made from cmd_reiserfs by
+ *
+ * (C) Copyright 2003 - 2004
+ * Sysgo Real-Time Solutions, AG <www.elinos.com>
+ * Pavel Bartusek <pba@sysgo.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/*
+ * Changelog:
+ * 0.1 - Newly created file for ext4fs support. Taken from cmd_ext2.c
+ * file in uboot. Added ext4fs ls load and write support.
+ */
+
+#include <common.h>
+#include <part.h>
+#include <config.h>
+#include <command.h>
+#include <image.h>
+#include <linux/ctype.h>
+#include <asm/byteorder.h>
+#include <ext_common.h>
+#include <ext4fs.h>
+#include <linux/stat.h>
+#include <malloc.h>
+
+#if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE)
+#include <usb.h>
+#endif
+
+#if !defined(CONFIG_DOS_PARTITION) && !defined(CONFIG_EFI_PARTITION)
+#error DOS or EFI partition support must be selected
+#endif
+
+#define DOS_PART_MAGIC_OFFSET 0x1fe
+#define DOS_FS_TYPE_OFFSET 0x36
+#define DOS_FS32_TYPE_OFFSET 0x52
+
+int do_ext_load(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ char *filename = NULL;
+ char *ep;
+ int dev;
+ unsigned long part = 1;
+ ulong addr = 0;
+ ulong part_length;
+ int filelen;
+ disk_partition_t info;
+ struct ext_filesystem *fs;
+ char buf[12];
+ unsigned long count;
+ const char *addr_str;
+
+ count = 0;
+ addr = simple_strtoul(argv[3], NULL, 16);
+ filename = getenv("bootfile");
+ switch (argc) {
+ case 3:
+ addr_str = getenv("loadaddr");
+ if (addr_str != NULL)
+ addr = simple_strtoul(addr_str, NULL, 16);
+ else
+ addr = CONFIG_SYS_LOAD_ADDR;
+
+ break;
+ case 4:
+ break;
+ case 5:
+ filename = argv[4];
+ break;
+ case 6:
+ filename = argv[4];
+ count = simple_strtoul(argv[5], NULL, 16);
+ break;
+
+ default:
+ return cmd_usage(cmdtp);
+ }
+
+ if (!filename) {
+ puts("** No boot file defined **\n");
+ return 1;
+ }
+
+ dev = (int)simple_strtoul(argv[2], &ep, 16);
+ ext4_dev_desc = get_dev(argv[1], dev);
+ if (ext4_dev_desc == NULL) {
+ printf("** Block device %s %d not supported\n", argv[1], dev);
+ return 1;
+ }
+ if (init_fs(ext4_dev_desc))
+ return 1;
+
+ fs = get_fs();
+ if (*ep) {
+ if (*ep != ':') {
+ puts("** Invalid boot device, use `dev[:part]' **\n");
+ goto fail;
+ }
+ part = simple_strtoul(++ep, NULL, 16);
+ }
+
+ if (part != 0) {
+ if (get_partition_info(fs->dev_desc, part, &info)) {
+ printf("** Bad partition %lu **\n", part);
+ goto fail;
+ }
+
+ if (strncmp((char *)info.type, BOOT_PART_TYPE,
+ strlen(BOOT_PART_TYPE)) != 0) {
+ printf("** Invalid partition type \"%s\""
+ " (expect \"" BOOT_PART_TYPE "\")\n", info.type);
+ goto fail;
+ }
+ printf("Loading file \"%s\" "
+ "from %s device %d:%lu %s\n",
+ filename, argv[1], dev, part, info.name);
+ } else {
+ printf("Loading file \"%s\" from %s device %d\n",
+ filename, argv[1], dev);
+ }
+
+ part_length = ext4fs_set_blk_dev(fs->dev_desc, part);
+ if (part_length == 0) {
+ printf("**Bad partition - %s %d:%lu **\n", argv[1], dev, part);
+ ext4fs_close();
+ goto fail;
+ }
+
+ if (!ext4fs_mount(part_length)) {
+ printf("** Bad ext2 partition or disk - %s %d:%lu **\n",
+ argv[1], dev, part);
+ ext4fs_close();
+ goto fail;
+ }
+
+ filelen = ext4fs_open(filename);
+ if (filelen < 0) {
+ printf("** File not found %s\n", filename);
+ ext4fs_close();
+ goto fail;
+ }
+ if ((count < filelen) && (count != 0))
+ filelen = count;
+
+ if (ext4fs_read((char *)addr, filelen) != filelen) {
+ printf("** Unable to read \"%s\" from %s %d:%lu **\n",
+ filename, argv[1], dev, part);
+ ext4fs_close();
+ goto fail;
+ }
+
+ ext4fs_close();
+ deinit_fs(fs->dev_desc);
+ /* Loading ok, update default load address */
+ load_addr = addr;
+
+ printf("%d bytes read\n", filelen);
+ sprintf(buf, "%X", filelen);
+ setenv("filesize", buf);
+
+ return 0;
+fail:
+ deinit_fs(fs->dev_desc);
+ return 1;
+}
+
+int do_ext_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ const char *filename = "/";
+ int dev;
+ unsigned long part = 1;
+ char *ep;
+ struct ext_filesystem *fs;
+ int part_length;
+ if (argc < 3)
+ return cmd_usage(cmdtp);
+
+ dev = (int)simple_strtoul(argv[2], &ep, 16);
+
+ ext4_dev_desc = get_dev(argv[1], dev);
+
+ if (ext4_dev_desc == NULL) {
+ printf("\n** Block device %s %d not supported\n", argv[1], dev);
+ return 1;
+ }
+
+ if (init_fs(ext4_dev_desc))
+ return 1;
+
+ fs = get_fs();
+ if (*ep) {
+ if (*ep != ':') {
+ puts("\n** Invalid boot device, use `dev[:part]' **\n");
+ goto fail;
+ }
+ part = simple_strtoul(++ep, NULL, 16);
+ }
+
+ if (argc == 4)
+ filename = argv[3];
+
+ part_length = ext4fs_set_blk_dev(fs->dev_desc, part);
+ if (part_length == 0) {
+ printf("** Bad partition - %s %d:%lu **\n", argv[1], dev, part);
+ ext4fs_close();
+ goto fail;
+ }
+
+ if (!ext4fs_mount(part_length)) {
+ printf("** Bad ext2 partition or disk - %s %d:%lu **\n",
+ argv[1], dev, part);
+ ext4fs_close();
+ goto fail;
+ }
+
+ if (ext4fs_ls(filename)) {
+ printf("** Error extfs_ls() **\n");
+ ext4fs_close();
+ goto fail;
+ };
+
+ ext4fs_close();
+ deinit_fs(fs->dev_desc);
+ return 0;
+
+fail:
+ deinit_fs(fs->dev_desc);
+ return 1;
+}
}
}
+ return CMD_RET_SUCCESS;
+ }
+
+ if (!working_fdt) {
+ puts(
+ "No FDT memory address configured. Please configure\n"
+ "the FDT address via \"fdt addr <address>\" command.\n"
+ "Aborting!\n");
+ return CMD_RET_FAILURE;
+ }
+
/*
* Move the working_fdt
*/
- } else if (strncmp(argv[1], "mo", 2) == 0) {
+ if (strncmp(argv[1], "mo", 2) == 0) {
struct fdt_header *newaddr;
int len;
int err;
rcode = flash_erase (info, s_first[bank], s_last[bank]);
}
}
- printf ("Erased %d sectors\n", erased);
+ if (rcode == 0)
+ printf("Erased %d sectors\n", erased);
} else if (rcode == 0) {
puts ("Error: start and/or end address"
" not on sector boundary\n");
U_BOOT_CMD(
mmcinfo, 1, 0, do_mmcinfo,
"display MMC info",
- " - device number of the device to dislay info of\n"
- ""
+ "- dislay info of the current MMC device"
);
int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
static void print_status(ulong start, ulong end, ulong erasesize, int status)
{
+ /*
+ * Micron NAND flash (e.g. MT29F4G08ABADAH4) BLOCK LOCK READ STATUS is
+ * not the same as others. Instead of bit 1 being lock, it is
+ * #lock_tight. To make the driver support either format, ignore bit 1
+ * and use only bit 0 and bit 2.
+ */
printf("%08lx - %08lx: %08lx blocks %s%s%s\n",
start,
end - 1,
(end - start) / erasesize,
((status & NAND_LOCK_STATUS_TIGHT) ? "TIGHT " : ""),
- ((status & NAND_LOCK_STATUS_LOCK) ? "LOCK " : ""),
+ (!(status & NAND_LOCK_STATUS_UNLOCK) ? "LOCK " : ""),
((status & NAND_LOCK_STATUS_UNLOCK) ? "UNLOCK " : ""));
}
return 0;
}
- if (strcmp(cmd, "unlock") == 0) {
+ if (strncmp(cmd, "unlock", 5) == 0) {
+ int allexcept = 0;
+
+ s = strchr(cmd, '.');
+
+ if (s && !strcmp(s, ".allexcept"))
+ allexcept = 1;
+
if (arg_off_size(argc - 2, argv + 2, &dev, &off, &size) < 0)
return 1;
- if (!nand_unlock(&nand_info[dev], off, size)) {
+ if (!nand_unlock(&nand_info[dev], off, size, allexcept)) {
puts("NAND flash successfully unlocked\n");
} else {
puts("Error unlocking NAND flash, "
"\n"
"nand lock [tight] [status]\n"
" bring nand to lock state or display locked pages\n"
- "nand unlock [offset] [size] - unlock section"
+ "nand unlock[.allexcept] [offset] [size] - unlock section"
#endif
#ifdef CONFIG_ENV_OFFSET_OOB
"\n"
#endif
/*
- * Set a new environment variable,
- * or replace or delete an existing one.
+ * Perform consistency checking before setting, replacing, or deleting an
+ * environment variable, then (if successful) apply the changes to internals so
+ * to make them effective. Code for this function was taken out of
+ * _do_env_set(), which now calls it instead.
+ * Also called as a callback function by himport_r().
+ * Returns 0 in case of success, 1 in case of failure.
+ * When (flag & H_FORCE) is set, do not print out any error message and force
+ * overwriting of write-once variables.
*/
-int _do_env_set(int flag, int argc, char * const argv[])
+
+int env_check_apply(const char *name, const char *oldval,
+ const char *newval, int flag)
{
- int i, len;
int console = -1;
- char *name, *value, *s;
- ENTRY e, *ep;
-
- name = argv[1];
-
- if (strchr(name, '=')) {
- printf("## Error: illegal character '=' in variable name"
- "\"%s\"\n", name);
- return 1;
- }
-
- env_id++;
- /*
- * search if variable with this name already exists
- */
- e.key = name;
- e.data = NULL;
- hsearch_r(e, FIND, &ep, &env_htab);
/* Check for console redirection */
if (strcmp(name, "stdin") == 0)
console = stderr;
if (console != -1) {
- if (argc < 3) { /* Cannot delete it! */
- printf("Can't delete \"%s\"\n", name);
+ if ((newval == NULL) || (*newval == '\0')) {
+ /* We cannot delete stdin/stdout/stderr */
+ if ((flag & H_FORCE) == 0)
+ printf("Can't delete \"%s\"\n", name);
return 1;
}
#ifdef CONFIG_CONSOLE_MUX
- i = iomux_doenv(console, argv[2]);
- if (i)
- return i;
+ if (iomux_doenv(console, newval))
+ return 1;
#else
/* Try assigning specified device */
- if (console_assign(console, argv[2]) < 0)
+ if (console_assign(console, newval) < 0)
return 1;
#ifdef CONFIG_SERIAL_MULTI
- if (serial_assign(argv[2]) < 0)
+ if (serial_assign(newval) < 0)
return 1;
#endif
#endif /* CONFIG_CONSOLE_MUX */
}
/*
- * Some variables like "ethaddr" and "serial#" can be set only
- * once and cannot be deleted; also, "ver" is readonly.
+ * Some variables like "ethaddr" and "serial#" can be set only once and
+ * cannot be deleted, unless CONFIG_ENV_OVERWRITE is defined.
*/
- if (ep) { /* variable exists */
#ifndef CONFIG_ENV_OVERWRITE
+ if (oldval != NULL && /* variable exists */
+ (flag & H_FORCE) == 0) { /* and we are not forced */
if (strcmp(name, "serial#") == 0 ||
(strcmp(name, "ethaddr") == 0
#if defined(CONFIG_OVERWRITE_ETHADDR_ONCE) && defined(CONFIG_ETHADDR)
- && strcmp(ep->data, MK_STR(CONFIG_ETHADDR)) != 0
+ && strcmp(oldval, MK_STR(CONFIG_ETHADDR)) != 0
#endif /* CONFIG_OVERWRITE_ETHADDR_ONCE && CONFIG_ETHADDR */
)) {
printf("Can't overwrite \"%s\"\n", name);
return 1;
}
+ }
#endif
+ /*
+ * When we change baudrate, or we are doing an env default -a
+ * (which will erase all variables prior to calling this),
+ * we want the baudrate to actually change - for real.
+ */
+ if (oldval != NULL || /* variable exists */
+ (flag & H_NOCLEAR) == 0) { /* or env is clear */
/*
* Switch to new baudrate if new baudrate is supported
*/
if (strcmp(name, "baudrate") == 0) {
- int baudrate = simple_strtoul(argv[2], NULL, 10);
+ int baudrate = simple_strtoul(newval, NULL, 10);
int i;
for (i = 0; i < N_BAUDRATES; ++i) {
if (baudrate == baudrate_table[i])
break;
}
if (i == N_BAUDRATES) {
- printf("## Baudrate %d bps not supported\n",
- baudrate);
+ if ((flag & H_FORCE) == 0)
+ printf("## Baudrate %d bps not "
+ "supported\n", baudrate);
return 1;
}
+ if (gd->baudrate == baudrate) {
+ /* If unchanged, we just say it's OK */
+ return 0;
+ }
printf("## Switch baudrate to %d bps and"
- "press ENTER ...\n", baudrate);
+ "press ENTER ...\n", baudrate);
udelay(50000);
gd->baudrate = baudrate;
#if defined(CONFIG_PPC) || defined(CONFIG_MCF52x2)
}
}
+ /*
+ * Some variables should be updated when the corresponding
+ * entry in the environment is changed
+ */
+ if (strcmp(name, "loadaddr") == 0) {
+ load_addr = simple_strtoul(newval, NULL, 16);
+ return 0;
+ }
+#if defined(CONFIG_CMD_NET)
+ else if (strcmp(name, "bootfile") == 0) {
+ copy_filename(BootFile, newval, sizeof(BootFile));
+ return 0;
+ }
+#endif
+ return 0;
+}
+
+/*
+ * Set a new environment variable,
+ * or replace or delete an existing one.
+*/
+int _do_env_set(int flag, int argc, char * const argv[])
+{
+ int i, len;
+ char *name, *value, *s;
+ ENTRY e, *ep;
+
+ name = argv[1];
+ value = argv[2];
+
+ if (strchr(name, '=')) {
+ printf("## Error: illegal character '='"
+ "in variable name \"%s\"\n", name);
+ return 1;
+ }
+
+ env_id++;
+ /*
+ * search if variable with this name already exists
+ */
+ e.key = name;
+ e.data = NULL;
+ hsearch_r(e, FIND, &ep, &env_htab);
+
+ /*
+ * Perform requested checks. Notice how since we are overwriting
+ * a single variable, we need to set H_NOCLEAR
+ */
+ if (env_check_apply(name, ep ? ep->data : NULL, value, H_NOCLEAR)) {
+ debug("check function did not approve, refusing\n");
+ return 1;
+ }
+
/* Delete only ? */
if (argc < 3 || argv[2] == NULL) {
- int rc = hdelete_r(name, &env_htab);
+ int rc = hdelete_r(name, &env_htab, 0);
return !rc;
}
return 1;
}
- /*
- * Some variables should be updated when the corresponding
- * entry in the environment is changed
- */
- if (strcmp(argv[1], "loadaddr") == 0) {
- load_addr = simple_strtoul(argv[2], NULL, 16);
- return 0;
- }
-#if defined(CONFIG_CMD_NET)
- else if (strcmp(argv[1], "bootfile") == 0) {
- copy_filename(BootFile, argv[2], sizeof(BootFile));
- return 0;
- }
-#endif
return 0;
}
return -1;
}
-static int do_env_default(cmd_tbl_t *cmdtp, int flag,
+static int do_env_default(cmd_tbl_t *cmdtp, int __flag,
int argc, char * const argv[])
{
- if (argc != 2 || strcmp(argv[1], "-f") != 0)
- return CMD_RET_USAGE;
+ int all = 0, flag = 0;
- set_default_env("## Resetting to default environment\n");
- return 0;
+ debug("Initial value for argc=%d\n", argc);
+ while (--argc > 0 && **++argv == '-') {
+ char *arg = *argv;
+
+ while (*++arg) {
+ switch (*arg) {
+ case 'a': /* default all */
+ all = 1;
+ break;
+ case 'f': /* force */
+ flag |= H_FORCE;
+ break;
+ default:
+ return cmd_usage(cmdtp);
+ }
+ }
+ }
+ debug("Final value for argc=%d\n", argc);
+ if (all && (argc == 0)) {
+ /* Reset the whole environment */
+ set_default_env("## Resetting to default environment\n");
+ return 0;
+ }
+ if (!all && (argc > 0)) {
+ /* Reset individual variables */
+ set_default_vars(argc, argv);
+ return 0;
+ }
+
+ return cmd_usage(cmdtp);
}
static int do_env_delete(cmd_tbl_t *cmdtp, int flag,
addr = (char *)ep->data;
}
- if (himport_r(&env_htab, addr, size, sep, del ? 0 : H_NOCLEAR) == 0) {
+ if (himport_r(&env_htab, addr, size, sep, del ? 0 : H_NOCLEAR,
+ 0, NULL, 0 /* do_apply */) == 0) {
error("Environment import failed: errno = %d\n", errno);
return 1;
}
#if defined(CONFIG_CMD_ASKENV)
"ask name [message] [size] - ask for environment variable\nenv "
#endif
- "default -f - reset default environment\n"
+ "default [-f] -a - [forcibly] reset default environment\n"
+ "env default [-f] var [...] - [forcibly] reset variable(s) to their default values\n"
#if defined(CONFIG_CMD_EDITENV)
"env edit name - edit environment variable\n"
#endif
+#if defined(CONFIG_CMD_EXPORTENV)
"env export [-t | -b | -c] [-s size] addr [var ...] - export environment\n"
+#endif
#if defined(CONFIG_CMD_GREPENV)
"env grep string [...] - search environment\n"
#endif
+#if defined(CONFIG_CMD_IMPORTENV)
"env import [-d] [-t | -b | -c] addr [size] - import environment\n"
+#endif
"env print [name ...] - print environment\n"
#if defined(CONFIG_CMD_RUN)
"env run var [...] - run commands in an environment variable\n"
#ifdef CONFIG_NEEDS_MANUAL_RELOC
void malloc_bin_reloc (void)
{
- unsigned long *p = (unsigned long *)(&av_[2]);
- int i;
- for (i=2; i<(sizeof(av_)/sizeof(mbinptr)); ++i) {
- *p++ += gd->reloc_off;
- }
+ mbinptr *p = &av_[2];
+ size_t i;
+
+ for (i = 2; i < ARRAY_SIZE(av_); ++i, ++p)
+ *p = (mbinptr)((ulong)*p + gd->reloc_off);
}
#endif
#ifdef CONFIG_ETH5ADDR
"eth5addr=" MK_STR(CONFIG_ETH5ADDR) "\0"
#endif
+#ifdef CONFIG_ETHPRIME
+ "ethprime=" CONFIG_ETHPRIME "\0"
+#endif
#ifdef CONFIG_IPADDR
"ipaddr=" MK_STR(CONFIG_IPADDR) "\0"
#endif
"\0"
};
-struct hsearch_data env_htab;
+struct hsearch_data env_htab = {
+ .apply = env_check_apply,
+};
static uchar __env_get_char_spec(int index)
{
void set_default_env(const char *s)
{
+ /*
+ * By default, do not apply changes as they will eventually
+ * be applied by someone else
+ */
+ int do_apply = 0;
if (sizeof(default_environment) > ENV_SIZE) {
puts("*** Error - default environment is too large\n\n");
return;
"using default environment\n\n",
s + 1);
} else {
+ /*
+ * This set_to_default was explicitly asked for
+ * by the user, as opposed to being a recovery
+ * mechanism. Therefore we check every single
+ * variable and apply changes to the system
+ * right away (e.g. baudrate, console).
+ */
+ do_apply = 1;
puts(s);
}
} else {
}
if (himport_r(&env_htab, (char *)default_environment,
- sizeof(default_environment), '\0', 0) == 0)
+ sizeof(default_environment), '\0', 0,
+ 0, NULL, do_apply) == 0)
error("Environment import failed: errno = %d\n", errno);
gd->flags |= GD_FLG_ENV_READY;
}
+
+/* [re]set individual variables to their value in the default environment */
+int set_default_vars(int nvars, char * const vars[])
+{
+ /*
+ * Special use-case: import from default environment
+ * (and use \0 as a separator)
+ */
+ return himport_r(&env_htab, (const char *)default_environment,
+ sizeof(default_environment), '\0', H_NOCLEAR,
+ nvars, vars, 1 /* do_apply */);
+}
+
/*
* Check if CRC is valid and (if yes) import the environment.
* Note that "buf" may or may not be aligned.
}
}
- if (himport_r(&env_htab, (char *)ep->data, ENV_SIZE, '\0', 0)) {
+ if (himport_r(&env_htab, (char *)ep->data, ENV_SIZE, '\0', 0,
+ 0, NULL, 0 /* do_apply */)) {
gd->flags |= GD_FLG_ENV_READY;
return 1;
}
int saveenv(void)
{
int ret = 0;
- env_t env_new;
+ ALLOC_CACHE_ALIGN_BUFFER(env_t, env_new, 1);
ssize_t len;
char *res;
nand_erase_options_t nand_erase_options;
if (CONFIG_ENV_RANGE < CONFIG_ENV_SIZE)
return 1;
- res = (char *)&env_new.data;
+ res = (char *)&env_new->data;
len = hexport_r(&env_htab, '\0', &res, ENV_SIZE, 0, NULL);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
return 1;
}
- env_new.crc = crc32(0, env_new.data, ENV_SIZE);
+ env_new->crc = crc32(0, env_new->data, ENV_SIZE);
puts("Erasing Nand...\n");
if (nand_erase_opts(&nand_info[0], &nand_erase_options))
return 1;
puts("Writing to Nand... ");
- if (writeenv(CONFIG_ENV_OFFSET, (u_char *)&env_new)) {
+ if (writeenv(CONFIG_ENV_OFFSET, (u_char *)env_new)) {
puts("FAILED!\n");
return 1;
}
{
#if !defined(ENV_IS_EMBEDDED)
int ret;
- char buf[CONFIG_ENV_SIZE];
+ ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE);
#if defined(CONFIG_ENV_OFFSET_OOB)
ret = get_nand_env_oob(&nand_info[0], &nand_env_oob_offset);
case ERR_PROG_ERROR:
puts ("General Flash Programming Error\n");
break;
+ case ERR_ABORTED:
+ puts("Flash Programming Aborted\n");
+ break;
default:
printf ("%s[%d] FIXME: rc=%d\n", __FILE__, __LINE__, err);
break;
#endif
#endif
#define SPECIAL_VAR_SYMBOL 03
+#define SUBSTED_VAR_SYMBOL 04
#ifndef __U_BOOT__
#define FLAG_EXIT_FROM_LOOP 1
#define FLAG_PARSE_SEMICOLON (1 << 1) /* symbol ';' is special for parser */
/* local variable support */
static char **make_list_in(char **inp, char *name);
static char *insert_var_value(char *inp);
+static char *insert_var_value_sub(char *inp, int tag_subst);
#ifndef __U_BOOT__
/* Table of built-in functions. They can be forked or not, depending on
static char *lookup_param(char *src)
{
char *p;
+ char *sep;
+ char *default_val = NULL;
+ int assign = 0;
+ int expand_empty = 0;
if (!src)
return NULL;
- p = getenv(src);
- if (!p)
- p = get_local_var(src);
+ sep = strchr(src, ':');
+
+ if (sep) {
+ *sep = '\0';
+ if (*(sep + 1) == '-')
+ default_val = sep+2;
+ if (*(sep + 1) == '=') {
+ default_val = sep+2;
+ assign = 1;
+ }
+ if (*(sep + 1) == '+') {
+ default_val = sep+2;
+ expand_empty = 1;
+ }
+ }
+
+ p = getenv(src);
+ if (!p)
+ p = get_local_var(src);
+
+ if (!p || strlen(p) == 0) {
+ p = default_val;
+ if (assign) {
+ char *var = malloc(strlen(src)+strlen(default_val)+2);
+ if (var) {
+ sprintf(var, "%s=%s", src, default_val);
+ set_local_var(var, 0);
+ }
+ free(var);
+ }
+ } else if (expand_empty) {
+ p += strlen(p);
+ }
+
+ if (sep)
+ *sep = ':';
return p;
}
return 1;
break;
#endif
+ case SUBSTED_VAR_SYMBOL:
+ dest->nonnull = 1;
+ while (ch = b_getch(input), ch != EOF &&
+ ch != SUBSTED_VAR_SYMBOL) {
+ debug_printf("subst, pass=%d\n", ch);
+ if (input->__promptme == 0)
+ return 1;
+ b_addchr(dest, ch);
+ }
+ debug_printf("subst, term=%d\n", ch);
+ if (ch == EOF) {
+ syntax();
+ return 1;
+ }
+ break;
default:
syntax(); /* this is really an internal logic error */
return 1;
mapset((uchar *)"\\$'\"`", 3); /* never flow through */
mapset((uchar *)"<>;&|(){}#", 1); /* flow through if quoted */
#else
+ {
+ uchar subst[2] = {SUBSTED_VAR_SYMBOL, 0};
+ mapset(subst, 3); /* never flow through */
+ }
mapset((uchar *)"\\$'\"", 3); /* never flow through */
mapset((uchar *)";&|#", 1); /* flow through if quoted */
#endif
#endif
static char *insert_var_value(char *inp)
+{
+ return insert_var_value_sub(inp, 0);
+}
+
+static char *insert_var_value_sub(char *inp, int tag_subst)
{
int res_str_len = 0;
int len;
char *p, *p1, *res_str = NULL;
while ((p = strchr(inp, SPECIAL_VAR_SYMBOL))) {
+ /* check the beginning of the string for normal charachters */
if (p != inp) {
+ /* copy any charachters to the result string */
len = p - inp;
res_str = xrealloc(res_str, (res_str_len + len));
strncpy((res_str + res_str_len), inp, len);
res_str_len += len;
}
inp = ++p;
+ /* find the ending marker */
p = strchr(inp, SPECIAL_VAR_SYMBOL);
*p = '\0';
+ /* look up the value to substitute */
if ((p1 = lookup_param(inp))) {
- len = res_str_len + strlen(p1);
+ if (tag_subst)
+ len = res_str_len + strlen(p1) + 2;
+ else
+ len = res_str_len + strlen(p1);
res_str = xrealloc(res_str, (1 + len));
- strcpy((res_str + res_str_len), p1);
+ if (tag_subst) {
+ /*
+ * copy the variable value to the result
+ * string
+ */
+ strcpy((res_str + res_str_len + 1), p1);
+
+ /*
+ * mark the replaced text to be accepted as
+ * is
+ */
+ res_str[res_str_len] = SUBSTED_VAR_SYMBOL;
+ res_str[res_str_len + 1 + strlen(p1)] =
+ SUBSTED_VAR_SYMBOL;
+ } else
+ /*
+ * copy the variable value to the result
+ * string
+ */
+ strcpy((res_str + res_str_len), p1);
+
res_str_len = len;
}
*p = SPECIAL_VAR_SYMBOL;
char *str = NULL;
int n;
int len = 2;
+ char *noeval_str;
+ int noeval = 0;
+ noeval_str = get_local_var("HUSH_NO_EVAL");
+ if (noeval_str != NULL && *noeval_str != '0' && *noeval_str != '\0')
+ noeval = 1;
for (n = 0; inp[n]; n++) {
- p = insert_var_value(inp[n]);
+ p = insert_var_value_sub(inp[n], noeval);
str = xrealloc(str, (len + strlen(p)));
if (n) {
strcat(str, " ");
printf("%s Architecture: %s\n", p, genimg_get_arch_name(arch));
}
- if (type == IH_TYPE_KERNEL) {
+ if ((type == IH_TYPE_KERNEL) || (type == IH_TYPE_RAMDISK)) {
fit_image_get_os(fit, image_noffset, &os);
printf("%s OS: %s\n", p, genimg_get_os_name(os));
}
if ((type == IH_TYPE_KERNEL) || (type == IH_TYPE_STANDALONE) ||
- (type == IH_TYPE_FIRMWARE)) {
+ (type == IH_TYPE_FIRMWARE) || (type == IH_TYPE_RAMDISK)) {
ret = fit_image_get_load(fit, image_noffset, &load);
printf("%s Load Address: ", p);
if (ret)
printf("0x%08lx\n", load);
}
- if ((type == IH_TYPE_KERNEL) || (type == IH_TYPE_STANDALONE)) {
+ if ((type == IH_TYPE_KERNEL) || (type == IH_TYPE_STANDALONE) ||
+ (type == IH_TYPE_RAMDISK)) {
fit_image_get_entry(fit, image_noffset, &entry);
printf("%s Entry Point: ", p);
if (ret)
#include <common.h>
#include <command.h>
#include <asm/processor.h>
+#include <asm/unaligned.h>
#include <linux/ctype.h>
#include <asm/byteorder.h>
#include <asm/unaligned.h>
int i;
ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, USB_BUFSIZ);
unsigned char *bitmap;
+ short hubCharacteristics;
struct usb_hub_descriptor *descriptor;
struct usb_hub_device *hub;
#ifdef USB_HUB_DEBUG
}
memcpy((unsigned char *)&hub->desc, buffer, descriptor->bLength);
/* adjust 16bit values */
- hub->desc.wHubCharacteristics =
- le16_to_cpu(descriptor->wHubCharacteristics);
+ put_unaligned(le16_to_cpu(get_unaligned(
+ &descriptor->wHubCharacteristics)),
+ &hub->desc.wHubCharacteristics);
/* set the bitmap */
bitmap = (unsigned char *)&hub->desc.DeviceRemovable[0];
/* devices not removable by default */
dev->maxchild = descriptor->bNbrPorts;
USB_HUB_PRINTF("%d ports detected\n", dev->maxchild);
- switch (hub->desc.wHubCharacteristics & HUB_CHAR_LPSM) {
+ hubCharacteristics = get_unaligned(&hub->desc.wHubCharacteristics);
+ switch (hubCharacteristics & HUB_CHAR_LPSM) {
case 0x00:
USB_HUB_PRINTF("ganged power switching\n");
break;
break;
}
- if (hub->desc.wHubCharacteristics & HUB_CHAR_COMPOUND)
+ if (hubCharacteristics & HUB_CHAR_COMPOUND)
USB_HUB_PRINTF("part of a compound device\n");
else
USB_HUB_PRINTF("standalone hub\n");
- switch (hub->desc.wHubCharacteristics & HUB_CHAR_OCPM) {
+ switch (hubCharacteristics & HUB_CHAR_OCPM) {
case 0x00:
USB_HUB_PRINTF("global over-current protection\n");
break;
struct usb_device *pusb_dev; /* this usb_device */
unsigned int flags; /* from filter initially */
+# define USB_READY (1 << 0)
unsigned char ifnum; /* interface number */
unsigned char ep_in; /* in endpoint */
unsigned char ep_out; /* out ....... */
trans_cmnd transport; /* transport routine */
};
+#ifdef CONFIG_USB_EHCI
/*
- * The U-Boot EHCI driver cannot handle more than 5 page aligned buffers
- * of 4096 bytes in a transfer without running itself out of qt_buffers
+ * The U-Boot EHCI driver can handle any transfer length as long as there is
+ * enough free heap space left, but the SCSI READ(10) and WRITE(10) commands are
+ * limited to 65535 blocks.
*/
-#define USB_MAX_XFER_BLK(start, blksz) (((4096 * 5) - (start % 4096)) / blksz)
+#define USB_MAX_XFER_BLK 65535
+#else
+#define USB_MAX_XFER_BLK 20
+#endif
static struct us_data usb_stor[USB_MAX_STOR_DEV];
usb_stor_BBB_reset(us);
return USB_STOR_TRANSPORT_FAILED;
}
- mdelay(5);
+ if (!(us->flags & USB_READY))
+ mdelay(5);
pipein = usb_rcvbulkpipe(us->pusb_dev, us->ep_in);
pipeout = usb_sndbulkpipe(us->pusb_dev, us->ep_out);
/* DATA phase + error handling */
srb->cmd[1] = srb->lun << 5;
srb->datalen = 0;
srb->cmdlen = 12;
- if (ss->transport(srb, ss) == USB_STOR_TRANSPORT_GOOD)
+ if (ss->transport(srb, ss) == USB_STOR_TRANSPORT_GOOD) {
+ ss->flags |= USB_READY;
return 0;
+ }
usb_request_sense(srb, ss);
mdelay(100);
} while (retries--);
unsigned long usb_stor_read(int device, unsigned long blknr,
unsigned long blkcnt, void *buffer)
{
- unsigned long start, blks, buf_addr, max_xfer_blk;
+ unsigned long start, blks, buf_addr;
unsigned short smallblks;
struct usb_device *dev;
struct us_data *ss;
buf_addr = (unsigned long)buffer;
start = blknr;
blks = blkcnt;
- if (usb_test_unit_ready(srb, ss)) {
- printf("Device NOT ready\n Request Sense returned %02X %02X"
- " %02X\n", srb->sense_buf[2], srb->sense_buf[12],
- srb->sense_buf[13]);
- return 0;
- }
USB_STOR_PRINTF("\nusb_read: dev %d startblk %lx, blccnt %lx"
" buffer %lx\n", device, start, blks, buf_addr);
/* XXX need some comment here */
retry = 2;
srb->pdata = (unsigned char *)buf_addr;
- max_xfer_blk = USB_MAX_XFER_BLK(buf_addr,
- usb_dev_desc[device].blksz);
- if (blks > max_xfer_blk)
- smallblks = (unsigned short) max_xfer_blk;
+ if (blks > USB_MAX_XFER_BLK)
+ smallblks = USB_MAX_XFER_BLK;
else
smallblks = (unsigned short) blks;
retry_it:
- if (smallblks == max_xfer_blk)
+ if (smallblks == USB_MAX_XFER_BLK)
usb_show_progress();
srb->datalen = usb_dev_desc[device].blksz * smallblks;
srb->pdata = (unsigned char *)buf_addr;
blks -= smallblks;
buf_addr += srb->datalen;
} while (blks != 0);
+ ss->flags &= ~USB_READY;
USB_STOR_PRINTF("usb_read: end startblk %lx, blccnt %x buffer %lx\n",
start, smallblks, buf_addr);
usb_disable_asynch(0); /* asynch transfer allowed */
- if (blkcnt >= max_xfer_blk)
+ if (blkcnt >= USB_MAX_XFER_BLK)
debug("\n");
return blkcnt;
}
unsigned long usb_stor_write(int device, unsigned long blknr,
unsigned long blkcnt, const void *buffer)
{
- unsigned long start, blks, buf_addr, max_xfer_blk;
+ unsigned long start, blks, buf_addr;
unsigned short smallblks;
struct usb_device *dev;
struct us_data *ss;
buf_addr = (unsigned long)buffer;
start = blknr;
blks = blkcnt;
- if (usb_test_unit_ready(srb, ss)) {
- printf("Device NOT ready\n Request Sense returned %02X %02X"
- " %02X\n", srb->sense_buf[2], srb->sense_buf[12],
- srb->sense_buf[13]);
- return 0;
- }
USB_STOR_PRINTF("\nusb_write: dev %d startblk %lx, blccnt %lx"
" buffer %lx\n", device, start, blks, buf_addr);
*/
retry = 2;
srb->pdata = (unsigned char *)buf_addr;
- max_xfer_blk = USB_MAX_XFER_BLK(buf_addr,
- usb_dev_desc[device].blksz);
- if (blks > max_xfer_blk)
- smallblks = (unsigned short) max_xfer_blk;
+ if (blks > USB_MAX_XFER_BLK)
+ smallblks = USB_MAX_XFER_BLK;
else
smallblks = (unsigned short) blks;
retry_it:
- if (smallblks == max_xfer_blk)
+ if (smallblks == USB_MAX_XFER_BLK)
usb_show_progress();
srb->datalen = usb_dev_desc[device].blksz * smallblks;
srb->pdata = (unsigned char *)buf_addr;
blks -= smallblks;
buf_addr += srb->datalen;
} while (blks != 0);
+ ss->flags &= ~USB_READY;
USB_STOR_PRINTF("usb_write: end startblk %lx, blccnt %x buffer %lx\n",
start, smallblks, buf_addr);
usb_disable_asynch(0); /* asynch transfer allowed */
- if (blkcnt >= max_xfer_blk)
+ if (blkcnt >= USB_MAX_XFER_BLK)
debug("\n");
return blkcnt;
cap[0] = 2880;
cap[1] = 0x200;
}
+ ss->flags &= ~USB_READY;
USB_STOR_PRINTF("Read Capacity returns: 0x%lx, 0x%lx\n", cap[0],
cap[1]);
#if 0
*/
int test_part_mac (block_dev_desc_t *dev_desc)
{
- mac_driver_desc_t ddesc;
- mac_partition_t mpart;
+ ALLOC_CACHE_ALIGN_BUFFER(mac_driver_desc_t, ddesc, 1);
+ ALLOC_CACHE_ALIGN_BUFFER(mac_partition_t, mpart, 1);
ulong i, n;
- if (part_mac_read_ddb (dev_desc, &ddesc)) {
+ if (part_mac_read_ddb (dev_desc, ddesc)) {
/* error reading Driver Desriptor Block, or no valid Signature */
return (-1);
}
n = 1; /* assuming at least one partition */
for (i=1; i<=n; ++i) {
- if ((dev_desc->block_read(dev_desc->dev, i, 1, (ulong *)&mpart) != 1) ||
- (mpart.signature != MAC_PARTITION_MAGIC) ) {
+ if ((dev_desc->block_read(dev_desc->dev, i, 1, (ulong *)mpart) != 1) ||
+ (mpart->signature != MAC_PARTITION_MAGIC) ) {
return (-1);
}
/* update partition count */
- n = mpart.map_count;
+ n = mpart->map_count;
}
return (0);
}
void print_part_mac (block_dev_desc_t *dev_desc)
{
ulong i, n;
- mac_driver_desc_t ddesc;
- mac_partition_t mpart;
+ ALLOC_CACHE_ALIGN_BUFFER(mac_driver_desc_t, ddesc, 1);
+ ALLOC_CACHE_ALIGN_BUFFER(mac_partition_t, mpart, 1);
ldiv_t mb, gb;
- if (part_mac_read_ddb (dev_desc, &ddesc)) {
+ if (part_mac_read_ddb (dev_desc, ddesc)) {
/* error reading Driver Desriptor Block, or no valid Signature */
return;
}
- n = ddesc.blk_count;
+ n = ddesc->blk_count;
- mb = ldiv(n, ((1024 * 1024) / ddesc.blk_size)); /* MB */
+ mb = ldiv(n, ((1024 * 1024) / ddesc->blk_size)); /* MB */
/* round to 1 digit */
- mb.rem *= 10 * ddesc.blk_size;
+ mb.rem *= 10 * ddesc->blk_size;
mb.rem += 512 * 1024;
mb.rem /= 1024 * 1024;
"DeviceType=0x%x, DeviceId=0x%x\n\n"
" #: type name"
" length base (size)\n",
- ddesc.blk_size,
- ddesc.blk_count,
+ ddesc->blk_size,
+ ddesc->blk_count,
mb.quot, mb.rem, gb.quot, gb.rem,
- ddesc.dev_type, ddesc.dev_id
+ ddesc->dev_type, ddesc->dev_id
);
n = 1; /* assuming at least one partition */
char c;
printf ("%4ld: ", i);
- if (dev_desc->block_read (dev_desc->dev, i, 1, (ulong *)&mpart) != 1) {
+ if (dev_desc->block_read (dev_desc->dev, i, 1, (ulong *)mpart) != 1) {
printf ("** Can't read Partition Map on %d:%ld **\n",
dev_desc->dev, i);
return;
}
- if (mpart.signature != MAC_PARTITION_MAGIC) {
+ if (mpart->signature != MAC_PARTITION_MAGIC) {
printf ("** Bad Signature on %d:%ld - "
"expected 0x%04x, got 0x%04x\n",
- dev_desc->dev, i, MAC_PARTITION_MAGIC, mpart.signature);
+ dev_desc->dev, i, MAC_PARTITION_MAGIC, mpart->signature);
return;
}
/* update partition count */
- n = mpart.map_count;
+ n = mpart->map_count;
c = 'k';
- bytes = mpart.block_count;
- bytes /= (1024 / ddesc.blk_size); /* kB; assumes blk_size == 512 */
+ bytes = mpart->block_count;
+ bytes /= (1024 / ddesc->blk_size); /* kB; assumes blk_size == 512 */
if (bytes >= 1024) {
bytes >>= 10;
c = 'M';
}
printf ("%20.32s %-18.32s %10u @ %-10u (%3ld%c)\n",
- mpart.type,
- mpart.name,
- mpart.block_count,
- mpart.start_block,
+ mpart->type,
+ mpart->name,
+ mpart->block_count,
+ mpart->start_block,
bytes, c
);
}
int get_partition_info_mac (block_dev_desc_t *dev_desc, int part, disk_partition_t *info)
{
- mac_driver_desc_t ddesc;
- mac_partition_t mpart;
+ ALLOC_CACHE_ALIGN_BUFFER(mac_driver_desc_t, ddesc, 1);
+ ALLOC_CACHE_ALIGN_BUFFER(mac_partition_t, mpart, 1);
- if (part_mac_read_ddb (dev_desc, &ddesc)) {
+ if (part_mac_read_ddb (dev_desc, ddesc)) {
return (-1);
}
- info->blksz = ddesc.blk_size;
+ info->blksz = ddesc->blk_size;
- if (part_mac_read_pdb (dev_desc, part, &mpart)) {
+ if (part_mac_read_pdb (dev_desc, part, mpart)) {
return (-1);
}
- info->start = mpart.start_block;
- info->size = mpart.block_count;
- memcpy (info->type, mpart.type, sizeof(info->type));
- memcpy (info->name, mpart.name, sizeof(info->name));
+ info->start = mpart->start_block;
+ info->size = mpart->block_count;
+ memcpy (info->type, mpart->type, sizeof(info->type));
+ memcpy (info->name, mpart->name, sizeof(info->name));
return (0);
}
This this case CPU will be set to "normal_cpu" during the main u-boot
build and "spl_cpu" during the SPL build.
+
+
+Debugging
+---------
+
+When building SPL with DEBUG set you may also need to set CONFIG_PANIC_HANG
+as in most cases do_reset is not defined within SPL.
+
+
+Estimating stack usage
+----------------------
+
+With gcc 4.6 (and later) and the use of GNU cflow it is possible to estimate
+stack usage at various points in run sequence of SPL. The -fstack-usage option
+to gcc will produce '.su' files (such as arch/arm/cpu/armv7/syslib.su) that
+will give stack usage information and cflow can construct program flow.
+
+Must have gcc 4.6 or later, which supports -fstack-usage
+
+1) Build normally
+2) Perform the following shell command to generate a list of C files used in
+SPL:
+$ find spl -name '*.su' | sed -e 's:^spl/::' -e 's:[.]su$:.c:' > used-spl.list
+3) Execute cflow:
+$ cflow --main=board_init_r `cat used-spl.list` 2>&1 | $PAGER
+
+cflow will spit out a number of warnings as it does not parse
+the config files and picks functions based on #ifdef. Parsing the '.i'
+files instead introduces another set of headaches. These warnings are
+not usually important to understanding the flow, however.
--- /dev/null
+This patch series adds support for ext4 ls,load and write features in uboot
+Journaling is supported for write feature.
+
+To Enable ext2 ls and load commands, modify the board specific config file with
+#define CONFIG_CMD_EXT2
+
+To Enable ext4 ls and load commands, modify the board specific config file with
+#define CONFIG_CMD_EXT4
+
+To enable ext4 write command, modify the board specific config file with
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+
+Steps to test:
+
+1. After applying the patch, ext4 specific commands can be seen
+ in the boot loader prompt using
+ UBOOT #help
+
+ ext4load- load binary file from a Ext4 file system
+ ext4ls - list files in a directory (default /)
+ ext4write- create a file in ext4 formatted partition
+
+2. To list the files in ext4 formatted partition, execute
+ ext4ls <interface> <dev[:part]> [directory]
+ For example:
+ UBOOT #ext4ls mmc 0:5 /usr/lib
+
+3. To read and load a file from an ext4 formatted partition to RAM, execute
+ ext4load <interface> <dev[:part]> [addr] [filename] [bytes]
+ For example:
+ UBOOT #ext4load mmc 2:2 0x30007fc0 uImage
+
+4. To write a file to a ext4 formatted partition.
+ a) First load a file to RAM at a particular address for example 0x30007fc0.
+ Now execute ext4write command
+ ext4write <interface> <dev[:part]> [filename] [Address] [sizebytes]
+ For example:
+ UBOOT #ext4write mmc 2:2 /boot/uImage 0x30007fc0 6183120
+ (here 6183120 is the size of the file to be written)
+ Note: Absolute path is required for the file to be written
+
+References :
+ -- ext4 implementation in Linux Kernel
+ -- Uboot existing ext2 load and ls implementation
+ -- Journaling block device JBD2 implementation in linux Kernel
"nand unlock [offset] [size]"
unlock consecutive area (can be called multiple times for different areas)
+ "nand unlock.allexcept [offset] [size]"
+ unlock all except specified consecutive area
I have tested the code with board containing 128MiB NAND large page chips
and 32MiB small page chips.
Board Arch CPU removed Commit last known maintainer/contact
=============================================================================
+apollon arm omap24xx - 2012-09-06 Kyungmin Park <kyungmin.park@samsung.com>
tb0229 mips mips32 - 2011-12-12
rmu powerpc MPC850 fb82fd7 2011-12-07 Wolfgang Denk <wd@denx.de>
OXC powerpc MPC8240 309a292 2011-12-07
completing. Note that CONFIG_SYS_TEXT_BASE must be clear of the areas that SPL
uses while running. This is why we have two versions of the memory map that
only vary in where the BSS and malloc pool reside.
-
-Estimating stack usage
-----------------------
-
-With gcc 4.6 (and later) and the use of GNU cflow it is possible to estimate
-stack usage at various points in run sequence of SPL. The -fstack-usage option
-to gcc will produce '.su' files (such as arch/arm/cpu/armv7/syslib.su) that
-will give stack usage information and cflow can construct program flow.
-
-Must have gcc 4.6 or later, which supports -fstack-usage
-
-1) Build normally
-2) Perform the following shell command to generate a list of C files used in
-SPL:
-$ find spl -name '*.su' | sed -e 's:^spl/::' -e 's:[.]su$:.c:' > used-spl.list
-3) Execute cflow:
-$ cflow --main=board_init_r `cat used-spl.list` 2>&1 | $PAGER
-
-cflow will spit out a number of warnings as it does not parse
-the config files and picks functions based on #ifdef. Parsing the '.i'
-files instead introduces another set of headaches. These warnings are
-not usually important to understanding the flow, however.
--- /dev/null
+The U-Boot Driver Model Project
+===============================
+Block device subsystem analysis
+===============================
+
+Pavel Herrmann <morpheus.ibis@gmail.com>
+2012-03-08
+
+I) Overview
+-----------
+
+ U-Boot currently implements several distinct APIs for block devices - some
+ drivers use the SATA API, some drivers use the IDE API, sym53c8xx and
+ AHCI use the SCSI API, mg_disk has a separate API, and systemace also has a
+ separate API. There are also MMC and USB APIs used outside of drivers/block,
+ those will be detailed in their specific documents.
+
+ Block devices are described by block_dev_desc structure, that holds, among
+ other things, the read/write/erase callbacks. Block device structures are
+ stored in any way depending on the API, but can be accessed by
+
+ block_dev_desc_t * $api_get_dev(int dev)
+
+ function, as seen in disk/part.c.
+
+ 1) SATA interface
+ -----------------
+
+ The SATA interface drivers implement the following functions:
+
+ int init_sata(int dev)
+ int scan_sata(int dev)
+ ulong sata_read(int dev, ulong blknr, ulong blkcnt, void *buffer)
+ ulong sata_write(int dev, ulong blknr, ulong blkcnt, const void *buffer)
+
+ Block devices are kept in sata_dev_desc[], which is prefilled with values
+ common to all SATA devices in cmd_sata.c, and then modified in init_sata
+ function in the drivers. Callbacks of the block device use SATA API
+ directly. The sata_get_dev function is defined in cmd_sata.c.
+
+ 2) SCSI interface
+ -----------------
+
+ The SCSI interface drivers implement the following functions:
+
+ void scsi_print_error(ccb *pccb)
+ int scsi_exec(ccb *pccb)
+ void scsi_bus_reset(void)
+ void scsi_low_level_init(int busdevfunc)
+
+ The SCSI API works through the scsi_exec function, the actual operation
+ requested is found in the ccb structure.
+
+ Block devices are kept in scsi_dev_desc[], which lives only in cmd_scsi.c.
+ Callbacks of the block device use functions from cmd_scsi.c, which in turn
+ call scsi_exec of the controller. The scsi_get_dev function is also defined
+ in cmd_scsi.c.
+
+ 3) mg_disk interface
+ --------------------
+
+ The mg_disk interface drivers implement the following functions:
+
+ struct mg_drv_data* mg_get_drv_data (void)
+ uint mg_disk_init (void)
+ uint mg_disk_read (u32 addr, u8 *buff, u32 len)
+ uint mg_disk_write(u32 addr, u8 *buff, u32 len)
+ uint mg_disk_write_sects(void *buff, u32 sect_num, u32 sect_cnt)
+ uint mg_disk_read_sects(void *buff, u32 sect_num, u32 sect_cnt)
+
+ The mg_get_drv_data function is to be overridden per-board, but there are no
+ board in-tree that do this.
+
+ Only one driver for this API exists, and it only supports one block device.
+ Callbacks for this device are implemented in mg_disk.c and call the mg_disk
+ API. The mg_disk_get_dev function is defined in mg_disk.c and ignores the
+ device number, always returning the same device.
+
+ 4) systemace interface
+ ----------------------
+
+ The systemace interface does not define any driver API, and has no command
+ itself. The single defined function is systemace_get_devs() from
+ systemace.c, which returns a single static structure for the only supported
+ block device. Callbacks for this device are also implemented in systemace.c.
+
+ 5) IDE interface
+ ----------------
+
+ The IDE interface drivers implement the following functions, but only if
+ CONFIG_IDE_AHB is set:
+
+ uchar ide_read_register(int dev, unsigned int port);
+ void ide_write_register(int dev, unsigned int port, unsigned char val);
+ void ide_read_data(int dev, ulong *sect_buf, int words);
+ void ide_write_data(int dev, ulong *sect_buf, int words);
+
+ The first two functions are called from ide_inb()/ide_outb(), and will
+ default to direct memory access if CONFIG_IDE_AHB is not set, or
+ ide_inb()/ide_outb() functions will get overridden by the board altogether.
+
+ The second two functions are called from input_data()/output_data()
+ functions, and also default to direct memory access, but cannot be
+ overridden by the board.
+
+ One function shared by IDE drivers (but not defined in ide.h) is
+ int ide_preinit(void)
+ This function gets called from ide_init in cmd_ide.c if CONFIG_IDE_PREINIT
+ is defined, and will do the driver-specific initialization of the device.
+
+ Block devices are kept in ide_dev_desc[], which is filled in cmd_ide.c.
+ Callbacks of the block device are defined in cmd_ide.c, and use the
+ ide_inb()/ide_outb()/input_data()/output_data() functions mentioned above.
+ The ide_get_dev function is defined in cmd_ide.c.
+
+II) Approach
+------------
+
+ A new block controller core and an associated API will be created to mimic the
+ current SATA API, its drivers will have the following ops:
+
+ struct block_ctrl_ops {
+ int scan(instance *i);
+ int reset(instance *i, int port);
+ lbaint_t read(instance *i, int port, lbaint_t start, lbatin_t length,
+ void *buffer);
+ lbaint_t write(instance *i, int port, lbaint_t start, lbatin_t length,
+ void*buffer);
+ }
+
+ The current sata_init() function will be changed into the driver probe()
+ function. The read() and write() functions should never be called directly,
+ instead they should be called by block device driver for disks.
+
+ Other block APIs would either be transformed into this API, or be kept as
+ legacy for old drivers, or be dropped altogether.
+
+ Legacy driver APIs will each have its own driver core that will contain the
+ shared logic, which is currently located mostly in cmd_* files. Callbacks for
+ block device drivers will then probably be implemented as a part of the core
+ logic, and will use the driver ops (which will copy current state of
+ respective APIs) to do the work.
+
+ All drivers will be cleaned up, most ifdefs should be converted into
+ platform_data, to enable support for multiple devices with different settings.
+
+ A new block device core will also be created, and will keep track of all
+ block devices on all interfaces.
+
+ Current block_dev_desc structure will be changed to fit the driver model, all
+ identification and configuration will be placed in private data, and
+ a single accessor and modifier will be defined, to accommodate the need for
+ different sets of options for different interfaces, while keeping the
+ structure small. The new block device drivers will have the following ops
+ structure (lbaint_t is either 32bit or 64bit unsigned, depending on
+ CONFIG_LBA48):
+
+ struct blockdev_ops {
+ lbaint_t (*block_read)(struct instance *i, lbaint_t start, lbaint_t blkcnt,
+ void *buffer);
+ lbaint_t (*block_write)(struct instance *i, lbaint_t start, lbaint_t blkcnt,
+ void *buffer);
+ lbaint_t (*block_erase)(struct instance *i, lbaint_t start, lbaint_t blkcnt
+ );
+ int (*get_option)(struct instance *i, enum blockdev_option_code op,
+ struct option *res);
+ int (*set_option)(struct instance *i, enum blockdev_option_code op,
+ struct option *val);
+ }
+
+ struct option {
+ uint32_t flags
+ union data {
+ uint64_t data_u;
+ char* data_s;
+ void* data_p;
+ }
+ }
+
+ enum blockdev_option_code {
+ BLKD_OPT_IFTYPE=0,
+ BLKD_OPT_TYPE,
+ BLKD_OPT_BLOCKSIZE,
+ BLKD_OPT_BLOCKCOUNT,
+ BLKD_OPT_REMOVABLE,
+ BLKD_OPT_LBA48,
+ BLKD_OPT_VENDOR,
+ BLKD_OPT_PRODICT,
+ BLKD_OPT_REVISION,
+ BLKD_OPT_SCSILUN,
+ BLKD_OPT_SCSITARGET,
+ BLKD_OPT_OFFSET
+ }
+
+ Flags in option above will contain the type of returned data (which should be
+ checked against what is expected, even though the option requested should
+ specify it), and a flag to indicate whether the returned pointer needs to be
+ free()'d.
+
+ The block device core will contain the logic now located in disk/part.c and
+ related files, and will be used to forward requests to block devices. The API
+ for the block device core will copy the ops of a block device (with a string
+ identifier instead of instance pointer). This means that partitions will also
+ be handled by the block device core, and exported as block devices, making
+ them transparent to the rest of the code.
+
+ Sadly, this will change how file systems can access the devices, and thus will
+ affect a lot of places. However, these changes should be localized and easy to
+ implement.
+
+ AHCI driver will be rewritten to fit the new unified block controller API,
+ making SCSI API easy to merge with sym53c8xx, or remove it once the device
+ driver has died.
+
+ Optionally, IDE core may be changed into one driver with unified block
+ controller API, as most of it is already in one place and device drivers are
+ just sets of hooks. Additionally, mg_disk driver is unused and may be removed
+ in near future.
+
+
+
+III) Analysis of in-tree drivers
+--------------------------------
+
+ 1) ahci.c
+ ---------
+ SCSI API, will be rewritten for a different API.
+
+ 2) ata_piix.c
+ -------------
+ SATA API, easy to port.
+
+ 3) fsl_sata.c
+ -------------
+ SATA API, few CONFIG macros, easy to port.
+
+ 4) ftide020.c
+ -------------
+ IDE API, defines CONFIG_IDE_AHB and ide_preinit hook functions.
+
+ 5) mg_disk.c
+ ------------
+ Single driver with mg_disk API, not much to change, easy to port.
+
+ 6) mvsata_ide.c
+ ---------------
+ IDE API, only defines ide_preinit hook function.
+
+ 7) mxc_ata.c
+ ------------
+ IDE API, only defines ide_preinit hook function.
+
+ 8) pata_bfin.c
+ --------------
+ SATA API, easy to port.
+
+ 9) sata_dwc.c
+ -------------
+ SATA API, easy to port.
+
+ 10) sata_sil3114.c
+ ------------------
+ SATA API, easy to port.
+
+ 11) sata_sil.c
+ --------------
+ SATA API, easy to port.
+
+ 12) sil680.c
+ ------------
+ IDE API, only defines ide_preinit hook function.
+
+ 13) sym53c8xx.c
+ ---------------
+ SCSI API, may be merged with code from cmd_scsi.
+
+ 14) systemace.c
+ ---------------
+ Single driver with systemace API, not much to change, easy to port.
--- /dev/null
+The U-Boot Driver Model Project
+===============================
+Driver cores API document
+=========================
+
+Pavel Herrmann <morpheus.ibis@gmail.com>
+
+1) Overview
+-----------
+ Driver cores will be used as a wrapper for devices of the same type, and as
+ an abstraction for device driver APIs. For each driver API (which roughly
+ correspond to device types), there will be one driver core. Each driver core
+ will implement three APIs - a driver API (which will be the same as API of
+ drivers the core wraps around), a core API (which will be implemented by all
+ cores) and a command API (core-specific API which will be exposed to
+ commands).
+
+ A) Command API
+ The command API will provide access to shared functionality for a specific
+ device, which is currently located mostly in commands. Commands will be
+ rewritten to be more lightweight by using this API. As this API will be
+ different for each core, it is out of scope of this document.
+
+ B) Driver API
+ The driver API will act as a wrapper around actual device drivers,
+ providing a single entrypoint for device access. All functions in this API
+ have an instance* argument (probably called "this" or "i"), which will be
+ examined by the core, and a correct function for the specified driver will
+ get called.
+
+ If the core gets called with a group instance pointer (as discussed in
+ design), it will automatically select the instance that is associated
+ with this core, and use it as target of the call. if the group contains
+ multiple instances of a single type, the caller must explicitly use an
+ accessor to select the correct instance.
+
+ This accessor will look like:
+ struct instance *get_instance_from_group(struct instance *group, int i)
+
+ When called with a non-group instance, it will simply return the instance.
+
+ C) Core API
+ The core API will be implemented by all cores, and will provide
+ functionality for getting driver instances from non-driver code. This API
+ will consist of following functions:
+
+ int get_count(struct instance *core);
+ struct instance* get_instance(struct instance *core, int index);
+ int init(struct instance *core);
+ int bind(struct instance *core, struct instance *dev, void *ops,
+ void *hint);
+ int unbind(struct instance *core, instance *dev);
+ int replace(struct instance *core, struct_instance *new_dev,
+ struct instance *old_dev);
+ int destroy(struct instance *core);
+ int reloc(struct instance *new_core, struct instance *old_core);
+
+ The 'hint' parameter of bind() serves for additional data a driver can
+ pass to the core, to help it create the correct internal state for this
+ instance. the replace() function will get called during instance
+ relocation, and will replace the old instance with the new one, keeping
+ the internal state untouched.
+
+
+2) Lifetime of a driver core
+----------------------------
+ Driver cores will be initialized at runtime, to limit memory footprint in
+ early-init stage, when we have to fit into ~1KB of memory. All active cores
+ will be stored in a tree structure (referenced as "Core tree") in global data,
+ which provides good tradeoff between size and access time.
+ Every core will have a number constant associated with it, which will be used
+ to find the instance in Core tree, and to refer to the core in all calls
+ working with the Core tree.
+ The Core Tree should be implemented using B-tree (or a similar structure)
+ to guarantee acceptable time overhead in all cases.
+
+ Code for working with the core (i2c in this example) follows:
+
+ core_init(CORE_I2C);
+ This will check whether we already have a i2c core, and if not it creates
+ a new instance and adds it into the Core tree. This will not be exported,
+ all code should depend on get_core_instance to init the core when
+ necessary.
+
+ get_core_instance(CORE_I2C);
+ This is an accessor into the Core tree, which will return the instance
+ of i2c core, creating it if necessary
+
+ core_bind(CORE_I2C, instance, driver_ops);
+ This will get called in bind() function of a driver, and will add the
+ instance into cores internal list of devices. If the core is not found, it
+ will get created.
+
+ driver_activate(instance *inst);
+ This call will recursively activate all devices necessary for using the
+ specified device. the code could be simplified as:
+ {
+ if (is_activated(inst))
+ return;
+ driver_activate(inst->bus);
+ get_driver(inst)->probe(inst);
+ }
+
+ The case with multiple parents will need to be handled here as well.
+ get_driver is an accessor to available drivers, which will get struct
+ driver based on a name in the instance.
+
+ i2c_write(instance *inst, ...);
+ An actual call to some method of the driver. This code will look like:
+ {
+ driver_activate(inst);
+ struct instance *core = get_core_instance(CORE_I2C);
+ device_ops = get_ops(inst);
+ device_ops->write(...);
+ }
+
+ get_ops will not be an exported function, it will be internal and specific
+ to the core, as it needs to know how are the ops stored, and what type
+ they are.
+
+ Please note that above examples represent the algorithm, not the actual code,
+ as they are missing checks for validity of return values.
+
+ core_init() function will get called the first time the core is requested,
+ either by core_link() or core_get_instance(). This way, the cores will get
+ created only when they are necessary, which will reduce our memory footprint.
--- /dev/null
+The U-Boot Driver Model Project
+===============================
+Design document
+===============
+Marek Vasut <marek.vasut@gmail.com>
+Pavel Herrmann <morpheus.ibis@gmail.com>
+2012-05-17
+
+I) The modular concept
+----------------------
+
+The driver core design is done with modularity in mind. The long-term plan is to
+extend this modularity to allow loading not only drivers, but various other
+objects into U-Boot at runtime -- like commands, support for other boards etc.
+
+II) Driver core initialization stages
+-------------------------------------
+
+The drivers have to be initialized in two stages, since the U-Boot bootloader
+runs in two stages itself. The first stage is the one which is executed before
+the bootloader itself is relocated. The second stage then happens after
+relocation.
+
+ 1) First stage
+ --------------
+
+ The first stage runs after the bootloader did very basic hardware init. This
+ means the stack pointer was configured, caches disabled and that's about it.
+ The problem with this part is the memory management isn't running at all. To
+ make things even worse, at this point, the RAM is still likely uninitialized
+ and therefore unavailable.
+
+ 2) Second stage
+ ---------------
+
+ At this stage, the bootloader has initialized RAM and is running from it's
+ final location. Dynamic memory allocations are working at this point. Most of
+ the driver initialization is executed here.
+
+III) The drivers
+----------------
+
+ 1) The structure of a driver
+ ----------------------------
+
+ The driver will contain a structure located in a separate section, which
+ will allow linker to create a list of compiled-in drivers at compile time.
+ Let's call this list "driver_list".
+
+ struct driver __attribute__((section(driver_list))) {
+ /* The name of the driver */
+ char name[STATIC_CONFIG_DRIVER_NAME_LENGTH];
+
+ /*
+ * This function should connect this driver with cores it depends on and
+ * with other drivers, likely bus drivers
+ */
+ int (*bind)(struct instance *i);
+
+ /* This function actually initializes the hardware. */
+ int (*probe)(struct instance *i);
+
+ /*
+ * The function of the driver called when U-Boot finished relocation.
+ * This is particularly important to eg. move pointers to DMA buffers
+ * and such from the location before relocation to their final location.
+ */
+ int (*reloc)(struct instance *i);
+
+ /*
+ * This is called when the driver is shuting down, to deinitialize the
+ * hardware.
+ */
+ int (*remove)(struct instance *i);
+
+ /* This is called to remove the driver from the driver tree */
+ int (*unbind)(struct instance *i);
+
+ /* This is a list of cores this driver depends on */
+ struct driver *cores[];
+ };
+
+ The cores[] array in here is very important. It allows u-boot to figure out,
+ in compile-time, which possible cores can be activated at runtime. Therefore
+ if there are cores that won't be ever activated, GCC LTO might remove them
+ from the final binary. Actually, this information might be used to drive build
+ of the cores.
+
+ FIXME: Should *cores[] be really struct driver, pointing to drivers that
+ represent the cores? Shouldn't it be core instance pointer?
+
+ 2) Instantiation of a driver
+ ----------------------------
+
+ The driver is instantiated by calling:
+
+ driver_bind(struct instance *bus, const struct driver_info *di)
+
+ The "struct instance *bus" is a pointer to a bus with which this driver should
+ be registered with. The "root" bus pointer is supplied to the board init
+ functions.
+
+ FIXME: We need some functions that will return list of busses of certain type
+ registered with the system so the user can find proper instance even if
+ he has no bus pointer (this will come handy if the user isn't
+ registering the driver from board init function, but somewhere else).
+
+ The "const struct driver_info *di" pointer points to a structure defining the
+ driver to be registered. The structure is defined as follows:
+
+ struct driver_info {
+ char name[STATIC_CONFIG_DRIVER_NAME_LENGTH];
+ void *platform_data;
+ }
+
+ The instantiation of a driver by calling driver_bind() creates an instance
+ of the driver by allocating "struct driver_instance". Note that only struct
+ instance is passed to the driver. The wrapping struct driver_instance is there
+ for purposes of the driver core:
+
+ struct driver_instance {
+ uint32_t flags;
+ struct instance i;
+ };
+
+ struct instance {
+ /* Pointer to a driver information passed by driver_register() */
+ const struct driver_info *info;
+ /* Pointer to a bus this driver is bound with */
+ struct instance *bus;
+ /* Pointer to this driver's own private data */
+ void *private_data;
+ /* Pointer to the first block of successor nodes (optional) */
+ struct successor_block *succ;
+ }
+
+ The instantiation of a driver does not mean the hardware is initialized. The
+ driver_bind() call only creates the instance of the driver, fills in the "bus"
+ pointer and calls the drivers' .bind() function. The .bind() function of the
+ driver should hook the driver with the remaining cores and/or drivers it
+ depends on.
+
+ It's important to note here, that in case the driver instance has multiple
+ parents, such parent can be connected with this instance by calling:
+
+ driver_link(struct instance *parent, struct instance *dev);
+
+ This will connect the other parent driver with the newly instantiated driver.
+ Note that this must be called after driver_bind() and before driver_acticate()
+ (driver_activate() will be explained below). To allow struct instance to have
+ multiple parent pointer, the struct instance *bus will utilize it's last bit
+ to indicate if this is a pointer to struct instance or to an array if
+ instances, struct successor block. The approach is similar as the approach to
+ *succ in struct instance, described in the following paragraph.
+
+ The last pointer of the struct instance, the pointer to successor nodes, is
+ used only in case of a bus driver. Otherwise the pointer contains NULL value.
+ The last bit of this field indicates if this is a bus having a single child
+ node (so the last bit is 0) or if this bus has multiple child nodes (the last
+ bit is 1). In the former case, the driver core should clear the last bit and
+ this pointer points directly to the child node. In the later case of a bus
+ driver, the pointer points to an instance of structure:
+
+ struct successor_block {
+ /* Array of pointers to instances of devices attached to this bus */
+ struct instance *dev[BLOCKING_FACTOR];
+ /* Pointer to next block of successors */
+ struct successor_block *next;
+ }
+
+ Some of the *dev[] array members might be NULL in case there are no more
+ devices attached. The *next is NULL in case the list of attached devices
+ doesn't continue anymore. The BLOCKING_FACTOR is used to allocate multiple
+ slots for successor devices at once to avoid fragmentation of memory.
+
+ 3) The bind() function of a driver
+ ----------------------------------
+
+ The bind function of a driver connects the driver with various cores the
+ driver provides functions for. The driver model related part will look like
+ the following example for a bus driver:
+
+ int driver_bind(struct instance *in)
+ {
+ ...
+ core_bind(&core_i2c_static_instance, in, i2c_bus_funcs);
+ ...
+ }
+
+ FIXME: What if we need to run-time determine, depending on some hardware
+ register, what kind of i2c_bus_funcs to pass?
+
+ This makes the i2c core aware of a new bus. The i2c_bus_funcs is a constant
+ structure of functions any i2c bus driver must provide to work. This will
+ allow the i2c command operate with the bus. The core_i2c_static_instance is
+ the pointer to the instance of a core this driver provides function to.
+
+ FIXME: Maybe replace "core-i2c" with CORE_I2C global pointer to an instance of
+ the core?
+
+ 4) The instantiation of a core driver
+ -------------------------------------
+
+ The core driver is special in the way that it's single-instance driver. It is
+ always present in the system, though it might not be activated. The fact that
+ it's single instance allows it to be instantiated at compile time.
+
+ Therefore, all possible structures of this driver can be in read-only memory,
+ especially struct driver and struct driver_instance. But the successor list,
+ which needs special treatment.
+
+ To solve the problem with a successor list and the core driver flags, a new
+ entry in struct gd (global data) will be introduced. This entry will point to
+ runtime allocated array of struct driver_instance. It will be possible to
+ allocate the exact amount of struct driver_instance necessary, as the number
+ of cores that might be activated will be known at compile time. The cores will
+ then behave like any usual driver.
+
+ Pointers to the struct instance of cores can be computed at compile time,
+ therefore allowing the resulting u-boot binary to save some overhead.
+
+ 5) The probe() function of a driver
+ -----------------------------------
+
+ The probe function of a driver allocates necessary resources and does required
+ initialization of the hardware itself. This is usually called only when the
+ driver is needed, as a part of the defered probe mechanism.
+
+ The driver core should implement a function called
+
+ int driver_activate(struct instance *in);
+
+ which should call the .probe() function of the driver and then configure the
+ state of the driver instance to "ACTIVATED". This state of a driver instance
+ should be stored in a wrap-around structure for the structure instance, the
+ struct driver_instance.
+
+ 6) The command side interface to a driver
+ -----------------------------------------
+
+ The U-Boot command shall communicate only with the specific driver core. The
+ driver core in turn exports necessary API towards the command.
+
+ 7) Demonstration imaginary board
+ --------------------------------
+
+ Consider the following computer:
+
+ *
+ |
+ +-- System power management logic
+ |
+ +-- CPU clock controlling logc
+ |
+ +-- NAND controller
+ | |
+ | +-- NAND flash chip
+ |
+ +-- 128MB of DDR DRAM
+ |
+ +-- I2C bus #0
+ | |
+ | +-- RTC
+ | |
+ | +-- EEPROM #0
+ | |
+ | +-- EEPROM #1
+ |
+ +-- USB host-only IP core
+ | |
+ | +-- USB storage device
+ |
+ +-- USB OTG-capable IP core
+ | |
+ | +-- connection to the host PC
+ |
+ +-- GPIO
+ | |
+ | +-- User LED #0
+ | |
+ | +-- User LED #1
+ |
+ +-- UART0
+ |
+ +-- UART1
+ |
+ +-- Ethernet controller #0
+ |
+ +-- Ethernet controller #1
+ |
+ +-- Audio codec
+ |
+ +-- PCI bridge
+ | |
+ | +-- Ethernet controller #2
+ | |
+ | +-- SPI host card
+ | | |
+ | | +-- Audio amplifier (must be operational before codec)
+ | |
+ | +-- GPIO host card
+ | |
+ | +-- User LED #2
+ |
+ +-- LCD controller
+ |
+ +-- PWM controller (must be enabled after LCD controller)
+ |
+ +-- SPI host controller
+ | |
+ | +-- SD/MMC connected via SPI
+ | |
+ | +-- SPI flash
+ |
+ +-- CPLD/FPGA with stored configuration of the board
--- /dev/null
+The U-Boot Driver Model Project
+===============================
+I/O system analysis
+===================
+Marek Vasut <marek.vasut@gmail.com>
+2012-02-21
+
+I) Overview
+-----------
+
+The current FPGA implementation is handled by command "fpga". This command in
+turn calls the following functions:
+
+fpga_info()
+fpga_load()
+fpga_dump()
+
+These functions are implemented by what appears to be FPGA multiplexer, located
+in drivers/fpga/fpga.c . This code determines which device to operate with
+depending on the device ID.
+
+The fpga_info() function is multiplexer of the functions providing information
+about the particular FPGA device. These functions are implemented in the drivers
+for the particular FPGA device:
+
+xilinx_info()
+altera_info()
+lattice_info()
+
+Similar approach is used for fpga_load(), which multiplexes "xilinx_load()",
+"altera_load()" and "lattice_load()" and is used to load firmware into the FPGA
+device.
+
+The fpga_dump() function, which prints the contents of the FPGA device, is no
+different either, by multiplexing "xilinx_dump()", "altera_dump()" and
+"lattice_dump()" functions.
+
+Finally, each new FPGA device is registered by calling "fpga_add()" function.
+This function takes two arguments, the second one being particularly important,
+because it's basically what will become platform_data. Currently, it's data that
+are passed to the driver from the board/platform code.
+
+II) Approach
+------------
+
+The path to conversion of the FPGA subsystem will be very straightforward, since
+the FPGA subsystem is already quite dynamic. Multiple things will need to be
+modified though.
+
+First is the registration of the new FPGA device towards the FPGA core. This
+will be achieved by calling:
+
+ fpga_device_register(struct instance *i, const struct fpga_ops *ops);
+
+The particularly interesting part is the struct fpga_ops, which contains
+operations supported by the FPGA device. These are basically the already used
+calls in the current implementation:
+
+struct fpga_ops {
+ int info(struct instance *i);
+ int load(struct instance *i, const char *buf, size_t size);
+ int dump(struct instance *i, const char *buf, size_t size);
+}
+
+The other piece that'll have to be modified is how the devices are tracked.
+It'll be necessary to introduce a linked list of devices within the FPGA core
+instead of tracking them by ID number.
+
+Next, the "Xilinx_desc", "Lattice_desc" and "Altera_desc" structures will have
+to be moved to driver's private_data. Finally, structures passed from the board
+and/or platform files, like "Xilinx_Virtex2_Slave_SelectMap_fns" would be passed
+via platform_data to the driver.
+
+III) Analysis of in-tree drivers
+--------------------------------
+
+ 1) Altera driver
+ ----------------
+ The driver is realized using the following files:
+
+ drivers/fpga/altera.c
+ drivers/fpga/ACEX1K.c
+ drivers/fpga/cyclon2.c
+ drivers/fpga/stratixII.c
+
+ All of the sub-drivers implement basically the same info-load-dump interface
+ and there's no expected problem during the conversion. The driver itself will
+ be realised by altera.c and all the sub-drivers will be linked in. The
+ distinction will be done by passing different platform data.
+
+ 2) Lattice driver
+ -----------------
+ The driver is realized using the following files:
+
+ drivers/fpga/lattice.c
+ drivers/fpga/ivm_core.c
+
+ This driver also implements the standard interface, but to realise the
+ operations with the FPGA device, uses functions from "ivm_core.c" file. This
+ file implements the main communications logic and has to be linked in together
+ with "lattice.c". No problem converting is expected here.
+
+ 3) Xilinx driver
+ ----------------
+ The driver is realized using the following files:
+
+ drivers/fpga/xilinx.c
+ drivers/fpga/spartan2.c
+ drivers/fpga/spartan3.c
+ drivers/fpga/virtex2.c
+
+ This set of sub-drivers is special by defining a big set of macros in
+ "include/spartan3.h" and similar files. These macros would need to be either
+ rewritten or replaced. Otherwise, there are no problems expected during the
+ conversion process.
--- /dev/null
+The U-Boot Driver Model Project
+===============================
+GPIO analysis
+=============
+Viktor Krivak <viktor.krivak@gmail.com>
+2012-02-24
+
+I) Overview
+-----------
+
+ At this moment U-Boot provides standard API that consists of 7 functions.
+
+ int gpio_request(unsigned gpio, const char *label)
+ int gpio_free(unsigned gpio)
+ int gpio_direction_input(unsigned gpio)
+ int gpio_direction_output(unsigned gpio, int value)
+ int gpio_get_value(unsigned gpio)
+ void gpio_set_value(unsigned gpio, int value)
+
+ Methods "gpio_request()" and "gpio_free()" are used for claiming and releasing
+ GPIOs. First one should check if the desired pin exists and if the pin wasn't
+ requested already elsewhere. The method also has a label argument that can be
+ used for debug purposes. The label argument should be copied into the internal
+ memory, but only if the DEBUG macro is set. The "gpio_free()" is the exact
+ opposite. It releases the particular pin. Other methods are used for setting
+ input or output direction and obtaining or setting values of the pins.
+
+II) Approach
+------------
+
+ 1) Request and free GPIO
+ ------------------------
+
+ The "gpio_request()" implementation is basically the same for all boards.
+ The function checks if the particular GPIO is correct and checks if the
+ GPIO pin is still free. If the conditions are met, the method marks the
+ GPIO claimed in it's internal structure. If macro DEBUG is defined, the
+ function also copies the label argument to the structure. If the pin is
+ already locked, the function returns -1 and if DEBUG is defined, certain
+ debug output is generated, including the contents of the label argument.
+ The "gpio_free()" function releases the lock and eventually deallocates
+ data used by the copied label argument.
+
+ 2) Internal data
+ ----------------
+
+ Internal data are driver specific. They have to contain some mechanism to
+ realise the locking though. This can be done for example using a bit field.
+
+ 3) Operations provided by the driver
+ ------------------------------------
+
+ The driver operations basically meet API that is already defined and used.
+ Except for "gpio_request()" and "gpio_free()", all methods can be converted in
+ a simple manner. The driver provides the following structure:
+
+ struct gpio_driver_ops {
+ int (*gpio_request)(struct instance *i, unsigned gpio,
+ const char *label);
+ int (*gpio_free)(struct instance *i, unsigned gpio);
+ int (*gpio_direction_input)(struct instance *i, unsigned gpio);
+ int (*gpio_direction_output)(struct instance *i, unsigned gpio,
+ int value);
+ int (*gpio_get_value)(struct instance *i, unsigned gpio);
+ void (*gpio_set_value)(struct instance *i, unsigned gpio, int value);
+ }
+
+III) Analysis of in-tree drivers
+--------------------------------
+
+ 1) altera_pio.c
+ ---------------
+ Meets standard API. Implements gpio_request() properly. Simple conversion
+ possible.
+
+ 2) at91_gpio.c
+ --------------
+ Don't meet standard API. Need some other methods to implement.
+
+ 3) da8xx_gpio.c
+ ---------------
+ Meets standard API. Implements gpio_request() properly. Simple conversion
+ possible.
+
+ 4) kw_gpio.c
+ ------------
+ Doesn't meet standard API. Needs some other methods to implement and move some
+ methods to another file.
+
+ 5) mpc83xx_gpio.c
+ -----------------
+ Meets standard API. Doesn't implement gpio_request() properly (only checks
+ if the pin is valid). Simple conversion possible.
+
+ 6) mvgpio.c
+ -----------
+ Meets standard API. Doesn't implement gpio_request() properly (only checks
+ if the pin is valid). Simple conversion possible.
+
+ 7) mvgpio.h
+ -----------
+ Wrong placement. Will be moved to another location.
+
+ 8) mvmfp.c
+ ----------
+ Wrong placement. Will be moved to another location.
--- /dev/null
+The U-Boot Driver Model Project
+===============================
+Hwmon device subsystem analysis
+===============================
+
+Tomas Hlavacek <tmshlvck@gmail.com>
+2012-03-02
+
+I) Overview
+-----------
+
+U-Boot currently implements one API for HW monitoring devices. The
+interface is defined in include/dtt.h and comprises of functions:
+
+ void dtt_init(void);
+ int dtt_init_one(int);
+ int dtt_read(int sensor, int reg);
+ int dtt_write(int sensor, int reg, int val);
+ int dtt_get_temp(int sensor);
+
+The functions are implemented by a proper device driver in drivers/hwmon
+directory and the driver to be compiled in is selected in a Makefile.
+Drivers are mutually exclusive.
+
+Drivers depends on I2O code and naturally on board specific data. There are
+few ad-hoc constants put in dtt.h file and driver headers and code. This
+has to be consolidated into board specific data or driver headers if those
+constants makes sense globally.
+
+
+II) Approach
+------------
+
+ 1) New API
+ ----------
+ In the UDM each hwmon driver would register itself by a function
+
+ int hwmon_device_register(struct instance *i,
+ struct hwmon_device_ops *o);
+
+ The structure being defined as follows:
+
+ struct hwmon_device_ops {
+ int (*read)(struct instance *i, int sensor, int reg);
+ int (*write)(struct instance *i, int sensor, int reg,
+ int val);
+ int (*get_temp)(struct instance *i, int sensor);
+ };
+
+
+ 2) Conversion thougths
+ ----------------------
+ U-Boot hwmon drivers exports virtually the same functions (with exceptions)
+ and we are considering low number of drivers and code anyway. The interface
+ is already similar and unified by the interface defined in dtt.h.
+ Current initialization functions dtt_init() and dtt_init_one() will be
+ converted into probe() and hwmon_device_register(), so the funcionality will
+ be kept in more proper places. Besides implementing core registration and
+ initialization we need to do code cleanup, especially separate
+ driver-specific and HW specific constants.
+
+ 3) Special consideration due to early initialization
+ ----------------------------------------------------
+ The dtt_init() function call is used during early initialization in
+ board/gdsys/405ex/io64.c for starting up fans. The dtt code is perfectly
+ usable in the early stage because it uses only local variables and no heap
+ memory is required at this level. However the underlying code of I2C has to
+ keep the same properties with regard to possibility of running in early
+ initialization stage.
+
+III) Analysis of in-tree drivers
+--------------------------------
+
+ 1) drivers/hwmon/lm81.c
+ -----------------------
+ The driver is standard dtt. Simple conversion is possible.
+
+
+ 2) drivers/hwmon/ds1722.c
+ -------------------------
+ The driver is not standard dtt, but interface is similar to dtt.
+ The interface has to be changed in order to comply to above mentioned
+ specification.
+
+
+ 3) drivers/hwmon/ds1775.c
+ -------------------------
+ The driver is standard dtt. Simple conversion is possible.
+
+
+ 4) drivers/hwmon/lm73.c
+ -----------------------
+ The driver is standard dtt. Simple conversion is possible.
+
+
+ 5) drivers/hwmon/lm63.c
+ -----------------------
+ The driver is standard dtt. Simple conversion is possible.
+
+
+ 6) drivers/hwmon/adt7460.c
+ --------------------------
+ The driver is standard dtt. Simple conversion is possible.
+
+
+ 7) drivers/hwmon/lm75.c
+ -----------------------
+ The driver is standard dtt. Simple conversion is possible.
+
+
+ 8) drivers/hwmon/ds1621.c
+ -------------------------
+ The driver is standard dtt. Simple conversion is possible.
+
+
+ 9) drivers/hwmon/adm1021.c
+ --------------------------
+ The driver is standard dtt. Simple conversion is possible.
--- /dev/null
+The U-Boot Driver Model Project
+===============================
+Keyboard input analysis
+=======================
+Marek Vasut <marek.vasut@gmail.com>
+2012-02-20
+
+I) Overview
+-----------
+
+The keyboard drivers are most often registered with STDIO subsystem. There are
+components of the keyboard drivers though, which operate in severe ad-hoc
+manner, often being related to interrupt-driven keypress reception. This
+components will require the most sanitization of all parts of keyboard input
+subsystem.
+
+Otherwise, the keyboard is no different from other standard input but with the
+necessity to decode scancodes. These are decoded using tables provided by
+keyboard drivers. These tables are often driver specific.
+
+II) Approach
+------------
+
+The most problematic part is the interrupt driven keypress reception. For this,
+the buffers that are currently shared throughout the whole U-Boot would need to
+be converted into driver's private data.
+
+III) Analysis of in-tree drivers
+--------------------------------
+
+ 1) board/mpl/common/kbd.c
+ -------------------------
+ This driver is a classic STDIO driver, no problem with conversion is expected.
+ Only necessary change will be to move this driver to a proper location.
+
+ 2) board/rbc823/kbd.c
+ ---------------------
+ This driver is a classic STDIO driver, no problem with conversion is expected.
+ Only necessary change will be to move this driver to a proper location.
+
+ 3) drivers/input/keyboard.c
+ ---------------------------
+ This driver is special in many ways. Firstly because this is a universal stub
+ driver for converting scancodes from i8042 and the likes. Secondly because the
+ buffer is filled by various other ad-hoc implementations of keyboard input by
+ using this buffer as an extern. This will need to be fixed by allowing drivers
+ to pass certain routines to this driver via platform data.
--- /dev/null
+The U-Boot Driver Model Project
+===============================
+MMC system analysis
+===================
+Marek Vasut <marek.vasut@gmail.com>
+2012-02-25
+
+I) Overview
+-----------
+
+The MMC subsystem is already quite dynamic in it's nature. It's only necessary
+to flip the subsystem to properly defined API.
+
+The probing process of MMC drivers start by calling "mmc_initialize()",
+implemented by MMC framework, from the architecture initialization file. The
+"mmc_initialize()" function in turn calls "board_mmc_init()" function and if
+this doesn't succeed, "cpu_mmc_init()" function is called. It is important to
+note that both of the "*_mmc_init()" functions have weak aliases to functions
+which automatically fail.
+
+Both of the "*_mmc_init()" functions though serve only one purpose. To call
+driver specific probe function, which in turn actually registers the driver with
+MMC subsystem. Each of the driver specific probe functions is currently done in
+very ad-hoc manner.
+
+The registration with the MMC subsystem is done by calling "mmc_register()",
+whose argument is a runtime configured structure of information about the MMC
+driver. Currently, the information structure is intermixed with driver's internal
+data. The description of the structure follows:
+
+struct mmc {
+ /*
+ * API: Allows this driver to be a member of the linked list of all MMC drivers
+ * registered with MMC subsystem
+ */
+ struct list_head link;
+
+ /* DRIVER: Name of the registered driver */
+ char name[32];
+
+ /* DRIVER: Driver's private data */
+ void *priv;
+
+ /* DRIVER: Voltages the host bus can provide */
+ uint voltages;
+
+ /* API: Version of the card */
+ uint version;
+
+ /* API: Test if the driver was already initialized */
+ uint has_init;
+
+ /* DRIVER: Minimum frequency the host bus can provide */
+ uint f_min;
+
+ /* DRIVER: Maximum frequency the host bus can provide */
+ uint f_max;
+
+ /* API: Is the card SDHC */
+ int high_capacity;
+
+ /* API: Actual width of the bus used by the current card */
+ uint bus_width;
+
+ /*
+ * DRIVER: Clock frequency to be configured on the host bus, this is read-only
+ * for the driver.
+ */
+ uint clock;
+
+ /* API: Capabilities of the card */
+ uint card_caps;
+
+ /* DRIVER: MMC bus capabilities */
+ uint host_caps;
+
+ /* API: Configuration and ID data retrieved from the card */
+ uint ocr;
+ uint scr[2];
+ uint csd[4];
+ uint cid[4];
+ ushort rca;
+
+ /* API: Partition configuration */
+ char part_config;
+
+ /* API: Number of partitions */
+ char part_num;
+
+ /* API: Transmission speed */
+ uint tran_speed;
+
+ /* API: Read block length */
+ uint read_bl_len;
+
+ /* API: Write block length */
+ uint write_bl_len;
+
+ /* API: Erase group size */
+ uint erase_grp_size;
+
+ /* API: Capacity of the card */
+ u64 capacity;
+
+ /* API: Descriptor of this block device */
+ block_dev_desc_t block_dev;
+
+ /* DRIVER: Function used to submit command to the card */
+ int (*send_cmd)(struct mmc *mmc,
+ struct mmc_cmd *cmd, struct mmc_data *data);
+
+ /* DRIVER: Function used to configure the host */
+ void (*set_ios)(struct mmc *mmc);
+
+ /* DRIVER: Function used to initialize the host */
+ int (*init)(struct mmc *mmc);
+
+ /* DRIVER: Function used to report the status of Card Detect pin */
+ int (*getcd)(struct mmc *mmc);
+
+ /*
+ * DRIVER: Maximum amount of blocks sent during multiblock xfer,
+ * set to 0 to autodetect.
+ */
+ uint b_max;
+};
+
+The API above is the new API used by most of the drivers. There're still drivers
+in the tree that use old, legacy API though.
+
+2) Approach
+-----------
+
+To convert the MMC subsystem to a proper driver model, the "struct mmc"
+structure will have to be properly split in the first place. The result will
+consist of multiple parts, first will be the structure defining operations
+provided by the MMC driver:
+
+struct mmc_driver_ops {
+ /* Function used to submit command to the card */
+ int (*send_cmd)(struct mmc *mmc,
+ struct mmc_cmd *cmd, struct mmc_data *data);
+ /* DRIVER: Function used to configure the host */
+ void (*set_ios)(struct mmc *mmc);
+ /* Function used to initialize the host */
+ int (*init)(struct mmc *mmc);
+ /* Function used to report the status of Card Detect pin */
+ int (*getcd)(struct mmc *mmc);
+}
+
+The second part will define the parameters of the MMC driver:
+
+struct mmc_driver_params {
+ /* Voltages the host bus can provide */
+ uint32_t voltages;
+ /* Minimum frequency the host bus can provide */
+ uint32_t f_min;
+ /* Maximum frequency the host bus can provide */
+ uint32_t f_max;
+ /* MMC bus capabilities */
+ uint32_t host_caps;
+ /*
+ * Maximum amount of blocks sent during multiblock xfer,
+ * set to 0 to autodetect.
+ */
+ uint32_t b_max;
+}
+
+And finally, the internal per-card data of the MMC subsystem core:
+
+struct mmc_card_props {
+ /* Version of the card */
+ uint32_t version;
+ /* Test if the driver was already initializes */
+ bool has_init;
+ /* Is the card SDHC */
+ bool high_capacity;
+ /* Actual width of the bus used by the current card */
+ uint8_t bus_width;
+ /* Capabilities of the card */
+ uint32_t card_caps;
+ /* Configuration and ID data retrieved from the card */
+ uint32_t ocr;
+ uint32_t scr[2];
+ uint32_t csd[4];
+ uint32_t cid[4];
+ uint16_t rca;
+ /* Partition configuration */
+ uint8_t part_config;
+ /* Number of partitions */
+ uint8_t part_num;
+ /* Transmission speed */
+ uint32_t tran_speed;
+ /* Read block length */
+ uint32_t read_bl_len;
+ /* Write block length */
+ uint32_t write_bl_len;
+ /* Erase group size */
+ uint32_t erase_grp_size;
+ /* Capacity of the card */
+ uint64_t capacity;
+ /* Descriptor of this block device */
+ block_dev_desc_t block_dev;
+}
+
+The probe() function will then register the MMC driver by calling:
+
+ mmc_device_register(struct instance *i, struct mmc_driver_ops *o,
+ struct mmc_driver_params *p);
+
+The struct mmc_driver_params will have to be dynamic in some cases, but the
+driver shouldn't modify it's contents elsewhere than in probe() call.
+
+Next, since the MMC drivers will now be consistently registered into the driver
+tree from board file, the functions "board_mmc_init()" and "cpu_mmc_init()" will
+disappear altogether.
+
+As for the legacy drivers, these will either be converted or removed altogether.
+
+III) Analysis of in-tree drivers
+--------------------------------
+
+ 1) arm_pl180_mmci.c
+ -------------------
+ Follows the new API and also has a good encapsulation of the whole driver. The
+ conversion here will be simple.
+
+ 2) atmel_mci.c
+ --------------
+ This driver uses the legacy API and should be removed unless converted. It is
+ probably possbible to replace this driver with gen_atmel_mci.c . No conversion
+ will be done on this driver.
+
+ 3) bfin_sdh.c
+ -------------
+ Follows the new API and also has a good encapsulation of the whole driver. The
+ conversion here will be simple.
+
+ 4) davinci_mmc.c
+ ----------------
+ Follows the new API and also has a good encapsulation of the whole driver. The
+ conversion here will be simple.
+
+ 5) fsl_esdhc.c
+ --------------
+ Follows the new API and also has a good encapsulation of the whole driver. The
+ conversion here will be simple, unless some problem appears due to the FDT
+ component of the driver.
+
+ 6) ftsdc010_esdhc.c
+ -------------------
+ Follows the new API and also has a good encapsulation of the whole driver. The
+ conversion here will be simple.
+
+ 7) gen_atmel_mci.c
+ ------------------
+ Follows the new API and also has a good encapsulation of the whole driver. The
+ conversion here will be simple.
+
+ 8) mmc_spi.c
+ ------------
+ Follows the new API and also has a good encapsulation of the whole driver. The
+ conversion here will be simple.
+
+ 9) mv_sdhci.c
+ -------------
+ This is a component of the SDHCI support, allowing it to run on Marvell
+ Kirkwood chip. It is probable the SDHCI support will have to be modified to
+ allow calling functions from this file based on information passed via
+ platform_data.
+
+ 10) mxcmmc.c
+ ------------
+ Follows the new API and also has a good encapsulation of the whole driver. The
+ conversion here will be simple.
+
+ 11) mxsmmc.c
+ ------------
+ Follows the new API and also has a good encapsulation of the whole driver. The
+ conversion here will be simple.
+
+ 12) omap_hsmmc.c
+ ----------------
+ Follows the new API and also has a good encapsulation of the whole driver. The
+ conversion here will be simple.
+
+ 13) pxa_mmc.c
+ -------------
+ This driver uses the legacy API and is written in a severely ad-hoc manner.
+ This driver will be removed in favor of pxa_mmc_gen.c, which is proved to work
+ better and is already well tested. No conversion will be done on this driver
+ anymore.
+
+ 14) pxa_mmc_gen.c
+ -----------------
+ Follows the new API and also has a good encapsulation of the whole driver. The
+ conversion here will be simple.
+
+ 15) s5p_mmc.c
+ -------------
+ Follows the new API and also has a good encapsulation of the whole driver. The
+ conversion here will be simple.
+
+ 16) sdhci.c
+ -----------
+ Follows the new API and also has a good encapsulation of the whole driver. The
+ conversion here will be simple, though it'd be necessary to modify this driver
+ to also support the Kirkwood series and probably also Tegra series of CPUs.
+ See the respective parts of this section for details.
+
+ 17) sh_mmcif.c
+ --------------
+ Follows the new API and also has a good encapsulation of the whole driver. The
+ conversion here will be simple.
+
+ 18) tegra2_mmc.c
+ ----------------
+ Follows the new API and also has a good encapsulation of the whole driver. The
+ conversion here will be simple.
--- /dev/null
+The U-Boot Driver Model Project
+===============================
+Net system analysis
+===================
+Marek Vasut <marek.vasut@gmail.com>
+2012-03-03
+
+I) Overview
+-----------
+
+The networking subsystem already supports multiple devices. Therefore the
+conversion shall not be very hard.
+
+The network subsystem is operated from net/eth.c, which tracks all registered
+ethernet interfaces and calls their particular functions registered via
+eth_register().
+
+The eth_register() is called from the network driver initialization function,
+which in turn is called most often either from "board_net_init()" or
+"cpu_net_init()". This function has one important argument, which is the
+"struct eth_device", defined at include/net.h:
+
+struct eth_device {
+ /* DRIVER: Name of the device */
+ char name[NAMESIZE];
+ /* DRIVER: MAC address */
+ unsigned char enetaddr[6];
+ /* DRIVER: Register base address */
+ int iobase;
+ /* CORE: state of the device */
+ int state;
+
+ /* DRIVER: Device initialization function */
+ int (*init) (struct eth_device*, bd_t*);
+ /* DRIVER: Function for sending packets */
+ int (*send) (struct eth_device*, volatile void* packet, int length);
+ /* DRIVER: Function for receiving packets */
+ int (*recv) (struct eth_device*);
+ /* DRIVER: Function to cease operation of the device */
+ void (*halt) (struct eth_device*);
+ /* DRIVER: Function to send multicast packet (OPTIONAL) */
+ int (*mcast) (struct eth_device*, u32 ip, u8 set);
+ /* DRIVER: Function to change ethernet MAC address */
+ int (*write_hwaddr) (struct eth_device*);
+ /* CORE: Next device in the linked list of devices managed by net core */
+ struct eth_device *next;
+ /* CORE: Device index */
+ int index;
+ /* DRIVER: Driver's private data */
+ void *priv;
+};
+
+This structure defines the particular driver, though also contains elements that
+should not be exposed to the driver, like core state.
+
+Small, but important part of the networking subsystem is the PHY management
+layer, whose drivers are contained in drivers/net/phy. These drivers register in
+a very similar manner to network drivers, by calling "phy_register()" with the
+argument of "struct phy_driver":
+
+struct phy_driver {
+ /* DRIVER: Name of the PHY driver */
+ char *name;
+ /* DRIVER: UID of the PHY driver */
+ unsigned int uid;
+ /* DRIVER: Mask for UID of the PHY driver */
+ unsigned int mask;
+ /* DRIVER: MMDS of the PHY driver */
+ unsigned int mmds;
+ /* DRIVER: Features the PHY driver supports */
+ u32 features;
+ /* DRIVER: Initialize the PHY hardware */
+ int (*probe)(struct phy_device *phydev);
+ /* DRIVER: Reconfigure the PHY hardware */
+ int (*config)(struct phy_device *phydev);
+ /* DRIVER: Turn on the PHY hardware, allow it to send/receive */
+ int (*startup)(struct phy_device *phydev);
+ /* DRIVER: Turn off the PHY hardware */
+ int (*shutdown)(struct phy_device *phydev);
+ /* CORE: Allows this driver to be part of list of drivers */
+ struct list_head list;
+};
+
+II) Approach
+------------
+
+To convert the elements of network subsystem to proper driver model method, the
+"struct eth_device" will have to be split into multiple components. The first
+will be a structure defining the driver operations:
+
+struct eth_driver_ops {
+ int (*init)(struct instance*, bd_t*);
+ int (*send)(struct instance*, void *packet, int length);
+ int (*recv)(struct instance*);
+ void (*halt)(struct instance*);
+ int (*mcast)(struct instance*, u32 ip, u8 set);
+ int (*write_hwaddr)(struct instance*);
+};
+
+Next, there'll be platform data which will be per-driver and will replace the
+"priv" part of "struct eth_device". Last part will be the per-device core state.
+
+With regards to the PHY part of the API, the "struct phy_driver" is almost ready
+to be used with the new driver model approach. The only change will be the
+replacement of per-driver initialization functions and removal of
+"phy_register()" function in favor or driver model approach.
+
+III) Analysis of in-tree drivers
+--------------------------------
+
+ 1) drivers/net/4xx_enet.c
+ -------------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 2) drivers/net/altera_tse.c
+ ---------------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 3) drivers/net/armada100_fec.c
+ ------------------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 4) drivers/net/at91_emac.c
+ --------------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 5) drivers/net/ax88180.c
+ ------------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 6) drivers/net/ax88796.c
+ ------------------------
+
+ This file contains a components of the NE2000 driver, implementing only
+ different parts on the NE2000 clone AX88796. This being no standalone driver,
+ no conversion will be done here.
+
+ 7) drivers/net/bfin_mac.c
+ -------------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 8) drivers/net/calxedaxgmac.c
+ -----------------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 9) drivers/net/cs8900.c
+ -----------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 10) drivers/net/davinci_emac.c
+ ------------------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 11) drivers/net/dc2114x.c
+ -------------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 12) drivers/net/designware.c
+ ----------------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 13) drivers/net/dm9000x.c
+ -------------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 14) drivers/net/dnet.c
+ ----------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 15) drivers/net/e1000.c
+ -----------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 16) drivers/net/e1000_spi.c
+ ---------------------------
+
+ Driver for the SPI bus integrated on the Intel E1000. This is not part of the
+ network stack.
+
+ 17) drivers/net/eepro100.c
+ --------------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 18) drivers/net/enc28j60.c
+ --------------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 19) drivers/net/ep93xx_eth.c
+ ----------------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 20) drivers/net/ethoc.c
+ -----------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 21) drivers/net/fec_mxc.c
+ -------------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 22) drivers/net/fsl_mcdmafec.c
+ ------------------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 23) drivers/net/fsl_mdio.c
+ --------------------------
+
+ This file contains driver for FSL MDIO interface, which is not part of the
+ networking stack.
+
+ 24) drivers/net/ftgmac100.c
+ ---------------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 25) drivers/net/ftmac100.c
+ --------------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 26) drivers/net/greth.c
+ -----------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 27) drivers/net/inca-ip_sw.c
+ ----------------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 28) drivers/net/ks8695eth.c
+ ---------------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 29) drivers/net/lan91c96.c
+ --------------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 30) drivers/net/macb.c
+ ----------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 31) drivers/net/mcffec.c
+ ------------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 32) drivers/net/mcfmii.c
+ ------------------------
+
+ This file contains MII interface driver for MCF FEC.
+
+ 33) drivers/net/mpc512x_fec.c
+ -----------------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 34) drivers/net/mpc5xxx_fec.c
+ -----------------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 35) drivers/net/mvgbe.c
+ -----------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 36) drivers/net/natsemi.c
+ -------------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 37) drivers/net/ne2000_base.c
+ -----------------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process. This driver contains the core
+ implementation of NE2000, which needs a few external functions, implemented by
+ AX88796, NE2000 etc.
+
+ 38) drivers/net/ne2000.c
+ ------------------------
+
+ This file implements external functions necessary for native NE2000 compatible
+ networking card to work.
+
+ 39) drivers/net/netarm_eth.c
+ ----------------------------
+
+ This driver uses the old, legacy, network API and will either have to be
+ converted or removed.
+
+ 40) drivers/net/netconsole.c
+ ----------------------------
+
+ This is actually an STDIO driver.
+
+ 41) drivers/net/ns8382x.c
+ -------------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 42) drivers/net/pcnet.c
+ -----------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 43) drivers/net/plb2800_eth.c
+ -----------------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 44) drivers/net/rtl8139.c
+ -------------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 45) drivers/net/rtl8169.c
+ -------------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 46) drivers/net/sh_eth.c
+ ------------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 47) drivers/net/smc91111.c
+ --------------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 48) drivers/net/smc911x.c
+ -------------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 49) drivers/net/tsec.c
+ ----------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 50) drivers/net/tsi108_eth.c
+ ----------------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 51) drivers/net/uli526x.c
+ -------------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 52) drivers/net/vsc7385.c
+ -------------------------
+
+ This is a driver that only uploads firmware to a switch. This is not subject
+ of conversion.
+
+ 53) drivers/net/xilinx_axi_emac.c
+ ---------------------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
+
+ 54) drivers/net/xilinx_emaclite.c
+ ---------------------------------
+
+ This driver uses the standard new networking API, therefore there should be no
+ obstacles throughout the conversion process.
--- /dev/null
+The U-Boot Driver Model Project
+===============================
+PCI subsystem analysis
+======================
+
+Pavel Herrmann <morpheus.ibis@gmail.com>
+2012-03-17
+
+I) Overview
+-----------
+
+ U-Boot already supports multiple PCI busses, stored in a linked-list of
+ pci_controller structures. This structure contains generic driver data, bus
+ interface operations and private data for the driver.
+
+ Bus interface operations for PCI are (names are self-explanatory):
+
+ read_byte()
+ read_word()
+ read_dword()
+ write_byte()
+ write_word()
+ write_dword()
+
+ Each driver has to implement dword operations, and either implement word and
+ byte operations, or use shared $operation_config_$type_via_dword (eg.
+ read_config_byte_via_dword and similar) function. These functions are used
+ for config space I/O (read_config_dword and similar functions of the PCI
+ subsystem), which is used to configure the connected devices for standard MMIO
+ operations. All data transfers by respective device drivers are then done by
+ MMIO
+
+ Each driver also defines a separate init function, which has unique symbol
+ name, and thus more drivers can be compiled in without colliding. This init
+ function is typically called from pci_init_board(), different for each
+ particular board.
+
+ Some boards also define a function called fixup_irq, which gets called after
+ scanning the PCI bus for devices, and should dismiss any interrupts.
+
+ Several drivers are also located in arch/ and should be moved to drivers/pci.
+
+II) Approach
+------------
+
+ The pci_controller structure needs to be broken down to fit the new driver
+ model. Due to a large number of members, this will be done through three
+ distinct accessors, one for memory regions, one for config table and one for
+ everything else. That will make the pci_ops structure look like this:
+
+ struct pci_ops {
+ int (*read_byte)(struct instance *bus, pci_dev_t *dev, int addr,
+ u8 *buf);
+ int (*read_word)(struct instance *bus, pci_dev_t *dev, int addr,
+ u16 *buf);
+ int (*read_dword)(struct instance *bus, pci_dev_t *dev, int addr,
+ u32 *buf);
+ int (*write_byte)(struct instance *bus, pci_dev_t *dev, int addr,
+ u8 val);
+ int (*write_byte)(struct instance *bus, pci_dev_t *dev, int addr,
+ u8 val);
+ int (*write_dword)(struct instance *bus, pci_dev_t *dev, int addr,
+ u32 val);
+ void (*fixup_irq)(struct instance *bus, pci_dev_t *dev);
+ struct pci_region* (*get_region)(struct instance *, uint num);
+ struct pci_config_table* (*get_cfg_table)(struct instance *bus);
+ uint (*get_option)(struct instance * bus, enum pci_option_code op);
+ }
+
+ enum pci_option_code {
+ PCI_OPT_BUS_NUMBER=0,
+ PCI_OPT_REGION_COUNT,
+ PCI_OPT_INDIRECT_TYPE,
+ PCI_OPT_AUTO_MEM,
+ PCI_OPT_AUTO_IO,
+ PCI_OPT_AUTO_PREFETCH,
+ PCI_OPT_AUTO_FB,
+ PCI_OPT_CURRENT_BUS,
+ PCI_OPT_CFG_ADDR,
+ }
+
+ The return value for get_option will be an unsigned integer value for any
+ option code. If the option currently is a pointer to pci_region, it will
+ return an index for get_region function. Special case has to be made for
+ PCI_OPT_CFG_ADDR, which should be interpreted as a pointer, but it is only
+ used for equality in find_hose_by_cfg_addr, and thus can be returned as an
+ uint. Other function using cfg_addr value are read/write functions for
+ specific drivers (especially ops for indirect bridges), and thus have access
+ to private_data of the driver instance.
+
+ The config table accessor will return a pointer to a NULL-terminated array of
+ pci_config_table, which is supplied by the board in platform_data, or NULL if
+ the board didn't specify one. This table is used to override PnP
+ auto-initialization, or to specific initialization functions for non-PNP
+ devices.
+
+ Transparent PCI-PCI bridges will get their own driver, and will forward all
+ operations to operations of their parent bus. This however makes it
+ impossible to use instances to identify devices, as not all devices will be
+ directly visible to the respective bus driver.
+
+ Init functions of controller drivers will be moved to their respective
+ probe() functions, in accordance to the driver model.
+
+ The PCI core will handle all mapping functions currently found in pci.c, as
+ well as proxy functions for read/write operations of the drivers. The PCI
+ core will also handle bus scanning and device configuration.
+
+ The PnP helper functions currently in pci_auto.c will also be a part of PCI
+ core, but they will be exposed only to PCI controller drivers, not to other
+ device drivers.
+
+ The PCI API for device drivers will remain largely unchanged, most drivers
+ will require no changes at all, and all modifications will be limited to
+ changing the pci_controlle into instance*.
+
+III) Analysis of in-tree drivers
+--------------------------------
+
+ A) drivers in drivers/pci/
+ --------------------------
+
+ 1) pci_indirect.c
+ -----------------
+ Shared driver for indirect PCI bridges, several CONFIG macros - will
+ require significant cleanup.
+
+ 2) pci_ixp.c
+ ------------
+ Standard driver, specifies all read/write functions separately.
+
+ 3) pci_sh4.c
+ ------------
+ Shared init function for SH4 drivers, uses dword for read/write ops.
+
+ 4) pci_sh7751.c
+ ---------------
+ Standard driver, uses SH4 shared init.
+
+ 5) pci_sh7780.c
+ ---------------
+ Standard driver, uses SH4 shared init.
+
+ 6) tsi108_pci.c
+ ---------------
+ Standard driver, uses dword for read/write ops.
+
+ 7) fsl_pci_init.c
+ -----------------
+ Driver for PCI and PCI-e, uses indirect functions.
+
+ 8) pci_ftpci100.c
+ -----------------
+ Standard driver, uses indirect functions, has separate scan/setup
+ functions.
+
+ B) driver in arch/
+ ------------------
+
+ 1) x86/lib/pci_type1.c
+ ----------------------
+ Standard driver, specifies all read/write functions separately.
+
+ 2) m68k/cpu/mcf5445x/pci.c
+ --------------------------
+ Standard driver, specifies all read/write functions separately.
+
+ 3) m68k/cpu/mcf547x_8x/pci.c
+ ----------------------------
+ Standard driver, specifies all read/write functions separately.
+
+ 4) powerpc/cpu/mpc824x/pci.c
+ ----------------------------
+ Standard driver, uses indirect functions, does not setup HW.
+
+ 5) powerpc/cpu/mpc8260/pci.c
+ ----------------------------
+ Standard driver, uses indirect functions.
+
+ 6) powerpc/cpu/ppc4xx/4xx_pci.c
+ -------------------------------
+ Standard driver, uses indirect functions.
+
+ 7) powerpc/cpu/ppc4xx/4xx_pcie.c
+ --------------------------------
+ PCI-e driver, specifies all read/write functions separately.
+
+ 8) powerpc/cpu/mpc83xx/pci.c
+ ----------------------------
+ Standard driver, uses indirect functions.
+
+ 9) powerpc/cpu/mpc83xx/pcie.c
+ -----------------------------
+ PCI-e driver, specifies all read/write functions separately.
+
+ 10) powerpc/cpu/mpc5xxx/pci_mpc5200.c
+ -------------------------------------
+ Standard driver, uses dword for read/write ops.
+
+ 11) powerpc/cpu/mpc512x/pci.c
+ -----------------------------
+ Standard driver, uses indirect functions.
+
+ 12) powerpc/cpu/mpc8220/pci.c
+ -----------------------------
+ Standard driver, specifies all read/write functions separately.
+
+ 13) powerpc/cpu/mpc85xx/pci.c
+ -----------------------------
+ Standard driver, uses indirect functions, has two busses.
+
+ C) drivers in board/
+ --------------------
+
+ 1) eltec/elppc/pci.c
+ --------------------
+ Standard driver, uses indirect functions.
+
+ 2) amirix/ap1000/pci.c
+ ----------------------
+ Standard driver, specifies all read/write functions separately.
+
+ 3) prodrive/p3mx/pci.c
+ ----------------------
+ Standard driver, uses dword for read/write ops, has two busses.
+
+ 4) esd/cpci750/pci.c
+ --------------------
+ Standard driver, uses dword for read/write ops, has two busses.
+
+ 5) esd/common/pci.c
+ -------------------
+ Standard driver, uses dword for read/write ops.
+
+ 6) dave/common/pci.c
+ --------------------
+ Standard driver, uses dword for read/write ops.
+
+ 7) ppmc7xx/pci.c
+ ----------------
+ Standard driver, uses indirect functions.
+
+ 8) pcippc2/cpc710_pci.c
+ -----------------------
+ Standard driver, uses indirect functions, has two busses.
+
+ 9) Marvell/db64360/pci.c
+ ------------------------
+ Standard driver, uses dword for read/write ops, has two busses.
+
+ 10) Marvell/db64460/pci.c
+ -------------------------
+ Standard driver, uses dword for read/write ops, has two busses.
+
+ 11) evb64260/pci.c
+ ------------------
+ Standard driver, uses dword for read/write ops, has two busses.
+
+ 12) armltd/integrator/pci.c
+ ---------------------------
+ Standard driver, specifies all read/write functions separately.
+
+ All drivers will be moved to drivers/pci. Several drivers seem
+ similar/identical, especially those located under board, and may be merged
+ into one.
--- /dev/null
+The U-Boot Driver Model Project
+===============================
+PCMCIA analysis
+===============
+Viktor Krivak <viktor.krivak@gmail.com>
+2012-03-17
+
+I) Overview
+-----------
+
+ U-boot implements only 2 methods to interoperate with pcmcia. One to turn
+ device on and other to turn device off. Names of these methods are usually
+ pcmcia_on() and pcmcia_off() without any parameters. Some files in driver
+ directory implements only internal API. These methods aren't used outside
+ driver directory and they are not converted to new driver model.
+
+II) Approach
+-----------
+
+ 1) New API
+ ----------
+
+ Current API is preserved and all internal methods are hiden.
+
+ struct ops {
+ void (*pcmcia_on)(struct instance *i);
+ void (*pcmcia_off)(struct instance *i);
+ }
+
+ 2) Conversion
+ -------------
+
+ In header file pcmcia.h are some other variables which are used for
+ additional configuration. But all have to be moved to platform data or to
+ specific driver implementation.
+
+ 3) Platform data
+ ----------------
+
+ Many boards have custom implementation of internal API. Pointers to these
+ methods are stored in platform_data. But the most implementations for Intel
+ 82365 and compatible PC Card controllers and Yenta-compatible
+ PCI-to-CardBus controllers implement whole API per board. In these cases
+ pcmcia_on() and pcmcia_off() behave only as wrappers and call specific
+ board methods.
+
+III) Analysis of in-tree drivers
+--------------------------------
+
+ 1) i82365.c
+ -----------
+ Driver methods have different name i82365_init() and i82365_exit but
+ all functionality is the same. Board files board/atc/ti113x.c and
+ board/cpc45/pd67290.c use their own implementation of these method.
+ In this case all methods in driver behave only as wrappers.
+
+ 2) marubun_pcmcia.c
+ -------------------
+ Meets standard API behaviour. Simple conversion.
+
+ 3) mpc8xx_pcmcia.c
+ ------------------
+ Meets standard API behaviour. Simple conversion.
+
+ 4) rpx_pcmcia.c
+ ---------------
+ Implements only internal API used in other drivers. Non of methods
+ implemented here are used outside driver model.
+
+ 5) ti_pci1410a.c
+ ----------------
+ Has different API but methods in this file are never called. Probably
+ dead code.
+
+ 6)tqm8xx_pcmcia.c
+ -----------------
+ Implements only internal API used in other drivers. Non of methods
+ implemented here are used outside driver model.
--- /dev/null
+The U-Boot Driver Model Project
+===============================
+POWER analysis
+==============
+Viktor Krivak <viktor.krivak@gmail.com>
+2012-03-09
+
+I) Overview
+-----------
+
+ 1) Actual state
+ ---------------
+
+ At this moment power doesn't contain API. There are many methods for
+ initialization of some board specific functions but only few does what is
+ expected. Basically only one file contains something meaningful for this
+ driver.
+
+ 2) Current implementation
+ -------------------------
+
+ In file twl6030.c are methods twl6030_stop_usb_charging() and
+ twl6030_start_usb_charging() for start and stop charging from USB. There are
+ also methods to get information about battery state and initialization of
+ battery charging. Only these methods are used in converted API.
+
+
+II) Approach
+------------
+
+ 1) New API
+ ----------
+
+ New API implements only functions specific for managing power. All board
+ specific init methods are moved to other files. Name of methods are
+ self-explanatory.
+
+ struct ops {
+ void (*start_usb_charging)(struct instance *i);
+ void (*stop_usb_charging)(struct instance *i);
+ int (*get_battery_current)(struct instance *i);
+ int (*get_battery_voltage)(struct instance *i);
+ void (*init_battery_charging)(struct instance *i);
+ }
+
+ 2) Conversions of other methods
+ -------------------------------
+
+ Methods that can't be converted to new API are moved to board file or to
+ special file for board hacks.
+
+III) Analysis of in-tree drivers
+--------------------------------
+
+ 1) ftpmu010.c
+ -------------
+ All methods of this file are moved to another location.
+ void ftpmu010_32768osc_enable(void): Move to boards hacks
+ void ftpmu010_mfpsr_select_dev(unsigned int dev): Move to board file
+ arch/nds32/lib/board.c
+ void ftpmu010_mfpsr_diselect_dev(unsigned int dev): Dead code
+ void ftpmu010_dlldis_disable(void): Dead code
+ void ftpmu010_sdram_clk_disable(unsigned int cr0): Move to board file
+ arch/nds32/lib/board.c
+ void ftpmu010_sdramhtc_set(unsigned int val): Move to board file
+ arch/nds32/lib/board.c
+
+ 2) twl4030.c
+ ------------
+ All methods of this file are moved to another location.
+ void twl4030_power_reset_init(void): Move to board hacks
+ void twl4030_pmrecv_vsel_cfg(u8 vsel_reg, u8 vsel_val, u8 dev_grp,
+ u8 dev_grp_sel): Move to board hacks
+ void twl4030_power_init(void): Move to board hacks
+ void twl4030_power_mmc_init(void): Move to board hacks
+
+ 3) twl6030.c
+ ------------
+ Some methods are converted to new API and rest are moved to another location.
+ void twl6030_stop_usb_charging(void): Convert to new API
+ void twl6030_start_usb_charging(void): Convert to new API
+ int twl6030_get_battery_current(void): Convert to new API
+ int twl6030_get_battery_voltage(void): Convert to new API
+ void twl6030_init_battery_charging(void): Convert to new API
+ void twl6030_power_mmc_init(): Move to board file
+ drivers/mmc/omap_hsmmc.c
+ void twl6030_usb_device_settings(): Move to board file
+ drivers/usb/musb/omap3.c
--- /dev/null
+=============================
+RTC device subsystem analysis
+=============================
+
+Tomas Hlavacek <tmshlvck@gmail.com>
+2012-03-10
+
+I) Overview
+-----------
+
+U-Boot currently implements one common API for RTC devices. The interface
+is defined in include/rtc.h and comprises of functions and structures:
+
+ struct rtc_time {
+ int tm_sec;
+ int tm_min;
+ int tm_hour;
+ int tm_mday;
+ int tm_mon;
+ int tm_year;
+ int tm_wday;
+ int tm_yday;
+ int tm_isdst;
+ };
+
+ int rtc_get (struct rtc_time *);
+ int rtc_set (struct rtc_time *);
+ void rtc_reset (void);
+
+The functions are implemented by a proper device driver in drivers/rtc
+directory and the driver to be compiled in is selected in a Makefile.
+Drivers are mutually exclusive.
+
+Drivers depends on date code in drivers/rtc/date.c and naturally on board
+specific data.
+
+II) Approach
+------------
+
+ 1) New API
+ ----------
+ In the UDM each rtc driver would register itself by a function
+
+ int rtc_device_register(struct instance *i,
+ struct rtc_device_ops *o);
+
+ The structure being defined as follows:
+
+ struct rtc_device_ops {
+ int (*get_time)(struct instance *i, struct rtc_time *t);
+ int (*set_time)(struct instance *i, struct rtc_time *t);
+ int (*reset)(struct instance *i);
+ };
+
+
+ 2) Conversion thougths
+ ----------------------
+ U-Boot RTC drivers exports the same functions and therefore the conversion
+ of the drivers is straight-forward. There is no initialization needed.
+
+
+III) Analysis of in-tree drivers
+--------------------------------
+
+ 1) drivers/rtc/rv3029.c
+ -----------------------
+ The driver is standard rtc. Simple conversion is possible.
+
+
+ 2) drivers/rtc/s3c24x0_rtc.c
+ ----------------------------
+ The driver is standard rtc. Simple conversion is possible.
+
+
+ 3) drivers/rtc/pt7c4338.c
+ -------------------------
+ The driver is standard rtc. Simple conversion is possible.
+
+
+ 4) drivers/rtc/mvrtc.c
+ ----------------------
+ The driver is standard rtc. Simple conversion is possible.
+
+
+ 5) drivers/rtc/ftrtc010.c
+ -------------------------
+ The driver is standard rtc. Simple conversion is possible.
+
+
+ 6) drivers/rtc/mpc5xxx.c
+ ------------------------
+ The driver is standard rtc. Simple conversion is possible.
+
+
+ 7) drivers/rtc/ds164x.c
+ -----------------------
+ The driver is standard rtc. Simple conversion is possible.
+
+
+ 8) drivers/rtc/rs5c372.c
+ ------------------------
+ The driver is standard rtc. Simple conversion is possible.
+
+
+ 9) drivers/rtc/m41t94.c
+ -----------------------
+ The driver is standard rtc. Simple conversion is possible.
+
+
+ 10) drivers/rtc/mc13xxx-rtc.c
+ -----------------------------
+ The driver is standard rtc. Simple conversion is possible.
+
+
+ 11) drivers/rtc/mcfrtc.c
+ ------------------------
+ The driver is standard rtc. Simple conversion is possible.
+
+
+ 12) drivers/rtc/davinci.c
+ -------------------------
+ The driver is standard rtc. Simple conversion is possible.
+
+
+ 13) drivers/rtc/rx8025.c
+ ------------------------
+ The driver is standard rtc. Simple conversion is possible.
+
+
+ 14) drivers/rtc/bfin_rtc.c
+ --------------------------
+ The driver is standard rtc. Simple conversion is possible.
+
+
+ 15) drivers/rtc/m41t62.c
+ ------------------------
+ The driver is standard rtc. Simple conversion is possible.
+
+
+ 16) drivers/rtc/ds1306.c
+ ------------------------
+ The driver is standard rtc. Simple conversion is possible.
+
+
+ 17) drivers/rtc/mpc8xx.c
+ ------------------------
+ The driver is standard rtc. Simple conversion is possible.
+
+
+ 18) drivers/rtc/ds3231.c
+ ------------------------
+ The driver is standard rtc. Simple conversion is possible.
+
+
+ 19) drivers/rtc/ds12887.c
+ -------------------------
+ The driver is standard rtc. Simple conversion is possible.
+
+
+ 20) drivers/rtc/ds1302.c
+ ------------------------
+ The driver is standard rtc. Simple conversion is possible.
+
+
+ 21) drivers/rtc/ds1374.c
+ ------------------------
+ The driver is standard rtc. Simple conversion is possible.
+
+
+ 22) drivers/rtc/ds174x.c
+ ------------------------
+ The driver is standard rtc. Simple conversion is possible.
+
+
+ 23) drivers/rtc/m41t60.c
+ ------------------------
+ The driver is standard rtc. Simple conversion is possible.
+
+
+ 24) drivers/rtc/m48t35ax.c
+ --------------------------
+ The driver is standard rtc. Simple conversion is possible.
+
+
+ 25) drivers/rtc/pl031.c
+ -----------------------
+ The driver is standard rtc. Simple conversion is possible.
+
+
+ 26) drivers/rtc/x1205.c
+ -----------------------
+ The driver is standard rtc. Simple conversion is possible.
+
+
+ 27) drivers/rtc/m41t11.c
+ ------------------------
+ The driver is standard rtc. Simple conversion is possible.
+
+
+ 28) drivers/rtc/pcf8563.c
+ -------------------------
+ The driver is standard rtc. Simple conversion is possible.
+
+
+ 29) drivers/rtc/mk48t59.c
+ -------------------------
+ Macros needs cleanup. Besides that the driver is standard rtc.
+ Simple conversion is possible.
+
+
+ 30) drivers/rtc/mxsrtc.c
+ ------------------------
+ The driver is standard rtc. Simple conversion is possible.
+
+
+ 31) drivers/rtc/ds1307.c
+ ------------------------
+ The driver is standard rtc. Simple conversion is possible.
+
+
+ 32) drivers/rtc/ds1556.c
+ ------------------------
+ The driver is standard rtc. Simple conversion is possible.
+
+
+ 33) drivers/rtc/rtc4543.c
+ -------------------------
+ The driver is standard rtc. Simple conversion is possible.
+
+
+ 34) drivers/rtc/s3c44b0_rtc.c
+ -----------------------------
+ The driver is standard rtc. Simple conversion is possible.
+
+
+ 35) drivers/rtc/ds1337.c
+ ------------------------
+ The driver is standard rtc. Simple conversion is possible.
+
+
+ 36) drivers/rtc/isl1208.c
+ -------------------------
+ The driver is standard rtc. Simple conversion is possible.
+
+
+ 37) drivers/rtc/max6900.c
+ -------------------------
+ The driver is standard rtc. Simple conversion is possible.
+
+
+ 38) drivers/rtc/mc146818.c
+ --------------------------
+ The driver is standard rtc. Simple conversion is possible.
+
+
+ 39) drivers/rtc/at91sam9_rtt.c
+ ------------------------------
+ The driver is standard rtc. Simple conversion is possible.
--- /dev/null
+The U-Boot Driver Model Project
+===============================
+Serial I/O analysis
+===================
+Marek Vasut <marek.vasut@gmail.com>
+2012-02-20
+
+I) Overview
+-----------
+
+The serial port support currently requires the driver to export the following
+functions:
+
+ serial_putc() ...... Output a character
+ serial_puts() ...... Output string, often done using serial_putc()
+ serial_tstc() ...... Test if incoming character is in a buffer
+ serial_getc() ...... Retrieve incoming character
+ serial_setbrg() .... Configure port options
+ serial_init() ...... Initialize the hardware
+
+The simpliest implementation, supporting only one port, simply defines these six
+functions and calls them. Such calls are scattered all around U-Boot, especiall
+serial_putc(), serial_puts(), serial_tstc() and serial_getc(). The serial_init()
+and serial_setbrg() are often called from platform-dependent places.
+
+It's important to consider current implementation of CONFIG_SERIAL_MULTI though.
+This resides in common/serial.c and behaves as a multiplexer for serial ports.
+This, by calling serial_assign(), allows user to switch I/O from one serial port
+to another. Though the environmental variables "stdin", "stdout", "stderr"
+remain set to "serial".
+
+These variables are managed by the IOMUX. This resides in common/iomux.c and
+manages all console input/output from U-Boot. For serial port, only one IOMUX is
+always registered, called "serial" and the switching of different serial ports
+is done by code in common/serial.c.
+
+On a final note, it's important to mention function default_serial_console(),
+which is platform specific and reports the default serial console for the
+platform, unless proper environment variable overrides this.
+
+II) Approach
+------------
+
+Drivers not using CONFIG_SERIAL_MULTI already will have to be converted to
+similar approach. The probe() function of a driver will call a function
+registering the driver with a STDIO subsystem core, stdio_device_register().
+
+The serial_init() function will now be replaced by probe() function of the
+driver, the rest of the components of the driver will be converted to standard
+STDIO driver calls. See [ UDM-stdio.txt ] for details.
+
+The serial_setbrg() function depends on global data pointer. This is wrong,
+since there is likely to be user willing to configure different baudrate on two
+different serial ports. The function will be replaced with STDIO's "conf()"
+call, with STDIO_CONFIG_SERIAL_BAUDRATE argument.
+
+III) Analysis of in-tree drivers
+--------------------------------
+
+ 1) altera_jtag_uart.c
+ ---------------------
+ No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
+
+ 2) altera_uart.c
+ ----------------
+ No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
+
+ 3) arm_dcc.c
+ ------------
+ No support for CONFIG_SERIAL_MULTI. Simple conversion possible, unless used
+ with CONFIG_ARM_DCC_MULTI. Then it registers another separate IOMUX.
+
+ 4) atmel_usart.c
+ ----------------
+ No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
+
+ 5) mcfuart.c
+ ------------
+ No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
+
+ 6) ns16550.c
+ ------------
+ This driver seems complicated and certain consideration will need to be made
+ during conversion. This driver is implemented in very universal manner,
+ therefore it'll be necessary to properly design it's platform_data.
+
+ 7) ns9750_serial.c
+ ------------------
+ No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
+
+ 8) opencores_yanu.c
+ -------------------
+ No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
+
+ 9) s3c4510b_uart.c
+ ------------------
+ No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
+
+ 10) s3c64xx.c
+ -------------
+ No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
+
+ 11) sandbox.c
+ -------------
+ No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
+
+ 12) serial.c
+ ------------
+ This is a complementary part of NS16550 UART driver, see above.
+
+ 13) serial_clps7111.c
+ ---------------------
+ No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
+
+ 14) serial_imx.c
+ ----------------
+ No support for CONFIG_SERIAL_MULTI. Simple conversion possible. This driver
+ might be removed in favor of serial_mxc.c .
+
+ 15) serial_ixp.c
+ ----------------
+ No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
+
+ 16) serial_ks8695.c
+ -------------------
+ No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
+
+ 17) serial_lh7a40x.c
+ --------------------
+ No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
+
+ 18) serial_lpc2292.c
+ --------------------
+ No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
+
+ 19) serial_max3100.c
+ --------------------
+ No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
+
+ 20) serial_mxc.c
+ ----------------
+ No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
+
+ 21) serial_netarm.c
+ -------------------
+ No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
+
+ 22) serial_pl01x.c
+ ------------------
+ No support for CONFIG_SERIAL_MULTI. Simple conversion possible, though this
+ driver in fact contains two drivers in total.
+
+ 23) serial_pxa.c
+ ----------------
+ This driver is a bit complicated, but due to clean support for
+ CONFIG_SERIAL_MULTI, there are no expected obstructions throughout the
+ conversion process.
+
+ 24) serial_s3c24x0.c
+ --------------------
+ This driver, being quite ad-hoc might need some work to bring back to shape.
+
+ 25) serial_s3c44b0.c
+ --------------------
+ No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
+
+ 26) serial_s5p.c
+ ----------------
+ No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
+
+ 27) serial_sa1100.c
+ -------------------
+ No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
+
+ 28) serial_sh.c
+ ---------------
+ No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
+
+ 29) serial_xuartlite.c
+ ----------------------
+ No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
+
+ 30) usbtty.c
+ ------------
+ This driver seems very complicated and entangled with USB framework. The
+ conversion might be complicated here.
+
+ 31) arch/powerpc/cpu/mpc512x/serial.c
+ -------------------------------------
+ This driver supports CONFIG_SERIAL_MULTI. This driver will need to be moved to
+ proper place.
--- /dev/null
+The U-Boot Driver Model Project
+===============================
+SPI analysis
+============
+Viktor Krivak <viktor.krivak@gmail.com>
+2012-03-03
+
+I) Overview
+-----------
+
+ 1) The SPI driver
+ -----------------
+
+ At this moment U-Boot provides standard API that consist of 7 functions:
+
+ void spi_init(void);
+ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode);
+ void spi_free_slave(struct spi_slave *slave);
+ int spi_claim_bus(struct spi_slave *slave);
+ void spi_release_bus(struct spi_slave *slave);
+ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags);
+ int spi_cs_is_valid(unsigned int bus, unsigned int cs);
+ void spi_cs_activate(struct spi_slave *slave);
+ void spi_cs_deactivate(struct spi_slave *slave);
+ void spi_set_speed(struct spi_slave *slave, uint hz);
+
+ Method spi_init() is usually empty. All necessary configuration are sets by
+ spi_setup_slave(). But this configuration is usually stored only in memory.
+ No real hardware sets are made. All hardware settings are provided by method
+ spi_claim_bus(). This method claims the bus and it can't be claimed again
+ until it's release. That's mean all calls of method spi_claim_bus() will
+ fail. But lots of cpu implementation don't meet this behaviour.
+ Method spi_release_bus() does exact opposite. It release bus directly by
+ some hardware sets. spi_free_slave() only free memory allocated by
+ spi_setup_slave(). Method spi_xfer() do actually read and write operation
+ throw specified bus and cs. Other methods are self explanatory.
+
+ 2) Current limitations
+ ----------------------
+
+ Theoretically at this moment api allows use more then one bus per device at
+ the time. But in real this can be achieved only when all buses have their
+ own base addresses in memory.
+
+
+II) Approach
+------------
+
+ 1) Claiming bus
+ ---------------
+
+ The current api cannot be used because struct spi_slave have to be in
+ private data. In that case user are prohibited to use different bus on one
+ device at same time. But when base memory address for bus are different.
+ It's possible make more instance of this driver. Otherwise it can't can be
+ done because of hardware limitation.
+
+ 2) API change
+ -------------
+
+ Method spi_init() is moved to probe. Methods spi_setup_slave() and
+ spi_claim_bus() are joined to one method. This method checks if desired bus
+ exists and is available then configure necessary hardware and claims bus.
+ Method spi_release_bus() and spi_free_slave() are also joined to meet this
+ new approach. Other function remain same. Only struct spi_slave was change
+ to instance.
+
+ struct ops {
+ int (*spi_request_bus)(struct instance *i, unsigned int bus,
+ unsigned int cs, unsigned int max_hz,
+ unsigned int mode);
+ void (*spi_release_bus)(struct instance *i);
+ int (*spi_xfer) (struct instance *i, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags);
+ int (*spi_cs_is_valid)(struct instance *i, unsigned int bus,
+ unsigned int cs);
+ void (*spi_cs_activate)(struct instance *i);
+ void (*spi_cs_deactivate)(struct instance *i);
+ void (*spi_set_speed)(struct instance *i, uint hz);
+ }
+
+ 3) Legacy API
+ -------------
+
+ To easy conversion of the whole driver. Original and new api can exist next
+ to each other. New API is designed to be only a wrapper that extracts
+ necessary information from private_data and use old api. When driver can
+ use more than one bus at the time. New API require multiple instance. One
+ for each bus. In this case spi_slave have to be copied in each instance.
+
+ 4) Conversion TIME-LINE
+ -----------------------
+
+ To prevent build corruption api conversion have to be processed in several
+ independent steps. In first step all old API methods are renamed. After that
+ new API and core function are implemented. Next step is conversion of all
+ board init methods to set platform data. After all these steps it is possible
+ to start conversion of all remaining calls. This procedure guarantees that
+ build procedure and binaries are never broken.
+
+III) Analysis of in-tree drivers
+--------------------------------
+
+ 1) altera_spi.c
+ ---------------
+ All methods have designated structure. Simple conversion possible.
+
+ 2) andes_spi.c
+ --------------
+ All methods have designated structure. Simple conversion possible.
+
+ 3) andes_spi.h
+ --------------
+ Support file for andes_spi.c. No conversion is needed.
+
+ 4) armada100_spi.c
+ ------------------
+ All methods have designated structure. Simple conversion possible.
+
+ 5) atmel_dataflash_spi.c
+ ------------------------
+ Wrong placement. Will be moved to another location.
+
+ 6) atmel_spi.c
+ --------------
+ Supports more than one bus. Need some minor change.
+
+ 7) atmel_spi.h
+ --------------
+ Support file for andes_spi.c. No conversion is needed.
+
+ 8) bfin_spi.c
+ -------------
+ Supports more than one bus. Need some minor change.
+
+ 9) cf_spi.c
+ -----------
+ Cooperate with some cpu specific methods from other files. Hard conversion.
+
+ 10) davinci_spi.c
+ -----------------
+ All methods have designated structure. Simple conversion possible.
+
+ 11) davinci_spi.h
+ -----------------
+ Support file for davinci_spi.h. No conversion is needed.
+
+ 12) fsl_espi.c
+ --------------
+ All methods have designated structure. Simple conversion possible.
+
+ 13) kirkwood_spi.c
+ ------------------
+ All methods have designated structure. Simple conversion possible.
+
+ 14) mpc8xxx_spi.c
+ -----------------
+ All methods have designated structure. Simple conversion possible.
+
+ 15) mpc52xx_spi.c
+ -----------------
+ All methods have designated structure. Simple conversion possible.
+
+ 16) mxc_spi.c
+ -------------
+ All methods have designated structure. Simple conversion possible.
+
+ 17) mxs_spi.c
+ -------------
+ All methods have designated structure. Simple conversion possible.
+
+ 18) oc_tiny_spi.c
+ -----------------
+ Supports more than one bus. Need some minor change.
+
+ 19) omap3_spi.c
+ ---------------
+ Supports more than one bus. Need some minor change.
+
+ 20) omap3_spi.h
+ ---------------
+ Support file for omap3_spi.c. No conversion is needed.
+
+ 21) sh_spi.c
+ ------------
+ All methods have designated structure. Simple conversion possible.
+
+ 22) sh_spi.h
+ ------------
+ Support file for sh_spi.h. No conversion is needed.
+
+ 23) soft_spi.c
+ --------------
+ Use many board specific method linked from other files. Need careful debugging.
+
+ 24) tegra2_spi.c
+ ----------------
+ Some hardware specific problem when releasing bus.
--- /dev/null
+The U-Boot Driver Model Project
+===============================
+I/O system analysis
+===================
+Marek Vasut <marek.vasut@gmail.com>
+2012-02-20
+
+I) Overview
+-----------
+
+The console input and output is currently done using the STDIO subsystem in
+U-Boot. The design of this subsystem is already flexible enough to be easily
+converted to new driver model approach. Minor changes will need to be done
+though.
+
+Each device that wants to register with STDIO subsystem has to define struct
+stdio_dev, defined in include/stdio_dev.h and containing the following fields:
+
+struct stdio_dev {
+ int flags; /* Device flags: input/output/system */
+ int ext; /* Supported extensions */
+ char name[16]; /* Device name */
+
+/* GENERAL functions */
+
+ int (*start) (void); /* To start the device */
+ int (*stop) (void); /* To stop the device */
+
+/* OUTPUT functions */
+
+ void (*putc) (const char c); /* To put a char */
+ void (*puts) (const char *s); /* To put a string (accelerator) */
+
+/* INPUT functions */
+
+ int (*tstc) (void); /* To test if a char is ready... */
+ int (*getc) (void); /* To get that char */
+
+/* Other functions */
+
+ void *priv; /* Private extensions */
+ struct list_head list;
+};
+
+Currently used flags are DEV_FLAGS_INPUT, DEV_FLAGS_OUTPUT and DEV_FLAGS_SYSTEM,
+extensions being only one, the DEV_EXT_VIDEO.
+
+The private extensions are now used as a per-device carrier of private data and
+finally list allows this structure to be a member of linked list of STDIO
+devices.
+
+The STDIN, STDOUT and STDERR routing is handled by environment variables
+"stdin", "stdout" and "stderr". By configuring the variable to the name of a
+driver, functions of such driver are called to execute that particular
+operation.
+
+II) Approach
+------------
+
+ 1) Similarity of serial, video and keyboard drivers
+ ---------------------------------------------------
+
+ All of these drivers can be unified under the STDIO subsystem if modified
+ slightly. The serial drivers basically define both input and output functions
+ and need function to configure baudrate. The keyboard drivers provide only
+ input. On the other hand, video drivers provide output, but need to be
+ configured in certain way. This configuration might be dynamic, therefore the
+ STDIO has to be modified to provide such flexibility.
+
+ 2) Unification of serial, video and keyboard drivers
+ ----------------------------------------------------
+
+ Every STDIO device would register a structure containing operation it supports
+ with the STDIO core by calling:
+
+ int stdio_device_register(struct instance *i, struct stdio_device_ops *o);
+
+ The structure being defined as follows:
+
+ struct stdio_device_ops {
+ void (*putc)(struct instance *i, const char c);
+ void (*puts)(struct instance *i, const char *s); /* OPTIONAL */
+
+ int (*tstc)(struct instance *i);
+ int (*getc)(struct instance *i);
+
+ int (*init)(struct instance *i);
+ int (*exit)(struct instance *i);
+ int (*conf)(struct instance *i, enum stdio_config c, const void *data);
+ };
+
+ The "putc()" function will emit a character, the "puts()" function will emit a
+ string. If both of these are set to NULL, the device is considered STDIN only,
+ aka input only device.
+
+ The "getc()" retrieves a character from a STDIN device, while "tstc()" tests
+ if there is a character in the buffer of STDIN device. In case these two are
+ set to NULL, this device is STDOUT / STDERR device.
+
+ Setting all "putc()", "puts()", "getc()" and "tstc()" calls to NULL isn't an
+ error condition, though such device does nothing. By instroducing tests for
+ these functions being NULL, the "flags" and "ext" fields from original struct
+ stdio_dev can be eliminated.
+
+ The "init()" and "exit()" calls are replacement for "start()" and "exit()"
+ calls in the old approach. The "priv" part of the old struct stdio_dev will be
+ replaced by common private data in the driver model and the struct list_head
+ list will be eliminated by introducing common STDIO core, that tracks all the
+ STDIO devices.
+
+ Lastly, the "conf()" call will allow the user to configure various options of
+ the driver. The enum stdio_config contains all possible configuration options
+ available to the STDIO devices, const void *data being the argument to be
+ configured. Currently, the enum stdio_config will contain at least the
+ following options:
+
+ enum stdio_config {
+ STDIO_CONFIG_SERIAL_BAUDRATE,
+ };
+
+ 3) Transformation of stdio routing
+ ----------------------------------
+
+ By allowing multiple instances of drivers, the environment variables "stdin",
+ "stdout" and "stderr" can no longer be set to the name of the driver.
+ Therefore the STDIO core, tracking all of the STDIO devices in the system will
+ need to have a small amount of internal data for each device:
+
+ struct stdio_device_node {
+ struct instance *i;
+ struct stdio_device_ops *ops;
+ uint8_t id;
+ uint8_t flags;
+ struct list_head list;
+ }
+
+ The "id" is the order of the instance of the same driver. The "flags" variable
+ allows multiple drivers to be used at the same time and even for different
+ purpose. The following flags will be defined:
+
+ STDIO_FLG_STDIN ..... This device will be used as an input device. All input
+ from all devices with this flag set will be received
+ and passed to the upper layers.
+ STDIO_FLG_STDOUT .... This device will be used as an output device. All
+ output sent to stdout will be routed to all devices
+ with this flag set.
+ STDIO_FLG_STDERR .... This device will be used as an standard error output
+ device. All output sent to stderr will be routed to
+ all devices with this flag set.
+
+ The "list" member of this structure allows to have a linked list of all
+ registered STDIO devices.
+
+III) Analysis of in-tree drivers
+--------------------------------
+
+For in-depth analysis of serial port drivers, refer to [ UDM-serial.txt ].
+For in-depth analysis of keyboard drivers, refer to [ UDM-keyboard.txt ].
+For in-depth analysis of video drivers, refer to [ UDM-video.txt ].
+
+ 1) arch/blackfin/cpu/jtag-console.c
+ -----------------------------------
+ This driver is a classic STDIO driver, no problem with conversion is expected.
+
+ 2) board/mpl/pati/pati.c
+ ------------------------
+ This driver registers with the STDIO framework, though it uses a lot of ad-hoc
+ stuff which will need to be sorted out.
+
+ 3) board/netphone/phone_console.c
+ ---------------------------------
+ This driver is a classic STDIO driver, no problem with conversion is expected.
+
+ 4) drivers/net/netconsole.c
+ ---------------------------
+ This driver is a classic STDIO driver, no problem with conversion is expected.
+
+IV) Other involved files (To be removed)
+----------------------------------------
+
+common/cmd_console.c
+common/cmd_log.c
+common/cmd_terminal.c
+common/console.c
+common/fdt_support.c
+common/iomux.c
+common/lcd.c
+common/serial.c
+common/stdio.c
+common/usb_kbd.c
+doc/README.iomux
--- /dev/null
+The U-Boot Driver Model Project
+===============================
+TPM system analysis
+===================
+Marek Vasut <marek.vasut@gmail.com>
+2012-02-23
+
+I) Overview
+-----------
+
+There is currently only one TPM chip driver available and therefore the API
+controlling it is very much based on this. The API is very simple:
+
+ int tis_open(void);
+ int tis_close(void);
+ int tis_sendrecv(const u8 *sendbuf, size_t send_size,
+ u8 *recvbuf, size_t *recv_len);
+
+The command operating the TPM chip only provides operations to send and receive
+bytes from the chip.
+
+II) Approach
+------------
+
+The API can't be generalised too much considering there's only one TPM chip
+supported. But it's a good idea to split the tis_sendrecv() function in two
+functions. Therefore the new API will use register the TPM chip by calling:
+
+ tpm_device_register(struct instance *i, const struct tpm_ops *ops);
+
+And the struct tpm_ops will contain the following members:
+
+ struct tpm_ops {
+ int (*tpm_open)(struct instance *i);
+ int (*tpm_close)(struct instance *i);
+ int (*tpm_send)(const uint8_t *buf, const size_t size);
+ int (*tpm_recv)(uint8_t *buf, size_t *size);
+ };
+
+The behaviour of "tpm_open()" and "tpm_close()" will basically copy the
+behaviour of "tis_open()" and "tis_close()". The "tpm_send()" will be based on
+the "tis_senddata()" and "tis_recv()" will be based on "tis_readresponse()".
+
+III) Analysis of in-tree drivers
+--------------------------------
+
+There is only one in-tree driver present, the "drivers/tpm/generic_lpc_tpm.c",
+which will be simply converted as outlined in previous chapter.
--- /dev/null
+==================================
+TWserial device subsystem analysis
+==================================
+
+Tomas Hlavacek<tmshlvck@gmail.com>
+2012-03-21
+
+I) Overview
+-----------
+
+U-Boot currently implements one common API for TWSerial devices. The interface
+is defined in include/tws.h and comprises of functions:
+
+ int tws_read(uchar *buffer, int len);
+ int tws_write(uchar *buffer, int len);
+
+The functions are implemented by a proper device driver in drivers/twserial
+directory and the driver to be compiled in is selected in a Makefile. There is
+only one driver present now.
+
+The driver depends on ad-hoc code in board specific data, namely functions:
+
+ void tws_ce(unsigned bit);
+ void tws_wr(unsigned bit);
+ void tws_clk(unsigned bit);
+ void tws_data(unsigned bit);
+ unsigned tws_data_read(void);
+ void tws_data_config_output(unsigned output);
+
+implemented in include/configs/inka4x0.h .
+
+II) Approach
+------------
+
+ U-Boot TWserial drivers exports two simple functions and therefore the conversion
+ of the driver and creating a core for it is not needed. It should be consolidated
+ with include/configs/inka4x0.h and taken to the misc/ dir.
+
+
+III) Analysis of in-tree drivers
+--------------------------------
+
+ 1) drivers/twserial/soft_tws.c
+ ------------------------------
+ The driver is the only TWserial driver. The ad-hoc part in
+ include/configs/inka4x0.h and the core soft_tws driver should be consolidated
+ to one compact driver and moved to misc/ .
--- /dev/null
+The U-Boot Driver Model Project
+===============================
+USB analysis
+============
+Marek Vasut <marek.vasut@gmail.com>
+2012-02-16
+
+I) Overview
+-----------
+
+ 1) The USB Host driver
+ ----------------------
+ There are basically four or five USB host drivers. All such drivers currently
+ provide at least the following fuctions:
+
+ usb_lowlevel_init() ... Do the initialization of the USB controller hardware
+ usb_lowlevel_stop() ... Do the shutdown of the USB controller hardware
+
+ usb_event_poll() ...... Poll interrupt from USB device, often used by KBD
+
+ submit_control_msg() .. Submit message via Control endpoint
+ submit_int_msg() ...... Submit message via Interrupt endpoint
+ submit_bulk_msg() ..... Submit message via Bulk endpoint
+
+
+ This allows for the host driver to be easily abstracted.
+
+ 2) The USB hierarchy
+ --------------------
+
+ In the current implementation, the USB Host driver provides operations to
+ communicate via the USB bus. This is realised by providing access to a USB
+ root port to which an USB root hub is attached. The USB bus is scanned and for
+ each newly found device, a struct usb_device is allocated. See common/usb.c
+ and include/usb.h for details.
+
+II) Approach
+------------
+
+ 1) The USB Host driver
+ ----------------------
+
+ Converting the host driver will follow the classic driver model consideration.
+ Though, the host driver will have to call a function that registers a root
+ port with the USB core in it's probe() function, let's call this function
+
+ usb_register_root_port(&ops);
+
+ This will allow the USB core to track all available root ports. The ops
+ parameter will contain structure describing operations supported by the root
+ port:
+
+ struct usb_port_ops {
+ void (*usb_event_poll)();
+ int (*submit_control_msg)();
+ int (*submit_int_msg)();
+ int (*submit_bulk_msg)();
+ }
+
+ 2) The USB hierarchy and hub drivers
+ ------------------------------------
+
+ Converting the USB heirarchy should be fairy simple, considering the already
+ dynamic nature of the implementation. The current usb_hub_device structure
+ will have to be converted to a struct instance. Every such instance will
+ contain components of struct usb_device and struct usb_hub_device in it's
+ private data, providing only accessors in order to properly encapsulate the
+ driver.
+
+ By registering the root port, the USB framework will instantiate a USB hub
+ driver, which is always present, the root hub. The root hub and any subsequent
+ hub instance is represented by struct instance and it's private data contain
+ amongst others common bits from struct usb_device.
+
+ Note the USB hub driver is partly defying the usual method of registering a
+ set of callbacks to a particular core driver. Instead, a static set of
+ functions is defined and the USB hub instance is passed to those. This creates
+ certain restrictions as of how the USB hub driver looks, but considering the
+ specification for USB hub is given and a different type of USB hub won't ever
+ exist, this approach is ok:
+
+ - Report how many ports does this hub have:
+ uint get_nr_ports(struct instance *hub);
+ - Get pointer to device connected to a port:
+ struct instance *(*get_child)(struct instance *hub, int port);
+ - Instantiate and configure device on port:
+ struct instance *(*enum_dev_on_port)(struct instance *hub, int port);
+
+ 3) USB device drivers
+ ---------------------
+
+ The USB device driver, in turn, will have to register various ops structures
+ with certain cores. For example, USB disc driver will have to register it's
+ ops with core handling USB discs etc.
--- /dev/null
+The U-Boot Driver Model Project
+===============================
+Video output analysis
+=====================
+Marek Vasut <marek.vasut@gmail.com>
+2012-02-20
+
+I) Overview
+-----------
+
+The video drivers are most often registered with video subsystem. This subsystem
+often expects to be allowed access to framebuffer of certain parameters. This
+subsystem also provides calls for STDIO subsystem to allow it to output
+characters on the screen. For this part, see [ UDM-stdio.txt ].
+
+Therefore the API has two parts, the video driver part and the part where the
+video driver core registers with STDIO API.
+
+The video driver part will follow the current cfb_console approach, though
+allowing it to be more dynamic.
+
+II) Approach
+------------
+
+Registering the video driver into the video driver core is done by calling the
+following function from the driver probe() function:
+
+ video_device_register(struct instance *i, GraphicDevice *gd);
+
+Because the video driver core is in charge or rendering characters as well as
+bitmaps on the screen, it will in turn call stdio_device_register(i, so), where
+"i" is the same instance as the video driver's one. But "so" will be special
+static struct stdio_device_ops handling the character output.
+
+
+III) Analysis of in-tree drivers
+--------------------------------
+
+ 1) arch/powerpc/cpu/mpc8xx/video.c
+ ----------------------------------
+ This driver copies the cfb_console [ see drivers/video/cfb_console.c ]
+ approach and acts only as a STDIO device. Therefore there are currently two
+ possible approaches, first being the conversion of this driver to usual STDIO
+ device and second, long-term one, being conversion of this driver to video
+ driver that provides console.
+
+ 2) arch/x86/lib/video.c
+ -----------------------
+ This driver registers two separate STDIO devices and should be therefore
+ converted as such.
+
+ 3) board/bf527-ezkit/video.c
+ ----------------------------
+ This driver seems bogus as it behaves as STDIO device, but provides no input
+ or output capabilities. It relies on DEV_EXT_VIDEO, which is no longer in use
+ or present otherwise than as a dead code/define.
+
+ 4) board/bf533-stamp/video.c
+ ----------------------------
+ This driver seems bogus as it behaves as STDIO device, but provides no input
+ or output capabilities. It relies on DEV_EXT_VIDEO, which is no longer in use
+ or present otherwise than as a dead code/define.
+
+ 5) board/bf548-ezkit/video.c
+ ----------------------------
+ This driver seems bogus as it behaves as STDIO device, but provides no input
+ or output capabilities. It relies on DEV_EXT_VIDEO, which is no longer in use
+ or present otherwise than as a dead code/define.
+
+ 6) board/cm-bf548/video.c
+ ----------------------------
+ This driver seems bogus as it behaves as STDIO device, but provides no input
+ or output capabilities. It relies on DEV_EXT_VIDEO, which is no longer in use
+ or present otherwise than as a dead code/define.
--- /dev/null
+The U-Boot Driver Model Project
+===============================
+Watchdog device subsystem analysis
+==================================
+
+Tomas Hlavacek <tmshlvck@gmail.com>
+2012-03-09
+
+I) Overview
+-----------
+
+U-Boot currently implements an API for HW watchdog devices as explicit drivers
+in drivers/watchdog directory. There are also drivers for both hardware and
+software watchdog on particular CPUs implemented in arch/*/cpu/*/cpu.c. There
+are macros in include/watchdog.h that selects between SW and HW watchdog and
+assembly SW implementation.
+
+The current common interface comprises of one set out of these two possible
+variants:
+
+ 1)
+ void watchdog_reset(void);
+ int watchdog_disable(void);
+ int watchdog_init(void);
+
+ 2)
+ void hw_watchdog_reset(void);
+ void hw_watchdog_init(void);
+
+The watchdog implementations are also spread through board/*/*.c that in
+some cases. The API and semantics is in most cases same as the above
+mentioned common functions.
+
+
+II) Approach
+------------
+
+ 1) New API
+ ----------
+
+ In the UDM each watchdog driver would register itself by a function
+
+ int watchdog_device_register(struct instance *i,
+ const struct watchdog_device_ops *o);
+
+ The structure being defined as follows:
+
+ struct watchdog_device_ops {
+ int (*disable)(struct instance *i);
+ void (*reset)(struct instance *i);
+ };
+
+ The watchdog_init() function will be dissolved into probe() function.
+
+ 2) Conversion thougths
+ ----------------------
+
+ Conversion of watchdog implementations to a new API could be divided
+ to three subsections: a) HW implementations, which are mostly compliant
+ to the above mentioned API; b) SW implementations, which are compliant
+ to the above mentioned API and c) SW implementations that are not compliant
+ to the API and has to be rectified or partially rewritten.
+
+III) Analysis of in-tree drivers
+--------------------------------
+
+ 1) drivers/watchdog/at91sam9_wdt.c
+ ----------------------------------
+ The driver is standard HW watchdog. Simple conversion is possible.
+
+
+ 2) drivers/watchdog/ftwdt010_wdt.c
+ ----------------------------------
+ The driver is ad-hoc HW watchdog. Conversion has to take into account
+ driver parts spread in include/faraday/*. Restructuring the driver and
+ code cleanup has to be considered.
+
+
+ 3) arch/arm/cpu/arm1136/mx31/timer.c
+ ------------------------------------
+ The driver is semi-standard ad-hoc HW watchdog. Conversion has to take
+ into account driver parts spread in the timer.c file.
+
+
+ 4) arch/arm/cpu/arm926ejs/davinci/timer.c
+ -----------------------------------------
+ The driver is ad-hoc semi-standard HW watchdog. Conversion has to take
+ into account driver parts spread in the timer.c file.
+
+
+ 5) arch/arm/cpu/armv7/omap-common/hwinit-common.c
+ -------------------------------------------------
+ The driver is non-standard ad-hoc HW watchdog. Conversion is possible
+ but functions has to be renamed and constants moved to another places.
+
+
+ 6) arch/arm/cpu/armv7/omap3/board.c
+ -----------------------------------
+ The driver is non-standard ad-hoc HW watchdog. Conversion is possible
+ but functions has to be renamed and constants moved to another places.
+
+
+ 7) arch/blackfin/cpu/watchdog.c
+ -------------------------------
+ The driver is standard HW watchdog. Simple conversion is possible.
+
+
+ 8) arch/m68k/cpu/mcf523x/cpu.c
+ ------------------------------
+ The driver is standard HW watchdog. Simple conversion is possible.
+
+
+ 9) arch/m68k/cpu/mcf52x2/cpu.c
+ ------------------------------
+ The driver is standard HW watchdog. Simple conversion is possible.
+
+
+ 10) arch/m68k/cpu/mcf532x/cpu.c
+ -------------------------------
+ The driver is standard HW watchdog. Simple conversion is possible.
+
+
+ 11) arch/m68k/cpu/mcf547x_8x/cpu.c
+ ----------------------------------
+ The driver is standard HW watchdog (there is slight naming convention
+ violation that has to be rectified). Simple conversion is possible.
+
+
+ 12) arch/powerpc/cpu/74xx_7xx/cpu.c
+ -----------------------------------
+ The driver is standard HW watchdog. Simple conversion is possible.
+
+
+ 13) arch/powerpc/cpu/mpc512x/cpu.c
+ ----------------------------------
+ The driver is standard HW watchdog. Simple conversion is possible.
+
+
+ 14) arch/powerpc/cpu/mpc5xx/cpu.c
+ ---------------------------------
+ The driver is standard HW watchdog. Simple conversion is possible.
+
+
+ 15) arch/powerpc/cpu/mpc5xxx/cpu.c
+ ----------------------------------
+ The driver is standard HW watchdog. Simple conversion is possible.
+
+
+ 16) arch/powerpc/cpu/mpc8260/cpu.c
+ ----------------------------------
+ The driver is standard HW watchdog. Simple conversion is possible.
+
+
+ 17) arch/powerpc/cpu/mpc83xx/cpu.c
+ ----------------------------------
+ The driver is standard HW watchdog. Simple conversion is possible.
+
+
+ 18) arch/powerpc/cpu/mpc85xx/cpu.c
+ ----------------------------------
+ The driver is standard HW watchdog. Simple conversion is possible.
+
+
+ 19) arch/powerpc/cpu/mpc86xx/cpu.c
+ ----------------------------------
+ The driver is standard HW watchdog. Simple conversion is possible.
+
+
+ 20) arch/powerpc/cpu/mpc8xx/cpu.c
+
+ The driver is standard HW watchdog. Simple conversion is possible.
+
+
+ 21) arch/powerpc/cpu/ppc4xx/cpu.c
+ ---------------------------------
+ The driver is standard HW watchdog. Simple conversion is possible.
+
+
+ 22) arch/sh/cpu/sh2/watchdog.c
+ ------------------------------
+ The driver is standard HW watchdog. Simple conversion is possible.
+
+
+ 23) arch/sh/cpu/sh3/watchdog.c
+ ------------------------------
+ The driver is standard HW watchdog. Simple conversion is possible.
+
+
+ 24) arch/sh/cpu/sh4/watchdog.c
+ ------------------------------
+ The driver is standard HW watchdog. Simple conversion is possible.
+
+
+ 25) board/amcc/luan/luan.c
+ --------------------------
+ The driver is standard HW watchdog. Simple conversion is possible.
+
+
+ 26) board/amcc/yosemite/yosemite.c
+ ----------------------------------
+ The driver is standard HW watchdog. Simple conversion is possible.
+
+
+ 27) board/apollon/apollon.c
+ ---------------------------
+ The driver is standard HW watchdog however the watchdog_init()
+ function is called in early initialization. Simple conversion is possible.
+
+
+ 28) board/bmw/m48t59y.c
+ -----------------------
+ Special watchdog driver. Dead code. To be removed.
+
+
+ 29) board/davedenx/qong/qong.c
+ ------------------------------
+ The driver is standard HW watchdog. Simple conversion is possible.
+
+
+ 30) board/dvlhost/watchdog.c
+ ----------------------------
+ The driver is standard HW watchdog. Simple conversion is possible.
+
+
+ 31) board/eNET/eNET.c
+ ---------------------
+ The driver is standard HW watchdog. Simple conversion is possible.
+
+
+ 32) board/eltec/elppc/elppc.c
+ -----------------------------
+ The driver is standard HW watchdog. Simple conversion is possible.
+
+
+ 33) board/enbw/enbw_cmc/enbw_cmc.c
+ ----------------------------------
+ Only function proxy call. Code cleanup needed.
+
+
+ 34) board/freescale/mx31pdk/mx31pdk.c
+ -------------------------------------
+ Only function proxy call. Code cleanup needed.
+
+
+ 35) board/gth2/gth2.c
+ ---------------------
+ The driver is standard HW watchdog. Simple conversion is possible.
+
+
+ 36) board/lwmon5/lwmon5.c
+ -------------------------
+ The driver is standard HW watchdog. Simple conversion is possible.
+
+
+ 37) board/manroland/mucmc52/mucmc52.c
+ -------------------------------------
+ The driver is standard HW watchdog. Simple conversion is possible.
+
+
+ 38) board/manroland/uc101/uc101.c
+ ---------------------------------
+ The driver is standard HW watchdog. Simple conversion is possible.
+
+
+ 39) board/mousse/m48t59y.c
+ --------------------------
+ Special watchdog driver. Dead code. To be removed.
+
+
+ 40) board/mvblue/mvblue.c
+ -------------------------
+ The driver is standard HW watchdog. Simple conversion is possible.
+
+
+ 41) board/netphone/netphone.c
+ -----------------------------
+ The driver is standard HW watchdog. Simple conversion is possible.
+
+
+ 42) board/netta/netta.c
+ -----------------------
+ The driver is standard HW watchdog. Simple conversion is possible.
+
+
+ 43) board/netta2/netta2.c
+ -------------------------
+ The driver is standard HW watchdog. Simple conversion is possible.
+
+
+ 44) board/omicron/calimain/calimain.c
+ -------------------------------------
+ Only function proxy call. Code cleanup needed.
+
+
+ 45) board/pcippc2/pcippc2.c
+ ---------------------------
+ The driver is standard HW watchdog. Simple conversion is possible.
+
+
+ 46) board/pcs440ep/pcs440ep.c
+ -----------------------------
+ The driver is standard HW watchdog. Simple conversion is possible.
+
+
+ 47) board/stx/stxxtc/stxxtc.c
+ -----------------------------
+ The driver is standard HW watchdog. Simple conversion is possible.
+
+
+ 48) board/ti/omap2420h4/omap2420h4.c
+ ------------------------------------
+ The driver is standard HW watchdog. Simple conversion is possible.
+
+
+ 49) board/ttcontrol/vision2/vision2.c
+ -------------------------------------
+ The driver is standard HW watchdog but namespace is polluted by
+ non-standard macros. Simple conversion is possible, code cleanup
+ needed.
+
+
+ 50) board/v38b/v38b.c
+ ---------------------
+ The driver is standard HW watchdog. Simple conversion is possible.
+
+
+ 51) board/ve8313/ve8313.c
+ -------------------------
+ The driver is standard HW watchdog. Simple conversion is possible.
+
+
+ 52) board/w7o/watchdog.c
+ ------------------------
+ The driver is standard HW watchdog. Simple conversion is possible.
* to be the base address for the chip, usually in the local
* peripheral bus.
*/
-#if (CONFIG_SYS_SYSTEMACE_WIDTH == 8)
+
+static u32 base = CONFIG_SYS_SYSTEMACE_BASE;
+static u32 width = CONFIG_SYS_SYSTEMACE_WIDTH;
+
+static void ace_writew(u16 val, unsigned off)
+{
+ if (width == 8) {
#if !defined(__BIG_ENDIAN)
-#define ace_readw(off) ((readb(CONFIG_SYS_SYSTEMACE_BASE+off)<<8) | \
- (readb(CONFIG_SYS_SYSTEMACE_BASE+off+1)))
-#define ace_writew(val, off) {writeb(val>>8, CONFIG_SYS_SYSTEMACE_BASE+off); \
- writeb(val, CONFIG_SYS_SYSTEMACE_BASE+off+1);}
+ writeb(val >> 8, base + off);
+ writeb(val, base + off + 1);
#else
-#define ace_readw(off) ((readb(CONFIG_SYS_SYSTEMACE_BASE+off)) | \
- (readb(CONFIG_SYS_SYSTEMACE_BASE+off+1)<<8))
-#define ace_writew(val, off) {writeb(val, CONFIG_SYS_SYSTEMACE_BASE+off); \
- writeb(val>>8, CONFIG_SYS_SYSTEMACE_BASE+off+1);}
+ writeb(val, base + off);
+ writeb(val >> 8, base + off + 1);
#endif
+ }
+ out16(base + off, val);
+}
+
+static u16 ace_readw(unsigned off)
+{
+ if (width == 8) {
+#if !defined(__BIG_ENDIAN)
+ return (readb(base + off) << 8) | readb(base + off + 1);
#else
-#define ace_readw(off) (in16(CONFIG_SYS_SYSTEMACE_BASE+off))
-#define ace_writew(val, off) (out16(CONFIG_SYS_SYSTEMACE_BASE+off,val))
+ return readb(base + off) | (readb(base + off + 1) << 8);
#endif
+ }
-/* */
+ return in16(base + off);
+}
static unsigned long systemace_read(int dev, unsigned long start,
unsigned long blkcnt, void *buffer);
/*
* Ensure the correct bus mode (8/16 bits) gets enabled
*/
- ace_writew(CONFIG_SYS_SYSTEMACE_WIDTH == 8 ? 0 : 0x0001, 0);
+ ace_writew(width == 8 ? 0 : 0x0001, 0);
init_part(&systemace_dev);
--- /dev/null
+#
+# Copyright (C) 2012 Samsung Electronics
+# Lukasz Majewski <l.majewski@samsung.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)libdfu.o
+
+COBJS-$(CONFIG_DFU_FUNCTION) += dfu.o
+COBJS-$(CONFIG_DFU_MMC) += dfu_mmc.o
+
+SRCS := $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * dfu.c -- DFU back-end routines
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ * author: Lukasz Majewski <l.majewski@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <fat.h>
+#include <dfu.h>
+#include <linux/list.h>
+#include <linux/compiler.h>
+
+static LIST_HEAD(dfu_list);
+static int dfu_alt_num;
+
+static int dfu_find_alt_num(const char *s)
+{
+ int i = 0;
+
+ for (; *s; s++)
+ if (*s == ';')
+ i++;
+
+ return ++i;
+}
+
+static unsigned char __aligned(CONFIG_SYS_CACHELINE_SIZE)
+ dfu_buf[DFU_DATA_BUF_SIZE];
+
+int dfu_write(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num)
+{
+ static unsigned char *i_buf;
+ static int i_blk_seq_num;
+ long w_size = 0;
+ int ret = 0;
+
+ debug("%s: name: %s buf: 0x%p size: 0x%x p_num: 0x%x i_buf: 0x%p\n",
+ __func__, dfu->name, buf, size, blk_seq_num, i_buf);
+
+ if (blk_seq_num == 0) {
+ i_buf = dfu_buf;
+ i_blk_seq_num = 0;
+ }
+
+ if (i_blk_seq_num++ != blk_seq_num) {
+ printf("%s: Wrong sequence number! [%d] [%d]\n",
+ __func__, i_blk_seq_num, blk_seq_num);
+ return -1;
+ }
+
+ memcpy(i_buf, buf, size);
+ i_buf += size;
+
+ if (size == 0) {
+ /* Integrity check (if needed) */
+ debug("%s: %s %d [B] CRC32: 0x%x\n", __func__, dfu->name,
+ i_buf - dfu_buf, crc32(0, dfu_buf, i_buf - dfu_buf));
+
+ w_size = i_buf - dfu_buf;
+ ret = dfu->write_medium(dfu, dfu_buf, &w_size);
+ if (ret)
+ debug("%s: Write error!\n", __func__);
+
+ i_blk_seq_num = 0;
+ i_buf = NULL;
+ return ret;
+ }
+
+ return ret;
+}
+
+int dfu_read(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num)
+{
+ static unsigned char *i_buf;
+ static int i_blk_seq_num;
+ static long r_size;
+ static u32 crc;
+ int ret = 0;
+
+ debug("%s: name: %s buf: 0x%p size: 0x%x p_num: 0x%x i_buf: 0x%p\n",
+ __func__, dfu->name, buf, size, blk_seq_num, i_buf);
+
+ if (blk_seq_num == 0) {
+ i_buf = dfu_buf;
+ ret = dfu->read_medium(dfu, i_buf, &r_size);
+ debug("%s: %s %ld [B]\n", __func__, dfu->name, r_size);
+ i_blk_seq_num = 0;
+ /* Integrity check (if needed) */
+ crc = crc32(0, dfu_buf, r_size);
+ }
+
+ if (i_blk_seq_num++ != blk_seq_num) {
+ printf("%s: Wrong sequence number! [%d] [%d]\n",
+ __func__, i_blk_seq_num, blk_seq_num);
+ return -1;
+ }
+
+ if (r_size >= size) {
+ memcpy(buf, i_buf, size);
+ i_buf += size;
+ r_size -= size;
+ return size;
+ } else {
+ memcpy(buf, i_buf, r_size);
+ i_buf += r_size;
+ debug("%s: %s CRC32: 0x%x\n", __func__, dfu->name, crc);
+ puts("UPLOAD ... done\nCtrl+C to exit ...\n");
+
+ i_buf = NULL;
+ i_blk_seq_num = 0;
+ crc = 0;
+ return r_size;
+ }
+ return ret;
+}
+
+static int dfu_fill_entity(struct dfu_entity *dfu, char *s, int alt,
+ char *interface, int num)
+{
+ char *st;
+
+ debug("%s: %s interface: %s num: %d\n", __func__, s, interface, num);
+ st = strsep(&s, " ");
+ strcpy(dfu->name, st);
+
+ dfu->dev_num = num;
+ dfu->alt = alt;
+
+ /* Specific for mmc device */
+ if (strcmp(interface, "mmc") == 0) {
+ if (dfu_fill_entity_mmc(dfu, s))
+ return -1;
+ } else {
+ printf("%s: Device %s not (yet) supported!\n",
+ __func__, interface);
+ return -1;
+ }
+
+ return 0;
+}
+
+void dfu_free_entities(void)
+{
+ struct dfu_entity *dfu, *p, *t = NULL;
+
+ list_for_each_entry_safe_reverse(dfu, p, &dfu_list, list) {
+ list_del(&dfu->list);
+ t = dfu;
+ }
+ if (t)
+ free(t);
+ INIT_LIST_HEAD(&dfu_list);
+}
+
+int dfu_config_entities(char *env, char *interface, int num)
+{
+ struct dfu_entity *dfu;
+ int i, ret;
+ char *s;
+
+ dfu_alt_num = dfu_find_alt_num(env);
+ debug("%s: dfu_alt_num=%d\n", __func__, dfu_alt_num);
+
+ dfu = calloc(sizeof(*dfu), dfu_alt_num);
+ if (!dfu)
+ return -1;
+ for (i = 0; i < dfu_alt_num; i++) {
+
+ s = strsep(&env, ";");
+ ret = dfu_fill_entity(&dfu[i], s, i, interface, num);
+ if (ret)
+ return -1;
+
+ list_add_tail(&dfu[i].list, &dfu_list);
+ }
+
+ return 0;
+}
+
+const char *dfu_get_dev_type(enum dfu_device_type t)
+{
+ const char *dev_t[] = {NULL, "eMMC", "OneNAND", "NAND" };
+ return dev_t[t];
+}
+
+const char *dfu_get_layout(enum dfu_layout l)
+{
+ const char *dfu_layout[] = {NULL, "RAW_ADDR", "FAT", "EXT2",
+ "EXT3", "EXT4" };
+ return dfu_layout[l];
+}
+
+void dfu_show_entities(void)
+{
+ struct dfu_entity *dfu;
+
+ puts("DFU alt settings list:\n");
+
+ list_for_each_entry(dfu, &dfu_list, list) {
+ printf("dev: %s alt: %d name: %s layout: %s\n",
+ dfu_get_dev_type(dfu->dev_type), dfu->alt,
+ dfu->name, dfu_get_layout(dfu->layout));
+ }
+}
+
+int dfu_get_alt_number(void)
+{
+ return dfu_alt_num;
+}
+
+struct dfu_entity *dfu_get_entity(int alt)
+{
+ struct dfu_entity *dfu;
+
+ list_for_each_entry(dfu, &dfu_list, list) {
+ if (dfu->alt == alt)
+ return dfu;
+ }
+
+ return NULL;
+}
--- /dev/null
+/*
+ * dfu.c -- DFU back-end routines
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ * author: Lukasz Majewski <l.majewski@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <dfu.h>
+
+enum dfu_mmc_op {
+ DFU_OP_READ = 1,
+ DFU_OP_WRITE,
+};
+
+static int mmc_block_op(enum dfu_mmc_op op, struct dfu_entity *dfu,
+ void *buf, long *len)
+{
+ char cmd_buf[DFU_CMD_BUF_SIZE];
+
+ sprintf(cmd_buf, "mmc %s 0x%x %x %x",
+ op == DFU_OP_READ ? "read" : "write",
+ (unsigned int) buf,
+ dfu->data.mmc.lba_start,
+ dfu->data.mmc.lba_size);
+
+ if (op == DFU_OP_READ)
+ *len = dfu->data.mmc.lba_blk_size * dfu->data.mmc.lba_size;
+
+ debug("%s: %s 0x%p\n", __func__, cmd_buf, cmd_buf);
+ return run_command(cmd_buf, 0);
+}
+
+static inline int mmc_block_write(struct dfu_entity *dfu, void *buf, long *len)
+{
+ return mmc_block_op(DFU_OP_WRITE, dfu, buf, len);
+}
+
+static inline int mmc_block_read(struct dfu_entity *dfu, void *buf, long *len)
+{
+ return mmc_block_op(DFU_OP_READ, dfu, buf, len);
+}
+
+static int mmc_file_op(enum dfu_mmc_op op, struct dfu_entity *dfu,
+ void *buf, long *len)
+{
+ char cmd_buf[DFU_CMD_BUF_SIZE];
+ char *str_env;
+ int ret;
+
+ switch (dfu->layout) {
+ case DFU_FS_FAT:
+ sprintf(cmd_buf, "fat%s mmc %d:%d 0x%x %s %lx",
+ op == DFU_OP_READ ? "load" : "write",
+ dfu->data.mmc.dev, dfu->data.mmc.part,
+ (unsigned int) buf, dfu->name, *len);
+ break;
+ case DFU_FS_EXT4:
+ sprintf(cmd_buf, "ext4%s mmc %d:%d /%s 0x%x %ld",
+ op == DFU_OP_READ ? "load" : "write",
+ dfu->data.mmc.dev, dfu->data.mmc.part,
+ dfu->name, (unsigned int) buf, *len);
+ break;
+ default:
+ printf("%s: Layout (%s) not (yet) supported!\n", __func__,
+ dfu_get_layout(dfu->layout));
+ }
+
+ debug("%s: %s 0x%p\n", __func__, cmd_buf, cmd_buf);
+
+ ret = run_command(cmd_buf, 0);
+ if (ret) {
+ puts("dfu: Read error!\n");
+ return ret;
+ }
+
+ if (dfu->layout != DFU_RAW_ADDR && op == DFU_OP_READ) {
+ str_env = getenv("filesize");
+ if (str_env == NULL) {
+ puts("dfu: Wrong file size!\n");
+ return -1;
+ }
+ *len = simple_strtoul(str_env, NULL, 16);
+ }
+
+ return ret;
+}
+
+static inline int mmc_file_write(struct dfu_entity *dfu, void *buf, long *len)
+{
+ return mmc_file_op(DFU_OP_WRITE, dfu, buf, len);
+}
+
+static inline int mmc_file_read(struct dfu_entity *dfu, void *buf, long *len)
+{
+ return mmc_file_op(DFU_OP_READ, dfu, buf, len);
+}
+
+int dfu_write_medium_mmc(struct dfu_entity *dfu, void *buf, long *len)
+{
+ int ret = -1;
+
+ switch (dfu->layout) {
+ case DFU_RAW_ADDR:
+ ret = mmc_block_write(dfu, buf, len);
+ break;
+ case DFU_FS_FAT:
+ case DFU_FS_EXT4:
+ ret = mmc_file_write(dfu, buf, len);
+ break;
+ default:
+ printf("%s: Layout (%s) not (yet) supported!\n", __func__,
+ dfu_get_layout(dfu->layout));
+ }
+
+ return ret;
+}
+
+int dfu_read_medium_mmc(struct dfu_entity *dfu, void *buf, long *len)
+{
+ int ret = -1;
+
+ switch (dfu->layout) {
+ case DFU_RAW_ADDR:
+ ret = mmc_block_read(dfu, buf, len);
+ break;
+ case DFU_FS_FAT:
+ case DFU_FS_EXT4:
+ ret = mmc_file_read(dfu, buf, len);
+ break;
+ default:
+ printf("%s: Layout (%s) not (yet) supported!\n", __func__,
+ dfu_get_layout(dfu->layout));
+ }
+
+ return ret;
+}
+
+int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *s)
+{
+ char *st;
+
+ dfu->dev_type = DFU_DEV_MMC;
+ st = strsep(&s, " ");
+ if (!strcmp(st, "mmc")) {
+ dfu->layout = DFU_RAW_ADDR;
+ dfu->data.mmc.lba_start = simple_strtoul(s, &s, 16);
+ dfu->data.mmc.lba_size = simple_strtoul(++s, &s, 16);
+ dfu->data.mmc.lba_blk_size = get_mmc_blk_size(dfu->dev_num);
+ } else if (!strcmp(st, "fat")) {
+ dfu->layout = DFU_FS_FAT;
+ } else if (!strcmp(st, "ext4")) {
+ dfu->layout = DFU_FS_EXT4;
+ } else {
+ printf("%s: Memory layout (%s) not supported!\n", __func__, st);
+ }
+
+ if (dfu->layout == DFU_FS_EXT4 || dfu->layout == DFU_FS_FAT) {
+ dfu->data.mmc.dev = simple_strtoul(s, &s, 10);
+ dfu->data.mmc.part = simple_strtoul(++s, &s, 10);
+ }
+
+ dfu->read_medium = dfu_read_medium_mmc;
+ dfu->write_medium = dfu_write_medium_mmc;
+
+ return 0;
+}
return -1;
}
+#if I2C_BUS_MAX == 4
+ if (bus == 3)
+ i2c_base = (struct i2c *)I2C_BASE4;
+ else
+ if (bus == 2)
+ i2c_base = (struct i2c *)I2C_BASE3;
+ else
+#endif
#if I2C_BUS_MAX == 3
if (bus == 2)
i2c_base = (struct i2c *)I2C_BASE3;
* MA 02111-1307 USA
*/
+#include <common.h>
#include <fdtdec.h>
#include <key_matrix.h>
#include <malloc.h>
debug("CMD%d time out\n", cmd->cmdidx);
return TIMEOUT;
} else if ((hoststatus & SDI_STA_CCRCFAIL) &&
- (cmd->flags & MMC_RSP_CRC)) {
+ (cmd->resp_type & MMC_RSP_CRC)) {
printf("CMD%d CRC error\n", cmd->cmdidx);
return -EILSEQ;
}
printf("CMD_SEND:%d\n", cmd->cmdidx);
printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
- printf("\t\tFLAG\t\t\t %d\n", cmd->flags);
ret = mmc->send_cmd(mmc, cmd, data);
switch (cmd->resp_type) {
case MMC_RSP_NONE:
cmd.resp_type = MMC_RSP_R1;
if (!mmc_host_is_spi(mmc))
cmd.cmdarg = mmc->rca << 16;
- cmd.flags = 0;
do {
err = mmc_send_cmd(mmc, &cmd, NULL);
status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9;
printf("CURR STATE:%d\n", status);
#endif
- if (!timeout) {
+ if (timeout <= 0) {
printf("Timeout waiting card ready\n");
return TIMEOUT;
}
cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
cmd.resp_type = MMC_RSP_R1;
cmd.cmdarg = len;
- cmd.flags = 0;
return mmc_send_cmd(mmc, &cmd, NULL);
}
cmd.cmdidx = start_cmd;
cmd.cmdarg = start;
cmd.resp_type = MMC_RSP_R1;
- cmd.flags = 0;
err = mmc_send_cmd(mmc, &cmd, NULL);
if (err)
cmd.cmdarg = start * mmc->write_bl_len;
cmd.resp_type = MMC_RSP_R1;
- cmd.flags = 0;
data.src = src;
data.blocks = blkcnt;
cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
cmd.cmdarg = 0;
cmd.resp_type = MMC_RSP_R1b;
- cmd.flags = 0;
if (mmc_send_cmd(mmc, &cmd, NULL)) {
printf("mmc fail to send stop cmd\n");
return 0;
cmd.cmdarg = start * mmc->read_bl_len;
cmd.resp_type = MMC_RSP_R1;
- cmd.flags = 0;
data.dest = dst;
data.blocks = blkcnt;
cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
cmd.cmdarg = 0;
cmd.resp_type = MMC_RSP_R1b;
- cmd.flags = 0;
if (mmc_send_cmd(mmc, &cmd, NULL)) {
printf("mmc fail to send stop cmd\n");
return 0;
cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
cmd.cmdarg = 0;
cmd.resp_type = MMC_RSP_NONE;
- cmd.flags = 0;
err = mmc_send_cmd(mmc, &cmd, NULL);
cmd.cmdidx = MMC_CMD_APP_CMD;
cmd.resp_type = MMC_RSP_R1;
cmd.cmdarg = 0;
- cmd.flags = 0;
err = mmc_send_cmd(mmc, &cmd, NULL);
cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
cmd.resp_type = MMC_RSP_R3;
cmd.cmdarg = 0;
- cmd.flags = 0;
err = mmc_send_cmd(mmc, &cmd, NULL);
cmd.cmdidx = MMC_CMD_SEND_OP_COND;
cmd.resp_type = MMC_RSP_R3;
cmd.cmdarg = 0;
- cmd.flags = 0;
err = mmc_send_cmd(mmc, &cmd, NULL);
if (mmc->host_caps & MMC_MODE_HC)
cmd.cmdarg |= OCR_HCS;
- cmd.flags = 0;
-
err = mmc_send_cmd(mmc, &cmd, NULL);
if (err)
cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
cmd.resp_type = MMC_RSP_R3;
cmd.cmdarg = 0;
- cmd.flags = 0;
err = mmc_send_cmd(mmc, &cmd, NULL);
}
-int mmc_send_ext_csd(struct mmc *mmc, char *ext_csd)
+int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
{
struct mmc_cmd cmd;
struct mmc_data data;
cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
cmd.resp_type = MMC_RSP_R1;
cmd.cmdarg = 0;
- cmd.flags = 0;
- data.dest = ext_csd;
+ data.dest = (char *)ext_csd;
data.blocks = 1;
data.blocksize = 512;
data.flags = MMC_DATA_READ;
cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
(index << 16) |
(value << 8);
- cmd.flags = 0;
ret = mmc_send_cmd(mmc, &cmd, NULL);
int mmc_change_freq(struct mmc *mmc)
{
- ALLOC_CACHE_ALIGN_BUFFER(char, ext_csd, 512);
+ ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, 512);
char cardtype;
int err;
cmd.cmdarg = (mode << 31) | 0xffffff;
cmd.cmdarg &= ~(0xf << (group * 4));
cmd.cmdarg |= value << (group * 4);
- cmd.flags = 0;
data.dest = (char *)resp;
data.blocksize = 64;
cmd.cmdidx = MMC_CMD_APP_CMD;
cmd.resp_type = MMC_RSP_R1;
cmd.cmdarg = mmc->rca << 16;
- cmd.flags = 0;
err = mmc_send_cmd(mmc, &cmd, NULL);
cmd.cmdidx = SD_CMD_APP_SEND_SCR;
cmd.resp_type = MMC_RSP_R1;
cmd.cmdarg = 0;
- cmd.flags = 0;
timeout = 3;
uint mult, freq;
u64 cmult, csize, capacity;
struct mmc_cmd cmd;
- ALLOC_CACHE_ALIGN_BUFFER(char, ext_csd, 512);
- ALLOC_CACHE_ALIGN_BUFFER(char, test_csd, 512);
+ ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, 512);
+ ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, 512);
int timeout = 1000;
#ifdef CONFIG_MMC_SPI_CRC_ON
cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
cmd.resp_type = MMC_RSP_R1;
cmd.cmdarg = 1;
- cmd.flags = 0;
err = mmc_send_cmd(mmc, &cmd, NULL);
if (err)
MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
cmd.resp_type = MMC_RSP_R2;
cmd.cmdarg = 0;
- cmd.flags = 0;
err = mmc_send_cmd(mmc, &cmd, NULL);
cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
cmd.cmdarg = mmc->rca << 16;
cmd.resp_type = MMC_RSP_R6;
- cmd.flags = 0;
err = mmc_send_cmd(mmc, &cmd, NULL);
cmd.cmdidx = MMC_CMD_SEND_CSD;
cmd.resp_type = MMC_RSP_R2;
cmd.cmdarg = mmc->rca << 16;
- cmd.flags = 0;
err = mmc_send_cmd(mmc, &cmd, NULL);
cmd.cmdidx = MMC_CMD_SELECT_CARD;
cmd.resp_type = MMC_RSP_R1;
cmd.cmdarg = mmc->rca << 16;
- cmd.flags = 0;
err = mmc_send_cmd(mmc, &cmd, NULL);
if (err)
cmd.cmdidx = MMC_CMD_APP_CMD;
cmd.resp_type = MMC_RSP_R1;
cmd.cmdarg = mmc->rca << 16;
- cmd.flags = 0;
err = mmc_send_cmd(mmc, &cmd, NULL);
if (err)
cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
cmd.resp_type = MMC_RSP_R1;
cmd.cmdarg = 2;
- cmd.flags = 0;
err = mmc_send_cmd(mmc, &cmd, NULL);
if (err)
return err;
(mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff);
sprintf(mmc->block_dev.revision, "%d.%d", mmc->cid[2] >> 28,
(mmc->cid[2] >> 24) & 0xf);
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
init_part(&mmc->block_dev);
+#endif
return 0;
}
/* We set the bit if the host supports voltages between 2.7 and 3.6 V */
cmd.cmdarg = ((mmc->voltages & 0xff8000) != 0) << 8 | 0xaa;
cmd.resp_type = MMC_RSP_R7;
- cmd.flags = 0;
err = mmc_send_cmd(mmc, &cmd, NULL);
block_dev_desc_t *mmc_get_dev(int dev)
{
struct mmc *mmc = find_mmc_device(dev);
- if (!mmc)
+ if (!mmc || mmc_init(mmc))
return NULL;
- mmc_init(mmc);
return &mmc->block_dev;
}
#endif
int ret;
/* The card can send a "busy" response */
- if (cmd->flags & MMC_RSP_BUSY)
+ if (cmd->resp_type & MMC_RSP_BUSY)
cmdat |= MMC_CMDAT_BUSY;
/* Inform the controller about response type */
/* The command response didn't arrive */
if (stat & MMC_STAT_TIME_OUT_RESPONSE)
return -ETIMEDOUT;
- else if (stat & MMC_STAT_RES_CRC_ERROR && cmd->flags & MMC_RSP_CRC) {
+ else if (stat & MMC_STAT_RES_CRC_ERROR
+ && cmd->resp_type & MMC_RSP_CRC) {
#ifdef PXAMMC_CRC_SKIP
- if (cmd->flags & MMC_RSP_136 && cmd->response[0] & (1 << 31))
+ if (cmd->resp_type & MMC_RSP_136
+ && cmd->response[0] & (1 << 31))
printf("Ignoring CRC, this may be dangerous!\n");
else
#endif
#include <malloc.h>
#include <sdhci.h>
#include <asm/arch/mmc.h>
+#include <asm/arch/clk.h>
static char *S5P_NAME = "SAMSUNG SDHCI";
static void s5p_sdhci_set_control_reg(struct sdhci_host *host)
* 00 = Delay3 (inverter delay)
* 10 = Delay4 (inverter delay + 2ns)
*/
- val = SDHCI_CTRL3_FCSEL3 | SDHCI_CTRL3_FCSEL1;
+ val = SDHCI_CTRL3_FCSEL0 | SDHCI_CTRL3_FCSEL1;
sdhci_writel(host, val, SDHCI_CONTROL3);
/*
sdhci_writel(host, ctrl, SDHCI_CONTROL2);
}
-int s5p_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks)
+int s5p_sdhci_init(u32 regbase, int index, int bus_width)
{
struct sdhci_host *host = NULL;
host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
host->name = S5P_NAME;
host->ioaddr = (void *)regbase;
- host->quirks = quirks;
- host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE;
+ host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE |
+ SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR;
host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
- if (quirks & SDHCI_QUIRK_REG32_RW)
- host->version = sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
- else
- host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
+ host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
host->set_control_reg = &s5p_sdhci_set_control_reg;
+ host->set_clock = set_mmc_clk;
+ host->index = index;
host->host_caps = MMC_MODE_HC;
- add_sdhci(host, max_clk, min_clk);
+ add_sdhci(host, 52000000, 400000);
return 0;
}
if (clock == 0)
return 0;
- if (host->version >= SDHCI_SPEC_300) {
+ if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) {
/* Version 3.00 divisors must be a multiple of 2. */
if (mmc->f_max <= clock)
div = 1;
}
div >>= 1;
+ if (host->set_clock)
+ host->set_clock(host->index, div);
+
clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
<< SDHCI_DIVIDER_HI_SHIFT;
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
if (mmc->bus_width == 8) {
ctrl &= ~SDHCI_CTRL_4BITBUS;
- if (host->version >= SDHCI_SPEC_300)
+ if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300)
ctrl |= SDHCI_CTRL_8BITBUS;
} else {
- if (host->version >= SDHCI_SPEC_300)
+ if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300)
ctrl &= ~SDHCI_CTRL_8BITBUS;
if (mmc->bus_width == 4)
ctrl |= SDHCI_CTRL_4BITBUS;
}
}
+ sdhci_set_power(host, fls(mmc->voltages) - 1);
+
+ if (host->quirks & SDHCI_QUIRK_NO_CD) {
+ unsigned int status;
+
+ sdhci_writel(host, SDHCI_CTRL_CD_TEST_INS | SDHCI_CTRL_CD_TEST,
+ SDHCI_HOST_CONTROL);
+
+ status = sdhci_readl(host, SDHCI_PRESENT_STATE);
+ while ((!(status & SDHCI_CARD_PRESENT)) ||
+ (!(status & SDHCI_CARD_STATE_STABLE)) ||
+ (!(status & SDHCI_CARD_DETECT_PIN_LEVEL)))
+ status = sdhci_readl(host, SDHCI_PRESENT_STATE);
+ }
+
/* Eable all state */
sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_ENABLE);
sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_SIGNAL_ENABLE);
- sdhci_set_power(host, fls(mmc->voltages) - 1);
-
return 0;
}
if (max_clk)
mmc->f_max = max_clk;
else {
- if (host->version >= SDHCI_SPEC_300)
+ if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300)
mmc->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK)
>> SDHCI_CLOCK_BASE_SHIFT;
else
if (min_clk)
mmc->f_min = min_clk;
else {
- if (host->version >= SDHCI_SPEC_300)
+ if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300)
mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_300;
else
mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_200;
mmc->f_max = CLKDEV_EMMC_DATA;
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT |
- MMC_MODE_8BIT;
+ MMC_MODE_8BIT | MMC_MODE_HC;
memcpy(mmc->name, DRIVER_NAME, sizeof(DRIVER_NAME));
mmc->send_cmd = sh_mmcif_request;
mmc->set_ios = sh_mmcif_set_ios;
for (sect = s_first; sect <= s_last; sect++) {
+ if (ctrlc()) {
+ printf("\n");
+ return 1;
+ }
+
if (info->protect[sect] == 0) { /* not protected */
+#ifdef CONFIG_SYS_FLASH_CHECK_BLANK_BEFORE_ERASE
+ int k;
+ int size;
+ int erased;
+ u32 *flash;
+
+ /*
+ * Check if whole sector is erased
+ */
+ size = flash_sector_size(info, sect);
+ erased = 1;
+ flash = (u32 *)info->start[sect];
+ /* divide by 4 for longword access */
+ size = size >> 2;
+ for (k = 0; k < size; k++) {
+ if (flash_read32(flash++) != 0xffffffff) {
+ erased = 0;
+ break;
+ }
+ }
+ if (erased) {
+ if (flash_verbose)
+ putc(',');
+ continue;
+ }
+#endif
switch (info->vendor) {
case CFI_CMDSET_INTEL_PROG_REGIONS:
case CFI_CMDSET_INTEL_STANDARD:
src += i;
cnt -= i;
FLASH_SHOW_PROGRESS(scale, dots, digit, i);
+ /* Only check every once in a while */
+ if ((cnt & 0xFFFF) < buffered_size && ctrlc())
+ return ERR_ABORTED;
}
#else
while (cnt >= info->portwidth) {
wp += info->portwidth;
cnt -= info->portwidth;
FLASH_SHOW_PROGRESS(scale, dots, digit, info->portwidth);
+ /* Only check every once in a while */
+ if ((cnt & 0xFFFF) < info->portwidth && ctrlc())
+ return ERR_ABORTED;
}
#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35)
#include <asm/arch/imx-regs.h>
#endif
+#include <fsl_nfc.h>
#define DRIVER_NAME "mxc_nand"
-/*
- * TODO: Use same register defs here as nand_spl mxc nand driver.
- */
-/*
- * Register map and bit definitions for the Freescale NAND Flash Controller
- * present in various i.MX devices.
- *
- * MX31 and MX27 have version 1 which has
- * 4 512 byte main buffers and
- * 4 16 byte spare buffers
- * to support up to 2K byte pagesize nand.
- * Reading or writing a 2K page requires 4 FDI/FDO cycles.
- *
- * MX25 has version 1.1 which has
- * 8 512 byte main buffers and
- * 8 64 byte spare buffers
- * to support up to 4K byte pagesize nand.
- * Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle.
- * Also some of registers are moved and/or changed meaning as seen below.
- */
-#if defined(CONFIG_MX31) || defined(CONFIG_MX27)
-#define MXC_NFC_V1
-#elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
-#define MXC_NFC_V1_1
-#else
-#warning "MXC NFC version not defined"
-#endif
-
-#if defined(MXC_NFC_V1)
-#define NAND_MXC_NR_BUFS 4
-#define NAND_MXC_SPARE_BUF_SIZE 16
-#define NAND_MXC_REG_OFFSET 0xe00
-#define is_mxc_nfc_11() 0
-#elif defined(MXC_NFC_V1_1)
-#define NAND_MXC_NR_BUFS 8
-#define NAND_MXC_SPARE_BUF_SIZE 64
-#define NAND_MXC_REG_OFFSET 0x1e00
-#define is_mxc_nfc_11() 1
-#else
-#error "define CONFIG_NAND_MXC_VXXX to use mtd mxc nand driver"
-#endif
-struct nfc_regs {
- uint8_t main_area[NAND_MXC_NR_BUFS][0x200];
- uint8_t spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE];
- /*
- * reserved size is offset of nfc registers
- * minus total main and spare sizes
- */
- uint8_t reserved1[NAND_MXC_REG_OFFSET
- - NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)];
-#if defined(MXC_NFC_V1)
- uint16_t nfc_buf_size;
- uint16_t reserved2;
- uint16_t nfc_buf_addr;
- uint16_t nfc_flash_addr;
- uint16_t nfc_flash_cmd;
- uint16_t nfc_config;
- uint16_t nfc_ecc_status_result;
- uint16_t nfc_rsltmain_area;
- uint16_t nfc_rsltspare_area;
- uint16_t nfc_wrprot;
- uint16_t nfc_unlockstart_blkaddr;
- uint16_t nfc_unlockend_blkaddr;
- uint16_t nfc_nf_wrprst;
- uint16_t nfc_config1;
- uint16_t nfc_config2;
-#elif defined(MXC_NFC_V1_1)
- uint16_t reserved2[2];
- uint16_t nfc_buf_addr;
- uint16_t nfc_flash_addr;
- uint16_t nfc_flash_cmd;
- uint16_t nfc_config;
- uint16_t nfc_ecc_status_result;
- uint16_t nfc_ecc_status_result2;
- uint16_t nfc_spare_area_size;
- uint16_t nfc_wrprot;
- uint16_t reserved3[2];
- uint16_t nfc_nf_wrprst;
- uint16_t nfc_config1;
- uint16_t nfc_config2;
- uint16_t reserved4;
- uint16_t nfc_unlockstart_blkaddr;
- uint16_t nfc_unlockend_blkaddr;
- uint16_t nfc_unlockstart_blkaddr1;
- uint16_t nfc_unlockend_blkaddr1;
- uint16_t nfc_unlockstart_blkaddr2;
- uint16_t nfc_unlockend_blkaddr2;
- uint16_t nfc_unlockstart_blkaddr3;
- uint16_t nfc_unlockend_blkaddr3;
-#endif
-};
-
-/*
- * Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register
- * for Command operation
- */
-#define NFC_CMD 0x1
-
-/*
- * Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register
- * for Address operation
- */
-#define NFC_ADDR 0x2
-
-/*
- * Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register
- * for Input operation
- */
-#define NFC_INPUT 0x4
-
-/*
- * Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register
- * for Data Output operation
- */
-#define NFC_OUTPUT 0x8
-
-/*
- * Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register
- * for Read ID operation
- */
-#define NFC_ID 0x10
-
-/*
- * Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register
- * for Read Status operation
- */
-#define NFC_STATUS 0x20
-
-/*
- * Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read
- * Status operation
- */
-#define NFC_INT 0x8000
-
-#ifdef MXC_NFC_V1_1
-#define NFC_4_8N_ECC (1 << 0)
-#else
-#define NFC_4_8N_ECC 0
-#endif
-#define NFC_SP_EN (1 << 2)
-#define NFC_ECC_EN (1 << 3)
-#define NFC_BIG (1 << 5)
-#define NFC_RST (1 << 6)
-#define NFC_CE (1 << 7)
-#define NFC_ONE_CYCLE (1 << 8)
-
typedef enum {false, true} bool;
struct mxc_nand_host {
- struct mtd_info mtd;
- struct nand_chip *nand;
-
- struct nfc_regs __iomem *regs;
- int spare_only;
- int status_request;
- int pagesize_2k;
- int clk_act;
- uint16_t col_addr;
- unsigned int page_addr;
+ struct mtd_info mtd;
+ struct nand_chip *nand;
+
+ struct fsl_nfc_regs __iomem *regs;
+ int spare_only;
+ int status_request;
+ int pagesize_2k;
+ int clk_act;
+ uint16_t col_addr;
+ unsigned int page_addr;
};
static struct mxc_nand_host mxc_host;
.oobfree = { {2, 4}, {11, 11}, {27, 11}, {43, 11}, {59, 5} },
};
#endif
-#elif defined(MXC_NFC_V1_1)
+#elif defined(MXC_NFC_V2_1)
#ifndef CONFIG_SYS_NAND_LARGEPAGE
static struct nand_ecclayout nand_hw_eccoob = {
.eccbytes = 9,
#elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
static int is_16bit_nand(void)
{
- struct ccm_regs *ccm =
- (struct ccm_regs *)IMX_CCM_BASE;
+ struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
if (readl(&ccm->rcsr) & CCM_RCSR_NF_16BIT_SEL)
return 1;
uint32_t tmp;
while (max_retries-- > 0) {
- if (readw(&host->regs->nfc_config2) & NFC_INT) {
- tmp = readw(&host->regs->nfc_config2);
+ if (readw(&host->regs->config2) & NFC_INT) {
+ tmp = readw(&host->regs->config2);
tmp &= ~NFC_INT;
- writew(tmp, &host->regs->nfc_config2);
+ writew(tmp, &host->regs->config2);
break;
}
udelay(1);
{
MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd);
- writew(cmd, &host->regs->nfc_flash_cmd);
- writew(NFC_CMD, &host->regs->nfc_config2);
+ writew(cmd, &host->regs->flash_cmd);
+ writew(NFC_CMD, &host->regs->config2);
/* Wait for operation to complete */
wait_op_done(host, TROP_US_DELAY, cmd);
{
MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x)\n", addr);
- writew(addr, &host->regs->nfc_flash_addr);
- writew(NFC_ADDR, &host->regs->nfc_config2);
+ writew(addr, &host->regs->flash_addr);
+ writew(NFC_ADDR, &host->regs->config2);
/* Wait for operation to complete */
wait_op_done(host, TROP_US_DELAY, addr);
if (spare_only)
MTDDEBUG(MTD_DEBUG_LEVEL1, "send_prog_page (%d)\n", spare_only);
- if (is_mxc_nfc_11()) {
+ if (is_mxc_nfc_21()) {
int i;
/*
* The controller copies the 64 bytes of spare data from
}
}
- writew(buf_id, &host->regs->nfc_buf_addr);
+ writew(buf_id, &host->regs->buf_addr);
/* Configure spare or page+spare access */
if (!host->pagesize_2k) {
- uint16_t config1 = readw(&host->regs->nfc_config1);
+ uint16_t config1 = readw(&host->regs->config1);
if (spare_only)
config1 |= NFC_SP_EN;
else
- config1 &= ~(NFC_SP_EN);
- writew(config1, &host->regs->nfc_config1);
+ config1 &= ~NFC_SP_EN;
+ writew(config1, &host->regs->config1);
}
- writew(NFC_INPUT, &host->regs->nfc_config2);
+ writew(NFC_INPUT, &host->regs->config2);
/* Wait for operation to complete */
wait_op_done(host, TROP_US_DELAY, spare_only);
{
MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only);
- writew(buf_id, &host->regs->nfc_buf_addr);
+ writew(buf_id, &host->regs->buf_addr);
/* Configure spare or page+spare access */
if (!host->pagesize_2k) {
- uint32_t config1 = readw(&host->regs->nfc_config1);
+ uint32_t config1 = readw(&host->regs->config1);
if (spare_only)
config1 |= NFC_SP_EN;
else
config1 &= ~NFC_SP_EN;
- writew(config1, &host->regs->nfc_config1);
+ writew(config1, &host->regs->config1);
}
- writew(NFC_OUTPUT, &host->regs->nfc_config2);
+ writew(NFC_OUTPUT, &host->regs->config2);
/* Wait for operation to complete */
wait_op_done(host, TROP_US_DELAY, spare_only);
- if (is_mxc_nfc_11()) {
+ if (is_mxc_nfc_21()) {
int i;
/*
uint16_t tmp;
/* NANDFC buffer 0 is used for device ID output */
- writew(0x0, &host->regs->nfc_buf_addr);
+ writew(0x0, &host->regs->buf_addr);
/* Read ID into main buffer */
- tmp = readw(&host->regs->nfc_config1);
+ tmp = readw(&host->regs->config1);
tmp &= ~NFC_SP_EN;
- writew(tmp, &host->regs->nfc_config1);
+ writew(tmp, &host->regs->config1);
- writew(NFC_ID, &host->regs->nfc_config2);
+ writew(NFC_ID, &host->regs->config2);
/* Wait for operation to complete */
wait_op_done(host, TROP_US_DELAY, 0);
/* store the main area1 first word, later do recovery */
store = readl(main_buf);
/* NANDFC buffer 1 is used for device status */
- writew(1, &host->regs->nfc_buf_addr);
+ writew(1, &host->regs->buf_addr);
/* Read status into main buffer */
- tmp = readw(&host->regs->nfc_config1);
+ tmp = readw(&host->regs->config1);
tmp &= ~NFC_SP_EN;
- writew(tmp, &host->regs->nfc_config1);
+ writew(tmp, &host->regs->config1);
- writew(NFC_STATUS, &host->regs->nfc_config2);
+ writew(NFC_STATUS, &host->regs->config2);
/* Wait for operation to complete */
wait_op_done(host, TROP_US_DELAY, 0);
return 1;
}
-#ifdef CONFIG_MXC_NAND_HWECC
-static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
-{
- /*
- * If HW ECC is enabled, we turn it on during init. There is
- * no need to enable again here.
- */
-}
-
-#ifdef MXC_NFC_V1_1
static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on)
{
struct nand_chip *nand_chip = mtd->priv;
struct mxc_nand_host *host = nand_chip->priv;
- uint16_t tmp = readw(&host->regs->nfc_config1);
+ uint16_t tmp = readw(&host->regs->config1);
if (on)
tmp |= NFC_ECC_EN;
else
tmp &= ~NFC_ECC_EN;
- writew(tmp, &host->regs->nfc_config1);
+ writew(tmp, &host->regs->config1);
+}
+
+#ifdef CONFIG_MXC_NAND_HWECC
+static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
+{
+ /*
+ * If HW ECC is enabled, we turn it on during init. There is
+ * no need to enable again here.
+ */
}
+#ifdef MXC_NFC_V2_1
static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd,
struct nand_chip *chip,
int page, int sndcmd)
size = mtd->oobsize - (oob - chip->oob_poi);
if (size)
chip->read_buf(mtd, oob, size);
- _mxc_nand_enable_hwecc(mtd, 0);
+ _mxc_nand_enable_hwecc(mtd, 1);
return 0;
}
{
struct nand_chip *nand_chip = mtd->priv;
struct mxc_nand_host *host = nand_chip->priv;
- uint16_t ecc_status = readw(&host->regs->nfc_ecc_status_result);
+ uint32_t ecc_status = readl(&host->regs->ecc_status_result);
int subpages = mtd->writesize / nand_chip->subpagesize;
int pg2blk_shift = nand_chip->phys_erase_shift -
nand_chip->page_shift;
#define mxc_nand_write_page_syndrome NULL
#define mxc_nand_write_page_raw_syndrome NULL
#define mxc_nand_write_oob_syndrome NULL
-#define mxc_nfc_11_nand_correct_data NULL
static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
u_char *read_ecc, u_char *calc_ecc)
* additional correction. 2-Bit errors cannot be corrected by
* HW ECC, so we need to return failure
*/
- uint16_t ecc_status = readw(&host->regs->nfc_ecc_status_result);
+ uint16_t ecc_status = readw(&host->regs->ecc_status_result);
if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
MTDDEBUG(MTD_DEBUG_LEVEL0,
case NAND_CMD_PAGEPROG:
send_prog_page(host, 0, host->spare_only);
- if (host->pagesize_2k && !is_mxc_nfc_11()) {
+ if (host->pagesize_2k && is_mxc_nfc_1()) {
/* data in 4 areas */
send_prog_page(host, 1, host->spare_only);
send_prog_page(host, 2, host->spare_only);
send_cmd(host, NAND_CMD_READSTART);
/* read for each AREA */
send_read_page(host, 0, host->spare_only);
- if (!is_mxc_nfc_11()) {
+ if (is_mxc_nfc_1()) {
send_read_page(host, 1, host->spare_only);
send_read_page(host, 2, host->spare_only);
send_read_page(host, 3, host->spare_only);
}
}
-#ifdef MXC_NFC_V1_1
-static void mxc_setup_config1(void)
-{
- uint16_t tmp;
-
- tmp = readw(&host->regs->nfc_config1);
- tmp |= NFC_ONE_CYCLE;
- tmp |= NFC_4_8N_ECC;
- writew(tmp, &host->regs->nfc_config1);
- if (host->pagesize_2k)
- writew(64/2, &host->regs->nfc_spare_area_size);
- else
- writew(16/2, &host->regs->nfc_spare_area_size);
-}
-#else
-#define mxc_setup_config1()
-#endif
-
#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
int board_nand_init(struct nand_chip *this)
{
struct mtd_info *mtd;
+#ifdef MXC_NFC_V2_1
uint16_t tmp;
- int err = 0;
+#endif
#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
this->options |= NAND_USE_FLASH_BBT;
this->read_buf = mxc_nand_read_buf;
this->verify_buf = mxc_nand_verify_buf;
- host->regs = (struct nfc_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
+ host->regs = (struct fsl_nfc_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
host->clk_act = 1;
#ifdef CONFIG_MXC_NAND_HWECC
this->ecc.calculate = mxc_nand_calculate_ecc;
this->ecc.hwctl = mxc_nand_enable_hwecc;
this->ecc.correct = mxc_nand_correct_data;
- if (is_mxc_nfc_11()) {
+ if (is_mxc_nfc_21()) {
this->ecc.mode = NAND_ECC_HW_SYNDROME;
this->ecc.read_page = mxc_nand_read_page_syndrome;
this->ecc.read_page_raw = mxc_nand_read_page_raw_syndrome;
host->pagesize_2k = 0;
this->ecc.size = 512;
- tmp = readw(&host->regs->nfc_config1);
- tmp |= NFC_ECC_EN;
- writew(tmp, &host->regs->nfc_config1);
+ _mxc_nand_enable_hwecc(mtd, 1);
#else
this->ecc.layout = &nand_soft_eccoob;
this->ecc.mode = NAND_ECC_SOFT;
- tmp = readw(&host->regs->nfc_config1);
- tmp &= ~NFC_ECC_EN;
- writew(tmp, &host->regs->nfc_config1);
+ _mxc_nand_enable_hwecc(mtd, 0);
#endif
/* Reset NAND */
this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+ /* NAND bus width determines access functions used by upper layer */
+ if (is_16bit_nand())
+ this->options |= NAND_BUSWIDTH_16;
+
+#ifdef CONFIG_SYS_NAND_LARGEPAGE
+ host->pagesize_2k = 1;
+ this->ecc.layout = &nand_hw_eccoob2k;
+#else
+ host->pagesize_2k = 0;
+ this->ecc.layout = &nand_hw_eccoob;
+#endif
+
+#ifdef MXC_NFC_V2_1
+ tmp = readw(&host->regs->config1);
+ tmp |= NFC_ONE_CYCLE;
+ tmp |= NFC_4_8N_ECC;
+ writew(tmp, &host->regs->config1);
+ if (host->pagesize_2k)
+ writew(64/2, &host->regs->spare_area_size);
+ else
+ writew(16/2, &host->regs->spare_area_size);
+#endif
+
/*
* preset operation
* Unlock the internal RAM Buffer
*/
- writew(0x2, &host->regs->nfc_config);
+ writew(0x2, &host->regs->config);
/* Blocks to be unlocked */
- writew(0x0, &host->regs->nfc_unlockstart_blkaddr);
+ writew(0x0, &host->regs->unlockstart_blkaddr);
/* Originally (Freescale LTIB 2.6.21) 0x4000 was written to the
* unlockend_blkaddr, but the magic 0x4000 does not always work
* when writing more than some 32 megabytes (on 2k page nands)
* This might be NAND chip specific and the i.MX31 datasheet is
* extremely vague about the semantics of this register.
*/
- writew(0xFFFF, &host->regs->nfc_unlockend_blkaddr);
+ writew(0xFFFF, &host->regs->unlockend_blkaddr);
/* Unlock Block Command for given address range */
- writew(0x4, &host->regs->nfc_wrprot);
+ writew(0x4, &host->regs->wrprot);
- /* NAND bus width determines access functions used by upper layer */
- if (is_16bit_nand())
- this->options |= NAND_BUSWIDTH_16;
-
-#ifdef CONFIG_SYS_NAND_LARGEPAGE
- host->pagesize_2k = 1;
- this->ecc.layout = &nand_hw_eccoob2k;
-#else
- host->pagesize_2k = 0;
- this->ecc.layout = &nand_hw_eccoob;
-#endif
- mxc_setup_config1();
- return err;
+ return 0;
}
mtd->writesize = le32_to_cpu(p->byte_per_page);
mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
- chip->chipsize = (uint64_t)le32_to_cpu(p->blocks_per_lun) * mtd->erasesize;
+ chip->chipsize = le32_to_cpu(p->blocks_per_lun);
+ chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
*busw = 0;
if (le16_to_cpu(p->features) & 1)
*busw = NAND_BUSWIDTH_16;
- chip->options &= ~NAND_CHIPOPTIONS_MSK;
- chip->options |= (NAND_NO_READRDY |
- NAND_NO_AUTOINCR) & NAND_CHIPOPTIONS_MSK;
+ chip->options |= NAND_NO_READRDY | NAND_NO_AUTOINCR;
return 1;
}
}
}
/* Get chip options, preserve non chip based options */
- chip->options &= ~NAND_CHIPOPTIONS_MSK;
- chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
+ chip->options |= type->options;
/* Check if chip is a not a samsung device. Do not clear the
* options for chips which are not having an extended id.
* Support for locking / unlocking operations of some NAND devices
*****************************************************************************/
-#define NAND_CMD_LOCK 0x2a
-#define NAND_CMD_LOCK_TIGHT 0x2c
-#define NAND_CMD_UNLOCK1 0x23
-#define NAND_CMD_UNLOCK2 0x24
-#define NAND_CMD_LOCK_STATUS 0x7a
-
/**
* nand_lock: Set all pages of NAND flash chip to the LOCK or LOCK-TIGHT
* state
* >0 lock status:
* bitfield with the following combinations:
* NAND_LOCK_STATUS_TIGHT: page in tight state
- * NAND_LOCK_STATUS_LOCK: page locked
* NAND_LOCK_STATUS_UNLOCK: page unlocked
*
*/
chip->cmdfunc(mtd, NAND_CMD_LOCK_STATUS, -1, page & chip->pagemask);
ret = chip->read_byte(mtd) & (NAND_LOCK_STATUS_TIGHT
- | NAND_LOCK_STATUS_LOCK
| NAND_LOCK_STATUS_UNLOCK);
out:
* @param start start byte address
* @param length number of bytes to unlock (must be a multiple of
* page size nand->writesize)
+ * @param allexcept if set, unlock everything not selected
*
* @return 0 on success, -1 in case of error
*/
-int nand_unlock(struct mtd_info *mtd, ulong start, ulong length)
+int nand_unlock(struct mtd_info *mtd, loff_t start, size_t length,
+ int allexcept)
{
int ret = 0;
int chipnr;
int status;
int page;
struct nand_chip *chip = mtd->priv;
- printf ("nand_unlock: start: %08x, length: %d!\n",
- (int)start, (int)length);
+
+ debug("nand_unlock%s: start: %08llx, length: %d!\n",
+ allexcept ? " (allexcept)" : "", start, length);
/* select the NAND device */
chipnr = (int)(start >> chip->chip_shift);
/* submit ADDRESS of LAST page to unlock */
page += (int)(length >> chip->page_shift);
+
+ /*
+ * Page addresses for unlocking are supposed to be block-aligned.
+ * At least some NAND chips use the low bit to indicate that the
+ * page range should be inverted.
+ */
+ if (allexcept)
+ page |= 1;
+
chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1, page & chip->pagemask);
/* call wait ready function */
greth_regs *regs = greth->regs;
greth_bd *rxbd;
unsigned int status, len = 0, bad;
- unsigned char *d;
+ char *d;
int enable = 0;
int i;
goto done;
}
- debug("greth_recv: packet 0x%lx, 0x%lx, len: %d\n",
+ debug("greth_recv: packet 0x%x, 0x%x, len: %d\n",
(unsigned int)rxbd, status, status & GRETH_BD_LEN);
/* Check status for errors.
greth->regs = (greth_regs *) apbdev.address;
greth->irq = apbdev.irq;
- debug("Found GRETH at 0x%lx, irq %d\n", greth->regs, greth->irq);
+ debug("Found GRETH at %p, irq %d\n", greth->regs, greth->irq);
dev->priv = (void *)greth;
dev->iobase = (unsigned int)greth->regs;
dev->init = greth_init;
/* initiate PHY, select speed/duplex depending on connected PHY */
if (greth_init_phy(greth, bis)) {
/* Failed to init PHY (timedout) */
- debug("GRETH[0x%08x]: Failed to init PHY\n", greth->regs);
+ debug("GRETH[%p]: Failed to init PHY\n", greth->regs);
return -1;
}
/* set and remember MAC address */
greth_set_hwaddr(greth, addr);
- debug("GRETH[0x%08x]: Initialized successfully\n", greth->regs);
+ debug("GRETH[%p]: Initialized successfully\n", greth->regs);
return 0;
}
}
/* PHY isn't up to snuff */
- printf("%s: PHY not found", macb->netdev.name);
+ printf("%s: PHY not found\n", macb->netdev.name);
return 0;
}
void *pci_map_bar(pci_dev_t pdev, int bar, int flags)
{
pci_addr_t pci_bus_addr;
- u32 bar_response;
+ pci_addr_t bar_response;
/* read BAR address */
pci_read_config_dword(pdev, bar, &bar_response);
- pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
+ pci_bus_addr = bar_response & ~0xf;
/*
* Pass "0" as the length argument to pci_bus_to_virt. The arg
*phose = hose;
}
-struct pci_controller *pci_bus_to_hose (int bus)
+struct pci_controller *pci_bus_to_hose(int bus)
{
struct pci_controller *hose;
- for (hose = hose_head; hose; hose = hose->next)
+ for (hose = hose_head; hose; hose = hose->next) {
if (bus >= hose->first_busno && bus <= hose->last_busno)
return hose;
+ }
printf("pci_bus_to_hose() failed\n");
return NULL;
pci_dev_t bdf;
int i, bus, found_multi = 0;
- for (hose = hose_head; hose; hose = hose->next)
- {
+ for (hose = hose_head; hose; hose = hose->next) {
#ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
for (bus = hose->last_busno; bus >= hose->first_busno; bus--)
#else
for (bus = hose->first_busno; bus <= hose->last_busno; bus++)
#endif
- for (bdf = PCI_BDF(bus,0,0);
+ for (bdf = PCI_BDF(bus, 0, 0);
#if defined(CONFIG_ELPPC) || defined(CONFIG_PPMC7XX)
- bdf < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
+ bdf < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
+ PCI_MAX_PCI_FUNCTIONS - 1);
#else
- bdf < PCI_BDF(bus+1,0,0);
+ bdf < PCI_BDF(bus + 1, 0, 0);
#endif
- bdf += PCI_BDF(0,0,1))
- {
+ bdf += PCI_BDF(0, 0, 1)) {
if (!PCI_FUNC(bdf)) {
pci_read_config_byte(bdf,
PCI_HEADER_TYPE,
PCI_DEVICE_ID,
&device);
- for (i=0; ids[i].vendor != 0; i++)
+ for (i = 0; ids[i].vendor != 0; i++) {
if (vendor == ids[i].vendor &&
- device == ids[i].device)
- {
+ device == ids[i].device) {
if (index <= 0)
return bdf;
index--;
}
+ }
}
}
- return (-1);
+ return -1;
}
pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
*
*/
-int __pci_hose_phys_to_bus (struct pci_controller *hose,
+int __pci_hose_phys_to_bus(struct pci_controller *hose,
phys_addr_t phys_addr,
unsigned long flags,
unsigned long skip_mask,
int ret;
if (!hose) {
- puts ("pci_hose_phys_to_bus: invalid hose\n");
+ puts("pci_hose_phys_to_bus: invalid hose\n");
return bus_addr;
}
- /* if PCI_REGION_MEM is set we do a two pass search with preference
- * on matches that don't have PCI_REGION_SYS_MEMORY set */
+ /*
+ * if PCI_REGION_MEM is set we do a two pass search with preference
+ * on matches that don't have PCI_REGION_SYS_MEMORY set
+ */
if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
ret = __pci_hose_phys_to_bus(hose, phys_addr,
flags, PCI_REGION_SYS_MEMORY, &bus_addr);
ret = __pci_hose_phys_to_bus(hose, phys_addr, flags, 0, &bus_addr);
if (ret)
- puts ("pci_hose_phys_to_bus: invalid physical address\n");
+ puts("pci_hose_phys_to_bus: invalid physical address\n");
return bus_addr;
}
-int __pci_hose_bus_to_phys (struct pci_controller *hose,
+int __pci_hose_bus_to_phys(struct pci_controller *hose,
pci_addr_t bus_addr,
unsigned long flags,
unsigned long skip_mask,
int ret;
if (!hose) {
- puts ("pci_hose_bus_to_phys: invalid hose\n");
+ puts("pci_hose_bus_to_phys: invalid hose\n");
return phys_addr;
}
- /* if PCI_REGION_MEM is set we do a two pass search with preference
- * on matches that don't have PCI_REGION_SYS_MEMORY set */
+ /*
+ * if PCI_REGION_MEM is set we do a two pass search with preference
+ * on matches that don't have PCI_REGION_SYS_MEMORY set
+ */
if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
ret = __pci_hose_bus_to_phys(hose, bus_addr,
flags, PCI_REGION_SYS_MEMORY, &phys_addr);
ret = __pci_hose_bus_to_phys(hose, bus_addr, flags, 0, &phys_addr);
if (ret)
- puts ("pci_hose_bus_to_phys: invalid physical address\n");
+ puts("pci_hose_bus_to_phys: invalid physical address\n");
return phys_addr;
}
pci_addr_t mem,
unsigned long command)
{
- unsigned int bar_response, old_command;
+ pci_addr_t bar_response;
+ unsigned int old_command;
pci_addr_t bar_value;
pci_size_t bar_size;
unsigned char pin;
int bar, found_mem64;
- debug ("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n",
- io, (u64)mem, command);
+ debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io,
+ (u64)mem, command);
- pci_hose_write_config_dword (hose, dev, PCI_COMMAND, 0);
+ pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0);
for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
- pci_hose_write_config_dword (hose, dev, bar, 0xffffffff);
- pci_hose_read_config_dword (hose, dev, bar, &bar_response);
+ pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
+ pci_hose_read_config_dword(hose, dev, bar, &bar_response);
if (!bar_response)
continue;
PCI_BASE_ADDRESS_MEM_TYPE_64) {
u32 bar_response_upper;
u64 bar64;
- pci_hose_write_config_dword(hose, dev, bar+4, 0xffffffff);
- pci_hose_read_config_dword(hose, dev, bar+4, &bar_response_upper);
+ pci_hose_write_config_dword(hose, dev, bar + 4,
+ 0xffffffff);
+ pci_hose_read_config_dword(hose, dev, bar + 4,
+ &bar_response_upper);
bar64 = ((u64)bar_response_upper << 32) | bar_response;
if (found_mem64) {
bar += 4;
#ifdef CONFIG_SYS_PCI_64BIT
- pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
+ pci_hose_write_config_dword(hose, dev, bar,
+ (u32)(bar_value >> 32));
#else
- pci_hose_write_config_dword (hose, dev, bar, 0x00000000);
+ pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
#endif
}
}
/* Configure Cache Line Size Register */
- pci_hose_write_config_byte (hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+ pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
/* Configure Latency Timer */
- pci_hose_write_config_byte (hose, dev, PCI_LATENCY_TIMER, 0x80);
+ pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
/* Disable interrupt line, if device says it wants to use interrupts */
- pci_hose_read_config_byte (hose, dev, PCI_INTERRUPT_PIN, &pin);
+ pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
if (pin != 0) {
- pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, 0xff);
+ pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 0xff);
}
- pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &old_command);
- pci_hose_write_config_dword (hose, dev, PCI_COMMAND,
+ pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command);
+ pci_hose_write_config_dword(hose, dev, PCI_COMMAND,
(old_command & 0xffff0000) | command);
return 0;
pci_dev_t dev,
struct pci_config_table *entry)
{
- pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1], entry->priv[2]);
+ pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1],
+ entry->priv[2]);
}
void pci_cfgfunc_do_nothing(struct pci_controller *hose,
}
/*
- *
- */
-
-/* HJF: Changed this to return int. I think this is required
+ * HJF: Changed this to return int. I think this is required
* to get the correct result when scanning bridges
*/
extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
int pci_hose_scan_bus(struct pci_controller *hose, int bus)
{
- unsigned int sub_bus, found_multi=0;
+ unsigned int sub_bus, found_multi = 0;
unsigned short vendor, device, class;
unsigned char header_type;
+#ifndef CONFIG_PCI_PNP
struct pci_config_table *cfg;
+#endif
pci_dev_t dev;
#ifdef CONFIG_PCI_SCAN_SHOW
static int indent = 0;
sub_bus = bus;
for (dev = PCI_BDF(bus,0,0);
- dev < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
- dev += PCI_BDF(0,0,1)) {
+ dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
+ PCI_MAX_PCI_FUNCTIONS - 1);
+ dev += PCI_BDF(0, 0, 1)) {
if (pci_skip_dev(hose, dev))
continue;
if (!PCI_FUNC(dev))
found_multi = header_type & 0x80;
- debug ("PCI Scan: Found Bus %d, Device %d, Function %d\n",
- PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev) );
+ debug("PCI Scan: Found Bus %d, Device %d, Function %d\n",
+ PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
}
#endif
+#ifdef CONFIG_PCI_PNP
+ sub_bus = max(pciauto_config_device(hose, dev), sub_bus);
+#else
cfg = pci_find_config(hose, class, vendor, device,
PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
if (cfg) {
cfg->config_device(hose, dev, cfg);
sub_bus = max(sub_bus, hose->current_busno);
-#ifdef CONFIG_PCI_PNP
- } else {
- int n = pciauto_config_device(hose, dev);
-
- sub_bus = max(sub_bus, n);
-#endif
}
+#endif
#ifdef CONFIG_PCI_SCAN_SHOW
indent--;
}
#endif /* CONFIG_PCI_BOOTDELAY */
- /* Start scan at current_busno.
+ /*
+ * Start scan at current_busno.
* PCIe will start scan at first_busno+1.
*/
- /* For legacy support, ensure current>=first */
+ /* For legacy support, ensure current >= first */
if (hose->first_busno > hose->current_busno)
hose->current_busno = hose->first_busno;
#ifdef CONFIG_PCI_PNP
*
*/
-void pciauto_region_init(struct pci_region* res)
+void pciauto_region_init(struct pci_region *res)
{
/*
* Avoid allocating PCI resources from address 0 -- this is illegal
res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1;
}
-int pciauto_region_allocate(struct pci_region* res, pci_size_t size, pci_addr_t *bar)
+int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
+ pci_addr_t *bar)
{
pci_addr_t addr;
struct pci_region *prefetch,
struct pci_region *io)
{
- unsigned int bar_response;
- pci_addr_t bar_value;
+ pci_addr_t bar_response;
pci_size_t bar_size;
- unsigned int cmdstat = 0;
- struct pci_region *bar_res;
+ u16 cmdstat = 0;
int bar, bar_nr = 0;
+#ifndef CONFIG_PCI_ENUM_ONLY
+ pci_addr_t bar_value;
+ struct pci_region *bar_res;
int found_mem64 = 0;
+#endif
- pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
+ pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
- for (bar = PCI_BASE_ADDRESS_0; bar < PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4) {
+ for (bar = PCI_BASE_ADDRESS_0;
+ bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
/* Tickle the BAR and get the response */
+#ifndef CONFIG_PCI_ENUM_ONLY
pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
+#endif
pci_hose_read_config_dword(hose, dev, bar, &bar_response);
/* If BAR is not implemented go to the next BAR */
if (!bar_response)
continue;
+#ifndef CONFIG_PCI_ENUM_ONLY
found_mem64 = 0;
+#endif
/* Check the BAR type and set our address mask */
if (bar_response & PCI_BASE_ADDRESS_SPACE) {
bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
& 0xffff) + 1;
+#ifndef CONFIG_PCI_ENUM_ONLY
bar_res = io;
+#endif
DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ", bar_nr, (u64)bar_size);
} else {
- if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
+ if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
PCI_BASE_ADDRESS_MEM_TYPE_64) {
u32 bar_response_upper;
u64 bar64;
- pci_hose_write_config_dword(hose, dev, bar+4, 0xffffffff);
- pci_hose_read_config_dword(hose, dev, bar+4, &bar_response_upper);
+
+#ifndef CONFIG_PCI_ENUM_ONLY
+ pci_hose_write_config_dword(hose, dev, bar + 4,
+ 0xffffffff);
+#endif
+ pci_hose_read_config_dword(hose, dev, bar + 4,
+ &bar_response_upper);
bar64 = ((u64)bar_response_upper << 32) | bar_response;
bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
+#ifndef CONFIG_PCI_ENUM_ONLY
found_mem64 = 1;
+#endif
} else {
bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
}
+#ifndef CONFIG_PCI_ENUM_ONLY
if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
bar_res = prefetch;
else
bar_res = mem;
+#endif
DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%llx, ", bar_nr, (u64)bar_size);
}
+#ifndef CONFIG_PCI_ENUM_ONLY
if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
/* Write it out and update our limit */
pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
#endif
}
- cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
- PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
}
+#endif
+ cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
+ PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
DEBUGF("\n");
bar_nr++;
}
- pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
+ pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
CONFIG_SYS_PCI_CACHE_LINE_SIZE);
pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
struct pci_region *pci_mem = hose->pci_mem;
struct pci_region *pci_prefetch = hose->pci_prefetch;
struct pci_region *pci_io = hose->pci_io;
- unsigned int cmdstat;
+ u16 cmdstat;
- pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
+ pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
/* Configure bus number registers */
pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
}
/* Enable memory and I/O accesses, enable bus master */
- pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);
+ pci_hose_write_config_word(hose, dev, PCI_COMMAND,
+ cmdstat | PCI_COMMAND_MASTER);
}
void pciauto_postscan_setup_bridge(struct pci_controller *hose,
pciauto_region_align(pci_mem, 0x100000);
pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
- (pci_mem->bus_lower-1) >> 16);
+ (pci_mem->bus_lower - 1) >> 16);
}
if (pci_prefetch) {
pciauto_region_align(pci_prefetch, 0x100000);
pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
- (pci_prefetch->bus_lower-1) >> 16);
+ (pci_prefetch->bus_lower - 1) >> 16);
}
if (pci_io) {
pciauto_region_align(pci_io, 0x1000);
pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
- ((pci_io->bus_lower-1) & 0x0000f000) >> 8);
+ ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
- ((pci_io->bus_lower-1) & 0xffff0000) >> 16);
+ ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
}
}
hose->pci_io = hose->pci_mem = NULL;
- for (i=0; i<hose->region_count; i++) {
+ for (i = 0; i < hose->region_count; i++) {
switch(hose->regions[i].flags) {
case PCI_REGION_IO:
if (!hose->pci_io ||
}
}
-/* HJF: Changed this to return int. I think this is required
+/*
+ * HJF: Changed this to return int. I think this is required
* to get the correct result when scanning bridges
*/
int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
- switch(class) {
- case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
- DEBUGF("PCI AutoConfig: Found PowerPC device\n");
- pciauto_setup_device(hose, dev, 6, hose->pci_mem,
- hose->pci_prefetch, hose->pci_io);
- break;
-
+ switch (class) {
case PCI_CLASS_BRIDGE_PCI:
hose->current_busno++;
- pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
+ pciauto_setup_device(hose, dev, 2, hose->pci_mem,
+ hose->pci_prefetch, hose->pci_io);
DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev));
return sub_bus;
}
- pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
+ pciauto_setup_device(hose, dev, 6, hose->pci_mem,
+ hose->pci_prefetch, hose->pci_io);
break;
case PCI_CLASS_BRIDGE_CARDBUS:
- /* just do a minimal setup of the bridge, let the OS take care of the rest */
- pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
+ /*
+ * just do a minimal setup of the bridge,
+ * let the OS take care of the rest
+ */
+ pciauto_setup_device(hose, dev, 0, hose->pci_mem,
+ hose->pci_prefetch, hose->pci_io);
- DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n", PCI_DEV(dev));
+ DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
+ PCI_DEV(dev));
hose->current_busno++;
break;
* the PIMMR window to be allocated (BAR0 - 1MB size)
*/
DEBUGF("PCI Autoconfig: Broken bridge found, only minimal config\n");
- pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
+ pciauto_setup_device(hose, dev, 0, hose->pci_mem,
+ hose->pci_prefetch, hose->pci_io);
break;
#endif
+
+ case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
+ DEBUGF("PCI AutoConfig: Found PowerPC device\n");
+
default:
- pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
+ pciauto_setup_device(hose, dev, 6, hose->pci_mem,
+ hose->pci_prefetch, hose->pci_io);
break;
}
tmp->tm_hour = bcd2bin (hour & 0x3F);
tmp->tm_mday = bcd2bin (mday & 0x3F);
tmp->tm_mon = bcd2bin (mon_cent & 0x1F);
- tmp->tm_year = bcd2bin (year) + ((mon_cent & 0x80) ? 2000 : 1900);
+ tmp->tm_year = bcd2bin (year) + ((mon_cent & 0x80) ? 1900 : 2000);
tmp->tm_wday = bcd2bin (wday & 0x07);
tmp->tm_yday = 0;
tmp->tm_isdst= 0;
rtc_write (0x08, bin2bcd(tmp->tm_year % 100));
- century = (tmp->tm_year >= 2000) ? 0x80 : 0;
+ century = (tmp->tm_year >= 2000) ? 0 : 0x80;
rtc_write (0x07, bin2bcd(tmp->tm_mon) | century);
rtc_write (0x06, bin2bcd(tmp->tm_wday));
return in_be32(®s->status) & SR_RX_FIFO_VALID_DATA;
}
+static int uartlite_serial_init(const int port)
+{
+ if (userial_ports[port])
+ return 0;
+ return -1;
+}
+
#if !defined(CONFIG_SERIAL_MULTI)
int serial_init(void)
{
- /* FIXME: Nothing for now. We should initialize fifo, etc */
- return 0;
+ return uartlite_serial_init(0);
}
void serial_setbrg(void)
/* Multi serial device functions */
#define DECLARE_ESERIAL_FUNCTIONS(port) \
int userial##port##_init(void) \
- { return(0); } \
+ { return uartlite_serial_init(port); } \
void userial##port##_setbrg(void) {} \
int userial##port##_getc(void) \
{ return uartlite_serial_getc(port); } \
__weak struct serial_device *default_serial_console(void)
{
-# ifdef XILINX_UARTLITE_BASEADDR
- return &uartlite_serial0_device;
-# endif /* XILINX_UARTLITE_BASEADDR */
-# ifdef XILINX_UARTLITE_BASEADDR1
- return &uartlite_serial1_device;
-# endif /* XILINX_UARTLITE_BASEADDR1 */
-# ifdef XILINX_UARTLITE_BASEADDR2
- return &uartlite_serial2_device;
-# endif /* XILINX_UARTLITE_BASEADDR2 */
-# ifdef XILINX_UARTLITE_BASEADDR3
- return &uartlite_serial3_device;
-# endif /* XILINX_UARTLITE_BASEADDR3 */
+ if (userial_ports[0])
+ return &uartlite_serial0_device;
+ if (userial_ports[1])
+ return &uartlite_serial1_device;
+ if (userial_ports[2])
+ return &uartlite_serial2_device;
+ if (userial_ports[3])
+ return &uartlite_serial3_device;
+
+ return NULL;
}
#endif /* CONFIG_SERIAL_MULTI */
COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o
COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o
COBJS-$(CONFIG_CF_SPI) += cf_spi.o
+COBJS-$(CONFIG_CF_QSPI) += cf_qspi.o
COBJS-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
COBJS-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o
--- /dev/null
+/*
+ * Freescale Coldfire Queued SPI driver
+ *
+ * NOTE:
+ * This driver is written to transfer 8 bit at-a-time and uses the dedicated
+ * SPI slave select pins as bit-banged GPIO to work with spi_flash subsystem.
+ *
+ *
+ * Copyright (C) 2011 Ruggedcom, Inc.
+ * Richard Retanubun (richardretanubun@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <spi.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define clamp(x, low, high) (min(max(low, x), high))
+#define to_cf_qspi_slave(s) container_of(s, struct cf_qspi_slave, s)
+
+struct cf_qspi_slave {
+ struct spi_slave slave; /* Specific bus:cs ID for each device */
+ qspi_t *regs; /* Pointer to SPI controller registers */
+ u16 qmr; /* QMR: Queued Mode Register */
+ u16 qwr; /* QWR: Queued Wrap Register */
+ u16 qcr; /* QCR: Queued Command Ram */
+};
+
+/* Register write wrapper functions */
+static void write_qmr(volatile qspi_t *qspi, u16 val) { qspi->mr = val; }
+static void write_qdlyr(volatile qspi_t *qspi, u16 val) { qspi->dlyr = val; }
+static void write_qwr(volatile qspi_t *qspi, u16 val) { qspi->wr = val; }
+static void write_qir(volatile qspi_t *qspi, u16 val) { qspi->ir = val; }
+static void write_qar(volatile qspi_t *qspi, u16 val) { qspi->ar = val; }
+static void write_qdr(volatile qspi_t *qspi, u16 val) { qspi->dr = val; }
+/* Register read wrapper functions */
+static u16 read_qdlyr(volatile qspi_t *qspi) { return qspi->dlyr; }
+static u16 read_qwr(volatile qspi_t *qspi) { return qspi->wr; }
+static u16 read_qir(volatile qspi_t *qspi) { return qspi->ir; }
+static u16 read_qdr(volatile qspi_t *qspi) { return qspi->dr; }
+
+/* These call points may be different for each ColdFire CPU */
+extern void cfspi_port_conf(void);
+static void cfspi_cs_activate(uint bus, uint cs, uint cs_active_high);
+static void cfspi_cs_deactivate(uint bus, uint cs, uint cs_active_high);
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ return 0;
+}
+void spi_release_bus(struct spi_slave *slave)
+{
+}
+
+__attribute__((weak))
+void spi_init(void)
+{
+ cfspi_port_conf();
+}
+
+__attribute__((weak))
+void spi_cs_activate(struct spi_slave *slave)
+{
+ struct cf_qspi_slave *dev = to_cf_qspi_slave(slave);
+
+ cfspi_cs_activate(slave->bus, slave->cs, !(dev->qwr & QSPI_QWR_CSIV));
+}
+
+__attribute__((weak))
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ struct cf_qspi_slave *dev = to_cf_qspi_slave(slave);
+
+ cfspi_cs_deactivate(slave->bus, slave->cs, !(dev->qwr & QSPI_QWR_CSIV));
+}
+
+__attribute__((weak))
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ /* Only 1 bus and 4 chipselect per controller */
+ if (bus == 0 && (cs >= 0 && cs < 4))
+ return 1;
+ else
+ return 0;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ struct cf_qspi_slave *dev = to_cf_qspi_slave(slave);
+
+ free(dev);
+}
+
+/* Translate information given by spi_setup_slave to members of cf_qspi_slave */
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct cf_qspi_slave *dev = NULL;
+
+ if (!spi_cs_is_valid(bus, cs))
+ return NULL;
+
+ dev = malloc(sizeof(struct cf_qspi_slave));
+ if (!dev)
+ return NULL;
+
+ /* Initialize to known value */
+ dev->slave.bus = bus;
+ dev->slave.cs = cs;
+ dev->regs = (qspi_t *)MMAP_QSPI;
+ dev->qmr = 0;
+ dev->qwr = 0;
+ dev->qcr = 0;
+
+
+ /* Map max_hz to QMR[BAUD] */
+ if (max_hz == 0) /* Go as fast as possible */
+ dev->qmr = 2u;
+ else /* Get the closest baud rate */
+ dev->qmr = clamp(((gd->bus_clk >> 2) + max_hz - 1)/max_hz,
+ 2u, 255u);
+
+ /* Map mode to QMR[CPOL] and QMR[CPHA] */
+ if (mode & SPI_CPOL)
+ dev->qmr |= QSPI_QMR_CPOL;
+
+ if (mode & SPI_CPHA)
+ dev->qmr |= QSPI_QMR_CPHA;
+
+ /* Hardcode bit length to 8 bit per transter */
+ dev->qmr |= QSPI_QMR_BITS_8;
+
+ /* Set QMR[MSTR] to enable QSPI as master */
+ dev->qmr |= QSPI_QMR_MSTR;
+
+ /*
+ * Set QCR and QWR to default values for spi flash operation.
+ * If more custom QCR and QRW are needed, overload mode variable
+ */
+ dev->qcr = (QSPI_QDR_CONT | QSPI_QDR_BITSE);
+
+ if (!(mode & SPI_CS_HIGH))
+ dev->qwr |= QSPI_QWR_CSIV;
+
+ return &dev->slave;
+}
+
+/* Transfer 8 bit at a time */
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+ void *din, unsigned long flags)
+{
+ struct cf_qspi_slave *dev = to_cf_qspi_slave(slave);
+ volatile qspi_t *qspi = dev->regs;
+ u8 *txbuf = (u8 *)dout;
+ u8 *rxbuf = (u8 *)din;
+ u32 count = ((bitlen / 8) + (bitlen % 8 ? 1 : 0));
+ u32 n, i = 0;
+
+ /* Sanitize arguments */
+ if (slave == NULL) {
+ printf("%s: NULL slave ptr\n", __func__);
+ return -1;
+ }
+
+ if (flags & SPI_XFER_BEGIN)
+ spi_cs_activate(slave);
+
+ /* There is something to send, lets process it. spi_xfer is also called
+ * just to toggle chip select, so bitlen of 0 is valid */
+ if (count > 0) {
+ /*
+ * NOTE: Since chip select is driven as a bit-bang-ed GPIO
+ * using spi_cs_activate() and spi_cs_deactivate(),
+ * the chip select settings inside the controller
+ * (i.e. QCR[CONT] and QWR[CSIV]) are moot. The bits are set to
+ * keep the controller settings consistent with the actual
+ * operation of the bus.
+ */
+
+ /* Write the slave device's settings for the controller.*/
+ write_qmr(qspi, dev->qmr);
+ write_qwr(qspi, dev->qwr);
+
+ /* Limit transfer to 16 at a time */
+ n = min(count, 16u);
+ do {
+ /* Setup queue end point */
+ write_qwr(qspi, ((read_qwr(qspi) & QSPI_QWR_ENDQP_MASK)
+ | QSPI_QWR_ENDQP((n-1))));
+
+ /* Write Command RAM */
+ write_qar(qspi, QSPI_QAR_CMD);
+ for (i = 0; i < n; ++i)
+ write_qdr(qspi, dev->qcr);
+
+ /* Write TxBuf, if none given, fill with ZEROes */
+ write_qar(qspi, QSPI_QAR_TRANS);
+ if (txbuf) {
+ for (i = 0; i < n; ++i)
+ write_qdr(qspi, *txbuf++);
+ } else {
+ for (i = 0; i < n; ++i)
+ write_qdr(qspi, 0);
+ }
+
+ /* Clear QIR[SPIF] by writing a 1 to it */
+ write_qir(qspi, read_qir(qspi) | QSPI_QIR_SPIF);
+ /* Set QDLYR[SPE] to start sending */
+ write_qdlyr(qspi, read_qdlyr(qspi) | QSPI_QDLYR_SPE);
+
+ /* Poll QIR[SPIF] for transfer completion */
+ while ((read_qir(qspi) & QSPI_QIR_SPIF) != 1)
+ udelay(1);
+
+ /* If given read RxBuf, load data to it */
+ if (rxbuf) {
+ write_qar(qspi, QSPI_QAR_RECV);
+ for (i = 0; i < n; ++i)
+ *rxbuf++ = read_qdr(qspi);
+ }
+
+ /* Decrement count */
+ count -= n;
+ } while (count);
+ }
+
+ if (flags & SPI_XFER_END)
+ spi_cs_deactivate(slave);
+
+ return 0;
+}
+
+/* Each MCF CPU may have different pin assignments for chip selects. */
+#if defined(CONFIG_M5271)
+/* Assert chip select, val = [1|0] , dir = out, mode = GPIO */
+void cfspi_cs_activate(uint bus, uint cs, uint cs_active_high)
+{
+ debug("%s: bus %d cs %d cs_active_high %d\n",
+ __func__, bus, cs, cs_active_high);
+
+ switch (cs) {
+ case 0: /* QSPI_CS[0] = PQSPI[3] */
+ if (cs_active_high)
+ mbar_writeByte(MCF_GPIO_PPDSDR_QSPI, 0x08);
+ else
+ mbar_writeByte(MCF_GPIO_PCLRR_QSPI, 0xF7);
+
+ mbar_writeByte(MCF_GPIO_PDDR_QSPI,
+ mbar_readByte(MCF_GPIO_PDDR_QSPI) | 0x08);
+
+ mbar_writeByte(MCF_GPIO_PAR_QSPI,
+ mbar_readByte(MCF_GPIO_PAR_QSPI) & 0xDF);
+ break;
+ case 1: /* QSPI_CS[1] = PQSPI[4] */
+ if (cs_active_high)
+ mbar_writeByte(MCF_GPIO_PPDSDR_QSPI, 0x10);
+ else
+ mbar_writeByte(MCF_GPIO_PCLRR_QSPI, 0xEF);
+
+ mbar_writeByte(MCF_GPIO_PDDR_QSPI,
+ mbar_readByte(MCF_GPIO_PDDR_QSPI) | 0x10);
+
+ mbar_writeByte(MCF_GPIO_PAR_QSPI,
+ mbar_readByte(MCF_GPIO_PAR_QSPI) & 0x3F);
+ break;
+ case 2: /* QSPI_CS[2] = PTIMER[7] */
+ if (cs_active_high)
+ mbar_writeByte(MCF_GPIO_PPDSDR_TIMER, 0x80);
+ else
+ mbar_writeByte(MCF_GPIO_PCLRR_TIMER, 0x7F);
+
+ mbar_writeByte(MCF_GPIO_PDDR_TIMER,
+ mbar_readByte(MCF_GPIO_PDDR_TIMER) | 0x80);
+
+ mbar_writeShort(MCF_GPIO_PAR_TIMER,
+ mbar_readShort(MCF_GPIO_PAR_TIMER) & 0x3FFF);
+ break;
+ case 3: /* QSPI_CS[3] = PTIMER[3] */
+ if (cs_active_high)
+ mbar_writeByte(MCF_GPIO_PPDSDR_TIMER, 0x08);
+ else
+ mbar_writeByte(MCF_GPIO_PCLRR_TIMER, 0xF7);
+
+ mbar_writeByte(MCF_GPIO_PDDR_TIMER,
+ mbar_readByte(MCF_GPIO_PDDR_TIMER) | 0x08);
+
+ mbar_writeShort(MCF_GPIO_PAR_TIMER,
+ mbar_readShort(MCF_GPIO_PAR_TIMER) & 0xFF3F);
+ break;
+ }
+}
+
+/* Deassert chip select, val = [1|0], dir = in, mode = GPIO
+ * direction set as IN to undrive the pin, external pullup/pulldown will bring
+ * bus to deassert state.
+ */
+void cfspi_cs_deactivate(uint bus, uint cs, uint cs_active_high)
+{
+ debug("%s: bus %d cs %d cs_active_high %d\n",
+ __func__, bus, cs, cs_active_high);
+
+ switch (cs) {
+ case 0: /* QSPI_CS[0] = PQSPI[3] */
+ if (cs_active_high)
+ mbar_writeByte(MCF_GPIO_PCLRR_QSPI, 0xF7);
+ else
+ mbar_writeByte(MCF_GPIO_PPDSDR_QSPI, 0x08);
+
+ mbar_writeByte(MCF_GPIO_PDDR_QSPI,
+ mbar_readByte(MCF_GPIO_PDDR_QSPI) & 0xF7);
+
+ mbar_writeByte(MCF_GPIO_PAR_QSPI,
+ mbar_readByte(MCF_GPIO_PAR_QSPI) & 0xDF);
+ break;
+ case 1: /* QSPI_CS[1] = PQSPI[4] */
+ if (cs_active_high)
+ mbar_writeByte(MCF_GPIO_PCLRR_QSPI, 0xEF);
+ else
+ mbar_writeByte(MCF_GPIO_PPDSDR_QSPI, 0x10);
+
+ mbar_writeByte(MCF_GPIO_PDDR_QSPI,
+ mbar_readByte(MCF_GPIO_PDDR_QSPI) & 0xEF);
+
+ mbar_writeByte(MCF_GPIO_PAR_QSPI,
+ mbar_readByte(MCF_GPIO_PAR_QSPI) & 0x3F);
+ break;
+ case 2: /* QSPI_CS[2] = PTIMER[7] */
+ if (cs_active_high)
+ mbar_writeByte(MCF_GPIO_PCLRR_TIMER, 0x7F);
+ else
+ mbar_writeByte(MCF_GPIO_PPDSDR_TIMER, 0x80);
+
+ mbar_writeByte(MCF_GPIO_PDDR_TIMER,
+ mbar_readByte(MCF_GPIO_PDDR_TIMER) & 0x7F);
+
+ mbar_writeShort(MCF_GPIO_PAR_TIMER,
+ mbar_readShort(MCF_GPIO_PAR_TIMER) & 0x3FFF);
+ break;
+ case 3: /* QSPI_CS[3] = PTIMER[3] */
+ if (cs_active_high)
+ mbar_writeByte(MCF_GPIO_PCLRR_TIMER, 0xF7);
+ else
+ mbar_writeByte(MCF_GPIO_PPDSDR_TIMER, 0x08);
+
+ mbar_writeByte(MCF_GPIO_PDDR_TIMER,
+ mbar_readByte(MCF_GPIO_PDDR_TIMER) & 0xF7);
+
+ mbar_writeShort(MCF_GPIO_PAR_TIMER,
+ mbar_readShort(MCF_GPIO_PAR_TIMER) & 0xFF3F);
+ break;
+ }
+}
+#endif /* CONFIG_M5271 */
* len > 16 0
*/
+ spi->mode &= ~SPI_MODE_EN;
+
if (bitlen <= 16) {
if (bitlen <= 4)
spi->mode = (spi->mode & 0xff0fffff) |
dout += 4;
}
+ spi->mode |= SPI_MODE_EN;
+
spi->tx = tmpdout; /* Write the data out */
debug("*** spi_xfer: ... %08x written\n", tmpdout);
unsigned int max_hz, unsigned int mode)
{
struct xilinx_spi_slave *xilspi;
- struct xilinx_spi_reg *regs;
if (!spi_cs_is_valid(bus, cs)) {
printf("XILSPI error: %s: unsupported bus %d / cs %d\n",
ifdef CONFIG_USB_GADGET
COBJS-y += epautoconf.o config.o usbstring.o
COBJS-$(CONFIG_USB_GADGET_S3C_UDC_OTG) += s3c_udc_otg.o
+COBJS-$(CONFIG_USBDOWNLOAD_GADGET) += g_dnl.o
+COBJS-$(CONFIG_DFU_FUNCTION) += f_dfu.o
endif
ifdef CONFIG_USB_ETHER
COBJS-y += ether.o epautoconf.o config.o usbstring.o
--- /dev/null
+/*
+ * f_dfu.c -- Device Firmware Update USB function
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ * authors: Andrzej Pietrasiewicz <andrzej.p@samsung.com>
+ * Lukasz Majewski <l.majewski@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <errno.h>
+#include <common.h>
+#include <malloc.h>
+
+#include <linux/usb/ch9.h>
+#include <usbdescriptors.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/composite.h>
+
+#include <dfu.h>
+#include "f_dfu.h"
+
+struct f_dfu {
+ struct usb_function usb_function;
+
+ struct usb_descriptor_header **function;
+ struct usb_string *strings;
+
+ /* when configured, we have one config */
+ u8 config;
+ u8 altsetting;
+ enum dfu_state dfu_state;
+ unsigned int dfu_status;
+
+ /* Send/received block number is handy for data integrity check */
+ int blk_seq_num;
+};
+
+typedef int (*dfu_state_fn) (struct f_dfu *,
+ const struct usb_ctrlrequest *,
+ struct usb_gadget *,
+ struct usb_request *);
+
+static inline struct f_dfu *func_to_dfu(struct usb_function *f)
+{
+ return container_of(f, struct f_dfu, usb_function);
+}
+
+static const struct dfu_function_descriptor dfu_func = {
+ .bLength = sizeof dfu_func,
+ .bDescriptorType = DFU_DT_FUNC,
+ .bmAttributes = DFU_BIT_WILL_DETACH |
+ DFU_BIT_MANIFESTATION_TOLERANT |
+ DFU_BIT_CAN_UPLOAD |
+ DFU_BIT_CAN_DNLOAD,
+ .wDetachTimeOut = 0,
+ .wTransferSize = DFU_USB_BUFSIZ,
+ .bcdDFUVersion = __constant_cpu_to_le16(0x0110),
+};
+
+static struct usb_interface_descriptor dfu_intf_runtime = {
+ .bLength = sizeof dfu_intf_runtime,
+ .bDescriptorType = USB_DT_INTERFACE,
+ .bNumEndpoints = 0,
+ .bInterfaceClass = USB_CLASS_APP_SPEC,
+ .bInterfaceSubClass = 1,
+ .bInterfaceProtocol = 1,
+ /* .iInterface = DYNAMIC */
+};
+
+static struct usb_descriptor_header *dfu_runtime_descs[] = {
+ (struct usb_descriptor_header *) &dfu_intf_runtime,
+ NULL,
+};
+
+static const struct usb_qualifier_descriptor dev_qualifier = {
+ .bLength = sizeof dev_qualifier,
+ .bDescriptorType = USB_DT_DEVICE_QUALIFIER,
+ .bcdUSB = __constant_cpu_to_le16(0x0200),
+ .bDeviceClass = USB_CLASS_VENDOR_SPEC,
+ .bNumConfigurations = 1,
+};
+
+static const char dfu_name[] = "Device Firmware Upgrade";
+
+/*
+ * static strings, in UTF-8
+ *
+ * dfu_generic configuration
+ */
+static struct usb_string strings_dfu_generic[] = {
+ [0].s = dfu_name,
+ { } /* end of list */
+};
+
+static struct usb_gadget_strings stringtab_dfu_generic = {
+ .language = 0x0409, /* en-us */
+ .strings = strings_dfu_generic,
+};
+
+static struct usb_gadget_strings *dfu_generic_strings[] = {
+ &stringtab_dfu_generic,
+ NULL,
+};
+
+/*
+ * usb_function specific
+ */
+static struct usb_gadget_strings stringtab_dfu = {
+ .language = 0x0409, /* en-us */
+ /*
+ * .strings
+ *
+ * assigned during initialization,
+ * depends on number of flash entities
+ *
+ */
+};
+
+static struct usb_gadget_strings *dfu_strings[] = {
+ &stringtab_dfu,
+ NULL,
+};
+
+/*-------------------------------------------------------------------------*/
+
+static void dnload_request_complete(struct usb_ep *ep, struct usb_request *req)
+{
+ struct f_dfu *f_dfu = req->context;
+
+ dfu_write(dfu_get_entity(f_dfu->altsetting), req->buf,
+ req->length, f_dfu->blk_seq_num);
+
+ if (req->length == 0)
+ puts("DOWNLOAD ... OK\nCtrl+C to exit ...\n");
+}
+
+static void handle_getstatus(struct usb_request *req)
+{
+ struct dfu_status *dstat = (struct dfu_status *)req->buf;
+ struct f_dfu *f_dfu = req->context;
+
+ switch (f_dfu->dfu_state) {
+ case DFU_STATE_dfuDNLOAD_SYNC:
+ case DFU_STATE_dfuDNBUSY:
+ f_dfu->dfu_state = DFU_STATE_dfuDNLOAD_IDLE;
+ break;
+ case DFU_STATE_dfuMANIFEST_SYNC:
+ break;
+ default:
+ break;
+ }
+
+ /* send status response */
+ dstat->bStatus = f_dfu->dfu_status;
+ dstat->bState = f_dfu->dfu_state;
+ dstat->iString = 0;
+}
+
+static void handle_getstate(struct usb_request *req)
+{
+ struct f_dfu *f_dfu = req->context;
+
+ ((u8 *)req->buf)[0] = f_dfu->dfu_state;
+ req->actual = sizeof(u8);
+}
+
+static inline void to_dfu_mode(struct f_dfu *f_dfu)
+{
+ f_dfu->usb_function.strings = dfu_strings;
+ f_dfu->usb_function.hs_descriptors = f_dfu->function;
+}
+
+static inline void to_runtime_mode(struct f_dfu *f_dfu)
+{
+ f_dfu->usb_function.strings = NULL;
+ f_dfu->usb_function.hs_descriptors = dfu_runtime_descs;
+}
+
+static int handle_upload(struct usb_request *req, u16 len)
+{
+ struct f_dfu *f_dfu = req->context;
+
+ return dfu_read(dfu_get_entity(f_dfu->altsetting), req->buf,
+ req->length, f_dfu->blk_seq_num);
+}
+
+static int handle_dnload(struct usb_gadget *gadget, u16 len)
+{
+ struct usb_composite_dev *cdev = get_gadget_data(gadget);
+ struct usb_request *req = cdev->req;
+ struct f_dfu *f_dfu = req->context;
+
+ if (len == 0)
+ f_dfu->dfu_state = DFU_STATE_dfuMANIFEST_SYNC;
+
+ req->complete = dnload_request_complete;
+
+ return len;
+}
+
+/*-------------------------------------------------------------------------*/
+/* DFU state machine */
+static int state_app_idle(struct f_dfu *f_dfu,
+ const struct usb_ctrlrequest *ctrl,
+ struct usb_gadget *gadget,
+ struct usb_request *req)
+{
+ int value = 0;
+
+ switch (ctrl->bRequest) {
+ case USB_REQ_DFU_GETSTATUS:
+ handle_getstatus(req);
+ value = RET_STAT_LEN;
+ break;
+ case USB_REQ_DFU_GETSTATE:
+ handle_getstate(req);
+ break;
+ case USB_REQ_DFU_DETACH:
+ f_dfu->dfu_state = DFU_STATE_appDETACH;
+ to_dfu_mode(f_dfu);
+ f_dfu->dfu_state = DFU_STATE_dfuIDLE;
+ value = RET_ZLP;
+ break;
+ default:
+ value = RET_STALL;
+ break;
+ }
+
+ return value;
+}
+
+static int state_app_detach(struct f_dfu *f_dfu,
+ const struct usb_ctrlrequest *ctrl,
+ struct usb_gadget *gadget,
+ struct usb_request *req)
+{
+ int value = 0;
+
+ switch (ctrl->bRequest) {
+ case USB_REQ_DFU_GETSTATUS:
+ handle_getstatus(req);
+ value = RET_STAT_LEN;
+ break;
+ case USB_REQ_DFU_GETSTATE:
+ handle_getstate(req);
+ break;
+ default:
+ f_dfu->dfu_state = DFU_STATE_appIDLE;
+ value = RET_STALL;
+ break;
+ }
+
+ return value;
+}
+
+static int state_dfu_idle(struct f_dfu *f_dfu,
+ const struct usb_ctrlrequest *ctrl,
+ struct usb_gadget *gadget,
+ struct usb_request *req)
+{
+ u16 w_value = le16_to_cpu(ctrl->wValue);
+ u16 len = le16_to_cpu(ctrl->wLength);
+ int value = 0;
+
+ switch (ctrl->bRequest) {
+ case USB_REQ_DFU_DNLOAD:
+ if (len == 0) {
+ f_dfu->dfu_state = DFU_STATE_dfuERROR;
+ value = RET_STALL;
+ break;
+ }
+ f_dfu->dfu_state = DFU_STATE_dfuDNLOAD_SYNC;
+ f_dfu->blk_seq_num = w_value;
+ value = handle_dnload(gadget, len);
+ break;
+ case USB_REQ_DFU_UPLOAD:
+ f_dfu->dfu_state = DFU_STATE_dfuUPLOAD_IDLE;
+ f_dfu->blk_seq_num = 0;
+ value = handle_upload(req, len);
+ break;
+ case USB_REQ_DFU_ABORT:
+ /* no zlp? */
+ value = RET_ZLP;
+ break;
+ case USB_REQ_DFU_GETSTATUS:
+ handle_getstatus(req);
+ value = RET_STAT_LEN;
+ break;
+ case USB_REQ_DFU_GETSTATE:
+ handle_getstate(req);
+ break;
+ case USB_REQ_DFU_DETACH:
+ /*
+ * Proprietary extension: 'detach' from idle mode and
+ * get back to runtime mode in case of USB Reset. As
+ * much as I dislike this, we just can't use every USB
+ * bus reset to switch back to runtime mode, since at
+ * least the Linux USB stack likes to send a number of
+ * resets in a row :(
+ */
+ f_dfu->dfu_state =
+ DFU_STATE_dfuMANIFEST_WAIT_RST;
+ to_runtime_mode(f_dfu);
+ f_dfu->dfu_state = DFU_STATE_appIDLE;
+ break;
+ default:
+ f_dfu->dfu_state = DFU_STATE_dfuERROR;
+ value = RET_STALL;
+ break;
+ }
+
+ return value;
+}
+
+static int state_dfu_dnload_sync(struct f_dfu *f_dfu,
+ const struct usb_ctrlrequest *ctrl,
+ struct usb_gadget *gadget,
+ struct usb_request *req)
+{
+ int value = 0;
+
+ switch (ctrl->bRequest) {
+ case USB_REQ_DFU_GETSTATUS:
+ handle_getstatus(req);
+ value = RET_STAT_LEN;
+ break;
+ case USB_REQ_DFU_GETSTATE:
+ handle_getstate(req);
+ break;
+ default:
+ f_dfu->dfu_state = DFU_STATE_dfuERROR;
+ value = RET_STALL;
+ break;
+ }
+
+ return value;
+}
+
+static int state_dfu_dnbusy(struct f_dfu *f_dfu,
+ const struct usb_ctrlrequest *ctrl,
+ struct usb_gadget *gadget,
+ struct usb_request *req)
+{
+ int value = 0;
+
+ switch (ctrl->bRequest) {
+ case USB_REQ_DFU_GETSTATUS:
+ handle_getstatus(req);
+ value = RET_STAT_LEN;
+ break;
+ default:
+ f_dfu->dfu_state = DFU_STATE_dfuERROR;
+ value = RET_STALL;
+ break;
+ }
+
+ return value;
+}
+
+static int state_dfu_dnload_idle(struct f_dfu *f_dfu,
+ const struct usb_ctrlrequest *ctrl,
+ struct usb_gadget *gadget,
+ struct usb_request *req)
+{
+ u16 w_value = le16_to_cpu(ctrl->wValue);
+ u16 len = le16_to_cpu(ctrl->wLength);
+ int value = 0;
+
+ switch (ctrl->bRequest) {
+ case USB_REQ_DFU_DNLOAD:
+ f_dfu->dfu_state = DFU_STATE_dfuDNLOAD_SYNC;
+ f_dfu->blk_seq_num = w_value;
+ value = handle_dnload(gadget, len);
+ break;
+ case USB_REQ_DFU_ABORT:
+ f_dfu->dfu_state = DFU_STATE_dfuIDLE;
+ value = RET_ZLP;
+ break;
+ case USB_REQ_DFU_GETSTATUS:
+ handle_getstatus(req);
+ value = RET_STAT_LEN;
+ break;
+ case USB_REQ_DFU_GETSTATE:
+ handle_getstate(req);
+ break;
+ default:
+ f_dfu->dfu_state = DFU_STATE_dfuERROR;
+ value = RET_STALL;
+ break;
+ }
+
+ return value;
+}
+
+static int state_dfu_manifest_sync(struct f_dfu *f_dfu,
+ const struct usb_ctrlrequest *ctrl,
+ struct usb_gadget *gadget,
+ struct usb_request *req)
+{
+ int value = 0;
+
+ switch (ctrl->bRequest) {
+ case USB_REQ_DFU_GETSTATUS:
+ /* We're MainfestationTolerant */
+ f_dfu->dfu_state = DFU_STATE_dfuIDLE;
+ handle_getstatus(req);
+ f_dfu->blk_seq_num = 0;
+ value = RET_STAT_LEN;
+ break;
+ case USB_REQ_DFU_GETSTATE:
+ handle_getstate(req);
+ break;
+ default:
+ f_dfu->dfu_state = DFU_STATE_dfuERROR;
+ value = RET_STALL;
+ break;
+ }
+
+ return value;
+}
+
+static int state_dfu_upload_idle(struct f_dfu *f_dfu,
+ const struct usb_ctrlrequest *ctrl,
+ struct usb_gadget *gadget,
+ struct usb_request *req)
+{
+ u16 w_value = le16_to_cpu(ctrl->wValue);
+ u16 len = le16_to_cpu(ctrl->wLength);
+ int value = 0;
+
+ switch (ctrl->bRequest) {
+ case USB_REQ_DFU_UPLOAD:
+ /* state transition if less data then requested */
+ f_dfu->blk_seq_num = w_value;
+ value = handle_upload(req, len);
+ if (value >= 0 && value < len)
+ f_dfu->dfu_state = DFU_STATE_dfuIDLE;
+ break;
+ case USB_REQ_DFU_ABORT:
+ f_dfu->dfu_state = DFU_STATE_dfuIDLE;
+ /* no zlp? */
+ value = RET_ZLP;
+ break;
+ case USB_REQ_DFU_GETSTATUS:
+ handle_getstatus(req);
+ value = RET_STAT_LEN;
+ break;
+ case USB_REQ_DFU_GETSTATE:
+ handle_getstate(req);
+ break;
+ default:
+ f_dfu->dfu_state = DFU_STATE_dfuERROR;
+ value = RET_STALL;
+ break;
+ }
+
+ return value;
+}
+
+static int state_dfu_error(struct f_dfu *f_dfu,
+ const struct usb_ctrlrequest *ctrl,
+ struct usb_gadget *gadget,
+ struct usb_request *req)
+{
+ int value = 0;
+
+ switch (ctrl->bRequest) {
+ case USB_REQ_DFU_GETSTATUS:
+ handle_getstatus(req);
+ value = RET_STAT_LEN;
+ break;
+ case USB_REQ_DFU_GETSTATE:
+ handle_getstate(req);
+ break;
+ case USB_REQ_DFU_CLRSTATUS:
+ f_dfu->dfu_state = DFU_STATE_dfuIDLE;
+ f_dfu->dfu_status = DFU_STATUS_OK;
+ /* no zlp? */
+ value = RET_ZLP;
+ break;
+ default:
+ f_dfu->dfu_state = DFU_STATE_dfuERROR;
+ value = RET_STALL;
+ break;
+ }
+
+ return value;
+}
+
+static dfu_state_fn dfu_state[] = {
+ state_app_idle, /* DFU_STATE_appIDLE */
+ state_app_detach, /* DFU_STATE_appDETACH */
+ state_dfu_idle, /* DFU_STATE_dfuIDLE */
+ state_dfu_dnload_sync, /* DFU_STATE_dfuDNLOAD_SYNC */
+ state_dfu_dnbusy, /* DFU_STATE_dfuDNBUSY */
+ state_dfu_dnload_idle, /* DFU_STATE_dfuDNLOAD_IDLE */
+ state_dfu_manifest_sync, /* DFU_STATE_dfuMANIFEST_SYNC */
+ NULL, /* DFU_STATE_dfuMANIFEST */
+ NULL, /* DFU_STATE_dfuMANIFEST_WAIT_RST */
+ state_dfu_upload_idle, /* DFU_STATE_dfuUPLOAD_IDLE */
+ state_dfu_error /* DFU_STATE_dfuERROR */
+};
+
+static int
+dfu_handle(struct usb_function *f, const struct usb_ctrlrequest *ctrl)
+{
+ struct usb_gadget *gadget = f->config->cdev->gadget;
+ struct usb_request *req = f->config->cdev->req;
+ struct f_dfu *f_dfu = f->config->cdev->req->context;
+ u16 len = le16_to_cpu(ctrl->wLength);
+ u16 w_value = le16_to_cpu(ctrl->wValue);
+ int value = 0;
+ u8 req_type = ctrl->bRequestType & USB_TYPE_MASK;
+
+ debug("w_value: 0x%x len: 0x%x\n", w_value, len);
+ debug("req_type: 0x%x ctrl->bRequest: 0x%x f_dfu->dfu_state: 0x%x\n",
+ req_type, ctrl->bRequest, f_dfu->dfu_state);
+
+ if (req_type == USB_TYPE_STANDARD) {
+ if (ctrl->bRequest == USB_REQ_GET_DESCRIPTOR &&
+ (w_value >> 8) == DFU_DT_FUNC) {
+ value = min(len, (u16) sizeof(dfu_func));
+ memcpy(req->buf, &dfu_func, value);
+ }
+ } else /* DFU specific request */
+ value = dfu_state[f_dfu->dfu_state] (f_dfu, ctrl, gadget, req);
+
+ if (value >= 0) {
+ req->length = value;
+ req->zero = value < len;
+ value = usb_ep_queue(gadget->ep0, req, 0);
+ if (value < 0) {
+ debug("ep_queue --> %d\n", value);
+ req->status = 0;
+ }
+ }
+
+ return value;
+}
+
+/*-------------------------------------------------------------------------*/
+
+static int
+dfu_prepare_strings(struct f_dfu *f_dfu, int n)
+{
+ struct dfu_entity *de = NULL;
+ int i = 0;
+
+ f_dfu->strings = calloc(sizeof(struct usb_string), n + 1);
+ if (!f_dfu->strings)
+ goto enomem;
+
+ for (i = 0; i < n; ++i) {
+ de = dfu_get_entity(i);
+ f_dfu->strings[i].s = de->name;
+ }
+
+ f_dfu->strings[i].id = 0;
+ f_dfu->strings[i].s = NULL;
+
+ return 0;
+
+enomem:
+ while (i)
+ f_dfu->strings[--i].s = NULL;
+
+ free(f_dfu->strings);
+
+ return -ENOMEM;
+}
+
+static int dfu_prepare_function(struct f_dfu *f_dfu, int n)
+{
+ struct usb_interface_descriptor *d;
+ int i = 0;
+
+ f_dfu->function = calloc(sizeof(struct usb_descriptor_header *), n);
+ if (!f_dfu->function)
+ goto enomem;
+
+ for (i = 0; i < n; ++i) {
+ d = calloc(sizeof(*d), 1);
+ if (!d)
+ goto enomem;
+
+ d->bLength = sizeof(*d);
+ d->bDescriptorType = USB_DT_INTERFACE;
+ d->bAlternateSetting = i;
+ d->bNumEndpoints = 0;
+ d->bInterfaceClass = USB_CLASS_APP_SPEC;
+ d->bInterfaceSubClass = 1;
+ d->bInterfaceProtocol = 2;
+
+ f_dfu->function[i] = (struct usb_descriptor_header *)d;
+ }
+ f_dfu->function[i] = NULL;
+
+ return 0;
+
+enomem:
+ while (i) {
+ free(f_dfu->function[--i]);
+ f_dfu->function[i] = NULL;
+ }
+ free(f_dfu->function);
+
+ return -ENOMEM;
+}
+
+static int dfu_bind(struct usb_configuration *c, struct usb_function *f)
+{
+ struct usb_composite_dev *cdev = c->cdev;
+ struct f_dfu *f_dfu = func_to_dfu(f);
+ int alt_num = dfu_get_alt_number();
+ int rv, id, i;
+
+ id = usb_interface_id(c, f);
+ if (id < 0)
+ return id;
+ dfu_intf_runtime.bInterfaceNumber = id;
+
+ f_dfu->dfu_state = DFU_STATE_appIDLE;
+ f_dfu->dfu_status = DFU_STATUS_OK;
+
+ rv = dfu_prepare_function(f_dfu, alt_num);
+ if (rv)
+ goto error;
+
+ rv = dfu_prepare_strings(f_dfu, alt_num);
+ if (rv)
+ goto error;
+ for (i = 0; i < alt_num; i++) {
+ id = usb_string_id(cdev);
+ if (id < 0)
+ return id;
+ f_dfu->strings[i].id = id;
+ ((struct usb_interface_descriptor *)f_dfu->function[i])
+ ->iInterface = id;
+ }
+
+ stringtab_dfu.strings = f_dfu->strings;
+
+ cdev->req->context = f_dfu;
+
+error:
+ return rv;
+}
+
+static void dfu_unbind(struct usb_configuration *c, struct usb_function *f)
+{
+ struct f_dfu *f_dfu = func_to_dfu(f);
+ int alt_num = dfu_get_alt_number();
+ int i;
+
+ if (f_dfu->strings) {
+ i = alt_num;
+ while (i)
+ f_dfu->strings[--i].s = NULL;
+
+ free(f_dfu->strings);
+ }
+
+ if (f_dfu->function) {
+ i = alt_num;
+ while (i) {
+ free(f_dfu->function[--i]);
+ f_dfu->function[i] = NULL;
+ }
+ free(f_dfu->function);
+ }
+
+ free(f_dfu);
+}
+
+static int dfu_set_alt(struct usb_function *f, unsigned intf, unsigned alt)
+{
+ struct f_dfu *f_dfu = func_to_dfu(f);
+
+ debug("%s: intf:%d alt:%d\n", __func__, intf, alt);
+
+ f_dfu->altsetting = alt;
+
+ return 0;
+}
+
+/* TODO: is this really what we need here? */
+static void dfu_disable(struct usb_function *f)
+{
+ struct f_dfu *f_dfu = func_to_dfu(f);
+ if (f_dfu->config == 0)
+ return;
+
+ debug("%s: reset config\n", __func__);
+
+ f_dfu->config = 0;
+}
+
+static int dfu_bind_config(struct usb_configuration *c)
+{
+ struct f_dfu *f_dfu;
+ int status;
+
+ f_dfu = calloc(sizeof(*f_dfu), 1);
+ if (!f_dfu)
+ return -ENOMEM;
+ f_dfu->usb_function.name = "dfu";
+ f_dfu->usb_function.hs_descriptors = dfu_runtime_descs;
+ f_dfu->usb_function.bind = dfu_bind;
+ f_dfu->usb_function.unbind = dfu_unbind;
+ f_dfu->usb_function.set_alt = dfu_set_alt;
+ f_dfu->usb_function.disable = dfu_disable;
+ f_dfu->usb_function.strings = dfu_generic_strings,
+ f_dfu->usb_function.setup = dfu_handle,
+
+ status = usb_add_function(c, &f_dfu->usb_function);
+ if (status)
+ free(f_dfu);
+
+ return status;
+}
+
+int dfu_add(struct usb_configuration *c)
+{
+ int id;
+
+ id = usb_string_id(c->cdev);
+ if (id < 0)
+ return id;
+ strings_dfu_generic[0].id = id;
+ dfu_intf_runtime.iInterface = id;
+
+ debug("%s: cdev: 0x%p gadget:0x%p gadget->ep0: 0x%p\n", __func__,
+ c->cdev, c->cdev->gadget, c->cdev->gadget->ep0);
+
+ return dfu_bind_config(c);
+}
--- /dev/null
+/*
+ * f_dfu.h -- Device Firmware Update gadget
+ *
+ * Copyright (C) 2011-2012 Samsung Electronics
+ * author: Andrzej Pietrasiewicz <andrzej.p@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __F_DFU_H_
+#define __F_DFU_H_
+
+#include <linux/compiler.h>
+#include <linux/usb/composite.h>
+
+#define DFU_CONFIG_VAL 1
+#define DFU_DT_FUNC 0x21
+
+#define DFU_BIT_WILL_DETACH (0x1 << 3)
+#define DFU_BIT_MANIFESTATION_TOLERANT (0x1 << 2)
+#define DFU_BIT_CAN_UPLOAD (0x1 << 1)
+#define DFU_BIT_CAN_DNLOAD 0x1
+
+/* big enough to hold our biggest descriptor */
+#define DFU_USB_BUFSIZ 4096
+
+#define USB_REQ_DFU_DETACH 0x00
+#define USB_REQ_DFU_DNLOAD 0x01
+#define USB_REQ_DFU_UPLOAD 0x02
+#define USB_REQ_DFU_GETSTATUS 0x03
+#define USB_REQ_DFU_CLRSTATUS 0x04
+#define USB_REQ_DFU_GETSTATE 0x05
+#define USB_REQ_DFU_ABORT 0x06
+
+#define DFU_STATUS_OK 0x00
+#define DFU_STATUS_errTARGET 0x01
+#define DFU_STATUS_errFILE 0x02
+#define DFU_STATUS_errWRITE 0x03
+#define DFU_STATUS_errERASE 0x04
+#define DFU_STATUS_errCHECK_ERASED 0x05
+#define DFU_STATUS_errPROG 0x06
+#define DFU_STATUS_errVERIFY 0x07
+#define DFU_STATUS_errADDRESS 0x08
+#define DFU_STATUS_errNOTDONE 0x09
+#define DFU_STATUS_errFIRMWARE 0x0a
+#define DFU_STATUS_errVENDOR 0x0b
+#define DFU_STATUS_errUSBR 0x0c
+#define DFU_STATUS_errPOR 0x0d
+#define DFU_STATUS_errUNKNOWN 0x0e
+#define DFU_STATUS_errSTALLEDPKT 0x0f
+
+#define RET_STALL -1
+#define RET_ZLP 0
+#define RET_STAT_LEN 6
+
+enum dfu_state {
+ DFU_STATE_appIDLE = 0,
+ DFU_STATE_appDETACH = 1,
+ DFU_STATE_dfuIDLE = 2,
+ DFU_STATE_dfuDNLOAD_SYNC = 3,
+ DFU_STATE_dfuDNBUSY = 4,
+ DFU_STATE_dfuDNLOAD_IDLE = 5,
+ DFU_STATE_dfuMANIFEST_SYNC = 6,
+ DFU_STATE_dfuMANIFEST = 7,
+ DFU_STATE_dfuMANIFEST_WAIT_RST = 8,
+ DFU_STATE_dfuUPLOAD_IDLE = 9,
+ DFU_STATE_dfuERROR = 10,
+};
+
+struct dfu_status {
+ __u8 bStatus;
+ __u8 bwPollTimeout[3];
+ __u8 bState;
+ __u8 iString;
+} __packed;
+
+struct dfu_function_descriptor {
+ __u8 bLength;
+ __u8 bDescriptorType;
+ __u8 bmAttributes;
+ __le16 wDetachTimeOut;
+ __le16 wTransferSize;
+ __le16 bcdDFUVersion;
+} __packed;
+
+/* configuration-specific linkup */
+int dfu_add(struct usb_configuration *c);
+#endif /* __F_DFU_H_ */
--- /dev/null
+/*
+ * g_dnl.c -- USB Downloader Gadget
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ * Lukasz Majewski <l.majewski@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <errno.h>
+#include <common.h>
+#include <malloc.h>
+
+#include <mmc.h>
+#include <part.h>
+
+#include <g_dnl.h>
+#include "f_dfu.h"
+
+#include "gadget_chips.h"
+#include "composite.c"
+
+/*
+ * One needs to define the following:
+ * CONFIG_G_DNL_VENDOR_NUM
+ * CONFIG_G_DNL_PRODUCT_NUM
+ * CONFIG_G_DNL_MANUFACTURER
+ * at e.g. ./include/configs/<board>.h
+ */
+
+#define STRING_MANUFACTURER 25
+#define STRING_PRODUCT 2
+#define STRING_USBDOWN 2
+#define CONFIG_USBDOWNLOADER 2
+
+#define DRIVER_VERSION "usb_dnl 2.0"
+
+static const char shortname[] = "usb_dnl_";
+static const char product[] = "USB download gadget";
+static const char manufacturer[] = CONFIG_G_DNL_MANUFACTURER;
+
+static struct usb_device_descriptor device_desc = {
+ .bLength = sizeof device_desc,
+ .bDescriptorType = USB_DT_DEVICE,
+
+ .bcdUSB = __constant_cpu_to_le16(0x0200),
+ .bDeviceClass = USB_CLASS_COMM,
+ .bDeviceSubClass = 0x02, /*0x02:CDC-modem , 0x00:CDC-serial*/
+
+ .idVendor = __constant_cpu_to_le16(CONFIG_G_DNL_VENDOR_NUM),
+ .idProduct = __constant_cpu_to_le16(CONFIG_G_DNL_PRODUCT_NUM),
+ .iProduct = STRING_PRODUCT,
+ .bNumConfigurations = 1,
+};
+
+/* static strings, in UTF-8 */
+static struct usb_string g_dnl_string_defs[] = {
+ { 0, manufacturer, },
+ { 1, product, },
+};
+
+static struct usb_gadget_strings g_dnl_string_tab = {
+ .language = 0x0409, /* en-us */
+ .strings = g_dnl_string_defs,
+};
+
+static struct usb_gadget_strings *g_dnl_composite_strings[] = {
+ &g_dnl_string_tab,
+ NULL,
+};
+
+static int g_dnl_unbind(struct usb_composite_dev *cdev)
+{
+ debug("%s\n", __func__);
+ return 0;
+}
+
+static int g_dnl_do_config(struct usb_configuration *c)
+{
+ const char *s = c->cdev->driver->name;
+ int ret = -1;
+
+ debug("%s: configuration: 0x%p composite dev: 0x%p\n",
+ __func__, c, c->cdev);
+
+ printf("GADGET DRIVER: %s\n", s);
+ if (!strcmp(s, "usb_dnl_dfu"))
+ ret = dfu_add(c);
+
+ return ret;
+}
+
+static int g_dnl_config_register(struct usb_composite_dev *cdev)
+{
+ static struct usb_configuration config = {
+ .label = "usb_dnload",
+ .bmAttributes = USB_CONFIG_ATT_ONE | USB_CONFIG_ATT_SELFPOWER,
+ .bConfigurationValue = CONFIG_USBDOWNLOADER,
+ .iConfiguration = STRING_USBDOWN,
+
+ .bind = g_dnl_do_config,
+ };
+
+ return usb_add_config(cdev, &config);
+}
+
+static int g_dnl_bind(struct usb_composite_dev *cdev)
+{
+ struct usb_gadget *gadget = cdev->gadget;
+ int id, ret;
+ int gcnum;
+
+ debug("%s: gadget: 0x%p cdev: 0x%p\n", __func__, gadget, cdev);
+
+ id = usb_string_id(cdev);
+
+ if (id < 0)
+ return id;
+ g_dnl_string_defs[0].id = id;
+ device_desc.iManufacturer = id;
+
+ id = usb_string_id(cdev);
+ if (id < 0)
+ return id;
+
+ g_dnl_string_defs[1].id = id;
+ device_desc.iProduct = id;
+
+ ret = g_dnl_config_register(cdev);
+ if (ret)
+ goto error;
+
+ gcnum = usb_gadget_controller_number(gadget);
+
+ debug("gcnum: %d\n", gcnum);
+ if (gcnum >= 0)
+ device_desc.bcdDevice = cpu_to_le16(0x0200 + gcnum);
+ else {
+ debug("%s: controller '%s' not recognized\n",
+ shortname, gadget->name);
+ device_desc.bcdDevice = __constant_cpu_to_le16(0x9999);
+ }
+
+ return 0;
+
+ error:
+ g_dnl_unbind(cdev);
+ return -ENOMEM;
+}
+
+static struct usb_composite_driver g_dnl_driver = {
+ .name = NULL,
+ .dev = &device_desc,
+ .strings = g_dnl_composite_strings,
+
+ .bind = g_dnl_bind,
+ .unbind = g_dnl_unbind,
+};
+
+int g_dnl_register(const char *type)
+{
+ /* We only allow "dfu" atm, so 3 should be enough */
+ static char name[sizeof(shortname) + 3];
+ int ret;
+
+ if (!strcmp(type, "dfu")) {
+ strcpy(name, shortname);
+ strcat(name, type);
+ } else {
+ printf("%s: unknown command: %s\n", __func__, type);
+ return -EINVAL;
+ }
+
+ g_dnl_driver.name = name;
+
+ debug("%s: g_dnl_driver.name: %s\n", __func__, g_dnl_driver.name);
+ ret = usb_composite_register(&g_dnl_driver);
+
+ if (ret) {
+ printf("%s: failed!, error: %d\n", __func__, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+void g_dnl_unregister(void)
+{
+ usb_composite_unregister(&g_dnl_driver);
+}
*/
#include <common.h>
#include <asm/byteorder.h>
+#include <asm/unaligned.h>
#include <usb.h>
#include <asm/io.h>
#include <malloc.h>
#ifdef CONFIG_USB_EHCI_TXFIFO_THRESH
cmd = ehci_readl(&hcor->or_txfilltuning);
- cmd &= ~TXFIFO_THRESH(0x3f);
+ cmd &= ~TXFIFO_THRESH_MASK;
cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH);
ehci_writel(&hcor->or_txfilltuning, cmd);
#endif
flush_dcache_range(addr, ALIGN(addr + sz, ARCH_DMA_MINALIGN));
idx = 0;
- while (idx < 5) {
+ while (idx < QT_BUFFER_CNT) {
td->qt_buffer[idx] = cpu_to_hc32(addr);
td->qt_buffer_hi[idx] = 0;
- next = (addr + 4096) & ~4095;
+ next = (addr + EHCI_PAGE_SIZE) & ~(EHCI_PAGE_SIZE - 1);
delta = next - addr;
if (delta >= sz)
break;
idx++;
}
- if (idx == 5) {
+ if (idx == QT_BUFFER_CNT) {
printf("out of buffer pointers (%u bytes left)\n", sz);
return -1;
}
int length, struct devrequest *req)
{
ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN);
- ALLOC_ALIGN_BUFFER(struct qTD, qtd, 3, USB_DMA_MINALIGN);
+ struct qTD *qtd;
+ int qtd_count = 0;
int qtd_counter = 0;
volatile struct qTD *vtd;
unsigned long ts;
uint32_t *tdp;
- uint32_t endpt, token, usbsts;
+ uint32_t endpt, maxpacket, token, usbsts;
uint32_t c, toggle;
uint32_t cmd;
int timeout;
le16_to_cpu(req->value), le16_to_cpu(req->value),
le16_to_cpu(req->index));
+#define PKT_ALIGN 512
+ /*
+ * The USB transfer is split into qTD transfers. Eeach qTD transfer is
+ * described by a transfer descriptor (the qTD). The qTDs form a linked
+ * list with a queue head (QH).
+ *
+ * Each qTD transfer starts with a new USB packet, i.e. a packet cannot
+ * have its beginning in a qTD transfer and its end in the following
+ * one, so the qTD transfer lengths have to be chosen accordingly.
+ *
+ * Each qTD transfer uses up to QT_BUFFER_CNT data buffers, mapped to
+ * single pages. The first data buffer can start at any offset within a
+ * page (not considering the cache-line alignment issues), while the
+ * following buffers must be page-aligned. There is no alignment
+ * constraint on the size of a qTD transfer.
+ */
+ if (req != NULL)
+ /* 1 qTD will be needed for SETUP, and 1 for ACK. */
+ qtd_count += 1 + 1;
+ if (length > 0 || req == NULL) {
+ /*
+ * Determine the qTD transfer size that will be used for the
+ * data payload (not considering the first qTD transfer, which
+ * may be longer or shorter, and the final one, which may be
+ * shorter).
+ *
+ * In order to keep each packet within a qTD transfer, the qTD
+ * transfer size is aligned to PKT_ALIGN, which is a multiple of
+ * wMaxPacketSize (except in some cases for interrupt transfers,
+ * see comment in submit_int_msg()).
+ *
+ * By default, i.e. if the input buffer is aligned to PKT_ALIGN,
+ * QT_BUFFER_CNT full pages will be used.
+ */
+ int xfr_sz = QT_BUFFER_CNT;
+ /*
+ * However, if the input buffer is not aligned to PKT_ALIGN, the
+ * qTD transfer size will be one page shorter, and the first qTD
+ * data buffer of each transfer will be page-unaligned.
+ */
+ if ((uint32_t)buffer & (PKT_ALIGN - 1))
+ xfr_sz--;
+ /* Convert the qTD transfer size to bytes. */
+ xfr_sz *= EHCI_PAGE_SIZE;
+ /*
+ * Approximate by excess the number of qTDs that will be
+ * required for the data payload. The exact formula is way more
+ * complicated and saves at most 2 qTDs, i.e. a total of 128
+ * bytes.
+ */
+ qtd_count += 2 + length / xfr_sz;
+ }
+/*
+ * Threshold value based on the worst-case total size of the allocated qTDs for
+ * a mass-storage transfer of 65535 blocks of 512 bytes.
+ */
+#if CONFIG_SYS_MALLOC_LEN <= 64 + 128 * 1024
+#warning CONFIG_SYS_MALLOC_LEN may be too small for EHCI
+#endif
+ qtd = memalign(USB_DMA_MINALIGN, qtd_count * sizeof(struct qTD));
+ if (qtd == NULL) {
+ printf("unable to allocate TDs\n");
+ return -1;
+ }
+
memset(qh, 0, sizeof(struct QH));
- memset(qtd, 0, 3 * sizeof(*qtd));
+ memset(qtd, 0, qtd_count * sizeof(*qtd));
toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
* - qh_overlay.qt_altnext
*/
qh->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH);
- c = (usb_pipespeed(pipe) != USB_SPEED_HIGH &&
- usb_pipeendpoint(pipe) == 0) ? 1 : 0;
- endpt = (8 << 28) |
- (c << 27) |
- (usb_maxpacket(dev, pipe) << 16) |
- (0 << 15) |
- (1 << 14) |
- (usb_pipespeed(pipe) << 12) |
- (usb_pipeendpoint(pipe) << 8) |
- (0 << 7) | (usb_pipedevice(pipe) << 0);
+ c = usb_pipespeed(pipe) != USB_SPEED_HIGH && !usb_pipeendpoint(pipe);
+ maxpacket = usb_maxpacket(dev, pipe);
+ endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) |
+ QH_ENDPT1_MAXPKTLEN(maxpacket) | QH_ENDPT1_H(0) |
+ QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD) |
+ QH_ENDPT1_EPS(usb_pipespeed(pipe)) |
+ QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) |
+ QH_ENDPT1_DEVADDR(usb_pipedevice(pipe));
qh->qh_endpt1 = cpu_to_hc32(endpt);
- endpt = (1 << 30) |
- (dev->portnr << 23) |
- (dev->parent->devnum << 16) | (0 << 8) | (0 << 0);
+ endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_PORTNUM(dev->portnr) |
+ QH_ENDPT2_HUBADDR(dev->parent->devnum) |
+ QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0);
qh->qh_endpt2 = cpu_to_hc32(endpt);
qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
*/
qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
- token = (0 << 31) |
- (sizeof(*req) << 16) |
- (0 << 15) | (0 << 12) | (3 << 10) | (2 << 8) | (0x80 << 0);
+ token = QT_TOKEN_DT(0) | QT_TOKEN_TOTALBYTES(sizeof(*req)) |
+ QT_TOKEN_IOC(0) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
+ QT_TOKEN_PID(QT_TOKEN_PID_SETUP) |
+ QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
qtd[qtd_counter].qt_token = cpu_to_hc32(token);
- if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req)) != 0) {
- printf("unable construct SETUP td\n");
+ if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req))) {
+ printf("unable to construct SETUP TD\n");
goto fail;
}
/* Update previous qTD! */
}
if (length > 0 || req == NULL) {
- /*
- * Setup request qTD (3.5 in ehci-r10.pdf)
- *
- * qt_next ................ 03-00 H
- * qt_altnext ............. 07-04 H
- * qt_token ............... 0B-08 H
- *
- * [ buffer, buffer_hi ] loaded with "buffer".
- */
- qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
- qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
- token = (toggle << 31) |
- (length << 16) |
- ((req == NULL ? 1 : 0) << 15) |
- (0 << 12) |
- (3 << 10) |
- ((usb_pipein(pipe) ? 1 : 0) << 8) | (0x80 << 0);
- qtd[qtd_counter].qt_token = cpu_to_hc32(token);
- if (ehci_td_buffer(&qtd[qtd_counter], buffer, length) != 0) {
- printf("unable construct DATA td\n");
- goto fail;
- }
- /* Update previous qTD! */
- *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]);
- tdp = &qtd[qtd_counter++].qt_next;
+ uint8_t *buf_ptr = buffer;
+ int left_length = length;
+
+ do {
+ /*
+ * Determine the size of this qTD transfer. By default,
+ * QT_BUFFER_CNT full pages can be used.
+ */
+ int xfr_bytes = QT_BUFFER_CNT * EHCI_PAGE_SIZE;
+ /*
+ * However, if the input buffer is not page-aligned, the
+ * portion of the first page before the buffer start
+ * offset within that page is unusable.
+ */
+ xfr_bytes -= (uint32_t)buf_ptr & (EHCI_PAGE_SIZE - 1);
+ /*
+ * In order to keep each packet within a qTD transfer,
+ * align the qTD transfer size to PKT_ALIGN.
+ */
+ xfr_bytes &= ~(PKT_ALIGN - 1);
+ /*
+ * This transfer may be shorter than the available qTD
+ * transfer size that has just been computed.
+ */
+ xfr_bytes = min(xfr_bytes, left_length);
+
+ /*
+ * Setup request qTD (3.5 in ehci-r10.pdf)
+ *
+ * qt_next ................ 03-00 H
+ * qt_altnext ............. 07-04 H
+ * qt_token ............... 0B-08 H
+ *
+ * [ buffer, buffer_hi ] loaded with "buffer".
+ */
+ qtd[qtd_counter].qt_next =
+ cpu_to_hc32(QT_NEXT_TERMINATE);
+ qtd[qtd_counter].qt_altnext =
+ cpu_to_hc32(QT_NEXT_TERMINATE);
+ token = QT_TOKEN_DT(toggle) |
+ QT_TOKEN_TOTALBYTES(xfr_bytes) |
+ QT_TOKEN_IOC(req == NULL) | QT_TOKEN_CPAGE(0) |
+ QT_TOKEN_CERR(3) |
+ QT_TOKEN_PID(usb_pipein(pipe) ?
+ QT_TOKEN_PID_IN : QT_TOKEN_PID_OUT) |
+ QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
+ qtd[qtd_counter].qt_token = cpu_to_hc32(token);
+ if (ehci_td_buffer(&qtd[qtd_counter], buf_ptr,
+ xfr_bytes)) {
+ printf("unable to construct DATA TD\n");
+ goto fail;
+ }
+ /* Update previous qTD! */
+ *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]);
+ tdp = &qtd[qtd_counter++].qt_next;
+ /*
+ * Data toggle has to be adjusted since the qTD transfer
+ * size is not always an even multiple of
+ * wMaxPacketSize.
+ */
+ if ((xfr_bytes / maxpacket) & 1)
+ toggle ^= 1;
+ buf_ptr += xfr_bytes;
+ left_length -= xfr_bytes;
+ } while (left_length > 0);
}
if (req != NULL) {
*/
qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
- token = (toggle << 31) |
- (0 << 16) |
- (1 << 15) |
- (0 << 12) |
- (3 << 10) |
- ((usb_pipein(pipe) ? 0 : 1) << 8) | (0x80 << 0);
+ token = QT_TOKEN_DT(1) | QT_TOKEN_TOTALBYTES(0) |
+ QT_TOKEN_IOC(1) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
+ QT_TOKEN_PID(usb_pipein(pipe) ?
+ QT_TOKEN_PID_OUT : QT_TOKEN_PID_IN) |
+ QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
qtd[qtd_counter].qt_token = cpu_to_hc32(token);
/* Update previous qTD! */
*tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]);
flush_dcache_range((uint32_t)qh_list,
ALIGN_END_ADDR(struct QH, qh_list, 1));
flush_dcache_range((uint32_t)qh, ALIGN_END_ADDR(struct QH, qh, 1));
- flush_dcache_range((uint32_t)qtd, ALIGN_END_ADDR(struct qTD, qtd, 3));
+ flush_dcache_range((uint32_t)qtd,
+ ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
/* Set async. queue head pointer. */
ehci_writel(&hcor->or_asynclistaddr, (uint32_t)qh_list);
cmd |= CMD_ASE;
ehci_writel(&hcor->or_usbcmd, cmd);
- ret = handshake((uint32_t *)&hcor->or_usbsts, STD_ASS, STD_ASS,
+ ret = handshake((uint32_t *)&hcor->or_usbsts, STS_ASS, STS_ASS,
100 * 1000);
if (ret < 0) {
- printf("EHCI fail timeout STD_ASS set\n");
+ printf("EHCI fail timeout STS_ASS set\n");
goto fail;
}
invalidate_dcache_range((uint32_t)qh,
ALIGN_END_ADDR(struct QH, qh, 1));
invalidate_dcache_range((uint32_t)qtd,
- ALIGN_END_ADDR(struct qTD, qtd, 3));
+ ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
token = hc32_to_cpu(vtd->qt_token);
- if (!(token & 0x80))
+ if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE))
break;
WATCHDOG_RESET();
} while (get_timer(ts) < timeout);
ALIGN((uint32_t)buffer + length, ARCH_DMA_MINALIGN));
/* Check that the TD processing happened */
- if (token & 0x80) {
+ if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)
printf("EHCI timed out on TD - token=%#x\n", token);
- }
/* Disable async schedule. */
cmd = ehci_readl(&hcor->or_usbcmd);
cmd &= ~CMD_ASE;
ehci_writel(&hcor->or_usbcmd, cmd);
- ret = handshake((uint32_t *)&hcor->or_usbsts, STD_ASS, 0,
+ ret = handshake((uint32_t *)&hcor->or_usbsts, STS_ASS, 0,
100 * 1000);
if (ret < 0) {
- printf("EHCI fail timeout STD_ASS reset\n");
+ printf("EHCI fail timeout STS_ASS reset\n");
goto fail;
}
token = hc32_to_cpu(qh->qh_overlay.qt_token);
- if (!(token & 0x80)) {
+ if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)) {
debug("TOKEN=%#x\n", token);
- switch (token & 0xfc) {
+ switch (QT_TOKEN_GET_STATUS(token) &
+ ~(QT_TOKEN_STATUS_SPLITXSTATE | QT_TOKEN_STATUS_PERR)) {
case 0:
- toggle = token >> 31;
+ toggle = QT_TOKEN_GET_DT(token);
usb_settoggle(dev, usb_pipeendpoint(pipe),
usb_pipeout(pipe), toggle);
dev->status = 0;
break;
- case 0x40:
+ case QT_TOKEN_STATUS_HALTED:
dev->status = USB_ST_STALLED;
break;
- case 0xa0:
- case 0x20:
+ case QT_TOKEN_STATUS_ACTIVE | QT_TOKEN_STATUS_DATBUFERR:
+ case QT_TOKEN_STATUS_DATBUFERR:
dev->status = USB_ST_BUF_ERR;
break;
- case 0x50:
- case 0x10:
+ case QT_TOKEN_STATUS_HALTED | QT_TOKEN_STATUS_BABBLEDET:
+ case QT_TOKEN_STATUS_BABBLEDET:
dev->status = USB_ST_BABBLE_DET;
break;
default:
dev->status = USB_ST_CRC_ERR;
- if ((token & 0x40) == 0x40)
+ if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_HALTED)
dev->status |= USB_ST_STALLED;
break;
}
- dev->act_len = length - ((token >> 16) & 0x7fff);
+ dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(token);
} else {
dev->act_len = 0;
debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
ehci_readl(&hcor->or_portsc[1]));
}
+ free(qtd);
return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
fail:
+ free(qtd);
return -1;
}
case USB_DT_DEVICE:
debug("USB_DT_DEVICE request\n");
srcptr = &descriptor.device;
- srclen = 0x12;
+ srclen = descriptor.device.bLength;
break;
case USB_DT_CONFIG:
debug("USB_DT_CONFIG config\n");
srcptr = &descriptor.config;
- srclen = 0x19;
+ srclen = descriptor.config.bLength +
+ descriptor.interface.bLength +
+ descriptor.endpoint.bLength;
break;
case USB_DT_STRING:
debug("USB_DT_STRING config\n");
case USB_DT_HUB:
debug("USB_DT_HUB config\n");
srcptr = &descriptor.hub;
- srclen = 0x8;
+ srclen = descriptor.hub.bLength;
break;
default:
debug("unknown value %x\n", le16_to_cpu(req->value));
tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
if (ehci_is_TDI()) {
- switch ((reg >> 26) & 3) {
- case 0:
+ switch (PORTSC_PSPD(reg)) {
+ case PORTSC_PSPD_FS:
break;
- case 1:
+ case PORTSC_PSPD_LS:
tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
break;
- case 2:
+ case PORTSC_PSPD_HS:
default:
tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
break;
uint32_t reg;
uint32_t cmd;
- if (ehci_hcd_init() != 0)
+ if (ehci_hcd_init())
return -1;
/* EHCI spec section 4.1 */
- if (ehci_reset() != 0)
+ if (ehci_reset())
return -1;
#if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
- if (ehci_hcd_init() != 0)
+ if (ehci_hcd_init())
return -1;
#endif
/* Set head of reclaim list */
memset(qh_list, 0, sizeof(*qh_list));
qh_list->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH);
- qh_list->qh_endpt1 = cpu_to_hc32((1 << 15) | (USB_SPEED_HIGH << 12));
+ qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) |
+ QH_ENDPT1_EPS(USB_SPEED_HIGH));
qh_list->qh_curtd = cpu_to_hc32(QT_NEXT_TERMINATE);
qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
- qh_list->qh_overlay.qt_token = cpu_to_hc32(0x40);
+ qh_list->qh_overlay.qt_token =
+ cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED));
reg = ehci_readl(&hccr->cr_hcsparams);
descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
/* Port Indicators */
if (HCS_INDICATOR(reg))
- descriptor.hub.wHubCharacteristics |= 0x80;
+ put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
+ | 0x80, &descriptor.hub.wHubCharacteristics);
/* Port Power Control */
if (HCS_PPC(reg))
- descriptor.hub.wHubCharacteristics |= 0x01;
+ put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
+ | 0x01, &descriptor.hub.wHubCharacteristics);
/* Start the host controller. */
cmd = ehci_readl(&hcor->or_usbcmd);
}
if (usb_pipedevice(pipe) == rootdev) {
- if (rootdev == 0)
+ if (!rootdev)
dev->speed = USB_SPEED_HIGH;
return ehci_submit_root(dev, pipe, buffer, length, setup);
}
submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
int length, int interval)
{
-
debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
dev, pipe, buffer, length, interval);
+
+ /*
+ * Interrupt transfers requiring several transactions are not supported
+ * because bInterval is ignored.
+ *
+ * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2
+ * <= PKT_ALIGN if several qTDs are required, while the USB
+ * specification does not constrain this for interrupt transfers. That
+ * means that ehci_submit_async() would support interrupt transfers
+ * requiring several transactions only as long as the transfer size does
+ * not require more than a single qTD.
+ */
+ if (length > usb_maxpacket(dev, pipe)) {
+ printf("%s: Interrupt transfers requiring several transactions "
+ "are not supported.\n", __func__);
+ return -1;
+ }
return ehci_submit_async(dev, pipe, buffer, length, NULL);
}
#define CMD_RESET (1 << 1) /* reset HC not bus */
#define CMD_RUN (1 << 0) /* start/stop HC */
uint32_t or_usbsts;
-#define STD_ASS (1 << 15)
+#define STS_ASS (1 << 15)
#define STS_HALT (1 << 12)
uint32_t or_usbintr;
#define INTR_UE (1 << 0) /* USB interrupt enable */
uint32_t _reserved_0_;
uint32_t or_burstsize;
uint32_t or_txfilltuning;
+#define TXFIFO_THRESH_MASK (0x3f << 16)
#define TXFIFO_THRESH(p) ((p & 0x3f) << 16)
uint32_t _reserved_1_[6];
uint32_t or_configflag;
#define FLAG_CF (1 << 0) /* true: we'll support "high speed" */
uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS];
+#define PORTSC_PSPD(x) (((x) >> 26) & 0x3)
+#define PORTSC_PSPD_FS 0x0
+#define PORTSC_PSPD_LS 0x1
+#define PORTSC_PSPD_HS 0x2
uint32_t or_systune;
} __attribute__ ((packed, aligned(4)));
/* Queue Element Transfer Descriptor (qTD). */
struct qTD {
/* this part defined by EHCI spec */
- uint32_t qt_next; /* see EHCI 3.5.1 */
+ uint32_t qt_next; /* see EHCI 3.5.1 */
#define QT_NEXT_TERMINATE 1
- uint32_t qt_altnext; /* see EHCI 3.5.2 */
- uint32_t qt_token; /* see EHCI 3.5.3 */
- uint32_t qt_buffer[5]; /* see EHCI 3.5.4 */
- uint32_t qt_buffer_hi[5]; /* Appendix B */
+ uint32_t qt_altnext; /* see EHCI 3.5.2 */
+ uint32_t qt_token; /* see EHCI 3.5.3 */
+#define QT_TOKEN_DT(x) (((x) & 0x1) << 31) /* Data Toggle */
+#define QT_TOKEN_GET_DT(x) (((x) >> 31) & 0x1)
+#define QT_TOKEN_TOTALBYTES(x) (((x) & 0x7fff) << 16) /* Total Bytes to Transfer */
+#define QT_TOKEN_GET_TOTALBYTES(x) (((x) >> 16) & 0x7fff)
+#define QT_TOKEN_IOC(x) (((x) & 0x1) << 15) /* Interrupt On Complete */
+#define QT_TOKEN_CPAGE(x) (((x) & 0x7) << 12) /* Current Page */
+#define QT_TOKEN_CERR(x) (((x) & 0x3) << 10) /* Error Counter */
+#define QT_TOKEN_PID(x) (((x) & 0x3) << 8) /* PID Code */
+#define QT_TOKEN_PID_OUT 0x0
+#define QT_TOKEN_PID_IN 0x1
+#define QT_TOKEN_PID_SETUP 0x2
+#define QT_TOKEN_STATUS(x) (((x) & 0xff) << 0) /* Status */
+#define QT_TOKEN_GET_STATUS(x) (((x) >> 0) & 0xff)
+#define QT_TOKEN_STATUS_ACTIVE 0x80
+#define QT_TOKEN_STATUS_HALTED 0x40
+#define QT_TOKEN_STATUS_DATBUFERR 0x20
+#define QT_TOKEN_STATUS_BABBLEDET 0x10
+#define QT_TOKEN_STATUS_XACTERR 0x08
+#define QT_TOKEN_STATUS_MISSEDUFRAME 0x04
+#define QT_TOKEN_STATUS_SPLITXSTATE 0x02
+#define QT_TOKEN_STATUS_PERR 0x01
+#define QT_BUFFER_CNT 5
+ uint32_t qt_buffer[QT_BUFFER_CNT]; /* see EHCI 3.5.4 */
+ uint32_t qt_buffer_hi[QT_BUFFER_CNT]; /* Appendix B */
/* pad struct for 32 byte alignment */
uint32_t unused[3];
};
+#define EHCI_PAGE_SIZE 4096
+
/* Queue Head (QH). */
struct QH {
uint32_t qh_link;
#define QH_LINK_TYPE_SITD 4
#define QH_LINK_TYPE_FSTN 6
uint32_t qh_endpt1;
+#define QH_ENDPT1_RL(x) (((x) & 0xf) << 28) /* NAK Count Reload */
+#define QH_ENDPT1_C(x) (((x) & 0x1) << 27) /* Control Endpoint Flag */
+#define QH_ENDPT1_MAXPKTLEN(x) (((x) & 0x7ff) << 16) /* Maximum Packet Length */
+#define QH_ENDPT1_H(x) (((x) & 0x1) << 15) /* Head of Reclamation List Flag */
+#define QH_ENDPT1_DTC(x) (((x) & 0x1) << 14) /* Data Toggle Control */
+#define QH_ENDPT1_DTC_IGNORE_QTD_TD 0x0
+#define QH_ENDPT1_DTC_DT_FROM_QTD 0x1
+#define QH_ENDPT1_EPS(x) (((x) & 0x3) << 12) /* Endpoint Speed */
+#define QH_ENDPT1_EPS_FS 0x0
+#define QH_ENDPT1_EPS_LS 0x1
+#define QH_ENDPT1_EPS_HS 0x2
+#define QH_ENDPT1_ENDPT(x) (((x) & 0xf) << 8) /* Endpoint Number */
+#define QH_ENDPT1_I(x) (((x) & 0x1) << 7) /* Inactivate on Next Transaction */
+#define QH_ENDPT1_DEVADDR(x) (((x) & 0x7f) << 0) /* Device Address */
uint32_t qh_endpt2;
+#define QH_ENDPT2_MULT(x) (((x) & 0x3) << 30) /* High-Bandwidth Pipe Multiplier */
+#define QH_ENDPT2_PORTNUM(x) (((x) & 0x7f) << 23) /* Port Number */
+#define QH_ENDPT2_HUBADDR(x) (((x) & 0x7f) << 16) /* Hub Address */
+#define QH_ENDPT2_UFCMASK(x) (((x) & 0xff) << 8) /* Split Completion Mask */
+#define QH_ENDPT2_UFSMASK(x) (((x) & 0xff) << 0) /* Interrupt Schedule Mask */
uint32_t qh_curtd;
struct qTD qh_overlay;
/*
int leni = transfer_len;
int len = 0;
int stat = 0;
- __u32 datab[4];
- union {
- void *ptr;
- __u8 *u8;
- __u16 *u16;
- __u32 *u32;
- } databuf;
__u16 bmRType_bReq;
__u16 wValue;
__u16 wIndex;
__u16 wLength;
-
- databuf.u32 = (__u32 *)datab;
+ ALLOC_ALIGN_BUFFER(__u8, databuf, 16, sizeof(u32));
#ifdef DEBUG
pkt_print(NULL, dev, pipe, buffer, transfer_len,
*/
case RH_GET_STATUS:
- databuf.u16[0] = cpu_to_le16(1);
+ *(u16 *)databuf = cpu_to_le16(1);
OK(2);
case RH_GET_STATUS | RH_INTERFACE:
- databuf.u16[0] = cpu_to_le16(0);
+ *(u16 *)databuf = cpu_to_le16(0);
OK(2);
case RH_GET_STATUS | RH_ENDPOINT:
- databuf.u16[0] = cpu_to_le16(0);
+ *(u16 *)databuf = cpu_to_le16(0);
OK(2);
case RH_GET_STATUS | RH_CLASS:
- databuf.u32[0] = cpu_to_le32(
+ *(u32 *)databuf = cpu_to_le32(
RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
OK(4);
case RH_GET_STATUS | RH_OTHER | RH_CLASS:
- databuf.u32[0] = cpu_to_le32(RD_RH_PORTSTAT);
+ *(u32 *)databuf = cpu_to_le32(RD_RH_PORTSTAT);
OK(4);
case RH_CLEAR_FEATURE | RH_ENDPOINT:
min_t(unsigned int,
sizeof(root_hub_dev_des),
wLength));
- databuf.ptr = root_hub_dev_des; OK(len);
+ databuf = root_hub_dev_des; OK(len);
case (0x02): /* configuration descriptor */
len = min_t(unsigned int,
leni,
min_t(unsigned int,
sizeof(root_hub_config_des),
wLength));
- databuf.ptr = root_hub_config_des; OK(len);
+ databuf = root_hub_config_des; OK(len);
case (0x03): /* string descriptors */
if (wValue == 0x0300) {
len = min_t(unsigned int,
min_t(unsigned int,
sizeof(root_hub_str_index0),
wLength));
- databuf.ptr = root_hub_str_index0;
+ databuf = root_hub_str_index0;
OK(len);
}
if (wValue == 0x0301) {
min_t(unsigned int,
sizeof(root_hub_str_index1),
wLength));
- databuf.ptr = root_hub_str_index1;
+ databuf = root_hub_str_index1;
OK(len);
}
default:
{
__u32 temp = roothub_a(&gohci);
- databuf.u8[0] = 9; /* min length; */
- databuf.u8[1] = 0x29;
- databuf.u8[2] = temp & RH_A_NDP;
+ databuf[0] = 9; /* min length; */
+ databuf[1] = 0x29;
+ databuf[2] = temp & RH_A_NDP;
#ifdef CONFIG_AT91C_PQFP_UHPBUG
- databuf.u8[2] = (databuf.u8[2] == 2) ? 1 : 0;
+ databuf[2] = (databuf[2] == 2) ? 1 : 0;
#endif
- databuf.u8[3] = 0;
+ databuf[3] = 0;
if (temp & RH_A_PSM) /* per-port power switching? */
- databuf.u8[3] |= 0x1;
+ databuf[3] |= 0x1;
if (temp & RH_A_NOCP) /* no overcurrent reporting? */
- databuf.u8[3] |= 0x10;
+ databuf[3] |= 0x10;
else if (temp & RH_A_OCPM)/* per-port overcurrent reporting? */
- databuf.u8[3] |= 0x8;
+ databuf[3] |= 0x8;
- /* corresponds to databuf.u8[4-7] */
- databuf.u8[1] = 0;
- databuf.u8[5] = (temp & RH_A_POTPGT) >> 24;
+ databuf[4] = 0;
+ databuf[5] = (temp & RH_A_POTPGT) >> 24;
+ databuf[6] = 0;
temp = roothub_b(&gohci);
- databuf.u8[7] = temp & RH_B_DR;
- if (databuf.u8[2] < 7) {
- databuf.u8[8] = 0xff;
+ databuf[7] = temp & RH_B_DR;
+ if (databuf[2] < 7) {
+ databuf[8] = 0xff;
} else {
- databuf.u8[0] += 2;
- databuf.u8[8] = (temp & RH_B_DR) >> 8;
- databuf.u8[10] = databuf.u8[9] = 0xff;
+ databuf[0] += 2;
+ databuf[8] = (temp & RH_B_DR) >> 8;
+ databuf[10] = databuf[9] = 0xff;
}
len = min_t(unsigned int, leni,
- min_t(unsigned int, databuf.u8[0], wLength));
+ min_t(unsigned int, databuf[0], wLength));
OK(len);
}
case RH_GET_CONFIGURATION:
- databuf.u8[0] = 0x01;
+ databuf[0] = 0x01;
OK(1);
case RH_SET_CONFIGURATION:
#endif
len = min_t(int, len, leni);
- if (data != databuf.ptr)
- memcpy(data, databuf.ptr, len);
+ if (data != databuf)
+ memcpy(data, databuf, len);
dev->act_len = len;
dev->status = stat;
* should be a usb device connected.
*/
timeout = musb_cfg.timeout;
- while (timeout--)
+ while (--timeout)
if (readb(&musbr->devctl) & MUSB_DEVCTL_HM)
break;
#
subdirs-$(CONFIG_CMD_CRAMFS) := cramfs
-subdirs-$(CONFIG_CMD_EXT2) += ext2
+subdirs-$(CONFIG_CMD_EXT4) += ext4
+ifndef CONFIG_CMD_EXT4
+subdirs-$(CONFIG_CMD_EXT2) += ext4
+endif
subdirs-$(CONFIG_CMD_FAT) += fat
subdirs-$(CONFIG_CMD_FDOS) += fdos
subdirs-$(CONFIG_CMD_JFFS2) += jffs2
+++ /dev/null
-/*
- * (C) Copyright 2004
- * esd gmbh <www.esd-electronics.com>
- * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
- *
- * based on code of fs/reiserfs/dev.c by
- *
- * (C) Copyright 2003 - 2004
- * Sysgo AG, <www.elinos.com>, Pavel Bartusek <pba@sysgo.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-
-#include <common.h>
-#include <config.h>
-#include <ext2fs.h>
-
-static block_dev_desc_t *ext2fs_block_dev_desc;
-static disk_partition_t part_info;
-
-int ext2fs_set_blk_dev(block_dev_desc_t *rbdd, int part)
-{
- ext2fs_block_dev_desc = rbdd;
-
- if (part == 0) {
- /* disk doesn't use partition table */
- part_info.start = 0;
- part_info.size = rbdd->lba;
- part_info.blksz = rbdd->blksz;
- } else {
- if (get_partition_info
- (ext2fs_block_dev_desc, part, &part_info)) {
- return 0;
- }
- }
- return part_info.size;
-}
-
-
-int ext2fs_devread(int sector, int byte_offset, int byte_len, char *buf)
-{
- ALLOC_CACHE_ALIGN_BUFFER(char, sec_buf, SECTOR_SIZE);
- unsigned sectors;
-
- /*
- * Check partition boundaries
- */
- if ((sector < 0) ||
- ((sector + ((byte_offset + byte_len - 1) >> SECTOR_BITS)) >=
- part_info.size)) {
- /* errnum = ERR_OUTSIDE_PART; */
- printf(" ** %s read outside partition sector %d\n",
- __func__,
- sector);
- return 0;
- }
-
- /*
- * Get the read to the beginning of a partition.
- */
- sector += byte_offset >> SECTOR_BITS;
- byte_offset &= SECTOR_SIZE - 1;
-
- debug(" <%d, %d, %d>\n", sector, byte_offset, byte_len);
-
- if (ext2fs_block_dev_desc == NULL) {
- printf(" ** %s Invalid Block Device Descriptor (NULL)\n",
- __func__);
- return 0;
- }
-
- if (byte_offset != 0) {
- /* read first part which isn't aligned with start of sector */
- if (ext2fs_block_dev_desc->
- block_read(ext2fs_block_dev_desc->dev,
- part_info.start + sector, 1,
- (unsigned long *) sec_buf) != 1) {
- printf(" ** %s read error **\n", __func__);
- return 0;
- }
- memcpy(buf, sec_buf + byte_offset,
- min(SECTOR_SIZE - byte_offset, byte_len));
- buf += min(SECTOR_SIZE - byte_offset, byte_len);
- byte_len -= min(SECTOR_SIZE - byte_offset, byte_len);
- sector++;
- }
-
- /* read sector aligned part */
- sectors = byte_len / SECTOR_SIZE;
-
- if (sectors > 0) {
- if (ext2fs_block_dev_desc->block_read(
- ext2fs_block_dev_desc->dev,
- part_info.start + sector,
- sectors,
- (unsigned long *) buf) != sectors) {
- printf(" ** %s read error - block\n", __func__);
- return 0;
- }
-
- buf += sectors * SECTOR_SIZE;
- byte_len -= sectors * SECTOR_SIZE;
- sector += sectors;
- }
-
- if (byte_len != 0) {
- /* read rest of data which are not in whole sector */
- if (ext2fs_block_dev_desc->
- block_read(ext2fs_block_dev_desc->dev,
- part_info.start + sector, 1,
- (unsigned long *) sec_buf) != 1) {
- printf(" ** %s read error - last part\n", __func__);
- return 0;
- }
- memcpy(buf, sec_buf, byte_len);
- }
- return 1;
-}
+++ /dev/null
-/*
- * (C) Copyright 2004
- * esd gmbh <www.esd-electronics.com>
- * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
- *
- * based on code from grub2 fs/ext2.c and fs/fshelp.c by
- *
- * GRUB -- GRand Unified Bootloader
- * Copyright (C) 2003, 2004 Free Software Foundation, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <ext2fs.h>
-#include <malloc.h>
-#include <asm/byteorder.h>
-
-extern int ext2fs_devread (int sector, int byte_offset, int byte_len,
- char *buf);
-
-/* Magic value used to identify an ext2 filesystem. */
-#define EXT2_MAGIC 0xEF53
-/* Amount of indirect blocks in an inode. */
-#define INDIRECT_BLOCKS 12
-/* Maximum lenght of a pathname. */
-#define EXT2_PATH_MAX 4096
-/* Maximum nesting of symlinks, used to prevent a loop. */
-#define EXT2_MAX_SYMLINKCNT 8
-
-/* Filetype used in directory entry. */
-#define FILETYPE_UNKNOWN 0
-#define FILETYPE_REG 1
-#define FILETYPE_DIRECTORY 2
-#define FILETYPE_SYMLINK 7
-
-/* Filetype information as used in inodes. */
-#define FILETYPE_INO_MASK 0170000
-#define FILETYPE_INO_REG 0100000
-#define FILETYPE_INO_DIRECTORY 0040000
-#define FILETYPE_INO_SYMLINK 0120000
-
-/* Bits used as offset in sector */
-#define DISK_SECTOR_BITS 9
-
-/* Log2 size of ext2 block in 512 blocks. */
-#define LOG2_EXT2_BLOCK_SIZE(data) (__le32_to_cpu (data->sblock.log2_block_size) + 1)
-
-/* Log2 size of ext2 block in bytes. */
-#define LOG2_BLOCK_SIZE(data) (__le32_to_cpu (data->sblock.log2_block_size) + 10)
-
-/* The size of an ext2 block in bytes. */
-#define EXT2_BLOCK_SIZE(data) (1 << LOG2_BLOCK_SIZE(data))
-
-/* The ext2 superblock. */
-struct ext2_sblock {
- uint32_t total_inodes;
- uint32_t total_blocks;
- uint32_t reserved_blocks;
- uint32_t free_blocks;
- uint32_t free_inodes;
- uint32_t first_data_block;
- uint32_t log2_block_size;
- uint32_t log2_fragment_size;
- uint32_t blocks_per_group;
- uint32_t fragments_per_group;
- uint32_t inodes_per_group;
- uint32_t mtime;
- uint32_t utime;
- uint16_t mnt_count;
- uint16_t max_mnt_count;
- uint16_t magic;
- uint16_t fs_state;
- uint16_t error_handling;
- uint16_t minor_revision_level;
- uint32_t lastcheck;
- uint32_t checkinterval;
- uint32_t creator_os;
- uint32_t revision_level;
- uint16_t uid_reserved;
- uint16_t gid_reserved;
- uint32_t first_inode;
- uint16_t inode_size;
- uint16_t block_group_number;
- uint32_t feature_compatibility;
- uint32_t feature_incompat;
- uint32_t feature_ro_compat;
- uint32_t unique_id[4];
- char volume_name[16];
- char last_mounted_on[64];
- uint32_t compression_info;
-};
-
-/* The ext2 blockgroup. */
-struct ext2_block_group {
- uint32_t block_id;
- uint32_t inode_id;
- uint32_t inode_table_id;
- uint16_t free_blocks;
- uint16_t free_inodes;
- uint16_t used_dir_cnt;
- uint32_t reserved[3];
-};
-
-/* The ext2 inode. */
-struct ext2_inode {
- uint16_t mode;
- uint16_t uid;
- uint32_t size;
- uint32_t atime;
- uint32_t ctime;
- uint32_t mtime;
- uint32_t dtime;
- uint16_t gid;
- uint16_t nlinks;
- uint32_t blockcnt; /* Blocks of 512 bytes!! */
- uint32_t flags;
- uint32_t osd1;
- union {
- struct datablocks {
- uint32_t dir_blocks[INDIRECT_BLOCKS];
- uint32_t indir_block;
- uint32_t double_indir_block;
- uint32_t tripple_indir_block;
- } blocks;
- char symlink[60];
- } b;
- uint32_t version;
- uint32_t acl;
- uint32_t dir_acl;
- uint32_t fragment_addr;
- uint32_t osd2[3];
-};
-
-/* The header of an ext2 directory entry. */
-struct ext2_dirent {
- uint32_t inode;
- uint16_t direntlen;
- uint8_t namelen;
- uint8_t filetype;
-};
-
-struct ext2fs_node {
- struct ext2_data *data;
- struct ext2_inode inode;
- int ino;
- int inode_read;
-};
-
-/* Information about a "mounted" ext2 filesystem. */
-struct ext2_data {
- struct ext2_sblock sblock;
- struct ext2_inode *inode;
- struct ext2fs_node diropen;
-};
-
-
-typedef struct ext2fs_node *ext2fs_node_t;
-
-struct ext2_data *ext2fs_root = NULL;
-ext2fs_node_t ext2fs_file = NULL;
-int symlinknest = 0;
-uint32_t *indir1_block = NULL;
-int indir1_size = 0;
-int indir1_blkno = -1;
-uint32_t *indir2_block = NULL;
-int indir2_size = 0;
-int indir2_blkno = -1;
-static unsigned int inode_size;
-
-
-static int ext2fs_blockgroup
- (struct ext2_data *data, int group, struct ext2_block_group *blkgrp) {
- unsigned int blkno;
- unsigned int blkoff;
- unsigned int desc_per_blk;
-
- desc_per_blk = EXT2_BLOCK_SIZE(data) / sizeof(struct ext2_block_group);
-
- blkno = __le32_to_cpu(data->sblock.first_data_block) + 1 +
- group / desc_per_blk;
- blkoff = (group % desc_per_blk) * sizeof(struct ext2_block_group);
-#ifdef DEBUG
- printf ("ext2fs read %d group descriptor (blkno %d blkoff %d)\n",
- group, blkno, blkoff);
-#endif
- return (ext2fs_devread (blkno << LOG2_EXT2_BLOCK_SIZE(data),
- blkoff, sizeof(struct ext2_block_group), (char *)blkgrp));
-
-}
-
-
-static int ext2fs_read_inode
- (struct ext2_data *data, int ino, struct ext2_inode *inode) {
- struct ext2_block_group blkgrp;
- struct ext2_sblock *sblock = &data->sblock;
- int inodes_per_block;
- int status;
-
- unsigned int blkno;
- unsigned int blkoff;
-
-#ifdef DEBUG
- printf ("ext2fs read inode %d, inode_size %d\n", ino, inode_size);
-#endif
- /* It is easier to calculate if the first inode is 0. */
- ino--;
- status = ext2fs_blockgroup (data, ino / __le32_to_cpu
- (sblock->inodes_per_group), &blkgrp);
- if (status == 0) {
- return (0);
- }
-
- inodes_per_block = EXT2_BLOCK_SIZE(data) / inode_size;
-
- blkno = __le32_to_cpu (blkgrp.inode_table_id) +
- (ino % __le32_to_cpu (sblock->inodes_per_group))
- / inodes_per_block;
- blkoff = (ino % inodes_per_block) * inode_size;
-#ifdef DEBUG
- printf ("ext2fs read inode blkno %d blkoff %d\n", blkno, blkoff);
-#endif
- /* Read the inode. */
- status = ext2fs_devread (blkno << LOG2_EXT2_BLOCK_SIZE (data), blkoff,
- sizeof (struct ext2_inode), (char *) inode);
- if (status == 0) {
- return (0);
- }
-
- return (1);
-}
-
-
-void ext2fs_free_node (ext2fs_node_t node, ext2fs_node_t currroot) {
- if ((node != &ext2fs_root->diropen) && (node != currroot)) {
- free (node);
- }
-}
-
-
-static int ext2fs_read_block (ext2fs_node_t node, int fileblock) {
- struct ext2_data *data = node->data;
- struct ext2_inode *inode = &node->inode;
- int blknr;
- int blksz = EXT2_BLOCK_SIZE (data);
- int log2_blksz = LOG2_EXT2_BLOCK_SIZE (data);
- int status;
-
- /* Direct blocks. */
- if (fileblock < INDIRECT_BLOCKS) {
- blknr = __le32_to_cpu (inode->b.blocks.dir_blocks[fileblock]);
- }
- /* Indirect. */
- else if (fileblock < (INDIRECT_BLOCKS + (blksz / 4))) {
- if (indir1_block == NULL) {
- indir1_block = (uint32_t *) memalign(ARCH_DMA_MINALIGN,
- blksz);
- if (indir1_block == NULL) {
- printf ("** ext2fs read block (indir 1) malloc failed. **\n");
- return (-1);
- }
- indir1_size = blksz;
- indir1_blkno = -1;
- }
- if (blksz != indir1_size) {
- free (indir1_block);
- indir1_block = NULL;
- indir1_size = 0;
- indir1_blkno = -1;
- indir1_block = (uint32_t *) memalign(ARCH_DMA_MINALIGN,
- blksz);
- if (indir1_block == NULL) {
- printf ("** ext2fs read block (indir 1) malloc failed. **\n");
- return (-1);
- }
- indir1_size = blksz;
- }
- if ((__le32_to_cpu (inode->b.blocks.indir_block) <<
- log2_blksz) != indir1_blkno) {
- status = ext2fs_devread (__le32_to_cpu(inode->b.blocks.indir_block) << log2_blksz,
- 0, blksz,
- (char *) indir1_block);
- if (status == 0) {
- printf ("** ext2fs read block (indir 1) failed. **\n");
- return (0);
- }
- indir1_blkno =
- __le32_to_cpu (inode->b.blocks.
- indir_block) << log2_blksz;
- }
- blknr = __le32_to_cpu (indir1_block
- [fileblock - INDIRECT_BLOCKS]);
- }
- /* Double indirect. */
- else if (fileblock <
- (INDIRECT_BLOCKS + (blksz / 4 * (blksz / 4 + 1)))) {
- unsigned int perblock = blksz / 4;
- unsigned int rblock = fileblock - (INDIRECT_BLOCKS
- + blksz / 4);
-
- if (indir1_block == NULL) {
- indir1_block = (uint32_t *) memalign(ARCH_DMA_MINALIGN,
- blksz);
- if (indir1_block == NULL) {
- printf ("** ext2fs read block (indir 2 1) malloc failed. **\n");
- return (-1);
- }
- indir1_size = blksz;
- indir1_blkno = -1;
- }
- if (blksz != indir1_size) {
- free (indir1_block);
- indir1_block = NULL;
- indir1_size = 0;
- indir1_blkno = -1;
- indir1_block = (uint32_t *) memalign(ARCH_DMA_MINALIGN,
- blksz);
- if (indir1_block == NULL) {
- printf ("** ext2fs read block (indir 2 1) malloc failed. **\n");
- return (-1);
- }
- indir1_size = blksz;
- }
- if ((__le32_to_cpu (inode->b.blocks.double_indir_block) <<
- log2_blksz) != indir1_blkno) {
- status = ext2fs_devread (__le32_to_cpu(inode->b.blocks.double_indir_block) << log2_blksz,
- 0, blksz,
- (char *) indir1_block);
- if (status == 0) {
- printf ("** ext2fs read block (indir 2 1) failed. **\n");
- return (-1);
- }
- indir1_blkno =
- __le32_to_cpu (inode->b.blocks.double_indir_block) << log2_blksz;
- }
-
- if (indir2_block == NULL) {
- indir2_block = (uint32_t *) memalign(ARCH_DMA_MINALIGN,
- blksz);
- if (indir2_block == NULL) {
- printf ("** ext2fs read block (indir 2 2) malloc failed. **\n");
- return (-1);
- }
- indir2_size = blksz;
- indir2_blkno = -1;
- }
- if (blksz != indir2_size) {
- free (indir2_block);
- indir2_block = NULL;
- indir2_size = 0;
- indir2_blkno = -1;
- indir2_block = (uint32_t *) memalign(ARCH_DMA_MINALIGN,
- blksz);
- if (indir2_block == NULL) {
- printf ("** ext2fs read block (indir 2 2) malloc failed. **\n");
- return (-1);
- }
- indir2_size = blksz;
- }
- if ((__le32_to_cpu (indir1_block[rblock / perblock]) <<
- log2_blksz) != indir2_blkno) {
- status = ext2fs_devread (__le32_to_cpu(indir1_block[rblock / perblock]) << log2_blksz,
- 0, blksz,
- (char *) indir2_block);
- if (status == 0) {
- printf ("** ext2fs read block (indir 2 2) failed. **\n");
- return (-1);
- }
- indir2_blkno =
- __le32_to_cpu (indir1_block[rblock / perblock]) << log2_blksz;
- }
- blknr = __le32_to_cpu (indir2_block[rblock % perblock]);
- }
- /* Tripple indirect. */
- else {
- printf ("** ext2fs doesn't support tripple indirect blocks. **\n");
- return (-1);
- }
-#ifdef DEBUG
- printf ("ext2fs_read_block %08x\n", blknr);
-#endif
- return (blknr);
-}
-
-
-int ext2fs_read_file
- (ext2fs_node_t node, int pos, unsigned int len, char *buf) {
- int i;
- int blockcnt;
- int log2blocksize = LOG2_EXT2_BLOCK_SIZE (node->data);
- int blocksize = 1 << (log2blocksize + DISK_SECTOR_BITS);
- unsigned int filesize = __le32_to_cpu(node->inode.size);
-
- /* Adjust len so it we can't read past the end of the file. */
- if (len > filesize) {
- len = filesize;
- }
- blockcnt = ((len + pos) + blocksize - 1) / blocksize;
-
- for (i = pos / blocksize; i < blockcnt; i++) {
- int blknr;
- int blockoff = pos % blocksize;
- int blockend = blocksize;
-
- int skipfirst = 0;
-
- blknr = ext2fs_read_block (node, i);
- if (blknr < 0) {
- return (-1);
- }
-
- /* Last block. */
- if (i == blockcnt - 1) {
- blockend = (len + pos) % blocksize;
-
- /* The last portion is exactly blocksize. */
- if (!blockend) {
- blockend = blocksize;
- }
- }
-
- /* First block. */
- if (i == pos / blocksize) {
- skipfirst = blockoff;
- blockend -= skipfirst;
- }
-
- /* grab middle blocks in one go */
- if (i != pos / blocksize && i < blockcnt - 1 && blockcnt > 3) {
- int oldblk = blknr;
- int blocknxt = ext2fs_read_block(node, i + 1);
- while (i < blockcnt - 1) {
- if (blocknxt == (oldblk + 1)) {
- oldblk = blocknxt;
- i++;
- } else {
- blocknxt = ext2fs_read_block(node, i);
- break;
- }
- blocknxt = ext2fs_read_block(node, i);
- }
-
- if (oldblk == blknr)
- blockend = blocksize;
- else
- blockend = (1 + blocknxt - blknr) * blocksize;
- }
-
- blknr = blknr << log2blocksize;
-
- /* If the block number is 0 this block is not stored on disk but
- is zero filled instead. */
- if (blknr) {
- int status;
-
- status = ext2fs_devread (blknr, skipfirst, blockend, buf);
- if (status == 0) {
- return (-1);
- }
- } else {
- memset (buf, 0, blocksize - skipfirst);
- }
- buf += blockend - skipfirst;
- }
- return (len);
-}
-
-
-static int ext2fs_iterate_dir (ext2fs_node_t dir, char *name, ext2fs_node_t * fnode, int *ftype)
-{
- unsigned int fpos = 0;
- int status;
- struct ext2fs_node *diro = (struct ext2fs_node *) dir;
-
-#ifdef DEBUG
- if (name != NULL)
- printf ("Iterate dir %s\n", name);
-#endif /* of DEBUG */
- if (!diro->inode_read) {
- status = ext2fs_read_inode (diro->data, diro->ino,
- &diro->inode);
- if (status == 0) {
- return (0);
- }
- }
- /* Search the file. */
- while (fpos < __le32_to_cpu (diro->inode.size)) {
- struct ext2_dirent dirent;
-
- status = ext2fs_read_file (diro, fpos,
- sizeof (struct ext2_dirent),
- (char *) &dirent);
- if (status < 1) {
- return (0);
- }
- if (dirent.namelen != 0) {
- char filename[dirent.namelen + 1];
- ext2fs_node_t fdiro;
- int type = FILETYPE_UNKNOWN;
-
- status = ext2fs_read_file (diro,
- fpos + sizeof (struct ext2_dirent),
- dirent.namelen, filename);
- if (status < 1) {
- return (0);
- }
- fdiro = malloc (sizeof (struct ext2fs_node));
- if (!fdiro) {
- return (0);
- }
-
- fdiro->data = diro->data;
- fdiro->ino = __le32_to_cpu (dirent.inode);
-
- filename[dirent.namelen] = '\0';
-
- if (dirent.filetype != FILETYPE_UNKNOWN) {
- fdiro->inode_read = 0;
-
- if (dirent.filetype == FILETYPE_DIRECTORY) {
- type = FILETYPE_DIRECTORY;
- } else if (dirent.filetype ==
- FILETYPE_SYMLINK) {
- type = FILETYPE_SYMLINK;
- } else if (dirent.filetype == FILETYPE_REG) {
- type = FILETYPE_REG;
- }
- } else {
- /* The filetype can not be read from the dirent, get it from inode */
-
- status = ext2fs_read_inode (diro->data,
- __le32_to_cpu(dirent.inode),
- &fdiro->inode);
- if (status == 0) {
- free (fdiro);
- return (0);
- }
- fdiro->inode_read = 1;
-
- if ((__le16_to_cpu (fdiro->inode.mode) &
- FILETYPE_INO_MASK) ==
- FILETYPE_INO_DIRECTORY) {
- type = FILETYPE_DIRECTORY;
- } else if ((__le16_to_cpu (fdiro->inode.mode)
- & FILETYPE_INO_MASK) ==
- FILETYPE_INO_SYMLINK) {
- type = FILETYPE_SYMLINK;
- } else if ((__le16_to_cpu (fdiro->inode.mode)
- & FILETYPE_INO_MASK) ==
- FILETYPE_INO_REG) {
- type = FILETYPE_REG;
- }
- }
-#ifdef DEBUG
- printf ("iterate >%s<\n", filename);
-#endif /* of DEBUG */
- if ((name != NULL) && (fnode != NULL)
- && (ftype != NULL)) {
- if (strcmp (filename, name) == 0) {
- *ftype = type;
- *fnode = fdiro;
- return (1);
- }
- } else {
- if (fdiro->inode_read == 0) {
- status = ext2fs_read_inode (diro->data,
- __le32_to_cpu (dirent.inode),
- &fdiro->inode);
- if (status == 0) {
- free (fdiro);
- return (0);
- }
- fdiro->inode_read = 1;
- }
- switch (type) {
- case FILETYPE_DIRECTORY:
- printf ("<DIR> ");
- break;
- case FILETYPE_SYMLINK:
- printf ("<SYM> ");
- break;
- case FILETYPE_REG:
- printf (" ");
- break;
- default:
- printf ("< ? > ");
- break;
- }
- printf ("%10d %s\n",
- __le32_to_cpu (fdiro->inode.size),
- filename);
- }
- free (fdiro);
- }
- fpos += __le16_to_cpu (dirent.direntlen);
- }
- return (0);
-}
-
-
-static char *ext2fs_read_symlink (ext2fs_node_t node) {
- char *symlink;
- struct ext2fs_node *diro = node;
- int status;
-
- if (!diro->inode_read) {
- status = ext2fs_read_inode (diro->data, diro->ino,
- &diro->inode);
- if (status == 0) {
- return (0);
- }
- }
- symlink = malloc (__le32_to_cpu (diro->inode.size) + 1);
- if (!symlink) {
- return (0);
- }
- /* If the filesize of the symlink is bigger than
- 60 the symlink is stored in a separate block,
- otherwise it is stored in the inode. */
- if (__le32_to_cpu (diro->inode.size) <= 60) {
- strncpy (symlink, diro->inode.b.symlink,
- __le32_to_cpu (diro->inode.size));
- } else {
- status = ext2fs_read_file (diro, 0,
- __le32_to_cpu (diro->inode.size),
- symlink);
- if (status == 0) {
- free (symlink);
- return (0);
- }
- }
- symlink[__le32_to_cpu (diro->inode.size)] = '\0';
- return (symlink);
-}
-
-
-int ext2fs_find_file1
- (const char *currpath,
- ext2fs_node_t currroot, ext2fs_node_t * currfound, int *foundtype) {
- char fpath[strlen (currpath) + 1];
- char *name = fpath;
- char *next;
- int status;
- int type = FILETYPE_DIRECTORY;
- ext2fs_node_t currnode = currroot;
- ext2fs_node_t oldnode = currroot;
-
- strncpy (fpath, currpath, strlen (currpath) + 1);
-
- /* Remove all leading slashes. */
- while (*name == '/') {
- name++;
- }
- if (!*name) {
- *currfound = currnode;
- return (1);
- }
-
- for (;;) {
- int found;
-
- /* Extract the actual part from the pathname. */
- next = strchr (name, '/');
- if (next) {
- /* Remove all leading slashes. */
- while (*next == '/') {
- *(next++) = '\0';
- }
- }
-
- /* At this point it is expected that the current node is a directory, check if this is true. */
- if (type != FILETYPE_DIRECTORY) {
- ext2fs_free_node (currnode, currroot);
- return (0);
- }
-
- oldnode = currnode;
-
- /* Iterate over the directory. */
- found = ext2fs_iterate_dir (currnode, name, &currnode, &type);
- if (found == 0) {
- return (0);
- }
- if (found == -1) {
- break;
- }
-
- /* Read in the symlink and follow it. */
- if (type == FILETYPE_SYMLINK) {
- char *symlink;
-
- /* Test if the symlink does not loop. */
- if (++symlinknest == 8) {
- ext2fs_free_node (currnode, currroot);
- ext2fs_free_node (oldnode, currroot);
- return (0);
- }
-
- symlink = ext2fs_read_symlink (currnode);
- ext2fs_free_node (currnode, currroot);
-
- if (!symlink) {
- ext2fs_free_node (oldnode, currroot);
- return (0);
- }
-#ifdef DEBUG
- printf ("Got symlink >%s<\n", symlink);
-#endif /* of DEBUG */
- /* The symlink is an absolute path, go back to the root inode. */
- if (symlink[0] == '/') {
- ext2fs_free_node (oldnode, currroot);
- oldnode = &ext2fs_root->diropen;
- }
-
- /* Lookup the node the symlink points to. */
- status = ext2fs_find_file1 (symlink, oldnode,
- &currnode, &type);
-
- free (symlink);
-
- if (status == 0) {
- ext2fs_free_node (oldnode, currroot);
- return (0);
- }
- }
-
- ext2fs_free_node (oldnode, currroot);
-
- /* Found the node! */
- if (!next || *next == '\0') {
- *currfound = currnode;
- *foundtype = type;
- return (1);
- }
- name = next;
- }
- return (-1);
-}
-
-
-int ext2fs_find_file
- (const char *path,
- ext2fs_node_t rootnode, ext2fs_node_t * foundnode, int expecttype) {
- int status;
- int foundtype = FILETYPE_DIRECTORY;
-
-
- symlinknest = 0;
- if (!path) {
- return (0);
- }
-
- status = ext2fs_find_file1 (path, rootnode, foundnode, &foundtype);
- if (status == 0) {
- return (0);
- }
- /* Check if the node that was found was of the expected type. */
- if ((expecttype == FILETYPE_REG) && (foundtype != expecttype)) {
- return (0);
- } else if ((expecttype == FILETYPE_DIRECTORY)
- && (foundtype != expecttype)) {
- return (0);
- }
- return (1);
-}
-
-
-int ext2fs_ls (const char *dirname) {
- ext2fs_node_t dirnode;
- int status;
-
- if (ext2fs_root == NULL) {
- return (0);
- }
-
- status = ext2fs_find_file (dirname, &ext2fs_root->diropen, &dirnode,
- FILETYPE_DIRECTORY);
- if (status != 1) {
- printf ("** Can not find directory. **\n");
- return (1);
- }
- ext2fs_iterate_dir (dirnode, NULL, NULL, NULL);
- ext2fs_free_node (dirnode, &ext2fs_root->diropen);
- return (0);
-}
-
-
-int ext2fs_open (const char *filename) {
- ext2fs_node_t fdiro = NULL;
- int status;
- int len;
-
- if (ext2fs_root == NULL) {
- return (-1);
- }
- ext2fs_file = NULL;
- status = ext2fs_find_file (filename, &ext2fs_root->diropen, &fdiro,
- FILETYPE_REG);
- if (status == 0) {
- goto fail;
- }
- if (!fdiro->inode_read) {
- status = ext2fs_read_inode (fdiro->data, fdiro->ino,
- &fdiro->inode);
- if (status == 0) {
- goto fail;
- }
- }
- len = __le32_to_cpu (fdiro->inode.size);
- ext2fs_file = fdiro;
- return (len);
-
-fail:
- ext2fs_free_node (fdiro, &ext2fs_root->diropen);
- return (-1);
-}
-
-
-int ext2fs_close (void
- ) {
- if ((ext2fs_file != NULL) && (ext2fs_root != NULL)) {
- ext2fs_free_node (ext2fs_file, &ext2fs_root->diropen);
- ext2fs_file = NULL;
- }
- if (ext2fs_root != NULL) {
- free (ext2fs_root);
- ext2fs_root = NULL;
- }
- if (indir1_block != NULL) {
- free (indir1_block);
- indir1_block = NULL;
- indir1_size = 0;
- indir1_blkno = -1;
- }
- if (indir2_block != NULL) {
- free (indir2_block);
- indir2_block = NULL;
- indir2_size = 0;
- indir2_blkno = -1;
- }
- return (0);
-}
-
-
-int ext2fs_read (char *buf, unsigned len) {
- int status;
-
- if (ext2fs_root == NULL) {
- return (0);
- }
-
- if (ext2fs_file == NULL) {
- return (0);
- }
-
- status = ext2fs_read_file (ext2fs_file, 0, len, buf);
- return (status);
-}
-
-
-int ext2fs_mount (unsigned part_length) {
- struct ext2_data *data;
- int status;
-
- data = malloc (sizeof (struct ext2_data));
- if (!data) {
- return (0);
- }
- /* Read the superblock. */
- status = ext2fs_devread (1 * 2, 0, sizeof (struct ext2_sblock),
- (char *) &data->sblock);
- if (status == 0) {
- goto fail;
- }
- /* Make sure this is an ext2 filesystem. */
- if (__le16_to_cpu (data->sblock.magic) != EXT2_MAGIC) {
- goto fail;
- }
- if (__le32_to_cpu(data->sblock.revision_level == 0)) {
- inode_size = 128;
- } else {
- inode_size = __le16_to_cpu(data->sblock.inode_size);
- }
-#ifdef DEBUG
- printf("EXT2 rev %d, inode_size %d\n",
- __le32_to_cpu(data->sblock.revision_level), inode_size);
-#endif
- data->diropen.data = data;
- data->diropen.ino = 2;
- data->diropen.inode_read = 1;
- data->inode = &data->diropen.inode;
-
- status = ext2fs_read_inode (data, 2, data->inode);
- if (status == 0) {
- goto fail;
- }
-
- ext2fs_root = data;
-
- return (1);
-
-fail:
- printf ("Failed to mount ext2 filesystem...\n");
- free (data);
- ext2fs_root = NULL;
- return (0);
-}
include $(TOPDIR)/config.mk
-LIB = $(obj)libext2fs.o
+LIB = $(obj)libext4fs.o
AOBJS =
-COBJS-$(CONFIG_CMD_EXT2) := ext2fs.o dev.o
+COBJS-$(CONFIG_CMD_EXT4) := ext4fs.o ext4_common.o dev.o
+ifndef CONFIG_CMD_EXT4
+COBJS-$(CONFIG_CMD_EXT2) := ext4fs.o ext4_common.o dev.o
+endif
+COBJS-$(CONFIG_CMD_EXT4_WRITE) += ext4_journal.o crc16.o
SRCS := $(AOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS-y))
-#CPPFLAGS +=
all: $(LIB) $(AOBJS)
--- /dev/null
+/*
+ * crc16.c
+ *
+ * This source code is licensed under the GNU General Public License,
+ * Version 2. See the file COPYING for more details.
+ */
+
+#include <common.h>
+#include <asm/byteorder.h>
+#include <linux/stat.h>
+#include "crc16.h"
+
+/** CRC table for the CRC-16. The poly is 0x8005 (x16 + x15 + x2 + 1) */
+static __u16 const crc16_table[256] = {
+ 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
+ 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
+ 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
+ 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
+ 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
+ 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
+ 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
+ 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
+ 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
+ 0x3600, 0xF6C1, 0xF781, 0x3740, 0xF501, 0x35C0, 0x3480, 0xF441,
+ 0x3C00, 0xFCC1, 0xFD81, 0x3D40, 0xFF01, 0x3FC0, 0x3E80, 0xFE41,
+ 0xFA01, 0x3AC0, 0x3B80, 0xFB41, 0x3900, 0xF9C1, 0xF881, 0x3840,
+ 0x2800, 0xE8C1, 0xE981, 0x2940, 0xEB01, 0x2BC0, 0x2A80, 0xEA41,
+ 0xEE01, 0x2EC0, 0x2F80, 0xEF41, 0x2D00, 0xEDC1, 0xEC81, 0x2C40,
+ 0xE401, 0x24C0, 0x2580, 0xE541, 0x2700, 0xE7C1, 0xE681, 0x2640,
+ 0x2200, 0xE2C1, 0xE381, 0x2340, 0xE101, 0x21C0, 0x2080, 0xE041,
+ 0xA001, 0x60C0, 0x6180, 0xA141, 0x6300, 0xA3C1, 0xA281, 0x6240,
+ 0x6600, 0xA6C1, 0xA781, 0x6740, 0xA501, 0x65C0, 0x6480, 0xA441,
+ 0x6C00, 0xACC1, 0xAD81, 0x6D40, 0xAF01, 0x6FC0, 0x6E80, 0xAE41,
+ 0xAA01, 0x6AC0, 0x6B80, 0xAB41, 0x6900, 0xA9C1, 0xA881, 0x6840,
+ 0x7800, 0xB8C1, 0xB981, 0x7940, 0xBB01, 0x7BC0, 0x7A80, 0xBA41,
+ 0xBE01, 0x7EC0, 0x7F80, 0xBF41, 0x7D00, 0xBDC1, 0xBC81, 0x7C40,
+ 0xB401, 0x74C0, 0x7580, 0xB541, 0x7700, 0xB7C1, 0xB681, 0x7640,
+ 0x7200, 0xB2C1, 0xB381, 0x7340, 0xB101, 0x71C0, 0x7080, 0xB041,
+ 0x5000, 0x90C1, 0x9181, 0x5140, 0x9301, 0x53C0, 0x5280, 0x9241,
+ 0x9601, 0x56C0, 0x5780, 0x9741, 0x5500, 0x95C1, 0x9481, 0x5440,
+ 0x9C01, 0x5CC0, 0x5D80, 0x9D41, 0x5F00, 0x9FC1, 0x9E81, 0x5E40,
+ 0x5A00, 0x9AC1, 0x9B81, 0x5B40, 0x9901, 0x59C0, 0x5880, 0x9841,
+ 0x8801, 0x48C0, 0x4980, 0x8941, 0x4B00, 0x8BC1, 0x8A81, 0x4A40,
+ 0x4E00, 0x8EC1, 0x8F81, 0x4F40, 0x8D01, 0x4DC0, 0x4C80, 0x8C41,
+ 0x4400, 0x84C1, 0x8581, 0x4540, 0x8701, 0x47C0, 0x4680, 0x8641,
+ 0x8201, 0x42C0, 0x4380, 0x8341, 0x4100, 0x81C1, 0x8081, 0x4040
+};
+
+/**
+ * Compute the CRC-16 for the data buffer
+*/
+
+unsigned int ext2fs_crc16(unsigned int crc,
+ const void *buffer, unsigned int len)
+{
+ const unsigned char *cp = buffer;
+
+ while (len--)
+ crc = (((crc >> 8) & 0xffU) ^
+ crc16_table[(crc ^ *cp++) & 0xffU]) & 0x0000ffffU;
+ return crc;
+}
--- /dev/null
+/*
+ * crc16.h - CRC-16 routine
+ * Implements the standard CRC-16:
+ * Width 16
+ * Poly 0x8005 (x16 + x15 + x2 + 1)
+ * Init 0
+ *
+ * Copyright (c) 2005 Ben Gardner <bgardner@wabtec.com>
+ * This source code is licensed under the GNU General Public License,
+ * Version 2. See the file COPYING for more details.
+ */
+#ifndef __CRC16_H
+#define __CRC16_H
+extern unsigned int ext2fs_crc16(unsigned int crc,
+ const void *buffer, unsigned int len);
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2011 - 2012 Samsung Electronics
+ * EXT4 filesystem implementation in Uboot by
+ * Uma Shankar <uma.shankar@samsung.com>
+ * Manjunatha C Achar <a.manjunatha@samsung.com>
+ *
+ * made from existing ext2/dev.c file of Uboot
+ * (C) Copyright 2004
+ * esd gmbh <www.esd-electronics.com>
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * based on code of fs/reiserfs/dev.c by
+ *
+ * (C) Copyright 2003 - 2004
+ * Sysgo AG, <www.elinos.com>, Pavel Bartusek <pba@sysgo.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+/*
+ * Changelog:
+ * 0.1 - Newly created file for ext4fs support. Taken from
+ * fs/ext2/dev.c file in uboot.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <ext_common.h>
+
+static block_dev_desc_t *ext4fs_block_dev_desc;
+static disk_partition_t part_info;
+
+int ext4fs_set_blk_dev(block_dev_desc_t *rbdd, int part)
+{
+ ext4fs_block_dev_desc = rbdd;
+
+ if (part == 0) {
+ /* disk doesn't use partition table */
+ part_info.start = 0;
+ part_info.size = rbdd->lba;
+ part_info.blksz = rbdd->blksz;
+ } else {
+ if (get_partition_info(ext4fs_block_dev_desc,
+ part, &part_info))
+ return 0;
+ }
+ return part_info.size;
+}
+
+int ext4fs_devread(int sector, int byte_offset, int byte_len, char *buf)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(char, sec_buf, SECTOR_SIZE);
+ unsigned block_len;
+
+ /* Check partition boundaries */
+ if ((sector < 0)
+ || ((sector + ((byte_offset + byte_len - 1) >> SECTOR_BITS)) >=
+ part_info.size)) {
+ printf("%s read outside partition %d\n", __func__, sector);
+ return 0;
+ }
+
+ /* Get the read to the beginning of a partition */
+ sector += byte_offset >> SECTOR_BITS;
+ byte_offset &= SECTOR_SIZE - 1;
+
+ debug(" <%d, %d, %d>\n", sector, byte_offset, byte_len);
+
+ if (ext4fs_block_dev_desc == NULL) {
+ printf("** Invalid Block Device Descriptor (NULL)\n");
+ return 0;
+ }
+
+ if (byte_offset != 0) {
+ /* read first part which isn't aligned with start of sector */
+ if (ext4fs_block_dev_desc->
+ block_read(ext4fs_block_dev_desc->dev,
+ part_info.start + sector, 1,
+ (unsigned long *) sec_buf) != 1) {
+ printf(" ** ext2fs_devread() read error **\n");
+ return 0;
+ }
+ memcpy(buf, sec_buf + byte_offset,
+ min(SECTOR_SIZE - byte_offset, byte_len));
+ buf += min(SECTOR_SIZE - byte_offset, byte_len);
+ byte_len -= min(SECTOR_SIZE - byte_offset, byte_len);
+ sector++;
+ }
+
+ if (byte_len == 0)
+ return 1;
+
+ /* read sector aligned part */
+ block_len = byte_len & ~(SECTOR_SIZE - 1);
+
+ if (block_len == 0) {
+ ALLOC_CACHE_ALIGN_BUFFER(u8, p, SECTOR_SIZE);
+
+ block_len = SECTOR_SIZE;
+ ext4fs_block_dev_desc->block_read(ext4fs_block_dev_desc->dev,
+ part_info.start + sector,
+ 1, (unsigned long *)p);
+ memcpy(buf, p, byte_len);
+ return 1;
+ }
+
+ if (ext4fs_block_dev_desc->block_read(ext4fs_block_dev_desc->dev,
+ part_info.start + sector,
+ block_len / SECTOR_SIZE,
+ (unsigned long *) buf) !=
+ block_len / SECTOR_SIZE) {
+ printf(" ** %s read error - block\n", __func__);
+ return 0;
+ }
+ block_len = byte_len & ~(SECTOR_SIZE - 1);
+ buf += block_len;
+ byte_len -= block_len;
+ sector += block_len / SECTOR_SIZE;
+
+ if (byte_len != 0) {
+ /* read rest of data which are not in whole sector */
+ if (ext4fs_block_dev_desc->
+ block_read(ext4fs_block_dev_desc->dev,
+ part_info.start + sector, 1,
+ (unsigned long *) sec_buf) != 1) {
+ printf("* %s read error - last part\n", __func__);
+ return 0;
+ }
+ memcpy(buf, sec_buf, byte_len);
+ }
+ return 1;
+}
--- /dev/null
+/*
+ * (C) Copyright 2011 - 2012 Samsung Electronics
+ * EXT4 filesystem implementation in Uboot by
+ * Uma Shankar <uma.shankar@samsung.com>
+ * Manjunatha C Achar <a.manjunatha@samsung.com>
+ *
+ * ext4ls and ext4load : Based on ext2 ls load support in Uboot.
+ *
+ * (C) Copyright 2004
+ * esd gmbh <www.esd-electronics.com>
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * based on code from grub2 fs/ext2.c and fs/fshelp.c by
+ * GRUB -- GRand Unified Bootloader
+ * Copyright (C) 2003, 2004 Free Software Foundation, Inc.
+ *
+ * ext4write : Based on generic ext4 protocol.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <ext_common.h>
+#include <ext4fs.h>
+#include <malloc.h>
+#include <stddef.h>
+#include <linux/stat.h>
+#include <linux/time.h>
+#include <asm/byteorder.h>
+#include "ext4_common.h"
+
+struct ext2_data *ext4fs_root;
+struct ext2fs_node *ext4fs_file;
+uint32_t *ext4fs_indir1_block;
+int ext4fs_indir1_size;
+int ext4fs_indir1_blkno = -1;
+uint32_t *ext4fs_indir2_block;
+int ext4fs_indir2_size;
+int ext4fs_indir2_blkno = -1;
+
+uint32_t *ext4fs_indir3_block;
+int ext4fs_indir3_size;
+int ext4fs_indir3_blkno = -1;
+struct ext2_inode *g_parent_inode;
+static int symlinknest;
+
+#if defined(CONFIG_CMD_EXT4_WRITE)
+uint32_t ext4fs_div_roundup(uint32_t size, uint32_t n)
+{
+ uint32_t res = size / n;
+ if (res * n != size)
+ res++;
+
+ return res;
+}
+
+void put_ext4(uint64_t off, void *buf, uint32_t size)
+{
+ uint64_t startblock;
+ uint64_t remainder;
+ unsigned char *temp_ptr = NULL;
+ ALLOC_CACHE_ALIGN_BUFFER(unsigned char, sec_buf, SECTOR_SIZE);
+ struct ext_filesystem *fs = get_fs();
+
+ startblock = off / (uint64_t)SECTOR_SIZE;
+ startblock += part_offset;
+ remainder = off % (uint64_t)SECTOR_SIZE;
+ remainder &= SECTOR_SIZE - 1;
+
+ if (fs->dev_desc == NULL)
+ return;
+
+ if ((startblock + (size / SECTOR_SIZE)) >
+ (part_offset + fs->total_sect)) {
+ printf("part_offset is %lu\n", part_offset);
+ printf("total_sector is %llu\n", fs->total_sect);
+ printf("error: overflow occurs\n");
+ return;
+ }
+
+ if (remainder) {
+ if (fs->dev_desc->block_read) {
+ fs->dev_desc->block_read(fs->dev_desc->dev,
+ startblock, 1, sec_buf);
+ temp_ptr = sec_buf;
+ memcpy((temp_ptr + remainder),
+ (unsigned char *)buf, size);
+ fs->dev_desc->block_write(fs->dev_desc->dev,
+ startblock, 1, sec_buf);
+ }
+ } else {
+ if (size / SECTOR_SIZE != 0) {
+ fs->dev_desc->block_write(fs->dev_desc->dev,
+ startblock,
+ size / SECTOR_SIZE,
+ (unsigned long *)buf);
+ } else {
+ fs->dev_desc->block_read(fs->dev_desc->dev,
+ startblock, 1, sec_buf);
+ temp_ptr = sec_buf;
+ memcpy(temp_ptr, buf, size);
+ fs->dev_desc->block_write(fs->dev_desc->dev,
+ startblock, 1,
+ (unsigned long *)sec_buf);
+ }
+ }
+}
+
+static int _get_new_inode_no(unsigned char *buffer)
+{
+ struct ext_filesystem *fs = get_fs();
+ unsigned char input;
+ int operand, status;
+ int count = 1;
+ int j = 0;
+
+ /* get the blocksize of the filesystem */
+ unsigned char *ptr = buffer;
+ while (*ptr == 255) {
+ ptr++;
+ count += 8;
+ if (count > ext4fs_root->sblock.inodes_per_group)
+ return -1;
+ }
+
+ for (j = 0; j < fs->blksz; j++) {
+ input = *ptr;
+ int i = 0;
+ while (i <= 7) {
+ operand = 1 << i;
+ status = input & operand;
+ if (status) {
+ i++;
+ count++;
+ } else {
+ *ptr |= operand;
+ return count;
+ }
+ }
+ ptr = ptr + 1;
+ }
+
+ return -1;
+}
+
+static int _get_new_blk_no(unsigned char *buffer)
+{
+ unsigned char input;
+ int operand, status;
+ int count = 0;
+ int j = 0;
+ unsigned char *ptr = buffer;
+ struct ext_filesystem *fs = get_fs();
+
+ if (fs->blksz != 1024)
+ count = 0;
+ else
+ count = 1;
+
+ while (*ptr == 255) {
+ ptr++;
+ count += 8;
+ if (count == (fs->blksz * 8))
+ return -1;
+ }
+
+ for (j = 0; j < fs->blksz; j++) {
+ input = *ptr;
+ int i = 0;
+ while (i <= 7) {
+ operand = 1 << i;
+ status = input & operand;
+ if (status) {
+ i++;
+ count++;
+ } else {
+ *ptr |= operand;
+ return count;
+ }
+ }
+ ptr = ptr + 1;
+ }
+
+ return -1;
+}
+
+int ext4fs_set_block_bmap(long int blockno, unsigned char *buffer, int index)
+{
+ int i, remainder, status;
+ unsigned char *ptr = buffer;
+ unsigned char operand;
+ i = blockno / 8;
+ remainder = blockno % 8;
+ int blocksize = EXT2_BLOCK_SIZE(ext4fs_root);
+
+ i = i - (index * blocksize);
+ if (blocksize != 1024) {
+ ptr = ptr + i;
+ operand = 1 << remainder;
+ status = *ptr & operand;
+ if (status)
+ return -1;
+
+ *ptr = *ptr | operand;
+ return 0;
+ } else {
+ if (remainder == 0) {
+ ptr = ptr + i - 1;
+ operand = (1 << 7);
+ } else {
+ ptr = ptr + i;
+ operand = (1 << (remainder - 1));
+ }
+ status = *ptr & operand;
+ if (status)
+ return -1;
+
+ *ptr = *ptr | operand;
+ return 0;
+ }
+}
+
+void ext4fs_reset_block_bmap(long int blockno, unsigned char *buffer, int index)
+{
+ int i, remainder, status;
+ unsigned char *ptr = buffer;
+ unsigned char operand;
+ i = blockno / 8;
+ remainder = blockno % 8;
+ int blocksize = EXT2_BLOCK_SIZE(ext4fs_root);
+
+ i = i - (index * blocksize);
+ if (blocksize != 1024) {
+ ptr = ptr + i;
+ operand = (1 << remainder);
+ status = *ptr & operand;
+ if (status)
+ *ptr = *ptr & ~(operand);
+ } else {
+ if (remainder == 0) {
+ ptr = ptr + i - 1;
+ operand = (1 << 7);
+ } else {
+ ptr = ptr + i;
+ operand = (1 << (remainder - 1));
+ }
+ status = *ptr & operand;
+ if (status)
+ *ptr = *ptr & ~(operand);
+ }
+}
+
+int ext4fs_set_inode_bmap(int inode_no, unsigned char *buffer, int index)
+{
+ int i, remainder, status;
+ unsigned char *ptr = buffer;
+ unsigned char operand;
+
+ inode_no -= (index * ext4fs_root->sblock.inodes_per_group);
+ i = inode_no / 8;
+ remainder = inode_no % 8;
+ if (remainder == 0) {
+ ptr = ptr + i - 1;
+ operand = (1 << 7);
+ } else {
+ ptr = ptr + i;
+ operand = (1 << (remainder - 1));
+ }
+ status = *ptr & operand;
+ if (status)
+ return -1;
+
+ *ptr = *ptr | operand;
+
+ return 0;
+}
+
+void ext4fs_reset_inode_bmap(int inode_no, unsigned char *buffer, int index)
+{
+ int i, remainder, status;
+ unsigned char *ptr = buffer;
+ unsigned char operand;
+
+ inode_no -= (index * ext4fs_root->sblock.inodes_per_group);
+ i = inode_no / 8;
+ remainder = inode_no % 8;
+ if (remainder == 0) {
+ ptr = ptr + i - 1;
+ operand = (1 << 7);
+ } else {
+ ptr = ptr + i;
+ operand = (1 << (remainder - 1));
+ }
+ status = *ptr & operand;
+ if (status)
+ *ptr = *ptr & ~(operand);
+}
+
+int ext4fs_checksum_update(unsigned int i)
+{
+ struct ext2_block_group *desc;
+ struct ext_filesystem *fs = get_fs();
+ __u16 crc = 0;
+
+ desc = (struct ext2_block_group *)&fs->gd[i];
+ if (fs->sb->feature_ro_compat & EXT4_FEATURE_RO_COMPAT_GDT_CSUM) {
+ int offset = offsetof(struct ext2_block_group, bg_checksum);
+
+ crc = ext2fs_crc16(~0, fs->sb->unique_id,
+ sizeof(fs->sb->unique_id));
+ crc = ext2fs_crc16(crc, &i, sizeof(i));
+ crc = ext2fs_crc16(crc, desc, offset);
+ offset += sizeof(desc->bg_checksum); /* skip checksum */
+ assert(offset == sizeof(*desc));
+ }
+
+ return crc;
+}
+
+static int check_void_in_dentry(struct ext2_dirent *dir, char *filename)
+{
+ int dentry_length;
+ int sizeof_void_space;
+ int new_entry_byte_reqd;
+ short padding_factor = 0;
+
+ if (dir->namelen % 4 != 0)
+ padding_factor = 4 - (dir->namelen % 4);
+
+ dentry_length = sizeof(struct ext2_dirent) +
+ dir->namelen + padding_factor;
+ sizeof_void_space = dir->direntlen - dentry_length;
+ if (sizeof_void_space == 0)
+ return 0;
+
+ padding_factor = 0;
+ if (strlen(filename) % 4 != 0)
+ padding_factor = 4 - (strlen(filename) % 4);
+
+ new_entry_byte_reqd = strlen(filename) +
+ sizeof(struct ext2_dirent) + padding_factor;
+ if (sizeof_void_space >= new_entry_byte_reqd) {
+ dir->direntlen = dentry_length;
+ return sizeof_void_space;
+ }
+
+ return 0;
+}
+
+void ext4fs_update_parent_dentry(char *filename, int *p_ino, int file_type)
+{
+ unsigned int *zero_buffer = NULL;
+ char *root_first_block_buffer = NULL;
+ int direct_blk_idx;
+ long int root_blknr;
+ long int first_block_no_of_root = 0;
+ long int previous_blknr = -1;
+ int totalbytes = 0;
+ short int padding_factor = 0;
+ unsigned int new_entry_byte_reqd;
+ unsigned int last_entry_dirlen;
+ int sizeof_void_space = 0;
+ int templength = 0;
+ int inodeno;
+ int status;
+ struct ext_filesystem *fs = get_fs();
+ /* directory entry */
+ struct ext2_dirent *dir;
+ char *ptr = NULL;
+ char *temp_dir = NULL;
+
+ zero_buffer = zalloc(fs->blksz);
+ if (!zero_buffer) {
+ printf("No Memory\n");
+ return;
+ }
+ root_first_block_buffer = zalloc(fs->blksz);
+ if (!root_first_block_buffer) {
+ free(zero_buffer);
+ printf("No Memory\n");
+ return;
+ }
+restart:
+
+ /* read the block no allocated to a file */
+ for (direct_blk_idx = 0; direct_blk_idx < INDIRECT_BLOCKS;
+ direct_blk_idx++) {
+ root_blknr = read_allocated_block(g_parent_inode,
+ direct_blk_idx);
+ if (root_blknr == 0) {
+ first_block_no_of_root = previous_blknr;
+ break;
+ }
+ previous_blknr = root_blknr;
+ }
+
+ status = ext4fs_devread(first_block_no_of_root
+ * fs->sect_perblk,
+ 0, fs->blksz, root_first_block_buffer);
+ if (status == 0)
+ goto fail;
+
+ if (ext4fs_log_journal(root_first_block_buffer, first_block_no_of_root))
+ goto fail;
+ dir = (struct ext2_dirent *)root_first_block_buffer;
+ ptr = (char *)dir;
+ totalbytes = 0;
+ while (dir->direntlen > 0) {
+ /*
+ * blocksize-totalbytes because last directory length
+ * i.e. dir->direntlen is free availble space in the
+ * block that means it is a last entry of directory
+ * entry
+ */
+
+ /* traversing the each directory entry */
+ if (fs->blksz - totalbytes == dir->direntlen) {
+ if (strlen(filename) % 4 != 0)
+ padding_factor = 4 - (strlen(filename) % 4);
+
+ new_entry_byte_reqd = strlen(filename) +
+ sizeof(struct ext2_dirent) + padding_factor;
+ padding_factor = 0;
+ /*
+ * update last directory entry length to its
+ * length because we are creating new directory
+ * entry
+ */
+ if (dir->namelen % 4 != 0)
+ padding_factor = 4 - (dir->namelen % 4);
+
+ last_entry_dirlen = dir->namelen +
+ sizeof(struct ext2_dirent) + padding_factor;
+ if ((fs->blksz - totalbytes - last_entry_dirlen) <
+ new_entry_byte_reqd) {
+ printf("1st Block Full:Allocate new block\n");
+
+ if (direct_blk_idx == INDIRECT_BLOCKS - 1) {
+ printf("Directory exceeds limit\n");
+ goto fail;
+ }
+ g_parent_inode->b.blocks.dir_blocks
+ [direct_blk_idx] = ext4fs_get_new_blk_no();
+ if (g_parent_inode->b.blocks.dir_blocks
+ [direct_blk_idx] == -1) {
+ printf("no block left to assign\n");
+ goto fail;
+ }
+ put_ext4(((uint64_t)
+ (g_parent_inode->b.
+ blocks.dir_blocks[direct_blk_idx] *
+ fs->blksz)), zero_buffer, fs->blksz);
+ g_parent_inode->size =
+ g_parent_inode->size + fs->blksz;
+ g_parent_inode->blockcnt =
+ g_parent_inode->blockcnt + fs->sect_perblk;
+ if (ext4fs_put_metadata
+ (root_first_block_buffer,
+ first_block_no_of_root))
+ goto fail;
+ goto restart;
+ }
+ dir->direntlen = last_entry_dirlen;
+ break;
+ }
+
+ templength = dir->direntlen;
+ totalbytes = totalbytes + templength;
+ sizeof_void_space = check_void_in_dentry(dir, filename);
+ if (sizeof_void_space)
+ break;
+
+ dir = (struct ext2_dirent *)((char *)dir + templength);
+ ptr = (char *)dir;
+ }
+
+ /* make a pointer ready for creating next directory entry */
+ templength = dir->direntlen;
+ totalbytes = totalbytes + templength;
+ dir = (struct ext2_dirent *)((char *)dir + templength);
+ ptr = (char *)dir;
+
+ /* get the next available inode number */
+ inodeno = ext4fs_get_new_inode_no();
+ if (inodeno == -1) {
+ printf("no inode left to assign\n");
+ goto fail;
+ }
+ dir->inode = inodeno;
+ if (sizeof_void_space)
+ dir->direntlen = sizeof_void_space;
+ else
+ dir->direntlen = fs->blksz - totalbytes;
+
+ dir->namelen = strlen(filename);
+ dir->filetype = FILETYPE_REG; /* regular file */
+ temp_dir = (char *)dir;
+ temp_dir = temp_dir + sizeof(struct ext2_dirent);
+ memcpy(temp_dir, filename, strlen(filename));
+
+ *p_ino = inodeno;
+
+ /* update or write the 1st block of root inode */
+ if (ext4fs_put_metadata(root_first_block_buffer,
+ first_block_no_of_root))
+ goto fail;
+
+fail:
+ free(zero_buffer);
+ free(root_first_block_buffer);
+}
+
+static int search_dir(struct ext2_inode *parent_inode, char *dirname)
+{
+ int status;
+ int inodeno;
+ int totalbytes;
+ int templength;
+ int direct_blk_idx;
+ long int blknr;
+ int found = 0;
+ char *ptr = NULL;
+ unsigned char *block_buffer = NULL;
+ struct ext2_dirent *dir = NULL;
+ struct ext2_dirent *previous_dir = NULL;
+ struct ext_filesystem *fs = get_fs();
+
+ /* read the block no allocated to a file */
+ for (direct_blk_idx = 0; direct_blk_idx < INDIRECT_BLOCKS;
+ direct_blk_idx++) {
+ blknr = read_allocated_block(parent_inode, direct_blk_idx);
+ if (blknr == 0)
+ goto fail;
+
+ /* read the blocks of parenet inode */
+ block_buffer = zalloc(fs->blksz);
+ if (!block_buffer)
+ goto fail;
+
+ status = ext4fs_devread(blknr * fs->sect_perblk,
+ 0, fs->blksz, (char *)block_buffer);
+ if (status == 0)
+ goto fail;
+
+ dir = (struct ext2_dirent *)block_buffer;
+ ptr = (char *)dir;
+ totalbytes = 0;
+ while (dir->direntlen >= 0) {
+ /*
+ * blocksize-totalbytes because last directory
+ * length i.e.,*dir->direntlen is free availble
+ * space in the block that means
+ * it is a last entry of directory entry
+ */
+ if (strlen(dirname) == dir->namelen) {
+ if (strncmp(dirname, ptr +
+ sizeof(struct ext2_dirent),
+ dir->namelen) == 0) {
+ previous_dir->direntlen +=
+ dir->direntlen;
+ inodeno = dir->inode;
+ dir->inode = 0;
+ found = 1;
+ break;
+ }
+ }
+
+ if (fs->blksz - totalbytes == dir->direntlen)
+ break;
+
+ /* traversing the each directory entry */
+ templength = dir->direntlen;
+ totalbytes = totalbytes + templength;
+ previous_dir = dir;
+ dir = (struct ext2_dirent *)((char *)dir + templength);
+ ptr = (char *)dir;
+ }
+
+ if (found == 1) {
+ free(block_buffer);
+ block_buffer = NULL;
+ return inodeno;
+ }
+
+ free(block_buffer);
+ block_buffer = NULL;
+ }
+
+fail:
+ free(block_buffer);
+
+ return -1;
+}
+
+static int find_dir_depth(char *dirname)
+{
+ char *token = strtok(dirname, "/");
+ int count = 0;
+ while (token != NULL) {
+ token = strtok(NULL, "/");
+ count++;
+ }
+ return count + 1 + 1;
+ /*
+ * for example for string /home/temp
+ * depth=home(1)+temp(1)+1 extra for NULL;
+ * so count is 4;
+ */
+}
+
+static int parse_path(char **arr, char *dirname)
+{
+ char *token = strtok(dirname, "/");
+ int i = 0;
+
+ /* add root */
+ arr[i] = zalloc(strlen("/") + 1);
+ if (!arr[i])
+ return -ENOMEM;
+
+ arr[i++] = "/";
+
+ /* add each path entry after root */
+ while (token != NULL) {
+ arr[i] = zalloc(strlen(token) + 1);
+ if (!arr[i])
+ return -ENOMEM;
+ memcpy(arr[i++], token, strlen(token));
+ token = strtok(NULL, "/");
+ }
+ arr[i] = NULL;
+
+ return 0;
+}
+
+int ext4fs_iget(int inode_no, struct ext2_inode *inode)
+{
+ if (ext4fs_read_inode(ext4fs_root, inode_no, inode) == 0)
+ return -1;
+
+ return 0;
+}
+
+/*
+ * Function: ext4fs_get_parent_inode_num
+ * Return Value: inode Number of the parent directory of file/Directory to be
+ * created
+ * dirname : Input parmater, input path name of the file/directory to be created
+ * dname : Output parameter, to be filled with the name of the directory
+ * extracted from dirname
+ */
+int ext4fs_get_parent_inode_num(const char *dirname, char *dname, int flags)
+{
+ int i;
+ int depth = 0;
+ int matched_inode_no;
+ int result_inode_no = -1;
+ char **ptr = NULL;
+ char *depth_dirname = NULL;
+ char *parse_dirname = NULL;
+ struct ext2_inode *parent_inode = NULL;
+ struct ext2_inode *first_inode = NULL;
+ struct ext2_inode temp_inode;
+
+ if (*dirname != '/') {
+ printf("Please supply Absolute path\n");
+ return -1;
+ }
+
+ /* TODO: input validation make equivalent to linux */
+ depth_dirname = zalloc(strlen(dirname) + 1);
+ if (!depth_dirname)
+ return -ENOMEM;
+
+ memcpy(depth_dirname, dirname, strlen(dirname));
+ depth = find_dir_depth(depth_dirname);
+ parse_dirname = zalloc(strlen(dirname) + 1);
+ if (!parse_dirname)
+ goto fail;
+ memcpy(parse_dirname, dirname, strlen(dirname));
+
+ /* allocate memory for each directory level */
+ ptr = zalloc((depth) * sizeof(char *));
+ if (!ptr)
+ goto fail;
+ if (parse_path(ptr, parse_dirname))
+ goto fail;
+ parent_inode = zalloc(sizeof(struct ext2_inode));
+ if (!parent_inode)
+ goto fail;
+ first_inode = zalloc(sizeof(struct ext2_inode));
+ if (!first_inode)
+ goto fail;
+ memcpy(parent_inode, ext4fs_root->inode, sizeof(struct ext2_inode));
+ memcpy(first_inode, parent_inode, sizeof(struct ext2_inode));
+ if (flags & F_FILE)
+ result_inode_no = EXT2_ROOT_INO;
+ for (i = 1; i < depth; i++) {
+ matched_inode_no = search_dir(parent_inode, ptr[i]);
+ if (matched_inode_no == -1) {
+ if (ptr[i + 1] == NULL && i == 1) {
+ result_inode_no = EXT2_ROOT_INO;
+ goto end;
+ } else {
+ if (ptr[i + 1] == NULL)
+ break;
+ printf("Invalid path\n");
+ result_inode_no = -1;
+ goto fail;
+ }
+ } else {
+ if (ptr[i + 1] != NULL) {
+ memset(parent_inode, '\0',
+ sizeof(struct ext2_inode));
+ if (ext4fs_iget(matched_inode_no,
+ parent_inode)) {
+ result_inode_no = -1;
+ goto fail;
+ }
+ result_inode_no = matched_inode_no;
+ } else {
+ break;
+ }
+ }
+ }
+
+end:
+ if (i == 1)
+ matched_inode_no = search_dir(first_inode, ptr[i]);
+ else
+ matched_inode_no = search_dir(parent_inode, ptr[i]);
+
+ if (matched_inode_no != -1) {
+ ext4fs_iget(matched_inode_no, &temp_inode);
+ if (temp_inode.mode & S_IFDIR) {
+ printf("It is a Directory\n");
+ result_inode_no = -1;
+ goto fail;
+ }
+ }
+
+ if (strlen(ptr[i]) > 256) {
+ result_inode_no = -1;
+ goto fail;
+ }
+ memcpy(dname, ptr[i], strlen(ptr[i]));
+
+fail:
+ free(depth_dirname);
+ free(parse_dirname);
+ free(ptr);
+ free(parent_inode);
+ free(first_inode);
+
+ return result_inode_no;
+}
+
+static int check_filename(char *filename, unsigned int blknr)
+{
+ unsigned int first_block_no_of_root;
+ int totalbytes = 0;
+ int templength = 0;
+ int status, inodeno;
+ int found = 0;
+ char *root_first_block_buffer = NULL;
+ char *root_first_block_addr = NULL;
+ struct ext2_dirent *dir = NULL;
+ struct ext2_dirent *previous_dir = NULL;
+ char *ptr = NULL;
+ struct ext_filesystem *fs = get_fs();
+
+ /* get the first block of root */
+ first_block_no_of_root = blknr;
+ root_first_block_buffer = zalloc(fs->blksz);
+ if (!root_first_block_buffer)
+ return -ENOMEM;
+ root_first_block_addr = root_first_block_buffer;
+ status = ext4fs_devread(first_block_no_of_root *
+ fs->sect_perblk, 0,
+ fs->blksz, root_first_block_buffer);
+ if (status == 0)
+ goto fail;
+
+ if (ext4fs_log_journal(root_first_block_buffer, first_block_no_of_root))
+ goto fail;
+ dir = (struct ext2_dirent *)root_first_block_buffer;
+ ptr = (char *)dir;
+ totalbytes = 0;
+ while (dir->direntlen >= 0) {
+ /*
+ * blocksize-totalbytes because last
+ * directory length i.e., *dir->direntlen
+ * is free availble space in the block that
+ * means it is a last entry of directory entry
+ */
+ if (strlen(filename) == dir->namelen) {
+ if (strncmp(filename, ptr + sizeof(struct ext2_dirent),
+ dir->namelen) == 0) {
+ printf("file found deleting\n");
+ previous_dir->direntlen += dir->direntlen;
+ inodeno = dir->inode;
+ dir->inode = 0;
+ found = 1;
+ break;
+ }
+ }
+
+ if (fs->blksz - totalbytes == dir->direntlen)
+ break;
+
+ /* traversing the each directory entry */
+ templength = dir->direntlen;
+ totalbytes = totalbytes + templength;
+ previous_dir = dir;
+ dir = (struct ext2_dirent *)((char *)dir + templength);
+ ptr = (char *)dir;
+ }
+
+
+ if (found == 1) {
+ if (ext4fs_put_metadata(root_first_block_addr,
+ first_block_no_of_root))
+ goto fail;
+ return inodeno;
+ }
+fail:
+ free(root_first_block_buffer);
+
+ return -1;
+}
+
+int ext4fs_filename_check(char *filename)
+{
+ short direct_blk_idx = 0;
+ long int blknr = -1;
+ int inodeno = -1;
+
+ /* read the block no allocated to a file */
+ for (direct_blk_idx = 0; direct_blk_idx < INDIRECT_BLOCKS;
+ direct_blk_idx++) {
+ blknr = read_allocated_block(g_parent_inode, direct_blk_idx);
+ if (blknr == 0)
+ break;
+ inodeno = check_filename(filename, blknr);
+ if (inodeno != -1)
+ return inodeno;
+ }
+
+ return -1;
+}
+
+long int ext4fs_get_new_blk_no(void)
+{
+ short i;
+ short status;
+ int remainder;
+ unsigned int bg_idx;
+ static int prev_bg_bitmap_index = -1;
+ unsigned int blk_per_grp = ext4fs_root->sblock.blocks_per_group;
+ struct ext_filesystem *fs = get_fs();
+ char *journal_buffer = zalloc(fs->blksz);
+ char *zero_buffer = zalloc(fs->blksz);
+ if (!journal_buffer || !zero_buffer)
+ goto fail;
+ struct ext2_block_group *gd = (struct ext2_block_group *)fs->gdtable;
+
+ if (fs->first_pass_bbmap == 0) {
+ for (i = 0; i < fs->no_blkgrp; i++) {
+ if (gd[i].free_blocks) {
+ if (gd[i].bg_flags & EXT4_BG_BLOCK_UNINIT) {
+ put_ext4(((uint64_t) (gd[i].block_id *
+ fs->blksz)),
+ zero_buffer, fs->blksz);
+ gd[i].bg_flags =
+ gd[i].
+ bg_flags & ~EXT4_BG_BLOCK_UNINIT;
+ memcpy(fs->blk_bmaps[i], zero_buffer,
+ fs->blksz);
+ }
+ fs->curr_blkno =
+ _get_new_blk_no(fs->blk_bmaps[i]);
+ if (fs->curr_blkno == -1)
+ /* if block bitmap is completely fill */
+ continue;
+ fs->curr_blkno = fs->curr_blkno +
+ (i * fs->blksz * 8);
+ fs->first_pass_bbmap++;
+ gd[i].free_blocks--;
+ fs->sb->free_blocks--;
+ status = ext4fs_devread(gd[i].block_id *
+ fs->sect_perblk, 0,
+ fs->blksz,
+ journal_buffer);
+ if (status == 0)
+ goto fail;
+ if (ext4fs_log_journal(journal_buffer,
+ gd[i].block_id))
+ goto fail;
+ goto success;
+ } else {
+ debug("no space left on block group %d\n", i);
+ }
+ }
+
+ goto fail;
+ } else {
+restart:
+ fs->curr_blkno++;
+ /* get the blockbitmap index respective to blockno */
+ if (fs->blksz != 1024) {
+ bg_idx = fs->curr_blkno / blk_per_grp;
+ } else {
+ bg_idx = fs->curr_blkno / blk_per_grp;
+ remainder = fs->curr_blkno % blk_per_grp;
+ if (!remainder)
+ bg_idx--;
+ }
+
+ /*
+ * To skip completely filled block group bitmaps
+ * Optimize the block allocation
+ */
+ if (bg_idx >= fs->no_blkgrp)
+ goto fail;
+
+ if (gd[bg_idx].free_blocks == 0) {
+ debug("block group %u is full. Skipping\n", bg_idx);
+ fs->curr_blkno = fs->curr_blkno + blk_per_grp;
+ fs->curr_blkno--;
+ goto restart;
+ }
+
+ if (gd[bg_idx].bg_flags & EXT4_BG_BLOCK_UNINIT) {
+ memset(zero_buffer, '\0', fs->blksz);
+ put_ext4(((uint64_t) (gd[bg_idx].block_id * fs->blksz)),
+ zero_buffer, fs->blksz);
+ memcpy(fs->blk_bmaps[bg_idx], zero_buffer, fs->blksz);
+ gd[bg_idx].bg_flags = gd[bg_idx].bg_flags &
+ ~EXT4_BG_BLOCK_UNINIT;
+ }
+
+ if (ext4fs_set_block_bmap(fs->curr_blkno, fs->blk_bmaps[bg_idx],
+ bg_idx) != 0) {
+ debug("going for restart for the block no %ld %u\n",
+ fs->curr_blkno, bg_idx);
+ goto restart;
+ }
+
+ /* journal backup */
+ if (prev_bg_bitmap_index != bg_idx) {
+ memset(journal_buffer, '\0', fs->blksz);
+ status = ext4fs_devread(gd[bg_idx].block_id
+ * fs->sect_perblk,
+ 0, fs->blksz, journal_buffer);
+ if (status == 0)
+ goto fail;
+ if (ext4fs_log_journal(journal_buffer,
+ gd[bg_idx].block_id))
+ goto fail;
+
+ prev_bg_bitmap_index = bg_idx;
+ }
+ gd[bg_idx].free_blocks--;
+ fs->sb->free_blocks--;
+ goto success;
+ }
+success:
+ free(journal_buffer);
+ free(zero_buffer);
+
+ return fs->curr_blkno;
+fail:
+ free(journal_buffer);
+ free(zero_buffer);
+
+ return -1;
+}
+
+int ext4fs_get_new_inode_no(void)
+{
+ short i;
+ short status;
+ unsigned int ibmap_idx;
+ static int prev_inode_bitmap_index = -1;
+ unsigned int inodes_per_grp = ext4fs_root->sblock.inodes_per_group;
+ struct ext_filesystem *fs = get_fs();
+ char *journal_buffer = zalloc(fs->blksz);
+ char *zero_buffer = zalloc(fs->blksz);
+ if (!journal_buffer || !zero_buffer)
+ goto fail;
+ struct ext2_block_group *gd = (struct ext2_block_group *)fs->gdtable;
+
+ if (fs->first_pass_ibmap == 0) {
+ for (i = 0; i < fs->no_blkgrp; i++) {
+ if (gd[i].free_inodes) {
+ if (gd[i].bg_itable_unused != gd[i].free_inodes)
+ gd[i].bg_itable_unused =
+ gd[i].free_inodes;
+ if (gd[i].bg_flags & EXT4_BG_INODE_UNINIT) {
+ put_ext4(((uint64_t)
+ (gd[i].inode_id * fs->blksz)),
+ zero_buffer, fs->blksz);
+ gd[i].bg_flags = gd[i].bg_flags &
+ ~EXT4_BG_INODE_UNINIT;
+ memcpy(fs->inode_bmaps[i],
+ zero_buffer, fs->blksz);
+ }
+ fs->curr_inode_no =
+ _get_new_inode_no(fs->inode_bmaps[i]);
+ if (fs->curr_inode_no == -1)
+ /* if block bitmap is completely fill */
+ continue;
+ fs->curr_inode_no = fs->curr_inode_no +
+ (i * inodes_per_grp);
+ fs->first_pass_ibmap++;
+ gd[i].free_inodes--;
+ gd[i].bg_itable_unused--;
+ fs->sb->free_inodes--;
+ status = ext4fs_devread(gd[i].inode_id *
+ fs->sect_perblk, 0,
+ fs->blksz,
+ journal_buffer);
+ if (status == 0)
+ goto fail;
+ if (ext4fs_log_journal(journal_buffer,
+ gd[i].inode_id))
+ goto fail;
+ goto success;
+ } else
+ debug("no inode left on block group %d\n", i);
+ }
+ goto fail;
+ } else {
+restart:
+ fs->curr_inode_no++;
+ /* get the blockbitmap index respective to blockno */
+ ibmap_idx = fs->curr_inode_no / inodes_per_grp;
+ if (gd[ibmap_idx].bg_flags & EXT4_BG_INODE_UNINIT) {
+ memset(zero_buffer, '\0', fs->blksz);
+ put_ext4(((uint64_t) (gd[ibmap_idx].inode_id *
+ fs->blksz)), zero_buffer,
+ fs->blksz);
+ gd[ibmap_idx].bg_flags =
+ gd[ibmap_idx].bg_flags & ~EXT4_BG_INODE_UNINIT;
+ memcpy(fs->inode_bmaps[ibmap_idx], zero_buffer,
+ fs->blksz);
+ }
+
+ if (ext4fs_set_inode_bmap(fs->curr_inode_no,
+ fs->inode_bmaps[ibmap_idx],
+ ibmap_idx) != 0) {
+ debug("going for restart for the block no %d %u\n",
+ fs->curr_inode_no, ibmap_idx);
+ goto restart;
+ }
+
+ /* journal backup */
+ if (prev_inode_bitmap_index != ibmap_idx) {
+ memset(journal_buffer, '\0', fs->blksz);
+ status = ext4fs_devread(gd[ibmap_idx].inode_id
+ * fs->sect_perblk,
+ 0, fs->blksz, journal_buffer);
+ if (status == 0)
+ goto fail;
+ if (ext4fs_log_journal(journal_buffer,
+ gd[ibmap_idx].inode_id))
+ goto fail;
+ prev_inode_bitmap_index = ibmap_idx;
+ }
+ if (gd[ibmap_idx].bg_itable_unused != gd[ibmap_idx].free_inodes)
+ gd[ibmap_idx].bg_itable_unused =
+ gd[ibmap_idx].free_inodes;
+ gd[ibmap_idx].free_inodes--;
+ gd[ibmap_idx].bg_itable_unused--;
+ fs->sb->free_inodes--;
+ goto success;
+ }
+
+success:
+ free(journal_buffer);
+ free(zero_buffer);
+
+ return fs->curr_inode_no;
+fail:
+ free(journal_buffer);
+ free(zero_buffer);
+
+ return -1;
+
+}
+
+
+static void alloc_single_indirect_block(struct ext2_inode *file_inode,
+ unsigned int *total_remaining_blocks,
+ unsigned int *no_blks_reqd)
+{
+ short i;
+ short status;
+ long int actual_block_no;
+ long int si_blockno;
+ /* si :single indirect */
+ unsigned int *si_buffer = NULL;
+ unsigned int *si_start_addr = NULL;
+ struct ext_filesystem *fs = get_fs();
+
+ if (*total_remaining_blocks != 0) {
+ si_buffer = zalloc(fs->blksz);
+ if (!si_buffer) {
+ printf("No Memory\n");
+ return;
+ }
+ si_start_addr = si_buffer;
+ si_blockno = ext4fs_get_new_blk_no();
+ if (si_blockno == -1) {
+ printf("no block left to assign\n");
+ goto fail;
+ }
+ (*no_blks_reqd)++;
+ debug("SIPB %ld: %u\n", si_blockno, *total_remaining_blocks);
+
+ status = ext4fs_devread(si_blockno * fs->sect_perblk,
+ 0, fs->blksz, (char *)si_buffer);
+ memset(si_buffer, '\0', fs->blksz);
+ if (status == 0)
+ goto fail;
+
+ for (i = 0; i < (fs->blksz / sizeof(int)); i++) {
+ actual_block_no = ext4fs_get_new_blk_no();
+ if (actual_block_no == -1) {
+ printf("no block left to assign\n");
+ goto fail;
+ }
+ *si_buffer = actual_block_no;
+ debug("SIAB %u: %u\n", *si_buffer,
+ *total_remaining_blocks);
+
+ si_buffer++;
+ (*total_remaining_blocks)--;
+ if (*total_remaining_blocks == 0)
+ break;
+ }
+
+ /* write the block to disk */
+ put_ext4(((uint64_t) (si_blockno * fs->blksz)),
+ si_start_addr, fs->blksz);
+ file_inode->b.blocks.indir_block = si_blockno;
+ }
+fail:
+ free(si_start_addr);
+}
+
+static void alloc_double_indirect_block(struct ext2_inode *file_inode,
+ unsigned int *total_remaining_blocks,
+ unsigned int *no_blks_reqd)
+{
+ short i;
+ short j;
+ short status;
+ long int actual_block_no;
+ /* di:double indirect */
+ long int di_blockno_parent;
+ long int di_blockno_child;
+ unsigned int *di_parent_buffer = NULL;
+ unsigned int *di_child_buff = NULL;
+ unsigned int *di_block_start_addr = NULL;
+ unsigned int *di_child_buff_start = NULL;
+ struct ext_filesystem *fs = get_fs();
+
+ if (*total_remaining_blocks != 0) {
+ /* double indirect parent block connecting to inode */
+ di_blockno_parent = ext4fs_get_new_blk_no();
+ if (di_blockno_parent == -1) {
+ printf("no block left to assign\n");
+ goto fail;
+ }
+ di_parent_buffer = zalloc(fs->blksz);
+ if (!di_parent_buffer)
+ goto fail;
+
+ di_block_start_addr = di_parent_buffer;
+ (*no_blks_reqd)++;
+ debug("DIPB %ld: %u\n", di_blockno_parent,
+ *total_remaining_blocks);
+
+ status = ext4fs_devread(di_blockno_parent *
+ fs->sect_perblk, 0,
+ fs->blksz, (char *)di_parent_buffer);
+ memset(di_parent_buffer, '\0', fs->blksz);
+
+ /*
+ * start:for each double indirect parent
+ * block create one more block
+ */
+ for (i = 0; i < (fs->blksz / sizeof(int)); i++) {
+ di_blockno_child = ext4fs_get_new_blk_no();
+ if (di_blockno_child == -1) {
+ printf("no block left to assign\n");
+ goto fail;
+ }
+ di_child_buff = zalloc(fs->blksz);
+ if (!di_child_buff)
+ goto fail;
+
+ di_child_buff_start = di_child_buff;
+ *di_parent_buffer = di_blockno_child;
+ di_parent_buffer++;
+ (*no_blks_reqd)++;
+ debug("DICB %ld: %u\n", di_blockno_child,
+ *total_remaining_blocks);
+
+ status = ext4fs_devread(di_blockno_child *
+ fs->sect_perblk, 0,
+ fs->blksz,
+ (char *)di_child_buff);
+ memset(di_child_buff, '\0', fs->blksz);
+ /* filling of actual datablocks for each child */
+ for (j = 0; j < (fs->blksz / sizeof(int)); j++) {
+ actual_block_no = ext4fs_get_new_blk_no();
+ if (actual_block_no == -1) {
+ printf("no block left to assign\n");
+ goto fail;
+ }
+ *di_child_buff = actual_block_no;
+ debug("DIAB %ld: %u\n", actual_block_no,
+ *total_remaining_blocks);
+
+ di_child_buff++;
+ (*total_remaining_blocks)--;
+ if (*total_remaining_blocks == 0)
+ break;
+ }
+ /* write the block table */
+ put_ext4(((uint64_t) (di_blockno_child * fs->blksz)),
+ di_child_buff_start, fs->blksz);
+ free(di_child_buff_start);
+ di_child_buff_start = NULL;
+
+ if (*total_remaining_blocks == 0)
+ break;
+ }
+ put_ext4(((uint64_t) (di_blockno_parent * fs->blksz)),
+ di_block_start_addr, fs->blksz);
+ file_inode->b.blocks.double_indir_block = di_blockno_parent;
+ }
+fail:
+ free(di_block_start_addr);
+}
+
+static void alloc_triple_indirect_block(struct ext2_inode *file_inode,
+ unsigned int *total_remaining_blocks,
+ unsigned int *no_blks_reqd)
+{
+ short i;
+ short j;
+ short k;
+ long int actual_block_no;
+ /* ti: Triple Indirect */
+ long int ti_gp_blockno;
+ long int ti_parent_blockno;
+ long int ti_child_blockno;
+ unsigned int *ti_gp_buff = NULL;
+ unsigned int *ti_parent_buff = NULL;
+ unsigned int *ti_child_buff = NULL;
+ unsigned int *ti_gp_buff_start_addr = NULL;
+ unsigned int *ti_pbuff_start_addr = NULL;
+ unsigned int *ti_cbuff_start_addr = NULL;
+ struct ext_filesystem *fs = get_fs();
+ if (*total_remaining_blocks != 0) {
+ /* triple indirect grand parent block connecting to inode */
+ ti_gp_blockno = ext4fs_get_new_blk_no();
+ if (ti_gp_blockno == -1) {
+ printf("no block left to assign\n");
+ goto fail;
+ }
+ ti_gp_buff = zalloc(fs->blksz);
+ if (!ti_gp_buff)
+ goto fail;
+
+ ti_gp_buff_start_addr = ti_gp_buff;
+ (*no_blks_reqd)++;
+ debug("TIGPB %ld: %u\n", ti_gp_blockno,
+ *total_remaining_blocks);
+
+ /* for each 4 byte grand parent entry create one more block */
+ for (i = 0; i < (fs->blksz / sizeof(int)); i++) {
+ ti_parent_blockno = ext4fs_get_new_blk_no();
+ if (ti_parent_blockno == -1) {
+ printf("no block left to assign\n");
+ goto fail;
+ }
+ ti_parent_buff = zalloc(fs->blksz);
+ if (!ti_parent_buff)
+ goto fail;
+
+ ti_pbuff_start_addr = ti_parent_buff;
+ *ti_gp_buff = ti_parent_blockno;
+ ti_gp_buff++;
+ (*no_blks_reqd)++;
+ debug("TIPB %ld: %u\n", ti_parent_blockno,
+ *total_remaining_blocks);
+
+ /* for each 4 byte entry parent create one more block */
+ for (j = 0; j < (fs->blksz / sizeof(int)); j++) {
+ ti_child_blockno = ext4fs_get_new_blk_no();
+ if (ti_child_blockno == -1) {
+ printf("no block left assign\n");
+ goto fail;
+ }
+ ti_child_buff = zalloc(fs->blksz);
+ if (!ti_child_buff)
+ goto fail;
+
+ ti_cbuff_start_addr = ti_child_buff;
+ *ti_parent_buff = ti_child_blockno;
+ ti_parent_buff++;
+ (*no_blks_reqd)++;
+ debug("TICB %ld: %u\n", ti_parent_blockno,
+ *total_remaining_blocks);
+
+ /* fill actual datablocks for each child */
+ for (k = 0; k < (fs->blksz / sizeof(int));
+ k++) {
+ actual_block_no =
+ ext4fs_get_new_blk_no();
+ if (actual_block_no == -1) {
+ printf("no block left\n");
+ goto fail;
+ }
+ *ti_child_buff = actual_block_no;
+ debug("TIAB %ld: %u\n", actual_block_no,
+ *total_remaining_blocks);
+
+ ti_child_buff++;
+ (*total_remaining_blocks)--;
+ if (*total_remaining_blocks == 0)
+ break;
+ }
+ /* write the child block */
+ put_ext4(((uint64_t) (ti_child_blockno *
+ fs->blksz)),
+ ti_cbuff_start_addr, fs->blksz);
+ free(ti_cbuff_start_addr);
+
+ if (*total_remaining_blocks == 0)
+ break;
+ }
+ /* write the parent block */
+ put_ext4(((uint64_t) (ti_parent_blockno * fs->blksz)),
+ ti_pbuff_start_addr, fs->blksz);
+ free(ti_pbuff_start_addr);
+
+ if (*total_remaining_blocks == 0)
+ break;
+ }
+ /* write the grand parent block */
+ put_ext4(((uint64_t) (ti_gp_blockno * fs->blksz)),
+ ti_gp_buff_start_addr, fs->blksz);
+ file_inode->b.blocks.triple_indir_block = ti_gp_blockno;
+ }
+fail:
+ free(ti_gp_buff_start_addr);
+}
+
+void ext4fs_allocate_blocks(struct ext2_inode *file_inode,
+ unsigned int total_remaining_blocks,
+ unsigned int *total_no_of_block)
+{
+ short i;
+ long int direct_blockno;
+ unsigned int no_blks_reqd = 0;
+
+ /* allocation of direct blocks */
+ for (i = 0; i < INDIRECT_BLOCKS; i++) {
+ direct_blockno = ext4fs_get_new_blk_no();
+ if (direct_blockno == -1) {
+ printf("no block left to assign\n");
+ return;
+ }
+ file_inode->b.blocks.dir_blocks[i] = direct_blockno;
+ debug("DB %ld: %u\n", direct_blockno, total_remaining_blocks);
+
+ total_remaining_blocks--;
+ if (total_remaining_blocks == 0)
+ break;
+ }
+
+ alloc_single_indirect_block(file_inode, &total_remaining_blocks,
+ &no_blks_reqd);
+ alloc_double_indirect_block(file_inode, &total_remaining_blocks,
+ &no_blks_reqd);
+ alloc_triple_indirect_block(file_inode, &total_remaining_blocks,
+ &no_blks_reqd);
+ *total_no_of_block += no_blks_reqd;
+}
+
+#endif
+
+static struct ext4_extent_header *ext4fs_get_extent_block
+ (struct ext2_data *data, char *buf,
+ struct ext4_extent_header *ext_block,
+ uint32_t fileblock, int log2_blksz)
+{
+ struct ext4_extent_idx *index;
+ unsigned long long block;
+ struct ext_filesystem *fs = get_fs();
+ int i;
+
+ while (1) {
+ index = (struct ext4_extent_idx *)(ext_block + 1);
+
+ if (le32_to_cpu(ext_block->eh_magic) != EXT4_EXT_MAGIC)
+ return 0;
+
+ if (ext_block->eh_depth == 0)
+ return ext_block;
+ i = -1;
+ do {
+ i++;
+ if (i >= le32_to_cpu(ext_block->eh_entries))
+ break;
+ } while (fileblock > le32_to_cpu(index[i].ei_block));
+
+ if (--i < 0)
+ return 0;
+
+ block = le32_to_cpu(index[i].ei_leaf_hi);
+ block = (block << 32) + le32_to_cpu(index[i].ei_leaf_lo);
+
+ if (ext4fs_devread(block << log2_blksz, 0, fs->blksz, buf))
+ ext_block = (struct ext4_extent_header *)buf;
+ else
+ return 0;
+ }
+}
+
+static int ext4fs_blockgroup
+ (struct ext2_data *data, int group, struct ext2_block_group *blkgrp)
+{
+ long int blkno;
+ unsigned int blkoff, desc_per_blk;
+
+ desc_per_blk = EXT2_BLOCK_SIZE(data) / sizeof(struct ext2_block_group);
+
+ blkno = __le32_to_cpu(data->sblock.first_data_block) + 1 +
+ group / desc_per_blk;
+ blkoff = (group % desc_per_blk) * sizeof(struct ext2_block_group);
+
+ debug("ext4fs read %d group descriptor (blkno %ld blkoff %u)\n",
+ group, blkno, blkoff);
+
+ return ext4fs_devread(blkno << LOG2_EXT2_BLOCK_SIZE(data),
+ blkoff, sizeof(struct ext2_block_group),
+ (char *)blkgrp);
+}
+
+int ext4fs_read_inode(struct ext2_data *data, int ino, struct ext2_inode *inode)
+{
+ struct ext2_block_group blkgrp;
+ struct ext2_sblock *sblock = &data->sblock;
+ struct ext_filesystem *fs = get_fs();
+ int inodes_per_block, status;
+ long int blkno;
+ unsigned int blkoff;
+
+ /* It is easier to calculate if the first inode is 0. */
+ ino--;
+ status = ext4fs_blockgroup(data, ino / __le32_to_cpu
+ (sblock->inodes_per_group), &blkgrp);
+ if (status == 0)
+ return 0;
+
+ inodes_per_block = EXT2_BLOCK_SIZE(data) / fs->inodesz;
+ blkno = __le32_to_cpu(blkgrp.inode_table_id) +
+ (ino % __le32_to_cpu(sblock->inodes_per_group)) / inodes_per_block;
+ blkoff = (ino % inodes_per_block) * fs->inodesz;
+ /* Read the inode. */
+ status = ext4fs_devread(blkno << LOG2_EXT2_BLOCK_SIZE(data), blkoff,
+ sizeof(struct ext2_inode), (char *)inode);
+ if (status == 0)
+ return 0;
+
+ return 1;
+}
+
+long int read_allocated_block(struct ext2_inode *inode, int fileblock)
+{
+ long int blknr;
+ int blksz;
+ int log2_blksz;
+ int status;
+ long int rblock;
+ long int perblock_parent;
+ long int perblock_child;
+ unsigned long long start;
+ /* get the blocksize of the filesystem */
+ blksz = EXT2_BLOCK_SIZE(ext4fs_root);
+ log2_blksz = LOG2_EXT2_BLOCK_SIZE(ext4fs_root);
+ if (le32_to_cpu(inode->flags) & EXT4_EXTENTS_FL) {
+ char *buf = zalloc(blksz);
+ if (!buf)
+ return -ENOMEM;
+ struct ext4_extent_header *ext_block;
+ struct ext4_extent *extent;
+ int i = -1;
+ ext_block = ext4fs_get_extent_block(ext4fs_root, buf,
+ (struct ext4_extent_header
+ *)inode->b.
+ blocks.dir_blocks,
+ fileblock, log2_blksz);
+ if (!ext_block) {
+ printf("invalid extent block\n");
+ free(buf);
+ return -EINVAL;
+ }
+
+ extent = (struct ext4_extent *)(ext_block + 1);
+
+ do {
+ i++;
+ if (i >= le32_to_cpu(ext_block->eh_entries))
+ break;
+ } while (fileblock >= le32_to_cpu(extent[i].ee_block));
+ if (--i >= 0) {
+ fileblock -= le32_to_cpu(extent[i].ee_block);
+ if (fileblock >= le32_to_cpu(extent[i].ee_len)) {
+ free(buf);
+ return 0;
+ }
+
+ start = le32_to_cpu(extent[i].ee_start_hi);
+ start = (start << 32) +
+ le32_to_cpu(extent[i].ee_start_lo);
+ free(buf);
+ return fileblock + start;
+ }
+
+ printf("Extent Error\n");
+ free(buf);
+ return -1;
+ }
+
+ /* Direct blocks. */
+ if (fileblock < INDIRECT_BLOCKS)
+ blknr = __le32_to_cpu(inode->b.blocks.dir_blocks[fileblock]);
+
+ /* Indirect. */
+ else if (fileblock < (INDIRECT_BLOCKS + (blksz / 4))) {
+ if (ext4fs_indir1_block == NULL) {
+ ext4fs_indir1_block = zalloc(blksz);
+ if (ext4fs_indir1_block == NULL) {
+ printf("** SI ext2fs read block (indir 1)"
+ "malloc failed. **\n");
+ return -1;
+ }
+ ext4fs_indir1_size = blksz;
+ ext4fs_indir1_blkno = -1;
+ }
+ if (blksz != ext4fs_indir1_size) {
+ free(ext4fs_indir1_block);
+ ext4fs_indir1_block = NULL;
+ ext4fs_indir1_size = 0;
+ ext4fs_indir1_blkno = -1;
+ ext4fs_indir1_block = zalloc(blksz);
+ if (ext4fs_indir1_block == NULL) {
+ printf("** SI ext2fs read block (indir 1):"
+ "malloc failed. **\n");
+ return -1;
+ }
+ ext4fs_indir1_size = blksz;
+ }
+ if ((__le32_to_cpu(inode->b.blocks.indir_block) <<
+ log2_blksz) != ext4fs_indir1_blkno) {
+ status =
+ ext4fs_devread(__le32_to_cpu
+ (inode->b.blocks.
+ indir_block) << log2_blksz, 0,
+ blksz, (char *)ext4fs_indir1_block);
+ if (status == 0) {
+ printf("** SI ext2fs read block (indir 1)"
+ "failed. **\n");
+ return 0;
+ }
+ ext4fs_indir1_blkno =
+ __le32_to_cpu(inode->b.blocks.
+ indir_block) << log2_blksz;
+ }
+ blknr = __le32_to_cpu(ext4fs_indir1_block
+ [fileblock - INDIRECT_BLOCKS]);
+ }
+ /* Double indirect. */
+ else if (fileblock < (INDIRECT_BLOCKS + (blksz / 4 *
+ (blksz / 4 + 1)))) {
+
+ long int perblock = blksz / 4;
+ long int rblock = fileblock - (INDIRECT_BLOCKS + blksz / 4);
+
+ if (ext4fs_indir1_block == NULL) {
+ ext4fs_indir1_block = zalloc(blksz);
+ if (ext4fs_indir1_block == NULL) {
+ printf("** DI ext2fs read block (indir 2 1)"
+ "malloc failed. **\n");
+ return -1;
+ }
+ ext4fs_indir1_size = blksz;
+ ext4fs_indir1_blkno = -1;
+ }
+ if (blksz != ext4fs_indir1_size) {
+ free(ext4fs_indir1_block);
+ ext4fs_indir1_block = NULL;
+ ext4fs_indir1_size = 0;
+ ext4fs_indir1_blkno = -1;
+ ext4fs_indir1_block = zalloc(blksz);
+ if (ext4fs_indir1_block == NULL) {
+ printf("** DI ext2fs read block (indir 2 1)"
+ "malloc failed. **\n");
+ return -1;
+ }
+ ext4fs_indir1_size = blksz;
+ }
+ if ((__le32_to_cpu(inode->b.blocks.double_indir_block) <<
+ log2_blksz) != ext4fs_indir1_blkno) {
+ status =
+ ext4fs_devread(__le32_to_cpu
+ (inode->b.blocks.
+ double_indir_block) << log2_blksz,
+ 0, blksz,
+ (char *)ext4fs_indir1_block);
+ if (status == 0) {
+ printf("** DI ext2fs read block (indir 2 1)"
+ "failed. **\n");
+ return -1;
+ }
+ ext4fs_indir1_blkno =
+ __le32_to_cpu(inode->b.blocks.double_indir_block) <<
+ log2_blksz;
+ }
+
+ if (ext4fs_indir2_block == NULL) {
+ ext4fs_indir2_block = zalloc(blksz);
+ if (ext4fs_indir2_block == NULL) {
+ printf("** DI ext2fs read block (indir 2 2)"
+ "malloc failed. **\n");
+ return -1;
+ }
+ ext4fs_indir2_size = blksz;
+ ext4fs_indir2_blkno = -1;
+ }
+ if (blksz != ext4fs_indir2_size) {
+ free(ext4fs_indir2_block);
+ ext4fs_indir2_block = NULL;
+ ext4fs_indir2_size = 0;
+ ext4fs_indir2_blkno = -1;
+ ext4fs_indir2_block = zalloc(blksz);
+ if (ext4fs_indir2_block == NULL) {
+ printf("** DI ext2fs read block (indir 2 2)"
+ "malloc failed. **\n");
+ return -1;
+ }
+ ext4fs_indir2_size = blksz;
+ }
+ if ((__le32_to_cpu(ext4fs_indir1_block[rblock / perblock]) <<
+ log2_blksz) != ext4fs_indir2_blkno) {
+ status = ext4fs_devread(__le32_to_cpu
+ (ext4fs_indir1_block
+ [rblock /
+ perblock]) << log2_blksz, 0,
+ blksz,
+ (char *)ext4fs_indir2_block);
+ if (status == 0) {
+ printf("** DI ext2fs read block (indir 2 2)"
+ "failed. **\n");
+ return -1;
+ }
+ ext4fs_indir2_blkno =
+ __le32_to_cpu(ext4fs_indir1_block[rblock
+ /
+ perblock]) <<
+ log2_blksz;
+ }
+ blknr = __le32_to_cpu(ext4fs_indir2_block[rblock % perblock]);
+ }
+ /* Tripple indirect. */
+ else {
+ rblock = fileblock - (INDIRECT_BLOCKS + blksz / 4 +
+ (blksz / 4 * blksz / 4));
+ perblock_child = blksz / 4;
+ perblock_parent = ((blksz / 4) * (blksz / 4));
+
+ if (ext4fs_indir1_block == NULL) {
+ ext4fs_indir1_block = zalloc(blksz);
+ if (ext4fs_indir1_block == NULL) {
+ printf("** TI ext2fs read block (indir 2 1)"
+ "malloc failed. **\n");
+ return -1;
+ }
+ ext4fs_indir1_size = blksz;
+ ext4fs_indir1_blkno = -1;
+ }
+ if (blksz != ext4fs_indir1_size) {
+ free(ext4fs_indir1_block);
+ ext4fs_indir1_block = NULL;
+ ext4fs_indir1_size = 0;
+ ext4fs_indir1_blkno = -1;
+ ext4fs_indir1_block = zalloc(blksz);
+ if (ext4fs_indir1_block == NULL) {
+ printf("** TI ext2fs read block (indir 2 1)"
+ "malloc failed. **\n");
+ return -1;
+ }
+ ext4fs_indir1_size = blksz;
+ }
+ if ((__le32_to_cpu(inode->b.blocks.triple_indir_block) <<
+ log2_blksz) != ext4fs_indir1_blkno) {
+ status = ext4fs_devread
+ (__le32_to_cpu(inode->b.blocks.triple_indir_block)
+ << log2_blksz, 0, blksz,
+ (char *)ext4fs_indir1_block);
+ if (status == 0) {
+ printf("** TI ext2fs read block (indir 2 1)"
+ "failed. **\n");
+ return -1;
+ }
+ ext4fs_indir1_blkno =
+ __le32_to_cpu(inode->b.blocks.triple_indir_block) <<
+ log2_blksz;
+ }
+
+ if (ext4fs_indir2_block == NULL) {
+ ext4fs_indir2_block = zalloc(blksz);
+ if (ext4fs_indir2_block == NULL) {
+ printf("** TI ext2fs read block (indir 2 2)"
+ "malloc failed. **\n");
+ return -1;
+ }
+ ext4fs_indir2_size = blksz;
+ ext4fs_indir2_blkno = -1;
+ }
+ if (blksz != ext4fs_indir2_size) {
+ free(ext4fs_indir2_block);
+ ext4fs_indir2_block = NULL;
+ ext4fs_indir2_size = 0;
+ ext4fs_indir2_blkno = -1;
+ ext4fs_indir2_block = zalloc(blksz);
+ if (ext4fs_indir2_block == NULL) {
+ printf("** TI ext2fs read block (indir 2 2)"
+ "malloc failed. **\n");
+ return -1;
+ }
+ ext4fs_indir2_size = blksz;
+ }
+ if ((__le32_to_cpu(ext4fs_indir1_block[rblock /
+ perblock_parent]) <<
+ log2_blksz)
+ != ext4fs_indir2_blkno) {
+ status = ext4fs_devread(__le32_to_cpu
+ (ext4fs_indir1_block
+ [rblock /
+ perblock_parent]) <<
+ log2_blksz, 0, blksz,
+ (char *)ext4fs_indir2_block);
+ if (status == 0) {
+ printf("** TI ext2fs read block (indir 2 2)"
+ "failed. **\n");
+ return -1;
+ }
+ ext4fs_indir2_blkno =
+ __le32_to_cpu(ext4fs_indir1_block[rblock /
+ perblock_parent])
+ << log2_blksz;
+ }
+
+ if (ext4fs_indir3_block == NULL) {
+ ext4fs_indir3_block = zalloc(blksz);
+ if (ext4fs_indir3_block == NULL) {
+ printf("** TI ext2fs read block (indir 2 2)"
+ "malloc failed. **\n");
+ return -1;
+ }
+ ext4fs_indir3_size = blksz;
+ ext4fs_indir3_blkno = -1;
+ }
+ if (blksz != ext4fs_indir3_size) {
+ free(ext4fs_indir3_block);
+ ext4fs_indir3_block = NULL;
+ ext4fs_indir3_size = 0;
+ ext4fs_indir3_blkno = -1;
+ ext4fs_indir3_block = zalloc(blksz);
+ if (ext4fs_indir3_block == NULL) {
+ printf("** TI ext2fs read block (indir 2 2)"
+ "malloc failed. **\n");
+ return -1;
+ }
+ ext4fs_indir3_size = blksz;
+ }
+ if ((__le32_to_cpu(ext4fs_indir2_block[rblock
+ /
+ perblock_child]) <<
+ log2_blksz) != ext4fs_indir3_blkno) {
+ status =
+ ext4fs_devread(__le32_to_cpu
+ (ext4fs_indir2_block
+ [(rblock / perblock_child)
+ % (blksz / 4)]) << log2_blksz, 0,
+ blksz, (char *)ext4fs_indir3_block);
+ if (status == 0) {
+ printf("** TI ext2fs read block (indir 2 2)"
+ "failed. **\n");
+ return -1;
+ }
+ ext4fs_indir3_blkno =
+ __le32_to_cpu(ext4fs_indir2_block[(rblock /
+ perblock_child) %
+ (blksz /
+ 4)]) <<
+ log2_blksz;
+ }
+
+ blknr = __le32_to_cpu(ext4fs_indir3_block
+ [rblock % perblock_child]);
+ }
+ debug("ext4fs_read_block %ld\n", blknr);
+
+ return blknr;
+}
+
+void ext4fs_close(void)
+{
+ if ((ext4fs_file != NULL) && (ext4fs_root != NULL)) {
+ ext4fs_free_node(ext4fs_file, &ext4fs_root->diropen);
+ ext4fs_file = NULL;
+ }
+ if (ext4fs_root != NULL) {
+ free(ext4fs_root);
+ ext4fs_root = NULL;
+ }
+ if (ext4fs_indir1_block != NULL) {
+ free(ext4fs_indir1_block);
+ ext4fs_indir1_block = NULL;
+ ext4fs_indir1_size = 0;
+ ext4fs_indir1_blkno = -1;
+ }
+ if (ext4fs_indir2_block != NULL) {
+ free(ext4fs_indir2_block);
+ ext4fs_indir2_block = NULL;
+ ext4fs_indir2_size = 0;
+ ext4fs_indir2_blkno = -1;
+ }
+ if (ext4fs_indir3_block != NULL) {
+ free(ext4fs_indir3_block);
+ ext4fs_indir3_block = NULL;
+ ext4fs_indir3_size = 0;
+ ext4fs_indir3_blkno = -1;
+ }
+}
+
+int ext4fs_iterate_dir(struct ext2fs_node *dir, char *name,
+ struct ext2fs_node **fnode, int *ftype)
+{
+ unsigned int fpos = 0;
+ int status;
+ struct ext2fs_node *diro = (struct ext2fs_node *) dir;
+
+#ifdef DEBUG
+ if (name != NULL)
+ printf("Iterate dir %s\n", name);
+#endif /* of DEBUG */
+ if (!diro->inode_read) {
+ status = ext4fs_read_inode(diro->data, diro->ino, &diro->inode);
+ if (status == 0)
+ return 0;
+ }
+ /* Search the file. */
+ while (fpos < __le32_to_cpu(diro->inode.size)) {
+ struct ext2_dirent dirent;
+
+ status = ext4fs_read_file(diro, fpos,
+ sizeof(struct ext2_dirent),
+ (char *) &dirent);
+ if (status < 1)
+ return 0;
+
+ if (dirent.namelen != 0) {
+ char filename[dirent.namelen + 1];
+ struct ext2fs_node *fdiro;
+ int type = FILETYPE_UNKNOWN;
+
+ status = ext4fs_read_file(diro,
+ fpos +
+ sizeof(struct ext2_dirent),
+ dirent.namelen, filename);
+ if (status < 1)
+ return 0;
+
+ fdiro = zalloc(sizeof(struct ext2fs_node));
+ if (!fdiro)
+ return 0;
+
+ fdiro->data = diro->data;
+ fdiro->ino = __le32_to_cpu(dirent.inode);
+
+ filename[dirent.namelen] = '\0';
+
+ if (dirent.filetype != FILETYPE_UNKNOWN) {
+ fdiro->inode_read = 0;
+
+ if (dirent.filetype == FILETYPE_DIRECTORY)
+ type = FILETYPE_DIRECTORY;
+ else if (dirent.filetype == FILETYPE_SYMLINK)
+ type = FILETYPE_SYMLINK;
+ else if (dirent.filetype == FILETYPE_REG)
+ type = FILETYPE_REG;
+ } else {
+ status = ext4fs_read_inode(diro->data,
+ __le32_to_cpu
+ (dirent.inode),
+ &fdiro->inode);
+ if (status == 0) {
+ free(fdiro);
+ return 0;
+ }
+ fdiro->inode_read = 1;
+
+ if ((__le16_to_cpu(fdiro->inode.mode) &
+ FILETYPE_INO_MASK) ==
+ FILETYPE_INO_DIRECTORY) {
+ type = FILETYPE_DIRECTORY;
+ } else if ((__le16_to_cpu(fdiro->inode.mode)
+ & FILETYPE_INO_MASK) ==
+ FILETYPE_INO_SYMLINK) {
+ type = FILETYPE_SYMLINK;
+ } else if ((__le16_to_cpu(fdiro->inode.mode)
+ & FILETYPE_INO_MASK) ==
+ FILETYPE_INO_REG) {
+ type = FILETYPE_REG;
+ }
+ }
+#ifdef DEBUG
+ printf("iterate >%s<\n", filename);
+#endif /* of DEBUG */
+ if ((name != NULL) && (fnode != NULL)
+ && (ftype != NULL)) {
+ if (strcmp(filename, name) == 0) {
+ *ftype = type;
+ *fnode = fdiro;
+ return 1;
+ }
+ } else {
+ if (fdiro->inode_read == 0) {
+ status = ext4fs_read_inode(diro->data,
+ __le32_to_cpu(
+ dirent.inode),
+ &fdiro->inode);
+ if (status == 0) {
+ free(fdiro);
+ return 0;
+ }
+ fdiro->inode_read = 1;
+ }
+ switch (type) {
+ case FILETYPE_DIRECTORY:
+ printf("<DIR> ");
+ break;
+ case FILETYPE_SYMLINK:
+ printf("<SYM> ");
+ break;
+ case FILETYPE_REG:
+ printf(" ");
+ break;
+ default:
+ printf("< ? > ");
+ break;
+ }
+ printf("%10d %s\n",
+ __le32_to_cpu(fdiro->inode.size),
+ filename);
+ }
+ free(fdiro);
+ }
+ fpos += __le16_to_cpu(dirent.direntlen);
+ }
+ return 0;
+}
+
+static char *ext4fs_read_symlink(struct ext2fs_node *node)
+{
+ char *symlink;
+ struct ext2fs_node *diro = node;
+ int status;
+
+ if (!diro->inode_read) {
+ status = ext4fs_read_inode(diro->data, diro->ino, &diro->inode);
+ if (status == 0)
+ return 0;
+ }
+ symlink = zalloc(__le32_to_cpu(diro->inode.size) + 1);
+ if (!symlink)
+ return 0;
+
+ if (__le32_to_cpu(diro->inode.size) <= 60) {
+ strncpy(symlink, diro->inode.b.symlink,
+ __le32_to_cpu(diro->inode.size));
+ } else {
+ status = ext4fs_read_file(diro, 0,
+ __le32_to_cpu(diro->inode.size),
+ symlink);
+ if (status == 0) {
+ free(symlink);
+ return 0;
+ }
+ }
+ symlink[__le32_to_cpu(diro->inode.size)] = '\0';
+ return symlink;
+}
+
+static int ext4fs_find_file1(const char *currpath,
+ struct ext2fs_node *currroot,
+ struct ext2fs_node **currfound, int *foundtype)
+{
+ char fpath[strlen(currpath) + 1];
+ char *name = fpath;
+ char *next;
+ int status;
+ int type = FILETYPE_DIRECTORY;
+ struct ext2fs_node *currnode = currroot;
+ struct ext2fs_node *oldnode = currroot;
+
+ strncpy(fpath, currpath, strlen(currpath) + 1);
+
+ /* Remove all leading slashes. */
+ while (*name == '/')
+ name++;
+
+ if (!*name) {
+ *currfound = currnode;
+ return 1;
+ }
+
+ for (;;) {
+ int found;
+
+ /* Extract the actual part from the pathname. */
+ next = strchr(name, '/');
+ if (next) {
+ /* Remove all leading slashes. */
+ while (*next == '/')
+ *(next++) = '\0';
+ }
+
+ if (type != FILETYPE_DIRECTORY) {
+ ext4fs_free_node(currnode, currroot);
+ return 0;
+ }
+
+ oldnode = currnode;
+
+ /* Iterate over the directory. */
+ found = ext4fs_iterate_dir(currnode, name, &currnode, &type);
+ if (found == 0)
+ return 0;
+
+ if (found == -1)
+ break;
+
+ /* Read in the symlink and follow it. */
+ if (type == FILETYPE_SYMLINK) {
+ char *symlink;
+
+ /* Test if the symlink does not loop. */
+ if (++symlinknest == 8) {
+ ext4fs_free_node(currnode, currroot);
+ ext4fs_free_node(oldnode, currroot);
+ return 0;
+ }
+
+ symlink = ext4fs_read_symlink(currnode);
+ ext4fs_free_node(currnode, currroot);
+
+ if (!symlink) {
+ ext4fs_free_node(oldnode, currroot);
+ return 0;
+ }
+
+ debug("Got symlink >%s<\n", symlink);
+
+ if (symlink[0] == '/') {
+ ext4fs_free_node(oldnode, currroot);
+ oldnode = &ext4fs_root->diropen;
+ }
+
+ /* Lookup the node the symlink points to. */
+ status = ext4fs_find_file1(symlink, oldnode,
+ &currnode, &type);
+
+ free(symlink);
+
+ if (status == 0) {
+ ext4fs_free_node(oldnode, currroot);
+ return 0;
+ }
+ }
+
+ ext4fs_free_node(oldnode, currroot);
+
+ /* Found the node! */
+ if (!next || *next == '\0') {
+ *currfound = currnode;
+ *foundtype = type;
+ return 1;
+ }
+ name = next;
+ }
+ return -1;
+}
+
+int ext4fs_find_file(const char *path, struct ext2fs_node *rootnode,
+ struct ext2fs_node **foundnode, int expecttype)
+{
+ int status;
+ int foundtype = FILETYPE_DIRECTORY;
+
+ symlinknest = 0;
+ if (!path)
+ return 0;
+
+ status = ext4fs_find_file1(path, rootnode, foundnode, &foundtype);
+ if (status == 0)
+ return 0;
+
+ /* Check if the node that was found was of the expected type. */
+ if ((expecttype == FILETYPE_REG) && (foundtype != expecttype))
+ return 0;
+ else if ((expecttype == FILETYPE_DIRECTORY)
+ && (foundtype != expecttype))
+ return 0;
+
+ return 1;
+}
+
+int ext4fs_open(const char *filename)
+{
+ struct ext2fs_node *fdiro = NULL;
+ int status;
+ int len;
+
+ if (ext4fs_root == NULL)
+ return -1;
+
+ ext4fs_file = NULL;
+ status = ext4fs_find_file(filename, &ext4fs_root->diropen, &fdiro,
+ FILETYPE_REG);
+ if (status == 0)
+ goto fail;
+
+ if (!fdiro->inode_read) {
+ status = ext4fs_read_inode(fdiro->data, fdiro->ino,
+ &fdiro->inode);
+ if (status == 0)
+ goto fail;
+ }
+ len = __le32_to_cpu(fdiro->inode.size);
+ ext4fs_file = fdiro;
+
+ return len;
+fail:
+ ext4fs_free_node(fdiro, &ext4fs_root->diropen);
+
+ return -1;
+}
+
+int ext4fs_mount(unsigned part_length)
+{
+ struct ext2_data *data;
+ int status;
+ struct ext_filesystem *fs = get_fs();
+ data = zalloc(sizeof(struct ext2_data));
+ if (!data)
+ return 0;
+
+ /* Read the superblock. */
+ status = ext4fs_devread(1 * 2, 0, sizeof(struct ext2_sblock),
+ (char *)&data->sblock);
+
+ if (status == 0)
+ goto fail;
+
+ /* Make sure this is an ext2 filesystem. */
+ if (__le16_to_cpu(data->sblock.magic) != EXT2_MAGIC)
+ goto fail;
+
+ if (__le32_to_cpu(data->sblock.revision_level == 0))
+ fs->inodesz = 128;
+ else
+ fs->inodesz = __le16_to_cpu(data->sblock.inode_size);
+
+ debug("EXT2 rev %d, inode_size %d\n",
+ __le32_to_cpu(data->sblock.revision_level), fs->inodesz);
+
+ data->diropen.data = data;
+ data->diropen.ino = 2;
+ data->diropen.inode_read = 1;
+ data->inode = &data->diropen.inode;
+
+ status = ext4fs_read_inode(data, 2, data->inode);
+ if (status == 0)
+ goto fail;
+
+ ext4fs_root = data;
+
+ return 1;
+fail:
+ printf("Failed to mount ext2 filesystem...\n");
+ free(data);
+ ext4fs_root = NULL;
+
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2011 - 2012 Samsung Electronics
+ * EXT4 filesystem implementation in Uboot by
+ * Uma Shankar <uma.shankar@samsung.com>
+ * Manjunatha C Achar <a.manjunatha@samsung.com>
+ *
+ * ext4ls and ext4load : based on ext2 ls load support in Uboot.
+ *
+ * (C) Copyright 2004
+ * esd gmbh <www.esd-electronics.com>
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * based on code from grub2 fs/ext2.c and fs/fshelp.c by
+ * GRUB -- GRand Unified Bootloader
+ * Copyright (C) 2003, 2004 Free Software Foundation, Inc.
+ *
+ * ext4write : Based on generic ext4 protocol.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __EXT4_COMMON__
+#define __EXT4_COMMON__
+#include <ext_common.h>
+#include <ext4fs.h>
+#include <malloc.h>
+#include <asm/errno.h>
+#if defined(CONFIG_CMD_EXT4_WRITE)
+#include "ext4_journal.h"
+#include "crc16.h"
+#endif
+
+#define YES 1
+#define NO 0
+#define TRUE 1
+#define FALSE 0
+#define RECOVER 1
+#define SCAN 0
+
+#define S_IFLNK 0120000 /* symbolic link */
+#define BLOCK_NO_ONE 1
+#define SUPERBLOCK_SECTOR 2
+#define SUPERBLOCK_SIZE 1024
+#define F_FILE 1
+
+static inline void *zalloc(size_t size)
+{
+ void *p = memalign(ARCH_DMA_MINALIGN, size);
+ memset(p, 0, size);
+ return p;
+}
+
+extern unsigned long part_offset;
+int ext4fs_read_inode(struct ext2_data *data, int ino,
+ struct ext2_inode *inode);
+int ext4fs_read_file(struct ext2fs_node *node, int pos,
+ unsigned int len, char *buf);
+int ext4fs_find_file(const char *path, struct ext2fs_node *rootnode,
+ struct ext2fs_node **foundnode, int expecttype);
+int ext4fs_iterate_dir(struct ext2fs_node *dir, char *name,
+ struct ext2fs_node **fnode, int *ftype);
+
+#if defined(CONFIG_CMD_EXT4_WRITE)
+uint32_t ext4fs_div_roundup(uint32_t size, uint32_t n);
+int ext4fs_checksum_update(unsigned int i);
+int ext4fs_get_parent_inode_num(const char *dirname, char *dname, int flags);
+void ext4fs_update_parent_dentry(char *filename, int *p_ino, int file_type);
+long int ext4fs_get_new_blk_no(void);
+int ext4fs_get_new_inode_no(void);
+void ext4fs_reset_block_bmap(long int blockno, unsigned char *buffer,
+ int index);
+int ext4fs_set_block_bmap(long int blockno, unsigned char *buffer, int index);
+int ext4fs_set_inode_bmap(int inode_no, unsigned char *buffer, int index);
+void ext4fs_reset_inode_bmap(int inode_no, unsigned char *buffer, int index);
+int ext4fs_iget(int inode_no, struct ext2_inode *inode);
+void ext4fs_allocate_blocks(struct ext2_inode *file_inode,
+ unsigned int total_remaining_blocks,
+ unsigned int *total_no_of_block);
+void put_ext4(uint64_t off, void *buf, uint32_t size);
+#endif
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2011 - 2012 Samsung Electronics
+ * EXT4 filesystem implementation in Uboot by
+ * Uma Shankar <uma.shankar@samsung.com>
+ * Manjunatha C Achar <a.manjunatha@samsung.com>
+ *
+ * Journal data structures and headers for Journaling feature of ext4
+ * have been referred from JBD2 (Journaling Block device 2)
+ * implementation in Linux Kernel.
+ * Written by Stephen C. Tweedie <sct@redhat.com>
+ *
+ * Copyright 1998-2000 Red Hat, Inc --- All Rights Reserved
+ * This file is part of the Linux kernel and is made available under
+ * the terms of the GNU General Public License, version 2, or at your
+ * option, any later version, incorporated herein by reference.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <ext4fs.h>
+#include <malloc.h>
+#include <ext_common.h>
+#include "ext4_common.h"
+
+static struct revoke_blk_list *revk_blk_list;
+static struct revoke_blk_list *prev_node;
+static int first_node = TRUE;
+
+int gindex;
+int gd_index;
+int jrnl_blk_idx;
+struct journal_log *journal_ptr[MAX_JOURNAL_ENTRIES];
+struct dirty_blocks *dirty_block_ptr[MAX_JOURNAL_ENTRIES];
+
+int ext4fs_init_journal(void)
+{
+ int i;
+ char *temp = NULL;
+ struct ext_filesystem *fs = get_fs();
+
+ /* init globals */
+ revk_blk_list = NULL;
+ prev_node = NULL;
+ gindex = 0;
+ gd_index = 0;
+ jrnl_blk_idx = 1;
+
+ for (i = 0; i < MAX_JOURNAL_ENTRIES; i++) {
+ journal_ptr[i] = zalloc(sizeof(struct journal_log));
+ if (!journal_ptr[i])
+ goto fail;
+ dirty_block_ptr[i] = zalloc(sizeof(struct dirty_blocks));
+ if (!dirty_block_ptr[i])
+ goto fail;
+ journal_ptr[i]->buf = NULL;
+ journal_ptr[i]->blknr = -1;
+
+ dirty_block_ptr[i]->buf = NULL;
+ dirty_block_ptr[i]->blknr = -1;
+ }
+
+ if (fs->blksz == 4096) {
+ temp = zalloc(fs->blksz);
+ if (!temp)
+ goto fail;
+ journal_ptr[gindex]->buf = zalloc(fs->blksz);
+ if (!journal_ptr[gindex]->buf)
+ goto fail;
+ ext4fs_devread(0, 0, fs->blksz, temp);
+ memcpy(temp + SUPERBLOCK_SIZE, fs->sb, SUPERBLOCK_SIZE);
+ memcpy(journal_ptr[gindex]->buf, temp, fs->blksz);
+ journal_ptr[gindex++]->blknr = 0;
+ free(temp);
+ } else {
+ journal_ptr[gindex]->buf = zalloc(fs->blksz);
+ if (!journal_ptr[gindex]->buf)
+ goto fail;
+ memcpy(journal_ptr[gindex]->buf, fs->sb, SUPERBLOCK_SIZE);
+ journal_ptr[gindex++]->blknr = 1;
+ }
+
+ /* Check the file system state using journal super block */
+ if (ext4fs_check_journal_state(SCAN))
+ goto fail;
+ /* Check the file system state using journal super block */
+ if (ext4fs_check_journal_state(RECOVER))
+ goto fail;
+
+ return 0;
+fail:
+ return -1;
+}
+
+void ext4fs_dump_metadata(void)
+{
+ struct ext_filesystem *fs = get_fs();
+ int i;
+ for (i = 0; i < MAX_JOURNAL_ENTRIES; i++) {
+ if (dirty_block_ptr[i]->blknr == -1)
+ break;
+ put_ext4((uint64_t) ((uint64_t)dirty_block_ptr[i]->blknr *
+ (uint64_t)fs->blksz), dirty_block_ptr[i]->buf,
+ fs->blksz);
+ }
+}
+
+void ext4fs_free_journal(void)
+{
+ int i;
+ for (i = 0; i < MAX_JOURNAL_ENTRIES; i++) {
+ if (dirty_block_ptr[i]->blknr == -1)
+ break;
+ if (dirty_block_ptr[i]->buf)
+ free(dirty_block_ptr[i]->buf);
+ }
+
+ for (i = 0; i < MAX_JOURNAL_ENTRIES; i++) {
+ if (journal_ptr[i]->blknr == -1)
+ break;
+ if (journal_ptr[i]->buf)
+ free(journal_ptr[i]->buf);
+ }
+
+ for (i = 0; i < MAX_JOURNAL_ENTRIES; i++) {
+ if (journal_ptr[i])
+ free(journal_ptr[i]);
+ if (dirty_block_ptr[i])
+ free(dirty_block_ptr[i]);
+ }
+ gindex = 0;
+ gd_index = 0;
+ jrnl_blk_idx = 1;
+}
+
+int ext4fs_log_gdt(char *gd_table)
+{
+ struct ext_filesystem *fs = get_fs();
+ short i;
+ long int var = fs->gdtable_blkno;
+ for (i = 0; i < fs->no_blk_pergdt; i++) {
+ journal_ptr[gindex]->buf = zalloc(fs->blksz);
+ if (!journal_ptr[gindex]->buf)
+ return -ENOMEM;
+ memcpy(journal_ptr[gindex]->buf, gd_table, fs->blksz);
+ gd_table += fs->blksz;
+ journal_ptr[gindex++]->blknr = var++;
+ }
+
+ return 0;
+}
+
+/*
+ * This function stores the backup copy of meta data in RAM
+ * journal_buffer -- Buffer containing meta data
+ * blknr -- Block number on disk of the meta data buffer
+ */
+int ext4fs_log_journal(char *journal_buffer, long int blknr)
+{
+ struct ext_filesystem *fs = get_fs();
+ short i;
+
+ if (!journal_buffer) {
+ printf("Invalid input arguments %s\n", __func__);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < MAX_JOURNAL_ENTRIES; i++) {
+ if (journal_ptr[i]->blknr == -1)
+ break;
+ if (journal_ptr[i]->blknr == blknr)
+ return 0;
+ }
+
+ journal_ptr[gindex]->buf = zalloc(fs->blksz);
+ if (!journal_ptr[gindex]->buf)
+ return -ENOMEM;
+
+ memcpy(journal_ptr[gindex]->buf, journal_buffer, fs->blksz);
+ journal_ptr[gindex++]->blknr = blknr;
+
+ return 0;
+}
+
+/*
+ * This function stores the modified meta data in RAM
+ * metadata_buffer -- Buffer containing meta data
+ * blknr -- Block number on disk of the meta data buffer
+ */
+int ext4fs_put_metadata(char *metadata_buffer, long int blknr)
+{
+ struct ext_filesystem *fs = get_fs();
+ if (!metadata_buffer) {
+ printf("Invalid input arguments %s\n", __func__);
+ return -EINVAL;
+ }
+ dirty_block_ptr[gd_index]->buf = zalloc(fs->blksz);
+ if (!dirty_block_ptr[gd_index]->buf)
+ return -ENOMEM;
+ memcpy(dirty_block_ptr[gd_index]->buf, metadata_buffer, fs->blksz);
+ dirty_block_ptr[gd_index++]->blknr = blknr;
+
+ return 0;
+}
+
+void print_revoke_blks(char *revk_blk)
+{
+ int offset;
+ int max;
+ long int blocknr;
+ struct journal_revoke_header_t *header;
+
+ if (revk_blk == NULL)
+ return;
+
+ header = (struct journal_revoke_header_t *) revk_blk;
+ offset = sizeof(struct journal_revoke_header_t);
+ max = be32_to_cpu(header->r_count);
+ printf("total bytes %d\n", max);
+
+ while (offset < max) {
+ blocknr = be32_to_cpu(*((long int *)(revk_blk + offset)));
+ printf("revoke blknr is %ld\n", blocknr);
+ offset += 4;
+ }
+}
+
+static struct revoke_blk_list *_get_node(void)
+{
+ struct revoke_blk_list *tmp_node;
+ tmp_node = zalloc(sizeof(struct revoke_blk_list));
+ if (tmp_node == NULL)
+ return NULL;
+ tmp_node->content = NULL;
+ tmp_node->next = NULL;
+
+ return tmp_node;
+}
+
+void ext4fs_push_revoke_blk(char *buffer)
+{
+ struct revoke_blk_list *node = NULL;
+ struct ext_filesystem *fs = get_fs();
+ if (buffer == NULL) {
+ printf("buffer ptr is NULL\n");
+ return;
+ }
+ node = _get_node();
+ if (!node) {
+ printf("_get_node: malloc failed\n");
+ return;
+ }
+
+ node->content = zalloc(fs->blksz);
+ if (node->content == NULL)
+ return;
+ memcpy(node->content, buffer, fs->blksz);
+
+ if (first_node == TRUE) {
+ revk_blk_list = node;
+ prev_node = node;
+ first_node = FALSE;
+ } else {
+ prev_node->next = node;
+ prev_node = node;
+ }
+}
+
+void ext4fs_free_revoke_blks(void)
+{
+ struct revoke_blk_list *tmp_node = revk_blk_list;
+ struct revoke_blk_list *next_node = NULL;
+
+ while (tmp_node != NULL) {
+ if (tmp_node->content)
+ free(tmp_node->content);
+ tmp_node = tmp_node->next;
+ }
+
+ tmp_node = revk_blk_list;
+ while (tmp_node != NULL) {
+ next_node = tmp_node->next;
+ free(tmp_node);
+ tmp_node = next_node;
+ }
+
+ revk_blk_list = NULL;
+ prev_node = NULL;
+ first_node = TRUE;
+}
+
+int check_blknr_for_revoke(long int blknr, int sequence_no)
+{
+ struct journal_revoke_header_t *header;
+ int offset;
+ int max;
+ long int blocknr;
+ char *revk_blk;
+ struct revoke_blk_list *tmp_revk_node = revk_blk_list;
+ while (tmp_revk_node != NULL) {
+ revk_blk = tmp_revk_node->content;
+
+ header = (struct journal_revoke_header_t *) revk_blk;
+ if (sequence_no < be32_to_cpu(header->r_header.h_sequence)) {
+ offset = sizeof(struct journal_revoke_header_t);
+ max = be32_to_cpu(header->r_count);
+
+ while (offset < max) {
+ blocknr = be32_to_cpu(*((long int *)
+ (revk_blk + offset)));
+ if (blocknr == blknr)
+ goto found;
+ offset += 4;
+ }
+ }
+ tmp_revk_node = tmp_revk_node->next;
+ }
+
+ return -1;
+
+found:
+ return 0;
+}
+
+/*
+ * This function parses the journal blocks and replays the
+ * suceessful transactions. A transaction is successfull
+ * if commit block is found for a descriptor block
+ * The tags in descriptor block contain the disk block
+ * numbers of the metadata to be replayed
+ */
+void recover_transaction(int prev_desc_logical_no)
+{
+ struct ext2_inode inode_journal;
+ struct ext_filesystem *fs = get_fs();
+ struct journal_header_t *jdb;
+ long int blknr;
+ char *p_jdb;
+ int ofs, flags;
+ int i;
+ struct ext3_journal_block_tag *tag;
+ char *temp_buff = zalloc(fs->blksz);
+ char *metadata_buff = zalloc(fs->blksz);
+ if (!temp_buff || !metadata_buff)
+ goto fail;
+ i = prev_desc_logical_no;
+ ext4fs_read_inode(ext4fs_root, EXT2_JOURNAL_INO,
+ (struct ext2_inode *)&inode_journal);
+ blknr = read_allocated_block((struct ext2_inode *)
+ &inode_journal, i);
+ ext4fs_devread(blknr * fs->sect_perblk, 0, fs->blksz, temp_buff);
+ p_jdb = (char *)temp_buff;
+ jdb = (struct journal_header_t *) temp_buff;
+ ofs = sizeof(struct journal_header_t);
+
+ do {
+ tag = (struct ext3_journal_block_tag *)&p_jdb[ofs];
+ ofs += sizeof(struct ext3_journal_block_tag);
+
+ if (ofs > fs->blksz)
+ break;
+
+ flags = be32_to_cpu(tag->flags);
+ if (!(flags & EXT3_JOURNAL_FLAG_SAME_UUID))
+ ofs += 16;
+
+ i++;
+ debug("\t\ttag %u\n", be32_to_cpu(tag->block));
+ if (revk_blk_list != NULL) {
+ if (check_blknr_for_revoke(be32_to_cpu(tag->block),
+ be32_to_cpu(jdb->h_sequence)) == 0)
+ continue;
+ }
+ blknr = read_allocated_block(&inode_journal, i);
+ ext4fs_devread(blknr * fs->sect_perblk, 0,
+ fs->blksz, metadata_buff);
+ put_ext4((uint64_t)(be32_to_cpu(tag->block) * fs->blksz),
+ metadata_buff, (uint32_t) fs->blksz);
+ } while (!(flags & EXT3_JOURNAL_FLAG_LAST_TAG));
+fail:
+ free(temp_buff);
+ free(metadata_buff);
+}
+
+void print_jrnl_status(int recovery_flag)
+{
+ if (recovery_flag == RECOVER)
+ printf("Journal Recovery Completed\n");
+ else
+ printf("Journal Scan Completed\n");
+}
+
+int ext4fs_check_journal_state(int recovery_flag)
+{
+ int i;
+ int DB_FOUND = NO;
+ long int blknr;
+ int transaction_state = TRANSACTION_COMPLETE;
+ int prev_desc_logical_no = 0;
+ int curr_desc_logical_no = 0;
+ int ofs, flags, block;
+ struct ext2_inode inode_journal;
+ struct journal_superblock_t *jsb = NULL;
+ struct journal_header_t *jdb = NULL;
+ char *p_jdb = NULL;
+ struct ext3_journal_block_tag *tag = NULL;
+ char *temp_buff = NULL;
+ char *temp_buff1 = NULL;
+ struct ext_filesystem *fs = get_fs();
+
+ temp_buff = zalloc(fs->blksz);
+ if (!temp_buff)
+ return -ENOMEM;
+ temp_buff1 = zalloc(fs->blksz);
+ if (!temp_buff1) {
+ free(temp_buff);
+ return -ENOMEM;
+ }
+
+ ext4fs_read_inode(ext4fs_root, EXT2_JOURNAL_INO, &inode_journal);
+ blknr = read_allocated_block(&inode_journal, EXT2_JOURNAL_SUPERBLOCK);
+ ext4fs_devread(blknr * fs->sect_perblk, 0, fs->blksz, temp_buff);
+ jsb = (struct journal_superblock_t *) temp_buff;
+
+ if (fs->sb->feature_incompat & EXT3_FEATURE_INCOMPAT_RECOVER) {
+ if (recovery_flag == RECOVER)
+ printf("Recovery required\n");
+ } else {
+ if (recovery_flag == RECOVER)
+ printf("File System is consistent\n");
+ goto end;
+ }
+
+ if (be32_to_cpu(jsb->s_start) == 0)
+ goto end;
+
+ if (!(jsb->s_feature_compat &
+ cpu_to_be32(JBD2_FEATURE_COMPAT_CHECKSUM)))
+ jsb->s_feature_compat |=
+ cpu_to_be32(JBD2_FEATURE_COMPAT_CHECKSUM);
+
+ i = be32_to_cpu(jsb->s_first);
+ while (1) {
+ block = be32_to_cpu(jsb->s_first);
+ blknr = read_allocated_block(&inode_journal, i);
+ memset(temp_buff1, '\0', fs->blksz);
+ ext4fs_devread(blknr * fs->sect_perblk,
+ 0, fs->blksz, temp_buff1);
+ jdb = (struct journal_header_t *) temp_buff1;
+
+ if (be32_to_cpu(jdb->h_blocktype) ==
+ EXT3_JOURNAL_DESCRIPTOR_BLOCK) {
+ if (be32_to_cpu(jdb->h_sequence) !=
+ be32_to_cpu(jsb->s_sequence)) {
+ print_jrnl_status(recovery_flag);
+ break;
+ }
+
+ curr_desc_logical_no = i;
+ if (transaction_state == TRANSACTION_COMPLETE)
+ transaction_state = TRANSACTION_RUNNING;
+ else
+ return -1;
+ p_jdb = (char *)temp_buff1;
+ ofs = sizeof(struct journal_header_t);
+ do {
+ tag = (struct ext3_journal_block_tag *)
+ &p_jdb[ofs];
+ ofs += sizeof(struct ext3_journal_block_tag);
+ if (ofs > fs->blksz)
+ break;
+ flags = be32_to_cpu(tag->flags);
+ if (!(flags & EXT3_JOURNAL_FLAG_SAME_UUID))
+ ofs += 16;
+ i++;
+ debug("\t\ttag %u\n", be32_to_cpu(tag->block));
+ } while (!(flags & EXT3_JOURNAL_FLAG_LAST_TAG));
+ i++;
+ DB_FOUND = YES;
+ } else if (be32_to_cpu(jdb->h_blocktype) ==
+ EXT3_JOURNAL_COMMIT_BLOCK) {
+ if (be32_to_cpu(jdb->h_sequence) !=
+ be32_to_cpu(jsb->s_sequence)) {
+ print_jrnl_status(recovery_flag);
+ break;
+ }
+
+ if (transaction_state == TRANSACTION_RUNNING ||
+ (DB_FOUND == NO)) {
+ transaction_state = TRANSACTION_COMPLETE;
+ i++;
+ jsb->s_sequence =
+ cpu_to_be32(be32_to_cpu(
+ jsb->s_sequence) + 1);
+ }
+ prev_desc_logical_no = curr_desc_logical_no;
+ if ((recovery_flag == RECOVER) && (DB_FOUND == YES))
+ recover_transaction(prev_desc_logical_no);
+
+ DB_FOUND = NO;
+ } else if (be32_to_cpu(jdb->h_blocktype) ==
+ EXT3_JOURNAL_REVOKE_BLOCK) {
+ if (be32_to_cpu(jdb->h_sequence) !=
+ be32_to_cpu(jsb->s_sequence)) {
+ print_jrnl_status(recovery_flag);
+ break;
+ }
+ if (recovery_flag == SCAN)
+ ext4fs_push_revoke_blk((char *)jdb);
+ i++;
+ } else {
+ debug("Else Case\n");
+ if (be32_to_cpu(jdb->h_sequence) !=
+ be32_to_cpu(jsb->s_sequence)) {
+ print_jrnl_status(recovery_flag);
+ break;
+ }
+ }
+ }
+
+end:
+ if (recovery_flag == RECOVER) {
+ jsb->s_start = cpu_to_be32(1);
+ jsb->s_sequence = cpu_to_be32(be32_to_cpu(jsb->s_sequence) + 1);
+ /* get the superblock */
+ ext4fs_devread(SUPERBLOCK_SECTOR, 0, SUPERBLOCK_SIZE,
+ (char *)fs->sb);
+ fs->sb->feature_incompat |= EXT3_FEATURE_INCOMPAT_RECOVER;
+
+ /* Update the super block */
+ put_ext4((uint64_t) (SUPERBLOCK_SIZE),
+ (struct ext2_sblock *)fs->sb,
+ (uint32_t) SUPERBLOCK_SIZE);
+ ext4fs_devread(SUPERBLOCK_SECTOR, 0, SUPERBLOCK_SIZE,
+ (char *)fs->sb);
+
+ blknr = read_allocated_block(&inode_journal,
+ EXT2_JOURNAL_SUPERBLOCK);
+ put_ext4((uint64_t) (blknr * fs->blksz),
+ (struct journal_superblock_t *)temp_buff,
+ (uint32_t) fs->blksz);
+ ext4fs_free_revoke_blks();
+ }
+ free(temp_buff);
+ free(temp_buff1);
+
+ return 0;
+}
+
+static void update_descriptor_block(long int blknr)
+{
+ int i;
+ long int jsb_blknr;
+ struct journal_header_t jdb;
+ struct ext3_journal_block_tag tag;
+ struct ext2_inode inode_journal;
+ struct journal_superblock_t *jsb = NULL;
+ char *buf = NULL;
+ char *temp = NULL;
+ struct ext_filesystem *fs = get_fs();
+ char *temp_buff = zalloc(fs->blksz);
+ if (!temp_buff)
+ return;
+
+ ext4fs_read_inode(ext4fs_root, EXT2_JOURNAL_INO, &inode_journal);
+ jsb_blknr = read_allocated_block(&inode_journal,
+ EXT2_JOURNAL_SUPERBLOCK);
+ ext4fs_devread(jsb_blknr * fs->sect_perblk, 0, fs->blksz, temp_buff);
+ jsb = (struct journal_superblock_t *) temp_buff;
+
+ jdb.h_blocktype = cpu_to_be32(EXT3_JOURNAL_DESCRIPTOR_BLOCK);
+ jdb.h_magic = cpu_to_be32(EXT3_JOURNAL_MAGIC_NUMBER);
+ jdb.h_sequence = jsb->s_sequence;
+ buf = zalloc(fs->blksz);
+ if (!buf) {
+ free(temp_buff);
+ return;
+ }
+ temp = buf;
+ memcpy(buf, &jdb, sizeof(struct journal_header_t));
+ temp += sizeof(struct journal_header_t);
+
+ for (i = 0; i < MAX_JOURNAL_ENTRIES; i++) {
+ if (journal_ptr[i]->blknr == -1)
+ break;
+
+ tag.block = cpu_to_be32(journal_ptr[i]->blknr);
+ tag.flags = cpu_to_be32(EXT3_JOURNAL_FLAG_SAME_UUID);
+ memcpy(temp, &tag, sizeof(struct ext3_journal_block_tag));
+ temp = temp + sizeof(struct ext3_journal_block_tag);
+ }
+
+ tag.block = cpu_to_be32(journal_ptr[--i]->blknr);
+ tag.flags = cpu_to_be32(EXT3_JOURNAL_FLAG_LAST_TAG);
+ memcpy(temp - sizeof(struct ext3_journal_block_tag), &tag,
+ sizeof(struct ext3_journal_block_tag));
+ put_ext4((uint64_t) (blknr * fs->blksz), buf, (uint32_t) fs->blksz);
+
+ free(temp_buff);
+ free(buf);
+}
+
+static void update_commit_block(long int blknr)
+{
+ struct journal_header_t jdb;
+ struct ext_filesystem *fs = get_fs();
+ char *buf = NULL;
+ struct ext2_inode inode_journal;
+ struct journal_superblock_t *jsb;
+ long int jsb_blknr;
+ char *temp_buff = zalloc(fs->blksz);
+ if (!temp_buff)
+ return;
+
+ ext4fs_read_inode(ext4fs_root, EXT2_JOURNAL_INO, &inode_journal);
+ jsb_blknr = read_allocated_block(&inode_journal,
+ EXT2_JOURNAL_SUPERBLOCK);
+ ext4fs_devread(jsb_blknr * fs->sect_perblk, 0, fs->blksz, temp_buff);
+ jsb = (struct journal_superblock_t *) temp_buff;
+
+ jdb.h_blocktype = cpu_to_be32(EXT3_JOURNAL_COMMIT_BLOCK);
+ jdb.h_magic = cpu_to_be32(EXT3_JOURNAL_MAGIC_NUMBER);
+ jdb.h_sequence = jsb->s_sequence;
+ buf = zalloc(fs->blksz);
+ if (!buf) {
+ free(temp_buff);
+ return;
+ }
+ memcpy(buf, &jdb, sizeof(struct journal_header_t));
+ put_ext4((uint64_t) (blknr * fs->blksz), buf, (uint32_t) fs->blksz);
+
+ free(temp_buff);
+ free(buf);
+}
+
+void ext4fs_update_journal(void)
+{
+ struct ext2_inode inode_journal;
+ struct ext_filesystem *fs = get_fs();
+ long int blknr;
+ int i;
+ ext4fs_read_inode(ext4fs_root, EXT2_JOURNAL_INO, &inode_journal);
+ blknr = read_allocated_block(&inode_journal, jrnl_blk_idx++);
+ update_descriptor_block(blknr);
+ for (i = 0; i < MAX_JOURNAL_ENTRIES; i++) {
+ if (journal_ptr[i]->blknr == -1)
+ break;
+ blknr = read_allocated_block(&inode_journal, jrnl_blk_idx++);
+ put_ext4((uint64_t) ((uint64_t)blknr * (uint64_t)fs->blksz),
+ journal_ptr[i]->buf, fs->blksz);
+ }
+ blknr = read_allocated_block(&inode_journal, jrnl_blk_idx++);
+ update_commit_block(blknr);
+ printf("update journal finished\n");
+}
--- /dev/null
+/*
+ * (C) Copyright 2011 - 2012 Samsung Electronics
+ * EXT4 filesystem implementation in Uboot by
+ * Uma Shankar <uma.shankar@samsung.com>
+ * Manjunatha C Achar <a.manjunatha@samsung.com>
+ *
+ * Journal data structures and headers for Journaling feature of ext4
+ * have been referred from JBD2 (Journaling Block device 2)
+ * implementation in Linux Kernel.
+ *
+ * Written by Stephen C. Tweedie <sct@redhat.com>
+ *
+ * Copyright 1998-2000 Red Hat, Inc --- All Rights Reserved
+ * This file is part of the Linux kernel and is made available under
+ * the terms of the GNU General Public License, version 2, or at your
+ * option, any later version, incorporated herein by reference.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __EXT4_JRNL__
+#define __EXT4_JRNL__
+
+#define EXT2_JOURNAL_INO 8 /* Journal inode */
+#define EXT2_JOURNAL_SUPERBLOCK 0 /* Journal Superblock number */
+
+#define JBD2_FEATURE_COMPAT_CHECKSUM 0x00000001
+#define EXT3_JOURNAL_MAGIC_NUMBER 0xc03b3998U
+#define TRANSACTION_RUNNING 1
+#define TRANSACTION_COMPLETE 0
+#define EXT3_FEATURE_INCOMPAT_RECOVER 0x0004 /* Needs recovery */
+#define EXT3_JOURNAL_DESCRIPTOR_BLOCK 1
+#define EXT3_JOURNAL_COMMIT_BLOCK 2
+#define EXT3_JOURNAL_SUPERBLOCK_V1 3
+#define EXT3_JOURNAL_SUPERBLOCK_V2 4
+#define EXT3_JOURNAL_REVOKE_BLOCK 5
+#define EXT3_JOURNAL_FLAG_ESCAPE 1
+#define EXT3_JOURNAL_FLAG_SAME_UUID 2
+#define EXT3_JOURNAL_FLAG_DELETED 4
+#define EXT3_JOURNAL_FLAG_LAST_TAG 8
+
+/* Maximum entries in 1 journal transaction */
+#define MAX_JOURNAL_ENTRIES 100
+struct journal_log {
+ char *buf;
+ int blknr;
+};
+
+struct dirty_blocks {
+ char *buf;
+ int blknr;
+};
+
+/* Standard header for all descriptor blocks: */
+struct journal_header_t {
+ __u32 h_magic;
+ __u32 h_blocktype;
+ __u32 h_sequence;
+};
+
+/* The journal superblock. All fields are in big-endian byte order. */
+struct journal_superblock_t {
+ /* 0x0000 */
+ struct journal_header_t s_header;
+
+ /* Static information describing the journal */
+ __u32 s_blocksize; /* journal device blocksize */
+ __u32 s_maxlen; /* total blocks in journal file */
+ __u32 s_first; /* first block of log information */
+
+ /* Dynamic information describing the current state of the log */
+ __u32 s_sequence; /* first commit ID expected in log */
+ __u32 s_start; /* blocknr of start of log */
+
+ /* Error value, as set by journal_abort(). */
+ __s32 s_errno;
+
+ /* Remaining fields are only valid in a version-2 superblock */
+ __u32 s_feature_compat; /* compatible feature set */
+ __u32 s_feature_incompat; /* incompatible feature set */
+ __u32 s_feature_ro_compat; /* readonly-compatible feature set */
+ /* 0x0030 */
+ __u8 s_uuid[16]; /* 128-bit uuid for journal */
+
+ /* 0x0040 */
+ __u32 s_nr_users; /* Nr of filesystems sharing log */
+
+ __u32 s_dynsuper; /* Blocknr of dynamic superblock copy */
+
+ /* 0x0048 */
+ __u32 s_max_transaction; /* Limit of journal blocks per trans. */
+ __u32 s_max_trans_data; /* Limit of data blocks per trans. */
+
+ /* 0x0050 */
+ __u32 s_padding[44];
+
+ /* 0x0100 */
+ __u8 s_users[16 * 48]; /* ids of all fs'es sharing the log */
+ /* 0x0400 */
+} ;
+
+struct ext3_journal_block_tag {
+ uint32_t block;
+ uint32_t flags;
+};
+
+struct journal_revoke_header_t {
+ struct journal_header_t r_header;
+ int r_count; /* Count of bytes used in the block */
+};
+
+struct revoke_blk_list {
+ char *content; /* revoke block itself */
+ struct revoke_blk_list *next;
+};
+
+extern struct ext2_data *ext4fs_root;
+
+int ext4fs_init_journal(void);
+int ext4fs_log_gdt(char *gd_table);
+int ext4fs_check_journal_state(int recovery_flag);
+int ext4fs_log_journal(char *journal_buffer, long int blknr);
+int ext4fs_put_metadata(char *metadata_buffer, long int blknr);
+void ext4fs_update_journal(void);
+void ext4fs_dump_metadata(void);
+void ext4fs_push_revoke_blk(char *buffer);
+void ext4fs_free_journal(void);
+void ext4fs_free_revoke_blks(void);
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2011 - 2012 Samsung Electronics
+ * EXT4 filesystem implementation in Uboot by
+ * Uma Shankar <uma.shankar@samsung.com>
+ * Manjunatha C Achar <a.manjunatha@samsung.com>
+ *
+ * ext4ls and ext4load : Based on ext2 ls and load support in Uboot.
+ * Ext4 read optimization taken from Open-Moko
+ * Qi bootloader
+ *
+ * (C) Copyright 2004
+ * esd gmbh <www.esd-electronics.com>
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * based on code from grub2 fs/ext2.c and fs/fshelp.c by
+ * GRUB -- GRand Unified Bootloader
+ * Copyright (C) 2003, 2004 Free Software Foundation, Inc.
+ *
+ * ext4write : Based on generic ext4 protocol.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <ext_common.h>
+#include <ext4fs.h>
+#include <linux/stat.h>
+#include <linux/time.h>
+#include <asm/byteorder.h>
+#include "ext4_common.h"
+
+int ext4fs_symlinknest;
+block_dev_desc_t *ext4_dev_desc;
+
+struct ext_filesystem *get_fs(void)
+{
+ if (ext4_dev_desc == NULL || ext4_dev_desc->priv == NULL)
+ printf("Invalid Input Arguments %s\n", __func__);
+
+ return ext4_dev_desc->priv;
+}
+
+int init_fs(block_dev_desc_t *dev_desc)
+{
+ struct ext_filesystem *fs;
+ if (dev_desc == NULL) {
+ printf("Invalid Input Arguments %s\n", __func__);
+ return -EINVAL;
+ }
+
+ fs = zalloc(sizeof(struct ext_filesystem));
+ if (fs == NULL) {
+ printf("malloc failed: %s\n", __func__);
+ return -ENOMEM;
+ }
+
+ fs->dev_desc = dev_desc;
+ dev_desc->priv = fs;
+
+ return 0;
+}
+
+void deinit_fs(block_dev_desc_t *dev_desc)
+{
+ if (dev_desc == NULL) {
+ printf("Invalid Input Arguments %s\n", __func__);
+ return;
+ }
+ free(dev_desc->priv);
+ dev_desc->priv = NULL;
+}
+
+void ext4fs_free_node(struct ext2fs_node *node, struct ext2fs_node *currroot)
+{
+ if ((node != &ext4fs_root->diropen) && (node != currroot))
+ free(node);
+}
+
+/*
+ * Taken from openmoko-kernel mailing list: By Andy green
+ * Optimized read file API : collects and defers contiguous sector
+ * reads into one potentially more efficient larger sequential read action
+ */
+int ext4fs_read_file(struct ext2fs_node *node, int pos,
+ unsigned int len, char *buf)
+{
+ int i;
+ int blockcnt;
+ int log2blocksize = LOG2_EXT2_BLOCK_SIZE(node->data);
+ int blocksize = 1 << (log2blocksize + DISK_SECTOR_BITS);
+ unsigned int filesize = __le32_to_cpu(node->inode.size);
+ int previous_block_number = -1;
+ int delayed_start = 0;
+ int delayed_extent = 0;
+ int delayed_skipfirst = 0;
+ int delayed_next = 0;
+ char *delayed_buf = NULL;
+ short status;
+
+ /* Adjust len so it we can't read past the end of the file. */
+ if (len > filesize)
+ len = filesize;
+
+ blockcnt = ((len + pos) + blocksize - 1) / blocksize;
+
+ for (i = pos / blocksize; i < blockcnt; i++) {
+ int blknr;
+ int blockoff = pos % blocksize;
+ int blockend = blocksize;
+ int skipfirst = 0;
+ blknr = read_allocated_block(&(node->inode), i);
+ if (blknr < 0)
+ return -1;
+
+ blknr = blknr << log2blocksize;
+
+ /* Last block. */
+ if (i == blockcnt - 1) {
+ blockend = (len + pos) % blocksize;
+
+ /* The last portion is exactly blocksize. */
+ if (!blockend)
+ blockend = blocksize;
+ }
+
+ /* First block. */
+ if (i == pos / blocksize) {
+ skipfirst = blockoff;
+ blockend -= skipfirst;
+ }
+ if (blknr) {
+ int status;
+
+ if (previous_block_number != -1) {
+ if (delayed_next == blknr) {
+ delayed_extent += blockend;
+ delayed_next += blockend >> SECTOR_BITS;
+ } else { /* spill */
+ status = ext4fs_devread(delayed_start,
+ delayed_skipfirst,
+ delayed_extent,
+ delayed_buf);
+ if (status == 0)
+ return -1;
+ previous_block_number = blknr;
+ delayed_start = blknr;
+ delayed_extent = blockend;
+ delayed_skipfirst = skipfirst;
+ delayed_buf = buf;
+ delayed_next = blknr +
+ (blockend >> SECTOR_BITS);
+ }
+ } else {
+ previous_block_number = blknr;
+ delayed_start = blknr;
+ delayed_extent = blockend;
+ delayed_skipfirst = skipfirst;
+ delayed_buf = buf;
+ delayed_next = blknr +
+ (blockend >> SECTOR_BITS);
+ }
+ } else {
+ if (previous_block_number != -1) {
+ /* spill */
+ status = ext4fs_devread(delayed_start,
+ delayed_skipfirst,
+ delayed_extent,
+ delayed_buf);
+ if (status == 0)
+ return -1;
+ previous_block_number = -1;
+ }
+ memset(buf, 0, blocksize - skipfirst);
+ }
+ buf += blocksize - skipfirst;
+ }
+ if (previous_block_number != -1) {
+ /* spill */
+ status = ext4fs_devread(delayed_start,
+ delayed_skipfirst, delayed_extent,
+ delayed_buf);
+ if (status == 0)
+ return -1;
+ previous_block_number = -1;
+ }
+
+ return len;
+}
+
+int ext4fs_ls(const char *dirname)
+{
+ struct ext2fs_node *dirnode;
+ int status;
+
+ if (dirname == NULL)
+ return 0;
+
+ status = ext4fs_find_file(dirname, &ext4fs_root->diropen, &dirnode,
+ FILETYPE_DIRECTORY);
+ if (status != 1) {
+ printf("** Can not find directory. **\n");
+ return 1;
+ }
+
+ ext4fs_iterate_dir(dirnode, NULL, NULL, NULL);
+ ext4fs_free_node(dirnode, &ext4fs_root->diropen);
+
+ return 0;
+}
+
+int ext4fs_read(char *buf, unsigned len)
+{
+ if (ext4fs_root == NULL || ext4fs_file == NULL)
+ return 0;
+
+ return ext4fs_read_file(ext4fs_file, 0, len, buf);
+}
+
+#if defined(CONFIG_CMD_EXT4_WRITE)
+static void ext4fs_update(void)
+{
+ short i;
+ ext4fs_update_journal();
+ struct ext_filesystem *fs = get_fs();
+
+ /* update super block */
+ put_ext4((uint64_t)(SUPERBLOCK_SIZE),
+ (struct ext2_sblock *)fs->sb, (uint32_t)SUPERBLOCK_SIZE);
+
+ /* update block groups */
+ for (i = 0; i < fs->no_blkgrp; i++) {
+ fs->gd[i].bg_checksum = ext4fs_checksum_update(i);
+ put_ext4((uint64_t)(fs->gd[i].block_id * fs->blksz),
+ fs->blk_bmaps[i], fs->blksz);
+ }
+
+ /* update inode table groups */
+ for (i = 0; i < fs->no_blkgrp; i++) {
+ put_ext4((uint64_t) (fs->gd[i].inode_id * fs->blksz),
+ fs->inode_bmaps[i], fs->blksz);
+ }
+
+ /* update the block group descriptor table */
+ put_ext4((uint64_t)(fs->gdtable_blkno * fs->blksz),
+ (struct ext2_block_group *)fs->gdtable,
+ (fs->blksz * fs->no_blk_pergdt));
+
+ ext4fs_dump_metadata();
+
+ gindex = 0;
+ gd_index = 0;
+}
+
+int ext4fs_get_bgdtable(void)
+{
+ int status;
+ int grp_desc_size;
+ struct ext_filesystem *fs = get_fs();
+ grp_desc_size = sizeof(struct ext2_block_group);
+ fs->no_blk_pergdt = (fs->no_blkgrp * grp_desc_size) / fs->blksz;
+ if ((fs->no_blkgrp * grp_desc_size) % fs->blksz)
+ fs->no_blk_pergdt++;
+
+ /* allocate memory for gdtable */
+ fs->gdtable = zalloc(fs->blksz * fs->no_blk_pergdt);
+ if (!fs->gdtable)
+ return -ENOMEM;
+ /* read the group descriptor table */
+ status = ext4fs_devread(fs->gdtable_blkno * fs->sect_perblk, 0,
+ fs->blksz * fs->no_blk_pergdt, fs->gdtable);
+ if (status == 0)
+ goto fail;
+
+ if (ext4fs_log_gdt(fs->gdtable)) {
+ printf("Error in ext4fs_log_gdt\n");
+ return -1;
+ }
+
+ return 0;
+fail:
+ free(fs->gdtable);
+ fs->gdtable = NULL;
+
+ return -1;
+}
+
+static void delete_single_indirect_block(struct ext2_inode *inode)
+{
+ struct ext2_block_group *gd = NULL;
+ static int prev_bg_bmap_idx = -1;
+ long int blknr;
+ int remainder;
+ int bg_idx;
+ int status;
+ unsigned int blk_per_grp = ext4fs_root->sblock.blocks_per_group;
+ struct ext_filesystem *fs = get_fs();
+ char *journal_buffer = zalloc(fs->blksz);
+ if (!journal_buffer) {
+ printf("No memory\n");
+ return;
+ }
+ /* get block group descriptor table */
+ gd = (struct ext2_block_group *)fs->gdtable;
+
+ /* deleting the single indirect block associated with inode */
+ if (inode->b.blocks.indir_block != 0) {
+ debug("SIPB releasing %u\n", inode->b.blocks.indir_block);
+ blknr = inode->b.blocks.indir_block;
+ if (fs->blksz != 1024) {
+ bg_idx = blknr / blk_per_grp;
+ } else {
+ bg_idx = blknr / blk_per_grp;
+ remainder = blknr % blk_per_grp;
+ if (!remainder)
+ bg_idx--;
+ }
+ ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx], bg_idx);
+ gd[bg_idx].free_blocks++;
+ fs->sb->free_blocks++;
+ /* journal backup */
+ if (prev_bg_bmap_idx != bg_idx) {
+ status =
+ ext4fs_devread(gd[bg_idx].block_id *
+ fs->sect_perblk, 0, fs->blksz,
+ journal_buffer);
+ if (status == 0)
+ goto fail;
+ if (ext4fs_log_journal
+ (journal_buffer, gd[bg_idx].block_id))
+ goto fail;
+ prev_bg_bmap_idx = bg_idx;
+ }
+ }
+fail:
+ free(journal_buffer);
+}
+
+static void delete_double_indirect_block(struct ext2_inode *inode)
+{
+ int i;
+ short status;
+ static int prev_bg_bmap_idx = -1;
+ long int blknr;
+ int remainder;
+ int bg_idx;
+ unsigned int blk_per_grp = ext4fs_root->sblock.blocks_per_group;
+ unsigned int *di_buffer = NULL;
+ unsigned int *DIB_start_addr = NULL;
+ struct ext2_block_group *gd = NULL;
+ struct ext_filesystem *fs = get_fs();
+ char *journal_buffer = zalloc(fs->blksz);
+ if (!journal_buffer) {
+ printf("No memory\n");
+ return;
+ }
+ /* get the block group descriptor table */
+ gd = (struct ext2_block_group *)fs->gdtable;
+
+ if (inode->b.blocks.double_indir_block != 0) {
+ di_buffer = zalloc(fs->blksz);
+ if (!di_buffer) {
+ printf("No memory\n");
+ return;
+ }
+ DIB_start_addr = (unsigned int *)di_buffer;
+ blknr = inode->b.blocks.double_indir_block;
+ status = ext4fs_devread(blknr * fs->sect_perblk, 0, fs->blksz,
+ (char *)di_buffer);
+ for (i = 0; i < fs->blksz / sizeof(int); i++) {
+ if (*di_buffer == 0)
+ break;
+
+ debug("DICB releasing %u\n", *di_buffer);
+ if (fs->blksz != 1024) {
+ bg_idx = (*di_buffer) / blk_per_grp;
+ } else {
+ bg_idx = (*di_buffer) / blk_per_grp;
+ remainder = (*di_buffer) % blk_per_grp;
+ if (!remainder)
+ bg_idx--;
+ }
+ ext4fs_reset_block_bmap(*di_buffer,
+ fs->blk_bmaps[bg_idx], bg_idx);
+ di_buffer++;
+ gd[bg_idx].free_blocks++;
+ fs->sb->free_blocks++;
+ /* journal backup */
+ if (prev_bg_bmap_idx != bg_idx) {
+ status = ext4fs_devread(gd[bg_idx].block_id
+ * fs->sect_perblk, 0,
+ fs->blksz,
+ journal_buffer);
+ if (status == 0)
+ goto fail;
+
+ if (ext4fs_log_journal(journal_buffer,
+ gd[bg_idx].block_id))
+ goto fail;
+ prev_bg_bmap_idx = bg_idx;
+ }
+ }
+
+ /* removing the parent double indirect block */
+ blknr = inode->b.blocks.double_indir_block;
+ if (fs->blksz != 1024) {
+ bg_idx = blknr / blk_per_grp;
+ } else {
+ bg_idx = blknr / blk_per_grp;
+ remainder = blknr % blk_per_grp;
+ if (!remainder)
+ bg_idx--;
+ }
+ ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx], bg_idx);
+ gd[bg_idx].free_blocks++;
+ fs->sb->free_blocks++;
+ /* journal backup */
+ if (prev_bg_bmap_idx != bg_idx) {
+ memset(journal_buffer, '\0', fs->blksz);
+ status = ext4fs_devread(gd[bg_idx].block_id *
+ fs->sect_perblk, 0, fs->blksz,
+ journal_buffer);
+ if (status == 0)
+ goto fail;
+
+ if (ext4fs_log_journal(journal_buffer,
+ gd[bg_idx].block_id))
+ goto fail;
+ prev_bg_bmap_idx = bg_idx;
+ }
+ debug("DIPB releasing %ld\n", blknr);
+ }
+fail:
+ free(DIB_start_addr);
+ free(journal_buffer);
+}
+
+static void delete_triple_indirect_block(struct ext2_inode *inode)
+{
+ int i, j;
+ short status;
+ static int prev_bg_bmap_idx = -1;
+ long int blknr;
+ int remainder;
+ int bg_idx;
+ unsigned int blk_per_grp = ext4fs_root->sblock.blocks_per_group;
+ unsigned int *tigp_buffer = NULL;
+ unsigned int *tib_start_addr = NULL;
+ unsigned int *tip_buffer = NULL;
+ unsigned int *tipb_start_addr = NULL;
+ struct ext2_block_group *gd = NULL;
+ struct ext_filesystem *fs = get_fs();
+ char *journal_buffer = zalloc(fs->blksz);
+ if (!journal_buffer) {
+ printf("No memory\n");
+ return;
+ }
+ /* get block group descriptor table */
+ gd = (struct ext2_block_group *)fs->gdtable;
+
+ if (inode->b.blocks.triple_indir_block != 0) {
+ tigp_buffer = zalloc(fs->blksz);
+ if (!tigp_buffer) {
+ printf("No memory\n");
+ return;
+ }
+ tib_start_addr = (unsigned int *)tigp_buffer;
+ blknr = inode->b.blocks.triple_indir_block;
+ status = ext4fs_devread(blknr * fs->sect_perblk, 0, fs->blksz,
+ (char *)tigp_buffer);
+ for (i = 0; i < fs->blksz / sizeof(int); i++) {
+ if (*tigp_buffer == 0)
+ break;
+ debug("tigp buffer releasing %u\n", *tigp_buffer);
+
+ tip_buffer = zalloc(fs->blksz);
+ if (!tip_buffer)
+ goto fail;
+ tipb_start_addr = (unsigned int *)tip_buffer;
+ status = ext4fs_devread((*tigp_buffer) *
+ fs->sect_perblk, 0, fs->blksz,
+ (char *)tip_buffer);
+ for (j = 0; j < fs->blksz / sizeof(int); j++) {
+ if (*tip_buffer == 0)
+ break;
+ if (fs->blksz != 1024) {
+ bg_idx = (*tip_buffer) / blk_per_grp;
+ } else {
+ bg_idx = (*tip_buffer) / blk_per_grp;
+
+ remainder = (*tip_buffer) % blk_per_grp;
+ if (!remainder)
+ bg_idx--;
+ }
+
+ ext4fs_reset_block_bmap(*tip_buffer,
+ fs->blk_bmaps[bg_idx],
+ bg_idx);
+
+ tip_buffer++;
+ gd[bg_idx].free_blocks++;
+ fs->sb->free_blocks++;
+ /* journal backup */
+ if (prev_bg_bmap_idx != bg_idx) {
+ status =
+ ext4fs_devread(gd[bg_idx].block_id *
+ fs->sect_perblk, 0,
+ fs->blksz,
+ journal_buffer);
+ if (status == 0)
+ goto fail;
+
+ if (ext4fs_log_journal(journal_buffer,
+ gd[bg_idx].
+ block_id))
+ goto fail;
+ prev_bg_bmap_idx = bg_idx;
+ }
+ }
+ free(tipb_start_addr);
+ tipb_start_addr = NULL;
+
+ /*
+ * removing the grand parent blocks
+ * which is connected to inode
+ */
+ if (fs->blksz != 1024) {
+ bg_idx = (*tigp_buffer) / blk_per_grp;
+ } else {
+ bg_idx = (*tigp_buffer) / blk_per_grp;
+
+ remainder = (*tigp_buffer) % blk_per_grp;
+ if (!remainder)
+ bg_idx--;
+ }
+ ext4fs_reset_block_bmap(*tigp_buffer,
+ fs->blk_bmaps[bg_idx], bg_idx);
+
+ tigp_buffer++;
+ gd[bg_idx].free_blocks++;
+ fs->sb->free_blocks++;
+ /* journal backup */
+ if (prev_bg_bmap_idx != bg_idx) {
+ memset(journal_buffer, '\0', fs->blksz);
+ status =
+ ext4fs_devread(gd[bg_idx].block_id *
+ fs->sect_perblk, 0,
+ fs->blksz, journal_buffer);
+ if (status == 0)
+ goto fail;
+
+ if (ext4fs_log_journal(journal_buffer,
+ gd[bg_idx].block_id))
+ goto fail;
+ prev_bg_bmap_idx = bg_idx;
+ }
+ }
+
+ /* removing the grand parent triple indirect block */
+ blknr = inode->b.blocks.triple_indir_block;
+ if (fs->blksz != 1024) {
+ bg_idx = blknr / blk_per_grp;
+ } else {
+ bg_idx = blknr / blk_per_grp;
+ remainder = blknr % blk_per_grp;
+ if (!remainder)
+ bg_idx--;
+ }
+ ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx], bg_idx);
+ gd[bg_idx].free_blocks++;
+ fs->sb->free_blocks++;
+ /* journal backup */
+ if (prev_bg_bmap_idx != bg_idx) {
+ memset(journal_buffer, '\0', fs->blksz);
+ status = ext4fs_devread(gd[bg_idx].block_id *
+ fs->sect_perblk, 0, fs->blksz,
+ journal_buffer);
+ if (status == 0)
+ goto fail;
+
+ if (ext4fs_log_journal(journal_buffer,
+ gd[bg_idx].block_id))
+ goto fail;
+ prev_bg_bmap_idx = bg_idx;
+ }
+ debug("tigp buffer itself releasing %ld\n", blknr);
+ }
+fail:
+ free(tib_start_addr);
+ free(tipb_start_addr);
+ free(journal_buffer);
+}
+
+static int ext4fs_delete_file(int inodeno)
+{
+ struct ext2_inode inode;
+ short status;
+ int i;
+ int remainder;
+ long int blknr;
+ int bg_idx;
+ int ibmap_idx;
+ char *read_buffer = NULL;
+ char *start_block_address = NULL;
+ unsigned int no_blocks;
+
+ static int prev_bg_bmap_idx = -1;
+ unsigned int inodes_per_block;
+ long int blkno;
+ unsigned int blkoff;
+ unsigned int blk_per_grp = ext4fs_root->sblock.blocks_per_group;
+ unsigned int inode_per_grp = ext4fs_root->sblock.inodes_per_group;
+ struct ext2_inode *inode_buffer = NULL;
+ struct ext2_block_group *gd = NULL;
+ struct ext_filesystem *fs = get_fs();
+ char *journal_buffer = zalloc(fs->blksz);
+ if (!journal_buffer)
+ return -ENOMEM;
+ /* get the block group descriptor table */
+ gd = (struct ext2_block_group *)fs->gdtable;
+ status = ext4fs_read_inode(ext4fs_root, inodeno, &inode);
+ if (status == 0)
+ goto fail;
+
+ /* read the block no allocated to a file */
+ no_blocks = inode.size / fs->blksz;
+ if (inode.size % fs->blksz)
+ no_blocks++;
+
+ if (le32_to_cpu(inode.flags) & EXT4_EXTENTS_FL) {
+ struct ext2fs_node *node_inode =
+ zalloc(sizeof(struct ext2fs_node));
+ if (!node_inode)
+ goto fail;
+ node_inode->data = ext4fs_root;
+ node_inode->ino = inodeno;
+ node_inode->inode_read = 0;
+ memcpy(&(node_inode->inode), &inode, sizeof(struct ext2_inode));
+
+ for (i = 0; i < no_blocks; i++) {
+ blknr = read_allocated_block(&(node_inode->inode), i);
+ if (fs->blksz != 1024) {
+ bg_idx = blknr / blk_per_grp;
+ } else {
+ bg_idx = blknr / blk_per_grp;
+ remainder = blknr % blk_per_grp;
+ if (!remainder)
+ bg_idx--;
+ }
+ ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx],
+ bg_idx);
+ debug("EXT4_EXTENTS Block releasing %ld: %d\n",
+ blknr, bg_idx);
+
+ gd[bg_idx].free_blocks++;
+ fs->sb->free_blocks++;
+
+ /* journal backup */
+ if (prev_bg_bmap_idx != bg_idx) {
+ status =
+ ext4fs_devread(gd[bg_idx].block_id *
+ fs->sect_perblk, 0,
+ fs->blksz, journal_buffer);
+ if (status == 0)
+ goto fail;
+ if (ext4fs_log_journal(journal_buffer,
+ gd[bg_idx].block_id))
+ goto fail;
+ prev_bg_bmap_idx = bg_idx;
+ }
+ }
+ if (node_inode) {
+ free(node_inode);
+ node_inode = NULL;
+ }
+ } else {
+
+ delete_single_indirect_block(&inode);
+ delete_double_indirect_block(&inode);
+ delete_triple_indirect_block(&inode);
+
+ /* read the block no allocated to a file */
+ no_blocks = inode.size / fs->blksz;
+ if (inode.size % fs->blksz)
+ no_blocks++;
+ for (i = 0; i < no_blocks; i++) {
+ blknr = read_allocated_block(&inode, i);
+ if (fs->blksz != 1024) {
+ bg_idx = blknr / blk_per_grp;
+ } else {
+ bg_idx = blknr / blk_per_grp;
+ remainder = blknr % blk_per_grp;
+ if (!remainder)
+ bg_idx--;
+ }
+ ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx],
+ bg_idx);
+ debug("ActualB releasing %ld: %d\n", blknr, bg_idx);
+
+ gd[bg_idx].free_blocks++;
+ fs->sb->free_blocks++;
+ /* journal backup */
+ if (prev_bg_bmap_idx != bg_idx) {
+ memset(journal_buffer, '\0', fs->blksz);
+ status = ext4fs_devread(gd[bg_idx].block_id
+ * fs->sect_perblk,
+ 0, fs->blksz,
+ journal_buffer);
+ if (status == 0)
+ goto fail;
+ if (ext4fs_log_journal(journal_buffer,
+ gd[bg_idx].block_id))
+ goto fail;
+ prev_bg_bmap_idx = bg_idx;
+ }
+ }
+ }
+
+ /* from the inode no to blockno */
+ inodes_per_block = fs->blksz / fs->inodesz;
+ ibmap_idx = inodeno / inode_per_grp;
+
+ /* get the block no */
+ inodeno--;
+ blkno = __le32_to_cpu(gd[ibmap_idx].inode_table_id) +
+ (inodeno % __le32_to_cpu(inode_per_grp)) / inodes_per_block;
+
+ /* get the offset of the inode */
+ blkoff = ((inodeno) % inodes_per_block) * fs->inodesz;
+
+ /* read the block no containing the inode */
+ read_buffer = zalloc(fs->blksz);
+ if (!read_buffer)
+ goto fail;
+ start_block_address = read_buffer;
+ status = ext4fs_devread(blkno * fs->sect_perblk,
+ 0, fs->blksz, read_buffer);
+ if (status == 0)
+ goto fail;
+
+ if (ext4fs_log_journal(read_buffer, blkno))
+ goto fail;
+
+ read_buffer = read_buffer + blkoff;
+ inode_buffer = (struct ext2_inode *)read_buffer;
+ memset(inode_buffer, '\0', sizeof(struct ext2_inode));
+
+ /* write the inode to original position in inode table */
+ if (ext4fs_put_metadata(start_block_address, blkno))
+ goto fail;
+
+ /* update the respective inode bitmaps */
+ inodeno++;
+ ext4fs_reset_inode_bmap(inodeno, fs->inode_bmaps[ibmap_idx], ibmap_idx);
+ gd[ibmap_idx].free_inodes++;
+ fs->sb->free_inodes++;
+ /* journal backup */
+ memset(journal_buffer, '\0', fs->blksz);
+ status = ext4fs_devread(gd[ibmap_idx].inode_id *
+ fs->sect_perblk, 0, fs->blksz, journal_buffer);
+ if (status == 0)
+ goto fail;
+ if (ext4fs_log_journal(journal_buffer, gd[ibmap_idx].inode_id))
+ goto fail;
+
+ ext4fs_update();
+ ext4fs_deinit();
+
+ if (ext4fs_init() != 0) {
+ printf("error in File System init\n");
+ goto fail;
+ }
+
+ free(start_block_address);
+ free(journal_buffer);
+
+ return 0;
+fail:
+ free(start_block_address);
+ free(journal_buffer);
+
+ return -1;
+}
+
+int ext4fs_init(void)
+{
+ short status;
+ int i;
+ unsigned int real_free_blocks = 0;
+ struct ext_filesystem *fs = get_fs();
+
+ /* populate fs */
+ fs->blksz = EXT2_BLOCK_SIZE(ext4fs_root);
+ fs->inodesz = INODE_SIZE_FILESYSTEM(ext4fs_root);
+ fs->sect_perblk = fs->blksz / SECTOR_SIZE;
+
+ /* get the superblock */
+ fs->sb = zalloc(SUPERBLOCK_SIZE);
+ if (!fs->sb)
+ return -ENOMEM;
+ if (!ext4fs_devread(SUPERBLOCK_SECTOR, 0, SUPERBLOCK_SIZE,
+ (char *)fs->sb))
+ goto fail;
+
+ /* init journal */
+ if (ext4fs_init_journal())
+ goto fail;
+
+ /* get total no of blockgroups */
+ fs->no_blkgrp = (uint32_t)ext4fs_div_roundup(
+ (ext4fs_root->sblock.total_blocks -
+ ext4fs_root->sblock.first_data_block),
+ ext4fs_root->sblock.blocks_per_group);
+
+ /* get the block group descriptor table */
+ fs->gdtable_blkno = ((EXT2_MIN_BLOCK_SIZE == fs->blksz) + 1);
+ if (ext4fs_get_bgdtable() == -1) {
+ printf("Error in getting the block group descriptor table\n");
+ goto fail;
+ }
+ fs->gd = (struct ext2_block_group *)fs->gdtable;
+
+ /* load all the available bitmap block of the partition */
+ fs->blk_bmaps = zalloc(fs->no_blkgrp * sizeof(char *));
+ if (!fs->blk_bmaps)
+ goto fail;
+ for (i = 0; i < fs->no_blkgrp; i++) {
+ fs->blk_bmaps[i] = zalloc(fs->blksz);
+ if (!fs->blk_bmaps[i])
+ goto fail;
+ }
+
+ for (i = 0; i < fs->no_blkgrp; i++) {
+ status =
+ ext4fs_devread(fs->gd[i].block_id * fs->sect_perblk, 0,
+ fs->blksz, (char *)fs->blk_bmaps[i]);
+ if (status == 0)
+ goto fail;
+ }
+
+ /* load all the available inode bitmap of the partition */
+ fs->inode_bmaps = zalloc(fs->no_blkgrp * sizeof(unsigned char *));
+ if (!fs->inode_bmaps)
+ goto fail;
+ for (i = 0; i < fs->no_blkgrp; i++) {
+ fs->inode_bmaps[i] = zalloc(fs->blksz);
+ if (!fs->inode_bmaps[i])
+ goto fail;
+ }
+
+ for (i = 0; i < fs->no_blkgrp; i++) {
+ status = ext4fs_devread(fs->gd[i].inode_id * fs->sect_perblk,
+ 0, fs->blksz,
+ (char *)fs->inode_bmaps[i]);
+ if (status == 0)
+ goto fail;
+ }
+
+ /*
+ * check filesystem consistency with free blocks of file system
+ * some time we observed that superblock freeblocks does not match
+ * with the blockgroups freeblocks when improper
+ * reboot of a linux kernel
+ */
+ for (i = 0; i < fs->no_blkgrp; i++)
+ real_free_blocks = real_free_blocks + fs->gd[i].free_blocks;
+ if (real_free_blocks != fs->sb->free_blocks)
+ fs->sb->free_blocks = real_free_blocks;
+
+ return 0;
+fail:
+ ext4fs_deinit();
+
+ return -1;
+}
+
+void ext4fs_deinit(void)
+{
+ int i;
+ struct ext2_inode inode_journal;
+ struct journal_superblock_t *jsb;
+ long int blknr;
+ struct ext_filesystem *fs = get_fs();
+
+ /* free journal */
+ char *temp_buff = zalloc(fs->blksz);
+ if (temp_buff) {
+ ext4fs_read_inode(ext4fs_root, EXT2_JOURNAL_INO,
+ &inode_journal);
+ blknr = read_allocated_block(&inode_journal,
+ EXT2_JOURNAL_SUPERBLOCK);
+ ext4fs_devread(blknr * fs->sect_perblk, 0, fs->blksz,
+ temp_buff);
+ jsb = (struct journal_superblock_t *)temp_buff;
+ jsb->s_start = cpu_to_be32(0);
+ put_ext4((uint64_t) (blknr * fs->blksz),
+ (struct journal_superblock_t *)temp_buff, fs->blksz);
+ free(temp_buff);
+ }
+ ext4fs_free_journal();
+
+ /* get the superblock */
+ ext4fs_devread(SUPERBLOCK_SECTOR, 0, SUPERBLOCK_SIZE, (char *)fs->sb);
+ fs->sb->feature_incompat &= ~EXT3_FEATURE_INCOMPAT_RECOVER;
+ put_ext4((uint64_t)(SUPERBLOCK_SIZE),
+ (struct ext2_sblock *)fs->sb, (uint32_t)SUPERBLOCK_SIZE);
+ free(fs->sb);
+ fs->sb = NULL;
+
+ if (fs->blk_bmaps) {
+ for (i = 0; i < fs->no_blkgrp; i++) {
+ free(fs->blk_bmaps[i]);
+ fs->blk_bmaps[i] = NULL;
+ }
+ free(fs->blk_bmaps);
+ fs->blk_bmaps = NULL;
+ }
+
+ if (fs->inode_bmaps) {
+ for (i = 0; i < fs->no_blkgrp; i++) {
+ free(fs->inode_bmaps[i]);
+ fs->inode_bmaps[i] = NULL;
+ }
+ free(fs->inode_bmaps);
+ fs->inode_bmaps = NULL;
+ }
+
+
+ free(fs->gdtable);
+ fs->gdtable = NULL;
+ fs->gd = NULL;
+ /*
+ * reinitiliazed the global inode and
+ * block bitmap first execution check variables
+ */
+ fs->first_pass_ibmap = 0;
+ fs->first_pass_bbmap = 0;
+ fs->curr_inode_no = 0;
+ fs->curr_blkno = 0;
+}
+
+static int ext4fs_write_file(struct ext2_inode *file_inode,
+ int pos, unsigned int len, char *buf)
+{
+ int i;
+ int blockcnt;
+ int log2blocksize = LOG2_EXT2_BLOCK_SIZE(ext4fs_root);
+ unsigned int filesize = __le32_to_cpu(file_inode->size);
+ struct ext_filesystem *fs = get_fs();
+ int previous_block_number = -1;
+ int delayed_start = 0;
+ int delayed_extent = 0;
+ int delayed_skipfirst = 0;
+ int delayed_next = 0;
+ char *delayed_buf = NULL;
+
+ /* Adjust len so it we can't read past the end of the file. */
+ if (len > filesize)
+ len = filesize;
+
+ blockcnt = ((len + pos) + fs->blksz - 1) / fs->blksz;
+
+ for (i = pos / fs->blksz; i < blockcnt; i++) {
+ long int blknr;
+ int blockend = fs->blksz;
+ int skipfirst = 0;
+ blknr = read_allocated_block(file_inode, i);
+ if (blknr < 0)
+ return -1;
+
+ blknr = blknr << log2blocksize;
+
+ if (blknr) {
+ if (previous_block_number != -1) {
+ if (delayed_next == blknr) {
+ delayed_extent += blockend;
+ delayed_next += blockend >> SECTOR_BITS;
+ } else { /* spill */
+ put_ext4((uint64_t) (delayed_start *
+ SECTOR_SIZE),
+ delayed_buf,
+ (uint32_t) delayed_extent);
+ previous_block_number = blknr;
+ delayed_start = blknr;
+ delayed_extent = blockend;
+ delayed_skipfirst = skipfirst;
+ delayed_buf = buf;
+ delayed_next = blknr +
+ (blockend >> SECTOR_BITS);
+ }
+ } else {
+ previous_block_number = blknr;
+ delayed_start = blknr;
+ delayed_extent = blockend;
+ delayed_skipfirst = skipfirst;
+ delayed_buf = buf;
+ delayed_next = blknr +
+ (blockend >> SECTOR_BITS);
+ }
+ } else {
+ if (previous_block_number != -1) {
+ /* spill */
+ put_ext4((uint64_t) (delayed_start *
+ SECTOR_SIZE), delayed_buf,
+ (uint32_t) delayed_extent);
+ previous_block_number = -1;
+ }
+ memset(buf, 0, fs->blksz - skipfirst);
+ }
+ buf += fs->blksz - skipfirst;
+ }
+ if (previous_block_number != -1) {
+ /* spill */
+ put_ext4((uint64_t) (delayed_start * SECTOR_SIZE),
+ delayed_buf, (uint32_t) delayed_extent);
+ previous_block_number = -1;
+ }
+
+ return len;
+}
+
+int ext4fs_write(const char *fname, unsigned char *buffer,
+ unsigned long sizebytes)
+{
+ int ret = 0;
+ struct ext2_inode *file_inode = NULL;
+ unsigned char *inode_buffer = NULL;
+ int parent_inodeno;
+ int inodeno;
+ time_t timestamp = 0;
+
+ uint64_t bytes_reqd_for_file;
+ unsigned int blks_reqd_for_file;
+ unsigned int blocks_remaining;
+ int existing_file_inodeno;
+ char filename[256];
+
+ char *temp_ptr = NULL;
+ long int itable_blkno;
+ long int parent_itable_blkno;
+ long int blkoff;
+ struct ext2_sblock *sblock = &(ext4fs_root->sblock);
+ unsigned int inodes_per_block;
+ unsigned int ibmap_idx;
+ struct ext_filesystem *fs = get_fs();
+ g_parent_inode = zalloc(sizeof(struct ext2_inode));
+ if (!g_parent_inode)
+ goto fail;
+
+ if (ext4fs_init() != 0) {
+ printf("error in File System init\n");
+ return -1;
+ }
+ inodes_per_block = fs->blksz / fs->inodesz;
+ parent_inodeno = ext4fs_get_parent_inode_num(fname, filename, F_FILE);
+ if (parent_inodeno == -1)
+ goto fail;
+ if (ext4fs_iget(parent_inodeno, g_parent_inode))
+ goto fail;
+ /* check if the filename is already present in root */
+ existing_file_inodeno = ext4fs_filename_check(filename);
+ if (existing_file_inodeno != -1) {
+ ret = ext4fs_delete_file(existing_file_inodeno);
+ fs->first_pass_bbmap = 0;
+ fs->curr_blkno = 0;
+
+ fs->first_pass_ibmap = 0;
+ fs->curr_inode_no = 0;
+ if (ret)
+ goto fail;
+ }
+ /* calucalate how many blocks required */
+ bytes_reqd_for_file = sizebytes;
+ blks_reqd_for_file = bytes_reqd_for_file / fs->blksz;
+ if (bytes_reqd_for_file % fs->blksz != 0) {
+ blks_reqd_for_file++;
+ debug("total bytes for a file %u\n", blks_reqd_for_file);
+ }
+ blocks_remaining = blks_reqd_for_file;
+ /* test for available space in partition */
+ if (fs->sb->free_blocks < blks_reqd_for_file) {
+ printf("Not enough space on partition !!!\n");
+ goto fail;
+ }
+
+ ext4fs_update_parent_dentry(filename, &inodeno, FILETYPE_REG);
+ /* prepare file inode */
+ inode_buffer = zalloc(fs->inodesz);
+ if (!inode_buffer)
+ goto fail;
+ file_inode = (struct ext2_inode *)inode_buffer;
+ file_inode->mode = S_IFREG | S_IRWXU |
+ S_IRGRP | S_IROTH | S_IXGRP | S_IXOTH;
+ /* ToDo: Update correct time */
+ file_inode->mtime = timestamp;
+ file_inode->atime = timestamp;
+ file_inode->ctime = timestamp;
+ file_inode->nlinks = 1;
+ file_inode->size = sizebytes;
+
+ /* Allocate data blocks */
+ ext4fs_allocate_blocks(file_inode, blocks_remaining,
+ &blks_reqd_for_file);
+ file_inode->blockcnt = (blks_reqd_for_file * fs->blksz) / SECTOR_SIZE;
+
+ temp_ptr = zalloc(fs->blksz);
+ if (!temp_ptr)
+ goto fail;
+ ibmap_idx = inodeno / ext4fs_root->sblock.inodes_per_group;
+ inodeno--;
+ itable_blkno = __le32_to_cpu(fs->gd[ibmap_idx].inode_table_id) +
+ (inodeno % __le32_to_cpu(sblock->inodes_per_group)) /
+ inodes_per_block;
+ blkoff = (inodeno % inodes_per_block) * fs->inodesz;
+ ext4fs_devread(itable_blkno * fs->sect_perblk, 0, fs->blksz, temp_ptr);
+ if (ext4fs_log_journal(temp_ptr, itable_blkno))
+ goto fail;
+
+ memcpy(temp_ptr + blkoff, inode_buffer, fs->inodesz);
+ if (ext4fs_put_metadata(temp_ptr, itable_blkno))
+ goto fail;
+ /* copy the file content into data blocks */
+ if (ext4fs_write_file(file_inode, 0, sizebytes, (char *)buffer) == -1) {
+ printf("Error in copying content\n");
+ goto fail;
+ }
+ ibmap_idx = parent_inodeno / ext4fs_root->sblock.inodes_per_group;
+ parent_inodeno--;
+ parent_itable_blkno = __le32_to_cpu(fs->gd[ibmap_idx].inode_table_id) +
+ (parent_inodeno %
+ __le32_to_cpu(sblock->inodes_per_group)) / inodes_per_block;
+ blkoff = (parent_inodeno % inodes_per_block) * fs->inodesz;
+ if (parent_itable_blkno != itable_blkno) {
+ memset(temp_ptr, '\0', fs->blksz);
+ ext4fs_devread(parent_itable_blkno * fs->sect_perblk,
+ 0, fs->blksz, temp_ptr);
+ if (ext4fs_log_journal(temp_ptr, parent_itable_blkno))
+ goto fail;
+
+ memcpy(temp_ptr + blkoff, g_parent_inode,
+ sizeof(struct ext2_inode));
+ if (ext4fs_put_metadata(temp_ptr, parent_itable_blkno))
+ goto fail;
+ free(temp_ptr);
+ } else {
+ /*
+ * If parent and child fall in same inode table block
+ * both should be kept in 1 buffer
+ */
+ memcpy(temp_ptr + blkoff, g_parent_inode,
+ sizeof(struct ext2_inode));
+ gd_index--;
+ if (ext4fs_put_metadata(temp_ptr, itable_blkno))
+ goto fail;
+ free(temp_ptr);
+ }
+ ext4fs_update();
+ ext4fs_deinit();
+
+ fs->first_pass_bbmap = 0;
+ fs->curr_blkno = 0;
+ fs->first_pass_ibmap = 0;
+ fs->curr_inode_no = 0;
+ free(inode_buffer);
+ free(g_parent_inode);
+ g_parent_inode = NULL;
+
+ return 0;
+fail:
+ ext4fs_deinit();
+ free(inode_buffer);
+ free(g_parent_inode);
+ g_parent_inode = NULL;
+
+ return -1;
+}
+#endif
/*
* Convert a string to lowercase.
*/
-static void downcase (char *str)
+static void downcase(char *str)
{
while (*str != '\0') {
TOLOWER(*str);
cur_part_info.start + block, nr_blocks, buf);
}
-int fat_register_device (block_dev_desc_t * dev_desc, int part_no)
+int fat_register_device(block_dev_desc_t * dev_desc, int part_no)
{
ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz);
* Get the first occurence of a directory delimiter ('/' or '\') in a string.
* Return index into string if found, -1 otherwise.
*/
-static int dirdelim (char *str)
+static int dirdelim(char *str)
{
char *start = str;
/*
* Extract zero terminated short name from a directory entry.
*/
-static void get_name (dir_entry *dirent, char *s_name)
+static void get_name(dir_entry *dirent, char *s_name)
{
char *ptr;
* Get the entry at index 'entry' in a FAT (12/16/32) table.
* On failure 0x00 is returned.
*/
-static __u32 get_fatent (fsdata *mydata, __u32 entry)
+static __u32 get_fatent(fsdata *mydata, __u32 entry)
{
__u32 bufnum;
__u32 off16, offset;
__u32 fatlength = mydata->fatlength;
__u32 startblock = bufnum * FATBUFBLOCKS;
- if (getsize > fatlength)
- getsize = fatlength;
+ if (startblock + getsize > fatlength)
+ getsize = fatlength - startblock;
- fatlength *= mydata->sect_size; /* We want it in bytes now */
startblock += mydata->fat_sect; /* Offset from start of disk */
if (disk_read(startblock, getsize, bufptr) < 0) {
* Return 0 on success, -1 otherwise.
*/
static int
-get_cluster (fsdata *mydata, __u32 clustnum, __u8 *buffer,
- unsigned long size)
+get_cluster(fsdata *mydata, __u32 clustnum, __u8 *buffer, unsigned long size)
{
__u32 idx = 0;
__u32 startsect;
- __u32 nr_sect;
int ret;
if (clustnum > 0) {
debug("gc - clustnum: %d, startsect: %d\n", clustnum, startsect);
- nr_sect = size / mydata->sect_size;
- ret = disk_read(startsect, nr_sect, buffer);
- if (ret != nr_sect) {
- debug("Error reading data (got %d)\n", ret);
- return -1;
- }
- if (size % mydata->sect_size) {
+ if ((unsigned long)buffer & (ARCH_DMA_MINALIGN - 1)) {
ALLOC_CACHE_ALIGN_BUFFER(__u8, tmpbuf, mydata->sect_size);
+ printf("FAT: Misaligned buffer address (%p)\n", buffer);
+
+ while (size >= mydata->sect_size) {
+ ret = disk_read(startsect++, 1, tmpbuf);
+ if (ret != 1) {
+ debug("Error reading data (got %d)\n", ret);
+ return -1;
+ }
+
+ memcpy(buffer, tmpbuf, mydata->sect_size);
+ buffer += mydata->sect_size;
+ size -= mydata->sect_size;
+ }
+ } else {
idx = size / mydata->sect_size;
- ret = disk_read(startsect + idx, 1, tmpbuf);
+ ret = disk_read(startsect, idx, buffer);
+ if (ret != idx) {
+ debug("Error reading data (got %d)\n", ret);
+ return -1;
+ }
+ startsect += idx;
+ idx *= mydata->sect_size;
+ buffer += idx;
+ size -= idx;
+ }
+ if (size) {
+ ALLOC_CACHE_ALIGN_BUFFER(__u8, tmpbuf, mydata->sect_size);
+
+ ret = disk_read(startsect, 1, tmpbuf);
if (ret != 1) {
debug("Error reading data (got %d)\n", ret);
return -1;
}
- buffer += idx * mydata->sect_size;
- memcpy(buffer, tmpbuf, size % mydata->sect_size);
- return 0;
+ memcpy(buffer, tmpbuf, size);
}
return 0;
* Return the number of bytes read or -1 on fatal errors.
*/
static long
-get_contents (fsdata *mydata, dir_entry *dentptr, __u8 *buffer,
- unsigned long maxsize)
+get_contents(fsdata *mydata, dir_entry *dentptr, __u8 *buffer,
+ unsigned long maxsize)
{
unsigned long filesize = FAT2CPU32(dentptr->size), gotsize = 0;
unsigned int bytesperclust = mydata->clust_size * mydata->sect_size;
actsize += bytesperclust;
}
- /* actsize >= file size */
- actsize -= bytesperclust;
-
- /* get remaining clusters */
- if (get_cluster(mydata, curclust, buffer, (int)actsize) != 0) {
- printf("Error reading cluster\n");
- return -1;
- }
-
/* get remaining bytes */
- gotsize += (int)actsize;
- filesize -= actsize;
- buffer += actsize;
actsize = filesize;
- if (get_cluster(mydata, endclust, buffer, (int)actsize) != 0) {
+ if (get_cluster(mydata, curclust, buffer, (int)actsize) != 0) {
printf("Error reading cluster\n");
return -1;
}
* starting at l_name[*idx].
* Return 1 if terminator (zero byte) is found, 0 otherwise.
*/
-static int slot2str (dir_slot *slotptr, char *l_name, int *idx)
+static int slot2str(dir_slot *slotptr, char *l_name, int *idx)
{
int j;
__aligned(ARCH_DMA_MINALIGN);
static int
-get_vfatname (fsdata *mydata, int curclust, __u8 *cluster,
- dir_entry *retdent, char *l_name)
+get_vfatname(fsdata *mydata, int curclust, __u8 *cluster,
+ dir_entry *retdent, char *l_name)
{
dir_entry *realdent;
dir_slot *slotptr = (dir_slot *)retdent;
}
/* Calculate short name checksum */
-static __u8 mkcksum (const char *str)
+static __u8 mkcksum(const char *str)
{
int i;
__u8 get_dentfromdir_block[MAX_CLUSTSIZE]
__aligned(ARCH_DMA_MINALIGN);
-static dir_entry *get_dentfromdir (fsdata *mydata, int startsect,
- char *filename, dir_entry *retdent,
- int dols)
+static dir_entry *get_dentfromdir(fsdata *mydata, int startsect,
+ char *filename, dir_entry *retdent,
+ int dols)
{
__u16 prevcksum = 0xffff;
__u32 curclust = START(retdent);
* Read boot sector and volume info from a FAT filesystem
*/
static int
-read_bootsectandvi (boot_sector *bs, volume_info *volinfo, int *fatsize)
+read_bootsectandvi(boot_sector *bs, volume_info *volinfo, int *fatsize)
{
__u8 *block;
volume_info *vistart;
return -1;
}
- if (disk_read (0, 1, block) < 0) {
+ if (disk_read(0, 1, block) < 0) {
debug("Error: reading block\n");
goto fail;
}
__aligned(ARCH_DMA_MINALIGN);
long
-do_fat_read (const char *filename, void *buffer, unsigned long maxsize,
- int dols)
+do_fat_read(const char *filename, void *buffer, unsigned long maxsize, int dols)
{
char fnamecopy[2048];
boot_sector bs;
volume_info volinfo;
fsdata datablock;
fsdata *mydata = &datablock;
- dir_entry *dentptr;
+ dir_entry *dentptr = NULL;
__u16 prevcksum = 0xffff;
char *subname = "";
__u32 cursect;
while (1) {
int i;
- debug("FAT read sect=%d, clust_size=%d, DIRENTSPERBLOCK=%zd\n",
- cursect, mydata->clust_size, DIRENTSPERBLOCK);
+ if (j == 0) {
+ debug("FAT read sect=%d, clust_size=%d, DIRENTSPERBLOCK=%zd\n",
+ cursect, mydata->clust_size, DIRENTSPERBLOCK);
- if (disk_read(cursect,
- (mydata->fatsize == 32) ?
- (mydata->clust_size) :
- PREFETCH_BLOCKS,
- do_fat_read_block) < 0) {
- debug("Error: reading rootdir block\n");
- goto exit;
- }
+ if (disk_read(cursect,
+ (mydata->fatsize == 32) ?
+ (mydata->clust_size) :
+ PREFETCH_BLOCKS,
+ do_fat_read_block) < 0) {
+ debug("Error: reading rootdir block\n");
+ goto exit;
+ }
- dentptr = (dir_entry *) do_fat_read_block;
+ dentptr = (dir_entry *) do_fat_read_block;
+ }
for (i = 0; i < DIRENTSPERBLOCK; i++) {
char s_name[14], l_name[VFAT_MAXLEN_BYTES];
* completely processed.
*/
++j;
- int fat32_end = 0;
- if ((mydata->fatsize == 32) && (j == mydata->clust_size)) {
- int nxtsect = 0;
- int nxt_clust = 0;
+ int rootdir_end = 0;
+ if (mydata->fatsize == 32) {
+ if (j == mydata->clust_size) {
+ int nxtsect = 0;
+ int nxt_clust = 0;
- nxt_clust = get_fatent(mydata, root_cluster);
- fat32_end = CHECK_CLUST(nxt_clust, 32);
+ nxt_clust = get_fatent(mydata, root_cluster);
+ rootdir_end = CHECK_CLUST(nxt_clust, 32);
- nxtsect = mydata->data_begin +
- (nxt_clust * mydata->clust_size);
+ nxtsect = mydata->data_begin +
+ (nxt_clust * mydata->clust_size);
- root_cluster = nxt_clust;
+ root_cluster = nxt_clust;
- cursect = nxtsect;
- j = 0;
+ cursect = nxtsect;
+ j = 0;
+ }
} else {
- cursect++;
+ if (j == PREFETCH_BLOCKS)
+ j = 0;
+
+ rootdir_end = (++cursect - mydata->rootdir_sect >=
+ rootdir_size);
}
/* If end of rootdir reached */
- if ((mydata->fatsize == 32 && fat32_end) ||
- (mydata->fatsize != 32 && j == rootdir_size)) {
+ if (rootdir_end) {
if (dols == LS_ROOT) {
printf("\n%d file(s), %d dir(s)\n\n",
files, dirs);
goto exit;
}
- if (idx >= 0) {
- if (!(dentptr->attr & ATTR_DIR))
- goto exit;
+ if (isdir && !(dentptr->attr & ATTR_DIR))
+ goto exit;
+
+ if (idx >= 0)
subname = nextname;
- }
}
ret = get_contents(mydata, dentptr, buffer, maxsize);
return ret;
}
-int file_fat_detectfs (void)
+int file_fat_detectfs(void)
{
boot_sector bs;
volume_info volinfo;
return 0;
}
-int file_fat_ls (const char *dir)
+int file_fat_ls(const char *dir)
{
return do_fat_read(dir, NULL, 0, LS_YES);
}
-long file_fat_read (const char *filename, void *buffer, unsigned long maxsize)
+long file_fat_read(const char *filename, void *buffer, unsigned long maxsize)
{
printf("reading %s\n", filename);
return do_fat_read(filename, buffer, maxsize, LS_NO);
static int gzip_decompress(const unsigned char *in, size_t in_len,
unsigned char *out, size_t *out_len)
{
- unsigned long len = in_len;
- return zunzip(out, *out_len, (unsigned char *)in, &len, 0, 0);
+ return zunzip(out, *out_len, (unsigned char *)in,
+ (unsigned long *)out_len, 0, 0);
}
/* Fake description object for the "none" compressor */
struct file *file;
struct dentry *dentry;
struct inode *dir;
+ int ret = 0;
file = kzalloc(sizeof(struct file), 0);
dentry = kzalloc(sizeof(struct dentry), 0);
if ((strncmp(dirname, (char *)dent->name, nm.len) == 0) &&
(strlen(dirname) == nm.len)) {
*inum = le64_to_cpu(dent->inum);
- return 1;
+ ret = 1;
+ goto out_free;
}
/* Switch to the next entry */
}
out:
- if (err != -ENOENT) {
+ if (err != -ENOENT)
ubifs_err("cannot find next direntry, error %d", err);
- return err;
- }
+out_free:
if (file->private_data)
kfree(file->private_data);
if (file)
if (dir)
free(dir);
- return 0;
+ return ret;
}
static unsigned long ubifs_findfile(struct super_block *sb, char *filename)
COBJS-$(CONFIG_YAFFS2) := \
yaffs_allocator.o yaffs_attribs.o yaffs_bitmap.o yaffs_uboot_glue.o\
yaffs_checkptrw.o yaffs_ecc.o yaffs_error.o \
- yaffsfs.o yaffs_guts.o yaffs_hweight.o yaffs_nameval.o yaffs_nand.o\
+ yaffsfs.o yaffs_guts.o yaffs_nameval.o yaffs_nand.o\
yaffs_packedtags1.o yaffs_packedtags2.o yaffs_qsort.o \
yaffs_summary.o yaffs_tagscompat.o yaffs_verify.o yaffs_yaffs1.o \
yaffs_yaffs2.o yaffs_mtdif.o yaffs_mtdif2.o
+++ /dev/null
-/* Dummy header for u-boot */
+++ /dev/null
-/* Dummy header for u-boot */
+++ /dev/null
-#include <linux/stddef.h>
-#include <linux/string.h>
-#include <linux/stat.h>
-#include <common.h>
+++ /dev/null
-/*
- * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
- *
- * Copyright (C) 2002-2011 Aleph One Ltd.
- * for Toby Churchill Ltd and Brightstar Engineering
- *
- * Created by Charles Manning <charles@aleph1.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-/* These functions have been renamed to hweightxx to match the
- * equivaqlent functions in the Linux kernel.
- */
-
-#include "yaffs_hweight.h"
-
-static const char yaffs_count_bits_table[256] = {
- 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4,
- 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5,
- 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5,
- 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
- 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5,
- 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
- 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
- 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7,
- 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5,
- 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
- 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
- 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7,
- 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
- 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7,
- 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7,
- 4, 5, 5, 6, 5, 6, 6, 7, 5, 6, 6, 7, 6, 7, 7, 8
-};
-
-int yaffs_hweight8(u8 x)
-{
- int ret_val;
- ret_val = yaffs_count_bits_table[x];
- return ret_val;
-}
-
-int yaffs_hweight32(u32 x)
-{
- return yaffs_hweight8(x & 0xff) +
- yaffs_hweight8((x >> 8) & 0xff) +
- yaffs_hweight8((x >> 16) & 0xff) +
- yaffs_hweight8((x >> 24) & 0xff);
-}
+++ /dev/null
-/*
- * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
- *
- * Copyright (C) 2002-2011 Aleph One Ltd.
- * for Toby Churchill Ltd and Brightstar Engineering
- *
- * Created by Charles Manning <charles@aleph1.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License version 2.1 as
- * published by the Free Software Foundation.
- *
- * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
- */
-
-#ifndef __YAFFS_HWEIGHT_H__
-#define __YAFFS_HWEIGHT_H__
-
-#include "yportenv.h"
-
-int yaffs_hweight8(u8 x);
-int yaffs_hweight32(u32 x);
-
-#endif
#include "yaffs_trace.h"
#include "yaffs_packedtags2.h"
-#include "string.h"
#define yaffs_dev_to_mtd(dev) ((struct mtd_info *)((dev)->driver_context))
#define yaffs_dev_to_lc(dev) ((struct yaffs_linux_context *)((dev)->os_context))
struct mtd_oob_ops ops;
int retval = 0;
-
loff_t addr;
- u8 local_spare[128];
struct yaffs_packed_tags2 pt;
#include "yportenv.h"
#include "yaffs_trace.h"
-#include "string.h"
-
#define YAFFSFS_MAX_SYMLINK_DEREFERENCES 5
#ifndef NULL
#ifndef __YDIRECTENV_H__
#define __YDIRECTENV_H__
-#include "stdlib.h"
-#include "stdio.h"
-#include "string.h"
+#include <common.h>
+#include <malloc.h>
+#include <linux/compat.h>
+
#include "yaffs_osglue.h"
-#include "yaffs_hweight.h"
void yaffs_bug_fn(const char *file_name, int line_no);
-#define BUG() do { yaffs_bug_fn(__FILE__, __LINE__); } while (0)
#define YCHAR char
#define yaffs_strncmp(a, b, c) strncmp(a, b, c)
#endif
-#define hweight8(x) yaffs_hweight8(x)
-#define hweight32(x) yaffs_hweight32(x)
void yaffs_qsort(void *aa, size_t n, size_t es,
int (*cmp)(const void *, const void *));
#define inline __inline__
#endif
-#define kmalloc(x, flags) yaffsfs_malloc(x)
-#define kfree(x) yaffsfs_free(x)
-#define vmalloc(x) yaffsfs_malloc(x)
-#define vfree(x) yaffsfs_free(x)
-
#define cond_resched() do {} while (0)
#define yaffs_trace(msk, fmt, ...) do { \
#ifndef __YPORTENV_H__
#define __YPORTENV_H__
+#include <linux/types.h>
/* Definition of types */
#ifdef CONFIG_YAFFS_DEFINES_TYPES
/*
* Configuation settings for the Freescale MCF5373 FireEngine board.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
-#ifdef NANDFLASH_SIZE
+#ifdef CONFIG_NANDFLASH_SIZE
# define CONFIG_CMD_NAND
#endif
# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
#endif
-#ifdef NANDFLASH_SIZE
+#ifdef CONFIG_NANDFLASH_SIZE
# define CONFIG_SYS_MAX_NAND_DEVICE 1
# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
# define CONFIG_SYS_NAND_SIZE 1
#define CONFIG_SYS_CS1_MASK 0x001f0001
#define CONFIG_SYS_CS1_CTRL 0x002A3780
-#ifdef NANDFLASH_SIZE
+#ifdef CONFIG_NANDFLASH_SIZE
#define CONFIG_SYS_CS2_BASE 0x20000000
-#define CONFIG_SYS_CS2_MASK ((NANDFLASH_SIZE << 20) | 1)
+#define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1)
#define CONFIG_SYS_CS2_CTRL 0x00001f60
#endif
#define CONFIG_MISC_INIT_R
+/* new uImage format support */
+#define CONFIG_FIT 1
+#define CONFIG_FIT_VERBOSE 1
+
+#define CONFIG_MMC 1
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ESDHC_USE_PIO
+
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
/*
* On-board devices
*
#define CONFIG_SYS_I2C_OFFSET 0x3000
#define CONFIG_SYS_I2C2_OFFSET 0x3100
+/*
+ * SPI on header J8
+ *
+ * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch)
+ * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins.
+ */
+#ifdef CONFIG_MPC8XXX_SPI
+#define CONFIG_CMD_SPI
+#define CONFIG_USE_SPIFLASH
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_CMD_SF
+#endif
/*
* Board info - revision and where boot from
+++ /dev/null
-/*
- * (C) Copyright 2005-2008
- * Samsung Electronics,
- * Kyungmin Park <kyungmin.park@samsung.com>
- *
- * Configuration settings for the 2420 Samsung Apollon board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
-#define CONFIG_OMAP 1 /* in a TI OMAP core */
-#define CONFIG_OMAP2420 1 /* which is in a 2420 */
-#define CONFIG_OMAP2420_APOLLON 1
-#define CONFIG_APOLLON 1
-#define CONFIG_APOLLON_PLUS 1 /* If you have apollon plus 1.x */
-
-#define CONFIG_ONENAND_U_BOOT y
-
-/* Clock config to target*/
-#define PRCM_CONFIG_I 1
-/* #define PRCM_CONFIG_II 1 */
-
-/* Boot method */
-/* uncomment if you use NOR boot */
-/* #define CONFIG_SYS_NOR_BOOT 1 */
-
-/* uncomment if you use NOR on CS3 */
-/* #define CONFIG_SYS_USE_NOR 1 */
-
-#ifdef CONFIG_SYS_NOR_BOOT
-#undef CONFIG_SYS_USE_NOR
-#define CONFIG_SYS_USE_NOR 1
-#endif
-
-/* uncommnet if you want to use UBI */
-#define CONFIG_SYS_USE_UBI
-
-#include <asm/arch/omap2420.h> /* get chip and board defs */
-
-#define V_SCLK 12000000
-
-/* input clock of PLL */
-/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */
-#define CONFIG_SYS_CLK_FREQ V_SCLK
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-#define CONFIG_REVISION_TAG 1
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_ENV_SIZE SZ_128K /* Total Size of Environment Sector */
-#define CONFIG_ENV_SIZE_FLEX SZ_256K
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_1M)
-
-/*
- * Hardware drivers
- */
-
-/*
- * SMC91c96 Etherent
- */
-#define CONFIG_LAN91C96
-#define CONFIG_LAN91C96_BASE (APOLLON_CS1_BASE+0x300)
-#define CONFIG_LAN91C96_EXT_PHY
-
-/*
- * NS16550 Configuration
- */
-#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK /* 3MHz (1.5MHz*2) */
-#define CONFIG_SYS_NS16550_COM1 OMAP2420_UART1
-
-/*
- * select serial console configuration
- */
-#define CONFIG_SERIAL1 1 /* UART1 on H4 */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_ONENAND
-
-#ifdef CONFIG_SYS_USE_UBI
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_UBI
-#define CONFIG_RBTREE
-#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
-#define CONFIG_MTD_PARTITIONS
-#endif
-
-#undef CONFIG_CMD_SOURCE
-
-#ifndef CONFIG_SYS_USE_NOR
-# undef CONFIG_CMD_FLASH
-# undef CONFIG_CMD_IMLS
-#endif
-
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
-
-#define CONFIG_BOOTDELAY 1
-
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_IPADDR 192.168.116.25
-#define CONFIG_SERVERIP 192.168.116.1
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_ETHADDR 00:0E:99:00:24:20
-
-#ifdef CONFIG_APOLLON_PLUS
-#define CONFIG_SYS_MEM "mem=64M"
-#else
-#define CONFIG_SYS_MEM "mem=128"
-#endif
-
-#ifdef CONFIG_SYS_USE_UBI
-#define CONFIG_SYS_UBI "ubi.mtd=4"
-#else
-#define CONFIG_SYS_UBI ""
-#endif
-
-#define CONFIG_BOOTARGS "root=/dev/nfs rw " CONFIG_SYS_MEM \
- " console=ttyS0,115200n8" \
- " ip=192.168.116.25:192.168.116.1:192.168.116.1:255.255.255.0:" \
- "apollon:eth0:off nfsroot=/tftpboot/nfsroot profile=2 " \
- CONFIG_SYS_UBI
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "Image=tftp 0x80008000 Image; go 0x80008000\0" \
- "zImage=tftp 0x80180000 zImage; go 0x80180000\0" \
- "uImage=tftp 0x80180000 uImage; bootm 0x80180000\0" \
- "uboot=tftp 0x80008000 u-boot.bin; go 0x80008000\0" \
- "xloader=tftp 0x80180000 x-load.bin; " \
- " cp.w 0x80180000 0x00000400 0x1000; go 0x00000400\0" \
- "syncmode50=mw.w 0x1e442 0xc0c4; mw 0x6800a060 0xe30d1201\0" \
- "syncmode=mw.w 0x1e442 0xe0f4; mw 0x6800a060 0xe30d1201\0" \
- "norboot=cp32 0x18040000 0x80008000 0x200000; go 0x80008000\0" \
- "oneboot=onenand read 0x80008000 0x40000 0x200000; go 0x80008000\0" \
- "onesyncboot=run syncmode oneboot\0" \
- "updateb=tftp 0x80180000 u-boot-onenand.bin; " \
- " onenand erase 0x0 0x20000; onenand write 0x80180000 0x0 0x20000\0" \
- "ubi=setenv bootargs ${bootargs} ubi.mtd=4 ${mtdparts}; run uImage\0" \
- "bootcmd=run uboot\0"
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "Apollon # "
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-/* memtest works on */
-#define CONFIG_SYS_MEMTEST_START (OMAP2420_SDRC_CS0)
-#define CONFIG_SYS_MEMTEST_END (OMAP2420_SDRC_CS0+SZ_31M)
-
-/* default load address */
-#define CONFIG_SYS_LOAD_ADDR (OMAP2420_SDRC_CS0)
-
-/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2)
- * or by 32KHz clk, or from external sig. This rate is divided by a local
- * divisor.
- */
-#define CONFIG_SYS_TIMERBASE OMAP2420_GPT2
-#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */
-#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1 /* CS1 may or may not be populated */
-#define PHYS_SDRAM_1 OMAP2420_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE SZ_128M
-#define PHYS_SDRAM_2 OMAP2420_SDRC_CS1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#ifdef CONFIG_SYS_USE_NOR
-/* OneNAND boot, NOR has CS3, But NOR has CS0 when NOR boot */
-# define CONFIG_SYS_FLASH_BASE 0x18000000
-# define CONFIG_SYS_MAX_FLASH_BANKS 1
-# define CONFIG_SYS_MAX_FLASH_SECT 1024
-/*-----------------------------------------------------------------------
- * CFI FLASH driver setup
- */
-/* Flash memory is CFI compliant */
-# define CONFIG_SYS_FLASH_CFI 1
-# define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
-/* Use buffered writes (~10x faster) */
-/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 */
-/* Use h/w sector protection*/
-# define CONFIG_SYS_FLASH_PROTECTION 1
-
-#else /* !CONFIG_SYS_USE_NOR */
-# define CONFIG_SYS_NO_FLASH 1
-#endif /* CONFIG_SYS_USE_NOR */
-
-/* OneNAND boot, OneNAND has CS0, NOR boot ONeNAND has CS2 */
-#define CONFIG_SYS_ONENAND_BASE 0x00000000
-#define CONFIG_SYS_MONITOR_LEN SZ_256K /* U-Boot image size */
-#define CONFIG_ENV_IS_IN_ONENAND 1
-#define CONFIG_ENV_ADDR 0x00020000
-#define CONFIG_ENV_ADDR_FLEX 0x00040000
-
-#ifdef CONFIG_SYS_USE_UBI
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT "onenand0=onenand"
-#define MTDPARTS_DEFAULT "mtdparts=onenand:128k(bootloader)," \
- "128k(params)," \
- "2m(kernel)," \
- "16m(rootfs)," \
- "32m(fs)," \
- "-(ubifs)"
-#endif
-
-#define PHYS_SRAM 0x4020F800
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM
-
-#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * Copyright (C) 2012 Andreas Bießmann <andreas.devel@googlemail.com>
+ *
+ * Configuration settings for the AVR32 Network Gateway
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/hardware.h>
+
+#define CONFIG_AVR32
+#define CONFIG_AT32AP
+#define CONFIG_AT32AP7000
+#define CONFIG_ATNGW100MKII
+
+/*
+ * Timer clock frequency. We're using the CPU-internal COUNT register
+ * for this, so this is equivalent to the CPU core clock frequency
+ */
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
+ * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
+ * and the PBA bus to run at 1/4 the PLL frequency.
+ */
+#define CONFIG_PLL
+#define CONFIG_SYS_POWER_MANAGER
+#define CONFIG_SYS_OSC0_HZ 20000000
+#define CONFIG_SYS_PLL0_DIV 1
+#define CONFIG_SYS_PLL0_MUL 7
+#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
+/*
+ * Set the CPU running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
+ */
+#define CONFIG_SYS_CLKDIV_CPU 0
+/*
+ * Set the HSB running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
+ */
+#define CONFIG_SYS_CLKDIV_HSB 1
+/*
+ * Set the PBA running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
+ */
+#define CONFIG_SYS_CLKDIV_PBA 2
+/*
+ * Set the PBB running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
+ */
+#define CONFIG_SYS_CLKDIV_PBB 1
+
+/* Reserve VM regions for NOR flash, NAND flash and SDRAM */
+#define CONFIG_SYS_NR_VM_REGIONS 3
+
+/*
+ * The PLLOPT register controls the PLL like this:
+ * icp = PLLOPT<2>
+ * ivco = PLLOPT<1:0>
+ *
+ * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
+ */
+#define CONFIG_SYS_PLL0_OPT 0x04
+
+#define CONFIG_USART_BASE ATMEL_BASE_USART1
+#define CONFIG_USART_ID 1
+
+/* User serviceable stuff */
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_STACKSIZE (2048)
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_BOOTARGS \
+ "root=mtd:main rootfstype=jffs2"
+#define CONFIG_BOOTCOMMAND \
+ "fsload 0x10400000 /uImage; bootm"
+
+/*
+ * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
+ * data on the serial line may interrupt the boot sequence.
+ */
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_AUTOBOOT
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT \
+ "Press SPACE to abort autoboot in %d seconds\n", bootdelay
+#define CONFIG_AUTOBOOT_DELAY_STR "d"
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+/*
+ * After booting the board for the first time, new ethernet addresses
+ * should be generated and assigned to the environment variables
+ * "ethaddr" and "eth1addr". This is normally done during production.
+ */
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+#define CONFIG_NET_MULTI
+
+/*
+ * BOOTP/DHCP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_MII
+
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
+#define CONFIG_ATMEL_USART
+#define CONFIG_MACB
+#define CONFIG_PORTMUX_PIO
+#define CONFIG_SYS_NR_PIOS 5
+#define CONFIG_SYS_HSDRAMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#define CONFIG_GENERIC_MMC
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT 1
+#define CONFIG_ATMEL_SPI
+
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_ATMEL
+
+#define CONFIG_SYS_DCACHE_LINESZ 32
+#define CONFIG_SYS_ICACHE_LINESZ 32
+
+#define CONFIG_NR_DRAM_BANKS 1
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_PROTECTION
+
+#define CONFIG_SYS_FLASH_BASE 0x00000000
+#define CONFIG_SYS_FLASH_SIZE 0x800000
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 135
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
+#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
+#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SIZE 65536
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
+
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN (256*1024)
+#define CONFIG_SYS_DMA_ALLOC_LEN (16384)
+
+/* Allow 4MB for the kernel run-time image */
+#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
+#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
+
+/* Other configuration settings that shouldn't have to change all that often */
+#define CONFIG_SYS_PROMPT "U-Boot> "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000)
+
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+
+#endif /* __CONFIG_H */
* NAND FLASH driver setup
*/
#define CONFIG_NAND_MXC
-#define CONFIG_NAND_MXC_V1_1
#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR)
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR)
#endif
/* timer */
-#ifdef XILINX_TIMER_BASEADDR
-# if (XILINX_TIMER_IRQ != -1)
-# define CONFIG_SYS_TIMER_0 1
+#if defined(XILINX_TIMER_BASEADDR) && defined(XILINX_TIMER_IRQ)
# define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR
# define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ
-# define FREQUENCE XILINX_CLOCK_FREQ
-# define CONFIG_SYS_TIMER_0_PRELOAD ( FREQUENCE/1000 )
-# endif
-#elif XILINX_CLOCK_FREQ
-# define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ
-#else
-# error BAD CLOCK FREQ
#endif
+
/* FSL */
/* #define CONFIG_SYS_FSL_2 */
/* #define FSL_INTR_2 1 */
* NAND FLASH driver setup
*/
#define CONFIG_NAND_MXC
-#define CONFIG_NAND_MXC_V1_1
#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR)
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR)
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "qemu-mips # " /* Monitor Command Prompt */
+/* Monitor Command Prompt */
+#if defined(CONFIG_SYS_LITTLE_ENDIAN)
+#define CONFIG_SYS_PROMPT "qemu-mipsel # "
+#else
+#define CONFIG_SYS_PROMPT "qemu-mips # "
+#endif
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
#define __CONFIG_QI_LB60_H
#define CONFIG_MIPS32 /* MIPS32 CPU core */
+#define CONFIG_SYS_LITTLE_ENDIAN
#define CONFIG_JZSOC /* Jz SoC */
#define CONFIG_JZ4740 /* Jz4740 SoC */
#define CONFIG_NAND_JZ4740
#define CONFIG_MMC
#define CONFIG_S5P_SDHCI
#define CONFIG_SDHCI
+#define CONFIG_MMC_SDMA
/* PWM */
#define CONFIG_PWM
#undef CONFIG_CMD_ONENAND
#undef CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_MMC
+#define CONFIG_CMD_DFU
+
+/* FAT */
+#define CONFIG_CMD_FAT
+#define CONFIG_FAT_WRITE
+
+/* USB Composite download gadget - g_dnl */
+#define CONFIG_USBDOWNLOAD_GADGET
+#define CONFIG_DFU_FUNCTION
+#define CONFIG_DFU_MMC
+
+/* USB Samsung's IDs */
+#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
+#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
+#define CONFIG_G_DNL_MANUFACTURER "Samsung"
#define CONFIG_BOOTDELAY 1
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_BOOTBLOCK "10"
#define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}"
+#define CONFIG_DFU_ALT \
+ "dfu_alt_info=" \
+ "u-boot mmc 80 400;" \
+ "uImage fat 0 2\0" \
+
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
"mmcdev=0\0" \
"mmcbootpart=2\0" \
"mmcrootpart=3\0" \
- "opts=always_resume=1"
+ "opts=always_resume=1\0" \
+ CONFIG_DFU_ALT
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_CACHELINE_SIZE 32
-#include <asm/arch/gpio.h>
-/*
- * I2C Settings
- */
-#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_part1_get_nr(b, 7)
-#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_part1_get_nr(b, 6)
#define CONFIG_SOFT_I2C
#define CONFIG_SOFT_I2C_READ_REPEATED_START
+#define CONFIG_SYS_I2C_INIT_BOARD
#define CONFIG_SYS_I2C_SPEED 50000
#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_MAX_I2C_BUS 7
+#define CONFIG_SOFT_I2C_MULTI_BUS
+#define CONFIG_SYS_MAX_I2C_BUS 15
+
+#include <asm/arch/gpio.h>
+
+/* I2C PMIC */
+#define CONFIG_SOFT_I2C_I2C5_SCL exynos4_gpio_part1_get_nr(b, 7)
+#define CONFIG_SOFT_I2C_I2C5_SDA exynos4_gpio_part1_get_nr(b, 6)
+
+/* I2C FG */
+#define CONFIG_SOFT_I2C_I2C9_SCL exynos4_gpio_part2_get_nr(y4, 1)
+#define CONFIG_SOFT_I2C_I2C9_SDA exynos4_gpio_part2_get_nr(y4, 0)
+
+#define CONFIG_SOFT_I2C_GPIO_SCL get_multi_scl_pin()
+#define CONFIG_SOFT_I2C_GPIO_SDA get_multi_sda_pin()
+#define I2C_INIT multi_i2c_init()
#define CONFIG_PMIC
#define CONFIG_PMIC_I2C
#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_S3C_UDC_OTG
#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
/* LCD */
#define CONFIG_EXYNOS_FB
/* NAND */
#define CONFIG_NAND_MXC
-#define CONFIG_NAND_MXC_V1_1
#define CONFIG_MXC_NAND_REGS_BASE (0xBB000000)
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE (0xBB000000)
--- /dev/null
+/*
+ * dfu.h - DFU flashable area description
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ * authors: Andrzej Pietrasiewicz <andrzej.p@samsung.com>
+ * Lukasz Majewski <l.majewski@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __DFU_ENTITY_H_
+#define __DFU_ENTITY_H_
+
+#include <common.h>
+#include <linux/list.h>
+#include <mmc.h>
+
+enum dfu_device_type {
+ DFU_DEV_MMC = 1,
+ DFU_DEV_ONENAND,
+ DFU_DEV_NAND,
+};
+
+enum dfu_layout {
+ DFU_RAW_ADDR = 1,
+ DFU_FS_FAT,
+ DFU_FS_EXT2,
+ DFU_FS_EXT3,
+ DFU_FS_EXT4,
+};
+
+struct mmc_internal_data {
+ /* RAW programming */
+ unsigned int lba_start;
+ unsigned int lba_size;
+ unsigned int lba_blk_size;
+
+ /* FAT/EXT */
+ unsigned int dev;
+ unsigned int part;
+};
+
+static inline unsigned int get_mmc_blk_size(int dev)
+{
+ return find_mmc_device(dev)->read_bl_len;
+}
+
+#define DFU_NAME_SIZE 32
+#define DFU_CMD_BUF_SIZE 128
+#define DFU_DATA_BUF_SIZE (1024*1024*4) /* 4 MiB */
+
+struct dfu_entity {
+ char name[DFU_NAME_SIZE];
+ int alt;
+ void *dev_private;
+ int dev_num;
+ enum dfu_device_type dev_type;
+ enum dfu_layout layout;
+
+ union {
+ struct mmc_internal_data mmc;
+ } data;
+
+ int (*read_medium)(struct dfu_entity *dfu, void *buf, long *len);
+ int (*write_medium)(struct dfu_entity *dfu, void *buf, long *len);
+
+ struct list_head list;
+};
+
+int dfu_config_entities(char *s, char *interface, int num);
+void dfu_free_entities(void);
+void dfu_show_entities(void);
+int dfu_get_alt_number(void);
+const char *dfu_get_dev_type(enum dfu_device_type t);
+const char *dfu_get_layout(enum dfu_layout l);
+struct dfu_entity *dfu_get_entity(int alt);
+char *dfu_extract_token(char** e, int *n);
+
+int dfu_read(struct dfu_entity *de, void *buf, int size, int blk_seq_num);
+int dfu_write(struct dfu_entity *de, void *buf, int size, int blk_seq_num);
+/* Device specific */
+#ifdef CONFIG_DFU_MMC
+extern int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *s);
+#else
+static inline int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *s)
+{
+ puts("MMC support not available!\n");
+ return -1;
+}
+#endif
+#endif /* __DFU_ENTITY_H_ */
/* [re]set to the default environment */
void set_default_env(const char *s);
+/* [re]set individual variables to their value in the default environment */
+int set_default_vars(int nvars, char * const vars[]);
+
/* Import from binary representation into hash table */
int env_import(const char *buf, int check);
+/*
+ * Check if variable "name" can be changed from oldval to newval,
+ * and if so, apply the changes (e.g. baudrate).
+ * When (flag & H_FORCE) is set, it does not print out any error
+ * message and forces overwriting of write-once variables.
+ */
+int env_check_apply(const char *name, const char *oldval,
+ const char *newval, int flag);
+
#endif /* DO_DEPS_ONLY */
#endif /* _ENVIRONMENT_H_ */
+++ /dev/null
-/*
- * GRUB -- GRand Unified Bootloader
- * Copyright (C) 2000, 2001 Free Software Foundation, Inc.
- *
- * (C) Copyright 2003 Sysgo Real-Time Solutions, AG <www.elinos.com>
- * Pavel Bartusek <pba@sysgo.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-/* An implementation for the Ext2FS filesystem ported from GRUB.
- * Some parts of this code (mainly the structures and defines) are
- * from the original ext2 fs code, as found in the linux kernel.
- */
-
-
-#define SECTOR_SIZE 0x200
-#define SECTOR_BITS 9
-
-/* Error codes */
-typedef enum
-{
- ERR_NONE = 0,
- ERR_BAD_FILENAME,
- ERR_BAD_FILETYPE,
- ERR_BAD_GZIP_DATA,
- ERR_BAD_GZIP_HEADER,
- ERR_BAD_PART_TABLE,
- ERR_BAD_VERSION,
- ERR_BELOW_1MB,
- ERR_BOOT_COMMAND,
- ERR_BOOT_FAILURE,
- ERR_BOOT_FEATURES,
- ERR_DEV_FORMAT,
- ERR_DEV_VALUES,
- ERR_EXEC_FORMAT,
- ERR_FILELENGTH,
- ERR_FILE_NOT_FOUND,
- ERR_FSYS_CORRUPT,
- ERR_FSYS_MOUNT,
- ERR_GEOM,
- ERR_NEED_LX_KERNEL,
- ERR_NEED_MB_KERNEL,
- ERR_NO_DISK,
- ERR_NO_PART,
- ERR_NUMBER_PARSING,
- ERR_OUTSIDE_PART,
- ERR_READ,
- ERR_SYMLINK_LOOP,
- ERR_UNRECOGNIZED,
- ERR_WONT_FIT,
- ERR_WRITE,
- ERR_BAD_ARGUMENT,
- ERR_UNALIGNED,
- ERR_PRIVILEGED,
- ERR_DEV_NEED_INIT,
- ERR_NO_DISK_SPACE,
- ERR_NUMBER_OVERFLOW,
-
- MAX_ERR_NUM
-} ext2fs_error_t;
-
-
-extern int ext2fs_set_blk_dev(block_dev_desc_t *rbdd, int part);
-extern int ext2fs_ls (const char *dirname);
-extern int ext2fs_open (const char *filename);
-extern int ext2fs_read (char *buf, unsigned len);
-extern int ext2fs_mount (unsigned part_length);
-extern int ext2fs_close(void);
--- /dev/null
+/*
+ * (C) Copyright 2011 - 2012 Samsung Electronics
+ * EXT4 filesystem implementation in Uboot by
+ * Uma Shankar <uma.shankar@samsung.com>
+ * Manjunatha C Achar <a.manjunatha@samsung.com>
+ *
+ * Ext4 Extent data structures are taken from original ext4 fs code
+ * as found in the linux kernel.
+ *
+ * Copyright (c) 2003-2006, Cluster File Systems, Inc, info@clusterfs.com
+ * Written by Alex Tomas <alex@clusterfs.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __EXT4__
+#define __EXT4__
+#include <ext_common.h>
+
+#define EXT4_EXTENTS_FL 0x00080000 /* Inode uses extents */
+#define EXT4_EXT_MAGIC 0xf30a
+#define EXT4_FEATURE_RO_COMPAT_GDT_CSUM 0x0010
+#define EXT4_FEATURE_INCOMPAT_EXTENTS 0x0040
+#define EXT4_INDIRECT_BLOCKS 12
+
+#define EXT4_BG_INODE_UNINIT 0x0001
+#define EXT4_BG_BLOCK_UNINIT 0x0002
+#define EXT4_BG_INODE_ZEROED 0x0004
+
+/*
+ * ext4_inode has i_block array (60 bytes total).
+ * The first 12 bytes store ext4_extent_header;
+ * the remainder stores an array of ext4_extent.
+ */
+
+/*
+ * This is the extent on-disk structure.
+ * It's used at the bottom of the tree.
+ */
+struct ext4_extent {
+ __le32 ee_block; /* first logical block extent covers */
+ __le16 ee_len; /* number of blocks covered by extent */
+ __le16 ee_start_hi; /* high 16 bits of physical block */
+ __le32 ee_start_lo; /* low 32 bits of physical block */
+};
+
+/*
+ * This is index on-disk structure.
+ * It's used at all the levels except the bottom.
+ */
+struct ext4_extent_idx {
+ __le32 ei_block; /* index covers logical blocks from 'block' */
+ __le32 ei_leaf_lo; /* pointer to the physical block of the next *
+ * level. leaf or next index could be there */
+ __le16 ei_leaf_hi; /* high 16 bits of physical block */
+ __u16 ei_unused;
+};
+
+/* Each block (leaves and indexes), even inode-stored has header. */
+struct ext4_extent_header {
+ __le16 eh_magic; /* probably will support different formats */
+ __le16 eh_entries; /* number of valid entries */
+ __le16 eh_max; /* capacity of store in entries */
+ __le16 eh_depth; /* has tree real underlying blocks? */
+ __le32 eh_generation; /* generation of the tree */
+};
+
+struct ext_filesystem {
+ /* Total Sector of partition */
+ uint64_t total_sect;
+ /* Block size of partition */
+ uint32_t blksz;
+ /* Inode size of partition */
+ uint32_t inodesz;
+ /* Sectors per Block */
+ uint32_t sect_perblk;
+ /* Group Descriptor Block Number */
+ uint32_t gdtable_blkno;
+ /* Total block groups of partition */
+ uint32_t no_blkgrp;
+ /* No of blocks required for bgdtable */
+ uint32_t no_blk_pergdt;
+ /* Superblock */
+ struct ext2_sblock *sb;
+ /* Block group descritpor table */
+ struct ext2_block_group *gd;
+ char *gdtable;
+
+ /* Block Bitmap Related */
+ unsigned char **blk_bmaps;
+ long int curr_blkno;
+ uint16_t first_pass_bbmap;
+
+ /* Inode Bitmap Related */
+ unsigned char **inode_bmaps;
+ int curr_inode_no;
+ uint16_t first_pass_ibmap;
+
+ /* Journal Related */
+
+ /* Block Device Descriptor */
+ block_dev_desc_t *dev_desc;
+};
+
+extern block_dev_desc_t *ext4_dev_desc;
+extern struct ext2_data *ext4fs_root;
+extern struct ext2fs_node *ext4fs_file;
+
+#if defined(CONFIG_CMD_EXT4_WRITE)
+extern struct ext2_inode *g_parent_inode;
+extern int gd_index;
+extern int gindex;
+
+int ext4fs_init(void);
+void ext4fs_deinit(void);
+int ext4fs_filename_check(char *filename);
+int ext4fs_write(const char *fname, unsigned char *buffer,
+ unsigned long sizebytes);
+#endif
+
+struct ext_filesystem *get_fs(void);
+int init_fs(block_dev_desc_t *dev_desc);
+void deinit_fs(block_dev_desc_t *dev_desc);
+int ext4fs_open(const char *filename);
+int ext4fs_read(char *buf, unsigned len);
+int ext4fs_mount(unsigned part_length);
+void ext4fs_close(void);
+int ext4fs_ls(const char *dirname);
+void ext4fs_free_node(struct ext2fs_node *node, struct ext2fs_node *currroot);
+int ext4fs_devread(int sector, int byte_offset, int byte_len, char *buf);
+int ext4fs_set_blk_dev(block_dev_desc_t *rbdd, int part);
+long int read_allocated_block(struct ext2_inode *inode, int fileblock);
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2011 - 2012 Samsung Electronics
+ * EXT4 filesystem implementation in Uboot by
+ * Uma Shankar <uma.shankar@samsung.com>
+ * Manjunatha C Achar <a.manjunatha@samsung.com>
+ *
+ * Data structures and headers for ext4 support have been taken from
+ * ext2 ls load support in Uboot
+ *
+ * (C) Copyright 2004
+ * esd gmbh <www.esd-electronics.com>
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * based on code from grub2 fs/ext2.c and fs/fshelp.c by
+ * GRUB -- GRand Unified Bootloader
+ * Copyright (C) 2003, 2004 Free Software Foundation, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __EXT_COMMON__
+#define __EXT_COMMON__
+#include <command.h>
+#define SECTOR_SIZE 0x200
+#define SECTOR_BITS 9
+
+/* Magic value used to identify an ext2 filesystem. */
+#define EXT2_MAGIC 0xEF53
+/* Amount of indirect blocks in an inode. */
+#define INDIRECT_BLOCKS 12
+/* Maximum lenght of a pathname. */
+#define EXT2_PATH_MAX 4096
+/* Maximum nesting of symlinks, used to prevent a loop. */
+#define EXT2_MAX_SYMLINKCNT 8
+
+/* Filetype used in directory entry. */
+#define FILETYPE_UNKNOWN 0
+#define FILETYPE_REG 1
+#define FILETYPE_DIRECTORY 2
+#define FILETYPE_SYMLINK 7
+
+/* Filetype information as used in inodes. */
+#define FILETYPE_INO_MASK 0170000
+#define FILETYPE_INO_REG 0100000
+#define FILETYPE_INO_DIRECTORY 0040000
+#define FILETYPE_INO_SYMLINK 0120000
+#define EXT2_ROOT_INO 2 /* Root inode */
+
+/* Bits used as offset in sector */
+#define DISK_SECTOR_BITS 9
+/* The size of an ext2 block in bytes. */
+#define EXT2_BLOCK_SIZE(data) (1 << LOG2_BLOCK_SIZE(data))
+
+/* Log2 size of ext2 block in 512 blocks. */
+#define LOG2_EXT2_BLOCK_SIZE(data) (__le32_to_cpu \
+ (data->sblock.log2_block_size) + 1)
+
+/* Log2 size of ext2 block in bytes. */
+#define LOG2_BLOCK_SIZE(data) (__le32_to_cpu \
+ (data->sblock.log2_block_size) + 10)
+#define INODE_SIZE_FILESYSTEM(data) (__le32_to_cpu \
+ (data->sblock.inode_size))
+
+#define EXT2_FT_DIR 2
+#define SUCCESS 1
+
+/* Macro-instructions used to manage several block sizes */
+#define EXT2_MIN_BLOCK_LOG_SIZE 10 /* 1024 */
+#define EXT2_MAX_BLOCK_LOG_SIZE 16 /* 65536 */
+#define EXT2_MIN_BLOCK_SIZE (1 << EXT2_MIN_BLOCK_LOG_SIZE)
+#define EXT2_MAX_BLOCK_SIZE (1 << EXT2_MAX_BLOCK_LOG_SIZE)
+
+/* The ext2 superblock. */
+struct ext2_sblock {
+ uint32_t total_inodes;
+ uint32_t total_blocks;
+ uint32_t reserved_blocks;
+ uint32_t free_blocks;
+ uint32_t free_inodes;
+ uint32_t first_data_block;
+ uint32_t log2_block_size;
+ uint32_t log2_fragment_size;
+ uint32_t blocks_per_group;
+ uint32_t fragments_per_group;
+ uint32_t inodes_per_group;
+ uint32_t mtime;
+ uint32_t utime;
+ uint16_t mnt_count;
+ uint16_t max_mnt_count;
+ uint16_t magic;
+ uint16_t fs_state;
+ uint16_t error_handling;
+ uint16_t minor_revision_level;
+ uint32_t lastcheck;
+ uint32_t checkinterval;
+ uint32_t creator_os;
+ uint32_t revision_level;
+ uint16_t uid_reserved;
+ uint16_t gid_reserved;
+ uint32_t first_inode;
+ uint16_t inode_size;
+ uint16_t block_group_number;
+ uint32_t feature_compatibility;
+ uint32_t feature_incompat;
+ uint32_t feature_ro_compat;
+ uint32_t unique_id[4];
+ char volume_name[16];
+ char last_mounted_on[64];
+ uint32_t compression_info;
+};
+
+struct ext2_block_group {
+ __u32 block_id; /* Blocks bitmap block */
+ __u32 inode_id; /* Inodes bitmap block */
+ __u32 inode_table_id; /* Inodes table block */
+ __u16 free_blocks; /* Free blocks count */
+ __u16 free_inodes; /* Free inodes count */
+ __u16 used_dir_cnt; /* Directories count */
+ __u16 bg_flags;
+ __u32 bg_reserved[2];
+ __u16 bg_itable_unused; /* Unused inodes count */
+ __u16 bg_checksum; /* crc16(s_uuid+grouo_num+group_desc)*/
+};
+
+/* The ext2 inode. */
+struct ext2_inode {
+ uint16_t mode;
+ uint16_t uid;
+ uint32_t size;
+ uint32_t atime;
+ uint32_t ctime;
+ uint32_t mtime;
+ uint32_t dtime;
+ uint16_t gid;
+ uint16_t nlinks;
+ uint32_t blockcnt; /* Blocks of 512 bytes!! */
+ uint32_t flags;
+ uint32_t osd1;
+ union {
+ struct datablocks {
+ uint32_t dir_blocks[INDIRECT_BLOCKS];
+ uint32_t indir_block;
+ uint32_t double_indir_block;
+ uint32_t triple_indir_block;
+ } blocks;
+ char symlink[60];
+ } b;
+ uint32_t version;
+ uint32_t acl;
+ uint32_t dir_acl;
+ uint32_t fragment_addr;
+ uint32_t osd2[3];
+};
+
+/* The header of an ext2 directory entry. */
+struct ext2_dirent {
+ uint32_t inode;
+ uint16_t direntlen;
+ uint8_t namelen;
+ uint8_t filetype;
+};
+
+struct ext2fs_node {
+ struct ext2_data *data;
+ struct ext2_inode inode;
+ int ino;
+ int inode_read;
+};
+
+/* Information about a "mounted" ext2 filesystem. */
+struct ext2_data {
+ struct ext2_sblock sblock;
+ struct ext2_inode *inode;
+ struct ext2fs_node diropen;
+};
+
+int do_ext2ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+int do_ext2load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+int do_ext4_load(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[]);
+int do_ext4_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]);
+int do_ext4_write(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[]);
+int do_ext_load(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[]);
+int do_ext_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]);
+#endif
#define ERR_UNKNOWN_FLASH_VENDOR 32
#define ERR_UNKNOWN_FLASH_TYPE 64
#define ERR_PROG_ERROR 128
+#define ERR_ABORTED 256
/*-----------------------------------------------------------------------
* Protection Flags for flash_protect():
#define __FSL_NFC_H
/*
- * TODO: Use same register defs for nand_spl mxc nand driver
- * and mtd mxc nand driver.
+ * Register map and bit definitions for the Freescale NAND Flash Controller
+ * present in various i.MX devices.
*
- * Register map and bit definitions for the Freescale NAND Flash
- * Controller present in various i.MX devices.
+ * MX31 and MX27 have version 1, which has:
+ * 4 512-byte main buffers and
+ * 4 16-byte spare buffers
+ * to support up to 2K byte pagesize nand.
+ * Reading or writing a 2K page requires 4 FDI/FDO cycles.
*
- * MX31 and MX27 have version 1 which has
- * 4 512 byte main buffers and
- * 4 16 byte spare buffers
- * to support up to 2K byte pagesize nand.
- * Reading or writing a 2K page requires 4 FDI/FDO cycles.
- *
- * MX25 has version 1.1 which has
- * 8 512 byte main buffers and
- * 8 64 byte spare buffers
- * to support up to 4K byte pagesize nand.
- * Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle.
- * Also some of registers are moved and/or changed meaning as seen below.
+ * MX25 and MX35 have version 2.1, which has:
+ * 8 512-byte main buffers and
+ * 8 64-byte spare buffers
+ * to support up to 4K byte pagesize nand.
+ * Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle.
+ * Also some of registers are moved and/or changed meaning as seen below.
*/
-#if defined(CONFIG_MX31) || defined(CONFIG_MX27)
+#if defined(CONFIG_MX27) || defined(CONFIG_MX31)
#define MXC_NFC_V1
-#elif defined(CONFIG_MX25)
-#define MXC_NFC_V1_1
+#define is_mxc_nfc_1() 1
+#define is_mxc_nfc_21() 0
+#elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
+#define MXC_NFC_V2_1
+#define is_mxc_nfc_1() 0
+#define is_mxc_nfc_21() 1
#else
-#warning "MXC NFC version not defined"
+#error "MXC NFC implementation not supported"
#endif
#if defined(MXC_NFC_V1)
#define NAND_MXC_NR_BUFS 4
#define NAND_MXC_SPARE_BUF_SIZE 16
#define NAND_MXC_REG_OFFSET 0xe00
-#define NAND_MXC_2K_MULTI_CYCLE 1
-#elif defined(MXC_NFC_V1_1)
+#define NAND_MXC_2K_MULTI_CYCLE
+#elif defined(MXC_NFC_V2_1)
#define NAND_MXC_NR_BUFS 8
#define NAND_MXC_SPARE_BUF_SIZE 64
#define NAND_MXC_REG_OFFSET 0x1e00
-#else
-#error "define CONFIG_NAND_MXC_VXXX to use the mxc spl_nand driver"
#endif
struct fsl_nfc_regs {
- u32 main_area[NAND_MXC_NR_BUFS][512/4];
- u32 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE/4];
+ u8 main_area[NAND_MXC_NR_BUFS][0x200];
+ u8 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE];
/*
* reserved size is offset of nfc registers
* minus total main and spare sizes
u8 reserved1[NAND_MXC_REG_OFFSET
- NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)];
#if defined(MXC_NFC_V1)
- u16 bufsiz;
+ u16 buf_size;
u16 reserved2;
- u16 buffer_address;
- u16 flash_add;
+ u16 buf_addr;
+ u16 flash_addr;
u16 flash_cmd;
- u16 configuration;
+ u16 config;
u16 ecc_status_result;
- u16 ecc_rslt_main_area;
- u16 ecc_rslt_spare_area;
- u16 nf_wr_prot;
- u16 unlock_start_blk_add;
- u16 unlock_end_blk_add;
- u16 nand_flash_wr_pr_st;
- u16 nand_flash_config1;
- u16 nand_flash_config2;
-#elif defined(MXC_NFC_V1_1)
+ u16 rsltmain_area;
+ u16 rsltspare_area;
+ u16 wrprot;
+ u16 unlockstart_blkaddr;
+ u16 unlockend_blkaddr;
+ u16 nf_wrprst;
+ u16 config1;
+ u16 config2;
+#elif defined(MXC_NFC_V2_1)
u16 reserved2[2];
- u16 buffer_address;
- u16 flash_add;
+ u16 buf_addr;
+ u16 flash_addr;
u16 flash_cmd;
- u16 configuration;
- u16 ecc_status_result;
- u16 ecc_status_result2;
+ u16 config;
+ u32 ecc_status_result;
u16 spare_area_size;
- u16 nf_wr_prot;
+ u16 wrprot;
u16 reserved3[2];
- u16 nand_flash_wr_pr_st;
- u16 nand_flash_config1;
- u16 nand_flash_config2;
+ u16 nf_wrprst;
+ u16 config1;
+ u16 config2;
u16 reserved4;
- u16 unlock_start_blk_add0;
- u16 unlock_end_blk_add0;
- u16 unlock_start_blk_add1;
- u16 unlock_end_blk_add1;
- u16 unlock_start_blk_add2;
- u16 unlock_end_blk_add2;
- u16 unlock_start_blk_add3;
- u16 unlock_end_blk_add3;
+ u16 unlockstart_blkaddr;
+ u16 unlockend_blkaddr;
+ u16 unlockstart_blkaddr1;
+ u16 unlockend_blkaddr1;
+ u16 unlockstart_blkaddr2;
+ u16 unlockend_blkaddr2;
+ u16 unlockstart_blkaddr3;
+ u16 unlockend_blkaddr3;
#endif
};
*/
#define NFC_INT 0x8000
-#ifdef MXC_NFC_V1_1
+#ifdef MXC_NFC_V2_1
#define NFC_4_8N_ECC (1 << 0)
#endif
#define NFC_SP_EN (1 << 2)
#define NFC_RST (1 << 6)
#define NFC_CE (1 << 7)
#define NFC_ONE_CYCLE (1 << 8)
+#define NFC_FP_INT (1 << 11)
#endif /* __FSL_NFC_H */
/*
- * (C) Copyright 2005-2008 Samsung Electronics
- * Kyungmin Park <kyungmin.park@samsung.com>
- *
- * Derived from x-loader
- *
- * See file CREDITS for list of people who contributed to this
- * project.
+ * Copyright (C) 2012 Samsung Electronics
+ * Lukasz Majewski <l.majewski@samsung.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* MA 02111-1307 USA
*/
-#include <common.h>
-
-#include "onenand_ipl.h"
-
-typedef int (init_fnc_t)(void);
-
-void start_oneboot(void)
-{
- uchar *buf;
-
- buf = (uchar *) CONFIG_SYS_LOAD_ADDR;
-
- onenand_read_block(buf);
+#ifndef __G_DOWNLOAD_H_
+#define __G_DOWNLOAD_H_
- ((init_fnc_t *)CONFIG_SYS_LOAD_ADDR)();
+#include <linux/usb/ch9.h>
+#include <usbdescriptors.h>
+#include <linux/usb/gadget.h>
- /* should never come here */
-}
+int g_dnl_register(const char *s);
+void g_dnl_unregister(void);
-void hang(void)
-{
- for (;;);
-}
+/* USB initialization declaration - board specific */
+void board_usb_init(void);
+#endif /* __G_DOWNLOAD_H_ */
i2c_set_bus_num(bus);
}
+/* Multi I2C definitions */
+enum {
+ I2C_0, I2C_1, I2C_2, I2C_3, I2C_4, I2C_5, I2C_6, I2C_7,
+ I2C_8, I2C_9, I2C_10,
+};
+
+/* Multi I2C busses handling */
+#ifdef CONFIG_SOFT_I2C_MULTI_BUS
+extern int get_multi_scl_pin(void);
+extern int get_multi_sda_pin(void);
+extern int multi_i2c_init(void);
+#endif
#endif /* _I2C_H_ */
#define NAND_CMD_RESET 0xff
#define NAND_CMD_LOCK 0x2a
+#define NAND_CMD_LOCK_TIGHT 0x2c
#define NAND_CMD_UNLOCK1 0x23
#define NAND_CMD_UNLOCK2 0x24
+#define NAND_CMD_LOCK_STATUS 0x7a
/* Extended commands for large page devices */
#define NAND_CMD_READSTART 0x30
#define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \
&& (chip->page_shift > 9))
-/* Mask to zero out the chip options, which come from the id table */
-#define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
-
/* Non chip related options */
/*
* Use a flash based bad block table. OOB identifier is saved in OOB area.
uint resp_type;
uint cmdarg;
uint response[4];
- uint flags;
};
struct mmc_data {
int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts);
#define NAND_LOCK_STATUS_TIGHT 0x01
-#define NAND_LOCK_STATUS_LOCK 0x02
#define NAND_LOCK_STATUS_UNLOCK 0x04
-int nand_lock( nand_info_t *meminfo, int tight );
-int nand_unlock( nand_info_t *meminfo, ulong start, ulong length );
+int nand_lock(nand_info_t *meminfo, int tight);
+int nand_unlock(nand_info_t *meminfo, loff_t start, size_t length,
+ int allexcept);
int nand_get_lock_status(nand_info_t *meminfo, loff_t offset);
int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst);
#define PCI_DEVICE_ID_ATI_RS400_166 0x5a32
#define PCI_DEVICE_ID_ATI_RS400_200 0x5a33
#define PCI_DEVICE_ID_ATI_RS480 0x5950
+/* additional Radeon families */
+#define PCI_DEVICE_ID_ATI_EVERGREEN 0x9802
+#define PCI_DEVICE_ID_ATI_EVERGREEN2 0x9804
+#define PCI_DEVICE_ID_ATI_WRESTLER 0x9806
/* ATI IXP Chipset */
#define PCI_DEVICE_ID_ATI_IXP200_IDE 0x4349
#define PCI_DEVICE_ID_ATI_IXP200_SMBUS 0x4353
#define PCI_DEVICE_ID_ATI_IXP400_SATA 0x4379
#define PCI_DEVICE_ID_ATI_IXP400_SATA2 0x437a
#define PCI_DEVICE_ID_ATI_IXP600_SATA 0x4380
+#define PCI_DEVICE_ID_ATI_SBX00_PCI_BRIDGE 0x4384
#define PCI_DEVICE_ID_ATI_SBX00_SMBUS 0x4385
#define PCI_DEVICE_ID_ATI_IXP600_IDE 0x438c
#define PCI_DEVICE_ID_ATI_IXP700_SATA 0x4390
+#define PCI_DEVICE_ID_ATI_SBX00_SATA_AHCI 0x4391
+#define PCI_DEVICE_ID_ATI_SBX00_EHCI 0x4396
+#define PCI_DEVICE_ID_ATI_SBX00_OHCI 0x4397
#define PCI_DEVICE_ID_ATI_IXP700_IDE 0x439c
#define PCI_VENDOR_ID_VLSI 0x1004
#define PCI_DEVICE_ID_INTEL_82840_HB 0x1a21
#define PCI_DEVICE_ID_INTEL_82845_HB 0x1a30
#define PCI_DEVICE_ID_INTEL_IOAT 0x1a38
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE 0x1c03
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6 0x1c02
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_HDA 0x1c20
#define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN 0x1c41
#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX 0x1c5f
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE 0x1e03
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_HDA 0x1e20
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN 0x1e41
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX 0x1e5f
#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
#define PCI_DEVICE_ID_INTEL_PATSBURG_LPC 0x1d40
#define PCI_DEVICE_ID_INTEL_82801AA_0 0x2410
#define PCI_DEVICE_ID_INTEL_ICH7_30 0x27b0
#define PCI_DEVICE_ID_INTEL_TGP_LPC 0x27bc
#define PCI_DEVICE_ID_INTEL_ICH7_31 0x27bd
+#define PCI_DEVICE_ID_INTEL_NM10_AHCI 0x27c1
#define PCI_DEVICE_ID_INTEL_ICH7_17 0x27da
#define PCI_DEVICE_ID_INTEL_ICH7_19 0x27dd
#define PCI_DEVICE_ID_INTEL_ICH7_20 0x27de
#define SDHCI_SPACE_AVAILABLE 0x00000400
#define SDHCI_DATA_AVAILABLE 0x00000800
#define SDHCI_CARD_PRESENT 0x00010000
+#define SDHCI_CARD_STATE_STABLE 0x00020000
+#define SDHCI_CARD_DETECT_PIN_LEVEL 0x00040000
#define SDHCI_WRITE_PROTECT 0x00080000
#define SDHCI_HOST_CONTROL 0x28
#define SDHCI_CTRL_ADMA1 0x08
#define SDHCI_CTRL_ADMA32 0x10
#define SDHCI_CTRL_ADMA64 0x18
-#define SDHCI_CTRL_8BITBUS 0x20
+#define SDHCI_CTRL_8BITBUS 0x20
+#define SDHCI_CTRL_CD_TEST_INS 0x40
+#define SDHCI_CTRL_CD_TEST 0x80
#define SDHCI_POWER_CONTROL 0x29
#define SDHCI_POWER_ON 0x01
#define SDHCI_QUIRK_BROKEN_R1B (1 << 2)
#define SDHCI_QUIRK_NO_HISPD_BIT (1 << 3)
#define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4)
+#define SDHCI_QUIRK_NO_CD (1 << 5)
/* to make gcc happy */
struct sdhci_host;
unsigned int clock;
struct mmc *mmc;
const struct sdhci_ops *ops;
+ int index;
void (*set_control_reg)(struct sdhci_host *host);
+ void (*set_clock)(int dev_index, unsigned int div);
uint voltages;
};
struct _ENTRY *table;
unsigned int size;
unsigned int filled;
+/*
+ * Callback function which will check whether the given change for variable
+ * "name" from "oldval" to "newval" may be applied or not, and possibly apply
+ * such change.
+ * When (flag & H_FORCE) is set, it shall not print out any error message and
+ * shall force overwriting of write-once variables.
+.* Must return 0 for approval, 1 for denial.
+ */
+ int (*apply)(const char *name, const char *oldval,
+ const char *newval, int flag);
};
/* Create a new hashing table which will at most contain NEL elements. */
extern int hcreate_r(size_t __nel, struct hsearch_data *__htab);
/* Destroy current internal hashing table. */
-extern void hdestroy_r(struct hsearch_data *__htab);
+extern void hdestroy_r(struct hsearch_data *__htab, int do_apply);
/*
* Search for entry matching ITEM.key in internal hash table. If
struct hsearch_data *__htab);
/* Search and delete entry matching ITEM.key in internal hash table. */
-extern int hdelete_r(const char *__key, struct hsearch_data *__htab);
+extern int hdelete_r(const char *__key, struct hsearch_data *__htab,
+ int do_apply);
extern ssize_t hexport_r(struct hsearch_data *__htab,
const char __sep, char **__resp, size_t __size,
int argc, char * const argv[]);
+/*
+ * nvars: length of vars array
+ * vars: array of strings (variable names) to import (nvars == 0 means all)
+ * do_apply: whether to call callback function to check the new argument,
+ * and possibly apply changes (false means accept everything)
+ */
extern int himport_r(struct hsearch_data *__htab,
const char *__env, size_t __size, const char __sep,
- int __flag);
+ int __flag, int nvars, char * const vars[], int do_apply);
/* Flags for himport_r() */
-#define H_NOCLEAR 1 /* do not clear hash table before importing */
+#define H_NOCLEAR (1 << 0) /* do not clear hash table before importing */
+#define H_FORCE (1 << 1) /* overwrite read-only/write-once variables */
#endif /* search.h */
defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) || \
defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) || \
- defined(CONFIG_TEGRA20) || defined(CONFIG_SYS_COREBOOT)
+ defined(CONFIG_TEGRA20) || defined(CONFIG_SYS_COREBOOT) || \
+ defined(CONFIG_MICROBLAZE)
extern struct serial_device serial0_device;
extern struct serial_device serial1_device;
#if defined(CONFIG_SYS_NS16550_SERIAL)
*
* returns 0 on success, ULPI_ERROR on failure.
*/
-int ulpi_enable_vbus(struct ulpi_viewport *ulpi_vp,
+int ulpi_set_vbus(struct ulpi_viewport *ulpi_vp,
int on, int ext_power, int ext_ind);
/*
* be freed and the local static variable can be marked as not used.
*/
-void hdestroy_r(struct hsearch_data *htab)
+void hdestroy_r(struct hsearch_data *htab, int do_apply)
{
int i;
for (i = 1; i <= htab->size; ++i) {
if (htab->table[i].used > 0) {
ENTRY *ep = &htab->table[i].entry;
-
+ if (do_apply && htab->apply != NULL) {
+ /* deletion is always forced */
+ htab->apply(ep->key, ep->data, NULL, H_FORCE);
+ }
free((void *)ep->key);
free(ep->data);
}
* do that.
*/
-int hdelete_r(const char *key, struct hsearch_data *htab)
+int hdelete_r(const char *key, struct hsearch_data *htab, int do_apply)
{
ENTRY e, *ep;
int idx;
/* free used ENTRY */
debug("hdelete: DELETING key \"%s\"\n", key);
-
+ if (do_apply && htab->apply != NULL)
+ htab->apply(ep->key, ep->data, NULL, H_FORCE);
free((void *)ep->key);
free(ep->data);
htab->table[idx].used = -1;
* himport()
*/
+/*
+ * Check whether variable 'name' is amongst vars[],
+ * and remove all instances by setting the pointer to NULL
+ */
+static int drop_var_from_set(const char *name, int nvars, char * vars[])
+{
+ int i = 0;
+ int res = 0;
+
+ /* No variables specified means process all of them */
+ if (nvars == 0)
+ return 1;
+
+ for (i = 0; i < nvars; i++) {
+ if (vars[i] == NULL)
+ continue;
+ /* If we found it, delete all of them */
+ if (!strcmp(name, vars[i])) {
+ vars[i] = NULL;
+ res = 1;
+ }
+ }
+ if (!res)
+ debug("Skipping non-listed variable %s\n", name);
+
+ return res;
+}
+
/*
* Import linearized data into hash table.
*
*/
int himport_r(struct hsearch_data *htab,
- const char *env, size_t size, const char sep, int flag)
+ const char *env, size_t size, const char sep, int flag,
+ int nvars, char * const vars[], int do_apply)
{
char *data, *sp, *dp, *name, *value;
+ char *localvars[nvars];
+ int i;
/* Test for correct arguments. */
if (htab == NULL) {
memcpy(data, env, size);
dp = data;
+ /* make a local copy of the list of variables */
+ if (nvars)
+ memcpy(localvars, vars, sizeof(vars[0]) * nvars);
+
if ((flag & H_NOCLEAR) == 0) {
/* Destroy old hash table if one exists */
debug("Destroy Hash Table: %p table = %p\n", htab,
htab->table);
if (htab->table)
- hdestroy_r(htab);
+ hdestroy_r(htab, do_apply);
}
/*
*dp++ = '\0'; /* terminate name */
debug("DELETE CANDIDATE: \"%s\"\n", name);
+ if (!drop_var_from_set(name, nvars, localvars))
+ continue;
- if (hdelete_r(name, htab) == 0)
+ if (hdelete_r(name, htab, do_apply) == 0)
debug("DELETE ERROR ##############################\n");
continue;
*sp++ = '\0'; /* terminate value */
++dp;
+ /* Skip variables which are not supposed to be processed */
+ if (!drop_var_from_set(name, nvars, localvars))
+ continue;
+
/* enter into hash table */
e.key = name;
e.data = value;
+ /* if there is an apply function, check what it has to say */
+ if (do_apply && htab->apply != NULL) {
+ debug("searching before calling cb function"
+ " for %s\n", name);
+ /*
+ * Search for variable in existing env, so to pass
+ * its previous value to the apply callback
+ */
+ hsearch_r(e, FIND, &rv, htab);
+ debug("previous value was %s\n", rv ? rv->data : "");
+ if (htab->apply(name, rv ? rv->data : NULL,
+ value, flag)) {
+ debug("callback function refused to set"
+ " variable %s, skipping it!\n", name);
+ continue;
+ }
+ }
+
hsearch_r(e, ENTER, &rv, htab);
if (rv == NULL) {
printf("himport_r: can't insert \"%s=%s\" into hash table\n",
debug("INSERT: free(data = %p)\n", data);
free(data);
+ /* process variables which were not considered */
+ for (i = 0; i < nvars; i++) {
+ if (localvars[i] == NULL)
+ continue;
+ /*
+ * All variables which were not deleted from the variable list
+ * were not present in the imported env
+ * This could mean two things:
+ * a) if the variable was present in current env, we delete it
+ * b) if the variable was not present in current env, we notify
+ * it might be a typo
+ */
+ if (hdelete_r(localvars[i], htab, do_apply) == 0)
+ printf("WARNING: '%s' neither in running nor in imported env!\n", localvars[i]);
+ else
+ printf("WARNING: '%s' not in imported env, deleting it!\n", localvars[i]);
+ }
+
debug("INSERT: done\n");
return 1; /* everything OK */
}
mtsdram(SDRAM_INITPLR11, 0x80000432);
mtsdram(SDRAM_INITPLR12, 0x808103C0);
mtsdram(SDRAM_INITPLR13, 0x80810040);
- mtsdram(SDRAM_INITPLR14, 0x00000000);
- mtsdram(SDRAM_INITPLR15, 0x00000000);
mtsdram(SDRAM_RDCC, 0x40000000);
mtsdram(SDRAM_RQDC, 0x80000038);
mtsdram(SDRAM_RFDC, 0x00000257);
mtdcr(SDRAM_R0BAS, 0x0000F800); /* MQ0_B0BAS */
- mtdcr(SDRAM_R1BAS, 0x0400F800); /* MQ0_B1BAS */
}
phys_size_t initdram(int board_type)
{
uint32_t tmp;
- while (!(readw(&nfc->nand_flash_config2) & NFC_INT))
+ while (!(readw(&nfc->config2) & NFC_INT))
;
/* Reset interrupt flag */
- tmp = readw(&nfc->nand_flash_config2);
+ tmp = readw(&nfc->config2);
tmp &= ~NFC_INT;
- writew(tmp, &nfc->nand_flash_config2);
+ writew(tmp, &nfc->config2);
}
-void nfc_nand_init(void)
+static void nfc_nand_init(void)
{
-#if defined(MXC_NFC_V1_1)
- int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512;
+#if defined(MXC_NFC_V2_1)
+ int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512;
int config1;
writew(CONFIG_SYS_NAND_SPARE_SIZE / 2, &nfc->spare_area_size);
/* unlocking RAM Buff */
- writew(0x2, &nfc->configuration);
+ writew(0x2, &nfc->config);
/* hardware ECC checking and correct */
- config1 = readw(&nfc->nand_flash_config1) | NFC_ECC_EN | 0x800;
+ config1 = readw(&nfc->config1) | NFC_ECC_EN | NFC_INT_MSK |
+ NFC_ONE_CYCLE | NFC_FP_INT;
/*
* if spare size is larger that 16 bytes per 512 byte hunk
* then use 8 symbol correction instead of 4
*/
- if ((CONFIG_SYS_NAND_SPARE_SIZE / ecc_per_page) > 16)
+ if (CONFIG_SYS_NAND_SPARE_SIZE / ecc_per_page > 16)
config1 &= ~NFC_4_8N_ECC;
else
config1 |= NFC_4_8N_ECC;
- writew(config1, &nfc->nand_flash_config1);
+ writew(config1, &nfc->config1);
#elif defined(MXC_NFC_V1)
/* unlocking RAM Buff */
- writew(0x2, &nfc->configuration);
+ writew(0x2, &nfc->config);
/* hardware ECC checking and correct */
- writew(NFC_ECC_EN, &nfc->nand_flash_config1);
+ writew(NFC_ECC_EN | NFC_INT_MSK, &nfc->config1);
#endif
}
static void nfc_nand_command(unsigned short command)
{
writew(command, &nfc->flash_cmd);
- writew(NFC_CMD, &nfc->nand_flash_config2);
+ writew(NFC_CMD, &nfc->config2);
+ nfc_wait_ready();
+}
+
+static void nfc_nand_address(unsigned short address)
+{
+ writew(address, &nfc->flash_addr);
+ writew(NFC_ADDR, &nfc->config2);
nfc_wait_ready();
}
{
unsigned int page_count;
- writew(0x00, &nfc->flash_add);
- writew(NFC_ADDR, &nfc->nand_flash_config2);
- nfc_wait_ready();
+ nfc_nand_address(0x00);
/* code only for large page flash */
- if (CONFIG_SYS_NAND_PAGE_SIZE > 512) {
- writew(0x00, &nfc->flash_add);
- writew(NFC_ADDR, &nfc->nand_flash_config2);
- nfc_wait_ready();
- }
+ if (CONFIG_SYS_NAND_PAGE_SIZE > 512)
+ nfc_nand_address(0x00);
page_count = CONFIG_SYS_NAND_SIZE / CONFIG_SYS_NAND_PAGE_SIZE;
if (page_address <= page_count) {
page_count--; /* transform 0x01000000 to 0x00ffffff */
do {
- writew(page_address & 0xff, &nfc->flash_add);
- writew(NFC_ADDR, &nfc->nand_flash_config2);
- nfc_wait_ready();
+ nfc_nand_address(page_address & 0xff);
page_address = page_address >> 8;
page_count = page_count >> 8;
} while (page_count);
}
- writew(0x00, &nfc->flash_add);
- writew(NFC_ADDR, &nfc->nand_flash_config2);
- nfc_wait_ready();
+ nfc_nand_address(0x00);
}
static void nfc_nand_data_output(void)
{
- int config1 = readw(&nfc->nand_flash_config1);
#ifdef NAND_MXC_2K_MULTI_CYCLE
int i;
#endif
- config1 |= NFC_ECC_EN | NFC_INT_MSK;
- writew(config1, &nfc->nand_flash_config1);
- writew(0, &nfc->buffer_address);
- writew(NFC_OUTPUT, &nfc->nand_flash_config2);
+ writew(0, &nfc->buf_addr);
+ writew(NFC_OUTPUT, &nfc->config2);
nfc_wait_ready();
#ifdef NAND_MXC_2K_MULTI_CYCLE
/*
* This NAND controller requires multiple input commands
* for pages larger than 512 bytes.
*/
- for (i = 1; i < (CONFIG_SYS_NAND_PAGE_SIZE / 512); i++) {
- config1 = readw(&nfc->nand_flash_config1);
- config1 |= NFC_ECC_EN | NFC_INT_MSK;
- writew(config1, &nfc->nand_flash_config1);
- writew(i, &nfc->buffer_address);
- writew(NFC_OUTPUT, &nfc->nand_flash_config2);
+ for (i = 1; i < CONFIG_SYS_NAND_PAGE_SIZE / 512; i++) {
+ writew(i, &nfc->buf_addr);
+ writew(NFC_OUTPUT, &nfc->config2);
nfc_wait_ready();
}
#endif
static int nfc_nand_check_ecc(void)
{
- return readw(&nfc->ecc_status_result);
+#if defined(MXC_NFC_V1)
+ u16 ecc_status = readw(&nfc->ecc_status_result);
+ return (ecc_status & 0x3) == 2 || (ecc_status >> 2) == 2;
+#elif defined(MXC_NFC_V2_1)
+ u32 ecc_status = readl(&nfc->ecc_status_result);
+ int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512;
+ int err_limit = CONFIG_SYS_NAND_SPARE_SIZE / ecc_per_page > 16 ? 8 : 4;
+ int subpages = CONFIG_SYS_NAND_PAGE_SIZE / 512;
+
+ do {
+ if ((ecc_status & 0xf) > err_limit)
+ return 1;
+ ecc_status >>= 4;
+ } while (--subpages);
+
+ return 0;
+#endif
}
-static int nfc_read_page(unsigned int page_address, unsigned char *buf)
+static void nfc_nand_read_page(unsigned int page_address)
{
- int i;
- u32 *src;
- u32 *dst;
-
- writew(0, &nfc->buffer_address); /* read in first 0 buffer */
+ writew(0, &nfc->buf_addr); /* read in first 0 buffer */
nfc_nand_command(NAND_CMD_READ0);
nfc_nand_page_address(page_address);
nfc_nand_command(NAND_CMD_READSTART);
nfc_nand_data_output(); /* fill the main buffer 0 */
+}
+
+static int nfc_read_page(unsigned int page_address, unsigned char *buf)
+{
+ int i;
+ u32 *src;
+ u32 *dst;
+
+ nfc_nand_read_page(page_address);
if (nfc_nand_check_ecc())
return -1;
- src = &nfc->main_area[0][0];
+ src = (u32 *)&nfc->main_area[0][0];
dst = (u32 *)buf;
/* main copy loop from NAND-buffer to SDRAM memory */
- for (i = 0; i < (CONFIG_SYS_NAND_PAGE_SIZE / 4); i++) {
+ for (i = 0; i < CONFIG_SYS_NAND_PAGE_SIZE / 4; i++) {
writel(readl(src), dst);
src++;
dst++;
/* Check the first two pages for bad block markers */
for (page = pagenumber; page < pagenumber + 2; page++) {
- writew(0, &nfc->buffer_address); /* read in first 0 buffer */
- nfc_nand_command(NAND_CMD_READ0);
- nfc_nand_page_address(page);
-
- if (CONFIG_SYS_NAND_PAGE_SIZE > 512)
- nfc_nand_command(NAND_CMD_READSTART);
-
- nfc_nand_data_output(); /* fill the main buffer 0 */
+ nfc_nand_read_page(page);
- src = &nfc->spare_area[0][0];
+ src = (u32 *)&nfc->spare_area[0][0];
/*
* IMPORTANT NOTE: The nand flash controller uses a non-
page = from / CONFIG_SYS_NAND_PAGE_SIZE;
i = 0;
- while (i < (size / CONFIG_SYS_NAND_PAGE_SIZE)) {
+ while (i < size / CONFIG_SYS_NAND_PAGE_SIZE) {
if (nfc_read_page(page, buf) < 0)
return -1;
+++ /dev/null
-
-include $(TOPDIR)/config.mk
-include $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/config.mk
-
-LDSCRIPT= $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/u-boot.onenand.lds
-LDFLAGS = -Bstatic -T $(onenandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(PLATFORM_LDFLAGS)
-AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_ONENAND_IPL
-CFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_ONENAND_IPL
-OBJCFLAGS += --gap-fill=0x00
-
-SOBJS := low_levelinit.o
-SOBJS += start.o
-COBJS := apollon.o
-COBJS += onenand_read.o
-COBJS += onenand_boot.o
-
-SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(OBJTREE)/onenand_ipl/board/$(BOARDDIR)
-
-onenandobj := $(OBJTREE)/onenand_ipl/
-
-ALL = $(onenandobj)onenand-ipl $(onenandobj)onenand-ipl.bin $(onenandobj)onenand-ipl-2k.bin $(onenandobj)onenand-ipl-4k.bin
-
-all: $(obj).depend $(ALL)
-
-$(onenandobj)onenand-ipl-2k.bin: $(onenandobj)onenand-ipl
- $(OBJCOPY) ${OBJCFLAGS} --pad-to=0x800 -O binary $< $@
-
-$(onenandobj)onenand-ipl-4k.bin: $(onenandobj)onenand-ipl
- $(OBJCOPY) ${OBJCFLAGS} --pad-to=0x1000 -O binary $< $@
-
-$(onenandobj)onenand-ipl.bin: $(onenandobj)onenand-ipl
- $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
-
-$(onenandobj)onenand-ipl: $(OBJS) $(onenandobj)u-boot.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
- -Map $@.map -o $@
-
-$(onenandobj)u-boot.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
-
-# create symbolic links from common files
-
-# from cpu directory
-$(obj)start.S:
- @rm -f $@
- ln -s $(SRCTREE)/$(CPUDIR)/start.S $@
-
-# from onenand_ipl directory
-$(obj)onenand_ipl.h:
- @rm -f $@
- ln -s $(SRCTREE)/onenand_ipl/onenand_ipl.h $@
-
-$(obj)onenand_boot.c: $(obj)onenand_ipl.h
- @rm -f $@
- ln -s $(SRCTREE)/onenand_ipl/onenand_boot.c $@
-
-$(obj)onenand_read.c: $(obj)onenand_ipl.h
- @rm -f $@
- ln -s $(SRCTREE)/onenand_ipl/onenand_read.c $@
-
-ifneq ($(OBJTREE), $(SRCTREE))
-$(obj)apollon.c:
- @rm -f $@
- ln -s $(SRCTREE)/onenand_ipl/board/$(BOARDDIR)/apollon.c $@
-
-$(obj)low_levelinit.S:
- @rm -f $@
- ln -s $(SRCTREE)/onenand_ipl/board/$(BOARDDIR)/low_levelinit.S $@
-endif
-
-#########################################################################
-
-$(obj)%.o: $(obj)%.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(obj)$.c
- $(CC) $(CFLAGS) -c -o $@ $<
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-/*
- * (C) Copyright 2005-2008 Samsung Electronics
- * Kyungmin Park <kyungmin.park@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <asm/arch/mux.h>
-
-#define write_config_reg(reg, value) \
-do { \
- writeb(value, reg); \
-} while (0)
-
-/*****************************************
- * Routine: board_init
- * Description: Early hardware init.
- *****************************************/
-int board_init(void)
-{
- return 0;
-}
-
-#ifdef CONFIG_SYS_PRINTF
-/* Pin Muxing registers used for UART1 */
-/****************************************
- * Routine: muxSetupUART1 (ostboot)
- * Description: Set up uart1 muxing
- *****************************************/
-static void muxSetupUART1(void)
-{
- /* UART1_CTS pin configuration, PIN = D21 */
- write_config_reg(CONTROL_PADCONF_UART1_CTS, 0);
- /* UART1_RTS pin configuration, PIN = H21 */
- write_config_reg(CONTROL_PADCONF_UART1_RTS, 0);
- /* UART1_TX pin configuration, PIN = L20 */
- write_config_reg(CONTROL_PADCONF_UART1_TX, 0);
- /* UART1_RX pin configuration, PIN = T21 */
- write_config_reg(CONTROL_PADCONF_UART1_RX, 0);
-}
-#endif
-
-/**********************************************************
- * Routine: s_init
- * Description: Does early system init of muxing and clocks.
- * - Called at time when only stack is available.
- **********************************************************/
-int s_init(int skip)
-{
-#ifdef CONFIG_SYS_PRINTF
- muxSetupUART1();
-#endif
- return 0;
-}
+++ /dev/null
-#
-# (C) Copyright 2005-2008 Samsung Electronics
-# Kyungmin Park <kyungmin.park@samsung.com>
-#
-# Samsung Apollon board with OMAP2420 (ARM1136) cpu
-#
-# Apollon has 1 bank of 128MB mDDR-SDRAM on CS0
-# Physical Address:
-# 8000'0000 (bank0)
-# 8800'0000 (bank1)
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-
-CONFIG_SYS_TEXT_BASE = 0x00000000
+++ /dev/null
-/*
- * Board specific setup info
- *
- * (C) Copyright 2005-2008 Samsung Electronics
- * Kyungmin Park <kyungmin.park@samsung.com>
- *
- * Derived from board/omap2420h4/platform.S
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/omap2420.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/clocks.h>
-
-#define APOLLON_CS0_BASE 0x00000000
-
-#ifdef PRCM_CONFIG_I
-#define SDRC_ACTIM_CTRLA_0_VAL 0x7BA35907
-#define SDRC_ACTIM_CTRLB_0_VAL 0x00000013
-#define SDRC_RFR_CTRL_0_VAL 0x00044C01
-
-/* GPMC */
-#define APOLLON_GPMC_CONFIG1_0 0xe30d1201
-#define APOLLON_GPMC_CONFIG2_0 0x000c1000
-#define APOLLON_GPMC_CONFIG3_0 0x00030400
-#define APOLLON_GPMC_CONFIG4_0 0x0B841006
-#define APOLLON_GPMC_CONFIG5_0 0x020F0C11
-#define APOLLON_GPMC_CONFIG6_0 0x00000000
-#define APOLLON_GPMC_CONFIG7_0 (0x00000e40 | (APOLLON_CS0_BASE >> 24))
-
-#elif defined(PRCM_CONFIG_II)
-#define SDRC_ACTIM_CTRLA_0_VAL 0x4A59B485
-#define SDRC_ACTIM_CTRLB_0_VAL 0x0000000C
-#define SDRC_RFR_CTRL_0_VAL 0x00030001
-
-/* GPMC */
-#define APOLLON_GPMC_CONFIG1_0 0xe30d1201
-#define APOLLON_GPMC_CONFIG2_0 0x00080E81
-#define APOLLON_GPMC_CONFIG3_0 0x00030400
-#define APOLLON_GPMC_CONFIG4_0 0x08041586
-#define APOLLON_GPMC_CONFIG5_0 0x020C090E
-#define APOLLON_GPMC_CONFIG6_0 0x00000000
-#define APOLLON_GPMC_CONFIG7_0 (0x00000e40 | (APOLLON_CS0_BASE >> 24))
-
-#else
-#error "Please configure PRCM schecm"
-#endif
-
-_TEXT_BASE:
- .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
-
-.globl lowlevel_init
-lowlevel_init:
- mov r3, r0 /* save skip information */
-
- /* Disable watchdog */
- ldr r0, =WD2_BASE
- ldr r1, =WD_UNLOCK1
- str r1, [r0, #WSPR]
-
- ldr r1, =WD_UNLOCK2
- str r1, [r0, #WSPR]
-
-#ifdef DEBUG_LED
- /* LED0 OFF */
- ldr r0, =0x480000E5 /* ball AA10, mode 3 */
- mov r1, #0x0b
- strb r1, [r0]
-#endif
-
- /* Pin muxing for SDRC */
- mov r1, #0x00
- ldr r0, =0x480000A1 /* ball C12, mode 0 */
- strb r1, [r0]
-
- ldr r0, =0x48000032 /* ball D11, mode 0 */
- strb r1, [r0]
-
- ldr r0, =0x480000A3 /* ball B13, mode 0 */
- strb r1, [r0]
-
- /* SDRC setting */
- ldr r0, =OMAP2420_SDRC_BASE
- ldr r1, =0x00000010
- str r1, [r0, #0x10]
-
- ldr r1, =0x00000100
- str r1, [r0, #0x44]
-
- /* SDRC CS0 configuration */
-#ifdef CONFIG_APOLLON_PLUS
- ldr r1, =0x01702011
-#else
- ldr r1, =0x00d04011
-#endif
- str r1, [r0, #0x80]
-
- ldr r1, =SDRC_ACTIM_CTRLA_0_VAL
- str r1, [r0, #0x9C]
-
- ldr r1, =SDRC_ACTIM_CTRLB_0_VAL
- str r1, [r0, #0xA0]
-
- ldr r1, =SDRC_RFR_CTRL_0_VAL
- str r1, [r0, #0xA4]
-
- ldr r1, =0x00000041
- str r1, [r0, #0x70]
-
- /* Manual command sequence */
- ldr r1, =0x00000007
- str r1, [r0, #0xA8]
-
- ldr r1, =0x00000000
- str r1, [r0, #0xA8]
-
- ldr r1, =0x00000001
- str r1, [r0, #0xA8]
-
- ldr r1, =0x00000002
- str r1, [r0, #0xA8]
- str r1, [r0, #0xA8]
-
- /*
- * CS0 SDRC Mode register
- * Burst length = 4 - DDR memory
- * Serial mode
- * CAS latency = 3
- */
- ldr r1, =0x00000032
- str r1, [r0, #0x84]
-
- /* Note: You MUST set EMR values */
- /* EMR1 & EMR2 */
- ldr r1, =0x00000000
- str r1, [r0, #0x88]
- str r1, [r0, #0x8C]
-
-#ifdef OLD_SDRC_DLLA_CTRL
- /* SDRC_DLLA_CTRL */
- ldr r1, =0x00007306
- str r1, [r0, #0x60]
-
- ldr r1, =0x00007303
- str r1, [r0, #0x60]
-#else
- /* SDRC_DLLA_CTRL */
- ldr r1, =0x00000506
- str r1, [r0, #0x60]
-
- ldr r1, =0x00000503
- str r1, [r0, #0x60]
-#endif
-
-#ifdef __BROKEN_FEATURE__
- /* SDRC_DLLB_CTRL */
- ldr r1, =0x00000506
- str r1, [r0, #0x68]
-
- ldr r1, =0x00000503
- str r1, [r0, #0x68]
-#endif
-
- /* little delay after init */
- mov r2, #0x1800
-1:
- subs r2, r2, #0x1
- bne 1b
-
- ldr sp, SRAM_STACK
- str ip, [sp] /* stash old link register */
- mov ip, lr /* save link reg across call */
- mov r0, r3 /* pass skip info to s_init */
-
- bl s_init /* go setup pll,mux,memory */
-
- ldr ip, [sp] /* restore save ip */
- mov lr, ip /* restore link reg */
-
- /* back to arch calling code */
- mov pc, lr
-
- /* the literal pools origin */
- .ltorg
-
-SRAM_STACK:
- .word LOW_LEVEL_SRAM_STACK
+++ /dev/null
-/*
- * (C) Copyright 2005-2008 Samsung Electronics
- * Kyungmin Park <kyungmin.park@samsung.com>
- *
- * Derived from X-loader
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- start.o (.text)
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : { *(.data) }
-
- . = ALIGN(4);
- .got : { *(.got) }
-
- . = ALIGN(4);
- __bss_start = .;
- .bss : { *(.bss) . = ALIGN(4); }
- __bss_end__ = .;
-}
+++ /dev/null
-/*
- * (C) Copyright 2005-2008 Samsung Electronics
- * Kyungmin Park <kyungmin.park@samsung.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _ONENAND_IPL_H
-#define _ONENAND_IPL_H
-
-#include <linux/mtd/onenand_regs.h>
-
-#define onenand_readw(a) readw(THIS_ONENAND(a))
-#define onenand_writew(v, a) writew(v, THIS_ONENAND(a))
-
-#define THIS_ONENAND(a) (CONFIG_SYS_ONENAND_BASE + (a))
-
-#define READ_INTERRUPT() onenand_readw(ONENAND_REG_INTERRUPT)
-
-extern int (*onenand_read_page)(ulong block, ulong page,
- u_char *buf, int pagesize);
-extern int onenand_read_block(unsigned char *buf);
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2005-2009 Samsung Electronics
- * Kyungmin Park <kyungmin.park@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#include <asm/io.h>
-#include <asm/string.h>
-
-#include "onenand_ipl.h"
-
-#define onenand_block_address(block) (block)
-#define onenand_sector_address(page) (page << 2)
-#define onenand_buffer_address() ((1 << 3) << 8)
-#define onenand_bufferram_address(block) (0)
-
-#ifdef __HAVE_ARCH_MEMCPY32
-extern void *memcpy32(void *dest, void *src, int size);
-#endif
-
-int (*onenand_read_page)(ulong block, ulong page, u_char *buf, int pagesize);
-
-/* read a page with ECC */
-static int generic_onenand_read_page(ulong block, ulong page,
- u_char * buf, int pagesize)
-{
- unsigned long *base;
-
-#ifndef __HAVE_ARCH_MEMCPY32
- unsigned int offset, value;
- unsigned long *p;
-#endif
-
- onenand_writew(onenand_block_address(block),
- ONENAND_REG_START_ADDRESS1);
-
- onenand_writew(onenand_bufferram_address(block),
- ONENAND_REG_START_ADDRESS2);
-
- onenand_writew(onenand_sector_address(page),
- ONENAND_REG_START_ADDRESS8);
-
- onenand_writew(onenand_buffer_address(),
- ONENAND_REG_START_BUFFER);
-
- onenand_writew(ONENAND_INT_CLEAR, ONENAND_REG_INTERRUPT);
-
- onenand_writew(ONENAND_CMD_READ, ONENAND_REG_COMMAND);
-
-#ifndef __HAVE_ARCH_MEMCPY32
- p = (unsigned long *) buf;
-#endif
- base = (unsigned long *) (CONFIG_SYS_ONENAND_BASE + ONENAND_DATARAM);
-
- while (!(READ_INTERRUPT() & ONENAND_INT_READ))
- continue;
-
- /* Check for invalid block mark */
- if (page < 2 && (onenand_readw(ONENAND_SPARERAM) != 0xffff))
- return 1;
-
-#ifdef __HAVE_ARCH_MEMCPY32
- /* 32 bytes boundary memory copy */
- memcpy32(buf, base, pagesize);
-#else
- for (offset = 0; offset < (pagesize >> 2); offset++) {
- value = *(base + offset);
- *p++ = value;
- }
-#endif
-
- return 0;
-}
-
-#ifndef CONFIG_ONENAND_START_PAGE
-#define CONFIG_ONENAND_START_PAGE 1
-#endif
-#define ONENAND_PAGES_PER_BLOCK 64
-
-static void onenand_generic_init(int *page_is_4KiB, int *page)
-{
- int dev_id, density;
-
- if (onenand_readw(ONENAND_REG_TECHNOLOGY))
- *page_is_4KiB = 1;
- dev_id = onenand_readw(ONENAND_REG_DEVICE_ID);
- density = dev_id >> ONENAND_DEVICE_DENSITY_SHIFT;
- density &= ONENAND_DEVICE_DENSITY_MASK;
- if (density >= ONENAND_DEVICE_DENSITY_4Gb &&
- !(dev_id & ONENAND_DEVICE_IS_DDP))
- *page_is_4KiB = 1;
-}
-
-/**
- * onenand_read_block - Read CONFIG_SYS_MONITOR_LEN from begining
- * of OneNAND, skipping bad blocks
- * @return 0 on success
- */
-int onenand_read_block(unsigned char *buf)
-{
- int block, nblocks;
- int page = CONFIG_ONENAND_START_PAGE, offset = 0;
- int pagesize, erasesize, erase_shift;
- int page_is_4KiB = 0;
-
- onenand_read_page = generic_onenand_read_page;
-
- onenand_generic_init(&page_is_4KiB, &page);
-
- if (page_is_4KiB) {
- pagesize = 4096; /* OneNAND has 4KiB pagesize */
- erase_shift = 18;
- } else {
- pagesize = 2048; /* OneNAND has 2KiB pagesize */
- erase_shift = 17;
- }
-
- erasesize = (1 << erase_shift);
- nblocks = (CONFIG_SYS_MONITOR_LEN + erasesize - 1) >> erase_shift;
-
- /* NOTE: you must read page from page 1 of block 0 */
- /* read the block page by page */
- for (block = 0; block < nblocks; block++) {
- for (; page < ONENAND_PAGES_PER_BLOCK; page++) {
- if (onenand_read_page(block, page, buf + offset,
- pagesize)) {
- /* This block is bad. Skip it
- * and read next block */
- offset -= page * pagesize;
- nblocks++;
- break;
- }
- offset += pagesize;
- }
- page = 0;
- }
-
- return 0;
-}
$(OBJCOPY) $(OBJCFLAGS) -O binary $< $@
GEN_UBOOT = \
- UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) | \
- sed -n -e 's/.*\($(SYM_PREFIX)__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
- cd $(obj) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) $$UNDEF_SYM $(__START) \
+ cd $(obj) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) $(__START) \
--start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \
-Map u-boot-spl.map -o u-boot-spl
#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0)
"pcidelay=" MK_STR (CONFIG_PCI_BOOTDELAY) "\0"
#endif
+#ifdef CONFIG_ENV_VARS_UBOOT_CONFIG
+ "arch=" CONFIG_SYS_ARCH "\0"
+ "cpu=" CONFIG_SYS_CPU "\0"
+ "board=" CONFIG_SYS_BOARD "\0"
+#ifdef CONFIG_SYS_VENDOR
+ "vendor=" CONFIG_SYS_VENDOR "\0"
+#endif
+#ifdef CONFIG_SYS_SOC
+ "soc=" CONFIG_SYS_SOC "\0"
+#endif
+#endif
#ifdef CONFIG_EXTRA_ENV_SETTINGS
CONFIG_EXTRA_ENV_SETTINGS
#endif
# Lines which are allowed after a TEST= line
re_allowed_after_test = re.compile('^Signed-off-by:')
+# Signoffs
+re_signoff = re.compile('^Signed-off-by:')
+
# The start of the cover letter
re_cover = re.compile('^Cover-letter:')
re_series = re.compile('^Series-(\w*): *(.*)')
# Commit tags that we want to collect and keep
-re_tag = re.compile('^(Tested-by|Acked-by|Signed-off-by|Cc): (.*)')
+re_tag = re.compile('^(Tested-by|Acked-by|Cc): (.*)')
# The start of a new commit in the git log
re_commit = re.compile('^commit (.*)')
if is_blank:
# Blank line ends this change list
self.in_change = 0
+ elif line == '---' or re_signoff.match(line):
+ self.in_change = 0
+ out = self.ProcessLine(line)
else:
- self.series.AddChange(self.in_change, self.commit, line)
+ if self.is_log:
+ self.series.AddChange(self.in_change, self.commit, line)
self.skip_blank = False
# Detect Series-xxx tags
# Detect tags in the commit message
elif tag_match:
- # Onlly allow a single signoff tag
- if tag_match.group(1) == 'Signed-off-by':
- if self.signoff:
- self.warn.append('Patch has more than one Signed-off-by '
- 'tag')
- self.signoff += [line]
-
# Remove Tested-by self, since few will take much notice
- elif (tag_match.group(1) == 'Tested-by' and
+ if (tag_match.group(1) == 'Tested-by' and
tag_match.group(2).find(os.getenv('USER') + '@') != -1):
self.warn.append("Ignoring %s" % line)
elif tag_match.group(1) == 'Cc':
# Output the tags (signeoff first), then change list
out = []
- if self.signoff:
- out += self.signoff
log = self.series.MakeChangeLog(self.commit)
out += self.FormatTags(self.tags)
out += [line] + log
cc_list += gitutil.BuildEmailList(commit.tags)
cc_list += gitutil.BuildEmailList(commit.cc_list)
+ # Skip items in To list
+ if 'to' in self:
+ try:
+ map(cc_list.remove, gitutil.BuildEmailList(self.to))
+ except ValueError:
+ pass
+
for email in cc_list:
if email == None:
email = col.Color(col.YELLOW, "<alias '%s' not found>"
for this_commit, text in self.changes[change]:
if commit and this_commit != commit:
continue
- if text not in out:
- out.append(text)
+ out.append(text)
if out:
- out = ['Changes in v%d:' % change] + sorted(out)
+ out = ['Changes in v%d:' % change] + out
if need_blank:
out = [''] + out
final += out
col = terminal.Color()
if self.get('version'):
changes_copy = dict(self.changes)
- for version in range(2, int(self.version) + 1):
+ for version in range(1, int(self.version) + 1):
if self.changes.get(version):
del changes_copy[version]
else:
- str = 'Change log missing for v%d' % version
- print col.Color(col.RED, str)
+ if version > 1:
+ str = 'Change log missing for v%d' % version
+ print col.Color(col.RED, str)
for version in changes_copy:
str = 'Change log for unknown version v%d' % version
print col.Color(col.RED, str)
projects / karo-tx-uboot.git / commitdiff