{
/* Address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
+
+ if (ctrlc() || (wrsr & WRSR_TOUT)) {
+ printf("CTRL-C detected; Skipping boot critical setup\n");
+ return 1;
+ }
return 0;
}
},
};
- #define to_tx51_esdhc_cfg(p) container_of(p, struct tx51_esdhc_cfg, cfg)
+ static inline struct tx51_esdhc_cfg *to_tx51_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
+ {
+ return container_of(cfg, struct tx51_esdhc_cfg, cfg);
+ }
int board_mmc_getcd(struct mmc *mmc)
{
struct tx51_esdhc_cfg *cfg = &tx51_esdhc_cfg[i];
int ret;
- if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
- break;
-
imx_iomux_v3_setup_multiple_pads(cfg->pads,
cfg->num_pads);
cfg->cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
- fsl_esdhc_initialize(bis, &cfg->cfg);
-
ret = gpio_request_one(cfg->cd_gpio,
GPIOF_INPUT, "MMC CD");
if (ret) {
continue;
}
+ debug("%s: Initializing MMC slot %d\n", __func__, i);
+ fsl_esdhc_initialize(bis, &cfg->cfg);
+
mmc = find_mmc_device(i);
if (mmc == NULL)
continue;
ret = cpu_eth_init(bis);
if (ret)
printf("cpu_eth_init() failed: %d\n", ret);
+
return ret;
}
#endif /* CONFIG_FEC_MXC */
};
#ifdef CONFIG_LCD
+ static u16 tx51_cmap[256];
vidinfo_t panel_info = {
/* set to max. size supported by SoC */
.vl_col = 1600,
.vl_row = 1200,
.vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
+ .cmap = tx51_cmap,
};
static struct fb_videomode tx51_fb_modes[] = {
};
static int lcd_enabled = 1;
+static int lcd_bl_polarity;
+
+static int lcd_backlight_polarity(void)
+{
+ return lcd_bl_polarity;
+}
void lcd_enable(void)
{
udelay(100);
gpio_set_value(TX51_LCD_RST_GPIO, 1);
udelay(300000);
- gpio_set_value(TX51_LCD_BACKLIGHT_GPIO, 0);
+ gpio_set_value(TX51_LCD_BACKLIGHT_GPIO,
+ lcd_backlight_polarity());
}
}
{
if (lcd_enabled) {
debug("Switching LCD off\n");
- gpio_set_value(TX51_LCD_BACKLIGHT_GPIO, 1);
+ gpio_set_value(TX51_LCD_BACKLIGHT_GPIO,
+ !lcd_backlight_polarity());
gpio_set_value(TX51_LCD_RST_GPIO, 0);
gpio_set_value(TX51_LCD_PWR_GPIO, 0);
}
void lcd_ctrl_init(void *lcdbase)
{
int color_depth = 24;
- char *vm;
+ const char *video_mode = karo_get_vmode(getenv("video_mode"));
+ const char *vm;
unsigned long val;
int refresh = 60;
struct fb_videomode *p = &tx51_fb_modes[0];
struct fb_videomode fb_mode;
int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
- int pix_fmt = 0;
+ int pix_fmt;
+ int lcd_bus_width;
ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3;
unsigned long di_clk_rate = 65000000;
return;
}
- if (tstc() || (wrsr & WRSR_TOUT)) {
+ if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
debug("Disabling LCD\n");
lcd_enabled = 0;
setenv("splashimage", NULL);
}
karo_fdt_move_fdt();
+ lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
- vm = getenv("video_mode");
- if (vm == NULL) {
+ if (video_mode == NULL) {
debug("Disabling LCD\n");
lcd_enabled = 0;
return;
}
- if (karo_fdt_get_fb_mode(working_fdt, vm, &fb_mode) == 0) {
+ vm = video_mode;
+ if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
p = &fb_mode;
debug("Using video mode from FDT\n");
vm += strlen(vm);
break;
default:
- if (!pix_fmt) {
- char *tmp;
-
- pix_fmt = IPU_PIX_FMT_RGB24;
- tmp = strchr(vm, ':');
- if (tmp)
- vm = tmp;
- }
if (*vm != '\0')
vm++;
}
p->pixclock = KHZ2PICOS(refresh *
(p->xres + p->left_margin + p->right_margin + p->hsync_len) *
- (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
- / 1000);
+ (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
+ 1000);
debug("Pixel clock set to %lu.%03lu MHz\n",
PICOS2KHZ(p->pixclock) / 1000,
PICOS2KHZ(p->pixclock) % 1000);
if (p != &fb_mode) {
int ret;
- char *modename = getenv("video_mode");
- printf("Creating new display-timing node from '%s'\n",
- modename);
- ret = karo_fdt_create_fb_mode(working_fdt, modename, p);
+ debug("Creating new display-timing node from '%s'\n",
+ video_mode);
+ ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
if (ret)
printf("Failed to create new display-timing node from '%s': %d\n",
- modename, ret);
+ video_mode, ret);
}
gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
ARRAY_SIZE(stk5_lcd_pads));
- debug("Initializing FB driver\n");
- if (!pix_fmt)
+ lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
+ switch (lcd_bus_width) {
+ case 24:
pix_fmt = IPU_PIX_FMT_RGB24;
+ break;
+
+ case 18:
+ pix_fmt = IPU_PIX_FMT_RGB666;
+ break;
+
+ case 16:
+ pix_fmt = IPU_PIX_FMT_RGB565;
+ break;
+ default:
+ lcd_enabled = 0;
+ printf("Invalid LCD bus width: %d\n", lcd_bus_width);
+ return;
+ }
if (karo_load_splashimage(0) == 0) {
int ret;
struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)MXC_CCM_BASE;
static void tx51_set_cpu_clock(void)
{
unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
- int ret;
- if (tstc() || (wrsr & WRSR_TOUT))
+ if (had_ctrlc() || (wrsr & WRSR_TOUT))
return;
if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
return;
- ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK);
- if (ret != 0) {
+ if (mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
+ cpu_clk = mxc_get_clock(MXC_ARM_CLK);
+ printf("CPU clock set to %lu.%03lu MHz\n",
+ cpu_clk / 1000000, cpu_clk / 1000 % 1000);
+ } else {
printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
- return;
}
- printf("CPU clock set to %u.%03u MHz\n",
- mxc_get_clock(MXC_ARM_CLK) / 1000000,
- mxc_get_clock(MXC_ARM_CLK) / 1000 % 1000);
}
static void tx51_init_mac(void)
return;
}
- eth_setenv_enetaddr("ethaddr", mac);
printf("MAC addr from fuse: %pM\n", mac);
+ eth_setenv_enetaddr("ethaddr", mac);
}
int board_late_init(void)
if (!baseboard)
goto exit;
+ printf("Baseboard: %s\n", baseboard);
+
if (strncmp(baseboard, "stk5", 4) == 0) {
- printf("Baseboard: %s\n", baseboard);
if ((strlen(baseboard) == 4) ||
strcmp(baseboard, "stk5-v3") == 0) {
stk5v3_board_init();
exit:
tx51_init_mac();
+
gpio_set_value(TX51_RESET_OUT_GPIO, 1);
+ clear_ctrlc();
return ret;
}
#ifdef CONFIG_FDT_FIXUP_PARTITIONS
#include <jffs2/jffs2.h>
#include <mtd_node.h>
- struct node_info nodes[] = {
+ static struct node_info nodes[] = {
{ "fsl,imx51-nand", MTD_DEV_TYPE_NAND, },
};
-
#else
#define fdt_fixup_mtdparts(b,n,c) do { } while (0)
#endif
void ft_board_setup(void *blob, bd_t *bd)
{
+ const char *video_mode = karo_get_vmode(getenv("video_mode"));
+ int ret;
+
+ ret = fdt_increase_size(blob, 4096);
+ if (ret)
+ printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
+
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
fdt_fixup_ethernet(blob);
karo_fdt_fixup_touchpanel(blob, tx51_touchpanels,
ARRAY_SIZE(tx51_touchpanels));
- karo_fdt_fixup_usb_otg(blob, "fsl,imx-otg", "fsl,usbphy");
- karo_fdt_update_fb_mode(blob, getenv("video_mode"));
+ karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy");
+ karo_fdt_update_fb_mode(blob, video_mode);
}
- #endif
+ #endif /* CONFIG_OF_BOARD_SETUP */
/*
- * Copyright (C) 2012 <LW@KARO-electronics.de>
+ * Copyright (C) 2012-2014 <LW@KARO-electronics.de>
*
* SPDX-License-Identifier: GPL-2.0
*
#endif /* CONFIG_LCD */
/*
- * Memory configurations
+ * Memory configuration options
*/
#ifndef CONFIG_SYS_SDRAM_CLK
#define CONFIG_SYS_SDRAM_CLK 166
#if CONFIG_NR_DRAM_BANKS > 1
#define PHYS_SDRAM_2 0x98000000 /* Base address of bank 2 */
#define PHYS_SDRAM_2_SIZE SZ_128M
- #else
- #define TX51_MOD_SUFFIX "0"
#endif
#define CONFIG_STACKSIZE SZ_128K
#define CONFIG_SYS_MALLOC_LEN SZ_8M
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* Memtest start address */
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + SZ_4M) /* 4 MB RAM test */
- #if CONFIG_SYS_SDRAM_CLK == 200
- #define CONFIG_SYS_CLKTL_CBCDR 0x59e35180
- #define TX51_MOD_SUFFIX "1"
- #elif CONFIG_SYS_SDRAM_CLK == 166
+ #define CONFIG_SYS_SDRAM_CLK 166
#define CONFIG_SYS_CLKTL_CBCDR 0x01e35180
- #ifndef TX51_MOD_SUFFIX
- #define TX51_MOD_SUFFIX "2"
- #endif
- #else
- #error Invalid SDRAM clock
- #endif
/*
* U-Boot general configurations
*/
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_DEFAULT_DEVICE_TREE tx51
-#define CONFIG_ARCH_DEVICE_TREE mx51
#define CONFIG_SYS_FDT_ADDR (PHYS_SDRAM_1 + SZ_16M)
/*
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_SYS_AUTOLOAD "no"
#define CONFIG_BOOTFILE "uImage"
- #define CONFIG_BOOTARGS "console=ttymxc0,115200 ro debug panic=1"
- #define CONFIG_BOOTCOMMAND "run bootcmd_nand"
+ #define CONFIG_BOOTARGS "init=/linuxrc console=ttymxc0,115200 ro debug panic=1"
+ #define CONFIG_BOOTCOMMAND "run bootcmd_${boot_mode} bootm_cmd"
#define CONFIG_LOADADDR 94000000
#define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR)
#define CONFIG_U_BOOT_IMG_SIZE SZ_1M
#define CONFIG_HW_WATCHDOG
/*
- * Extra Environments
+ * Extra Environment Settings
*/
+ #define CONFIG_SYS_CPU_CLK_STR xstr(CONFIG_SYS_CPU_CLK)
+
#define CONFIG_EXTRA_ENV_SETTINGS \
"autostart=no\0" \
"baseboard=stk5-v3\0" \
- "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}" \
- " root=/dev/mmcblk0p3 rootwait\0" \
- "bootargs_nand=run default_bootargs;set bootargs ${bootargs}" \
+ "bootargs_jffs2=run default_bootargs;set bootargs ${bootargs}" \
" root=/dev/mtdblock3 rootfstype=jffs2\0" \
- "nfsroot=/tftpboot/rootfs\0" \
+ "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}" \
+ " root=/dev/mmcblk0p2 rootwait\0" \
"bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \
- " root=/dev/nfs ip=dhcp nfsroot=${nfs_server}:${nfsroot},nolock\0"\
- "bootcmd_mmc=set autostart no;run bootargs_mmc;" \
- "mmc read ${loadaddr} 100 3000;run bootm_cmd\0" \
- "bootcmd_nand=set autostart no;run bootargs_nand;" \
- "nboot linux;run bootm_cmd\0" \
- "bootcmd_net=set autostart no;run bootargs_nfs;dhcp;" \
- "run bootm_cmd\0" \
+ " root=/dev/nfs nfsroot=${nfs_server}:${nfsroot},nolock" \
+ " ip=dhcp\0" \
+ "bootargs_ubifs=run default_bootargs;set bootargs ${bootargs}" \
+ " ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs\0" \
+ "bootcmd_jffs2=set autostart no;run bootargs_jffs2" \
+ ";nboot linux\0" \
+ "bootcmd_mmc=set autostart no;run bootargs_mmc" \
+ ";fatload mmc 0 ${loadaddr} uImage\0" \
+ "bootcmd_nand=set autostart no;run bootargs_ubifs" \
+ ";nboot linux\0" \
+ "bootcmd_net=set autoload y;set autostart n;run bootargs_nfs" \
+ ";dhcp\0" \
"bootm_cmd=bootm ${loadaddr} - ${fdtaddr}\0" \
+ "boot_mode=nand\0" \
+ "cpu_clk=" CONFIG_SYS_CPU_CLK_STR "\0" \
"default_bootargs=set bootargs " CONFIG_BOOTARGS \
" ${append_bootargs}\0" \
- "cpu_clk=" xstr(CONFIG_SYS_CPU_CLK) "\0" \
"fdtaddr=91000000\0" \
- "fdtsave=nand erase.part dtb;nand write ${fdtaddr} dtb ${fdtsize}\0" \
+ "fdtsave=nand erase.part dtb" \
+ ";nand write ${fdtaddr} dtb ${fdtsize}\0" \
"mtdids=" MTDIDS_DEFAULT "\0" \
"mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "nfsroot=/tftpboot/rootfs\0" \
"otg_mode=device\0" \
"touchpanel=tsc2007\0" \
"video_mode=VGA\0"
#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
#define CONFIG_MXC_NAND_HWECC
#define CONFIG_CMD_NAND_TRIMFFS
- #define CONFIG_SYS_MAX_FLASH_SECT 1024
- #define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_ENV_SIZE 0x20000 /* 128 KiB */
#define CONFIG_ENV_RANGE 0x60000
#endif
- #ifndef CONFIG_SYS_NO_FLASH
- #define CONFIG_CMD_FLASH
- #define CONFIG_SYS_NAND_BASE 0xa0000000
- #define CONFIG_FIT
- #else
#define CONFIG_SYS_NAND_BASE 0x00000000
#define CONFIG_CMD_ROMUPDATE
- #endif
#endif /* CONFIG_CMD_NAND */
/*
#define CONFIG_GENERIC_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_ESDHC_NUM 2
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_FAT
xstr(CONFIG_ENV_RANGE) \
"(env)," \
xstr(CONFIG_ENV_RANGE) \
- "(env2),4m(linux),16m(rootfs),256k(dtb),?(userfs),512k@0x7f80000(bbt)ro"
+ "(env2),4m(linux),16m(rootfs),108032k(userfs),256k(dtb),512k@0x7f80000(bbt)ro"
#else
#define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
"1m(u-boot)," \
xstr(CONFIG_ENV_RANGE) \
- "(env),4m(linux),16m(rootfs),256k(dtb),?(userfs),512k@0x7f80000(bbt)ro"
+ "(env),4m(linux),16m(rootfs),108416k(userfs),256k(dtb),512k@0x7f80000(bbt)ro"
#endif
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1