* Enable NAND flash support for NC650 board.

* Patch by Thomas Lange 07 Oct 2004:
  Updated README for DBAu1x00 boards to match current status

diff --git a/CHANGELOG b/CHANGELOG
index 4edd3e96640bdbfdbad840796037e3da42edeebe..6cded5185aa11caaa2e1c3dfa7a5eaa5ccd5cce1 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,11 @@
 Changes since U-Boot 1.1.1:
 ======================================================================
 
+* Enable NAND flash support for NC650 board.
+
+* Patch by Thomas Lange 07 Oct 2004:
+  Updated README for DBAu1x00 boards to match current status
+
 * Patch by Philippe Robin, 28 Sept 2004:
   Fix Flash support for Versatile.
 

diff --git a/board/dbau1x00/README b/board/dbau1x00/README
index 024fbbe3ec7623e31ddd3fb4722021ed50fdaada..d8f9eccaa5a3e0c95491e21c6f119c523e933b5e 100644 (file)
--- a/board/dbau1x00/README
+++ b/board/dbau1x00/README
@@ -1,30 +1,40 @@
-By Thomas.Lange@corelatus.se 2003-10-06
+By Thomas.Lange@corelatus.se 2004-Oct-05
 ----------------------------------------
-DbAu1000 is a development board from AMD containing
-an Alchemy AU1000 with mips32 core.
+DbAu1xx0 are development boards from AMD containing
+an Alchemy AU1xx0 series cpu with mips32 core.
+Existing cpu:s are Au1000, Au1100, Au1500 and Au1550
 
 Limitations & comments
 ----------------------
-I assume that you set board to BIG endian!
-Little endian not tested, most probably broken.
+Support was originally big endian only.
+I have not tested, but several u-boot users report working
+configurations in little endian mode.
 
 I named the board dbau1x00, to allow
 support for all three development boards
-some day ( dbau1000, dbau1100 and dbau1500 ).
+( dbau1000, dbau1100 and dbau1500 ).
+Now there is a new board called dbau1550 also, which 
+should be supported RSN.
 
-I only have a dbau1000, so all testing is limited
-to this board!
+I only have a dbau1000, so my testing is limited
+to this board.
 
 The board has two different flash banks, that can
 be selected via dip switch. This makes it possible
 to test new bootloaders without thrashing the YAMON
-boot loader deliviered with board.
+boot loader delivered with board.
+
+NOTE! When you switch between the two boot flashes, the
+base addresses will be swapped. 
+Have this in mind when you compile u-boot. TEXT_BASE has
+to match the address where u-boot is located when you 
+actually launch. 
 
 Ethernet only supported for mac0.
 
-Pcmcia only supported for slot 0, only 3.3V.
+PCMCIA only supported for slot 0, only 3.3V.
 
-Pcmcia IDE tested with Sandisk Compact Flash and
+PCMCIA IDE tested with Sandisk Compact Flash and
 IBM microdrive.
 
 ###################################
@@ -32,7 +42,7 @@ IBM microdrive.
 ###################################
 If you partition a disk on another system (e.g. laptop),
 all bytes will be swapped on 16bit level when using
-PCMCIA!!!!
+PCMCIA and running cpu in big endian mode!!!!
 
 This is probably due to an error in Au1000 chip.
 

diff --git a/board/nc650/nc650.c b/board/nc650/nc650.c
index 376dbbdca32d304061bfa6f15a216bf5a9337b04..c2f0c79286d28867e6ee04ccee66abfb2db12bef 100644 (file)
--- a/board/nc650/nc650.c
+++ b/board/nc650/nc650.c
@@ -205,3 +205,13 @@ static long int dram_size (long int mamr_value, long int *base,
 
        return (get_ram_size(base, maxsize));
 }
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+void nand_init(void)
+{
+       unsigned long totlen = nand_probe(CFG_NAND_BASE);
+
+       printf ("%4lu MB\n", totlen >> 20);
+}
+#endif
+

diff --git a/include/configs/NC650.h b/include/configs/NC650.h
index 48bea694df302cd3fed16b7a77af90952e6391b4..8f52014a44ac9948d882a5fbc9824d23b2ce336c 100644 (file)
--- a/include/configs/NC650.h
+++ b/include/configs/NC650.h
@@ -96,8 +96,8 @@
 /*
  * Software (bit-bang) I2C driver configuration
  */
-#define SCL            0x10000000      /* PA 3 */
-#define SDA            0x40000000      /* PA 1 */
+#define SCL            0x1000          /* PA 3 */
+#define SDA            0x2000          /* PA 2 */
 
 #define PAR            immr->im_ioport.iop_papar
 #define DIR            immr->im_ioport.iop_padir
@@ -111,19 +111,16 @@
                        else DAT &= ~SDA
 #define I2C_SCL(bit)   if (bit) DAT |=  SCL; \
                        else DAT &= ~SCL
-#define I2C_DELAY      udelay(50)      /* 1/4 I2C clock duration */
+#define I2C_DELAY      udelay(5)       /* 1/4 I2C clock duration */
 
-#define CFG_I2C_EEPROM_ADDR            0x50
-#define CFG_I2C_EEPROM_ADDR_LEN                1
-#define CFG_EEPROM_PAGE_WRITE_BITS     4       /* 16 bytes page write mode */
-
-#define        CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
+#define CONFIG_RTC_PCF8563
+#define CFG_I2C_RTC_ADDR               0x51
 
 #define CONFIG_COMMANDS              ( CONFIG_CMD_DFL  | \
                                CFG_CMD_ASKENV  | \
                                CFG_CMD_DHCP    | \
-                               CFG_CMD_EEPROM  | \
                                CFG_CMD_I2C     | \
+                               CFG_CMD_NAND    | \
                                CFG_CMD_DATE    )
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
@@ -216,6 +213,31 @@
 #define CFG_CACHELINE_SHIFT    4       /* log base 2 of the above value        */
 #endif
 
+/*
+ * NAND flash support
+ */
+#define CFG_MAX_NAND_DEVICE    1
+#define NAND_ChipID_UNKNOWN    0x00
+#define SECTORSIZE             512
+#define NAND_MAX_FLOORS                1
+#define NAND_MAX_CHIPS         1
+#define ADDR_PAGE              2
+#define ADDR_COLUMN_PAGE       3
+#define ADDR_COLUMN            1
+#define NAND_NO_RB
+
+#define NAND_WAIT_READY(nand)          udelay(12)
+#define WRITE_NAND_COMMAND(d, adr)     WRITE_NAND(d, adr + 2)
+#define WRITE_NAND_ADDRESS(d, adr)     WRITE_NAND(d, adr + 1)
+#define WRITE_NAND(d, adr)             (*(volatile uint8_t *)(adr) = (uint8_t)(d))
+#define READ_NAND(adr)                 (*(volatile uint8_t *)(adr))
+#define NAND_DISABLE_CE(nand)          /* nop */
+#define NAND_ENABLE_CE(nand)           /* nop */
+#define NAND_CTL_CLRALE(nandptr)       /* nop */
+#define NAND_CTL_SETALE(nandptr)       /* nop */
+#define NAND_CTL_CLRCLE(nandptr)       /* nop */
+#define NAND_CTL_SETCLE(nandptr)       /* nop */
+
 /*-----------------------------------------------------------------------
  * SYPCR - System Protection Control                                   11-9
  * SYPCR can only be written once after reset!
@@ -286,6 +308,18 @@
 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
 
+/*
+ * BR2 and OR2 (NAND Flash)
+ */
+#define CFG_NAND_BASE          0x50000000
+#define CFG_NAND_SIZE          0x04000000
+
+#define CFG_OR_TIMING_NAND     (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
+                                OR_SCY_15_CLK | OR_EHTR | OR_TRLX)
+
+#define CFG_BR2_PRELIM  ((CFG_NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
+#define CFG_OR2_PRELIM  (((-CFG_NAND_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_NAND)
+
 /*
  * BR3 and OR3 (SDRAM)
  */