Add PCI support for MPC8250 Boards (PM825 module)

diff --git a/CHANGELOG b/CHANGELOG
index 35a6e4a95982da76f8251db704b67c5fd8c8a2d9..b80fed3b5c4fb0132de61cc5bd837cbc8593a646 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,8 @@
 Changes since U-Boot 0.2.2:
 ======================================================================
 
 Changes since U-Boot 0.2.2:
 ======================================================================
 

+* Add PCI support for MPC8250 Boards (PM825 module)
+

 * Patch by Stefan Roese, 25 Mar 2003:
   - PCI405 update.
 
 * Patch by Stefan Roese, 25 Mar 2003:
   - PCI405 update.
 

diff --git a/board/pm826/pm826.c b/board/pm826/pm826.c
index 3ba8ca990dee737b6a6ada0e0a0bcea1f668b93d..926d74bdd64e44c434b41d561abbecd1205b0bee 100644 (file)
--- a/board/pm826/pm826.c
+++ b/board/pm826/pm826.c
@@ -24,6 +24,7 @@
 #include <common.h>
 #include <ioports.h>
 #include <mpc8260.h>
 #include <common.h>
 #include <ioports.h>
 #include <mpc8260.h>

+#include <pci.h>

 
 /*
  * I/O Port configuration table
 
 /*
  * I/O Port configuration table


@@ -349,3 +350,12 @@ void doc_init (void)
        doc_probe (CFG_DOC_BASE);
 }
 #endif
        doc_probe (CFG_DOC_BASE);
 }
 #endif

+
+struct pci_controller hose;
+
+extern void pci_mpc8250_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+       pci_mpc8250_init(&hose);
+}

diff --git a/common/cmd_boot.c b/common/cmd_boot.c
index 93ab10f3af1e718dffd1b86f37cd35353af90fbf..2604e41bfaff2d9c148deab69e2c65c51c4e04ce 100644 (file)
--- a/common/cmd_boot.c
+++ b/common/cmd_boot.c
@@ -50,6 +50,7 @@ static void print_num(const char *, ulong);
 
 #ifndef CONFIG_ARM     /* PowerPC and other */
 
 
 #ifndef CONFIG_ARM     /* PowerPC and other */
 

+#ifdef CONFIG_PPC

 static void print_str(const char *, const char *);
 
 int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 static void print_str(const char *, const char *);
 
 int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])


@@ -110,6 +111,34 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
        return 0;
 }
 
        return 0;
 }
 

+#else /* MIPS */
+
+int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+       DECLARE_GLOBAL_DATA_PTR;
+
+       int i;
+       bd_t *bd = gd->bd;
+
+       print_num ("boot_params",       (ulong)bd->bi_boot_params);
+       print_num ("memstart",          (ulong)bd->bi_memstart);
+       print_num ("memsize",           (ulong)bd->bi_memsize);
+       print_num ("flashstart",        (ulong)bd->bi_flashstart);
+       print_num ("flashsize",         (ulong)bd->bi_flashsize);
+       print_num ("flashoffset",       (ulong)bd->bi_flashoffset);
+
+       printf ("ethaddr     =");
+       for (i=0; i<6; ++i) {
+               printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
+       }
+       printf ("\nip_addr     = ");
+       print_IPaddr (bd->bi_ip_addr);
+       printf ("\nbaudrate    = %d bps\n", bd->bi_baudrate);
+
+       return 0;
+}
+#endif  /* MIPS */
+

 #else  /* ARM */
 
 int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 #else  /* ARM */
 
 int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])


@@ -150,12 +179,12 @@ static void print_num(const char *name, ulong value)
        printf ("%-12s= 0x%08lX\n", name, value);
 }
 
        printf ("%-12s= 0x%08lX\n", name, value);
 }
 

-#ifndef        CONFIG_ARM
+#ifdef CONFIG_PPC

 static void print_str(const char *name, const char *str)
 {
        printf ("%-12s= %6s MHz\n", name, str);
 }
 static void print_str(const char *name, const char *str)
 {
        printf ("%-12s= %6s MHz\n", name, str);
 }

-#endif /* CONFIG_ARM */
+#endif /* CONFIG_PPC */

 
 #endif /* CFG_CMD_BDI */
 
 
 #endif /* CFG_CMD_BDI */
 

diff --git a/cpu/mpc8260/Makefile b/cpu/mpc8260/Makefile
index 80afc96cacbab77c7d0989f067d7167307eea4d6..22d323e21dcd09820ef619e2135bfc54bdd90175 100644 (file)
--- a/cpu/mpc8260/Makefile
+++ b/cpu/mpc8260/Makefile
@@ -28,7 +28,7 @@ LIB   = lib$(CPU).a
 START  = start.o kgdb.o
 OBJS   = traps.o serial_smc.o serial_scc.o cpu.o cpu_init.o speed.o \
          interrupts.o ether_scc.o ether_fcc.o i2c.o commproc.o \
 START  = start.o kgdb.o
 OBJS   = traps.o serial_smc.o serial_scc.o cpu.o cpu_init.o speed.o \
          interrupts.o ether_scc.o ether_fcc.o i2c.o commproc.o \

-         bedbug_603e.o status_led.o
+         bedbug_603e.o status_led.o pci.o

 
 all:   .depend $(START) $(LIB)
 
 
 all:   .depend $(START) $(LIB)
 

diff --git a/cpu/mpc8260/pci.c b/cpu/mpc8260/pci.c
new file mode 100644 (file)
index 0000000..f9f1e27
--- /dev/null
+++ b/cpu/mpc8260/pci.c
@@ -0,0 +1,244 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_PCI
+
+#include <pci.h>
+#include <asm/m8260_pci.h>
+
+/*
+ *   Local->PCI map (from CPU)                             controlled by
+ *   MPC826x master window
+ *
+ *   0x80000000 - 0xBFFFFFFF    Total CPU2PCI space        PCIBR0
+ *                       
+ *   0x80000000 - 0x8FFFFFFF    PCI Mem with prefetch      (Outbound ATU #1)
+ *   0x90000000 - 0x9FFFFFFF    PCI Mem w/o  prefetch      (Outbound ATU #2)
+ *   0xA0000000 - 0xAFFFFFFF    32-bit PCI IO              (Outbound ATU #3)
+ *                      
+ *   PCI->Local map (from PCI)
+ *   MPC826x slave window                                  controlled by
+ *
+ *   0x00000000 - 0x07FFFFFF    MPC826x local memory       (Inbound ATU #1)
+ */
+
+/* 
+ * Slave window that allows PCI masters to access MPC826x local memory. 
+ * This window is set up using the first set of Inbound ATU registers
+ */
+
+#define PCI_SLV_MEM_LOCAL      CFG_SDRAM_BASE          /* Local base */
+#define PCI_SLV_MEM_BUS                0x00000000              /* PCI base */
+#define PICMR0_MASK_ATTRIB     (PICMR_MASK_512MB | PICMR_ENABLE | \
+                                PICMR_PREFETCH_EN)
+
+/* 
+ * This is the window that allows the CPU to access PCI address space.
+ * It will be setup with the SIU PCIBR0 register. All three PCI master
+ * windows, which allow the CPU to access PCI prefetch, non prefetch,
+ * and IO space (see below), must all fit within this window. 
+ */
+
+#define PCI_MSTR_LOCAL         0x80000000              /* Local base */
+#define PCIMSK0_MASK           PCIMSK_1GB              /* Size of window */
+
+/* 
+ * Master window that allows the CPU to access PCI Memory (prefetch).
+ * This window will be setup with the first set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define PCI_MSTR_MEM_LOCAL     0x80000000          /* Local base */
+#define PCI_MSTR_MEM_BUS       0x80000000          /* PCI base   */
+#define CPU_PCI_MEM_START      PCI_MSTR_MEM_LOCAL
+#define PCI_MSTR_MEM_SIZE      0x10000000          /* 256MB */
+#define POCMR0_MASK_ATTRIB     (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
+
+/* 
+ * Master window that allows the CPU to access PCI Memory (non-prefetch).
+ * This window will be setup with the second set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define PCI_MSTR_MEMIO_LOCAL    0x90000000          /* Local base */
+#define PCI_MSTR_MEMIO_BUS      0x90000000          /* PCI base   */
+#define CPU_PCI_MEMIO_START     PCI_MSTR_MEMIO_LOCAL
+#define PCI_MSTR_MEMIO_SIZE     0x10000000          /* 256MB */
+#define POCMR1_MASK_ATTRIB      (POCMR_MASK_256MB | POCMR_ENABLE)
+
+/* 
+ * Master window that allows the CPU to access PCI IO space.
+ * This window will be setup with the third set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define PCI_MSTR_IO_LOCAL       0xA0000000          /* Local base */
+#define PCI_MSTR_IO_BUS         0xA0000000          /* PCI base   */
+#define CPU_PCI_IO_START        PCI_MSTR_IO_LOCAL
+#define PCI_MSTR_IO_SIZE        0x10000000          /* 256MB */
+#define POCMR2_MASK_ATTRIB      (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO)
+
+/* PCI bus configuration registers.
+ */
+
+#define PCI_CLASS_BRIDGE_CTLR  0x06
+
+
+static inline void  pci_outl(u32 addr, u32 data)
+{
+    *(volatile u32 *) addr = cpu_to_le32(data);
+}
+
+void pci_mpc8250_init(struct pci_controller *hose)
+{
+    u16 tempShort;
+    u32 immr_addr = CFG_IMMR;
+    volatile immap_t *immap = (immap_t *) CFG_IMMR;
+    pci_dev_t host_devno = PCI_BDF(0, 0, 0);
+
+    pci_setup_indirect(hose, CFG_IMMR + PCI_CFG_ADDR_REG,
+                                CFG_IMMR + PCI_CFG_DATA_REG);
+
+    /* 
+     * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]), 
+     * and local bus for PCI (SIUMCR [LBPC]).
+     */
+    immap->im_siu_conf.sc_siumcr = 0x00640000;
+
+    /* Make PCI lowest priority */
+    /* Each 4 bits is a device bus request  and the MS 4bits 
+       is highest priority */
+    /* Bus               4bit value 
+          ---               ----------
+       CPM high          0b0000
+       CPM middle        0b0001
+          CPM low           0b0010
+       PCI reguest       0b0011
+       Reserved          0b0100
+       Reserved          0b0101
+       Internal Core     0b0110
+       External Master 1 0b0111
+       External Master 2 0b1000
+       External Master 3 0b1001
+       The rest are reserved */
+    immap->im_siu_conf.sc_ppc_alrh = 0x61207893;
+
+    /* Park bus on core while modifying PCI Bus accesses */
+    immap->im_siu_conf.sc_ppc_acr = 0x6;
+
+    /* 
+     * Set up master window that allows the CPU to access PCI space. This 
+     * window is set up using the first SIU PCIBR registers.
+     */
+    *(volatile unsigned long*)(immr_addr + M8265_PCIMSK0) = PCIMSK0_MASK;
+    *(volatile unsigned long*)(immr_addr + M8265_PCIBR0) =
+           PCI_MSTR_LOCAL | PCIBR_ENABLE;
+
+    /* Release PCI RST (by default the PCI RST signal is held low)  */
+    pci_outl (immr_addr | PCI_GCR_REG, PCIGCR_PCI_BUS_EN);
+
+    /* give it some time */
+    udelay(1000);
+
+    /* 
+     * Set up master window that allows the CPU to access PCI Memory (prefetch) 
+     * space. This window is set up using the first set of Outbound ATU registers.
+     */
+    pci_outl (immr_addr | POTAR_REG0, PCI_MSTR_MEM_BUS >> 12);      /* PCI base */
+    pci_outl (immr_addr | POBAR_REG0, PCI_MSTR_MEM_LOCAL >> 12);    /* Local base */
+    pci_outl (immr_addr | POCMR_REG0, POCMR0_MASK_ATTRIB);    /* Size & attribute */
+
+    /* 
+     * Set up master window that allows the CPU to access PCI Memory (non-prefetch) 
+     * space. This window is set up using the second set of Outbound ATU registers.
+     */
+    pci_outl (immr_addr | POTAR_REG1, PCI_MSTR_MEMIO_BUS >> 12);    /* PCI base */
+    pci_outl (immr_addr | POBAR_REG1, PCI_MSTR_MEMIO_LOCAL >> 12);  /* Local base */
+    pci_outl (immr_addr | POCMR_REG1, POCMR1_MASK_ATTRIB);    /* Size & attribute */
+    
+    /* 
+     * Set up master window that allows the CPU to access PCI IO space. This window
+     * is set up using the third set of Outbound ATU registers.
+     */
+    pci_outl (immr_addr | POTAR_REG2, PCI_MSTR_IO_BUS >> 12);       /* PCI base */
+    pci_outl (immr_addr | POBAR_REG2, PCI_MSTR_IO_LOCAL >> 12);     /* Local base */
+    pci_outl (immr_addr | POCMR_REG2, POCMR2_MASK_ATTRIB);    /* Size & attribute */
+
+    /* 
+     * Set up slave window that allows PCI masters to access MPC826x local memory. 
+     * This window is set up using the first set of Inbound ATU registers
+     */
+    pci_outl (immr_addr | PITAR_REG0, PCI_SLV_MEM_LOCAL >> 12);     /* Local base */
+    pci_outl (immr_addr | PIBAR_REG0, PCI_SLV_MEM_BUS >> 12);       /* PCI base */
+    pci_outl (immr_addr | PICMR_REG0, PICMR0_MASK_ATTRIB);    /* Size & attribute */
+
+     /* See above for description - puts PCI request as highest priority */
+    immap->im_siu_conf.sc_ppc_alrh = 0x03124567;
+
+    /* Park the bus on the PCI */
+    immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
+
+    /* Host mode - specify the bridge as a host-PCI bridge */
+
+    pci_hose_write_config_byte(hose, host_devno, PCI_CLASS_CODE,
+                                  PCI_CLASS_BRIDGE_CTLR);
+
+    /* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */
+    pci_hose_read_config_word(hose, host_devno, PCI_COMMAND, &tempShort);
+    pci_hose_write_config_word(hose, host_devno, PCI_COMMAND,
+                        tempShort | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+
+    hose->first_busno = 0;
+    hose->last_busno = 0xff;
+
+    /* System memory space */
+    pci_set_region(hose->regions + 0,
+                      CFG_SDRAM_BASE,
+                      CFG_SDRAM_BASE,
+                      0x4000000,
+                      PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+    /* PCI memory space */
+    pci_set_region(hose->regions + 1,
+                      PCI_MSTR_MEM_BUS,
+                      PCI_MSTR_MEM_LOCAL,
+                      PCI_MSTR_MEM_SIZE,
+                      PCI_REGION_MEM);
+
+    /* PCI I/O space */
+    pci_set_region(hose->regions + 2,
+                      PCI_MSTR_IO_BUS,
+                      PCI_MSTR_IO_LOCAL,
+                      PCI_MSTR_IO_SIZE,
+                      PCI_REGION_IO);
+
+    hose->region_count = 3;
+
+    pci_register_hose(hose);
+
+    hose->last_busno = pci_hose_scan(hose);
+}
+
+#endif /* CONFIG_PCI */

diff --git a/drivers/pci_indirect.c b/drivers/pci_indirect.c
index 08be082e31e9413c799e2a4a021e777ced3ca5fb..f7b442245199775f87defaae437610d7b7f5a634 100644 (file)
--- a/drivers/pci_indirect.c
+++ b/drivers/pci_indirect.c
@@ -21,15 +21,28 @@
 #define cfg_read(val, addr, type, op)  *val = op((type)(addr))
 #define cfg_write(val, addr, type, op) op((type *)(addr), (val))
 
 #define cfg_read(val, addr, type, op)  *val = op((type)(addr))
 #define cfg_write(val, addr, type, op) op((type *)(addr), (val))
 

+#ifdef CONFIG_PM826

 #define INDIRECT_PCI_OP(rw, size, type, op, mask)                       \
 static int                                                              \
 indirect_##rw##_config_##size(struct pci_controller *hose,              \
                              pci_dev_t dev, int offset, type val)       \
 {                                                                       \
        out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000);    \
 #define INDIRECT_PCI_OP(rw, size, type, op, mask)                       \
 static int                                                              \
 indirect_##rw##_config_##size(struct pci_controller *hose,              \
                              pci_dev_t dev, int offset, type val)       \
 {                                                                       \
        out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000);    \

+       sync();                                                          \

        cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);       \
        return 0;                                                        \
 }
        cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);       \
        return 0;                                                        \
 }

+#else
+#define INDIRECT_PCI_OP(rw, size, type, op, mask)                       \
+static int                                                              \
+indirect_##rw##_config_##size(struct pci_controller *hose,              \
+                             pci_dev_t dev, int offset, type val)       \
+{                                                                       \
+       out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000);    \
+       cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);       \
+       return 0;                                                        \
+}
+#endif

 
 #define INDIRECT_PCI_OP_ERRATA6(rw, size, type, op, mask)               \
 static int                                                              \
 
 #define INDIRECT_PCI_OP_ERRATA6(rw, size, type, op, mask)               \
 static int                                                              \

diff --git a/include/asm-mips/u-boot.h b/include/asm-mips/u-boot.h
index ff189d936769b157c73484d046315077fc5ce016..0de0b4da8a119aa4891d642e46797d021582672d 100644 (file)
--- a/include/asm-mips/u-boot.h
+++ b/include/asm-mips/u-boot.h
@@ -25,19 +25,17 @@
 #define _U_BOOT_H_     1
 
 typedef struct bd_info {
 #define _U_BOOT_H_     1
 
 typedef struct bd_info {

-    int                        bi_baudrate;    /* serial console baudrate */
-    unsigned long      bi_ip_addr;     /* IP Address */
-    unsigned char      bi_enetaddr[6]; /* Ethernet adress */
-    struct environment_s              *bi_env;
-    ulong              bi_arch_number; /* unique id for this board */
-    ulong              bi_boot_params; /* where this board expects params */
-    struct                             /* RAM configuration */
-    {
-       ulong start;
-       ulong size;
-    }                  bi_dram[CONFIG_NR_DRAM_BANKS];
+       int             bi_baudrate;    /* serial console baudrate */
+       unsigned long   bi_ip_addr;     /* IP Address */
+       unsigned char   bi_enetaddr[6]; /* Ethernet adress */
+       unsigned long   bi_arch_number; /* unique id for this board */
+       unsigned long   bi_boot_params; /* where this board expects params */
+       unsigned long   bi_memstart;    /* start of DRAM memory */
+       unsigned long   bi_memsize;     /* size  of DRAM memory in bytes */
+       unsigned long   bi_flashstart;  /* start of FLASH memory */
+       unsigned long   bi_flashsize;   /* size  of FLASH memory */
+       unsigned long   bi_flashoffset; /* reserved area for startup monitor */

 } bd_t;
 } bd_t;

-

 #define bi_env_data bi_env->data
 #define bi_env_crc  bi_env->crc
 
 #define bi_env_data bi_env->data
 #define bi_env_crc  bi_env->crc
 

diff --git a/include/asm-ppc/m8260_pci.h b/include/asm-ppc/m8260_pci.h
new file mode 100644 (file)
index 0000000..2675658
--- /dev/null
+++ b/include/asm-ppc/m8260_pci.h
@@ -0,0 +1,166 @@
+
+#ifndef _PPC_KERNEL_M8260_PCI_H
+#define _PPC_KERNEL_M8260_PCI_H
+
+#define M8265_PCIBR0   0x101ac
+#define M8265_PCIBR1   0x101b0
+#define M8265_PCIMSK0  0x101c4
+#define M8265_PCIMSK1  0x101c8
+
+/* Bit definitions for PCIBR registers */
+
+#define PCIBR_ENABLE        0x00000001
+
+/* Bit definitions for PCIMSK registers */
+
+#define PCIMSK_32KB         0xFFFF8000  /* Size of window, smallest */
+#define PCIMSK_64KB         0xFFFF0000
+#define PCIMSK_128KB        0xFFFE0000
+#define PCIMSK_256KB        0xFFFC0000
+#define PCIMSK_512KB        0xFFF80000
+#define PCIMSK_1MB          0xFFF00000
+#define PCIMSK_2MB          0xFFE00000
+#define PCIMSK_4MB          0xFFC00000
+#define PCIMSK_8MB          0xFF800000
+#define PCIMSK_16MB         0xFF000000
+#define PCIMSK_32MB         0xFE000000
+#define PCIMSK_64MB         0xFC000000
+#define PCIMSK_128MB        0xF8000000
+#define PCIMSK_256MB        0xF0000000
+#define PCIMSK_512MB        0xE0000000
+#define PCIMSK_1GB          0xC0000000  /* Size of window, largest */
+
+
+#define M826X_SCCR_PCI_MODE_EN 0x100
+
+
+/*
+ * Outbound ATU registers (3 sets). These registers control how 60x bus (local) 
+ * addresses are translated to PCI addresses when the MPC826x is a PCI bus 
+ * master (initiator).
+ */
+
+#define POTAR_REG0          0x10800     /* PCI Outbound Translation Addr registers */
+#define POTAR_REG1          0x10818
+#define POTAR_REG2          0x10830
+
+#define POBAR_REG0          0x10808     /* PCI Outbound Base Addr registers */
+#define POBAR_REG1          0x10820
+#define POBAR_REG2          0x10838
+
+#define POCMR_REG0          0x10810     /* PCI Outbound Comparison Mask registers */
+#define POCMR_REG1          0x10828
+#define POCMR_REG2          0x10840
+
+/* Bit definitions for POMCR registers */
+
+#define POCMR_MASK_4KB      0x000FFFFF
+#define POCMR_MASK_8KB      0x000FFFFE
+#define POCMR_MASK_16KB     0x000FFFFC
+#define POCMR_MASK_32KB     0x000FFFF8
+#define POCMR_MASK_64KB     0x000FFFF0
+#define POCMR_MASK_128KB    0x000FFFE0
+#define POCMR_MASK_256KB    0x000FFFC0
+#define POCMR_MASK_512KB    0x000FFF80
+#define POCMR_MASK_1MB      0x000FFF00
+#define POCMR_MASK_2MB      0x000FFE00
+#define POCMR_MASK_4MB      0x000FFC00
+#define POCMR_MASK_8MB      0x000FF800
+#define POCMR_MASK_16MB     0x000FF000
+#define POCMR_MASK_32MB     0x000FE000
+#define POCMR_MASK_64MB     0x000FC000
+#define POCMR_MASK_128MB    0x000F8000
+#define POCMR_MASK_256MB    0x000F0000
+#define POCMR_MASK_512MB    0x000E0000
+#define POCMR_MASK_1GB      0x000C0000
+
+#define POCMR_ENABLE        0x80000000
+#define POCMR_PCI_IO        0x40000000
+#define POCMR_PREFETCH_EN   0x20000000
+
+/* Soft PCI reset */
+
+#define PCI_GCR_REG         0x10880
+
+/* Bit definitions for PCI_GCR registers */
+
+#define PCIGCR_PCI_BUS_EN   0x1
+
+/*
+ * Inbound ATU registers (2 sets). These registers control how PCI addresses 
+ * are translated to 60x bus (local) addresses when the MPC826x is a PCI bus target.
+ */
+
+#define PITAR_REG1          0x108D0
+#define PIBAR_REG1          0x108D8
+#define PICMR_REG1          0x108E0
+#define PITAR_REG0          0x108E8
+#define PIBAR_REG0          0x108F0
+#define PICMR_REG0          0x108F8
+
+/* Bit definitions for PCI Inbound Comparison Mask registers */
+
+#define PICMR_MASK_4KB       0x000FFFFF
+#define PICMR_MASK_8KB       0x000FFFFE
+#define PICMR_MASK_16KB      0x000FFFFC
+#define PICMR_MASK_32KB      0x000FFFF8
+#define PICMR_MASK_64KB      0x000FFFF0
+#define PICMR_MASK_128KB     0x000FFFE0
+#define PICMR_MASK_256KB     0x000FFFC0
+#define PICMR_MASK_512KB     0x000FFF80
+#define PICMR_MASK_1MB       0x000FFF00
+#define PICMR_MASK_2MB       0x000FFE00
+#define PICMR_MASK_4MB       0x000FFC00
+#define PICMR_MASK_8MB       0x000FF800
+#define PICMR_MASK_16MB      0x000FF000
+#define PICMR_MASK_32MB      0x000FE000
+#define PICMR_MASK_64MB      0x000FC000
+#define PICMR_MASK_128MB     0x000F8000
+#define PICMR_MASK_256MB     0x000F0000
+#define PICMR_MASK_512MB     0x000E0000
+#define PICMR_MASK_1GB       0x000C0000
+
+#define PICMR_ENABLE         0x80000000
+#define PICMR_NO_SNOOP_EN    0x40000000
+#define PICMR_PREFETCH_EN    0x20000000
+
+/* PCI error Registers */
+
+#define        PCI_ERROR_STATUS_REG            0x10884
+#define        PCI_ERROR_MASK_REG              0x10888
+#define        PCI_ERROR_CONTROL_REG           0x1088C
+#define PCI_ERROR_ADRS_CAPTURE_REG      0x10890
+#define PCI_ERROR_DATA_CAPTURE_REG      0x10898
+#define PCI_ERROR_CTRL_CAPTURE_REG      0x108A0
+
+/* PCI error Register bit defines */
+
+#define        PCI_ERROR_PCI_ADDR_PAR                  0x00000001
+#define        PCI_ERROR_PCI_DATA_PAR_WR               0x00000002
+#define        PCI_ERROR_PCI_DATA_PAR_RD               0x00000004
+#define        PCI_ERROR_PCI_NO_RSP                    0x00000008
+#define        PCI_ERROR_PCI_TAR_ABT                   0x00000010
+#define        PCI_ERROR_PCI_SERR                      0x00000020
+#define        PCI_ERROR_PCI_PERR_RD                   0x00000040
+#define        PCI_ERROR_PCI_PERR_WR                   0x00000080
+#define        PCI_ERROR_I2O_OFQO                      0x00000100
+#define        PCI_ERROR_I2O_IPQO                      0x00000200
+#define        PCI_ERROR_IRA                           0x00000400
+#define        PCI_ERROR_NMI                           0x00000800
+#define        PCI_ERROR_I2O_DBMC                      0x00001000
+
+/*
+ * Register pair used to generate configuration cycles on the PCI bus
+ * and access the MPC826x's own PCI configuration registers.
+ */
+
+#define PCI_CFG_ADDR_REG     0x10900
+#define PCI_CFG_DATA_REG     0x10904
+
+/* Bus parking decides where the bus control sits when idle */
+/* If modifying memory controllers for PCI park on the core */
+
+#define PPC_ACR_BUS_PARK_CORE 0x6
+#define PPC_ACR_BUS_PARK_PCI  0x3
+
+#endif /* _PPC_KERNEL_M8260_PCI_H */

diff --git a/include/configs/PM826.h b/include/configs/PM826.h
index d95596cadf6b0cfdc4564aac23666f745afebe23..05f7130b2740f960d7e2496ad23ae9793ba0bded 100644 (file)
--- a/include/configs/PM826.h
+++ b/include/configs/PM826.h
@@ -303,6 +303,10 @@
 # define CFG_RAMBOOT
 #endif
 
 # define CFG_RAMBOOT
 #endif
 

+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_EEPRO100
+

 /*
  * Internal Definitions
  *
 /*
  * Internal Definitions
  *