u-boot-dtb.bin: u-boot.bin dts/dt.dtb FORCE
$(call if_changed,cat)
+%.imx: %.bin
+ $(Q)$(MAKE) $(build)=arch/arm/imx-common $@
+
quiet_cmd_copy = COPY $@
cmd_copy = cp $< $@
u-boot.img u-boot.kwb u-boot.pbl: u-boot.bin FORCE
$(call if_changed,mkimage)
-u-boot.imx: u-boot.bin
- $(Q)$(MAKE) $(build)=arch/arm/imx-common $@
-
u-boot.sha1: u-boot.bin
tools/ubsha1 u-boot.bin
u-boot.ais: spl/u-boot-spl.ais u-boot.img FORCE
$(call if_changed,pad_cat)
+u-boot-signed.sb: u-boot.bin spl/u-boot-spl.bin
+ $(Q)$(MAKE) $(build)=arch/arm/cpu/arm926ejs/mxs u-boot-signed.sb
u-boot.sb: u-boot.bin spl/u-boot-spl.bin
$(Q)$(MAKE) $(build)=arch/arm/cpu/arm926ejs/mxs u-boot.sb
CONFIG_ARM_ERRATA_742230
CONFIG_ARM_ERRATA_743622
CONFIG_ARM_ERRATA_751472
+ CONFIG_ARM_ERRATA_794072
+ CONFIG_ARM_ERRATA_761320
If set, the workarounds for these ARM errata are applied early
during U-Boot startup. Note that these options force the
# SPDX-License-Identifier: GPL-2.0+
#
-ifeq ($(CROSS_COMPILE),)
-CROSS_COMPILE := arm-linux-
-endif
-
ifndef CONFIG_STANDALONE_LOAD_ADDR
ifneq ($(CONFIG_OMAP_COMMON),)
CONFIG_STANDALONE_LOAD_ADDR = 0x80300000
ALL-y += SPL
endif
else
+ifeq ($(CONFIG_OF_SEPARATE),y)
+ALL-y += u-boot-dtb.imx
+else
ALL-y += u-boot.imx
endif
endif
+endif
MKIMAGE_TARGET-$(CONFIG_MX23) = mxsimage.mx23.cfg
MKIMAGE_TARGET-$(CONFIG_MX28) = mxsimage.mx28.cfg
+# Generate HAB-capable IVT
+#
+# Note on computing the post-IVT size field value for the U-Boot binary.
+# The value is the result of adding the following:
+# -> The size of U-Boot binary aligned to 64B (u-boot.bin)
+# -> The size of IVT block aligned to 64B (u-boot.ivt)
+# -> The size of U-Boot signature (u-boot.sig), 3904 B
+# -> The 64B hole in front of U-Boot binary for 'struct mxs_spl_data' passing
+#
+quiet_cmd_mkivt_mxs = MXSIVT $@
+cmd_mkivt_mxs = \
+ sz=`expr \`stat -c "%s" $^\` + 64 + 3904 + 128` ; \
+ echo -n "0x402000d1 $2 0 0 0 $3 $4 0 $$sz 0 0 0 0 0 0 0" | \
+ tr -s " " | xargs -d " " -i printf "%08x\n" "{}" | rev | \
+ sed "s/\(.\)\(.\)/\\\\\\\\x\2\1\n/g" | xargs -i printf "{}" >$@
+
+# Align binary to 64B
+quiet_cmd_mkalign_mxs = MXSALGN $@
+cmd_mkalign_mxs = \
+ dd if=$^ of=$@ ibs=64 conv=sync 2>/dev/null && \
+ mv $@ $^
+
+# Assemble the CSF file
+quiet_cmd_mkcsfreq_mxs = MXSCSFR $@
+cmd_mkcsfreq_mxs = \
+ ivt=$(word 1,$^) ; \
+ bin=$(word 2,$^) ; \
+ csf=$(word 3,$^) ; \
+ sed "s@VENDOR@$(VENDOR)@g;s@BOARD@$(BOARD)@g" "$$csf" | \
+ sed '/^\#\#Blocks/ d' > $@ ; \
+ echo " Blocks = $2 0x0 `stat -c '%s' $$bin` \"$$bin\" , \\" >> $@ ; \
+ echo " $3 0x0 0x40 \"$$ivt\"" >> $@
+
+# Sign files
+quiet_cmd_mkcst_mxs = MXSCST $@
+cmd_mkcst_mxs = cst -o $@ < $^ \
+ $(if $(KBUILD_VERBOSE:1=), >/dev/null)
+
+spl/u-boot-spl.ivt: spl/u-boot-spl.bin
+ $(call if_changed,mkalign_mxs)
+ $(call if_changed,mkivt_mxs,$(CONFIG_SPL_TEXT_BASE),\
+ 0x00008000,0x00008040)
+
+u-boot.ivt: u-boot.bin
+ $(call if_changed,mkalign_mxs)
+ $(call if_changed,mkivt_mxs,$(CONFIG_SYS_TEXT_BASE),\
+ 0x40001000,0x40001040)
+
+spl/u-boot-spl.csf: spl/u-boot-spl.ivt spl/u-boot-spl.bin board/$(VENDOR)/$(BOARD)/sign/u-boot-spl.csf
+ $(call if_changed,mkcsfreq_mxs,$(CONFIG_SPL_TEXT_BASE),0x8000)
+
+u-boot.csf: u-boot.ivt u-boot.bin board/$(VENDOR)/$(BOARD)/sign/u-boot.csf
+ $(call if_changed,mkcsfreq_mxs,$(CONFIG_SYS_TEXT_BASE),0x40001000)
+
+%.sig: %.csf
+ $(call if_changed,mkcst_mxs)
+
quiet_cmd_mkimage_mxs = MKIMAGE $@
cmd_mkimage_mxs = $(objtree)/tools/mkimage -n $< -T mxsimage $@ \
$(if $(KBUILD_VERBOSE:1=), >/dev/null)
u-boot.sb: $(src)/$(MKIMAGE_TARGET-y) u-boot.bin spl/u-boot-spl.bin FORCE
$(call if_changed,mkimage_mxs)
+
+u-boot-signed.sb: $(src)/mxsimage-signed.cfg u-boot.ivt u-boot.sig spl/u-boot-spl.ivt spl/u-boot-spl.sig FORCE
+ $(call if_changed,mkimage_mxs)
--- /dev/null
+SECTION 0x0 BOOTABLE
+ TAG LAST
+ LOAD 0x1000 spl/u-boot-spl.bin
+ LOAD 0x8000 spl/u-boot-spl.ivt
+ LOAD 0x8040 spl/u-boot-spl.sig
+ CALL HAB 0x8000 0x0
+ LOAD 0x40002000 u-boot.bin
+ LOAD 0x40001000 u-boot.ivt
+ LOAD 0x40001040 u-boot.sig
+ CALL HAB 0x40001000 0x0
SECTION 0x0 BOOTABLE
TAG LAST
- LOAD 0x0 spl/u-boot-spl.bin
- CALL 0x14 0x0
- LOAD 0x40000100 u-boot.bin
- CALL 0x40000100 0x0
+ LOAD 0x1000 spl/u-boot-spl.bin
+ CALL 0x1000 0x0
+ LOAD 0x40002000 u-boot.bin
+ CALL 0x40002000 0x0
SECTION 0x0 BOOTABLE
TAG LAST
- LOAD 0x0 spl/u-boot-spl.bin
- LOAD IVT 0x8000 0x14
+ LOAD 0x1000 spl/u-boot-spl.bin
+ LOAD IVT 0x8000 0x1000
CALL HAB 0x8000 0x0
- LOAD 0x40000100 u-boot.bin
- LOAD IVT 0x8000 0x40000100
+ LOAD 0x40002000 u-boot.bin
+ LOAD IVT 0x8000 0x40002000
CALL HAB 0x8000 0x0
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
+#include <linux/compiler.h>
#include "mxs_init.h"
+DECLARE_GLOBAL_DATA_PTR;
+static gd_t gdata __section(".data");
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+static bd_t bdata __section(".data");
+#endif
+
/*
* This delay function is intended to be used only in early stage of boot, where
* clock are not set up yet. The timer used here is reset on every boot and
return i;
}
+static void mxs_spl_fixup_vectors(void)
+{
+ /*
+ * Copy our vector table to 0x0, since due to HAB, we cannot
+ * be loaded to 0x0. We want to have working vectoring though,
+ * thus this fixup. Our vectoring table is PIC, so copying is
+ * fine.
+ */
+ extern uint32_t _start;
+ memcpy(0x0, &_start, 0x60);
+}
+
+static void mxs_spl_console_init(void)
+{
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+ gd->bd = &bdata;
+ gd->baudrate = CONFIG_BAUDRATE;
+ serial_init();
+ gd->have_console = 1;
+#endif
+}
+
void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
const iomux_cfg_t *iomux_setup,
const unsigned int iomux_size)
struct mxs_spl_data *data = (struct mxs_spl_data *)
((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
uint8_t bootmode = mxs_get_bootmode_index();
+ gd = &gdata;
+
+ mxs_spl_fixup_vectors();
mxs_iomux_setup_multiple_pads(iomux_setup, iomux_size);
+
+ mxs_spl_console_init();
+
mxs_power_init();
mxs_mem_init();
ENTRY(_start)
SECTIONS
{
- . = 0x00000000;
+ . = CONFIG_SPL_TEXT_BASE;
. = ALIGN(4);
.text :
}
#endif
+#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
void s_init(void)
{
/*
#ifdef CONFIG_SPL_BUILD
save_omap_boot_params();
#endif
-#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
watchdog_disable();
timer_init();
set_uart_mux_conf();
setup_clocks_for_console();
uart_soft_reset();
-#endif
#ifdef CONFIG_NOR_BOOT
gd->baudrate = CONFIG_BAUDRATE;
serial_init();
gd->have_console = 1;
-#else
+#elif defined(CONFIG_SPL_BUILD)
gd = &gdata;
preloader_console_init();
#endif
-#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
prcm_init();
set_mux_conf_regs();
#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
rtc32k_enable();
#endif
sdram_init();
-#endif
}
+#endif
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
start = 4;
count = 2;
break;
+ default:
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return;
}
for (i = start; i < start + count; i++) {
s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
start = 4;
count = 2;
break;
+ default:
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return;
}
for (i = start; i < start + count; i++) {
bank = &gpio1->c4;
bank_ext = NULL;
break;
+ default:
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return -1;
}
if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
debug("SDMMC device %d does not support 8bit mode",
start = 4;
count = 2;
break;
+ default:
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return;
}
for (i = start; i < start + count; i++) {
s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
}
#ifdef CONFIG_OF_CONTROL
+static int exynos4_pinmux_decode_periph_id(const void *blob, int node)
+{
+ int err;
+ u32 cell[3];
+
+ err = fdtdec_get_int_array(blob, node, "interrupts", cell,
+ ARRAY_SIZE(cell));
+ if (err) {
+ debug(" invalid peripheral id\n");
+ return PERIPH_ID_NONE;
+ }
+
+ return cell[1];
+}
+
static int exynos5_pinmux_decode_periph_id(const void *blob, int node)
{
int err;
{
if (cpu_is_exynos5())
return exynos5_pinmux_decode_periph_id(blob, node);
+ else if (cpu_is_exynos4())
+ return exynos4_pinmux_decode_periph_id(blob, node);
else
return PERIPH_ID_NONE;
}
#
obj-y := lowlevel_init.o
-obj-y += misc.o timer.o reset_manager.o system_manager.o
+obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o
obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
--- /dev/null
+/*
+ * Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock_manager.h>
+
+static const struct socfpga_clock_manager *clock_manager_base =
+ (void *)SOCFPGA_CLKMGR_ADDRESS;
+
+#define CLKMGR_BYPASS_ENABLE 1
+#define CLKMGR_BYPASS_DISABLE 0
+#define CLKMGR_STAT_IDLE 0
+#define CLKMGR_STAT_BUSY 1
+#define CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1 0
+#define CLKMGR_BYPASS_PERPLLSRC_SELECT_INPUT_MUX 1
+#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1 0
+#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_INPUT_MUX 1
+
+#define CLEAR_BGP_EN_PWRDN \
+ (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
+ CLKMGR_MAINPLLGRP_VCO_EN_SET(0)| \
+ CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
+
+#define VCO_EN_BASE \
+ (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
+ CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \
+ CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
+
+static inline void cm_wait_for_lock(uint32_t mask)
+{
+ register uint32_t inter_val;
+ do {
+ inter_val = readl(&clock_manager_base->inter) & mask;
+ } while (inter_val != mask);
+}
+
+/* function to poll in the fsm busy bit */
+static inline void cm_wait_for_fsm(void)
+{
+ while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY)
+ ;
+}
+
+/*
+ * function to write the bypass register which requires a poll of the
+ * busy bit
+ */
+static inline void cm_write_bypass(uint32_t val)
+{
+ writel(val, &clock_manager_base->bypass);
+ cm_wait_for_fsm();
+}
+
+/* function to write the ctrl register which requires a poll of the busy bit */
+static inline void cm_write_ctrl(uint32_t val)
+{
+ writel(val, &clock_manager_base->ctrl);
+ cm_wait_for_fsm();
+}
+
+/* function to write a clock register that has phase information */
+static inline void cm_write_with_phase(uint32_t value,
+ uint32_t reg_address, uint32_t mask)
+{
+ /* poll until phase is zero */
+ while (readl(reg_address) & mask)
+ ;
+
+ writel(value, reg_address);
+
+ while (readl(reg_address) & mask)
+ ;
+}
+
+/*
+ * Setup clocks while making no assumptions about previous state of the clocks.
+ *
+ * Start by being paranoid and gate all sw managed clocks
+ * Put all plls in bypass
+ * Put all plls VCO registers back to reset value (bandgap power down).
+ * Put peripheral and main pll src to reset value to avoid glitch.
+ * Delay 5 us.
+ * Deassert bandgap power down and set numerator and denominator
+ * Start 7 us timer.
+ * set internal dividers
+ * Wait for 7 us timer.
+ * Enable plls
+ * Set external dividers while plls are locking
+ * Wait for pll lock
+ * Assert/deassert outreset all.
+ * Take all pll's out of bypass
+ * Clear safe mode
+ * set source main and peripheral clocks
+ * Ungate clocks
+ */
+
+void cm_basic_init(const cm_config_t *cfg)
+{
+ uint32_t start, timeout;
+
+ /* Start by being paranoid and gate all sw managed clocks */
+
+ /*
+ * We need to disable nandclk
+ * and then do another apb access before disabling
+ * gatting off the rest of the periperal clocks.
+ */
+ writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
+ readl(&clock_manager_base->per_pll_en),
+ &clock_manager_base->per_pll_en);
+
+ /* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */
+ writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK |
+ CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK |
+ CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK |
+ CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK |
+ CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK |
+ CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK,
+ &clock_manager_base->main_pll_en);
+
+ writel(0, &clock_manager_base->sdr_pll_en);
+
+ /* now we can gate off the rest of the peripheral clocks */
+ writel(0, &clock_manager_base->per_pll_en);
+
+ /* Put all plls in bypass */
+ cm_write_bypass(
+ CLKMGR_BYPASS_PERPLLSRC_SET(
+ CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) |
+ CLKMGR_BYPASS_SDRPLLSRC_SET(
+ CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) |
+ CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_ENABLE) |
+ CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_ENABLE) |
+ CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_ENABLE));
+
+ /*
+ * Put all plls VCO registers back to reset value.
+ * Some code might have messed with them.
+ */
+ writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE,
+ &clock_manager_base->main_pll_vco);
+ writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE,
+ &clock_manager_base->per_pll_vco);
+ writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE,
+ &clock_manager_base->sdr_pll_vco);
+
+ /*
+ * The clocks to the flash devices and the L4_MAIN clocks can
+ * glitch when coming out of safe mode if their source values
+ * are different from their reset value. So the trick it to
+ * put them back to their reset state, and change input
+ * after exiting safe mode but before ungating the clocks.
+ */
+ writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE,
+ &clock_manager_base->per_pll_src);
+ writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE,
+ &clock_manager_base->main_pll_l4src);
+
+ /* read back for the required 5 us delay. */
+ readl(&clock_manager_base->main_pll_vco);
+ readl(&clock_manager_base->per_pll_vco);
+ readl(&clock_manager_base->sdr_pll_vco);
+
+
+ /*
+ * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
+ * with numerator and denominator.
+ */
+ writel(cfg->main_vco_base | CLEAR_BGP_EN_PWRDN |
+ CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
+ &clock_manager_base->main_pll_vco);
+
+ writel(cfg->peri_vco_base | CLEAR_BGP_EN_PWRDN |
+ CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
+ &clock_manager_base->per_pll_vco);
+
+ writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
+ CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
+ cfg->sdram_vco_base | CLEAR_BGP_EN_PWRDN |
+ CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
+ &clock_manager_base->sdr_pll_vco);
+
+ /*
+ * Time starts here
+ * must wait 7 us from BGPWRDN_SET(0) to VCO_ENABLE_SET(1)
+ */
+ reset_timer();
+ start = get_timer(0);
+ /* timeout in unit of us as CONFIG_SYS_HZ = 1000*1000 */
+ timeout = 7;
+
+ /* main mpu */
+ writel(cfg->mpuclk, &clock_manager_base->main_pll_mpuclk);
+
+ /* main main clock */
+ writel(cfg->mainclk, &clock_manager_base->main_pll_mainclk);
+
+ /* main for dbg */
+ writel(cfg->dbgatclk, &clock_manager_base->main_pll_dbgatclk);
+
+ /* main for cfgs2fuser0clk */
+ writel(cfg->cfg2fuser0clk,
+ &clock_manager_base->main_pll_cfgs2fuser0clk);
+
+ /* Peri emac0 50 MHz default to RMII */
+ writel(cfg->emac0clk, &clock_manager_base->per_pll_emac0clk);
+
+ /* Peri emac1 50 MHz default to RMII */
+ writel(cfg->emac1clk, &clock_manager_base->per_pll_emac1clk);
+
+ /* Peri QSPI */
+ writel(cfg->mainqspiclk, &clock_manager_base->main_pll_mainqspiclk);
+
+ writel(cfg->perqspiclk, &clock_manager_base->per_pll_perqspiclk);
+
+ /* Peri pernandsdmmcclk */
+ writel(cfg->pernandsdmmcclk,
+ &clock_manager_base->per_pll_pernandsdmmcclk);
+
+ /* Peri perbaseclk */
+ writel(cfg->perbaseclk, &clock_manager_base->per_pll_perbaseclk);
+
+ /* Peri s2fuser1clk */
+ writel(cfg->s2fuser1clk, &clock_manager_base->per_pll_s2fuser1clk);
+
+ /* 7 us must have elapsed before we can enable the VCO */
+ while (get_timer(start) < timeout)
+ ;
+
+ /* Enable vco */
+ /* main pll vco */
+ writel(cfg->main_vco_base | VCO_EN_BASE,
+ &clock_manager_base->main_pll_vco);
+
+ /* periferal pll */
+ writel(cfg->peri_vco_base | VCO_EN_BASE,
+ &clock_manager_base->per_pll_vco);
+
+ /* sdram pll vco */
+ writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
+ CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
+ cfg->sdram_vco_base | VCO_EN_BASE,
+ &clock_manager_base->sdr_pll_vco);
+
+ /* L3 MP and L3 SP */
+ writel(cfg->maindiv, &clock_manager_base->main_pll_maindiv);
+
+ writel(cfg->dbgdiv, &clock_manager_base->main_pll_dbgdiv);
+
+ writel(cfg->tracediv, &clock_manager_base->main_pll_tracediv);
+
+ /* L4 MP, L4 SP, can0, and can1 */
+ writel(cfg->perdiv, &clock_manager_base->per_pll_div);
+
+ writel(cfg->gpiodiv, &clock_manager_base->per_pll_gpiodiv);
+
+#define LOCKED_MASK \
+ (CLKMGR_INTER_SDRPLLLOCKED_MASK | \
+ CLKMGR_INTER_PERPLLLOCKED_MASK | \
+ CLKMGR_INTER_MAINPLLLOCKED_MASK)
+
+ cm_wait_for_lock(LOCKED_MASK);
+
+ /* write the sdram clock counters before toggling outreset all */
+ writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK,
+ &clock_manager_base->sdr_pll_ddrdqsclk);
+
+ writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK,
+ &clock_manager_base->sdr_pll_ddr2xdqsclk);
+
+ writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK,
+ &clock_manager_base->sdr_pll_ddrdqclk);
+
+ writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK,
+ &clock_manager_base->sdr_pll_s2fuser2clk);
+
+ /*
+ * after locking, but before taking out of bypass
+ * assert/deassert outresetall
+ */
+ uint32_t mainvco = readl(&clock_manager_base->main_pll_vco);
+
+ /* assert main outresetall */
+ writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
+ &clock_manager_base->main_pll_vco);
+
+ uint32_t periphvco = readl(&clock_manager_base->per_pll_vco);
+
+ /* assert pheriph outresetall */
+ writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
+ &clock_manager_base->per_pll_vco);
+
+ /* assert sdram outresetall */
+ writel(cfg->sdram_vco_base | VCO_EN_BASE|
+ CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(1),
+ &clock_manager_base->sdr_pll_vco);
+
+ /* deassert main outresetall */
+ writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
+ &clock_manager_base->main_pll_vco);
+
+ /* deassert pheriph outresetall */
+ writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
+ &clock_manager_base->per_pll_vco);
+
+ /* deassert sdram outresetall */
+ writel(CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
+ cfg->sdram_vco_base | VCO_EN_BASE,
+ &clock_manager_base->sdr_pll_vco);
+
+ /*
+ * now that we've toggled outreset all, all the clocks
+ * are aligned nicely; so we can change any phase.
+ */
+ cm_write_with_phase(cfg->ddrdqsclk,
+ (uint32_t)&clock_manager_base->sdr_pll_ddrdqsclk,
+ CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
+
+ /* SDRAM DDR2XDQSCLK */
+ cm_write_with_phase(cfg->ddr2xdqsclk,
+ (uint32_t)&clock_manager_base->sdr_pll_ddr2xdqsclk,
+ CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
+
+ cm_write_with_phase(cfg->ddrdqclk,
+ (uint32_t)&clock_manager_base->sdr_pll_ddrdqclk,
+ CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
+
+ cm_write_with_phase(cfg->s2fuser2clk,
+ (uint32_t)&clock_manager_base->sdr_pll_s2fuser2clk,
+ CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
+
+ /* Take all three PLLs out of bypass when safe mode is cleared. */
+ cm_write_bypass(
+ CLKMGR_BYPASS_PERPLLSRC_SET(
+ CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) |
+ CLKMGR_BYPASS_SDRPLLSRC_SET(
+ CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) |
+ CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_DISABLE) |
+ CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_DISABLE) |
+ CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_DISABLE));
+
+ /* clear safe mode */
+ cm_write_ctrl(readl(&clock_manager_base->ctrl) |
+ CLKMGR_CTRL_SAFEMODE_SET(CLKMGR_CTRL_SAFEMODE_MASK));
+
+ /*
+ * now that safe mode is clear with clocks gated
+ * it safe to change the source mux for the flashes the the L4_MAIN
+ */
+ writel(cfg->persrc, &clock_manager_base->per_pll_src);
+ writel(cfg->l4src, &clock_manager_base->main_pll_l4src);
+
+ /* Now ungate non-hw-managed clocks */
+ writel(~0, &clock_manager_base->main_pll_en);
+ writel(~0, &clock_manager_base->per_pll_en);
+ writel(~0, &clock_manager_base->sdr_pll_en);
+}
void spl_board_init(void)
{
#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
+ cm_config_t cm_default_cfg = {
+ /* main group */
+ MAIN_VCO_BASE,
+ CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(
+ CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT),
+ CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(
+ CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT),
+ CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(
+ CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT),
+ CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(
+ CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT),
+ CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(
+ CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT),
+ CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(
+ CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT),
+ CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(
+ CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK) |
+ CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(
+ CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK) |
+ CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(
+ CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK) |
+ CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(
+ CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK),
+ CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(
+ CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK) |
+ CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(
+ CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK),
+ CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(
+ CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK),
+ CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(
+ CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP) |
+ CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(
+ CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP),
+
+ /* peripheral group */
+ PERI_VCO_BASE,
+ CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(
+ CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT),
+ CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(
+ CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT),
+ CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(
+ CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT),
+ CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(
+ CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT),
+ CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(
+ CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT),
+ CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(
+ CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT),
+ CLKMGR_PERPLLGRP_DIV_USBCLK_SET(
+ CONFIG_HPS_PERPLLGRP_DIV_USBCLK) |
+ CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(
+ CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK) |
+ CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(
+ CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK) |
+ CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(
+ CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK),
+ CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(
+ CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK),
+ CLKMGR_PERPLLGRP_SRC_QSPI_SET(
+ CONFIG_HPS_PERPLLGRP_SRC_QSPI) |
+ CLKMGR_PERPLLGRP_SRC_NAND_SET(
+ CONFIG_HPS_PERPLLGRP_SRC_NAND) |
+ CLKMGR_PERPLLGRP_SRC_SDMMC_SET(
+ CONFIG_HPS_PERPLLGRP_SRC_SDMMC),
+
+ /* sdram pll group */
+ SDR_VCO_BASE,
+ CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(
+ CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE) |
+ CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(
+ CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT),
+ CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(
+ CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE) |
+ CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(
+ CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT),
+ CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(
+ CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE) |
+ CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(
+ CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT),
+ CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(
+ CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE) |
+ CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(
+ CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT),
+ };
+
debug("Freezing all I/O banks\n");
/* freeze all IO banks */
sys_mgr_frzctrl_freeze_req();
+ debug("Reconfigure Clock Manager\n");
+ /* reconfigure the PLLs */
+ cm_basic_init(&cm_default_cfg);
+
/* configure the pin muxing through system manager */
sysmgr_pinmux_init();
#endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
mcr p15, 0, r0, c1, c0, 0 @ write system control register
#endif
-#ifdef CONFIG_ARM_ERRATA_742230
+#if (defined(CONFIG_ARM_ERRATA_742230) || defined(CONFIG_ARM_ERRATA_794072))
mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
orr r0, r0, #1 << 4 @ set bit #4
mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
orr r0, r0, #1 << 11 @ set bit #11
mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
#endif
+#ifdef CONFIG_ARM_ERRATA_761320
+ mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
+ orr r0, r0, #1 << 21 @ set bit #21
+ mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
+#endif
mov pc, lr @ back to my caller
ENDPROC(cpu_init_cp15)
obj-y += exceptions.o
obj-y += cache.o
obj-y += tlb.o
-obj-y += gic.o
obj-y += transition.o
* clean and invalidate one level cache.
*
* x0: cache level
- * x1~x9: clobbered
+ * x1: 0 flush & invalidate, 1 invalidate only
+ * x2~x9: clobbered
*/
ENTRY(__asm_flush_dcache_level)
- lsl x1, x0, #1
- msr csselr_el1, x1 /* select cache level */
+ lsl x12, x0, #1
+ msr csselr_el1, x12 /* select cache level */
isb /* sync change of cssidr_el1 */
mrs x6, ccsidr_el1 /* read the new cssidr_el1 */
and x2, x6, #7 /* x2 <- log2(cache line size)-4 */
add x2, x2, #4 /* x2 <- log2(cache line size) */
mov x3, #0x3ff
and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */
- add w4, w3, w3
- sub w4, w4, 1 /* round up log2(#ways + 1) */
- clz w5, w4 /* bit position of #ways */
+ clz w5, w3 /* bit position of #ways */
mov x4, #0x7fff
and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */
- /* x1 <- cache level << 1 */
+ /* x12 <- cache level << 1 */
/* x2 <- line length offset */
/* x3 <- number of cache ways - 1 */
/* x4 <- number of cache sets - 1 */
mov x6, x3 /* x6 <- working copy of #ways */
loop_way:
lsl x7, x6, x5
- orr x9, x1, x7 /* map way and level to cisw value */
+ orr x9, x12, x7 /* map way and level to cisw value */
lsl x7, x4, x2
orr x9, x9, x7 /* map set number to cisw value */
- dc cisw, x9 /* clean & invalidate by set/way */
- subs x6, x6, #1 /* decrement the way */
+ tbz w1, #0, 1f
+ dc isw, x9
+ b 2f
+1: dc cisw, x9 /* clean & invalidate by set/way */
+2: subs x6, x6, #1 /* decrement the way */
b.ge loop_way
subs x4, x4, #1 /* decrement the set */
b.ge loop_set
ENDPROC(__asm_flush_dcache_level)
/*
- * void __asm_flush_dcache_all(void)
+ * void __asm_flush_dcache_all(int invalidate_only)
+ *
+ * x0: 0 flush & invalidate, 1 invalidate only
*
* clean and invalidate all data cache by SET/WAY.
*/
-ENTRY(__asm_flush_dcache_all)
+ENTRY(__asm_dcache_all)
+ mov x1, x0
dsb sy
mrs x10, clidr_el1 /* read clidr_el1 */
lsr x11, x10, #24
/* x15 <- return address */
loop_level:
- lsl x1, x0, #1
- add x1, x1, x0 /* x0 <- tripled cache level */
- lsr x1, x10, x1
- and x1, x1, #7 /* x1 <- cache type */
- cmp x1, #2
+ lsl x12, x0, #1
+ add x12, x12, x0 /* x0 <- tripled cache level */
+ lsr x12, x10, x12
+ and x12, x12, #7 /* x12 <- cache type */
+ cmp x12, #2
b.lt skip /* skip if no cache or icache */
- bl __asm_flush_dcache_level
+ bl __asm_flush_dcache_level /* x1 = 0 flush, 1 invalidate */
skip:
add x0, x0, #1 /* increment cache level */
cmp x11, x0
finished:
ret
+ENDPROC(__asm_dcache_all)
+
+ENTRY(__asm_flush_dcache_all)
+ mov x16, lr
+ mov x0, #0
+ bl __asm_dcache_all
+ mov lr, x16
+ ret
ENDPROC(__asm_flush_dcache_all)
+ENTRY(__asm_invalidate_dcache_all)
+ mov x16, lr
+ mov x0, #0xffff
+ bl __asm_dcache_all
+ mov lr, x16
+ ret
+ENDPROC(__asm_invalidate_dcache_all)
+
/*
* void __asm_flush_dcache_range(start, end)
*
/* load TTBR0 */
el = current_el();
- if (el == 1)
+ if (el == 1) {
asm volatile("msr ttbr0_el1, %0"
: : "r" (gd->arch.tlb_addr) : "memory");
- else if (el == 2)
+ asm volatile("msr tcr_el1, %0"
+ : : "r" (TCR_FLAGS | TCR_EL1_IPS_BITS)
+ : "memory");
+ asm volatile("msr mair_el1, %0"
+ : : "r" (MEMORY_ATTRIBUTES) : "memory");
+ } else if (el == 2) {
asm volatile("msr ttbr0_el2, %0"
: : "r" (gd->arch.tlb_addr) : "memory");
- else
+ asm volatile("msr tcr_el2, %0"
+ : : "r" (TCR_FLAGS | TCR_EL2_IPS_BITS)
+ : "memory");
+ asm volatile("msr mair_el2, %0"
+ : : "r" (MEMORY_ATTRIBUTES) : "memory");
+ } else {
asm volatile("msr ttbr0_el3, %0"
: : "r" (gd->arch.tlb_addr) : "memory");
+ asm volatile("msr tcr_el3, %0"
+ : : "r" (TCR_FLAGS | TCR_EL2_IPS_BITS)
+ : "memory");
+ asm volatile("msr mair_el3, %0"
+ : : "r" (MEMORY_ATTRIBUTES) : "memory");
+ }
/* enable the mmu */
set_sctlr(get_sctlr() | CR_M);
*/
void invalidate_dcache_all(void)
{
- __asm_flush_dcache_all();
+ __asm_invalidate_dcache_all();
}
/*
void icache_enable(void)
{
+ __asm_invalidate_icache_all();
set_sctlr(get_sctlr() | CR_I);
}
+++ /dev/null
-/*
- * GIC Initialization Routines.
- *
- * (C) Copyright 2013
- * David Feng <fenghua@phytium.com.cn>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <linux/linkage.h>
-#include <asm/macro.h>
-#include <asm/gic.h>
-
-
-/*************************************************************************
- *
- * void gic_init(void) __attribute__((weak));
- *
- * Currently, this routine only initialize secure copy of GIC
- * with Security Extensions at EL3.
- *
- *************************************************************************/
-WEAK(gic_init)
- branch_if_slave x0, 2f
-
- /* Initialize Distributor and SPIs */
- ldr x1, =GICD_BASE
- mov w0, #0x3 /* EnableGrp0 | EnableGrp1 */
- str w0, [x1, GICD_CTLR] /* Secure GICD_CTLR */
- ldr w0, [x1, GICD_TYPER]
- and w2, w0, #0x1f /* ITLinesNumber */
- cbz w2, 2f /* No SPIs */
- add x1, x1, (GICD_IGROUPRn + 4)
- mov w0, #~0 /* Config SPIs as Grp1 */
-1: str w0, [x1], #0x4
- sub w2, w2, #0x1
- cbnz w2, 1b
-
- /* Initialize SGIs and PPIs */
-2: ldr x1, =GICD_BASE
- mov w0, #~0 /* Config SGIs and PPIs as Grp1 */
- str w0, [x1, GICD_IGROUPRn] /* GICD_IGROUPR0 */
- mov w0, #0x1 /* Enable SGI 0 */
- str w0, [x1, GICD_ISENABLERn]
-
- /* Initialize Cpu Interface */
- ldr x1, =GICC_BASE
- mov w0, #0x1e7 /* Disable IRQ/FIQ Bypass & */
- /* Enable Ack Group1 Interrupt & */
- /* EnableGrp0 & EnableGrp1 */
- str w0, [x1, GICC_CTLR] /* Secure GICC_CTLR */
-
- mov w0, #0x1 << 7 /* Non-Secure access to GICC_PMR */
- str w0, [x1, GICC_PMR]
-
- ret
-ENDPROC(gic_init)
-
-
-/*************************************************************************
- *
- * void gic_send_sgi(u64 sgi) __attribute__((weak));
- *
- *************************************************************************/
-WEAK(gic_send_sgi)
- ldr x1, =GICD_BASE
- mov w2, #0x8000
- movk w2, #0x100, lsl #16
- orr w2, w2, w0
- str w2, [x1, GICD_SGIR]
- ret
-ENDPROC(gic_send_sgi)
-
-
-/*************************************************************************
- *
- * void wait_for_wakeup(void) __attribute__((weak));
- *
- * Wait for SGI 0 from master.
- *
- *************************************************************************/
-WEAK(wait_for_wakeup)
- ldr x1, =GICC_BASE
-0: wfi
- ldr w0, [x1, GICC_AIAR]
- str w0, [x1, GICC_AEOIR]
- cbnz w0, 0b
- ret
-ENDPROC(wait_for_wakeup)
-
-
-/*************************************************************************
- *
- * void smp_kick_all_cpus(void) __attribute__((weak));
- *
- *************************************************************************/
-WEAK(smp_kick_all_cpus)
- /* Kick secondary cpus up by SGI 0 interrupt */
- mov x0, xzr /* SGI 0 */
- mov x29, lr /* Save LR */
- bl gic_send_sgi
- mov lr, x29 /* Restore LR */
- ret
-ENDPROC(smp_kick_all_cpus)
*/
adr x0, vectors
switch_el x1, 3f, 2f, 1f
-3: msr vbar_el3, x0
+3: mrs x0, scr_el3
+ orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */
+ msr scr_el3, x0
+ msr vbar_el3, x0
msr cptr_el3, xzr /* Enable FP/SIMD */
ldr x0, =COUNTER_FREQUENCY
msr cntfrq_el0, x0 /* Initialize CNTFRQ */
msr cpacr_el1, x0 /* Enable FP/SIMD */
0:
- /* Cache/BPB/TLB Invalidate */
- bl __asm_flush_dcache_all /* dCache clean&invalidate */
- bl __asm_invalidate_icache_all /* iCache invalidate */
- bl __asm_invalidate_tlb_all /* invalidate TLBs */
+ /*
+ * Cache/BPB/TLB Invalidate
+ * i-cache is invalidated before enabled in icache_enable()
+ * tlb is invalidated before mmu is enabled in dcache_enable()
+ * d-cache is invalidated before enabled in dcache_enable()
+ */
/* Processor specific initialization */
bl lowlevel_init
/*-----------------------------------------------------------------------*/
WEAK(lowlevel_init)
- /* Initialize GIC Secure Bank Status */
mov x29, lr /* Save LR */
- bl gic_init
- branch_if_master x0, x1, 1f
+#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
+ branch_if_slave x0, 1f
+ ldr x0, =GICD_BASE
+ bl gic_init_secure
+1:
+#if defined(CONFIG_GICV3)
+ ldr x0, =GICR_BASE
+ bl gic_init_secure_percpu
+#elif defined(CONFIG_GICV2)
+ ldr x0, =GICD_BASE
+ ldr x1, =GICC_BASE
+ bl gic_init_secure_percpu
+#endif
+#endif
+
+ branch_if_master x0, x1, 2f
/*
* Slave should wait for master clearing spin table.
* This sync prevent salves observing incorrect
* value of spin table and jumping to wrong place.
*/
- bl wait_for_wakeup
+#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
+#ifdef CONFIG_GICV2
+ ldr x0, =GICC_BASE
+#endif
+ bl gic_wait_for_interrupt
+#endif
/*
- * All processors will enter EL2 and optionally EL1.
+ * All slaves will enter EL2 and optionally EL1.
*/
bl armv8_switch_to_el2
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
bl armv8_switch_to_el1
#endif
-1:
+2:
mov lr, x29 /* Restore LR */
ret
ENDPROC(lowlevel_init)
-/*-----------------------------------------------------------------------*/
-
-ENTRY(c_runtime_cpu_setup)
- /* If I-cache is enabled invalidate it */
-#ifndef CONFIG_SYS_ICACHE_OFF
- ic iallu /* I+BTB cache invalidate */
- isb sy
+WEAK(smp_kick_all_cpus)
+ /* Kick secondary cpus up by SGI 0 interrupt */
+ mov x29, lr /* Save LR */
+#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
+ ldr x0, =GICD_BASE
+ bl gic_kick_secondary_cpus
#endif
+ mov lr, x29 /* Restore LR */
+ ret
+ENDPROC(smp_kick_all_cpus)
-#ifndef CONFIG_SYS_DCACHE_OFF
- /*
- * Setup MAIR and TCR.
- */
- ldr x0, =MEMORY_ATTRIBUTES
- ldr x1, =TCR_FLAGS
-
- switch_el x2, 3f, 2f, 1f
-3: orr x1, x1, TCR_EL3_IPS_BITS
- msr mair_el3, x0
- msr tcr_el3, x1
- b 0f
-2: orr x1, x1, TCR_EL2_IPS_BITS
- msr mair_el2, x0
- msr tcr_el2, x1
- b 0f
-1: orr x1, x1, TCR_EL1_IPS_BITS
- msr mair_el1, x0
- msr tcr_el1, x1
-0:
-#endif
+/*-----------------------------------------------------------------------*/
+ENTRY(c_runtime_cpu_setup)
/* Relocate vBAR */
adr x0, vectors
switch_el x1, 3f, 2f, 1f
.dynamic : { *(.dynamic*) }
.plt : { *(.plt*) }
.interp : { *(.interp*) }
+ .gnu.hash : { *(.gnu.hash) }
.gnu : { *(.gnu*) }
.ARM.exidx : { *(.ARM.exidx*) }
.gnu.linkonce.armexidx : { *(.gnu.linkonce.armexidx.*) }
+dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
+ exynos4210-universal_c210.dtb \
+ exynos4210-trats.dtb \
+ exynos4412-trats2.dtb
+
dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
exynos5250-snow.dtb \
exynos5250-smdk5250.dtb \
exynos5420-smdk5420.dtb
+dtb-$(CONFIG_MX6) += imx6q-sabreauto.dtb
dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
tegra20-paz00.dtb \
--- /dev/null
+/*
+ * Samsung's Exynos4 SoC common device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ serial@13800000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x13800000 0x3c>;
+ id = <0>;
+ };
+
+ serial@13810000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x13810000 0x3c>;
+ id = <1>;
+ };
+
+ serial@13820000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x13820000 0x3c>;
+ id = <2>;
+ };
+
+ serial@13830000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x13830000 0x3c>;
+ id = <3>;
+ };
+
+ serial@13840000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x13840000 0x3c>;
+ id = <4>;
+ };
+
+ i2c@13860000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ interrupts = <0 0 0>;
+ };
+
+ i2c@13870000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ interrupts = <1 1 0>;
+ };
+
+ i2c@13880000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ interrupts = <2 2 0>;
+ };
+
+ i2c@13890000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ interrupts = <3 3 0>;
+ };
+
+ i2c@138a0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ interrupts = <4 4 0>;
+ };
+
+ i2c@138b0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ interrupts = <5 5 0>;
+ };
+
+ i2c@138c0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ interrupts = <6 6 0>;
+ };
+
+ i2c@138d0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ interrupts = <7 7 0>;
+ };
+
+ sdhci@12510000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos-mmc";
+ reg = <0x12510000 0x1000>;
+ interrupts = <0 75 0>;
+ };
+
+ sdhci@12520000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos-mmc";
+ reg = <0x12520000 0x1000>;
+ interrupts = <0 76 0>;
+ };
+
+ sdhci@12530000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos-mmc";
+ reg = <0x12530000 0x1000>;
+ interrupts = <0 77 0>;
+ };
+
+ sdhci@12540000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos-mmc";
+ reg = <0x12540000 0x1000>;
+ interrupts = <0 78 0>;
+ };
+
+ gpio: gpio {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
--- /dev/null
+/*
+ * Samsung's Exynos4210 based Origen board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "skeleton.dtsi"
+/include/ "exynos4.dtsi"
+
+/ {
+ model = "Insignal Origen evaluation board based on Exynos4210";
+ compatible = "insignal,origen", "samsung,exynos4210";
+
+ chosen {
+ bootargs ="";
+ };
+
+ aliases {
+ serial0 = "/serial@13800000";
+ console = "/serial@13820000";
+ mmc2 = "sdhci@12530000";
+ };
+
+ sdhci@12510000 {
+ status = "disabled";
+ };
+
+ sdhci@12520000 {
+ status = "disabled";
+ };
+
+ sdhci@12530000 {
+ samsung,bus-width = <4>;
+ samsung,timing = <1 2 3>;
+ cd-gpios = <&gpio 0x2008002 0>;
+ };
+
+ sdhci@12540000 {
+ status = "disabled";
+ };
+};
\ No newline at end of file
--- /dev/null
+/*
+ * Samsung's Exynos4210 based Trats board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "exynos4.dtsi"
+
+/ {
+ model = "Samsung Trats based on Exynos4210";
+ compatible = "samsung,trats", "samsung,exynos4210";
+
+ config {
+ samsung,dsim-device-name = "s6e8ax0";
+ };
+
+ aliases {
+ i2c0 = "/i2c@13860000";
+ i2c1 = "/i2c@13870000";
+ i2c2 = "/i2c@13880000";
+ i2c3 = "/i2c@13890000";
+ i2c4 = "/i2c@138a0000";
+ i2c5 = "/i2c@138b0000";
+ i2c6 = "/i2c@138c0000";
+ i2c7 = "/i2c@138d0000";
+ serial0 = "/serial@13800000";
+ console = "/serial@13820000";
+ mmc0 = "sdhci@12510000";
+ mmc2 = "sdhci@12530000";
+ };
+
+ fimd@11c00000 {
+ compatible = "samsung,exynos-fimd";
+ reg = <0x11c00000 0xa4>;
+
+ samsung,vl-freq = <60>;
+ samsung,vl-col = <720>;
+ samsung,vl-row = <1280>;
+ samsung,vl-width = <720>;
+ samsung,vl-height = <1280>;
+
+ samsung,vl-clkp = <0>;
+ samsung,vl-oep = <0>;
+ samsung,vl-hsp = <1>;
+ samsung,vl-vsp = <1>;
+ samsung,vl-dp = <1>;
+ samsung,vl-bpix = <4>;
+
+ samsung,vl-hspw = <5>;
+ samsung,vl-hbpd = <10>;
+ samsung,vl-hfpd = <10>;
+ samsung,vl-vspw = <2>;
+ samsung,vl-vbpd = <1>;
+ samsung,vl-vfpd = <13>;
+ samsung,vl-cmd-allow-len = <0xf>;
+
+ samsung,winid = <3>;
+ samsung,power-on-delay = <30>;
+ samsung,interface-mode = <1>;
+ samsung,mipi-enabled = <1>;
+ samsung,dp-enabled;
+ samsung,dual-lcd-enabled;
+
+ samsung,logo-on = <1>;
+ samsung,resolution = <0>;
+ samsung,rgb-mode = <0>;
+ };
+
+ mipidsi@11c80000 {
+ compatible = "samsung,exynos-mipi-dsi";
+ reg = <0x11c80000 0x5c>;
+
+ samsung,dsim-config-e-interface = <1>;
+ samsung,dsim-config-e-virtual-ch = <0>;
+ samsung,dsim-config-e-pixel-format = <7>;
+ samsung,dsim-config-e-burst-mode = <1>;
+ samsung,dsim-config-e-no-data-lane = <3>;
+ samsung,dsim-config-e-byte-clk = <0>;
+ samsung,dsim-config-hfp = <1>;
+
+ samsung,dsim-config-p = <3>;
+ samsung,dsim-config-m = <120>;
+ samsung,dsim-config-s = <1>;
+
+ samsung,dsim-config-pll-stable-time = <500>;
+ samsung,dsim-config-esc-clk = <20000000>;
+ samsung,dsim-config-stop-holding-cnt = <0x7ff>;
+ samsung,dsim-config-bta-timeout = <0xff>;
+ samsung,dsim-config-rx-timeout = <0xffff>;
+
+ samsung,dsim-device-id = <0xffffffff>;
+ samsung,dsim-device-bus-id = <0>;
+
+ samsung,dsim-device-reverse-panel = <1>;
+ };
+
+ sdhci@12510000 {
+ samsung,bus-width = <8>;
+ samsung,timing = <1 3 3>;
+ pwr-gpios = <&gpio 0x2008002 0>;
+ };
+
+ sdhci@12520000 {
+ status = "disabled";
+ };
+
+ sdhci@12530000 {
+ samsung,bus-width = <4>;
+ samsung,timing = <1 2 3>;
+ cd-gpios = <&gpio 0x20c6004 0>;
+ };
+
+ sdhci@12540000 {
+ status = "disabled";
+ };
+};
\ No newline at end of file
--- /dev/null
+/*
+ * Samsung's Exynos4210 based Universal C210 board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "exynos4.dtsi"
+
+/ {
+ model = "Samsung Universal C210 based on Exynos4210 rev0";
+ compatible = "samsung,universal_c210", "samsung,exynos4210";
+
+ aliases {
+ serial0 = "/serial@13800000";
+ console = "/serial@13820000";
+ mmc0 = "sdhci@12510000";
+ mmc2 = "sdhci@12530000";
+ };
+
+ sdhci@12510000 {
+ samsung,bus-width = <8>;
+ samsung,timing = <1 3 3>;
+ pwr-gpios = <&gpio 0x2008002 0>;
+ };
+
+ sdhci@12520000 {
+ status = "disabled";
+ };
+
+ sdhci@12530000 {
+ samsung,bus-width = <4>;
+ samsung,timing = <1 2 3>;
+ cd-gpios = <&gpio 0x20c6004 0>;
+ };
+
+ sdhci@12540000 {
+ status = "disabled";
+ };
+
+ fimd@11c00000 {
+ compatible = "samsung,exynos-fimd";
+ reg = <0x11c00000 0xa4>;
+
+ samsung,vl-freq = <60>;
+ samsung,vl-col = <480>;
+ samsung,vl-row = <800>;
+ samsung,vl-width = <480>;
+ samsung,vl-height = <800>;
+
+ samsung,vl-clkp = <0>;
+ samsung,vl-oep = <0>;
+ samsung,vl-hsp = <1>;
+ samsung,vl-vsp = <1>;
+ samsung,vl-dp = <1>;
+ samsung,vl-bpix = <4>;
+
+ samsung,vl-hspw = <2>;
+ samsung,vl-hbpd = <16>;
+ samsung,vl-hfpd = <16>;
+ samsung,vl-vspw = <2>;
+ samsung,vl-vbpd = <8>;
+ samsung,vl-vfpd = <8>;
+ samsung,vl-cmd-allow-len = <0xf>;
+
+ samsung,pclk_name = <1>;
+ samsung,sclk_div = <1>;
+
+ samsung,winid = <0>;
+ samsung,power-on-delay = <10000>;
+ samsung,interface-mode = <1>;
+ samsung,mipi-enabled = <0>;
+ samsung,dp-enabled;
+ samsung,dual-lcd-enabled;
+
+ samsung,logo-on = <1>;
+ samsung,resolution = <0>;
+ samsung,rgb-mode = <0>;
+ };
+};
--- /dev/null
+/*
+ * Samsung's Exynos4412 based Trats2 board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "exynos4.dtsi"
+
+/ {
+ model = "Samsung Trats2 based on Exynos4412";
+ compatible = "samsung,trats2", "samsung,exynos4412";
+
+ config {
+ samsung,dsim-device-name = "s6e8ax0";
+ };
+
+ aliases {
+ i2c0 = "/i2c@13860000";
+ i2c1 = "/i2c@13870000";
+ i2c2 = "/i2c@13880000";
+ i2c3 = "/i2c@13890000";
+ i2c4 = "/i2c@138a0000";
+ i2c5 = "/i2c@138b0000";
+ i2c6 = "/i2c@138c0000";
+ i2c7 = "/i2c@138d0000";
+ serial0 = "/serial@13800000";
+ console = "/serial@13820000";
+ mmc0 = "sdhci@12510000";
+ mmc2 = "sdhci@12530000";
+ };
+
+ i2c@138d0000 {
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-slave-addr = <0x10>;
+ samsung,i2c-max-bus-freq = <100000>;
+ status = "okay";
+
+ max77686_pmic@09 {
+ compatible = "maxim,max77686_pmic";
+ interrupts = <7 0>;
+ reg = <0x09 0 0>;
+ #clock-cells = <1>;
+
+ voltage-regulators {
+ ldo1_reg: ldo1 {
+ regulator-compatible = "LDO1";
+ regulator-name = "VALIVE_1.0V_AP";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo2_reg: ldo2 {
+ regulator-compatible = "LDO2";
+ regulator-name = "VM1M2_1.2V_AP";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo3_reg: ldo3 {
+ regulator-compatible = "LDO3";
+ regulator-name = "VCC_1.8V_AP";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo4_reg: ldo4 {
+ regulator-compatible = "LDO4";
+ regulator-name = "VCC_2.8V_AP";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo5_reg: ldo5 {
+ regulator-compatible = "LDO5";
+ regulator-name = "VCC_1.8V_IO";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo6_reg: ldo6 {
+ regulator-compatible = "LDO6";
+ regulator-name = "VMPLL_1.0V_AP";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo7_reg: ldo7 {
+ regulator-compatible = "LDO7";
+ regulator-name = "VPLL_1.0V_AP";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo8_reg: ldo8 {
+ regulator-compatible = "LDO8";
+ regulator-name = "VMIPI_1.0V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-mem-off;
+ };
+
+ ldo9_reg: ldo9 {
+ regulator-compatible = "LDO9";
+ regulator-name = "CAM_ISP_MIPI_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-mem-idle;
+ };
+
+ ldo10_reg: ldo10 {
+ regulator-compatible = "LDO10";
+ regulator-name = "VMIPI_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-off;
+ };
+
+ ldo11_reg: ldo11 {
+ regulator-compatible = "LDO11";
+ regulator-name = "VABB1_1.95V";
+ regulator-min-microvolt = <1950000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-always-on;
+ regulator-mem-off;
+ };
+
+ ldo12_reg: ldo12 {
+ regulator-compatible = "LDO12";
+ regulator-name = "VUOTG_3.0V";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-mem-off;
+ };
+
+ ldo13_reg: ldo13 {
+ regulator-compatible = "LDO13";
+ regulator-name = "NFC_AVDD_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-idle;
+ };
+
+ ldo14_reg: ldo14 {
+ regulator-compatible = "LDO14";
+ regulator-name = "VABB2_1.95V";
+ regulator-min-microvolt = <1950000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-always-on;
+ regulator-mem-off;
+ };
+
+ ldo15_reg: ldo15 {
+ regulator-compatible = "LDO15";
+ regulator-name = "VHSIC_1.0V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-mem-off;
+ };
+
+ ldo16_reg: ldo16 {
+ regulator-compatible = "LDO16";
+ regulator-name = "VHSIC_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-off;
+ };
+
+ ldo17_reg: ldo17 {
+ regulator-compatible = "LDO17";
+ regulator-name = "CAM_SENSOR_CORE_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-mem-idle;
+ };
+
+ ldo18_reg: ldo18 {
+ regulator-compatible = "LDO18";
+ regulator-name = "CAM_ISP_SEN_IO_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-idle;
+ };
+
+ ldo19_reg: ldo19 {
+ regulator-compatible = "LDO19";
+ regulator-name = "VT_CAM_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-idle;
+ };
+
+ ldo20_reg: ldo20 {
+ regulator-compatible = "LDO20";
+ regulator-name = "VDDQ_PRE_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-idle;
+ };
+
+ ldo21_reg: ldo21 {
+ regulator-compatible = "LDO21";
+ regulator-name = "VTF_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-mem-idle;
+ };
+
+ ldo22_reg: ldo22 {
+ regulator-compatible = "LDO22";
+ regulator-name = "VMEM_VDD_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ regulator-mem-off;
+ };
+
+ ldo23_reg: ldo23 {
+ regulator-compatible = "LDO23";
+ regulator-name = "TSP_AVDD_3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-mem-idle;
+ };
+
+ ldo24_reg: ldo24 {
+ regulator-compatible = "LDO24";
+ regulator-name = "TSP_VDD_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-idle;
+ };
+
+ ldo25_reg: ldo25 {
+ regulator-compatible = "LDO25";
+ regulator-name = "LCD_VCC_3.3V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-mem-idle;
+ };
+
+ ldo26_reg: ldo26 {
+ regulator-compatible = "LDO26";
+ regulator-name = "MOTOR_VCC_3.0V";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-mem-idle;
+ };
+
+ buck1_reg: buck1 {
+ regulator-compatible = "BUCK1";
+ regulator-name = "vdd_mif";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-mem-off;
+ };
+
+ buck2_reg: buck2 {
+ regulator-compatible = "BUCK2";
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-mem-off;
+ };
+
+ buck3_reg: buck3 {
+ regulator-compatible = "BUCK3";
+ regulator-name = "vdd_int";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-mem-off;
+ };
+
+ buck4_reg: buck4 {
+ regulator-compatible = "BUCK4";
+ regulator-name = "vdd_g3d";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-mem-off;
+ };
+
+ buck5_reg: buck5 {
+ regulator-compatible = "BUCK5";
+ regulator-name = "VMEM_1.2V_AP";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ buck6_reg: buck6 {
+ regulator-compatible = "BUCK6";
+ regulator-name = "VCC_SUB_1.35V";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ };
+
+ buck7_reg: buck7 {
+ regulator-compatible = "BUCK7";
+ regulator-name = "VCC_SUB_2.0V";
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-always-on;
+ };
+
+ buck8_reg: buck8 {
+ regulator-compatible = "BUCK8";
+ regulator-name = "VMEM_VDDF_3.0V";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ regulator-mem-off;
+ };
+
+ buck9_reg: buck9 {
+ regulator-compatible = "BUCK9";
+ regulator-name = "CAM_ISP_CORE_1.2V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-mem-off;
+ };
+ };
+ };
+ };
+
+ fimd@11c00000 {
+ compatible = "samsung,exynos-fimd";
+ reg = <0x11c00000 0xa4>;
+
+ samsung,vl-freq = <60>;
+ samsung,vl-col = <720>;
+ samsung,vl-row = <1280>;
+ samsung,vl-width = <720>;
+ samsung,vl-height = <1280>;
+
+ samsung,vl-clkp = <0>;
+ samsung,vl-oep = <0>;
+ samsung,vl-hsp = <1>;
+ samsung,vl-vsp = <1>;
+ samsung,vl-dp = <1>;
+ samsung,vl-bpix = <4>;
+
+ samsung,vl-hspw = <5>;
+ samsung,vl-hbpd = <10>;
+ samsung,vl-hfpd = <10>;
+ samsung,vl-vspw = <2>;
+ samsung,vl-vbpd = <1>;
+ samsung,vl-vfpd = <13>;
+ samsung,vl-cmd-allow-len = <0xf>;
+
+ samsung,winid = <0>;
+ samsung,power-on-delay = <30>;
+ samsung,interface-mode = <1>;
+ samsung,mipi-enabled = <1>;
+ samsung,dp-enabled;
+ samsung,dual-lcd-enabled;
+
+ samsung,logo-on = <1>;
+ samsung,resolution = <0>;
+ samsung,rgb-mode = <0>;
+ };
+
+ mipidsi@11c80000 {
+ compatible = "samsung,exynos-mipi-dsi";
+ reg = <0x11c80000 0x5c>;
+
+ samsung,dsim-config-e-interface = <1>;
+ samsung,dsim-config-e-virtual-ch = <0>;
+ samsung,dsim-config-e-pixel-format = <7>;
+ samsung,dsim-config-e-burst-mode = <1>;
+ samsung,dsim-config-e-no-data-lane = <3>;
+ samsung,dsim-config-e-byte-clk = <0>;
+ samsung,dsim-config-hfp = <1>;
+
+ samsung,dsim-config-p = <3>;
+ samsung,dsim-config-m = <120>;
+ samsung,dsim-config-s = <1>;
+
+ samsung,dsim-config-pll-stable-time = <500>;
+ samsung,dsim-config-esc-clk = <20000000>;
+ samsung,dsim-config-stop-holding-cnt = <0x7ff>;
+ samsung,dsim-config-bta-timeout = <0xff>;
+ samsung,dsim-config-rx-timeout = <0xffff>;
+
+ samsung,dsim-device-id = <0xffffffff>;
+ samsung,dsim-device-bus-id = <0>;
+
+ samsung,dsim-device-reverse-panel = <1>;
+ };
+
+ sdhci@12510000 {
+ samsung,bus-width = <8>;
+ samsung,timing = <1 3 3>;
+ pwr-gpios = <&gpio 0x2004002 0>;
+ };
+
+ sdhci@12520000 {
+ status = "disabled";
+ };
+
+ sdhci@12530000 {
+ samsung,bus-width = <4>;
+ samsung,timing = <1 2 3>;
+ cd-gpios = <&gpio 0x20C6004 0>;
+ };
+
+ sdhci@12540000 {
+ status = "disabled";
+ };
+};
--- /dev/null
+/*
+ + * Copyright 2012 Freescale Semiconductor, Inc.
+ + * Copyright 2011 Linaro Ltd.
+ + *
+ + * SPDX-License-Identifier: GPL-2.0+
+ + */
+
+/dts-v1/;
+
+/ {
+ model = "Freescale i.MX6 Quad SABRE Automotive Board";
+ compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
+};
u-boot.imx: u-boot.bin $(IMX_CONFIG) FORCE
$(call if_changed,mkimage)
+ifeq ($(CONFIG_OF_SEPARATE),y)
+MKIMAGEFLAGS_u-boot-dtb.imx = -n $(filter-out $< $(PHONY),$^) -T imximage \
+ -e $(CONFIG_SYS_TEXT_BASE)
+
+u-boot-dtb.imx: u-boot-dtb.bin $(IMX_CONFIG) FORCE
+ $(call if_changed,mkimage)
+endif
+
MKIMAGEFLAGS_SPL = -n $(filter-out $< $(PHONY),$^) -T imximage \
-e $(CONFIG_SPL_TEXT_BASE)
*/
int exynos_init(void);
+/*
+ * Exynos board specific changes for
+ * board_early_init_f
+ */
+int exynos_early_init_f(void);
+
+/*
+ * Exynos board specific changes for
+ * board_power_init
+ */
+int exynos_power_init(void);
+
#endif /* EXYNOS_BOARD_H */
#include <linux/list.h>
#include <linux/fb.h>
+#include <lcd.h>
#define PANEL_NAME_SIZE (32)
*lcd_dev);
void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd);
+void exynos_init_dsim_platform_data(vidinfo_t *vid);
/* panel driver init based on mipi dsi interface */
void s6e8ax0_init(void);
+#ifdef CONFIG_OF_CONTROL
+extern int mipi_power(void);
+#endif
#endif /* _DSIM_H */
#define SDHCI_CTRL4_DRIVE_MASK(_x) ((_x) << 16)
#define SDHCI_CTRL4_DRIVE_SHIFT (16)
+#define SDHCI_MAX_HOSTS 4
+
int s5p_sdhci_init(u32 regbase, int index, int bus_width);
static inline int s5p_mmc_init(int index, int bus_width)
return s5p_sdhci_init(base, index, bus_width);
}
+
+#ifdef CONFIG_OF_CONTROL
+int exynos_mmc_init(const void *blob);
+#endif
+
#endif
--- /dev/null
+/*
+ * Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CLOCK_MANAGER_H_
+#define _CLOCK_MANAGER_H_
+
+typedef struct {
+ /* main group */
+ uint32_t main_vco_base;
+ uint32_t mpuclk;
+ uint32_t mainclk;
+ uint32_t dbgatclk;
+ uint32_t mainqspiclk;
+ uint32_t mainnandsdmmcclk;
+ uint32_t cfg2fuser0clk;
+ uint32_t maindiv;
+ uint32_t dbgdiv;
+ uint32_t tracediv;
+ uint32_t l4src;
+
+ /* peripheral group */
+ uint32_t peri_vco_base;
+ uint32_t emac0clk;
+ uint32_t emac1clk;
+ uint32_t perqspiclk;
+ uint32_t pernandsdmmcclk;
+ uint32_t perbaseclk;
+ uint32_t s2fuser1clk;
+ uint32_t perdiv;
+ uint32_t gpiodiv;
+ uint32_t persrc;
+
+ /* sdram pll group */
+ uint32_t sdram_vco_base;
+ uint32_t ddrdqsclk;
+ uint32_t ddr2xdqsclk;
+ uint32_t ddrdqclk;
+ uint32_t s2fuser2clk;
+} cm_config_t;
+
+extern void cm_basic_init(const cm_config_t *cfg);
+
+struct socfpga_clock_manager {
+ u32 ctrl;
+ u32 bypass;
+ u32 inter;
+ u32 intren;
+ u32 dbctrl;
+ u32 stat;
+ u32 _pad_0x18_0x3f[10];
+ u32 mainpllgrp;
+ u32 perpllgrp;
+ u32 sdrpllgrp;
+ u32 _pad_0xe0_0x200[72];
+
+ u32 main_pll_vco;
+ u32 main_pll_misc;
+ u32 main_pll_mpuclk;
+ u32 main_pll_mainclk;
+ u32 main_pll_dbgatclk;
+ u32 main_pll_mainqspiclk;
+ u32 main_pll_mainnandsdmmcclk;
+ u32 main_pll_cfgs2fuser0clk;
+ u32 main_pll_en;
+ u32 main_pll_maindiv;
+ u32 main_pll_dbgdiv;
+ u32 main_pll_tracediv;
+ u32 main_pll_l4src;
+ u32 main_pll_stat;
+ u32 main_pll__pad_0x38_0x40[2];
+
+ u32 per_pll_vco;
+ u32 per_pll_misc;
+ u32 per_pll_emac0clk;
+ u32 per_pll_emac1clk;
+ u32 per_pll_perqspiclk;
+ u32 per_pll_pernandsdmmcclk;
+ u32 per_pll_perbaseclk;
+ u32 per_pll_s2fuser1clk;
+ u32 per_pll_en;
+ u32 per_pll_div;
+ u32 per_pll_gpiodiv;
+ u32 per_pll_src;
+ u32 per_pll_stat;
+ u32 per_pll__pad_0x34_0x40[3];
+
+ u32 sdr_pll_vco;
+ u32 sdr_pll_ctrl;
+ u32 sdr_pll_ddrdqsclk;
+ u32 sdr_pll_ddr2xdqsclk;
+ u32 sdr_pll_ddrdqclk;
+ u32 sdr_pll_s2fuser2clk;
+ u32 sdr_pll_en;
+ u32 sdr_pll_stat;
+};
+
+#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200
+#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080
+#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040
+#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020
+#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010
+#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004
+#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d
+#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d
+#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d
+#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(x) (((x) << 4) & 0x00000070)
+#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(x) (((x) << 7) & 0x00000380)
+#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(x) (((x) << 0) & 0x00000001)
+#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(x) (((x) << 1) & 0x00000002)
+#define CLKMGR_PERPLLGRP_SRC_QSPI_SET(x) (((x) << 4) & 0x00000030)
+#define CLKMGR_PERPLLGRP_SRC_NAND_SET(x) (((x) << 2) & 0x0000000c)
+#define CLKMGR_PERPLLGRP_SRC_SDMMC_SET(x) (((x) << 0) & 0x00000003)
+#define CLKMGR_MAINPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
+#define CLKMGR_MAINPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
+#define CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(x) (((x) << 2) & 0x00000004)
+#define CLKMGR_MAINPLLGRP_VCO_EN_SET(x) (((x) << 1) & 0x00000002)
+#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(x) (((x) << 0) & 0x00000001)
+#define CLKMGR_PERPLLGRP_VCO_PSRC_SET(x) (((x) << 22) & 0x00c00000)
+#define CLKMGR_PERPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
+#define CLKMGR_PERPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(x) (((x) << 25) & 0x7e000000)
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
+#define CLKMGR_SDRPLLGRP_VCO_SSRC_SET(x) (((x) << 22) & 0x00c00000)
+#define CLKMGR_SDRPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
+#define CLKMGR_SDRPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
+#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(x) \
+ (((x) << 0) & 0x000001ff)
+#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_SET(x) \
+ (((x) << 0) & 0x000001ff)
+#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(x) (((x) << 2) & 0x0000000c)
+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(x) (((x) << 0) & 0x00000003)
+#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(x) (((x) << 0) & 0x00000007)
+#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(x) (((x) << 0) & 0x00000003)
+#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(x) (((x) << 2) & 0x0000000c)
+#define CLKMGR_BYPASS_PERPLL_SET(x) (((x) << 3) & 0x00000008)
+#define CLKMGR_BYPASS_SDRPLL_SET(x) (((x) << 1) & 0x00000002)
+#define CLKMGR_BYPASS_MAINPLL_SET(x) (((x) << 0) & 0x00000001)
+#define CLKMGR_PERPLLGRP_DIV_USBCLK_SET(x) (((x) << 0) & 0x00000007)
+#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
+#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(x) (((x) << 6) & 0x000001c0)
+#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(x) (((x) << 9) & 0x00000e00)
+#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100
+#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080
+#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040
+#define CLKMGR_CTRL_SAFEMODE_MASK 0x00000001
+#define CLKMGR_CTRL_SAFEMODE_SET(x) (((x) << 0) & 0x00000001)
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
+#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
+#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x00ffffff)
+#define CLKMGR_BYPASS_PERPLLSRC_SET(x) (((x) << 4) & 0x00000010)
+#define CLKMGR_BYPASS_SDRPLLSRC_SET(x) (((x) << 2) & 0x00000004)
+#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015
+#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000
+#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
+#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
+#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x001ffe00
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x001ffe00
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x001ffe00
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x001ffe00
+#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
+#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
+#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff
+
+#define MAIN_VCO_BASE \
+ (CLKMGR_MAINPLLGRP_VCO_DENOM_SET(CONFIG_HPS_MAINPLLGRP_VCO_DENOM) | \
+ CLKMGR_MAINPLLGRP_VCO_NUMER_SET(CONFIG_HPS_MAINPLLGRP_VCO_NUMER))
+
+#define PERI_VCO_BASE \
+ (CLKMGR_PERPLLGRP_VCO_PSRC_SET(CONFIG_HPS_PERPLLGRP_VCO_PSRC) | \
+ CLKMGR_PERPLLGRP_VCO_DENOM_SET(CONFIG_HPS_PERPLLGRP_VCO_DENOM) | \
+ CLKMGR_PERPLLGRP_VCO_NUMER_SET(CONFIG_HPS_PERPLLGRP_VCO_NUMER))
+
+#define SDR_VCO_BASE \
+ (CLKMGR_SDRPLLGRP_VCO_SSRC_SET(CONFIG_HPS_SDRPLLGRP_VCO_SSRC) | \
+ CLKMGR_SDRPLLGRP_VCO_DENOM_SET(CONFIG_HPS_SDRPLLGRP_VCO_DENOM) | \
+ CLKMGR_SDRPLLGRP_VCO_NUMER_SET(CONFIG_HPS_SDRPLLGRP_VCO_NUMER))
+
+#endif /* _CLOCK_MANAGER_H_ */
#define SOCFPGA_UART0_ADDRESS 0xffc02000
#define SOCFPGA_UART1_ADDRESS 0xffc03000
#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
+#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
/* Analog components control digital interface (ANADIG) */
struct anadig_reg {
+ u32 reserved_0x000[4];
u32 pll3_ctrl;
- u32 resv0[3];
+ u32 reserved_0x014[3];
u32 pll7_ctrl;
- u32 resv1[3];
+ u32 reserved_0x024[3];
u32 pll2_ctrl;
- u32 resv2[3];
+ u32 reserved_0x034[3];
u32 pll2_ss;
- u32 resv3[3];
+ u32 reserved_0x044[3];
u32 pll2_num;
- u32 resv4[3];
+ u32 reserved_0x054[3];
u32 pll2_denom;
- u32 resv5[3];
+ u32 reserved_0x064[3];
u32 pll4_ctrl;
- u32 resv6[3];
+ u32 reserved_0x074[3];
u32 pll4_num;
- u32 resv7[3];
+ u32 reserved_0x084[3];
u32 pll4_denom;
+ u32 reserved_0x094[3];
u32 pll6_ctrl;
- u32 resv8[3];
+ u32 reserved_0x0A4[3];
u32 pll6_num;
- u32 resv9[3];
+ u32 reserved_0x0B4[3];
u32 pll6_denom;
- u32 resv10[3];
+ u32 reserved_0x0C4[7];
u32 pll5_ctrl;
- u32 resv11[3];
+ u32 reserved_0x0E4[3];
u32 pll3_pfd;
- u32 resv12[3];
+ u32 reserved_0x0F4[3];
u32 pll2_pfd;
- u32 resv13[3];
+ u32 reserved_0x104[3];
u32 reg_1p1;
- u32 resv14[3];
+ u32 reserved_0x114[3];
u32 reg_3p0;
- u32 resv15[3];
+ u32 reserved_0x124[3];
u32 reg_2p5;
- u32 resv16[7];
+ u32 reserved_0x134[7];
u32 ana_misc0;
- u32 resv17[3];
+ u32 reserved_0x154[3];
u32 ana_misc1;
- u32 resv18[63];
+ u32 reserved_0x164[63];
u32 anadig_digprog;
- u32 resv19[3];
+ u32 reserved_0x264[3];
u32 pll1_ctrl;
- u32 resv20[3];
+ u32 reserved_0x274[3];
u32 pll1_ss;
- u32 resv21[3];
+ u32 reserved_0x284[3];
u32 pll1_num;
- u32 resv22[3];
+ u32 reserved_0x294[3];
u32 pll1_denom;
- u32 resv23[3];
+ u32 reserved_0x2A4[3];
u32 pll1_pdf;
- u32 resv24[3];
+ u32 reserved_0x2B4[3];
u32 pll_lock;
};
#endif
#define CCM_CSCMR2_RMII_CLK_SEL(v) (((v) & 0x3) << 4)
#define CCM_REG_CTRL_MASK 0xffffffff
+#define CCM_CCGR0_UART0_CTRL_MASK (0x3 << 14)
#define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16)
#define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14)
#define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28)
#define CCM_CCGR9_FEC0_CTRL_MASK 0x3
#define CCM_CCGR9_FEC1_CTRL_MASK (0x3 << 2)
+#define ANADIG_PLL5_CTRL_BYPASS (1 << 16)
+#define ANADIG_PLL5_CTRL_ENABLE (1 << 13)
+#define ANADIG_PLL5_CTRL_POWERDOWN (1 << 12)
+#define ANADIG_PLL5_CTRL_DIV_SELECT 1
#define ANADIG_PLL2_CTRL_ENABLE (1 << 13)
#define ANADIG_PLL2_CTRL_POWERDOWN (1 << 12)
#define ANADIG_PLL2_CTRL_DIV_SELECT 1
#define ESDHC0_BASE_ADDR (AIPS1_BASE_ADDR + 0x00031000)
#define ESDHC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000)
#define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x00050000)
+#define ENET1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00051000)
/* MUX mode and PAD ctrl are in one register */
#define CONFIG_IOMUX_SHARE_CONF_REG
enum {
VF610_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTA6__RMII0_CLKOUT = IOMUX_PAD(0x0000, 0x0000, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
VF610_PAD_PTB4__UART1_TX = IOMUX_PAD(0x0068, 0x0068, 2, 0x0380, 0, VF610_UART_PAD_CTRL),
VF610_PAD_PTB5__UART1_RX = IOMUX_PAD(0x006c, 0x006c, 2, 0x037c, 0, VF610_UART_PAD_CTRL),
+ VF610_PAD_PTB10__UART0_TX = IOMUX_PAD(0x0080, 0x0080, 1, __NA_, 0, VF610_UART_PAD_CTRL),
+ VF610_PAD_PTB11__UART0_RX = IOMUX_PAD(0x0084, 0x0084, 1, __NA_, 0, VF610_UART_PAD_CTRL),
VF610_PAD_PTC1__RMII0_MDIO = IOMUX_PAD(0x00b8, 0x00b8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
VF610_PAD_PTC0__RMII0_MDC = IOMUX_PAD(0x00b4, 0x00b4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
VF610_PAD_PTC2__RMII0_CRS_DV = IOMUX_PAD(0x00bc, 0x00bc, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
VF610_PAD_PTC6__RMII0_TD1 = IOMUX_PAD(0x00cc, 0x00cc, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
VF610_PAD_PTC7__RMII0_TD0 = IOMUX_PAD(0x00D0, 0x00D0, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
VF610_PAD_PTC8__RMII0_TXEN = IOMUX_PAD(0x00D4, 0x00D4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTC10__RMII1_MDIO = IOMUX_PAD(0x00dc, 0x00dc, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTC9__RMII1_MDC = IOMUX_PAD(0x00d8, 0x00d8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTC11__RMII1_CRS_DV = IOMUX_PAD(0x00e0, 0x00e0, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTC12__RMII1_RD1 = IOMUX_PAD(0x00e4, 0x00e4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTC13__RMII1_RD0 = IOMUX_PAD(0x00e8, 0x00e8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTC14__RMII1_RXER = IOMUX_PAD(0x00ec, 0x00ec, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTC15__RMII1_TD1 = IOMUX_PAD(0x00f0, 0x00f0, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTC16__RMII1_TD0 = IOMUX_PAD(0x00f4, 0x00f4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTC17__RMII1_TXEN = IOMUX_PAD(0x00f8, 0x00f8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
VF610_PAD_PTA24__ESDHC1_CLK = IOMUX_PAD(0x0038, 0x0038, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
VF610_PAD_PTA25__ESDHC1_CMD = IOMUX_PAD(0x003c, 0x003c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
VF610_PAD_PTA26__ESDHC1_DAT0 = IOMUX_PAD(0x0040, 0x0040, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
#define GICC_IIDR 0x00fc
#define GICC_DIR 0x1000
+/* ReDistributor Registers for Control and Physical LPIs */
+#define GICR_CTLR 0x0000
+#define GICR_IIDR 0x0004
+#define GICR_TYPER 0x0008
+#define GICR_STATUSR 0x0010
+#define GICR_WAKER 0x0014
+#define GICR_SETLPIR 0x0040
+#define GICR_CLRLPIR 0x0048
+#define GICR_SEIR 0x0068
+#define GICR_PROPBASER 0x0070
+#define GICR_PENDBASER 0x0078
+#define GICR_INVLPIR 0x00a0
+#define GICR_INVALLR 0x00b0
+#define GICR_SYNCR 0x00c0
+#define GICR_MOVLPIR 0x0100
+#define GICR_MOVALLR 0x0110
+
+/* ReDistributor Registers for SGIs and PPIs */
+#define GICR_IGROUPRn 0x0080
+#define GICR_ISENABLERn 0x0100
+#define GICR_ICENABLERn 0x0180
+#define GICR_ISPENDRn 0x0200
+#define GICR_ICPENDRn 0x0280
+#define GICR_ISACTIVERn 0x0300
+#define GICR_ICACTIVERn 0x0380
+#define GICR_IPRIORITYRn 0x0400
+#define GICR_ICFGR0 0x0c00
+#define GICR_ICFGR1 0x0c04
+#define GICR_IGROUPMODRn 0x0d00
+#define GICR_NSACRn 0x0e00
+
+/* Cpu Interface System Registers */
+#define ICC_IAR0_EL1 S3_0_C12_C8_0
+#define ICC_IAR1_EL1 S3_0_C12_C12_0
+#define ICC_EOIR0_EL1 S3_0_C12_C8_1
+#define ICC_EOIR1_EL1 S3_0_C12_C12_1
+#define ICC_HPPIR0_EL1 S3_0_C12_C8_2
+#define ICC_HPPIR1_EL1 S3_0_C12_C12_2
+#define ICC_BPR0_EL1 S3_0_C12_C8_3
+#define ICC_BPR1_EL1 S3_0_C12_C12_3
+#define ICC_DIR_EL1 S3_0_C12_C11_1
+#define ICC_PMR_EL1 S3_0_C4_C6_0
+#define ICC_RPR_EL1 S3_0_C12_C11_3
+#define ICC_CTLR_EL1 S3_0_C12_C12_4
+#define ICC_CTLR_EL3 S3_6_C12_C12_4
+#define ICC_SRE_EL1 S3_0_C12_C12_5
+#define ICC_SRE_EL2 S3_4_C12_C9_5
+#define ICC_SRE_EL3 S3_6_C12_C12_5
+#define ICC_IGRPEN0_EL1 S3_0_C12_C12_6
+#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
+#define ICC_IGRPEN1_EL3 S3_6_C12_C12_7
+#define ICC_SEIEN_EL1 S3_0_C12_C13_0
+#define ICC_SGI0R_EL1 S3_0_C12_C11_7
+#define ICC_SGI1R_EL1 S3_0_C12_C11_5
+#define ICC_ASGI1R_EL1 S3_0_C12_C11_6
+
#endif /* __GIC_H__ */
}
void __asm_flush_dcache_all(void);
+void __asm_invalidate_dcache_all(void);
void __asm_flush_dcache_range(u64 start, u64 end);
void __asm_invalidate_tlb_all(void);
void __asm_invalidate_icache_all(void);
obj-y += sections.o
ifdef CONFIG_ARM64
+obj-y += gic_64.o
obj-y += interrupts_64.o
else
obj-y += interrupts.o
"(fake run for tracing)" : "");
bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
#ifdef CONFIG_BOOTSTAGE_FDT
- if (flag == BOOTM_STATE_OS_FAKE_GO)
- bootstage_fdt_add_report();
+ bootstage_fdt_add_report();
#endif
#ifdef CONFIG_BOOTSTAGE_REPORT
bootstage_report();
#ifdef CONFIG_ARM64
smp_kick_all_cpus();
+ flush_dcache_all(); /* flush cache before swtiching to EL2 */
armv8_switch_to_el2();
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
armv8_switch_to_el1();
--- /dev/null
+/*
+ * GIC Initialization Routines.
+ *
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/macro.h>
+#include <asm/gic.h>
+
+
+/*************************************************************************
+ *
+ * void gic_init_secure(DistributorBase);
+ *
+ * Initialize secure copy of GIC at EL3.
+ *
+ *************************************************************************/
+ENTRY(gic_init_secure)
+ /*
+ * Initialize Distributor
+ * x0: Distributor Base
+ */
+#if defined(CONFIG_GICV3)
+ mov w9, #0x37 /* EnableGrp0 | EnableGrp1NS */
+ /* EnableGrp1S | ARE_S | ARE_NS */
+ str w9, [x0, GICD_CTLR] /* Secure GICD_CTLR */
+ ldr w9, [x0, GICD_TYPER]
+ and w10, w9, #0x1f /* ITLinesNumber */
+ cbz w10, 1f /* No SPIs */
+ add x11, x0, (GICD_IGROUPRn + 4)
+ add x12, x0, (GICD_IGROUPMODRn + 4)
+ mov w9, #~0
+0: str w9, [x11], #0x4
+ str wzr, [x12], #0x4 /* Config SPIs as Group1NS */
+ sub w10, w10, #0x1
+ cbnz w10, 0b
+#elif defined(CONFIG_GICV2)
+ mov w9, #0x3 /* EnableGrp0 | EnableGrp1 */
+ str w9, [x0, GICD_CTLR] /* Secure GICD_CTLR */
+ ldr w9, [x0, GICD_TYPER]
+ and w10, w9, #0x1f /* ITLinesNumber */
+ cbz w10, 1f /* No SPIs */
+ add x11, x0, (GICD_IGROUPRn + 4)
+ mov w9, #~0 /* Config SPIs as Grp1 */
+0: str w9, [x11], #0x4
+ sub w10, w10, #0x1
+ cbnz w10, 0b
+#endif
+1:
+ ret
+ENDPROC(gic_init_secure)
+
+
+/*************************************************************************
+ * For Gicv2:
+ * void gic_init_secure_percpu(DistributorBase, CpuInterfaceBase);
+ * For Gicv3:
+ * void gic_init_secure_percpu(ReDistributorBase);
+ *
+ * Initialize secure copy of GIC at EL3.
+ *
+ *************************************************************************/
+ENTRY(gic_init_secure_percpu)
+#if defined(CONFIG_GICV3)
+ /*
+ * Initialize ReDistributor
+ * x0: ReDistributor Base
+ */
+ mrs x10, mpidr_el1
+ lsr x9, x10, #32
+ bfi x10, x9, #24, #8 /* w10 is aff3:aff2:aff1:aff0 */
+ mov x9, x0
+1: ldr x11, [x9, GICR_TYPER]
+ lsr x11, x11, #32 /* w11 is aff3:aff2:aff1:aff0 */
+ cmp w10, w11
+ b.eq 2f
+ add x9, x9, #(2 << 16)
+ b 1b
+
+ /* x9: ReDistributor Base Address of Current CPU */
+2: mov w10, #~0x2
+ ldr w11, [x9, GICR_WAKER]
+ and w11, w11, w10 /* Clear ProcessorSleep */
+ str w11, [x9, GICR_WAKER]
+ dsb st
+ isb
+3: ldr w10, [x9, GICR_WAKER]
+ tbnz w10, #2, 3b /* Wait Children be Alive */
+
+ add x10, x9, #(1 << 16) /* SGI_Base */
+ mov w11, #~0
+ str w11, [x10, GICR_IGROUPRn]
+ str wzr, [x10, GICR_IGROUPMODRn] /* SGIs|PPIs Group1NS */
+ mov w11, #0x1 /* Enable SGI 0 */
+ str w11, [x10, GICR_ISENABLERn]
+
+ /* Initialize Cpu Interface */
+ mrs x10, ICC_SRE_EL3
+ orr x10, x10, #0xf /* SRE & Disable IRQ/FIQ Bypass & */
+ /* Allow EL2 access to ICC_SRE_EL2 */
+ msr ICC_SRE_EL3, x10
+ isb
+
+ mrs x10, ICC_SRE_EL2
+ orr x10, x10, #0xf /* SRE & Disable IRQ/FIQ Bypass & */
+ /* Allow EL1 access to ICC_SRE_EL1 */
+ msr ICC_SRE_EL2, x10
+ isb
+
+ mov x10, #0x3 /* EnableGrp1NS | EnableGrp1S */
+ msr ICC_IGRPEN1_EL3, x10
+ isb
+
+ msr ICC_CTLR_EL3, xzr
+ isb
+
+ msr ICC_CTLR_EL1, xzr /* NonSecure ICC_CTLR_EL1 */
+ isb
+
+ mov x10, #0x1 << 7 /* Non-Secure access to ICC_PMR_EL1 */
+ msr ICC_PMR_EL1, x10
+ isb
+#elif defined(CONFIG_GICV2)
+ /*
+ * Initialize SGIs and PPIs
+ * x0: Distributor Base
+ * x1: Cpu Interface Base
+ */
+ mov w9, #~0 /* Config SGIs and PPIs as Grp1 */
+ str w9, [x0, GICD_IGROUPRn] /* GICD_IGROUPR0 */
+ mov w9, #0x1 /* Enable SGI 0 */
+ str w9, [x0, GICD_ISENABLERn]
+
+ /* Initialize Cpu Interface */
+ mov w9, #0x1e7 /* Disable IRQ/FIQ Bypass & */
+ /* Enable Ack Group1 Interrupt & */
+ /* EnableGrp0 & EnableGrp1 */
+ str w9, [x1, GICC_CTLR] /* Secure GICC_CTLR */
+
+ mov w9, #0x1 << 7 /* Non-Secure access to GICC_PMR */
+ str w9, [x1, GICC_PMR]
+#endif
+ ret
+ENDPROC(gic_init_secure_percpu)
+
+
+/*************************************************************************
+ * For Gicv2:
+ * void gic_kick_secondary_cpus(DistributorBase);
+ * For Gicv3:
+ * void gic_kick_secondary_cpus(void);
+ *
+ *************************************************************************/
+ENTRY(gic_kick_secondary_cpus)
+#if defined(CONFIG_GICV3)
+ mov x9, #(1 << 40)
+ msr ICC_ASGI1R_EL1, x9
+ isb
+#elif defined(CONFIG_GICV2)
+ mov w9, #0x8000
+ movk w9, #0x100, lsl #16
+ str w9, [x0, GICD_SGIR]
+#endif
+ ret
+ENDPROC(gic_kick_secondary_cpus)
+
+
+/*************************************************************************
+ * For Gicv2:
+ * void gic_wait_for_interrupt(CpuInterfaceBase);
+ * For Gicv3:
+ * void gic_wait_for_interrupt(void);
+ *
+ * Wait for SGI 0 from master.
+ *
+ *************************************************************************/
+ENTRY(gic_wait_for_interrupt)
+0: wfi
+#if defined(CONFIG_GICV3)
+ mrs x9, ICC_IAR1_EL1
+ msr ICC_EOIR1_EL1, x9
+#elif defined(CONFIG_GICV2)
+ ldr w9, [x0, GICC_AIAR]
+ str w9, [x0, GICC_AEOIR]
+#endif
+ cbnz w9, 0b
+ ret
+ENDPROC(gic_wait_for_interrupt)
#include <asm-offsets.h>
#include <config.h>
#include <linux/linkage.h>
+#include <asm/macro.h>
/*
* void relocate_code (addr_moni)
* x0 holds the destination address.
*/
ENTRY(relocate_code)
+ stp x29, x30, [sp, #-32]! /* create a stack frame */
+ mov x29, sp
+ str x0, [sp, #16]
/*
* Copy u-boot from flash to RAM
*/
stp x10, x11, [x0], #16 /* copy to target address [x0] */
cmp x1, x2 /* until source end address [x2] */
b.lo copy_loop
+ str x0, [sp, #24]
/*
* Fix .rela.dyn relocations
b.lo fixloop
relocate_done:
+ switch_el x1, 3f, 2f, 1f
+ bl hang
+3: mrs x0, sctlr_el3
+ b 0f
+2: mrs x0, sctlr_el2
+ b 0f
+1: mrs x0, sctlr_el1
+0: tbz w0, #2, 5f /* skip flushing cache if disabled */
+ tbz w0, #12, 4f /* invalide i-cache is enabled */
+ ic iallu /* i-cache invalidate all */
+ isb sy
+4: ldp x0, x1, [sp, #16]
+ bl __asm_flush_dcache_range
+5: ldp x29, x30, [sp],#16
ret
ENDPROC(relocate_code)
/* power-ON 3V3 via Resetcontroller */
oldspeed = i2c_get_bus_speed();
- if (0 != i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC)) {
+ if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
buf = RSTCTRL_FORCE_PWR_NEN;
i2c_write(RSTCTRL_ADDR, RSTCTRL_CTRLREG, 1,
(uint8_t *)&buf, sizeof(buf));
TPS65217_WLEDCTRL1, 0x09, 0xFF);
/* write bootinfo into scratchregister of resetcontroller */
oldspeed = i2c_get_bus_speed();
- if (0 != i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC)) {
+ if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
i2c_write(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1,
(uint8_t *)&buf, sizeof(buf));
i2c_set_bus_speed(oldspeed);
--- /dev/null
+/*
+ * Copyright Altera Corporation (C) 2012-2014. All rights reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* This file is generated by Preloader Generator */
+
+#ifndef _PRELOADER_PLL_CONFIG_H_
+#define _PRELOADER_PLL_CONFIG_H_
+
+/* PLL configuration data */
+/* Main PLL */
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM (0)
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (63)
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0)
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0)
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0)
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (3)
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (3)
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (12)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (1)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK (1)
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK (0)
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK (1)
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK (0)
+/*
+ * To tell where is the clock source:
+ * 0 = MAINPLL
+ * 1 = PERIPHPLL
+ */
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP (1)
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP (1)
+
+/* Peripheral PLL */
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM (1)
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (79)
+/*
+ * To tell where is the VCOs source:
+ * 0 = EOSC1
+ * 1 = EOSC2
+ * 2 = F2S
+ */
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0)
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (3)
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (3)
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (1)
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (4)
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (4)
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (9)
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (0)
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (0)
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (1)
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (1)
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249)
+/*
+ * To tell where is the clock source:
+ * 0 = F2S_PERIPH_REF_CLK
+ * 1 = MAIN_CLK
+ * 2 = PERIPH_CLK
+ */
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (2)
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND (2)
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1)
+
+/* SDRAM PLL */
+#ifdef CONFIG_SOCFPGA_ARRIA5
+/* Arria V SDRAM will run at 533MHz while Cyclone V still at 400MHz
+ * This if..else... is not required if generated by tools */
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (2)
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (127)
+#else
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (0)
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (31)
+#endif /* CONFIG_SOCFPGA_ARRIA5 */
+
+/*
+ * To tell where is the VCOs source:
+ * 0 = EOSC1
+ * 1 = EOSC2
+ * 2 = F2S
+ */
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC (0)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT (1)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE (0)
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT (0)
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE (0)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT (1)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE (4)
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT (5)
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE (0)
+
+/* Info for driver */
+#define CONFIG_HPS_CLK_OSC1_HZ (25000000)
+#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000)
+#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000)
+#ifdef CONFIG_SOCFPGA_ARRIA5
+/* The if..else... is not required if generated by tools */
+#define CONFIG_HPS_CLK_SDRVCO_HZ (1066000000)
+#else
+#define CONFIG_HPS_CLK_SDRVCO_HZ (800000000)
+#endif
+#define CONFIG_HPS_CLK_EMAC0_HZ (250000000)
+#define CONFIG_HPS_CLK_EMAC1_HZ (250000000)
+#define CONFIG_HPS_CLK_USBCLK_HZ (200000000)
+#define CONFIG_HPS_CLK_NAND_HZ (50000000)
+#define CONFIG_HPS_CLK_SDMMC_HZ (200000000)
+#define CONFIG_HPS_CLK_QSPI_HZ (400000000)
+#define CONFIG_HPS_CLK_SPIM_HZ (200000000)
+#define CONFIG_HPS_CLK_CAN0_HZ (100000000)
+#define CONFIG_HPS_CLK_CAN1_HZ (100000000)
+#define CONFIG_HPS_CLK_GPIODB_HZ (32000)
+#define CONFIG_HPS_CLK_L4_MP_HZ (100000000)
+#define CONFIG_HPS_CLK_L4_SP_HZ (100000000)
+
+#endif /* _PRELOADER_PLL_CONFIG_H_ */
DECLARE_GLOBAL_DATA_PTR;
-int dram_init(void)
+static uint32_t mx53_dram_size[2];
+
+phys_size_t get_effective_memsize(void)
{
- u32 size1, size2;
+ /*
+ * WARNING: We must override get_effective_memsize() function here
+ * to report only the size of the first DRAM bank. This is to make
+ * U-Boot relocator place U-Boot into valid memory, that is, at the
+ * end of the first DRAM bank. If we did not override this function
+ * like so, U-Boot would be placed at the address of the first DRAM
+ * bank + total DRAM size - sizeof(uboot), which in the setup where
+ * each DRAM bank contains 512MiB of DRAM would result in placing
+ * U-Boot into invalid memory area close to the end of the first
+ * DRAM bank.
+ */
+ return mx53_dram_size[0];
+}
- size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
- size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+int dram_init(void)
+{
+ mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
+ mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
- gd->ram_size = size1 + size2;
+ gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
return 0;
}
+
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->bd->bi_dram[0].size = mx53_dram_size[0];
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+ gd->bd->bi_dram[1].size = mx53_dram_size[1];
}
static void setup_iomux_uart(void)
DECLARE_GLOBAL_DATA_PTR;
-int dram_init(void)
+static uint32_t mx53_dram_size[2];
+
+phys_size_t get_effective_memsize(void)
{
- u32 size1, size2;
+ /*
+ * WARNING: We must override get_effective_memsize() function here
+ * to report only the size of the first DRAM bank. This is to make
+ * U-Boot relocator place U-Boot into valid memory, that is, at the
+ * end of the first DRAM bank. If we did not override this function
+ * like so, U-Boot would be placed at the address of the first DRAM
+ * bank + total DRAM size - sizeof(uboot), which in the setup where
+ * each DRAM bank contains 512MiB of DRAM would result in placing
+ * U-Boot into invalid memory area close to the end of the first
+ * DRAM bank.
+ */
+ return mx53_dram_size[0];
+}
- size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
- size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+int dram_init(void)
+{
+ mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
+ mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
- gd->ram_size = size1 + size2;
+ gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
return 0;
}
+
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->bd->bi_dram[0].size = mx53_dram_size[0];
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+ gd->bd->bi_dram[1].size = mx53_dram_size[1];
}
u32 get_board_rev(void)
imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
}
+iomux_v3_cfg_t const pcie_pads[] = {
+ MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), /* POWER */
+ MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */
+};
+
+static void setup_pcie(void)
+{
+ imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
+}
+
iomux_v3_cfg_t const di0_pads[] = {
MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* DISP0_CLK */
MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* DISP0_HSYNC */
int board_eth_init(bd_t *bis)
{
setup_iomux_enet();
+ setup_pcie();
return cpu_eth_init(bis);
}
void setup_iomux_ddr(void)
{
static const iomux_v3_cfg_t ddr_pads[] = {
- VF610_PAD_DDR_A15__DDR_A_15,
VF610_PAD_DDR_A15__DDR_A_15,
VF610_PAD_DDR_A14__DDR_A_14,
VF610_PAD_DDR_A13__DDR_A_13,
--- /dev/null
+#
+# Copyright (C) 2012-2013, Guennadi Liakhovetski <lg@denx.de>
+# (C) Copyright 2012-2013 Freescale Semiconductor, Inc.
+# Copyright (C) 2013, Gateworks Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := gw_ventana.o gsc.o
+
--- /dev/null
+U-Boot for the Gateworks Ventana Product Family boards
+
+This file contains information for the port of U-Boot to the Gateworks
+Ventana Product family boards.
+
+1. Boot source, boot from NAND
+------------------------------
+
+The i.MX6 BOOT ROM expects some structures that provide details of NAND layout
+and bad block information (referred to as 'bootstreams') which are replicated
+multiple times in NAND. The number of replications is configurable through
+board strapping options and eFUSE settings. The Freescale 'kobs-ng'
+application from the Freescale LTIB BSP, which runs under Linux, must be used
+to program the bootstream in order to setup the replicated headers correctly.
+
+The Gateworks Ventana boards with NAND flash have been factory programmed
+such that their eFUSE settings expect 2 copies of the boostream (this is
+specified by providing kobs-ng with the --search_exponent=1 argument). Once in
+Linux with MTD support for the NAND on /dev/mtd0 you can program the boostream
+with:
+
+kobs-ng init -v -x --search_exponent=1 u-boot.imx
+
+The kobs-ng application uses an imximage (u-boot.imx) which contains the
+Image Vector Table (IVT) and Device Configuration Data (DCD) structures that
+the i.MX6 BOOT ROM requires to boot. The kobs-ng adds the Firmware
+Configuration Block (FCB) and Discovered Bad Block Table (DBBT).
+
+This information is taken from:
+ http://trac.gateworks.com/wiki/ventana/bootloader#NANDFLASH
+
+More details about the i.MX6 BOOT ROM can be found in the IMX6 reference manual.
+
+2. Build
+--------
+
+There are several Gateworks Ventana boards that share a simliar design but
+vary based on CPU, Memory configuration, and subloaded devices. Although
+the subloaded devices are handled dynamically in the bootloader using
+factory configured EEPROM data to modify the device-tree, the CPU choice
+(IMX6Q vs IMX6DL) and memory configurations are currently compile-time
+options.
+
+The following Gateworks Ventana configurations exist:
+ gwventanaq1gspi: MX6Q,1GB,SPI FLASH
+ gwventanaq : MX6Q,512MB,NAND FLASH
+ gwventanaq1g : MX6Q,1GB,NAND FLASH
+ gwventanadl : MX6DL,512MB,NAND FLASH
+ gwventanadl1g : MX6DL,1GB,NAND FLASH
+
+To build U-Boot for the MX6Q,1GB,NAND FLASH for example:
+
+ make gwventanaq1g_config
+ make
+
--- /dev/null
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2013 Gateworks Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
+DATA 4, CCM_CCGR1, 0x0030FC03
+DATA 4, CCM_CCGR2, 0x0FFFC000
+DATA 4, CCM_CCGR3, 0x3FF00000
+DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */
+DATA 4, CCM_CCGR5, 0x0F0000C3
+DATA 4, CCM_CCGR6, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
+DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en = 1 --> CKO1 enabled
+ * cko1_div = 111 --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+DATA 4, CCM_CCOSR, 0x000000fb
--- /dev/null
+/*
+ * Copyright (C) 2013 Gateworks Corporation
+ *
+ * Author: Tim Harvey <tharvey@gateworks.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/errno.h>
+#include <common.h>
+#include <i2c.h>
+#include <linux/ctype.h>
+
+#include "gsc.h"
+
+#define MINMAX(n, percent) ((n)*(100-percent)/100), ((n)*(100+percent)/100)
+
+/*
+ * The Gateworks System Controller will fail to ACK a master transaction if
+ * it is busy, which can occur during its 1HZ timer tick while reading ADC's.
+ * When this does occur, it will never be busy long enough to fail more than
+ * 2 back-to-back transfers. Thus we wrap i2c_read and i2c_write with
+ * 3 retries.
+ */
+int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
+{
+ int retry = 3;
+ int n = 0;
+ int ret;
+
+ while (n++ < retry) {
+ ret = i2c_read(chip, addr, alen, buf, len);
+ if (!ret)
+ break;
+ debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr,
+ n, ret);
+ if (ret != -ENODEV)
+ break;
+ mdelay(10);
+ }
+ return ret;
+}
+
+int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
+{
+ int retry = 3;
+ int n = 0;
+ int ret;
+
+ while (n++ < retry) {
+ ret = i2c_write(chip, addr, alen, buf, len);
+ if (!ret)
+ break;
+ debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr,
+ n, ret);
+ if (ret != -ENODEV)
+ break;
+ mdelay(10);
+ }
+ mdelay(1);
+ return ret;
+}
+
+#ifdef CONFIG_CMD_GSC
+static void read_hwmon(const char *name, uint reg, uint size, uint low,
+ uint high)
+{
+ unsigned char buf[3];
+ uint ui;
+
+ printf("%-8s:", name);
+ memset(buf, 0, sizeof(buf));
+ if (gsc_i2c_read(GSC_HWMON_ADDR, reg, 1, buf, size)) {
+ puts("fRD\n");
+ } else {
+ ui = buf[0] | (buf[1]<<8) | (buf[2]<<16);
+ if (ui == 0xffffff)
+ printf("invalid");
+ else if (ui < low)
+ printf("%d Failed - Low", ui);
+ else if (ui > high)
+ printf("%d Failed - High", ui);
+ else
+ printf("%d", ui);
+ }
+ puts("\n");
+}
+
+int do_gsc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ const char *model = getenv("model");
+
+ i2c_set_bus_num(0);
+ read_hwmon("Temp", GSC_HWMON_TEMP, 2, 0, 9000);
+ read_hwmon("VIN", GSC_HWMON_VIN, 3, 8000, 60000);
+ read_hwmon("VBATT", GSC_HWMON_VBATT, 3, 1800, 3500);
+ read_hwmon("VDD_3P3", GSC_HWMON_VDD_3P3, 3, MINMAX(3300, 10));
+ read_hwmon("VDD_HIGH", GSC_HWMON_VDD_HIGH, 3, MINMAX(3000, 10));
+ read_hwmon("VDD_DDR", GSC_HWMON_VDD_DDR, 3, MINMAX(1500, 10));
+ read_hwmon("VDD_5P0", GSC_HWMON_VDD_5P0, 3, MINMAX(5000, 10));
+ read_hwmon("VDD_2P5", GSC_HWMON_VDD_2P5, 3, MINMAX(2500, 10));
+ read_hwmon("VDD_1P8", GSC_HWMON_VDD_1P8, 3, MINMAX(1800, 10));
+
+ switch (model[3]) {
+ case '1': /* GW51xx */
+ read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1175, 10));
+ read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1175, 10));
+ break;
+ case '2': /* GW52xx */
+ case '3': /* GW53xx */
+ read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1175, 10));
+ read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1175, 10));
+ read_hwmon("VDD_1P0", GSC_HWMON_VDD_1P0, 3, MINMAX(1000, 10));
+ break;
+ case '4': /* GW54xx */
+ read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1375, 10));
+ read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1375, 10));
+ read_hwmon("VDD_1P0", GSC_HWMON_VDD_1P0, 3, MINMAX(1000, 10));
+ break;
+ }
+ return 0;
+}
+
+U_BOOT_CMD(gsc, 1, 1, do_gsc,
+ "GSC test",
+ ""
+);
+
+#endif /* CONFIG_CMD_GSC */
--- /dev/null
+/*
+ * Copyright (C) 2013 Gateworks Corporation
+ *
+ * Author: Tim Harvey <tharvey@gateworks.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASSEMBLY__
+
+/* i2c slave addresses */
+#define GSC_SC_ADDR 0x20
+#define GSC_RTC_ADDR 0x68
+#define GSC_HWMON_ADDR 0x29
+#define GSC_EEPROM_ADDR 0x51
+
+/* System Controller registers */
+enum {
+ GSC_SC_CTRL0 = 0x00,
+ GSC_SC_CTRL1 = 0x01,
+ GSC_SC_STATUS = 0x0a,
+ GSC_SC_FWVER = 0x0e,
+};
+
+/* System Controller Control1 bits */
+enum {
+ GSC_SC_CTRL1_WDDIS = 7, /* 1 = disable watchdog */
+};
+
+/* System Controller Interrupt bits */
+enum {
+ GSC_SC_IRQ_PB = 0, /* Pushbutton switch */
+ GSC_SC_IRQ_SECURE = 1, /* Secure Key erase operation complete */
+ GSC_SC_IRQ_EEPROM_WP = 2, /* EEPROM write violation */
+ GSC_SC_IRQ_GPIO = 4, /* GPIO change */
+ GSC_SC_IRQ_TAMPER = 5, /* Tamper detect */
+ GSC_SC_IRQ_WATCHDOG = 6, /* Watchdog trip */
+ GSC_SC_IRQ_PBLONG = 7, /* Pushbutton long hold */
+};
+
+/* Hardware Monitor registers */
+enum {
+ GSC_HWMON_TEMP = 0x00,
+ GSC_HWMON_VIN = 0x02,
+ GSC_HWMON_VDD_3P3 = 0x05,
+ GSC_HWMON_VBATT = 0x08,
+ GSC_HWMON_VDD_5P0 = 0x0b,
+ GSC_HWMON_VDD_CORE = 0x0e,
+ GSC_HWMON_VDD_HIGH = 0x14,
+ GSC_HWMON_VDD_DDR = 0x17,
+ GSC_HWMON_VDD_SOC = 0x11,
+ GSC_HWMON_VDD_1P8 = 0x1d,
+ GSC_HWMON_VDD_2P5 = 0x23,
+ GSC_HWMON_VDD_1P0 = 0x20,
+};
+
+/*
+ * I2C transactions to the GSC are done via these functions which
+ * perform retries in the case of a busy GSC NAK'ing the transaction
+ */
+int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len);
+int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len);
+#endif
+
--- /dev/null
+/*
+ * Copyright (C) 2013 Gateworks Corporation
+ *
+ * Author: Tim Harvey <tharvey@gateworks.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/sata.h>
+#include <jffs2/load_kernel.h>
+#include <hwconfig.h>
+#include <i2c.h>
+#include <linux/ctype.h>
+#include <fdt_support.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <mmc.h>
+#include <mtd_node.h>
+#include <netdev.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include <i2c.h>
+#include <fdt_support.h>
+#include <jffs2/load_kernel.h>
+#include <spi_flash.h>
+
+#include "gsc.h"
+#include "ventana_eeprom.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* GPIO's common to all baseboards */
+#define GP_PHY_RST IMX_GPIO_NR(1, 30)
+#define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22)
+#define GP_SD3_CD IMX_GPIO_NR(7, 0)
+#define GP_RS232_EN IMX_GPIO_NR(2, 11)
+#define GP_MSATA_SEL IMX_GPIO_NR(2, 8)
+
+/* I2C bus numbers */
+#define I2C_GSC 0
+#define I2C_PMIC 1
+
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | \
+ PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define DIO_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+/*
+ * EEPROM board info struct populated by read_eeprom so that we only have to
+ * read it once.
+ */
+static struct ventana_board_info ventana_info;
+
+enum {
+ GW54proto, /* original GW5400-A prototype */
+ GW51xx,
+ GW52xx,
+ GW53xx,
+ GW54xx,
+ GW_UNKNOWN,
+};
+
+int board_type;
+
+/* UART1: Function varies per baseboard */
+iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+/* UART2: Serial Console */
+iomux_v3_cfg_t const uart2_pads[] = {
+ MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+/* I2C1: GSC */
+struct i2c_pads_info i2c_pad_info0 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
+ .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
+ .gp = IMX_GPIO_NR(3, 21)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
+ .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
+ .gp = IMX_GPIO_NR(3, 28)
+ }
+};
+
+/* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */
+struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
+ .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
+ .gp = IMX_GPIO_NR(4, 12)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
+ .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+ .gp = IMX_GPIO_NR(4, 13)
+ }
+};
+
+/* I2C3: Misc/Expansion */
+struct i2c_pads_info i2c_pad_info2 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
+ .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
+ .gp = IMX_GPIO_NR(1, 3)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
+ .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC,
+ .gp = IMX_GPIO_NR(1, 6)
+ }
+};
+
+/* MMC */
+iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+/* ENET */
+iomux_v3_cfg_t const enet_pads[] = {
+ MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ /* PHY nRST */
+ MX6_PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+/* NAND */
+iomux_v3_cfg_t const nfc_pads[] = {
+ MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#ifdef CONFIG_CMD_NAND
+static void setup_gpmi_nand(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ /* config gpmi nand iomux */
+ imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
+
+ /* config gpmi and bch clock to 100 MHz */
+ clrsetbits_le32(&mxc_ccm->cs2cdr,
+ MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
+ MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
+ MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
+ MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
+
+ /* enable gpmi and bch clock gating */
+ setbits_le32(&mxc_ccm->CCGR4,
+ MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+ MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
+
+ /* enable apbh clock gating */
+ setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+#endif
+
+static void setup_iomux_enet(void)
+{
+ imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+
+ /* toggle PHY_RST# */
+ gpio_direction_output(GP_PHY_RST, 0);
+ mdelay(2);
+ gpio_set_value(GP_PHY_RST, 1);
+}
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+ imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+iomux_v3_cfg_t const usb_pads[] = {
+ MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(DIO_PAD_CTRL),
+ MX6_PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(DIO_PAD_CTRL),
+ MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(DIO_PAD_CTRL), /* OTG PWR */
+};
+
+int board_ehci_hcd_init(int port)
+{
+ struct ventana_board_info *info = &ventana_info;
+
+ imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
+
+ /* Reset USB HUB (present on GW54xx/GW53xx) */
+ switch (info->model[3]) {
+ case '3': /* GW53xx */
+ imx_iomux_v3_setup_pad(MX6_PAD_GPIO_9__GPIO1_IO09|
+ MUX_PAD_CTRL(NO_PAD_CTRL));
+ gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
+ mdelay(2);
+ gpio_set_value(IMX_GPIO_NR(1, 9), 1);
+ break;
+ case '4': /* GW54xx */
+ imx_iomux_v3_setup_pad(MX6_PAD_SD1_DAT0__GPIO1_IO16 |
+ MUX_PAD_CTRL(NO_PAD_CTRL));
+ gpio_direction_output(IMX_GPIO_NR(1, 16), 0);
+ mdelay(2);
+ gpio_set_value(IMX_GPIO_NR(1, 16), 1);
+ break;
+ }
+
+ return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+ if (port)
+ return 0;
+ gpio_set_value(GP_USB_OTG_PWR, on);
+ return 0;
+}
+#endif /* CONFIG_USB_EHCI_MX6 */
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ /* Card Detect */
+ gpio_direction_input(GP_SD3_CD);
+ return !gpio_get_value(GP_SD3_CD);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ /* Only one USDHC controller on Ventana */
+ imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ usdhc_cfg.max_bus_width = 4;
+
+ return fsl_esdhc_initialize(bis, &usdhc_cfg);
+}
+#endif /* CONFIG_FSL_ESDHC */
+
+#ifdef CONFIG_MXC_SPI
+iomux_v3_cfg_t const ecspi1_pads[] = {
+ /* SS1 */
+ MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+};
+
+static void setup_spi(void)
+{
+ gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
+ imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
+ ARRAY_SIZE(ecspi1_pads));
+}
+#endif
+
+/* configure eth0 PHY board-specific LED behavior */
+int board_phy_config(struct phy_device *phydev)
+{
+ unsigned short val;
+
+ /* Marvel 88E1510 */
+ if (phydev->phy_id == 0x1410dd1) {
+ /*
+ * Page 3, Register 16: LED[2:0] Function Control Register
+ * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
+ * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
+ */
+ phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
+ val &= 0xff00;
+ val |= 0x0017;
+ phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
+ phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
+ }
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ setup_iomux_enet();
+
+#ifdef CONFIG_FEC_MXC
+ cpu_eth_init(bis);
+#endif
+
+#ifdef CONFIG_CI_UDC
+ /* For otg ethernet*/
+ usb_eth_initialize(bis);
+#endif
+
+ return 0;
+}
+
+/* read ventana EEPROM, check for validity, and return baseboard type */
+static int
+read_eeprom(void)
+{
+ int i;
+ int chksum;
+ char baseboard;
+ int type;
+ struct ventana_board_info *info = &ventana_info;
+ unsigned char *buf = (unsigned char *)&ventana_info;
+
+ memset(info, 0, sizeof(ventana_info));
+
+ /*
+ * On a board with a missing/depleted backup battery for GSC, the
+ * board may be ready to probe the GSC before its firmware is
+ * running. We will wait here indefinately for the GSC/EEPROM.
+ */
+ while (1) {
+ if (0 == i2c_set_bus_num(I2C_GSC) &&
+ 0 == i2c_probe(GSC_EEPROM_ADDR))
+ break;
+ mdelay(1);
+ }
+
+ /* read eeprom config section */
+ if (gsc_i2c_read(GSC_EEPROM_ADDR, 0x00, 1, buf, sizeof(ventana_info))) {
+ puts("EEPROM: Failed to read EEPROM\n");
+ info->model[0] = 0;
+ return GW_UNKNOWN;
+ }
+
+ /* sanity checks */
+ if (info->model[0] != 'G' || info->model[1] != 'W') {
+ puts("EEPROM: Invalid Model in EEPROM\n");
+ info->model[0] = 0;
+ return GW_UNKNOWN;
+ }
+
+ /* validate checksum */
+ for (chksum = 0, i = 0; i < sizeof(*info)-2; i++)
+ chksum += buf[i];
+ if ((info->chksum[0] != chksum>>8) ||
+ (info->chksum[1] != (chksum&0xff))) {
+ puts("EEPROM: Failed EEPROM checksum\n");
+ info->model[0] = 0;
+ return GW_UNKNOWN;
+ }
+
+ /* original GW5400-A prototype */
+ baseboard = info->model[3];
+ if (strncasecmp((const char *)info->model, "GW5400-A", 8) == 0)
+ baseboard = '0';
+
+ switch (baseboard) {
+ case '0': /* original GW5400-A prototype */
+ type = GW54proto;
+ break;
+ case '1':
+ type = GW51xx;
+ break;
+ case '2':
+ type = GW52xx;
+ break;
+ case '3':
+ type = GW53xx;
+ break;
+ case '4':
+ type = GW54xx;
+ break;
+ default:
+ printf("EEPROM: Unknown model in EEPROM: %s\n", info->model);
+ type = GW_UNKNOWN;
+ break;
+ }
+ return type;
+}
+
+/*
+ * Baseboard specific GPIO
+ */
+
+/* common to add baseboards */
+static iomux_v3_cfg_t const gw_gpio_pads[] = {
+ /* MSATA_EN */
+ MX6_PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* RS232_EN# */
+ MX6_PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+/* prototype */
+static iomux_v3_cfg_t const gwproto_gpio_pads[] = {
+ /* PANLEDG# */
+ MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* PANLEDR# */
+ MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* LOCLED# */
+ MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* RS485_EN */
+ MX6_PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* IOEXP_PWREN# */
+ MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* IOEXP_IRQ# */
+ MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* VID_EN */
+ MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* DIOI2C_DIS# */
+ MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* PCICK_SSON */
+ MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* PCI_RST# */
+ MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
+ /* PANLEDG# */
+ MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* PANLEDR# */
+ MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* IOEXP_PWREN# */
+ MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* IOEXP_IRQ# */
+ MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+ /* GPS_SHDN */
+ MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* VID_PWR */
+ MX6_PAD_CSI0_DATA_EN__GPIO5_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* PCI_RST# */
+ MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
+ /* PANLEDG# */
+ MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* PANLEDR# */
+ MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* IOEXP_PWREN# */
+ MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* IOEXP_IRQ# */
+ MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+ /* MX6_LOCLED# */
+ MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* GPS_SHDN */
+ MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* USBOTG_SEL */
+ MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* VID_PWR */
+ MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* PCI_RST# */
+ MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
+ /* PANLEDG# */
+ MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* PANLEDR# */
+ MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* IOEXP_PWREN# */
+ MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* IOEXP_IRQ# */
+ MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+ /* MX6_LOCLED# */
+ MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* GPS_SHDN */
+ MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* VID_EN */
+ MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* PCI_RST# */
+ MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
+ /* PANLEDG# */
+ MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* PANLEDR# */
+ MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* MX6_LOCLED# */
+ MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* MIPI_DIO */
+ MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* RS485_EN */
+ MX6_PAD_EIM_D24__GPIO3_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* IOEXP_PWREN# */
+ MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* IOEXP_IRQ# */
+ MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* DIOI2C_DIS# */
+ MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* DIOI2C_DIS# */
+ MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* PCICK_SSON */
+ MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* PCI_RST# */
+ MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+/*
+ * each baseboard has 4 user configurable Digital IO lines which can
+ * be pinmuxed as a GPIO or in some cases a PWM
+ */
+struct dio_cfg {
+ iomux_v3_cfg_t gpio_padmux;
+ unsigned gpio_param;
+ iomux_v3_cfg_t pwm_padmux;
+ unsigned pwm_param;
+};
+
+struct ventana {
+ /* pinmux */
+ iomux_v3_cfg_t const *gpio_pads;
+ int num_pads;
+ /* DIO pinmux/val */
+ struct dio_cfg dio_cfg[4];
+ /* various gpios (0 if non-existent) */
+ int leds[3];
+ int pcie_rst;
+ int mezz_pwren;
+ int mezz_irq;
+ int rs485en;
+ int gps_shdn;
+ int vidin_en;
+ int dioi2c_en;
+ int pcie_sson;
+ int usb_sel;
+};
+
+struct ventana gpio_cfg[] = {
+ /* GW5400proto */
+ {
+ .gpio_pads = gw54xx_gpio_pads,
+ .num_pads = ARRAY_SIZE(gw54xx_gpio_pads),
+ .dio_cfg = {
+ { MX6_PAD_GPIO_9__GPIO1_IO09, IMX_GPIO_NR(1, 9),
+ MX6_PAD_GPIO_9__PWM1_OUT, 1 },
+ { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
+ MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
+ { MX6_PAD_SD4_DAT1__GPIO2_IO09, IMX_GPIO_NR(2, 9),
+ MX6_PAD_SD4_DAT1__PWM3_OUT, 3 },
+ { MX6_PAD_SD4_DAT2__GPIO2_IO10, IMX_GPIO_NR(2, 10),
+ MX6_PAD_SD4_DAT2__PWM4_OUT, 4 },
+ },
+ .leds = {
+ IMX_GPIO_NR(4, 6),
+ IMX_GPIO_NR(4, 10),
+ IMX_GPIO_NR(4, 15),
+ },
+ .pcie_rst = IMX_GPIO_NR(1, 29),
+ .mezz_pwren = IMX_GPIO_NR(4, 7),
+ .mezz_irq = IMX_GPIO_NR(4, 9),
+ .rs485en = IMX_GPIO_NR(3, 24),
+ .dioi2c_en = IMX_GPIO_NR(4, 5),
+ .pcie_sson = IMX_GPIO_NR(1, 20),
+ },
+
+ /* GW51xx */
+ {
+ .gpio_pads = gw51xx_gpio_pads,
+ .num_pads = ARRAY_SIZE(gw51xx_gpio_pads),
+ .dio_cfg = {
+ { MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16),
+ 0, 0 },
+ { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
+ MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
+ { MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17),
+ MX6_PAD_SD1_DAT1__PWM3_OUT, 3 },
+ { MX6_PAD_SD1_CMD__GPIO1_IO18, IMX_GPIO_NR(1, 18),
+ MX6_PAD_SD1_CMD__PWM4_OUT, 4 },
+ },
+ .leds = {
+ IMX_GPIO_NR(4, 6),
+ IMX_GPIO_NR(4, 10),
+ },
+ .pcie_rst = IMX_GPIO_NR(1, 0),
+ .mezz_pwren = IMX_GPIO_NR(2, 19),
+ .mezz_irq = IMX_GPIO_NR(2, 18),
+ .gps_shdn = IMX_GPIO_NR(1, 2),
+ .vidin_en = IMX_GPIO_NR(5, 20),
+ },
+
+ /* GW52xx */
+ {
+ .gpio_pads = gw52xx_gpio_pads,
+ .num_pads = ARRAY_SIZE(gw52xx_gpio_pads),
+ .dio_cfg = {
+ { MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16),
+ 0, 0 },
+ { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
+ MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
+ { MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17),
+ MX6_PAD_SD1_DAT1__PWM3_OUT, 3 },
+ { MX6_PAD_SD1_CLK__GPIO1_IO20, IMX_GPIO_NR(1, 20),
+ 0, 0 },
+ },
+ .leds = {
+ IMX_GPIO_NR(4, 6),
+ IMX_GPIO_NR(4, 7),
+ IMX_GPIO_NR(4, 15),
+ },
+ .pcie_rst = IMX_GPIO_NR(1, 29),
+ .mezz_pwren = IMX_GPIO_NR(2, 19),
+ .mezz_irq = IMX_GPIO_NR(2, 18),
+ .gps_shdn = IMX_GPIO_NR(1, 27),
+ .vidin_en = IMX_GPIO_NR(3, 31),
+ .usb_sel = IMX_GPIO_NR(1, 2),
+ },
+
+ /* GW53xx */
+ {
+ .gpio_pads = gw53xx_gpio_pads,
+ .num_pads = ARRAY_SIZE(gw53xx_gpio_pads),
+ .dio_cfg = {
+ { MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16),
+ 0, 0 },
+ { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
+ MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
+ { MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17),
+ MX6_PAD_SD1_DAT1__PWM3_OUT, 3 },
+ { MX6_PAD_SD1_CLK__GPIO1_IO20, IMX_GPIO_NR(1, 20),
+ 0, 0 },
+ },
+ .leds = {
+ IMX_GPIO_NR(4, 6),
+ IMX_GPIO_NR(4, 7),
+ IMX_GPIO_NR(4, 15),
+ },
+ .pcie_rst = IMX_GPIO_NR(1, 29),
+ .mezz_pwren = IMX_GPIO_NR(2, 19),
+ .mezz_irq = IMX_GPIO_NR(2, 18),
+ .gps_shdn = IMX_GPIO_NR(1, 27),
+ .vidin_en = IMX_GPIO_NR(3, 31),
+ },
+
+ /* GW54xx */
+ {
+ .gpio_pads = gw54xx_gpio_pads,
+ .num_pads = ARRAY_SIZE(gw54xx_gpio_pads),
+ .dio_cfg = {
+ { MX6_PAD_GPIO_9__GPIO1_IO09, IMX_GPIO_NR(1, 9),
+ MX6_PAD_GPIO_9__PWM1_OUT, 1 },
+ { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
+ MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
+ { MX6_PAD_SD4_DAT1__GPIO2_IO09, IMX_GPIO_NR(2, 9),
+ MX6_PAD_SD4_DAT1__PWM3_OUT, 3 },
+ { MX6_PAD_SD4_DAT2__GPIO2_IO10, IMX_GPIO_NR(2, 10),
+ MX6_PAD_SD4_DAT2__PWM4_OUT, 4 },
+ },
+ .leds = {
+ IMX_GPIO_NR(4, 6),
+ IMX_GPIO_NR(4, 7),
+ IMX_GPIO_NR(4, 15),
+ },
+ .pcie_rst = IMX_GPIO_NR(1, 29),
+ .mezz_pwren = IMX_GPIO_NR(2, 19),
+ .mezz_irq = IMX_GPIO_NR(2, 18),
+ .rs485en = IMX_GPIO_NR(7, 1),
+ .vidin_en = IMX_GPIO_NR(3, 31),
+ .dioi2c_en = IMX_GPIO_NR(4, 5),
+ .pcie_sson = IMX_GPIO_NR(1, 20),
+ },
+};
+
+/* setup GPIO pinmux and default configuration per baseboard */
+static void setup_board_gpio(int board)
+{
+ struct ventana_board_info *info = &ventana_info;
+ const char *s;
+ char arg[10];
+ size_t len;
+ int i;
+ int quiet = simple_strtol(getenv("quiet"), NULL, 10);
+
+ if (board >= GW_UNKNOWN)
+ return;
+
+ /* RS232_EN# */
+ gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1);
+
+ /* MSATA Enable */
+ if (is_cpu_type(MXC_CPU_MX6Q) &&
+ test_bit(EECONFIG_SATA, info->config)) {
+ gpio_direction_output(GP_MSATA_SEL,
+ (hwconfig("msata")) ? 1 : 0);
+ } else {
+ gpio_direction_output(GP_MSATA_SEL, 0);
+ }
+
+ /*
+ * assert PCI_RST# (released by OS when clock is valid)
+ * TODO: figure out why leaving this de-asserted from PCI scan on boot
+ * causes linux pcie driver to hang during enumeration
+ */
+ gpio_direction_output(gpio_cfg[board].pcie_rst, 0);
+
+ /* turn off (active-high) user LED's */
+ for (i = 0; i < 4; i++) {
+ if (gpio_cfg[board].leds[i])
+ gpio_direction_output(gpio_cfg[board].leds[i], 1);
+ }
+
+ /* Expansion Mezzanine IO */
+ gpio_direction_output(gpio_cfg[board].mezz_pwren, 0);
+ gpio_direction_input(gpio_cfg[board].mezz_irq);
+
+ /* RS485 Transmit Enable */
+ if (gpio_cfg[board].rs485en)
+ gpio_direction_output(gpio_cfg[board].rs485en, 0);
+
+ /* GPS_SHDN */
+ if (gpio_cfg[board].gps_shdn)
+ gpio_direction_output(gpio_cfg[board].gps_shdn, 1);
+
+ /* Analog video codec power enable */
+ if (gpio_cfg[board].vidin_en)
+ gpio_direction_output(gpio_cfg[board].vidin_en, 1);
+
+ /* DIOI2C_DIS# */
+ if (gpio_cfg[board].dioi2c_en)
+ gpio_direction_output(gpio_cfg[board].dioi2c_en, 0);
+
+ /* PCICK_SSON: disable spread-spectrum clock */
+ if (gpio_cfg[board].pcie_sson)
+ gpio_direction_output(gpio_cfg[board].pcie_sson, 0);
+
+ /* USBOTG Select (PCISKT or FrontPanel) */
+ if (gpio_cfg[board].usb_sel)
+ gpio_direction_output(gpio_cfg[board].usb_sel, 0);
+
+ /*
+ * Configure DIO pinmux/padctl registers
+ * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
+ */
+ for (i = 0; i < 4; i++) {
+ struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
+ unsigned ctrl = DIO_PAD_CTRL;
+
+ sprintf(arg, "dio%d", i);
+ if (!hwconfig(arg))
+ continue;
+ s = hwconfig_subarg(arg, "padctrl", &len);
+ if (s)
+ ctrl = simple_strtoul(s, NULL, 16) & 0x3ffff;
+ if (hwconfig_subarg_cmp(arg, "mode", "gpio")) {
+ if (!quiet) {
+ printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i,
+ (cfg->gpio_param/32)+1,
+ cfg->gpio_param%32,
+ cfg->gpio_param);
+ }
+ imx_iomux_v3_setup_pad(cfg->gpio_padmux |
+ MUX_PAD_CTRL(ctrl));
+ gpio_direction_input(cfg->gpio_param);
+ } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") &&
+ cfg->pwm_padmux) {
+ if (!quiet)
+ printf("DIO%d: pwm%d\n", i, cfg->pwm_param);
+ imx_iomux_v3_setup_pad(cfg->pwm_padmux |
+ MUX_PAD_CTRL(ctrl));
+ }
+ }
+
+ if (!quiet) {
+ if (is_cpu_type(MXC_CPU_MX6Q) &&
+ (test_bit(EECONFIG_SATA, info->config))) {
+ printf("MSATA: %s\n", (hwconfig("msata") ?
+ "enabled" : "disabled"));
+ }
+ printf("RS232: %s\n", (hwconfig("rs232")) ?
+ "enabled" : "disabled");
+ }
+}
+
+#if defined(CONFIG_CMD_PCI)
+int imx6_pcie_toggle_reset(void)
+{
+ if (board_type < GW_UNKNOWN) {
+ gpio_direction_output(gpio_cfg[board_type].pcie_rst, 0);
+ mdelay(50);
+ gpio_direction_output(gpio_cfg[board_type].pcie_rst, 1);
+ }
+ return 0;
+}
+#endif /* CONFIG_CMD_PCI */
+
+#ifdef CONFIG_SERIAL_TAG
+/*
+ * called when setting up ATAGS before booting kernel
+ * populate serialnum from the following (in order of priority):
+ * serial# env var
+ * eeprom
+ */
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+ char *serial = getenv("serial#");
+
+ if (serial) {
+ serialnr->high = 0;
+ serialnr->low = simple_strtoul(serial, NULL, 10);
+ } else if (ventana_info.model[0]) {
+ serialnr->high = 0;
+ serialnr->low = ventana_info.serial;
+ } else {
+ serialnr->high = 0;
+ serialnr->low = 0;
+ }
+}
+#endif
+
+/*
+ * Board Support
+ */
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+ gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
+ CONFIG_DDR_MB*1024*1024);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ struct iomuxc_base_regs *const iomuxc_regs
+ = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+
+ clrsetbits_le32(&iomuxc_regs->gpr[1],
+ IOMUXC_GPR1_OTG_ID_MASK,
+ IOMUXC_GPR1_OTG_ID_GPIO1);
+
+ /* address of linux boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+ setup_gpmi_nand();
+#endif
+#ifdef CONFIG_MXC_SPI
+ setup_spi();
+#endif
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+
+#ifdef CONFIG_CMD_SATA
+ setup_sata();
+#endif
+ /* read Gateworks EEPROM into global struct (used later) */
+ board_type = read_eeprom();
+
+ /* board-specifc GPIO iomux */
+ if (board_type < GW_UNKNOWN) {
+ imx_iomux_v3_setup_multiple_pads(gw_gpio_pads,
+ ARRAY_SIZE(gw_gpio_pads));
+ imx_iomux_v3_setup_multiple_pads(gpio_cfg[board_type].gpio_pads,
+ gpio_cfg[board_type].num_pads);
+ }
+
+ return 0;
+}
+
+#if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
+/*
+ * called during late init (after relocation and after board_init())
+ * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
+ * EEPROM read.
+ */
+int checkboard(void)
+{
+ struct ventana_board_info *info = &ventana_info;
+ unsigned char buf[4];
+ const char *p;
+ int quiet; /* Quiet or minimal output mode */
+
+ quiet = 0;
+ p = getenv("quiet");
+ if (p)
+ quiet = simple_strtol(p, NULL, 10);
+ else
+ setenv("quiet", "0");
+
+ puts("\nGateworks Corporation Copyright 2014\n");
+ if (info->model[0]) {
+ printf("Model: %s\n", info->model);
+ printf("MFGDate: %02x-%02x-%02x%02x\n",
+ info->mfgdate[0], info->mfgdate[1],
+ info->mfgdate[2], info->mfgdate[3]);
+ printf("Serial:%d\n", info->serial);
+ } else {
+ puts("Invalid EEPROM - board will not function fully\n");
+ }
+ if (quiet)
+ return 0;
+
+ /* Display GSC firmware revision/CRC/status */
+ i2c_set_bus_num(I2C_GSC);
+ if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_FWVER, 1, buf, 1)) {
+ printf("GSC: v%d", buf[0]);
+ if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, buf, 4)) {
+ printf(" 0x%04x", buf[2] | buf[3]<<8); /* CRC */
+ printf(" 0x%02x", buf[0]); /* irq status */
+ }
+ puts("\n");
+ }
+ /* Display RTC */
+ if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
+ printf("RTC: %d\n",
+ buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
+ }
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_CMD_BMODE
+/*
+ * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
+ * see Table 8-11 and Table 5-9
+ * BOOT_CFG1[7] = 1 (boot from NAND)
+ * BOOT_CFG1[5] = 0 - raw NAND
+ * BOOT_CFG1[4] = 0 - default pad settings
+ * BOOT_CFG1[3:2] = 00 - devices = 1
+ * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
+ * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
+ * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
+ * BOOT_CFG2[0] = 0 - Reset time 12ms
+ */
+static const struct boot_mode board_boot_modes[] = {
+ /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
+ { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
+ { NULL, 0 },
+};
+#endif
+
+/* late init */
+int misc_init_r(void)
+{
+ struct ventana_board_info *info = &ventana_info;
+ unsigned char reg;
+
+ /* set env vars based on EEPROM data */
+ if (ventana_info.model[0]) {
+ char str[16], fdt[36];
+ char *p;
+ const char *cputype = "";
+ int i;
+
+ /*
+ * FDT name will be prefixed with CPU type. Three versions
+ * will be created each increasingly generic and bootloader
+ * env scripts will try loading each from most specific to
+ * least.
+ */
+ if (is_cpu_type(MXC_CPU_MX6Q))
+ cputype = "imx6q";
+ else if (is_cpu_type(MXC_CPU_MX6DL))
+ cputype = "imx6dl";
+ memset(str, 0, sizeof(str));
+ for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
+ str[i] = tolower(info->model[i]);
+ if (!getenv("model"))
+ setenv("model", str);
+ if (!getenv("fdt_file")) {
+ sprintf(fdt, "%s-%s.dtb", cputype, str);
+ setenv("fdt_file", fdt);
+ }
+ p = strchr(str, '-');
+ if (p) {
+ *p++ = 0;
+
+ setenv("model_base", str);
+ if (!getenv("fdt_file1")) {
+ sprintf(fdt, "%s-%s.dtb", cputype, str);
+ setenv("fdt_file1", fdt);
+ }
+ str[4] = 'x';
+ str[5] = 'x';
+ str[6] = 0;
+ if (!getenv("fdt_file2")) {
+ sprintf(fdt, "%s-%s.dtb", cputype, str);
+ setenv("fdt_file2", fdt);
+ }
+ }
+
+ /* initialize env from EEPROM */
+ if (test_bit(EECONFIG_ETH0, info->config) &&
+ !getenv("ethaddr")) {
+ eth_setenv_enetaddr("ethaddr", info->mac0);
+ }
+ if (test_bit(EECONFIG_ETH1, info->config) &&
+ !getenv("eth1addr")) {
+ eth_setenv_enetaddr("eth1addr", info->mac1);
+ }
+
+ /* board serial-number */
+ sprintf(str, "%6d", info->serial);
+ setenv("serial#", str);
+ }
+
+ /* configure PFUZE100 PMIC (not used on all Ventana baseboards) */
+ if ((board_type == GW54xx || board_type == GW54proto) &&
+ !pmic_init(I2C_PMIC)) {
+ struct pmic *p = pmic_get("PFUZE100_PMIC");
+ u32 reg;
+ if (p && !pmic_probe(p)) {
+ pmic_reg_read(p, PFUZE100_DEVICEID, ®);
+ printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
+
+ /* Set VGEN1 to 1.5V and enable */
+ pmic_reg_read(p, PFUZE100_VGEN1VOL, ®);
+ reg &= ~(LDO_VOL_MASK);
+ reg |= (LDOA_1_50V | LDO_EN);
+ pmic_reg_write(p, PFUZE100_VGEN1VOL, reg);
+
+ /* Set SWBST to 5.0V and enable */
+ pmic_reg_read(p, PFUZE100_SWBSTCON1, ®);
+ reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
+ reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
+ pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
+ }
+ }
+
+ /* setup baseboard specific GPIO pinmux and config */
+ setup_board_gpio(board_type);
+
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
+
+ /*
+ * The Gateworks System Controller implements a boot
+ * watchdog (always enabled) as a workaround for IMX6 boot related
+ * errata such as:
+ * ERR005768 - no fix
+ * ERR006282 - fixed in silicon r1.3
+ * ERR007117 - fixed in silicon r1.3
+ * ERR007220 - fixed in silicon r1.3
+ * see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf
+ *
+ * Disable the boot watchdog and display/clear the timeout flag if set
+ */
+ i2c_set_bus_num(I2C_GSC);
+ if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) {
+ reg |= (1 << GSC_SC_CTRL1_WDDIS);
+ if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
+ puts("Error: could not disable GSC Watchdog\n");
+ } else {
+ puts("Error: could not disable GSC Watchdog\n");
+ }
+ if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, ®, 1)) {
+ if (reg & (1 << GSC_SC_IRQ_WATCHDOG)) { /* watchdog timeout */
+ puts("GSC boot watchdog timeout detected");
+ reg &= ~(1 << GSC_SC_IRQ_WATCHDOG); /* clear flag */
+ gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, ®, 1);
+ }
+ }
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+
+/* FDT aliases associated with EEPROM config bits */
+const char *fdt_aliases[] = {
+ "ethernet0",
+ "ethernet1",
+ "hdmi_out",
+ "ahci0",
+ "pcie",
+ "ssi0",
+ "ssi1",
+ "lcd0",
+ "lvds0",
+ "lvds1",
+ "usb0",
+ "usb1",
+ "mmc0",
+ "mmc1",
+ "mmc2",
+ "mmc3",
+ "uart0",
+ "uart1",
+ "uart2",
+ "uart3",
+ "uart4",
+ "ipu0",
+ "ipu1",
+ "can0",
+ "mipi_dsi",
+ "mipi_csi",
+ "tzasc0",
+ "tzasc1",
+ "i2c0",
+ "i2c1",
+ "i2c2",
+ "vpu",
+ "csi0",
+ "csi1",
+ "caam",
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ "spi0",
+ "spi1",
+ "spi2",
+ "spi3",
+ "spi4",
+ "spi5",
+ NULL,
+ NULL,
+ "pps",
+ NULL,
+ NULL,
+ NULL,
+ "hdmi_in",
+ "cvbs_out",
+ "cvbs_in",
+ "nand",
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+};
+
+/*
+ * called prior to booting kernel or by 'fdt boardsetup' command
+ *
+ * unless 'fdt_noauto' env var is set we will update the following in the DTB:
+ * - mtd partitions based on mtdparts/mtdids env
+ * - system-serial (board serial num from EEPROM)
+ * - board (full model from EEPROM)
+ * - peripherals removed from DTB if not loaded on board (per EEPROM config)
+ */
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ int bit;
+ struct ventana_board_info *info = &ventana_info;
+ struct node_info nodes[] = {
+ { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */
+ { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
+ };
+ const char *model = getenv("model");
+
+ if (getenv("fdt_noauto")) {
+ puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
+ return;
+ }
+
+ /* Update partition nodes using info from mtdparts env var */
+ puts(" Updating MTD partitions...\n");
+ fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+
+ if (!model) {
+ puts("invalid board info: Leaving FDT fully enabled\n");
+ return;
+ }
+ printf(" Adjusting FDT per EEPROM for %s...\n", model);
+
+ /* board serial number */
+ fdt_setprop(blob, 0, "system-serial", getenv("serial#"),
+ strlen(getenv("serial#") + 1));
+
+ /* board (model contains model from device-tree) */
+ fdt_setprop(blob, 0, "board", info->model,
+ strlen((const char *)info->model) + 1);
+
+ /*
+ * Peripheral Config:
+ * remove nodes by alias path if EEPROM config tells us the
+ * peripheral is not loaded on the board.
+ */
+ for (bit = 0; bit < 64; bit++) {
+ if (!test_bit(bit, info->config))
+ fdt_del_node_and_alias(blob, fdt_aliases[bit]);
+ }
+}
+#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
+
--- /dev/null
+/*
+ * Copyright (C) 2013 Gateworks Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd, nand, sata
+ */
+#ifdef CONFIG_SPI_FLASH
+BOOT_FROM spi
+#else
+BOOT_FROM nand
+#endif
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+/* Memory configuration (size is overridden via eeprom config) */
+#include "../../boundary/nitrogen6x/ddr-setup.cfg"
+#if defined(CONFIG_MX6Q) && CONFIG_DDR_MB == 1024
+ #include "../../boundary/nitrogen6x/1066mhz_4x128mx16.cfg"
+#elif defined(CONFIG_MX6DL) && CONFIG_DDR_MB == 1024
+ #include "../../boundary/nitrogen6x/800mhz_4x128mx16.cfg"
+#elif defined(CONFIG_MX6DL) && CONFIG_DDR_MB == 512
+ #include "../../boundary/nitrogen6x/800mhz_2x128mx16.cfg"
+#elif defined(CONFIG_MX6Q) && CONFIG_DDR_MB == 512
+ #include "../../boundary/nitrogen6x/800mhz_2x128mx16.cfg"
+#else
+ #error "Unsupported CPU/Memory configuration"
+#endif
+#include "clocks.cfg"
--- /dev/null
+/*
+ * Copyright (C) 2013 Gateworks Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _VENTANA_EEPROM_
+#define _VENTANA_EEPROM_
+
+struct ventana_board_info {
+ u8 mac0[6]; /* 0x00: MAC1 */
+ u8 mac1[6]; /* 0x06: MAC2 */
+ u8 res0[12]; /* 0x0C: reserved */
+ u32 serial; /* 0x18: Serial Number (read only) */
+ u8 res1[4]; /* 0x1C: reserved */
+ u8 mfgdate[4]; /* 0x20: MFG date (read only) */
+ u8 res2[7]; /* 0x24 */
+ /* sdram config */
+ u8 sdram_size; /* 0x2B: enum (512,1024,2048) MB */
+ u8 sdram_speed; /* 0x2C: enum (100,133,166,200,267,333,400) MHz */
+ u8 sdram_width; /* 0x2D: enum (32,64) bit */
+ /* cpu config */
+ u8 cpu_speed; /* 0x2E: enum (800,1000,1200) MHz */
+ u8 cpu_type; /* 0x2F: enum (imx6q,imx6d,imx6dl,imx6s) */
+ u8 model[16]; /* 0x30: model string */
+ /* FLASH config */
+ u8 nand_flash_size; /* 0x40: enum (4,8,16,32,64,128) MB */
+ u8 spi_flash_size; /* 0x41: enum (4,8,16,32,64,128) MB */
+
+ /* Config1: SoC Peripherals */
+ u8 config[8]; /* 0x42: loading options */
+
+ u8 res3[4]; /* 0x4A */
+
+ u8 chksum[2]; /* 0x4E */
+};
+
+/* config bits */
+enum {
+ EECONFIG_ETH0,
+ EECONFIG_ETH1,
+ EECONFIG_HDMI_OUT,
+ EECONFIG_SATA,
+ EECONFIG_PCIE,
+ EECONFIG_SSI0,
+ EECONFIG_SSI1,
+ EECONFIG_LCD,
+ EECONFIG_LVDS0,
+ EECONFIG_LVDS1,
+ EECONFIG_USB0,
+ EECONFIG_USB1,
+ EECONFIG_SD0,
+ EECONFIG_SD1,
+ EECONFIG_SD2,
+ EECONFIG_SD3,
+ EECONFIG_UART0,
+ EECONFIG_UART1,
+ EECONFIG_UART2,
+ EECONFIG_UART3,
+ EECONFIG_UART4,
+ EECONFIG_IPU0,
+ EECONFIG_IPU1,
+ EECONFIG_FLEXCAN,
+ EECONFIG_MIPI_DSI,
+ EECONFIG_MIPI_CSI,
+ EECONFIG_TZASC0,
+ EECONFIG_TZASC1,
+ EECONFIG_I2C0,
+ EECONFIG_I2C1,
+ EECONFIG_I2C2,
+ EECONFIG_VPU,
+ EECONFIG_CSI0,
+ EECONFIG_CSI1,
+ EECONFIG_CAAM,
+ EECONFIG_MEZZ,
+ EECONFIG_RES1,
+ EECONFIG_RES2,
+ EECONFIG_RES3,
+ EECONFIG_RES4,
+ EECONFIG_ESPCI0,
+ EECONFIG_ESPCI1,
+ EECONFIG_ESPCI2,
+ EECONFIG_ESPCI3,
+ EECONFIG_ESPCI4,
+ EECONFIG_ESPCI5,
+ EECONFIG_RES5,
+ EECONFIG_RES6,
+ EECONFIG_GPS,
+ EECONFIG_SPIFL0,
+ EECONFIG_SPIFL1,
+ EECONFIG_GSPBATT,
+ EECONFIG_HDMI_IN,
+ EECONFIG_VID_OUT,
+ EECONFIG_VID_IN,
+ EECONFIG_NAND,
+ EECONFIG_RES8,
+ EECONFIG_RES9,
+ EECONFIG_RES10,
+ EECONFIG_RES11,
+ EECONFIG_RES12,
+ EECONFIG_RES13,
+ EECONFIG_RES14,
+ EECONFIG_RES15,
+};
+
+#endif
DEFAULT_PINMUX(ULPI_STP, ULPI, NORMAL, NORMAL, OUTPUT),
/* I2C3 pinmux */
- I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
- I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+ I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* VI pinmux */
VI_PINMUX(CAM_MCLK, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
VI_PINMUX(GPIO_PBB4, VGP4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
/* I2C2 pinmux */
- I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
- I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+ I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* UARTD pinmux */
DEFAULT_PINMUX(GMI_A16, UARTD, NORMAL, NORMAL, OUTPUT),
DEFAULT_PINMUX(KB_ROW9, UARTA, NORMAL, NORMAL, OUTPUT),
/* I2CPWR pinmux (I2C5) */
- I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
- I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+ I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* SYSCLK pinmux */
DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT),
DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
/* I2C1 pinmux */
- I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
- I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+ I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* UARTB pinmux */
DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(ULPI_STP, SPI1, NORMAL, NORMAL, INPUT),
/* I2C3 (TPM) pinmux */
- I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
- I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+ I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* I2C2 pinmux */
- I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
- I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+ I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* UARTD pinmux (UART4 on Servo board, unused) */
DEFAULT_PINMUX(GPIO_PJ7, UARTD, NORMAL, NORMAL, OUTPUT),
DEFAULT_PINMUX(KB_ROW10, UARTA, UP, TRISTATE, INPUT),
/* I2CPWR pinmux (I2C5) */
- I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
- I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+ I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* RTCK pinmux */
DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
/* I2C1 pinmux */
- I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
- I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+ I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* UARTB, GPS */
DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, TRISTATE, INPUT),
#include <asm/arch/power.h>
#include <power/pmic.h>
#include <asm/arch/sromc.h>
-#include <power/max77686_pmic.h>
+#include <lcd.h>
+#include <samsung/misc.h>
DECLARE_GLOBAL_DATA_PTR;
+int __exynos_early_init_f(void)
+{
+ return 0;
+}
+int exynos_early_init_f(void)
+ __attribute__((weak, alias("__exynos_early_init_f")));
+
+int __exynos_power_init(void)
+{
+ return 0;
+}
+int exynos_power_init(void)
+ __attribute__((weak, alias("__exynos_power_init")));
+
#if defined CONFIG_EXYNOS_TMU
/* Boot Time Thermal Analysis for SoC temperature threshold breach */
static void boot_temp_check(void)
board_i2c_init(gd->fdt_blob);
#endif
- return err;
+ return exynos_early_init_f();
}
#endif
#if defined(CONFIG_POWER)
-#ifdef CONFIG_POWER_MAX77686
-static int pmic_reg_update(struct pmic *p, int reg, uint regval)
-{
- u32 val;
- int ret = 0;
-
- ret = pmic_reg_read(p, reg, &val);
- if (ret) {
- debug("%s: PMIC %d register read failed\n", __func__, reg);
- return -1;
- }
- val |= regval;
- ret = pmic_reg_write(p, reg, val);
- if (ret) {
- debug("%s: PMIC %d register write failed\n", __func__, reg);
- return -1;
- }
- return 0;
-}
-
-static int max77686_init(void)
-{
- struct pmic *p;
-
- if (pmic_init(I2C_PMIC))
- return -1;
-
- p = pmic_get("MAX77686_PMIC");
- if (!p)
- return -ENODEV;
-
- if (pmic_probe(p))
- return -1;
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
- return -1;
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
- MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
- return -1;
-
- /* VDD_MIF */
- if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
- MAX77686_BUCK1OUT_1V)) {
- debug("%s: PMIC %d register write failed\n", __func__,
- MAX77686_REG_PMIC_BUCK1OUT);
- return -1;
- }
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
- MAX77686_BUCK1CTRL_EN))
- return -1;
-
- /* VDD_ARM */
- if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
- MAX77686_BUCK2DVS1_1_3V)) {
- debug("%s: PMIC %d register write failed\n", __func__,
- MAX77686_REG_PMIC_BUCK2DVS1);
- return -1;
- }
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
- MAX77686_BUCK2CTRL_ON))
- return -1;
-
- /* VDD_INT */
- if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
- MAX77686_BUCK3DVS1_1_0125V)) {
- debug("%s: PMIC %d register write failed\n", __func__,
- MAX77686_REG_PMIC_BUCK3DVS1);
- return -1;
- }
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
- MAX77686_BUCK3CTRL_ON))
- return -1;
-
- /* VDD_G3D */
- if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
- MAX77686_BUCK4DVS1_1_2V)) {
- debug("%s: PMIC %d register write failed\n", __func__,
- MAX77686_REG_PMIC_BUCK4DVS1);
- return -1;
- }
-
- if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
- MAX77686_BUCK3CTRL_ON))
- return -1;
-
- /* VDD_LDO2 */
- if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
- MAX77686_LD02CTRL1_1_5V | EN_LDO))
- return -1;
-
- /* VDD_LDO3 */
- if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
- MAX77686_LD03CTRL1_1_8V | EN_LDO))
- return -1;
-
- /* VDD_LDO5 */
- if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
- MAX77686_LD05CTRL1_1_8V | EN_LDO))
- return -1;
-
- /* VDD_LDO10 */
- if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
- MAX77686_LD10CTRL1_1_8V | EN_LDO))
- return -1;
-
- return 0;
-}
-#endif
-
int power_init_board(void)
{
- int ret = 0;
-
set_ps_hold_ctrl();
-#ifdef CONFIG_POWER_MAX77686
- ret = max77686_init();
-#endif
-
- return ret;
+ return exynos_power_init();
}
#endif
#ifdef CONFIG_OF_CONTROL
+#ifdef CONFIG_SMC911X
static int decode_sromc(const void *blob, struct fdt_sromc *config)
{
int err;
}
return 0;
}
+#endif
int board_eth_init(bd_t *bis)
{
{
int ret;
+#ifdef CONFIG_SDHCI
+ /* mmc initializattion for available channels */
+ ret = exynos_mmc_init(gd->fdt_blob);
+ if (ret)
+ debug("mmc init failed\n");
+#endif
+#ifdef CONFIG_DWMMC
/* dwmmc initializattion for available channels */
ret = exynos_dwmmc_init(gd->fdt_blob);
if (ret)
debug("dwmmc init failed\n");
+#endif
return ret;
}
#endif
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+ const char *board_name;
+
+ board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
+ printf("Board: %s\n", board_name ? board_name : "unknown");
+
+ return 0;
+}
#endif
+#endif /* CONFIG_OF_CONTROL */
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
return 0;
}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ set_board_info();
+#endif
+#ifdef CONFIG_LCD_MENU
+ keys_init();
+ check_boot_mode();
+#endif
+#ifdef CONFIG_CMD_BMP
+ if (panel_info.logo_on)
+ draw_logo();
+#endif
+ return 0;
+}
+#endif
#include <asm/arch/mmc.h>
#include <asm/arch/periph.h>
#include <asm/arch/pinmux.h>
+#include <usb.h>
DECLARE_GLOBAL_DATA_PTR;
-struct exynos4_gpio_part1 *gpio1;
-struct exynos4_gpio_part2 *gpio2;
-int board_init(void)
+u32 get_board_rev(void)
{
- gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
- gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
-
- gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
return 0;
}
-static int board_uart_init(void)
+int exynos_init(void)
{
- int err;
-
- err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE);
- if (err) {
- debug("UART0 not configured\n");
- return err;
- }
-
- err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE);
- if (err) {
- debug("UART1 not configured\n");
- return err;
- }
-
- err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE);
- if (err) {
- debug("UART2 not configured\n");
- return err;
- }
-
- err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
- if (err) {
- debug("UART3 not configured\n");
- return err;
- }
-
return 0;
}
-#ifdef CONFIG_BOARD_EARLY_INIT_F
-int board_early_init_f(void)
-{
- int err;
- err = board_uart_init();
- if (err) {
- debug("UART init failed\n");
- return err;
- }
- return err;
-}
-#endif
-
-int dram_init(void)
+int board_usb_init(int index, enum usb_init_type init)
{
- gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
- + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
- + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
- + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
-
return 0;
}
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, \
- PHYS_SDRAM_1_SIZE);
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, \
- PHYS_SDRAM_2_SIZE);
- gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
- gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, \
- PHYS_SDRAM_3_SIZE);
- gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
- gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, \
- PHYS_SDRAM_4_SIZE);
-}
-
-#ifdef CONFIG_DISPLAY_BOARDINFO
-int checkboard(void)
+#ifdef CONFIG_USB_CABLE_CHECK
+int usb_cable_connected(void)
{
- printf("\nBoard: ORIGEN\n");
return 0;
}
#endif
-#ifdef CONFIG_GENERIC_MMC
-int board_mmc_init(bd_t *bis)
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int exynos_early_init_f(void)
{
- int i, err;
-
- /*
- * MMC2 SD card GPIO:
- *
- * GPK2[0] SD_2_CLK(2)
- * GPK2[1] SD_2_CMD(2)
- * GPK2[2] SD_2_CDn
- * GPK2[3:6] SD_2_DATA[0:3](2)
- */
- for (i = 0; i < 7; i++) {
- /* GPK2[0:6] special function 2 */
- s5p_gpio_cfg_pin(&gpio2->k2, i, GPIO_FUNC(0x2));
-
- /* GPK2[0:6] drv 4x */
- s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X);
-
- /* GPK2[0:1] pull disable */
- if (i == 0 || i == 1) {
- s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE);
- continue;
- }
-
- /* GPK2[2:6] pull up */
- s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_UP);
- }
-
- err = s5p_mmc_init(2, 4);
- return err;
+ return 0;
}
#endif
return 0;
}
-#ifdef CONFIG_DISPLAY_BOARDINFO
-int checkboard(void)
-{
- const char *board_name;
-
- board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
- if (board_name == NULL)
- printf("\nUnknown Board\n");
- else
- printf("\nBoard: %s\n", board_name);
-
- return 0;
-}
-#endif
-
#ifdef CONFIG_LCD
void exynos_cfg_lcd_gpio(void)
{
}
}
+#if defined(CONFIG_POWER)
+#ifdef CONFIG_POWER_MAX77686
+static int pmic_reg_update(struct pmic *p, int reg, uint regval)
+{
+ u32 val;
+ int ret = 0;
+
+ ret = pmic_reg_read(p, reg, &val);
+ if (ret) {
+ debug("%s: PMIC %d register read failed\n", __func__, reg);
+ return -1;
+ }
+ val |= regval;
+ ret = pmic_reg_write(p, reg, val);
+ if (ret) {
+ debug("%s: PMIC %d register write failed\n", __func__, reg);
+ return -1;
+ }
+ return 0;
+}
+
+static int max77686_init(void)
+{
+ struct pmic *p;
+
+ if (pmic_init(I2C_PMIC))
+ return -1;
+
+ p = pmic_get("MAX77686_PMIC");
+ if (!p)
+ return -ENODEV;
+
+ if (pmic_probe(p))
+ return -1;
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
+ return -1;
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
+ MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
+ return -1;
+
+ /* VDD_MIF */
+ if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
+ MAX77686_BUCK1OUT_1V)) {
+ debug("%s: PMIC %d register write failed\n", __func__,
+ MAX77686_REG_PMIC_BUCK1OUT);
+ return -1;
+ }
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
+ MAX77686_BUCK1CTRL_EN))
+ return -1;
+
+ /* VDD_ARM */
+ if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
+ MAX77686_BUCK2DVS1_1_3V)) {
+ debug("%s: PMIC %d register write failed\n", __func__,
+ MAX77686_REG_PMIC_BUCK2DVS1);
+ return -1;
+ }
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
+ MAX77686_BUCK2CTRL_ON))
+ return -1;
+
+ /* VDD_INT */
+ if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
+ MAX77686_BUCK3DVS1_1_0125V)) {
+ debug("%s: PMIC %d register write failed\n", __func__,
+ MAX77686_REG_PMIC_BUCK3DVS1);
+ return -1;
+ }
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
+ MAX77686_BUCK3CTRL_ON))
+ return -1;
+
+ /* VDD_G3D */
+ if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
+ MAX77686_BUCK4DVS1_1_2V)) {
+ debug("%s: PMIC %d register write failed\n", __func__,
+ MAX77686_REG_PMIC_BUCK4DVS1);
+ return -1;
+ }
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
+ MAX77686_BUCK3CTRL_ON))
+ return -1;
+
+ /* VDD_LDO2 */
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
+ MAX77686_LD02CTRL1_1_5V | EN_LDO))
+ return -1;
+
+ /* VDD_LDO3 */
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
+ MAX77686_LD03CTRL1_1_8V | EN_LDO))
+ return -1;
+
+ /* VDD_LDO5 */
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
+ MAX77686_LD05CTRL1_1_8V | EN_LDO))
+ return -1;
+
+ /* VDD_LDO10 */
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
+ MAX77686_LD10CTRL1_1_8V | EN_LDO))
+ return -1;
+
+ return 0;
+}
+#endif /* CONFIG_POWER_MAX77686 */
+
+int exynos_power_init(void)
+{
+ int ret = 0;
+
+#ifdef CONFIG_POWER_MAX77686
+ ret = max77686_init();
+#endif
+ return ret;
+}
+#endif /* CONFIG_POWER */
+
#ifdef CONFIG_LCD
void exynos_cfg_lcd_gpio(void)
{
{
return 0;
}
-
-#ifdef CONFIG_DISPLAY_BOARDINFO
-int checkboard(void)
-{
- const char *board_name;
-
- board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
- if (board_name == NULL)
- printf("\nUnknown Board\n");
- else
- printf("\nBoard: %s\n", board_name);
-
- return 0;
-}
-#endif
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/gpio.h>
-#include <asm/arch/mmc.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/clock.h>
-#include <asm/arch/clk.h>
#include <asm/arch/mipi_dsim.h>
#include <asm/arch/watchdog.h>
#include <asm/arch/power.h>
#include <power/pmic.h>
#include <usb/s3c_udc.h>
#include <power/max8997_pmic.h>
-#include <libtizen.h>
#include <power/max8997_muic.h>
#include <power/battery.h>
#include <power/max17042_fg.h>
+#include <libtizen.h>
#include <usb.h>
#include <usb_mass_storage.h>
-#include <samsung/misc.h>
#include "setup.h"
static void check_hw_revision(void);
struct s3c_plat_otg_data s5pc210_otg_data;
-int board_init(void)
+int exynos_init(void)
{
- gd->bd->bi_boot_params = CONFIG_SYS_SPL_ARGS_ADDR;
-
check_hw_revision();
printf("HW Revision:\t0x%x\n", board_rev);
return 0;
}
-int power_init_board(void)
+int exynos_power_init(void)
{
int chrg, ret;
struct power_battery *pb;
return 0;
}
-int dram_init(void)
-{
- gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
- get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) +
- get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) +
- get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
-
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
- gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
- gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
- gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
- gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-}
-
static unsigned int get_hw_revision(void)
{
struct exynos4_gpio_part1 *gpio =
board_rev |= hwrev;
}
-#ifdef CONFIG_DISPLAY_BOARDINFO
-int checkboard(void)
-{
- puts("Board:\tTRATS\n");
- return 0;
-}
-#endif
-
-#ifdef CONFIG_GENERIC_MMC
-int board_mmc_init(bd_t *bis)
-{
- struct exynos4_gpio_part2 *gpio =
- (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
- int err;
-
- /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
- s5p_gpio_direction_output(&gpio->k0, 2, 1);
- s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE);
-
- /*
- * MMC device init
- * mmc0 : eMMC (8-bit buswidth)
- * mmc2 : SD card (4-bit buswidth)
- */
- err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
- if (err)
- debug("SDMMC0 not configured\n");
- else
- err = s5p_mmc_init(0, 8);
-
- /* T-flash detect */
- s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf);
- s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP);
-
- /*
- * Check the T-flash detect pin
- * GPX3[4] T-flash detect pin
- */
- if (!s5p_gpio_get_value(&gpio->x3, 4)) {
- err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
- if (err)
- debug("SDMMC2 not configured\n");
- else
- err = s5p_mmc_init(2, 4);
- }
-
- return err;
-}
-#endif
#ifdef CONFIG_USB_GADGET
static int s5pc210_phy_control(int on)
writel(0, (unsigned int)&pwr->arm_core1_configuration);
}
-static void board_uart_init(void)
+static void exynos_uart_init(void)
{
- struct exynos4_gpio_part1 *gpio1 =
- (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
struct exynos4_gpio_part2 *gpio2 =
(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
- int i;
-
- /*
- * UART2 GPIOs
- * GPA1CON[0] = UART_2_RXD(2)
- * GPA1CON[1] = UART_2_TXD(2)
- * GPA1CON[2] = I2C_3_SDA (3)
- * GPA1CON[3] = I2C_3_SCL (3)
- */
-
- for (i = 0; i < 4; i++) {
- s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE);
- s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2));
- }
/* UART_SEL GPY4[7] (part2) at EXYNOS4 */
s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP);
s5p_gpio_direction_output(&gpio2->y4, 7, 1);
}
-int board_early_init_f(void)
+int exynos_early_init_f(void)
{
wdt_stop();
pmic_reset();
board_clock_init();
- board_uart_init();
+ exynos_uart_init();
board_power_init();
return 0;
s5p_gpio_direction_output(&gpio2->y4, 5, 1);
}
-static int lcd_power(void)
+int lcd_power(void)
{
int ret = 0;
struct pmic *p = pmic_get("MAX8997_PMIC");
return 0;
}
-static struct mipi_dsim_config dsim_config = {
- .e_interface = DSIM_VIDEO,
- .e_virtual_ch = DSIM_VIRTUAL_CH_0,
- .e_pixel_format = DSIM_24BPP_888,
- .e_burst_mode = DSIM_BURST_SYNC_EVENT,
- .e_no_data_lane = DSIM_DATA_LANE_4,
- .e_byte_clk = DSIM_PLL_OUT_DIV8,
- .hfp = 1,
-
- .p = 3,
- .m = 120,
- .s = 1,
-
- /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
- .pll_stable_time = 500,
-
- /* escape clk : 10MHz */
- .esc_clk = 20 * 1000000,
-
- /* stop state holding counter after bta change count 0 ~ 0xfff */
- .stop_holding_cnt = 0x7ff,
- /* bta timeout 0 ~ 0xff */
- .bta_timeout = 0xff,
- /* lp rx timeout 0 ~ 0xffff */
- .rx_timeout = 0xffff,
-};
-
-static struct exynos_platform_mipi_dsim s6e8ax0_platform_data = {
- .lcd_panel_info = NULL,
- .dsim_config = &dsim_config,
-};
-
-static struct mipi_dsim_lcd_device mipi_lcd_device = {
- .name = "s6e8ax0",
- .id = -1,
- .bus_id = 0,
- .platform_data = (void *)&s6e8ax0_platform_data,
-};
-
-static int mipi_power(void)
+int mipi_power(void)
{
int ret = 0;
struct pmic *p = pmic_get("MAX8997_PMIC");
return 0;
}
-vidinfo_t panel_info = {
- .vl_freq = 60,
- .vl_col = 720,
- .vl_row = 1280,
- .vl_width = 720,
- .vl_height = 1280,
- .vl_clkp = CONFIG_SYS_HIGH,
- .vl_hsp = CONFIG_SYS_LOW,
- .vl_vsp = CONFIG_SYS_LOW,
- .vl_dp = CONFIG_SYS_LOW,
- .vl_bpix = 4, /* Bits per pixel, 2^4 = 16 */
-
- /* s6e8ax0 Panel infomation */
- .vl_hspw = 5,
- .vl_hbpd = 10,
- .vl_hfpd = 10,
-
- .vl_vspw = 2,
- .vl_vbpd = 1,
- .vl_vfpd = 13,
- .vl_cmd_allow_len = 0xf,
-
- .win_id = 3,
- .dual_lcd_enabled = 0,
-
- .init_delay = 0,
- .power_on_delay = 0,
- .reset_delay = 0,
- .interface_mode = FIMD_RGB_INTERFACE,
- .mipi_enabled = 1,
-};
-
-void init_panel_info(vidinfo_t *vid)
+void exynos_lcd_misc_init(vidinfo_t *vid)
{
- vid->logo_on = 1,
- vid->resolution = HD_RESOLUTION,
- vid->rgb_mode = MODE_RGB_P,
-
#ifdef CONFIG_TIZEN
get_tizen_logo_info(vid);
#endif
- mipi_lcd_device.reverse_panel = 1;
-
- strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name);
- s6e8ax0_platform_data.lcd_power = lcd_power;
- s6e8ax0_platform_data.mipi_power = mipi_power;
- s6e8ax0_platform_data.phy_enable = set_mipi_phy_ctrl;
- s6e8ax0_platform_data.lcd_panel_info = (void *)vid;
- exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device);
+#ifdef CONFIG_S6E8AX0
s6e8ax0_init();
- exynos_set_dsim_platform_data(&s6e8ax0_platform_data);
-
setenv("lcdinfo", "lcd=s6e8ax0");
-}
-
-#ifdef CONFIG_MISC_INIT_R
-int misc_init_r(void)
-{
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
- set_board_info();
-#endif
-#ifdef CONFIG_LCD_MENU
- keys_init();
- check_boot_mode();
#endif
-#ifdef CONFIG_CMD_BMP
- if (panel_info.logo_on)
- draw_logo();
-#endif
- return 0;
}
-#endif
#include <common.h>
#include <lcd.h>
-#include <asm/io.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/mmc.h>
-#include <asm/arch/power.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/mipi_dsim.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/power.h>
+#include <asm/arch/mipi_dsim.h>
#include <power/pmic.h>
#include <power/max77686_pmic.h>
#include <power/battery.h>
#include <usb.h>
#include <usb/s3c_udc.h>
#include <usb_mass_storage.h>
-#include <samsung/misc.h>
DECLARE_GLOBAL_DATA_PTR;
board_rev = modelrev << 8;
}
-#ifdef CONFIG_DISPLAY_BOARDINFO
-int checkboard(void)
-{
- puts("Board:\tTRATS2\n");
- printf("HW Revision:\t0x%04x\n", board_rev);
-
- return 0;
-}
-#endif
-
u32 get_board_rev(void)
{
return board_rev;
}
#endif
-int board_early_init_f(void)
+int exynos_early_init_f(void)
{
- check_hw_revision();
board_external_gpio_init();
- gd->flags |= GD_FLG_DISABLE_CONSOLE;
-
return 0;
}
static int pmic_init_max77686(void);
-int board_init(void)
+int exynos_init(void)
{
- struct exynos4_power *pwr =
- (struct exynos4_power *)samsung_get_base_power();
-
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- /* workaround: clear INFORM4..5 */
- writel(0, (unsigned int)&pwr->inform4);
- writel(0, (unsigned int)&pwr->inform5);
+ check_hw_revision();
+ printf("HW Revision:\t0x%04x\n", board_rev);
return 0;
}
-int power_init_board(void)
+int exynos_power_init(void)
{
int chrg;
struct power_battery *pb;
return 0;
}
-int dram_init(void)
-{
- u32 size_mb;
-
- size_mb = (get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
- get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) +
- get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) +
- get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE)) >> 20;
-
- gd->ram_size = size_mb << 20;
-
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
- gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
- gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
- gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
- gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- int err0, err2 = 0;
-
- gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2();
-
- /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
- s5p_gpio_direction_output(&gpio2->k0, 2, 1);
- s5p_gpio_set_pull(&gpio2->k0, 2, GPIO_PULL_NONE);
-
- /*
- * eMMC GPIO:
- * SDR 8-bit@48MHz at MMC0
- * GPK0[0] SD_0_CLK(2)
- * GPK0[1] SD_0_CMD(2)
- * GPK0[2] SD_0_CDn -> Not used
- * GPK0[3:6] SD_0_DATA[0:3](2)
- * GPK1[3:6] SD_0_DATA[0:3](3)
- *
- * DDR 4-bit@26MHz at MMC4
- * GPK0[0] SD_4_CLK(3)
- * GPK0[1] SD_4_CMD(3)
- * GPK0[2] SD_4_CDn -> Not used
- * GPK0[3:6] SD_4_DATA[0:3](3)
- * GPK1[3:6] SD_4_DATA[4:7](4)
- */
-
- err0 = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
-
- /*
- * MMC device init
- * mmc0 : eMMC (8-bit buswidth)
- * mmc2 : SD card (4-bit buswidth)
- */
- if (err0)
- debug("SDMMC0 not configured\n");
- else
- err0 = s5p_mmc_init(0, 8);
-
- /* T-flash detect */
- s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf);
- s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP);
-
- /*
- * Check the T-flash detect pin
- * GPX3[4] T-flash detect pin
- */
- if (!s5p_gpio_get_value(&gpio2->x3, 4)) {
- err2 = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
- if (err2)
- debug("SDMMC2 not configured\n");
- else
- err2 = s5p_mmc_init(2, 4);
- }
-
- return err0 & err2;
-}
-
#ifdef CONFIG_USB_GADGET
static int s5pc210_phy_control(int on)
{
*/
#ifdef CONFIG_LCD
-static struct mipi_dsim_config dsim_config = {
- .e_interface = DSIM_VIDEO,
- .e_virtual_ch = DSIM_VIRTUAL_CH_0,
- .e_pixel_format = DSIM_24BPP_888,
- .e_burst_mode = DSIM_BURST_SYNC_EVENT,
- .e_no_data_lane = DSIM_DATA_LANE_4,
- .e_byte_clk = DSIM_PLL_OUT_DIV8,
- .hfp = 1,
-
- .p = 3,
- .m = 120,
- .s = 1,
-
- /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
- .pll_stable_time = 500,
-
- /* escape clk : 10MHz */
- .esc_clk = 20 * 1000000,
-
- /* stop state holding counter after bta change count 0 ~ 0xfff */
- .stop_holding_cnt = 0x7ff,
- /* bta timeout 0 ~ 0xff */
- .bta_timeout = 0xff,
- /* lp rx timeout 0 ~ 0xffff */
- .rx_timeout = 0xffff,
-};
-
-static struct exynos_platform_mipi_dsim dsim_platform_data = {
- .lcd_panel_info = NULL,
- .dsim_config = &dsim_config,
-};
-
-static struct mipi_dsim_lcd_device mipi_lcd_device = {
- .name = "s6e8ax0",
- .id = -1,
- .bus_id = 0,
- .platform_data = (void *)&dsim_platform_data,
-};
-
-static int mipi_power(void)
+int mipi_power(void)
{
struct pmic *p = pmic_get("MAX77686_PMIC");
s5p_gpio_set_value(&gpio1->f2, 1, 1);
}
-vidinfo_t panel_info = {
- .vl_freq = 60,
- .vl_col = 720,
- .vl_row = 1280,
- .vl_width = 720,
- .vl_height = 1280,
- .vl_clkp = CONFIG_SYS_HIGH,
- .vl_hsp = CONFIG_SYS_LOW,
- .vl_vsp = CONFIG_SYS_LOW,
- .vl_dp = CONFIG_SYS_LOW,
- .vl_bpix = 4, /* Bits per pixel, 2^4 = 16 */
-
- /* s6e8ax0 Panel infomation */
- .vl_hspw = 5,
- .vl_hbpd = 10,
- .vl_hfpd = 10,
-
- .vl_vspw = 2,
- .vl_vbpd = 1,
- .vl_vfpd = 13,
- .vl_cmd_allow_len = 0xf,
- .mipi_enabled = 1,
-
- .dual_lcd_enabled = 0,
-
- .init_delay = 0,
- .power_on_delay = 25,
- .reset_delay = 0,
- .interface_mode = FIMD_RGB_INTERFACE,
-};
-
-void init_panel_info(vidinfo_t *vid)
+void exynos_lcd_misc_init(vidinfo_t *vid)
{
- vid->logo_on = 1;
- vid->resolution = HD_RESOLUTION;
- vid->rgb_mode = MODE_RGB_P;
-
- vid->power_on_delay = 30;
-
- mipi_lcd_device.reverse_panel = 1;
-
#ifdef CONFIG_TIZEN
get_tizen_logo_info(vid);
#endif
-
- strcpy(dsim_platform_data.lcd_panel_name, mipi_lcd_device.name);
- dsim_platform_data.mipi_power = mipi_power;
- dsim_platform_data.phy_enable = set_mipi_phy_ctrl;
- dsim_platform_data.lcd_panel_info = (void *)vid;
- exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device);
-
+#ifdef CONFIG_S6E8AX0
s6e8ax0_init();
-
- exynos_set_dsim_platform_data(&dsim_platform_data);
-}
-#endif /* LCD */
-
-#ifdef CONFIG_MISC_INIT_R
-int misc_init_r(void)
-{
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
- set_board_info();
-#endif
-#ifdef CONFIG_LCD_MENU
- keys_init();
- check_boot_mode();
#endif
-#ifdef CONFIG_CMD_BMP
- if (panel_info.logo_on)
- draw_logo();
-#endif
- return 0;
}
-#endif
+#endif /* LCD */
#include <asm/gpio.h>
#include <asm/arch/adc.h>
#include <asm/arch/gpio.h>
-#include <asm/arch/mmc.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/watchdog.h>
-#include <libtizen.h>
#include <ld9040.h>
#include <power/pmic.h>
+#include <usb.h>
#include <usb/s3c_udc.h>
#include <asm/arch/cpu.h>
#include <power/max8998_pmic.h>
+#include <libtizen.h>
#include <samsung/misc.h>
+#include <usb_mass_storage.h>
DECLARE_GLOBAL_DATA_PTR;
static void init_pmic_lcd(void);
-int power_init_board(void)
+int exynos_power_init(void)
{
int ret;
return 0;
}
-int dram_init(void)
-{
- gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
- get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
-
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-}
-
static unsigned short get_adc_value(int channel)
{
struct s5p_adc *adc = (struct s5p_adc *)samsung_get_base_adc();
board_rev |= hwrev;
}
-#ifdef CONFIG_DISPLAY_BOARDINFO
-int checkboard(void)
-{
- puts("Board:\tUniversal C210\n");
- return 0;
-}
-#endif
-
-#ifdef CONFIG_GENERIC_MMC
-int board_mmc_init(bd_t *bis)
-{
- int err;
-
- switch (get_hwrev()) {
- case 0:
- /*
- * Set the low to enable LDO_EN
- * But when you use the test board for eMMC booting
- * you should set it HIGH since it removes the inverter
- */
- /* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */
- s5p_gpio_direction_output(&gpio1->e3, 6, 0);
- break;
- default:
- /*
- * Default reset state is High and there's no inverter
- * But set it as HIGH to ensure
- */
- /* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */
- s5p_gpio_direction_output(&gpio1->e1, 3, 1);
- break;
- }
-
- /*
- * MMC device init
- * mmc0 : eMMC (8-bit buswidth)
- * mmc2 : SD card (4-bit buswidth)
- */
- err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
- if (err)
- debug("SDMMC0 not configured\n");
- else
- err = s5p_mmc_init(0, 8);
-
- /* T-flash detect */
- s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf);
- s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP);
-
- /*
- * Check the T-flash detect pin
- * GPX3[4] T-flash detect pin
- */
- if (!s5p_gpio_get_value(&gpio2->x3, 4)) {
- err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
- if (err)
- debug("SDMMC2 not configured\n");
- else
- err = s5p_mmc_init(2, 4);
- }
-
- return err;
-
-}
-#endif
-
#ifdef CONFIG_USB_GADGET
static int s5pc210_phy_control(int on)
{
};
#endif
-int board_early_init_f(void)
+int board_usb_init(int index, enum usb_init_type init)
+{
+ debug("USB_udc_probe\n");
+ return s3c_udc_probe(&s5pc210_otg_data);
+}
+
+#ifdef CONFIG_USB_CABLE_CHECK
+int usb_cable_connected(void)
+{
+ return 0;
+}
+#endif
+
+int exynos_early_init_f(void)
{
wdt_stop();
spi_init();
}
+int mipi_power(void)
+{
+ return 0;
+}
+
void exynos_reset_lcd(void)
{
s5p_gpio_set_value(&gpio2->y4, 5, 1);
pmic_set_output(p, MAX8998_REG_ONOFF2, MAX8998_LDO7, LDO_ON);
}
-vidinfo_t panel_info = {
- .vl_freq = 60,
- .vl_col = 480,
- .vl_row = 800,
- .vl_width = 480,
- .vl_height = 800,
- .vl_clkp = CONFIG_SYS_HIGH,
- .vl_hsp = CONFIG_SYS_HIGH,
- .vl_vsp = CONFIG_SYS_HIGH,
- .vl_dp = CONFIG_SYS_HIGH,
-
- .vl_bpix = 4, /* Bits per pixel */
-
- /* LD9040 LCD Panel */
- .vl_hspw = 2,
- .vl_hbpd = 16,
- .vl_hfpd = 16,
-
- .vl_vspw = 2,
- .vl_vbpd = 8,
- .vl_vfpd = 8,
- .vl_cmd_allow_len = 0xf,
-
- .win_id = 0,
- .dual_lcd_enabled = 0,
-
- .init_delay = 0,
- .power_on_delay = 10000,
- .reset_delay = 10000,
- .interface_mode = FIMD_RGB_INTERFACE,
- .mipi_enabled = 0,
-};
-
void exynos_cfg_ldo(void)
{
ld9040_cfg_ldo();
ld9040_enable_ldo(onoff);
}
-void init_panel_info(vidinfo_t *vid)
-{
- vid->logo_on = 1;
- vid->resolution = HD_RESOLUTION;
- vid->rgb_mode = MODE_RGB_P;
-
-#ifdef CONFIG_TIZEN
- get_tizen_logo_info(vid);
-#endif
-
- /* for LD9040. */
- vid->pclk_name = 1; /* MPLL */
- vid->sclk_div = 1;
-
- setenv("lcdinfo", "lcd=ld9040");
-}
-
-int board_init(void)
+int exynos_init(void)
{
gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ switch (get_hwrev()) {
+ case 0:
+ /*
+ * Set the low to enable LDO_EN
+ * But when you use the test board for eMMC booting
+ * you should set it HIGH since it removes the inverter
+ */
+ /* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */
+ s5p_gpio_direction_output(&gpio1->e3, 6, 0);
+ break;
+ default:
+ /*
+ * Default reset state is High and there's no inverter
+ * But set it as HIGH to ensure
+ */
+ /* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */
+ s5p_gpio_direction_output(&gpio1->e1, 3, 1);
+ break;
+ }
#ifdef CONFIG_SOFT_SPI
soft_spi_init();
return 0;
}
-#ifdef CONFIG_MISC_INIT_R
-int misc_init_r(void)
+void exynos_lcd_misc_init(vidinfo_t *vid)
{
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
- set_board_info();
-#endif
-#ifdef CONFIG_LCD_MENU
- keys_init();
- check_boot_mode();
-#endif
-#ifdef CONFIG_CMD_BMP
- if (panel_info.logo_on)
- draw_logo();
+#ifdef CONFIG_TIZEN
+ get_tizen_logo_info(vid);
#endif
- return 0;
+
+ /* for LD9040. */
+ vid->pclk_name = 1; /* MPLL */
+ vid->sclk_div = 1;
+
+ setenv("lcdinfo", "lcd=ld9040");
}
-#endif
factoryset_setenv();
- /* Reset SMSC LAN9303 switch for default configuration */
- gpio_request(GPIO_LAN9303_NRST, "nRST");
- gpio_direction_output(GPIO_LAN9303_NRST, 0);
- /* assert active low reset for 200us */
- udelay(200);
- gpio_set_value(GPIO_LAN9303_NRST, 1);
-
/* Set rgmii mode and enable rmii clock to be sourced from chip */
writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
n += rv;
return n;
}
+
+static int do_switch_reset(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ /* Reset SMSC LAN9303 switch for default configuration */
+ gpio_request(GPIO_LAN9303_NRST, "nRST");
+ gpio_direction_output(GPIO_LAN9303_NRST, 0);
+ /* assert active low reset for 200us */
+ udelay(200);
+ gpio_set_value(GPIO_LAN9303_NRST, 1);
+
+ return 0;
+};
+
+U_BOOT_CMD(
+ switch_rst, CONFIG_SYS_MAXARGS, 1, do_switch_reset,
+ "Reset LAN9303 switch via its reset pin",
+ ""
+);
#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
.dynstr : { *(.dynstr*) }
.dynamic : { *(.dynamic*) }
.hash : { *(.hash*) }
+ .gnu.hash : { *(.gnu.hash) }
.plt : { *(.plt*) }
.interp : { *(.interp*) }
.gnu : { *(.gnu*) }
#include <miiphy.h>
#include <netdev.h>
#include <linux/fb.h>
+#include <phy.h>
+#include <input.h>
DECLARE_GLOBAL_DATA_PTR;
MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
-iomux_v3_cfg_t const usdhc1_pads[] = {
+static iomux_v3_cfg_t const usdhc1_pads[] = {
MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
Active arm armv7 mx6 freescale mx6sabresd mx6dlsabresd mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL Fabio Estevam <fabio.estevam@freescale.com>
Active arm armv7 mx6 freescale mx6sabresd mx6qsabresd mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Fabio Estevam <fabio.estevam@freescale.com>
Active arm armv7 mx6 freescale mx6slevk mx6slevk mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL Fabio Estevam <fabio.estevam@freescale.com>
+Active arm armv7 mx6 gateworks gw_ventana gwventanadl gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6DL,DDR_MB=512 Tim Harvey <tharvey@gateworks.com>
+Active arm armv7 mx6 gateworks gw_ventana gwventanadl1g gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6DL,DDR_MB=1024 Tim Harvey <tharvey@gateworks.com>
+Active arm armv7 mx6 gateworks gw_ventana gwventanaq gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=512 Tim Harvey <tharvey@gateworks.com>
+Active arm armv7 mx6 gateworks gw_ventana gwventanaq1g gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=1024 Tim Harvey <tharvey@gateworks.com>
+Active arm armv7 mx6 gateworks gw_ventana gwventanaq1gspi gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=1024,SPI_FLASH Tim Harvey <tharvey@gateworks.com>
Active arm armv7 mx6 solidrun hummingboard hummingboard_solo hummingboard:IMX_CONFIG=board/solidrun/hummingboard/solo.cfg,MX6S,DDR_MB=512 Jon Nettleton <jon.nettleton@gmail.com>
Active arm armv7 omap3 - overo omap3_overo - Steve Sakoman <sakoman@gmail.com>
Active arm armv7 omap3 - pandora omap3_pandora - Grazvydas Ignotas <notasas@gmail.com>
--- /dev/null
+Exynos MIPI-DSIM Controller
+=========================
+
+Required properties:
+SOC specific:
+ compatible: should be "samsung,exynos-mipi-dsi"
+ reg: Base address of MIPI-DSIM IP.
+
+Board specific:
+ samsung,dsim-config-e-interface: interface to be used (RGB interface
+ for main display or CPU interface for main or sub display).
+ samsung,dsim-config-e-virtual-ch: virtual channel number that main
+ or sub display uses.
+ samsung,dsim-config-e-pixel-format: pixel stream format for main
+ or sub display.
+ samsung,dsim-config-e-burst-mode: selects Burst mode in Video mode.
+ in Non-burst mode, RGB data area is filled with RGB data and
+ NULL packets, according to input bandwidth of RGB interface.
+ samsung,dsim-config-e-no-data-lane: data lane count used by Master.
+ samsung,dsim-config-e-byte-clk: select byte clock source.
+ It must be DSIM_PLL_OUT_DIV8.
+ DSIM_EXT_CLK_DIV8 and DSIM_EXT_CLK_BYPASSS are not supported.
+ samsung,dsim-config-hfp: HFP disable mode.
+ If set, DSI master ignores HFP area in VIDEO mode.
+ In command mode, this variable is ignored.
+ samsung,dsim-config-p: P value for PMS setting.
+ samsung,dsim-config-m: M value for PMS setting.
+ samsung,dsim-config-s: S value for PMS setting.
+ samsung,dsim-config-pll-stable-time: the PLL Timer for stability
+ of the ganerated clock.
+ samsung,dsim-config-esc-clk: escape clock frequency for getting
+ the escape clock prescaler value.
+ samsung,dsim-config-stop-holding-cnt: the interval value between
+ transmitting read packet (or write "set_tear_on" command)
+ and BTA request. After transmitting read packet or write
+ "set_tear_on" command, BTA requests to D-PHY automatically.
+ This counter value specifies the interval between them.
+ samsung,dsim-config-bta-timeout: the timer for BTA. This register
+ specifies time out from BTA request to change the direction
+ with respect to Tx escape clock.
+ samsung,dsim-config-rx-timeout: the timer for LP Rx mode timeout.
+ this register specifies time out on how long RxValid deasserts,
+ after RxLpdt asserts with respect to Tx escape clock.
+ - RxValid specifies Rx data valid indicator.
+ - RxLpdt specifies an indicator that D-PHY is under RxLpdt mode
+ - RxValid and RxLpdt specifies signal from D-PHY.
+ samsung,dsim-device-name: name of the device.
+ samsung,dsim-device-id: unique device id.
+ samsung,dsim-device-bus_id: bus id for identifing connected bus
+ and this bus id should be same as id of mipi_dsim_device.
+
+Optional properties:
+ samsung,dsim-device-reverse-panel: reverse panel.
+
+Example:
+ mipidsi@11c80000 {
+ compatible = "samsung,exynos-mipi-dsi";
+ reg = <0x11c80000 0x5c>;
+
+ samsung,dsim-config-e-interface = <1>;
+ samsung,dsim-config-e-virtual-ch = <0>;
+ samsung,dsim-config-e-pixel-format = <7>;
+ samsung,dsim-config-e-burst-mode = <1>;
+ samsung,dsim-config-e-no-data-lane = <3>;
+ samsung,dsim-config-e-byte-clk = <0>;
+ samsung,dsim-config-hfp = <1>;
+
+ samsung,dsim-config-p = <3>;
+ samsung,dsim-config-m = <120>;
+ samsung,dsim-config-s = <1>;
+
+ samsung,dsim-config-pll-stable-time = <500>;
+ samsung,dsim-config-esc-clk = <20000000>;
+ samsung,dsim-config-stop-holding-cnt = <0x7ff>;
+ samsung,dsim-config-bta-timeout = <0xff>;
+ samsung,dsim-config-rx-timeout = <0xffff>;
+
+ samsung,dsim-device-id = <0xffffffff>;
+ samsung,dsim-device-bus-id = <0>;
+
+ samsung,dsim-device-reverse-panel = <1>;
+ };
static bool dfu_reset_request;
static LIST_HEAD(dfu_list);
static int dfu_alt_num;
+static int alt_num_cnt;
bool dfu_reset(void)
{
if (t)
free(t);
INIT_LIST_HEAD(&dfu_list);
+
+ alt_num_cnt = 0;
}
int dfu_config_entities(char *env, char *interface, int num)
for (i = 0; i < dfu_alt_num; i++) {
s = strsep(&env, ";");
- ret = dfu_fill_entity(&dfu[i], s, i, interface, num);
+ ret = dfu_fill_entity(&dfu[i], s, alt_num_cnt, interface, num);
if (ret)
return -1;
list_add_tail(&dfu[i].list, &dfu_list);
+ alt_num_cnt++;
}
return 0;
obj-$(CONFIG_GPIO_LED) += gpio_led.o
obj-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o
obj-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o
+obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o
obj-$(CONFIG_NS87308) += ns87308.o
obj-$(CONFIG_PDSP188x) += pdsp188x.o
obj-$(CONFIG_STATUS_LED) += status_led.o
--- /dev/null
+/*
+ * Freescale i.MX28 OCOTP Driver
+ *
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Note: The i.MX23/i.MX28 OCOTP block is a predecessor to the OCOTP block
+ * used in i.MX6 . While these blocks are very similar at the first
+ * glance, by digging deeper, one will notice differences (like the
+ * tight dependence on MXS power block, some completely new registers
+ * etc.) which would make common driver an ifdef nightmare :-(
+ */
+
+#include <common.h>
+#include <fuse.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+#define MXS_OCOTP_TIMEOUT 100000
+
+static struct mxs_ocotp_regs *ocotp_regs =
+ (struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
+static struct mxs_power_regs *power_regs =
+ (struct mxs_power_regs *)MXS_POWER_BASE;
+static struct mxs_clkctrl_regs *clkctrl_regs =
+ (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+
+static int mxs_ocotp_wait_busy_clear(void)
+{
+ uint32_t reg;
+ int timeout = MXS_OCOTP_TIMEOUT;
+
+ while (--timeout) {
+ reg = readl(&ocotp_regs->hw_ocotp_ctrl);
+ if (!(reg & OCOTP_CTRL_BUSY))
+ break;
+ udelay(10);
+ }
+
+ if (!timeout)
+ return -EINVAL;
+
+ /* Wait a little as per FSL datasheet's 'write postamble' section. */
+ udelay(10);
+
+ return 0;
+}
+
+static void mxs_ocotp_clear_error(void)
+{
+ writel(OCOTP_CTRL_ERROR, &ocotp_regs->hw_ocotp_ctrl_clr);
+}
+
+static int mxs_ocotp_read_bank_open(bool open)
+{
+ int ret = 0;
+
+ if (open) {
+ writel(OCOTP_CTRL_RD_BANK_OPEN,
+ &ocotp_regs->hw_ocotp_ctrl_set);
+
+ /*
+ * Wait before polling the BUSY bit, since the BUSY bit might
+ * be asserted only after a few HCLK cycles and if we were to
+ * poll immediatelly, we could miss the busy bit.
+ */
+ udelay(10);
+ ret = mxs_ocotp_wait_busy_clear();
+ } else {
+ writel(OCOTP_CTRL_RD_BANK_OPEN,
+ &ocotp_regs->hw_ocotp_ctrl_clr);
+ }
+
+ return ret;
+}
+
+static void mxs_ocotp_scale_vddio(bool enter, uint32_t *val)
+{
+ uint32_t scale_val;
+
+ if (enter) {
+ /*
+ * Enter the fuse programming VDDIO voltage setup. We start
+ * scaling the voltage from it's current value down to 2.8V
+ * which is the one and only correct voltage for programming
+ * the OCOTP fuses (according to datasheet).
+ */
+ scale_val = readl(&power_regs->hw_power_vddioctrl);
+ scale_val &= POWER_VDDIOCTRL_TRG_MASK;
+
+ /* Return the original voltage. */
+ *val = scale_val;
+
+ /*
+ * Start scaling VDDIO down to 0x2, which is 2.8V . Actually,
+ * the value 0x0 should be 2.8V, but that's not the case on
+ * most designs due to load etc., so we play safe. Undervolt
+ * can actually cause incorrect programming of the fuses and
+ * or reboots of the board.
+ */
+ while (scale_val > 2) {
+ clrsetbits_le32(&power_regs->hw_power_vddioctrl,
+ POWER_VDDIOCTRL_TRG_MASK, --scale_val);
+ udelay(500);
+ }
+ } else {
+ /* Start scaling VDDIO up to original value . */
+ for (scale_val = 2; scale_val <= *val; scale_val++) {
+ clrsetbits_le32(&power_regs->hw_power_vddioctrl,
+ POWER_VDDIOCTRL_TRG_MASK, scale_val);
+ udelay(500);
+ }
+ }
+
+ mdelay(10);
+}
+
+static int mxs_ocotp_wait_hclk_ready(void)
+{
+ uint32_t reg, timeout = MXS_OCOTP_TIMEOUT;
+
+ while (--timeout) {
+ reg = readl(&clkctrl_regs->hw_clkctrl_hbus);
+ if (!(reg & CLKCTRL_HBUS_ASM_BUSY))
+ break;
+ }
+
+ if (!timeout)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int mxs_ocotp_scale_hclk(bool enter, uint32_t *val)
+{
+ uint32_t scale_val;
+ int ret;
+
+ ret = mxs_ocotp_wait_hclk_ready();
+ if (ret)
+ return ret;
+
+ /* Set CPU bypass */
+ writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
+ &clkctrl_regs->hw_clkctrl_clkseq_set);
+
+ if (enter) {
+ /* Return the original HCLK clock speed. */
+ *val = readl(&clkctrl_regs->hw_clkctrl_hbus);
+ *val &= CLKCTRL_HBUS_DIV_MASK;
+
+ /* Scale the HCLK to 454/19 = 23.9 MHz . */
+ scale_val = (~19) << CLKCTRL_HBUS_DIV_OFFSET;
+ scale_val &= CLKCTRL_HBUS_DIV_MASK;
+ } else {
+ /* Scale the HCLK back to original frequency. */
+ scale_val = (~(*val)) << CLKCTRL_HBUS_DIV_OFFSET;
+ scale_val &= CLKCTRL_HBUS_DIV_MASK;
+ }
+
+ writel(CLKCTRL_HBUS_DIV_MASK,
+ &clkctrl_regs->hw_clkctrl_hbus_set);
+ writel(scale_val,
+ &clkctrl_regs->hw_clkctrl_hbus_clr);
+
+ mdelay(10);
+
+ ret = mxs_ocotp_wait_hclk_ready();
+ if (ret)
+ return ret;
+
+ /* Disable CPU bypass */
+ writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
+ &clkctrl_regs->hw_clkctrl_clkseq_clr);
+
+ mdelay(10);
+
+ return 0;
+}
+
+static int mxs_ocotp_write_fuse(uint32_t addr, uint32_t mask)
+{
+ uint32_t hclk_val, vddio_val;
+ int ret;
+
+ /* Make sure the banks are closed for reading. */
+ ret = mxs_ocotp_read_bank_open(0);
+ if (ret) {
+ puts("Failed closing banks for reading!\n");
+ return ret;
+ }
+
+ ret = mxs_ocotp_scale_hclk(1, &hclk_val);
+ if (ret) {
+ puts("Failed scaling down the HCLK!\n");
+ return ret;
+ }
+ mxs_ocotp_scale_vddio(1, &vddio_val);
+
+ ret = mxs_ocotp_wait_busy_clear();
+ if (ret) {
+ puts("Failed waiting for ready state!\n");
+ goto fail;
+ }
+
+ /* Program the fuse address */
+ writel(addr | OCOTP_CTRL_WR_UNLOCK_KEY, &ocotp_regs->hw_ocotp_ctrl);
+
+ /* Program the data. */
+ writel(mask, &ocotp_regs->hw_ocotp_data);
+
+ udelay(10);
+
+ ret = mxs_ocotp_wait_busy_clear();
+ if (ret) {
+ puts("Failed waiting for ready state!\n");
+ goto fail;
+ }
+
+fail:
+ mxs_ocotp_scale_vddio(0, &vddio_val);
+ ret = mxs_ocotp_scale_hclk(0, &hclk_val);
+ if (ret) {
+ puts("Failed scaling up the HCLK!\n");
+ return ret;
+ }
+
+ return ret;
+}
+
+static int mxs_ocotp_read_fuse(uint32_t reg, uint32_t *val)
+{
+ int ret;
+
+ /* Register offset from CUST0 */
+ reg = ((uint32_t)&ocotp_regs->hw_ocotp_cust0) + (reg << 4);
+
+ ret = mxs_ocotp_wait_busy_clear();
+ if (ret) {
+ puts("Failed waiting for ready state!\n");
+ return ret;
+ }
+
+ mxs_ocotp_clear_error();
+
+ ret = mxs_ocotp_read_bank_open(1);
+ if (ret) {
+ puts("Failed opening banks for reading!\n");
+ return ret;
+ }
+
+ *val = readl(reg);
+
+ ret = mxs_ocotp_read_bank_open(0);
+ if (ret) {
+ puts("Failed closing banks for reading!\n");
+ return ret;
+ }
+
+ return ret;
+}
+
+static int mxs_ocotp_valid(u32 bank, u32 word)
+{
+ if (bank > 4)
+ return -EINVAL;
+ if (word > 7)
+ return -EINVAL;
+ return 0;
+}
+
+/*
+ * The 'fuse' command API
+ */
+int fuse_read(u32 bank, u32 word, u32 *val)
+{
+ int ret;
+
+ ret = mxs_ocotp_valid(bank, word);
+ if (ret)
+ return ret;
+
+ return mxs_ocotp_read_fuse((bank << 3) | word, val);
+}
+
+int fuse_prog(u32 bank, u32 word, u32 val)
+{
+ int ret;
+
+ ret = mxs_ocotp_valid(bank, word);
+ if (ret)
+ return ret;
+
+ return mxs_ocotp_write_fuse((bank << 3) | word, val);
+}
+
+int fuse_sense(u32 bank, u32 word, u32 *val)
+{
+ /* We do not support sensing :-( */
+ return -EINVAL;
+}
+
+int fuse_override(u32 bank, u32 word, u32 val)
+{
+ /* We do not support overriding :-( */
+ return -EINVAL;
+}
#include <common.h>
#include <malloc.h>
#include <sdhci.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+#include <asm/gpio.h>
#include <asm/arch/mmc.h>
#include <asm/arch/clk.h>
+#include <errno.h>
+#ifdef CONFIG_OF_CONTROL
+#include <asm/arch/pinmux.h>
+#endif
static char *S5P_NAME = "SAMSUNG SDHCI";
static void s5p_sdhci_set_control_reg(struct sdhci_host *host)
return add_sdhci(host, 52000000, 400000);
}
+
+#ifdef CONFIG_OF_CONTROL
+struct sdhci_host sdhci_host[SDHCI_MAX_HOSTS];
+
+static int do_sdhci_init(struct sdhci_host *host)
+{
+ int dev_id, flag;
+ int err = 0;
+
+ flag = host->bus_width == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
+ dev_id = host->index + PERIPH_ID_SDMMC0;
+
+ if (fdt_gpio_isvalid(&host->pwr_gpio)) {
+ gpio_direction_output(host->pwr_gpio.gpio, 1);
+ err = exynos_pinmux_config(dev_id, flag);
+ if (err) {
+ debug("MMC not configured\n");
+ return err;
+ }
+ }
+
+ if (fdt_gpio_isvalid(&host->cd_gpio)) {
+ gpio_direction_output(host->cd_gpio.gpio, 0xf);
+ if (gpio_get_value(host->cd_gpio.gpio))
+ return -ENODEV;
+
+ err = exynos_pinmux_config(dev_id, flag);
+ if (err) {
+ printf("external SD not configured\n");
+ return err;
+ }
+ }
+
+ host->name = S5P_NAME;
+
+ host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE |
+ SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR |
+ SDHCI_QUIRK_WAIT_SEND_CMD;
+ host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
+ host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
+
+ host->set_control_reg = &s5p_sdhci_set_control_reg;
+ host->set_clock = set_mmc_clk;
+
+ host->host_caps = MMC_MODE_HC;
+
+ return add_sdhci(host, 52000000, 400000);
+}
+
+static int sdhci_get_config(const void *blob, int node, struct sdhci_host *host)
+{
+ int bus_width, dev_id;
+ unsigned int base;
+
+ /* Get device id */
+ dev_id = pinmux_decode_periph_id(blob, node);
+ if (dev_id < PERIPH_ID_SDMMC0 && dev_id > PERIPH_ID_SDMMC3) {
+ debug("MMC: Can't get device id\n");
+ return -1;
+ }
+ host->index = dev_id - PERIPH_ID_SDMMC0;
+
+ /* Get bus width */
+ bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
+ if (bus_width <= 0) {
+ debug("MMC: Can't get bus-width\n");
+ return -1;
+ }
+ host->bus_width = bus_width;
+
+ /* Get the base address from the device node */
+ base = fdtdec_get_addr(blob, node, "reg");
+ if (!base) {
+ debug("MMC: Can't get base address\n");
+ return -1;
+ }
+ host->ioaddr = (void *)base;
+
+ fdtdec_decode_gpio(blob, node, "pwr-gpios", &host->pwr_gpio);
+ fdtdec_decode_gpio(blob, node, "cd-gpios", &host->cd_gpio);
+
+ return 0;
+}
+
+static int process_nodes(const void *blob, int node_list[], int count)
+{
+ struct sdhci_host *host;
+ int i, node;
+
+ debug("%s: count = %d\n", __func__, count);
+
+ /* build sdhci_host[] for each controller */
+ for (i = 0; i < count; i++) {
+ node = node_list[i];
+ if (node <= 0)
+ continue;
+
+ host = &sdhci_host[i];
+
+ if (sdhci_get_config(blob, node, host)) {
+ printf("%s: failed to decode dev %d\n", __func__, i);
+ return -1;
+ }
+ do_sdhci_init(host);
+ }
+ return 0;
+}
+
+int exynos_mmc_init(const void *blob)
+{
+ int count;
+ int node_list[SDHCI_MAX_HOSTS];
+
+ count = fdtdec_find_aliases_for_id(blob, "mmc",
+ COMPAT_SAMSUNG_EXYNOS_MMC, node_list,
+ SDHCI_MAX_HOSTS);
+
+ process_nodes(blob, node_list, count);
+
+ return 1;
+}
+#endif
{
struct cpsw_priv *priv = (struct cpsw_priv *)dev->priv;
struct phy_device *phydev;
- u32 supported = (SUPPORTED_10baseT_Half |
- SUPPORTED_10baseT_Full |
- SUPPORTED_100baseT_Half |
- SUPPORTED_100baseT_Full |
- SUPPORTED_1000baseT_Full);
+ u32 supported = PHY_GBIT_FEATURES;
phydev = phy_connect(priv->bus,
slave->data->phy_addr,
return 0;
}
+__weak int imx6_pcie_toggle_power(void)
+{
+#ifdef CONFIG_PCIE_IMX_POWER_GPIO
+ gpio_direction_output(CONFIG_PCIE_IMX_POWER_GPIO, 0);
+ mdelay(20);
+ gpio_set_value(CONFIG_PCIE_IMX_POWER_GPIO, 1);
+ mdelay(20);
+#endif
+ return 0;
+}
+
__weak int imx6_pcie_toggle_reset(void)
{
/*
{
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
- /* FIXME: Power-up GPIO goes here. */
+ imx6_pcie_toggle_power();
/* Enable PCIe */
clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o
+obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o
obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o
--- /dev/null
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Tim Harvey <tharvey@gateworks.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+
+int pmic_init(unsigned char bus)
+{
+ static const char name[] = "PFUZE100_PMIC";
+ struct pmic *p = pmic_alloc();
+
+ if (!p) {
+ printf("%s: POWER allocation error!\n", __func__);
+ return -ENOMEM;
+ }
+
+ p->name = name;
+ p->interface = PMIC_I2C;
+ p->number_of_regs = PMIC_NUM_OF_REGS;
+ p->hw.i2c.addr = CONFIG_POWER_PFUZE100_I2C_ADDR;
+ p->hw.i2c.tx_num = 1;
+ p->bus = bus;
+
+ return 0;
+}
}
/* wait to finish of transfer */
- while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) &
- OMAP3_MCSPI_CHSTAT_EOT));
+ while ((readl(&ds->regs->channel[ds->slave.cs].chstat) &
+ (OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS)) !=
+ (OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS));
/* Disable the channel otherwise the next immediate RX will get affected */
omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS);
void exynos_backlight_reset(void)
__attribute__((weak, alias("__exynos_backlight_reset")));
+int __exynos_lcd_misc_init(vidinfo_t *vid)
+{
+ return 0;
+}
+int exynos_lcd_misc_init(vidinfo_t *vid)
+ __attribute__((weak, alias("__exynos_lcd_misc_init")));
+
static void lcd_panel_on(vidinfo_t *vid)
{
udelay(vid->init_delay);
#ifdef CONFIG_OF_CONTROL
if (exynos_fimd_parse_dt(gd->fdt_blob))
debug("Can't get proper panel info\n");
+#ifdef CONFIG_EXYNOS_MIPI_DSIM
+ exynos_init_dsim_platform_data(&panel_info);
+#endif
+ exynos_lcd_misc_init(&panel_info);
#else
/* initialize parameters which is specific to panel. */
init_panel_info(&panel_info);
#endif
+
panel_width = panel_info.vl_width;
panel_height = panel_info.vl_height;
#include <common.h>
#include <malloc.h>
+#include <fdtdec.h>
+#include <libfdt.h>
#include <linux/err.h>
#include <asm/arch/dsim.h>
#include <asm/arch/mipi_dsim.h>
#define master_to_driver(a) (a->dsim_lcd_drv)
#define master_to_device(a) (a->dsim_lcd_dev)
+DECLARE_GLOBAL_DATA_PTR;
+
static struct exynos_platform_mipi_dsim *dsim_pd;
+#ifdef CONFIG_OF_CONTROL
+static struct mipi_dsim_config dsim_config_dt;
+static struct exynos_platform_mipi_dsim dsim_platform_data_dt;
+static struct mipi_dsim_lcd_device mipi_lcd_device_dt;
+#endif
struct mipi_dsim_ddi {
int bus_id;
dsim_pd = pd;
}
+
+#ifdef CONFIG_OF_CONTROL
+int exynos_dsim_config_parse_dt(const void *blob)
+{
+ int node;
+
+ node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_MIPI_DSI);
+ if (node <= 0) {
+ printf("exynos_mipi_dsi: Can't get device node for mipi dsi\n");
+ return -ENODEV;
+ }
+
+ dsim_config_dt.e_interface = fdtdec_get_int(blob, node,
+ "samsung,dsim-config-e-interface", 0);
+
+ dsim_config_dt.e_virtual_ch = fdtdec_get_int(blob, node,
+ "samsung,dsim-config-e-virtual-ch", 0);
+
+ dsim_config_dt.e_pixel_format = fdtdec_get_int(blob, node,
+ "samsung,dsim-config-e-pixel-format", 0);
+
+ dsim_config_dt.e_burst_mode = fdtdec_get_int(blob, node,
+ "samsung,dsim-config-e-burst-mode", 0);
+
+ dsim_config_dt.e_no_data_lane = fdtdec_get_int(blob, node,
+ "samsung,dsim-config-e-no-data-lane", 0);
+
+ dsim_config_dt.e_byte_clk = fdtdec_get_int(blob, node,
+ "samsung,dsim-config-e-byte-clk", 0);
+
+ dsim_config_dt.hfp = fdtdec_get_int(blob, node,
+ "samsung,dsim-config-hfp", 0);
+
+ dsim_config_dt.p = fdtdec_get_int(blob, node,
+ "samsung,dsim-config-p", 0);
+ dsim_config_dt.m = fdtdec_get_int(blob, node,
+ "samsung,dsim-config-m", 0);
+ dsim_config_dt.s = fdtdec_get_int(blob, node,
+ "samsung,dsim-config-s", 0);
+
+ dsim_config_dt.pll_stable_time = fdtdec_get_int(blob, node,
+ "samsung,dsim-config-pll-stable-time", 0);
+
+ dsim_config_dt.esc_clk = fdtdec_get_int(blob, node,
+ "samsung,dsim-config-esc-clk", 0);
+
+ dsim_config_dt.stop_holding_cnt = fdtdec_get_int(blob, node,
+ "samsung,dsim-config-stop-holding-cnt", 0);
+
+ dsim_config_dt.bta_timeout = fdtdec_get_int(blob, node,
+ "samsung,dsim-config-bta-timeout", 0);
+
+ dsim_config_dt.rx_timeout = fdtdec_get_int(blob, node,
+ "samsung,dsim-config-rx-timeout", 0);
+
+ mipi_lcd_device_dt.name = fdtdec_get_config_string(blob,
+ "samsung,dsim-device-name");
+
+ mipi_lcd_device_dt.id = fdtdec_get_int(blob, node,
+ "samsung,dsim-device-id", 0);
+
+ mipi_lcd_device_dt.bus_id = fdtdec_get_int(blob, node,
+ "samsung,dsim-device-bus_id", 0);
+
+ mipi_lcd_device_dt.reverse_panel = fdtdec_get_int(blob, node,
+ "samsung,dsim-device-reverse-panel", 0);
+
+ return 0;
+}
+
+void exynos_init_dsim_platform_data(vidinfo_t *vid)
+{
+ if (exynos_dsim_config_parse_dt(gd->fdt_blob))
+ debug("Can't get proper dsim config.\n");
+
+ strcpy(dsim_platform_data_dt.lcd_panel_name, mipi_lcd_device_dt.name);
+ dsim_platform_data_dt.dsim_config = &dsim_config_dt;
+ dsim_platform_data_dt.mipi_power = mipi_power;
+ dsim_platform_data_dt.phy_enable = set_mipi_phy_ctrl;
+ dsim_platform_data_dt.lcd_panel_info = (void *)vid;
+
+ mipi_lcd_device_dt.platform_data = (void *)&dsim_platform_data_dt;
+ exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device_dt);
+
+ dsim_pd = &dsim_platform_data_dt;
+}
+#endif
#define CONFIG_SYS_FLASH_BASE (0x08000000)
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+/* Reduce SPL size by removing unlikey targets */
+#undef CONFIG_SPL_SPI_SUPPORT
#ifdef CONFIG_NOR_BOOT
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
/* Timer information */
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
-
+#define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC /* enable 32kHz OSC at bootime */
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_POWER_TPS65217
/* CS0 */
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
+#define GPMC_NAND_ECC_LP_x8_LAYOUT
+
/* Environment information */
#define CONFIG_BOOTDELAY 3
#define CONFIG_ZERO_BOOTDELAY_CHECK
--- /dev/null
+/*
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG EXYNOS5 board.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_SAMSUNG /* in a SAMSUNG core */
+#define CONFIG_S5P /* S5P Family */
+#define CONFIG_EXYNOS4 /* which is in a Exynos4 Family */
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_COMMON
+
+/* Enable fdt support */
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
+/* input clock of PLL: EXYNOS4 boards have 24MHz input clock */
+#define CONFIG_SYS_CLK_FREQ 24000000
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_EDITING
+
+#include <linux/sizes.h>
+
+/* SD/MMC configuration */
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_S5P_SDHCI
+#define CONFIG_SDHCI
+#define CONFIG_MMC_SDMA
+#define CONFIG_MMC_DEFAULT_DEV 0
+
+/* PWM */
+#define CONFIG_PWM
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Command definition*/
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_MISC
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_XIMG
+#undef CONFIG_CMD_CACHE
+#undef CONFIG_CMD_ONENAND
+#undef CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_DFU
+#define CONFIG_CMD_GPT
+#define CONFIG_CMD_PMIC
+#define CONFIG_CMD_SETEXPR
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+/* FAT */
+#define CONFIG_CMD_FAT
+#define CONFIG_FAT_WRITE
+
+/* EXT4 */
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+
+/* USB Composite download gadget - g_dnl */
+#define CONFIG_USBDOWNLOAD_GADGET
+
+/* TIZEN THOR downloader support */
+#define CONFIG_CMD_THOR_DOWNLOAD
+#define CONFIG_THOR_FUNCTION
+
+#define CONFIG_DFU_FUNCTION
+#define CONFIG_DFU_MMC
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M
+#define DFU_DEFAULT_POLL_TIMEOUT 300
+
+/* USB Samsung's IDs */
+#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
+#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
+#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
+#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D
+#define CONFIG_G_DNL_MANUFACTURER "Samsung"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_CMD_PART
+#define CONFIG_PARTITION_UUIDS
+
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_S3C_UDC_OTG
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+#define CONFIG_USB_CABLE_CHECK
+
+#define CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_USB_GADGET_MASS_STORAGE
+
+/* Enable devicetree support */
+#define CONFIG_OF_LIBFDT
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Copyright (C) 2013 Gateworks Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+#define CONFIG_MX6
+#define CONFIG_DISPLAY_CPUINFO /* display cpu info */
+#define CONFIG_DISPLAY_BOARDINFO_LATE /* display board info (after reloc) */
+
+#define CONFIG_MACH_TYPE 4520 /* Gateworks Ventana Platform */
+
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+
+/* ATAGs */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SERIAL_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
+
+/* Init Functions */
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MISC_INIT_R
+
+/* GPIO */
+#define CONFIG_MXC_GPIO
+
+/* Serial */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART2_BASE
+
+#ifdef CONFIG_SPI_FLASH
+
+/* SPI */
+#define CONFIG_CMD_SF
+#ifdef CONFIG_CMD_SF
+ #define CONFIG_MXC_SPI
+ #define CONFIG_SPI_FLASH_MTD
+ #define CONFIG_SPI_FLASH_BAR
+ #define CONFIG_SPI_FLASH_WINBOND
+ #define CONFIG_SF_DEFAULT_BUS 0
+ #define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(3, 19)<<8))
+ /* GPIO 3-19 (21248) */
+ #define CONFIG_SF_DEFAULT_SPEED 30000000
+ #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
+#endif
+
+#else
+/* Enable NAND support */
+#define CONFIG_CMD_TIME
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_TRIMFFS
+#ifdef CONFIG_CMD_NAND
+ #define CONFIG_NAND_MXS
+ #define CONFIG_SYS_MAX_NAND_DEVICE 1
+ #define CONFIG_SYS_NAND_BASE 0x40000000
+ #define CONFIG_SYS_NAND_5_ADDR_CYCLE
+ #define CONFIG_SYS_NAND_ONFI_DETECTION
+
+ /* DMA stuff, needed for GPMI/MXS NAND support */
+ #define CONFIG_APBH_DMA
+ #define CONFIG_APBH_DMA_BURST
+ #define CONFIG_APBH_DMA_BURST8
+#endif
+
+#endif /* CONFIG_SPI_FLASH */
+
+/* Flattened Image Tree Suport */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE
+
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_FSL_USDHC_NUM 1
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+
+/* Filesystem support */
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_UBIFS
+#define CONFIG_DOS_PARTITION
+
+/* Network config - Allow larger/faster download for TFTP/NFS */
+#define CONFIG_IP_DEFRAG
+#define CONFIG_TFTP_BLOCKSIZE 4096
+#define CONFIG_NFS_READ_SIZE 4096
+
+/*
+ * SATA Configs
+ */
+#define CONFIG_CMD_SATA
+#ifdef CONFIG_CMD_SATA
+ #define CONFIG_DWC_AHSATA
+ #define CONFIG_SYS_SATA_MAX_DEVICE 1
+ #define CONFIG_DWC_AHSATA_PORT_ID 0
+ #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
+ #define CONFIG_LBA48
+ #define CONFIG_LIBATA
+#endif
+
+/*
+ * PCI express
+ */
+#define CONFIG_CMD_PCI
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIE_IMX
+#endif
+
+/*
+ * PMIC
+ */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
+
+/* Various command support */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_BMODE /* set eFUSE shadow for a boot dev and reset */
+#define CONFIG_CMD_HDMIDETECT /* detect HDMI output device */
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_GSC
+#define CONFIG_CMD_UBI
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_CMD_FUSE /* eFUSE read/write support */
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+#endif
+
+
+/* Ethernet support */
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_ETHPRIME "FEC"
+#define CONFIG_FEC_MXC_PHYADDR 0
+#define CONFIG_PHYLIB
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/* USB Configs */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_USB_KEYBOARD
+#define CONFIG_CI_UDC
+#define CONFIG_USBD_HS
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_CDC
+#define CONFIG_NETCONSOLE
+#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
+#define CONFIG_USB_HUB_MIN_POWER_ON_DELAY 1200
+
+/* serial console (ttymxc1,115200) */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT "Ventana > "
+#define CONFIG_SYS_CBSIZE 1024
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_HWCONFIG
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/* Memory configuration */
+#define CONFIG_SYS_MEMTEST_START 0x10000000
+#define CONFIG_SYS_MEMTEST_END 0x10010000
+#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
+#define CONFIG_SYS_TEXT_BASE 0x17800000
+#define CONFIG_SYS_LOAD_ADDR 0x12000000
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH /* no NOR flash */
+
+/*
+ * MTD Command for mtdparts
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#ifdef CONFIG_SPI_FLASH
+#define MTDIDS_DEFAULT "nor0=nor"
+#define MTDPARTS_DEFAULT \
+ "mtdparts=nor:512k(uboot),64k(env),2m(kernel),-(rootfs)"
+#else
+#define MTDIDS_DEFAULT "nand0=nand"
+#define MTDPARTS_DEFAULT "mtdparts=nand:16m(uboot),1m(env),-(rootfs)"
+#endif
+
+/* Persistent Environment Config */
+#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
+#ifdef CONFIG_SPI_FLASH
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#else
+#define CONFIG_ENV_IS_IN_NAND
+#endif
+#if defined(CONFIG_ENV_IS_IN_MMC)
+ #define CONFIG_ENV_OFFSET (6 * 64 * 1024)
+ #define CONFIG_ENV_SIZE (8 * 1024)
+ #define CONFIG_SYS_MMC_ENV_DEV 0
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+ #define CONFIG_ENV_OFFSET (16 << 20)
+ #define CONFIG_ENV_SECT_SIZE (128 << 10)
+ #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+ #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + (512 << 10))
+ #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+ #define CONFIG_ENV_OFFSET (512 * 1024)
+ #define CONFIG_ENV_SECT_SIZE (64 * 1024)
+ #define CONFIG_ENV_SIZE (8 * 1024)
+ #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
+ #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
+ #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
+ #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+#endif
+
+/* Environment */
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
+#define CONFIG_IPADDR 192.168.1.1
+#define CONFIG_SERVERIP 192.168.1.146
+#define HWCONFIG_DEFAULT \
+ "hwconfig=rs232;" \
+ "dio0:mode=gpio;dio1:mode=gpio;dio2:mode=gpio;dio3:mode=gpio\0" \
+
+#define CONFIG_EXTRA_ENV_SETTINGS_COMMON \
+ "console=ttymxc1\0" \
+ "bootdevs=usb mmc sata flash\0" \
+ HWCONFIG_DEFAULT \
+ "video=\0" \
+ \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ \
+ "fdt_high=0xffffffff\0" \
+ "fdt_addr=0x18000000\0" \
+ "loadfdt=" \
+ "if ${fsload} ${fdt_addr} boot/${fdt_file}; then " \
+ "echo Loaded DTB from boot/${fdt_file}; " \
+ "elif ${fsload} ${fdt_addr} boot/${fdt_file1}; then " \
+ "echo Loaded DTB from boot/${fdt_file1}; " \
+ "elif ${fsload} ${fdt_addr} boot/${fdt_file2}; then " \
+ "echo Loaded DTB from boot/${fdt_file2}; " \
+ "fi\0" \
+ \
+ "script=boot/6x_bootscript-ventana\0" \
+ "loadscript=" \
+ "if ${fsload} ${loadaddr} ${script}; then " \
+ "source; " \
+ "fi\0" \
+ \
+ "uimage=boot/uImage\0" \
+ "mmc_root=/dev/mmcblk0p1 rootfstype=ext4 rootwait rw\0" \
+ "mmc_boot=" \
+ "setenv fsload 'ext2load mmc 0:1'; " \
+ "mmc dev 0 && mmc rescan && " \
+ "run loadscript; " \
+ "if ${fsload} ${loadaddr} ${uimage}; then " \
+ "setenv bootargs console=${console},${baudrate} " \
+ "root=/dev/mmcblk0p1 rootfstype=ext4 " \
+ "rootwait rw ${video} ${extra}; " \
+ "if run loadfdt && fdt addr ${fdt_addr}; then " \
+ "bootm ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "bootm; " \
+ "fi; " \
+ "fi\0" \
+ \
+ "sata_boot=" \
+ "setenv fsload 'ext2load sata 0:1'; sata init && " \
+ "run loadscript; " \
+ "if ${fsload} ${loadaddr} ${uimage}; then " \
+ "setenv bootargs console=${console},${baudrate} " \
+ "root=/dev/sda1 rootfstype=ext4 " \
+ "rootwait rw ${video} ${extra}; " \
+ "if run loadfdt && fdt addr ${fdt_addr}; then " \
+ "bootm ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "bootm; " \
+ "fi; " \
+ "fi\0" \
+ "usb_boot=" \
+ "setenv fsload 'ext2load usb 0:1'; usb start && usb dev 0 && " \
+ "run loadscript; " \
+ "if ${fsload} ${loadaddr} ${uimage}; then " \
+ "setenv bootargs console=${console},${baudrate} " \
+ "root=/dev/sda1 rootfstype=ext4 " \
+ "rootwait rw ${video} ${extra}; " \
+ "if run loadfdt && fdt addr ${fdt_addr}; then " \
+ "bootm ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "bootm; " \
+ "fi; " \
+ "fi\0"
+
+#ifdef CONFIG_SPI_FLASH
+ #define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_EXTRA_ENV_SETTINGS_COMMON \
+ "image_os=ventana/openwrt-imx6-imx6q-gw5400-a-squashfs.bin\0" \
+ "image_uboot=ventana/u-boot_spi.imx\0" \
+ \
+ "spi_koffset=0x90000\0" \
+ "spi_klen=0x200000\0" \
+ \
+ "spi_updateuboot=echo Updating uboot from " \
+ "${serverip}:${image_uboot}...; " \
+ "tftpboot ${loadaddr} ${image_uboot} && " \
+ "sf probe && sf erase 0 80000 && " \
+ "sf write ${loadaddr} 400 ${filesize}\0" \
+ "spi_update=echo Updating OS from ${serverip}:${image_os} " \
+ "to ${spi_koffset} ...; " \
+ "tftp ${loadaddr} ${image_os} && " \
+ "sf probe && " \
+ "sf update ${loadaddr} ${spi_koffset} ${filesize}\0" \
+ \
+ "flash_boot=" \
+ "if sf probe && " \
+ "sf read ${loadaddr} ${spi_koffset} ${spi_klen}; then " \
+ "setenv bootargs console=${console},${baudrate} " \
+ "root=/dev/mtdblock3 " \
+ "rootfstype=squashfs,jffs2 " \
+ "${video} ${extra}; " \
+ "bootm; " \
+ "fi\0"
+#else
+ #define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_EXTRA_ENV_SETTINGS_COMMON \
+ "image_rootfs=openwrt-imx6-ventana-rootfs.ubi\0" \
+ \
+ "nand_update=echo Updating NAND from ${serverip}:${image_rootfs}...; " \
+ "tftp ${loadaddr} ${image_rootfs} && " \
+ "nand erase.part rootfs && " \
+ "nand write ${loadaddr} rootfs ${filesize}\0" \
+ \
+ "flash_boot=" \
+ "setenv fsload 'ubifsload'; " \
+ "ubi part rootfs && ubifsmount ubi0:rootfs; " \
+ "run loadscript; " \
+ "if ${fsload} ${loadaddr} ${uimage}; then " \
+ "setenv bootargs console=${console},${baudrate} " \
+ "root=ubi0:rootfs ubi.mtd=2 " \
+ "rootfstype=ubifs ${video} ${extra}; " \
+ "if run loadfdt && fdt addr ${fdt_addr}; then " \
+ "ubifsumount; " \
+ "bootm ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "ubifsumount; bootm; " \
+ "fi; " \
+ "fi\0"
+#endif
+
+#define CONFIG_BOOTCOMMAND \
+ "for btype in ${bootdevs}; do " \
+ "echo; echo Attempting ${btype} boot...; " \
+ "if run ${btype}_boot; then; fi; " \
+ "done"
+
+/* Device Tree Support */
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_LIBFDT
+#define CONFIG_FDT_FIXUP_PARTITIONS
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+ #define CONFIG_CMD_CACHE
+#endif
+
+#endif /* __CONFIG_H */
*/
#define CONFIG_NR_DRAM_BANKS 2
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
-#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
+#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
#define PHYS_SDRAM_2 CSD1_BASE_ADDR
-#define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024)
-#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
+#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
+#define PHYS_SDRAM_SIZE (gd->ram_size)
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
#define CONFIG_SYS_MEMTEST_START 0x70000000
-#define CONFIG_SYS_MEMTEST_END 0xaff00000
+#define CONFIG_SYS_MEMTEST_END 0x8ff00000
#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
/* No NOR flash present */
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
#define CONFIG_ENV_SIZE (8 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_IS_IN_MMC
/* U-Boot general configuration */
#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
/* Print buffer sz */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_LOADADDR 0x81000000 /* loadaddr env var */
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_DEFAULT_FDT_FILE "imx25-pdk.dtb"
+
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
- "uimage=uImage\0" \
- "netargs=setenv bootargs console=ttymxc0,${baudrate} " \
+ "image=zImage\0" \
+ "console=ttymxc0\0" \
+ "splashpos=m,m\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "fdt_addr=0x82000000\0" \
+ "boot_fdt=try\0" \
+ "ip_dyn=yes\0" \
+ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+ "mmcpart=1\0" \
+ "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+ "update_sd_firmware_filename=u-boot.imx\0" \
+ "update_sd_firmware=" \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "if mmc dev ${mmcdev}; then " \
+ "if ${get_cmd} ${update_sd_firmware_filename}; then " \
+ "setexpr fw_sz ${filesize} / 0x200; " \
+ "setexpr fw_sz ${fw_sz} + 1; " \
+ "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+ "fi; " \
+ "fi\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${mmcroot}\0" \
+ "loadbootscript=" \
+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0" \
+ "netargs=setenv bootargs console=${console},${baudrate} " \
"root=/dev/nfs " \
- "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
- "bootcmd=run netargs; dhcp ${uimage}; bootm\0" \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "run netargs; " \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${image}; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loadimage; then " \
+ "run mmcboot; " \
+ "else run netboot; " \
+ "fi; " \
+ "fi; " \
+ "else run netboot; fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_AUTO_COMPLETE
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#endif /* __CONFIG_H */
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 2
-#define PHYS_SDRAM_1 CSD0_BASE_ADDR
-#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
-#define PHYS_SDRAM_2 CSD1_BASE_ADDR
-#define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024)
-#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
+#define PHYS_SDRAM_1 CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
+#define PHYS_SDRAM_2 CSD1_BASE_ADDR
+#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
+#define PHYS_SDRAM_SIZE (gd->ram_size)
#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
#define CONFIG_ARM_ERRATA_742230
#define CONFIG_ARM_ERRATA_743622
#define CONFIG_ARM_ERRATA_751472
+#define CONFIG_ARM_ERRATA_794072
+#define CONFIG_ARM_ERRATA_761320
#define CONFIG_BOARD_POSTCLK_INIT
#ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_OF_SEPARATE
+#define CONFIG_DEFAULT_DEVICE_TREE imx6q-sabreauto
+
#endif /* __MX6QSABREAUTO_CONFIG_H */
#define CONFIG_IPUV3_CLK 260000000
#define CONFIG_IMX_HDMI
+#define CONFIG_CMD_PCI
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIE_IMX
+#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
+#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19)
+#endif
+
#endif /* __MX6QSABRESD_CONFIG_H */
* We need to sacrifice first 4 bytes of RAM here to avoid triggering some
* strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
* binary. In case there was more of this mess, 0x100 bytes are skipped.
+ *
+ * In case of a HAB boot, we cannot for some weird reason use the first 4KiB
+ * of DRAM when loading. Moreover, we use the first 4 KiB for IVT and CST
+ * blocks, thus U-Boot starts at offset +8 KiB of DRAM start.
+ *
+ * As for the SPL, we must avoid the first 4 KiB as well, but we load the
+ * IVT and CST to 0x8000, so we don't need to waste the subsequent 4 KiB.
*/
-#define CONFIG_SYS_TEXT_BASE 0x40000100
+#define CONFIG_SYS_TEXT_BASE 0x40002000
+#define CONFIG_SPL_TEXT_BASE 0x00001000
/* U-Boot general configuration */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#endif
+/* OCOTP */
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXS_OCOTP
+#endif
+
/* SPI */
#ifdef CONFIG_CMD_SPI
#define CONFIG_HARD_SPI
/*
* PCI express
*/
-#define CONFIG_CMD_PCI
#ifdef CONFIG_CMD_PCI
#define CONFIG_PCI
#define CONFIG_PCI_PNP
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_ORIGEN_H
+#define __CONFIG_ORIGEN_H
+
+#include <configs/exynos4-dt.h>
+
+#define CONFIG_SYS_PROMPT "ORIGEN # "
+
+#undef CONFIG_DEFAULT_DEVICE_TREE
+#define CONFIG_DEFAULT_DEVICE_TREE exynos4210-origen
/* High Level Configuration Options */
-#define CONFIG_SAMSUNG 1 /* SAMSUNG core */
-#define CONFIG_S5P 1 /* S5P Family */
#define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */
#define CONFIG_ORIGEN 1 /* working with ORIGEN*/
-#include <asm/arch/cpu.h> /* get chip and board defs */
-
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_BOARD_EARLY_INIT_F
-
#define CONFIG_SYS_DCACHE_OFF 1
+/* ORIGEN has 4 bank of DRAM */
+#define CONFIG_NR_DRAM_BANKS 4
#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define CONFIG_SYS_TEXT_BASE 0x43E00000
+#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
-/* input clock of PLL: ORIGEN has 24MHz input clock */
-#define CONFIG_SYS_CLK_FREQ 24000000
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_INITRD_TAG
-#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_TEXT_BASE 0x43E00000
#define CONFIG_MACH_TYPE MACH_TYPE_ORIGEN
-/* Power Down Modes */
-#define S5P_CHECK_SLEEP 0x00000BAD
-#define S5P_CHECK_DIDLE 0xBAD00000
-#define S5P_CHECK_LPA 0xABAD0000
-
/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M))
/* select serial console configuration */
-#define CONFIG_SERIAL2 1 /* use SERIAL 2 */
+#define CONFIG_SERIAL2
#define CONFIG_BAUDRATE 115200
-#define EXYNOS4_DEFAULT_UART_OFFSET 0x020000
-#define CONFIG_SKIP_LOWLEVEL_INIT
+/* Console configuration */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
-/* SD/MMC configuration */
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
-#define CONFIG_SDHCI
-#define CONFIG_S5P_SDHCI
+#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
-/* PWM */
-#define CONFIG_PWM 1
+#define CONFIG_SYS_MONITOR_BASE 0x00000000
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/* Command definition*/
-#include <config_cmd_default.h>
+/* Power Down Modes */
+#define S5P_CHECK_SLEEP 0x00000BAD
+#define S5P_CHECK_DIDLE 0xBAD00000
+#define S5P_CHECK_LPA 0xABAD0000
#undef CONFIG_CMD_PING
#define CONFIG_CMD_ELF
#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_FAT
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_ZERO_BOOTDELAY_CHECK
/* MMC SPL */
#define CONFIG_SPL
#define COPY_BL2_FNPTR_ADDR 0x02020030
-
#define CONFIG_SPL_TEXT_BASE 0x02021410
#define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000"
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT "ORIGEN # "
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size*/
-#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-/* memtest works on */
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
-
-/* ORIGEN has 4 bank of DRAM */
-#define CONFIG_NR_DRAM_BANKS 4
-#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
-#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
-#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
-
-/* FLASH and environment organization */
-#define CONFIG_SYS_NO_FLASH 1
-#undef CONFIG_CMD_IMLS
#define CONFIG_IDENT_STRING " for ORIGEN"
#define CONFIG_CLK_1000_400_200
/* MIU (Memory Interleaving Unit) */
#define CONFIG_MIU_2BIT_21_7_INTERLEAVED
-#define CONFIG_ENV_IS_IN_MMC 1
+#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
#define RESERVE_BLOCK_SIZE (512)
#define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
#define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE)
-#define CONFIG_DOS_PARTITION 1
#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"
#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)
#define BL2_START_OFFSET ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512)
#define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512)
-/* Enable devicetree support */
-#define CONFIG_OF_LIBFDT
-
#endif /* __CONFIG_H */
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_UNIVERSAL_H
+#define __CONFIG_UNIVERSAL_H
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */
-#define CONFIG_S5P 1 /* which is in a S5P Family */
-#define CONFIG_EXYNOS4210 1 /* which is in a EXYNOS4210 */
-#define CONFIG_UNIVERSAL 1 /* working with Universal */
-#define CONFIG_TIZEN 1 /* TIZEN lib */
+#include <configs/exynos4-dt.h>
+
+#define CONFIG_SYS_PROMPT "Universal # " /* Monitor Command Prompt */
-#include <asm/arch/cpu.h> /* get chip and board defs */
+#undef CONFIG_DEFAULT_DEVICE_TREE
+#define CONFIG_DEFAULT_DEVICE_TREE exynos4210-universal_c210
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_TIZEN /* TIZEN lib */
/* Keep L2 Cache Disabled */
#define CONFIG_SYS_L2CACHE_OFF 1
+/* Universal has 2 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS 2
#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define CONFIG_SYS_TEXT_BASE 0x44800000
-
-/* input clock of PLL: Universal has 24MHz input clock at EXYNOS4210 */
-#define CONFIG_SYS_CLK_FREQ_C210 24000000
-#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_CLK_FREQ_C210
+#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_BOARD_EARLY_INIT_F
+#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M))
/* select serial console configuration */
-#define CONFIG_SERIAL2 1 /* use SERIAL 2 */
-#define CONFIG_BAUDRATE 115200
-
-/* MMC */
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
-#define CONFIG_SDHCI
-#define CONFIG_S5P_SDHCI
-
-/* PWM */
-#define CONFIG_PWM 1
-
-/* It should define before config_cmd_default.h */
-#define CONFIG_SYS_NO_FLASH 1
-
-/* Command definition */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_MISC
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_XIMG
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_ONENAND
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_FAT
-
-#define CONFIG_BOOTDELAY 1
-#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_SERIAL2
+#define CONFIG_BAUDRATE 115200
+
+/* Console configuration */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+#define CONFIG_BOOTARGS "Please use defined boot"
+#define CONFIG_BOOTCOMMAND "run mmcboot"
+#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
+
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
+ - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
+
+#define CONFIG_SYS_MONITOR_BASE 0x00000000
+
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
+
+#define CONFIG_SYS_TEXT_BASE 0x44800000
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
",100M(swap)"\
",-(UMS)\0"
-#define CONFIG_BOOTARGS "Please use defined boot"
-#define CONFIG_BOOTCOMMAND "run mmcboot"
-#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
-
#define CONFIG_ENV_UBI_MTD " ubi.mtd=${ubiblock} ubi.mtd=4 ubi.mtd=7"
#define CONFIG_BOOTBLOCK "10"
#define CONFIG_UBIBLOCK "9"
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV
+#define CONFIG_ENV_SIZE 4096
+#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */
+
#define CONFIG_ENV_UBIFS_OPTION " rootflags=bulk_read,no_chk_data_crc "
#define CONFIG_ENV_FLASHBOOT CONFIG_ENV_UBI_MTD CONFIG_ENV_UBIFS_OPTION \
"${mtdparts}"
#define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}"
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-
#define CONFIG_ENV_VARS_UBOOT_CONFIG
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
"mmcrootpart=3\0" \
"opts=always_resume=1"
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT "Universal # "
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-/* memtest works on */
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
-
-/* Universal has 2 banks of DRAM */
-#define CONFIG_NR_DRAM_BANKS 2
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* LDDDR2 DMC 0 */
-#define PHYS_SDRAM_1_SIZE (256 << 20) /* 256 MB in CS 0 */
-#define PHYS_SDRAM_2 0x50000000 /* LPDDR2 DMC 1 */
-#define PHYS_SDRAM_2_SIZE (256 << 20) /* 256 MB in CS 0 */
-
-#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
-
-#define CONFIG_SYS_MONITOR_BASE 0x00000000
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-
#define CONFIG_USE_ONENAND_BOARD_INIT
#define CONFIG_SAMSUNG_ONENAND
#define CONFIG_SYS_ONENAND_BASE 0x0C000000
-#define CONFIG_ENV_IS_IN_MMC 1
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_ENV_SIZE 4096
-#define CONFIG_ENV_OFFSET ((32 - 4) << 10)/* 32KiB - 4KiB */
-
-#define CONFIG_DOS_PARTITION 1
-
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
#include <asm/arch/gpio.h>
/*
* I2C Settings
#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_get(1, b, 7)
#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_get(1, b, 6)
+#define CONFIG_CMD_I2C
+
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
#define CONFIG_SYS_I2C_SOFT_SPEED 50000
#define CONFIG_CMD_BMP
#define CONFIG_BMP_16BPP
#define CONFIG_LD9040
-#define CONFIG_EXYNOS_MIPI_DSIM
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
+#define LCD_XRES 480
+#define LCD_YRES 800
+
#endif /* __CONFIG_H */
#include <asm/arch/socfpga_base_addrs.h>
#include "../../board/altera/socfpga/pinmux_config.h"
+#include "../../board/altera/socfpga/pll_config.h"
/*
* High level configuration
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_TRATS_H
+#define __CONFIG_TRATS_H
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_SAMSUNG /* in a SAMSUNG core */
-#define CONFIG_S5P /* which is in a S5P Family */
-#define CONFIG_EXYNOS4 /* which is in a EXYNOS4XXX */
-#define CONFIG_EXYNOS4210 /* which is in a EXYNOS4210 */
-#define CONFIG_TRATS /* working with TRATS */
-#define CONFIG_TIZEN /* TIZEN lib */
+#include <configs/exynos4-dt.h>
+
+#define CONFIG_SYS_PROMPT "Trats # " /* Monitor Command Prompt */
+
+#define CONFIG_TRATS
-#include <asm/arch/cpu.h> /* get chip and board defs */
+#undef CONFIG_DEFAULT_DEVICE_TREE
+#define CONFIG_DEFAULT_DEVICE_TREE exynos4210-trats
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_TIZEN /* TIZEN lib */
#define CONFIG_SYS_L2CACHE_OFF
#ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_PL310_BASE 0x10502000
#endif
+/* TRATS has 4 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS 4
#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_TEXT_BASE 0x63300000
+#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
-/* input clock of PLL: TRATS has 24MHz input clock at EXYNOS4210 */
-#define CONFIG_SYS_CLK_FREQ_C210 24000000
-#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_CLK_FREQ_C210
-
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_REVISION_TAG
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_BOARD_EARLY_INIT_F
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
-/* MACH_TYPE_TRATS macro will be removed once added to mach-types */
-#define MACH_TYPE_TRATS 3928
-#define CONFIG_MACH_TYPE MACH_TYPE_TRATS
+#define CONFIG_SYS_TEXT_BASE 0x63300000
#include <linux/sizes.h>
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M))
/* select serial console configuration */
-#define CONFIG_SERIAL2 /* use SERIAL 2 */
+#define CONFIG_SERIAL2
#define CONFIG_BAUDRATE 115200
-/* MMC */
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
-#define CONFIG_S5P_SDHCI
-#define CONFIG_SDHCI
-#define CONFIG_MMC_SDMA
-
-/* PWM */
-#define CONFIG_PWM
-
-/* It should define before config_cmd_default.h */
-#define CONFIG_SYS_NO_FLASH
-
-/* Command definition */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_MISC
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_XIMG
-#undef CONFIG_CMD_CACHE
-#undef CONFIG_CMD_ONENAND
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_DFU
-#define CONFIG_CMD_GPT
-#define CONFIG_CMD_SETEXPR
-
-/* FAT */
-#define CONFIG_CMD_FAT
-#define CONFIG_FAT_WRITE
-
-/* USB Composite download gadget - g_dnl */
-#define CONFIG_USBDOWNLOAD_GADGET
-
-/* TIZEN THOR downloader support */
-#define CONFIG_CMD_THOR_DOWNLOAD
-#define CONFIG_THOR_FUNCTION
-
-#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M
-#define DFU_DEFAULT_POLL_TIMEOUT 300
-#define CONFIG_DFU_FUNCTION
-#define CONFIG_DFU_MMC
-
-/* USB Samsung's IDs */
-#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
-#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
-#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
-#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D
-#define CONFIG_G_DNL_MANUFACTURER "Samsung"
-
-#define CONFIG_BOOTDELAY 1
-#define CONFIG_ZERO_BOOTDELAY_CHECK
+/* Console configuration */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/* MACH_TYPE_TRATS macro will be removed once added to mach-types */
+#define MACH_TYPE_TRATS 3928
+#define CONFIG_MACH_TYPE MACH_TYPE_TRATS
+
#define CONFIG_BOOTARGS "Please use defined boot"
#define CONFIG_BOOTCOMMAND "run mmcboot"
+#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
+
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
+ - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
+
+#define CONFIG_SYS_MONITOR_BASE 0x00000000
-#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
#define CONFIG_BOOTBLOCK "10"
#define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}"
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV
+#define CONFIG_ENV_SIZE 4096
+#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
/* Tizen - partitions definitions */
#define PARTS_CSA "csa-mmc"
-#define PARTS_BOOTLOADER "u-boot"
#define PARTS_BOOT "boot"
+#define PARTS_QBOOT "qboot"
+#define PARTS_CSC "csc"
#define PARTS_ROOT "platform"
#define PARTS_DATA "data"
-#define PARTS_CSC "csc"
#define PARTS_UMS "ums"
#define PARTS_DEFAULT \
"uuid_disk=${uuid_gpt_disk};" \
- "name="PARTS_CSA",size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
- "name="PARTS_BOOTLOADER",size=60MiB," \
- "uuid=${uuid_gpt_"PARTS_BOOTLOADER"};" \
- "name="PARTS_BOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
- "name="PARTS_ROOT",size=1GiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
- "name="PARTS_DATA",size=3GiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
+ "name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
+ "name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
+ "name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \
"name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
+ "name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
+ "name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
"name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
#define CONFIG_DFU_ALT \
"u-boot mmc 80 400;" \
"uImage ext4 0 2;" \
+ "modem.bin ext4 0 2;" \
"exynos4210-trats.dtb ext4 0 2;" \
+ ""PARTS_CSA" part 0 1;" \
""PARTS_BOOT" part 0 2;" \
+ ""PARTS_QBOOT" part 0 3;" \
+ ""PARTS_CSC" part 0 4;" \
""PARTS_ROOT" part 0 5;" \
""PARTS_DATA" part 0 6;" \
""PARTS_UMS" part 0 7;" \
"params.bin mmc 0x38 0x8\0"
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-
-#define CONFIG_ENV_VARS_UBOOT_CONFIG
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootk=" \
"run loaduimage;" \
"setenv spl_addr_tmp;\0" \
"fdtaddr=40800000\0" \
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT "TRATS # "
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-/* memtest works on */
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
-
-/* TRATS has 4 banks of DRAM */
-#define CONFIG_NR_DRAM_BANKS 4
-#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
-#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
-#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
-
-#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
-
-#define CONFIG_SYS_MONITOR_BASE 0x00000000
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-
-#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_ENV_SIZE 4096
-#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */
-
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-
-/* EXT4 */
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
/* Falcon mode definitions */
#define CONFIG_CMD_SPL
-#define CONFIG_SYS_SPL_ARGS_ADDR PHYS_SDRAM_1 + 0x100
+#define CONFIG_SYS_SPL_ARGS_ADDR CONFIG_SYS_SDRAM_BASE + 0x100
/* GPT */
-#define CONFIG_EFI_PARTITION
-#define CONFIG_PARTITION_UUIDS
#define CONFIG_RANDOM_UUID
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_CACHELINE_SIZE 32
+/* I2C */
+#include <asm/arch/gpio.h>
+
+#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_S3C24X0
#define CONFIG_SOFT_I2C_READ_REPEATED_START
#define CONFIG_SYS_I2C_INIT_BOARD
-#include <asm/arch/gpio.h>
-
/* I2C FG */
#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_get(2, y4, 1)
#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_get(2, y4, 0)
+/* POWER */
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_MAX8997
#define CONFIG_POWER_MUIC_MAX8997
#define CONFIG_POWER_BATTERY
#define CONFIG_POWER_BATTERY_TRATS
-#define CONFIG_USB_GADGET
-#define CONFIG_USB_GADGET_S3C_UDC_OTG
-#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW 2
-#define CONFIG_USB_CABLE_CHECK
/* Security subsystem - enable hw_rand() */
#define CONFIG_EXYNOS_ACE_SHA
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
-#define CONFIG_CMD_USB_MASS_STORAGE
-#define CONFIG_USB_GADGET_MASS_STORAGE
-
-/* Pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
+#define LCD_XRES 720
+#define LCD_YRES 1280
#endif /* __CONFIG_H */
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_TRATS2_H
+#define __CONFIG_TRATS2_H
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_SAMSUNG /* in a SAMSUNG core */
-#define CONFIG_S5P /* which is in a S5P Family */
-#define CONFIG_EXYNOS4 /* which is in a EXYNOS4XXX */
-#define CONFIG_TIZEN /* TIZEN lib */
-
-#include <asm/arch/cpu.h> /* get chip and board defs */
+#include <configs/exynos4-dt.h>
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_PROMPT "Trats2 # " /* Monitor Command Prompt */
-#define CONFIG_SKIP_LOWLEVEL_INIT
+#undef CONFIG_DEFAULT_DEVICE_TREE
+#define CONFIG_DEFAULT_DEVICE_TREE exynos4412-trats2
-#define CONFIG_SYS_CACHELINE_SIZE 32
+#define CONFIG_TIZEN /* TIZEN lib */
#define CONFIG_SYS_L2CACHE_OFF
#ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_PL310_BASE 0x10502000
#endif
-#define CONFIG_NR_DRAM_BANKS 4
-#define PHYS_SDRAM_1 0x40000000 /* LDDDR2 DMC 0 */
-#define PHYS_SDRAM_1_SIZE (256 << 20) /* 256 MB in CS 0 */
-#define PHYS_SDRAM_2 0x50000000 /* LPDDR2 DMC 1 */
-#define PHYS_SDRAM_2_SIZE (256 << 20) /* 256 MB in CS 0 */
-#define PHYS_SDRAM_3 0x60000000 /* LPDDR2 DMC 1 */
-#define PHYS_SDRAM_3_SIZE (256 << 20) /* 256 MB in CS 0 */
-#define PHYS_SDRAM_4 0x70000000 /* LPDDR2 DMC 1 */
-#define PHYS_SDRAM_4_SIZE (256 << 20) /* 256 MB in CS 0 */
-#define PHYS_SDRAM_END 0x80000000
-
-#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
-
-#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
-#define CONFIG_SYS_TEXT_BASE 0x78100000
-
-#define CONFIG_SYS_CLK_FREQ 24000000
-
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_REVISION_TAG
-
-/* MACH_TYPE_TRATS2 */
-#define MACH_TYPE_TRATS2 3765
-#define CONFIG_MACH_TYPE MACH_TYPE_TRATS2
+/* TRATS2 has 4 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS 4
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
-#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_SYS_TEXT_BASE 0x43e00000
#include <linux/sizes.h>
/* Size of malloc() pool */
/* select serial console configuration */
#define CONFIG_SERIAL2
+#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+/* Console configuration */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_CMDLINE_EDITING
+#define CONFIG_BOOTARGS "Please use defined boot"
+#define CONFIG_BOOTCOMMAND "run mmcboot"
+#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
-#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
+ - GENERATED_GBL_DATA_SIZE)
-/* It should define before config_cmd_default.h */
-#define CONFIG_SYS_NO_FLASH
-
-/***********************************************************
- * Command definition
- ***********************************************************/
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_ECHO
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_NAND
-#undef CONFIG_CMD_MISC
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_SOURCE
-#undef CONFIG_CMD_XIMG
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_DFU
-#define CONFIG_CMD_GPT
-#define CONFIG_CMD_PMIC
-
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
-#define CONFIG_CMD_FAT
-#define CONFIG_FAT_WRITE
-
-/* EXT4 */
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
-
-/* USB Composite download gadget - g_dnl */
-#define CONFIG_USBDOWNLOAD_GADGET
-#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M
-#define DFU_DEFAULT_POLL_TIMEOUT 300
-#define CONFIG_DFU_FUNCTION
-#define CONFIG_DFU_MMC
-
-/* TIZEN THOR downloader support */
-#define CONFIG_CMD_THOR_DOWNLOAD
-#define CONFIG_THOR_FUNCTION
-
-/* USB Samsung's IDs */
-#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
-#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
-#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
-#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D
-#define CONFIG_G_DNL_MANUFACTURER "Samsung"
-
-/* To use the TFTPBOOT over USB, Please enable the CONFIG_CMD_NET */
-#undef CONFIG_CMD_NET
-
-/* MMC */
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
-#define CONFIG_S5P_SDHCI
-#define CONFIG_SDHCI
-#define CONFIG_MMC_SDMA
-#define CONFIG_MMC_DEFAULT_DEV 0
-
-/* PWM */
-#define CONFIG_PWM
-
-#define CONFIG_BOOTARGS "Please use defined boot"
-#define CONFIG_BOOTCOMMAND "run mmcboot"
-#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
+#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
+
+#define CONFIG_SYS_MONITOR_BASE 0x00000000
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV
+#define CONFIG_ENV_SIZE 4096
+#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_ENV_VARS_UBOOT_CONFIG
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
/* Tizen - partitions definitions */
-#define PARTS_CSA "csa"
+#define PARTS_CSA "csa-mmc"
#define PARTS_BOOT "boot"
-#define PARTS_MODEM "modem"
+#define PARTS_QBOOT "qboot"
#define PARTS_CSC "csc"
#define PARTS_ROOT "platform"
#define PARTS_DATA "data"
#define PARTS_DEFAULT \
"uuid_disk=${uuid_gpt_disk};" \
"name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
- "name="PARTS_BOOT",size=64MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
- "name="PARTS_MODEM",size=100MiB,uuid=${uuid_gpt_"PARTS_MODEM"};" \
+ "name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
+ "name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \
"name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
"name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
- "name="PARTS_DATA",size=512MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
+ "name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
"name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
#define CONFIG_DFU_ALT \
"u-boot mmc 80 800;" \
"uImage ext4 0 2;" \
+ "modem.bin ext4 0 2;" \
"exynos4412-trats2.dtb ext4 0 2;" \
+ ""PARTS_CSA" part 0 1;" \
""PARTS_BOOT" part 0 2;" \
+ ""PARTS_QBOOT" part 0 3;" \
+ ""PARTS_CSC" part 0 4;" \
""PARTS_ROOT" part 0 5;" \
""PARTS_DATA" part 0 6;" \
""PARTS_UMS" part 0 7;" \
"setenv spl_addr_tmp;\0" \
"fdtaddr=40800000\0" \
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "Trats2 # " /* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
-
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-/* memtest works on */
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
-
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
- - GENERATED_GBL_DATA_SIZE)
-
-/* valid baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
-#define CONFIG_SYS_MONITOR_BASE 0x00000000
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-
-#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV
-#define CONFIG_ENV_SIZE 4096
-#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */
-#define CONFIG_EFI_PARTITION
-#define CONFIG_PARTITION_UUIDS
+/* GPT */
#define CONFIG_RANDOM_UUID
-#define CONFIG_BOARD_EARLY_INIT_F
-
/* I2C */
#include <asm/arch/gpio.h>
+#define CONFIG_CMD_I2C
+
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_S3C24X0
#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000
#define CONFIG_POWER_MUIC_MAX77693
#define CONFIG_POWER_FG_MAX77693
#define CONFIG_POWER_BATTERY_TRATS2
-#define CONFIG_USB_GADGET
-#define CONFIG_USB_GADGET_S3C_UDC_OTG
-#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW 2
-#define CONFIG_USB_CABLE_CHECK
/* Security subsystem - enable hw_rand() */
#define CONFIG_EXYNOS_ACE_SHA
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
-#define CONFIG_CMD_USB_MASS_STORAGE
-#define CONFIG_USB_GADGET_MASS_STORAGE
-
-/* Pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
+#define LCD_XRES 720
+#define LCD_YRES 1280
#endif /* __CONFIG_H */
#define CONFIG_REMAKE_ELF
+#define CONFIG_GICV3
+
/*#define CONFIG_ARMV8_SWITCH_TO_EL1*/
/*#define CONFIG_SYS_GENERIC_BOARD*/
#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */
/* Generic Interrupt Controller Definitions */
+#ifdef CONFIG_GICV3
+#define GICD_BASE (0x2f000000)
+#define GICR_BASE (0x2f100000)
+#else
#define GICD_BASE (0x2C001000)
#define GICC_BASE (0x2C002000)
+#endif
#define CONFIG_SYS_MEMTEST_START V2M_BASE
#define CONFIG_SYS_MEMTEST_END (V2M_BASE + 0x80000000)
/* Set TEXT in RAM */
#define CONFIG_SYS_TEXT_BASE 0x82000000
-#define CONFIG_BOOT_INTERNAL
-
/*
* SPL
*/
COMPAT_SAMSUNG_EXYNOS5_USB3_PHY,/* Exynos phy controller for usb3.0 */
COMPAT_SAMSUNG_EXYNOS_TMU, /* Exynos TMU */
COMPAT_SAMSUNG_EXYNOS_FIMD, /* Exynos Display controller */
+ COMPAT_SAMSUNG_EXYNOS_MIPI_DSI, /* Exynos mipi dsi */
COMPAT_SAMSUNG_EXYNOS5_DP, /* Exynos Display port controller */
COMPAT_SAMSUNG_EXYNOS5_DWMMC, /* Exynos5 DWMMC controller */
+ COMPAT_SAMSUNG_EXYNOS_MMC, /* Exynos MMC controller */
COMPAT_SAMSUNG_EXYNOS_SERIAL, /* Exynos UART */
COMPAT_MAXIM_MAX77686_PMIC, /* MAX77686 PMIC */
COMPAT_GENERIC_SPI_FLASH, /* Generic SPI Flash chip */
u32 flag;
};
+int board_video_skip(void);
+
#endif /* __KERNEL__ */
#endif /* _LINUX_FB_H */
int mmc_legacy_init(int verbose);
#endif
+int board_mmc_init(bd_t *bis);
+
/* Set block count limit because of 16 bit register limit on some hardware*/
#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
int phy_teranetics_init(void);
int phy_vitesse_init(void);
+int board_phy_config(struct phy_device *phydev);
+
/* PHY UIDs for various PHYs that are referenced in external code */
#define PHY_UID_TN2020 0x00a19410
--- /dev/null
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Tim Harvey <tharvey@gateworks.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __PFUZE100_PMIC_H_
+#define __PFUZE100_PMIC_H_
+
+/* PFUZE100 registers */
+enum {
+ PFUZE100_DEVICEID = 0x00,
+ PFUZE100_REVID = 0x03,
+ PFUZE100_FABID = 0x04,
+
+ PFUZE100_SW1ABVOL = 0x20,
+ PFUZE100_SW1CVOL = 0x2e,
+ PFUZE100_SW2VOL = 0x35,
+ PFUZE100_SW3AVOL = 0x3c,
+ PFUZE100_SW3BVOL = 0x43,
+ PFUZE100_SW4VOL = 0x4a,
+ PFUZE100_SWBSTCON1 = 0x66,
+ PFUZE100_VREFDDRCON = 0x6a,
+ PFUZE100_VSNVSVOL = 0x6b,
+ PFUZE100_VGEN1VOL = 0x6c,
+ PFUZE100_VGEN2VOL = 0x6d,
+ PFUZE100_VGEN3VOL = 0x6e,
+ PFUZE100_VGEN4VOL = 0x6f,
+ PFUZE100_VGEN5VOL = 0x70,
+ PFUZE100_VGEN6VOL = 0x71,
+
+ PMIC_NUM_OF_REGS = 0x7f,
+};
+
+/*
+ * LDO Configuration
+ */
+
+/* VGEN1/2 Voltage Configuration */
+#define LDOA_0_80V 0
+#define LDOA_0_85V 1
+#define LDOA_0_90V 2
+#define LDOA_0_95V 3
+#define LDOA_1_00V 4
+#define LDOA_1_05V 5
+#define LDOA_1_10V 6
+#define LDOA_1_15V 7
+#define LDOA_1_20V 8
+#define LDOA_1_25V 9
+#define LDOA_1_30V 10
+#define LDOA_1_35V 11
+#define LDOA_1_40V 12
+#define LDOA_1_45V 13
+#define LDOA_1_50V 14
+#define LDOA_1_55V 15
+
+/* VGEN3/4/5/6 Voltage Configuration */
+#define LDOB_1_80V 0
+#define LDOB_1_90V 1
+#define LDOB_2_00V 2
+#define LDOB_2_10V 3
+#define LDOB_2_20V 4
+#define LDOB_2_30V 5
+#define LDOB_2_40V 6
+#define LDOB_2_50V 7
+#define LDOB_2_60V 8
+#define LDOB_2_70V 9
+#define LDOB_2_80V 10
+#define LDOB_2_90V 11
+#define LDOB_3_00V 12
+#define LDOB_3_10V 13
+#define LDOB_3_20V 14
+#define LDOB_3_30V 15
+
+#define LDO_VOL_MASK 0xf
+#define LDO_EN 4
+
+/*
+ * Boost Regulator
+ */
+
+/* SWBST Output Voltage */
+#define SWBST_5_00V 0
+#define SWBST_5_05V 1
+#define SWBST_5_10V 2
+#define SWBST_5_15V 3
+
+#define SWBST_VOL_MASK 0x3
+#define SWBST_MODE_MASK 0x6
+#define SWBST_MODE_OFF (2 << 0)
+#define SWBST_MODE_PFM (2 << 1)
+#define SWBST_MODE_AUTO (2 << 2)
+#define SWBST_MODE_APS (2 << 3)
+
+#endif
#include <asm/io.h>
#include <mmc.h>
+#include <fdtdec.h>
/*
* Controller registers
const struct sdhci_ops *ops;
int index;
+ int bus_width;
+ struct fdt_gpio_state pwr_gpio; /* Power GPIO */
+ struct fdt_gpio_state cd_gpio; /* Card Detect GPIO */
+
void (*set_control_reg)(struct sdhci_host *host);
void (*set_clock)(int dev_index, unsigned int div);
uint voltages;
COMPAT(SAMSUNG_EXYNOS5_USB3_PHY, "samsung,exynos5250-usb3-phy"),
COMPAT(SAMSUNG_EXYNOS_TMU, "samsung,exynos-tmu"),
COMPAT(SAMSUNG_EXYNOS_FIMD, "samsung,exynos-fimd"),
+ COMPAT(SAMSUNG_EXYNOS_MIPI_DSI, "samsung,exynos-mipi-dsi"),
COMPAT(SAMSUNG_EXYNOS5_DP, "samsung,exynos5-dp"),
COMPAT(SAMSUNG_EXYNOS5_DWMMC, "samsung,exynos5250-dwmmc"),
+ COMPAT(SAMSUNG_EXYNOS_MMC, "samsung,exynos-mmc"),
COMPAT(SAMSUNG_EXYNOS_SERIAL, "samsung,exynos4210-uart"),
COMPAT(MAXIM_MAX77686_PMIC, "maxim,max77686_pmic"),
COMPAT(GENERIC_SPI_FLASH, "spi-flash"),
projects / karo-tx-uboot.git / commitdiff